From 7bb2ba23c86437fc00cf082966867477cbc9d918 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 7 Nov 2020 11:39:24 +0000 Subject: [PATCH] update full ls180 core --- experiments9/non_generated/full_core_ls180.il | 239292 ++++++++------- pinmux | 2 +- 2 files changed, 124755 insertions(+), 114539 deletions(-) diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 1ba1b0b..b2e8f45 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,8 +1,8 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14178 +autoidx 14657 attribute \src "libresoc.v:5.1-330.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" attribute \generator "nMigen" module \ALU_dec19 attribute \src "libresoc.v:279.3-288.6" @@ -71,7 +71,7 @@ module \ALU_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -79,15 +79,15 @@ module \ALU_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -102,7 +102,7 @@ module \ALU_dec19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110,7 +110,7 @@ module \ALU_dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -127,7 +127,7 @@ module \ALU_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203,13 +203,13 @@ module \ALU_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -217,21 +217,21 @@ module \ALU_dec19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec19_sgn attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \src "libresoc.v:189.3-198.6" process $proc$libresoc.v:189$1 @@ -244,7 +244,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -267,7 +267,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -290,7 +290,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -313,7 +313,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -336,7 +336,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -359,7 +359,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -382,7 +382,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -405,7 +405,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -428,7 +428,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -451,7 +451,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -474,7 +474,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -497,7 +497,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -520,7 +520,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -543,7 +543,7 @@ module \ALU_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0010010110 @@ -567,7 +567,7 @@ module \ALU_dec19 end attribute \src "libresoc.v:334.1-1750.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" attribute \generator "nMigen" module \ALU_dec31 attribute \src "libresoc.v:1457.3-1478.6" @@ -636,7 +636,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -644,15 +644,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -662,7 +662,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -670,15 +670,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -693,7 +693,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -701,7 +701,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -718,7 +718,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -794,13 +794,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -808,17 +808,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -828,7 +828,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -836,15 +836,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -859,7 +859,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -867,7 +867,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -884,7 +884,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -960,13 +960,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -974,17 +974,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_dec_sub10_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -994,7 +994,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1002,15 +1002,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -1025,7 +1025,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1033,7 +1033,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1050,7 +1050,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1126,13 +1126,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1140,17 +1140,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_dec_sub22_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1160,7 +1160,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1168,15 +1168,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -1191,7 +1191,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1199,7 +1199,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1216,7 +1216,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1292,13 +1292,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1306,17 +1306,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -1326,7 +1326,7 @@ module \ALU_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -1334,15 +1334,15 @@ module \ALU_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -1357,7 +1357,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1365,7 +1365,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1382,7 +1382,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1458,13 +1458,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1472,17 +1472,17 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_dec_sub8_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -1497,7 +1497,7 @@ module \ALU_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -1505,7 +1505,7 @@ module \ALU_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -1522,7 +1522,7 @@ module \ALU_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -1598,13 +1598,13 @@ module \ALU_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -1612,23 +1612,23 @@ module \ALU_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_sgn attribute \src "libresoc.v:335.7-335.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:1350.22-1366.4" @@ -1736,7 +1736,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1775,7 +1775,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1814,7 +1814,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1853,7 +1853,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1892,7 +1892,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1931,7 +1931,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -1970,7 +1970,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2009,7 +2009,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2048,7 +2048,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2087,7 +2087,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2126,7 +2126,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2165,7 +2165,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2204,7 +2204,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2243,7 +2243,7 @@ module \ALU_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -2289,7 +2289,7 @@ module \ALU_dec31 end attribute \src "libresoc.v:1754.1-2163.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" attribute \generator "nMigen" module \ALU_dec31_dec_sub0 attribute \src "libresoc.v:2082.3-2097.6" @@ -2358,7 +2358,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -2366,15 +2366,15 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_dec_sub0_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -2389,7 +2389,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -2397,7 +2397,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -2414,7 +2414,7 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -2490,13 +2490,13 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -2504,21 +2504,21 @@ module \ALU_dec31_dec_sub0 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_dec_sub0_sgn attribute \src "libresoc.v:1755.7-1755.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:1755.7-1755.20" process $proc$libresoc.v:1755$45 @@ -2539,7 +2539,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2570,7 +2570,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2601,7 +2601,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2632,7 +2632,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2663,7 +2663,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2694,7 +2694,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2725,7 +2725,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2756,7 +2756,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2787,7 +2787,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2818,7 +2818,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2849,7 +2849,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2880,7 +2880,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2911,7 +2911,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2942,7 +2942,7 @@ module \ALU_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -2966,7 +2966,7 @@ module \ALU_dec31_dec_sub0 end attribute \src "libresoc.v:2167.1-2870.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" attribute \generator "nMigen" module \ALU_dec31_dec_sub10 attribute \src "libresoc.v:2684.3-2720.6" @@ -3035,7 +3035,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -3043,15 +3043,15 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_dec_sub10_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -3066,7 +3066,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -3074,7 +3074,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -3091,7 +3091,7 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -3167,13 +3167,13 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -3181,21 +3181,21 @@ module \ALU_dec31_dec_sub10 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_dec_sub10_sgn attribute \src "libresoc.v:2168.7-2168.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:2168.7-2168.20" process $proc$libresoc.v:2168$60 @@ -3216,7 +3216,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3275,7 +3275,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3334,7 +3334,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3393,7 +3393,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3452,7 +3452,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3511,7 +3511,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3570,7 +3570,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3629,7 +3629,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3688,7 +3688,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3747,7 +3747,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3806,7 +3806,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3865,7 +3865,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3924,7 +3924,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -3983,7 +3983,7 @@ module \ALU_dec31_dec_sub10 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -4035,7 +4035,7 @@ module \ALU_dec31_dec_sub10 end attribute \src "libresoc.v:2874.1-3451.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" attribute \generator "nMigen" module \ALU_dec31_dec_sub22 attribute \src "libresoc.v:3310.3-3337.6" @@ -4104,7 +4104,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -4112,15 +4112,15 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_dec_sub22_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -4135,7 +4135,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -4143,7 +4143,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -4160,7 +4160,7 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -4236,13 +4236,13 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -4250,21 +4250,21 @@ module \ALU_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_dec_sub22_sgn attribute \src "libresoc.v:2875.7-2875.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:2875.7-2875.20" process $proc$libresoc.v:2875$75 @@ -4285,7 +4285,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4332,7 +4332,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4379,7 +4379,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4426,7 +4426,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4473,7 +4473,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4520,7 +4520,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4567,7 +4567,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4614,7 +4614,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4661,7 +4661,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4708,7 +4708,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4755,7 +4755,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4802,7 +4802,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4849,7 +4849,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4896,7 +4896,7 @@ module \ALU_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -4936,7 +4936,7 @@ module \ALU_dec31_dec_sub22 end attribute \src "libresoc.v:3455.1-3864.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" attribute \generator "nMigen" module \ALU_dec31_dec_sub26 attribute \src "libresoc.v:3783.3-3798.6" @@ -5005,7 +5005,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5013,15 +5013,15 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -5036,7 +5036,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5044,7 +5044,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5061,7 +5061,7 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5137,13 +5137,13 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5151,21 +5151,21 @@ module \ALU_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_dec_sub26_sgn attribute \src "libresoc.v:3456.7-3456.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:3456.7-3456.20" process $proc$libresoc.v:3456$90 @@ -5186,7 +5186,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5217,7 +5217,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5248,7 +5248,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5279,7 +5279,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5310,7 +5310,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5341,7 +5341,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5372,7 +5372,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5403,7 +5403,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5434,7 +5434,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5465,7 +5465,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5496,7 +5496,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5527,7 +5527,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5558,7 +5558,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5589,7 +5589,7 @@ module \ALU_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11101 @@ -5613,7 +5613,7 @@ module \ALU_dec31_dec_sub26 end attribute \src "libresoc.v:3868.1-4655.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" attribute \generator "nMigen" module \ALU_dec31_dec_sub8 attribute \src "libresoc.v:4439.3-4481.6" @@ -5682,7 +5682,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -5690,15 +5690,15 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_dec31_dec_sub8_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -5713,7 +5713,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -5721,7 +5721,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -5738,7 +5738,7 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -5814,13 +5814,13 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \ALU_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -5828,21 +5828,21 @@ module \ALU_dec31_dec_sub8 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_dec31_dec_sub8_sgn attribute \src "libresoc.v:3869.7-3869.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:3869.7-3869.20" process $proc$libresoc.v:3869$105 @@ -5863,7 +5863,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -5930,7 +5930,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -5997,7 +5997,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6064,7 +6064,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6131,7 +6131,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6198,7 +6198,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6265,7 +6265,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6332,7 +6332,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6399,7 +6399,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6466,7 +6466,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6533,7 +6533,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6600,7 +6600,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6667,7 +6667,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6734,7 +6734,7 @@ module \ALU_dec31_dec_sub8 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -6794,7 +6794,7 @@ module \ALU_dec31_dec_sub8 end attribute \src "libresoc.v:4659.1-4938.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" attribute \generator "nMigen" module \BRANCH_dec19 attribute \src "libresoc.v:4857.3-4872.6" @@ -6839,7 +6839,7 @@ module \BRANCH_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -6847,7 +6847,7 @@ module \BRANCH_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -6862,7 +6862,7 @@ module \BRANCH_dec19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -6879,7 +6879,7 @@ module \BRANCH_dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -6955,23 +6955,23 @@ module \BRANCH_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 7 \BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 8 \BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \BRANCH_dec19_rc_sel attribute \src "libresoc.v:4660.7-4660.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \src "libresoc.v:4660.7-4660.20" process $proc$libresoc.v:4660$114 @@ -6992,7 +6992,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7023,7 +7023,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7054,7 +7054,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7085,7 +7085,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7116,7 +7116,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7147,7 +7147,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7178,7 +7178,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7209,7 +7209,7 @@ module \BRANCH_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'1000010000 @@ -7233,7 +7233,7 @@ module \BRANCH_dec19 end attribute \src "libresoc.v:4942.1-5239.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" attribute \generator "nMigen" module \CR_dec19 attribute \src "libresoc.v:5136.3-5169.6" @@ -7266,7 +7266,7 @@ module \CR_dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7274,7 +7274,7 @@ module \CR_dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -7289,7 +7289,7 @@ module \CR_dec19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7365,19 +7365,19 @@ module \CR_dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec19_rc_sel attribute \src "libresoc.v:4943.7-4943.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \src "libresoc.v:4943.7-4943.20" process $proc$libresoc.v:4943$120 @@ -7398,7 +7398,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7453,7 +7453,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7508,7 +7508,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7563,7 +7563,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7618,7 +7618,7 @@ module \CR_dec19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -7666,7 +7666,7 @@ module \CR_dec19 end attribute \src "libresoc.v:5243.1-5972.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" attribute \generator "nMigen" module \CR_dec31 attribute \src "libresoc.v:5928.3-5946.6" @@ -7699,7 +7699,7 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7707,7 +7707,7 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7717,7 +7717,7 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7725,7 +7725,7 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -7740,7 +7740,7 @@ module \CR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7816,15 +7816,15 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec31_dec_sub0_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7834,7 +7834,7 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7842,7 +7842,7 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -7857,7 +7857,7 @@ module \CR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -7933,15 +7933,15 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec31_dec_sub15_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -7951,7 +7951,7 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -7959,7 +7959,7 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -7974,7 +7974,7 @@ module \CR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8050,15 +8050,15 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec31_dec_sub16_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -8068,7 +8068,7 @@ module \CR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8076,7 +8076,7 @@ module \CR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -8091,7 +8091,7 @@ module \CR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8167,15 +8167,15 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -8190,7 +8190,7 @@ module \CR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8266,21 +8266,21 @@ module \CR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec31_rc_sel attribute \src "libresoc.v:5244.7-5244.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:5839.21-5846.4" @@ -8341,7 +8341,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8376,7 +8376,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8411,7 +8411,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8446,7 +8446,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8481,7 +8481,7 @@ module \CR_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -8514,7 +8514,7 @@ module \CR_dec31 end attribute \src "libresoc.v:5976.1-6153.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" attribute \generator "nMigen" module \CR_dec31_dec_sub0 attribute \src "libresoc.v:6122.3-6131.6" @@ -8547,7 +8547,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8555,7 +8555,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec31_dec_sub0_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -8570,7 +8570,7 @@ module \CR_dec31_dec_sub0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec31_dec_sub0_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8646,19 +8646,19 @@ module \CR_dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec31_dec_sub0_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel attribute \src "libresoc.v:5977.7-5977.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:5977.7-5977.20" process $proc$libresoc.v:5977$132 @@ -8679,7 +8679,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8702,7 +8702,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8725,7 +8725,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8748,7 +8748,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8771,7 +8771,7 @@ module \CR_dec31_dec_sub0 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -8787,7 +8787,7 @@ module \CR_dec31_dec_sub0 end attribute \src "libresoc.v:6157.1-6799.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" attribute \generator "nMigen" module \CR_dec31_dec_sub15 attribute \src "libresoc.v:6489.3-6591.6" @@ -8820,7 +8820,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -8828,7 +8828,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec31_dec_sub15_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -8843,7 +8843,7 @@ module \CR_dec31_dec_sub15 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec31_dec_sub15_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -8919,19 +8919,19 @@ module \CR_dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec31_dec_sub15_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel attribute \src "libresoc.v:6158.7-6158.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:6158.7-6158.20" process $proc$libresoc.v:6158$138 @@ -8952,7 +8952,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9099,7 +9099,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9246,7 +9246,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9393,7 +9393,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9540,7 +9540,7 @@ module \CR_dec31_dec_sub15 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -9680,7 +9680,7 @@ module \CR_dec31_dec_sub15 end attribute \src "libresoc.v:6803.1-6980.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" attribute \generator "nMigen" module \CR_dec31_dec_sub16 attribute \src "libresoc.v:6949.3-6958.6" @@ -9713,7 +9713,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9721,7 +9721,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec31_dec_sub16_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -9736,7 +9736,7 @@ module \CR_dec31_dec_sub16 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec31_dec_sub16_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -9812,19 +9812,19 @@ module \CR_dec31_dec_sub16 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec31_dec_sub16_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel attribute \src "libresoc.v:6804.7-6804.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:6804.7-6804.20" process $proc$libresoc.v:6804$144 @@ -9845,7 +9845,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9868,7 +9868,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9891,7 +9891,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9914,7 +9914,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9937,7 +9937,7 @@ module \CR_dec31_dec_sub16 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -9953,7 +9953,7 @@ module \CR_dec31_dec_sub16 end attribute \src "libresoc.v:6984.1-7161.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" attribute \generator "nMigen" module \CR_dec31_dec_sub19 attribute \src "libresoc.v:7130.3-7139.6" @@ -9986,7 +9986,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \CR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -9994,7 +9994,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -10009,7 +10009,7 @@ module \CR_dec31_dec_sub19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \CR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10085,19 +10085,19 @@ module \CR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \CR_dec31_dec_sub19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel attribute \src "libresoc.v:6985.7-6985.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:6985.7-6985.20" process $proc$libresoc.v:6985$150 @@ -10118,7 +10118,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10141,7 +10141,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10164,7 +10164,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10187,7 +10187,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10210,7 +10210,7 @@ module \CR_dec31_dec_sub19 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -10226,7 +10226,7 @@ module \CR_dec31_dec_sub19 end attribute \src "libresoc.v:7165.1-7903.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" attribute \generator "nMigen" module \DIV_dec31 attribute \src "libresoc.v:7873.3-7885.6" @@ -10295,7 +10295,7 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10303,15 +10303,15 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \DIV_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10321,7 +10321,7 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10329,15 +10329,15 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -10352,7 +10352,7 @@ module \DIV_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10360,7 +10360,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10377,7 +10377,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10453,13 +10453,13 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10467,17 +10467,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \DIV_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -10487,7 +10487,7 @@ module \DIV_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -10495,15 +10495,15 @@ module \DIV_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -10518,7 +10518,7 @@ module \DIV_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10526,7 +10526,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10543,7 +10543,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10619,13 +10619,13 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10633,17 +10633,17 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \DIV_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -10658,7 +10658,7 @@ module \DIV_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -10666,7 +10666,7 @@ module \DIV_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -10683,7 +10683,7 @@ module \DIV_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -10759,13 +10759,13 @@ module \DIV_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -10773,23 +10773,23 @@ module \DIV_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \DIV_dec31_sgn attribute \src "libresoc.v:7166.7-7166.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:7683.23-7699.4" @@ -10848,7 +10848,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10875,7 +10875,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10902,7 +10902,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10929,7 +10929,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10956,7 +10956,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -10983,7 +10983,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11010,7 +11010,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11037,7 +11037,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11064,7 +11064,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11091,7 +11091,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11118,7 +11118,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11145,7 +11145,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11172,7 +11172,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11199,7 +11199,7 @@ module \DIV_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -11222,7 +11222,7 @@ module \DIV_dec31 end attribute \src "libresoc.v:7907.1-8610.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" attribute \generator "nMigen" module \DIV_dec31_dec_sub11 attribute \src "libresoc.v:8424.3-8460.6" @@ -11291,7 +11291,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -11299,15 +11299,15 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \DIV_dec31_dec_sub11_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -11322,7 +11322,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -11330,7 +11330,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -11347,7 +11347,7 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -11423,13 +11423,13 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \DIV_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -11437,21 +11437,21 @@ module \DIV_dec31_dec_sub11 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \DIV_dec31_dec_sub11_sgn attribute \src "libresoc.v:7908.7-7908.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:7908.7-7908.20" process $proc$libresoc.v:7908$180 @@ -11472,7 +11472,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11531,7 +11531,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11590,7 +11590,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11649,7 +11649,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11708,7 +11708,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11767,7 +11767,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11826,7 +11826,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11885,7 +11885,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -11944,7 +11944,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12003,7 +12003,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12062,7 +12062,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12121,7 +12121,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12180,7 +12180,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12239,7 +12239,7 @@ module \DIV_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12291,7 +12291,7 @@ module \DIV_dec31_dec_sub11 end attribute \src "libresoc.v:8614.1-9317.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" attribute \generator "nMigen" module \DIV_dec31_dec_sub9 attribute \src "libresoc.v:9131.3-9167.6" @@ -12360,7 +12360,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -12368,15 +12368,15 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \DIV_dec31_dec_sub9_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -12391,7 +12391,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -12399,7 +12399,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -12416,7 +12416,7 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -12492,13 +12492,13 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \DIV_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -12506,21 +12506,21 @@ module \DIV_dec31_dec_sub9 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \DIV_dec31_dec_sub9_sgn attribute \src "libresoc.v:8615.7-8615.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:8615.7-8615.20" process $proc$libresoc.v:8615$195 @@ -12541,7 +12541,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12600,7 +12600,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12659,7 +12659,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12718,7 +12718,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12777,7 +12777,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12836,7 +12836,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12895,7 +12895,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -12954,7 +12954,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13013,7 +13013,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13072,7 +13072,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13131,7 +13131,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13190,7 +13190,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13249,7 +13249,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13308,7 +13308,7 @@ module \DIV_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -13360,7 +13360,7 @@ module \DIV_dec31_dec_sub9 end attribute \src "libresoc.v:9321.1-10482.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" attribute \generator "nMigen" module \LDST_dec31 attribute \src "libresoc.v:10324.3-10342.6" @@ -13417,7 +13417,7 @@ module \LDST_dec31 wire $1\LDST_dec31_sgn_ext[0:0] attribute \src "libresoc.v:10286.3-10304.6" wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13427,7 +13427,7 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13435,9 +13435,9 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13447,7 +13447,7 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13455,7 +13455,7 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -13470,7 +13470,7 @@ module \LDST_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13478,7 +13478,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13495,7 +13495,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13571,9 +13571,9 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13581,28 +13581,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13612,7 +13612,7 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13620,7 +13620,7 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -13635,7 +13635,7 @@ module \LDST_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13643,7 +13643,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13660,7 +13660,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13736,9 +13736,9 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13746,28 +13746,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13777,7 +13777,7 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13785,7 +13785,7 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -13800,7 +13800,7 @@ module \LDST_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13808,7 +13808,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13825,7 +13825,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -13901,9 +13901,9 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -13911,28 +13911,28 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -13942,7 +13942,7 @@ module \LDST_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -13950,7 +13950,7 @@ module \LDST_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -13965,7 +13965,7 @@ module \LDST_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -13973,7 +13973,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -13990,7 +13990,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14066,9 +14066,9 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14076,26 +14076,26 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec31_dec_sub23_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -14110,7 +14110,7 @@ module \LDST_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14118,7 +14118,7 @@ module \LDST_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14135,7 +14135,7 @@ module \LDST_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14211,9 +14211,9 @@ module \LDST_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14221,32 +14221,32 @@ module \LDST_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec31_upd attribute \src "libresoc.v:9322.7-9322.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:10165.24-10180.4" @@ -14331,7 +14331,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14366,7 +14366,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14401,7 +14401,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14436,7 +14436,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14471,7 +14471,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14506,7 +14506,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14541,7 +14541,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14576,7 +14576,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14611,7 +14611,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14646,7 +14646,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14681,7 +14681,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14716,7 +14716,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14751,7 +14751,7 @@ module \LDST_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10110 @@ -14792,7 +14792,7 @@ module \LDST_dec31 end attribute \src "libresoc.v:10486.1-10994.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" attribute \generator "nMigen" module \LDST_dec31_dec_sub20 attribute \src "libresoc.v:10693.3-10717.6" @@ -14849,7 +14849,7 @@ module \LDST_dec31_dec_sub20 wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] attribute \src "libresoc.v:10943.3-10967.6" wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -14859,7 +14859,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -14867,7 +14867,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -14882,7 +14882,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -14890,7 +14890,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -14907,7 +14907,7 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -14983,9 +14983,9 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -14993,30 +14993,30 @@ module \LDST_dec31_dec_sub20 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec31_dec_sub20_upd attribute \src "libresoc.v:10487.7-10487.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:10487.7-10487.20" process $proc$libresoc.v:10487$223 @@ -15037,7 +15037,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15080,7 +15080,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15123,7 +15123,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15166,7 +15166,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15209,7 +15209,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15252,7 +15252,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15295,7 +15295,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15338,7 +15338,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15381,7 +15381,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15424,7 +15424,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15467,7 +15467,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15510,7 +15510,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15553,7 +15553,7 @@ module \LDST_dec31_dec_sub20 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -15589,7 +15589,7 @@ module \LDST_dec31_dec_sub20 end attribute \src "libresoc.v:10998.1-11818.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" attribute \generator "nMigen" module \LDST_dec31_dec_sub21 attribute \src "libresoc.v:11229.3-11277.6" @@ -15646,7 +15646,7 @@ module \LDST_dec31_dec_sub21 wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] attribute \src "libresoc.v:11719.3-11767.6" wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -15656,7 +15656,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -15664,7 +15664,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -15679,7 +15679,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -15687,7 +15687,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -15704,7 +15704,7 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -15780,9 +15780,9 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -15790,30 +15790,30 @@ module \LDST_dec31_dec_sub21 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec31_dec_sub21_upd attribute \src "libresoc.v:10999.7-10999.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:10999.7-10999.20" process $proc$libresoc.v:10999$237 @@ -15834,7 +15834,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -15909,7 +15909,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -15984,7 +15984,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16059,7 +16059,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16134,7 +16134,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16209,7 +16209,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16284,7 +16284,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16359,7 +16359,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16434,7 +16434,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16509,7 +16509,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16584,7 +16584,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16659,7 +16659,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16734,7 +16734,7 @@ module \LDST_dec31_dec_sub21 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -16802,7 +16802,7 @@ module \LDST_dec31_dec_sub21 end attribute \src "libresoc.v:11822.1-12408.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" attribute \generator "nMigen" module \LDST_dec31_dec_sub22 attribute \src "libresoc.v:12035.3-12065.6" @@ -16859,7 +16859,7 @@ module \LDST_dec31_dec_sub22 wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] attribute \src "libresoc.v:12345.3-12375.6" wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -16869,7 +16869,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -16877,7 +16877,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -16892,7 +16892,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -16900,7 +16900,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -16917,7 +16917,7 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -16993,9 +16993,9 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17003,30 +17003,30 @@ module \LDST_dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec31_dec_sub22_upd attribute \src "libresoc.v:11823.7-11823.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:11823.7-11823.20" process $proc$libresoc.v:11823$251 @@ -17047,7 +17047,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17098,7 +17098,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17149,7 +17149,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17200,7 +17200,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17251,7 +17251,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17302,7 +17302,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17353,7 +17353,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17404,7 +17404,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17455,7 +17455,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17506,7 +17506,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17557,7 +17557,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17608,7 +17608,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17659,7 +17659,7 @@ module \LDST_dec31_dec_sub22 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11000 @@ -17703,7 +17703,7 @@ module \LDST_dec31_dec_sub22 end attribute \src "libresoc.v:12412.1-13232.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" attribute \generator "nMigen" module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:12643.3-12691.6" @@ -17760,7 +17760,7 @@ module \LDST_dec31_dec_sub23 wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] attribute \src "libresoc.v:13133.3-13181.6" wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -17770,7 +17770,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -17778,7 +17778,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -17793,7 +17793,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -17801,7 +17801,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -17818,7 +17818,7 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -17894,9 +17894,9 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -17904,30 +17904,30 @@ module \LDST_dec31_dec_sub23 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec31_dec_sub23_upd attribute \src "libresoc.v:12413.7-12413.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:12413.7-12413.20" process $proc$libresoc.v:12413$265 @@ -17948,7 +17948,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18023,7 +18023,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18098,7 +18098,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18173,7 +18173,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18248,7 +18248,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18323,7 +18323,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18398,7 +18398,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18473,7 +18473,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18548,7 +18548,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18623,7 +18623,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18660,7 +18660,7 @@ module \LDST_dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } @@ -18698,7 +18698,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18773,7 +18773,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18848,7 +18848,7 @@ module \LDST_dec31_dec_sub23 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -18916,7 +18916,7 @@ module \LDST_dec31_dec_sub23 end attribute \src "libresoc.v:13236.1-13627.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec58" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" attribute \generator "nMigen" module \LDST_dec58 attribute \src "libresoc.v:13434.3-13449.6" @@ -18973,7 +18973,7 @@ module \LDST_dec58 wire $1\LDST_dec58_sgn_ext[0:0] attribute \src "libresoc.v:13594.3-13609.6" wire width 2 $1\LDST_dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -18983,7 +18983,7 @@ module \LDST_dec58 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -18991,7 +18991,7 @@ module \LDST_dec58 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -19006,7 +19006,7 @@ module \LDST_dec58 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19014,7 +19014,7 @@ module \LDST_dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19031,7 +19031,7 @@ module \LDST_dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19107,9 +19107,9 @@ module \LDST_dec58 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19117,30 +19117,30 @@ module \LDST_dec58 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec58_upd attribute \src "libresoc.v:13237.7-13237.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 2 \opcode_switch attribute \src "libresoc.v:13237.7-13237.20" process $proc$libresoc.v:13237$279 @@ -19161,7 +19161,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19192,7 +19192,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19223,7 +19223,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19254,7 +19254,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19285,7 +19285,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19316,7 +19316,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19347,7 +19347,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19378,7 +19378,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19409,7 +19409,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19440,7 +19440,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19471,7 +19471,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19502,7 +19502,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19533,7 +19533,7 @@ module \LDST_dec58 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19557,7 +19557,7 @@ module \LDST_dec58 end attribute \src "libresoc.v:13631.1-13983.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec62" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" attribute \generator "nMigen" module \LDST_dec62 attribute \src "libresoc.v:13826.3-13838.6" @@ -19614,7 +19614,7 @@ module \LDST_dec62 wire $1\LDST_dec62_sgn_ext[0:0] attribute \src "libresoc.v:13956.3-13968.6" wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -19624,7 +19624,7 @@ module \LDST_dec62 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -19632,7 +19632,7 @@ module \LDST_dec62 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -19647,7 +19647,7 @@ module \LDST_dec62 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -19655,7 +19655,7 @@ module \LDST_dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -19672,7 +19672,7 @@ module \LDST_dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -19748,9 +19748,9 @@ module \LDST_dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -19758,30 +19758,30 @@ module \LDST_dec62 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LDST_dec62_upd attribute \src "libresoc.v:13632.7-13632.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 2 \opcode_switch attribute \src "libresoc.v:13632.7-13632.20" process $proc$libresoc.v:13632$293 @@ -19802,7 +19802,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19829,7 +19829,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19856,7 +19856,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19883,7 +19883,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19910,7 +19910,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19937,7 +19937,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19964,7 +19964,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -19991,7 +19991,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20018,7 +20018,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20045,7 +20045,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20072,7 +20072,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20099,7 +20099,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20126,7 +20126,7 @@ module \LDST_dec62 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -20146,7 +20146,7 @@ module \LDST_dec62 end attribute \src "libresoc.v:13987.1-14725.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" attribute \generator "nMigen" module \LOGICAL_dec31 attribute \src "libresoc.v:14695.3-14707.6" @@ -20215,7 +20215,7 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20223,15 +20223,15 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LOGICAL_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20241,7 +20241,7 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20249,15 +20249,15 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -20272,7 +20272,7 @@ module \LOGICAL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20280,7 +20280,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20297,7 +20297,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20373,13 +20373,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20387,17 +20387,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -20407,7 +20407,7 @@ module \LOGICAL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -20415,15 +20415,15 @@ module \LOGICAL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -20438,7 +20438,7 @@ module \LOGICAL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20446,7 +20446,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20463,7 +20463,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20539,13 +20539,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20553,17 +20553,17 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -20578,7 +20578,7 @@ module \LOGICAL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -20586,7 +20586,7 @@ module \LOGICAL_dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -20603,7 +20603,7 @@ module \LOGICAL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -20679,13 +20679,13 @@ module \LOGICAL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -20693,23 +20693,23 @@ module \LOGICAL_dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \LOGICAL_dec31_sgn attribute \src "libresoc.v:13988.7-13988.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:14505.27-14521.4" @@ -20768,7 +20768,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20795,7 +20795,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20822,7 +20822,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20849,7 +20849,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20876,7 +20876,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20903,7 +20903,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20930,7 +20930,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20957,7 +20957,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -20984,7 +20984,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21011,7 +21011,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21038,7 +21038,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21065,7 +21065,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21092,7 +21092,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21119,7 +21119,7 @@ module \LOGICAL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11100 @@ -21142,7 +21142,7 @@ module \LOGICAL_dec31 end attribute \src "libresoc.v:14729.1-15390.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub26 attribute \src "libresoc.v:15219.3-15252.6" @@ -21211,7 +21211,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -21219,15 +21219,15 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LOGICAL_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -21242,7 +21242,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -21250,7 +21250,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -21267,7 +21267,7 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -21343,13 +21343,13 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LOGICAL_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -21357,21 +21357,21 @@ module \LOGICAL_dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \LOGICAL_dec31_dec_sub26_sgn attribute \src "libresoc.v:14730.7-14730.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:14730.7-14730.20" process $proc$libresoc.v:14730$323 @@ -21392,7 +21392,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21447,7 +21447,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21502,7 +21502,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21557,7 +21557,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21612,7 +21612,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21667,7 +21667,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21722,7 +21722,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21777,7 +21777,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21832,7 +21832,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21887,7 +21887,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21942,7 +21942,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -21997,7 +21997,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22052,7 +22052,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22107,7 +22107,7 @@ module \LOGICAL_dec31_dec_sub26 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -22155,7 +22155,7 @@ module \LOGICAL_dec31_dec_sub26 end attribute \src "libresoc.v:15394.1-16097.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" attribute \generator "nMigen" module \LOGICAL_dec31_dec_sub28 attribute \src "libresoc.v:15911.3-15947.6" @@ -22224,7 +22224,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -22232,15 +22232,15 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LOGICAL_dec31_dec_sub28_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -22255,7 +22255,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -22263,7 +22263,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -22280,7 +22280,7 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -22356,13 +22356,13 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LOGICAL_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -22370,21 +22370,21 @@ module \LOGICAL_dec31_dec_sub28 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \LOGICAL_dec31_dec_sub28_sgn attribute \src "libresoc.v:15395.7-15395.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:15395.7-15395.20" process $proc$libresoc.v:15395$338 @@ -22405,7 +22405,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22464,7 +22464,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22523,7 +22523,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22582,7 +22582,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22641,7 +22641,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22700,7 +22700,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22759,7 +22759,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22818,7 +22818,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22877,7 +22877,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22936,7 +22936,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -22995,7 +22995,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23054,7 +23054,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23113,7 +23113,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23172,7 +23172,7 @@ module \LOGICAL_dec31_dec_sub28 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -23224,7 +23224,7 @@ module \LOGICAL_dec31_dec_sub28 end attribute \src "libresoc.v:16101.1-16659.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" attribute \generator "nMigen" module \MUL_dec31 attribute \src "libresoc.v:16616.3-16628.6" @@ -23269,7 +23269,7 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23277,7 +23277,7 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \MUL_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23287,7 +23287,7 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23295,7 +23295,7 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -23310,7 +23310,7 @@ module \MUL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23327,7 +23327,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23403,19 +23403,19 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \MUL_dec31_dec_sub11_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -23425,7 +23425,7 @@ module \MUL_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23433,7 +23433,7 @@ module \MUL_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -23448,7 +23448,7 @@ module \MUL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23465,7 +23465,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23541,19 +23541,19 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \MUL_dec31_dec_sub9_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -23568,7 +23568,7 @@ module \MUL_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -23585,7 +23585,7 @@ module \MUL_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -23661,25 +23661,25 @@ module \MUL_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 7 \MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 8 \MUL_dec31_sgn attribute \src "libresoc.v:16102.7-16102.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 attribute \src "libresoc.v:16529.23-16539.4" @@ -23726,7 +23726,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23753,7 +23753,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23780,7 +23780,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23807,7 +23807,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23834,7 +23834,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23861,7 +23861,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23888,7 +23888,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23915,7 +23915,7 @@ module \MUL_dec31 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01001 @@ -23938,7 +23938,7 @@ module \MUL_dec31 end attribute \src "libresoc.v:16663.1-17014.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" attribute \generator "nMigen" module \MUL_dec31_dec_sub11 attribute \src "libresoc.v:16888.3-16912.6" @@ -23983,7 +23983,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -23991,7 +23991,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -24006,7 +24006,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24023,7 +24023,7 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24099,23 +24099,23 @@ module \MUL_dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 7 \MUL_dec31_dec_sub11_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 8 \MUL_dec31_dec_sub11_sgn attribute \src "libresoc.v:16664.7-16664.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:16664.7-16664.20" process $proc$libresoc.v:16664$356 @@ -24136,7 +24136,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24179,7 +24179,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24222,7 +24222,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24265,7 +24265,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24308,7 +24308,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24351,7 +24351,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24394,7 +24394,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24437,7 +24437,7 @@ module \MUL_dec31_dec_sub11 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24473,7 +24473,7 @@ module \MUL_dec31_dec_sub11 end attribute \src "libresoc.v:17018.1-17369.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" attribute \generator "nMigen" module \MUL_dec31_dec_sub9 attribute \src "libresoc.v:17243.3-17267.6" @@ -24518,7 +24518,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -24526,7 +24526,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -24541,7 +24541,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -24558,7 +24558,7 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -24634,23 +24634,23 @@ module \MUL_dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 7 \MUL_dec31_dec_sub9_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 8 \MUL_dec31_dec_sub9_sgn attribute \src "libresoc.v:17019.7-17019.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch attribute \src "libresoc.v:17019.7-17019.20" process $proc$libresoc.v:17019$365 @@ -24671,7 +24671,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24714,7 +24714,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24757,7 +24757,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24800,7 +24800,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24843,7 +24843,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24886,7 +24886,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24929,7 +24929,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -24972,7 +24972,7 @@ module \MUL_dec31_dec_sub9 case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -25006,52 +25006,56 @@ module \MUL_dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:17373.1-17904.10" +attribute \src "libresoc.v:17373.1-17944.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" attribute \generator "nMigen" module \SHIFT_ROT_dec30 - attribute \src "libresoc.v:17681.3-17717.6" + attribute \src "libresoc.v:17721.3-17757.6" wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17718.3-17754.6" + attribute \src "libresoc.v:17758.3-17794.6" wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17792.3-17828.6" + attribute \src "libresoc.v:17832.3-17868.6" wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17829.3-17865.6" + attribute \src "libresoc.v:17906.3-17942.6" wire $0\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17533.3-17569.6" + attribute \src "libresoc.v:17536.3-17572.6" wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17644.3-17680.6" + attribute \src "libresoc.v:17684.3-17720.6" wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17607.3-17643.6" + attribute \src "libresoc.v:17647.3-17683.6" wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17866.3-17902.6" + attribute \src "libresoc.v:17869.3-17905.6" + wire $0\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17573.3-17609.6" wire $0\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17755.3-17791.6" + attribute \src "libresoc.v:17795.3-17831.6" wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17570.3-17606.6" + attribute \src "libresoc.v:17610.3-17646.6" wire $0\SHIFT_ROT_dec30_sgn[0:0] attribute \src "libresoc.v:17374.7-17374.20" wire $0\initial[0:0] - attribute \src "libresoc.v:17681.3-17717.6" + attribute \src "libresoc.v:17721.3-17757.6" wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17718.3-17754.6" + attribute \src "libresoc.v:17758.3-17794.6" wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17792.3-17828.6" + attribute \src "libresoc.v:17832.3-17868.6" wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17829.3-17865.6" + attribute \src "libresoc.v:17906.3-17942.6" wire $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17533.3-17569.6" + attribute \src "libresoc.v:17536.3-17572.6" wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17644.3-17680.6" + attribute \src "libresoc.v:17684.3-17720.6" wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17607.3-17643.6" + attribute \src "libresoc.v:17647.3-17683.6" wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17866.3-17902.6" + attribute \src "libresoc.v:17869.3-17905.6" + wire $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17573.3-17609.6" wire $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17755.3-17791.6" + attribute \src "libresoc.v:17795.3-17831.6" wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17570.3-17606.6" + attribute \src "libresoc.v:17610.3-17646.6" wire $1\SHIFT_ROT_dec30_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25061,7 +25065,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25069,16 +25073,16 @@ module \SHIFT_ROT_dec30 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -25092,7 +25096,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -25109,7 +25113,7 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -25185,44 +25189,46 @@ module \SHIFT_ROT_dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec30_sgn attribute \src "libresoc.v:17374.7-17374.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 4 \opcode_switch attribute \src "libresoc.v:17374.7-17374.20" - process $proc$libresoc.v:17374$376 + process $proc$libresoc.v:17374$377 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:17533.3-17569.6" - process $proc$libresoc.v:17533$366 + attribute \src "libresoc.v:17536.3-17572.6" + process $proc$libresoc.v:17536$366 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17534.5-17534.29" + attribute \src "libresoc.v:17537.5-17537.29" switch \initial - attribute \src "libresoc.v:17534.9-17534.17" + attribute \src "libresoc.v:17537.9-17537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25270,18 +25276,77 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] end - attribute \src "libresoc.v:17570.3-17606.6" - process $proc$libresoc.v:17570$367 + attribute \src "libresoc.v:17573.3-17609.6" + process $proc$libresoc.v:17573$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17574.5-17574.29" + switch \initial + attribute \src "libresoc.v:17574.9-17574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + attribute \src "libresoc.v:17610.3-17646.6" + process $proc$libresoc.v:17610$368 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17571.5-17571.29" + attribute \src "libresoc.v:17611.5-17611.29" switch \initial - attribute \src "libresoc.v:17571.9-17571.17" + attribute \src "libresoc.v:17611.9-17611.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25329,18 +25394,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] end - attribute \src "libresoc.v:17607.3-17643.6" - process $proc$libresoc.v:17607$368 + attribute \src "libresoc.v:17647.3-17683.6" + process $proc$libresoc.v:17647$369 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17608.5-17608.29" + attribute \src "libresoc.v:17648.5-17648.29" switch \initial - attribute \src "libresoc.v:17608.9-17608.17" + attribute \src "libresoc.v:17648.9-17648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25388,18 +25453,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] end - attribute \src "libresoc.v:17644.3-17680.6" - process $proc$libresoc.v:17644$369 + attribute \src "libresoc.v:17684.3-17720.6" + process $proc$libresoc.v:17684$370 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17645.5-17645.29" + attribute \src "libresoc.v:17685.5-17685.29" switch \initial - attribute \src "libresoc.v:17645.9-17645.17" + attribute \src "libresoc.v:17685.9-17685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25447,18 +25512,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] end - attribute \src "libresoc.v:17681.3-17717.6" - process $proc$libresoc.v:17681$370 + attribute \src "libresoc.v:17721.3-17757.6" + process $proc$libresoc.v:17721$371 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17682.5-17682.29" + attribute \src "libresoc.v:17722.5-17722.29" switch \initial - attribute \src "libresoc.v:17682.9-17682.17" + attribute \src "libresoc.v:17722.9-17722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25506,18 +25571,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] end - attribute \src "libresoc.v:17718.3-17754.6" - process $proc$libresoc.v:17718$371 + attribute \src "libresoc.v:17758.3-17794.6" + process $proc$libresoc.v:17758$372 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17719.5-17719.29" + attribute \src "libresoc.v:17759.5-17759.29" switch \initial - attribute \src "libresoc.v:17719.9-17719.17" + attribute \src "libresoc.v:17759.9-17759.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25565,18 +25630,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] end - attribute \src "libresoc.v:17755.3-17791.6" - process $proc$libresoc.v:17755$372 + attribute \src "libresoc.v:17795.3-17831.6" + process $proc$libresoc.v:17795$373 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17756.5-17756.29" + attribute \src "libresoc.v:17796.5-17796.29" switch \initial - attribute \src "libresoc.v:17756.9-17756.17" + attribute \src "libresoc.v:17796.9-17796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25624,18 +25689,18 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] end - attribute \src "libresoc.v:17792.3-17828.6" - process $proc$libresoc.v:17792$373 + attribute \src "libresoc.v:17832.3-17868.6" + process $proc$libresoc.v:17832$374 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17793.5-17793.29" + attribute \src "libresoc.v:17833.5-17833.29" switch \initial - attribute \src "libresoc.v:17793.9-17793.17" + attribute \src "libresoc.v:17833.9-17833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -25683,172 +25748,176 @@ module \SHIFT_ROT_dec30 sync always update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] end - attribute \src "libresoc.v:17829.3-17865.6" - process $proc$libresoc.v:17829$374 + attribute \src "libresoc.v:17869.3-17905.6" + process $proc$libresoc.v:17869$375 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17830.5-17830.29" + assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17870.5-17870.29" switch \initial - attribute \src "libresoc.v:17830.9-17830.17" + attribute \src "libresoc.v:17870.9-17870.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 case - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 end sync always - update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] end - attribute \src "libresoc.v:17866.3-17902.6" - process $proc$libresoc.v:17866$375 + attribute \src "libresoc.v:17906.3-17942.6" + process $proc$libresoc.v:17906$376 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17867.5-17867.29" + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17907.5-17907.29" switch \initial - attribute \src "libresoc.v:17867.9-17867.17" + attribute \src "libresoc.v:17907.9-17907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 case - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 end sync always - update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:17908.1-18712.10" +attribute \src "libresoc.v:17948.1-18780.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" attribute \generator "nMigen" module \SHIFT_ROT_dec31 - attribute \src "libresoc.v:18675.3-18690.6" + attribute \src "libresoc.v:18743.3-18758.6" wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18691.3-18706.6" + attribute \src "libresoc.v:18759.3-18774.6" wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18563.3-18578.6" + attribute \src "libresoc.v:18615.3-18630.6" wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18579.3-18594.6" + attribute \src "libresoc.v:18647.3-18662.6" wire $0\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18627.3-18642.6" + attribute \src "libresoc.v:18695.3-18710.6" wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18659.3-18674.6" + attribute \src "libresoc.v:18727.3-18742.6" wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18643.3-18658.6" + attribute \src "libresoc.v:18711.3-18726.6" wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18595.3-18610.6" + attribute \src "libresoc.v:18631.3-18646.6" + wire $0\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18663.3-18678.6" wire $0\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18547.3-18562.6" + attribute \src "libresoc.v:18599.3-18614.6" wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18611.3-18626.6" + attribute \src "libresoc.v:18679.3-18694.6" wire $0\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:17909.7-17909.20" + attribute \src "libresoc.v:17949.7-17949.20" wire $0\initial[0:0] - attribute \src "libresoc.v:18675.3-18690.6" + attribute \src "libresoc.v:18743.3-18758.6" wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18691.3-18706.6" + attribute \src "libresoc.v:18759.3-18774.6" wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18563.3-18578.6" + attribute \src "libresoc.v:18615.3-18630.6" wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18579.3-18594.6" + attribute \src "libresoc.v:18647.3-18662.6" wire $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18627.3-18642.6" + attribute \src "libresoc.v:18695.3-18710.6" wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18659.3-18674.6" + attribute \src "libresoc.v:18727.3-18742.6" wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18643.3-18658.6" + attribute \src "libresoc.v:18711.3-18726.6" wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18595.3-18610.6" + attribute \src "libresoc.v:18631.3-18646.6" + wire $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18663.3-18678.6" wire $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18547.3-18562.6" + attribute \src "libresoc.v:18599.3-18614.6" wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18611.3-18626.6" + attribute \src "libresoc.v:18679.3-18694.6" wire $1\SHIFT_ROT_dec31_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -25858,7 +25927,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25866,16 +25935,16 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -25884,7 +25953,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -25892,15 +25961,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -25915,7 +25984,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -25932,7 +26001,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26008,19 +26077,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26030,7 +26101,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26038,15 +26109,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -26061,7 +26132,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26078,7 +26149,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26154,19 +26225,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26176,7 +26249,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26184,15 +26257,15 @@ module \SHIFT_ROT_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -26207,7 +26280,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26224,7 +26297,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26300,19 +26373,21 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -26327,7 +26402,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26344,7 +26419,7 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26420,28 +26495,30 @@ module \SHIFT_ROT_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_sgn - attribute \src "libresoc.v:17909.7-17909.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:17949.7-17949.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:18508.29-18520.4" + attribute \src "libresoc.v:18557.29-18570.4" cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out @@ -26450,13 +26527,14 @@ module \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18521.29-18533.4" + attribute \src "libresoc.v:18571.29-18584.4" cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out @@ -26465,13 +26543,14 @@ module \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:18534.29-18546.4" + attribute \src "libresoc.v:18585.29-18598.4" cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out @@ -26480,31 +26559,32 @@ module \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in end - attribute \src "libresoc.v:17909.7-17909.20" - process $proc$libresoc.v:17909$387 + attribute \src "libresoc.v:17949.7-17949.20" + process $proc$libresoc.v:17949$389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:18547.3-18562.6" - process $proc$libresoc.v:18547$377 + attribute \src "libresoc.v:18599.3-18614.6" + process $proc$libresoc.v:18599$378 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18548.5-18548.29" + attribute \src "libresoc.v:18600.5-18600.29" switch \initial - attribute \src "libresoc.v:18548.9-18548.17" + attribute \src "libresoc.v:18600.9-18600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26524,18 +26604,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:18563.3-18578.6" - process $proc$libresoc.v:18563$378 + attribute \src "libresoc.v:18615.3-18630.6" + process $proc$libresoc.v:18615$379 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18564.5-18564.29" + attribute \src "libresoc.v:18616.5-18616.29" switch \initial - attribute \src "libresoc.v:18564.9-18564.17" + attribute \src "libresoc.v:18616.9-18616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26555,18 +26635,49 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] end - attribute \src "libresoc.v:18579.3-18594.6" - process $proc$libresoc.v:18579$379 + attribute \src "libresoc.v:18631.3-18646.6" + process $proc$libresoc.v:18631$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18632.5-18632.29" + switch \initial + attribute \src "libresoc.v:18632.9-18632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + case + assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:18647.3-18662.6" + process $proc$libresoc.v:18647$381 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18580.5-18580.29" + attribute \src "libresoc.v:18648.5-18648.29" switch \initial - attribute \src "libresoc.v:18580.9-18580.17" + attribute \src "libresoc.v:18648.9-18648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26586,18 +26697,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] end - attribute \src "libresoc.v:18595.3-18610.6" - process $proc$libresoc.v:18595$380 + attribute \src "libresoc.v:18663.3-18678.6" + process $proc$libresoc.v:18663$382 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18596.5-18596.29" + attribute \src "libresoc.v:18664.5-18664.29" switch \initial - attribute \src "libresoc.v:18596.9-18596.17" + attribute \src "libresoc.v:18664.9-18664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26617,18 +26728,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] end - attribute \src "libresoc.v:18611.3-18626.6" - process $proc$libresoc.v:18611$381 + attribute \src "libresoc.v:18679.3-18694.6" + process $proc$libresoc.v:18679$383 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:18612.5-18612.29" + attribute \src "libresoc.v:18680.5-18680.29" switch \initial - attribute \src "libresoc.v:18612.9-18612.17" + attribute \src "libresoc.v:18680.9-18680.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26648,18 +26759,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] end - attribute \src "libresoc.v:18627.3-18642.6" - process $proc$libresoc.v:18627$382 + attribute \src "libresoc.v:18695.3-18710.6" + process $proc$libresoc.v:18695$384 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18628.5-18628.29" + attribute \src "libresoc.v:18696.5-18696.29" switch \initial - attribute \src "libresoc.v:18628.9-18628.17" + attribute \src "libresoc.v:18696.9-18696.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26679,18 +26790,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] end - attribute \src "libresoc.v:18643.3-18658.6" - process $proc$libresoc.v:18643$383 + attribute \src "libresoc.v:18711.3-18726.6" + process $proc$libresoc.v:18711$385 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18644.5-18644.29" + attribute \src "libresoc.v:18712.5-18712.29" switch \initial - attribute \src "libresoc.v:18644.9-18644.17" + attribute \src "libresoc.v:18712.9-18712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26710,18 +26821,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] end - attribute \src "libresoc.v:18659.3-18674.6" - process $proc$libresoc.v:18659$384 + attribute \src "libresoc.v:18727.3-18742.6" + process $proc$libresoc.v:18727$386 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18660.5-18660.29" + attribute \src "libresoc.v:18728.5-18728.29" switch \initial - attribute \src "libresoc.v:18660.9-18660.17" + attribute \src "libresoc.v:18728.9-18728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26741,18 +26852,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] end - attribute \src "libresoc.v:18675.3-18690.6" - process $proc$libresoc.v:18675$385 + attribute \src "libresoc.v:18743.3-18758.6" + process $proc$libresoc.v:18743$387 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18676.5-18676.29" + attribute \src "libresoc.v:18744.5-18744.29" switch \initial - attribute \src "libresoc.v:18676.9-18676.17" + attribute \src "libresoc.v:18744.9-18744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26772,18 +26883,18 @@ module \SHIFT_ROT_dec31 sync always update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] end - attribute \src "libresoc.v:18691.3-18706.6" - process $proc$libresoc.v:18691$386 + attribute \src "libresoc.v:18759.3-18774.6" + process $proc$libresoc.v:18759$388 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18692.5-18692.29" + attribute \src "libresoc.v:18760.5-18760.29" switch \initial - attribute \src "libresoc.v:18692.9-18692.17" + attribute \src "libresoc.v:18760.9-18760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -26809,52 +26920,56 @@ module \SHIFT_ROT_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:18716.1-19067.10" +attribute \src "libresoc.v:18784.1-19157.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub24 - attribute \src "libresoc.v:18952.3-18970.6" + attribute \src "libresoc.v:19042.3-19060.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:18971.3-18989.6" + attribute \src "libresoc.v:19061.3-19079.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19009.3-19027.6" + attribute \src "libresoc.v:19099.3-19117.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19028.3-19046.6" + attribute \src "libresoc.v:19137.3-19155.6" wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18876.3-18894.6" + attribute \src "libresoc.v:18947.3-18965.6" wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:18933.3-18951.6" + attribute \src "libresoc.v:19023.3-19041.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:18914.3-18932.6" + attribute \src "libresoc.v:19004.3-19022.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19047.3-19065.6" + attribute \src "libresoc.v:19118.3-19136.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:18966.3-18984.6" wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:18990.3-19008.6" + attribute \src "libresoc.v:19080.3-19098.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18895.3-18913.6" + attribute \src "libresoc.v:18985.3-19003.6" wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18717.7-18717.20" + attribute \src "libresoc.v:18785.7-18785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:18952.3-18970.6" + attribute \src "libresoc.v:19042.3-19060.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:18971.3-18989.6" + attribute \src "libresoc.v:19061.3-19079.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19009.3-19027.6" + attribute \src "libresoc.v:19099.3-19117.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19028.3-19046.6" + attribute \src "libresoc.v:19137.3-19155.6" wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18876.3-18894.6" + attribute \src "libresoc.v:18947.3-18965.6" wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:18933.3-18951.6" + attribute \src "libresoc.v:19023.3-19041.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:18914.3-18932.6" + attribute \src "libresoc.v:19004.3-19022.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19047.3-19065.6" + attribute \src "libresoc.v:19118.3-19136.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:18966.3-18984.6" wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:18990.3-19008.6" + attribute \src "libresoc.v:19080.3-19098.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18895.3-18913.6" + attribute \src "libresoc.v:18985.3-19003.6" wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -26864,7 +26979,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -26872,16 +26987,16 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -26895,7 +27010,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -26912,7 +27027,7 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -26988,44 +27103,46 @@ module \SHIFT_ROT_dec31_dec_sub24 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "libresoc.v:18717.7-18717.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "libresoc.v:18785.7-18785.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:18717.7-18717.20" - process $proc$libresoc.v:18717$398 + attribute \src "libresoc.v:18785.7-18785.20" + process $proc$libresoc.v:18785$401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:18876.3-18894.6" - process $proc$libresoc.v:18876$388 + attribute \src "libresoc.v:18947.3-18965.6" + process $proc$libresoc.v:18947$390 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:18877.5-18877.29" + attribute \src "libresoc.v:18948.5-18948.29" switch \initial - attribute \src "libresoc.v:18877.9-18877.17" + attribute \src "libresoc.v:18948.9-18948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27049,18 +27166,53 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] end - attribute \src "libresoc.v:18895.3-18913.6" - process $proc$libresoc.v:18895$389 + attribute \src "libresoc.v:18966.3-18984.6" + process $proc$libresoc.v:18966$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:18967.5-18967.29" + switch \initial + attribute \src "libresoc.v:18967.9-18967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:18985.3-19003.6" + process $proc$libresoc.v:18985$392 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18896.5-18896.29" + attribute \src "libresoc.v:18986.5-18986.29" switch \initial - attribute \src "libresoc.v:18896.9-18896.17" + attribute \src "libresoc.v:18986.9-18986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27084,18 +27236,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:18914.3-18932.6" - process $proc$libresoc.v:18914$390 + attribute \src "libresoc.v:19004.3-19022.6" + process $proc$libresoc.v:19004$393 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:18915.5-18915.29" + attribute \src "libresoc.v:19005.5-19005.29" switch \initial - attribute \src "libresoc.v:18915.9-18915.17" + attribute \src "libresoc.v:19005.9-19005.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27119,18 +27271,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:18933.3-18951.6" - process $proc$libresoc.v:18933$391 + attribute \src "libresoc.v:19023.3-19041.6" + process $proc$libresoc.v:19023$394 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:18934.5-18934.29" + attribute \src "libresoc.v:19024.5-19024.29" switch \initial - attribute \src "libresoc.v:18934.9-18934.17" + attribute \src "libresoc.v:19024.9-19024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27154,18 +27306,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:18952.3-18970.6" - process $proc$libresoc.v:18952$392 + attribute \src "libresoc.v:19042.3-19060.6" + process $proc$libresoc.v:19042$395 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:18953.5-18953.29" + attribute \src "libresoc.v:19043.5-19043.29" switch \initial - attribute \src "libresoc.v:18953.9-18953.17" + attribute \src "libresoc.v:19043.9-19043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27189,18 +27341,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:18971.3-18989.6" - process $proc$libresoc.v:18971$393 + attribute \src "libresoc.v:19061.3-19079.6" + process $proc$libresoc.v:19061$396 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:18972.5-18972.29" + attribute \src "libresoc.v:19062.5-19062.29" switch \initial - attribute \src "libresoc.v:18972.9-18972.17" + attribute \src "libresoc.v:19062.9-19062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27224,18 +27376,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:18990.3-19008.6" - process $proc$libresoc.v:18990$394 + attribute \src "libresoc.v:19080.3-19098.6" + process $proc$libresoc.v:19080$397 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18991.5-18991.29" + attribute \src "libresoc.v:19081.5-19081.29" switch \initial - attribute \src "libresoc.v:18991.9-18991.17" + attribute \src "libresoc.v:19081.9-19081.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27259,18 +27411,18 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:19009.3-19027.6" - process $proc$libresoc.v:19009$395 + attribute \src "libresoc.v:19099.3-19117.6" + process $proc$libresoc.v:19099$398 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19010.5-19010.29" + attribute \src "libresoc.v:19100.5-19100.29" switch \initial - attribute \src "libresoc.v:19010.9-19010.17" + attribute \src "libresoc.v:19100.9-19100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -27294,124 +27446,128 @@ module \SHIFT_ROT_dec31_dec_sub24 sync always update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:19028.3-19046.6" - process $proc$libresoc.v:19028$396 + attribute \src "libresoc.v:19118.3-19136.6" + process $proc$libresoc.v:19118$399 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19029.5-19029.29" + assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19119.5-19119.29" switch \initial - attribute \src "libresoc.v:19029.9-19029.17" + attribute \src "libresoc.v:19119.9-19119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 case - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:19047.3-19065.6" - process $proc$libresoc.v:19047$397 + attribute \src "libresoc.v:19137.3-19155.6" + process $proc$libresoc.v:19137$400 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19048.5-19048.29" + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19138.5-19138.29" switch \initial - attribute \src "libresoc.v:19048.9-19048.17" + attribute \src "libresoc.v:19138.9-19138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 case - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19071.1-19392.10" +attribute \src "libresoc.v:19161.1-19501.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub26 - attribute \src "libresoc.v:19295.3-19310.6" + attribute \src "libresoc.v:19404.3-19419.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19311.3-19326.6" + attribute \src "libresoc.v:19420.3-19435.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19343.3-19358.6" + attribute \src "libresoc.v:19452.3-19467.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19359.3-19374.6" + attribute \src "libresoc.v:19484.3-19499.6" wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19231.3-19246.6" + attribute \src "libresoc.v:19324.3-19339.6" wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19279.3-19294.6" + attribute \src "libresoc.v:19388.3-19403.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19263.3-19278.6" + attribute \src "libresoc.v:19372.3-19387.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19375.3-19390.6" + attribute \src "libresoc.v:19468.3-19483.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19340.3-19355.6" wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19327.3-19342.6" + attribute \src "libresoc.v:19436.3-19451.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19247.3-19262.6" + attribute \src "libresoc.v:19356.3-19371.6" wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19072.7-19072.20" + attribute \src "libresoc.v:19162.7-19162.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19295.3-19310.6" + attribute \src "libresoc.v:19404.3-19419.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19311.3-19326.6" + attribute \src "libresoc.v:19420.3-19435.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19343.3-19358.6" + attribute \src "libresoc.v:19452.3-19467.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19359.3-19374.6" + attribute \src "libresoc.v:19484.3-19499.6" wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19231.3-19246.6" + attribute \src "libresoc.v:19324.3-19339.6" wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19279.3-19294.6" + attribute \src "libresoc.v:19388.3-19403.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19263.3-19278.6" + attribute \src "libresoc.v:19372.3-19387.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19375.3-19390.6" + attribute \src "libresoc.v:19468.3-19483.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19340.3-19355.6" wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19327.3-19342.6" + attribute \src "libresoc.v:19436.3-19451.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19247.3-19262.6" + attribute \src "libresoc.v:19356.3-19371.6" wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -27421,7 +27577,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27429,16 +27585,16 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -27452,7 +27608,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27469,7 +27625,7 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -27545,44 +27701,46 @@ module \SHIFT_ROT_dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "libresoc.v:19072.7-19072.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:19162.7-19162.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:19072.7-19072.20" - process $proc$libresoc.v:19072$409 + attribute \src "libresoc.v:19162.7-19162.20" + process $proc$libresoc.v:19162$413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19231.3-19246.6" - process $proc$libresoc.v:19231$399 + attribute \src "libresoc.v:19324.3-19339.6" + process $proc$libresoc.v:19324$402 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19232.5-19232.29" + attribute \src "libresoc.v:19325.5-19325.29" switch \initial - attribute \src "libresoc.v:19232.9-19232.17" + attribute \src "libresoc.v:19325.9-19325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27602,18 +27760,49 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] end - attribute \src "libresoc.v:19247.3-19262.6" - process $proc$libresoc.v:19247$400 + attribute \src "libresoc.v:19340.3-19355.6" + process $proc$libresoc.v:19340$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19341.5-19341.29" + switch \initial + attribute \src "libresoc.v:19341.9-19341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:19356.3-19371.6" + process $proc$libresoc.v:19356$404 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19248.5-19248.29" + attribute \src "libresoc.v:19357.5-19357.29" switch \initial - attribute \src "libresoc.v:19248.9-19248.17" + attribute \src "libresoc.v:19357.9-19357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27633,18 +27822,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:19263.3-19278.6" - process $proc$libresoc.v:19263$401 + attribute \src "libresoc.v:19372.3-19387.6" + process $proc$libresoc.v:19372$405 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19264.5-19264.29" + attribute \src "libresoc.v:19373.5-19373.29" switch \initial - attribute \src "libresoc.v:19264.9-19264.17" + attribute \src "libresoc.v:19373.9-19373.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27664,18 +27853,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:19279.3-19294.6" - process $proc$libresoc.v:19279$402 + attribute \src "libresoc.v:19388.3-19403.6" + process $proc$libresoc.v:19388$406 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19280.5-19280.29" + attribute \src "libresoc.v:19389.5-19389.29" switch \initial - attribute \src "libresoc.v:19280.9-19280.17" + attribute \src "libresoc.v:19389.9-19389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27695,18 +27884,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:19295.3-19310.6" - process $proc$libresoc.v:19295$403 + attribute \src "libresoc.v:19404.3-19419.6" + process $proc$libresoc.v:19404$407 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19296.5-19296.29" + attribute \src "libresoc.v:19405.5-19405.29" switch \initial - attribute \src "libresoc.v:19296.9-19296.17" + attribute \src "libresoc.v:19405.9-19405.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27726,18 +27915,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:19311.3-19326.6" - process $proc$libresoc.v:19311$404 + attribute \src "libresoc.v:19420.3-19435.6" + process $proc$libresoc.v:19420$408 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19312.5-19312.29" + attribute \src "libresoc.v:19421.5-19421.29" switch \initial - attribute \src "libresoc.v:19312.9-19312.17" + attribute \src "libresoc.v:19421.9-19421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27757,18 +27946,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:19327.3-19342.6" - process $proc$libresoc.v:19327$405 + attribute \src "libresoc.v:19436.3-19451.6" + process $proc$libresoc.v:19436$409 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19328.5-19328.29" + attribute \src "libresoc.v:19437.5-19437.29" switch \initial - attribute \src "libresoc.v:19328.9-19328.17" + attribute \src "libresoc.v:19437.9-19437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27788,18 +27977,18 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:19343.3-19358.6" - process $proc$libresoc.v:19343$406 + attribute \src "libresoc.v:19452.3-19467.6" + process $proc$libresoc.v:19452$410 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19344.5-19344.29" + attribute \src "libresoc.v:19453.5-19453.29" switch \initial - attribute \src "libresoc.v:19344.9-19344.17" + attribute \src "libresoc.v:19453.9-19453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -27819,116 +28008,120 @@ module \SHIFT_ROT_dec31_dec_sub26 sync always update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:19359.3-19374.6" - process $proc$libresoc.v:19359$407 + attribute \src "libresoc.v:19468.3-19483.6" + process $proc$libresoc.v:19468$411 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19360.5-19360.29" + assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19469.5-19469.29" switch \initial - attribute \src "libresoc.v:19360.9-19360.17" + attribute \src "libresoc.v:19469.9-19469.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 case - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:19375.3-19390.6" - process $proc$libresoc.v:19375$408 + attribute \src "libresoc.v:19484.3-19499.6" + process $proc$libresoc.v:19484$412 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19376.5-19376.29" + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19485.5-19485.29" switch \initial - attribute \src "libresoc.v:19376.9-19376.17" + attribute \src "libresoc.v:19485.9-19485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 case - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19396.1-19747.10" +attribute \src "libresoc.v:19505.1-19878.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" attribute \generator "nMigen" module \SHIFT_ROT_dec31_dec_sub27 - attribute \src "libresoc.v:19632.3-19650.6" + attribute \src "libresoc.v:19763.3-19781.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19651.3-19669.6" + attribute \src "libresoc.v:19782.3-19800.6" wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19689.3-19707.6" + attribute \src "libresoc.v:19820.3-19838.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19708.3-19726.6" + attribute \src "libresoc.v:19858.3-19876.6" wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19556.3-19574.6" + attribute \src "libresoc.v:19668.3-19686.6" wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19613.3-19631.6" + attribute \src "libresoc.v:19744.3-19762.6" wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19594.3-19612.6" + attribute \src "libresoc.v:19725.3-19743.6" wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19727.3-19745.6" + attribute \src "libresoc.v:19839.3-19857.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19687.3-19705.6" wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19670.3-19688.6" + attribute \src "libresoc.v:19801.3-19819.6" wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19575.3-19593.6" + attribute \src "libresoc.v:19706.3-19724.6" wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19397.7-19397.20" + attribute \src "libresoc.v:19506.7-19506.20" wire $0\initial[0:0] - attribute \src "libresoc.v:19632.3-19650.6" + attribute \src "libresoc.v:19763.3-19781.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19651.3-19669.6" + attribute \src "libresoc.v:19782.3-19800.6" wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19689.3-19707.6" + attribute \src "libresoc.v:19820.3-19838.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19708.3-19726.6" + attribute \src "libresoc.v:19858.3-19876.6" wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19556.3-19574.6" + attribute \src "libresoc.v:19668.3-19686.6" wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19613.3-19631.6" + attribute \src "libresoc.v:19744.3-19762.6" wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19594.3-19612.6" + attribute \src "libresoc.v:19725.3-19743.6" wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19727.3-19745.6" + attribute \src "libresoc.v:19839.3-19857.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19687.3-19705.6" wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19670.3-19688.6" + attribute \src "libresoc.v:19801.3-19819.6" wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19575.3-19593.6" + attribute \src "libresoc.v:19706.3-19724.6" wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -27938,7 +28131,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -27946,16 +28139,16 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 8 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -27969,7 +28162,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -27986,7 +28179,7 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28062,44 +28255,46 @@ module \SHIFT_ROT_dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 9 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "libresoc.v:19397.7-19397.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:19506.7-19506.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" - wire width 32 input 11 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:19397.7-19397.20" - process $proc$libresoc.v:19397$420 + attribute \src "libresoc.v:19506.7-19506.20" + process $proc$libresoc.v:19506$425 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:19556.3-19574.6" - process $proc$libresoc.v:19556$410 + attribute \src "libresoc.v:19668.3-19686.6" + process $proc$libresoc.v:19668$414 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19557.5-19557.29" + attribute \src "libresoc.v:19669.5-19669.29" switch \initial - attribute \src "libresoc.v:19557.9-19557.17" + attribute \src "libresoc.v:19669.9-19669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28123,18 +28318,53 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] end - attribute \src "libresoc.v:19575.3-19593.6" - process $proc$libresoc.v:19575$411 + attribute \src "libresoc.v:19687.3-19705.6" + process $proc$libresoc.v:19687$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19688.5-19688.29" + switch \initial + attribute \src "libresoc.v:19688.9-19688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:19706.3-19724.6" + process $proc$libresoc.v:19706$416 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19576.5-19576.29" + attribute \src "libresoc.v:19707.5-19707.29" switch \initial - attribute \src "libresoc.v:19576.9-19576.17" + attribute \src "libresoc.v:19707.9-19707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28158,18 +28388,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:19594.3-19612.6" - process $proc$libresoc.v:19594$412 + attribute \src "libresoc.v:19725.3-19743.6" + process $proc$libresoc.v:19725$417 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19595.5-19595.29" + attribute \src "libresoc.v:19726.5-19726.29" switch \initial - attribute \src "libresoc.v:19595.9-19595.17" + attribute \src "libresoc.v:19726.9-19726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28193,18 +28423,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:19613.3-19631.6" - process $proc$libresoc.v:19613$413 + attribute \src "libresoc.v:19744.3-19762.6" + process $proc$libresoc.v:19744$418 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19614.5-19614.29" + attribute \src "libresoc.v:19745.5-19745.29" switch \initial - attribute \src "libresoc.v:19614.9-19614.17" + attribute \src "libresoc.v:19745.9-19745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28228,18 +28458,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:19632.3-19650.6" - process $proc$libresoc.v:19632$414 + attribute \src "libresoc.v:19763.3-19781.6" + process $proc$libresoc.v:19763$419 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19633.5-19633.29" + attribute \src "libresoc.v:19764.5-19764.29" switch \initial - attribute \src "libresoc.v:19633.9-19633.17" + attribute \src "libresoc.v:19764.9-19764.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28263,18 +28493,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:19651.3-19669.6" - process $proc$libresoc.v:19651$415 + attribute \src "libresoc.v:19782.3-19800.6" + process $proc$libresoc.v:19782$420 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19652.5-19652.29" + attribute \src "libresoc.v:19783.5-19783.29" switch \initial - attribute \src "libresoc.v:19652.9-19652.17" + attribute \src "libresoc.v:19783.9-19783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28298,18 +28528,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:19670.3-19688.6" - process $proc$libresoc.v:19670$416 + attribute \src "libresoc.v:19801.3-19819.6" + process $proc$libresoc.v:19801$421 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19671.5-19671.29" + attribute \src "libresoc.v:19802.5-19802.29" switch \initial - attribute \src "libresoc.v:19671.9-19671.17" + attribute \src "libresoc.v:19802.9-19802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28333,18 +28563,18 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:19689.3-19707.6" - process $proc$libresoc.v:19689$417 + attribute \src "libresoc.v:19820.3-19838.6" + process $proc$libresoc.v:19820$422 assign { } { } assign { } { } assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19690.5-19690.29" + attribute \src "libresoc.v:19821.5-19821.29" switch \initial - attribute \src "libresoc.v:19690.9-19690.17" + attribute \src "libresoc.v:19821.9-19821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -28368,108 +28598,108 @@ module \SHIFT_ROT_dec31_dec_sub27 sync always update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:19708.3-19726.6" - process $proc$libresoc.v:19708$418 + attribute \src "libresoc.v:19839.3-19857.6" + process $proc$libresoc.v:19839$423 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19709.5-19709.29" + assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19840.5-19840.29" switch \initial - attribute \src "libresoc.v:19709.9-19709.17" + attribute \src "libresoc.v:19840.9-19840.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 case - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:19727.3-19745.6" - process $proc$libresoc.v:19727$419 + attribute \src "libresoc.v:19858.3-19876.6" + process $proc$libresoc.v:19858$424 assign { } { } assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19728.5-19728.29" + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19859.5-19859.29" switch \initial - attribute \src "libresoc.v:19728.9-19728.17" + attribute \src "libresoc.v:19859.9-19859.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'00000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case 5'11001 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 5'10000 assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 case - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 end sync always - update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:19751.1-20073.10" +attribute \src "libresoc.v:19882.1-20204.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" attribute \generator "nMigen" module \SPR_dec31 - attribute \src "libresoc.v:20030.3-20039.6" + attribute \src "libresoc.v:20161.3-20170.6" wire width 3 $0\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20040.3-20049.6" + attribute \src "libresoc.v:20171.3-20180.6" wire width 3 $0\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20010.3-20019.6" + attribute \src "libresoc.v:20141.3-20150.6" wire width 12 $0\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20020.3-20029.6" + attribute \src "libresoc.v:20151.3-20160.6" wire width 7 $0\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20060.3-20069.6" + attribute \src "libresoc.v:20191.3-20200.6" wire $0\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20050.3-20059.6" + attribute \src "libresoc.v:20181.3-20190.6" wire width 2 $0\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:19752.7-19752.20" + attribute \src "libresoc.v:19883.7-19883.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20030.3-20039.6" + attribute \src "libresoc.v:20161.3-20170.6" wire width 3 $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20040.3-20049.6" + attribute \src "libresoc.v:20171.3-20180.6" wire width 3 $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20010.3-20019.6" + attribute \src "libresoc.v:20141.3-20150.6" wire width 12 $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20020.3-20029.6" + attribute \src "libresoc.v:20151.3-20160.6" wire width 7 $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20060.3-20069.6" + attribute \src "libresoc.v:20191.3-20200.6" wire $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20050.3-20059.6" + attribute \src "libresoc.v:20181.3-20190.6" wire width 2 $1\SPR_dec31_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28479,7 +28709,7 @@ module \SPR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28487,7 +28717,7 @@ module \SPR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SPR_dec31_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28497,7 +28727,7 @@ module \SPR_dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28505,7 +28735,7 @@ module \SPR_dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -28520,7 +28750,7 @@ module \SPR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28596,17 +28826,17 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SPR_dec31_dec_sub19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -28621,7 +28851,7 @@ module \SPR_dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -28697,26 +28927,26 @@ module \SPR_dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 6 \SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \SPR_dec31_rc_sel - attribute \src "libresoc.v:19752.7-19752.15" + attribute \src "libresoc.v:19883.7-19883.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:20001.23-20009.4" + attribute \src "libresoc.v:20132.23-20140.4" cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out @@ -28726,26 +28956,26 @@ module \SPR_dec31 connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel connect \opcode_in \SPR_dec31_dec_sub19_opcode_in end - attribute \src "libresoc.v:19752.7-19752.20" - process $proc$libresoc.v:19752$427 + attribute \src "libresoc.v:19883.7-19883.20" + process $proc$libresoc.v:19883$432 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20010.3-20019.6" - process $proc$libresoc.v:20010$421 + attribute \src "libresoc.v:20141.3-20150.6" + process $proc$libresoc.v:20141$426 assign { } { } assign { } { } assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20011.5-20011.29" + attribute \src "libresoc.v:20142.5-20142.29" switch \initial - attribute \src "libresoc.v:20011.9-20011.17" + attribute \src "libresoc.v:20142.9-20142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28757,18 +28987,18 @@ module \SPR_dec31 sync always update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] end - attribute \src "libresoc.v:20020.3-20029.6" - process $proc$libresoc.v:20020$422 + attribute \src "libresoc.v:20151.3-20160.6" + process $proc$libresoc.v:20151$427 assign { } { } assign { } { } assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20021.5-20021.29" + attribute \src "libresoc.v:20152.5-20152.29" switch \initial - attribute \src "libresoc.v:20021.9-20021.17" + attribute \src "libresoc.v:20152.9-20152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28780,18 +29010,18 @@ module \SPR_dec31 sync always update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] end - attribute \src "libresoc.v:20030.3-20039.6" - process $proc$libresoc.v:20030$423 + attribute \src "libresoc.v:20161.3-20170.6" + process $proc$libresoc.v:20161$428 assign { } { } assign { } { } assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20031.5-20031.29" + attribute \src "libresoc.v:20162.5-20162.29" switch \initial - attribute \src "libresoc.v:20031.9-20031.17" + attribute \src "libresoc.v:20162.9-20162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28803,18 +29033,18 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] end - attribute \src "libresoc.v:20040.3-20049.6" - process $proc$libresoc.v:20040$424 + attribute \src "libresoc.v:20171.3-20180.6" + process $proc$libresoc.v:20171$429 assign { } { } assign { } { } assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20041.5-20041.29" + attribute \src "libresoc.v:20172.5-20172.29" switch \initial - attribute \src "libresoc.v:20041.9-20041.17" + attribute \src "libresoc.v:20172.9-20172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28826,18 +29056,18 @@ module \SPR_dec31 sync always update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] end - attribute \src "libresoc.v:20050.3-20059.6" - process $proc$libresoc.v:20050$425 + attribute \src "libresoc.v:20181.3-20190.6" + process $proc$libresoc.v:20181$430 assign { } { } assign { } { } assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:20051.5-20051.29" + attribute \src "libresoc.v:20182.5-20182.29" switch \initial - attribute \src "libresoc.v:20051.9-20051.17" + attribute \src "libresoc.v:20182.9-20182.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28849,18 +29079,18 @@ module \SPR_dec31 sync always update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] end - attribute \src "libresoc.v:20060.3-20069.6" - process $proc$libresoc.v:20060$426 + attribute \src "libresoc.v:20191.3-20200.6" + process $proc$libresoc.v:20191$431 assign { } { } assign { } { } assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20061.5-20061.29" + attribute \src "libresoc.v:20192.5-20192.29" switch \initial - attribute \src "libresoc.v:20061.9-20061.17" + attribute \src "libresoc.v:20192.9-20192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'10011 @@ -28876,36 +29106,36 @@ module \SPR_dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:20077.1-20285.10" +attribute \src "libresoc.v:20208.1-20416.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" attribute \generator "nMigen" module \SPR_dec31_dec_sub19 - attribute \src "libresoc.v:20232.3-20244.6" + attribute \src "libresoc.v:20363.3-20375.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20245.3-20257.6" + attribute \src "libresoc.v:20376.3-20388.6" wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20206.3-20218.6" + attribute \src "libresoc.v:20337.3-20349.6" wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20219.3-20231.6" + attribute \src "libresoc.v:20350.3-20362.6" wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20271.3-20283.6" + attribute \src "libresoc.v:20402.3-20414.6" wire $0\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20258.3-20270.6" + attribute \src "libresoc.v:20389.3-20401.6" wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20078.7-20078.20" + attribute \src "libresoc.v:20209.7-20209.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20232.3-20244.6" + attribute \src "libresoc.v:20363.3-20375.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20245.3-20257.6" + attribute \src "libresoc.v:20376.3-20388.6" wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20206.3-20218.6" + attribute \src "libresoc.v:20337.3-20349.6" wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20219.3-20231.6" + attribute \src "libresoc.v:20350.3-20362.6" wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20271.3-20283.6" + attribute \src "libresoc.v:20402.3-20414.6" wire $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20258.3-20270.6" + attribute \src "libresoc.v:20389.3-20401.6" wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -28915,7 +29145,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -28923,7 +29153,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -28938,7 +29168,7 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -29014,42 +29244,42 @@ module \SPR_dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 6 \SPR_dec31_dec_sub19_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:20078.7-20078.15" + attribute \src "libresoc.v:20209.7-20209.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:20078.7-20078.20" - process $proc$libresoc.v:20078$434 + attribute \src "libresoc.v:20209.7-20209.20" + process $proc$libresoc.v:20209$439 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20206.3-20218.6" - process $proc$libresoc.v:20206$428 + attribute \src "libresoc.v:20337.3-20349.6" + process $proc$libresoc.v:20337$433 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20207.5-20207.29" + attribute \src "libresoc.v:20338.5-20338.29" switch \initial - attribute \src "libresoc.v:20207.9-20207.17" + attribute \src "libresoc.v:20338.9-20338.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29065,18 +29295,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] end - attribute \src "libresoc.v:20219.3-20231.6" - process $proc$libresoc.v:20219$429 + attribute \src "libresoc.v:20350.3-20362.6" + process $proc$libresoc.v:20350$434 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20220.5-20220.29" + attribute \src "libresoc.v:20351.5-20351.29" switch \initial - attribute \src "libresoc.v:20220.9-20220.17" + attribute \src "libresoc.v:20351.9-20351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29092,18 +29322,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:20232.3-20244.6" - process $proc$libresoc.v:20232$430 + attribute \src "libresoc.v:20363.3-20375.6" + process $proc$libresoc.v:20363$435 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20233.5-20233.29" + attribute \src "libresoc.v:20364.5-20364.29" switch \initial - attribute \src "libresoc.v:20233.9-20233.17" + attribute \src "libresoc.v:20364.9-20364.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29119,18 +29349,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:20245.3-20257.6" - process $proc$libresoc.v:20245$431 + attribute \src "libresoc.v:20376.3-20388.6" + process $proc$libresoc.v:20376$436 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20246.5-20246.29" + attribute \src "libresoc.v:20377.5-20377.29" switch \initial - attribute \src "libresoc.v:20246.9-20246.17" + attribute \src "libresoc.v:20377.9-20377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29146,18 +29376,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:20258.3-20270.6" - process $proc$libresoc.v:20258$432 + attribute \src "libresoc.v:20389.3-20401.6" + process $proc$libresoc.v:20389$437 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20259.5-20259.29" + attribute \src "libresoc.v:20390.5-20390.29" switch \initial - attribute \src "libresoc.v:20259.9-20259.17" + attribute \src "libresoc.v:20390.9-20390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29173,18 +29403,18 @@ module \SPR_dec31_dec_sub19 sync always update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:20271.3-20283.6" - process $proc$libresoc.v:20271$433 + attribute \src "libresoc.v:20402.3-20414.6" + process $proc$libresoc.v:20402$438 assign { } { } assign { } { } assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20272.5-20272.29" + attribute \src "libresoc.v:20403.5-20403.29" switch \initial - attribute \src "libresoc.v:20272.9-20272.17" + attribute \src "libresoc.v:20403.9-20403.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -29202,163 +29432,163 @@ module \SPR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:20289.1-20561.10" +attribute \src "libresoc.v:20420.1-20692.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.jtag._fsm" +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $0\fsm_state$next[3:0]$459 - attribute \src "libresoc.v:20375.3-20376.35" + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $0\fsm_state$next[3:0]$464 + attribute \src "libresoc.v:20506.3-20507.35" wire width 4 $0\fsm_state[3:0] - attribute \src "libresoc.v:20290.7-20290.20" + attribute \src "libresoc.v:20421.7-20421.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20381.3-20408.6" - wire $0\isdr$next[0:0]$455 - attribute \src "libresoc.v:20377.3-20378.25" + attribute \src "libresoc.v:20512.3-20539.6" + wire $0\isdr$next[0:0]$460 + attribute \src "libresoc.v:20508.3-20509.25" wire $0\isdr[0:0] - attribute \src "libresoc.v:20524.3-20551.6" - wire $0\isir$next[0:0]$472 - attribute \src "libresoc.v:20379.3-20380.25" + attribute \src "libresoc.v:20655.3-20682.6" + wire $0\isir$next[0:0]$477 + attribute \src "libresoc.v:20510.3-20511.25" wire $0\isir[0:0] - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $10\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $11\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $1\fsm_state$next[3:0]$460 - attribute \src "libresoc.v:20330.13-20330.29" + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $10\fsm_state$next[3:0]$474 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $11\fsm_state$next[3:0]$475 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20461.13-20461.29" wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20381.3-20408.6" - wire $1\isdr$next[0:0]$456 - attribute \src "libresoc.v:20335.7-20335.18" + attribute \src "libresoc.v:20512.3-20539.6" + wire $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20466.7-20466.18" wire $1\isdr[0:0] - attribute \src "libresoc.v:20524.3-20551.6" - wire $1\isir$next[0:0]$473 - attribute \src "libresoc.v:20340.7-20340.18" + attribute \src "libresoc.v:20655.3-20682.6" + wire $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20471.7-20471.18" wire $1\isir[0:0] - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $2\fsm_state$next[3:0]$461 - attribute \src "libresoc.v:20381.3-20408.6" - wire $2\isdr$next[0:0]$457 - attribute \src "libresoc.v:20524.3-20551.6" - wire $2\isir$next[0:0]$474 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $3\fsm_state$next[3:0]$462 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $4\fsm_state$next[3:0]$463 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $5\fsm_state$next[3:0]$464 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $6\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $7\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $8\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20409.3-20523.6" - wire width 4 $9\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20359.17-20359.110" - wire $eq$libresoc.v:20359$435_Y - attribute \src "libresoc.v:20360.18-20360.111" - wire $eq$libresoc.v:20360$436_Y - attribute \src "libresoc.v:20361.18-20361.111" - wire $eq$libresoc.v:20361$437_Y - attribute \src "libresoc.v:20362.18-20362.111" - wire $eq$libresoc.v:20362$438_Y - attribute \src "libresoc.v:20363.18-20363.111" - wire $eq$libresoc.v:20363$439_Y - attribute \src "libresoc.v:20364.17-20364.108" - wire $eq$libresoc.v:20364$440_Y - attribute \src "libresoc.v:20365.18-20365.111" - wire $eq$libresoc.v:20365$441_Y - attribute \src "libresoc.v:20366.18-20366.111" - wire $eq$libresoc.v:20366$442_Y - attribute \src "libresoc.v:20367.18-20367.111" - wire $eq$libresoc.v:20367$443_Y - attribute \src "libresoc.v:20368.18-20368.111" - wire $eq$libresoc.v:20368$444_Y - attribute \src "libresoc.v:20369.18-20369.111" - wire $eq$libresoc.v:20369$445_Y - attribute \src "libresoc.v:20370.18-20370.111" - wire $eq$libresoc.v:20370$446_Y - attribute \src "libresoc.v:20371.18-20371.112" - wire $eq$libresoc.v:20371$447_Y - attribute \src "libresoc.v:20372.17-20372.108" - wire $eq$libresoc.v:20372$448_Y - attribute \src "libresoc.v:20373.17-20373.108" - wire $eq$libresoc.v:20373$449_Y - attribute \src "libresoc.v:20374.17-20374.108" - wire $eq$libresoc.v:20374$450_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $2\fsm_state$next[3:0]$466 + attribute \src "libresoc.v:20512.3-20539.6" + wire $2\isdr$next[0:0]$462 + attribute \src "libresoc.v:20655.3-20682.6" + wire $2\isir$next[0:0]$479 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $3\fsm_state$next[3:0]$467 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $4\fsm_state$next[3:0]$468 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $5\fsm_state$next[3:0]$469 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $6\fsm_state$next[3:0]$470 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $7\fsm_state$next[3:0]$471 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $8\fsm_state$next[3:0]$472 + attribute \src "libresoc.v:20540.3-20654.6" + wire width 4 $9\fsm_state$next[3:0]$473 + attribute \src "libresoc.v:20490.17-20490.110" + wire $eq$libresoc.v:20490$440_Y + attribute \src "libresoc.v:20491.18-20491.111" + wire $eq$libresoc.v:20491$441_Y + attribute \src "libresoc.v:20492.18-20492.111" + wire $eq$libresoc.v:20492$442_Y + attribute \src "libresoc.v:20493.18-20493.111" + wire $eq$libresoc.v:20493$443_Y + attribute \src "libresoc.v:20494.18-20494.111" + wire $eq$libresoc.v:20494$444_Y + attribute \src "libresoc.v:20495.17-20495.108" + wire $eq$libresoc.v:20495$445_Y + attribute \src "libresoc.v:20496.18-20496.111" + wire $eq$libresoc.v:20496$446_Y + attribute \src "libresoc.v:20497.18-20497.111" + wire $eq$libresoc.v:20497$447_Y + attribute \src "libresoc.v:20498.18-20498.111" + wire $eq$libresoc.v:20498$448_Y + attribute \src "libresoc.v:20499.18-20499.111" + wire $eq$libresoc.v:20499$449_Y + attribute \src "libresoc.v:20500.18-20500.111" + wire $eq$libresoc.v:20500$450_Y + attribute \src "libresoc.v:20501.18-20501.111" + wire $eq$libresoc.v:20501$451_Y + attribute \src "libresoc.v:20502.18-20502.112" + wire $eq$libresoc.v:20502$452_Y + attribute \src "libresoc.v:20503.17-20503.108" + wire $eq$libresoc.v:20503$453_Y + attribute \src "libresoc.v:20504.17-20504.108" + wire $eq$libresoc.v:20504$454_Y + attribute \src "libresoc.v:20505.17-20505.108" + wire $eq$libresoc.v:20505$455_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire output 11 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" wire width 4 \fsm_state$next - attribute \src "libresoc.v:20290.7-20290.15" + attribute \src "libresoc.v:20421.7-20421.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire output 1 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \isdr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire output 4 \isir + wire output 11 \isdr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire \isir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:50" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" wire \local_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire output 8 \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire output 6 \negjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire output 7 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire output 5 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:37" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" wire \rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire output 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire output 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - cell $eq $eq$libresoc.v:20359$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20490$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29366,10 +29596,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20359$435_Y + connect \Y $eq$libresoc.v:20490$440_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - cell $eq $eq$libresoc.v:20360$436 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20491$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29377,10 +29607,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20360$436_Y + connect \Y $eq$libresoc.v:20491$441_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" - cell $eq $eq$libresoc.v:20361$437 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:20492$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29388,10 +29618,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20361$437_Y + connect \Y $eq$libresoc.v:20492$442_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" - cell $eq $eq$libresoc.v:20362$438 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:20493$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29399,10 +29629,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20362$438_Y + connect \Y $eq$libresoc.v:20493$443_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" - cell $eq $eq$libresoc.v:20363$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20494$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29410,10 +29640,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20363$439_Y + connect \Y $eq$libresoc.v:20494$444_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:20364$440 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:20495$445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29421,10 +29651,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:20364$440_Y + connect \Y $eq$libresoc.v:20495$445_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" - cell $eq $eq$libresoc.v:20365$441 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20496$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29432,10 +29662,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20365$441_Y + connect \Y $eq$libresoc.v:20496$446_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" - cell $eq $eq$libresoc.v:20366$442 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:20497$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29443,10 +29673,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20366$442_Y + connect \Y $eq$libresoc.v:20497$447_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" - cell $eq $eq$libresoc.v:20367$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:20498$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29454,10 +29684,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20367$443_Y + connect \Y $eq$libresoc.v:20498$448_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" - cell $eq $eq$libresoc.v:20368$444 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:20499$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29465,10 +29695,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20368$444_Y + connect \Y $eq$libresoc.v:20499$449_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" - cell $eq $eq$libresoc.v:20369$445 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:20500$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29476,10 +29706,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'1 - connect \Y $eq$libresoc.v:20369$445_Y + connect \Y $eq$libresoc.v:20500$450_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" - cell $eq $eq$libresoc.v:20370$446 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:20501$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29487,10 +29717,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20370$446_Y + connect \Y $eq$libresoc.v:20501$451_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" - cell $eq $eq$libresoc.v:20371$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:20502$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -29498,10 +29728,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \TAP_bus__tms connect \B 1'0 - connect \Y $eq$libresoc.v:20371$447_Y + connect \Y $eq$libresoc.v:20502$452_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:20372$448 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:20503$453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29509,10 +29739,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'11 - connect \Y $eq$libresoc.v:20372$448_Y + connect \Y $eq$libresoc.v:20503$453_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:20373$449 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:20504$454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29520,10 +29750,10 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 3'101 - connect \Y $eq$libresoc.v:20373$449_Y + connect \Y $eq$libresoc.v:20504$454_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:117" - cell $eq $eq$libresoc.v:20374$450 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:20505$455 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -29531,326 +29761,326 @@ module \_fsm parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 4'1000 - connect \Y $eq$libresoc.v:20374$450_Y + connect \Y $eq$libresoc.v:20505$455_Y end - attribute \src "libresoc.v:20290.7-20290.20" - process $proc$libresoc.v:20290$475 + attribute \src "libresoc.v:20421.7-20421.20" + process $proc$libresoc.v:20421$480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20330.13-20330.29" - process $proc$libresoc.v:20330$476 + attribute \src "libresoc.v:20461.13-20461.29" + process $proc$libresoc.v:20461$481 assign { } { } assign $1\fsm_state[3:0] 4'0000 sync always sync init update \fsm_state $1\fsm_state[3:0] end - attribute \src "libresoc.v:20335.7-20335.18" - process $proc$libresoc.v:20335$477 + attribute \src "libresoc.v:20466.7-20466.18" + process $proc$libresoc.v:20466$482 assign { } { } assign $1\isdr[0:0] 1'0 sync always sync init update \isdr $1\isdr[0:0] end - attribute \src "libresoc.v:20340.7-20340.18" - process $proc$libresoc.v:20340$478 + attribute \src "libresoc.v:20471.7-20471.18" + process $proc$libresoc.v:20471$483 assign { } { } assign $1\isir[0:0] 1'0 sync always sync init update \isir $1\isir[0:0] end - attribute \src "libresoc.v:20375.3-20376.35" - process $proc$libresoc.v:20375$451 + attribute \src "libresoc.v:20506.3-20507.35" + process $proc$libresoc.v:20506$456 assign { } { } assign $0\fsm_state[3:0] \fsm_state$next sync posedge \local_clk update \fsm_state $0\fsm_state[3:0] end - attribute \src "libresoc.v:20377.3-20378.25" - process $proc$libresoc.v:20377$452 + attribute \src "libresoc.v:20508.3-20509.25" + process $proc$libresoc.v:20508$457 assign { } { } assign $0\isdr[0:0] \isdr$next sync posedge \local_clk update \isdr $0\isdr[0:0] end - attribute \src "libresoc.v:20379.3-20380.25" - process $proc$libresoc.v:20379$453 + attribute \src "libresoc.v:20510.3-20511.25" + process $proc$libresoc.v:20510$458 assign { } { } assign $0\isir[0:0] \isir$next sync posedge \local_clk update \isir $0\isir[0:0] end - attribute \src "libresoc.v:20381.3-20408.6" - process $proc$libresoc.v:20381$454 + attribute \src "libresoc.v:20512.3-20539.6" + process $proc$libresoc.v:20512$459 assign { } { } assign { } { } - assign $0\isdr$next[0:0]$455 $1\isdr$next[0:0]$456 - attribute \src "libresoc.v:20382.5-20382.29" + assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20513.5-20513.29" switch \initial - attribute \src "libresoc.v:20382.9-20382.17" + attribute \src "libresoc.v:20513.9-20513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\isdr$next[0:0]$456 1'0 + assign $1\isdr$next[0:0]$461 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\isdr$next[0:0]$456 1'0 + assign $1\isdr$next[0:0]$461 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\isdr$next[0:0]$456 $2\isdr$next[0:0]$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\isdr$next[0:0]$457 1'1 + assign $2\isdr$next[0:0]$462 1'1 case - assign $2\isdr$next[0:0]$457 \isdr + assign $2\isdr$next[0:0]$462 \isdr end attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\isdr$next[0:0]$456 1'0 + assign $1\isdr$next[0:0]$461 1'0 case - assign $1\isdr$next[0:0]$456 \isdr + assign $1\isdr$next[0:0]$461 \isdr end sync always - update \isdr$next $0\isdr$next[0:0]$455 + update \isdr$next $0\isdr$next[0:0]$460 end - attribute \src "libresoc.v:20409.3-20523.6" - process $proc$libresoc.v:20409$458 + attribute \src "libresoc.v:20540.3-20654.6" + process $proc$libresoc.v:20540$463 assign { } { } assign { } { } - assign $0\fsm_state$next[3:0]$459 $1\fsm_state$next[3:0]$460 - attribute \src "libresoc.v:20410.5-20410.29" + assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20541.5-20541.29" switch \initial - attribute \src "libresoc.v:20410.9-20410.17" + attribute \src "libresoc.v:20541.9-20541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\fsm_state$next[3:0]$460 $2\fsm_state$next[3:0]$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:60" + assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[3:0]$461 4'0001 + assign $2\fsm_state$next[3:0]$466 4'0001 case - assign $2\fsm_state$next[3:0]$461 \fsm_state + assign $2\fsm_state$next[3:0]$466 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\fsm_state$next[3:0]$460 $3\fsm_state$next[3:0]$462 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:68" + assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[3:0]$462 4'0010 + assign $3\fsm_state$next[3:0]$467 4'0010 case - assign $3\fsm_state$next[3:0]$462 \fsm_state + assign $3\fsm_state$next[3:0]$467 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $1\fsm_state$next[3:0]$460 $4\fsm_state$next[3:0]$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:71" + assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[3:0]$463 4'0011 + assign $4\fsm_state$next[3:0]$468 4'0011 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fsm_state$next[3:0]$463 4'0100 + assign $4\fsm_state$next[3:0]$468 4'0100 end attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\fsm_state$next[3:0]$460 $5\fsm_state$next[3:0]$464 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[3:0]$464 4'0011 + assign $5\fsm_state$next[3:0]$469 4'0011 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\fsm_state$next[3:0]$464 4'0000 + assign $5\fsm_state$next[3:0]$469 4'0000 end attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } - assign $1\fsm_state$next[3:0]$460 $6\fsm_state$next[3:0]$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:83" + assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fsm_state$next[3:0]$465 4'0101 + assign $6\fsm_state$next[3:0]$470 4'0101 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $6\fsm_state$next[3:0]$465 4'0110 + assign $6\fsm_state$next[3:0]$470 4'0110 end attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } - assign $1\fsm_state$next[3:0]$460 $7\fsm_state$next[3:0]$466 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:88" + assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\fsm_state$next[3:0]$466 4'0110 + assign $7\fsm_state$next[3:0]$471 4'0110 case - assign $7\fsm_state$next[3:0]$466 \fsm_state + assign $7\fsm_state$next[3:0]$471 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } - assign $1\fsm_state$next[3:0]$460 $8\fsm_state$next[3:0]$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:91" + assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\fsm_state$next[3:0]$467 4'0111 + assign $8\fsm_state$next[3:0]$472 4'0111 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $8\fsm_state$next[3:0]$467 4'1000 + assign $8\fsm_state$next[3:0]$472 4'1000 end attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } - assign $1\fsm_state$next[3:0]$460 $9\fsm_state$next[3:0]$468 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:96" + assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\fsm_state$next[3:0]$468 4'1001 + assign $9\fsm_state$next[3:0]$473 4'1001 case - assign $9\fsm_state$next[3:0]$468 \fsm_state + assign $9\fsm_state$next[3:0]$473 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } - assign $1\fsm_state$next[3:0]$460 $10\fsm_state$next[3:0]$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:99" + assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fsm_state$next[3:0]$469 4'0101 + assign $10\fsm_state$next[3:0]$474 4'0101 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $10\fsm_state$next[3:0]$469 4'1000 + assign $10\fsm_state$next[3:0]$474 4'1000 end attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\fsm_state$next[3:0]$460 $11\fsm_state$next[3:0]$470 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:108" + assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $11\fsm_state$next[3:0]$470 4'0001 + assign $11\fsm_state$next[3:0]$475 4'0001 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $11\fsm_state$next[3:0]$470 4'0010 + assign $11\fsm_state$next[3:0]$475 4'0010 end case - assign $1\fsm_state$next[3:0]$460 \fsm_state + assign $1\fsm_state$next[3:0]$465 \fsm_state end sync always - update \fsm_state$next $0\fsm_state$next[3:0]$459 + update \fsm_state$next $0\fsm_state$next[3:0]$464 end - attribute \src "libresoc.v:20524.3-20551.6" - process $proc$libresoc.v:20524$471 + attribute \src "libresoc.v:20655.3-20682.6" + process $proc$libresoc.v:20655$476 assign { } { } assign { } { } - assign $0\isir$next[0:0]$472 $1\isir$next[0:0]$473 - attribute \src "libresoc.v:20525.5-20525.29" + assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20656.5-20656.29" switch \initial - attribute \src "libresoc.v:20525.9-20525.17" + attribute \src "libresoc.v:20656.9-20656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:53" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $1\isir$next[0:0]$473 1'0 + assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $1\isir$next[0:0]$473 1'0 + assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $1\isir$next[0:0]$473 $2\isir$next[0:0]$474 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:77" + assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\isir$next[0:0]$474 1'1 + assign $2\isir$next[0:0]$479 1'1 case - assign $2\isir$next[0:0]$474 \isir + assign $2\isir$next[0:0]$479 \isir end attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } - assign $1\isir$next[0:0]$473 1'0 - case - assign $1\isir$next[0:0]$473 \isir - end - sync always - update \isir$next $0\isir$next[0:0]$472 - end - connect \$9 $eq$libresoc.v:20359$435_Y - connect \$11 $eq$libresoc.v:20360$436_Y - connect \$13 $eq$libresoc.v:20361$437_Y - connect \$15 $eq$libresoc.v:20362$438_Y - connect \$17 $eq$libresoc.v:20363$439_Y - connect \$1 $eq$libresoc.v:20364$440_Y - connect \$19 $eq$libresoc.v:20365$441_Y - connect \$21 $eq$libresoc.v:20366$442_Y - connect \$23 $eq$libresoc.v:20367$443_Y - connect \$25 $eq$libresoc.v:20368$444_Y - connect \$27 $eq$libresoc.v:20369$445_Y - connect \$29 $eq$libresoc.v:20370$446_Y - connect \$31 $eq$libresoc.v:20371$447_Y - connect \$3 $eq$libresoc.v:20372$448_Y - connect \$5 $eq$libresoc.v:20373$449_Y - connect \$7 $eq$libresoc.v:20374$450_Y + assign $1\isir$next[0:0]$478 1'0 + case + assign $1\isir$next[0:0]$478 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$477 + end + connect \$9 $eq$libresoc.v:20490$440_Y + connect \$11 $eq$libresoc.v:20491$441_Y + connect \$13 $eq$libresoc.v:20492$442_Y + connect \$15 $eq$libresoc.v:20493$443_Y + connect \$17 $eq$libresoc.v:20494$444_Y + connect \$1 $eq$libresoc.v:20495$445_Y + connect \$19 $eq$libresoc.v:20496$446_Y + connect \$21 $eq$libresoc.v:20497$447_Y + connect \$23 $eq$libresoc.v:20498$448_Y + connect \$25 $eq$libresoc.v:20499$449_Y + connect \$27 $eq$libresoc.v:20500$450_Y + connect \$29 $eq$libresoc.v:20501$451_Y + connect \$31 $eq$libresoc.v:20502$452_Y + connect \$3 $eq$libresoc.v:20503$453_Y + connect \$5 $eq$libresoc.v:20504$454_Y + connect \$7 $eq$libresoc.v:20505$455_Y connect \update \$7 connect \shift \$5 connect \capture \$3 @@ -29861,458 +30091,250 @@ module \_fsm connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end -attribute \src "libresoc.v:20565.1-20676.10" +attribute \src "libresoc.v:20696.1-20768.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.jtag._idblock" +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock - attribute \src "libresoc.v:20649.3-20669.6" - wire width 32 $0\TAP_id_sr$next[31:0]$497 - attribute \src "libresoc.v:20647.3-20648.35" + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $0\TAP_id_sr$next[31:0]$489 + attribute \src "libresoc.v:20739.3-20740.35" wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20566.7-20566.20" + attribute \src "libresoc.v:20697.7-20697.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20649.3-20669.6" - wire width 32 $1\TAP_id_sr$next[31:0]$498 - attribute \src "libresoc.v:20602.14-20602.31" + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20707.14-20707.31" wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:20649.3-20669.6" - wire width 32 $2\TAP_id_sr$next[31:0]$499 - attribute \src "libresoc.v:20631.17-20631.105" - wire $and$libresoc.v:20631$479_Y - attribute \src "libresoc.v:20635.18-20635.103" - wire $and$libresoc.v:20635$483_Y - attribute \src "libresoc.v:20637.18-20637.105" - wire $and$libresoc.v:20637$485_Y - attribute \src "libresoc.v:20641.18-20641.103" - wire $and$libresoc.v:20641$489_Y - attribute \src "libresoc.v:20642.18-20642.106" - wire $and$libresoc.v:20642$490_Y - attribute \src "libresoc.v:20646.17-20646.101" - wire $and$libresoc.v:20646$494_Y - attribute \src "libresoc.v:20632.18-20632.102" - wire $eq$libresoc.v:20632$480_Y - attribute \src "libresoc.v:20633.18-20633.102" - wire $eq$libresoc.v:20633$481_Y - attribute \src "libresoc.v:20636.17-20636.101" - wire $eq$libresoc.v:20636$484_Y - attribute \src "libresoc.v:20638.18-20638.102" - wire $eq$libresoc.v:20638$486_Y - attribute \src "libresoc.v:20639.18-20639.102" - wire $eq$libresoc.v:20639$487_Y - attribute \src "libresoc.v:20643.18-20643.102" - wire $eq$libresoc.v:20643$491_Y - attribute \src "libresoc.v:20644.17-20644.101" - wire $eq$libresoc.v:20644$492_Y - attribute \src "libresoc.v:20634.18-20634.104" - wire $or$libresoc.v:20634$482_Y - attribute \src "libresoc.v:20640.18-20640.104" - wire $or$libresoc.v:20640$488_Y - attribute \src "libresoc.v:20645.17-20645.101" - wire $or$libresoc.v:20645$493_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "libresoc.v:20741.3-20761.6" + wire width 32 $2\TAP_id_sr$next[31:0]$491 + attribute \src "libresoc.v:20736.17-20736.110" + wire $and$libresoc.v:20736$484_Y + attribute \src "libresoc.v:20737.17-20737.108" + wire $and$libresoc.v:20737$485_Y + attribute \src "libresoc.v:20738.17-20738.109" + wire $and$libresoc.v:20738$486_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 5 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" wire width 32 \TAP_id_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:226" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" wire width 32 \TAP_id_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" wire output 6 \TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:233" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" wire \_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:230" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" wire \_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:231" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" wire \_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:229" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" wire \_tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:232" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" wire \_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 1 \capture - attribute \src "libresoc.v:20566.7-20566.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire width 4 input 9 \ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 2 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:20697.7-20697.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire input 3 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20631$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:20736$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$7 + connect \A \select_id connect \B \capture - connect \Y $and$libresoc.v:20631$479_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:20635$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$15 - connect \Y $and$libresoc.v:20635$483_Y + connect \Y $and$libresoc.v:20736$484_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20637$485 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:20737$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$17 + connect \A \select_id connect \B \shift - connect \Y $and$libresoc.v:20637$485_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:20641$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$25 - connect \Y $and$libresoc.v:20641$489_Y + connect \Y $and$libresoc.v:20737$485_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20642$490 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:20738$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$27 + connect \A \select_id connect \B \update - connect \Y $and$libresoc.v:20642$490_Y + connect \Y $and$libresoc.v:20738$486_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:20646$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isdr - connect \B \$5 - connect \Y $and$libresoc.v:20646$494_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20632$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:20632$480_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20633$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:20633$481_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20636$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:20636$484_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20638$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 1'1 - connect \Y $eq$libresoc.v:20638$486_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20639$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:20639$487_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:369" - cell $eq $eq$libresoc.v:20643$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:20643$491_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:20644$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:20644$492_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:20634$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \B \$13 - connect \Y $or$libresoc.v:20634$482_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:20640$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$21 - connect \B \$23 - connect \Y $or$libresoc.v:20640$488_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:20645$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:20645$493_Y - end - attribute \src "libresoc.v:20566.7-20566.20" - process $proc$libresoc.v:20566$500 + attribute \src "libresoc.v:20697.7-20697.20" + process $proc$libresoc.v:20697$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20602.14-20602.31" - process $proc$libresoc.v:20602$501 + attribute \src "libresoc.v:20707.14-20707.31" + process $proc$libresoc.v:20707$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20647.3-20648.35" - process $proc$libresoc.v:20647$495 + attribute \src "libresoc.v:20739.3-20740.35" + process $proc$libresoc.v:20739$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:20649.3-20669.6" - process $proc$libresoc.v:20649$496 + attribute \src "libresoc.v:20741.3-20761.6" + process $proc$libresoc.v:20741$488 assign { } { } assign { } { } - assign $0\TAP_id_sr$next[31:0]$497 $1\TAP_id_sr$next[31:0]$498 - attribute \src "libresoc.v:20650.5-20650.29" + assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20742.5-20742.29" switch \initial - attribute \src "libresoc.v:20650.9-20650.17" + attribute \src "libresoc.v:20742.9-20742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:244" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" switch { \_shift \_capture } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\TAP_id_sr$next[31:0]$498 6399 + assign $1\TAP_id_sr$next[31:0]$490 6399 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\TAP_id_sr$next[31:0]$498 $2\TAP_id_sr$next[31:0]$499 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:247" + assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" switch \_bypass attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\TAP_id_sr$next[31:0]$499 [31:1] \TAP_id_sr [31:1] - assign $2\TAP_id_sr$next[31:0]$499 [0] \_tdi + assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\TAP_id_sr$next[31:0]$499 { \_tdi \TAP_id_sr [31:1] } + assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } end case - assign $1\TAP_id_sr$next[31:0]$498 \TAP_id_sr + assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr end sync always - update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$497 + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end - connect \$9 $and$libresoc.v:20631$479_Y - connect \$11 $eq$libresoc.v:20632$480_Y - connect \$13 $eq$libresoc.v:20633$481_Y - connect \$15 $or$libresoc.v:20634$482_Y - connect \$17 $and$libresoc.v:20635$483_Y - connect \$1 $eq$libresoc.v:20636$484_Y - connect \$19 $and$libresoc.v:20637$485_Y - connect \$21 $eq$libresoc.v:20638$486_Y - connect \$23 $eq$libresoc.v:20639$487_Y - connect \$25 $or$libresoc.v:20640$488_Y - connect \$27 $and$libresoc.v:20641$489_Y - connect \$29 $and$libresoc.v:20642$490_Y - connect \$31 $eq$libresoc.v:20643$491_Y - connect \$3 $eq$libresoc.v:20644$492_Y - connect \$5 $or$libresoc.v:20645$493_Y - connect \$7 $and$libresoc.v:20646$494_Y + connect \$1 $and$libresoc.v:20736$484_Y + connect \$3 $and$libresoc.v:20737$485_Y + connect \$5 $and$libresoc.v:20738$486_Y connect \TAP_id_tdo \TAP_id_sr [0] - connect \_bypass \$31 - connect \_update \$29 - connect \_shift \$19 - connect \_capture \$9 + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 connect \_tdi \TAP_bus__tdi end -attribute \src "libresoc.v:20680.1-20764.10" +attribute \src "libresoc.v:20772.1-20856.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.jtag._irblock" +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock - attribute \src "libresoc.v:20681.7-20681.20" + attribute \src "libresoc.v:20773.7-20773.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20742.3-20762.6" - wire width 4 $0\ir$next[3:0]$514 - attribute \src "libresoc.v:20725.3-20726.21" + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $0\ir$next[3:0]$506 + attribute \src "libresoc.v:20817.3-20818.21" wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:20729.3-20741.6" - wire width 4 $0\shift_ir$next[3:0]$511 - attribute \src "libresoc.v:20727.3-20728.33" + attribute \src "libresoc.v:20821.3-20833.6" + wire width 4 $0\shift_ir$next[3:0]$503 + attribute \src "libresoc.v:20819.3-20820.33" wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:20742.3-20762.6" - wire width 4 $1\ir$next[3:0]$515 - attribute \src "libresoc.v:20700.13-20700.22" + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $1\ir$next[3:0]$507 + attribute \src "libresoc.v:20792.13-20792.22" wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:20729.3-20741.6" - wire width 4 $1\shift_ir$next[3:0]$512 - attribute \src "libresoc.v:20712.13-20712.28" + attribute \src "libresoc.v:20821.3-20833.6" + wire width 4 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:20804.13-20804.28" wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:20742.3-20762.6" - wire width 4 $2\ir$next[3:0]$516 - attribute \src "libresoc.v:20719.17-20719.103" - wire $and$libresoc.v:20719$502_Y - attribute \src "libresoc.v:20720.18-20720.105" - wire $and$libresoc.v:20720$503_Y - attribute \src "libresoc.v:20721.17-20721.105" - wire $and$libresoc.v:20721$504_Y - attribute \src "libresoc.v:20722.17-20722.103" - wire $and$libresoc.v:20722$505_Y - attribute \src "libresoc.v:20723.17-20723.104" - wire $and$libresoc.v:20723$506_Y - attribute \src "libresoc.v:20724.17-20724.105" - wire $and$libresoc.v:20724$507_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + attribute \src "libresoc.v:20834.3-20854.6" + wire width 4 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:20811.17-20811.103" + wire $and$libresoc.v:20811$494_Y + attribute \src "libresoc.v:20812.18-20812.105" + wire $and$libresoc.v:20812$495_Y + attribute \src "libresoc.v:20813.17-20813.105" + wire $and$libresoc.v:20813$496_Y + attribute \src "libresoc.v:20814.17-20814.103" + wire $and$libresoc.v:20814$497_Y + attribute \src "libresoc.v:20815.17-20815.104" + wire $and$libresoc.v:20815$498_Y + attribute \src "libresoc.v:20816.17-20816.105" + wire $and$libresoc.v:20816$499_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 4 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture - attribute \src "libresoc.v:20681.7-20681.15" + attribute \src "libresoc.v:20773.7-20773.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 \ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire input 5 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire input 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" wire width 4 \shift_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:139" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" wire width 4 \shift_ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire output 6 \tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - cell $and $and$libresoc.v:20719$502 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20811$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30320,10 +30342,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20719$502_Y + connect \Y $and$libresoc.v:20811$494_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - cell $and $and$libresoc.v:20720$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20812$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30331,10 +30353,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20720$503_Y + connect \Y $and$libresoc.v:20812$495_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - cell $and $and$libresoc.v:20721$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20813$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30342,10 +30364,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20721$504_Y + connect \Y $and$libresoc.v:20813$496_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:356" - cell $and $and$libresoc.v:20722$505 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20814$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30353,10 +30375,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:20722$505_Y + connect \Y $and$libresoc.v:20814$497_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:357" - cell $and $and$libresoc.v:20723$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20815$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30364,10 +30386,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:20723$506_Y + connect \Y $and$libresoc.v:20815$498_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:355" - cell $and $and$libresoc.v:20724$507 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20816$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30375,151 +30397,151 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:20724$507_Y + connect \Y $and$libresoc.v:20816$499_Y end - attribute \src "libresoc.v:20681.7-20681.20" - process $proc$libresoc.v:20681$517 + attribute \src "libresoc.v:20773.7-20773.20" + process $proc$libresoc.v:20773$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20700.13-20700.22" - process $proc$libresoc.v:20700$518 + attribute \src "libresoc.v:20792.13-20792.22" + process $proc$libresoc.v:20792$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end - attribute \src "libresoc.v:20712.13-20712.28" - process $proc$libresoc.v:20712$519 + attribute \src "libresoc.v:20804.13-20804.28" + process $proc$libresoc.v:20804$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end - attribute \src "libresoc.v:20725.3-20726.21" - process $proc$libresoc.v:20725$508 + attribute \src "libresoc.v:20817.3-20818.21" + process $proc$libresoc.v:20817$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end - attribute \src "libresoc.v:20727.3-20728.33" - process $proc$libresoc.v:20727$509 + attribute \src "libresoc.v:20819.3-20820.33" + process $proc$libresoc.v:20819$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end - attribute \src "libresoc.v:20729.3-20741.6" - process $proc$libresoc.v:20729$510 + attribute \src "libresoc.v:20821.3-20833.6" + process $proc$libresoc.v:20821$502 assign { } { } assign { } { } - assign $0\shift_ir$next[3:0]$511 $1\shift_ir$next[3:0]$512 - attribute \src "libresoc.v:20730.5-20730.29" + assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:20822.5-20822.29" switch \initial - attribute \src "libresoc.v:20730.9-20730.17" + attribute \src "libresoc.v:20822.9-20822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" switch { \$5 \$3 \$1 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\shift_ir$next[3:0]$512 \ir + assign $1\shift_ir$next[3:0]$504 \ir attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\shift_ir$next[3:0]$512 { \TAP_bus__tdi \shift_ir [3:1] } + assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } case - assign $1\shift_ir$next[3:0]$512 \shift_ir + assign $1\shift_ir$next[3:0]$504 \shift_ir end sync always - update \shift_ir$next $0\shift_ir$next[3:0]$511 + update \shift_ir$next $0\shift_ir$next[3:0]$503 end - attribute \src "libresoc.v:20742.3-20762.6" - process $proc$libresoc.v:20742$513 + attribute \src "libresoc.v:20834.3-20854.6" + process $proc$libresoc.v:20834$505 assign { } { } assign { } { } assign { } { } - assign $0\ir$next[3:0]$514 $2\ir$next[3:0]$516 - attribute \src "libresoc.v:20743.5-20743.29" + assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:20835.5-20835.29" switch \initial - attribute \src "libresoc.v:20743.9-20743.17" + attribute \src "libresoc.v:20835.9-20835.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:142" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" switch { \$11 \$9 \$7 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\ir$next[3:0]$515 \ir + assign $1\ir$next[3:0]$507 \ir attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\ir$next[3:0]$515 \ir + assign $1\ir$next[3:0]$507 \ir attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\ir$next[3:0]$515 \shift_ir + assign $1\ir$next[3:0]$507 \shift_ir case - assign $1\ir$next[3:0]$515 \ir + assign $1\ir$next[3:0]$507 \ir end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ir$next[3:0]$516 4'0001 + assign $2\ir$next[3:0]$508 4'0001 case - assign $2\ir$next[3:0]$516 $1\ir$next[3:0]$515 + assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 end sync always - update \ir$next $0\ir$next[3:0]$514 + update \ir$next $0\ir$next[3:0]$506 end - connect \$9 $and$libresoc.v:20719$502_Y - connect \$11 $and$libresoc.v:20720$503_Y - connect \$1 $and$libresoc.v:20721$504_Y - connect \$3 $and$libresoc.v:20722$505_Y - connect \$5 $and$libresoc.v:20723$506_Y - connect \$7 $and$libresoc.v:20724$507_Y + connect \$9 $and$libresoc.v:20811$494_Y + connect \$11 $and$libresoc.v:20812$495_Y + connect \$1 $and$libresoc.v:20813$496_Y + connect \$3 $and$libresoc.v:20814$497_Y + connect \$5 $and$libresoc.v:20815$498_Y + connect \$7 $and$libresoc.v:20816$499_Y connect \tdo \ir [0] end -attribute \src "libresoc.v:20768.1-20826.10" +attribute \src "libresoc.v:20860.1-20918.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l - attribute \src "libresoc.v:20769.7-20769.20" + attribute \src "libresoc.v:20861.7-20861.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20814.3-20822.6" - wire $0\q_int$next[0:0]$530 - attribute \src "libresoc.v:20812.3-20813.27" + attribute \src "libresoc.v:20906.3-20914.6" + wire $0\q_int$next[0:0]$522 + attribute \src "libresoc.v:20904.3-20905.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:20814.3-20822.6" - wire $1\q_int$next[0:0]$531 - attribute \src "libresoc.v:20793.7-20793.19" + attribute \src "libresoc.v:20906.3-20914.6" + wire $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:20885.7-20885.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:20804.17-20804.96" - wire $and$libresoc.v:20804$520_Y - attribute \src "libresoc.v:20809.17-20809.96" - wire $and$libresoc.v:20809$525_Y - attribute \src "libresoc.v:20806.18-20806.93" - wire $not$libresoc.v:20806$522_Y - attribute \src "libresoc.v:20808.17-20808.92" - wire $not$libresoc.v:20808$524_Y - attribute \src "libresoc.v:20811.17-20811.92" - wire $not$libresoc.v:20811$527_Y - attribute \src "libresoc.v:20805.18-20805.98" - wire $or$libresoc.v:20805$521_Y - attribute \src "libresoc.v:20807.18-20807.99" - wire $or$libresoc.v:20807$523_Y - attribute \src "libresoc.v:20810.17-20810.97" - wire $or$libresoc.v:20810$526_Y + attribute \src "libresoc.v:20896.17-20896.96" + wire $and$libresoc.v:20896$512_Y + attribute \src "libresoc.v:20901.17-20901.96" + wire $and$libresoc.v:20901$517_Y + attribute \src "libresoc.v:20898.18-20898.93" + wire $not$libresoc.v:20898$514_Y + attribute \src "libresoc.v:20900.17-20900.92" + wire $not$libresoc.v:20900$516_Y + attribute \src "libresoc.v:20903.17-20903.92" + wire $not$libresoc.v:20903$519_Y + attribute \src "libresoc.v:20897.18-20897.98" + wire $or$libresoc.v:20897$513_Y + attribute \src "libresoc.v:20899.18-20899.99" + wire $or$libresoc.v:20899$515_Y + attribute \src "libresoc.v:20902.17-20902.97" + wire $or$libresoc.v:20902$518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -30536,11 +30558,11 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:20769.7-20769.15" + attribute \src "libresoc.v:20861.7-20861.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 4 \q_adr @@ -30557,7 +30579,7 @@ module \adr_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20804$520 + cell $and $and$libresoc.v:20896$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30565,10 +30587,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:20804$520_Y + connect \Y $and$libresoc.v:20896$512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20809$525 + cell $and $and$libresoc.v:20901$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30576,34 +30598,34 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:20809$525_Y + connect \Y $and$libresoc.v:20901$517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20806$522 + cell $not $not$libresoc.v:20898$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr - connect \Y $not$libresoc.v:20806$522_Y + connect \Y $not$libresoc.v:20898$514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20808$524 + cell $not $not$libresoc.v:20900$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:20808$524_Y + connect \Y $not$libresoc.v:20900$516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20811$527 + cell $not $not$libresoc.v:20903$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:20811$527_Y + connect \Y $not$libresoc.v:20903$519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20805$521 + cell $or $or$libresoc.v:20897$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30611,10 +30633,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr - connect \Y $or$libresoc.v:20805$521_Y + connect \Y $or$libresoc.v:20897$513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20807$523 + cell $or $or$libresoc.v:20899$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30622,10 +30644,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int - connect \Y $or$libresoc.v:20807$523_Y + connect \Y $or$libresoc.v:20899$515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20810$526 + cell $or $or$libresoc.v:20902$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30633,39 +30655,39 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr - connect \Y $or$libresoc.v:20810$526_Y + connect \Y $or$libresoc.v:20902$518_Y end - attribute \src "libresoc.v:20769.7-20769.20" - process $proc$libresoc.v:20769$532 + attribute \src "libresoc.v:20861.7-20861.20" + process $proc$libresoc.v:20861$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20793.7-20793.19" - process $proc$libresoc.v:20793$533 + attribute \src "libresoc.v:20885.7-20885.19" + process $proc$libresoc.v:20885$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:20812.3-20813.27" - process $proc$libresoc.v:20812$528 + attribute \src "libresoc.v:20904.3-20905.27" + process $proc$libresoc.v:20904$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:20814.3-20822.6" - process $proc$libresoc.v:20814$529 + attribute \src "libresoc.v:20906.3-20914.6" + process $proc$libresoc.v:20906$521 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$530 $1\q_int$next[0:0]$531 - attribute \src "libresoc.v:20815.5-20815.29" + assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:20907.5-20907.29" switch \initial - attribute \src "libresoc.v:20815.9-20815.17" + attribute \src "libresoc.v:20907.9-20907.17" case 1'1 case end @@ -30674,56 +30696,56 @@ module \adr_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$531 1'0 + assign $1\q_int$next[0:0]$523 1'0 case - assign $1\q_int$next[0:0]$531 \$5 + assign $1\q_int$next[0:0]$523 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$530 + update \q_int$next $0\q_int$next[0:0]$522 end - connect \$9 $and$libresoc.v:20804$520_Y - connect \$11 $or$libresoc.v:20805$521_Y - connect \$13 $not$libresoc.v:20806$522_Y - connect \$15 $or$libresoc.v:20807$523_Y - connect \$1 $not$libresoc.v:20808$524_Y - connect \$3 $and$libresoc.v:20809$525_Y - connect \$5 $or$libresoc.v:20810$526_Y - connect \$7 $not$libresoc.v:20811$527_Y + connect \$9 $and$libresoc.v:20896$512_Y + connect \$11 $or$libresoc.v:20897$513_Y + connect \$13 $not$libresoc.v:20898$514_Y + connect \$15 $or$libresoc.v:20899$515_Y + connect \$1 $not$libresoc.v:20900$516_Y + connect \$3 $and$libresoc.v:20901$517_Y + connect \$5 $or$libresoc.v:20902$518_Y + connect \$7 $not$libresoc.v:20903$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end -attribute \src "libresoc.v:20830.1-20888.10" +attribute \src "libresoc.v:20922.1-20980.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l - attribute \src "libresoc.v:20831.7-20831.20" + attribute \src "libresoc.v:20923.7-20923.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20876.3-20884.6" - wire $0\q_int$next[0:0]$544 - attribute \src "libresoc.v:20874.3-20875.27" + attribute \src "libresoc.v:20968.3-20976.6" + wire $0\q_int$next[0:0]$536 + attribute \src "libresoc.v:20966.3-20967.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:20876.3-20884.6" - wire $1\q_int$next[0:0]$545 - attribute \src "libresoc.v:20855.7-20855.19" + attribute \src "libresoc.v:20968.3-20976.6" + wire $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:20947.7-20947.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:20866.17-20866.96" - wire $and$libresoc.v:20866$534_Y - attribute \src "libresoc.v:20871.17-20871.96" - wire $and$libresoc.v:20871$539_Y - attribute \src "libresoc.v:20868.18-20868.100" - wire $not$libresoc.v:20868$536_Y - attribute \src "libresoc.v:20870.17-20870.99" - wire $not$libresoc.v:20870$538_Y - attribute \src "libresoc.v:20873.17-20873.99" - wire $not$libresoc.v:20873$541_Y - attribute \src "libresoc.v:20867.18-20867.105" - wire $or$libresoc.v:20867$535_Y - attribute \src "libresoc.v:20869.18-20869.106" - wire $or$libresoc.v:20869$537_Y - attribute \src "libresoc.v:20872.17-20872.104" - wire $or$libresoc.v:20872$540_Y + attribute \src "libresoc.v:20958.17-20958.96" + wire $and$libresoc.v:20958$526_Y + attribute \src "libresoc.v:20963.17-20963.96" + wire $and$libresoc.v:20963$531_Y + attribute \src "libresoc.v:20960.18-20960.100" + wire $not$libresoc.v:20960$528_Y + attribute \src "libresoc.v:20962.17-20962.99" + wire $not$libresoc.v:20962$530_Y + attribute \src "libresoc.v:20965.17-20965.99" + wire $not$libresoc.v:20965$533_Y + attribute \src "libresoc.v:20959.18-20959.105" + wire $or$libresoc.v:20959$527_Y + attribute \src "libresoc.v:20961.18-20961.106" + wire $or$libresoc.v:20961$529_Y + attribute \src "libresoc.v:20964.17-20964.104" + wire $or$libresoc.v:20964$532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -30740,11 +30762,11 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:20831.7-20831.15" + attribute \src "libresoc.v:20923.7-20923.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 5 \q_addr_acked @@ -30761,7 +30783,7 @@ module \adrok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20866$534 + cell $and $and$libresoc.v:20958$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30769,10 +30791,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:20866$534_Y + connect \Y $and$libresoc.v:20958$526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20871$539 + cell $and $and$libresoc.v:20963$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30780,34 +30802,34 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:20871$539_Y + connect \Y $and$libresoc.v:20963$531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20868$536 + cell $not $not$libresoc.v:20960$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked - connect \Y $not$libresoc.v:20868$536_Y + connect \Y $not$libresoc.v:20960$528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20870$538 + cell $not $not$libresoc.v:20962$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:20870$538_Y + connect \Y $not$libresoc.v:20962$530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20873$541 + cell $not $not$libresoc.v:20965$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:20873$541_Y + connect \Y $not$libresoc.v:20965$533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20867$535 + cell $or $or$libresoc.v:20959$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30815,10 +30837,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked - connect \Y $or$libresoc.v:20867$535_Y + connect \Y $or$libresoc.v:20959$527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20869$537 + cell $or $or$libresoc.v:20961$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30826,10 +30848,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int - connect \Y $or$libresoc.v:20869$537_Y + connect \Y $or$libresoc.v:20961$529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20872$540 + cell $or $or$libresoc.v:20964$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30837,39 +30859,39 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked - connect \Y $or$libresoc.v:20872$540_Y + connect \Y $or$libresoc.v:20964$532_Y end - attribute \src "libresoc.v:20831.7-20831.20" - process $proc$libresoc.v:20831$546 + attribute \src "libresoc.v:20923.7-20923.20" + process $proc$libresoc.v:20923$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:20855.7-20855.19" - process $proc$libresoc.v:20855$547 + attribute \src "libresoc.v:20947.7-20947.19" + process $proc$libresoc.v:20947$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:20874.3-20875.27" - process $proc$libresoc.v:20874$542 + attribute \src "libresoc.v:20966.3-20967.27" + process $proc$libresoc.v:20966$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:20876.3-20884.6" - process $proc$libresoc.v:20876$543 + attribute \src "libresoc.v:20968.3-20976.6" + process $proc$libresoc.v:20968$535 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$544 $1\q_int$next[0:0]$545 - attribute \src "libresoc.v:20877.5-20877.29" + assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:20969.5-20969.29" switch \initial - attribute \src "libresoc.v:20877.9-20877.17" + attribute \src "libresoc.v:20969.9-20969.17" case 1'1 case end @@ -30878,600 +30900,600 @@ module \adrok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$545 1'0 + assign $1\q_int$next[0:0]$537 1'0 case - assign $1\q_int$next[0:0]$545 \$5 + assign $1\q_int$next[0:0]$537 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$544 + update \q_int$next $0\q_int$next[0:0]$536 end - connect \$9 $and$libresoc.v:20866$534_Y - connect \$11 $or$libresoc.v:20867$535_Y - connect \$13 $not$libresoc.v:20868$536_Y - connect \$15 $or$libresoc.v:20869$537_Y - connect \$1 $not$libresoc.v:20870$538_Y - connect \$3 $and$libresoc.v:20871$539_Y - connect \$5 $or$libresoc.v:20872$540_Y - connect \$7 $not$libresoc.v:20873$541_Y + connect \$9 $and$libresoc.v:20958$526_Y + connect \$11 $or$libresoc.v:20959$527_Y + connect \$13 $not$libresoc.v:20960$528_Y + connect \$15 $or$libresoc.v:20961$529_Y + connect \$1 $not$libresoc.v:20962$530_Y + connect \$3 $and$libresoc.v:20963$531_Y + connect \$5 $or$libresoc.v:20964$532_Y + connect \$7 $not$libresoc.v:20965$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end -attribute \src "libresoc.v:20892.1-22217.10" +attribute \src "libresoc.v:20984.1-22309.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 - attribute \src "libresoc.v:21728.3-21729.25" + attribute \src "libresoc.v:21820.3-21821.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$694 - attribute \src "libresoc.v:21700.3-21701.67" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 + attribute \src "libresoc.v:21792.3-21793.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 - attribute \src "libresoc.v:21670.3-21671.65" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 + attribute \src "libresoc.v:21762.3-21763.65" wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 - attribute \src "libresoc.v:21672.3-21673.79" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + attribute \src "libresoc.v:21764.3-21765.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 - attribute \src "libresoc.v:21674.3-21675.75" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + attribute \src "libresoc.v:21766.3-21767.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$698 - attribute \src "libresoc.v:21692.3-21693.73" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + attribute \src "libresoc.v:21784.3-21785.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$699 - attribute \src "libresoc.v:21702.3-21703.59" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 + attribute \src "libresoc.v:21794.3-21795.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$700 - attribute \src "libresoc.v:21668.3-21669.69" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + attribute \src "libresoc.v:21760.3-21761.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__invert_in$next[0:0]$701 - attribute \src "libresoc.v:21684.3-21685.69" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + attribute \src "libresoc.v:21776.3-21777.69" wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__invert_out$next[0:0]$702 - attribute \src "libresoc.v:21688.3-21689.71" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + attribute \src "libresoc.v:21780.3-21781.71" wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 - attribute \src "libresoc.v:21696.3-21697.67" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + attribute \src "libresoc.v:21788.3-21789.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__is_signed$next[0:0]$704 - attribute \src "libresoc.v:21698.3-21699.69" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + attribute \src "libresoc.v:21790.3-21791.69" wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 - attribute \src "libresoc.v:21680.3-21681.63" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + attribute \src "libresoc.v:21772.3-21773.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 - attribute \src "libresoc.v:21682.3-21683.63" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + attribute \src "libresoc.v:21774.3-21775.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__output_carry$next[0:0]$707 - attribute \src "libresoc.v:21694.3-21695.75" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + attribute \src "libresoc.v:21786.3-21787.75" wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 - attribute \src "libresoc.v:21678.3-21679.63" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + attribute \src "libresoc.v:21770.3-21771.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 - attribute \src "libresoc.v:21676.3-21677.63" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + attribute \src "libresoc.v:21768.3-21769.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 - attribute \src "libresoc.v:21690.3-21691.69" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + attribute \src "libresoc.v:21782.3-21783.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $0\alu_alu0_alu_op__zero_a$next[0:0]$711 - attribute \src "libresoc.v:21686.3-21687.63" + attribute \src "libresoc.v:22010.3-22048.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + attribute \src "libresoc.v:21778.3-21779.63" wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21726.3-21727.40" + attribute \src "libresoc.v:21818.3-21819.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22116.3-22124.6" - wire $0\alu_l_r_alu$next[0:0]$792 - attribute \src "libresoc.v:21636.3-21637.39" + attribute \src "libresoc.v:22208.3-22216.6" + wire $0\alu_l_r_alu$next[0:0]$784 + attribute \src "libresoc.v:21728.3-21729.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22107.3-22115.6" - wire $0\alui_l_r_alui$next[0:0]$789 - attribute \src "libresoc.v:21638.3-21639.43" + attribute \src "libresoc.v:22199.3-22207.6" + wire $0\alui_l_r_alui$next[0:0]$781 + attribute \src "libresoc.v:21730.3-21731.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:21957.3-21978.6" - wire width 64 $0\data_r0__o$next[63:0]$737 - attribute \src "libresoc.v:21664.3-21665.37" + attribute \src "libresoc.v:22049.3-22070.6" + wire width 64 $0\data_r0__o$next[63:0]$729 + attribute \src "libresoc.v:21756.3-21757.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:21957.3-21978.6" - wire $0\data_r0__o_ok$next[0:0]$738 - attribute \src "libresoc.v:21666.3-21667.43" + attribute \src "libresoc.v:22049.3-22070.6" + wire $0\data_r0__o_ok$next[0:0]$730 + attribute \src "libresoc.v:21758.3-21759.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:21979.3-22000.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$745 - attribute \src "libresoc.v:21660.3-21661.43" + attribute \src "libresoc.v:22071.3-22092.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$737 + attribute \src "libresoc.v:21752.3-21753.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:21979.3-22000.6" - wire $0\data_r1__cr_a_ok$next[0:0]$746 - attribute \src "libresoc.v:21662.3-21663.49" + attribute \src "libresoc.v:22071.3-22092.6" + wire $0\data_r1__cr_a_ok$next[0:0]$738 + attribute \src "libresoc.v:21754.3-21755.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22001.3-22022.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$753 - attribute \src "libresoc.v:21656.3-21657.47" + attribute \src "libresoc.v:22093.3-22114.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$745 + attribute \src "libresoc.v:21748.3-21749.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22001.3-22022.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$754 - attribute \src "libresoc.v:21658.3-21659.53" + attribute \src "libresoc.v:22093.3-22114.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$746 + attribute \src "libresoc.v:21750.3-21751.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22023.3-22044.6" - wire width 2 $0\data_r3__xer_ov$next[1:0]$761 - attribute \src "libresoc.v:21652.3-21653.47" + attribute \src "libresoc.v:22115.3-22136.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$753 + attribute \src "libresoc.v:21744.3-21745.47" wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22023.3-22044.6" - wire $0\data_r3__xer_ov_ok$next[0:0]$762 - attribute \src "libresoc.v:21654.3-21655.53" + attribute \src "libresoc.v:22115.3-22136.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$754 + attribute \src "libresoc.v:21746.3-21747.53" wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22045.3-22066.6" - wire $0\data_r4__xer_so$next[0:0]$769 - attribute \src "libresoc.v:21648.3-21649.47" + attribute \src "libresoc.v:22137.3-22158.6" + wire $0\data_r4__xer_so$next[0:0]$761 + attribute \src "libresoc.v:21740.3-21741.47" wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22045.3-22066.6" - wire $0\data_r4__xer_so_ok$next[0:0]$770 - attribute \src "libresoc.v:21650.3-21651.53" + attribute \src "libresoc.v:22137.3-22158.6" + wire $0\data_r4__xer_so_ok$next[0:0]$762 + attribute \src "libresoc.v:21742.3-21743.53" wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22125.3-22134.6" + attribute \src "libresoc.v:22217.3-22226.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22135.3-22144.6" + attribute \src "libresoc.v:22227.3-22236.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22145.3-22154.6" + attribute \src "libresoc.v:22237.3-22246.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22155.3-22164.6" + attribute \src "libresoc.v:22247.3-22256.6" wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22165.3-22174.6" + attribute \src "libresoc.v:22257.3-22266.6" wire $0\dest5_o[0:0] - attribute \src "libresoc.v:20893.7-20893.20" + attribute \src "libresoc.v:20985.7-20985.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21873.3-21881.6" - wire $0\opc_l_r_opc$next[0:0]$679 - attribute \src "libresoc.v:21712.3-21713.39" + attribute \src "libresoc.v:21965.3-21973.6" + wire $0\opc_l_r_opc$next[0:0]$671 + attribute \src "libresoc.v:21804.3-21805.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21864.3-21872.6" - wire $0\opc_l_s_opc$next[0:0]$676 - attribute \src "libresoc.v:21714.3-21715.39" + attribute \src "libresoc.v:21956.3-21964.6" + wire $0\opc_l_s_opc$next[0:0]$668 + attribute \src "libresoc.v:21806.3-21807.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22175.3-22183.6" - wire width 5 $0\prev_wr_go$next[4:0]$800 - attribute \src "libresoc.v:21724.3-21725.37" + attribute \src "libresoc.v:22267.3-22275.6" + wire width 5 $0\prev_wr_go$next[4:0]$792 + attribute \src "libresoc.v:21816.3-21817.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:21818.3-21827.6" + attribute \src "libresoc.v:21910.3-21919.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:21909.3-21917.6" - wire width 5 $0\req_l_r_req$next[4:0]$691 - attribute \src "libresoc.v:21704.3-21705.39" + attribute \src "libresoc.v:22001.3-22009.6" + wire width 5 $0\req_l_r_req$next[4:0]$683 + attribute \src "libresoc.v:21796.3-21797.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:21900.3-21908.6" - wire width 5 $0\req_l_s_req$next[4:0]$688 - attribute \src "libresoc.v:21706.3-21707.39" + attribute \src "libresoc.v:21992.3-22000.6" + wire width 5 $0\req_l_s_req$next[4:0]$680 + attribute \src "libresoc.v:21798.3-21799.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:21837.3-21845.6" - wire $0\rok_l_r_rdok$next[0:0]$667 - attribute \src "libresoc.v:21720.3-21721.41" + attribute \src "libresoc.v:21929.3-21937.6" + wire $0\rok_l_r_rdok$next[0:0]$659 + attribute \src "libresoc.v:21812.3-21813.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21828.3-21836.6" - wire $0\rok_l_s_rdok$next[0:0]$664 - attribute \src "libresoc.v:21722.3-21723.41" + attribute \src "libresoc.v:21920.3-21928.6" + wire $0\rok_l_s_rdok$next[0:0]$656 + attribute \src "libresoc.v:21814.3-21815.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21855.3-21863.6" - wire $0\rst_l_r_rst$next[0:0]$673 - attribute \src "libresoc.v:21716.3-21717.39" + attribute \src "libresoc.v:21947.3-21955.6" + wire $0\rst_l_r_rst$next[0:0]$665 + attribute \src "libresoc.v:21808.3-21809.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21846.3-21854.6" - wire $0\rst_l_s_rst$next[0:0]$670 - attribute \src "libresoc.v:21718.3-21719.39" + attribute \src "libresoc.v:21938.3-21946.6" + wire $0\rst_l_s_rst$next[0:0]$662 + attribute \src "libresoc.v:21810.3-21811.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21891.3-21899.6" - wire width 4 $0\src_l_r_src$next[3:0]$685 - attribute \src "libresoc.v:21708.3-21709.39" + attribute \src "libresoc.v:21983.3-21991.6" + wire width 4 $0\src_l_r_src$next[3:0]$677 + attribute \src "libresoc.v:21800.3-21801.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:21882.3-21890.6" - wire width 4 $0\src_l_s_src$next[3:0]$682 - attribute \src "libresoc.v:21710.3-21711.39" + attribute \src "libresoc.v:21974.3-21982.6" + wire width 4 $0\src_l_s_src$next[3:0]$674 + attribute \src "libresoc.v:21802.3-21803.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22067.3-22076.6" - wire width 64 $0\src_r0$next[63:0]$777 - attribute \src "libresoc.v:21646.3-21647.29" + attribute \src "libresoc.v:22159.3-22168.6" + wire width 64 $0\src_r0$next[63:0]$769 + attribute \src "libresoc.v:21738.3-21739.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22077.3-22086.6" - wire width 64 $0\src_r1$next[63:0]$780 - attribute \src "libresoc.v:21644.3-21645.29" + attribute \src "libresoc.v:22169.3-22178.6" + wire width 64 $0\src_r1$next[63:0]$772 + attribute \src "libresoc.v:21736.3-21737.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22087.3-22096.6" - wire $0\src_r2$next[0:0]$783 - attribute \src "libresoc.v:21642.3-21643.29" + attribute \src "libresoc.v:22179.3-22188.6" + wire $0\src_r2$next[0:0]$775 + attribute \src "libresoc.v:21734.3-21735.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:22097.3-22106.6" - wire width 2 $0\src_r3$next[1:0]$786 - attribute \src "libresoc.v:21640.3-21641.29" + attribute \src "libresoc.v:22189.3-22198.6" + wire width 2 $0\src_r3$next[1:0]$778 + attribute \src "libresoc.v:21732.3-21733.29" wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21031.7-21031.24" + attribute \src "libresoc.v:21123.7-21123.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$712 - attribute \src "libresoc.v:21039.13-21039.45" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + attribute \src "libresoc.v:21131.13-21131.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 - attribute \src "libresoc.v:21056.14-21056.48" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 + attribute \src "libresoc.v:21148.14-21148.48" wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 - attribute \src "libresoc.v:21060.14-21060.68" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + attribute \src "libresoc.v:21152.14-21152.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 - attribute \src "libresoc.v:21064.7-21064.43" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + attribute \src "libresoc.v:21156.7-21156.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 - attribute \src "libresoc.v:21072.13-21072.48" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + attribute \src "libresoc.v:21164.13-21164.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$717 - attribute \src "libresoc.v:21076.14-21076.43" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 + attribute \src "libresoc.v:21168.14-21168.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 - attribute \src "libresoc.v:21154.13-21154.47" + attribute \src "libresoc.v:22010.3-22048.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + attribute \src "libresoc.v:21246.13-21246.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__invert_in$next[0:0]$719 - attribute \src "libresoc.v:21158.7-21158.40" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + attribute \src "libresoc.v:21250.7-21250.40" wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__invert_out$next[0:0]$720 - attribute \src "libresoc.v:21162.7-21162.41" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + attribute \src "libresoc.v:21254.7-21254.41" wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 - attribute \src "libresoc.v:21166.7-21166.39" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + attribute \src "libresoc.v:21258.7-21258.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__is_signed$next[0:0]$722 - attribute \src "libresoc.v:21170.7-21170.40" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + attribute \src "libresoc.v:21262.7-21262.40" wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 - attribute \src "libresoc.v:21174.7-21174.37" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + attribute \src "libresoc.v:21266.7-21266.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 - attribute \src "libresoc.v:21178.7-21178.37" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + attribute \src "libresoc.v:21270.7-21270.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__output_carry$next[0:0]$725 - attribute \src "libresoc.v:21182.7-21182.43" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + attribute \src "libresoc.v:21274.7-21274.43" wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:21186.7-21186.37" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + attribute \src "libresoc.v:21278.7-21278.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:21190.7-21190.37" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + attribute \src "libresoc.v:21282.7-21282.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 - attribute \src "libresoc.v:21194.7-21194.40" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + attribute \src "libresoc.v:21286.7-21286.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire $1\alu_alu0_alu_op__zero_a$next[0:0]$729 - attribute \src "libresoc.v:21198.7-21198.37" + attribute \src "libresoc.v:22010.3-22048.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + attribute \src "libresoc.v:21290.7-21290.37" wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21230.7-21230.26" + attribute \src "libresoc.v:21322.7-21322.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22116.3-22124.6" - wire $1\alu_l_r_alu$next[0:0]$793 - attribute \src "libresoc.v:21238.7-21238.25" + attribute \src "libresoc.v:22208.3-22216.6" + wire $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:21330.7-21330.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22107.3-22115.6" - wire $1\alui_l_r_alui$next[0:0]$790 - attribute \src "libresoc.v:21250.7-21250.27" + attribute \src "libresoc.v:22199.3-22207.6" + wire $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:21342.7-21342.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:21957.3-21978.6" - wire width 64 $1\data_r0__o$next[63:0]$739 - attribute \src "libresoc.v:21284.14-21284.47" + attribute \src "libresoc.v:22049.3-22070.6" + wire width 64 $1\data_r0__o$next[63:0]$731 + attribute \src "libresoc.v:21376.14-21376.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:21957.3-21978.6" - wire $1\data_r0__o_ok$next[0:0]$740 - attribute \src "libresoc.v:21288.7-21288.27" + attribute \src "libresoc.v:22049.3-22070.6" + wire $1\data_r0__o_ok$next[0:0]$732 + attribute \src "libresoc.v:21380.7-21380.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:21979.3-22000.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$747 - attribute \src "libresoc.v:21292.13-21292.33" + attribute \src "libresoc.v:22071.3-22092.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$739 + attribute \src "libresoc.v:21384.13-21384.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:21979.3-22000.6" - wire $1\data_r1__cr_a_ok$next[0:0]$748 - attribute \src "libresoc.v:21296.7-21296.30" + attribute \src "libresoc.v:22071.3-22092.6" + wire $1\data_r1__cr_a_ok$next[0:0]$740 + attribute \src "libresoc.v:21388.7-21388.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22001.3-22022.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$755 - attribute \src "libresoc.v:21300.13-21300.35" + attribute \src "libresoc.v:22093.3-22114.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$747 + attribute \src "libresoc.v:21392.13-21392.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22001.3-22022.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$756 - attribute \src "libresoc.v:21304.7-21304.32" + attribute \src "libresoc.v:22093.3-22114.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$748 + attribute \src "libresoc.v:21396.7-21396.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22023.3-22044.6" - wire width 2 $1\data_r3__xer_ov$next[1:0]$763 - attribute \src "libresoc.v:21308.13-21308.35" + attribute \src "libresoc.v:22115.3-22136.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$755 + attribute \src "libresoc.v:21400.13-21400.35" wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22023.3-22044.6" - wire $1\data_r3__xer_ov_ok$next[0:0]$764 - attribute \src "libresoc.v:21312.7-21312.32" + attribute \src "libresoc.v:22115.3-22136.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$756 + attribute \src "libresoc.v:21404.7-21404.32" wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22045.3-22066.6" - wire $1\data_r4__xer_so$next[0:0]$771 - attribute \src "libresoc.v:21316.7-21316.29" + attribute \src "libresoc.v:22137.3-22158.6" + wire $1\data_r4__xer_so$next[0:0]$763 + attribute \src "libresoc.v:21408.7-21408.29" wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22045.3-22066.6" - wire $1\data_r4__xer_so_ok$next[0:0]$772 - attribute \src "libresoc.v:21320.7-21320.32" + attribute \src "libresoc.v:22137.3-22158.6" + wire $1\data_r4__xer_so_ok$next[0:0]$764 + attribute \src "libresoc.v:21412.7-21412.32" wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22125.3-22134.6" + attribute \src "libresoc.v:22217.3-22226.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22135.3-22144.6" + attribute \src "libresoc.v:22227.3-22236.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22145.3-22154.6" + attribute \src "libresoc.v:22237.3-22246.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22155.3-22164.6" + attribute \src "libresoc.v:22247.3-22256.6" wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22165.3-22174.6" + attribute \src "libresoc.v:22257.3-22266.6" wire $1\dest5_o[0:0] - attribute \src "libresoc.v:21873.3-21881.6" - wire $1\opc_l_r_opc$next[0:0]$680 - attribute \src "libresoc.v:21343.7-21343.25" + attribute \src "libresoc.v:21965.3-21973.6" + wire $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21435.7-21435.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21864.3-21872.6" - wire $1\opc_l_s_opc$next[0:0]$677 - attribute \src "libresoc.v:21347.7-21347.25" + attribute \src "libresoc.v:21956.3-21964.6" + wire $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21439.7-21439.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22175.3-22183.6" - wire width 5 $1\prev_wr_go$next[4:0]$801 - attribute \src "libresoc.v:21478.13-21478.31" + attribute \src "libresoc.v:22267.3-22275.6" + wire width 5 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:21570.13-21570.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:21818.3-21827.6" + attribute \src "libresoc.v:21910.3-21919.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:21909.3-21917.6" - wire width 5 $1\req_l_r_req$next[4:0]$692 - attribute \src "libresoc.v:21486.13-21486.32" + attribute \src "libresoc.v:22001.3-22009.6" + wire width 5 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:21578.13-21578.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:21900.3-21908.6" - wire width 5 $1\req_l_s_req$next[4:0]$689 - attribute \src "libresoc.v:21490.13-21490.32" + attribute \src "libresoc.v:21992.3-22000.6" + wire width 5 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21582.13-21582.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:21837.3-21845.6" - wire $1\rok_l_r_rdok$next[0:0]$668 - attribute \src "libresoc.v:21502.7-21502.26" + attribute \src "libresoc.v:21929.3-21937.6" + wire $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21594.7-21594.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21828.3-21836.6" - wire $1\rok_l_s_rdok$next[0:0]$665 - attribute \src "libresoc.v:21506.7-21506.26" + attribute \src "libresoc.v:21920.3-21928.6" + wire $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21598.7-21598.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21855.3-21863.6" - wire $1\rst_l_r_rst$next[0:0]$674 - attribute \src "libresoc.v:21510.7-21510.25" + attribute \src "libresoc.v:21947.3-21955.6" + wire $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21602.7-21602.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21846.3-21854.6" - wire $1\rst_l_s_rst$next[0:0]$671 - attribute \src "libresoc.v:21514.7-21514.25" + attribute \src "libresoc.v:21938.3-21946.6" + wire $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21606.7-21606.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21891.3-21899.6" - wire width 4 $1\src_l_r_src$next[3:0]$686 - attribute \src "libresoc.v:21530.13-21530.31" + attribute \src "libresoc.v:21983.3-21991.6" + wire width 4 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21622.13-21622.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:21882.3-21890.6" - wire width 4 $1\src_l_s_src$next[3:0]$683 - attribute \src "libresoc.v:21534.13-21534.31" + attribute \src "libresoc.v:21974.3-21982.6" + wire width 4 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21626.13-21626.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22067.3-22076.6" - wire width 64 $1\src_r0$next[63:0]$778 - attribute \src "libresoc.v:21542.14-21542.43" + attribute \src "libresoc.v:22159.3-22168.6" + wire width 64 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:21634.14-21634.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22077.3-22086.6" - wire width 64 $1\src_r1$next[63:0]$781 - attribute \src "libresoc.v:21546.14-21546.43" + attribute \src "libresoc.v:22169.3-22178.6" + wire width 64 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:21638.14-21638.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22087.3-22096.6" - wire $1\src_r2$next[0:0]$784 - attribute \src "libresoc.v:21550.7-21550.20" + attribute \src "libresoc.v:22179.3-22188.6" + wire $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:21642.7-21642.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:22097.3-22106.6" - wire width 2 $1\src_r3$next[1:0]$787 - attribute \src "libresoc.v:21554.13-21554.26" + attribute \src "libresoc.v:22189.3-22198.6" + wire width 2 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:21646.13-21646.26" wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:21918.3-21956.6" - wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 - attribute \src "libresoc.v:21918.3-21956.6" - wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 - attribute \src "libresoc.v:21918.3-21956.6" - wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 - attribute \src "libresoc.v:21918.3-21956.6" - wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 - attribute \src "libresoc.v:21918.3-21956.6" - wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 - attribute \src "libresoc.v:21918.3-21956.6" - wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 - attribute \src "libresoc.v:21957.3-21978.6" - wire width 64 $2\data_r0__o$next[63:0]$741 - attribute \src "libresoc.v:21957.3-21978.6" - wire $2\data_r0__o_ok$next[0:0]$742 - attribute \src "libresoc.v:21979.3-22000.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$749 - attribute \src "libresoc.v:21979.3-22000.6" - wire $2\data_r1__cr_a_ok$next[0:0]$750 - attribute \src "libresoc.v:22001.3-22022.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$757 - attribute \src "libresoc.v:22001.3-22022.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$758 - attribute \src "libresoc.v:22023.3-22044.6" - wire width 2 $2\data_r3__xer_ov$next[1:0]$765 - attribute \src "libresoc.v:22023.3-22044.6" - wire $2\data_r3__xer_ov_ok$next[0:0]$766 - attribute \src "libresoc.v:22045.3-22066.6" - wire $2\data_r4__xer_so$next[0:0]$773 - attribute \src "libresoc.v:22045.3-22066.6" - wire $2\data_r4__xer_so_ok$next[0:0]$774 - attribute \src "libresoc.v:21957.3-21978.6" - wire $3\data_r0__o_ok$next[0:0]$743 - attribute \src "libresoc.v:21979.3-22000.6" - wire $3\data_r1__cr_a_ok$next[0:0]$751 - attribute \src "libresoc.v:22001.3-22022.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$759 - attribute \src "libresoc.v:22023.3-22044.6" - wire $3\data_r3__xer_ov_ok$next[0:0]$767 - attribute \src "libresoc.v:22045.3-22066.6" - wire $3\data_r4__xer_so_ok$next[0:0]$775 - attribute \src "libresoc.v:21570.18-21570.134" - wire $and$libresoc.v:21570$549_Y - attribute \src "libresoc.v:21571.19-21571.133" - wire $and$libresoc.v:21571$550_Y - attribute \src "libresoc.v:21572.19-21572.161" - wire width 4 $and$libresoc.v:21572$551_Y - attribute \src "libresoc.v:21575.19-21575.134" - wire width 4 $and$libresoc.v:21575$554_Y - attribute \src "libresoc.v:21577.19-21577.115" - wire width 4 $and$libresoc.v:21577$556_Y - attribute \src "libresoc.v:21578.19-21578.125" - wire $and$libresoc.v:21578$557_Y - attribute \src "libresoc.v:21579.19-21579.125" - wire $and$libresoc.v:21579$558_Y - attribute \src "libresoc.v:21580.18-21580.110" - wire $and$libresoc.v:21580$559_Y - attribute \src "libresoc.v:21581.19-21581.125" - wire $and$libresoc.v:21581$560_Y - attribute \src "libresoc.v:21582.19-21582.125" - wire $and$libresoc.v:21582$561_Y - attribute \src "libresoc.v:21583.19-21583.125" - wire $and$libresoc.v:21583$562_Y - attribute \src "libresoc.v:21584.19-21584.157" - wire width 5 $and$libresoc.v:21584$563_Y - attribute \src "libresoc.v:21585.19-21585.121" - wire width 5 $and$libresoc.v:21585$564_Y - attribute \src "libresoc.v:21586.19-21586.127" - wire $and$libresoc.v:21586$565_Y - attribute \src "libresoc.v:21587.19-21587.127" - wire $and$libresoc.v:21587$566_Y - attribute \src "libresoc.v:21588.19-21588.127" - wire $and$libresoc.v:21588$567_Y - attribute \src "libresoc.v:21589.19-21589.127" - wire $and$libresoc.v:21589$568_Y - attribute \src "libresoc.v:21590.19-21590.127" - wire $and$libresoc.v:21590$569_Y - attribute \src "libresoc.v:21592.18-21592.98" - wire $and$libresoc.v:21592$571_Y - attribute \src "libresoc.v:21594.18-21594.100" - wire $and$libresoc.v:21594$573_Y - attribute \src "libresoc.v:21595.18-21595.171" - wire width 5 $and$libresoc.v:21595$574_Y - attribute \src "libresoc.v:21597.18-21597.119" - wire width 5 $and$libresoc.v:21597$576_Y - attribute \src "libresoc.v:21600.18-21600.116" - wire $and$libresoc.v:21600$579_Y - attribute \src "libresoc.v:21604.17-21604.123" - wire $and$libresoc.v:21604$583_Y - attribute \src "libresoc.v:21606.18-21606.113" - wire $and$libresoc.v:21606$585_Y - attribute \src "libresoc.v:21607.18-21607.125" - wire width 5 $and$libresoc.v:21607$586_Y - attribute \src "libresoc.v:21609.18-21609.112" - wire $and$libresoc.v:21609$588_Y - attribute \src "libresoc.v:21611.18-21611.126" - wire $and$libresoc.v:21611$590_Y - attribute \src "libresoc.v:21612.18-21612.126" - wire $and$libresoc.v:21612$591_Y - attribute \src "libresoc.v:21613.18-21613.117" - wire $and$libresoc.v:21613$592_Y - attribute \src "libresoc.v:21618.18-21618.130" - wire $and$libresoc.v:21618$597_Y - attribute \src "libresoc.v:21619.18-21619.124" - wire width 5 $and$libresoc.v:21619$598_Y - attribute \src "libresoc.v:21622.18-21622.116" - wire $and$libresoc.v:21622$601_Y - attribute \src "libresoc.v:21623.18-21623.119" - wire $and$libresoc.v:21623$602_Y - attribute \src "libresoc.v:21624.18-21624.121" - wire $and$libresoc.v:21624$603_Y - attribute \src "libresoc.v:21625.18-21625.121" - wire $and$libresoc.v:21625$604_Y - attribute \src "libresoc.v:21626.18-21626.121" - wire $and$libresoc.v:21626$605_Y - attribute \src "libresoc.v:21608.18-21608.113" - wire $eq$libresoc.v:21608$587_Y - attribute \src "libresoc.v:21610.18-21610.119" - wire $eq$libresoc.v:21610$589_Y - attribute \src "libresoc.v:21573.19-21573.126" - wire $not$libresoc.v:21573$552_Y - attribute \src "libresoc.v:21574.19-21574.132" - wire $not$libresoc.v:21574$553_Y - attribute \src "libresoc.v:21576.19-21576.115" - wire width 4 $not$libresoc.v:21576$555_Y - attribute \src "libresoc.v:21591.18-21591.97" - wire $not$libresoc.v:21591$570_Y - attribute \src "libresoc.v:21593.18-21593.99" - wire $not$libresoc.v:21593$572_Y - attribute \src "libresoc.v:21596.18-21596.113" - wire width 5 $not$libresoc.v:21596$575_Y - attribute \src "libresoc.v:21599.18-21599.106" - wire $not$libresoc.v:21599$578_Y - attribute \src "libresoc.v:21605.18-21605.120" - wire $not$libresoc.v:21605$584_Y - attribute \src "libresoc.v:21620.17-21620.113" - wire width 4 $not$libresoc.v:21620$599_Y - attribute \src "libresoc.v:21603.18-21603.112" - wire $or$libresoc.v:21603$582_Y - attribute \src "libresoc.v:21614.18-21614.122" - wire $or$libresoc.v:21614$593_Y - attribute \src "libresoc.v:21615.18-21615.124" - wire $or$libresoc.v:21615$594_Y - attribute \src "libresoc.v:21616.18-21616.181" - wire width 5 $or$libresoc.v:21616$595_Y - attribute \src "libresoc.v:21617.18-21617.168" - wire width 4 $or$libresoc.v:21617$596_Y - attribute \src "libresoc.v:21621.18-21621.120" - wire width 5 $or$libresoc.v:21621$600_Y - attribute \src "libresoc.v:21630.17-21630.117" - wire width 4 $or$libresoc.v:21630$609_Y - attribute \src "libresoc.v:21569.17-21569.104" - wire $reduce_and$libresoc.v:21569$548_Y - attribute \src "libresoc.v:21598.18-21598.106" - wire $reduce_or$libresoc.v:21598$577_Y - attribute \src "libresoc.v:21601.18-21601.113" - wire $reduce_or$libresoc.v:21601$580_Y - attribute \src "libresoc.v:21602.18-21602.112" - wire $reduce_or$libresoc.v:21602$581_Y - attribute \src "libresoc.v:21627.18-21627.154" - wire $ternary$libresoc.v:21627$606_Y - attribute \src "libresoc.v:21628.18-21628.155" - wire width 64 $ternary$libresoc.v:21628$607_Y - attribute \src "libresoc.v:21629.18-21629.160" - wire $ternary$libresoc.v:21629$608_Y - attribute \src "libresoc.v:21631.18-21631.172" - wire width 64 $ternary$libresoc.v:21631$610_Y - attribute \src "libresoc.v:21632.18-21632.115" - wire width 64 $ternary$libresoc.v:21632$611_Y - attribute \src "libresoc.v:21633.18-21633.125" - wire width 64 $ternary$libresoc.v:21633$612_Y - attribute \src "libresoc.v:21634.18-21634.118" - wire $ternary$libresoc.v:21634$613_Y - attribute \src "libresoc.v:21635.18-21635.118" - wire width 2 $ternary$libresoc.v:21635$614_Y + attribute \src "libresoc.v:22010.3-22048.6" + wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + attribute \src "libresoc.v:22010.3-22048.6" + wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + attribute \src "libresoc.v:22010.3-22048.6" + wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + attribute \src "libresoc.v:22010.3-22048.6" + wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + attribute \src "libresoc.v:22010.3-22048.6" + wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + attribute \src "libresoc.v:22010.3-22048.6" + wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22049.3-22070.6" + wire width 64 $2\data_r0__o$next[63:0]$733 + attribute \src "libresoc.v:22049.3-22070.6" + wire $2\data_r0__o_ok$next[0:0]$734 + attribute \src "libresoc.v:22071.3-22092.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$741 + attribute \src "libresoc.v:22071.3-22092.6" + wire $2\data_r1__cr_a_ok$next[0:0]$742 + attribute \src "libresoc.v:22093.3-22114.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$749 + attribute \src "libresoc.v:22093.3-22114.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$750 + attribute \src "libresoc.v:22115.3-22136.6" + wire width 2 $2\data_r3__xer_ov$next[1:0]$757 + attribute \src "libresoc.v:22115.3-22136.6" + wire $2\data_r3__xer_ov_ok$next[0:0]$758 + attribute \src "libresoc.v:22137.3-22158.6" + wire $2\data_r4__xer_so$next[0:0]$765 + attribute \src "libresoc.v:22137.3-22158.6" + wire $2\data_r4__xer_so_ok$next[0:0]$766 + attribute \src "libresoc.v:22049.3-22070.6" + wire $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22071.3-22092.6" + wire $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22093.3-22114.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22115.3-22136.6" + wire $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22137.3-22158.6" + wire $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:21662.18-21662.134" + wire $and$libresoc.v:21662$541_Y + attribute \src "libresoc.v:21663.19-21663.133" + wire $and$libresoc.v:21663$542_Y + attribute \src "libresoc.v:21664.19-21664.161" + wire width 4 $and$libresoc.v:21664$543_Y + attribute \src "libresoc.v:21667.19-21667.134" + wire width 4 $and$libresoc.v:21667$546_Y + attribute \src "libresoc.v:21669.19-21669.115" + wire width 4 $and$libresoc.v:21669$548_Y + attribute \src "libresoc.v:21670.19-21670.125" + wire $and$libresoc.v:21670$549_Y + attribute \src "libresoc.v:21671.19-21671.125" + wire $and$libresoc.v:21671$550_Y + attribute \src "libresoc.v:21672.18-21672.110" + wire $and$libresoc.v:21672$551_Y + attribute \src "libresoc.v:21673.19-21673.125" + wire $and$libresoc.v:21673$552_Y + attribute \src "libresoc.v:21674.19-21674.125" + wire $and$libresoc.v:21674$553_Y + attribute \src "libresoc.v:21675.19-21675.125" + wire $and$libresoc.v:21675$554_Y + attribute \src "libresoc.v:21676.19-21676.157" + wire width 5 $and$libresoc.v:21676$555_Y + attribute \src "libresoc.v:21677.19-21677.121" + wire width 5 $and$libresoc.v:21677$556_Y + attribute \src "libresoc.v:21678.19-21678.127" + wire $and$libresoc.v:21678$557_Y + attribute \src "libresoc.v:21679.19-21679.127" + wire $and$libresoc.v:21679$558_Y + attribute \src "libresoc.v:21680.19-21680.127" + wire $and$libresoc.v:21680$559_Y + attribute \src "libresoc.v:21681.19-21681.127" + wire $and$libresoc.v:21681$560_Y + attribute \src "libresoc.v:21682.19-21682.127" + wire $and$libresoc.v:21682$561_Y + attribute \src "libresoc.v:21684.18-21684.98" + wire $and$libresoc.v:21684$563_Y + attribute \src "libresoc.v:21686.18-21686.100" + wire $and$libresoc.v:21686$565_Y + attribute \src "libresoc.v:21687.18-21687.171" + wire width 5 $and$libresoc.v:21687$566_Y + attribute \src "libresoc.v:21689.18-21689.119" + wire width 5 $and$libresoc.v:21689$568_Y + attribute \src "libresoc.v:21692.18-21692.116" + wire $and$libresoc.v:21692$571_Y + attribute \src "libresoc.v:21696.17-21696.123" + wire $and$libresoc.v:21696$575_Y + attribute \src "libresoc.v:21698.18-21698.113" + wire $and$libresoc.v:21698$577_Y + attribute \src "libresoc.v:21699.18-21699.125" + wire width 5 $and$libresoc.v:21699$578_Y + attribute \src "libresoc.v:21701.18-21701.112" + wire $and$libresoc.v:21701$580_Y + attribute \src "libresoc.v:21703.18-21703.126" + wire $and$libresoc.v:21703$582_Y + attribute \src "libresoc.v:21704.18-21704.126" + wire $and$libresoc.v:21704$583_Y + attribute \src "libresoc.v:21705.18-21705.117" + wire $and$libresoc.v:21705$584_Y + attribute \src "libresoc.v:21710.18-21710.130" + wire $and$libresoc.v:21710$589_Y + attribute \src "libresoc.v:21711.18-21711.124" + wire width 5 $and$libresoc.v:21711$590_Y + attribute \src "libresoc.v:21714.18-21714.116" + wire $and$libresoc.v:21714$593_Y + attribute \src "libresoc.v:21715.18-21715.119" + wire $and$libresoc.v:21715$594_Y + attribute \src "libresoc.v:21716.18-21716.121" + wire $and$libresoc.v:21716$595_Y + attribute \src "libresoc.v:21717.18-21717.121" + wire $and$libresoc.v:21717$596_Y + attribute \src "libresoc.v:21718.18-21718.121" + wire $and$libresoc.v:21718$597_Y + attribute \src "libresoc.v:21700.18-21700.113" + wire $eq$libresoc.v:21700$579_Y + attribute \src "libresoc.v:21702.18-21702.119" + wire $eq$libresoc.v:21702$581_Y + attribute \src "libresoc.v:21665.19-21665.126" + wire $not$libresoc.v:21665$544_Y + attribute \src "libresoc.v:21666.19-21666.132" + wire $not$libresoc.v:21666$545_Y + attribute \src "libresoc.v:21668.19-21668.115" + wire width 4 $not$libresoc.v:21668$547_Y + attribute \src "libresoc.v:21683.18-21683.97" + wire $not$libresoc.v:21683$562_Y + attribute \src "libresoc.v:21685.18-21685.99" + wire $not$libresoc.v:21685$564_Y + attribute \src "libresoc.v:21688.18-21688.113" + wire width 5 $not$libresoc.v:21688$567_Y + attribute \src "libresoc.v:21691.18-21691.106" + wire $not$libresoc.v:21691$570_Y + attribute \src "libresoc.v:21697.18-21697.120" + wire $not$libresoc.v:21697$576_Y + attribute \src "libresoc.v:21712.17-21712.113" + wire width 4 $not$libresoc.v:21712$591_Y + attribute \src "libresoc.v:21695.18-21695.112" + wire $or$libresoc.v:21695$574_Y + attribute \src "libresoc.v:21706.18-21706.122" + wire $or$libresoc.v:21706$585_Y + attribute \src "libresoc.v:21707.18-21707.124" + wire $or$libresoc.v:21707$586_Y + attribute \src "libresoc.v:21708.18-21708.181" + wire width 5 $or$libresoc.v:21708$587_Y + attribute \src "libresoc.v:21709.18-21709.168" + wire width 4 $or$libresoc.v:21709$588_Y + attribute \src "libresoc.v:21713.18-21713.120" + wire width 5 $or$libresoc.v:21713$592_Y + attribute \src "libresoc.v:21722.17-21722.117" + wire width 4 $or$libresoc.v:21722$601_Y + attribute \src "libresoc.v:21661.17-21661.104" + wire $reduce_and$libresoc.v:21661$540_Y + attribute \src "libresoc.v:21690.18-21690.106" + wire $reduce_or$libresoc.v:21690$569_Y + attribute \src "libresoc.v:21693.18-21693.113" + wire $reduce_or$libresoc.v:21693$572_Y + attribute \src "libresoc.v:21694.18-21694.112" + wire $reduce_or$libresoc.v:21694$573_Y + attribute \src "libresoc.v:21719.18-21719.154" + wire $ternary$libresoc.v:21719$598_Y + attribute \src "libresoc.v:21720.18-21720.155" + wire width 64 $ternary$libresoc.v:21720$599_Y + attribute \src "libresoc.v:21721.18-21721.160" + wire $ternary$libresoc.v:21721$600_Y + attribute \src "libresoc.v:21723.18-21723.172" + wire width 64 $ternary$libresoc.v:21723$602_Y + attribute \src "libresoc.v:21724.18-21724.115" + wire width 64 $ternary$libresoc.v:21724$603_Y + attribute \src "libresoc.v:21725.18-21725.125" + wire width 64 $ternary$libresoc.v:21725$604_Y + attribute \src "libresoc.v:21726.18-21726.118" + wire $ternary$libresoc.v:21726$605_Y + attribute \src "libresoc.v:21727.18-21727.118" + wire width 2 $ternary$libresoc.v:21727$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -31779,13 +31801,13 @@ module \alu0 wire \alu_alu0_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_alu0_alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_alu0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire \alu_alu0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_alu0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_alu0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_alu0_p_ready_o @@ -31795,13 +31817,13 @@ module \alu0 wire width 64 \alu_alu0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_alu0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_alu0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_alu0_xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_alu0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \alu_alu0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_alu0_xer_so$1 @@ -31833,32 +31855,32 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 40 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o + wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i + wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 23 \cu_rd__go_i + wire width 4 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 22 \cu_rd__rel_o + wire width 4 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 21 \cu_rdmaskn_i + wire width 4 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 30 \cu_wr__go_i + wire width 5 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 29 \cu_wr__rel_o + wire width 5 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 5 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -31902,19 +31924,19 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 31 \dest1_o + wire width 64 output 32 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 33 \dest2_o + wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 35 \dest3_o + wire width 2 output 36 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 37 \dest4_o + wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 39 \dest5_o - attribute \src "libresoc.v:20893.7-20893.15" + wire output 40 \dest5_o + attribute \src "libresoc.v:20985.7-20985.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -31926,7 +31948,7 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_alu0__data_len + wire width 4 input 18 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -31941,19 +31963,19 @@ module \alu0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_alu0__fn_unit + wire width 12 input 3 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_alu0__imm_data__data + wire width 64 input 4 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_alu0__imm_data__ok + wire input 5 \oper_i_alu_alu0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \oper_i_alu_alu0__input_carry + wire width 2 input 14 \oper_i_alu_alu0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_alu0__insn + wire width 32 input 19 \oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -32029,29 +32051,29 @@ module \alu0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_alu0__insn_type + wire width 7 input 2 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_alu0__invert_in + wire input 10 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_alu0__invert_out + wire input 12 \oper_i_alu_alu0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_alu0__is_32bit + wire input 16 \oper_i_alu_alu0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_alu0__is_signed + wire input 17 \oper_i_alu_alu0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_alu0__oe__oe + wire input 8 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_alu0__oe__ok + wire input 9 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_alu0__output_carry + wire input 15 \oper_i_alu_alu0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_alu0__rc__ok + wire input 7 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_alu0__rc__rc + wire input 6 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_alu0__write_cr0 + wire input 13 \oper_i_alu_alu0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_alu0__zero_a + wire input 11 \oper_i_alu_alu0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -32095,13 +32117,13 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i + wire width 64 input 25 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i + wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 26 \src3_i + wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 27 \src4_i + wire width 2 input 28 \src4_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -32138,14 +32160,14 @@ module \alu0 wire \src_sel$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 34 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 35 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:21570$549 + cell $and $and$libresoc.v:21662$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32153,10 +32175,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:21570$549_Y + connect \Y $and$libresoc.v:21662$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:21571$550 + cell $and $and$libresoc.v:21663$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32164,10 +32186,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:21571$550_Y + connect \Y $and$libresoc.v:21663$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21572$551 + cell $and $and$libresoc.v:21664$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32175,10 +32197,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21572$551_Y + connect \Y $and$libresoc.v:21664$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21575$554 + cell $and $and$libresoc.v:21667$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32186,10 +32208,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } - connect \Y $and$libresoc.v:21575$554_Y + connect \Y $and$libresoc.v:21667$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21577$556 + cell $and $and$libresoc.v:21669$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32197,10 +32219,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 - connect \Y $and$libresoc.v:21577$556_Y + connect \Y $and$libresoc.v:21669$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21578$557 + cell $and $and$libresoc.v:21670$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32208,10 +32230,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21578$557_Y + connect \Y $and$libresoc.v:21670$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21579$558 + cell $and $and$libresoc.v:21671$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32219,10 +32241,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21579$558_Y + connect \Y $and$libresoc.v:21671$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:21580$559 + cell $and $and$libresoc.v:21672$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32230,10 +32252,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:21580$559_Y + connect \Y $and$libresoc.v:21672$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21581$560 + cell $and $and$libresoc.v:21673$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32241,10 +32263,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21581$560_Y + connect \Y $and$libresoc.v:21673$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21582$561 + cell $and $and$libresoc.v:21674$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32252,10 +32274,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21582$561_Y + connect \Y $and$libresoc.v:21674$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21583$562 + cell $and $and$libresoc.v:21675$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32263,10 +32285,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21583$562_Y + connect \Y $and$libresoc.v:21675$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21584$563 + cell $and $and$libresoc.v:21676$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32274,10 +32296,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$libresoc.v:21584$563_Y + connect \Y $and$libresoc.v:21676$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21585$564 + cell $and $and$libresoc.v:21677$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32285,10 +32307,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21585$564_Y + connect \Y $and$libresoc.v:21677$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21586$565 + cell $and $and$libresoc.v:21678$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32296,10 +32318,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21586$565_Y + connect \Y $and$libresoc.v:21678$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21587$566 + cell $and $and$libresoc.v:21679$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32307,10 +32329,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21587$566_Y + connect \Y $and$libresoc.v:21679$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21588$567 + cell $and $and$libresoc.v:21680$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32318,10 +32340,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21588$567_Y + connect \Y $and$libresoc.v:21680$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21589$568 + cell $and $and$libresoc.v:21681$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32329,10 +32351,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21589$568_Y + connect \Y $and$libresoc.v:21681$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21590$569 + cell $and $and$libresoc.v:21682$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32340,10 +32362,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21590$569_Y + connect \Y $and$libresoc.v:21682$561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:21592$571 + cell $and $and$libresoc.v:21684$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32351,10 +32373,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:21592$571_Y + connect \Y $and$libresoc.v:21684$563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:21594$573 + cell $and $and$libresoc.v:21686$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32362,10 +32384,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:21594$573_Y + connect \Y $and$libresoc.v:21686$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:21595$574 + cell $and $and$libresoc.v:21687$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32373,10 +32395,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21595$574_Y + connect \Y $and$libresoc.v:21687$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21597$576 + cell $and $and$libresoc.v:21689$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32384,10 +32406,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:21597$576_Y + connect \Y $and$libresoc.v:21689$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21600$579 + cell $and $and$libresoc.v:21692$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32395,10 +32417,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:21600$579_Y + connect \Y $and$libresoc.v:21692$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:21604$583 + cell $and $and$libresoc.v:21696$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32406,10 +32428,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:21604$583_Y + connect \Y $and$libresoc.v:21696$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:21606$585 + cell $and $and$libresoc.v:21698$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32417,10 +32439,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:21606$585_Y + connect \Y $and$libresoc.v:21698$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21607$586 + cell $and $and$libresoc.v:21699$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32428,10 +32450,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21607$586_Y + connect \Y $and$libresoc.v:21699$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:21609$588 + cell $and $and$libresoc.v:21701$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32439,10 +32461,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:21609$588_Y + connect \Y $and$libresoc.v:21701$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21611$590 + cell $and $and$libresoc.v:21703$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32450,10 +32472,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i - connect \Y $and$libresoc.v:21611$590_Y + connect \Y $and$libresoc.v:21703$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21612$591 + cell $and $and$libresoc.v:21704$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32461,10 +32483,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o - connect \Y $and$libresoc.v:21612$591_Y + connect \Y $and$libresoc.v:21704$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:21613$592 + cell $and $and$libresoc.v:21705$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32472,10 +32494,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:21613$592_Y + connect \Y $and$libresoc.v:21705$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:21618$597 + cell $and $and$libresoc.v:21710$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32483,10 +32505,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:21618$597_Y + connect \Y $and$libresoc.v:21710$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:21619$598 + cell $and $and$libresoc.v:21711$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32494,10 +32516,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21619$598_Y + connect \Y $and$libresoc.v:21711$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21622$601 + cell $and $and$libresoc.v:21714$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32505,10 +32527,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21622$601_Y + connect \Y $and$libresoc.v:21714$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21623$602 + cell $and $and$libresoc.v:21715$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32516,10 +32538,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21623$602_Y + connect \Y $and$libresoc.v:21715$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21624$603 + cell $and $and$libresoc.v:21716$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32527,10 +32549,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21624$603_Y + connect \Y $and$libresoc.v:21716$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21625$604 + cell $and $and$libresoc.v:21717$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32538,10 +32560,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21625$604_Y + connect \Y $and$libresoc.v:21717$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:21626$605 + cell $and $and$libresoc.v:21718$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32549,10 +32571,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:21626$605_Y + connect \Y $and$libresoc.v:21718$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:21608$587 + cell $eq $eq$libresoc.v:21700$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32560,10 +32582,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:21608$587_Y + connect \Y $eq$libresoc.v:21700$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:21610$589 + cell $eq $eq$libresoc.v:21702$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32571,82 +32593,82 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:21610$589_Y + connect \Y $eq$libresoc.v:21702$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21573$552 + cell $not $not$libresoc.v:21665$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$libresoc.v:21573$552_Y + connect \Y $not$libresoc.v:21665$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21574$553 + cell $not $not$libresoc.v:21666$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$libresoc.v:21574$553_Y + connect \Y $not$libresoc.v:21666$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:21576$555 + cell $not $not$libresoc.v:21668$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:21576$555_Y + connect \Y $not$libresoc.v:21668$547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:21591$570 + cell $not $not$libresoc.v:21683$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:21591$570_Y + connect \Y $not$libresoc.v:21683$562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:21593$572 + cell $not $not$libresoc.v:21685$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:21593$572_Y + connect \Y $not$libresoc.v:21685$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21596$575 + cell $not $not$libresoc.v:21688$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:21596$575_Y + connect \Y $not$libresoc.v:21688$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21599$578 + cell $not $not$libresoc.v:21691$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:21599$578_Y + connect \Y $not$libresoc.v:21691$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:21605$584 + cell $not $not$libresoc.v:21697$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i - connect \Y $not$libresoc.v:21605$584_Y + connect \Y $not$libresoc.v:21697$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:21620$599 + cell $not $not$libresoc.v:21712$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:21620$599_Y + connect \Y $not$libresoc.v:21712$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:21603$582 + cell $or $or$libresoc.v:21695$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32654,10 +32676,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:21603$582_Y + connect \Y $or$libresoc.v:21695$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:21614$593 + cell $or $or$libresoc.v:21706$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32665,10 +32687,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21614$593_Y + connect \Y $or$libresoc.v:21706$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:21615$594 + cell $or $or$libresoc.v:21707$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32676,10 +32698,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21615$594_Y + connect \Y $or$libresoc.v:21707$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:21616$595 + cell $or $or$libresoc.v:21708$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32687,10 +32709,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21616$595_Y + connect \Y $or$libresoc.v:21708$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:21617$596 + cell $or $or$libresoc.v:21709$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32698,10 +32720,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21617$596_Y + connect \Y $or$libresoc.v:21709$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:21621$600 + cell $or $or$libresoc.v:21713$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32709,10 +32731,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:21621$600_Y + connect \Y $or$libresoc.v:21713$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:21630$609 + cell $or $or$libresoc.v:21722$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32720,106 +32742,106 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:21630$609_Y + connect \Y $or$libresoc.v:21722$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21569$548 + cell $reduce_and $reduce_and$libresoc.v:21661$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:21569$548_Y + connect \Y $reduce_and$libresoc.v:21661$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21598$577 + cell $reduce_or $reduce_or$libresoc.v:21690$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:21598$577_Y + connect \Y $reduce_or$libresoc.v:21690$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21601$580 + cell $reduce_or $reduce_or$libresoc.v:21693$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21601$580_Y + connect \Y $reduce_or$libresoc.v:21693$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21602$581 + cell $reduce_or $reduce_or$libresoc.v:21694$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:21602$581_Y + connect \Y $reduce_or$libresoc.v:21694$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21627$606 + cell $mux $ternary$libresoc.v:21719$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21627$606_Y + connect \Y $ternary$libresoc.v:21719$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21628$607 + cell $mux $ternary$libresoc.v:21720$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21628$607_Y + connect \Y $ternary$libresoc.v:21720$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21629$608 + cell $mux $ternary$libresoc.v:21721$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21629$608_Y + connect \Y $ternary$libresoc.v:21721$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21631$610 + cell $mux $ternary$libresoc.v:21723$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21631$610_Y + connect \Y $ternary$libresoc.v:21723$602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21632$611 + cell $mux $ternary$libresoc.v:21724$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:21632$611_Y + connect \Y $ternary$libresoc.v:21724$603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21633$612 + cell $mux $ternary$libresoc.v:21725$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:21633$612_Y + connect \Y $ternary$libresoc.v:21725$604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21634$613 + cell $mux $ternary$libresoc.v:21726$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:21634$613_Y + connect \Y $ternary$libresoc.v:21726$605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21635$614 + cell $mux $ternary$libresoc.v:21727$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:21635$614_Y + connect \Y $ternary$libresoc.v:21727$606_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:21730.12-21769.4" + attribute \src "libresoc.v:21822.12-21861.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit @@ -32861,7 +32883,7 @@ module \alu0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:21770.9-21776.4" + attribute \src "libresoc.v:21862.9-21868.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32870,7 +32892,7 @@ module \alu0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:21777.10-21783.4" + attribute \src "libresoc.v:21869.10-21875.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32879,7 +32901,7 @@ module \alu0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:21784.9-21790.4" + attribute \src "libresoc.v:21876.9-21882.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32888,7 +32910,7 @@ module \alu0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:21791.9-21797.4" + attribute \src "libresoc.v:21883.9-21889.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32897,7 +32919,7 @@ module \alu0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:21798.9-21804.4" + attribute \src "libresoc.v:21890.9-21896.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32906,7 +32928,7 @@ module \alu0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:21805.9-21810.4" + attribute \src "libresoc.v:21897.9-21902.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32914,7 +32936,7 @@ module \alu0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:21811.9-21817.4" + attribute \src "libresoc.v:21903.9-21909.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -32922,727 +32944,727 @@ module \alu0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:20893.7-20893.20" - process $proc$libresoc.v:20893$802 + attribute \src "libresoc.v:20985.7-20985.20" + process $proc$libresoc.v:20985$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21031.7-21031.24" - process $proc$libresoc.v:21031$803 + attribute \src "libresoc.v:21123.7-21123.24" + process $proc$libresoc.v:21123$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:21039.13-21039.45" - process $proc$libresoc.v:21039$804 + attribute \src "libresoc.v:21131.13-21131.45" + process $proc$libresoc.v:21131$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21056.14-21056.48" - process $proc$libresoc.v:21056$805 + attribute \src "libresoc.v:21148.14-21148.48" + process $proc$libresoc.v:21148$797 assign { } { } assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] end - attribute \src "libresoc.v:21060.14-21060.68" - process $proc$libresoc.v:21060$806 + attribute \src "libresoc.v:21152.14-21152.68" + process $proc$libresoc.v:21152$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21064.7-21064.43" - process $proc$libresoc.v:21064$807 + attribute \src "libresoc.v:21156.7-21156.43" + process $proc$libresoc.v:21156$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21072.13-21072.48" - process $proc$libresoc.v:21072$808 + attribute \src "libresoc.v:21164.13-21164.48" + process $proc$libresoc.v:21164$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21076.14-21076.43" - process $proc$libresoc.v:21076$809 + attribute \src "libresoc.v:21168.14-21168.43" + process $proc$libresoc.v:21168$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21154.13-21154.47" - process $proc$libresoc.v:21154$810 + attribute \src "libresoc.v:21246.13-21246.47" + process $proc$libresoc.v:21246$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21158.7-21158.40" - process $proc$libresoc.v:21158$811 + attribute \src "libresoc.v:21250.7-21250.40" + process $proc$libresoc.v:21250$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21162.7-21162.41" - process $proc$libresoc.v:21162$812 + attribute \src "libresoc.v:21254.7-21254.41" + process $proc$libresoc.v:21254$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21166.7-21166.39" - process $proc$libresoc.v:21166$813 + attribute \src "libresoc.v:21258.7-21258.39" + process $proc$libresoc.v:21258$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21170.7-21170.40" - process $proc$libresoc.v:21170$814 + attribute \src "libresoc.v:21262.7-21262.40" + process $proc$libresoc.v:21262$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21174.7-21174.37" - process $proc$libresoc.v:21174$815 + attribute \src "libresoc.v:21266.7-21266.37" + process $proc$libresoc.v:21266$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21178.7-21178.37" - process $proc$libresoc.v:21178$816 + attribute \src "libresoc.v:21270.7-21270.37" + process $proc$libresoc.v:21270$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21182.7-21182.43" - process $proc$libresoc.v:21182$817 + attribute \src "libresoc.v:21274.7-21274.43" + process $proc$libresoc.v:21274$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21186.7-21186.37" - process $proc$libresoc.v:21186$818 + attribute \src "libresoc.v:21278.7-21278.37" + process $proc$libresoc.v:21278$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21190.7-21190.37" - process $proc$libresoc.v:21190$819 + attribute \src "libresoc.v:21282.7-21282.37" + process $proc$libresoc.v:21282$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21194.7-21194.40" - process $proc$libresoc.v:21194$820 + attribute \src "libresoc.v:21286.7-21286.40" + process $proc$libresoc.v:21286$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21198.7-21198.37" - process $proc$libresoc.v:21198$821 + attribute \src "libresoc.v:21290.7-21290.37" + process $proc$libresoc.v:21290$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21230.7-21230.26" - process $proc$libresoc.v:21230$822 + attribute \src "libresoc.v:21322.7-21322.26" + process $proc$libresoc.v:21322$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:21238.7-21238.25" - process $proc$libresoc.v:21238$823 + attribute \src "libresoc.v:21330.7-21330.25" + process $proc$libresoc.v:21330$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21250.7-21250.27" - process $proc$libresoc.v:21250$824 + attribute \src "libresoc.v:21342.7-21342.27" + process $proc$libresoc.v:21342$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21284.14-21284.47" - process $proc$libresoc.v:21284$825 + attribute \src "libresoc.v:21376.14-21376.47" + process $proc$libresoc.v:21376$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:21288.7-21288.27" - process $proc$libresoc.v:21288$826 + attribute \src "libresoc.v:21380.7-21380.27" + process $proc$libresoc.v:21380$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21292.13-21292.33" - process $proc$libresoc.v:21292$827 + attribute \src "libresoc.v:21384.13-21384.33" + process $proc$libresoc.v:21384$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21296.7-21296.30" - process $proc$libresoc.v:21296$828 + attribute \src "libresoc.v:21388.7-21388.30" + process $proc$libresoc.v:21388$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21300.13-21300.35" - process $proc$libresoc.v:21300$829 + attribute \src "libresoc.v:21392.13-21392.35" + process $proc$libresoc.v:21392$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21304.7-21304.32" - process $proc$libresoc.v:21304$830 + attribute \src "libresoc.v:21396.7-21396.32" + process $proc$libresoc.v:21396$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21308.13-21308.35" - process $proc$libresoc.v:21308$831 + attribute \src "libresoc.v:21400.13-21400.35" + process $proc$libresoc.v:21400$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21312.7-21312.32" - process $proc$libresoc.v:21312$832 + attribute \src "libresoc.v:21404.7-21404.32" + process $proc$libresoc.v:21404$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21316.7-21316.29" - process $proc$libresoc.v:21316$833 + attribute \src "libresoc.v:21408.7-21408.29" + process $proc$libresoc.v:21408$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21320.7-21320.32" - process $proc$libresoc.v:21320$834 + attribute \src "libresoc.v:21412.7-21412.32" + process $proc$libresoc.v:21412$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21343.7-21343.25" - process $proc$libresoc.v:21343$835 + attribute \src "libresoc.v:21435.7-21435.25" + process $proc$libresoc.v:21435$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21347.7-21347.25" - process $proc$libresoc.v:21347$836 + attribute \src "libresoc.v:21439.7-21439.25" + process $proc$libresoc.v:21439$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21478.13-21478.31" - process $proc$libresoc.v:21478$837 + attribute \src "libresoc.v:21570.13-21570.31" + process $proc$libresoc.v:21570$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:21486.13-21486.32" - process $proc$libresoc.v:21486$838 + attribute \src "libresoc.v:21578.13-21578.32" + process $proc$libresoc.v:21578$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:21490.13-21490.32" - process $proc$libresoc.v:21490$839 + attribute \src "libresoc.v:21582.13-21582.32" + process $proc$libresoc.v:21582$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:21502.7-21502.26" - process $proc$libresoc.v:21502$840 + attribute \src "libresoc.v:21594.7-21594.26" + process $proc$libresoc.v:21594$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21506.7-21506.26" - process $proc$libresoc.v:21506$841 + attribute \src "libresoc.v:21598.7-21598.26" + process $proc$libresoc.v:21598$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21510.7-21510.25" - process $proc$libresoc.v:21510$842 + attribute \src "libresoc.v:21602.7-21602.25" + process $proc$libresoc.v:21602$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21514.7-21514.25" - process $proc$libresoc.v:21514$843 + attribute \src "libresoc.v:21606.7-21606.25" + process $proc$libresoc.v:21606$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21530.13-21530.31" - process $proc$libresoc.v:21530$844 + attribute \src "libresoc.v:21622.13-21622.31" + process $proc$libresoc.v:21622$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:21534.13-21534.31" - process $proc$libresoc.v:21534$845 + attribute \src "libresoc.v:21626.13-21626.31" + process $proc$libresoc.v:21626$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:21542.14-21542.43" - process $proc$libresoc.v:21542$846 + attribute \src "libresoc.v:21634.14-21634.43" + process $proc$libresoc.v:21634$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:21546.14-21546.43" - process $proc$libresoc.v:21546$847 + attribute \src "libresoc.v:21638.14-21638.43" + process $proc$libresoc.v:21638$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:21550.7-21550.20" - process $proc$libresoc.v:21550$848 + attribute \src "libresoc.v:21642.7-21642.20" + process $proc$libresoc.v:21642$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:21554.13-21554.26" - process $proc$libresoc.v:21554$849 + attribute \src "libresoc.v:21646.13-21646.26" + process $proc$libresoc.v:21646$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end - attribute \src "libresoc.v:21636.3-21637.39" - process $proc$libresoc.v:21636$615 + attribute \src "libresoc.v:21728.3-21729.39" + process $proc$libresoc.v:21728$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21638.3-21639.43" - process $proc$libresoc.v:21638$616 + attribute \src "libresoc.v:21730.3-21731.43" + process $proc$libresoc.v:21730$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21640.3-21641.29" - process $proc$libresoc.v:21640$617 + attribute \src "libresoc.v:21732.3-21733.29" + process $proc$libresoc.v:21732$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end - attribute \src "libresoc.v:21642.3-21643.29" - process $proc$libresoc.v:21642$618 + attribute \src "libresoc.v:21734.3-21735.29" + process $proc$libresoc.v:21734$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:21644.3-21645.29" - process $proc$libresoc.v:21644$619 + attribute \src "libresoc.v:21736.3-21737.29" + process $proc$libresoc.v:21736$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:21646.3-21647.29" - process $proc$libresoc.v:21646$620 + attribute \src "libresoc.v:21738.3-21739.29" + process $proc$libresoc.v:21738$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:21648.3-21649.47" - process $proc$libresoc.v:21648$621 + attribute \src "libresoc.v:21740.3-21741.47" + process $proc$libresoc.v:21740$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21650.3-21651.53" - process $proc$libresoc.v:21650$622 + attribute \src "libresoc.v:21742.3-21743.53" + process $proc$libresoc.v:21742$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21652.3-21653.47" - process $proc$libresoc.v:21652$623 + attribute \src "libresoc.v:21744.3-21745.47" + process $proc$libresoc.v:21744$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21654.3-21655.53" - process $proc$libresoc.v:21654$624 + attribute \src "libresoc.v:21746.3-21747.53" + process $proc$libresoc.v:21746$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21656.3-21657.47" - process $proc$libresoc.v:21656$625 + attribute \src "libresoc.v:21748.3-21749.47" + process $proc$libresoc.v:21748$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21658.3-21659.53" - process $proc$libresoc.v:21658$626 + attribute \src "libresoc.v:21750.3-21751.53" + process $proc$libresoc.v:21750$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21660.3-21661.43" - process $proc$libresoc.v:21660$627 + attribute \src "libresoc.v:21752.3-21753.43" + process $proc$libresoc.v:21752$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21662.3-21663.49" - process $proc$libresoc.v:21662$628 + attribute \src "libresoc.v:21754.3-21755.49" + process $proc$libresoc.v:21754$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21664.3-21665.37" - process $proc$libresoc.v:21664$629 + attribute \src "libresoc.v:21756.3-21757.37" + process $proc$libresoc.v:21756$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:21666.3-21667.43" - process $proc$libresoc.v:21666$630 + attribute \src "libresoc.v:21758.3-21759.43" + process $proc$libresoc.v:21758$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21668.3-21669.69" - process $proc$libresoc.v:21668$631 + attribute \src "libresoc.v:21760.3-21761.69" + process $proc$libresoc.v:21760$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21670.3-21671.65" - process $proc$libresoc.v:21670$632 + attribute \src "libresoc.v:21762.3-21763.65" + process $proc$libresoc.v:21762$624 assign { } { } assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] end - attribute \src "libresoc.v:21672.3-21673.79" - process $proc$libresoc.v:21672$633 + attribute \src "libresoc.v:21764.3-21765.79" + process $proc$libresoc.v:21764$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21674.3-21675.75" - process $proc$libresoc.v:21674$634 + attribute \src "libresoc.v:21766.3-21767.75" + process $proc$libresoc.v:21766$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21676.3-21677.63" - process $proc$libresoc.v:21676$635 + attribute \src "libresoc.v:21768.3-21769.63" + process $proc$libresoc.v:21768$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21678.3-21679.63" - process $proc$libresoc.v:21678$636 + attribute \src "libresoc.v:21770.3-21771.63" + process $proc$libresoc.v:21770$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21680.3-21681.63" - process $proc$libresoc.v:21680$637 + attribute \src "libresoc.v:21772.3-21773.63" + process $proc$libresoc.v:21772$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21682.3-21683.63" - process $proc$libresoc.v:21682$638 + attribute \src "libresoc.v:21774.3-21775.63" + process $proc$libresoc.v:21774$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21684.3-21685.69" - process $proc$libresoc.v:21684$639 + attribute \src "libresoc.v:21776.3-21777.69" + process $proc$libresoc.v:21776$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21686.3-21687.63" - process $proc$libresoc.v:21686$640 + attribute \src "libresoc.v:21778.3-21779.63" + process $proc$libresoc.v:21778$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21688.3-21689.71" - process $proc$libresoc.v:21688$641 + attribute \src "libresoc.v:21780.3-21781.71" + process $proc$libresoc.v:21780$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21690.3-21691.69" - process $proc$libresoc.v:21690$642 + attribute \src "libresoc.v:21782.3-21783.69" + process $proc$libresoc.v:21782$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21692.3-21693.73" - process $proc$libresoc.v:21692$643 + attribute \src "libresoc.v:21784.3-21785.73" + process $proc$libresoc.v:21784$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21694.3-21695.75" - process $proc$libresoc.v:21694$644 + attribute \src "libresoc.v:21786.3-21787.75" + process $proc$libresoc.v:21786$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21696.3-21697.67" - process $proc$libresoc.v:21696$645 + attribute \src "libresoc.v:21788.3-21789.67" + process $proc$libresoc.v:21788$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21698.3-21699.69" - process $proc$libresoc.v:21698$646 + attribute \src "libresoc.v:21790.3-21791.69" + process $proc$libresoc.v:21790$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21700.3-21701.67" - process $proc$libresoc.v:21700$647 + attribute \src "libresoc.v:21792.3-21793.67" + process $proc$libresoc.v:21792$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21702.3-21703.59" - process $proc$libresoc.v:21702$648 + attribute \src "libresoc.v:21794.3-21795.59" + process $proc$libresoc.v:21794$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21704.3-21705.39" - process $proc$libresoc.v:21704$649 + attribute \src "libresoc.v:21796.3-21797.39" + process $proc$libresoc.v:21796$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:21706.3-21707.39" - process $proc$libresoc.v:21706$650 + attribute \src "libresoc.v:21798.3-21799.39" + process $proc$libresoc.v:21798$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:21708.3-21709.39" - process $proc$libresoc.v:21708$651 + attribute \src "libresoc.v:21800.3-21801.39" + process $proc$libresoc.v:21800$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:21710.3-21711.39" - process $proc$libresoc.v:21710$652 + attribute \src "libresoc.v:21802.3-21803.39" + process $proc$libresoc.v:21802$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:21712.3-21713.39" - process $proc$libresoc.v:21712$653 + attribute \src "libresoc.v:21804.3-21805.39" + process $proc$libresoc.v:21804$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21714.3-21715.39" - process $proc$libresoc.v:21714$654 + attribute \src "libresoc.v:21806.3-21807.39" + process $proc$libresoc.v:21806$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21716.3-21717.39" - process $proc$libresoc.v:21716$655 + attribute \src "libresoc.v:21808.3-21809.39" + process $proc$libresoc.v:21808$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21718.3-21719.39" - process $proc$libresoc.v:21718$656 + attribute \src "libresoc.v:21810.3-21811.39" + process $proc$libresoc.v:21810$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21720.3-21721.41" - process $proc$libresoc.v:21720$657 + attribute \src "libresoc.v:21812.3-21813.41" + process $proc$libresoc.v:21812$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21722.3-21723.41" - process $proc$libresoc.v:21722$658 + attribute \src "libresoc.v:21814.3-21815.41" + process $proc$libresoc.v:21814$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21724.3-21725.37" - process $proc$libresoc.v:21724$659 + attribute \src "libresoc.v:21816.3-21817.37" + process $proc$libresoc.v:21816$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:21726.3-21727.40" - process $proc$libresoc.v:21726$660 + attribute \src "libresoc.v:21818.3-21819.40" + process $proc$libresoc.v:21818$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:21728.3-21729.25" - process $proc$libresoc.v:21728$661 + attribute \src "libresoc.v:21820.3-21821.25" + process $proc$libresoc.v:21820$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:21818.3-21827.6" - process $proc$libresoc.v:21818$662 + attribute \src "libresoc.v:21910.3-21919.6" + process $proc$libresoc.v:21910$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:21819.5-21819.29" + attribute \src "libresoc.v:21911.5-21911.29" switch \initial - attribute \src "libresoc.v:21819.9-21819.17" + attribute \src "libresoc.v:21911.9-21911.17" case 1'1 case end @@ -33658,14 +33680,14 @@ module \alu0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:21828.3-21836.6" - process $proc$libresoc.v:21828$663 + attribute \src "libresoc.v:21920.3-21928.6" + process $proc$libresoc.v:21920$655 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$664 $1\rok_l_s_rdok$next[0:0]$665 - attribute \src "libresoc.v:21829.5-21829.29" + assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21921.5-21921.29" switch \initial - attribute \src "libresoc.v:21829.9-21829.17" + attribute \src "libresoc.v:21921.9-21921.17" case 1'1 case end @@ -33674,21 +33696,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$665 1'0 + assign $1\rok_l_s_rdok$next[0:0]$657 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$665 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$664 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end - attribute \src "libresoc.v:21837.3-21845.6" - process $proc$libresoc.v:21837$666 + attribute \src "libresoc.v:21929.3-21937.6" + process $proc$libresoc.v:21929$658 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$667 $1\rok_l_r_rdok$next[0:0]$668 - attribute \src "libresoc.v:21838.5-21838.29" + assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21930.5-21930.29" switch \initial - attribute \src "libresoc.v:21838.9-21838.17" + attribute \src "libresoc.v:21930.9-21930.17" case 1'1 case end @@ -33697,21 +33719,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$668 1'1 + assign $1\rok_l_r_rdok$next[0:0]$660 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$668 \$65 + assign $1\rok_l_r_rdok$next[0:0]$660 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$667 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end - attribute \src "libresoc.v:21846.3-21854.6" - process $proc$libresoc.v:21846$669 + attribute \src "libresoc.v:21938.3-21946.6" + process $proc$libresoc.v:21938$661 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$670 $1\rst_l_s_rst$next[0:0]$671 - attribute \src "libresoc.v:21847.5-21847.29" + assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21939.5-21939.29" switch \initial - attribute \src "libresoc.v:21847.9-21847.17" + attribute \src "libresoc.v:21939.9-21939.17" case 1'1 case end @@ -33720,21 +33742,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$671 1'0 + assign $1\rst_l_s_rst$next[0:0]$663 1'0 case - assign $1\rst_l_s_rst$next[0:0]$671 \all_rd + assign $1\rst_l_s_rst$next[0:0]$663 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$670 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end - attribute \src "libresoc.v:21855.3-21863.6" - process $proc$libresoc.v:21855$672 + attribute \src "libresoc.v:21947.3-21955.6" + process $proc$libresoc.v:21947$664 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$673 $1\rst_l_r_rst$next[0:0]$674 - attribute \src "libresoc.v:21856.5-21856.29" + assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21948.5-21948.29" switch \initial - attribute \src "libresoc.v:21856.9-21856.17" + attribute \src "libresoc.v:21948.9-21948.17" case 1'1 case end @@ -33743,21 +33765,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$674 1'1 + assign $1\rst_l_r_rst$next[0:0]$666 1'1 case - assign $1\rst_l_r_rst$next[0:0]$674 \rst_r + assign $1\rst_l_r_rst$next[0:0]$666 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$673 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end - attribute \src "libresoc.v:21864.3-21872.6" - process $proc$libresoc.v:21864$675 + attribute \src "libresoc.v:21956.3-21964.6" + process $proc$libresoc.v:21956$667 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$676 $1\opc_l_s_opc$next[0:0]$677 - attribute \src "libresoc.v:21865.5-21865.29" + assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21957.5-21957.29" switch \initial - attribute \src "libresoc.v:21865.9-21865.17" + attribute \src "libresoc.v:21957.9-21957.17" case 1'1 case end @@ -33766,21 +33788,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$677 1'0 + assign $1\opc_l_s_opc$next[0:0]$669 1'0 case - assign $1\opc_l_s_opc$next[0:0]$677 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$676 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end - attribute \src "libresoc.v:21873.3-21881.6" - process $proc$libresoc.v:21873$678 + attribute \src "libresoc.v:21965.3-21973.6" + process $proc$libresoc.v:21965$670 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$679 $1\opc_l_r_opc$next[0:0]$680 - attribute \src "libresoc.v:21874.5-21874.29" + assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21966.5-21966.29" switch \initial - attribute \src "libresoc.v:21874.9-21874.17" + attribute \src "libresoc.v:21966.9-21966.17" case 1'1 case end @@ -33789,21 +33811,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$680 1'1 + assign $1\opc_l_r_opc$next[0:0]$672 1'1 case - assign $1\opc_l_r_opc$next[0:0]$680 \req_done + assign $1\opc_l_r_opc$next[0:0]$672 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$679 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end - attribute \src "libresoc.v:21882.3-21890.6" - process $proc$libresoc.v:21882$681 + attribute \src "libresoc.v:21974.3-21982.6" + process $proc$libresoc.v:21974$673 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$682 $1\src_l_s_src$next[3:0]$683 - attribute \src "libresoc.v:21883.5-21883.29" + assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21975.5-21975.29" switch \initial - attribute \src "libresoc.v:21883.9-21883.17" + attribute \src "libresoc.v:21975.9-21975.17" case 1'1 case end @@ -33812,21 +33834,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$683 4'0000 + assign $1\src_l_s_src$next[3:0]$675 4'0000 case - assign $1\src_l_s_src$next[3:0]$683 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$682 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end - attribute \src "libresoc.v:21891.3-21899.6" - process $proc$libresoc.v:21891$684 + attribute \src "libresoc.v:21983.3-21991.6" + process $proc$libresoc.v:21983$676 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$685 $1\src_l_r_src$next[3:0]$686 - attribute \src "libresoc.v:21892.5-21892.29" + assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21984.5-21984.29" switch \initial - attribute \src "libresoc.v:21892.9-21892.17" + attribute \src "libresoc.v:21984.9-21984.17" case 1'1 case end @@ -33835,21 +33857,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$686 4'1111 + assign $1\src_l_r_src$next[3:0]$678 4'1111 case - assign $1\src_l_r_src$next[3:0]$686 \reset_r + assign $1\src_l_r_src$next[3:0]$678 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$685 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end - attribute \src "libresoc.v:21900.3-21908.6" - process $proc$libresoc.v:21900$687 + attribute \src "libresoc.v:21992.3-22000.6" + process $proc$libresoc.v:21992$679 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$688 $1\req_l_s_req$next[4:0]$689 - attribute \src "libresoc.v:21901.5-21901.29" + assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21993.5-21993.29" switch \initial - attribute \src "libresoc.v:21901.9-21901.17" + attribute \src "libresoc.v:21993.9-21993.17" case 1'1 case end @@ -33858,21 +33880,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$689 5'00000 + assign $1\req_l_s_req$next[4:0]$681 5'00000 case - assign $1\req_l_s_req$next[4:0]$689 \$67 + assign $1\req_l_s_req$next[4:0]$681 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$688 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end - attribute \src "libresoc.v:21909.3-21917.6" - process $proc$libresoc.v:21909$690 + attribute \src "libresoc.v:22001.3-22009.6" + process $proc$libresoc.v:22001$682 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$691 $1\req_l_r_req$next[4:0]$692 - attribute \src "libresoc.v:21910.5-21910.29" + assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:22002.5-22002.29" switch \initial - attribute \src "libresoc.v:21910.9-21910.17" + attribute \src "libresoc.v:22002.9-22002.17" case 1'1 case end @@ -33881,15 +33903,15 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$692 5'11111 + assign $1\req_l_r_req$next[4:0]$684 5'11111 case - assign $1\req_l_r_req$next[4:0]$692 \$69 + assign $1\req_l_r_req$next[4:0]$684 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$691 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end - attribute \src "libresoc.v:21918.3-21956.6" - process $proc$libresoc.v:21918$693 + attribute \src "libresoc.v:22010.3-22048.6" + process $proc$libresoc.v:22010$685 assign { } { } assign { } { } assign { } { } @@ -33926,33 +33948,33 @@ module \alu0 assign { } { } assign { } { } assign { } { } - assign $0\alu_alu0_alu_op__data_len$next[3:0]$694 $1\alu_alu0_alu_op__data_len$next[3:0]$712 - assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 + assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 assign { } { } assign { } { } - assign $0\alu_alu0_alu_op__input_carry$next[1:0]$698 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 - assign $0\alu_alu0_alu_op__insn$next[31:0]$699 $1\alu_alu0_alu_op__insn$next[31:0]$717 - assign $0\alu_alu0_alu_op__insn_type$next[6:0]$700 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 - assign $0\alu_alu0_alu_op__invert_in$next[0:0]$701 $1\alu_alu0_alu_op__invert_in$next[0:0]$719 - assign $0\alu_alu0_alu_op__invert_out$next[0:0]$702 $1\alu_alu0_alu_op__invert_out$next[0:0]$720 - assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 - assign $0\alu_alu0_alu_op__is_signed$next[0:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$722 + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 assign { } { } assign { } { } - assign $0\alu_alu0_alu_op__output_carry$next[0:0]$707 $1\alu_alu0_alu_op__output_carry$next[0:0]$725 + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 assign { } { } assign { } { } - assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 - assign $0\alu_alu0_alu_op__zero_a$next[0:0]$711 $1\alu_alu0_alu_op__zero_a$next[0:0]$729 - assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 - assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 - assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 - assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 - assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 - assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 - attribute \src "libresoc.v:21919.5-21919.29" + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22011.5-22011.29" switch \initial - attribute \src "libresoc.v:21919.9-21919.17" + attribute \src "libresoc.v:22011.9-22011.17" case 1'1 case end @@ -33978,26 +34000,26 @@ module \alu0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_alu0_alu_op__insn$next[31:0]$717 $1\alu_alu0_alu_op__data_len$next[3:0]$712 $1\alu_alu0_alu_op__is_signed$next[0:0]$722 $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 $1\alu_alu0_alu_op__output_carry$next[0:0]$725 $1\alu_alu0_alu_op__input_carry$next[1:0]$716 $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 $1\alu_alu0_alu_op__invert_out$next[0:0]$720 $1\alu_alu0_alu_op__zero_a$next[0:0]$729 $1\alu_alu0_alu_op__invert_in$next[0:0]$719 $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 $1\alu_alu0_alu_op__insn_type$next[6:0]$718 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } case - assign $1\alu_alu0_alu_op__data_len$next[3:0]$712 \alu_alu0_alu_op__data_len - assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$713 \alu_alu0_alu_op__fn_unit - assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 \alu_alu0_alu_op__imm_data__data - assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 \alu_alu0_alu_op__imm_data__ok - assign $1\alu_alu0_alu_op__input_carry$next[1:0]$716 \alu_alu0_alu_op__input_carry - assign $1\alu_alu0_alu_op__insn$next[31:0]$717 \alu_alu0_alu_op__insn - assign $1\alu_alu0_alu_op__insn_type$next[6:0]$718 \alu_alu0_alu_op__insn_type - assign $1\alu_alu0_alu_op__invert_in$next[0:0]$719 \alu_alu0_alu_op__invert_in - assign $1\alu_alu0_alu_op__invert_out$next[0:0]$720 \alu_alu0_alu_op__invert_out - assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$721 \alu_alu0_alu_op__is_32bit - assign $1\alu_alu0_alu_op__is_signed$next[0:0]$722 \alu_alu0_alu_op__is_signed - assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 \alu_alu0_alu_op__oe__oe - assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 \alu_alu0_alu_op__oe__ok - assign $1\alu_alu0_alu_op__output_carry$next[0:0]$725 \alu_alu0_alu_op__output_carry - assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 \alu_alu0_alu_op__rc__ok - assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 \alu_alu0_alu_op__rc__rc - assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$728 \alu_alu0_alu_op__write_cr0 - assign $1\alu_alu0_alu_op__zero_a$next[0:0]$729 \alu_alu0_alu_op__zero_a + assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -34009,54 +34031,54 @@ module \alu0 assign { } { } assign { } { } assign { } { } - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 1'0 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 1'0 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 1'0 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 1'0 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 1'0 + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 case - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$730 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$714 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$731 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$715 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$732 $1\alu_alu0_alu_op__oe__oe$next[0:0]$723 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$733 $1\alu_alu0_alu_op__oe__ok$next[0:0]$724 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$734 $1\alu_alu0_alu_op__rc__ok$next[0:0]$726 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$735 $1\alu_alu0_alu_op__rc__rc$next[0:0]$727 + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 end sync always - update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$694 - update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$695 - update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$696 - update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$697 - update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$698 - update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$699 - update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$700 - update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$701 - update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$702 - update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$703 - update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$704 - update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$705 - update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$706 - update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$707 - update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$708 - update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$709 - update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$710 - update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$711 + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end - attribute \src "libresoc.v:21957.3-21978.6" - process $proc$libresoc.v:21957$736 + attribute \src "libresoc.v:22049.3-22070.6" + process $proc$libresoc.v:22049$728 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$737 $2\data_r0__o$next[63:0]$741 + assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$738 $3\data_r0__o_ok$next[0:0]$743 - attribute \src "libresoc.v:21958.5-21958.29" + assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22050.5-22050.29" switch \initial - attribute \src "libresoc.v:21958.9-21958.17" + attribute \src "libresoc.v:22050.9-22050.17" case 1'1 case end @@ -34066,10 +34088,10 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$740 $1\data_r0__o$next[63:0]$739 } { \o_ok \alu_alu0_o } + assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } case - assign $1\data_r0__o$next[63:0]$739 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$740 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$731 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -34077,38 +34099,38 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$742 $2\data_r0__o$next[63:0]$741 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$741 $1\data_r0__o$next[63:0]$739 - assign $2\data_r0__o_ok$next[0:0]$742 $1\data_r0__o_ok$next[0:0]$740 + assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 + assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$743 1'0 + assign $3\data_r0__o_ok$next[0:0]$735 1'0 case - assign $3\data_r0__o_ok$next[0:0]$743 $2\data_r0__o_ok$next[0:0]$742 + assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$737 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$738 + update \data_r0__o$next $0\data_r0__o$next[63:0]$729 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end - attribute \src "libresoc.v:21979.3-22000.6" - process $proc$libresoc.v:21979$744 + attribute \src "libresoc.v:22071.3-22092.6" + process $proc$libresoc.v:22071$736 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$745 $2\data_r1__cr_a$next[3:0]$749 + assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$746 $3\data_r1__cr_a_ok$next[0:0]$751 - attribute \src "libresoc.v:21980.5-21980.29" + assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22072.5-22072.29" switch \initial - attribute \src "libresoc.v:21980.9-21980.17" + attribute \src "libresoc.v:22072.9-22072.17" case 1'1 case end @@ -34118,10 +34140,10 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$748 $1\data_r1__cr_a$next[3:0]$747 } { \cr_a_ok \alu_alu0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$747 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$748 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -34129,38 +34151,38 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$750 $2\data_r1__cr_a$next[3:0]$749 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$749 $1\data_r1__cr_a$next[3:0]$747 - assign $2\data_r1__cr_a_ok$next[0:0]$750 $1\data_r1__cr_a_ok$next[0:0]$748 + assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 + assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$751 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$751 $2\data_r1__cr_a_ok$next[0:0]$750 + assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$745 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$746 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end - attribute \src "libresoc.v:22001.3-22022.6" - process $proc$libresoc.v:22001$752 + attribute \src "libresoc.v:22093.3-22114.6" + process $proc$libresoc.v:22093$744 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$753 $2\data_r2__xer_ca$next[1:0]$757 + assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$754 $3\data_r2__xer_ca_ok$next[0:0]$759 - attribute \src "libresoc.v:22002.5-22002.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22094.5-22094.29" switch \initial - attribute \src "libresoc.v:22002.9-22002.17" + attribute \src "libresoc.v:22094.9-22094.17" case 1'1 case end @@ -34170,10 +34192,10 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$756 $1\data_r2__xer_ca$next[1:0]$755 } { \xer_ca_ok \alu_alu0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$755 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$756 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -34181,38 +34203,38 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$758 $2\data_r2__xer_ca$next[1:0]$757 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$757 $1\data_r2__xer_ca$next[1:0]$755 - assign $2\data_r2__xer_ca_ok$next[0:0]$758 $1\data_r2__xer_ca_ok$next[0:0]$756 + assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 + assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$759 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$759 $2\data_r2__xer_ca_ok$next[0:0]$758 + assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$753 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$754 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end - attribute \src "libresoc.v:22023.3-22044.6" - process $proc$libresoc.v:22023$760 + attribute \src "libresoc.v:22115.3-22136.6" + process $proc$libresoc.v:22115$752 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_ov$next[1:0]$761 $2\data_r3__xer_ov$next[1:0]$765 + assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } - assign $0\data_r3__xer_ov_ok$next[0:0]$762 $3\data_r3__xer_ov_ok$next[0:0]$767 - attribute \src "libresoc.v:22024.5-22024.29" + assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22116.5-22116.29" switch \initial - attribute \src "libresoc.v:22024.9-22024.17" + attribute \src "libresoc.v:22116.9-22116.17" case 1'1 case end @@ -34222,10 +34244,10 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_ov_ok$next[0:0]$764 $1\data_r3__xer_ov$next[1:0]$763 } { \xer_ov_ok \alu_alu0_xer_ov } + assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } case - assign $1\data_r3__xer_ov$next[1:0]$763 \data_r3__xer_ov - assign $1\data_r3__xer_ov_ok$next[0:0]$764 \data_r3__xer_ov_ok + assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -34233,38 +34255,38 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_ov_ok$next[0:0]$766 $2\data_r3__xer_ov$next[1:0]$765 } 3'000 + assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 case - assign $2\data_r3__xer_ov$next[1:0]$765 $1\data_r3__xer_ov$next[1:0]$763 - assign $2\data_r3__xer_ov_ok$next[0:0]$766 $1\data_r3__xer_ov_ok$next[0:0]$764 + assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 + assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_ov_ok$next[0:0]$767 1'0 + assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 case - assign $3\data_r3__xer_ov_ok$next[0:0]$767 $2\data_r3__xer_ov_ok$next[0:0]$766 + assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 end sync always - update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$761 - update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$762 + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end - attribute \src "libresoc.v:22045.3-22066.6" - process $proc$libresoc.v:22045$768 + attribute \src "libresoc.v:22137.3-22158.6" + process $proc$libresoc.v:22137$760 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_so$next[0:0]$769 $2\data_r4__xer_so$next[0:0]$773 + assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } - assign $0\data_r4__xer_so_ok$next[0:0]$770 $3\data_r4__xer_so_ok$next[0:0]$775 - attribute \src "libresoc.v:22046.5-22046.29" + assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:22138.5-22138.29" switch \initial - attribute \src "libresoc.v:22046.9-22046.17" + attribute \src "libresoc.v:22138.9-22138.17" case 1'1 case end @@ -34274,10 +34296,10 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_so_ok$next[0:0]$772 $1\data_r4__xer_so$next[0:0]$771 } { \xer_so_ok \alu_alu0_xer_so } + assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } case - assign $1\data_r4__xer_so$next[0:0]$771 \data_r4__xer_so - assign $1\data_r4__xer_so_ok$next[0:0]$772 \data_r4__xer_so_ok + assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -34285,32 +34307,32 @@ module \alu0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_so_ok$next[0:0]$774 $2\data_r4__xer_so$next[0:0]$773 } 2'00 + assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 case - assign $2\data_r4__xer_so$next[0:0]$773 $1\data_r4__xer_so$next[0:0]$771 - assign $2\data_r4__xer_so_ok$next[0:0]$774 $1\data_r4__xer_so_ok$next[0:0]$772 + assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 + assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_so_ok$next[0:0]$775 1'0 + assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 case - assign $3\data_r4__xer_so_ok$next[0:0]$775 $2\data_r4__xer_so_ok$next[0:0]$774 + assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 end sync always - update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$769 - update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$770 + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end - attribute \src "libresoc.v:22067.3-22076.6" - process $proc$libresoc.v:22067$776 + attribute \src "libresoc.v:22159.3-22168.6" + process $proc$libresoc.v:22159$768 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$777 $1\src_r0$next[63:0]$778 - attribute \src "libresoc.v:22068.5-22068.29" + assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:22160.5-22160.29" switch \initial - attribute \src "libresoc.v:22068.9-22068.17" + attribute \src "libresoc.v:22160.9-22160.17" case 1'1 case end @@ -34319,21 +34341,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$778 \src_or_imm + assign $1\src_r0$next[63:0]$770 \src_or_imm case - assign $1\src_r0$next[63:0]$778 \src_r0 + assign $1\src_r0$next[63:0]$770 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$777 + update \src_r0$next $0\src_r0$next[63:0]$769 end - attribute \src "libresoc.v:22077.3-22086.6" - process $proc$libresoc.v:22077$779 + attribute \src "libresoc.v:22169.3-22178.6" + process $proc$libresoc.v:22169$771 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$780 $1\src_r1$next[63:0]$781 - attribute \src "libresoc.v:22078.5-22078.29" + assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:22170.5-22170.29" switch \initial - attribute \src "libresoc.v:22078.9-22078.17" + attribute \src "libresoc.v:22170.9-22170.17" case 1'1 case end @@ -34342,21 +34364,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$781 \src_or_imm$88 + assign $1\src_r1$next[63:0]$773 \src_or_imm$88 case - assign $1\src_r1$next[63:0]$781 \src_r1 + assign $1\src_r1$next[63:0]$773 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$780 + update \src_r1$next $0\src_r1$next[63:0]$772 end - attribute \src "libresoc.v:22087.3-22096.6" - process $proc$libresoc.v:22087$782 + attribute \src "libresoc.v:22179.3-22188.6" + process $proc$libresoc.v:22179$774 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$783 $1\src_r2$next[0:0]$784 - attribute \src "libresoc.v:22088.5-22088.29" + assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:22180.5-22180.29" switch \initial - attribute \src "libresoc.v:22088.9-22088.17" + attribute \src "libresoc.v:22180.9-22180.17" case 1'1 case end @@ -34365,21 +34387,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$784 \src3_i + assign $1\src_r2$next[0:0]$776 \src3_i case - assign $1\src_r2$next[0:0]$784 \src_r2 + assign $1\src_r2$next[0:0]$776 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$783 + update \src_r2$next $0\src_r2$next[0:0]$775 end - attribute \src "libresoc.v:22097.3-22106.6" - process $proc$libresoc.v:22097$785 + attribute \src "libresoc.v:22189.3-22198.6" + process $proc$libresoc.v:22189$777 assign { } { } assign { } { } - assign $0\src_r3$next[1:0]$786 $1\src_r3$next[1:0]$787 - attribute \src "libresoc.v:22098.5-22098.29" + assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:22190.5-22190.29" switch \initial - attribute \src "libresoc.v:22098.9-22098.17" + attribute \src "libresoc.v:22190.9-22190.17" case 1'1 case end @@ -34388,21 +34410,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[1:0]$787 \src4_i + assign $1\src_r3$next[1:0]$779 \src4_i case - assign $1\src_r3$next[1:0]$787 \src_r3 + assign $1\src_r3$next[1:0]$779 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[1:0]$786 + update \src_r3$next $0\src_r3$next[1:0]$778 end - attribute \src "libresoc.v:22107.3-22115.6" - process $proc$libresoc.v:22107$788 + attribute \src "libresoc.v:22199.3-22207.6" + process $proc$libresoc.v:22199$780 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$789 $1\alui_l_r_alui$next[0:0]$790 - attribute \src "libresoc.v:22108.5-22108.29" + assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:22200.5-22200.29" switch \initial - attribute \src "libresoc.v:22108.9-22108.17" + attribute \src "libresoc.v:22200.9-22200.17" case 1'1 case end @@ -34411,21 +34433,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$790 1'1 + assign $1\alui_l_r_alui$next[0:0]$782 1'1 case - assign $1\alui_l_r_alui$next[0:0]$790 \$99 + assign $1\alui_l_r_alui$next[0:0]$782 \$99 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$789 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end - attribute \src "libresoc.v:22116.3-22124.6" - process $proc$libresoc.v:22116$791 + attribute \src "libresoc.v:22208.3-22216.6" + process $proc$libresoc.v:22208$783 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$792 $1\alu_l_r_alu$next[0:0]$793 - attribute \src "libresoc.v:22117.5-22117.29" + assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:22209.5-22209.29" switch \initial - attribute \src "libresoc.v:22117.9-22117.17" + attribute \src "libresoc.v:22209.9-22209.17" case 1'1 case end @@ -34434,21 +34456,21 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$793 1'1 + assign $1\alu_l_r_alu$next[0:0]$785 1'1 case - assign $1\alu_l_r_alu$next[0:0]$793 \$101 + assign $1\alu_l_r_alu$next[0:0]$785 \$101 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$792 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end - attribute \src "libresoc.v:22125.3-22134.6" - process $proc$libresoc.v:22125$794 + attribute \src "libresoc.v:22217.3-22226.6" + process $proc$libresoc.v:22217$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:22126.5-22126.29" + attribute \src "libresoc.v:22218.5-22218.29" switch \initial - attribute \src "libresoc.v:22126.9-22126.17" + attribute \src "libresoc.v:22218.9-22218.17" case 1'1 case end @@ -34464,14 +34486,14 @@ module \alu0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:22135.3-22144.6" - process $proc$libresoc.v:22135$795 + attribute \src "libresoc.v:22227.3-22236.6" + process $proc$libresoc.v:22227$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:22136.5-22136.29" + attribute \src "libresoc.v:22228.5-22228.29" switch \initial - attribute \src "libresoc.v:22136.9-22136.17" + attribute \src "libresoc.v:22228.9-22228.17" case 1'1 case end @@ -34487,14 +34509,14 @@ module \alu0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:22145.3-22154.6" - process $proc$libresoc.v:22145$796 + attribute \src "libresoc.v:22237.3-22246.6" + process $proc$libresoc.v:22237$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:22146.5-22146.29" + attribute \src "libresoc.v:22238.5-22238.29" switch \initial - attribute \src "libresoc.v:22146.9-22146.17" + attribute \src "libresoc.v:22238.9-22238.17" case 1'1 case end @@ -34510,14 +34532,14 @@ module \alu0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:22155.3-22164.6" - process $proc$libresoc.v:22155$797 + attribute \src "libresoc.v:22247.3-22256.6" + process $proc$libresoc.v:22247$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "libresoc.v:22156.5-22156.29" + attribute \src "libresoc.v:22248.5-22248.29" switch \initial - attribute \src "libresoc.v:22156.9-22156.17" + attribute \src "libresoc.v:22248.9-22248.17" case 1'1 case end @@ -34533,14 +34555,14 @@ module \alu0 sync always update \dest4_o $0\dest4_o[1:0] end - attribute \src "libresoc.v:22165.3-22174.6" - process $proc$libresoc.v:22165$798 + attribute \src "libresoc.v:22257.3-22266.6" + process $proc$libresoc.v:22257$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "libresoc.v:22166.5-22166.29" + attribute \src "libresoc.v:22258.5-22258.29" switch \initial - attribute \src "libresoc.v:22166.9-22166.17" + attribute \src "libresoc.v:22258.9-22258.17" case 1'1 case end @@ -34556,14 +34578,14 @@ module \alu0 sync always update \dest5_o $0\dest5_o[0:0] end - attribute \src "libresoc.v:22175.3-22183.6" - process $proc$libresoc.v:22175$799 + attribute \src "libresoc.v:22267.3-22275.6" + process $proc$libresoc.v:22267$791 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$800 $1\prev_wr_go$next[4:0]$801 - attribute \src "libresoc.v:22176.5-22176.29" + assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:22268.5-22268.29" switch \initial - attribute \src "libresoc.v:22176.9-22176.17" + attribute \src "libresoc.v:22268.9-22268.17" case 1'1 case end @@ -34572,80 +34594,80 @@ module \alu0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$801 5'00000 - case - assign $1\prev_wr_go$next[4:0]$801 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$800 - end - connect \$5 $reduce_and$libresoc.v:21569$548_Y - connect \$99 $and$libresoc.v:21570$549_Y - connect \$101 $and$libresoc.v:21571$550_Y - connect \$103 $and$libresoc.v:21572$551_Y - connect \$105 $not$libresoc.v:21573$552_Y - connect \$107 $not$libresoc.v:21574$553_Y - connect \$109 $and$libresoc.v:21575$554_Y - connect \$111 $not$libresoc.v:21576$555_Y - connect \$113 $and$libresoc.v:21577$556_Y - connect \$115 $and$libresoc.v:21578$557_Y - connect \$117 $and$libresoc.v:21579$558_Y - connect \$11 $and$libresoc.v:21580$559_Y - connect \$119 $and$libresoc.v:21581$560_Y - connect \$121 $and$libresoc.v:21582$561_Y - connect \$123 $and$libresoc.v:21583$562_Y - connect \$125 $and$libresoc.v:21584$563_Y - connect \$127 $and$libresoc.v:21585$564_Y - connect \$129 $and$libresoc.v:21586$565_Y - connect \$131 $and$libresoc.v:21587$566_Y - connect \$133 $and$libresoc.v:21588$567_Y - connect \$135 $and$libresoc.v:21589$568_Y - connect \$137 $and$libresoc.v:21590$569_Y - connect \$13 $not$libresoc.v:21591$570_Y - connect \$15 $and$libresoc.v:21592$571_Y - connect \$17 $not$libresoc.v:21593$572_Y - connect \$19 $and$libresoc.v:21594$573_Y - connect \$21 $and$libresoc.v:21595$574_Y - connect \$25 $not$libresoc.v:21596$575_Y - connect \$27 $and$libresoc.v:21597$576_Y - connect \$24 $reduce_or$libresoc.v:21598$577_Y - connect \$23 $not$libresoc.v:21599$578_Y - connect \$31 $and$libresoc.v:21600$579_Y - connect \$33 $reduce_or$libresoc.v:21601$580_Y - connect \$35 $reduce_or$libresoc.v:21602$581_Y - connect \$37 $or$libresoc.v:21603$582_Y - connect \$3 $and$libresoc.v:21604$583_Y - connect \$39 $not$libresoc.v:21605$584_Y - connect \$41 $and$libresoc.v:21606$585_Y - connect \$43 $and$libresoc.v:21607$586_Y - connect \$45 $eq$libresoc.v:21608$587_Y - connect \$47 $and$libresoc.v:21609$588_Y - connect \$49 $eq$libresoc.v:21610$589_Y - connect \$51 $and$libresoc.v:21611$590_Y - connect \$53 $and$libresoc.v:21612$591_Y - connect \$55 $and$libresoc.v:21613$592_Y - connect \$57 $or$libresoc.v:21614$593_Y - connect \$59 $or$libresoc.v:21615$594_Y - connect \$61 $or$libresoc.v:21616$595_Y - connect \$63 $or$libresoc.v:21617$596_Y - connect \$65 $and$libresoc.v:21618$597_Y - connect \$67 $and$libresoc.v:21619$598_Y - connect \$6 $not$libresoc.v:21620$599_Y - connect \$69 $or$libresoc.v:21621$600_Y - connect \$71 $and$libresoc.v:21622$601_Y - connect \$73 $and$libresoc.v:21623$602_Y - connect \$75 $and$libresoc.v:21624$603_Y - connect \$77 $and$libresoc.v:21625$604_Y - connect \$79 $and$libresoc.v:21626$605_Y - connect \$81 $ternary$libresoc.v:21627$606_Y - connect \$83 $ternary$libresoc.v:21628$607_Y - connect \$86 $ternary$libresoc.v:21629$608_Y - connect \$8 $or$libresoc.v:21630$609_Y - connect \$89 $ternary$libresoc.v:21631$610_Y - connect \$91 $ternary$libresoc.v:21632$611_Y - connect \$93 $ternary$libresoc.v:21633$612_Y - connect \$95 $ternary$libresoc.v:21634$613_Y - connect \$97 $ternary$libresoc.v:21635$614_Y + assign $1\prev_wr_go$next[4:0]$793 5'00000 + case + assign $1\prev_wr_go$next[4:0]$793 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 + end + connect \$5 $reduce_and$libresoc.v:21661$540_Y + connect \$99 $and$libresoc.v:21662$541_Y + connect \$101 $and$libresoc.v:21663$542_Y + connect \$103 $and$libresoc.v:21664$543_Y + connect \$105 $not$libresoc.v:21665$544_Y + connect \$107 $not$libresoc.v:21666$545_Y + connect \$109 $and$libresoc.v:21667$546_Y + connect \$111 $not$libresoc.v:21668$547_Y + connect \$113 $and$libresoc.v:21669$548_Y + connect \$115 $and$libresoc.v:21670$549_Y + connect \$117 $and$libresoc.v:21671$550_Y + connect \$11 $and$libresoc.v:21672$551_Y + connect \$119 $and$libresoc.v:21673$552_Y + connect \$121 $and$libresoc.v:21674$553_Y + connect \$123 $and$libresoc.v:21675$554_Y + connect \$125 $and$libresoc.v:21676$555_Y + connect \$127 $and$libresoc.v:21677$556_Y + connect \$129 $and$libresoc.v:21678$557_Y + connect \$131 $and$libresoc.v:21679$558_Y + connect \$133 $and$libresoc.v:21680$559_Y + connect \$135 $and$libresoc.v:21681$560_Y + connect \$137 $and$libresoc.v:21682$561_Y + connect \$13 $not$libresoc.v:21683$562_Y + connect \$15 $and$libresoc.v:21684$563_Y + connect \$17 $not$libresoc.v:21685$564_Y + connect \$19 $and$libresoc.v:21686$565_Y + connect \$21 $and$libresoc.v:21687$566_Y + connect \$25 $not$libresoc.v:21688$567_Y + connect \$27 $and$libresoc.v:21689$568_Y + connect \$24 $reduce_or$libresoc.v:21690$569_Y + connect \$23 $not$libresoc.v:21691$570_Y + connect \$31 $and$libresoc.v:21692$571_Y + connect \$33 $reduce_or$libresoc.v:21693$572_Y + connect \$35 $reduce_or$libresoc.v:21694$573_Y + connect \$37 $or$libresoc.v:21695$574_Y + connect \$3 $and$libresoc.v:21696$575_Y + connect \$39 $not$libresoc.v:21697$576_Y + connect \$41 $and$libresoc.v:21698$577_Y + connect \$43 $and$libresoc.v:21699$578_Y + connect \$45 $eq$libresoc.v:21700$579_Y + connect \$47 $and$libresoc.v:21701$580_Y + connect \$49 $eq$libresoc.v:21702$581_Y + connect \$51 $and$libresoc.v:21703$582_Y + connect \$53 $and$libresoc.v:21704$583_Y + connect \$55 $and$libresoc.v:21705$584_Y + connect \$57 $or$libresoc.v:21706$585_Y + connect \$59 $or$libresoc.v:21707$586_Y + connect \$61 $or$libresoc.v:21708$587_Y + connect \$63 $or$libresoc.v:21709$588_Y + connect \$65 $and$libresoc.v:21710$589_Y + connect \$67 $and$libresoc.v:21711$590_Y + connect \$6 $not$libresoc.v:21712$591_Y + connect \$69 $or$libresoc.v:21713$592_Y + connect \$71 $and$libresoc.v:21714$593_Y + connect \$73 $and$libresoc.v:21715$594_Y + connect \$75 $and$libresoc.v:21716$595_Y + connect \$77 $and$libresoc.v:21717$596_Y + connect \$79 $and$libresoc.v:21718$597_Y + connect \$81 $ternary$libresoc.v:21719$598_Y + connect \$83 $ternary$libresoc.v:21720$599_Y + connect \$86 $ternary$libresoc.v:21721$600_Y + connect \$8 $or$libresoc.v:21722$601_Y + connect \$89 $ternary$libresoc.v:21723$602_Y + connect \$91 $ternary$libresoc.v:21724$603_Y + connect \$93 $ternary$libresoc.v:21725$604_Y + connect \$95 $ternary$libresoc.v:21726$605_Y + connect \$97 $ternary$libresoc.v:21727$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 @@ -34680,9 +34702,9 @@ module \alu0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:22221.1-23281.10" +attribute \src "libresoc.v:22313.1-23373.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -34939,14 +34961,14 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" @@ -34955,10 +34977,10 @@ module \alu_alu0 wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 27 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 37 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" @@ -35217,9 +35239,9 @@ module \alu_alu0 wire \pipe1_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_alu_op__zero_a$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe1_muxid @@ -35229,9 +35251,9 @@ module \alu_alu0 wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe1_p_ready_o @@ -35241,21 +35263,21 @@ module \alu_alu0 wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe1_xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe1_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe1_xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \pipe2_alu_op__data_len @@ -35511,13 +35533,13 @@ module \alu_alu0 wire \pipe2_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_alu_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe2_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe2_muxid @@ -35527,76 +35549,76 @@ module \alu_alu0 wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ca$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_ca_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ov$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_ov_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so_ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 32 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 33 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 29 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 30 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 31 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 34 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:23120.5-23123.4" + attribute \src "libresoc.v:23212.5-23215.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23124.5-23127.4" + attribute \src "libresoc.v:23216.5-23219.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23128.9-23187.4" + attribute \src "libresoc.v:23220.9-23279.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 @@ -35658,7 +35680,7 @@ module \alu_alu0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:23188.9-23253.4" + attribute \src "libresoc.v:23280.9-23345.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 @@ -35753,9 +35775,9 @@ module \alu_alu0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:23285.1-23820.10" +attribute \src "libresoc.v:23377.1-23912.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -35964,24 +35986,24 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 15 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 18 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" @@ -35990,10 +36012,10 @@ module \alu_branch0 wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 17 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 22 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" @@ -36208,15 +36230,15 @@ module \alu_branch0 wire width 4 \pipe_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe_muxid @@ -36226,28 +36248,28 @@ module \alu_branch0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire \pipe_p_valid_i attribute \module_not_derived 1 - attribute \src "libresoc.v:23762.10-23765.4" + attribute \src "libresoc.v:23854.10-23857.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23766.10-23769.4" + attribute \src "libresoc.v:23858.10-23861.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23770.13-23804.4" + attribute \src "libresoc.v:23862.13-23896.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 @@ -36299,21 +36321,21 @@ module \alu_branch0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:23824.1-24327.10" +attribute \src "libresoc.v:23916.1-24419.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 16 \cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 17 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" @@ -36504,12 +36526,12 @@ module \alu_cr0 attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \cr_op__insn_type$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 output 11 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 15 \full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" @@ -36518,19 +36540,19 @@ module \alu_cr0 wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 20 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire input 19 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe_cr_a$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \pipe_cr_b @@ -36724,9 +36746,9 @@ module \alu_cr0 wire width 7 \pipe_cr_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \pipe_full_cr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe_muxid @@ -36736,9 +36758,9 @@ module \alu_cr0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe_p_ready_o @@ -36753,19 +36775,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 - attribute \src "libresoc.v:24273.9-24276.4" + attribute \src "libresoc.v:24365.9-24368.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24277.9-24280.4" + attribute \src "libresoc.v:24369.9-24372.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24281.8-24308.4" + attribute \src "libresoc.v:24373.8-24400.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -36813,19 +36835,19 @@ module \alu_cr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24331.1-25772.10" +attribute \src "libresoc.v:24423.1-25864.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 24 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -37088,17 +37110,17 @@ module \alu_div0 wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 26 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 34 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_end_div_by_zero @@ -37372,9 +37394,9 @@ module \alu_div0 wire \pipe_end_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe_end_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_end_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe_end_p_ready_o @@ -37388,15 +37410,15 @@ module \alu_div0 wire width 64 \pipe_end_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \pipe_end_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe_end_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_end_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_xer_so$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_end_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \pipe_middle_0_div_by_zero @@ -38004,30 +38026,30 @@ module \alu_div0 wire width 64 input 30 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 31 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 28 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:25528.10-25531.4" - cell \n$72 \n + attribute \src "libresoc.v:25620.10-25623.4" + cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:25532.10-25535.4" - cell \p$71 \p + attribute \src "libresoc.v:25624.10-25627.4" + cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:25536.12-25599.4" + attribute \src "libresoc.v:25628.12-25691.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38093,7 +38115,7 @@ module \alu_div0 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:25600.17-25666.4" + attribute \src "libresoc.v:25692.17-25758.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38162,7 +38184,7 @@ module \alu_div0 connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 - attribute \src "libresoc.v:25667.14-25726.4" + attribute \src "libresoc.v:25759.14-25818.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38269,37 +38291,37 @@ module \alu_div0 connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end -attribute \src "libresoc.v:25776.1-25834.10" +attribute \src "libresoc.v:25868.1-25926.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l - attribute \src "libresoc.v:25777.7-25777.20" + attribute \src "libresoc.v:25869.7-25869.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25822.3-25830.6" - wire $0\q_int$next[0:0]$860 - attribute \src "libresoc.v:25820.3-25821.27" + attribute \src "libresoc.v:25914.3-25922.6" + wire $0\q_int$next[0:0]$852 + attribute \src "libresoc.v:25912.3-25913.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:25822.3-25830.6" - wire $1\q_int$next[0:0]$861 - attribute \src "libresoc.v:25801.7-25801.19" + attribute \src "libresoc.v:25914.3-25922.6" + wire $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:25893.7-25893.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25812.17-25812.96" - wire $and$libresoc.v:25812$850_Y - attribute \src "libresoc.v:25817.17-25817.96" - wire $and$libresoc.v:25817$855_Y - attribute \src "libresoc.v:25814.18-25814.93" - wire $not$libresoc.v:25814$852_Y - attribute \src "libresoc.v:25816.17-25816.92" - wire $not$libresoc.v:25816$854_Y - attribute \src "libresoc.v:25819.17-25819.92" - wire $not$libresoc.v:25819$857_Y - attribute \src "libresoc.v:25813.18-25813.98" - wire $or$libresoc.v:25813$851_Y - attribute \src "libresoc.v:25815.18-25815.99" - wire $or$libresoc.v:25815$853_Y - attribute \src "libresoc.v:25818.17-25818.97" - wire $or$libresoc.v:25818$856_Y + attribute \src "libresoc.v:25904.17-25904.96" + wire $and$libresoc.v:25904$842_Y + attribute \src "libresoc.v:25909.17-25909.96" + wire $and$libresoc.v:25909$847_Y + attribute \src "libresoc.v:25906.18-25906.93" + wire $not$libresoc.v:25906$844_Y + attribute \src "libresoc.v:25908.17-25908.92" + wire $not$libresoc.v:25908$846_Y + attribute \src "libresoc.v:25911.17-25911.92" + wire $not$libresoc.v:25911$849_Y + attribute \src "libresoc.v:25905.18-25905.98" + wire $or$libresoc.v:25905$843_Y + attribute \src "libresoc.v:25907.18-25907.99" + wire $or$libresoc.v:25907$845_Y + attribute \src "libresoc.v:25910.17-25910.97" + wire $or$libresoc.v:25910$848_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -38316,11 +38338,11 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:25777.7-25777.15" + attribute \src "libresoc.v:25869.7-25869.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -38337,7 +38359,7 @@ module \alu_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25812$850 + cell $and $and$libresoc.v:25904$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38345,10 +38367,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25812$850_Y + connect \Y $and$libresoc.v:25904$842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25817$855 + cell $and $and$libresoc.v:25909$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38356,34 +38378,34 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:25817$855_Y + connect \Y $and$libresoc.v:25909$847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25814$852 + cell $not $not$libresoc.v:25906$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:25814$852_Y + connect \Y $not$libresoc.v:25906$844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25816$854 + cell $not $not$libresoc.v:25908$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25816$854_Y + connect \Y $not$libresoc.v:25908$846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25819$857 + cell $not $not$libresoc.v:25911$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25819$857_Y + connect \Y $not$libresoc.v:25911$849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25813$851 + cell $or $or$libresoc.v:25905$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38391,10 +38413,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25813$851_Y + connect \Y $or$libresoc.v:25905$843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25815$853 + cell $or $or$libresoc.v:25907$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38402,10 +38424,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:25815$853_Y + connect \Y $or$libresoc.v:25907$845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25818$856 + cell $or $or$libresoc.v:25910$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38413,39 +38435,39 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:25818$856_Y + connect \Y $or$libresoc.v:25910$848_Y end - attribute \src "libresoc.v:25777.7-25777.20" - process $proc$libresoc.v:25777$862 + attribute \src "libresoc.v:25869.7-25869.20" + process $proc$libresoc.v:25869$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25801.7-25801.19" - process $proc$libresoc.v:25801$863 + attribute \src "libresoc.v:25893.7-25893.19" + process $proc$libresoc.v:25893$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:25820.3-25821.27" - process $proc$libresoc.v:25820$858 + attribute \src "libresoc.v:25912.3-25913.27" + process $proc$libresoc.v:25912$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:25822.3-25830.6" - process $proc$libresoc.v:25822$859 + attribute \src "libresoc.v:25914.3-25922.6" + process $proc$libresoc.v:25914$851 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$860 $1\q_int$next[0:0]$861 - attribute \src "libresoc.v:25823.5-25823.29" + assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:25915.5-25915.29" switch \initial - attribute \src "libresoc.v:25823.9-25823.17" + attribute \src "libresoc.v:25915.9-25915.17" case 1'1 case end @@ -38454,56 +38476,56 @@ module \alu_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$861 1'0 + assign $1\q_int$next[0:0]$853 1'0 case - assign $1\q_int$next[0:0]$861 \$5 + assign $1\q_int$next[0:0]$853 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$860 + update \q_int$next $0\q_int$next[0:0]$852 end - connect \$9 $and$libresoc.v:25812$850_Y - connect \$11 $or$libresoc.v:25813$851_Y - connect \$13 $not$libresoc.v:25814$852_Y - connect \$15 $or$libresoc.v:25815$853_Y - connect \$1 $not$libresoc.v:25816$854_Y - connect \$3 $and$libresoc.v:25817$855_Y - connect \$5 $or$libresoc.v:25818$856_Y - connect \$7 $not$libresoc.v:25819$857_Y + connect \$9 $and$libresoc.v:25904$842_Y + connect \$11 $or$libresoc.v:25905$843_Y + connect \$13 $not$libresoc.v:25906$844_Y + connect \$15 $or$libresoc.v:25907$845_Y + connect \$1 $not$libresoc.v:25908$846_Y + connect \$3 $and$libresoc.v:25909$847_Y + connect \$5 $or$libresoc.v:25910$848_Y + connect \$7 $not$libresoc.v:25911$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:25838.1-25896.10" +attribute \src "libresoc.v:25930.1-25988.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" -module \alu_l$104 - attribute \src "libresoc.v:25839.7-25839.20" +module \alu_l$107 + attribute \src "libresoc.v:25931.7-25931.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25884.3-25892.6" - wire $0\q_int$next[0:0]$874 - attribute \src "libresoc.v:25882.3-25883.27" + attribute \src "libresoc.v:25976.3-25984.6" + wire $0\q_int$next[0:0]$866 + attribute \src "libresoc.v:25974.3-25975.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:25884.3-25892.6" - wire $1\q_int$next[0:0]$875 - attribute \src "libresoc.v:25863.7-25863.19" + attribute \src "libresoc.v:25976.3-25984.6" + wire $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:25955.7-25955.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25874.17-25874.96" - wire $and$libresoc.v:25874$864_Y - attribute \src "libresoc.v:25879.17-25879.96" - wire $and$libresoc.v:25879$869_Y - attribute \src "libresoc.v:25876.18-25876.93" - wire $not$libresoc.v:25876$866_Y - attribute \src "libresoc.v:25878.17-25878.92" - wire $not$libresoc.v:25878$868_Y - attribute \src "libresoc.v:25881.17-25881.92" - wire $not$libresoc.v:25881$871_Y - attribute \src "libresoc.v:25875.18-25875.98" - wire $or$libresoc.v:25875$865_Y - attribute \src "libresoc.v:25877.18-25877.99" - wire $or$libresoc.v:25877$867_Y - attribute \src "libresoc.v:25880.17-25880.97" - wire $or$libresoc.v:25880$870_Y + attribute \src "libresoc.v:25966.17-25966.96" + wire $and$libresoc.v:25966$856_Y + attribute \src "libresoc.v:25971.17-25971.96" + wire $and$libresoc.v:25971$861_Y + attribute \src "libresoc.v:25968.18-25968.93" + wire $not$libresoc.v:25968$858_Y + attribute \src "libresoc.v:25970.17-25970.92" + wire $not$libresoc.v:25970$860_Y + attribute \src "libresoc.v:25973.17-25973.92" + wire $not$libresoc.v:25973$863_Y + attribute \src "libresoc.v:25967.18-25967.98" + wire $or$libresoc.v:25967$857_Y + attribute \src "libresoc.v:25969.18-25969.99" + wire $or$libresoc.v:25969$859_Y + attribute \src "libresoc.v:25972.17-25972.97" + wire $or$libresoc.v:25972$862_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -38520,11 +38542,11 @@ module \alu_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:25839.7-25839.15" + attribute \src "libresoc.v:25931.7-25931.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -38541,7 +38563,7 @@ module \alu_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25874$864 + cell $and $and$libresoc.v:25966$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38549,10 +38571,10 @@ module \alu_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25874$864_Y + connect \Y $and$libresoc.v:25966$856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25879$869 + cell $and $and$libresoc.v:25971$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38560,34 +38582,34 @@ module \alu_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:25879$869_Y + connect \Y $and$libresoc.v:25971$861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25876$866 + cell $not $not$libresoc.v:25968$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:25876$866_Y + connect \Y $not$libresoc.v:25968$858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25878$868 + cell $not $not$libresoc.v:25970$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25878$868_Y + connect \Y $not$libresoc.v:25970$860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25881$871 + cell $not $not$libresoc.v:25973$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25881$871_Y + connect \Y $not$libresoc.v:25973$863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25875$865 + cell $or $or$libresoc.v:25967$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38595,10 +38617,10 @@ module \alu_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25875$865_Y + connect \Y $or$libresoc.v:25967$857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25877$867 + cell $or $or$libresoc.v:25969$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38606,10 +38628,10 @@ module \alu_l$104 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:25877$867_Y + connect \Y $or$libresoc.v:25969$859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25880$870 + cell $or $or$libresoc.v:25972$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38617,39 +38639,39 @@ module \alu_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:25880$870_Y + connect \Y $or$libresoc.v:25972$862_Y end - attribute \src "libresoc.v:25839.7-25839.20" - process $proc$libresoc.v:25839$876 + attribute \src "libresoc.v:25931.7-25931.20" + process $proc$libresoc.v:25931$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25863.7-25863.19" - process $proc$libresoc.v:25863$877 + attribute \src "libresoc.v:25955.7-25955.19" + process $proc$libresoc.v:25955$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:25882.3-25883.27" - process $proc$libresoc.v:25882$872 + attribute \src "libresoc.v:25974.3-25975.27" + process $proc$libresoc.v:25974$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:25884.3-25892.6" - process $proc$libresoc.v:25884$873 + attribute \src "libresoc.v:25976.3-25984.6" + process $proc$libresoc.v:25976$865 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$874 $1\q_int$next[0:0]$875 - attribute \src "libresoc.v:25885.5-25885.29" + assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:25977.5-25977.29" switch \initial - attribute \src "libresoc.v:25885.9-25885.17" + attribute \src "libresoc.v:25977.9-25977.17" case 1'1 case end @@ -38658,56 +38680,56 @@ module \alu_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$875 1'0 + assign $1\q_int$next[0:0]$867 1'0 case - assign $1\q_int$next[0:0]$875 \$5 + assign $1\q_int$next[0:0]$867 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$874 + update \q_int$next $0\q_int$next[0:0]$866 end - connect \$9 $and$libresoc.v:25874$864_Y - connect \$11 $or$libresoc.v:25875$865_Y - connect \$13 $not$libresoc.v:25876$866_Y - connect \$15 $or$libresoc.v:25877$867_Y - connect \$1 $not$libresoc.v:25878$868_Y - connect \$3 $and$libresoc.v:25879$869_Y - connect \$5 $or$libresoc.v:25880$870_Y - connect \$7 $not$libresoc.v:25881$871_Y + connect \$9 $and$libresoc.v:25966$856_Y + connect \$11 $or$libresoc.v:25967$857_Y + connect \$13 $not$libresoc.v:25968$858_Y + connect \$15 $or$libresoc.v:25969$859_Y + connect \$1 $not$libresoc.v:25970$860_Y + connect \$3 $and$libresoc.v:25971$861_Y + connect \$5 $or$libresoc.v:25972$862_Y + connect \$7 $not$libresoc.v:25973$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:25900.1-25958.10" +attribute \src "libresoc.v:25992.1-26050.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" -module \alu_l$122 - attribute \src "libresoc.v:25901.7-25901.20" +module \alu_l$125 + attribute \src "libresoc.v:25993.7-25993.20" wire $0\initial[0:0] - attribute \src "libresoc.v:25946.3-25954.6" - wire $0\q_int$next[0:0]$888 - attribute \src "libresoc.v:25944.3-25945.27" + attribute \src "libresoc.v:26038.3-26046.6" + wire $0\q_int$next[0:0]$880 + attribute \src "libresoc.v:26036.3-26037.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:25946.3-25954.6" - wire $1\q_int$next[0:0]$889 - attribute \src "libresoc.v:25925.7-25925.19" + attribute \src "libresoc.v:26038.3-26046.6" + wire $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26017.7-26017.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25936.17-25936.96" - wire $and$libresoc.v:25936$878_Y - attribute \src "libresoc.v:25941.17-25941.96" - wire $and$libresoc.v:25941$883_Y - attribute \src "libresoc.v:25938.18-25938.93" - wire $not$libresoc.v:25938$880_Y - attribute \src "libresoc.v:25940.17-25940.92" - wire $not$libresoc.v:25940$882_Y - attribute \src "libresoc.v:25943.17-25943.92" - wire $not$libresoc.v:25943$885_Y - attribute \src "libresoc.v:25937.18-25937.98" - wire $or$libresoc.v:25937$879_Y - attribute \src "libresoc.v:25939.18-25939.99" - wire $or$libresoc.v:25939$881_Y - attribute \src "libresoc.v:25942.17-25942.97" - wire $or$libresoc.v:25942$884_Y + attribute \src "libresoc.v:26028.17-26028.96" + wire $and$libresoc.v:26028$870_Y + attribute \src "libresoc.v:26033.17-26033.96" + wire $and$libresoc.v:26033$875_Y + attribute \src "libresoc.v:26030.18-26030.93" + wire $not$libresoc.v:26030$872_Y + attribute \src "libresoc.v:26032.17-26032.92" + wire $not$libresoc.v:26032$874_Y + attribute \src "libresoc.v:26035.17-26035.92" + wire $not$libresoc.v:26035$877_Y + attribute \src "libresoc.v:26029.18-26029.98" + wire $or$libresoc.v:26029$871_Y + attribute \src "libresoc.v:26031.18-26031.99" + wire $or$libresoc.v:26031$873_Y + attribute \src "libresoc.v:26034.17-26034.97" + wire $or$libresoc.v:26034$876_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -38724,11 +38746,11 @@ module \alu_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:25901.7-25901.15" + attribute \src "libresoc.v:25993.7-25993.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -38745,7 +38767,7 @@ module \alu_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25936$878 + cell $and $and$libresoc.v:26028$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38753,10 +38775,10 @@ module \alu_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25936$878_Y + connect \Y $and$libresoc.v:26028$870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25941$883 + cell $and $and$libresoc.v:26033$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38764,34 +38786,34 @@ module \alu_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:25941$883_Y + connect \Y $and$libresoc.v:26033$875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25938$880 + cell $not $not$libresoc.v:26030$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:25938$880_Y + connect \Y $not$libresoc.v:26030$872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25940$882 + cell $not $not$libresoc.v:26032$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25940$882_Y + connect \Y $not$libresoc.v:26032$874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25943$885 + cell $not $not$libresoc.v:26035$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:25943$885_Y + connect \Y $not$libresoc.v:26035$877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25937$879 + cell $or $or$libresoc.v:26029$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38799,10 +38821,10 @@ module \alu_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25937$879_Y + connect \Y $or$libresoc.v:26029$871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25939$881 + cell $or $or$libresoc.v:26031$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38810,10 +38832,10 @@ module \alu_l$122 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:25939$881_Y + connect \Y $or$libresoc.v:26031$873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25942$884 + cell $or $or$libresoc.v:26034$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38821,39 +38843,39 @@ module \alu_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:25942$884_Y + connect \Y $or$libresoc.v:26034$876_Y end - attribute \src "libresoc.v:25901.7-25901.20" - process $proc$libresoc.v:25901$890 + attribute \src "libresoc.v:25993.7-25993.20" + process $proc$libresoc.v:25993$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25925.7-25925.19" - process $proc$libresoc.v:25925$891 + attribute \src "libresoc.v:26017.7-26017.19" + process $proc$libresoc.v:26017$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:25944.3-25945.27" - process $proc$libresoc.v:25944$886 + attribute \src "libresoc.v:26036.3-26037.27" + process $proc$libresoc.v:26036$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:25946.3-25954.6" - process $proc$libresoc.v:25946$887 + attribute \src "libresoc.v:26038.3-26046.6" + process $proc$libresoc.v:26038$879 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$888 $1\q_int$next[0:0]$889 - attribute \src "libresoc.v:25947.5-25947.29" + assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26039.5-26039.29" switch \initial - attribute \src "libresoc.v:25947.9-25947.17" + attribute \src "libresoc.v:26039.9-26039.17" case 1'1 case end @@ -38862,56 +38884,56 @@ module \alu_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$889 1'0 + assign $1\q_int$next[0:0]$881 1'0 case - assign $1\q_int$next[0:0]$889 \$5 + assign $1\q_int$next[0:0]$881 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$888 + update \q_int$next $0\q_int$next[0:0]$880 end - connect \$9 $and$libresoc.v:25936$878_Y - connect \$11 $or$libresoc.v:25937$879_Y - connect \$13 $not$libresoc.v:25938$880_Y - connect \$15 $or$libresoc.v:25939$881_Y - connect \$1 $not$libresoc.v:25940$882_Y - connect \$3 $and$libresoc.v:25941$883_Y - connect \$5 $or$libresoc.v:25942$884_Y - connect \$7 $not$libresoc.v:25943$885_Y + connect \$9 $and$libresoc.v:26028$870_Y + connect \$11 $or$libresoc.v:26029$871_Y + connect \$13 $not$libresoc.v:26030$872_Y + connect \$15 $or$libresoc.v:26031$873_Y + connect \$1 $not$libresoc.v:26032$874_Y + connect \$3 $and$libresoc.v:26033$875_Y + connect \$5 $or$libresoc.v:26034$876_Y + connect \$7 $not$libresoc.v:26035$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:25962.1-26020.10" +attribute \src "libresoc.v:26054.1-26112.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" -module \alu_l$125 - attribute \src "libresoc.v:25963.7-25963.20" +module \alu_l$128 + attribute \src "libresoc.v:26055.7-26055.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26008.3-26016.6" - wire $0\q_int$next[0:0]$902 - attribute \src "libresoc.v:26006.3-26007.27" + attribute \src "libresoc.v:26100.3-26108.6" + wire $0\q_int$next[0:0]$894 + attribute \src "libresoc.v:26098.3-26099.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26008.3-26016.6" - wire $1\q_int$next[0:0]$903 - attribute \src "libresoc.v:25987.7-25987.19" + attribute \src "libresoc.v:26100.3-26108.6" + wire $1\q_int$next[0:0]$895 + attribute \src "libresoc.v:26079.7-26079.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:25998.17-25998.96" - wire $and$libresoc.v:25998$892_Y - attribute \src "libresoc.v:26003.17-26003.96" - wire $and$libresoc.v:26003$897_Y - attribute \src "libresoc.v:26000.18-26000.93" - wire $not$libresoc.v:26000$894_Y - attribute \src "libresoc.v:26002.17-26002.92" - wire $not$libresoc.v:26002$896_Y - attribute \src "libresoc.v:26005.17-26005.92" - wire $not$libresoc.v:26005$899_Y - attribute \src "libresoc.v:25999.18-25999.98" - wire $or$libresoc.v:25999$893_Y - attribute \src "libresoc.v:26001.18-26001.99" - wire $or$libresoc.v:26001$895_Y - attribute \src "libresoc.v:26004.17-26004.97" - wire $or$libresoc.v:26004$898_Y + attribute \src "libresoc.v:26090.17-26090.96" + wire $and$libresoc.v:26090$884_Y + attribute \src "libresoc.v:26095.17-26095.96" + wire $and$libresoc.v:26095$889_Y + attribute \src "libresoc.v:26092.18-26092.93" + wire $not$libresoc.v:26092$886_Y + attribute \src "libresoc.v:26094.17-26094.92" + wire $not$libresoc.v:26094$888_Y + attribute \src "libresoc.v:26097.17-26097.92" + wire $not$libresoc.v:26097$891_Y + attribute \src "libresoc.v:26091.18-26091.98" + wire $or$libresoc.v:26091$885_Y + attribute \src "libresoc.v:26093.18-26093.99" + wire $or$libresoc.v:26093$887_Y + attribute \src "libresoc.v:26096.17-26096.97" + wire $or$libresoc.v:26096$890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -38928,11 +38950,11 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:25963.7-25963.15" + attribute \src "libresoc.v:26055.7-26055.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 4 \q_alu @@ -38949,7 +38971,7 @@ module \alu_l$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25998$892 + cell $and $and$libresoc.v:26090$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38957,10 +38979,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:25998$892_Y + connect \Y $and$libresoc.v:26090$884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26003$897 + cell $and $and$libresoc.v:26095$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38968,34 +38990,34 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26003$897_Y + connect \Y $and$libresoc.v:26095$889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26000$894 + cell $not $not$libresoc.v:26092$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26000$894_Y + connect \Y $not$libresoc.v:26092$886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26002$896 + cell $not $not$libresoc.v:26094$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26002$896_Y + connect \Y $not$libresoc.v:26094$888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26005$899 + cell $not $not$libresoc.v:26097$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26005$899_Y + connect \Y $not$libresoc.v:26097$891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25999$893 + cell $or $or$libresoc.v:26091$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39003,10 +39025,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:25999$893_Y + connect \Y $or$libresoc.v:26091$885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26001$895 + cell $or $or$libresoc.v:26093$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39014,10 +39036,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26001$895_Y + connect \Y $or$libresoc.v:26093$887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26004$898 + cell $or $or$libresoc.v:26096$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39025,39 +39047,39 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26004$898_Y + connect \Y $or$libresoc.v:26096$890_Y end - attribute \src "libresoc.v:25963.7-25963.20" - process $proc$libresoc.v:25963$904 + attribute \src "libresoc.v:26055.7-26055.20" + process $proc$libresoc.v:26055$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:25987.7-25987.19" - process $proc$libresoc.v:25987$905 + attribute \src "libresoc.v:26079.7-26079.19" + process $proc$libresoc.v:26079$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26006.3-26007.27" - process $proc$libresoc.v:26006$900 + attribute \src "libresoc.v:26098.3-26099.27" + process $proc$libresoc.v:26098$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26008.3-26016.6" - process $proc$libresoc.v:26008$901 + attribute \src "libresoc.v:26100.3-26108.6" + process $proc$libresoc.v:26100$893 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$902 $1\q_int$next[0:0]$903 - attribute \src "libresoc.v:26009.5-26009.29" + assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 + attribute \src "libresoc.v:26101.5-26101.29" switch \initial - attribute \src "libresoc.v:26009.9-26009.17" + attribute \src "libresoc.v:26101.9-26101.17" case 1'1 case end @@ -39066,56 +39088,56 @@ module \alu_l$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$903 1'0 + assign $1\q_int$next[0:0]$895 1'0 case - assign $1\q_int$next[0:0]$903 \$5 + assign $1\q_int$next[0:0]$895 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$902 + update \q_int$next $0\q_int$next[0:0]$894 end - connect \$9 $and$libresoc.v:25998$892_Y - connect \$11 $or$libresoc.v:25999$893_Y - connect \$13 $not$libresoc.v:26000$894_Y - connect \$15 $or$libresoc.v:26001$895_Y - connect \$1 $not$libresoc.v:26002$896_Y - connect \$3 $and$libresoc.v:26003$897_Y - connect \$5 $or$libresoc.v:26004$898_Y - connect \$7 $not$libresoc.v:26005$899_Y + connect \$9 $and$libresoc.v:26090$884_Y + connect \$11 $or$libresoc.v:26091$885_Y + connect \$13 $not$libresoc.v:26092$886_Y + connect \$15 $or$libresoc.v:26093$887_Y + connect \$1 $not$libresoc.v:26094$888_Y + connect \$3 $and$libresoc.v:26095$889_Y + connect \$5 $or$libresoc.v:26096$890_Y + connect \$7 $not$libresoc.v:26097$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26024.1-26082.10" +attribute \src "libresoc.v:26116.1-26174.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 - attribute \src "libresoc.v:26025.7-26025.20" + attribute \src "libresoc.v:26117.7-26117.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26070.3-26078.6" - wire $0\q_int$next[0:0]$916 - attribute \src "libresoc.v:26068.3-26069.27" + attribute \src "libresoc.v:26162.3-26170.6" + wire $0\q_int$next[0:0]$908 + attribute \src "libresoc.v:26160.3-26161.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26070.3-26078.6" - wire $1\q_int$next[0:0]$917 - attribute \src "libresoc.v:26049.7-26049.19" + attribute \src "libresoc.v:26162.3-26170.6" + wire $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26141.7-26141.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26060.17-26060.96" - wire $and$libresoc.v:26060$906_Y - attribute \src "libresoc.v:26065.17-26065.96" - wire $and$libresoc.v:26065$911_Y - attribute \src "libresoc.v:26062.18-26062.93" - wire $not$libresoc.v:26062$908_Y - attribute \src "libresoc.v:26064.17-26064.92" - wire $not$libresoc.v:26064$910_Y - attribute \src "libresoc.v:26067.17-26067.92" - wire $not$libresoc.v:26067$913_Y - attribute \src "libresoc.v:26061.18-26061.98" - wire $or$libresoc.v:26061$907_Y - attribute \src "libresoc.v:26063.18-26063.99" - wire $or$libresoc.v:26063$909_Y - attribute \src "libresoc.v:26066.17-26066.97" - wire $or$libresoc.v:26066$912_Y + attribute \src "libresoc.v:26152.17-26152.96" + wire $and$libresoc.v:26152$898_Y + attribute \src "libresoc.v:26157.17-26157.96" + wire $and$libresoc.v:26157$903_Y + attribute \src "libresoc.v:26154.18-26154.93" + wire $not$libresoc.v:26154$900_Y + attribute \src "libresoc.v:26156.17-26156.92" + wire $not$libresoc.v:26156$902_Y + attribute \src "libresoc.v:26159.17-26159.92" + wire $not$libresoc.v:26159$905_Y + attribute \src "libresoc.v:26153.18-26153.98" + wire $or$libresoc.v:26153$899_Y + attribute \src "libresoc.v:26155.18-26155.99" + wire $or$libresoc.v:26155$901_Y + attribute \src "libresoc.v:26158.17-26158.97" + wire $or$libresoc.v:26158$904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -39132,11 +39154,11 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26025.7-26025.15" + attribute \src "libresoc.v:26117.7-26117.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -39153,7 +39175,7 @@ module \alu_l$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26060$906 + cell $and $and$libresoc.v:26152$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39161,10 +39183,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26060$906_Y + connect \Y $and$libresoc.v:26152$898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26065$911 + cell $and $and$libresoc.v:26157$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39172,34 +39194,34 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26065$911_Y + connect \Y $and$libresoc.v:26157$903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26062$908 + cell $not $not$libresoc.v:26154$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26062$908_Y + connect \Y $not$libresoc.v:26154$900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26064$910 + cell $not $not$libresoc.v:26156$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26064$910_Y + connect \Y $not$libresoc.v:26156$902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26067$913 + cell $not $not$libresoc.v:26159$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26067$913_Y + connect \Y $not$libresoc.v:26159$905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26061$907 + cell $or $or$libresoc.v:26153$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39207,10 +39229,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26061$907_Y + connect \Y $or$libresoc.v:26153$899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26063$909 + cell $or $or$libresoc.v:26155$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39218,10 +39240,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26063$909_Y + connect \Y $or$libresoc.v:26155$901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26066$912 + cell $or $or$libresoc.v:26158$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39229,39 +39251,39 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26066$912_Y + connect \Y $or$libresoc.v:26158$904_Y end - attribute \src "libresoc.v:26025.7-26025.20" - process $proc$libresoc.v:26025$918 + attribute \src "libresoc.v:26117.7-26117.20" + process $proc$libresoc.v:26117$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26049.7-26049.19" - process $proc$libresoc.v:26049$919 + attribute \src "libresoc.v:26141.7-26141.19" + process $proc$libresoc.v:26141$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26068.3-26069.27" - process $proc$libresoc.v:26068$914 + attribute \src "libresoc.v:26160.3-26161.27" + process $proc$libresoc.v:26160$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26070.3-26078.6" - process $proc$libresoc.v:26070$915 + attribute \src "libresoc.v:26162.3-26170.6" + process $proc$libresoc.v:26162$907 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$916 $1\q_int$next[0:0]$917 - attribute \src "libresoc.v:26071.5-26071.29" + assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26163.5-26163.29" switch \initial - attribute \src "libresoc.v:26071.9-26071.17" + attribute \src "libresoc.v:26163.9-26163.17" case 1'1 case end @@ -39270,56 +39292,56 @@ module \alu_l$16 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$917 1'0 + assign $1\q_int$next[0:0]$909 1'0 case - assign $1\q_int$next[0:0]$917 \$5 + assign $1\q_int$next[0:0]$909 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$916 + update \q_int$next $0\q_int$next[0:0]$908 end - connect \$9 $and$libresoc.v:26060$906_Y - connect \$11 $or$libresoc.v:26061$907_Y - connect \$13 $not$libresoc.v:26062$908_Y - connect \$15 $or$libresoc.v:26063$909_Y - connect \$1 $not$libresoc.v:26064$910_Y - connect \$3 $and$libresoc.v:26065$911_Y - connect \$5 $or$libresoc.v:26066$912_Y - connect \$7 $not$libresoc.v:26067$913_Y + connect \$9 $and$libresoc.v:26152$898_Y + connect \$11 $or$libresoc.v:26153$899_Y + connect \$13 $not$libresoc.v:26154$900_Y + connect \$15 $or$libresoc.v:26155$901_Y + connect \$1 $not$libresoc.v:26156$902_Y + connect \$3 $and$libresoc.v:26157$903_Y + connect \$5 $or$libresoc.v:26158$904_Y + connect \$7 $not$libresoc.v:26159$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26086.1-26144.10" +attribute \src "libresoc.v:26178.1-26236.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 - attribute \src "libresoc.v:26087.7-26087.20" + attribute \src "libresoc.v:26179.7-26179.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26132.3-26140.6" - wire $0\q_int$next[0:0]$930 - attribute \src "libresoc.v:26130.3-26131.27" + attribute \src "libresoc.v:26224.3-26232.6" + wire $0\q_int$next[0:0]$922 + attribute \src "libresoc.v:26222.3-26223.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26132.3-26140.6" - wire $1\q_int$next[0:0]$931 - attribute \src "libresoc.v:26111.7-26111.19" + attribute \src "libresoc.v:26224.3-26232.6" + wire $1\q_int$next[0:0]$923 + attribute \src "libresoc.v:26203.7-26203.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26122.17-26122.96" - wire $and$libresoc.v:26122$920_Y - attribute \src "libresoc.v:26127.17-26127.96" - wire $and$libresoc.v:26127$925_Y - attribute \src "libresoc.v:26124.18-26124.93" - wire $not$libresoc.v:26124$922_Y - attribute \src "libresoc.v:26126.17-26126.92" - wire $not$libresoc.v:26126$924_Y - attribute \src "libresoc.v:26129.17-26129.92" - wire $not$libresoc.v:26129$927_Y - attribute \src "libresoc.v:26123.18-26123.98" - wire $or$libresoc.v:26123$921_Y - attribute \src "libresoc.v:26125.18-26125.99" - wire $or$libresoc.v:26125$923_Y - attribute \src "libresoc.v:26128.17-26128.97" - wire $or$libresoc.v:26128$926_Y + attribute \src "libresoc.v:26214.17-26214.96" + wire $and$libresoc.v:26214$912_Y + attribute \src "libresoc.v:26219.17-26219.96" + wire $and$libresoc.v:26219$917_Y + attribute \src "libresoc.v:26216.18-26216.93" + wire $not$libresoc.v:26216$914_Y + attribute \src "libresoc.v:26218.17-26218.92" + wire $not$libresoc.v:26218$916_Y + attribute \src "libresoc.v:26221.17-26221.92" + wire $not$libresoc.v:26221$919_Y + attribute \src "libresoc.v:26215.18-26215.98" + wire $or$libresoc.v:26215$913_Y + attribute \src "libresoc.v:26217.18-26217.99" + wire $or$libresoc.v:26217$915_Y + attribute \src "libresoc.v:26220.17-26220.97" + wire $or$libresoc.v:26220$918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -39336,11 +39358,11 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26087.7-26087.15" + attribute \src "libresoc.v:26179.7-26179.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -39357,7 +39379,7 @@ module \alu_l$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26122$920 + cell $and $and$libresoc.v:26214$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39365,10 +39387,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26122$920_Y + connect \Y $and$libresoc.v:26214$912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26127$925 + cell $and $and$libresoc.v:26219$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39376,34 +39398,34 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26127$925_Y + connect \Y $and$libresoc.v:26219$917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26124$922 + cell $not $not$libresoc.v:26216$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26124$922_Y + connect \Y $not$libresoc.v:26216$914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26126$924 + cell $not $not$libresoc.v:26218$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26126$924_Y + connect \Y $not$libresoc.v:26218$916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26129$927 + cell $not $not$libresoc.v:26221$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26129$927_Y + connect \Y $not$libresoc.v:26221$919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26123$921 + cell $or $or$libresoc.v:26215$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39411,10 +39433,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26123$921_Y + connect \Y $or$libresoc.v:26215$913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26125$923 + cell $or $or$libresoc.v:26217$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39422,10 +39444,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26125$923_Y + connect \Y $or$libresoc.v:26217$915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26128$926 + cell $or $or$libresoc.v:26220$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39433,39 +39455,39 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26128$926_Y + connect \Y $or$libresoc.v:26220$918_Y end - attribute \src "libresoc.v:26087.7-26087.20" - process $proc$libresoc.v:26087$932 + attribute \src "libresoc.v:26179.7-26179.20" + process $proc$libresoc.v:26179$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26111.7-26111.19" - process $proc$libresoc.v:26111$933 + attribute \src "libresoc.v:26203.7-26203.19" + process $proc$libresoc.v:26203$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26130.3-26131.27" - process $proc$libresoc.v:26130$928 + attribute \src "libresoc.v:26222.3-26223.27" + process $proc$libresoc.v:26222$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26132.3-26140.6" - process $proc$libresoc.v:26132$929 + attribute \src "libresoc.v:26224.3-26232.6" + process $proc$libresoc.v:26224$921 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$930 $1\q_int$next[0:0]$931 - attribute \src "libresoc.v:26133.5-26133.29" + assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 + attribute \src "libresoc.v:26225.5-26225.29" switch \initial - attribute \src "libresoc.v:26133.9-26133.17" + attribute \src "libresoc.v:26225.9-26225.17" case 1'1 case end @@ -39474,56 +39496,56 @@ module \alu_l$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$931 1'0 + assign $1\q_int$next[0:0]$923 1'0 case - assign $1\q_int$next[0:0]$931 \$5 + assign $1\q_int$next[0:0]$923 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$930 + update \q_int$next $0\q_int$next[0:0]$922 end - connect \$9 $and$libresoc.v:26122$920_Y - connect \$11 $or$libresoc.v:26123$921_Y - connect \$13 $not$libresoc.v:26124$922_Y - connect \$15 $or$libresoc.v:26125$923_Y - connect \$1 $not$libresoc.v:26126$924_Y - connect \$3 $and$libresoc.v:26127$925_Y - connect \$5 $or$libresoc.v:26128$926_Y - connect \$7 $not$libresoc.v:26129$927_Y + connect \$9 $and$libresoc.v:26214$912_Y + connect \$11 $or$libresoc.v:26215$913_Y + connect \$13 $not$libresoc.v:26216$914_Y + connect \$15 $or$libresoc.v:26217$915_Y + connect \$1 $not$libresoc.v:26218$916_Y + connect \$3 $and$libresoc.v:26219$917_Y + connect \$5 $or$libresoc.v:26220$918_Y + connect \$7 $not$libresoc.v:26221$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26148.1-26206.10" +attribute \src "libresoc.v:26240.1-26298.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" -module \alu_l$42 - attribute \src "libresoc.v:26149.7-26149.20" +module \alu_l$45 + attribute \src "libresoc.v:26241.7-26241.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26194.3-26202.6" - wire $0\q_int$next[0:0]$944 - attribute \src "libresoc.v:26192.3-26193.27" + attribute \src "libresoc.v:26286.3-26294.6" + wire $0\q_int$next[0:0]$936 + attribute \src "libresoc.v:26284.3-26285.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26194.3-26202.6" - wire $1\q_int$next[0:0]$945 - attribute \src "libresoc.v:26173.7-26173.19" + attribute \src "libresoc.v:26286.3-26294.6" + wire $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26265.7-26265.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26184.17-26184.96" - wire $and$libresoc.v:26184$934_Y - attribute \src "libresoc.v:26189.17-26189.96" - wire $and$libresoc.v:26189$939_Y - attribute \src "libresoc.v:26186.18-26186.93" - wire $not$libresoc.v:26186$936_Y - attribute \src "libresoc.v:26188.17-26188.92" - wire $not$libresoc.v:26188$938_Y - attribute \src "libresoc.v:26191.17-26191.92" - wire $not$libresoc.v:26191$941_Y - attribute \src "libresoc.v:26185.18-26185.98" - wire $or$libresoc.v:26185$935_Y - attribute \src "libresoc.v:26187.18-26187.99" - wire $or$libresoc.v:26187$937_Y - attribute \src "libresoc.v:26190.17-26190.97" - wire $or$libresoc.v:26190$940_Y + attribute \src "libresoc.v:26276.17-26276.96" + wire $and$libresoc.v:26276$926_Y + attribute \src "libresoc.v:26281.17-26281.96" + wire $and$libresoc.v:26281$931_Y + attribute \src "libresoc.v:26278.18-26278.93" + wire $not$libresoc.v:26278$928_Y + attribute \src "libresoc.v:26280.17-26280.92" + wire $not$libresoc.v:26280$930_Y + attribute \src "libresoc.v:26283.17-26283.92" + wire $not$libresoc.v:26283$933_Y + attribute \src "libresoc.v:26277.18-26277.98" + wire $or$libresoc.v:26277$927_Y + attribute \src "libresoc.v:26279.18-26279.99" + wire $or$libresoc.v:26279$929_Y + attribute \src "libresoc.v:26282.17-26282.97" + wire $or$libresoc.v:26282$932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -39540,11 +39562,11 @@ module \alu_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26149.7-26149.15" + attribute \src "libresoc.v:26241.7-26241.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -39561,7 +39583,7 @@ module \alu_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26184$934 + cell $and $and$libresoc.v:26276$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39569,10 +39591,10 @@ module \alu_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26184$934_Y + connect \Y $and$libresoc.v:26276$926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26189$939 + cell $and $and$libresoc.v:26281$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39580,34 +39602,34 @@ module \alu_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26189$939_Y + connect \Y $and$libresoc.v:26281$931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26186$936 + cell $not $not$libresoc.v:26278$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26186$936_Y + connect \Y $not$libresoc.v:26278$928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26188$938 + cell $not $not$libresoc.v:26280$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26188$938_Y + connect \Y $not$libresoc.v:26280$930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26191$941 + cell $not $not$libresoc.v:26283$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26191$941_Y + connect \Y $not$libresoc.v:26283$933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26185$935 + cell $or $or$libresoc.v:26277$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39615,10 +39637,10 @@ module \alu_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26185$935_Y + connect \Y $or$libresoc.v:26277$927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26187$937 + cell $or $or$libresoc.v:26279$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39626,10 +39648,10 @@ module \alu_l$42 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26187$937_Y + connect \Y $or$libresoc.v:26279$929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26190$940 + cell $or $or$libresoc.v:26282$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39637,39 +39659,39 @@ module \alu_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26190$940_Y + connect \Y $or$libresoc.v:26282$932_Y end - attribute \src "libresoc.v:26149.7-26149.20" - process $proc$libresoc.v:26149$946 + attribute \src "libresoc.v:26241.7-26241.20" + process $proc$libresoc.v:26241$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26173.7-26173.19" - process $proc$libresoc.v:26173$947 + attribute \src "libresoc.v:26265.7-26265.19" + process $proc$libresoc.v:26265$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26192.3-26193.27" - process $proc$libresoc.v:26192$942 + attribute \src "libresoc.v:26284.3-26285.27" + process $proc$libresoc.v:26284$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26194.3-26202.6" - process $proc$libresoc.v:26194$943 + attribute \src "libresoc.v:26286.3-26294.6" + process $proc$libresoc.v:26286$935 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$944 $1\q_int$next[0:0]$945 - attribute \src "libresoc.v:26195.5-26195.29" + assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26287.5-26287.29" switch \initial - attribute \src "libresoc.v:26195.9-26195.17" + attribute \src "libresoc.v:26287.9-26287.17" case 1'1 case end @@ -39678,56 +39700,56 @@ module \alu_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$945 1'0 + assign $1\q_int$next[0:0]$937 1'0 case - assign $1\q_int$next[0:0]$945 \$5 + assign $1\q_int$next[0:0]$937 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$944 + update \q_int$next $0\q_int$next[0:0]$936 end - connect \$9 $and$libresoc.v:26184$934_Y - connect \$11 $or$libresoc.v:26185$935_Y - connect \$13 $not$libresoc.v:26186$936_Y - connect \$15 $or$libresoc.v:26187$937_Y - connect \$1 $not$libresoc.v:26188$938_Y - connect \$3 $and$libresoc.v:26189$939_Y - connect \$5 $or$libresoc.v:26190$940_Y - connect \$7 $not$libresoc.v:26191$941_Y + connect \$9 $and$libresoc.v:26276$926_Y + connect \$11 $or$libresoc.v:26277$927_Y + connect \$13 $not$libresoc.v:26278$928_Y + connect \$15 $or$libresoc.v:26279$929_Y + connect \$1 $not$libresoc.v:26280$930_Y + connect \$3 $and$libresoc.v:26281$931_Y + connect \$5 $or$libresoc.v:26282$932_Y + connect \$7 $not$libresoc.v:26283$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26210.1-26268.10" +attribute \src "libresoc.v:26302.1-26360.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" -module \alu_l$58 - attribute \src "libresoc.v:26211.7-26211.20" +module \alu_l$61 + attribute \src "libresoc.v:26303.7-26303.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26256.3-26264.6" - wire $0\q_int$next[0:0]$958 - attribute \src "libresoc.v:26254.3-26255.27" + attribute \src "libresoc.v:26348.3-26356.6" + wire $0\q_int$next[0:0]$950 + attribute \src "libresoc.v:26346.3-26347.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26256.3-26264.6" - wire $1\q_int$next[0:0]$959 - attribute \src "libresoc.v:26235.7-26235.19" + attribute \src "libresoc.v:26348.3-26356.6" + wire $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26327.7-26327.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26246.17-26246.96" - wire $and$libresoc.v:26246$948_Y - attribute \src "libresoc.v:26251.17-26251.96" - wire $and$libresoc.v:26251$953_Y - attribute \src "libresoc.v:26248.18-26248.93" - wire $not$libresoc.v:26248$950_Y - attribute \src "libresoc.v:26250.17-26250.92" - wire $not$libresoc.v:26250$952_Y - attribute \src "libresoc.v:26253.17-26253.92" - wire $not$libresoc.v:26253$955_Y - attribute \src "libresoc.v:26247.18-26247.98" - wire $or$libresoc.v:26247$949_Y - attribute \src "libresoc.v:26249.18-26249.99" - wire $or$libresoc.v:26249$951_Y - attribute \src "libresoc.v:26252.17-26252.97" - wire $or$libresoc.v:26252$954_Y + attribute \src "libresoc.v:26338.17-26338.96" + wire $and$libresoc.v:26338$940_Y + attribute \src "libresoc.v:26343.17-26343.96" + wire $and$libresoc.v:26343$945_Y + attribute \src "libresoc.v:26340.18-26340.93" + wire $not$libresoc.v:26340$942_Y + attribute \src "libresoc.v:26342.17-26342.92" + wire $not$libresoc.v:26342$944_Y + attribute \src "libresoc.v:26345.17-26345.92" + wire $not$libresoc.v:26345$947_Y + attribute \src "libresoc.v:26339.18-26339.98" + wire $or$libresoc.v:26339$941_Y + attribute \src "libresoc.v:26341.18-26341.99" + wire $or$libresoc.v:26341$943_Y + attribute \src "libresoc.v:26344.17-26344.97" + wire $or$libresoc.v:26344$946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -39744,11 +39766,11 @@ module \alu_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26211.7-26211.15" + attribute \src "libresoc.v:26303.7-26303.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -39765,7 +39787,7 @@ module \alu_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26246$948 + cell $and $and$libresoc.v:26338$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39773,10 +39795,10 @@ module \alu_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26246$948_Y + connect \Y $and$libresoc.v:26338$940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26251$953 + cell $and $and$libresoc.v:26343$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39784,34 +39806,34 @@ module \alu_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26251$953_Y + connect \Y $and$libresoc.v:26343$945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26248$950 + cell $not $not$libresoc.v:26340$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26248$950_Y + connect \Y $not$libresoc.v:26340$942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26250$952 + cell $not $not$libresoc.v:26342$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26250$952_Y + connect \Y $not$libresoc.v:26342$944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26253$955 + cell $not $not$libresoc.v:26345$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26253$955_Y + connect \Y $not$libresoc.v:26345$947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26247$949 + cell $or $or$libresoc.v:26339$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39819,10 +39841,10 @@ module \alu_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26247$949_Y + connect \Y $or$libresoc.v:26339$941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26249$951 + cell $or $or$libresoc.v:26341$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39830,10 +39852,10 @@ module \alu_l$58 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26249$951_Y + connect \Y $or$libresoc.v:26341$943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26252$954 + cell $or $or$libresoc.v:26344$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39841,39 +39863,39 @@ module \alu_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26252$954_Y + connect \Y $or$libresoc.v:26344$946_Y end - attribute \src "libresoc.v:26211.7-26211.20" - process $proc$libresoc.v:26211$960 + attribute \src "libresoc.v:26303.7-26303.20" + process $proc$libresoc.v:26303$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26235.7-26235.19" - process $proc$libresoc.v:26235$961 + attribute \src "libresoc.v:26327.7-26327.19" + process $proc$libresoc.v:26327$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26254.3-26255.27" - process $proc$libresoc.v:26254$956 + attribute \src "libresoc.v:26346.3-26347.27" + process $proc$libresoc.v:26346$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26256.3-26264.6" - process $proc$libresoc.v:26256$957 + attribute \src "libresoc.v:26348.3-26356.6" + process $proc$libresoc.v:26348$949 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$958 $1\q_int$next[0:0]$959 - attribute \src "libresoc.v:26257.5-26257.29" + assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26349.5-26349.29" switch \initial - attribute \src "libresoc.v:26257.9-26257.17" + attribute \src "libresoc.v:26349.9-26349.17" case 1'1 case end @@ -39882,56 +39904,56 @@ module \alu_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$959 1'0 + assign $1\q_int$next[0:0]$951 1'0 case - assign $1\q_int$next[0:0]$959 \$5 + assign $1\q_int$next[0:0]$951 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$958 + update \q_int$next $0\q_int$next[0:0]$950 end - connect \$9 $and$libresoc.v:26246$948_Y - connect \$11 $or$libresoc.v:26247$949_Y - connect \$13 $not$libresoc.v:26248$950_Y - connect \$15 $or$libresoc.v:26249$951_Y - connect \$1 $not$libresoc.v:26250$952_Y - connect \$3 $and$libresoc.v:26251$953_Y - connect \$5 $or$libresoc.v:26252$954_Y - connect \$7 $not$libresoc.v:26253$955_Y + connect \$9 $and$libresoc.v:26338$940_Y + connect \$11 $or$libresoc.v:26339$941_Y + connect \$13 $not$libresoc.v:26340$942_Y + connect \$15 $or$libresoc.v:26341$943_Y + connect \$1 $not$libresoc.v:26342$944_Y + connect \$3 $and$libresoc.v:26343$945_Y + connect \$5 $or$libresoc.v:26344$946_Y + connect \$7 $not$libresoc.v:26345$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26272.1-26330.10" +attribute \src "libresoc.v:26364.1-26422.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" -module \alu_l$70 - attribute \src "libresoc.v:26273.7-26273.20" +module \alu_l$73 + attribute \src "libresoc.v:26365.7-26365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26318.3-26326.6" - wire $0\q_int$next[0:0]$972 - attribute \src "libresoc.v:26316.3-26317.27" + attribute \src "libresoc.v:26410.3-26418.6" + wire $0\q_int$next[0:0]$964 + attribute \src "libresoc.v:26408.3-26409.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26318.3-26326.6" - wire $1\q_int$next[0:0]$973 - attribute \src "libresoc.v:26297.7-26297.19" + attribute \src "libresoc.v:26410.3-26418.6" + wire $1\q_int$next[0:0]$965 + attribute \src "libresoc.v:26389.7-26389.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26308.17-26308.96" - wire $and$libresoc.v:26308$962_Y - attribute \src "libresoc.v:26313.17-26313.96" - wire $and$libresoc.v:26313$967_Y - attribute \src "libresoc.v:26310.18-26310.93" - wire $not$libresoc.v:26310$964_Y - attribute \src "libresoc.v:26312.17-26312.92" - wire $not$libresoc.v:26312$966_Y - attribute \src "libresoc.v:26315.17-26315.92" - wire $not$libresoc.v:26315$969_Y - attribute \src "libresoc.v:26309.18-26309.98" - wire $or$libresoc.v:26309$963_Y - attribute \src "libresoc.v:26311.18-26311.99" - wire $or$libresoc.v:26311$965_Y - attribute \src "libresoc.v:26314.17-26314.97" - wire $or$libresoc.v:26314$968_Y + attribute \src "libresoc.v:26400.17-26400.96" + wire $and$libresoc.v:26400$954_Y + attribute \src "libresoc.v:26405.17-26405.96" + wire $and$libresoc.v:26405$959_Y + attribute \src "libresoc.v:26402.18-26402.93" + wire $not$libresoc.v:26402$956_Y + attribute \src "libresoc.v:26404.17-26404.92" + wire $not$libresoc.v:26404$958_Y + attribute \src "libresoc.v:26407.17-26407.92" + wire $not$libresoc.v:26407$961_Y + attribute \src "libresoc.v:26401.18-26401.98" + wire $or$libresoc.v:26401$955_Y + attribute \src "libresoc.v:26403.18-26403.99" + wire $or$libresoc.v:26403$957_Y + attribute \src "libresoc.v:26406.17-26406.97" + wire $or$libresoc.v:26406$960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -39948,11 +39970,11 @@ module \alu_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26273.7-26273.15" + attribute \src "libresoc.v:26365.7-26365.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -39969,7 +39991,7 @@ module \alu_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26308$962 + cell $and $and$libresoc.v:26400$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39977,10 +39999,10 @@ module \alu_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26308$962_Y + connect \Y $and$libresoc.v:26400$954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26313$967 + cell $and $and$libresoc.v:26405$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39988,34 +40010,34 @@ module \alu_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26313$967_Y + connect \Y $and$libresoc.v:26405$959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26310$964 + cell $not $not$libresoc.v:26402$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26310$964_Y + connect \Y $not$libresoc.v:26402$956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26312$966 + cell $not $not$libresoc.v:26404$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26312$966_Y + connect \Y $not$libresoc.v:26404$958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26315$969 + cell $not $not$libresoc.v:26407$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26315$969_Y + connect \Y $not$libresoc.v:26407$961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26309$963 + cell $or $or$libresoc.v:26401$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40023,10 +40045,10 @@ module \alu_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26309$963_Y + connect \Y $or$libresoc.v:26401$955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26311$965 + cell $or $or$libresoc.v:26403$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40034,10 +40056,10 @@ module \alu_l$70 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26311$965_Y + connect \Y $or$libresoc.v:26403$957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26314$968 + cell $or $or$libresoc.v:26406$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40045,39 +40067,39 @@ module \alu_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26314$968_Y + connect \Y $or$libresoc.v:26406$960_Y end - attribute \src "libresoc.v:26273.7-26273.20" - process $proc$libresoc.v:26273$974 + attribute \src "libresoc.v:26365.7-26365.20" + process $proc$libresoc.v:26365$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26297.7-26297.19" - process $proc$libresoc.v:26297$975 + attribute \src "libresoc.v:26389.7-26389.19" + process $proc$libresoc.v:26389$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26316.3-26317.27" - process $proc$libresoc.v:26316$970 + attribute \src "libresoc.v:26408.3-26409.27" + process $proc$libresoc.v:26408$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26318.3-26326.6" - process $proc$libresoc.v:26318$971 + attribute \src "libresoc.v:26410.3-26418.6" + process $proc$libresoc.v:26410$963 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$972 $1\q_int$next[0:0]$973 - attribute \src "libresoc.v:26319.5-26319.29" + assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 + attribute \src "libresoc.v:26411.5-26411.29" switch \initial - attribute \src "libresoc.v:26319.9-26319.17" + attribute \src "libresoc.v:26411.9-26411.17" case 1'1 case end @@ -40086,56 +40108,56 @@ module \alu_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$973 1'0 + assign $1\q_int$next[0:0]$965 1'0 case - assign $1\q_int$next[0:0]$973 \$5 + assign $1\q_int$next[0:0]$965 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$972 + update \q_int$next $0\q_int$next[0:0]$964 end - connect \$9 $and$libresoc.v:26308$962_Y - connect \$11 $or$libresoc.v:26309$963_Y - connect \$13 $not$libresoc.v:26310$964_Y - connect \$15 $or$libresoc.v:26311$965_Y - connect \$1 $not$libresoc.v:26312$966_Y - connect \$3 $and$libresoc.v:26313$967_Y - connect \$5 $or$libresoc.v:26314$968_Y - connect \$7 $not$libresoc.v:26315$969_Y + connect \$9 $and$libresoc.v:26400$954_Y + connect \$11 $or$libresoc.v:26401$955_Y + connect \$13 $not$libresoc.v:26402$956_Y + connect \$15 $or$libresoc.v:26403$957_Y + connect \$1 $not$libresoc.v:26404$958_Y + connect \$3 $and$libresoc.v:26405$959_Y + connect \$5 $or$libresoc.v:26406$960_Y + connect \$7 $not$libresoc.v:26407$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26334.1-26392.10" +attribute \src "libresoc.v:26426.1-26484.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" -module \alu_l$87 - attribute \src "libresoc.v:26335.7-26335.20" +module \alu_l$90 + attribute \src "libresoc.v:26427.7-26427.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26380.3-26388.6" - wire $0\q_int$next[0:0]$986 - attribute \src "libresoc.v:26378.3-26379.27" + attribute \src "libresoc.v:26472.3-26480.6" + wire $0\q_int$next[0:0]$978 + attribute \src "libresoc.v:26470.3-26471.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26380.3-26388.6" - wire $1\q_int$next[0:0]$987 - attribute \src "libresoc.v:26359.7-26359.19" + attribute \src "libresoc.v:26472.3-26480.6" + wire $1\q_int$next[0:0]$979 + attribute \src "libresoc.v:26451.7-26451.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26370.17-26370.96" - wire $and$libresoc.v:26370$976_Y - attribute \src "libresoc.v:26375.17-26375.96" - wire $and$libresoc.v:26375$981_Y - attribute \src "libresoc.v:26372.18-26372.93" - wire $not$libresoc.v:26372$978_Y - attribute \src "libresoc.v:26374.17-26374.92" - wire $not$libresoc.v:26374$980_Y - attribute \src "libresoc.v:26377.17-26377.92" - wire $not$libresoc.v:26377$983_Y - attribute \src "libresoc.v:26371.18-26371.98" - wire $or$libresoc.v:26371$977_Y - attribute \src "libresoc.v:26373.18-26373.99" - wire $or$libresoc.v:26373$979_Y - attribute \src "libresoc.v:26376.17-26376.97" - wire $or$libresoc.v:26376$982_Y + attribute \src "libresoc.v:26462.17-26462.96" + wire $and$libresoc.v:26462$968_Y + attribute \src "libresoc.v:26467.17-26467.96" + wire $and$libresoc.v:26467$973_Y + attribute \src "libresoc.v:26464.18-26464.93" + wire $not$libresoc.v:26464$970_Y + attribute \src "libresoc.v:26466.17-26466.92" + wire $not$libresoc.v:26466$972_Y + attribute \src "libresoc.v:26469.17-26469.92" + wire $not$libresoc.v:26469$975_Y + attribute \src "libresoc.v:26463.18-26463.98" + wire $or$libresoc.v:26463$969_Y + attribute \src "libresoc.v:26465.18-26465.99" + wire $or$libresoc.v:26465$971_Y + attribute \src "libresoc.v:26468.17-26468.97" + wire $or$libresoc.v:26468$974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -40152,11 +40174,11 @@ module \alu_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:26335.7-26335.15" + attribute \src "libresoc.v:26427.7-26427.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alu @@ -40173,7 +40195,7 @@ module \alu_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26370$976 + cell $and $and$libresoc.v:26462$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40181,10 +40203,10 @@ module \alu_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26370$976_Y + connect \Y $and$libresoc.v:26462$968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26375$981 + cell $and $and$libresoc.v:26467$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40192,34 +40214,34 @@ module \alu_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26375$981_Y + connect \Y $and$libresoc.v:26467$973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26372$978 + cell $not $not$libresoc.v:26464$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26372$978_Y + connect \Y $not$libresoc.v:26464$970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26374$980 + cell $not $not$libresoc.v:26466$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26374$980_Y + connect \Y $not$libresoc.v:26466$972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26377$983 + cell $not $not$libresoc.v:26469$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26377$983_Y + connect \Y $not$libresoc.v:26469$975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26371$977 + cell $or $or$libresoc.v:26463$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40227,10 +40249,10 @@ module \alu_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26371$977_Y + connect \Y $or$libresoc.v:26463$969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26373$979 + cell $or $or$libresoc.v:26465$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40238,10 +40260,10 @@ module \alu_l$87 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26373$979_Y + connect \Y $or$libresoc.v:26465$971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26376$982 + cell $or $or$libresoc.v:26468$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40249,39 +40271,39 @@ module \alu_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26376$982_Y + connect \Y $or$libresoc.v:26468$974_Y end - attribute \src "libresoc.v:26335.7-26335.20" - process $proc$libresoc.v:26335$988 + attribute \src "libresoc.v:26427.7-26427.20" + process $proc$libresoc.v:26427$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26359.7-26359.19" - process $proc$libresoc.v:26359$989 + attribute \src "libresoc.v:26451.7-26451.19" + process $proc$libresoc.v:26451$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26378.3-26379.27" - process $proc$libresoc.v:26378$984 + attribute \src "libresoc.v:26470.3-26471.27" + process $proc$libresoc.v:26470$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26380.3-26388.6" - process $proc$libresoc.v:26380$985 + attribute \src "libresoc.v:26472.3-26480.6" + process $proc$libresoc.v:26472$977 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$986 $1\q_int$next[0:0]$987 - attribute \src "libresoc.v:26381.5-26381.29" + assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 + attribute \src "libresoc.v:26473.5-26473.29" switch \initial - attribute \src "libresoc.v:26381.9-26381.17" + attribute \src "libresoc.v:26473.9-26473.17" case 1'1 case end @@ -40290,38 +40312,38 @@ module \alu_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$987 1'0 + assign $1\q_int$next[0:0]$979 1'0 case - assign $1\q_int$next[0:0]$987 \$5 + assign $1\q_int$next[0:0]$979 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$986 + update \q_int$next $0\q_int$next[0:0]$978 end - connect \$9 $and$libresoc.v:26370$976_Y - connect \$11 $or$libresoc.v:26371$977_Y - connect \$13 $not$libresoc.v:26372$978_Y - connect \$15 $or$libresoc.v:26373$979_Y - connect \$1 $not$libresoc.v:26374$980_Y - connect \$3 $and$libresoc.v:26375$981_Y - connect \$5 $or$libresoc.v:26376$982_Y - connect \$7 $not$libresoc.v:26377$983_Y + connect \$9 $and$libresoc.v:26462$968_Y + connect \$11 $or$libresoc.v:26463$969_Y + connect \$13 $not$libresoc.v:26464$970_Y + connect \$15 $or$libresoc.v:26465$971_Y + connect \$1 $not$libresoc.v:26466$972_Y + connect \$3 $and$libresoc.v:26467$973_Y + connect \$5 $or$libresoc.v:26468$974_Y + connect \$7 $not$libresoc.v:26469$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26396.1-27391.10" +attribute \src "libresoc.v:26488.1-27483.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 3 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 22 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -40576,9 +40598,9 @@ module \alu_logical0 wire input 15 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \logical_op__zero_a$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \logical_pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe1_logical_op__data_len @@ -40842,9 +40864,9 @@ module \alu_logical0 wire \logical_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \logical_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \logical_pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \logical_pipe1_p_ready_o @@ -40854,19 +40876,19 @@ module \alu_logical0 wire width 64 \logical_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \logical_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \logical_pipe1_xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \logical_pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \logical_pipe2_cr_a$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \logical_pipe2_logical_op__data_len @@ -41130,21 +41152,21 @@ module \alu_logical0 wire \logical_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \logical_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \logical_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \logical_pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \logical_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire \logical_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \logical_pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid @@ -41154,10 +41176,10 @@ module \alu_logical0 wire input 5 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 4 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 30 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" @@ -41169,7 +41191,7 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:27251.17-27305.4" + attribute \src "libresoc.v:27343.17-27397.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41226,7 +41248,7 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27306.17-27361.4" + attribute \src "libresoc.v:27398.17-27453.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41284,14 +41306,14 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27362.10-27365.4" - cell \n$44 \n + attribute \src "libresoc.v:27454.10-27457.4" + cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:27366.10-27369.4" - cell \p$43 \p + attribute \src "libresoc.v:27458.10-27461.4" + cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end @@ -41317,19 +41339,19 @@ module \alu_logical0 connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end -attribute \src "libresoc.v:27395.1-28588.10" +attribute \src "libresoc.v:27487.1-28680.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -42054,9 +42076,9 @@ module \alu_mul0 wire \mul_pipe2_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe2_xer_so$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -42294,23 +42316,23 @@ module \alu_mul0 wire \mul_pipe3_neg_res32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul_pipe3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \mul_pipe3_o$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \mul_pipe3_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul_pipe3_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid @@ -42320,10 +42342,10 @@ module \alu_mul0 wire input 7 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 28 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" @@ -42332,18 +42354,18 @@ module \alu_mul0 wire width 64 input 24 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 25 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 26 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:28416.13-28457.4" + attribute \src "libresoc.v:28508.13-28549.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42387,7 +42409,7 @@ module \alu_mul0 connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28458.13-28500.4" + attribute \src "libresoc.v:28550.13-28592.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42432,7 +42454,7 @@ module \alu_mul0 connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28501.13-28546.4" + attribute \src "libresoc.v:28593.13-28638.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42480,14 +42502,14 @@ module \alu_mul0 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:28547.10-28550.4" - cell \n$89 \n + attribute \src "libresoc.v:28639.10-28642.4" + cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:28551.10-28554.4" - cell \p$88 \p + attribute \src "libresoc.v:28643.10-28646.4" + cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end @@ -42525,38 +42547,38 @@ module \alu_mul0 connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end -attribute \src "libresoc.v:28592.1-29591.10" +attribute \src "libresoc.v:28684.1-29699.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 + wire width 2 \muxid$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire input 6 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 32 \p_ready_o + wire output 33 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 31 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 32 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe1_muxid @@ -42566,9 +42588,9 @@ module \alu_shift_rot0 wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe1_p_ready_o @@ -42629,15 +42651,15 @@ module \alu_shift_rot0 attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry$12 + wire width 2 \pipe1_sr_op__input_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__input_cr$14 + wire \pipe1_sr_op__input_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe1_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn$18 + wire width 32 \pipe1_sr_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -42791,13 +42813,17 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \pipe1_sr_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__is_32bit$16 + wire \pipe1_sr_op__is_32bit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__is_signed$17 + wire \pipe1_sr_op__is_signed$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42809,11 +42835,11 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__output_carry$13 + wire \pipe1_sr_op__output_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__output_cr$15 + wire \pipe1_sr_op__output_cr$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -42826,42 +42852,42 @@ module \alu_shift_rot0 wire \pipe1_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe1_sr_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe1_xer_so$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_cr_a_ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe2_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$21 + wire width 2 \pipe2_muxid$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire \pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" @@ -42895,15 +42921,15 @@ module \alu_shift_rot0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_sr_op__fn_unit$23 + wire width 12 \pipe2_sr_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \pipe2_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_sr_op__imm_data__data$24 + wire width 64 \pipe2_sr_op__imm_data__data$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__imm_data__ok$25 + wire \pipe2_sr_op__imm_data__ok$26 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -42915,15 +42941,15 @@ module \alu_shift_rot0 attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_sr_op__input_carry$31 + wire width 2 \pipe2_sr_op__input_carry$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__input_cr$33 + wire \pipe2_sr_op__input_cr$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 \pipe2_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_sr_op__insn$37 + wire width 32 \pipe2_sr_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -43075,61 +43101,65 @@ module \alu_shift_rot0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_sr_op__insn_type$22 + wire width 7 \pipe2_sr_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_32bit$35 + wire \pipe2_sr_op__is_32bit$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_signed$36 + wire \pipe2_sr_op__is_signed$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__oe__oe$28 + wire \pipe2_sr_op__oe__oe$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__oe__ok$29 + wire \pipe2_sr_op__oe__ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_carry$32 + wire \pipe2_sr_op__output_carry$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__output_cr$34 + wire \pipe2_sr_op__output_cr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__ok$27 + wire \pipe2_sr_op__rc__ok$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__rc__rc$26 + wire \pipe2_sr_op__rc__rc$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \pipe2_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__write_cr0$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_sr_op__write_cr0$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe2_xer_ca_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe2_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra + wire width 64 input 27 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb + wire width 64 input 28 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rc + wire width 64 input 29 \rc attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -43159,35 +43189,35 @@ module \alu_shift_rot0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$46 + wire width 12 \sr_op__fn_unit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 9 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$47 + wire width 64 \sr_op__imm_data__data$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 10 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$48 + wire \sr_op__imm_data__ok$50 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \sr_op__input_carry + wire width 2 input 17 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$54 + wire width 2 \sr_op__input_carry$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__input_cr + wire input 19 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$56 + wire \sr_op__input_cr$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \sr_op__insn + wire width 32 input 23 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$60 + wire width 32 \sr_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -43339,66 +43369,70 @@ module \alu_shift_rot0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$45 + wire width 7 \sr_op__insn_type$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__is_32bit + wire \sr_op__invert_in$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$58 + wire input 21 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \sr_op__is_signed + wire \sr_op__is_32bit$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$59 + wire input 22 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 13 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$51 + wire \sr_op__oe__oe$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$52 + wire \sr_op__oe__ok$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__output_carry + wire input 18 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$55 + wire \sr_op__output_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__output_cr + wire input 20 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$57 + wire \sr_op__output_cr$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 12 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$50 + wire \sr_op__rc__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 11 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$49 + wire \sr_op__rc__rc$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 15 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 25 \xer_ca + wire \sr_op__write_cr0$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 30 \xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ca_ok + wire width 2 input 31 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 29 \xer_so + wire input 30 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:29447.11-29450.4" - cell \n$106 \n + attribute \src "libresoc.v:29551.11-29554.4" + cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29451.11-29454.4" - cell \p$105 \p + attribute \src "libresoc.v:29555.11-29558.4" + cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:29455.15-29509.4" - cell \pipe1$107 \pipe1 + attribute \src "libresoc.v:29559.15-29615.4" + cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe1_cr_a @@ -43421,25 +43455,27 @@ module \alu_shift_rot0 connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 connect \sr_op__input_carry \pipe1_sr_op__input_carry - connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 + connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 connect \sr_op__input_cr \pipe1_sr_op__input_cr - connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 + connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 connect \sr_op__insn \pipe1_sr_op__insn - connect \sr_op__insn$17 \pipe1_sr_op__insn$18 + connect \sr_op__insn$18 \pipe1_sr_op__insn$19 connect \sr_op__insn_type \pipe1_sr_op__insn_type connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__invert_in \pipe1_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 connect \sr_op__is_32bit \pipe1_sr_op__is_32bit - connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 + connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 connect \sr_op__is_signed \pipe1_sr_op__is_signed - connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 + connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 connect \sr_op__oe__oe \pipe1_sr_op__oe__oe connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 connect \sr_op__oe__ok \pipe1_sr_op__oe__ok connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 connect \sr_op__output_carry \pipe1_sr_op__output_carry - connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 + connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 connect \sr_op__output_cr \pipe1_sr_op__output_cr - connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 + connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 connect \sr_op__rc__ok \pipe1_sr_op__rc__ok connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 connect \sr_op__rc__rc \pipe1_sr_op__rc__rc @@ -43447,84 +43483,86 @@ module \alu_shift_rot0 connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 connect \xer_ca \pipe1_xer_ca - connect \xer_ca$19 \pipe1_xer_ca$20 + connect \xer_ca$20 \pipe1_xer_ca$21 connect \xer_ca_ok \pipe1_xer_ca_ok connect \xer_so \pipe1_xer_so - connect \xer_so$18 \pipe1_xer_so$19 + connect \xer_so$19 \pipe1_xer_so$20 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:29510.15-29565.4" - cell \pipe2$112 \pipe2 + attribute \src "libresoc.v:29616.15-29673.4" + cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a \pipe2_cr_a - connect \cr_a$20 \pipe2_cr_a$40 + connect \cr_a$21 \pipe2_cr_a$42 connect \cr_a_ok \pipe2_cr_a_ok - connect \cr_a_ok$21 \pipe2_cr_a_ok$41 + connect \cr_a_ok$22 \pipe2_cr_a_ok$43 connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$21 + connect \muxid$1 \pipe2_muxid$22 connect \n_ready_i \pipe2_n_ready_i connect \n_valid_o \pipe2_n_valid_o connect \o \pipe2_o - connect \o$18 \pipe2_o$38 + connect \o$19 \pipe2_o$40 connect \o_ok \pipe2_o_ok - connect \o_ok$19 \pipe2_o_ok$39 + connect \o_ok$20 \pipe2_o_ok$41 connect \p_ready_o \pipe2_p_ready_o connect \p_valid_i \pipe2_p_valid_i connect \sr_op__fn_unit \pipe2_sr_op__fn_unit - connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 connect \sr_op__input_carry \pipe2_sr_op__input_carry - connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 + connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 connect \sr_op__input_cr \pipe2_sr_op__input_cr - connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 + connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 connect \sr_op__insn \pipe2_sr_op__insn - connect \sr_op__insn$17 \pipe2_sr_op__insn$37 + connect \sr_op__insn$18 \pipe2_sr_op__insn$39 connect \sr_op__insn_type \pipe2_sr_op__insn_type - connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 + connect \sr_op__invert_in \pipe2_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 connect \sr_op__is_32bit \pipe2_sr_op__is_32bit - connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 + connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 connect \sr_op__is_signed \pipe2_sr_op__is_signed - connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 + connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 connect \sr_op__oe__oe \pipe2_sr_op__oe__oe - connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 connect \sr_op__oe__ok \pipe2_sr_op__oe__ok - connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 connect \sr_op__output_carry \pipe2_sr_op__output_carry - connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 + connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 connect \sr_op__output_cr \pipe2_sr_op__output_cr - connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 + connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 connect \sr_op__rc__ok \pipe2_sr_op__rc__ok - connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 connect \sr_op__rc__rc \pipe2_sr_op__rc__rc - connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 connect \xer_ca \pipe2_xer_ca - connect \xer_ca$22 \pipe2_xer_ca$42 + connect \xer_ca$23 \pipe2_xer_ca$44 connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 + connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 connect \xer_so \pipe2_xer_so connect \xer_so_ok \pipe2_xer_so_ok end connect \muxid 2'00 - connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } - connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } - connect { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } - connect { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 \sr_op__oe__ok$52 \sr_op__oe__oe$51 \sr_op__rc__ok$50 \sr_op__rc__rc$49 \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } - connect \muxid$44 \pipe2_muxid$21 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } + connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } + connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } + connect \muxid$46 \pipe2_muxid$22 connect \pipe2_n_ready_i \n_ready_i connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_xer_ca$20 \xer_ca$1 - connect \pipe1_xer_so$19 \xer_so + connect \pipe1_xer_ca$21 \xer_ca$1 + connect \pipe1_xer_so$20 \xer_so connect \pipe1_rc \rc connect \pipe1_rb \rb connect \pipe1_ra \ra - connect { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \pipe1_muxid$2 2'00 connect \p_ready_o \pipe1_p_ready_o connect \pipe1_p_valid_i \p_valid_i @@ -43532,26 +43570,26 @@ module \alu_shift_rot0 connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } connect \pipe2_muxid \pipe1_muxid connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:29595.1-30141.10" +attribute \src "libresoc.v:29703.1-30249.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 7 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 22 \fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" @@ -43560,19 +43598,19 @@ module \alu_spr0 wire input 9 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 27 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe_muxid @@ -43582,9 +43620,9 @@ module \alu_spr0 wire \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \pipe_p_ready_o @@ -43594,9 +43632,9 @@ module \alu_spr0 wire width 64 \pipe_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -43790,30 +43828,30 @@ module \alu_spr0 wire \pipe_spr_op__is_32bit$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \pipe_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pipe_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 15 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 6 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -44004,39 +44042,39 @@ module \alu_spr0 wire input 13 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \spr_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 19 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 18 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 24 \xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 23 \xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:30076.10-30079.4" - cell \n$60 \n + attribute \src "libresoc.v:30184.10-30187.4" + cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30080.10-30083.4" - cell \p$59 \p + attribute \src "libresoc.v:30188.10-30191.4" + cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30084.13-30119.4" - cell \pipe$61 \pipe + attribute \src "libresoc.v:30192.13-30227.4" + cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \fast1 \pipe_fast1 @@ -44094,95 +44132,83 @@ module \alu_spr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:30145.1-30708.10" +attribute \src "libresoc.v:30253.1-31108.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 19 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 19 \fast2 + wire width 64 input 25 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 5 \msr_ok + wire width 64 input 26 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 + wire width 2 \muxid$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire input 8 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 27 \p_ready_o + wire output 28 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 26 \p_valid_i + wire input 27 \p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast1_ok + wire width 64 \pipe1_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_msr_ok + wire width 64 \pipe1_fast1$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid + wire width 2 \pipe1_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 + wire width 2 \pipe1_muxid$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i + wire \pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \pipe_o_ok + wire \pipe1_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o + wire \pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i + wire \pipe1_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra + wire width 64 \pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb + wire width 64 \pipe1_ra$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia + wire width 64 \pipe1_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia$8 + wire width 64 \pipe1_trap_op__cia$8 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -44197,7 +44223,7 @@ module \alu_trap0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_trap_op__fn_unit + wire width 12 \pipe1_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -44212,11 +44238,11 @@ module \alu_trap0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_trap_op__fn_unit$5 + wire width 12 \pipe1_trap_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn + wire width 32 \pipe1_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn$6 + wire width 32 \pipe1_trap_op__insn$6 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -44292,7 +44318,7 @@ module \alu_trap0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type + wire width 7 \pipe1_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -44368,31 +44394,285 @@ module \alu_trap0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type$4 + wire width 7 \pipe1_trap_op__insn_type$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_trap_op__is_32bit + wire \pipe1_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_trap_op__is_32bit$9 + wire \pipe1_trap_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr + wire width 8 \pipe1_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr$7 + wire width 8 \pipe1_trap_op__ldst_exc$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr + wire width 64 \pipe1_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr$11 + wire width 64 \pipe1_trap_op__msr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype + wire width 13 \pipe1_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype$10 + wire width 13 \pipe1_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe1_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_fast2$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__cia$22 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_trap_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_trap_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \ra + wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \rb + wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 13 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$19 + wire width 64 \trap_op__cia$34 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -44422,11 +44702,11 @@ module \alu_trap0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$16 + wire width 12 \trap_op__fn_unit$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 11 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$17 + wire width 32 \trap_op__insn$32 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -44578,127 +44858,179 @@ module \alu_trap0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$15 + wire width 7 \trap_op__insn_type$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 14 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$20 + wire \trap_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 17 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 12 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$18 + wire width 64 \trap_op__msr$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 input 16 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$22 + wire width 13 \trap_op__trapaddr$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 15 \trap_op__traptype + wire width 8 input 15 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$21 + wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 - attribute \src "libresoc.v:30642.10-30645.4" + attribute \src "libresoc.v:30996.10-30999.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30646.10-30649.4" + attribute \src "libresoc.v:31000.10-31003.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30650.13-30689.4" - cell \pipe$32 \pipe + attribute \src "libresoc.v:31004.14-31039.4" + cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \fast1 \pipe_fast1 - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2 \pipe_fast2 - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \msr \pipe_msr - connect \msr_ok \pipe_msr_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \trap_op__cia \pipe_trap_op__cia - connect \trap_op__cia$6 \pipe_trap_op__cia$8 - connect \trap_op__fn_unit \pipe_trap_op__fn_unit - connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 - connect \trap_op__insn \pipe_trap_op__insn - connect \trap_op__insn$4 \pipe_trap_op__insn$6 - connect \trap_op__insn_type \pipe_trap_op__insn_type - connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 - connect \trap_op__is_32bit \pipe_trap_op__is_32bit - connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 - connect \trap_op__msr \pipe_trap_op__msr - connect \trap_op__msr$5 \pipe_trap_op__msr$7 - connect \trap_op__trapaddr \pipe_trap_op__trapaddr - connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 - connect \trap_op__traptype \pipe_trap_op__traptype - connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 + connect \fast1 \pipe1_fast1 + connect \fast1$13 \pipe1_fast1$15 + connect \fast2 \pipe1_fast2 + connect \fast2$14 \pipe1_fast2$16 + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \ra$11 \pipe1_ra$13 + connect \rb \pipe1_rb + connect \rb$12 \pipe1_rb$14 + connect \trap_op__cia \pipe1_trap_op__cia + connect \trap_op__cia$6 \pipe1_trap_op__cia$8 + connect \trap_op__fn_unit \pipe1_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 + connect \trap_op__insn \pipe1_trap_op__insn + connect \trap_op__insn$4 \pipe1_trap_op__insn$6 + connect \trap_op__insn_type \pipe1_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe1_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 + connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 + connect \trap_op__msr \pipe1_trap_op__msr + connect \trap_op__msr$5 \pipe1_trap_op__msr$7 + connect \trap_op__trapaddr \pipe1_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe1_trap_op__traptype + connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31040.14-31081.4" + cell \pipe2$35 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe2_fast1 + connect \fast1$11 \pipe2_fast1$27 + connect \fast1_ok \pipe2_fast1_ok + connect \fast2 \pipe2_fast2 + connect \fast2$12 \pipe2_fast2$28 + connect \fast2_ok \pipe2_fast2_ok + connect \msr \pipe2_msr + connect \msr_ok \pipe2_msr_ok + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$17 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \nia \pipe2_nia + connect \nia_ok \pipe2_nia_ok + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \ra \pipe2_ra + connect \rb \pipe2_rb + connect \trap_op__cia \pipe2_trap_op__cia + connect \trap_op__cia$6 \pipe2_trap_op__cia$22 + connect \trap_op__fn_unit \pipe2_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 + connect \trap_op__insn \pipe2_trap_op__insn + connect \trap_op__insn$4 \pipe2_trap_op__insn$20 + connect \trap_op__insn_type \pipe2_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 + connect \trap_op__is_32bit \pipe2_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 + connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 + connect \trap_op__msr \pipe2_trap_op__msr + connect \trap_op__msr$5 \pipe2_trap_op__msr$21 + connect \trap_op__trapaddr \pipe2_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 + connect \trap_op__traptype \pipe2_trap_op__traptype + connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 end connect \muxid 2'00 - connect { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } - connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } - connect \muxid$14 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_fast2 \fast2$2 - connect \pipe_fast1 \fast1$1 - connect \pipe_rb \rb - connect \pipe_ra \ra - connect { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i + connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } + connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } + connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } + connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } + connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } + connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } + connect \muxid$29 \pipe2_muxid$17 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_fast2$16 \fast2$2 + connect \pipe1_fast1$15 \fast1$1 + connect \pipe1_rb$14 \rb + connect \pipe1_ra$13 \ra + connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect \pipe2_fast2 \pipe1_fast2 + connect \pipe2_fast1 \pipe1_fast1 + connect \pipe2_rb \pipe1_rb + connect \pipe2_ra \pipe1_ra + connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:30712.1-30770.10" +attribute \src "libresoc.v:31112.1-31170.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l - attribute \src "libresoc.v:30713.7-30713.20" + attribute \src "libresoc.v:31113.7-31113.20" wire $0\initial[0:0] - attribute \src "libresoc.v:30758.3-30766.6" - wire $0\q_int$next[0:0]$1000 - attribute \src "libresoc.v:30756.3-30757.27" + attribute \src "libresoc.v:31158.3-31166.6" + wire $0\q_int$next[0:0]$992 + attribute \src "libresoc.v:31156.3-31157.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:30758.3-30766.6" - wire $1\q_int$next[0:0]$1001 - attribute \src "libresoc.v:30737.7-30737.19" + attribute \src "libresoc.v:31158.3-31166.6" + wire $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31137.7-31137.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:30748.17-30748.96" - wire $and$libresoc.v:30748$990_Y - attribute \src "libresoc.v:30753.17-30753.96" - wire $and$libresoc.v:30753$995_Y - attribute \src "libresoc.v:30750.18-30750.94" - wire $not$libresoc.v:30750$992_Y - attribute \src "libresoc.v:30752.17-30752.93" - wire $not$libresoc.v:30752$994_Y - attribute \src "libresoc.v:30755.17-30755.93" - wire $not$libresoc.v:30755$997_Y - attribute \src "libresoc.v:30749.18-30749.99" - wire $or$libresoc.v:30749$991_Y - attribute \src "libresoc.v:30751.18-30751.100" - wire $or$libresoc.v:30751$993_Y - attribute \src "libresoc.v:30754.17-30754.98" - wire $or$libresoc.v:30754$996_Y + attribute \src "libresoc.v:31148.17-31148.96" + wire $and$libresoc.v:31148$982_Y + attribute \src "libresoc.v:31153.17-31153.96" + wire $and$libresoc.v:31153$987_Y + attribute \src "libresoc.v:31150.18-31150.94" + wire $not$libresoc.v:31150$984_Y + attribute \src "libresoc.v:31152.17-31152.93" + wire $not$libresoc.v:31152$986_Y + attribute \src "libresoc.v:31155.17-31155.93" + wire $not$libresoc.v:31155$989_Y + attribute \src "libresoc.v:31149.18-31149.99" + wire $or$libresoc.v:31149$983_Y + attribute \src "libresoc.v:31151.18-31151.100" + wire $or$libresoc.v:31151$985_Y + attribute \src "libresoc.v:31154.17-31154.98" + wire $or$libresoc.v:31154$988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -44715,11 +45047,11 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:30713.7-30713.15" + attribute \src "libresoc.v:31113.7-31113.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -44736,7 +45068,7 @@ module \alui_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:30748$990 + cell $and $and$libresoc.v:31148$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44744,10 +45076,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:30748$990_Y + connect \Y $and$libresoc.v:31148$982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:30753$995 + cell $and $and$libresoc.v:31153$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44755,34 +45087,34 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:30753$995_Y + connect \Y $and$libresoc.v:31153$987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:30750$992 + cell $not $not$libresoc.v:31150$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:30750$992_Y + connect \Y $not$libresoc.v:31150$984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:30752$994 + cell $not $not$libresoc.v:31152$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30752$994_Y + connect \Y $not$libresoc.v:31152$986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:30755$997 + cell $not $not$libresoc.v:31155$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30755$997_Y + connect \Y $not$libresoc.v:31155$989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:30749$991 + cell $or $or$libresoc.v:31149$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44790,10 +45122,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:30749$991_Y + connect \Y $or$libresoc.v:31149$983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:30751$993 + cell $or $or$libresoc.v:31151$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44801,10 +45133,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:30751$993_Y + connect \Y $or$libresoc.v:31151$985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:30754$996 + cell $or $or$libresoc.v:31154$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44812,39 +45144,39 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:30754$996_Y + connect \Y $or$libresoc.v:31154$988_Y end - attribute \src "libresoc.v:30713.7-30713.20" - process $proc$libresoc.v:30713$1002 + attribute \src "libresoc.v:31113.7-31113.20" + process $proc$libresoc.v:31113$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30737.7-30737.19" - process $proc$libresoc.v:30737$1003 + attribute \src "libresoc.v:31137.7-31137.19" + process $proc$libresoc.v:31137$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:30756.3-30757.27" - process $proc$libresoc.v:30756$998 + attribute \src "libresoc.v:31156.3-31157.27" + process $proc$libresoc.v:31156$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:30758.3-30766.6" - process $proc$libresoc.v:30758$999 + attribute \src "libresoc.v:31158.3-31166.6" + process $proc$libresoc.v:31158$991 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1000 $1\q_int$next[0:0]$1001 - attribute \src "libresoc.v:30759.5-30759.29" + assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31159.5-31159.29" switch \initial - attribute \src "libresoc.v:30759.9-30759.17" + attribute \src "libresoc.v:31159.9-31159.17" case 1'1 case end @@ -44853,56 +45185,56 @@ module \alui_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1001 1'0 + assign $1\q_int$next[0:0]$993 1'0 case - assign $1\q_int$next[0:0]$1001 \$5 + assign $1\q_int$next[0:0]$993 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1000 + update \q_int$next $0\q_int$next[0:0]$992 end - connect \$9 $and$libresoc.v:30748$990_Y - connect \$11 $or$libresoc.v:30749$991_Y - connect \$13 $not$libresoc.v:30750$992_Y - connect \$15 $or$libresoc.v:30751$993_Y - connect \$1 $not$libresoc.v:30752$994_Y - connect \$3 $and$libresoc.v:30753$995_Y - connect \$5 $or$libresoc.v:30754$996_Y - connect \$7 $not$libresoc.v:30755$997_Y + connect \$9 $and$libresoc.v:31148$982_Y + connect \$11 $or$libresoc.v:31149$983_Y + connect \$13 $not$libresoc.v:31150$984_Y + connect \$15 $or$libresoc.v:31151$985_Y + connect \$1 $not$libresoc.v:31152$986_Y + connect \$3 $and$libresoc.v:31153$987_Y + connect \$5 $or$libresoc.v:31154$988_Y + connect \$7 $not$libresoc.v:31155$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:30774.1-30832.10" +attribute \src "libresoc.v:31174.1-31232.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" -module \alui_l$103 - attribute \src "libresoc.v:30775.7-30775.20" +module \alui_l$106 + attribute \src "libresoc.v:31175.7-31175.20" wire $0\initial[0:0] - attribute \src "libresoc.v:30820.3-30828.6" - wire $0\q_int$next[0:0]$1014 - attribute \src "libresoc.v:30818.3-30819.27" + attribute \src "libresoc.v:31220.3-31228.6" + wire $0\q_int$next[0:0]$1006 + attribute \src "libresoc.v:31218.3-31219.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:30820.3-30828.6" - wire $1\q_int$next[0:0]$1015 - attribute \src "libresoc.v:30799.7-30799.19" + attribute \src "libresoc.v:31220.3-31228.6" + wire $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31199.7-31199.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:30810.17-30810.96" - wire $and$libresoc.v:30810$1004_Y - attribute \src "libresoc.v:30815.17-30815.96" - wire $and$libresoc.v:30815$1009_Y - attribute \src "libresoc.v:30812.18-30812.94" - wire $not$libresoc.v:30812$1006_Y - attribute \src "libresoc.v:30814.17-30814.93" - wire $not$libresoc.v:30814$1008_Y - attribute \src "libresoc.v:30817.17-30817.93" - wire $not$libresoc.v:30817$1011_Y - attribute \src "libresoc.v:30811.18-30811.99" - wire $or$libresoc.v:30811$1005_Y - attribute \src "libresoc.v:30813.18-30813.100" - wire $or$libresoc.v:30813$1007_Y - attribute \src "libresoc.v:30816.17-30816.98" - wire $or$libresoc.v:30816$1010_Y + attribute \src "libresoc.v:31210.17-31210.96" + wire $and$libresoc.v:31210$996_Y + attribute \src "libresoc.v:31215.17-31215.96" + wire $and$libresoc.v:31215$1001_Y + attribute \src "libresoc.v:31212.18-31212.94" + wire $not$libresoc.v:31212$998_Y + attribute \src "libresoc.v:31214.17-31214.93" + wire $not$libresoc.v:31214$1000_Y + attribute \src "libresoc.v:31217.17-31217.93" + wire $not$libresoc.v:31217$1003_Y + attribute \src "libresoc.v:31211.18-31211.99" + wire $or$libresoc.v:31211$997_Y + attribute \src "libresoc.v:31213.18-31213.100" + wire $or$libresoc.v:31213$999_Y + attribute \src "libresoc.v:31216.17-31216.98" + wire $or$libresoc.v:31216$1002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -44919,11 +45251,11 @@ module \alui_l$103 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:30775.7-30775.15" + attribute \src "libresoc.v:31175.7-31175.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -44940,7 +45272,7 @@ module \alui_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:30810$1004 + cell $and $and$libresoc.v:31210$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44948,10 +45280,10 @@ module \alui_l$103 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:30810$1004_Y + connect \Y $and$libresoc.v:31210$996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:30815$1009 + cell $and $and$libresoc.v:31215$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44959,34 +45291,34 @@ module \alui_l$103 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:30815$1009_Y + connect \Y $and$libresoc.v:31215$1001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:30812$1006 + cell $not $not$libresoc.v:31212$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:30812$1006_Y + connect \Y $not$libresoc.v:31212$998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:30814$1008 + cell $not $not$libresoc.v:31214$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30814$1008_Y + connect \Y $not$libresoc.v:31214$1000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:30817$1011 + cell $not $not$libresoc.v:31217$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30817$1011_Y + connect \Y $not$libresoc.v:31217$1003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:30811$1005 + cell $or $or$libresoc.v:31211$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -44994,10 +45326,10 @@ module \alui_l$103 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:30811$1005_Y + connect \Y $or$libresoc.v:31211$997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:30813$1007 + cell $or $or$libresoc.v:31213$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45005,10 +45337,10 @@ module \alui_l$103 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:30813$1007_Y + connect \Y $or$libresoc.v:31213$999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:30816$1010 + cell $or $or$libresoc.v:31216$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45016,39 +45348,39 @@ module \alui_l$103 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:30816$1010_Y + connect \Y $or$libresoc.v:31216$1002_Y end - attribute \src "libresoc.v:30775.7-30775.20" - process $proc$libresoc.v:30775$1016 + attribute \src "libresoc.v:31175.7-31175.20" + process $proc$libresoc.v:31175$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30799.7-30799.19" - process $proc$libresoc.v:30799$1017 + attribute \src "libresoc.v:31199.7-31199.19" + process $proc$libresoc.v:31199$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:30818.3-30819.27" - process $proc$libresoc.v:30818$1012 + attribute \src "libresoc.v:31218.3-31219.27" + process $proc$libresoc.v:31218$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:30820.3-30828.6" - process $proc$libresoc.v:30820$1013 + attribute \src "libresoc.v:31220.3-31228.6" + process $proc$libresoc.v:31220$1005 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1014 $1\q_int$next[0:0]$1015 - attribute \src "libresoc.v:30821.5-30821.29" + assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31221.5-31221.29" switch \initial - attribute \src "libresoc.v:30821.9-30821.17" + attribute \src "libresoc.v:31221.9-31221.17" case 1'1 case end @@ -45057,56 +45389,56 @@ module \alui_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1015 1'0 + assign $1\q_int$next[0:0]$1007 1'0 case - assign $1\q_int$next[0:0]$1015 \$5 + assign $1\q_int$next[0:0]$1007 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1014 + update \q_int$next $0\q_int$next[0:0]$1006 end - connect \$9 $and$libresoc.v:30810$1004_Y - connect \$11 $or$libresoc.v:30811$1005_Y - connect \$13 $not$libresoc.v:30812$1006_Y - connect \$15 $or$libresoc.v:30813$1007_Y - connect \$1 $not$libresoc.v:30814$1008_Y - connect \$3 $and$libresoc.v:30815$1009_Y - connect \$5 $or$libresoc.v:30816$1010_Y - connect \$7 $not$libresoc.v:30817$1011_Y + connect \$9 $and$libresoc.v:31210$996_Y + connect \$11 $or$libresoc.v:31211$997_Y + connect \$13 $not$libresoc.v:31212$998_Y + connect \$15 $or$libresoc.v:31213$999_Y + connect \$1 $not$libresoc.v:31214$1000_Y + connect \$3 $and$libresoc.v:31215$1001_Y + connect \$5 $or$libresoc.v:31216$1002_Y + connect \$7 $not$libresoc.v:31217$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:30836.1-30894.10" +attribute \src "libresoc.v:31236.1-31294.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" -module \alui_l$121 - attribute \src "libresoc.v:30837.7-30837.20" +module \alui_l$124 + attribute \src "libresoc.v:31237.7-31237.20" wire $0\initial[0:0] - attribute \src "libresoc.v:30882.3-30890.6" - wire $0\q_int$next[0:0]$1028 - attribute \src "libresoc.v:30880.3-30881.27" + attribute \src "libresoc.v:31282.3-31290.6" + wire $0\q_int$next[0:0]$1020 + attribute \src "libresoc.v:31280.3-31281.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:30882.3-30890.6" - wire $1\q_int$next[0:0]$1029 - attribute \src "libresoc.v:30861.7-30861.19" + attribute \src "libresoc.v:31282.3-31290.6" + wire $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31261.7-31261.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:30872.17-30872.96" - wire $and$libresoc.v:30872$1018_Y - attribute \src "libresoc.v:30877.17-30877.96" - wire $and$libresoc.v:30877$1023_Y - attribute \src "libresoc.v:30874.18-30874.94" - wire $not$libresoc.v:30874$1020_Y - attribute \src "libresoc.v:30876.17-30876.93" - wire $not$libresoc.v:30876$1022_Y - attribute \src "libresoc.v:30879.17-30879.93" - wire $not$libresoc.v:30879$1025_Y - attribute \src "libresoc.v:30873.18-30873.99" - wire $or$libresoc.v:30873$1019_Y - attribute \src "libresoc.v:30875.18-30875.100" - wire $or$libresoc.v:30875$1021_Y - attribute \src "libresoc.v:30878.17-30878.98" - wire $or$libresoc.v:30878$1024_Y + attribute \src "libresoc.v:31272.17-31272.96" + wire $and$libresoc.v:31272$1010_Y + attribute \src "libresoc.v:31277.17-31277.96" + wire $and$libresoc.v:31277$1015_Y + attribute \src "libresoc.v:31274.18-31274.94" + wire $not$libresoc.v:31274$1012_Y + attribute \src "libresoc.v:31276.17-31276.93" + wire $not$libresoc.v:31276$1014_Y + attribute \src "libresoc.v:31279.17-31279.93" + wire $not$libresoc.v:31279$1017_Y + attribute \src "libresoc.v:31273.18-31273.99" + wire $or$libresoc.v:31273$1011_Y + attribute \src "libresoc.v:31275.18-31275.100" + wire $or$libresoc.v:31275$1013_Y + attribute \src "libresoc.v:31278.17-31278.98" + wire $or$libresoc.v:31278$1016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -45123,11 +45455,11 @@ module \alui_l$121 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:30837.7-30837.15" + attribute \src "libresoc.v:31237.7-31237.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -45144,7 +45476,7 @@ module \alui_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:30872$1018 + cell $and $and$libresoc.v:31272$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45152,10 +45484,10 @@ module \alui_l$121 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:30872$1018_Y + connect \Y $and$libresoc.v:31272$1010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:30877$1023 + cell $and $and$libresoc.v:31277$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45163,34 +45495,34 @@ module \alui_l$121 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:30877$1023_Y + connect \Y $and$libresoc.v:31277$1015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:30874$1020 + cell $not $not$libresoc.v:31274$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:30874$1020_Y + connect \Y $not$libresoc.v:31274$1012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:30876$1022 + cell $not $not$libresoc.v:31276$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30876$1022_Y + connect \Y $not$libresoc.v:31276$1014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:30879$1025 + cell $not $not$libresoc.v:31279$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30879$1025_Y + connect \Y $not$libresoc.v:31279$1017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:30873$1019 + cell $or $or$libresoc.v:31273$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45198,10 +45530,10 @@ module \alui_l$121 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:30873$1019_Y + connect \Y $or$libresoc.v:31273$1011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:30875$1021 + cell $or $or$libresoc.v:31275$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45209,10 +45541,10 @@ module \alui_l$121 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:30875$1021_Y + connect \Y $or$libresoc.v:31275$1013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:30878$1024 + cell $or $or$libresoc.v:31278$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45220,39 +45552,39 @@ module \alui_l$121 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:30878$1024_Y + connect \Y $or$libresoc.v:31278$1016_Y end - attribute \src "libresoc.v:30837.7-30837.20" - process $proc$libresoc.v:30837$1030 + attribute \src "libresoc.v:31237.7-31237.20" + process $proc$libresoc.v:31237$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30861.7-30861.19" - process $proc$libresoc.v:30861$1031 + attribute \src "libresoc.v:31261.7-31261.19" + process $proc$libresoc.v:31261$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:30880.3-30881.27" - process $proc$libresoc.v:30880$1026 + attribute \src "libresoc.v:31280.3-31281.27" + process $proc$libresoc.v:31280$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:30882.3-30890.6" - process $proc$libresoc.v:30882$1027 + attribute \src "libresoc.v:31282.3-31290.6" + process $proc$libresoc.v:31282$1019 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1028 $1\q_int$next[0:0]$1029 - attribute \src "libresoc.v:30883.5-30883.29" + assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31283.5-31283.29" switch \initial - attribute \src "libresoc.v:30883.9-30883.17" + attribute \src "libresoc.v:31283.9-31283.17" case 1'1 case end @@ -45261,56 +45593,56 @@ module \alui_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1029 1'0 + assign $1\q_int$next[0:0]$1021 1'0 case - assign $1\q_int$next[0:0]$1029 \$5 + assign $1\q_int$next[0:0]$1021 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1028 + update \q_int$next $0\q_int$next[0:0]$1020 end - connect \$9 $and$libresoc.v:30872$1018_Y - connect \$11 $or$libresoc.v:30873$1019_Y - connect \$13 $not$libresoc.v:30874$1020_Y - connect \$15 $or$libresoc.v:30875$1021_Y - connect \$1 $not$libresoc.v:30876$1022_Y - connect \$3 $and$libresoc.v:30877$1023_Y - connect \$5 $or$libresoc.v:30878$1024_Y - connect \$7 $not$libresoc.v:30879$1025_Y + connect \$9 $and$libresoc.v:31272$1010_Y + connect \$11 $or$libresoc.v:31273$1011_Y + connect \$13 $not$libresoc.v:31274$1012_Y + connect \$15 $or$libresoc.v:31275$1013_Y + connect \$1 $not$libresoc.v:31276$1014_Y + connect \$3 $and$libresoc.v:31277$1015_Y + connect \$5 $or$libresoc.v:31278$1016_Y + connect \$7 $not$libresoc.v:31279$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:30898.1-30956.10" +attribute \src "libresoc.v:31298.1-31356.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 - attribute \src "libresoc.v:30899.7-30899.20" + attribute \src "libresoc.v:31299.7-31299.20" wire $0\initial[0:0] - attribute \src "libresoc.v:30944.3-30952.6" - wire $0\q_int$next[0:0]$1042 - attribute \src "libresoc.v:30942.3-30943.27" + attribute \src "libresoc.v:31344.3-31352.6" + wire $0\q_int$next[0:0]$1034 + attribute \src "libresoc.v:31342.3-31343.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:30944.3-30952.6" - wire $1\q_int$next[0:0]$1043 - attribute \src "libresoc.v:30923.7-30923.19" + attribute \src "libresoc.v:31344.3-31352.6" + wire $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31323.7-31323.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:30934.17-30934.96" - wire $and$libresoc.v:30934$1032_Y - attribute \src "libresoc.v:30939.17-30939.96" - wire $and$libresoc.v:30939$1037_Y - attribute \src "libresoc.v:30936.18-30936.94" - wire $not$libresoc.v:30936$1034_Y - attribute \src "libresoc.v:30938.17-30938.93" - wire $not$libresoc.v:30938$1036_Y - attribute \src "libresoc.v:30941.17-30941.93" - wire $not$libresoc.v:30941$1039_Y - attribute \src "libresoc.v:30935.18-30935.99" - wire $or$libresoc.v:30935$1033_Y - attribute \src "libresoc.v:30937.18-30937.100" - wire $or$libresoc.v:30937$1035_Y - attribute \src "libresoc.v:30940.17-30940.98" - wire $or$libresoc.v:30940$1038_Y + attribute \src "libresoc.v:31334.17-31334.96" + wire $and$libresoc.v:31334$1024_Y + attribute \src "libresoc.v:31339.17-31339.96" + wire $and$libresoc.v:31339$1029_Y + attribute \src "libresoc.v:31336.18-31336.94" + wire $not$libresoc.v:31336$1026_Y + attribute \src "libresoc.v:31338.17-31338.93" + wire $not$libresoc.v:31338$1028_Y + attribute \src "libresoc.v:31341.17-31341.93" + wire $not$libresoc.v:31341$1031_Y + attribute \src "libresoc.v:31335.18-31335.99" + wire $or$libresoc.v:31335$1025_Y + attribute \src "libresoc.v:31337.18-31337.100" + wire $or$libresoc.v:31337$1027_Y + attribute \src "libresoc.v:31340.17-31340.98" + wire $or$libresoc.v:31340$1030_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -45327,11 +45659,11 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:30899.7-30899.15" + attribute \src "libresoc.v:31299.7-31299.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -45348,7 +45680,7 @@ module \alui_l$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:30934$1032 + cell $and $and$libresoc.v:31334$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45356,10 +45688,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:30934$1032_Y + connect \Y $and$libresoc.v:31334$1024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:30939$1037 + cell $and $and$libresoc.v:31339$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45367,34 +45699,34 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:30939$1037_Y + connect \Y $and$libresoc.v:31339$1029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:30936$1034 + cell $not $not$libresoc.v:31336$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:30936$1034_Y + connect \Y $not$libresoc.v:31336$1026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:30938$1036 + cell $not $not$libresoc.v:31338$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30938$1036_Y + connect \Y $not$libresoc.v:31338$1028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:30941$1039 + cell $not $not$libresoc.v:31341$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:30941$1039_Y + connect \Y $not$libresoc.v:31341$1031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:30935$1033 + cell $or $or$libresoc.v:31335$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45402,10 +45734,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:30935$1033_Y + connect \Y $or$libresoc.v:31335$1025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:30937$1035 + cell $or $or$libresoc.v:31337$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45413,10 +45745,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:30937$1035_Y + connect \Y $or$libresoc.v:31337$1027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:30940$1038 + cell $or $or$libresoc.v:31340$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45424,39 +45756,39 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:30940$1038_Y + connect \Y $or$libresoc.v:31340$1030_Y end - attribute \src "libresoc.v:30899.7-30899.20" - process $proc$libresoc.v:30899$1044 + attribute \src "libresoc.v:31299.7-31299.20" + process $proc$libresoc.v:31299$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30923.7-30923.19" - process $proc$libresoc.v:30923$1045 + attribute \src "libresoc.v:31323.7-31323.19" + process $proc$libresoc.v:31323$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:30942.3-30943.27" - process $proc$libresoc.v:30942$1040 + attribute \src "libresoc.v:31342.3-31343.27" + process $proc$libresoc.v:31342$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:30944.3-30952.6" - process $proc$libresoc.v:30944$1041 + attribute \src "libresoc.v:31344.3-31352.6" + process $proc$libresoc.v:31344$1033 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1042 $1\q_int$next[0:0]$1043 - attribute \src "libresoc.v:30945.5-30945.29" + assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31345.5-31345.29" switch \initial - attribute \src "libresoc.v:30945.9-30945.17" + attribute \src "libresoc.v:31345.9-31345.17" case 1'1 case end @@ -45465,56 +45797,56 @@ module \alui_l$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1043 1'0 + assign $1\q_int$next[0:0]$1035 1'0 case - assign $1\q_int$next[0:0]$1043 \$5 + assign $1\q_int$next[0:0]$1035 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1042 + update \q_int$next $0\q_int$next[0:0]$1034 end - connect \$9 $and$libresoc.v:30934$1032_Y - connect \$11 $or$libresoc.v:30935$1033_Y - connect \$13 $not$libresoc.v:30936$1034_Y - connect \$15 $or$libresoc.v:30937$1035_Y - connect \$1 $not$libresoc.v:30938$1036_Y - connect \$3 $and$libresoc.v:30939$1037_Y - connect \$5 $or$libresoc.v:30940$1038_Y - connect \$7 $not$libresoc.v:30941$1039_Y + connect \$9 $and$libresoc.v:31334$1024_Y + connect \$11 $or$libresoc.v:31335$1025_Y + connect \$13 $not$libresoc.v:31336$1026_Y + connect \$15 $or$libresoc.v:31337$1027_Y + connect \$1 $not$libresoc.v:31338$1028_Y + connect \$3 $and$libresoc.v:31339$1029_Y + connect \$5 $or$libresoc.v:31340$1030_Y + connect \$7 $not$libresoc.v:31341$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:30960.1-31018.10" +attribute \src "libresoc.v:31360.1-31418.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 - attribute \src "libresoc.v:30961.7-30961.20" + attribute \src "libresoc.v:31361.7-31361.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31006.3-31014.6" - wire $0\q_int$next[0:0]$1056 - attribute \src "libresoc.v:31004.3-31005.27" + attribute \src "libresoc.v:31406.3-31414.6" + wire $0\q_int$next[0:0]$1048 + attribute \src "libresoc.v:31404.3-31405.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31006.3-31014.6" - wire $1\q_int$next[0:0]$1057 - attribute \src "libresoc.v:30985.7-30985.19" + attribute \src "libresoc.v:31406.3-31414.6" + wire $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31385.7-31385.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:30996.17-30996.96" - wire $and$libresoc.v:30996$1046_Y - attribute \src "libresoc.v:31001.17-31001.96" - wire $and$libresoc.v:31001$1051_Y - attribute \src "libresoc.v:30998.18-30998.94" - wire $not$libresoc.v:30998$1048_Y - attribute \src "libresoc.v:31000.17-31000.93" - wire $not$libresoc.v:31000$1050_Y - attribute \src "libresoc.v:31003.17-31003.93" - wire $not$libresoc.v:31003$1053_Y - attribute \src "libresoc.v:30997.18-30997.99" - wire $or$libresoc.v:30997$1047_Y - attribute \src "libresoc.v:30999.18-30999.100" - wire $or$libresoc.v:30999$1049_Y - attribute \src "libresoc.v:31002.17-31002.98" - wire $or$libresoc.v:31002$1052_Y + attribute \src "libresoc.v:31396.17-31396.96" + wire $and$libresoc.v:31396$1038_Y + attribute \src "libresoc.v:31401.17-31401.96" + wire $and$libresoc.v:31401$1043_Y + attribute \src "libresoc.v:31398.18-31398.94" + wire $not$libresoc.v:31398$1040_Y + attribute \src "libresoc.v:31400.17-31400.93" + wire $not$libresoc.v:31400$1042_Y + attribute \src "libresoc.v:31403.17-31403.93" + wire $not$libresoc.v:31403$1045_Y + attribute \src "libresoc.v:31397.18-31397.99" + wire $or$libresoc.v:31397$1039_Y + attribute \src "libresoc.v:31399.18-31399.100" + wire $or$libresoc.v:31399$1041_Y + attribute \src "libresoc.v:31402.17-31402.98" + wire $or$libresoc.v:31402$1044_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -45531,11 +45863,11 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:30961.7-30961.15" + attribute \src "libresoc.v:31361.7-31361.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -45552,7 +45884,7 @@ module \alui_l$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:30996$1046 + cell $and $and$libresoc.v:31396$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45560,10 +45892,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:30996$1046_Y + connect \Y $and$libresoc.v:31396$1038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31001$1051 + cell $and $and$libresoc.v:31401$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45571,34 +45903,34 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31001$1051_Y + connect \Y $and$libresoc.v:31401$1043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:30998$1048 + cell $not $not$libresoc.v:31398$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:30998$1048_Y + connect \Y $not$libresoc.v:31398$1040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31000$1050 + cell $not $not$libresoc.v:31400$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31000$1050_Y + connect \Y $not$libresoc.v:31400$1042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31003$1053 + cell $not $not$libresoc.v:31403$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31003$1053_Y + connect \Y $not$libresoc.v:31403$1045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:30997$1047 + cell $or $or$libresoc.v:31397$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45606,10 +45938,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:30997$1047_Y + connect \Y $or$libresoc.v:31397$1039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:30999$1049 + cell $or $or$libresoc.v:31399$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45617,10 +45949,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:30999$1049_Y + connect \Y $or$libresoc.v:31399$1041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31002$1052 + cell $or $or$libresoc.v:31402$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45628,39 +45960,39 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31002$1052_Y + connect \Y $or$libresoc.v:31402$1044_Y end - attribute \src "libresoc.v:30961.7-30961.20" - process $proc$libresoc.v:30961$1058 + attribute \src "libresoc.v:31361.7-31361.20" + process $proc$libresoc.v:31361$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:30985.7-30985.19" - process $proc$libresoc.v:30985$1059 + attribute \src "libresoc.v:31385.7-31385.19" + process $proc$libresoc.v:31385$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31004.3-31005.27" - process $proc$libresoc.v:31004$1054 + attribute \src "libresoc.v:31404.3-31405.27" + process $proc$libresoc.v:31404$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31006.3-31014.6" - process $proc$libresoc.v:31006$1055 + attribute \src "libresoc.v:31406.3-31414.6" + process $proc$libresoc.v:31406$1047 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1056 $1\q_int$next[0:0]$1057 - attribute \src "libresoc.v:31007.5-31007.29" + assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31407.5-31407.29" switch \initial - attribute \src "libresoc.v:31007.9-31007.17" + attribute \src "libresoc.v:31407.9-31407.17" case 1'1 case end @@ -45669,56 +46001,56 @@ module \alui_l$28 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1057 1'0 + assign $1\q_int$next[0:0]$1049 1'0 case - assign $1\q_int$next[0:0]$1057 \$5 + assign $1\q_int$next[0:0]$1049 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1056 + update \q_int$next $0\q_int$next[0:0]$1048 end - connect \$9 $and$libresoc.v:30996$1046_Y - connect \$11 $or$libresoc.v:30997$1047_Y - connect \$13 $not$libresoc.v:30998$1048_Y - connect \$15 $or$libresoc.v:30999$1049_Y - connect \$1 $not$libresoc.v:31000$1050_Y - connect \$3 $and$libresoc.v:31001$1051_Y - connect \$5 $or$libresoc.v:31002$1052_Y - connect \$7 $not$libresoc.v:31003$1053_Y + connect \$9 $and$libresoc.v:31396$1038_Y + connect \$11 $or$libresoc.v:31397$1039_Y + connect \$13 $not$libresoc.v:31398$1040_Y + connect \$15 $or$libresoc.v:31399$1041_Y + connect \$1 $not$libresoc.v:31400$1042_Y + connect \$3 $and$libresoc.v:31401$1043_Y + connect \$5 $or$libresoc.v:31402$1044_Y + connect \$7 $not$libresoc.v:31403$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31022.1-31080.10" +attribute \src "libresoc.v:31422.1-31480.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" -module \alui_l$41 - attribute \src "libresoc.v:31023.7-31023.20" +module \alui_l$44 + attribute \src "libresoc.v:31423.7-31423.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31068.3-31076.6" - wire $0\q_int$next[0:0]$1070 - attribute \src "libresoc.v:31066.3-31067.27" + attribute \src "libresoc.v:31468.3-31476.6" + wire $0\q_int$next[0:0]$1062 + attribute \src "libresoc.v:31466.3-31467.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31068.3-31076.6" - wire $1\q_int$next[0:0]$1071 - attribute \src "libresoc.v:31047.7-31047.19" + attribute \src "libresoc.v:31468.3-31476.6" + wire $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31447.7-31447.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31058.17-31058.96" - wire $and$libresoc.v:31058$1060_Y - attribute \src "libresoc.v:31063.17-31063.96" - wire $and$libresoc.v:31063$1065_Y - attribute \src "libresoc.v:31060.18-31060.94" - wire $not$libresoc.v:31060$1062_Y - attribute \src "libresoc.v:31062.17-31062.93" - wire $not$libresoc.v:31062$1064_Y - attribute \src "libresoc.v:31065.17-31065.93" - wire $not$libresoc.v:31065$1067_Y - attribute \src "libresoc.v:31059.18-31059.99" - wire $or$libresoc.v:31059$1061_Y - attribute \src "libresoc.v:31061.18-31061.100" - wire $or$libresoc.v:31061$1063_Y - attribute \src "libresoc.v:31064.17-31064.98" - wire $or$libresoc.v:31064$1066_Y + attribute \src "libresoc.v:31458.17-31458.96" + wire $and$libresoc.v:31458$1052_Y + attribute \src "libresoc.v:31463.17-31463.96" + wire $and$libresoc.v:31463$1057_Y + attribute \src "libresoc.v:31460.18-31460.94" + wire $not$libresoc.v:31460$1054_Y + attribute \src "libresoc.v:31462.17-31462.93" + wire $not$libresoc.v:31462$1056_Y + attribute \src "libresoc.v:31465.17-31465.93" + wire $not$libresoc.v:31465$1059_Y + attribute \src "libresoc.v:31459.18-31459.99" + wire $or$libresoc.v:31459$1053_Y + attribute \src "libresoc.v:31461.18-31461.100" + wire $or$libresoc.v:31461$1055_Y + attribute \src "libresoc.v:31464.17-31464.98" + wire $or$libresoc.v:31464$1058_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -45735,11 +46067,11 @@ module \alui_l$41 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:31023.7-31023.15" + attribute \src "libresoc.v:31423.7-31423.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -45756,7 +46088,7 @@ module \alui_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31058$1060 + cell $and $and$libresoc.v:31458$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45764,10 +46096,10 @@ module \alui_l$41 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31058$1060_Y + connect \Y $and$libresoc.v:31458$1052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31063$1065 + cell $and $and$libresoc.v:31463$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45775,34 +46107,34 @@ module \alui_l$41 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31063$1065_Y + connect \Y $and$libresoc.v:31463$1057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31060$1062 + cell $not $not$libresoc.v:31460$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31060$1062_Y + connect \Y $not$libresoc.v:31460$1054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31062$1064 + cell $not $not$libresoc.v:31462$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31062$1064_Y + connect \Y $not$libresoc.v:31462$1056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31065$1067 + cell $not $not$libresoc.v:31465$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31065$1067_Y + connect \Y $not$libresoc.v:31465$1059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31059$1061 + cell $or $or$libresoc.v:31459$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45810,10 +46142,10 @@ module \alui_l$41 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31059$1061_Y + connect \Y $or$libresoc.v:31459$1053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31061$1063 + cell $or $or$libresoc.v:31461$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45821,10 +46153,10 @@ module \alui_l$41 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31061$1063_Y + connect \Y $or$libresoc.v:31461$1055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31064$1066 + cell $or $or$libresoc.v:31464$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45832,39 +46164,39 @@ module \alui_l$41 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31064$1066_Y + connect \Y $or$libresoc.v:31464$1058_Y end - attribute \src "libresoc.v:31023.7-31023.20" - process $proc$libresoc.v:31023$1072 + attribute \src "libresoc.v:31423.7-31423.20" + process $proc$libresoc.v:31423$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31047.7-31047.19" - process $proc$libresoc.v:31047$1073 + attribute \src "libresoc.v:31447.7-31447.19" + process $proc$libresoc.v:31447$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31066.3-31067.27" - process $proc$libresoc.v:31066$1068 + attribute \src "libresoc.v:31466.3-31467.27" + process $proc$libresoc.v:31466$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31068.3-31076.6" - process $proc$libresoc.v:31068$1069 + attribute \src "libresoc.v:31468.3-31476.6" + process $proc$libresoc.v:31468$1061 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1070 $1\q_int$next[0:0]$1071 - attribute \src "libresoc.v:31069.5-31069.29" + assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31469.5-31469.29" switch \initial - attribute \src "libresoc.v:31069.9-31069.17" + attribute \src "libresoc.v:31469.9-31469.17" case 1'1 case end @@ -45873,56 +46205,56 @@ module \alui_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1071 1'0 + assign $1\q_int$next[0:0]$1063 1'0 case - assign $1\q_int$next[0:0]$1071 \$5 + assign $1\q_int$next[0:0]$1063 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1070 + update \q_int$next $0\q_int$next[0:0]$1062 end - connect \$9 $and$libresoc.v:31058$1060_Y - connect \$11 $or$libresoc.v:31059$1061_Y - connect \$13 $not$libresoc.v:31060$1062_Y - connect \$15 $or$libresoc.v:31061$1063_Y - connect \$1 $not$libresoc.v:31062$1064_Y - connect \$3 $and$libresoc.v:31063$1065_Y - connect \$5 $or$libresoc.v:31064$1066_Y - connect \$7 $not$libresoc.v:31065$1067_Y + connect \$9 $and$libresoc.v:31458$1052_Y + connect \$11 $or$libresoc.v:31459$1053_Y + connect \$13 $not$libresoc.v:31460$1054_Y + connect \$15 $or$libresoc.v:31461$1055_Y + connect \$1 $not$libresoc.v:31462$1056_Y + connect \$3 $and$libresoc.v:31463$1057_Y + connect \$5 $or$libresoc.v:31464$1058_Y + connect \$7 $not$libresoc.v:31465$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31084.1-31142.10" +attribute \src "libresoc.v:31484.1-31542.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" -module \alui_l$57 - attribute \src "libresoc.v:31085.7-31085.20" +module \alui_l$60 + attribute \src "libresoc.v:31485.7-31485.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31130.3-31138.6" - wire $0\q_int$next[0:0]$1084 - attribute \src "libresoc.v:31128.3-31129.27" + attribute \src "libresoc.v:31530.3-31538.6" + wire $0\q_int$next[0:0]$1076 + attribute \src "libresoc.v:31528.3-31529.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31130.3-31138.6" - wire $1\q_int$next[0:0]$1085 - attribute \src "libresoc.v:31109.7-31109.19" + attribute \src "libresoc.v:31530.3-31538.6" + wire $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31509.7-31509.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31120.17-31120.96" - wire $and$libresoc.v:31120$1074_Y - attribute \src "libresoc.v:31125.17-31125.96" - wire $and$libresoc.v:31125$1079_Y - attribute \src "libresoc.v:31122.18-31122.94" - wire $not$libresoc.v:31122$1076_Y - attribute \src "libresoc.v:31124.17-31124.93" - wire $not$libresoc.v:31124$1078_Y - attribute \src "libresoc.v:31127.17-31127.93" - wire $not$libresoc.v:31127$1081_Y - attribute \src "libresoc.v:31121.18-31121.99" - wire $or$libresoc.v:31121$1075_Y - attribute \src "libresoc.v:31123.18-31123.100" - wire $or$libresoc.v:31123$1077_Y - attribute \src "libresoc.v:31126.17-31126.98" - wire $or$libresoc.v:31126$1080_Y + attribute \src "libresoc.v:31520.17-31520.96" + wire $and$libresoc.v:31520$1066_Y + attribute \src "libresoc.v:31525.17-31525.96" + wire $and$libresoc.v:31525$1071_Y + attribute \src "libresoc.v:31522.18-31522.94" + wire $not$libresoc.v:31522$1068_Y + attribute \src "libresoc.v:31524.17-31524.93" + wire $not$libresoc.v:31524$1070_Y + attribute \src "libresoc.v:31527.17-31527.93" + wire $not$libresoc.v:31527$1073_Y + attribute \src "libresoc.v:31521.18-31521.99" + wire $or$libresoc.v:31521$1067_Y + attribute \src "libresoc.v:31523.18-31523.100" + wire $or$libresoc.v:31523$1069_Y + attribute \src "libresoc.v:31526.17-31526.98" + wire $or$libresoc.v:31526$1072_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -45939,11 +46271,11 @@ module \alui_l$57 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:31085.7-31085.15" + attribute \src "libresoc.v:31485.7-31485.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -45960,7 +46292,7 @@ module \alui_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31120$1074 + cell $and $and$libresoc.v:31520$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45968,10 +46300,10 @@ module \alui_l$57 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31120$1074_Y + connect \Y $and$libresoc.v:31520$1066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31125$1079 + cell $and $and$libresoc.v:31525$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45979,34 +46311,34 @@ module \alui_l$57 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31125$1079_Y + connect \Y $and$libresoc.v:31525$1071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31122$1076 + cell $not $not$libresoc.v:31522$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31122$1076_Y + connect \Y $not$libresoc.v:31522$1068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31124$1078 + cell $not $not$libresoc.v:31524$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31124$1078_Y + connect \Y $not$libresoc.v:31524$1070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31127$1081 + cell $not $not$libresoc.v:31527$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31127$1081_Y + connect \Y $not$libresoc.v:31527$1073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31121$1075 + cell $or $or$libresoc.v:31521$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46014,10 +46346,10 @@ module \alui_l$57 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31121$1075_Y + connect \Y $or$libresoc.v:31521$1067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31123$1077 + cell $or $or$libresoc.v:31523$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46025,10 +46357,10 @@ module \alui_l$57 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31123$1077_Y + connect \Y $or$libresoc.v:31523$1069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31126$1080 + cell $or $or$libresoc.v:31526$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46036,39 +46368,39 @@ module \alui_l$57 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31126$1080_Y + connect \Y $or$libresoc.v:31526$1072_Y end - attribute \src "libresoc.v:31085.7-31085.20" - process $proc$libresoc.v:31085$1086 + attribute \src "libresoc.v:31485.7-31485.20" + process $proc$libresoc.v:31485$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31109.7-31109.19" - process $proc$libresoc.v:31109$1087 + attribute \src "libresoc.v:31509.7-31509.19" + process $proc$libresoc.v:31509$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31128.3-31129.27" - process $proc$libresoc.v:31128$1082 + attribute \src "libresoc.v:31528.3-31529.27" + process $proc$libresoc.v:31528$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31130.3-31138.6" - process $proc$libresoc.v:31130$1083 + attribute \src "libresoc.v:31530.3-31538.6" + process $proc$libresoc.v:31530$1075 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1084 $1\q_int$next[0:0]$1085 - attribute \src "libresoc.v:31131.5-31131.29" + assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31531.5-31531.29" switch \initial - attribute \src "libresoc.v:31131.9-31131.17" + attribute \src "libresoc.v:31531.9-31531.17" case 1'1 case end @@ -46077,56 +46409,56 @@ module \alui_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1085 1'0 + assign $1\q_int$next[0:0]$1077 1'0 case - assign $1\q_int$next[0:0]$1085 \$5 + assign $1\q_int$next[0:0]$1077 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1084 + update \q_int$next $0\q_int$next[0:0]$1076 end - connect \$9 $and$libresoc.v:31120$1074_Y - connect \$11 $or$libresoc.v:31121$1075_Y - connect \$13 $not$libresoc.v:31122$1076_Y - connect \$15 $or$libresoc.v:31123$1077_Y - connect \$1 $not$libresoc.v:31124$1078_Y - connect \$3 $and$libresoc.v:31125$1079_Y - connect \$5 $or$libresoc.v:31126$1080_Y - connect \$7 $not$libresoc.v:31127$1081_Y + connect \$9 $and$libresoc.v:31520$1066_Y + connect \$11 $or$libresoc.v:31521$1067_Y + connect \$13 $not$libresoc.v:31522$1068_Y + connect \$15 $or$libresoc.v:31523$1069_Y + connect \$1 $not$libresoc.v:31524$1070_Y + connect \$3 $and$libresoc.v:31525$1071_Y + connect \$5 $or$libresoc.v:31526$1072_Y + connect \$7 $not$libresoc.v:31527$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31146.1-31204.10" +attribute \src "libresoc.v:31546.1-31604.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" -module \alui_l$69 - attribute \src "libresoc.v:31147.7-31147.20" +module \alui_l$72 + attribute \src "libresoc.v:31547.7-31547.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31192.3-31200.6" - wire $0\q_int$next[0:0]$1098 - attribute \src "libresoc.v:31190.3-31191.27" + attribute \src "libresoc.v:31592.3-31600.6" + wire $0\q_int$next[0:0]$1090 + attribute \src "libresoc.v:31590.3-31591.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31192.3-31200.6" - wire $1\q_int$next[0:0]$1099 - attribute \src "libresoc.v:31171.7-31171.19" + attribute \src "libresoc.v:31592.3-31600.6" + wire $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:31571.7-31571.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31182.17-31182.96" - wire $and$libresoc.v:31182$1088_Y - attribute \src "libresoc.v:31187.17-31187.96" - wire $and$libresoc.v:31187$1093_Y - attribute \src "libresoc.v:31184.18-31184.94" - wire $not$libresoc.v:31184$1090_Y - attribute \src "libresoc.v:31186.17-31186.93" - wire $not$libresoc.v:31186$1092_Y - attribute \src "libresoc.v:31189.17-31189.93" - wire $not$libresoc.v:31189$1095_Y - attribute \src "libresoc.v:31183.18-31183.99" - wire $or$libresoc.v:31183$1089_Y - attribute \src "libresoc.v:31185.18-31185.100" - wire $or$libresoc.v:31185$1091_Y - attribute \src "libresoc.v:31188.17-31188.98" - wire $or$libresoc.v:31188$1094_Y + attribute \src "libresoc.v:31582.17-31582.96" + wire $and$libresoc.v:31582$1080_Y + attribute \src "libresoc.v:31587.17-31587.96" + wire $and$libresoc.v:31587$1085_Y + attribute \src "libresoc.v:31584.18-31584.94" + wire $not$libresoc.v:31584$1082_Y + attribute \src "libresoc.v:31586.17-31586.93" + wire $not$libresoc.v:31586$1084_Y + attribute \src "libresoc.v:31589.17-31589.93" + wire $not$libresoc.v:31589$1087_Y + attribute \src "libresoc.v:31583.18-31583.99" + wire $or$libresoc.v:31583$1081_Y + attribute \src "libresoc.v:31585.18-31585.100" + wire $or$libresoc.v:31585$1083_Y + attribute \src "libresoc.v:31588.17-31588.98" + wire $or$libresoc.v:31588$1086_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -46143,11 +46475,11 @@ module \alui_l$69 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:31147.7-31147.15" + attribute \src "libresoc.v:31547.7-31547.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -46164,7 +46496,7 @@ module \alui_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31182$1088 + cell $and $and$libresoc.v:31582$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46172,10 +46504,10 @@ module \alui_l$69 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31182$1088_Y + connect \Y $and$libresoc.v:31582$1080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31187$1093 + cell $and $and$libresoc.v:31587$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46183,34 +46515,34 @@ module \alui_l$69 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31187$1093_Y + connect \Y $and$libresoc.v:31587$1085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31184$1090 + cell $not $not$libresoc.v:31584$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31184$1090_Y + connect \Y $not$libresoc.v:31584$1082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31186$1092 + cell $not $not$libresoc.v:31586$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31186$1092_Y + connect \Y $not$libresoc.v:31586$1084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31189$1095 + cell $not $not$libresoc.v:31589$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31189$1095_Y + connect \Y $not$libresoc.v:31589$1087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31183$1089 + cell $or $or$libresoc.v:31583$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46218,10 +46550,10 @@ module \alui_l$69 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31183$1089_Y + connect \Y $or$libresoc.v:31583$1081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31185$1091 + cell $or $or$libresoc.v:31585$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46229,10 +46561,10 @@ module \alui_l$69 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31185$1091_Y + connect \Y $or$libresoc.v:31585$1083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31188$1094 + cell $or $or$libresoc.v:31588$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46240,39 +46572,39 @@ module \alui_l$69 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31188$1094_Y + connect \Y $or$libresoc.v:31588$1086_Y end - attribute \src "libresoc.v:31147.7-31147.20" - process $proc$libresoc.v:31147$1100 + attribute \src "libresoc.v:31547.7-31547.20" + process $proc$libresoc.v:31547$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31171.7-31171.19" - process $proc$libresoc.v:31171$1101 + attribute \src "libresoc.v:31571.7-31571.19" + process $proc$libresoc.v:31571$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31190.3-31191.27" - process $proc$libresoc.v:31190$1096 + attribute \src "libresoc.v:31590.3-31591.27" + process $proc$libresoc.v:31590$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31192.3-31200.6" - process $proc$libresoc.v:31192$1097 + attribute \src "libresoc.v:31592.3-31600.6" + process $proc$libresoc.v:31592$1089 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1098 $1\q_int$next[0:0]$1099 - attribute \src "libresoc.v:31193.5-31193.29" + assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:31593.5-31593.29" switch \initial - attribute \src "libresoc.v:31193.9-31193.17" + attribute \src "libresoc.v:31593.9-31593.17" case 1'1 case end @@ -46281,56 +46613,56 @@ module \alui_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1099 1'0 + assign $1\q_int$next[0:0]$1091 1'0 case - assign $1\q_int$next[0:0]$1099 \$5 + assign $1\q_int$next[0:0]$1091 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1098 + update \q_int$next $0\q_int$next[0:0]$1090 end - connect \$9 $and$libresoc.v:31182$1088_Y - connect \$11 $or$libresoc.v:31183$1089_Y - connect \$13 $not$libresoc.v:31184$1090_Y - connect \$15 $or$libresoc.v:31185$1091_Y - connect \$1 $not$libresoc.v:31186$1092_Y - connect \$3 $and$libresoc.v:31187$1093_Y - connect \$5 $or$libresoc.v:31188$1094_Y - connect \$7 $not$libresoc.v:31189$1095_Y + connect \$9 $and$libresoc.v:31582$1080_Y + connect \$11 $or$libresoc.v:31583$1081_Y + connect \$13 $not$libresoc.v:31584$1082_Y + connect \$15 $or$libresoc.v:31585$1083_Y + connect \$1 $not$libresoc.v:31586$1084_Y + connect \$3 $and$libresoc.v:31587$1085_Y + connect \$5 $or$libresoc.v:31588$1086_Y + connect \$7 $not$libresoc.v:31589$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31208.1-31266.10" +attribute \src "libresoc.v:31608.1-31666.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" -module \alui_l$86 - attribute \src "libresoc.v:31209.7-31209.20" +module \alui_l$89 + attribute \src "libresoc.v:31609.7-31609.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31254.3-31262.6" - wire $0\q_int$next[0:0]$1112 - attribute \src "libresoc.v:31252.3-31253.27" + attribute \src "libresoc.v:31654.3-31662.6" + wire $0\q_int$next[0:0]$1104 + attribute \src "libresoc.v:31652.3-31653.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31254.3-31262.6" - wire $1\q_int$next[0:0]$1113 - attribute \src "libresoc.v:31233.7-31233.19" + attribute \src "libresoc.v:31654.3-31662.6" + wire $1\q_int$next[0:0]$1105 + attribute \src "libresoc.v:31633.7-31633.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31244.17-31244.96" - wire $and$libresoc.v:31244$1102_Y - attribute \src "libresoc.v:31249.17-31249.96" - wire $and$libresoc.v:31249$1107_Y - attribute \src "libresoc.v:31246.18-31246.94" - wire $not$libresoc.v:31246$1104_Y - attribute \src "libresoc.v:31248.17-31248.93" - wire $not$libresoc.v:31248$1106_Y - attribute \src "libresoc.v:31251.17-31251.93" - wire $not$libresoc.v:31251$1109_Y - attribute \src "libresoc.v:31245.18-31245.99" - wire $or$libresoc.v:31245$1103_Y - attribute \src "libresoc.v:31247.18-31247.100" - wire $or$libresoc.v:31247$1105_Y - attribute \src "libresoc.v:31250.17-31250.98" - wire $or$libresoc.v:31250$1108_Y + attribute \src "libresoc.v:31644.17-31644.96" + wire $and$libresoc.v:31644$1094_Y + attribute \src "libresoc.v:31649.17-31649.96" + wire $and$libresoc.v:31649$1099_Y + attribute \src "libresoc.v:31646.18-31646.94" + wire $not$libresoc.v:31646$1096_Y + attribute \src "libresoc.v:31648.17-31648.93" + wire $not$libresoc.v:31648$1098_Y + attribute \src "libresoc.v:31651.17-31651.93" + wire $not$libresoc.v:31651$1101_Y + attribute \src "libresoc.v:31645.18-31645.99" + wire $or$libresoc.v:31645$1095_Y + attribute \src "libresoc.v:31647.18-31647.100" + wire $or$libresoc.v:31647$1097_Y + attribute \src "libresoc.v:31650.17-31650.98" + wire $or$libresoc.v:31650$1100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -46347,11 +46679,11 @@ module \alui_l$86 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:31209.7-31209.15" + attribute \src "libresoc.v:31609.7-31609.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_alui @@ -46368,7 +46700,7 @@ module \alui_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31244$1102 + cell $and $and$libresoc.v:31644$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46376,10 +46708,10 @@ module \alui_l$86 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31244$1102_Y + connect \Y $and$libresoc.v:31644$1094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31249$1107 + cell $and $and$libresoc.v:31649$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46387,34 +46719,34 @@ module \alui_l$86 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31249$1107_Y + connect \Y $and$libresoc.v:31649$1099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31246$1104 + cell $not $not$libresoc.v:31646$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31246$1104_Y + connect \Y $not$libresoc.v:31646$1096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31248$1106 + cell $not $not$libresoc.v:31648$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31248$1106_Y + connect \Y $not$libresoc.v:31648$1098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31251$1109 + cell $not $not$libresoc.v:31651$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31251$1109_Y + connect \Y $not$libresoc.v:31651$1101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31245$1103 + cell $or $or$libresoc.v:31645$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46422,10 +46754,10 @@ module \alui_l$86 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31245$1103_Y + connect \Y $or$libresoc.v:31645$1095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31247$1105 + cell $or $or$libresoc.v:31647$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46433,10 +46765,10 @@ module \alui_l$86 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31247$1105_Y + connect \Y $or$libresoc.v:31647$1097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31250$1108 + cell $or $or$libresoc.v:31650$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46444,39 +46776,39 @@ module \alui_l$86 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31250$1108_Y + connect \Y $or$libresoc.v:31650$1100_Y end - attribute \src "libresoc.v:31209.7-31209.20" - process $proc$libresoc.v:31209$1114 + attribute \src "libresoc.v:31609.7-31609.20" + process $proc$libresoc.v:31609$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31233.7-31233.19" - process $proc$libresoc.v:31233$1115 + attribute \src "libresoc.v:31633.7-31633.19" + process $proc$libresoc.v:31633$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31252.3-31253.27" - process $proc$libresoc.v:31252$1110 + attribute \src "libresoc.v:31652.3-31653.27" + process $proc$libresoc.v:31652$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31254.3-31262.6" - process $proc$libresoc.v:31254$1111 + attribute \src "libresoc.v:31654.3-31662.6" + process $proc$libresoc.v:31654$1103 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1112 $1\q_int$next[0:0]$1113 - attribute \src "libresoc.v:31255.5-31255.29" + assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 + attribute \src "libresoc.v:31655.5-31655.29" switch \initial - attribute \src "libresoc.v:31255.9-31255.17" + attribute \src "libresoc.v:31655.9-31655.17" case 1'1 case end @@ -46485,82 +46817,82 @@ module \alui_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1113 1'0 + assign $1\q_int$next[0:0]$1105 1'0 case - assign $1\q_int$next[0:0]$1113 \$5 + assign $1\q_int$next[0:0]$1105 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1112 + update \q_int$next $0\q_int$next[0:0]$1104 end - connect \$9 $and$libresoc.v:31244$1102_Y - connect \$11 $or$libresoc.v:31245$1103_Y - connect \$13 $not$libresoc.v:31246$1104_Y - connect \$15 $or$libresoc.v:31247$1105_Y - connect \$1 $not$libresoc.v:31248$1106_Y - connect \$3 $and$libresoc.v:31249$1107_Y - connect \$5 $or$libresoc.v:31250$1108_Y - connect \$7 $not$libresoc.v:31251$1109_Y + connect \$9 $and$libresoc.v:31644$1094_Y + connect \$11 $or$libresoc.v:31645$1095_Y + connect \$13 $not$libresoc.v:31646$1096_Y + connect \$15 $or$libresoc.v:31647$1097_Y + connect \$1 $not$libresoc.v:31648$1098_Y + connect \$3 $and$libresoc.v:31649$1099_Y + connect \$5 $or$libresoc.v:31650$1100_Y + connect \$7 $not$libresoc.v:31651$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31270.1-32614.10" +attribute \src "libresoc.v:31670.1-33014.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd - attribute \src "libresoc.v:31271.7-31271.20" + attribute \src "libresoc.v:31671.7-31671.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire width 64 $0\perm[63:0] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $10\perm[4:4] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $11\perm[5:5] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $12\perm[5:5] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $13\perm[6:6] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $14\perm[6:6] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $15\perm[7:7] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $16\perm[7:7] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $1\perm[0:0] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $2\perm[0:0] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $3\perm[1:1] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $4\perm[1:1] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $5\perm[2:2] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $6\perm[2:2] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $7\perm[3:3] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $8\perm[3:3] - attribute \src "libresoc.v:31448.3-32539.6" + attribute \src "libresoc.v:31848.3-32939.6" wire $9\perm[4:4] - attribute \src "libresoc.v:31440.17-31440.104" - wire $lt$libresoc.v:31440$1116_Y - attribute \src "libresoc.v:31441.18-31441.105" - wire $lt$libresoc.v:31441$1117_Y - attribute \src "libresoc.v:31442.18-31442.105" - wire $lt$libresoc.v:31442$1118_Y - attribute \src "libresoc.v:31443.18-31443.105" - wire $lt$libresoc.v:31443$1119_Y - attribute \src "libresoc.v:31444.17-31444.104" - wire $lt$libresoc.v:31444$1120_Y - attribute \src "libresoc.v:31445.17-31445.104" - wire $lt$libresoc.v:31445$1121_Y - attribute \src "libresoc.v:31446.17-31446.104" - wire $lt$libresoc.v:31446$1122_Y - attribute \src "libresoc.v:31447.17-31447.104" - wire $lt$libresoc.v:31447$1123_Y + attribute \src "libresoc.v:31840.17-31840.104" + wire $lt$libresoc.v:31840$1108_Y + attribute \src "libresoc.v:31841.18-31841.105" + wire $lt$libresoc.v:31841$1109_Y + attribute \src "libresoc.v:31842.18-31842.105" + wire $lt$libresoc.v:31842$1110_Y + attribute \src "libresoc.v:31843.18-31843.105" + wire $lt$libresoc.v:31843$1111_Y + attribute \src "libresoc.v:31844.17-31844.104" + wire $lt$libresoc.v:31844$1112_Y + attribute \src "libresoc.v:31845.17-31845.104" + wire $lt$libresoc.v:31845$1113_Y + attribute \src "libresoc.v:31846.17-31846.104" + wire $lt$libresoc.v:31846$1114_Y + attribute \src "libresoc.v:31847.17-31847.104" + wire $lt$libresoc.v:31847$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" @@ -46593,7 +46925,7 @@ module \bpermd wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 - attribute \src "libresoc.v:31271.7-31271.15" + attribute \src "libresoc.v:31671.7-31671.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm @@ -46732,7 +47064,7 @@ module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31440$1116 + cell $lt $lt$libresoc.v:31840$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46740,10 +47072,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31440$1116_Y + connect \Y $lt$libresoc.v:31840$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31441$1117 + cell $lt $lt$libresoc.v:31841$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46751,10 +47083,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31441$1117_Y + connect \Y $lt$libresoc.v:31841$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31442$1118 + cell $lt $lt$libresoc.v:31842$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46762,10 +47094,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31442$1118_Y + connect \Y $lt$libresoc.v:31842$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31443$1119 + cell $lt $lt$libresoc.v:31843$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46773,10 +47105,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31443$1119_Y + connect \Y $lt$libresoc.v:31843$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31444$1120 + cell $lt $lt$libresoc.v:31844$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46784,10 +47116,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31444$1120_Y + connect \Y $lt$libresoc.v:31844$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31445$1121 + cell $lt $lt$libresoc.v:31845$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46795,10 +47127,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31445$1121_Y + connect \Y $lt$libresoc.v:31845$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31446$1122 + cell $lt $lt$libresoc.v:31846$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46806,10 +47138,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31446$1122_Y + connect \Y $lt$libresoc.v:31846$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31447$1123 + cell $lt $lt$libresoc.v:31847$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -46817,18 +47149,18 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 - connect \Y $lt$libresoc.v:31447$1123_Y + connect \Y $lt$libresoc.v:31847$1115_Y end - attribute \src "libresoc.v:31271.7-31271.20" - process $proc$libresoc.v:31271$1125 + attribute \src "libresoc.v:31671.7-31671.20" + process $proc$libresoc.v:31671$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31448.3-32539.6" - process $proc$libresoc.v:31448$1124 + attribute \src "libresoc.v:31848.3-32939.6" + process $proc$libresoc.v:31848$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] @@ -46839,9 +47171,9 @@ module \bpermd assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:31449.5-31449.29" + attribute \src "libresoc.v:31849.5-31849.29" switch \initial - attribute \src "libresoc.v:31449.9-31449.17" + attribute \src "libresoc.v:31849.9-31849.17" case 1'1 case end @@ -49008,14 +49340,14 @@ module \bpermd sync always update \perm $0\perm[63:0] end - connect \$9 $lt$libresoc.v:31440$1116_Y - connect \$11 $lt$libresoc.v:31441$1117_Y - connect \$13 $lt$libresoc.v:31442$1118_Y - connect \$15 $lt$libresoc.v:31443$1119_Y - connect \$1 $lt$libresoc.v:31444$1120_Y - connect \$3 $lt$libresoc.v:31445$1121_Y - connect \$5 $lt$libresoc.v:31446$1122_Y - connect \$7 $lt$libresoc.v:31447$1123_Y + connect \$9 $lt$libresoc.v:31840$1108_Y + connect \$11 $lt$libresoc.v:31841$1109_Y + connect \$13 $lt$libresoc.v:31842$1110_Y + connect \$15 $lt$libresoc.v:31843$1111_Y + connect \$1 $lt$libresoc.v:31844$1112_Y + connect \$3 $lt$libresoc.v:31845$1113_Y + connect \$5 $lt$libresoc.v:31846$1114_Y + connect \$7 $lt$libresoc.v:31847$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] @@ -49091,413 +49423,413 @@ module \bpermd connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end -attribute \src "libresoc.v:32618.1-33667.10" +attribute \src "libresoc.v:33018.1-34067.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 - attribute \src "libresoc.v:33234.3-33235.25" + attribute \src "libresoc.v:33684.3-33685.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33258.3-33259.61" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 + attribute \src "libresoc.v:33644.3-33645.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 - attribute \src "libresoc.v:33262.3-33263.69" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 + attribute \src "libresoc.v:33648.3-33649.69" wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33266.3-33267.83" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + attribute \src "libresoc.v:33652.3-33653.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33268.3-33269.79" + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + attribute \src "libresoc.v:33654.3-33655.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33264.3-33265.63" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 + attribute \src "libresoc.v:33650.3-33651.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33260.3-33261.73" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + attribute \src "libresoc.v:33646.3-33647.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33272.3-33273.71" + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + attribute \src "libresoc.v:33658.3-33659.71" wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $0\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33270.3-33271.59" + attribute \src "libresoc.v:33859.3-33883.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1246 + attribute \src "libresoc.v:33656.3-33657.59" wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33232.3-33233.43" + attribute \src "libresoc.v:33682.3-33683.43" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:33589.3-33597.6" - wire $0\alu_l_r_alu$next[0:0]$1302 - attribute \src "libresoc.v:33236.3-33237.39" + attribute \src "libresoc.v:33989.3-33997.6" + wire $0\alu_l_r_alu$next[0:0]$1294 + attribute \src "libresoc.v:33622.3-33623.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33580.3-33588.6" - wire $0\alui_l_r_alui$next[0:0]$1299 - attribute \src "libresoc.v:33238.3-33239.43" + attribute \src "libresoc.v:33980.3-33988.6" + wire $0\alui_l_r_alui$next[0:0]$1291 + attribute \src "libresoc.v:33624.3-33625.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33484.3-33505.6" - wire width 64 $0\data_r0__fast1$next[63:0]$1266 - attribute \src "libresoc.v:33254.3-33255.45" + attribute \src "libresoc.v:33884.3-33905.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1258 + attribute \src "libresoc.v:33640.3-33641.45" wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:33484.3-33505.6" - wire $0\data_r0__fast1_ok$next[0:0]$1267 - attribute \src "libresoc.v:33256.3-33257.51" + attribute \src "libresoc.v:33884.3-33905.6" + wire $0\data_r0__fast1_ok$next[0:0]$1259 + attribute \src "libresoc.v:33642.3-33643.51" wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33506.3-33527.6" - wire width 64 $0\data_r1__fast2$next[63:0]$1274 - attribute \src "libresoc.v:33250.3-33251.45" + attribute \src "libresoc.v:33906.3-33927.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1266 + attribute \src "libresoc.v:33636.3-33637.45" wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:33506.3-33527.6" - wire $0\data_r1__fast2_ok$next[0:0]$1275 - attribute \src "libresoc.v:33252.3-33253.51" + attribute \src "libresoc.v:33906.3-33927.6" + wire $0\data_r1__fast2_ok$next[0:0]$1267 + attribute \src "libresoc.v:33638.3-33639.51" wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33528.3-33549.6" - wire width 64 $0\data_r2__nia$next[63:0]$1282 - attribute \src "libresoc.v:33246.3-33247.41" + attribute \src "libresoc.v:33928.3-33949.6" + wire width 64 $0\data_r2__nia$next[63:0]$1274 + attribute \src "libresoc.v:33632.3-33633.41" wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:33528.3-33549.6" - wire $0\data_r2__nia_ok$next[0:0]$1283 - attribute \src "libresoc.v:33248.3-33249.47" + attribute \src "libresoc.v:33928.3-33949.6" + wire $0\data_r2__nia_ok$next[0:0]$1275 + attribute \src "libresoc.v:33634.3-33635.47" wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33598.3-33607.6" + attribute \src "libresoc.v:33998.3-34007.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:33608.3-33617.6" + attribute \src "libresoc.v:34008.3-34017.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:33618.3-33627.6" + attribute \src "libresoc.v:34018.3-34027.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:32619.7-32619.20" + attribute \src "libresoc.v:33019.7-33019.20" wire $0\initial[0:0] - attribute \src "libresoc.v:33414.3-33422.6" - wire $0\opc_l_r_opc$next[0:0]$1232 - attribute \src "libresoc.v:33282.3-33283.39" + attribute \src "libresoc.v:33814.3-33822.6" + wire $0\opc_l_r_opc$next[0:0]$1224 + attribute \src "libresoc.v:33668.3-33669.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33405.3-33413.6" - wire $0\opc_l_s_opc$next[0:0]$1229 - attribute \src "libresoc.v:33284.3-33285.39" + attribute \src "libresoc.v:33805.3-33813.6" + wire $0\opc_l_s_opc$next[0:0]$1221 + attribute \src "libresoc.v:33670.3-33671.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:33628.3-33636.6" - wire width 3 $0\prev_wr_go$next[2:0]$1308 - attribute \src "libresoc.v:33230.3-33231.37" + attribute \src "libresoc.v:34028.3-34036.6" + wire width 3 $0\prev_wr_go$next[2:0]$1300 + attribute \src "libresoc.v:33680.3-33681.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:33359.3-33368.6" + attribute \src "libresoc.v:33759.3-33768.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:33450.3-33458.6" - wire width 3 $0\req_l_r_req$next[2:0]$1244 - attribute \src "libresoc.v:33274.3-33275.39" + attribute \src "libresoc.v:33850.3-33858.6" + wire width 3 $0\req_l_r_req$next[2:0]$1236 + attribute \src "libresoc.v:33660.3-33661.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:33441.3-33449.6" - wire width 3 $0\req_l_s_req$next[2:0]$1241 - attribute \src "libresoc.v:33276.3-33277.39" + attribute \src "libresoc.v:33841.3-33849.6" + wire width 3 $0\req_l_s_req$next[2:0]$1233 + attribute \src "libresoc.v:33662.3-33663.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:33378.3-33386.6" - wire $0\rok_l_r_rdok$next[0:0]$1220 - attribute \src "libresoc.v:33226.3-33227.41" + attribute \src "libresoc.v:33778.3-33786.6" + wire $0\rok_l_r_rdok$next[0:0]$1212 + attribute \src "libresoc.v:33676.3-33677.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33369.3-33377.6" - wire $0\rok_l_s_rdok$next[0:0]$1217 - attribute \src "libresoc.v:33228.3-33229.41" + attribute \src "libresoc.v:33769.3-33777.6" + wire $0\rok_l_s_rdok$next[0:0]$1209 + attribute \src "libresoc.v:33678.3-33679.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33396.3-33404.6" - wire $0\rst_l_r_rst$next[0:0]$1226 - attribute \src "libresoc.v:33222.3-33223.39" + attribute \src "libresoc.v:33796.3-33804.6" + wire $0\rst_l_r_rst$next[0:0]$1218 + attribute \src "libresoc.v:33672.3-33673.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33387.3-33395.6" - wire $0\rst_l_s_rst$next[0:0]$1223 - attribute \src "libresoc.v:33224.3-33225.39" + attribute \src "libresoc.v:33787.3-33795.6" + wire $0\rst_l_s_rst$next[0:0]$1215 + attribute \src "libresoc.v:33674.3-33675.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33432.3-33440.6" - wire width 3 $0\src_l_r_src$next[2:0]$1238 - attribute \src "libresoc.v:33278.3-33279.39" + attribute \src "libresoc.v:33832.3-33840.6" + wire width 3 $0\src_l_r_src$next[2:0]$1230 + attribute \src "libresoc.v:33664.3-33665.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:33423.3-33431.6" - wire width 3 $0\src_l_s_src$next[2:0]$1235 - attribute \src "libresoc.v:33280.3-33281.39" + attribute \src "libresoc.v:33823.3-33831.6" + wire width 3 $0\src_l_s_src$next[2:0]$1227 + attribute \src "libresoc.v:33666.3-33667.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:33550.3-33559.6" - wire width 64 $0\src_r0$next[63:0]$1290 - attribute \src "libresoc.v:33244.3-33245.29" + attribute \src "libresoc.v:33950.3-33959.6" + wire width 64 $0\src_r0$next[63:0]$1282 + attribute \src "libresoc.v:33630.3-33631.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:33560.3-33569.6" - wire width 64 $0\src_r1$next[63:0]$1293 - attribute \src "libresoc.v:33242.3-33243.29" + attribute \src "libresoc.v:33960.3-33969.6" + wire width 64 $0\src_r1$next[63:0]$1285 + attribute \src "libresoc.v:33628.3-33629.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:33570.3-33579.6" - wire width 4 $0\src_r2$next[3:0]$1296 - attribute \src "libresoc.v:33240.3-33241.29" + attribute \src "libresoc.v:33970.3-33979.6" + wire width 4 $0\src_r2$next[3:0]$1288 + attribute \src "libresoc.v:33626.3-33627.29" wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:32737.7-32737.24" + attribute \src "libresoc.v:33137.7-33137.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1255 - attribute \src "libresoc.v:32745.14-32745.59" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 + attribute \src "libresoc.v:33145.14-33145.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 - attribute \src "libresoc.v:32762.14-32762.50" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 + attribute \src "libresoc.v:33162.14-33162.50" wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 - attribute \src "libresoc.v:32766.14-32766.70" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + attribute \src "libresoc.v:33166.14-33166.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 - attribute \src "libresoc.v:32770.7-32770.45" + attribute \src "libresoc.v:33859.3-33883.6" + wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + attribute \src "libresoc.v:33170.7-33170.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1259 - attribute \src "libresoc.v:32774.14-32774.45" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 + attribute \src "libresoc.v:33174.14-33174.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 - attribute \src "libresoc.v:32852.13-32852.49" + attribute \src "libresoc.v:33859.3-33883.6" + wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + attribute \src "libresoc.v:33252.13-33252.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 - attribute \src "libresoc.v:32856.7-32856.41" + attribute \src "libresoc.v:33859.3-33883.6" + wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + attribute \src "libresoc.v:33256.7-33256.41" wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire $1\alu_branch0_br_op__lk$next[0:0]$1262 - attribute \src "libresoc.v:32860.7-32860.35" + attribute \src "libresoc.v:33859.3-33883.6" + wire $1\alu_branch0_br_op__lk$next[0:0]$1254 + attribute \src "libresoc.v:33260.7-33260.35" wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:32886.7-32886.26" + attribute \src "libresoc.v:33286.7-33286.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:33589.3-33597.6" - wire $1\alu_l_r_alu$next[0:0]$1303 - attribute \src "libresoc.v:32894.7-32894.25" + attribute \src "libresoc.v:33989.3-33997.6" + wire $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:33294.7-33294.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33580.3-33588.6" - wire $1\alui_l_r_alui$next[0:0]$1300 - attribute \src "libresoc.v:32906.7-32906.27" + attribute \src "libresoc.v:33980.3-33988.6" + wire $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:33306.7-33306.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33484.3-33505.6" - wire width 64 $1\data_r0__fast1$next[63:0]$1268 - attribute \src "libresoc.v:32938.14-32938.51" + attribute \src "libresoc.v:33884.3-33905.6" + wire width 64 $1\data_r0__fast1$next[63:0]$1260 + attribute \src "libresoc.v:33338.14-33338.51" wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:33484.3-33505.6" - wire $1\data_r0__fast1_ok$next[0:0]$1269 - attribute \src "libresoc.v:32942.7-32942.31" + attribute \src "libresoc.v:33884.3-33905.6" + wire $1\data_r0__fast1_ok$next[0:0]$1261 + attribute \src "libresoc.v:33342.7-33342.31" wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33506.3-33527.6" - wire width 64 $1\data_r1__fast2$next[63:0]$1276 - attribute \src "libresoc.v:32946.14-32946.51" + attribute \src "libresoc.v:33906.3-33927.6" + wire width 64 $1\data_r1__fast2$next[63:0]$1268 + attribute \src "libresoc.v:33346.14-33346.51" wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:33506.3-33527.6" - wire $1\data_r1__fast2_ok$next[0:0]$1277 - attribute \src "libresoc.v:32950.7-32950.31" + attribute \src "libresoc.v:33906.3-33927.6" + wire $1\data_r1__fast2_ok$next[0:0]$1269 + attribute \src "libresoc.v:33350.7-33350.31" wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33528.3-33549.6" - wire width 64 $1\data_r2__nia$next[63:0]$1284 - attribute \src "libresoc.v:32954.14-32954.49" + attribute \src "libresoc.v:33928.3-33949.6" + wire width 64 $1\data_r2__nia$next[63:0]$1276 + attribute \src "libresoc.v:33354.14-33354.49" wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:33528.3-33549.6" - wire $1\data_r2__nia_ok$next[0:0]$1285 - attribute \src "libresoc.v:32958.7-32958.29" + attribute \src "libresoc.v:33928.3-33949.6" + wire $1\data_r2__nia_ok$next[0:0]$1277 + attribute \src "libresoc.v:33358.7-33358.29" wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33598.3-33607.6" + attribute \src "libresoc.v:33998.3-34007.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:33608.3-33617.6" + attribute \src "libresoc.v:34008.3-34017.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:33618.3-33627.6" + attribute \src "libresoc.v:34018.3-34027.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:33414.3-33422.6" - wire $1\opc_l_r_opc$next[0:0]$1233 - attribute \src "libresoc.v:32979.7-32979.25" + attribute \src "libresoc.v:33814.3-33822.6" + wire $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:33379.7-33379.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33405.3-33413.6" - wire $1\opc_l_s_opc$next[0:0]$1230 - attribute \src "libresoc.v:32983.7-32983.25" + attribute \src "libresoc.v:33805.3-33813.6" + wire $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:33383.7-33383.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:33628.3-33636.6" - wire width 3 $1\prev_wr_go$next[2:0]$1309 - attribute \src "libresoc.v:33090.13-33090.30" + attribute \src "libresoc.v:34028.3-34036.6" + wire width 3 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:33490.13-33490.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:33359.3-33368.6" + attribute \src "libresoc.v:33759.3-33768.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:33450.3-33458.6" - wire width 3 $1\req_l_r_req$next[2:0]$1245 - attribute \src "libresoc.v:33098.13-33098.31" + attribute \src "libresoc.v:33850.3-33858.6" + wire width 3 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:33498.13-33498.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:33441.3-33449.6" - wire width 3 $1\req_l_s_req$next[2:0]$1242 - attribute \src "libresoc.v:33102.13-33102.31" + attribute \src "libresoc.v:33841.3-33849.6" + wire width 3 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:33502.13-33502.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:33378.3-33386.6" - wire $1\rok_l_r_rdok$next[0:0]$1221 - attribute \src "libresoc.v:33114.7-33114.26" + attribute \src "libresoc.v:33778.3-33786.6" + wire $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:33514.7-33514.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33369.3-33377.6" - wire $1\rok_l_s_rdok$next[0:0]$1218 - attribute \src "libresoc.v:33118.7-33118.26" + attribute \src "libresoc.v:33769.3-33777.6" + wire $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:33518.7-33518.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33396.3-33404.6" - wire $1\rst_l_r_rst$next[0:0]$1227 - attribute \src "libresoc.v:33122.7-33122.25" + attribute \src "libresoc.v:33796.3-33804.6" + wire $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:33522.7-33522.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33387.3-33395.6" - wire $1\rst_l_s_rst$next[0:0]$1224 - attribute \src "libresoc.v:33126.7-33126.25" + attribute \src "libresoc.v:33787.3-33795.6" + wire $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:33526.7-33526.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33432.3-33440.6" - wire width 3 $1\src_l_r_src$next[2:0]$1239 - attribute \src "libresoc.v:33140.13-33140.31" + attribute \src "libresoc.v:33832.3-33840.6" + wire width 3 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:33540.13-33540.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:33423.3-33431.6" - wire width 3 $1\src_l_s_src$next[2:0]$1236 - attribute \src "libresoc.v:33144.13-33144.31" + attribute \src "libresoc.v:33823.3-33831.6" + wire width 3 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:33544.13-33544.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:33550.3-33559.6" - wire width 64 $1\src_r0$next[63:0]$1291 - attribute \src "libresoc.v:33150.14-33150.43" + attribute \src "libresoc.v:33950.3-33959.6" + wire width 64 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:33550.14-33550.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:33560.3-33569.6" - wire width 64 $1\src_r1$next[63:0]$1294 - attribute \src "libresoc.v:33154.14-33154.43" + attribute \src "libresoc.v:33960.3-33969.6" + wire width 64 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:33554.14-33554.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:33570.3-33579.6" - wire width 4 $1\src_r2$next[3:0]$1297 - attribute \src "libresoc.v:33158.13-33158.26" + attribute \src "libresoc.v:33970.3-33979.6" + wire width 4 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:33558.13-33558.26" wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:33459.3-33483.6" - wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 - attribute \src "libresoc.v:33459.3-33483.6" - wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 - attribute \src "libresoc.v:33484.3-33505.6" - wire width 64 $2\data_r0__fast1$next[63:0]$1270 - attribute \src "libresoc.v:33484.3-33505.6" - wire $2\data_r0__fast1_ok$next[0:0]$1271 - attribute \src "libresoc.v:33506.3-33527.6" - wire width 64 $2\data_r1__fast2$next[63:0]$1278 - attribute \src "libresoc.v:33506.3-33527.6" - wire $2\data_r1__fast2_ok$next[0:0]$1279 - attribute \src "libresoc.v:33528.3-33549.6" - wire width 64 $2\data_r2__nia$next[63:0]$1286 - attribute \src "libresoc.v:33528.3-33549.6" - wire $2\data_r2__nia_ok$next[0:0]$1287 - attribute \src "libresoc.v:33484.3-33505.6" - wire $3\data_r0__fast1_ok$next[0:0]$1272 - attribute \src "libresoc.v:33506.3-33527.6" - wire $3\data_r1__fast2_ok$next[0:0]$1280 - attribute \src "libresoc.v:33528.3-33549.6" - wire $3\data_r2__nia_ok$next[0:0]$1288 - attribute \src "libresoc.v:33166.18-33166.112" - wire width 3 $and$libresoc.v:33166$1127_Y - attribute \src "libresoc.v:33167.19-33167.125" - wire $and$libresoc.v:33167$1128_Y - attribute \src "libresoc.v:33168.19-33168.125" - wire $and$libresoc.v:33168$1129_Y - attribute \src "libresoc.v:33169.19-33169.125" - wire $and$libresoc.v:33169$1130_Y - attribute \src "libresoc.v:33170.19-33170.141" - wire width 3 $and$libresoc.v:33170$1131_Y - attribute \src "libresoc.v:33171.19-33171.121" - wire width 3 $and$libresoc.v:33171$1132_Y - attribute \src "libresoc.v:33172.19-33172.127" - wire $and$libresoc.v:33172$1133_Y - attribute \src "libresoc.v:33173.19-33173.127" - wire $and$libresoc.v:33173$1134_Y - attribute \src "libresoc.v:33174.19-33174.127" - wire $and$libresoc.v:33174$1135_Y - attribute \src "libresoc.v:33175.18-33175.110" - wire $and$libresoc.v:33175$1136_Y - attribute \src "libresoc.v:33177.18-33177.98" - wire $and$libresoc.v:33177$1138_Y - attribute \src "libresoc.v:33179.18-33179.100" - wire $and$libresoc.v:33179$1140_Y - attribute \src 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$ternary$libresoc.v:33214$1175_Y + attribute \src "libresoc.v:33859.3-33883.6" + wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 + attribute \src "libresoc.v:33859.3-33883.6" + wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 + attribute \src "libresoc.v:33884.3-33905.6" + wire width 64 $2\data_r0__fast1$next[63:0]$1262 + attribute \src "libresoc.v:33884.3-33905.6" + wire $2\data_r0__fast1_ok$next[0:0]$1263 + attribute \src "libresoc.v:33906.3-33927.6" + wire width 64 $2\data_r1__fast2$next[63:0]$1270 + attribute \src "libresoc.v:33906.3-33927.6" + wire $2\data_r1__fast2_ok$next[0:0]$1271 + attribute \src "libresoc.v:33928.3-33949.6" + wire width 64 $2\data_r2__nia$next[63:0]$1278 + attribute \src "libresoc.v:33928.3-33949.6" + wire $2\data_r2__nia_ok$next[0:0]$1279 + attribute \src "libresoc.v:33884.3-33905.6" + wire $3\data_r0__fast1_ok$next[0:0]$1264 + attribute \src "libresoc.v:33906.3-33927.6" + wire $3\data_r1__fast2_ok$next[0:0]$1272 + attribute \src "libresoc.v:33928.3-33949.6" + wire $3\data_r2__nia_ok$next[0:0]$1280 + attribute \src "libresoc.v:33566.18-33566.112" + wire width 3 $and$libresoc.v:33566$1119_Y + attribute \src "libresoc.v:33567.19-33567.125" + wire $and$libresoc.v:33567$1120_Y + attribute \src "libresoc.v:33568.19-33568.125" + wire $and$libresoc.v:33568$1121_Y + attribute \src "libresoc.v:33569.19-33569.125" + wire $and$libresoc.v:33569$1122_Y + attribute \src "libresoc.v:33570.19-33570.141" + wire width 3 $and$libresoc.v:33570$1123_Y + attribute \src "libresoc.v:33571.19-33571.121" + wire width 3 $and$libresoc.v:33571$1124_Y + attribute \src "libresoc.v:33572.19-33572.127" + wire $and$libresoc.v:33572$1125_Y + attribute \src "libresoc.v:33573.19-33573.127" + wire $and$libresoc.v:33573$1126_Y + attribute \src "libresoc.v:33574.19-33574.127" + wire $and$libresoc.v:33574$1127_Y + attribute \src "libresoc.v:33575.18-33575.110" + wire $and$libresoc.v:33575$1128_Y + attribute \src "libresoc.v:33577.18-33577.98" + wire $and$libresoc.v:33577$1130_Y + attribute \src "libresoc.v:33579.18-33579.100" + wire $and$libresoc.v:33579$1132_Y + attribute \src "libresoc.v:33580.18-33580.149" + wire width 3 $and$libresoc.v:33580$1133_Y + attribute \src "libresoc.v:33582.18-33582.119" + wire width 3 $and$libresoc.v:33582$1135_Y + attribute \src "libresoc.v:33585.18-33585.116" + wire $and$libresoc.v:33585$1138_Y + attribute \src "libresoc.v:33589.17-33589.123" + wire $and$libresoc.v:33589$1142_Y + attribute \src "libresoc.v:33591.18-33591.113" + wire $and$libresoc.v:33591$1144_Y + attribute \src "libresoc.v:33592.18-33592.125" + wire width 3 $and$libresoc.v:33592$1145_Y + attribute \src "libresoc.v:33594.18-33594.112" + wire $and$libresoc.v:33594$1147_Y + attribute \src "libresoc.v:33596.18-33596.129" + wire $and$libresoc.v:33596$1149_Y + attribute \src "libresoc.v:33597.18-33597.129" + wire $and$libresoc.v:33597$1150_Y + attribute \src "libresoc.v:33598.18-33598.117" + wire $and$libresoc.v:33598$1151_Y + attribute \src "libresoc.v:33603.18-33603.133" + wire $and$libresoc.v:33603$1156_Y + attribute \src "libresoc.v:33604.18-33604.124" + wire width 3 $and$libresoc.v:33604$1157_Y + attribute \src "libresoc.v:33607.18-33607.120" + wire $and$libresoc.v:33607$1160_Y + attribute \src "libresoc.v:33608.18-33608.120" + wire $and$libresoc.v:33608$1161_Y + attribute \src "libresoc.v:33609.18-33609.118" + wire $and$libresoc.v:33609$1162_Y + attribute \src "libresoc.v:33615.18-33615.137" + wire $and$libresoc.v:33615$1168_Y + attribute \src "libresoc.v:33617.18-33617.135" + wire $and$libresoc.v:33617$1170_Y + attribute \src "libresoc.v:33618.18-33618.149" + wire width 3 $and$libresoc.v:33618$1171_Y + attribute \src "libresoc.v:33620.18-33620.129" + wire width 3 $and$libresoc.v:33620$1173_Y + attribute \src "libresoc.v:33593.18-33593.113" + wire $eq$libresoc.v:33593$1146_Y + attribute \src "libresoc.v:33595.18-33595.119" + wire $eq$libresoc.v:33595$1148_Y + attribute \src "libresoc.v:33576.18-33576.97" + wire $not$libresoc.v:33576$1129_Y + attribute \src "libresoc.v:33578.18-33578.99" + wire $not$libresoc.v:33578$1131_Y + attribute \src "libresoc.v:33581.18-33581.113" + wire width 3 $not$libresoc.v:33581$1134_Y + attribute \src "libresoc.v:33584.18-33584.106" + wire $not$libresoc.v:33584$1137_Y + attribute \src "libresoc.v:33590.18-33590.123" + wire $not$libresoc.v:33590$1143_Y + attribute \src "libresoc.v:33605.17-33605.113" + wire width 3 $not$libresoc.v:33605$1158_Y + attribute \src "libresoc.v:33619.18-33619.133" + wire $not$libresoc.v:33619$1172_Y + attribute \src "libresoc.v:33621.18-33621.114" + wire width 3 $not$libresoc.v:33621$1174_Y + attribute \src "libresoc.v:33588.18-33588.112" + wire $or$libresoc.v:33588$1141_Y + attribute \src "libresoc.v:33599.18-33599.122" + wire $or$libresoc.v:33599$1152_Y + attribute \src "libresoc.v:33600.18-33600.124" + wire $or$libresoc.v:33600$1153_Y + attribute \src "libresoc.v:33601.18-33601.155" + wire width 3 $or$libresoc.v:33601$1154_Y + attribute \src "libresoc.v:33602.18-33602.155" + wire width 3 $or$libresoc.v:33602$1155_Y + attribute \src "libresoc.v:33606.18-33606.120" + wire width 3 $or$libresoc.v:33606$1159_Y + attribute \src "libresoc.v:33616.17-33616.117" + wire width 3 $or$libresoc.v:33616$1169_Y + attribute \src "libresoc.v:33565.17-33565.104" + wire $reduce_and$libresoc.v:33565$1118_Y + attribute \src "libresoc.v:33583.18-33583.106" + wire $reduce_or$libresoc.v:33583$1136_Y + attribute \src "libresoc.v:33586.18-33586.113" + wire $reduce_or$libresoc.v:33586$1139_Y + attribute \src "libresoc.v:33587.18-33587.112" + wire $reduce_or$libresoc.v:33587$1140_Y + attribute \src "libresoc.v:33610.18-33610.162" + wire $ternary$libresoc.v:33610$1163_Y + attribute \src "libresoc.v:33611.18-33611.176" + wire width 64 $ternary$libresoc.v:33611$1164_Y + attribute \src "libresoc.v:33612.18-33612.118" + wire width 64 $ternary$libresoc.v:33612$1165_Y + attribute \src "libresoc.v:33613.18-33613.115" + wire width 64 $ternary$libresoc.v:33613$1166_Y + attribute \src "libresoc.v:33614.18-33614.118" + wire width 4 $ternary$libresoc.v:33614$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -49743,11 +50075,11 @@ module \branch0 wire \alu_branch0_br_op__lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_branch0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_branch0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_branch0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_branch0_fast2$2 @@ -49755,7 +50087,7 @@ module \branch0 wire \alu_branch0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_branch0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_branch0_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_branch0_p_ready_o @@ -49789,30 +50121,30 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 25 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 10 \cu_busy_o + wire output 11 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 9 \cu_issue_i + wire input 10 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 13 \cu_rd__go_i + wire width 3 input 14 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 12 \cu_rd__rel_o + wire width 3 output 13 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 11 \cu_rdmaskn_i + wire width 3 input 12 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 19 \cu_wr__go_i + wire width 3 input 20 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 18 \cu_wr__rel_o + wire width 3 output 19 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -49840,19 +50172,19 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__nia_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 21 \dest1_o + wire width 64 output 22 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 22 \dest2_o + wire width 64 output 23 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 17 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 20 \fast2_ok - attribute \src "libresoc.v:32619.7-32619.15" + wire width 64 output 25 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \fast2_ok + attribute \src "libresoc.v:33019.7-33019.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -49864,7 +50196,7 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \oper_i_alu_branch0__cia + wire width 64 input 2 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -49879,13 +50211,13 @@ module \branch0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_branch0__fn_unit + wire width 12 input 4 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_branch0__imm_data__data + wire width 64 input 6 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_branch0__imm_data__ok + wire input 7 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \oper_i_alu_branch0__insn + wire width 32 input 5 \oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -49961,11 +50293,11 @@ module \branch0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_branch0__insn_type + wire width 7 input 3 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_branch0__is_32bit + wire input 9 \oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_branch0__lk + wire input 8 \oper_i_alu_branch0__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -50009,11 +50341,11 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src1_i + wire width 64 input 16 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src2_i + wire width 64 input 17 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src3_i + wire width 4 input 15 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -50043,7 +50375,7 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33166$1127 + cell $and $and$libresoc.v:33566$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50051,10 +50383,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:33166$1127_Y + connect \Y $and$libresoc.v:33566$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33167$1128 + cell $and $and$libresoc.v:33567$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50062,10 +50394,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33167$1128_Y + connect \Y $and$libresoc.v:33567$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33168$1129 + cell $and $and$libresoc.v:33568$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50073,10 +50405,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33168$1129_Y + connect \Y $and$libresoc.v:33568$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:33169$1130 + cell $and $and$libresoc.v:33569$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50084,10 +50416,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:33169$1130_Y + connect \Y $and$libresoc.v:33569$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33170$1131 + cell $and $and$libresoc.v:33570$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50095,10 +50427,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:33170$1131_Y + connect \Y $and$libresoc.v:33570$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:33171$1132 + cell $and $and$libresoc.v:33571$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50106,10 +50438,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33171$1132_Y + connect \Y $and$libresoc.v:33571$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33172$1133 + cell $and $and$libresoc.v:33572$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50117,10 +50449,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33172$1133_Y + connect \Y $and$libresoc.v:33572$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33173$1134 + cell $and $and$libresoc.v:33573$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50128,10 +50460,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33173$1134_Y + connect \Y $and$libresoc.v:33573$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:33174$1135 + cell $and $and$libresoc.v:33574$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50139,10 +50471,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:33174$1135_Y + connect \Y $and$libresoc.v:33574$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:33175$1136 + cell $and $and$libresoc.v:33575$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50150,10 +50482,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:33175$1136_Y + connect \Y $and$libresoc.v:33575$1128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:33177$1138 + cell $and $and$libresoc.v:33577$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50161,10 +50493,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:33177$1138_Y + connect \Y $and$libresoc.v:33577$1130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:33179$1140 + cell $and $and$libresoc.v:33579$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50172,10 +50504,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:33179$1140_Y + connect \Y $and$libresoc.v:33579$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:33180$1141 + cell $and $and$libresoc.v:33580$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50183,10 +50515,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33180$1141_Y + connect \Y $and$libresoc.v:33580$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33182$1143 + cell $and $and$libresoc.v:33582$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50194,10 +50526,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:33182$1143_Y + connect \Y $and$libresoc.v:33582$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:33185$1146 + cell $and $and$libresoc.v:33585$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50205,10 +50537,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:33185$1146_Y + connect \Y $and$libresoc.v:33585$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:33189$1150 + cell $and $and$libresoc.v:33589$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50216,10 +50548,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:33189$1150_Y + connect \Y $and$libresoc.v:33589$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:33191$1152 + cell $and $and$libresoc.v:33591$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50227,10 +50559,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:33191$1152_Y + connect \Y $and$libresoc.v:33591$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33192$1153 + cell $and $and$libresoc.v:33592$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50238,10 +50570,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33192$1153_Y + connect \Y $and$libresoc.v:33592$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:33194$1155 + cell $and $and$libresoc.v:33594$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50249,10 +50581,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:33194$1155_Y + connect \Y $and$libresoc.v:33594$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33196$1157 + cell $and $and$libresoc.v:33596$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50260,10 +50592,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:33196$1157_Y + connect \Y $and$libresoc.v:33596$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33197$1158 + cell $and $and$libresoc.v:33597$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50271,10 +50603,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:33197$1158_Y + connect \Y $and$libresoc.v:33597$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33198$1159 + cell $and $and$libresoc.v:33598$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50282,10 +50614,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:33198$1159_Y + connect \Y $and$libresoc.v:33598$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:33203$1164 + cell $and $and$libresoc.v:33603$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50293,10 +50625,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:33203$1164_Y + connect \Y $and$libresoc.v:33603$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:33204$1165 + cell $and $and$libresoc.v:33604$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50304,10 +50636,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33204$1165_Y + connect \Y $and$libresoc.v:33604$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33207$1168 + cell $and $and$libresoc.v:33607$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50315,10 +50647,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33207$1168_Y + connect \Y $and$libresoc.v:33607$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33208$1169 + cell $and $and$libresoc.v:33608$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50326,10 +50658,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33208$1169_Y + connect \Y $and$libresoc.v:33608$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33209$1170 + cell $and $and$libresoc.v:33609$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50337,10 +50669,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:33209$1170_Y + connect \Y $and$libresoc.v:33609$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:33215$1176 + cell $and $and$libresoc.v:33615$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50348,10 +50680,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:33215$1176_Y + connect \Y $and$libresoc.v:33615$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:33217$1178 + cell $and $and$libresoc.v:33617$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50359,10 +50691,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:33217$1178_Y + connect \Y $and$libresoc.v:33617$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33218$1179 + cell $and $and$libresoc.v:33618$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50370,10 +50702,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:33218$1179_Y + connect \Y $and$libresoc.v:33618$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33220$1181 + cell $and $and$libresoc.v:33620$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50381,10 +50713,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } - connect \Y $and$libresoc.v:33220$1181_Y + connect \Y $and$libresoc.v:33620$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:33193$1154 + cell $eq $eq$libresoc.v:33593$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50392,10 +50724,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:33193$1154_Y + connect \Y $eq$libresoc.v:33593$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:33195$1156 + cell $eq $eq$libresoc.v:33595$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50403,74 +50735,74 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:33195$1156_Y + connect \Y $eq$libresoc.v:33595$1148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33176$1137 + cell $not $not$libresoc.v:33576$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:33176$1137_Y + connect \Y $not$libresoc.v:33576$1129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33178$1139 + cell $not $not$libresoc.v:33578$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:33178$1139_Y + connect \Y $not$libresoc.v:33578$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33181$1142 + cell $not $not$libresoc.v:33581$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:33181$1142_Y + connect \Y $not$libresoc.v:33581$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33184$1145 + cell $not $not$libresoc.v:33584$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:33184$1145_Y + connect \Y $not$libresoc.v:33584$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:33190$1151 + cell $not $not$libresoc.v:33590$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:33190$1151_Y + connect \Y $not$libresoc.v:33590$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:33205$1166 + cell $not $not$libresoc.v:33605$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:33205$1166_Y + connect \Y $not$libresoc.v:33605$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:33219$1180 + cell $not $not$libresoc.v:33619$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:33219$1180_Y + connect \Y $not$libresoc.v:33619$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:33221$1182 + cell $not $not$libresoc.v:33621$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:33221$1182_Y + connect \Y $not$libresoc.v:33621$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:33188$1149 + cell $or $or$libresoc.v:33588$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50478,10 +50810,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:33188$1149_Y + connect \Y $or$libresoc.v:33588$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:33199$1160 + cell $or $or$libresoc.v:33599$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50489,10 +50821,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33199$1160_Y + connect \Y $or$libresoc.v:33599$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:33200$1161 + cell $or $or$libresoc.v:33600$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50500,10 +50832,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33200$1161_Y + connect \Y $or$libresoc.v:33600$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:33201$1162 + cell $or $or$libresoc.v:33601$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50511,10 +50843,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33201$1162_Y + connect \Y $or$libresoc.v:33601$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:33202$1163 + cell $or $or$libresoc.v:33602$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50522,10 +50854,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33202$1163_Y + connect \Y $or$libresoc.v:33602$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:33206$1167 + cell $or $or$libresoc.v:33606$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50533,10 +50865,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:33206$1167_Y + connect \Y $or$libresoc.v:33606$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:33216$1177 + cell $or $or$libresoc.v:33616$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50544,82 +50876,82 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:33216$1177_Y + connect \Y $or$libresoc.v:33616$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:33165$1126 + cell $reduce_and $reduce_and$libresoc.v:33565$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:33165$1126_Y + connect \Y $reduce_and$libresoc.v:33565$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:33183$1144 + cell $reduce_or $reduce_or$libresoc.v:33583$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:33183$1144_Y + connect \Y $reduce_or$libresoc.v:33583$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33186$1147 + cell $reduce_or $reduce_or$libresoc.v:33586$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:33186$1147_Y + connect \Y $reduce_or$libresoc.v:33586$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33187$1148 + cell $reduce_or $reduce_or$libresoc.v:33587$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:33187$1148_Y + connect \Y $reduce_or$libresoc.v:33587$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:33210$1171 + cell $mux $ternary$libresoc.v:33610$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33210$1171_Y + connect \Y $ternary$libresoc.v:33610$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:33211$1172 + cell $mux $ternary$libresoc.v:33611$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33211$1172_Y + connect \Y $ternary$libresoc.v:33611$1164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33212$1173 + cell $mux $ternary$libresoc.v:33612$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:33212$1173_Y + connect \Y $ternary$libresoc.v:33612$1165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33213$1174 + cell $mux $ternary$libresoc.v:33613$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:33213$1174_Y + connect \Y $ternary$libresoc.v:33613$1166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33214$1175 + cell $mux $ternary$libresoc.v:33614$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:33214$1175_Y + connect \Y $ternary$libresoc.v:33614$1167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:33286.15-33310.4" + attribute \src "libresoc.v:33686.15-33710.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit @@ -50646,7 +50978,7 @@ module \branch0 connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:33311.14-33317.4" + attribute \src "libresoc.v:33711.14-33717.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50655,7 +50987,7 @@ module \branch0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:33318.15-33324.4" + attribute \src "libresoc.v:33718.15-33724.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50664,7 +50996,7 @@ module \branch0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:33325.14-33331.4" + attribute \src "libresoc.v:33725.14-33731.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50673,7 +51005,7 @@ module \branch0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:33332.14-33338.4" + attribute \src "libresoc.v:33732.14-33738.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50682,7 +51014,7 @@ module \branch0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:33339.14-33345.4" + attribute \src "libresoc.v:33739.14-33745.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50691,7 +51023,7 @@ module \branch0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:33346.14-33351.4" + attribute \src "libresoc.v:33746.14-33751.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50699,7 +51031,7 @@ module \branch0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:33352.14-33358.4" + attribute \src "libresoc.v:33752.14-33758.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -50707,663 +51039,525 @@ module \branch0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:32619.7-32619.20" - process $proc$libresoc.v:32619$1310 + attribute \src "libresoc.v:33019.7-33019.20" + process $proc$libresoc.v:33019$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32737.7-32737.24" - process $proc$libresoc.v:32737$1311 + attribute \src "libresoc.v:33137.7-33137.24" + process $proc$libresoc.v:33137$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:32745.14-32745.59" - process $proc$libresoc.v:32745$1312 + attribute \src "libresoc.v:33145.14-33145.59" + process $proc$libresoc.v:33145$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:32762.14-32762.50" - process $proc$libresoc.v:32762$1313 + attribute \src "libresoc.v:33162.14-33162.50" + process $proc$libresoc.v:33162$1305 assign { } { } assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] end - attribute \src "libresoc.v:32766.14-32766.70" - process $proc$libresoc.v:32766$1314 + attribute \src "libresoc.v:33166.14-33166.70" + process $proc$libresoc.v:33166$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:32770.7-32770.45" - process $proc$libresoc.v:32770$1315 + attribute \src "libresoc.v:33170.7-33170.45" + process $proc$libresoc.v:33170$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:32774.14-32774.45" - process $proc$libresoc.v:32774$1316 + attribute \src "libresoc.v:33174.14-33174.45" + process $proc$libresoc.v:33174$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:32852.13-32852.49" - process $proc$libresoc.v:32852$1317 + attribute \src "libresoc.v:33252.13-33252.49" + process $proc$libresoc.v:33252$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:32856.7-32856.41" - process $proc$libresoc.v:32856$1318 + attribute \src "libresoc.v:33256.7-33256.41" + process $proc$libresoc.v:33256$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:32860.7-32860.35" - process $proc$libresoc.v:32860$1319 + attribute \src "libresoc.v:33260.7-33260.35" + process $proc$libresoc.v:33260$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:32886.7-32886.26" - process $proc$libresoc.v:32886$1320 + attribute \src "libresoc.v:33286.7-33286.26" + process $proc$libresoc.v:33286$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:32894.7-32894.25" - process $proc$libresoc.v:32894$1321 + attribute \src "libresoc.v:33294.7-33294.25" + process $proc$libresoc.v:33294$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:32906.7-32906.27" - process $proc$libresoc.v:32906$1322 + attribute \src "libresoc.v:33306.7-33306.27" + process $proc$libresoc.v:33306$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:32938.14-32938.51" - process $proc$libresoc.v:32938$1323 + attribute \src "libresoc.v:33338.14-33338.51" + process $proc$libresoc.v:33338$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end - attribute \src "libresoc.v:32942.7-32942.31" - process $proc$libresoc.v:32942$1324 + attribute \src "libresoc.v:33342.7-33342.31" + process $proc$libresoc.v:33342$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:32946.14-32946.51" - process $proc$libresoc.v:32946$1325 + attribute \src "libresoc.v:33346.14-33346.51" + process $proc$libresoc.v:33346$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end - attribute \src "libresoc.v:32950.7-32950.31" - process $proc$libresoc.v:32950$1326 + attribute \src "libresoc.v:33350.7-33350.31" + process $proc$libresoc.v:33350$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:32954.14-32954.49" - process $proc$libresoc.v:32954$1327 + attribute \src "libresoc.v:33354.14-33354.49" + process $proc$libresoc.v:33354$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end - attribute \src "libresoc.v:32958.7-32958.29" - process $proc$libresoc.v:32958$1328 + attribute \src "libresoc.v:33358.7-33358.29" + process $proc$libresoc.v:33358$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:32979.7-32979.25" - process $proc$libresoc.v:32979$1329 + attribute \src "libresoc.v:33379.7-33379.25" + process $proc$libresoc.v:33379$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:32983.7-32983.25" - process $proc$libresoc.v:32983$1330 + attribute \src "libresoc.v:33383.7-33383.25" + process $proc$libresoc.v:33383$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33090.13-33090.30" - process $proc$libresoc.v:33090$1331 + attribute \src "libresoc.v:33490.13-33490.30" + process $proc$libresoc.v:33490$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:33098.13-33098.31" - process $proc$libresoc.v:33098$1332 + attribute \src "libresoc.v:33498.13-33498.31" + process $proc$libresoc.v:33498$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:33102.13-33102.31" - process $proc$libresoc.v:33102$1333 + attribute \src "libresoc.v:33502.13-33502.31" + process $proc$libresoc.v:33502$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:33114.7-33114.26" - process $proc$libresoc.v:33114$1334 + attribute \src "libresoc.v:33514.7-33514.26" + process $proc$libresoc.v:33514$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33118.7-33118.26" - process $proc$libresoc.v:33118$1335 + attribute \src "libresoc.v:33518.7-33518.26" + process $proc$libresoc.v:33518$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33122.7-33122.25" - process $proc$libresoc.v:33122$1336 + attribute \src "libresoc.v:33522.7-33522.25" + process $proc$libresoc.v:33522$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33126.7-33126.25" - process $proc$libresoc.v:33126$1337 + attribute \src "libresoc.v:33526.7-33526.25" + process $proc$libresoc.v:33526$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33140.13-33140.31" - process $proc$libresoc.v:33140$1338 + attribute \src "libresoc.v:33540.13-33540.31" + process $proc$libresoc.v:33540$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:33144.13-33144.31" - process $proc$libresoc.v:33144$1339 + attribute \src "libresoc.v:33544.13-33544.31" + process $proc$libresoc.v:33544$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:33150.14-33150.43" - process $proc$libresoc.v:33150$1340 + attribute \src "libresoc.v:33550.14-33550.43" + process $proc$libresoc.v:33550$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:33154.14-33154.43" - process $proc$libresoc.v:33154$1341 + attribute \src "libresoc.v:33554.14-33554.43" + process $proc$libresoc.v:33554$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:33158.13-33158.26" - process $proc$libresoc.v:33158$1342 + attribute \src "libresoc.v:33558.13-33558.26" + process $proc$libresoc.v:33558$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end - attribute \src "libresoc.v:33222.3-33223.39" - process $proc$libresoc.v:33222$1183 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:33224.3-33225.39" - process $proc$libresoc.v:33224$1184 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:33226.3-33227.41" - process $proc$libresoc.v:33226$1185 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:33228.3-33229.41" - process $proc$libresoc.v:33228$1186 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:33230.3-33231.37" - process $proc$libresoc.v:33230$1187 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "libresoc.v:33232.3-33233.43" - process $proc$libresoc.v:33232$1188 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:33234.3-33235.25" - process $proc$libresoc.v:33234$1189 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:33236.3-33237.39" - process $proc$libresoc.v:33236$1190 + attribute \src "libresoc.v:33622.3-33623.39" + process $proc$libresoc.v:33622$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33238.3-33239.43" - process $proc$libresoc.v:33238$1191 + attribute \src "libresoc.v:33624.3-33625.43" + process $proc$libresoc.v:33624$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33240.3-33241.29" - process $proc$libresoc.v:33240$1192 + attribute \src "libresoc.v:33626.3-33627.29" + process $proc$libresoc.v:33626$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end - attribute \src "libresoc.v:33242.3-33243.29" - process $proc$libresoc.v:33242$1193 + attribute \src "libresoc.v:33628.3-33629.29" + process $proc$libresoc.v:33628$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:33244.3-33245.29" - process $proc$libresoc.v:33244$1194 + attribute \src "libresoc.v:33630.3-33631.29" + process $proc$libresoc.v:33630$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:33246.3-33247.41" - process $proc$libresoc.v:33246$1195 + attribute \src "libresoc.v:33632.3-33633.41" + process $proc$libresoc.v:33632$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end - attribute \src "libresoc.v:33248.3-33249.47" - process $proc$libresoc.v:33248$1196 + attribute \src "libresoc.v:33634.3-33635.47" + process $proc$libresoc.v:33634$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33250.3-33251.45" - process $proc$libresoc.v:33250$1197 + attribute \src "libresoc.v:33636.3-33637.45" + process $proc$libresoc.v:33636$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33252.3-33253.51" - process $proc$libresoc.v:33252$1198 + attribute \src "libresoc.v:33638.3-33639.51" + process $proc$libresoc.v:33638$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33254.3-33255.45" - process $proc$libresoc.v:33254$1199 + attribute \src "libresoc.v:33640.3-33641.45" + process $proc$libresoc.v:33640$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33256.3-33257.51" - process $proc$libresoc.v:33256$1200 + attribute \src "libresoc.v:33642.3-33643.51" + process $proc$libresoc.v:33642$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33258.3-33259.61" - process $proc$libresoc.v:33258$1201 + attribute \src "libresoc.v:33644.3-33645.61" + process $proc$libresoc.v:33644$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33260.3-33261.73" - process $proc$libresoc.v:33260$1202 + attribute \src "libresoc.v:33646.3-33647.73" + process $proc$libresoc.v:33646$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33262.3-33263.69" - process $proc$libresoc.v:33262$1203 + attribute \src "libresoc.v:33648.3-33649.69" + process $proc$libresoc.v:33648$1188 assign { } { } assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] end - attribute \src "libresoc.v:33264.3-33265.63" - process $proc$libresoc.v:33264$1204 + attribute \src "libresoc.v:33650.3-33651.63" + process $proc$libresoc.v:33650$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33266.3-33267.83" - process $proc$libresoc.v:33266$1205 + attribute \src "libresoc.v:33652.3-33653.83" + process $proc$libresoc.v:33652$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33268.3-33269.79" - process $proc$libresoc.v:33268$1206 + attribute \src "libresoc.v:33654.3-33655.79" + process $proc$libresoc.v:33654$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33270.3-33271.59" - process $proc$libresoc.v:33270$1207 + attribute \src "libresoc.v:33656.3-33657.59" + process $proc$libresoc.v:33656$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33272.3-33273.71" - process $proc$libresoc.v:33272$1208 + attribute \src "libresoc.v:33658.3-33659.71" + process $proc$libresoc.v:33658$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33274.3-33275.39" - process $proc$libresoc.v:33274$1209 + attribute \src "libresoc.v:33660.3-33661.39" + process $proc$libresoc.v:33660$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:33276.3-33277.39" - process $proc$libresoc.v:33276$1210 + attribute \src "libresoc.v:33662.3-33663.39" + process $proc$libresoc.v:33662$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:33278.3-33279.39" - process $proc$libresoc.v:33278$1211 + attribute \src "libresoc.v:33664.3-33665.39" + process $proc$libresoc.v:33664$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:33280.3-33281.39" - process $proc$libresoc.v:33280$1212 + attribute \src "libresoc.v:33666.3-33667.39" + process $proc$libresoc.v:33666$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:33282.3-33283.39" - process $proc$libresoc.v:33282$1213 + attribute \src "libresoc.v:33668.3-33669.39" + process $proc$libresoc.v:33668$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33284.3-33285.39" - process $proc$libresoc.v:33284$1214 + attribute \src "libresoc.v:33670.3-33671.39" + process $proc$libresoc.v:33670$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33359.3-33368.6" - process $proc$libresoc.v:33359$1215 - assign { } { } + attribute \src "libresoc.v:33672.3-33673.39" + process $proc$libresoc.v:33672$1200 assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:33360.5-33360.29" - switch \initial - attribute \src "libresoc.v:33360.9-33360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33369.3-33377.6" - process $proc$libresoc.v:33369$1216 - assign { } { } + attribute \src "libresoc.v:33674.3-33675.39" + process $proc$libresoc.v:33674$1201 assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$1217 $1\rok_l_s_rdok$next[0:0]$1218 - attribute \src "libresoc.v:33370.5-33370.29" - switch \initial - attribute \src "libresoc.v:33370.9-33370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$1218 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$1218 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1217 + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:33378.3-33386.6" - process $proc$libresoc.v:33378$1219 - assign { } { } + attribute \src "libresoc.v:33676.3-33677.41" + process $proc$libresoc.v:33676$1202 assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$1220 $1\rok_l_r_rdok$next[0:0]$1221 - attribute \src "libresoc.v:33379.5-33379.29" - switch \initial - attribute \src "libresoc.v:33379.9-33379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$1221 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$1221 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1220 + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33387.3-33395.6" - process $proc$libresoc.v:33387$1222 + attribute \src "libresoc.v:33678.3-33679.41" + process $proc$libresoc.v:33678$1203 assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$1223 $1\rst_l_s_rst$next[0:0]$1224 - attribute \src "libresoc.v:33388.5-33388.29" - switch \initial - attribute \src "libresoc.v:33388.9-33388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$1224 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$1224 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1223 + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33396.3-33404.6" - process $proc$libresoc.v:33396$1225 + attribute \src "libresoc.v:33680.3-33681.37" + process $proc$libresoc.v:33680$1204 assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$1226 $1\rst_l_r_rst$next[0:0]$1227 - attribute \src "libresoc.v:33397.5-33397.29" - switch \initial - attribute \src "libresoc.v:33397.9-33397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$1227 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$1227 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1226 + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:33405.3-33413.6" - process $proc$libresoc.v:33405$1228 + attribute \src "libresoc.v:33682.3-33683.43" + process $proc$libresoc.v:33682$1205 assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33684.3-33685.25" + process $proc$libresoc.v:33684$1206 assign { } { } - assign $0\opc_l_s_opc$next[0:0]$1229 $1\opc_l_s_opc$next[0:0]$1230 - attribute \src "libresoc.v:33406.5-33406.29" - switch \initial - attribute \src "libresoc.v:33406.9-33406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$1230 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$1230 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1229 + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:33414.3-33422.6" - process $proc$libresoc.v:33414$1231 + attribute \src "libresoc.v:33759.3-33768.6" + process $proc$libresoc.v:33759$1207 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$1232 $1\opc_l_r_opc$next[0:0]$1233 - attribute \src "libresoc.v:33415.5-33415.29" + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:33760.5-33760.29" switch \initial - attribute \src "libresoc.v:33415.9-33415.17" + attribute \src "libresoc.v:33760.9-33760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$1233 1'1 + assign $1\req_done[0:0] 1'1 case - assign $1\opc_l_r_opc$next[0:0]$1233 \req_done + assign $1\req_done[0:0] \$47 end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1232 + update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:33423.3-33431.6" - process $proc$libresoc.v:33423$1234 + attribute \src "libresoc.v:33769.3-33777.6" + process $proc$libresoc.v:33769$1208 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$1235 $1\src_l_s_src$next[2:0]$1236 - attribute \src "libresoc.v:33424.5-33424.29" + assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:33770.5-33770.29" switch \initial - attribute \src "libresoc.v:33424.9-33424.17" + attribute \src "libresoc.v:33770.9-33770.17" case 1'1 case end @@ -51372,21 +51566,21 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$1236 3'000 + assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 case - assign $1\src_l_s_src$next[2:0]$1236 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1235 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end - attribute \src "libresoc.v:33432.3-33440.6" - process $proc$libresoc.v:33432$1237 + attribute \src "libresoc.v:33778.3-33786.6" + process $proc$libresoc.v:33778$1211 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$1238 $1\src_l_r_src$next[2:0]$1239 - attribute \src "libresoc.v:33433.5-33433.29" + assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:33779.5-33779.29" switch \initial - attribute \src "libresoc.v:33433.9-33433.17" + attribute \src "libresoc.v:33779.9-33779.17" case 1'1 case end @@ -51395,21 +51589,21 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$1239 3'111 + assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 case - assign $1\src_l_r_src$next[2:0]$1239 \reset_r + assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1238 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end - attribute \src "libresoc.v:33441.3-33449.6" - process $proc$libresoc.v:33441$1240 + attribute \src "libresoc.v:33787.3-33795.6" + process $proc$libresoc.v:33787$1214 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$1241 $1\req_l_s_req$next[2:0]$1242 - attribute \src "libresoc.v:33442.5-33442.29" + assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:33788.5-33788.29" switch \initial - attribute \src "libresoc.v:33442.9-33442.17" + attribute \src "libresoc.v:33788.9-33788.17" case 1'1 case end @@ -51418,21 +51612,21 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$1242 3'000 + assign $1\rst_l_s_rst$next[0:0]$1216 1'0 case - assign $1\req_l_s_req$next[2:0]$1242 \$67 + assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1241 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end - attribute \src "libresoc.v:33450.3-33458.6" - process $proc$libresoc.v:33450$1243 + attribute \src "libresoc.v:33796.3-33804.6" + process $proc$libresoc.v:33796$1217 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$1244 $1\req_l_r_req$next[2:0]$1245 - attribute \src "libresoc.v:33451.5-33451.29" + assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:33797.5-33797.29" switch \initial - attribute \src "libresoc.v:33451.9-33451.17" + attribute \src "libresoc.v:33797.9-33797.17" case 1'1 case end @@ -51441,325 +51635,113 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$1245 3'111 + assign $1\rst_l_r_rst$next[0:0]$1219 1'1 case - assign $1\req_l_r_req$next[2:0]$1245 \$69 + assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1244 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end - attribute \src "libresoc.v:33459.3-33483.6" - process $proc$libresoc.v:33459$1246 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:33805.3-33813.6" + process $proc$libresoc.v:33805$1220 assign { } { } assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__cia$next[63:0]$1247 $1\alu_branch0_br_op__cia$next[63:0]$1255 - assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 - assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__insn$next[31:0]$1259 - assign $0\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 - assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 - assign $0\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__lk$next[0:0]$1262 - assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 - assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 - attribute \src "libresoc.v:33460.5-33460.29" + assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:33806.5-33806.29" switch \initial - attribute \src "libresoc.v:33460.9-33460.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:33806.9-33806.17" case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 $1\alu_branch0_br_op__lk$next[0:0]$1262 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 $1\alu_branch0_br_op__insn$next[31:0]$1259 $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 $1\alu_branch0_br_op__insn_type$next[6:0]$1260 $1\alu_branch0_br_op__cia$next[63:0]$1255 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } case - assign $1\alu_branch0_br_op__cia$next[63:0]$1255 \alu_branch0_br_op__cia - assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1256 \alu_branch0_br_op__fn_unit - assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 \alu_branch0_br_op__imm_data__data - assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 \alu_branch0_br_op__imm_data__ok - assign $1\alu_branch0_br_op__insn$next[31:0]$1259 \alu_branch0_br_op__insn - assign $1\alu_branch0_br_op__insn_type$next[6:0]$1260 \alu_branch0_br_op__insn_type - assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1261 \alu_branch0_br_op__is_32bit - assign $1\alu_branch0_br_op__lk$next[0:0]$1262 \alu_branch0_br_op__lk end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 1'0 + assign $1\opc_l_s_opc$next[0:0]$1222 1'0 case - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1263 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1257 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1264 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1258 + assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i end sync always - update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1247 - update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1248 - update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1251 - update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1252 - update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1253 - update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1254 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end - attribute \src "libresoc.v:33484.3-33505.6" - process $proc$libresoc.v:33484$1265 + attribute \src "libresoc.v:33814.3-33822.6" + process $proc$libresoc.v:33814$1223 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__fast1$next[63:0]$1266 $2\data_r0__fast1$next[63:0]$1270 - assign { } { } - assign $0\data_r0__fast1_ok$next[0:0]$1267 $3\data_r0__fast1_ok$next[0:0]$1272 - attribute \src "libresoc.v:33485.5-33485.29" + assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:33815.5-33815.29" switch \initial - attribute \src "libresoc.v:33485.9-33485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__fast1_ok$next[0:0]$1269 $1\data_r0__fast1$next[63:0]$1268 } { \fast1_ok \alu_branch0_fast1 } - case - assign $1\data_r0__fast1$next[63:0]$1268 \data_r0__fast1 - assign $1\data_r0__fast1_ok$next[0:0]$1269 \data_r0__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:33815.9-33815.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__fast1_ok$next[0:0]$1271 $2\data_r0__fast1$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__fast1$next[63:0]$1270 $1\data_r0__fast1$next[63:0]$1268 - assign $2\data_r0__fast1_ok$next[0:0]$1271 $1\data_r0__fast1_ok$next[0:0]$1269 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__fast1_ok$next[0:0]$1272 1'0 + assign $1\opc_l_r_opc$next[0:0]$1225 1'1 case - assign $3\data_r0__fast1_ok$next[0:0]$1272 $2\data_r0__fast1_ok$next[0:0]$1271 + assign $1\opc_l_r_opc$next[0:0]$1225 \req_done end sync always - update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1266 - update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1267 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end - attribute \src "libresoc.v:33506.3-33527.6" - process $proc$libresoc.v:33506$1273 - assign { } { } - assign { } { } + attribute \src "libresoc.v:33823.3-33831.6" + process $proc$libresoc.v:33823$1226 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__fast2$next[63:0]$1274 $2\data_r1__fast2$next[63:0]$1278 - assign { } { } - assign $0\data_r1__fast2_ok$next[0:0]$1275 $3\data_r1__fast2_ok$next[0:0]$1280 - attribute \src "libresoc.v:33507.5-33507.29" + assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:33824.5-33824.29" switch \initial - attribute \src "libresoc.v:33507.9-33507.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__fast2_ok$next[0:0]$1277 $1\data_r1__fast2$next[63:0]$1276 } { \fast2_ok \alu_branch0_fast2 } - case - assign $1\data_r1__fast2$next[63:0]$1276 \data_r1__fast2 - assign $1\data_r1__fast2_ok$next[0:0]$1277 \data_r1__fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:33824.9-33824.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__fast2_ok$next[0:0]$1279 $2\data_r1__fast2$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast2$next[63:0]$1278 $1\data_r1__fast2$next[63:0]$1276 - assign $2\data_r1__fast2_ok$next[0:0]$1279 $1\data_r1__fast2_ok$next[0:0]$1277 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast2_ok$next[0:0]$1280 1'0 + assign $1\src_l_s_src$next[2:0]$1228 3'000 case - assign $3\data_r1__fast2_ok$next[0:0]$1280 $2\data_r1__fast2_ok$next[0:0]$1279 + assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1274 - update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1275 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end - attribute \src "libresoc.v:33528.3-33549.6" - process $proc$libresoc.v:33528$1281 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:33832.3-33840.6" + process $proc$libresoc.v:33832$1229 assign { } { } assign { } { } - assign { } { } - assign $0\data_r2__nia$next[63:0]$1282 $2\data_r2__nia$next[63:0]$1286 - assign { } { } - assign $0\data_r2__nia_ok$next[0:0]$1283 $3\data_r2__nia_ok$next[0:0]$1288 - attribute \src "libresoc.v:33529.5-33529.29" + assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:33833.5-33833.29" switch \initial - attribute \src "libresoc.v:33529.9-33529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__nia_ok$next[0:0]$1285 $1\data_r2__nia$next[63:0]$1284 } { \nia_ok \alu_branch0_nia } - case - assign $1\data_r2__nia$next[63:0]$1284 \data_r2__nia - assign $1\data_r2__nia_ok$next[0:0]$1285 \data_r2__nia_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:33833.9-33833.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__nia_ok$next[0:0]$1287 $2\data_r2__nia$next[63:0]$1286 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__nia$next[63:0]$1286 $1\data_r2__nia$next[63:0]$1284 - assign $2\data_r2__nia_ok$next[0:0]$1287 $1\data_r2__nia_ok$next[0:0]$1285 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__nia_ok$next[0:0]$1288 1'0 - case - assign $3\data_r2__nia_ok$next[0:0]$1288 $2\data_r2__nia_ok$next[0:0]$1287 - end - sync always - update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1282 - update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1283 - end - attribute \src "libresoc.v:33550.3-33559.6" - process $proc$libresoc.v:33550$1289 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$1290 $1\src_r0$next[63:0]$1291 - attribute \src "libresoc.v:33551.5-33551.29" - switch \initial - attribute \src "libresoc.v:33551.9-33551.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$1291 \src1_i - case - assign $1\src_r0$next[63:0]$1291 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$1290 - end - attribute \src "libresoc.v:33560.3-33569.6" - process $proc$libresoc.v:33560$1292 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$1293 $1\src_r1$next[63:0]$1294 - attribute \src "libresoc.v:33561.5-33561.29" - switch \initial - attribute \src "libresoc.v:33561.9-33561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$1294 \src_or_imm - case - assign $1\src_r1$next[63:0]$1294 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$1293 - end - attribute \src "libresoc.v:33570.3-33579.6" - process $proc$libresoc.v:33570$1295 - assign { } { } - assign { } { } - assign $0\src_r2$next[3:0]$1296 $1\src_r2$next[3:0]$1297 - attribute \src "libresoc.v:33571.5-33571.29" - switch \initial - attribute \src "libresoc.v:33571.9-33571.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[3:0]$1297 \src3_i + assign $1\src_l_r_src$next[2:0]$1231 3'111 case - assign $1\src_r2$next[3:0]$1297 \src_r2 + assign $1\src_l_r_src$next[2:0]$1231 \reset_r end sync always - update \src_r2$next $0\src_r2$next[3:0]$1296 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end - attribute \src "libresoc.v:33580.3-33588.6" - process $proc$libresoc.v:33580$1298 + attribute \src "libresoc.v:33841.3-33849.6" + process $proc$libresoc.v:33841$1232 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$1299 $1\alui_l_r_alui$next[0:0]$1300 - attribute \src "libresoc.v:33581.5-33581.29" + assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:33842.5-33842.29" switch \initial - attribute \src "libresoc.v:33581.9-33581.17" + attribute \src "libresoc.v:33842.9-33842.17" case 1'1 case end @@ -51768,21 +51750,21 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$1300 1'1 + assign $1\req_l_s_req$next[2:0]$1234 3'000 case - assign $1\alui_l_r_alui$next[0:0]$1300 \$87 + assign $1\req_l_s_req$next[2:0]$1234 \$67 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1299 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end - attribute \src "libresoc.v:33589.3-33597.6" - process $proc$libresoc.v:33589$1301 + attribute \src "libresoc.v:33850.3-33858.6" + process $proc$libresoc.v:33850$1235 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$1302 $1\alu_l_r_alu$next[0:0]$1303 - attribute \src "libresoc.v:33590.5-33590.29" + assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:33851.5-33851.29" switch \initial - attribute \src "libresoc.v:33590.9-33590.17" + attribute \src "libresoc.v:33851.9-33851.17" case 1'1 case end @@ -51791,21 +51773,371 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$1303 1'1 + assign $1\req_l_r_req$next[2:0]$1237 3'111 case - assign $1\alu_l_r_alu$next[0:0]$1303 \$89 + assign $1\req_l_r_req$next[2:0]$1237 \$69 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1302 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end - attribute \src "libresoc.v:33598.3-33607.6" - process $proc$libresoc.v:33598$1304 + attribute \src "libresoc.v:33859.3-33883.6" + process $proc$libresoc.v:33859$1238 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 + assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 + attribute \src "libresoc.v:33860.5-33860.29" + switch \initial + attribute \src "libresoc.v:33860.9-33860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 + end + attribute \src "libresoc.v:33884.3-33905.6" + process $proc$libresoc.v:33884$1257 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 + attribute \src "libresoc.v:33885.5-33885.29" + switch \initial + attribute \src "libresoc.v:33885.9-33885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 + assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 + end + attribute \src "libresoc.v:33906.3-33927.6" + process $proc$libresoc.v:33906$1265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 + attribute \src "libresoc.v:33907.5-33907.29" + switch \initial + attribute \src "libresoc.v:33907.9-33907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 + assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 + end + attribute \src "libresoc.v:33928.3-33949.6" + process $proc$libresoc.v:33928$1273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 + attribute \src "libresoc.v:33929.5-33929.29" + switch \initial + attribute \src "libresoc.v:33929.9-33929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 + assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 + end + attribute \src "libresoc.v:33950.3-33959.6" + process $proc$libresoc.v:33950$1281 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:33951.5-33951.29" + switch \initial + attribute \src "libresoc.v:33951.9-33951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1283 \src1_i + case + assign $1\src_r0$next[63:0]$1283 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1282 + end + attribute \src "libresoc.v:33960.3-33969.6" + process $proc$libresoc.v:33960$1284 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:33961.5-33961.29" + switch \initial + attribute \src "libresoc.v:33961.9-33961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1286 \src_or_imm + case + assign $1\src_r1$next[63:0]$1286 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1285 + end + attribute \src "libresoc.v:33970.3-33979.6" + process $proc$libresoc.v:33970$1287 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:33971.5-33971.29" + switch \initial + attribute \src "libresoc.v:33971.9-33971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1289 \src3_i + case + assign $1\src_r2$next[3:0]$1289 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1288 + end + attribute \src "libresoc.v:33980.3-33988.6" + process $proc$libresoc.v:33980$1290 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:33981.5-33981.29" + switch \initial + attribute \src "libresoc.v:33981.9-33981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1292 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1292 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 + end + attribute \src "libresoc.v:33989.3-33997.6" + process $proc$libresoc.v:33989$1293 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:33990.5-33990.29" + switch \initial + attribute \src "libresoc.v:33990.9-33990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1295 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1295 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 + end + attribute \src "libresoc.v:33998.3-34007.6" + process $proc$libresoc.v:33998$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:33599.5-33599.29" + attribute \src "libresoc.v:33999.5-33999.29" switch \initial - attribute \src "libresoc.v:33599.9-33599.17" + attribute \src "libresoc.v:33999.9-33999.17" case 1'1 case end @@ -51821,14 +52153,14 @@ module \branch0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:33608.3-33617.6" - process $proc$libresoc.v:33608$1305 + attribute \src "libresoc.v:34008.3-34017.6" + process $proc$libresoc.v:34008$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:33609.5-33609.29" + attribute \src "libresoc.v:34009.5-34009.29" switch \initial - attribute \src "libresoc.v:33609.9-33609.17" + attribute \src "libresoc.v:34009.9-34009.17" case 1'1 case end @@ -51844,14 +52176,14 @@ module \branch0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:33618.3-33627.6" - process $proc$libresoc.v:33618$1306 + attribute \src "libresoc.v:34018.3-34027.6" + process $proc$libresoc.v:34018$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:33619.5-33619.29" + attribute \src "libresoc.v:34019.5-34019.29" switch \initial - attribute \src "libresoc.v:33619.9-33619.17" + attribute \src "libresoc.v:34019.9-34019.17" case 1'1 case end @@ -51867,14 +52199,14 @@ module \branch0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:33628.3-33636.6" - process $proc$libresoc.v:33628$1307 + attribute \src "libresoc.v:34028.3-34036.6" + process $proc$libresoc.v:34028$1299 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$1308 $1\prev_wr_go$next[2:0]$1309 - attribute \src "libresoc.v:33629.5-33629.29" + assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:34029.5-34029.29" switch \initial - attribute \src "libresoc.v:33629.9-33629.17" + attribute \src "libresoc.v:34029.9-34029.17" case 1'1 case end @@ -51883,70 +52215,70 @@ module \branch0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$1309 3'000 - case - assign $1\prev_wr_go$next[2:0]$1309 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1308 - end - connect \$5 $reduce_and$libresoc.v:33165$1126_Y - connect \$99 $and$libresoc.v:33166$1127_Y - connect \$101 $and$libresoc.v:33167$1128_Y - connect \$103 $and$libresoc.v:33168$1129_Y - connect \$105 $and$libresoc.v:33169$1130_Y - connect \$107 $and$libresoc.v:33170$1131_Y - connect \$109 $and$libresoc.v:33171$1132_Y - connect \$111 $and$libresoc.v:33172$1133_Y - connect \$113 $and$libresoc.v:33173$1134_Y - connect \$115 $and$libresoc.v:33174$1135_Y - connect \$11 $and$libresoc.v:33175$1136_Y - connect \$13 $not$libresoc.v:33176$1137_Y - connect \$15 $and$libresoc.v:33177$1138_Y - connect \$17 $not$libresoc.v:33178$1139_Y - connect \$19 $and$libresoc.v:33179$1140_Y - connect \$21 $and$libresoc.v:33180$1141_Y - connect \$25 $not$libresoc.v:33181$1142_Y - connect \$27 $and$libresoc.v:33182$1143_Y - connect \$24 $reduce_or$libresoc.v:33183$1144_Y - connect \$23 $not$libresoc.v:33184$1145_Y - connect \$31 $and$libresoc.v:33185$1146_Y - connect \$33 $reduce_or$libresoc.v:33186$1147_Y - connect \$35 $reduce_or$libresoc.v:33187$1148_Y - connect \$37 $or$libresoc.v:33188$1149_Y - connect \$3 $and$libresoc.v:33189$1150_Y - connect \$39 $not$libresoc.v:33190$1151_Y - connect \$41 $and$libresoc.v:33191$1152_Y - connect \$43 $and$libresoc.v:33192$1153_Y - connect \$45 $eq$libresoc.v:33193$1154_Y - connect \$47 $and$libresoc.v:33194$1155_Y - connect \$49 $eq$libresoc.v:33195$1156_Y - connect \$51 $and$libresoc.v:33196$1157_Y - connect \$53 $and$libresoc.v:33197$1158_Y - connect \$55 $and$libresoc.v:33198$1159_Y - connect \$57 $or$libresoc.v:33199$1160_Y - connect \$59 $or$libresoc.v:33200$1161_Y - connect \$61 $or$libresoc.v:33201$1162_Y - connect \$63 $or$libresoc.v:33202$1163_Y - connect \$65 $and$libresoc.v:33203$1164_Y - connect \$67 $and$libresoc.v:33204$1165_Y - connect \$6 $not$libresoc.v:33205$1166_Y - connect \$69 $or$libresoc.v:33206$1167_Y - connect \$71 $and$libresoc.v:33207$1168_Y - connect \$73 $and$libresoc.v:33208$1169_Y - connect \$75 $and$libresoc.v:33209$1170_Y - connect \$77 $ternary$libresoc.v:33210$1171_Y - connect \$79 $ternary$libresoc.v:33211$1172_Y - connect \$81 $ternary$libresoc.v:33212$1173_Y - connect \$83 $ternary$libresoc.v:33213$1174_Y - connect \$85 $ternary$libresoc.v:33214$1175_Y - connect \$87 $and$libresoc.v:33215$1176_Y - connect \$8 $or$libresoc.v:33216$1177_Y - connect \$89 $and$libresoc.v:33217$1178_Y - connect \$91 $and$libresoc.v:33218$1179_Y - connect \$93 $not$libresoc.v:33219$1180_Y - connect \$95 $and$libresoc.v:33220$1181_Y - connect \$97 $not$libresoc.v:33221$1182_Y + assign $1\prev_wr_go$next[2:0]$1301 3'000 + case + assign $1\prev_wr_go$next[2:0]$1301 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 + end + connect \$5 $reduce_and$libresoc.v:33565$1118_Y + connect \$99 $and$libresoc.v:33566$1119_Y + connect \$101 $and$libresoc.v:33567$1120_Y + connect \$103 $and$libresoc.v:33568$1121_Y + connect \$105 $and$libresoc.v:33569$1122_Y + connect \$107 $and$libresoc.v:33570$1123_Y + connect \$109 $and$libresoc.v:33571$1124_Y + connect \$111 $and$libresoc.v:33572$1125_Y + connect \$113 $and$libresoc.v:33573$1126_Y + connect \$115 $and$libresoc.v:33574$1127_Y + connect \$11 $and$libresoc.v:33575$1128_Y + connect \$13 $not$libresoc.v:33576$1129_Y + connect \$15 $and$libresoc.v:33577$1130_Y + connect \$17 $not$libresoc.v:33578$1131_Y + connect \$19 $and$libresoc.v:33579$1132_Y + connect \$21 $and$libresoc.v:33580$1133_Y + connect \$25 $not$libresoc.v:33581$1134_Y + connect \$27 $and$libresoc.v:33582$1135_Y + connect \$24 $reduce_or$libresoc.v:33583$1136_Y + connect \$23 $not$libresoc.v:33584$1137_Y + connect \$31 $and$libresoc.v:33585$1138_Y + connect \$33 $reduce_or$libresoc.v:33586$1139_Y + connect \$35 $reduce_or$libresoc.v:33587$1140_Y + connect \$37 $or$libresoc.v:33588$1141_Y + connect \$3 $and$libresoc.v:33589$1142_Y + connect \$39 $not$libresoc.v:33590$1143_Y + connect \$41 $and$libresoc.v:33591$1144_Y + connect \$43 $and$libresoc.v:33592$1145_Y + connect \$45 $eq$libresoc.v:33593$1146_Y + connect \$47 $and$libresoc.v:33594$1147_Y + connect \$49 $eq$libresoc.v:33595$1148_Y + connect \$51 $and$libresoc.v:33596$1149_Y + connect \$53 $and$libresoc.v:33597$1150_Y + connect \$55 $and$libresoc.v:33598$1151_Y + connect \$57 $or$libresoc.v:33599$1152_Y + connect \$59 $or$libresoc.v:33600$1153_Y + connect \$61 $or$libresoc.v:33601$1154_Y + connect \$63 $or$libresoc.v:33602$1155_Y + connect \$65 $and$libresoc.v:33603$1156_Y + connect \$67 $and$libresoc.v:33604$1157_Y + connect \$6 $not$libresoc.v:33605$1158_Y + connect \$69 $or$libresoc.v:33606$1159_Y + connect \$71 $and$libresoc.v:33607$1160_Y + connect \$73 $and$libresoc.v:33608$1161_Y + connect \$75 $and$libresoc.v:33609$1162_Y + connect \$77 $ternary$libresoc.v:33610$1163_Y + connect \$79 $ternary$libresoc.v:33611$1164_Y + connect \$81 $ternary$libresoc.v:33612$1165_Y + connect \$83 $ternary$libresoc.v:33613$1166_Y + connect \$85 $ternary$libresoc.v:33614$1167_Y + connect \$87 $and$libresoc.v:33615$1168_Y + connect \$8 $or$libresoc.v:33616$1169_Y + connect \$89 $and$libresoc.v:33617$1170_Y + connect \$91 $and$libresoc.v:33618$1171_Y + connect \$93 $not$libresoc.v:33619$1172_Y + connect \$95 $and$libresoc.v:33620$1173_Y + connect \$97 $not$libresoc.v:33621$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -51978,37 +52310,37 @@ module \branch0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:33671.1-33729.10" +attribute \src "libresoc.v:34071.1-34129.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l - attribute \src "libresoc.v:33672.7-33672.20" + attribute \src "libresoc.v:34072.7-34072.20" wire $0\initial[0:0] - attribute \src "libresoc.v:33717.3-33725.6" - wire $0\q_int$next[0:0]$1353 - attribute \src "libresoc.v:33715.3-33716.27" + attribute \src "libresoc.v:34117.3-34125.6" + wire $0\q_int$next[0:0]$1345 + attribute \src "libresoc.v:34115.3-34116.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:33717.3-33725.6" - wire $1\q_int$next[0:0]$1354 - attribute \src "libresoc.v:33696.7-33696.19" + attribute \src "libresoc.v:34117.3-34125.6" + wire $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34096.7-34096.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:33707.17-33707.96" - wire $and$libresoc.v:33707$1343_Y - attribute \src "libresoc.v:33712.17-33712.96" - wire $and$libresoc.v:33712$1348_Y - attribute \src "libresoc.v:33709.18-33709.94" - wire $not$libresoc.v:33709$1345_Y - attribute \src "libresoc.v:33711.17-33711.93" - wire $not$libresoc.v:33711$1347_Y - attribute \src "libresoc.v:33714.17-33714.93" - wire $not$libresoc.v:33714$1350_Y - attribute \src "libresoc.v:33708.18-33708.99" - wire $or$libresoc.v:33708$1344_Y - attribute \src "libresoc.v:33710.18-33710.100" - wire $or$libresoc.v:33710$1346_Y - attribute \src "libresoc.v:33713.17-33713.98" - wire $or$libresoc.v:33713$1349_Y + attribute \src "libresoc.v:34107.17-34107.96" + wire $and$libresoc.v:34107$1335_Y + attribute \src "libresoc.v:34112.17-34112.96" + wire $and$libresoc.v:34112$1340_Y + attribute \src "libresoc.v:34109.18-34109.94" + wire $not$libresoc.v:34109$1337_Y + attribute \src "libresoc.v:34111.17-34111.93" + wire $not$libresoc.v:34111$1339_Y + attribute \src "libresoc.v:34114.17-34114.93" + wire $not$libresoc.v:34114$1342_Y + attribute \src "libresoc.v:34108.18-34108.99" + wire $or$libresoc.v:34108$1336_Y + attribute \src "libresoc.v:34110.18-34110.100" + wire $or$libresoc.v:34110$1338_Y + attribute \src "libresoc.v:34113.17-34113.98" + wire $or$libresoc.v:34113$1341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -52025,11 +52357,11 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:33672.7-33672.15" + attribute \src "libresoc.v:34072.7-34072.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 4 \q_busy @@ -52046,7 +52378,7 @@ module \busy_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:33707$1343 + cell $and $and$libresoc.v:34107$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52054,10 +52386,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:33707$1343_Y + connect \Y $and$libresoc.v:34107$1335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:33712$1348 + cell $and $and$libresoc.v:34112$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52065,34 +52397,34 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:33712$1348_Y + connect \Y $and$libresoc.v:34112$1340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:33709$1345 + cell $not $not$libresoc.v:34109$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy - connect \Y $not$libresoc.v:33709$1345_Y + connect \Y $not$libresoc.v:34109$1337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:33711$1347 + cell $not $not$libresoc.v:34111$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:33711$1347_Y + connect \Y $not$libresoc.v:34111$1339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:33714$1350 + cell $not $not$libresoc.v:34114$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:33714$1350_Y + connect \Y $not$libresoc.v:34114$1342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:33708$1344 + cell $or $or$libresoc.v:34108$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52100,10 +52432,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy - connect \Y $or$libresoc.v:33708$1344_Y + connect \Y $or$libresoc.v:34108$1336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:33710$1346 + cell $or $or$libresoc.v:34110$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52111,10 +52443,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int - connect \Y $or$libresoc.v:33710$1346_Y + connect \Y $or$libresoc.v:34110$1338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:33713$1349 + cell $or $or$libresoc.v:34113$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52122,39 +52454,39 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy - connect \Y $or$libresoc.v:33713$1349_Y + connect \Y $or$libresoc.v:34113$1341_Y end - attribute \src "libresoc.v:33672.7-33672.20" - process $proc$libresoc.v:33672$1355 + attribute \src "libresoc.v:34072.7-34072.20" + process $proc$libresoc.v:34072$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:33696.7-33696.19" - process $proc$libresoc.v:33696$1356 + attribute \src "libresoc.v:34096.7-34096.19" + process $proc$libresoc.v:34096$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:33715.3-33716.27" - process $proc$libresoc.v:33715$1351 + attribute \src "libresoc.v:34115.3-34116.27" + process $proc$libresoc.v:34115$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:33717.3-33725.6" - process $proc$libresoc.v:33717$1352 + attribute \src "libresoc.v:34117.3-34125.6" + process $proc$libresoc.v:34117$1344 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$1353 $1\q_int$next[0:0]$1354 - attribute \src "libresoc.v:33718.5-33718.29" + assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34118.5-34118.29" switch \initial - attribute \src "libresoc.v:33718.9-33718.17" + attribute \src "libresoc.v:34118.9-34118.17" case 1'1 case end @@ -52163,532 +52495,1059 @@ module \busy_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$1354 1'0 + assign $1\q_int$next[0:0]$1346 1'0 case - assign $1\q_int$next[0:0]$1354 \$5 + assign $1\q_int$next[0:0]$1346 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$1353 + update \q_int$next $0\q_int$next[0:0]$1345 end - connect \$9 $and$libresoc.v:33707$1343_Y - connect \$11 $or$libresoc.v:33708$1344_Y - connect \$13 $not$libresoc.v:33709$1345_Y - connect \$15 $or$libresoc.v:33710$1346_Y - connect \$1 $not$libresoc.v:33711$1347_Y - connect \$3 $and$libresoc.v:33712$1348_Y - connect \$5 $or$libresoc.v:33713$1349_Y - connect \$7 $not$libresoc.v:33714$1350_Y + connect \$9 $and$libresoc.v:34107$1335_Y + connect \$11 $or$libresoc.v:34108$1336_Y + connect \$13 $not$libresoc.v:34109$1337_Y + connect \$15 $or$libresoc.v:34110$1338_Y + connect \$1 $not$libresoc.v:34111$1339_Y + connect \$3 $and$libresoc.v:34112$1340_Y + connect \$5 $or$libresoc.v:34113$1341_Y + connect \$7 $not$libresoc.v:34114$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end -attribute \src "libresoc.v:33733.1-35341.10" +attribute \src "libresoc.v:34133.1-34316.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \nmigen.hierarchy "test_issuer.clksel" +attribute \generator "nMigen" +module \clksel + attribute \src "libresoc.v:34267.3-34286.6" + wire $0\clk1$next[0:0]$1378 + attribute \src "libresoc.v:34201.3-34202.25" + wire $0\clk1[0:0] + attribute \src "libresoc.v:34220.3-34234.6" + wire $0\clk2$next[0:0]$1366 + attribute \src "libresoc.v:34207.3-34208.25" + wire $0\clk2[0:0] + attribute \src "libresoc.v:34252.3-34266.6" + wire $0\clk3$next[0:0]$1374 + attribute \src "libresoc.v:34203.3-34204.25" + wire $0\clk3[0:0] + attribute \src "libresoc.v:34211.3-34219.6" + wire $0\clk4$next[0:0]$1363 + attribute \src "libresoc.v:34209.3-34210.25" + wire $0\clk4[0:0] + attribute \src "libresoc.v:34287.3-34309.6" + wire $0\core_clk_o[0:0] + attribute \src "libresoc.v:34235.3-34251.6" + wire width 2 $0\counter3$next[1:0]$1370 + attribute \src "libresoc.v:34205.3-34206.33" + wire width 2 $0\counter3[1:0] + attribute \src "libresoc.v:34134.7-34134.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34267.3-34286.6" + wire $1\clk1$next[0:0]$1379 + attribute \src "libresoc.v:34156.7-34156.18" + wire $1\clk1[0:0] + attribute \src "libresoc.v:34220.3-34234.6" + wire $1\clk2$next[0:0]$1367 + attribute \src "libresoc.v:34160.7-34160.18" + wire $1\clk2[0:0] + attribute \src "libresoc.v:34252.3-34266.6" + wire $1\clk3$next[0:0]$1375 + attribute \src "libresoc.v:34164.7-34164.18" + wire $1\clk3[0:0] + attribute \src "libresoc.v:34211.3-34219.6" + wire $1\clk4$next[0:0]$1364 + attribute \src "libresoc.v:34168.7-34168.18" + wire $1\clk4[0:0] + attribute \src "libresoc.v:34287.3-34309.6" + wire $1\core_clk_o[0:0] + attribute \src "libresoc.v:34235.3-34251.6" + wire width 2 $1\counter3$next[1:0]$1371 + attribute \src "libresoc.v:34184.13-34184.28" + wire width 2 $1\counter3[1:0] + attribute \src "libresoc.v:34267.3-34286.6" + wire $2\clk1$next[0:0]$1380 + attribute \src "libresoc.v:34220.3-34234.6" + wire $2\clk2$next[0:0]$1368 + attribute \src "libresoc.v:34252.3-34266.6" + wire $2\clk3$next[0:0]$1376 + attribute \src "libresoc.v:34235.3-34251.6" + wire width 2 $2\counter3$next[1:0]$1372 + attribute \src "libresoc.v:34267.3-34286.6" + wire $3\clk1$next[0:0]$1381 + attribute \src "libresoc.v:34200.17-34200.101" + wire width 3 $add$libresoc.v:34200$1356_Y + attribute \src "libresoc.v:34193.18-34193.103" + wire $eq$libresoc.v:34193$1349_Y + attribute \src "libresoc.v:34195.18-34195.103" + wire $eq$libresoc.v:34195$1351_Y + attribute \src "libresoc.v:34199.17-34199.102" + wire $eq$libresoc.v:34199$1355_Y + attribute \src "libresoc.v:34194.18-34194.93" + wire $not$libresoc.v:34194$1350_Y + attribute \src "libresoc.v:34196.18-34196.93" + wire $not$libresoc.v:34196$1352_Y + attribute \src "libresoc.v:34197.17-34197.92" + wire $not$libresoc.v:34197$1353_Y + attribute \src "libresoc.v:34198.17-34198.92" + wire $not$libresoc.v:34198$1354_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" + wire width 3 \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" + wire \clk7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" + wire width 3 input 3 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" + wire \core_clk_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:45" + wire width 2 \counter3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:45" + wire width 2 \counter3$next + attribute \src "libresoc.v:34134.7-34134.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" + wire output 4 \pll_48_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire input 5 \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire input 2 \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" + cell $add $add$libresoc.v:34200$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \counter3 + connect \B 1'1 + connect \Y $add$libresoc.v:34200$1356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + cell $eq $eq$libresoc.v:34193$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:34193$1349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + cell $eq $eq$libresoc.v:34195$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:34195$1351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + cell $eq $eq$libresoc.v:34199$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \counter3 + connect \B 2'10 + connect \Y $eq$libresoc.v:34199$1355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" + cell $not $not$libresoc.v:34194$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk3 + connect \Y $not$libresoc.v:34194$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" + cell $not $not$libresoc.v:34196$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk1 + connect \Y $not$libresoc.v:34196$1352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:53" + cell $not $not$libresoc.v:34197$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk4 + connect \Y $not$libresoc.v:34197$1353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" + cell $not $not$libresoc.v:34198$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk2 + connect \Y $not$libresoc.v:34198$1354_Y + end + attribute \src "libresoc.v:34134.7-34134.20" + process $proc$libresoc.v:34134$1383 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34156.7-34156.18" + process $proc$libresoc.v:34156$1384 + assign { } { } + assign $1\clk1[0:0] 1'0 + sync always + sync init + update \clk1 $1\clk1[0:0] + end + attribute \src "libresoc.v:34160.7-34160.18" + process $proc$libresoc.v:34160$1385 + assign { } { } + assign $1\clk2[0:0] 1'0 + sync always + sync init + update \clk2 $1\clk2[0:0] + end + attribute \src "libresoc.v:34164.7-34164.18" + process $proc$libresoc.v:34164$1386 + assign { } { } + assign $1\clk3[0:0] 1'0 + sync always + sync init + update \clk3 $1\clk3[0:0] + end + attribute \src "libresoc.v:34168.7-34168.18" + process $proc$libresoc.v:34168$1387 + assign { } { } + assign $1\clk4[0:0] 1'0 + sync always + sync init + update \clk4 $1\clk4[0:0] + end + attribute \src "libresoc.v:34184.13-34184.28" + process $proc$libresoc.v:34184$1388 + assign { } { } + assign $1\counter3[1:0] 2'00 + sync always + sync init + update \counter3 $1\counter3[1:0] + end + attribute \src "libresoc.v:34201.3-34202.25" + process $proc$libresoc.v:34201$1357 + assign { } { } + assign $0\clk1[0:0] \clk1$next + sync posedge \pllclk_clk + update \clk1 $0\clk1[0:0] + end + attribute \src "libresoc.v:34203.3-34204.25" + process $proc$libresoc.v:34203$1358 + assign { } { } + assign $0\clk3[0:0] \clk3$next + sync posedge \pllclk_clk + update \clk3 $0\clk3[0:0] + end + attribute \src "libresoc.v:34205.3-34206.33" + process $proc$libresoc.v:34205$1359 + assign { } { } + assign $0\counter3[1:0] \counter3$next + sync posedge \pllclk_clk + update \counter3 $0\counter3[1:0] + end + attribute \src "libresoc.v:34207.3-34208.25" + process $proc$libresoc.v:34207$1360 + assign { } { } + assign $0\clk2[0:0] \clk2$next + sync posedge \pllclk_clk + update \clk2 $0\clk2[0:0] + end + attribute \src "libresoc.v:34209.3-34210.25" + process $proc$libresoc.v:34209$1361 + assign { } { } + assign $0\clk4[0:0] \clk4$next + sync posedge \pllclk_clk + update \clk4 $0\clk4[0:0] + end + attribute \src "libresoc.v:34211.3-34219.6" + process $proc$libresoc.v:34211$1362 + assign { } { } + assign { } { } + assign $0\clk4$next[0:0]$1363 $1\clk4$next[0:0]$1364 + attribute \src "libresoc.v:34212.5-34212.29" + switch \initial + attribute \src "libresoc.v:34212.9-34212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk4$next[0:0]$1364 1'0 + case + assign $1\clk4$next[0:0]$1364 \$1 + end + sync always + update \clk4$next $0\clk4$next[0:0]$1363 + end + attribute \src "libresoc.v:34220.3-34234.6" + process $proc$libresoc.v:34220$1365 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk2$next[0:0]$1366 $2\clk2$next[0:0]$1368 + attribute \src "libresoc.v:34221.5-34221.29" + switch \initial + attribute \src "libresoc.v:34221.9-34221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:54" + switch \clk4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk2$next[0:0]$1367 \$3 + case + assign $1\clk2$next[0:0]$1367 \clk2 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk2$next[0:0]$1368 1'0 + case + assign $2\clk2$next[0:0]$1368 $1\clk2$next[0:0]$1367 + end + sync always + update \clk2$next $0\clk2$next[0:0]$1366 + end + attribute \src "libresoc.v:34235.3-34251.6" + process $proc$libresoc.v:34235$1369 + assign { } { } + assign { } { } + assign $0\counter3$next[1:0]$1370 $2\counter3$next[1:0]$1372 + attribute \src "libresoc.v:34236.5-34236.29" + switch \initial + attribute \src "libresoc.v:34236.9-34236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter3$next[1:0]$1371 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\counter3$next[1:0]$1371 \$7 [1:0] + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter3$next[1:0]$1372 2'00 + case + assign $2\counter3$next[1:0]$1372 $1\counter3$next[1:0]$1371 + end + sync always + update \counter3$next $0\counter3$next[1:0]$1370 + end + attribute \src "libresoc.v:34252.3-34266.6" + process $proc$libresoc.v:34252$1373 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk3$next[0:0]$1374 $2\clk3$next[0:0]$1376 + attribute \src "libresoc.v:34253.5-34253.29" + switch \initial + attribute \src "libresoc.v:34253.9-34253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + switch \$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk3$next[0:0]$1375 \$12 + case + assign $1\clk3$next[0:0]$1375 \clk3 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk3$next[0:0]$1376 1'0 + case + assign $2\clk3$next[0:0]$1376 $1\clk3$next[0:0]$1375 + end + sync always + update \clk3$next $0\clk3$next[0:0]$1374 + end + attribute \src "libresoc.v:34267.3-34286.6" + process $proc$libresoc.v:34267$1377 + assign { } { } + assign { } { } + assign { } { } + assign $0\clk1$next[0:0]$1378 $3\clk1$next[0:0]$1381 + attribute \src "libresoc.v:34268.5-34268.29" + switch \initial + attribute \src "libresoc.v:34268.9-34268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\clk1$next[0:0]$1379 $2\clk1$next[0:0]$1380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:59" + switch \clk3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\clk1$next[0:0]$1380 \$16 + case + assign $2\clk1$next[0:0]$1380 \clk1 + end + case + assign $1\clk1$next[0:0]$1379 \clk1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \pllclk_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\clk1$next[0:0]$1381 1'0 + case + assign $3\clk1$next[0:0]$1381 $1\clk1$next[0:0]$1379 + end + sync always + update \clk1$next $0\clk1$next[0:0]$1378 + end + attribute \src "libresoc.v:34287.3-34309.6" + process $proc$libresoc.v:34287$1382 + assign { } { } + assign { } { } + assign $0\core_clk_o[0:0] $1\core_clk_o[0:0] + attribute \src "libresoc.v:34288.5-34288.29" + switch \initial + attribute \src "libresoc.v:34288.9-34288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:65" + switch \clk_sel_i + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\core_clk_o[0:0] \clk0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\core_clk_o[0:0] \clk1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\core_clk_o[0:0] \clk2 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\core_clk_o[0:0] \clk3 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_clk_o[0:0] \clk4 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\core_clk_o[0:0] \clk5 + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\core_clk_o[0:0] \clk6 + attribute \src "libresoc.v:0.0-0.0" + case 3'--- + assign { } { } + assign $1\core_clk_o[0:0] \clk7 + case + assign $1\core_clk_o[0:0] 1'0 + end + sync always + update \core_clk_o $0\core_clk_o[0:0] + end + connect \$10 $eq$libresoc.v:34193$1349_Y + connect \$12 $not$libresoc.v:34194$1350_Y + connect \$14 $eq$libresoc.v:34195$1351_Y + connect \$16 $not$libresoc.v:34196$1352_Y + connect \$1 $not$libresoc.v:34197$1353_Y + connect \$3 $not$libresoc.v:34198$1354_Y + connect \$5 $eq$libresoc.v:34199$1355_Y + connect \$8 $add$libresoc.v:34200$1356_Y + connect \$7 \$8 + connect \clk5 1'0 + connect \pll_48_o \clk1 + connect \clk7 1'1 + connect \clk6 1'0 + connect \clk0 \clk_24_i +end +attribute \src "libresoc.v:34320.1-35928.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz - attribute \src "libresoc.v:34208.3-34222.6" + attribute \src "libresoc.v:34795.3-34809.6" wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:34298.3-34312.6" + attribute \src "libresoc.v:34885.3-34899.6" wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:34313.3-34327.6" + attribute \src "libresoc.v:34900.3-34914.6" wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:34328.3-34342.6" + attribute \src "libresoc.v:34915.3-34929.6" wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:34343.3-34357.6" + attribute \src "libresoc.v:34930.3-34944.6" wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:34358.3-34372.6" + attribute \src "libresoc.v:34945.3-34959.6" wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:34388.3-34402.6" + attribute \src "libresoc.v:34975.3-34989.6" wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:34403.3-34417.6" + attribute \src "libresoc.v:34990.3-35004.6" wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:34418.3-34432.6" + attribute \src "libresoc.v:35005.3-35019.6" wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:34433.3-34447.6" + attribute \src "libresoc.v:35020.3-35034.6" wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:34448.3-34462.6" + attribute \src "libresoc.v:35035.3-35049.6" wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:34373.3-34387.6" + attribute \src "libresoc.v:34960.3-34974.6" wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:34463.3-34477.6" + attribute \src "libresoc.v:35050.3-35064.6" wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:34478.3-34492.6" + attribute \src "libresoc.v:35065.3-35079.6" wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:34493.3-34507.6" + attribute \src "libresoc.v:35080.3-35094.6" wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:34508.3-34522.6" + attribute \src "libresoc.v:35095.3-35109.6" wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:34523.3-34537.6" + attribute \src "libresoc.v:35110.3-35124.6" wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:34553.3-34567.6" + attribute \src "libresoc.v:35140.3-35154.6" wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:34568.3-34582.6" + attribute \src "libresoc.v:35155.3-35169.6" wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:34583.3-34597.6" + attribute \src "libresoc.v:35170.3-35184.6" wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:34598.3-34612.6" + attribute \src "libresoc.v:35185.3-35199.6" wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:34613.3-34627.6" + attribute \src "libresoc.v:35200.3-35214.6" wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:34538.3-34552.6" + attribute \src "libresoc.v:35125.3-35139.6" wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:34628.3-34642.6" + attribute \src "libresoc.v:35215.3-35229.6" wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:34643.3-34657.6" + attribute \src "libresoc.v:35230.3-35244.6" wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:34778.3-34792.6" + attribute \src "libresoc.v:35365.3-35379.6" wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:35193.3-35207.6" + attribute \src "libresoc.v:35780.3-35794.6" wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:34223.3-34237.6" + attribute \src "libresoc.v:34810.3-34824.6" wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:34238.3-34252.6" + attribute \src "libresoc.v:34825.3-34839.6" wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:34253.3-34267.6" + attribute \src "libresoc.v:34840.3-34854.6" wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:34268.3-34282.6" + attribute \src "libresoc.v:34855.3-34869.6" wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:34283.3-34297.6" + attribute \src "libresoc.v:34870.3-34884.6" wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:34658.3-34677.6" + attribute \src "libresoc.v:35245.3-35264.6" wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:34758.3-34777.6" + attribute \src "libresoc.v:35345.3-35364.6" wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:34793.3-34812.6" + attribute \src "libresoc.v:35380.3-35399.6" wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:34813.3-34832.6" + attribute \src "libresoc.v:35400.3-35419.6" wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:34833.3-34852.6" + attribute \src "libresoc.v:35420.3-35439.6" wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:34853.3-34872.6" + attribute \src "libresoc.v:35440.3-35459.6" wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:34873.3-34892.6" + attribute \src "libresoc.v:35460.3-35479.6" wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:34893.3-34912.6" + attribute \src "libresoc.v:35480.3-35499.6" wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:34913.3-34932.6" + attribute \src "libresoc.v:35500.3-35519.6" wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:34933.3-34952.6" + attribute \src "libresoc.v:35520.3-35539.6" wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:34953.3-34972.6" + attribute \src "libresoc.v:35540.3-35559.6" wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:34678.3-34697.6" + attribute \src "libresoc.v:35265.3-35284.6" wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:34973.3-34992.6" + attribute \src "libresoc.v:35560.3-35579.6" wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:34698.3-34717.6" + attribute \src "libresoc.v:35285.3-35304.6" wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:34718.3-34737.6" + attribute \src "libresoc.v:35305.3-35324.6" wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:34738.3-34757.6" + attribute \src "libresoc.v:35325.3-35344.6" wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:34993.3-35012.6" + attribute \src "libresoc.v:35580.3-35599.6" wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35093.3-35112.6" + attribute \src "libresoc.v:35680.3-35699.6" wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35113.3-35132.6" + attribute \src "libresoc.v:35700.3-35719.6" wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:35133.3-35152.6" + attribute \src "libresoc.v:35720.3-35739.6" wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35013.3-35032.6" + attribute \src "libresoc.v:35600.3-35619.6" wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35033.3-35052.6" + attribute \src "libresoc.v:35620.3-35639.6" wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35053.3-35072.6" + attribute \src "libresoc.v:35640.3-35659.6" wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35073.3-35092.6" + attribute \src "libresoc.v:35660.3-35679.6" wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:35153.3-35172.6" + attribute \src "libresoc.v:35740.3-35759.6" wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:35173.3-35192.6" + attribute \src "libresoc.v:35760.3-35779.6" wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:35208.3-35227.6" + attribute \src "libresoc.v:35795.3-35814.6" wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:35228.3-35247.6" + attribute \src "libresoc.v:35815.3-35834.6" wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:35248.3-35267.6" + attribute \src "libresoc.v:35835.3-35854.6" wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:35268.3-35287.6" + attribute \src "libresoc.v:35855.3-35874.6" wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:35288.3-35307.6" + attribute \src "libresoc.v:35875.3-35894.6" wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:33734.7-33734.20" + attribute \src "libresoc.v:34321.7-34321.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34208.3-34222.6" + attribute \src "libresoc.v:34795.3-34809.6" wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34298.3-34312.6" + attribute \src "libresoc.v:34885.3-34899.6" wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34313.3-34327.6" + attribute \src "libresoc.v:34900.3-34914.6" wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34328.3-34342.6" + attribute \src "libresoc.v:34915.3-34929.6" wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34343.3-34357.6" + attribute \src "libresoc.v:34930.3-34944.6" wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34358.3-34372.6" + attribute \src "libresoc.v:34945.3-34959.6" wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34388.3-34402.6" + attribute \src "libresoc.v:34975.3-34989.6" wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34403.3-34417.6" + attribute \src "libresoc.v:34990.3-35004.6" wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:34418.3-34432.6" + attribute \src "libresoc.v:35005.3-35019.6" wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:34433.3-34447.6" + attribute \src "libresoc.v:35020.3-35034.6" wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:34448.3-34462.6" + attribute \src "libresoc.v:35035.3-35049.6" wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:34373.3-34387.6" + attribute \src "libresoc.v:34960.3-34974.6" wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:34463.3-34477.6" + attribute \src "libresoc.v:35050.3-35064.6" wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:34478.3-34492.6" + attribute \src "libresoc.v:35065.3-35079.6" wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:34493.3-34507.6" + attribute \src "libresoc.v:35080.3-35094.6" wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:34508.3-34522.6" + attribute \src "libresoc.v:35095.3-35109.6" wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:34523.3-34537.6" + attribute \src "libresoc.v:35110.3-35124.6" wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:34553.3-34567.6" + attribute \src "libresoc.v:35140.3-35154.6" wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:34568.3-34582.6" + attribute \src "libresoc.v:35155.3-35169.6" wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:34583.3-34597.6" + attribute \src "libresoc.v:35170.3-35184.6" wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:34598.3-34612.6" + attribute \src "libresoc.v:35185.3-35199.6" wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:34613.3-34627.6" + attribute \src "libresoc.v:35200.3-35214.6" wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:34538.3-34552.6" + attribute \src "libresoc.v:35125.3-35139.6" wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:34628.3-34642.6" + attribute \src "libresoc.v:35215.3-35229.6" wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:34643.3-34657.6" + attribute \src "libresoc.v:35230.3-35244.6" wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:34778.3-34792.6" + attribute \src "libresoc.v:35365.3-35379.6" wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35193.3-35207.6" + attribute \src "libresoc.v:35780.3-35794.6" wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:34223.3-34237.6" + attribute \src "libresoc.v:34810.3-34824.6" wire width 2 $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34238.3-34252.6" + attribute \src "libresoc.v:34825.3-34839.6" wire width 2 $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34253.3-34267.6" + attribute \src "libresoc.v:34840.3-34854.6" wire width 2 $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34268.3-34282.6" + attribute \src "libresoc.v:34855.3-34869.6" wire width 2 $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34283.3-34297.6" + attribute \src "libresoc.v:34870.3-34884.6" wire width 2 $1\cnt_1_9[1:0] - attribute \src "libresoc.v:34658.3-34677.6" + attribute \src "libresoc.v:35245.3-35264.6" wire width 3 $1\cnt_2_0[2:0] - attribute \src "libresoc.v:34758.3-34777.6" + attribute \src "libresoc.v:35345.3-35364.6" wire width 3 $1\cnt_2_10[2:0] - attribute \src "libresoc.v:34793.3-34812.6" + attribute \src "libresoc.v:35380.3-35399.6" wire width 3 $1\cnt_2_12[2:0] - attribute \src "libresoc.v:34813.3-34832.6" + attribute \src "libresoc.v:35400.3-35419.6" wire width 3 $1\cnt_2_14[2:0] - attribute \src "libresoc.v:34833.3-34852.6" + attribute \src "libresoc.v:35420.3-35439.6" wire width 3 $1\cnt_2_16[2:0] - attribute \src "libresoc.v:34853.3-34872.6" + attribute \src "libresoc.v:35440.3-35459.6" wire width 3 $1\cnt_2_18[2:0] - attribute \src "libresoc.v:34873.3-34892.6" + attribute \src "libresoc.v:35460.3-35479.6" wire width 3 $1\cnt_2_20[2:0] - attribute \src "libresoc.v:34893.3-34912.6" + attribute \src "libresoc.v:35480.3-35499.6" wire width 3 $1\cnt_2_22[2:0] - attribute \src "libresoc.v:34913.3-34932.6" + attribute \src "libresoc.v:35500.3-35519.6" wire width 3 $1\cnt_2_24[2:0] - attribute \src "libresoc.v:34933.3-34952.6" + attribute \src "libresoc.v:35520.3-35539.6" wire width 3 $1\cnt_2_26[2:0] - attribute \src "libresoc.v:34953.3-34972.6" + attribute \src "libresoc.v:35540.3-35559.6" wire width 3 $1\cnt_2_28[2:0] - attribute \src "libresoc.v:34678.3-34697.6" + attribute \src "libresoc.v:35265.3-35284.6" wire width 3 $1\cnt_2_2[2:0] - attribute \src "libresoc.v:34973.3-34992.6" + attribute \src "libresoc.v:35560.3-35579.6" wire width 3 $1\cnt_2_30[2:0] - attribute \src "libresoc.v:34698.3-34717.6" + attribute \src "libresoc.v:35285.3-35304.6" wire width 3 $1\cnt_2_4[2:0] - attribute \src "libresoc.v:34718.3-34737.6" + attribute \src "libresoc.v:35305.3-35324.6" wire width 3 $1\cnt_2_6[2:0] - attribute \src "libresoc.v:34738.3-34757.6" + attribute \src "libresoc.v:35325.3-35344.6" wire width 3 $1\cnt_2_8[2:0] - attribute \src "libresoc.v:34993.3-35012.6" + attribute \src "libresoc.v:35580.3-35599.6" wire width 4 $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35093.3-35112.6" + attribute \src "libresoc.v:35680.3-35699.6" wire width 4 $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35113.3-35132.6" + attribute \src "libresoc.v:35700.3-35719.6" wire width 4 $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35133.3-35152.6" + attribute \src "libresoc.v:35720.3-35739.6" wire width 4 $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35013.3-35032.6" + attribute \src "libresoc.v:35600.3-35619.6" wire width 4 $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35033.3-35052.6" + attribute \src "libresoc.v:35620.3-35639.6" wire width 4 $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35053.3-35072.6" + attribute \src "libresoc.v:35640.3-35659.6" wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35073.3-35092.6" + attribute \src "libresoc.v:35660.3-35679.6" wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35153.3-35172.6" + attribute \src "libresoc.v:35740.3-35759.6" wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35173.3-35192.6" + attribute \src "libresoc.v:35760.3-35779.6" wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35208.3-35227.6" + attribute \src "libresoc.v:35795.3-35814.6" wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35228.3-35247.6" + attribute \src "libresoc.v:35815.3-35834.6" wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35248.3-35267.6" + attribute \src "libresoc.v:35835.3-35854.6" wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35268.3-35287.6" + attribute \src "libresoc.v:35855.3-35874.6" wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35288.3-35307.6" + attribute \src "libresoc.v:35875.3-35894.6" wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:34658.3-34677.6" + attribute \src "libresoc.v:35245.3-35264.6" wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:34758.3-34777.6" + attribute \src "libresoc.v:35345.3-35364.6" wire width 3 $2\cnt_2_10[2:0] - attribute \src "libresoc.v:34793.3-34812.6" + attribute \src "libresoc.v:35380.3-35399.6" wire width 3 $2\cnt_2_12[2:0] - attribute \src "libresoc.v:34813.3-34832.6" + attribute \src "libresoc.v:35400.3-35419.6" wire width 3 $2\cnt_2_14[2:0] - attribute \src "libresoc.v:34833.3-34852.6" + attribute \src "libresoc.v:35420.3-35439.6" wire width 3 $2\cnt_2_16[2:0] - attribute \src "libresoc.v:34853.3-34872.6" + attribute \src "libresoc.v:35440.3-35459.6" wire width 3 $2\cnt_2_18[2:0] - attribute \src "libresoc.v:34873.3-34892.6" + attribute \src "libresoc.v:35460.3-35479.6" wire width 3 $2\cnt_2_20[2:0] - attribute \src "libresoc.v:34893.3-34912.6" + attribute \src "libresoc.v:35480.3-35499.6" wire width 3 $2\cnt_2_22[2:0] - attribute \src "libresoc.v:34913.3-34932.6" + attribute \src "libresoc.v:35500.3-35519.6" wire width 3 $2\cnt_2_24[2:0] - attribute \src "libresoc.v:34933.3-34952.6" + attribute \src "libresoc.v:35520.3-35539.6" wire width 3 $2\cnt_2_26[2:0] - attribute \src "libresoc.v:34953.3-34972.6" + attribute \src "libresoc.v:35540.3-35559.6" wire width 3 $2\cnt_2_28[2:0] - attribute \src "libresoc.v:34678.3-34697.6" + attribute \src "libresoc.v:35265.3-35284.6" wire width 3 $2\cnt_2_2[2:0] - attribute \src "libresoc.v:34973.3-34992.6" + attribute \src "libresoc.v:35560.3-35579.6" wire width 3 $2\cnt_2_30[2:0] - attribute \src "libresoc.v:34698.3-34717.6" + attribute \src "libresoc.v:35285.3-35304.6" wire width 3 $2\cnt_2_4[2:0] - attribute \src "libresoc.v:34718.3-34737.6" + attribute \src "libresoc.v:35305.3-35324.6" wire width 3 $2\cnt_2_6[2:0] - attribute \src "libresoc.v:34738.3-34757.6" + attribute \src "libresoc.v:35325.3-35344.6" wire width 3 $2\cnt_2_8[2:0] - attribute \src "libresoc.v:34993.3-35012.6" + attribute \src "libresoc.v:35580.3-35599.6" wire width 4 $2\cnt_3_0[3:0] - attribute \src "libresoc.v:35093.3-35112.6" + attribute \src "libresoc.v:35680.3-35699.6" wire width 4 $2\cnt_3_10[3:0] - attribute \src "libresoc.v:35113.3-35132.6" + attribute \src "libresoc.v:35700.3-35719.6" wire width 4 $2\cnt_3_12[3:0] - attribute \src "libresoc.v:35133.3-35152.6" + attribute \src "libresoc.v:35720.3-35739.6" wire width 4 $2\cnt_3_14[3:0] - attribute \src "libresoc.v:35013.3-35032.6" + attribute \src "libresoc.v:35600.3-35619.6" wire width 4 $2\cnt_3_2[3:0] - attribute \src "libresoc.v:35033.3-35052.6" + attribute \src "libresoc.v:35620.3-35639.6" wire width 4 $2\cnt_3_4[3:0] - attribute \src "libresoc.v:35053.3-35072.6" + attribute \src "libresoc.v:35640.3-35659.6" wire width 4 $2\cnt_3_6[3:0] - attribute \src "libresoc.v:35073.3-35092.6" + attribute \src "libresoc.v:35660.3-35679.6" wire width 4 $2\cnt_3_8[3:0] - attribute \src "libresoc.v:35153.3-35172.6" + attribute \src "libresoc.v:35740.3-35759.6" wire width 5 $2\cnt_4_0[4:0] - attribute \src "libresoc.v:35173.3-35192.6" + attribute \src "libresoc.v:35760.3-35779.6" wire width 5 $2\cnt_4_2[4:0] - attribute \src "libresoc.v:35208.3-35227.6" + attribute \src "libresoc.v:35795.3-35814.6" wire width 5 $2\cnt_4_4[4:0] - attribute \src "libresoc.v:35228.3-35247.6" + attribute \src "libresoc.v:35815.3-35834.6" wire width 5 $2\cnt_4_6[4:0] - attribute \src "libresoc.v:35248.3-35267.6" + attribute \src "libresoc.v:35835.3-35854.6" wire width 6 $2\cnt_5_0[5:0] - attribute \src "libresoc.v:35268.3-35287.6" + attribute \src "libresoc.v:35855.3-35874.6" wire width 6 $2\cnt_5_2[5:0] - attribute \src "libresoc.v:35288.3-35307.6" + attribute \src "libresoc.v:35875.3-35894.6" wire width 7 $2\cnt_6_0[6:0] - attribute \src "libresoc.v:34115.17-34115.101" - wire $eq$libresoc.v:34115$1357_Y - attribute \src "libresoc.v:34116.18-34116.102" - wire $eq$libresoc.v:34116$1358_Y - attribute \src "libresoc.v:34118.19-34118.103" - wire $eq$libresoc.v:34118$1360_Y - attribute \src "libresoc.v:34119.19-34119.103" - wire $eq$libresoc.v:34119$1361_Y - attribute \src "libresoc.v:34121.19-34121.104" - wire $eq$libresoc.v:34121$1363_Y - attribute \src "libresoc.v:34122.19-34122.103" - wire $eq$libresoc.v:34122$1364_Y - attribute \src "libresoc.v:34124.19-34124.104" - wire $eq$libresoc.v:34124$1366_Y - attribute \src "libresoc.v:34125.19-34125.104" - wire $eq$libresoc.v:34125$1367_Y - attribute \src "libresoc.v:34128.19-34128.104" - wire $eq$libresoc.v:34128$1370_Y - attribute \src "libresoc.v:34129.19-34129.104" - wire $eq$libresoc.v:34129$1371_Y - attribute \src "libresoc.v:34131.19-34131.104" - wire $eq$libresoc.v:34131$1373_Y - attribute \src "libresoc.v:34132.19-34132.104" - wire $eq$libresoc.v:34132$1374_Y - attribute \src "libresoc.v:34134.19-34134.104" - wire $eq$libresoc.v:34134$1376_Y - attribute \src "libresoc.v:34135.19-34135.104" - wire $eq$libresoc.v:34135$1377_Y - attribute \src "libresoc.v:34137.18-34137.102" - wire $eq$libresoc.v:34137$1379_Y - attribute \src "libresoc.v:34138.19-34138.104" - wire $eq$libresoc.v:34138$1380_Y - attribute \src "libresoc.v:34139.19-34139.104" - wire $eq$libresoc.v:34139$1381_Y - attribute \src "libresoc.v:34141.19-34141.103" - wire $eq$libresoc.v:34141$1383_Y - attribute \src "libresoc.v:34142.19-34142.103" - wire $eq$libresoc.v:34142$1384_Y - attribute \src "libresoc.v:34144.19-34144.103" - wire $eq$libresoc.v:34144$1386_Y - attribute \src "libresoc.v:34145.19-34145.103" - wire $eq$libresoc.v:34145$1387_Y - attribute \src "libresoc.v:34147.19-34147.104" - wire $eq$libresoc.v:34147$1389_Y - attribute \src "libresoc.v:34148.18-34148.102" - wire $eq$libresoc.v:34148$1390_Y - attribute \src "libresoc.v:34149.19-34149.103" - wire $eq$libresoc.v:34149$1391_Y - attribute \src "libresoc.v:34151.19-34151.104" - wire $eq$libresoc.v:34151$1393_Y - attribute \src "libresoc.v:34152.19-34152.104" - wire $eq$libresoc.v:34152$1394_Y - attribute \src "libresoc.v:34154.19-34154.103" - wire $eq$libresoc.v:34154$1396_Y - attribute \src "libresoc.v:34155.19-34155.103" - wire $eq$libresoc.v:34155$1397_Y - attribute \src "libresoc.v:34157.19-34157.103" - wire $eq$libresoc.v:34157$1399_Y - attribute \src "libresoc.v:34158.19-34158.103" - wire $eq$libresoc.v:34158$1400_Y - attribute \src "libresoc.v:34161.19-34161.103" - wire $eq$libresoc.v:34161$1403_Y - attribute \src "libresoc.v:34162.19-34162.103" - wire $eq$libresoc.v:34162$1404_Y - attribute \src "libresoc.v:34164.17-34164.101" - wire $eq$libresoc.v:34164$1406_Y - attribute \src "libresoc.v:34165.18-34165.102" - wire $eq$libresoc.v:34165$1407_Y - attribute \src "libresoc.v:34166.18-34166.102" - wire $eq$libresoc.v:34166$1408_Y - attribute \src "libresoc.v:34168.18-34168.102" - wire $eq$libresoc.v:34168$1410_Y - attribute \src "libresoc.v:34169.18-34169.102" - wire $eq$libresoc.v:34169$1411_Y - attribute \src "libresoc.v:34171.18-34171.103" - wire $eq$libresoc.v:34171$1413_Y - attribute \src "libresoc.v:34172.18-34172.103" - wire $eq$libresoc.v:34172$1414_Y - attribute \src "libresoc.v:34174.18-34174.103" - wire $eq$libresoc.v:34174$1416_Y - attribute \src "libresoc.v:34175.17-34175.101" - wire $eq$libresoc.v:34175$1417_Y - attribute \src "libresoc.v:34176.18-34176.103" - wire $eq$libresoc.v:34176$1418_Y - attribute \src "libresoc.v:34178.18-34178.103" - wire $eq$libresoc.v:34178$1420_Y - attribute \src "libresoc.v:34179.18-34179.103" - wire $eq$libresoc.v:34179$1421_Y - attribute \src "libresoc.v:34181.18-34181.103" - wire $eq$libresoc.v:34181$1423_Y - attribute \src "libresoc.v:34182.18-34182.103" - wire $eq$libresoc.v:34182$1424_Y - attribute \src "libresoc.v:34184.18-34184.103" - wire $eq$libresoc.v:34184$1426_Y - attribute \src "libresoc.v:34185.18-34185.103" - wire $eq$libresoc.v:34185$1427_Y - attribute \src "libresoc.v:34188.18-34188.103" - wire $eq$libresoc.v:34188$1430_Y - attribute \src "libresoc.v:34189.18-34189.103" - wire $eq$libresoc.v:34189$1431_Y - attribute \src "libresoc.v:34191.18-34191.103" - wire $eq$libresoc.v:34191$1433_Y - attribute \src "libresoc.v:34192.18-34192.103" - wire $eq$libresoc.v:34192$1434_Y - attribute \src "libresoc.v:34194.18-34194.103" - wire $eq$libresoc.v:34194$1436_Y - attribute \src "libresoc.v:34195.18-34195.103" - wire $eq$libresoc.v:34195$1437_Y - attribute \src "libresoc.v:34197.17-34197.101" - wire $eq$libresoc.v:34197$1439_Y - attribute \src "libresoc.v:34198.18-34198.103" - wire $eq$libresoc.v:34198$1440_Y - attribute \src "libresoc.v:34199.18-34199.103" - wire $eq$libresoc.v:34199$1441_Y - attribute \src "libresoc.v:34201.18-34201.103" - wire $eq$libresoc.v:34201$1443_Y - attribute \src "libresoc.v:34202.18-34202.103" - wire $eq$libresoc.v:34202$1444_Y - attribute \src "libresoc.v:34204.18-34204.103" - wire $eq$libresoc.v:34204$1446_Y - attribute \src "libresoc.v:34205.18-34205.103" - wire $eq$libresoc.v:34205$1447_Y - attribute \src "libresoc.v:34207.18-34207.102" - wire $eq$libresoc.v:34207$1449_Y - attribute \src "libresoc.v:34117.19-34117.109" - wire width 4 $pos$libresoc.v:34117$1359_Y - attribute \src "libresoc.v:34120.19-34120.109" - wire width 4 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$eq$libresoc.v:34776$1463_Y + attribute \src "libresoc.v:34778.18-34778.103" + wire $eq$libresoc.v:34778$1465_Y + attribute \src "libresoc.v:34779.18-34779.103" + wire $eq$libresoc.v:34779$1466_Y + attribute \src "libresoc.v:34781.18-34781.103" + wire $eq$libresoc.v:34781$1468_Y + attribute \src "libresoc.v:34782.18-34782.103" + wire $eq$libresoc.v:34782$1469_Y + attribute \src "libresoc.v:34784.17-34784.101" + wire $eq$libresoc.v:34784$1471_Y + attribute \src "libresoc.v:34785.18-34785.103" + wire $eq$libresoc.v:34785$1472_Y + attribute \src "libresoc.v:34786.18-34786.103" + wire $eq$libresoc.v:34786$1473_Y + attribute \src "libresoc.v:34788.18-34788.103" + wire $eq$libresoc.v:34788$1475_Y + attribute \src "libresoc.v:34789.18-34789.103" + wire $eq$libresoc.v:34789$1476_Y + attribute \src "libresoc.v:34791.18-34791.103" + wire $eq$libresoc.v:34791$1478_Y + attribute \src "libresoc.v:34792.18-34792.103" + wire $eq$libresoc.v:34792$1479_Y + attribute \src "libresoc.v:34794.18-34794.102" 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"libresoc.v:34733.19-34733.109" + wire width 5 $pos$libresoc.v:34733$1420_Y + attribute \src "libresoc.v:34737.19-34737.109" + wire width 5 $pos$libresoc.v:34737$1424_Y + attribute \src "libresoc.v:34740.19-34740.110" + wire width 5 $pos$libresoc.v:34740$1427_Y + attribute \src "libresoc.v:34743.19-34743.109" + wire width 6 $pos$libresoc.v:34743$1430_Y + attribute \src "libresoc.v:34746.18-34746.106" + wire width 3 $pos$libresoc.v:34746$1433_Y + attribute \src "libresoc.v:34747.19-34747.109" + wire width 6 $pos$libresoc.v:34747$1434_Y + attribute \src "libresoc.v:34750.19-34750.109" + wire width 7 $pos$libresoc.v:34750$1437_Y + attribute \src "libresoc.v:34754.18-34754.106" + wire width 3 $pos$libresoc.v:34754$1441_Y + attribute \src "libresoc.v:34757.18-34757.106" + wire width 3 $pos$libresoc.v:34757$1444_Y + attribute \src "libresoc.v:34760.18-34760.107" + wire width 3 $pos$libresoc.v:34760$1447_Y + attribute \src "libresoc.v:34764.18-34764.107" + wire width 3 $pos$libresoc.v:34764$1451_Y + attribute \src "libresoc.v:34767.18-34767.107" + wire width 3 $pos$libresoc.v:34767$1454_Y + attribute \src "libresoc.v:34770.18-34770.107" + wire width 3 $pos$libresoc.v:34770$1457_Y + attribute \src "libresoc.v:34773.17-34773.105" + wire width 3 $pos$libresoc.v:34773$1460_Y + attribute \src "libresoc.v:34774.18-34774.107" + wire width 3 $pos$libresoc.v:34774$1461_Y + attribute \src "libresoc.v:34777.18-34777.107" + wire width 3 $pos$libresoc.v:34777$1464_Y + attribute \src "libresoc.v:34780.18-34780.107" + wire width 3 $pos$libresoc.v:34780$1467_Y + attribute \src "libresoc.v:34783.18-34783.107" + wire width 3 $pos$libresoc.v:34783$1470_Y + attribute \src "libresoc.v:34787.18-34787.107" + wire width 3 $pos$libresoc.v:34787$1474_Y + attribute \src "libresoc.v:34790.18-34790.107" + wire width 3 $pos$libresoc.v:34790$1477_Y + attribute \src "libresoc.v:34793.18-34793.107" + wire width 3 $pos$libresoc.v:34793$1480_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" @@ -53001,7 +53860,7 @@ module \clz wire width 6 \cnt_5_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" wire width 7 \cnt_6_0 - attribute \src "libresoc.v:33734.7-33734.15" + attribute \src "libresoc.v:34321.7-34321.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" wire width 7 output 1 \lz @@ -53072,7 +53931,7 @@ module \clz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" wire width 64 input 2 \sig_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34115$1357 + cell $eq $eq$libresoc.v:34702$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53080,10 +53939,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34115$1357_Y + connect \Y $eq$libresoc.v:34702$1389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34116$1358 + cell $eq $eq$libresoc.v:34703$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53091,10 +53950,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34116$1358_Y + connect \Y $eq$libresoc.v:34703$1390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34118$1360 + cell $eq $eq$libresoc.v:34705$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53102,10 +53961,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34118$1360_Y + connect \Y $eq$libresoc.v:34705$1392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34119$1361 + cell $eq $eq$libresoc.v:34706$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53113,10 +53972,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34119$1361_Y + connect \Y $eq$libresoc.v:34706$1393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34121$1363 + cell $eq $eq$libresoc.v:34708$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53124,10 +53983,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34121$1363_Y + connect \Y $eq$libresoc.v:34708$1395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34122$1364 + cell $eq $eq$libresoc.v:34709$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53135,10 +53994,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34122$1364_Y + connect \Y $eq$libresoc.v:34709$1396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34124$1366 + cell $eq $eq$libresoc.v:34711$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53146,10 +54005,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34124$1366_Y + connect \Y $eq$libresoc.v:34711$1398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34125$1367 + cell $eq $eq$libresoc.v:34712$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53157,10 +54016,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34125$1367_Y + connect \Y $eq$libresoc.v:34712$1399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34128$1370 + cell $eq $eq$libresoc.v:34715$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53168,10 +54027,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34128$1370_Y + connect \Y $eq$libresoc.v:34715$1402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34129$1371 + cell $eq $eq$libresoc.v:34716$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53179,10 +54038,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34129$1371_Y + connect \Y $eq$libresoc.v:34716$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34131$1373 + cell $eq $eq$libresoc.v:34718$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53190,10 +54049,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34131$1373_Y + connect \Y $eq$libresoc.v:34718$1405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34132$1374 + cell $eq $eq$libresoc.v:34719$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53201,10 +54060,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34132$1374_Y + connect \Y $eq$libresoc.v:34719$1406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34134$1376 + cell $eq $eq$libresoc.v:34721$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53212,10 +54071,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34134$1376_Y + connect \Y $eq$libresoc.v:34721$1408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34135$1377 + cell $eq $eq$libresoc.v:34722$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53223,10 +54082,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34135$1377_Y + connect \Y $eq$libresoc.v:34722$1409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34137$1379 + cell $eq $eq$libresoc.v:34724$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53234,10 +54093,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34137$1379_Y + connect \Y $eq$libresoc.v:34724$1411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34138$1380 + cell $eq $eq$libresoc.v:34725$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53245,10 +54104,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34138$1380_Y + connect \Y $eq$libresoc.v:34725$1412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34139$1381 + cell $eq $eq$libresoc.v:34726$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53256,10 +54115,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34139$1381_Y + connect \Y $eq$libresoc.v:34726$1413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34141$1383 + cell $eq $eq$libresoc.v:34728$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53267,10 +54126,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34141$1383_Y + connect \Y $eq$libresoc.v:34728$1415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34142$1384 + cell $eq $eq$libresoc.v:34729$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53278,10 +54137,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34142$1384_Y + connect \Y $eq$libresoc.v:34729$1416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34144$1386 + cell $eq $eq$libresoc.v:34731$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53289,10 +54148,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34144$1386_Y + connect \Y $eq$libresoc.v:34731$1418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34145$1387 + cell $eq $eq$libresoc.v:34732$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53300,10 +54159,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34145$1387_Y + connect \Y $eq$libresoc.v:34732$1419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34147$1389 + cell $eq $eq$libresoc.v:34734$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53311,10 +54170,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34147$1389_Y + connect \Y $eq$libresoc.v:34734$1421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34148$1390 + cell $eq $eq$libresoc.v:34735$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53322,10 +54181,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34148$1390_Y + connect \Y $eq$libresoc.v:34735$1422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34149$1391 + cell $eq $eq$libresoc.v:34736$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53333,10 +54192,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34149$1391_Y + connect \Y $eq$libresoc.v:34736$1423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34151$1393 + cell $eq $eq$libresoc.v:34738$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53344,10 +54203,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34151$1393_Y + connect \Y $eq$libresoc.v:34738$1425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34152$1394 + cell $eq $eq$libresoc.v:34739$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53355,10 +54214,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:34152$1394_Y + connect \Y $eq$libresoc.v:34739$1426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34154$1396 + cell $eq $eq$libresoc.v:34741$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53366,10 +54225,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34154$1396_Y + connect \Y $eq$libresoc.v:34741$1428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34155$1397 + cell $eq $eq$libresoc.v:34742$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53377,10 +54236,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34155$1397_Y + connect \Y $eq$libresoc.v:34742$1429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34157$1399 + cell $eq $eq$libresoc.v:34744$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53388,10 +54247,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34157$1399_Y + connect \Y $eq$libresoc.v:34744$1431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34158$1400 + cell $eq $eq$libresoc.v:34745$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53399,10 +54258,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:34158$1400_Y + connect \Y $eq$libresoc.v:34745$1432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34161$1403 + cell $eq $eq$libresoc.v:34748$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53410,10 +54269,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34161$1403_Y + connect \Y $eq$libresoc.v:34748$1435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34162$1404 + cell $eq $eq$libresoc.v:34749$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53421,10 +54280,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:34162$1404_Y + connect \Y $eq$libresoc.v:34749$1436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34164$1406 + cell $eq $eq$libresoc.v:34751$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53432,10 +54291,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34164$1406_Y + connect \Y $eq$libresoc.v:34751$1438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34165$1407 + cell $eq $eq$libresoc.v:34752$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53443,10 +54302,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34165$1407_Y + connect \Y $eq$libresoc.v:34752$1439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34166$1408 + cell $eq $eq$libresoc.v:34753$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53454,10 +54313,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34166$1408_Y + connect \Y $eq$libresoc.v:34753$1440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34168$1410 + cell $eq $eq$libresoc.v:34755$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53465,10 +54324,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34168$1410_Y + connect \Y $eq$libresoc.v:34755$1442_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34169$1411 + cell $eq $eq$libresoc.v:34756$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53476,10 +54335,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34169$1411_Y + connect \Y $eq$libresoc.v:34756$1443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34171$1413 + cell $eq $eq$libresoc.v:34758$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53487,10 +54346,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34171$1413_Y + connect \Y $eq$libresoc.v:34758$1445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34172$1414 + cell $eq $eq$libresoc.v:34759$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53498,10 +54357,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34172$1414_Y + connect \Y $eq$libresoc.v:34759$1446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34174$1416 + cell $eq $eq$libresoc.v:34761$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53509,10 +54368,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34174$1416_Y + connect \Y $eq$libresoc.v:34761$1448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34175$1417 + cell $eq $eq$libresoc.v:34762$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53520,10 +54379,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34175$1417_Y + connect \Y $eq$libresoc.v:34762$1449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34176$1418 + cell $eq $eq$libresoc.v:34763$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53531,10 +54390,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34176$1418_Y + connect \Y $eq$libresoc.v:34763$1450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34178$1420 + cell $eq $eq$libresoc.v:34765$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53542,10 +54401,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34178$1420_Y + connect \Y $eq$libresoc.v:34765$1452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34179$1421 + cell $eq $eq$libresoc.v:34766$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53553,10 +54412,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34179$1421_Y + connect \Y $eq$libresoc.v:34766$1453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34181$1423 + cell $eq $eq$libresoc.v:34768$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53564,10 +54423,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34181$1423_Y + connect \Y $eq$libresoc.v:34768$1455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34182$1424 + cell $eq $eq$libresoc.v:34769$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53575,10 +54434,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34182$1424_Y + connect \Y $eq$libresoc.v:34769$1456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34184$1426 + cell $eq $eq$libresoc.v:34771$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53586,10 +54445,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34184$1426_Y + connect \Y $eq$libresoc.v:34771$1458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34185$1427 + cell $eq $eq$libresoc.v:34772$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53597,10 +54456,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34185$1427_Y + connect \Y $eq$libresoc.v:34772$1459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34188$1430 + cell $eq $eq$libresoc.v:34775$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53608,10 +54467,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34188$1430_Y + connect \Y $eq$libresoc.v:34775$1462_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34189$1431 + cell $eq $eq$libresoc.v:34776$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53619,10 +54478,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34189$1431_Y + connect \Y $eq$libresoc.v:34776$1463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34191$1433 + cell $eq $eq$libresoc.v:34778$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53630,10 +54489,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34191$1433_Y + connect \Y $eq$libresoc.v:34778$1465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34192$1434 + cell $eq $eq$libresoc.v:34779$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53641,10 +54500,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34192$1434_Y + connect \Y $eq$libresoc.v:34779$1466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34194$1436 + cell $eq $eq$libresoc.v:34781$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53652,10 +54511,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34194$1436_Y + connect \Y $eq$libresoc.v:34781$1468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34195$1437 + cell $eq $eq$libresoc.v:34782$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53663,10 +54522,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34195$1437_Y + connect \Y $eq$libresoc.v:34782$1469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34197$1439 + cell $eq $eq$libresoc.v:34784$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53674,10 +54533,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34197$1439_Y + connect \Y $eq$libresoc.v:34784$1471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34198$1440 + cell $eq $eq$libresoc.v:34785$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53685,10 +54544,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34198$1440_Y + connect \Y $eq$libresoc.v:34785$1472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34199$1441 + cell $eq $eq$libresoc.v:34786$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53696,10 +54555,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34199$1441_Y + connect \Y $eq$libresoc.v:34786$1473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34201$1443 + cell $eq $eq$libresoc.v:34788$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53707,10 +54566,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34201$1443_Y + connect \Y $eq$libresoc.v:34788$1475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34202$1444 + cell $eq $eq$libresoc.v:34789$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53718,10 +54577,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34202$1444_Y + connect \Y $eq$libresoc.v:34789$1476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34204$1446 + cell $eq $eq$libresoc.v:34791$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53729,10 +54588,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34204$1446_Y + connect \Y $eq$libresoc.v:34791$1478_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34205$1447 + cell $eq $eq$libresoc.v:34792$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53740,10 +54599,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34205$1447_Y + connect \Y $eq$libresoc.v:34792$1479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34207$1449 + cell $eq $eq$libresoc.v:34794$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53751,271 +54610,271 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34207$1449_Y + connect \Y $eq$libresoc.v:34794$1481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34117$1359 + cell $pos $pos$libresoc.v:34704$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34117$1359_Y + connect \Y $pos$libresoc.v:34704$1391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34120$1362 + cell $pos $pos$libresoc.v:34707$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34120$1362_Y + connect \Y $pos$libresoc.v:34707$1394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34123$1365 + cell $pos $pos$libresoc.v:34710$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34123$1365_Y + connect \Y $pos$libresoc.v:34710$1397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34126$1368 + cell $pos $pos$libresoc.v:34713$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34126$1368_Y + connect \Y $pos$libresoc.v:34713$1400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34127$1369 + cell $pos $pos$libresoc.v:34714$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34127$1369_Y + connect \Y $pos$libresoc.v:34714$1401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34130$1372 + cell $pos $pos$libresoc.v:34717$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34130$1372_Y + connect \Y $pos$libresoc.v:34717$1404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34133$1375 + cell $pos $pos$libresoc.v:34720$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:34133$1375_Y + connect \Y $pos$libresoc.v:34720$1407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34136$1378 + cell $pos $pos$libresoc.v:34723$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:34136$1378_Y + connect \Y $pos$libresoc.v:34723$1410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34140$1382 + cell $pos $pos$libresoc.v:34727$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:34140$1382_Y + connect \Y $pos$libresoc.v:34727$1414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34143$1385 + cell $pos $pos$libresoc.v:34730$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:34143$1385_Y + connect \Y $pos$libresoc.v:34730$1417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34146$1388 + cell $pos $pos$libresoc.v:34733$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:34146$1388_Y + connect \Y $pos$libresoc.v:34733$1420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34150$1392 + cell $pos $pos$libresoc.v:34737$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:34150$1392_Y + connect \Y $pos$libresoc.v:34737$1424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34153$1395 + cell $pos $pos$libresoc.v:34740$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:34153$1395_Y + connect \Y $pos$libresoc.v:34740$1427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34156$1398 + cell $pos $pos$libresoc.v:34743$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:34156$1398_Y + connect \Y $pos$libresoc.v:34743$1430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34159$1401 + cell $pos $pos$libresoc.v:34746$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:34159$1401_Y + connect \Y $pos$libresoc.v:34746$1433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34160$1402 + cell $pos $pos$libresoc.v:34747$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:34160$1402_Y + connect \Y $pos$libresoc.v:34747$1434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34163$1405 + cell $pos $pos$libresoc.v:34750$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:34163$1405_Y + connect \Y $pos$libresoc.v:34750$1437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34167$1409 + cell $pos $pos$libresoc.v:34754$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:34167$1409_Y + connect \Y $pos$libresoc.v:34754$1441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34170$1412 + cell $pos $pos$libresoc.v:34757$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:34170$1412_Y + connect \Y $pos$libresoc.v:34757$1444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34173$1415 + cell $pos $pos$libresoc.v:34760$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:34173$1415_Y + connect \Y $pos$libresoc.v:34760$1447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34177$1419 + cell $pos $pos$libresoc.v:34764$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:34177$1419_Y + connect \Y $pos$libresoc.v:34764$1451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34180$1422 + cell $pos $pos$libresoc.v:34767$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:34180$1422_Y + connect \Y $pos$libresoc.v:34767$1454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34183$1425 + cell $pos $pos$libresoc.v:34770$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:34183$1425_Y + connect \Y $pos$libresoc.v:34770$1457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34186$1428 + cell $pos $pos$libresoc.v:34773$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:34186$1428_Y + connect \Y $pos$libresoc.v:34773$1460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34187$1429 + cell $pos $pos$libresoc.v:34774$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:34187$1429_Y + connect \Y $pos$libresoc.v:34774$1461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34190$1432 + cell $pos $pos$libresoc.v:34777$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:34190$1432_Y + connect \Y $pos$libresoc.v:34777$1464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34193$1435 + cell $pos $pos$libresoc.v:34780$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:34193$1435_Y + connect \Y $pos$libresoc.v:34780$1467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34196$1438 + cell $pos $pos$libresoc.v:34783$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:34196$1438_Y + connect \Y $pos$libresoc.v:34783$1470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34200$1442 + cell $pos $pos$libresoc.v:34787$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:34200$1442_Y + connect \Y $pos$libresoc.v:34787$1474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34203$1445 + cell $pos $pos$libresoc.v:34790$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:34203$1445_Y + connect \Y $pos$libresoc.v:34790$1477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34206$1448 + cell $pos $pos$libresoc.v:34793$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:34206$1448_Y + connect \Y $pos$libresoc.v:34793$1480_Y end - attribute \src "libresoc.v:33734.7-33734.20" - process $proc$libresoc.v:33734$1513 + attribute \src "libresoc.v:34321.7-34321.20" + process $proc$libresoc.v:34321$1545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34208.3-34222.6" - process $proc$libresoc.v:34208$1450 + attribute \src "libresoc.v:34795.3-34809.6" + process $proc$libresoc.v:34795$1482 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34209.5-34209.29" + attribute \src "libresoc.v:34796.5-34796.29" switch \initial - attribute \src "libresoc.v:34209.9-34209.17" + attribute \src "libresoc.v:34796.9-34796.17" case 1'1 case end @@ -54037,13 +54896,13 @@ module \clz sync always update \cnt_1_0 $0\cnt_1_0[1:0] end - attribute \src "libresoc.v:34223.3-34237.6" - process $proc$libresoc.v:34223$1451 + attribute \src "libresoc.v:34810.3-34824.6" + process $proc$libresoc.v:34810$1483 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34224.5-34224.29" + attribute \src "libresoc.v:34811.5-34811.29" switch \initial - attribute \src "libresoc.v:34224.9-34224.17" + attribute \src "libresoc.v:34811.9-34811.17" case 1'1 case end @@ -54065,13 +54924,13 @@ module \clz sync always update \cnt_1_5 $0\cnt_1_5[1:0] end - attribute \src "libresoc.v:34238.3-34252.6" - process $proc$libresoc.v:34238$1452 + attribute \src "libresoc.v:34825.3-34839.6" + process $proc$libresoc.v:34825$1484 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34239.5-34239.29" + attribute \src "libresoc.v:34826.5-34826.29" switch \initial - attribute \src "libresoc.v:34239.9-34239.17" + attribute \src "libresoc.v:34826.9-34826.17" case 1'1 case end @@ -54093,13 +54952,13 @@ module \clz sync always update \cnt_1_6 $0\cnt_1_6[1:0] end - attribute \src "libresoc.v:34253.3-34267.6" - process $proc$libresoc.v:34253$1453 + attribute \src "libresoc.v:34840.3-34854.6" + process $proc$libresoc.v:34840$1485 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34254.5-34254.29" + attribute \src "libresoc.v:34841.5-34841.29" switch \initial - attribute \src "libresoc.v:34254.9-34254.17" + attribute \src "libresoc.v:34841.9-34841.17" case 1'1 case end @@ -54121,13 +54980,13 @@ module \clz sync always update \cnt_1_7 $0\cnt_1_7[1:0] end - attribute \src "libresoc.v:34268.3-34282.6" - process $proc$libresoc.v:34268$1454 + attribute \src "libresoc.v:34855.3-34869.6" + process $proc$libresoc.v:34855$1486 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34269.5-34269.29" + attribute \src "libresoc.v:34856.5-34856.29" switch \initial - attribute \src "libresoc.v:34269.9-34269.17" + attribute \src "libresoc.v:34856.9-34856.17" case 1'1 case end @@ -54149,13 +55008,13 @@ module \clz sync always update \cnt_1_8 $0\cnt_1_8[1:0] end - attribute \src "libresoc.v:34283.3-34297.6" - process $proc$libresoc.v:34283$1455 + attribute \src "libresoc.v:34870.3-34884.6" + process $proc$libresoc.v:34870$1487 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:34284.5-34284.29" + attribute \src "libresoc.v:34871.5-34871.29" switch \initial - attribute \src "libresoc.v:34284.9-34284.17" + attribute \src "libresoc.v:34871.9-34871.17" case 1'1 case end @@ -54177,13 +55036,13 @@ module \clz sync always update \cnt_1_9 $0\cnt_1_9[1:0] end - attribute \src "libresoc.v:34298.3-34312.6" - process $proc$libresoc.v:34298$1456 + attribute \src "libresoc.v:34885.3-34899.6" + process $proc$libresoc.v:34885$1488 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34299.5-34299.29" + attribute \src "libresoc.v:34886.5-34886.29" switch \initial - attribute \src "libresoc.v:34299.9-34299.17" + attribute \src "libresoc.v:34886.9-34886.17" case 1'1 case end @@ -54205,13 +55064,13 @@ module \clz sync always update \cnt_1_10 $0\cnt_1_10[1:0] end - attribute \src "libresoc.v:34313.3-34327.6" - process $proc$libresoc.v:34313$1457 + attribute \src "libresoc.v:34900.3-34914.6" + process $proc$libresoc.v:34900$1489 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34314.5-34314.29" + attribute \src "libresoc.v:34901.5-34901.29" switch \initial - attribute \src "libresoc.v:34314.9-34314.17" + attribute \src "libresoc.v:34901.9-34901.17" case 1'1 case end @@ -54233,13 +55092,13 @@ module \clz sync always update \cnt_1_11 $0\cnt_1_11[1:0] end - attribute \src "libresoc.v:34328.3-34342.6" - process $proc$libresoc.v:34328$1458 + attribute \src "libresoc.v:34915.3-34929.6" + process $proc$libresoc.v:34915$1490 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34329.5-34329.29" + attribute \src "libresoc.v:34916.5-34916.29" switch \initial - attribute \src "libresoc.v:34329.9-34329.17" + attribute \src "libresoc.v:34916.9-34916.17" case 1'1 case end @@ -54261,13 +55120,13 @@ module \clz sync always update \cnt_1_12 $0\cnt_1_12[1:0] end - attribute \src "libresoc.v:34343.3-34357.6" - process $proc$libresoc.v:34343$1459 + attribute \src "libresoc.v:34930.3-34944.6" + process $proc$libresoc.v:34930$1491 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34344.5-34344.29" + attribute \src "libresoc.v:34931.5-34931.29" switch \initial - attribute \src "libresoc.v:34344.9-34344.17" + attribute \src "libresoc.v:34931.9-34931.17" case 1'1 case end @@ -54289,13 +55148,13 @@ module \clz sync always update \cnt_1_13 $0\cnt_1_13[1:0] end - attribute \src "libresoc.v:34358.3-34372.6" - process $proc$libresoc.v:34358$1460 + attribute \src "libresoc.v:34945.3-34959.6" + process $proc$libresoc.v:34945$1492 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34359.5-34359.29" + attribute \src "libresoc.v:34946.5-34946.29" switch \initial - attribute \src "libresoc.v:34359.9-34359.17" + attribute \src "libresoc.v:34946.9-34946.17" case 1'1 case end @@ -54317,13 +55176,13 @@ module \clz sync always update \cnt_1_14 $0\cnt_1_14[1:0] end - attribute \src "libresoc.v:34373.3-34387.6" - process $proc$libresoc.v:34373$1461 + attribute \src "libresoc.v:34960.3-34974.6" + process $proc$libresoc.v:34960$1493 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:34374.5-34374.29" + attribute \src "libresoc.v:34961.5-34961.29" switch \initial - attribute \src "libresoc.v:34374.9-34374.17" + attribute \src "libresoc.v:34961.9-34961.17" case 1'1 case end @@ -54345,13 +55204,13 @@ module \clz sync always update \cnt_1_1 $0\cnt_1_1[1:0] end - attribute \src "libresoc.v:34388.3-34402.6" - process $proc$libresoc.v:34388$1462 + attribute \src "libresoc.v:34975.3-34989.6" + process $proc$libresoc.v:34975$1494 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34389.5-34389.29" + attribute \src "libresoc.v:34976.5-34976.29" switch \initial - attribute \src "libresoc.v:34389.9-34389.17" + attribute \src "libresoc.v:34976.9-34976.17" case 1'1 case end @@ -54373,13 +55232,13 @@ module \clz sync always update \cnt_1_15 $0\cnt_1_15[1:0] end - attribute \src "libresoc.v:34403.3-34417.6" - process $proc$libresoc.v:34403$1463 + attribute \src "libresoc.v:34990.3-35004.6" + process $proc$libresoc.v:34990$1495 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:34404.5-34404.29" + attribute \src "libresoc.v:34991.5-34991.29" switch \initial - attribute \src "libresoc.v:34404.9-34404.17" + attribute \src "libresoc.v:34991.9-34991.17" case 1'1 case end @@ -54401,13 +55260,13 @@ module \clz sync always update \cnt_1_16 $0\cnt_1_16[1:0] end - attribute \src "libresoc.v:34418.3-34432.6" - process $proc$libresoc.v:34418$1464 + attribute \src "libresoc.v:35005.3-35019.6" + process $proc$libresoc.v:35005$1496 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:34419.5-34419.29" + attribute \src "libresoc.v:35006.5-35006.29" switch \initial - attribute \src "libresoc.v:34419.9-34419.17" + attribute \src "libresoc.v:35006.9-35006.17" case 1'1 case end @@ -54429,13 +55288,13 @@ module \clz sync always update \cnt_1_17 $0\cnt_1_17[1:0] end - attribute \src "libresoc.v:34433.3-34447.6" - process $proc$libresoc.v:34433$1465 + attribute \src "libresoc.v:35020.3-35034.6" + process $proc$libresoc.v:35020$1497 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:34434.5-34434.29" + attribute \src "libresoc.v:35021.5-35021.29" switch \initial - attribute \src "libresoc.v:34434.9-34434.17" + attribute \src "libresoc.v:35021.9-35021.17" case 1'1 case end @@ -54457,13 +55316,13 @@ module \clz sync always update \cnt_1_18 $0\cnt_1_18[1:0] end - attribute \src "libresoc.v:34448.3-34462.6" - process $proc$libresoc.v:34448$1466 + attribute \src "libresoc.v:35035.3-35049.6" + process $proc$libresoc.v:35035$1498 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:34449.5-34449.29" + attribute \src "libresoc.v:35036.5-35036.29" switch \initial - attribute \src "libresoc.v:34449.9-34449.17" + attribute \src "libresoc.v:35036.9-35036.17" case 1'1 case end @@ -54485,13 +55344,13 @@ module \clz sync always update \cnt_1_19 $0\cnt_1_19[1:0] end - attribute \src "libresoc.v:34463.3-34477.6" - process $proc$libresoc.v:34463$1467 + attribute \src "libresoc.v:35050.3-35064.6" + process $proc$libresoc.v:35050$1499 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:34464.5-34464.29" + attribute \src "libresoc.v:35051.5-35051.29" switch \initial - attribute \src "libresoc.v:34464.9-34464.17" + attribute \src "libresoc.v:35051.9-35051.17" case 1'1 case end @@ -54513,13 +55372,13 @@ module \clz sync always update \cnt_1_20 $0\cnt_1_20[1:0] end - attribute \src "libresoc.v:34478.3-34492.6" - process $proc$libresoc.v:34478$1468 + attribute \src "libresoc.v:35065.3-35079.6" + process $proc$libresoc.v:35065$1500 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:34479.5-34479.29" + attribute \src "libresoc.v:35066.5-35066.29" switch \initial - attribute \src "libresoc.v:34479.9-34479.17" + attribute \src "libresoc.v:35066.9-35066.17" case 1'1 case end @@ -54541,13 +55400,13 @@ module \clz sync always update \cnt_1_21 $0\cnt_1_21[1:0] end - attribute \src "libresoc.v:34493.3-34507.6" - process $proc$libresoc.v:34493$1469 + attribute \src "libresoc.v:35080.3-35094.6" + process $proc$libresoc.v:35080$1501 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:34494.5-34494.29" + attribute \src "libresoc.v:35081.5-35081.29" switch \initial - attribute \src "libresoc.v:34494.9-34494.17" + attribute \src "libresoc.v:35081.9-35081.17" case 1'1 case end @@ -54569,13 +55428,13 @@ module \clz sync always update \cnt_1_22 $0\cnt_1_22[1:0] end - attribute \src "libresoc.v:34508.3-34522.6" - process $proc$libresoc.v:34508$1470 + attribute \src "libresoc.v:35095.3-35109.6" + process $proc$libresoc.v:35095$1502 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:34509.5-34509.29" + attribute \src "libresoc.v:35096.5-35096.29" switch \initial - attribute \src "libresoc.v:34509.9-34509.17" + attribute \src "libresoc.v:35096.9-35096.17" case 1'1 case end @@ -54597,13 +55456,13 @@ module \clz sync always update \cnt_1_23 $0\cnt_1_23[1:0] end - attribute \src "libresoc.v:34523.3-34537.6" - process $proc$libresoc.v:34523$1471 + attribute \src "libresoc.v:35110.3-35124.6" + process $proc$libresoc.v:35110$1503 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:34524.5-34524.29" + attribute \src "libresoc.v:35111.5-35111.29" switch \initial - attribute \src "libresoc.v:34524.9-34524.17" + attribute \src "libresoc.v:35111.9-35111.17" case 1'1 case end @@ -54625,13 +55484,13 @@ module \clz sync always update \cnt_1_24 $0\cnt_1_24[1:0] end - attribute \src "libresoc.v:34538.3-34552.6" - process $proc$libresoc.v:34538$1472 + attribute \src "libresoc.v:35125.3-35139.6" + process $proc$libresoc.v:35125$1504 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:34539.5-34539.29" + attribute \src "libresoc.v:35126.5-35126.29" switch \initial - attribute \src "libresoc.v:34539.9-34539.17" + attribute \src "libresoc.v:35126.9-35126.17" case 1'1 case end @@ -54653,13 +55512,13 @@ module \clz sync always update \cnt_1_2 $0\cnt_1_2[1:0] end - attribute \src "libresoc.v:34553.3-34567.6" - process $proc$libresoc.v:34553$1473 + attribute \src "libresoc.v:35140.3-35154.6" + process $proc$libresoc.v:35140$1505 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:34554.5-34554.29" + attribute \src "libresoc.v:35141.5-35141.29" switch \initial - attribute \src "libresoc.v:34554.9-34554.17" + attribute \src "libresoc.v:35141.9-35141.17" case 1'1 case end @@ -54681,13 +55540,13 @@ module \clz sync always update \cnt_1_25 $0\cnt_1_25[1:0] end - attribute \src "libresoc.v:34568.3-34582.6" - process $proc$libresoc.v:34568$1474 + attribute \src "libresoc.v:35155.3-35169.6" + process $proc$libresoc.v:35155$1506 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:34569.5-34569.29" + attribute \src "libresoc.v:35156.5-35156.29" switch \initial - attribute \src "libresoc.v:34569.9-34569.17" + attribute \src "libresoc.v:35156.9-35156.17" case 1'1 case end @@ -54709,13 +55568,13 @@ module \clz sync always update \cnt_1_26 $0\cnt_1_26[1:0] end - attribute \src "libresoc.v:34583.3-34597.6" - process $proc$libresoc.v:34583$1475 + attribute \src "libresoc.v:35170.3-35184.6" + process $proc$libresoc.v:35170$1507 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:34584.5-34584.29" + attribute \src "libresoc.v:35171.5-35171.29" switch \initial - attribute \src "libresoc.v:34584.9-34584.17" + attribute \src "libresoc.v:35171.9-35171.17" case 1'1 case end @@ -54737,13 +55596,13 @@ module \clz sync always update \cnt_1_27 $0\cnt_1_27[1:0] end - attribute \src "libresoc.v:34598.3-34612.6" - process $proc$libresoc.v:34598$1476 + attribute \src "libresoc.v:35185.3-35199.6" + process $proc$libresoc.v:35185$1508 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:34599.5-34599.29" + attribute \src "libresoc.v:35186.5-35186.29" switch \initial - attribute \src "libresoc.v:34599.9-34599.17" + attribute \src "libresoc.v:35186.9-35186.17" case 1'1 case end @@ -54765,13 +55624,13 @@ module \clz sync always update \cnt_1_28 $0\cnt_1_28[1:0] end - attribute \src "libresoc.v:34613.3-34627.6" - process $proc$libresoc.v:34613$1477 + attribute \src "libresoc.v:35200.3-35214.6" + process $proc$libresoc.v:35200$1509 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:34614.5-34614.29" + attribute \src "libresoc.v:35201.5-35201.29" switch \initial - attribute \src "libresoc.v:34614.9-34614.17" + attribute \src "libresoc.v:35201.9-35201.17" case 1'1 case end @@ -54793,13 +55652,13 @@ module \clz sync always update \cnt_1_29 $0\cnt_1_29[1:0] end - attribute \src "libresoc.v:34628.3-34642.6" - process $proc$libresoc.v:34628$1478 + attribute \src "libresoc.v:35215.3-35229.6" + process $proc$libresoc.v:35215$1510 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:34629.5-34629.29" + attribute \src "libresoc.v:35216.5-35216.29" switch \initial - attribute \src "libresoc.v:34629.9-34629.17" + attribute \src "libresoc.v:35216.9-35216.17" case 1'1 case end @@ -54821,13 +55680,13 @@ module \clz sync always update \cnt_1_30 $0\cnt_1_30[1:0] end - attribute \src "libresoc.v:34643.3-34657.6" - process $proc$libresoc.v:34643$1479 + attribute \src "libresoc.v:35230.3-35244.6" + process $proc$libresoc.v:35230$1511 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:34644.5-34644.29" + attribute \src "libresoc.v:35231.5-35231.29" switch \initial - attribute \src "libresoc.v:34644.9-34644.17" + attribute \src "libresoc.v:35231.9-35231.17" case 1'1 case end @@ -54849,13 +55708,13 @@ module \clz sync always update \cnt_1_31 $0\cnt_1_31[1:0] end - attribute \src "libresoc.v:34658.3-34677.6" - process $proc$libresoc.v:34658$1480 + attribute \src "libresoc.v:35245.3-35264.6" + process $proc$libresoc.v:35245$1512 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:34659.5-34659.29" + attribute \src "libresoc.v:35246.5-35246.29" switch \initial - attribute \src "libresoc.v:34659.9-34659.17" + attribute \src "libresoc.v:35246.9-35246.17" case 1'1 case end @@ -54884,13 +55743,13 @@ module \clz sync always update \cnt_2_0 $0\cnt_2_0[2:0] end - attribute \src "libresoc.v:34678.3-34697.6" - process $proc$libresoc.v:34678$1481 + attribute \src "libresoc.v:35265.3-35284.6" + process $proc$libresoc.v:35265$1513 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:34679.5-34679.29" + attribute \src "libresoc.v:35266.5-35266.29" switch \initial - attribute \src "libresoc.v:34679.9-34679.17" + attribute \src "libresoc.v:35266.9-35266.17" case 1'1 case end @@ -54919,13 +55778,13 @@ module \clz sync always update \cnt_2_2 $0\cnt_2_2[2:0] end - attribute \src "libresoc.v:34698.3-34717.6" - process $proc$libresoc.v:34698$1482 + attribute \src "libresoc.v:35285.3-35304.6" + process $proc$libresoc.v:35285$1514 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:34699.5-34699.29" + attribute \src "libresoc.v:35286.5-35286.29" switch \initial - attribute \src "libresoc.v:34699.9-34699.17" + attribute \src "libresoc.v:35286.9-35286.17" case 1'1 case end @@ -54954,13 +55813,13 @@ module \clz sync always update \cnt_2_4 $0\cnt_2_4[2:0] end - attribute \src "libresoc.v:34718.3-34737.6" - process $proc$libresoc.v:34718$1483 + attribute \src "libresoc.v:35305.3-35324.6" + process $proc$libresoc.v:35305$1515 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:34719.5-34719.29" + attribute \src "libresoc.v:35306.5-35306.29" switch \initial - attribute \src "libresoc.v:34719.9-34719.17" + attribute \src "libresoc.v:35306.9-35306.17" case 1'1 case end @@ -54989,13 +55848,13 @@ module \clz sync always update \cnt_2_6 $0\cnt_2_6[2:0] end - attribute \src "libresoc.v:34738.3-34757.6" - process $proc$libresoc.v:34738$1484 + attribute \src "libresoc.v:35325.3-35344.6" + process $proc$libresoc.v:35325$1516 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:34739.5-34739.29" + attribute \src "libresoc.v:35326.5-35326.29" switch \initial - attribute \src "libresoc.v:34739.9-34739.17" + attribute \src "libresoc.v:35326.9-35326.17" case 1'1 case end @@ -55024,13 +55883,13 @@ module \clz sync always update \cnt_2_8 $0\cnt_2_8[2:0] end - attribute \src "libresoc.v:34758.3-34777.6" - process $proc$libresoc.v:34758$1485 + attribute \src "libresoc.v:35345.3-35364.6" + process $proc$libresoc.v:35345$1517 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:34759.5-34759.29" + attribute \src "libresoc.v:35346.5-35346.29" switch \initial - attribute \src "libresoc.v:34759.9-34759.17" + attribute \src "libresoc.v:35346.9-35346.17" case 1'1 case end @@ -55059,13 +55918,13 @@ module \clz sync always update \cnt_2_10 $0\cnt_2_10[2:0] end - attribute \src "libresoc.v:34778.3-34792.6" - process $proc$libresoc.v:34778$1486 + attribute \src "libresoc.v:35365.3-35379.6" + process $proc$libresoc.v:35365$1518 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:34779.5-34779.29" + attribute \src "libresoc.v:35366.5-35366.29" switch \initial - attribute \src "libresoc.v:34779.9-34779.17" + attribute \src "libresoc.v:35366.9-35366.17" case 1'1 case end @@ -55087,13 +55946,13 @@ module \clz sync always update \cnt_1_3 $0\cnt_1_3[1:0] end - attribute \src "libresoc.v:34793.3-34812.6" - process $proc$libresoc.v:34793$1487 + attribute \src "libresoc.v:35380.3-35399.6" + process $proc$libresoc.v:35380$1519 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:34794.5-34794.29" + attribute \src "libresoc.v:35381.5-35381.29" switch \initial - attribute \src "libresoc.v:34794.9-34794.17" + attribute \src "libresoc.v:35381.9-35381.17" case 1'1 case end @@ -55122,13 +55981,13 @@ module \clz sync always update \cnt_2_12 $0\cnt_2_12[2:0] end - attribute \src "libresoc.v:34813.3-34832.6" - process $proc$libresoc.v:34813$1488 + attribute \src "libresoc.v:35400.3-35419.6" + process $proc$libresoc.v:35400$1520 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:34814.5-34814.29" + attribute \src "libresoc.v:35401.5-35401.29" switch \initial - attribute \src "libresoc.v:34814.9-34814.17" + attribute \src "libresoc.v:35401.9-35401.17" case 1'1 case end @@ -55157,13 +56016,13 @@ module \clz sync always update \cnt_2_14 $0\cnt_2_14[2:0] end - attribute \src "libresoc.v:34833.3-34852.6" - process $proc$libresoc.v:34833$1489 + attribute \src "libresoc.v:35420.3-35439.6" + process $proc$libresoc.v:35420$1521 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:34834.5-34834.29" + attribute \src "libresoc.v:35421.5-35421.29" switch \initial - attribute \src "libresoc.v:34834.9-34834.17" + attribute \src "libresoc.v:35421.9-35421.17" case 1'1 case end @@ -55192,13 +56051,13 @@ module \clz sync always update \cnt_2_16 $0\cnt_2_16[2:0] end - attribute \src "libresoc.v:34853.3-34872.6" - process $proc$libresoc.v:34853$1490 + attribute \src "libresoc.v:35440.3-35459.6" + process $proc$libresoc.v:35440$1522 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:34854.5-34854.29" + attribute \src "libresoc.v:35441.5-35441.29" switch \initial - attribute \src "libresoc.v:34854.9-34854.17" + attribute \src "libresoc.v:35441.9-35441.17" case 1'1 case end @@ -55227,13 +56086,13 @@ module \clz sync always update \cnt_2_18 $0\cnt_2_18[2:0] end - attribute \src "libresoc.v:34873.3-34892.6" - process $proc$libresoc.v:34873$1491 + attribute \src "libresoc.v:35460.3-35479.6" + process $proc$libresoc.v:35460$1523 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:34874.5-34874.29" + attribute \src "libresoc.v:35461.5-35461.29" switch \initial - attribute \src "libresoc.v:34874.9-34874.17" + attribute \src "libresoc.v:35461.9-35461.17" case 1'1 case end @@ -55262,13 +56121,13 @@ module \clz sync always update \cnt_2_20 $0\cnt_2_20[2:0] end - attribute \src "libresoc.v:34893.3-34912.6" - process $proc$libresoc.v:34893$1492 + attribute \src "libresoc.v:35480.3-35499.6" + process $proc$libresoc.v:35480$1524 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:34894.5-34894.29" + attribute \src "libresoc.v:35481.5-35481.29" switch \initial - attribute \src "libresoc.v:34894.9-34894.17" + attribute \src "libresoc.v:35481.9-35481.17" case 1'1 case end @@ -55297,13 +56156,13 @@ module \clz sync always update \cnt_2_22 $0\cnt_2_22[2:0] end - attribute \src "libresoc.v:34913.3-34932.6" - process $proc$libresoc.v:34913$1493 + attribute \src "libresoc.v:35500.3-35519.6" + process $proc$libresoc.v:35500$1525 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:34914.5-34914.29" + attribute \src "libresoc.v:35501.5-35501.29" switch \initial - attribute \src "libresoc.v:34914.9-34914.17" + attribute \src "libresoc.v:35501.9-35501.17" case 1'1 case end @@ -55332,13 +56191,13 @@ module \clz sync always update \cnt_2_24 $0\cnt_2_24[2:0] end - attribute \src "libresoc.v:34933.3-34952.6" - process $proc$libresoc.v:34933$1494 + attribute \src "libresoc.v:35520.3-35539.6" + process $proc$libresoc.v:35520$1526 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:34934.5-34934.29" + attribute \src "libresoc.v:35521.5-35521.29" switch \initial - attribute \src "libresoc.v:34934.9-34934.17" + attribute \src "libresoc.v:35521.9-35521.17" case 1'1 case end @@ -55367,13 +56226,13 @@ module \clz sync always update \cnt_2_26 $0\cnt_2_26[2:0] end - attribute \src "libresoc.v:34953.3-34972.6" - process $proc$libresoc.v:34953$1495 + attribute \src "libresoc.v:35540.3-35559.6" + process $proc$libresoc.v:35540$1527 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:34954.5-34954.29" + attribute \src "libresoc.v:35541.5-35541.29" switch \initial - attribute \src "libresoc.v:34954.9-34954.17" + attribute \src "libresoc.v:35541.9-35541.17" case 1'1 case end @@ -55402,13 +56261,13 @@ module \clz sync always update \cnt_2_28 $0\cnt_2_28[2:0] end - attribute \src "libresoc.v:34973.3-34992.6" - process $proc$libresoc.v:34973$1496 + attribute \src "libresoc.v:35560.3-35579.6" + process $proc$libresoc.v:35560$1528 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:34974.5-34974.29" + attribute \src "libresoc.v:35561.5-35561.29" switch \initial - attribute \src "libresoc.v:34974.9-34974.17" + attribute \src "libresoc.v:35561.9-35561.17" case 1'1 case end @@ -55437,13 +56296,13 @@ module \clz sync always update \cnt_2_30 $0\cnt_2_30[2:0] end - attribute \src "libresoc.v:34993.3-35012.6" - process $proc$libresoc.v:34993$1497 + attribute \src "libresoc.v:35580.3-35599.6" + process $proc$libresoc.v:35580$1529 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:34994.5-34994.29" + attribute \src "libresoc.v:35581.5-35581.29" switch \initial - attribute \src "libresoc.v:34994.9-34994.17" + attribute \src "libresoc.v:35581.9-35581.17" case 1'1 case end @@ -55472,13 +56331,13 @@ module \clz sync always update \cnt_3_0 $0\cnt_3_0[3:0] end - attribute \src "libresoc.v:35013.3-35032.6" - process $proc$libresoc.v:35013$1498 + attribute \src "libresoc.v:35600.3-35619.6" + process $proc$libresoc.v:35600$1530 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35014.5-35014.29" + attribute \src "libresoc.v:35601.5-35601.29" switch \initial - attribute \src "libresoc.v:35014.9-35014.17" + attribute \src "libresoc.v:35601.9-35601.17" case 1'1 case end @@ -55507,13 +56366,13 @@ module \clz sync always update \cnt_3_2 $0\cnt_3_2[3:0] end - attribute \src "libresoc.v:35033.3-35052.6" - process $proc$libresoc.v:35033$1499 + attribute \src "libresoc.v:35620.3-35639.6" + process $proc$libresoc.v:35620$1531 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35034.5-35034.29" + attribute \src "libresoc.v:35621.5-35621.29" switch \initial - attribute \src "libresoc.v:35034.9-35034.17" + attribute \src "libresoc.v:35621.9-35621.17" case 1'1 case end @@ -55542,13 +56401,13 @@ module \clz sync always update \cnt_3_4 $0\cnt_3_4[3:0] end - attribute \src "libresoc.v:35053.3-35072.6" - process $proc$libresoc.v:35053$1500 + attribute \src "libresoc.v:35640.3-35659.6" + process $proc$libresoc.v:35640$1532 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35054.5-35054.29" + attribute \src "libresoc.v:35641.5-35641.29" switch \initial - attribute \src "libresoc.v:35054.9-35054.17" + attribute \src "libresoc.v:35641.9-35641.17" case 1'1 case end @@ -55577,13 +56436,13 @@ module \clz sync always update \cnt_3_6 $0\cnt_3_6[3:0] end - attribute \src "libresoc.v:35073.3-35092.6" - process $proc$libresoc.v:35073$1501 + attribute \src "libresoc.v:35660.3-35679.6" + process $proc$libresoc.v:35660$1533 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35074.5-35074.29" + attribute \src "libresoc.v:35661.5-35661.29" switch \initial - attribute \src "libresoc.v:35074.9-35074.17" + attribute \src "libresoc.v:35661.9-35661.17" case 1'1 case end @@ -55612,13 +56471,13 @@ module \clz sync always update \cnt_3_8 $0\cnt_3_8[3:0] end - attribute \src "libresoc.v:35093.3-35112.6" - process $proc$libresoc.v:35093$1502 + attribute \src "libresoc.v:35680.3-35699.6" + process $proc$libresoc.v:35680$1534 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35094.5-35094.29" + attribute \src "libresoc.v:35681.5-35681.29" switch \initial - attribute \src "libresoc.v:35094.9-35094.17" + attribute \src "libresoc.v:35681.9-35681.17" case 1'1 case end @@ -55647,13 +56506,13 @@ module \clz sync always update \cnt_3_10 $0\cnt_3_10[3:0] end - attribute \src "libresoc.v:35113.3-35132.6" - process $proc$libresoc.v:35113$1503 + attribute \src "libresoc.v:35700.3-35719.6" + process $proc$libresoc.v:35700$1535 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35114.5-35114.29" + attribute \src "libresoc.v:35701.5-35701.29" switch \initial - attribute \src "libresoc.v:35114.9-35114.17" + attribute \src "libresoc.v:35701.9-35701.17" case 1'1 case end @@ -55682,13 +56541,13 @@ module \clz sync always update \cnt_3_12 $0\cnt_3_12[3:0] end - attribute \src "libresoc.v:35133.3-35152.6" - process $proc$libresoc.v:35133$1504 + attribute \src "libresoc.v:35720.3-35739.6" + process $proc$libresoc.v:35720$1536 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35134.5-35134.29" + attribute \src "libresoc.v:35721.5-35721.29" switch \initial - attribute \src "libresoc.v:35134.9-35134.17" + attribute \src "libresoc.v:35721.9-35721.17" case 1'1 case end @@ -55717,13 +56576,13 @@ module \clz sync always update \cnt_3_14 $0\cnt_3_14[3:0] end - attribute \src "libresoc.v:35153.3-35172.6" - process $proc$libresoc.v:35153$1505 + attribute \src "libresoc.v:35740.3-35759.6" + process $proc$libresoc.v:35740$1537 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35154.5-35154.29" + attribute \src "libresoc.v:35741.5-35741.29" switch \initial - attribute \src "libresoc.v:35154.9-35154.17" + attribute \src "libresoc.v:35741.9-35741.17" case 1'1 case end @@ -55752,13 +56611,13 @@ module \clz sync always update \cnt_4_0 $0\cnt_4_0[4:0] end - attribute \src "libresoc.v:35173.3-35192.6" - process $proc$libresoc.v:35173$1506 + attribute \src "libresoc.v:35760.3-35779.6" + process $proc$libresoc.v:35760$1538 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35174.5-35174.29" + attribute \src "libresoc.v:35761.5-35761.29" switch \initial - attribute \src "libresoc.v:35174.9-35174.17" + attribute \src "libresoc.v:35761.9-35761.17" case 1'1 case end @@ -55787,13 +56646,13 @@ module \clz sync always update \cnt_4_2 $0\cnt_4_2[4:0] end - attribute \src "libresoc.v:35193.3-35207.6" - process $proc$libresoc.v:35193$1507 + attribute \src "libresoc.v:35780.3-35794.6" + process $proc$libresoc.v:35780$1539 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35194.5-35194.29" + attribute \src "libresoc.v:35781.5-35781.29" switch \initial - attribute \src "libresoc.v:35194.9-35194.17" + attribute \src "libresoc.v:35781.9-35781.17" case 1'1 case end @@ -55815,13 +56674,13 @@ module \clz sync always update \cnt_1_4 $0\cnt_1_4[1:0] end - attribute \src "libresoc.v:35208.3-35227.6" - process $proc$libresoc.v:35208$1508 + attribute \src "libresoc.v:35795.3-35814.6" + process $proc$libresoc.v:35795$1540 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35209.5-35209.29" + attribute \src "libresoc.v:35796.5-35796.29" switch \initial - attribute \src "libresoc.v:35209.9-35209.17" + attribute \src "libresoc.v:35796.9-35796.17" case 1'1 case end @@ -55850,13 +56709,13 @@ module \clz sync always update \cnt_4_4 $0\cnt_4_4[4:0] end - attribute \src "libresoc.v:35228.3-35247.6" - process $proc$libresoc.v:35228$1509 + attribute \src "libresoc.v:35815.3-35834.6" + process $proc$libresoc.v:35815$1541 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35229.5-35229.29" + attribute \src "libresoc.v:35816.5-35816.29" switch \initial - attribute \src "libresoc.v:35229.9-35229.17" + attribute \src "libresoc.v:35816.9-35816.17" case 1'1 case end @@ -55885,13 +56744,13 @@ module \clz sync always update \cnt_4_6 $0\cnt_4_6[4:0] end - attribute \src "libresoc.v:35248.3-35267.6" - process $proc$libresoc.v:35248$1510 + attribute \src "libresoc.v:35835.3-35854.6" + process $proc$libresoc.v:35835$1542 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35249.5-35249.29" + attribute \src "libresoc.v:35836.5-35836.29" switch \initial - attribute \src "libresoc.v:35249.9-35249.17" + attribute \src "libresoc.v:35836.9-35836.17" case 1'1 case end @@ -55920,13 +56779,13 @@ module \clz sync always update \cnt_5_0 $0\cnt_5_0[5:0] end - attribute \src "libresoc.v:35268.3-35287.6" - process $proc$libresoc.v:35268$1511 + attribute \src "libresoc.v:35855.3-35874.6" + process $proc$libresoc.v:35855$1543 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35269.5-35269.29" + attribute \src "libresoc.v:35856.5-35856.29" switch \initial - attribute \src "libresoc.v:35269.9-35269.17" + attribute \src "libresoc.v:35856.9-35856.17" case 1'1 case end @@ -55955,13 +56814,13 @@ module \clz sync always update \cnt_5_2 $0\cnt_5_2[5:0] end - attribute \src "libresoc.v:35288.3-35307.6" - process $proc$libresoc.v:35288$1512 + attribute \src "libresoc.v:35875.3-35894.6" + process $proc$libresoc.v:35875$1544 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35289.5-35289.29" + attribute \src "libresoc.v:35876.5-35876.29" switch \initial - attribute \src "libresoc.v:35289.9-35289.17" + attribute \src "libresoc.v:35876.9-35876.17" case 1'1 case end @@ -55990,99 +56849,99 @@ module \clz sync always update \cnt_6_0 $0\cnt_6_0[6:0] end - connect \$9 $eq$libresoc.v:34115$1357_Y - connect \$99 $eq$libresoc.v:34116$1358_Y - connect \$101 $pos$libresoc.v:34117$1359_Y - connect \$103 $eq$libresoc.v:34118$1360_Y - connect \$105 $eq$libresoc.v:34119$1361_Y - connect \$107 $pos$libresoc.v:34120$1362_Y - connect \$109 $eq$libresoc.v:34121$1363_Y - connect \$111 $eq$libresoc.v:34122$1364_Y - connect \$113 $pos$libresoc.v:34123$1365_Y - connect \$115 $eq$libresoc.v:34124$1366_Y - connect \$117 $eq$libresoc.v:34125$1367_Y - connect \$11 $pos$libresoc.v:34126$1368_Y - connect \$119 $pos$libresoc.v:34127$1369_Y - connect \$121 $eq$libresoc.v:34128$1370_Y - connect \$123 $eq$libresoc.v:34129$1371_Y - connect \$125 $pos$libresoc.v:34130$1372_Y - connect \$127 $eq$libresoc.v:34131$1373_Y - connect \$129 $eq$libresoc.v:34132$1374_Y - connect \$131 $pos$libresoc.v:34133$1375_Y - connect \$133 $eq$libresoc.v:34134$1376_Y - connect \$135 $eq$libresoc.v:34135$1377_Y - connect \$137 $pos$libresoc.v:34136$1378_Y - connect \$13 $eq$libresoc.v:34137$1379_Y - connect \$139 $eq$libresoc.v:34138$1380_Y - connect \$141 $eq$libresoc.v:34139$1381_Y - connect \$143 $pos$libresoc.v:34140$1382_Y - connect \$145 $eq$libresoc.v:34141$1383_Y - connect \$147 $eq$libresoc.v:34142$1384_Y - connect \$149 $pos$libresoc.v:34143$1385_Y - connect \$151 $eq$libresoc.v:34144$1386_Y - connect \$153 $eq$libresoc.v:34145$1387_Y - connect \$155 $pos$libresoc.v:34146$1388_Y - connect \$157 $eq$libresoc.v:34147$1389_Y - connect \$15 $eq$libresoc.v:34148$1390_Y - connect \$159 $eq$libresoc.v:34149$1391_Y - connect \$161 $pos$libresoc.v:34150$1392_Y - connect \$163 $eq$libresoc.v:34151$1393_Y - connect \$165 $eq$libresoc.v:34152$1394_Y - connect \$167 $pos$libresoc.v:34153$1395_Y - connect \$169 $eq$libresoc.v:34154$1396_Y - connect \$171 $eq$libresoc.v:34155$1397_Y - connect \$173 $pos$libresoc.v:34156$1398_Y - connect \$175 $eq$libresoc.v:34157$1399_Y - connect \$177 $eq$libresoc.v:34158$1400_Y - connect \$17 $pos$libresoc.v:34159$1401_Y - connect \$179 $pos$libresoc.v:34160$1402_Y - connect \$181 $eq$libresoc.v:34161$1403_Y - connect \$183 $eq$libresoc.v:34162$1404_Y - connect \$185 $pos$libresoc.v:34163$1405_Y - connect \$1 $eq$libresoc.v:34164$1406_Y - connect \$19 $eq$libresoc.v:34165$1407_Y - connect \$21 $eq$libresoc.v:34166$1408_Y - connect \$23 $pos$libresoc.v:34167$1409_Y - connect \$25 $eq$libresoc.v:34168$1410_Y - connect \$27 $eq$libresoc.v:34169$1411_Y - connect \$29 $pos$libresoc.v:34170$1412_Y - connect \$31 $eq$libresoc.v:34171$1413_Y - connect \$33 $eq$libresoc.v:34172$1414_Y - connect \$35 $pos$libresoc.v:34173$1415_Y - connect \$37 $eq$libresoc.v:34174$1416_Y - connect \$3 $eq$libresoc.v:34175$1417_Y - connect \$39 $eq$libresoc.v:34176$1418_Y - connect \$41 $pos$libresoc.v:34177$1419_Y - connect \$43 $eq$libresoc.v:34178$1420_Y - connect \$45 $eq$libresoc.v:34179$1421_Y - connect \$47 $pos$libresoc.v:34180$1422_Y - connect \$49 $eq$libresoc.v:34181$1423_Y - connect \$51 $eq$libresoc.v:34182$1424_Y - connect \$53 $pos$libresoc.v:34183$1425_Y - connect \$55 $eq$libresoc.v:34184$1426_Y - connect \$57 $eq$libresoc.v:34185$1427_Y - connect \$5 $pos$libresoc.v:34186$1428_Y - connect \$59 $pos$libresoc.v:34187$1429_Y - connect \$61 $eq$libresoc.v:34188$1430_Y - connect \$63 $eq$libresoc.v:34189$1431_Y - connect \$65 $pos$libresoc.v:34190$1432_Y - connect \$67 $eq$libresoc.v:34191$1433_Y - connect \$69 $eq$libresoc.v:34192$1434_Y - connect \$71 $pos$libresoc.v:34193$1435_Y - connect \$73 $eq$libresoc.v:34194$1436_Y - connect \$75 $eq$libresoc.v:34195$1437_Y - connect \$77 $pos$libresoc.v:34196$1438_Y - connect \$7 $eq$libresoc.v:34197$1439_Y - connect \$79 $eq$libresoc.v:34198$1440_Y - connect \$81 $eq$libresoc.v:34199$1441_Y - connect \$83 $pos$libresoc.v:34200$1442_Y - connect \$85 $eq$libresoc.v:34201$1443_Y - connect \$87 $eq$libresoc.v:34202$1444_Y - connect \$89 $pos$libresoc.v:34203$1445_Y - connect \$91 $eq$libresoc.v:34204$1446_Y - connect \$93 $eq$libresoc.v:34205$1447_Y - connect \$95 $pos$libresoc.v:34206$1448_Y - connect \$97 $eq$libresoc.v:34207$1449_Y + connect \$9 $eq$libresoc.v:34702$1389_Y + connect \$99 $eq$libresoc.v:34703$1390_Y + connect \$101 $pos$libresoc.v:34704$1391_Y + connect \$103 $eq$libresoc.v:34705$1392_Y + connect \$105 $eq$libresoc.v:34706$1393_Y + connect \$107 $pos$libresoc.v:34707$1394_Y + connect \$109 $eq$libresoc.v:34708$1395_Y + connect \$111 $eq$libresoc.v:34709$1396_Y + connect \$113 $pos$libresoc.v:34710$1397_Y + connect \$115 $eq$libresoc.v:34711$1398_Y + connect \$117 $eq$libresoc.v:34712$1399_Y + connect \$11 $pos$libresoc.v:34713$1400_Y + connect \$119 $pos$libresoc.v:34714$1401_Y + connect \$121 $eq$libresoc.v:34715$1402_Y + connect \$123 $eq$libresoc.v:34716$1403_Y + connect \$125 $pos$libresoc.v:34717$1404_Y + connect \$127 $eq$libresoc.v:34718$1405_Y + connect \$129 $eq$libresoc.v:34719$1406_Y + connect \$131 $pos$libresoc.v:34720$1407_Y + connect \$133 $eq$libresoc.v:34721$1408_Y + connect \$135 $eq$libresoc.v:34722$1409_Y + connect \$137 $pos$libresoc.v:34723$1410_Y + connect \$13 $eq$libresoc.v:34724$1411_Y + connect \$139 $eq$libresoc.v:34725$1412_Y + connect \$141 $eq$libresoc.v:34726$1413_Y + connect \$143 $pos$libresoc.v:34727$1414_Y + connect \$145 $eq$libresoc.v:34728$1415_Y + connect \$147 $eq$libresoc.v:34729$1416_Y + connect \$149 $pos$libresoc.v:34730$1417_Y + connect \$151 $eq$libresoc.v:34731$1418_Y + connect \$153 $eq$libresoc.v:34732$1419_Y + connect \$155 $pos$libresoc.v:34733$1420_Y + connect \$157 $eq$libresoc.v:34734$1421_Y + connect \$15 $eq$libresoc.v:34735$1422_Y + connect \$159 $eq$libresoc.v:34736$1423_Y + connect \$161 $pos$libresoc.v:34737$1424_Y + connect \$163 $eq$libresoc.v:34738$1425_Y + connect \$165 $eq$libresoc.v:34739$1426_Y + connect \$167 $pos$libresoc.v:34740$1427_Y + connect \$169 $eq$libresoc.v:34741$1428_Y + connect \$171 $eq$libresoc.v:34742$1429_Y + connect \$173 $pos$libresoc.v:34743$1430_Y + connect \$175 $eq$libresoc.v:34744$1431_Y + connect \$177 $eq$libresoc.v:34745$1432_Y + connect \$17 $pos$libresoc.v:34746$1433_Y + connect \$179 $pos$libresoc.v:34747$1434_Y + connect \$181 $eq$libresoc.v:34748$1435_Y + connect \$183 $eq$libresoc.v:34749$1436_Y + connect \$185 $pos$libresoc.v:34750$1437_Y + connect \$1 $eq$libresoc.v:34751$1438_Y + connect \$19 $eq$libresoc.v:34752$1439_Y + connect \$21 $eq$libresoc.v:34753$1440_Y + connect \$23 $pos$libresoc.v:34754$1441_Y + connect \$25 $eq$libresoc.v:34755$1442_Y + connect \$27 $eq$libresoc.v:34756$1443_Y + connect \$29 $pos$libresoc.v:34757$1444_Y + connect \$31 $eq$libresoc.v:34758$1445_Y + connect \$33 $eq$libresoc.v:34759$1446_Y + connect \$35 $pos$libresoc.v:34760$1447_Y + connect \$37 $eq$libresoc.v:34761$1448_Y + connect \$3 $eq$libresoc.v:34762$1449_Y + connect \$39 $eq$libresoc.v:34763$1450_Y + connect \$41 $pos$libresoc.v:34764$1451_Y + connect \$43 $eq$libresoc.v:34765$1452_Y + connect \$45 $eq$libresoc.v:34766$1453_Y + connect \$47 $pos$libresoc.v:34767$1454_Y + connect \$49 $eq$libresoc.v:34768$1455_Y + connect \$51 $eq$libresoc.v:34769$1456_Y + connect \$53 $pos$libresoc.v:34770$1457_Y + connect \$55 $eq$libresoc.v:34771$1458_Y + connect \$57 $eq$libresoc.v:34772$1459_Y + connect \$5 $pos$libresoc.v:34773$1460_Y + connect \$59 $pos$libresoc.v:34774$1461_Y + connect \$61 $eq$libresoc.v:34775$1462_Y + connect \$63 $eq$libresoc.v:34776$1463_Y + connect \$65 $pos$libresoc.v:34777$1464_Y + connect \$67 $eq$libresoc.v:34778$1465_Y + connect \$69 $eq$libresoc.v:34779$1466_Y + connect \$71 $pos$libresoc.v:34780$1467_Y + connect \$73 $eq$libresoc.v:34781$1468_Y + connect \$75 $eq$libresoc.v:34782$1469_Y + connect \$77 $pos$libresoc.v:34783$1470_Y + connect \$7 $eq$libresoc.v:34784$1471_Y + connect \$79 $eq$libresoc.v:34785$1472_Y + connect \$81 $eq$libresoc.v:34786$1473_Y + connect \$83 $pos$libresoc.v:34787$1474_Y + connect \$85 $eq$libresoc.v:34788$1475_Y + connect \$87 $eq$libresoc.v:34789$1476_Y + connect \$89 $pos$libresoc.v:34790$1477_Y + connect \$91 $eq$libresoc.v:34791$1478_Y + connect \$93 $eq$libresoc.v:34792$1479_Y + connect \$95 $pos$libresoc.v:34793$1480_Y + connect \$97 $eq$libresoc.v:34794$1481_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] @@ -56117,4163 +56976,4171 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:35345.1-48039.10" +attribute \src "libresoc.v:35932.1-48737.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core" +attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:45017.3-45037.6" - wire $0\core_terminate_o$next[0:0]$2597 - attribute \src "libresoc.v:41976.3-41977.49" + attribute \src "libresoc.v:45707.3-45727.6" + wire $0\core_terminate_o$next[0:0]$2628 + attribute \src "libresoc.v:42599.3-42600.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:44833.3-44859.6" - wire width 2 $0\counter$next[1:0]$2571 - attribute \src "libresoc.v:41978.3-41979.31" + attribute \src "libresoc.v:45532.3-45558.6" + wire width 2 $0\counter$next[1:0]$2605 + attribute \src "libresoc.v:42601.3-42602.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:45318.3-45326.6" - wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 - attribute \src "libresoc.v:41912.3-41913.57" + attribute \src "libresoc.v:46017.3-46025.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 + attribute \src "libresoc.v:42535.3-42536.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45299.3-45307.6" - wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 - attribute \src "libresoc.v:41914.3-41915.49" + attribute \src "libresoc.v:45998.3-46006.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 + attribute \src "libresoc.v:42537.3-42538.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:45337.3-45345.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 - attribute \src "libresoc.v:41910.3-41911.49" + attribute \src "libresoc.v:46036.3-46044.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 + attribute \src "libresoc.v:42533.3-42534.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:45386.3-45394.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 - attribute \src "libresoc.v:41908.3-41909.49" + attribute \src "libresoc.v:46085.3-46093.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 + attribute \src "libresoc.v:42531.3-42532.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45250.3-45258.6" - wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 - attribute \src "libresoc.v:41916.3-41917.55" + attribute \src "libresoc.v:45949.3-45957.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 + attribute \src "libresoc.v:42539.3-42540.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:45405.3-45413.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 - attribute \src "libresoc.v:41906.3-41907.63" + attribute \src "libresoc.v:46104.3-46112.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 + attribute \src "libresoc.v:42529.3-42530.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:45472.3-45480.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 - attribute \src "libresoc.v:41902.3-41903.57" + attribute \src "libresoc.v:46171.3-46179.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 + attribute \src "libresoc.v:42525.3-42526.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:45424.3-45432.6" - wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 - attribute \src "libresoc.v:41904.3-41905.59" + attribute \src "libresoc.v:46123.3-46131.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 + attribute \src "libresoc.v:42527.3-42528.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:45491.3-45499.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 - attribute \src "libresoc.v:41900.3-41901.63" + attribute \src "libresoc.v:46219.3-46227.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 + attribute \src "libresoc.v:42523.3-42524.63" wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:45539.3-45547.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 - attribute \src "libresoc.v:41898.3-41899.59" + attribute \src "libresoc.v:46238.3-46246.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 + attribute \src "libresoc.v:42521.3-42522.59" wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:44472.3-44480.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2463 - attribute \src "libresoc.v:41974.3-41975.49" + attribute \src "libresoc.v:45171.3-45179.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2497 + attribute \src "libresoc.v:42597.3-42598.49" wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:44491.3-44499.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2467 - attribute \src "libresoc.v:41972.3-41973.47" + attribute \src "libresoc.v:45190.3-45198.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2501 + attribute \src "libresoc.v:42595.3-42596.47" wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:44567.3-44575.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2491 - attribute \src "libresoc.v:41964.3-41965.49" + attribute \src "libresoc.v:45266.3-45274.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2525 + attribute \src "libresoc.v:42587.3-42588.49" wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:44624.3-44632.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2509 - attribute \src "libresoc.v:41958.3-41959.51" + attribute \src "libresoc.v:45323.3-45331.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2543 + attribute \src "libresoc.v:42581.3-42582.51" wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:44529.3-44537.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2479 - attribute \src "libresoc.v:41968.3-41969.57" + attribute \src "libresoc.v:45228.3-45236.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2513 + attribute \src "libresoc.v:42591.3-42592.57" wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:44586.3-44594.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2497 - attribute \src "libresoc.v:41962.3-41963.49" + attribute \src "libresoc.v:45285.3-45293.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2531 + attribute \src "libresoc.v:42585.3-42586.49" wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:44605.3-44613.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 - attribute \src "libresoc.v:41960.3-41961.59" + attribute \src "libresoc.v:45304.3-45312.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 + attribute \src "libresoc.v:42583.3-42584.59" wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:44548.3-44556.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2485 - attribute \src "libresoc.v:41966.3-41967.49" + attribute \src "libresoc.v:45247.3-45255.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2519 + attribute \src "libresoc.v:42589.3-42590.49" wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:44510.3-44518.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2473 - attribute \src "libresoc.v:41970.3-41971.51" + attribute \src "libresoc.v:45209.3-45217.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2507 + attribute \src "libresoc.v:42593.3-42594.51" wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:44643.3-44651.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2515 - attribute \src "libresoc.v:41956.3-41957.49" + attribute \src "libresoc.v:45342.3-45350.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2549 + attribute \src "libresoc.v:42579.3-42580.49" wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:44662.3-44670.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2519 - attribute \src "libresoc.v:41954.3-41955.47" + attribute \src "libresoc.v:45361.3-45369.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2553 + attribute \src "libresoc.v:42577.3-42578.47" wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:44719.3-44727.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2537 - attribute \src "libresoc.v:41948.3-41949.49" + attribute \src "libresoc.v:45418.3-45426.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2571 + attribute \src "libresoc.v:42571.3-42572.49" wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:44776.3-44784.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2555 - attribute \src "libresoc.v:41942.3-41943.51" + attribute \src "libresoc.v:45475.3-45483.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2589 + attribute \src "libresoc.v:42565.3-42566.51" wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:44700.3-44708.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2531 - attribute \src "libresoc.v:41950.3-41951.57" + attribute \src "libresoc.v:45399.3-45407.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2565 + attribute \src "libresoc.v:42573.3-42574.57" wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:44738.3-44746.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2543 - attribute \src "libresoc.v:41946.3-41947.49" + attribute \src "libresoc.v:45437.3-45445.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2577 + attribute \src "libresoc.v:42569.3-42570.49" wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:44757.3-44765.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 - attribute \src "libresoc.v:41944.3-41945.59" + attribute \src "libresoc.v:45456.3-45464.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 + attribute \src "libresoc.v:42567.3-42568.59" wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:44681.3-44689.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2525 - attribute \src "libresoc.v:41952.3-41953.51" + attribute \src "libresoc.v:45380.3-45388.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2559 + attribute \src "libresoc.v:42575.3-42576.51" wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:44814.3-44822.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2565 - attribute \src "libresoc.v:41938.3-41939.51" + attribute \src "libresoc.v:45513.3-45521.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2599 + attribute \src "libresoc.v:42561.3-42562.51" wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:44795.3-44803.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 - attribute \src "libresoc.v:41940.3-41941.59" + attribute \src "libresoc.v:45494.3-45502.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 + attribute \src "libresoc.v:42563.3-42564.59" wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:45587.3-45595.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 - attribute \src "libresoc.v:41896.3-41897.53" + attribute \src "libresoc.v:46286.3-46294.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 + attribute \src "libresoc.v:42519.3-42520.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45115.3-45123.6" - wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 - attribute \src "libresoc.v:41924.3-41925.57" + attribute \src "libresoc.v:45814.3-45822.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 + attribute \src "libresoc.v:42547.3-42548.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45182.3-45190.6" - wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 - attribute \src "libresoc.v:41920.3-41921.67" + attribute \src "libresoc.v:45881.3-45889.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 + attribute \src "libresoc.v:42543.3-42544.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45163.3-45171.6" - wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 - attribute \src "libresoc.v:41922.3-41923.57" + attribute \src "libresoc.v:45862.3-45870.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 + attribute \src "libresoc.v:42545.3-42546.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45231.3-45239.6" - wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 - attribute \src "libresoc.v:41918.3-41919.57" + attribute \src "libresoc.v:45930.3-45938.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 + attribute \src "libresoc.v:42541.3-42542.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:44860.3-44868.6" - wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 - attribute \src "libresoc.v:41936.3-41937.57" + attribute \src "libresoc.v:45559.3-45567.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 + attribute \src "libresoc.v:42559.3-42560.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45008.3-45016.6" - wire $0\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:41930.3-41931.57" + attribute \src "libresoc.v:45728.3-45736.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2633 + attribute \src "libresoc.v:42553.3-42554.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:44879.3-44887.6" - wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 - attribute \src "libresoc.v:41934.3-41935.65" + attribute \src "libresoc.v:45669.3-45677.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 + attribute \src "libresoc.v:42557.3-42558.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45048.3-45056.6" - wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:41928.3-41929.57" + attribute \src "libresoc.v:45747.3-45755.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 + attribute \src "libresoc.v:42551.3-42552.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45067.3-45075.6" - wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:41926.3-41927.67" + attribute \src "libresoc.v:45795.3-45803.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 + attribute \src "libresoc.v:42549.3-42550.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:44989.3-44997.6" - wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 - attribute \src "libresoc.v:41932.3-41933.57" + attribute \src "libresoc.v:45688.3-45696.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 + attribute \src "libresoc.v:42555.3-42556.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46839.3-46867.6" - wire $0\fus_cu_issue_i$10[0:0]$2869 - attribute \src "libresoc.v:47335.3-47363.6" - wire $0\fus_cu_issue_i$13[0:0]$2894 - attribute \src "libresoc.v:42720.3-42748.6" - wire $0\fus_cu_issue_i$16[0:0]$2363 - attribute \src "libresoc.v:43216.3-43244.6" - wire $0\fus_cu_issue_i$19[0:0]$2388 - attribute \src "libresoc.v:43538.3-43566.6" - wire $0\fus_cu_issue_i$22[0:0]$2407 - attribute \src "libresoc.v:43976.3-44004.6" - wire $0\fus_cu_issue_i$25[0:0]$2430 - attribute \src "libresoc.v:44414.3-44442.6" - wire $0\fus_cu_issue_i$28[0:0]$2453 - attribute \src "libresoc.v:46107.3-46135.6" - wire $0\fus_cu_issue_i$4[0:0]$2774 - attribute \src "libresoc.v:46504.3-46532.6" - wire $0\fus_cu_issue_i$7[0:0]$2836 - attribute \src "libresoc.v:45899.3-45927.6" + attribute \src "libresoc.v:46806.3-46834.6" + wire $0\fus_cu_issue_i$11[0:0]$2808 + attribute \src "libresoc.v:47203.3-47231.6" + wire $0\fus_cu_issue_i$14[0:0]$2870 + attribute \src "libresoc.v:47567.3-47595.6" + wire $0\fus_cu_issue_i$17[0:0]$2904 + attribute \src "libresoc.v:48063.3-48091.6" + wire $0\fus_cu_issue_i$20[0:0]$2929 + attribute \src "libresoc.v:43390.3-43418.6" + wire $0\fus_cu_issue_i$23[0:0]$2396 + attribute \src "libresoc.v:43886.3-43914.6" + wire $0\fus_cu_issue_i$26[0:0]$2421 + attribute \src "libresoc.v:44208.3-44236.6" + wire $0\fus_cu_issue_i$29[0:0]$2440 + attribute \src "libresoc.v:44675.3-44703.6" + wire $0\fus_cu_issue_i$32[0:0]$2464 + attribute \src "libresoc.v:45113.3-45141.6" + wire $0\fus_cu_issue_i$35[0:0]$2487 + attribute \src "libresoc.v:46598.3-46626.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46868.3-46896.6" - wire width 4 $0\fus_cu_rdmaskn_i$12[3:0]$2874 - attribute \src "libresoc.v:47364.3-47392.6" - wire width 3 $0\fus_cu_rdmaskn_i$15[2:0]$2899 - attribute \src "libresoc.v:42749.3-42777.6" - wire width 6 $0\fus_cu_rdmaskn_i$18[5:0]$2368 - attribute \src "libresoc.v:43245.3-43273.6" - wire width 3 $0\fus_cu_rdmaskn_i$21[2:0]$2393 - attribute \src "libresoc.v:43567.3-43595.6" - wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2412 - attribute \src "libresoc.v:44005.3-44033.6" - wire width 5 $0\fus_cu_rdmaskn_i$27[4:0]$2435 - attribute \src "libresoc.v:44443.3-44471.6" - wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2458 - attribute \src "libresoc.v:46154.3-46182.6" - wire width 6 $0\fus_cu_rdmaskn_i$6[5:0]$2785 - attribute \src "libresoc.v:46542.3-46570.6" - wire width 3 $0\fus_cu_rdmaskn_i$9[2:0]$2844 - attribute \src "libresoc.v:45937.3-45965.6" + attribute \src "libresoc.v:46844.3-46872.6" + wire width 6 $0\fus_cu_rdmaskn_i$13[5:0]$2816 + attribute \src "libresoc.v:47241.3-47269.6" + wire width 3 $0\fus_cu_rdmaskn_i$16[2:0]$2878 + attribute \src "libresoc.v:47596.3-47624.6" + wire width 4 $0\fus_cu_rdmaskn_i$19[3:0]$2909 + attribute \src "libresoc.v:48092.3-48120.6" + wire width 3 $0\fus_cu_rdmaskn_i$22[2:0]$2934 + attribute \src "libresoc.v:43419.3-43447.6" + wire width 6 $0\fus_cu_rdmaskn_i$25[5:0]$2401 + attribute \src "libresoc.v:43915.3-43943.6" + wire width 3 $0\fus_cu_rdmaskn_i$28[2:0]$2426 + attribute \src "libresoc.v:44237.3-44265.6" + wire width 3 $0\fus_cu_rdmaskn_i$31[2:0]$2445 + attribute \src "libresoc.v:44704.3-44732.6" + wire width 5 $0\fus_cu_rdmaskn_i$34[4:0]$2469 + attribute \src "libresoc.v:45142.3-45170.6" + wire width 3 $0\fus_cu_rdmaskn_i$37[2:0]$2492 + attribute \src "libresoc.v:46636.3-46664.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:45814.3-45842.6" + attribute \src "libresoc.v:46513.3-46541.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45134.3-45162.6" + attribute \src "libresoc.v:45823.3-45851.6" wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45653.3-45681.6" + attribute \src "libresoc.v:46343.3-46371.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46560.3-46588.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45076.3-45104.6" + attribute \src "libresoc.v:45766.3-45794.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45443.3-45471.6" + attribute \src "libresoc.v:46142.3-46170.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45558.3-45586.6" + attribute \src "libresoc.v:46257.3-46285.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:45738.3-45766.6" + attribute \src "libresoc.v:46428.3-46456.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:45776.3-45804.6" + attribute \src "libresoc.v:46475.3-46503.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:46390.3-46418.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45606.3-45634.6" + attribute \src "libresoc.v:46305.3-46333.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:45500.3-45528.6" + attribute \src "libresoc.v:46190.3-46218.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46192.3-46220.6" + attribute \src "libresoc.v:46891.3-46919.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46277.3-46305.6" + attribute \src "libresoc.v:46976.3-47004.6" wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46315.3-46343.6" + attribute \src "libresoc.v:47014.3-47042.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46239.3-46267.6" + attribute \src "libresoc.v:46929.3-46957.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46457.3-46485.6" + attribute \src "libresoc.v:47156.3-47184.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46419.3-46447.6" + attribute \src "libresoc.v:47118.3-47146.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46022.3-46050.6" + attribute \src "libresoc.v:46721.3-46749.6" wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46069.3-46097.6" + attribute \src "libresoc.v:46768.3-46796.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:45984.3-46012.6" + attribute \src "libresoc.v:46674.3-46702.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43158.3-43186.6" + attribute \src "libresoc.v:43828.3-43856.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:42807.3-42835.6" + attribute \src "libresoc.v:43477.3-43505.6" wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:42984.3-43012.6" + attribute \src "libresoc.v:43654.3-43682.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43187.3-43215.6" + attribute \src "libresoc.v:43857.3-43885.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:42778.3-42806.6" + attribute \src "libresoc.v:43448.3-43476.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:42926.3-42954.6" + attribute \src "libresoc.v:43596.3-43624.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43013.3-43041.6" + attribute \src "libresoc.v:43683.3-43711.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43100.3-43128.6" + attribute \src "libresoc.v:43770.3-43798.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43129.3-43157.6" + attribute \src "libresoc.v:43799.3-43827.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43071.3-43099.6" + attribute \src "libresoc.v:43741.3-43769.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43042.3-43070.6" + attribute \src "libresoc.v:43712.3-43740.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:42955.3-42983.6" + attribute \src "libresoc.v:43625.3-43653.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47277.3-47305.6" + attribute \src "libresoc.v:48005.3-48033.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:46926.3-46954.6" + attribute \src "libresoc.v:47654.3-47682.6" wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47103.3-47131.6" + attribute \src "libresoc.v:47831.3-47859.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47306.3-47334.6" + attribute \src "libresoc.v:48034.3-48062.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:46897.3-46925.6" + attribute \src "libresoc.v:47625.3-47653.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47045.3-47073.6" + attribute \src "libresoc.v:47773.3-47801.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47132.3-47160.6" + attribute \src "libresoc.v:47860.3-47888.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47219.3-47247.6" + attribute \src "libresoc.v:47947.3-47975.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47248.3-47276.6" + attribute \src "libresoc.v:47976.3-48004.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47190.3-47218.6" + attribute \src "libresoc.v:47918.3-47946.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47161.3-47189.6" + attribute \src "libresoc.v:47889.3-47917.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47074.3-47102.6" + attribute \src "libresoc.v:47802.3-47830.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43303.3-43331.6" + attribute \src "libresoc.v:43973.3-44001.6" wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43509.3-43537.6" + attribute \src "libresoc.v:44179.3-44207.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43274.3-43302.6" + attribute \src "libresoc.v:43944.3-43972.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43451.3-43479.6" + attribute \src "libresoc.v:44121.3-44149.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43480.3-43508.6" + attribute \src "libresoc.v:44150.3-44178.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43422.3-43450.6" + attribute \src "libresoc.v:44092.3-44120.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" + attribute \src "libresoc.v:44295.3-44323.6" wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:43773.3-43801.6" + attribute \src "libresoc.v:44472.3-44500.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:43831.3-43859.6" + attribute \src "libresoc.v:44530.3-44558.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:43947.3-43975.6" + attribute \src "libresoc.v:44646.3-44674.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:43596.3-43624.6" + attribute \src "libresoc.v:44266.3-44294.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:43889.3-43917.6" + attribute \src "libresoc.v:44443.3-44471.6" + wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44588.3-44616.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:43918.3-43946.6" + attribute \src "libresoc.v:44617.3-44645.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:43802.3-43830.6" + attribute \src "libresoc.v:44501.3-44529.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:43860.3-43888.6" + attribute \src "libresoc.v:44559.3-44587.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:43744.3-43772.6" + attribute \src "libresoc.v:44414.3-44442.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47422.3-47450.6" + attribute \src "libresoc.v:48150.3-48178.6" wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47451.3-47479.6" + attribute \src "libresoc.v:43332.3-43360.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:48121.3-48149.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:42691.3-42719.6" + attribute \src "libresoc.v:43361.3-43389.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:46723.3-46751.6" + attribute \src "libresoc.v:47422.3-47450.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:46627.3-46655.6" + attribute \src "libresoc.v:47326.3-47354.6" wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:46665.3-46693.6" + attribute \src "libresoc.v:47364.3-47392.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:46589.3-46617.6" + attribute \src "libresoc.v:47279.3-47307.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:46752.3-46780.6" + attribute \src "libresoc.v:47451.3-47479.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:47538.3-47566.6" + wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47393.3-47421.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:46810.3-46838.6" + attribute \src "libresoc.v:47509.3-47537.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:46781.3-46809.6" - wire width 7 $0\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "libresoc.v:44298.3-44326.6" + attribute \src "libresoc.v:47480.3-47508.6" + wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44997.3-45025.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44269.3-44297.6" + attribute \src "libresoc.v:44968.3-44996.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44063.3-44091.6" + attribute \src "libresoc.v:44762.3-44790.6" wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44385.3-44413.6" + attribute \src "libresoc.v:45084.3-45112.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44034.3-44062.6" + attribute \src "libresoc.v:44733.3-44761.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44211.3-44239.6" + attribute \src "libresoc.v:44910.3-44938.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44240.3-44268.6" + attribute \src "libresoc.v:44939.3-44967.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44356.3-44384.6" + attribute \src "libresoc.v:45055.3-45083.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44327.3-44355.6" + attribute \src "libresoc.v:45026.3-45054.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44122.3-44150.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44500.3-44509.6" - wire width 64 $0\fus_src1_i$33[63:0]$2470 - attribute \src "libresoc.v:44519.3-44528.6" - wire width 64 $0\fus_src1_i$36[63:0]$2476 - attribute \src "libresoc.v:44538.3-44547.6" - wire width 64 $0\fus_src1_i$39[63:0]$2482 - attribute \src "libresoc.v:44557.3-44566.6" - wire width 64 $0\fus_src1_i$42[63:0]$2488 - attribute \src "libresoc.v:44576.3-44585.6" - wire width 64 $0\fus_src1_i$45[63:0]$2494 - attribute \src "libresoc.v:44595.3-44604.6" - wire width 64 $0\fus_src1_i$48[63:0]$2500 - attribute \src "libresoc.v:44614.3-44623.6" - wire width 64 $0\fus_src1_i$51[63:0]$2506 - attribute \src "libresoc.v:44633.3-44642.6" - wire width 64 $0\fus_src1_i$54[63:0]$2512 - attribute \src "libresoc.v:45414.3-45423.6" - wire width 64 $0\fus_src1_i$77[63:0]$2675 - attribute \src "libresoc.v:44481.3-44490.6" + attribute \src "libresoc.v:45199.3-45208.6" + wire width 64 $0\fus_src1_i$40[63:0]$2504 + attribute \src "libresoc.v:45218.3-45227.6" + wire width 64 $0\fus_src1_i$43[63:0]$2510 + attribute \src "libresoc.v:45237.3-45246.6" + wire width 64 $0\fus_src1_i$46[63:0]$2516 + attribute \src "libresoc.v:45256.3-45265.6" + wire width 64 $0\fus_src1_i$49[63:0]$2522 + attribute \src "libresoc.v:45275.3-45284.6" + wire width 64 $0\fus_src1_i$52[63:0]$2528 + attribute \src "libresoc.v:45294.3-45303.6" + wire width 64 $0\fus_src1_i$55[63:0]$2534 + attribute \src "libresoc.v:45313.3-45322.6" + wire width 64 $0\fus_src1_i$58[63:0]$2540 + attribute \src "libresoc.v:45332.3-45341.6" + wire width 64 $0\fus_src1_i$61[63:0]$2546 + attribute \src "libresoc.v:46113.3-46122.6" + wire width 64 $0\fus_src1_i$84[63:0]$2709 + attribute \src "libresoc.v:45180.3-45189.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:44671.3-44680.6" - wire width 64 $0\fus_src2_i$55[63:0]$2522 - attribute \src "libresoc.v:44690.3-44699.6" - wire width 64 $0\fus_src2_i$56[63:0]$2528 - attribute \src "libresoc.v:44709.3-44718.6" - wire width 64 $0\fus_src2_i$57[63:0]$2534 - attribute \src "libresoc.v:44728.3-44737.6" - wire width 64 $0\fus_src2_i$58[63:0]$2540 - attribute \src "libresoc.v:44747.3-44756.6" - wire width 64 $0\fus_src2_i$59[63:0]$2546 - attribute \src "libresoc.v:44766.3-44775.6" - wire width 64 $0\fus_src2_i$60[63:0]$2552 - attribute \src "libresoc.v:44785.3-44794.6" - wire width 64 $0\fus_src2_i$61[63:0]$2558 - attribute \src "libresoc.v:45529.3-45538.6" - wire width 64 $0\fus_src2_i$80[63:0]$2695 - attribute \src "libresoc.v:45596.3-45605.6" - wire width 64 $0\fus_src2_i$82[63:0]$2708 - attribute \src "libresoc.v:44652.3-44661.6" + attribute \src "libresoc.v:45370.3-45379.6" + wire width 64 $0\fus_src2_i$62[63:0]$2556 + attribute \src "libresoc.v:45389.3-45398.6" + wire width 64 $0\fus_src2_i$63[63:0]$2562 + attribute \src "libresoc.v:45408.3-45417.6" + wire width 64 $0\fus_src2_i$64[63:0]$2568 + attribute \src "libresoc.v:45427.3-45436.6" + wire width 64 $0\fus_src2_i$65[63:0]$2574 + attribute \src "libresoc.v:45446.3-45455.6" + wire width 64 $0\fus_src2_i$66[63:0]$2580 + attribute \src "libresoc.v:45465.3-45474.6" + wire width 64 $0\fus_src2_i$67[63:0]$2586 + attribute \src "libresoc.v:45484.3-45493.6" + wire width 64 $0\fus_src2_i$68[63:0]$2592 + attribute \src "libresoc.v:46228.3-46237.6" + wire width 64 $0\fus_src2_i$87[63:0]$2729 + attribute \src "libresoc.v:46295.3-46304.6" + wire width 64 $0\fus_src2_i$89[63:0]$2742 + attribute \src "libresoc.v:45351.3-45360.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:44823.3-44832.6" - wire width 64 $0\fus_src3_i$62[63:0]$2568 - attribute \src "libresoc.v:44869.3-44878.6" - wire $0\fus_src3_i$63[0:0]$2580 - attribute \src "libresoc.v:44979.3-44988.6" - wire $0\fus_src3_i$64[0:0]$2587 - attribute \src "libresoc.v:45038.3-45047.6" - wire $0\fus_src3_i$65[0:0]$2602 - attribute \src "libresoc.v:45057.3-45066.6" - wire $0\fus_src3_i$66[0:0]$2608 - attribute \src "libresoc.v:45259.3-45268.6" - wire width 32 $0\fus_src3_i$70[31:0]$2643 - attribute \src "libresoc.v:45327.3-45336.6" - wire width 4 $0\fus_src3_i$74[3:0]$2656 - attribute \src "libresoc.v:45433.3-45442.6" - wire width 64 $0\fus_src3_i$78[63:0]$2681 - attribute \src "libresoc.v:45481.3-45490.6" - wire width 64 $0\fus_src3_i$79[63:0]$2688 - attribute \src "libresoc.v:44804.3-44813.6" + attribute \src "libresoc.v:45522.3-45531.6" + wire width 64 $0\fus_src3_i$69[63:0]$2602 + attribute \src "libresoc.v:45568.3-45577.6" + wire $0\fus_src3_i$70[0:0]$2614 + attribute \src "libresoc.v:45678.3-45687.6" + wire $0\fus_src3_i$71[0:0]$2621 + attribute \src "libresoc.v:45737.3-45746.6" + wire $0\fus_src3_i$72[0:0]$2636 + attribute \src "libresoc.v:45756.3-45765.6" + wire $0\fus_src3_i$73[0:0]$2642 + attribute \src "libresoc.v:45958.3-45967.6" + wire width 32 $0\fus_src3_i$77[31:0]$2677 + attribute \src "libresoc.v:46026.3-46035.6" + wire width 4 $0\fus_src3_i$81[3:0]$2690 + attribute \src "libresoc.v:46132.3-46141.6" + wire width 64 $0\fus_src3_i$85[63:0]$2715 + attribute \src "libresoc.v:46180.3-46189.6" + wire width 64 $0\fus_src3_i$86[63:0]$2722 + attribute \src "libresoc.v:45503.3-45512.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:45105.3-45114.6" - wire $0\fus_src4_i$67[0:0]$2615 - attribute \src "libresoc.v:45124.3-45133.6" - wire width 2 $0\fus_src4_i$68[1:0]$2621 - attribute \src "libresoc.v:45308.3-45317.6" - wire width 4 $0\fus_src4_i$71[3:0]$2650 - attribute \src "libresoc.v:45548.3-45557.6" - wire width 64 $0\fus_src4_i$81[63:0]$2701 - attribute \src "libresoc.v:44998.3-45007.6" + attribute \src "libresoc.v:45804.3-45813.6" + wire $0\fus_src4_i$74[0:0]$2649 + attribute \src "libresoc.v:45852.3-45861.6" + wire width 2 $0\fus_src4_i$75[1:0]$2656 + attribute \src "libresoc.v:46007.3-46016.6" + wire width 4 $0\fus_src4_i$78[3:0]$2684 + attribute \src "libresoc.v:46247.3-46256.6" + wire width 64 $0\fus_src4_i$88[63:0]$2735 + attribute \src "libresoc.v:45697.3-45706.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:45240.3-45249.6" - wire width 2 $0\fus_src5_i$69[1:0]$2637 - attribute \src "libresoc.v:45346.3-45355.6" - wire width 4 $0\fus_src5_i$75[3:0]$2662 - attribute \src "libresoc.v:45191.3-45200.6" + attribute \src "libresoc.v:45939.3-45948.6" + wire width 2 $0\fus_src5_i$76[1:0]$2671 + attribute \src "libresoc.v:46045.3-46054.6" + wire width 4 $0\fus_src5_i$82[3:0]$2696 + attribute \src "libresoc.v:45920.3-45929.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:45395.3-45404.6" - wire width 4 $0\fus_src6_i$76[3:0]$2669 - attribute \src "libresoc.v:45172.3-45181.6" + attribute \src "libresoc.v:46094.3-46103.6" + wire width 4 $0\fus_src6_i$83[3:0]$2703 + attribute \src "libresoc.v:45871.3-45880.6" wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:35346.7-35346.20" + attribute \src "libresoc.v:35933.7-35933.20" wire $0\initial[0:0] - attribute \src "libresoc.v:45720.3-45728.6" - wire $0\wr_pick_dly$1007$next[0:0]$2723 - attribute \src "libresoc.v:41888.3-41889.51" - wire $0\wr_pick_dly$1007[0:0]$2313 - attribute \src "libresoc.v:40720.7-40720.32" - wire $0\wr_pick_dly$1007[0:0]$2951 - attribute \src "libresoc.v:45729.3-45737.6" - wire $0\wr_pick_dly$1025$next[0:0]$2726 - attribute \src "libresoc.v:41886.3-41887.51" - wire $0\wr_pick_dly$1025[0:0]$2311 - attribute \src "libresoc.v:40724.7-40724.32" - wire $0\wr_pick_dly$1025[0:0]$2953 - attribute \src "libresoc.v:45767.3-45775.6" - wire $0\wr_pick_dly$1047$next[0:0]$2730 - attribute \src "libresoc.v:41884.3-41885.51" - wire $0\wr_pick_dly$1047[0:0]$2309 - attribute \src "libresoc.v:40728.7-40728.32" - wire $0\wr_pick_dly$1047[0:0]$2955 - attribute \src "libresoc.v:45805.3-45813.6" - wire $0\wr_pick_dly$1067$next[0:0]$2734 - attribute \src "libresoc.v:41882.3-41883.51" - wire $0\wr_pick_dly$1067[0:0]$2307 - attribute \src "libresoc.v:40732.7-40732.32" - wire $0\wr_pick_dly$1067[0:0]$2957 - attribute \src "libresoc.v:45843.3-45851.6" - wire $0\wr_pick_dly$1087$next[0:0]$2738 - attribute \src "libresoc.v:41880.3-41881.51" - wire $0\wr_pick_dly$1087[0:0]$2305 - attribute \src "libresoc.v:40736.7-40736.32" - wire $0\wr_pick_dly$1087[0:0]$2959 - attribute \src "libresoc.v:45852.3-45860.6" - wire $0\wr_pick_dly$1106$next[0:0]$2741 - attribute \src "libresoc.v:41878.3-41879.51" - wire $0\wr_pick_dly$1106[0:0]$2303 - attribute \src "libresoc.v:40740.7-40740.32" - wire $0\wr_pick_dly$1106[0:0]$2961 - attribute \src "libresoc.v:45890.3-45898.6" - wire $0\wr_pick_dly$1124$next[0:0]$2745 - attribute \src "libresoc.v:41876.3-41877.51" - wire $0\wr_pick_dly$1124[0:0]$2301 - attribute \src "libresoc.v:40744.7-40744.32" - wire $0\wr_pick_dly$1124[0:0]$2963 - attribute \src "libresoc.v:45928.3-45936.6" - wire $0\wr_pick_dly$1197$next[0:0]$2749 - attribute \src "libresoc.v:41874.3-41875.51" - wire $0\wr_pick_dly$1197[0:0]$2299 - attribute \src "libresoc.v:40748.7-40748.32" - wire $0\wr_pick_dly$1197[0:0]$2965 - attribute \src "libresoc.v:45966.3-45974.6" - wire $0\wr_pick_dly$1225$next[0:0]$2753 - attribute \src "libresoc.v:41872.3-41873.51" - wire $0\wr_pick_dly$1225[0:0]$2297 - attribute \src "libresoc.v:40752.7-40752.32" - wire $0\wr_pick_dly$1225[0:0]$2967 - attribute \src "libresoc.v:45975.3-45983.6" - wire $0\wr_pick_dly$1245$next[0:0]$2756 - attribute \src "libresoc.v:41870.3-41871.51" - wire $0\wr_pick_dly$1245[0:0]$2295 - attribute \src "libresoc.v:40756.7-40756.32" - wire $0\wr_pick_dly$1245[0:0]$2969 - attribute \src "libresoc.v:46013.3-46021.6" - wire $0\wr_pick_dly$1265$next[0:0]$2760 - attribute \src "libresoc.v:41868.3-41869.51" - wire $0\wr_pick_dly$1265[0:0]$2293 - attribute \src "libresoc.v:40760.7-40760.32" - wire $0\wr_pick_dly$1265[0:0]$2971 - attribute \src "libresoc.v:46051.3-46059.6" - wire $0\wr_pick_dly$1285$next[0:0]$2764 - attribute \src "libresoc.v:41866.3-41867.51" - wire $0\wr_pick_dly$1285[0:0]$2291 - attribute \src "libresoc.v:40764.7-40764.32" - wire $0\wr_pick_dly$1285[0:0]$2973 - attribute \src "libresoc.v:46060.3-46068.6" - wire $0\wr_pick_dly$1305$next[0:0]$2767 - attribute \src "libresoc.v:41864.3-41865.51" - wire $0\wr_pick_dly$1305[0:0]$2289 - attribute \src "libresoc.v:40768.7-40768.32" - wire $0\wr_pick_dly$1305[0:0]$2975 - attribute \src "libresoc.v:46098.3-46106.6" - wire $0\wr_pick_dly$1325$next[0:0]$2771 - attribute \src "libresoc.v:41862.3-41863.51" - wire $0\wr_pick_dly$1325[0:0]$2287 - attribute \src "libresoc.v:40772.7-40772.32" - wire $0\wr_pick_dly$1325[0:0]$2977 - attribute \src "libresoc.v:46136.3-46144.6" - wire $0\wr_pick_dly$1372$next[0:0]$2779 - attribute \src "libresoc.v:41860.3-41861.51" - wire $0\wr_pick_dly$1372[0:0]$2285 - attribute \src "libresoc.v:40776.7-40776.32" - wire $0\wr_pick_dly$1372[0:0]$2979 - attribute \src "libresoc.v:46145.3-46153.6" - wire $0\wr_pick_dly$1388$next[0:0]$2782 - attribute \src "libresoc.v:41858.3-41859.51" - wire $0\wr_pick_dly$1388[0:0]$2283 - attribute \src "libresoc.v:40780.7-40780.32" - wire $0\wr_pick_dly$1388[0:0]$2981 - attribute \src "libresoc.v:46183.3-46191.6" - wire $0\wr_pick_dly$1404$next[0:0]$2790 - attribute \src "libresoc.v:41856.3-41857.51" - wire $0\wr_pick_dly$1404[0:0]$2281 - attribute \src "libresoc.v:40784.7-40784.32" - wire $0\wr_pick_dly$1404[0:0]$2983 - attribute \src "libresoc.v:46221.3-46229.6" - wire $0\wr_pick_dly$1438$next[0:0]$2794 - attribute \src "libresoc.v:41854.3-41855.51" - wire $0\wr_pick_dly$1438[0:0]$2279 - attribute \src "libresoc.v:40788.7-40788.32" - wire $0\wr_pick_dly$1438[0:0]$2985 - attribute \src "libresoc.v:46230.3-46238.6" - wire $0\wr_pick_dly$1454$next[0:0]$2797 - attribute \src "libresoc.v:41852.3-41853.51" - wire $0\wr_pick_dly$1454[0:0]$2277 - attribute \src "libresoc.v:40792.7-40792.32" - wire $0\wr_pick_dly$1454[0:0]$2987 - attribute \src "libresoc.v:46268.3-46276.6" - wire $0\wr_pick_dly$1470$next[0:0]$2801 - attribute \src "libresoc.v:41850.3-41851.51" - wire $0\wr_pick_dly$1470[0:0]$2275 - attribute \src "libresoc.v:40796.7-40796.32" - wire $0\wr_pick_dly$1470[0:0]$2989 - attribute \src "libresoc.v:46306.3-46314.6" - wire $0\wr_pick_dly$1486$next[0:0]$2805 - attribute \src "libresoc.v:41848.3-41849.51" - wire $0\wr_pick_dly$1486[0:0]$2273 - attribute \src "libresoc.v:40800.7-40800.32" - wire $0\wr_pick_dly$1486[0:0]$2991 - attribute \src "libresoc.v:46344.3-46352.6" - wire $0\wr_pick_dly$1522$next[0:0]$2809 - attribute \src "libresoc.v:41846.3-41847.51" - wire $0\wr_pick_dly$1522[0:0]$2271 - attribute \src "libresoc.v:40804.7-40804.32" - wire $0\wr_pick_dly$1522[0:0]$2993 - attribute \src "libresoc.v:46353.3-46361.6" - wire $0\wr_pick_dly$1538$next[0:0]$2812 - attribute \src "libresoc.v:41844.3-41845.51" - wire $0\wr_pick_dly$1538[0:0]$2269 - attribute \src "libresoc.v:40808.7-40808.32" - wire $0\wr_pick_dly$1538[0:0]$2995 - attribute \src "libresoc.v:46392.3-46400.6" - wire $0\wr_pick_dly$1554$next[0:0]$2816 - attribute \src "libresoc.v:41842.3-41843.51" - wire $0\wr_pick_dly$1554[0:0]$2267 - attribute \src "libresoc.v:40812.7-40812.32" - wire $0\wr_pick_dly$1554[0:0]$2997 - attribute \src "libresoc.v:46401.3-46409.6" - wire $0\wr_pick_dly$1570$next[0:0]$2819 - attribute \src "libresoc.v:41840.3-41841.51" - wire $0\wr_pick_dly$1570[0:0]$2265 - attribute \src "libresoc.v:40816.7-40816.32" - wire $0\wr_pick_dly$1570[0:0]$2999 - attribute \src "libresoc.v:46410.3-46418.6" - wire $0\wr_pick_dly$1612$next[0:0]$2822 - attribute \src "libresoc.v:41838.3-41839.51" - wire $0\wr_pick_dly$1612[0:0]$2263 - attribute \src "libresoc.v:40820.7-40820.32" - wire $0\wr_pick_dly$1612[0:0]$3001 - attribute \src "libresoc.v:46448.3-46456.6" - wire $0\wr_pick_dly$1631$next[0:0]$2826 - attribute \src "libresoc.v:41836.3-41837.51" - wire $0\wr_pick_dly$1631[0:0]$2261 - attribute \src "libresoc.v:40824.7-40824.32" - wire $0\wr_pick_dly$1631[0:0]$3003 - attribute \src "libresoc.v:46486.3-46494.6" - wire $0\wr_pick_dly$1647$next[0:0]$2830 - attribute \src "libresoc.v:41834.3-41835.51" - wire $0\wr_pick_dly$1647[0:0]$2259 - attribute \src "libresoc.v:40828.7-40828.32" - wire $0\wr_pick_dly$1647[0:0]$3005 - attribute \src "libresoc.v:46495.3-46503.6" - wire $0\wr_pick_dly$1663$next[0:0]$2833 - attribute \src "libresoc.v:41832.3-41833.51" - wire $0\wr_pick_dly$1663[0:0]$2257 - attribute \src "libresoc.v:40832.7-40832.32" - wire $0\wr_pick_dly$1663[0:0]$3007 - attribute \src "libresoc.v:46533.3-46541.6" - wire $0\wr_pick_dly$1679$next[0:0]$2841 - attribute \src "libresoc.v:41830.3-41831.51" - wire $0\wr_pick_dly$1679[0:0]$2255 - attribute \src "libresoc.v:40836.7-40836.32" - wire $0\wr_pick_dly$1679[0:0]$3009 - attribute \src "libresoc.v:46571.3-46579.6" - wire $0\wr_pick_dly$1723$next[0:0]$2849 - attribute \src "libresoc.v:41828.3-41829.51" - wire $0\wr_pick_dly$1723[0:0]$2253 - attribute \src "libresoc.v:40840.7-40840.32" - wire $0\wr_pick_dly$1723[0:0]$3011 - attribute \src "libresoc.v:46580.3-46588.6" - wire $0\wr_pick_dly$1739$next[0:0]$2852 - attribute \src "libresoc.v:41826.3-41827.51" - wire $0\wr_pick_dly$1739[0:0]$2251 - attribute \src "libresoc.v:40844.7-40844.32" - wire $0\wr_pick_dly$1739[0:0]$3013 - attribute \src "libresoc.v:46618.3-46626.6" - wire $0\wr_pick_dly$1763$next[0:0]$2856 - attribute \src "libresoc.v:41824.3-41825.51" - wire $0\wr_pick_dly$1763[0:0]$2249 - attribute \src "libresoc.v:40848.7-40848.32" - wire $0\wr_pick_dly$1763[0:0]$3015 - attribute \src "libresoc.v:46656.3-46664.6" - wire $0\wr_pick_dly$1783$next[0:0]$2860 - attribute \src "libresoc.v:41822.3-41823.51" - wire $0\wr_pick_dly$1783[0:0]$2247 - attribute \src "libresoc.v:40852.7-40852.32" - wire $0\wr_pick_dly$1783[0:0]$3017 - attribute \src "libresoc.v:45644.3-45652.6" - wire $0\wr_pick_dly$967$next[0:0]$2715 - attribute \src "libresoc.v:41892.3-41893.49" - wire $0\wr_pick_dly$967[0:0]$2317 - attribute \src "libresoc.v:40856.7-40856.31" - wire $0\wr_pick_dly$967[0:0]$3019 - attribute \src "libresoc.v:45682.3-45690.6" - wire $0\wr_pick_dly$986$next[0:0]$2719 - attribute \src "libresoc.v:41890.3-41891.49" - wire $0\wr_pick_dly$986[0:0]$2315 - attribute \src "libresoc.v:40860.7-40860.31" - wire $0\wr_pick_dly$986[0:0]$3021 - attribute \src "libresoc.v:45635.3-45643.6" - wire $0\wr_pick_dly$next[0:0]$2712 - attribute \src "libresoc.v:41894.3-41895.39" + attribute \src "libresoc.v:46381.3-46389.6" + wire $0\wr_pick_dly$1000$next[0:0]$2753 + attribute \src "libresoc.v:42513.3-42514.51" + wire $0\wr_pick_dly$1000[0:0]$2347 + attribute \src "libresoc.v:41343.7-41343.32" + wire $0\wr_pick_dly$1000[0:0]$2985 + attribute \src "libresoc.v:46419.3-46427.6" + wire $0\wr_pick_dly$1021$next[0:0]$2757 + attribute \src "libresoc.v:42511.3-42512.51" + wire $0\wr_pick_dly$1021[0:0]$2345 + attribute \src "libresoc.v:41347.7-41347.32" + wire $0\wr_pick_dly$1021[0:0]$2987 + attribute \src "libresoc.v:46457.3-46465.6" + wire $0\wr_pick_dly$1039$next[0:0]$2761 + attribute \src "libresoc.v:42509.3-42510.51" + wire $0\wr_pick_dly$1039[0:0]$2343 + attribute \src "libresoc.v:41351.7-41351.32" + wire $0\wr_pick_dly$1039[0:0]$2989 + attribute \src "libresoc.v:46466.3-46474.6" + wire $0\wr_pick_dly$1061$next[0:0]$2764 + attribute \src "libresoc.v:42507.3-42508.51" + wire $0\wr_pick_dly$1061[0:0]$2341 + attribute \src "libresoc.v:41355.7-41355.32" + wire $0\wr_pick_dly$1061[0:0]$2991 + attribute \src "libresoc.v:46504.3-46512.6" + wire $0\wr_pick_dly$1081$next[0:0]$2768 + attribute \src "libresoc.v:42505.3-42506.51" + wire $0\wr_pick_dly$1081[0:0]$2339 + attribute \src "libresoc.v:41359.7-41359.32" + wire $0\wr_pick_dly$1081[0:0]$2993 + attribute \src "libresoc.v:46542.3-46550.6" + wire $0\wr_pick_dly$1101$next[0:0]$2772 + attribute \src "libresoc.v:42503.3-42504.51" + wire $0\wr_pick_dly$1101[0:0]$2337 + attribute \src "libresoc.v:41363.7-41363.32" + wire $0\wr_pick_dly$1101[0:0]$2995 + attribute \src "libresoc.v:46551.3-46559.6" + wire $0\wr_pick_dly$1120$next[0:0]$2775 + attribute \src "libresoc.v:42501.3-42502.51" + wire $0\wr_pick_dly$1120[0:0]$2335 + attribute \src "libresoc.v:41367.7-41367.32" + wire $0\wr_pick_dly$1120[0:0]$2997 + attribute \src "libresoc.v:46589.3-46597.6" + wire $0\wr_pick_dly$1138$next[0:0]$2779 + attribute \src "libresoc.v:42499.3-42500.51" + wire $0\wr_pick_dly$1138[0:0]$2333 + attribute \src "libresoc.v:41371.7-41371.32" + wire $0\wr_pick_dly$1138[0:0]$2999 + attribute \src "libresoc.v:46627.3-46635.6" + wire $0\wr_pick_dly$1211$next[0:0]$2783 + attribute \src "libresoc.v:42497.3-42498.51" + wire $0\wr_pick_dly$1211[0:0]$2331 + attribute \src "libresoc.v:41375.7-41375.32" + wire $0\wr_pick_dly$1211[0:0]$3001 + attribute \src "libresoc.v:46665.3-46673.6" + wire $0\wr_pick_dly$1239$next[0:0]$2787 + attribute \src "libresoc.v:42495.3-42496.51" + wire $0\wr_pick_dly$1239[0:0]$2329 + attribute \src "libresoc.v:41379.7-41379.32" + wire $0\wr_pick_dly$1239[0:0]$3003 + attribute \src "libresoc.v:46703.3-46711.6" + wire $0\wr_pick_dly$1259$next[0:0]$2791 + attribute \src "libresoc.v:42493.3-42494.51" + wire $0\wr_pick_dly$1259[0:0]$2327 + attribute \src "libresoc.v:41383.7-41383.32" + wire $0\wr_pick_dly$1259[0:0]$3005 + attribute \src "libresoc.v:46712.3-46720.6" + wire $0\wr_pick_dly$1279$next[0:0]$2794 + attribute \src "libresoc.v:42491.3-42492.51" + wire $0\wr_pick_dly$1279[0:0]$2325 + attribute \src "libresoc.v:41387.7-41387.32" + wire $0\wr_pick_dly$1279[0:0]$3007 + attribute \src "libresoc.v:46750.3-46758.6" + wire $0\wr_pick_dly$1299$next[0:0]$2798 + attribute \src "libresoc.v:42489.3-42490.51" + wire $0\wr_pick_dly$1299[0:0]$2323 + attribute \src "libresoc.v:41391.7-41391.32" + wire $0\wr_pick_dly$1299[0:0]$3009 + attribute \src "libresoc.v:46759.3-46767.6" + wire $0\wr_pick_dly$1319$next[0:0]$2801 + attribute \src "libresoc.v:42487.3-42488.51" + wire $0\wr_pick_dly$1319[0:0]$2321 + attribute \src "libresoc.v:41395.7-41395.32" + wire $0\wr_pick_dly$1319[0:0]$3011 + attribute \src "libresoc.v:46797.3-46805.6" + wire $0\wr_pick_dly$1339$next[0:0]$2805 + attribute \src "libresoc.v:42485.3-42486.51" + wire $0\wr_pick_dly$1339[0:0]$2319 + attribute \src "libresoc.v:41399.7-41399.32" + wire $0\wr_pick_dly$1339[0:0]$3013 + attribute \src "libresoc.v:46835.3-46843.6" + wire $0\wr_pick_dly$1386$next[0:0]$2813 + attribute \src "libresoc.v:42483.3-42484.51" + wire $0\wr_pick_dly$1386[0:0]$2317 + attribute \src "libresoc.v:41403.7-41403.32" + wire $0\wr_pick_dly$1386[0:0]$3015 + attribute \src "libresoc.v:46873.3-46881.6" + wire $0\wr_pick_dly$1402$next[0:0]$2821 + attribute \src "libresoc.v:42481.3-42482.51" + wire $0\wr_pick_dly$1402[0:0]$2315 + attribute \src "libresoc.v:41407.7-41407.32" + wire $0\wr_pick_dly$1402[0:0]$3017 + attribute \src "libresoc.v:46882.3-46890.6" + wire $0\wr_pick_dly$1418$next[0:0]$2824 + attribute \src "libresoc.v:42479.3-42480.51" + wire $0\wr_pick_dly$1418[0:0]$2313 + attribute \src "libresoc.v:41411.7-41411.32" + wire $0\wr_pick_dly$1418[0:0]$3019 + attribute \src "libresoc.v:46920.3-46928.6" + wire $0\wr_pick_dly$1452$next[0:0]$2828 + attribute \src "libresoc.v:42477.3-42478.51" + wire $0\wr_pick_dly$1452[0:0]$2311 + attribute \src "libresoc.v:41415.7-41415.32" + wire $0\wr_pick_dly$1452[0:0]$3021 + attribute \src "libresoc.v:46958.3-46966.6" + wire $0\wr_pick_dly$1468$next[0:0]$2832 + attribute \src "libresoc.v:42475.3-42476.51" + wire $0\wr_pick_dly$1468[0:0]$2309 + attribute \src "libresoc.v:41419.7-41419.32" + wire $0\wr_pick_dly$1468[0:0]$3023 + attribute \src "libresoc.v:46967.3-46975.6" + wire $0\wr_pick_dly$1484$next[0:0]$2835 + attribute \src "libresoc.v:42473.3-42474.51" + wire $0\wr_pick_dly$1484[0:0]$2307 + attribute \src "libresoc.v:41423.7-41423.32" + wire $0\wr_pick_dly$1484[0:0]$3025 + attribute \src "libresoc.v:47005.3-47013.6" + wire $0\wr_pick_dly$1500$next[0:0]$2839 + attribute \src "libresoc.v:42471.3-42472.51" + wire $0\wr_pick_dly$1500[0:0]$2305 + attribute \src "libresoc.v:41427.7-41427.32" + wire $0\wr_pick_dly$1500[0:0]$3027 + attribute \src "libresoc.v:47043.3-47051.6" + wire $0\wr_pick_dly$1536$next[0:0]$2843 + attribute \src "libresoc.v:42469.3-42470.51" + wire $0\wr_pick_dly$1536[0:0]$2303 + attribute \src "libresoc.v:41431.7-41431.32" + wire $0\wr_pick_dly$1536[0:0]$3029 + attribute \src "libresoc.v:47052.3-47060.6" + wire $0\wr_pick_dly$1552$next[0:0]$2846 + attribute \src "libresoc.v:42467.3-42468.51" + wire $0\wr_pick_dly$1552[0:0]$2301 + attribute \src "libresoc.v:41435.7-41435.32" + wire $0\wr_pick_dly$1552[0:0]$3031 + attribute \src "libresoc.v:47091.3-47099.6" + wire $0\wr_pick_dly$1568$next[0:0]$2850 + attribute \src "libresoc.v:42465.3-42466.51" + wire $0\wr_pick_dly$1568[0:0]$2299 + attribute \src "libresoc.v:41439.7-41439.32" + wire $0\wr_pick_dly$1568[0:0]$3033 + attribute \src "libresoc.v:47100.3-47108.6" + wire $0\wr_pick_dly$1584$next[0:0]$2853 + attribute \src "libresoc.v:42463.3-42464.51" + wire $0\wr_pick_dly$1584[0:0]$2297 + attribute \src "libresoc.v:41443.7-41443.32" + wire $0\wr_pick_dly$1584[0:0]$3035 + attribute \src "libresoc.v:47109.3-47117.6" + wire $0\wr_pick_dly$1626$next[0:0]$2856 + attribute \src "libresoc.v:42461.3-42462.51" + wire $0\wr_pick_dly$1626[0:0]$2295 + attribute \src "libresoc.v:41447.7-41447.32" + wire $0\wr_pick_dly$1626[0:0]$3037 + attribute \src "libresoc.v:47147.3-47155.6" + wire $0\wr_pick_dly$1645$next[0:0]$2860 + attribute \src "libresoc.v:42459.3-42460.51" + wire $0\wr_pick_dly$1645[0:0]$2293 + attribute \src "libresoc.v:41451.7-41451.32" + wire $0\wr_pick_dly$1645[0:0]$3039 + attribute \src "libresoc.v:47185.3-47193.6" + wire $0\wr_pick_dly$1661$next[0:0]$2864 + attribute \src "libresoc.v:42457.3-42458.51" + wire $0\wr_pick_dly$1661[0:0]$2291 + attribute \src "libresoc.v:41455.7-41455.32" + wire $0\wr_pick_dly$1661[0:0]$3041 + attribute \src "libresoc.v:47194.3-47202.6" + wire $0\wr_pick_dly$1677$next[0:0]$2867 + attribute \src "libresoc.v:42455.3-42456.51" + wire $0\wr_pick_dly$1677[0:0]$2289 + attribute \src "libresoc.v:41459.7-41459.32" + wire $0\wr_pick_dly$1677[0:0]$3043 + attribute \src "libresoc.v:47232.3-47240.6" + wire $0\wr_pick_dly$1693$next[0:0]$2875 + attribute \src "libresoc.v:42453.3-42454.51" + wire $0\wr_pick_dly$1693[0:0]$2287 + attribute \src "libresoc.v:41463.7-41463.32" + wire $0\wr_pick_dly$1693[0:0]$3045 + attribute \src "libresoc.v:47270.3-47278.6" + wire $0\wr_pick_dly$1737$next[0:0]$2883 + attribute \src "libresoc.v:42451.3-42452.51" + wire $0\wr_pick_dly$1737[0:0]$2285 + attribute \src "libresoc.v:41467.7-41467.32" + wire $0\wr_pick_dly$1737[0:0]$3047 + attribute \src "libresoc.v:47308.3-47316.6" + wire $0\wr_pick_dly$1753$next[0:0]$2887 + attribute \src "libresoc.v:42449.3-42450.51" + wire $0\wr_pick_dly$1753[0:0]$2283 + attribute \src "libresoc.v:41471.7-41471.32" + wire $0\wr_pick_dly$1753[0:0]$3049 + attribute \src "libresoc.v:47317.3-47325.6" + wire $0\wr_pick_dly$1777$next[0:0]$2890 + attribute \src "libresoc.v:42447.3-42448.51" + wire $0\wr_pick_dly$1777[0:0]$2281 + attribute \src "libresoc.v:41475.7-41475.32" + wire $0\wr_pick_dly$1777[0:0]$3051 + attribute \src "libresoc.v:47355.3-47363.6" + wire $0\wr_pick_dly$1797$next[0:0]$2894 + attribute \src "libresoc.v:42445.3-42446.51" + wire $0\wr_pick_dly$1797[0:0]$2279 + attribute \src "libresoc.v:41479.7-41479.32" + wire $0\wr_pick_dly$1797[0:0]$3053 + attribute \src "libresoc.v:46372.3-46380.6" + wire $0\wr_pick_dly$981$next[0:0]$2750 + attribute \src "libresoc.v:42515.3-42516.49" + wire $0\wr_pick_dly$981[0:0]$2349 + attribute \src "libresoc.v:41483.7-41483.31" + wire $0\wr_pick_dly$981[0:0]$3055 + attribute \src "libresoc.v:46334.3-46342.6" + wire $0\wr_pick_dly$next[0:0]$2746 + attribute \src "libresoc.v:42517.3-42518.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:45017.3-45037.6" - wire $1\core_terminate_o$next[0:0]$2598 - attribute \src "libresoc.v:37364.7-37364.30" + attribute \src "libresoc.v:45707.3-45727.6" + wire $1\core_terminate_o$next[0:0]$2629 + attribute \src "libresoc.v:37965.7-37965.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:44833.3-44859.6" - wire width 2 $1\counter$next[1:0]$2572 - attribute \src "libresoc.v:37377.13-37377.27" + attribute \src "libresoc.v:45532.3-45558.6" + wire width 2 $1\counter$next[1:0]$2606 + attribute \src "libresoc.v:37978.13-37978.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:45318.3-45326.6" - wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 - attribute \src "libresoc.v:38505.7-38505.34" + attribute \src "libresoc.v:46017.3-46025.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 + attribute \src "libresoc.v:39108.7-39108.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45299.3-45307.6" - wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 - attribute \src "libresoc.v:38509.7-38509.30" + attribute \src "libresoc.v:45998.3-46006.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 + attribute \src "libresoc.v:39112.7-39112.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:45337.3-45345.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:38513.7-38513.30" + attribute \src "libresoc.v:46036.3-46044.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 + attribute \src "libresoc.v:39116.7-39116.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:45386.3-45394.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:38517.7-38517.30" + attribute \src "libresoc.v:46085.3-46093.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 + attribute \src "libresoc.v:39120.7-39120.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45250.3-45258.6" - wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 - attribute \src "libresoc.v:38521.7-38521.33" + attribute \src "libresoc.v:45949.3-45957.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 + attribute \src "libresoc.v:39124.7-39124.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:45405.3-45413.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 - attribute \src "libresoc.v:38525.7-38525.37" + attribute \src "libresoc.v:46104.3-46112.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 + attribute \src "libresoc.v:39128.7-39128.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:45472.3-45480.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 - attribute \src "libresoc.v:38529.7-38529.34" + attribute \src "libresoc.v:46171.3-46179.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 + attribute \src "libresoc.v:39132.7-39132.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:45424.3-45432.6" - wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 - attribute \src "libresoc.v:38533.7-38533.35" + attribute \src "libresoc.v:46123.3-46131.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 + attribute \src "libresoc.v:39136.7-39136.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:45491.3-45499.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 - attribute \src "libresoc.v:38537.7-38537.37" + attribute \src "libresoc.v:46219.3-46227.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 + attribute \src "libresoc.v:39140.7-39140.37" wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:45539.3-45547.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 - attribute \src "libresoc.v:38541.7-38541.35" + attribute \src "libresoc.v:46238.3-46246.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 + attribute \src "libresoc.v:39144.7-39144.35" wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:44472.3-44480.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2464 - attribute \src "libresoc.v:38545.7-38545.30" + attribute \src "libresoc.v:45171.3-45179.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2498 + attribute \src "libresoc.v:39148.7-39148.30" wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:44491.3-44499.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2468 - attribute \src "libresoc.v:38549.7-38549.29" + attribute \src "libresoc.v:45190.3-45198.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2502 + attribute \src "libresoc.v:39152.7-39152.29" wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:44567.3-44575.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2492 - attribute \src "libresoc.v:38553.7-38553.30" + attribute \src "libresoc.v:45266.3-45274.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2526 + attribute \src "libresoc.v:39156.7-39156.30" wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:44624.3-44632.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2510 - attribute \src "libresoc.v:38557.7-38557.31" + attribute \src "libresoc.v:45323.3-45331.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2544 + attribute \src "libresoc.v:39160.7-39160.31" wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:44529.3-44537.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2480 - attribute \src "libresoc.v:38561.7-38561.34" + attribute \src "libresoc.v:45228.3-45236.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2514 + attribute \src "libresoc.v:39164.7-39164.34" wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:44586.3-44594.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2498 - attribute \src "libresoc.v:38565.7-38565.30" + attribute \src "libresoc.v:45285.3-45293.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2532 + attribute \src "libresoc.v:39168.7-39168.30" wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:44605.3-44613.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 - attribute \src "libresoc.v:38569.7-38569.35" + attribute \src "libresoc.v:45304.3-45312.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 + attribute \src "libresoc.v:39172.7-39172.35" wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:44548.3-44556.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2486 - attribute \src "libresoc.v:38573.7-38573.30" + attribute \src "libresoc.v:45247.3-45255.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2520 + attribute \src "libresoc.v:39176.7-39176.30" wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:44510.3-44518.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2474 - attribute \src "libresoc.v:38577.7-38577.31" + attribute \src "libresoc.v:45209.3-45217.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2508 + attribute \src "libresoc.v:39180.7-39180.31" wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:44643.3-44651.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2516 - attribute \src "libresoc.v:38581.7-38581.30" + attribute \src "libresoc.v:45342.3-45350.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2550 + attribute \src "libresoc.v:39184.7-39184.30" wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:44662.3-44670.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2520 - attribute \src "libresoc.v:38585.7-38585.29" + attribute \src "libresoc.v:45361.3-45369.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2554 + attribute \src "libresoc.v:39188.7-39188.29" wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:44719.3-44727.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2538 - attribute \src "libresoc.v:38589.7-38589.30" + attribute \src "libresoc.v:45418.3-45426.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2572 + attribute \src "libresoc.v:39192.7-39192.30" wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:44776.3-44784.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2556 - attribute \src "libresoc.v:38593.7-38593.31" + attribute \src "libresoc.v:45475.3-45483.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2590 + attribute \src "libresoc.v:39196.7-39196.31" wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:44700.3-44708.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2532 - attribute \src "libresoc.v:38597.7-38597.34" + attribute \src "libresoc.v:45399.3-45407.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2566 + attribute \src "libresoc.v:39200.7-39200.34" wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:44738.3-44746.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2544 - attribute \src "libresoc.v:38601.7-38601.30" + attribute \src "libresoc.v:45437.3-45445.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2578 + attribute \src "libresoc.v:39204.7-39204.30" wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:44757.3-44765.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 - attribute \src "libresoc.v:38605.7-38605.35" + attribute \src "libresoc.v:45456.3-45464.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 + attribute \src "libresoc.v:39208.7-39208.35" wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:44681.3-44689.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2526 - attribute \src "libresoc.v:38609.7-38609.31" + attribute \src "libresoc.v:45380.3-45388.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2560 + attribute \src "libresoc.v:39212.7-39212.31" wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:44814.3-44822.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2566 - attribute \src "libresoc.v:38613.7-38613.31" + attribute \src "libresoc.v:45513.3-45521.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2600 + attribute \src "libresoc.v:39216.7-39216.31" wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:44795.3-44803.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 - attribute \src "libresoc.v:38617.7-38617.35" + attribute \src "libresoc.v:45494.3-45502.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 + attribute \src "libresoc.v:39220.7-39220.35" wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:45587.3-45595.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 - attribute \src "libresoc.v:38621.7-38621.32" + attribute \src "libresoc.v:46286.3-46294.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 + attribute \src "libresoc.v:39224.7-39224.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45115.3-45123.6" - wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 - attribute \src "libresoc.v:38625.7-38625.34" + attribute \src "libresoc.v:45814.3-45822.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 + attribute \src "libresoc.v:39228.7-39228.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45182.3-45190.6" - wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 - attribute \src "libresoc.v:38629.7-38629.39" + attribute \src "libresoc.v:45881.3-45889.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 + attribute \src "libresoc.v:39232.7-39232.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45163.3-45171.6" - wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 - attribute \src "libresoc.v:38633.7-38633.34" + attribute \src "libresoc.v:45862.3-45870.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 + attribute \src "libresoc.v:39236.7-39236.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45231.3-45239.6" - wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 - attribute \src "libresoc.v:38637.7-38637.34" + attribute \src "libresoc.v:45930.3-45938.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 + attribute \src "libresoc.v:39240.7-39240.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:44860.3-44868.6" - wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 - attribute \src "libresoc.v:38641.7-38641.34" + attribute \src "libresoc.v:45559.3-45567.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 + attribute \src "libresoc.v:39244.7-39244.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45008.3-45016.6" - wire $1\dp_XER_xer_so_div0_3$next[0:0]$2595 - attribute \src "libresoc.v:38645.7-38645.34" + attribute \src "libresoc.v:45728.3-45736.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2634 + attribute \src "libresoc.v:39248.7-39248.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:44879.3-44887.6" - wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 - attribute \src "libresoc.v:38649.7-38649.38" + attribute \src "libresoc.v:45669.3-45677.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 + attribute \src "libresoc.v:39252.7-39252.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45048.3-45056.6" - wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 - attribute \src "libresoc.v:38653.7-38653.34" + attribute \src "libresoc.v:45747.3-45755.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 + attribute \src "libresoc.v:39256.7-39256.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45067.3-45075.6" - wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 - attribute \src "libresoc.v:38657.7-38657.39" + attribute \src "libresoc.v:45795.3-45803.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 + attribute \src "libresoc.v:39260.7-39260.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:44989.3-44997.6" - wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 - attribute \src "libresoc.v:38661.7-38661.34" + attribute \src "libresoc.v:45688.3-45696.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 + attribute \src "libresoc.v:39264.7-39264.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46839.3-46867.6" - wire $1\fus_cu_issue_i$10[0:0]$2870 - attribute \src "libresoc.v:47335.3-47363.6" - wire $1\fus_cu_issue_i$13[0:0]$2895 - attribute \src "libresoc.v:42720.3-42748.6" - wire $1\fus_cu_issue_i$16[0:0]$2364 - attribute \src "libresoc.v:43216.3-43244.6" - wire $1\fus_cu_issue_i$19[0:0]$2389 - attribute \src "libresoc.v:43538.3-43566.6" - wire $1\fus_cu_issue_i$22[0:0]$2408 - attribute \src "libresoc.v:43976.3-44004.6" - wire $1\fus_cu_issue_i$25[0:0]$2431 - attribute \src "libresoc.v:44414.3-44442.6" - wire $1\fus_cu_issue_i$28[0:0]$2454 - attribute \src "libresoc.v:46107.3-46135.6" - wire $1\fus_cu_issue_i$4[0:0]$2775 - attribute \src "libresoc.v:46504.3-46532.6" - wire $1\fus_cu_issue_i$7[0:0]$2837 - attribute \src "libresoc.v:45899.3-45927.6" + attribute \src "libresoc.v:46806.3-46834.6" + wire $1\fus_cu_issue_i$11[0:0]$2809 + attribute \src "libresoc.v:47203.3-47231.6" + wire $1\fus_cu_issue_i$14[0:0]$2871 + attribute \src "libresoc.v:47567.3-47595.6" + wire $1\fus_cu_issue_i$17[0:0]$2905 + attribute \src "libresoc.v:48063.3-48091.6" + wire $1\fus_cu_issue_i$20[0:0]$2930 + attribute \src "libresoc.v:43390.3-43418.6" + wire $1\fus_cu_issue_i$23[0:0]$2397 + attribute \src "libresoc.v:43886.3-43914.6" + wire $1\fus_cu_issue_i$26[0:0]$2422 + attribute \src "libresoc.v:44208.3-44236.6" + wire $1\fus_cu_issue_i$29[0:0]$2441 + attribute \src "libresoc.v:44675.3-44703.6" + wire $1\fus_cu_issue_i$32[0:0]$2465 + attribute \src "libresoc.v:45113.3-45141.6" + wire $1\fus_cu_issue_i$35[0:0]$2488 + attribute \src "libresoc.v:46598.3-46626.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46868.3-46896.6" - wire width 4 $1\fus_cu_rdmaskn_i$12[3:0]$2875 - attribute \src "libresoc.v:47364.3-47392.6" - wire width 3 $1\fus_cu_rdmaskn_i$15[2:0]$2900 - attribute \src "libresoc.v:42749.3-42777.6" - wire width 6 $1\fus_cu_rdmaskn_i$18[5:0]$2369 - attribute \src "libresoc.v:43245.3-43273.6" - wire width 3 $1\fus_cu_rdmaskn_i$21[2:0]$2394 - attribute \src "libresoc.v:43567.3-43595.6" - wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2413 - attribute \src "libresoc.v:44005.3-44033.6" - wire width 5 $1\fus_cu_rdmaskn_i$27[4:0]$2436 - attribute \src "libresoc.v:44443.3-44471.6" - wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2459 - attribute \src "libresoc.v:46154.3-46182.6" - wire width 6 $1\fus_cu_rdmaskn_i$6[5:0]$2786 - attribute \src "libresoc.v:46542.3-46570.6" - wire width 3 $1\fus_cu_rdmaskn_i$9[2:0]$2845 - attribute \src "libresoc.v:45937.3-45965.6" + attribute \src "libresoc.v:46844.3-46872.6" + wire width 6 $1\fus_cu_rdmaskn_i$13[5:0]$2817 + attribute \src "libresoc.v:47241.3-47269.6" + wire width 3 $1\fus_cu_rdmaskn_i$16[2:0]$2879 + attribute \src "libresoc.v:47596.3-47624.6" + wire width 4 $1\fus_cu_rdmaskn_i$19[3:0]$2910 + attribute \src "libresoc.v:48092.3-48120.6" + wire width 3 $1\fus_cu_rdmaskn_i$22[2:0]$2935 + attribute \src "libresoc.v:43419.3-43447.6" + wire width 6 $1\fus_cu_rdmaskn_i$25[5:0]$2402 + attribute \src "libresoc.v:43915.3-43943.6" + wire width 3 $1\fus_cu_rdmaskn_i$28[2:0]$2427 + attribute \src "libresoc.v:44237.3-44265.6" + wire width 3 $1\fus_cu_rdmaskn_i$31[2:0]$2446 + attribute \src "libresoc.v:44704.3-44732.6" + wire width 5 $1\fus_cu_rdmaskn_i$34[4:0]$2470 + attribute \src "libresoc.v:45142.3-45170.6" + wire width 3 $1\fus_cu_rdmaskn_i$37[2:0]$2493 + attribute \src "libresoc.v:46636.3-46664.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:45814.3-45842.6" + attribute \src "libresoc.v:46513.3-46541.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45134.3-45162.6" + attribute \src "libresoc.v:45823.3-45851.6" wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45653.3-45681.6" + attribute \src "libresoc.v:46343.3-46371.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46560.3-46588.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45076.3-45104.6" + attribute \src "libresoc.v:45766.3-45794.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45443.3-45471.6" + attribute \src "libresoc.v:46142.3-46170.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45558.3-45586.6" + attribute \src "libresoc.v:46257.3-46285.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:45738.3-45766.6" + attribute \src "libresoc.v:46428.3-46456.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:45776.3-45804.6" + attribute \src "libresoc.v:46475.3-46503.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:46390.3-46418.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45606.3-45634.6" + attribute \src "libresoc.v:46305.3-46333.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:45500.3-45528.6" + attribute \src "libresoc.v:46190.3-46218.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46192.3-46220.6" + attribute \src "libresoc.v:46891.3-46919.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46277.3-46305.6" + attribute \src "libresoc.v:46976.3-47004.6" wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46315.3-46343.6" + attribute \src "libresoc.v:47014.3-47042.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46239.3-46267.6" + attribute \src "libresoc.v:46929.3-46957.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46457.3-46485.6" + attribute \src "libresoc.v:47156.3-47184.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46419.3-46447.6" + attribute \src "libresoc.v:47118.3-47146.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46022.3-46050.6" + attribute \src "libresoc.v:46721.3-46749.6" wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46069.3-46097.6" + attribute \src "libresoc.v:46768.3-46796.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:45984.3-46012.6" + attribute \src "libresoc.v:46674.3-46702.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43158.3-43186.6" + attribute \src "libresoc.v:43828.3-43856.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:42807.3-42835.6" + attribute \src "libresoc.v:43477.3-43505.6" wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:42984.3-43012.6" + attribute \src "libresoc.v:43654.3-43682.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43187.3-43215.6" + attribute \src "libresoc.v:43857.3-43885.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:42778.3-42806.6" + attribute \src "libresoc.v:43448.3-43476.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:42926.3-42954.6" + attribute \src "libresoc.v:43596.3-43624.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43013.3-43041.6" + attribute \src "libresoc.v:43683.3-43711.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43100.3-43128.6" + attribute \src "libresoc.v:43770.3-43798.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43129.3-43157.6" + attribute \src "libresoc.v:43799.3-43827.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43071.3-43099.6" + attribute \src "libresoc.v:43741.3-43769.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43042.3-43070.6" + attribute \src "libresoc.v:43712.3-43740.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:42955.3-42983.6" + attribute \src "libresoc.v:43625.3-43653.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47277.3-47305.6" + attribute \src "libresoc.v:48005.3-48033.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:46926.3-46954.6" + attribute \src "libresoc.v:47654.3-47682.6" wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47103.3-47131.6" + attribute \src "libresoc.v:47831.3-47859.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47306.3-47334.6" + attribute \src "libresoc.v:48034.3-48062.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:46897.3-46925.6" + attribute \src "libresoc.v:47625.3-47653.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47045.3-47073.6" + attribute \src "libresoc.v:47773.3-47801.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47132.3-47160.6" + attribute \src "libresoc.v:47860.3-47888.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47219.3-47247.6" + attribute \src "libresoc.v:47947.3-47975.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47248.3-47276.6" + attribute \src "libresoc.v:47976.3-48004.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47190.3-47218.6" + attribute \src "libresoc.v:47918.3-47946.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47161.3-47189.6" + attribute \src "libresoc.v:47889.3-47917.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47074.3-47102.6" + attribute \src "libresoc.v:47802.3-47830.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43303.3-43331.6" + attribute \src "libresoc.v:43973.3-44001.6" wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43509.3-43537.6" + attribute \src "libresoc.v:44179.3-44207.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43274.3-43302.6" + attribute \src "libresoc.v:43944.3-43972.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43451.3-43479.6" + attribute \src "libresoc.v:44121.3-44149.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43480.3-43508.6" + attribute \src "libresoc.v:44150.3-44178.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43422.3-43450.6" + attribute \src "libresoc.v:44092.3-44120.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" + attribute \src "libresoc.v:44295.3-44323.6" wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:43773.3-43801.6" + attribute \src "libresoc.v:44472.3-44500.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:43831.3-43859.6" + attribute \src "libresoc.v:44530.3-44558.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:43947.3-43975.6" + attribute \src "libresoc.v:44646.3-44674.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:43596.3-43624.6" + attribute \src "libresoc.v:44266.3-44294.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:43889.3-43917.6" + attribute \src "libresoc.v:44443.3-44471.6" + wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44588.3-44616.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:43918.3-43946.6" + attribute \src "libresoc.v:44617.3-44645.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:43802.3-43830.6" + attribute \src "libresoc.v:44501.3-44529.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:43860.3-43888.6" + attribute \src "libresoc.v:44559.3-44587.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:43744.3-43772.6" + attribute \src "libresoc.v:44414.3-44442.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47422.3-47450.6" + attribute \src "libresoc.v:48150.3-48178.6" wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47451.3-47479.6" + attribute \src "libresoc.v:43332.3-43360.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:48121.3-48149.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:42691.3-42719.6" + attribute \src "libresoc.v:43361.3-43389.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:46723.3-46751.6" + attribute \src "libresoc.v:47422.3-47450.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:46627.3-46655.6" + attribute \src "libresoc.v:47326.3-47354.6" wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:46665.3-46693.6" + attribute \src "libresoc.v:47364.3-47392.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:46589.3-46617.6" + attribute \src "libresoc.v:47279.3-47307.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:46752.3-46780.6" + attribute \src "libresoc.v:47451.3-47479.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:47538.3-47566.6" + wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47393.3-47421.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:46810.3-46838.6" + attribute \src "libresoc.v:47509.3-47537.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:46781.3-46809.6" - wire width 7 $1\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "libresoc.v:44298.3-44326.6" + attribute \src "libresoc.v:47480.3-47508.6" + wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44997.3-45025.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44269.3-44297.6" + attribute \src "libresoc.v:44968.3-44996.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44063.3-44091.6" + attribute \src "libresoc.v:44762.3-44790.6" wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44385.3-44413.6" + attribute \src "libresoc.v:45084.3-45112.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44034.3-44062.6" + attribute \src "libresoc.v:44733.3-44761.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44211.3-44239.6" + attribute \src "libresoc.v:44910.3-44938.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44240.3-44268.6" + attribute \src "libresoc.v:44939.3-44967.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44356.3-44384.6" + attribute \src "libresoc.v:45055.3-45083.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44327.3-44355.6" + attribute \src "libresoc.v:45026.3-45054.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44122.3-44150.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44500.3-44509.6" - wire width 64 $1\fus_src1_i$33[63:0]$2471 - attribute \src "libresoc.v:44519.3-44528.6" - wire width 64 $1\fus_src1_i$36[63:0]$2477 - attribute \src "libresoc.v:44538.3-44547.6" - wire width 64 $1\fus_src1_i$39[63:0]$2483 - attribute \src "libresoc.v:44557.3-44566.6" - wire width 64 $1\fus_src1_i$42[63:0]$2489 - attribute \src "libresoc.v:44576.3-44585.6" - wire width 64 $1\fus_src1_i$45[63:0]$2495 - attribute \src "libresoc.v:44595.3-44604.6" - wire width 64 $1\fus_src1_i$48[63:0]$2501 - attribute \src "libresoc.v:44614.3-44623.6" - wire width 64 $1\fus_src1_i$51[63:0]$2507 - attribute \src "libresoc.v:44633.3-44642.6" - wire width 64 $1\fus_src1_i$54[63:0]$2513 - attribute \src "libresoc.v:45414.3-45423.6" - wire width 64 $1\fus_src1_i$77[63:0]$2676 - attribute \src "libresoc.v:44481.3-44490.6" + attribute \src "libresoc.v:45199.3-45208.6" + wire width 64 $1\fus_src1_i$40[63:0]$2505 + attribute \src "libresoc.v:45218.3-45227.6" + wire width 64 $1\fus_src1_i$43[63:0]$2511 + attribute \src "libresoc.v:45237.3-45246.6" + wire width 64 $1\fus_src1_i$46[63:0]$2517 + attribute \src "libresoc.v:45256.3-45265.6" + wire width 64 $1\fus_src1_i$49[63:0]$2523 + attribute \src "libresoc.v:45275.3-45284.6" + wire width 64 $1\fus_src1_i$52[63:0]$2529 + attribute \src "libresoc.v:45294.3-45303.6" + wire width 64 $1\fus_src1_i$55[63:0]$2535 + attribute \src "libresoc.v:45313.3-45322.6" + wire width 64 $1\fus_src1_i$58[63:0]$2541 + attribute \src "libresoc.v:45332.3-45341.6" + wire width 64 $1\fus_src1_i$61[63:0]$2547 + attribute \src "libresoc.v:46113.3-46122.6" + wire width 64 $1\fus_src1_i$84[63:0]$2710 + attribute \src "libresoc.v:45180.3-45189.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:44671.3-44680.6" - wire width 64 $1\fus_src2_i$55[63:0]$2523 - attribute \src "libresoc.v:44690.3-44699.6" - wire width 64 $1\fus_src2_i$56[63:0]$2529 - attribute \src "libresoc.v:44709.3-44718.6" - wire width 64 $1\fus_src2_i$57[63:0]$2535 - attribute \src "libresoc.v:44728.3-44737.6" - wire width 64 $1\fus_src2_i$58[63:0]$2541 - attribute \src "libresoc.v:44747.3-44756.6" - wire width 64 $1\fus_src2_i$59[63:0]$2547 - attribute \src "libresoc.v:44766.3-44775.6" - wire width 64 $1\fus_src2_i$60[63:0]$2553 - attribute \src "libresoc.v:44785.3-44794.6" - wire width 64 $1\fus_src2_i$61[63:0]$2559 - attribute \src "libresoc.v:45529.3-45538.6" - wire width 64 $1\fus_src2_i$80[63:0]$2696 - attribute \src "libresoc.v:45596.3-45605.6" - wire width 64 $1\fus_src2_i$82[63:0]$2709 - attribute \src "libresoc.v:44652.3-44661.6" + attribute \src "libresoc.v:45370.3-45379.6" + wire width 64 $1\fus_src2_i$62[63:0]$2557 + attribute \src "libresoc.v:45389.3-45398.6" + wire width 64 $1\fus_src2_i$63[63:0]$2563 + attribute \src "libresoc.v:45408.3-45417.6" + wire width 64 $1\fus_src2_i$64[63:0]$2569 + attribute \src "libresoc.v:45427.3-45436.6" + wire width 64 $1\fus_src2_i$65[63:0]$2575 + attribute \src "libresoc.v:45446.3-45455.6" + wire width 64 $1\fus_src2_i$66[63:0]$2581 + attribute \src "libresoc.v:45465.3-45474.6" + wire width 64 $1\fus_src2_i$67[63:0]$2587 + attribute \src "libresoc.v:45484.3-45493.6" + wire width 64 $1\fus_src2_i$68[63:0]$2593 + attribute \src "libresoc.v:46228.3-46237.6" + wire width 64 $1\fus_src2_i$87[63:0]$2730 + attribute \src "libresoc.v:46295.3-46304.6" + wire width 64 $1\fus_src2_i$89[63:0]$2743 + attribute \src "libresoc.v:45351.3-45360.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:44823.3-44832.6" - wire width 64 $1\fus_src3_i$62[63:0]$2569 - attribute \src "libresoc.v:44869.3-44878.6" - wire $1\fus_src3_i$63[0:0]$2581 - attribute \src "libresoc.v:44979.3-44988.6" - wire $1\fus_src3_i$64[0:0]$2588 - attribute \src "libresoc.v:45038.3-45047.6" - wire $1\fus_src3_i$65[0:0]$2603 - attribute \src "libresoc.v:45057.3-45066.6" - wire $1\fus_src3_i$66[0:0]$2609 - attribute \src "libresoc.v:45259.3-45268.6" - wire width 32 $1\fus_src3_i$70[31:0]$2644 - attribute \src "libresoc.v:45327.3-45336.6" - wire width 4 $1\fus_src3_i$74[3:0]$2657 - attribute \src "libresoc.v:45433.3-45442.6" - wire width 64 $1\fus_src3_i$78[63:0]$2682 - attribute \src "libresoc.v:45481.3-45490.6" - wire width 64 $1\fus_src3_i$79[63:0]$2689 - attribute \src "libresoc.v:44804.3-44813.6" + attribute \src "libresoc.v:45522.3-45531.6" + wire width 64 $1\fus_src3_i$69[63:0]$2603 + attribute \src "libresoc.v:45568.3-45577.6" + wire $1\fus_src3_i$70[0:0]$2615 + attribute \src "libresoc.v:45678.3-45687.6" + wire $1\fus_src3_i$71[0:0]$2622 + attribute \src "libresoc.v:45737.3-45746.6" + wire $1\fus_src3_i$72[0:0]$2637 + attribute \src "libresoc.v:45756.3-45765.6" + wire $1\fus_src3_i$73[0:0]$2643 + attribute \src "libresoc.v:45958.3-45967.6" + wire width 32 $1\fus_src3_i$77[31:0]$2678 + attribute \src "libresoc.v:46026.3-46035.6" + wire width 4 $1\fus_src3_i$81[3:0]$2691 + attribute \src "libresoc.v:46132.3-46141.6" + wire width 64 $1\fus_src3_i$85[63:0]$2716 + attribute \src "libresoc.v:46180.3-46189.6" + wire width 64 $1\fus_src3_i$86[63:0]$2723 + attribute \src "libresoc.v:45503.3-45512.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45105.3-45114.6" - wire $1\fus_src4_i$67[0:0]$2616 - attribute \src "libresoc.v:45124.3-45133.6" - wire width 2 $1\fus_src4_i$68[1:0]$2622 - attribute \src "libresoc.v:45308.3-45317.6" - wire width 4 $1\fus_src4_i$71[3:0]$2651 - attribute \src "libresoc.v:45548.3-45557.6" - wire width 64 $1\fus_src4_i$81[63:0]$2702 - attribute \src "libresoc.v:44998.3-45007.6" + attribute \src "libresoc.v:45804.3-45813.6" + wire $1\fus_src4_i$74[0:0]$2650 + attribute \src "libresoc.v:45852.3-45861.6" + wire width 2 $1\fus_src4_i$75[1:0]$2657 + attribute \src "libresoc.v:46007.3-46016.6" + wire width 4 $1\fus_src4_i$78[3:0]$2685 + attribute \src "libresoc.v:46247.3-46256.6" + wire width 64 $1\fus_src4_i$88[63:0]$2736 + attribute \src "libresoc.v:45697.3-45706.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45240.3-45249.6" - wire width 2 $1\fus_src5_i$69[1:0]$2638 - attribute \src "libresoc.v:45346.3-45355.6" - wire width 4 $1\fus_src5_i$75[3:0]$2663 - attribute \src "libresoc.v:45191.3-45200.6" + attribute \src "libresoc.v:45939.3-45948.6" + wire width 2 $1\fus_src5_i$76[1:0]$2672 + attribute \src "libresoc.v:46045.3-46054.6" + wire width 4 $1\fus_src5_i$82[3:0]$2697 + attribute \src "libresoc.v:45920.3-45929.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:45395.3-45404.6" - wire width 4 $1\fus_src6_i$76[3:0]$2670 - attribute \src "libresoc.v:45172.3-45181.6" + attribute \src "libresoc.v:46094.3-46103.6" + wire width 4 $1\fus_src6_i$83[3:0]$2704 + attribute \src "libresoc.v:45871.3-45880.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45720.3-45728.6" - wire $1\wr_pick_dly$1007$next[0:0]$2724 - attribute \src "libresoc.v:45729.3-45737.6" - wire $1\wr_pick_dly$1025$next[0:0]$2727 - attribute \src "libresoc.v:45767.3-45775.6" - wire $1\wr_pick_dly$1047$next[0:0]$2731 - attribute \src "libresoc.v:45805.3-45813.6" - wire $1\wr_pick_dly$1067$next[0:0]$2735 - attribute \src "libresoc.v:45843.3-45851.6" - wire $1\wr_pick_dly$1087$next[0:0]$2739 - attribute \src "libresoc.v:45852.3-45860.6" - wire $1\wr_pick_dly$1106$next[0:0]$2742 - attribute \src "libresoc.v:45890.3-45898.6" - wire $1\wr_pick_dly$1124$next[0:0]$2746 - attribute \src "libresoc.v:45928.3-45936.6" - wire $1\wr_pick_dly$1197$next[0:0]$2750 - attribute \src "libresoc.v:45966.3-45974.6" - wire $1\wr_pick_dly$1225$next[0:0]$2754 - attribute \src "libresoc.v:45975.3-45983.6" - wire $1\wr_pick_dly$1245$next[0:0]$2757 - attribute \src "libresoc.v:46013.3-46021.6" - wire $1\wr_pick_dly$1265$next[0:0]$2761 - attribute \src "libresoc.v:46051.3-46059.6" - wire $1\wr_pick_dly$1285$next[0:0]$2765 - attribute \src "libresoc.v:46060.3-46068.6" - wire $1\wr_pick_dly$1305$next[0:0]$2768 - attribute \src "libresoc.v:46098.3-46106.6" - wire $1\wr_pick_dly$1325$next[0:0]$2772 - attribute \src "libresoc.v:46136.3-46144.6" - wire $1\wr_pick_dly$1372$next[0:0]$2780 - attribute \src "libresoc.v:46145.3-46153.6" - wire $1\wr_pick_dly$1388$next[0:0]$2783 - attribute \src "libresoc.v:46183.3-46191.6" - wire $1\wr_pick_dly$1404$next[0:0]$2791 - attribute \src "libresoc.v:46221.3-46229.6" - wire $1\wr_pick_dly$1438$next[0:0]$2795 - attribute \src "libresoc.v:46230.3-46238.6" - wire $1\wr_pick_dly$1454$next[0:0]$2798 - attribute \src "libresoc.v:46268.3-46276.6" - wire $1\wr_pick_dly$1470$next[0:0]$2802 - attribute \src "libresoc.v:46306.3-46314.6" - wire $1\wr_pick_dly$1486$next[0:0]$2806 - attribute \src "libresoc.v:46344.3-46352.6" - wire $1\wr_pick_dly$1522$next[0:0]$2810 - attribute \src "libresoc.v:46353.3-46361.6" - wire $1\wr_pick_dly$1538$next[0:0]$2813 - attribute \src "libresoc.v:46392.3-46400.6" - wire $1\wr_pick_dly$1554$next[0:0]$2817 - attribute \src "libresoc.v:46401.3-46409.6" - wire $1\wr_pick_dly$1570$next[0:0]$2820 - attribute \src "libresoc.v:46410.3-46418.6" - wire $1\wr_pick_dly$1612$next[0:0]$2823 - attribute \src "libresoc.v:46448.3-46456.6" - wire $1\wr_pick_dly$1631$next[0:0]$2827 - attribute \src "libresoc.v:46486.3-46494.6" - wire $1\wr_pick_dly$1647$next[0:0]$2831 - attribute \src "libresoc.v:46495.3-46503.6" - wire $1\wr_pick_dly$1663$next[0:0]$2834 - attribute \src "libresoc.v:46533.3-46541.6" - wire $1\wr_pick_dly$1679$next[0:0]$2842 - attribute \src "libresoc.v:46571.3-46579.6" - wire $1\wr_pick_dly$1723$next[0:0]$2850 - attribute \src "libresoc.v:46580.3-46588.6" - wire $1\wr_pick_dly$1739$next[0:0]$2853 - attribute \src "libresoc.v:46618.3-46626.6" - wire $1\wr_pick_dly$1763$next[0:0]$2857 - attribute \src "libresoc.v:46656.3-46664.6" - wire $1\wr_pick_dly$1783$next[0:0]$2861 - attribute \src "libresoc.v:45644.3-45652.6" - wire $1\wr_pick_dly$967$next[0:0]$2716 - attribute \src "libresoc.v:45682.3-45690.6" - wire $1\wr_pick_dly$986$next[0:0]$2720 - attribute \src "libresoc.v:45635.3-45643.6" - wire $1\wr_pick_dly$next[0:0]$2713 - attribute \src "libresoc.v:40718.7-40718.25" + attribute \src "libresoc.v:46381.3-46389.6" + wire $1\wr_pick_dly$1000$next[0:0]$2754 + attribute \src "libresoc.v:46419.3-46427.6" + wire $1\wr_pick_dly$1021$next[0:0]$2758 + attribute \src "libresoc.v:46457.3-46465.6" + wire $1\wr_pick_dly$1039$next[0:0]$2762 + attribute \src "libresoc.v:46466.3-46474.6" + wire $1\wr_pick_dly$1061$next[0:0]$2765 + attribute \src "libresoc.v:46504.3-46512.6" + wire $1\wr_pick_dly$1081$next[0:0]$2769 + attribute \src "libresoc.v:46542.3-46550.6" + wire $1\wr_pick_dly$1101$next[0:0]$2773 + attribute \src "libresoc.v:46551.3-46559.6" + wire $1\wr_pick_dly$1120$next[0:0]$2776 + attribute \src "libresoc.v:46589.3-46597.6" + wire $1\wr_pick_dly$1138$next[0:0]$2780 + attribute \src "libresoc.v:46627.3-46635.6" + wire $1\wr_pick_dly$1211$next[0:0]$2784 + attribute \src "libresoc.v:46665.3-46673.6" + wire $1\wr_pick_dly$1239$next[0:0]$2788 + attribute \src "libresoc.v:46703.3-46711.6" + wire $1\wr_pick_dly$1259$next[0:0]$2792 + attribute \src "libresoc.v:46712.3-46720.6" + wire $1\wr_pick_dly$1279$next[0:0]$2795 + attribute \src "libresoc.v:46750.3-46758.6" + wire $1\wr_pick_dly$1299$next[0:0]$2799 + attribute \src "libresoc.v:46759.3-46767.6" + wire $1\wr_pick_dly$1319$next[0:0]$2802 + attribute \src "libresoc.v:46797.3-46805.6" + wire $1\wr_pick_dly$1339$next[0:0]$2806 + attribute \src "libresoc.v:46835.3-46843.6" + wire $1\wr_pick_dly$1386$next[0:0]$2814 + attribute \src "libresoc.v:46873.3-46881.6" + wire $1\wr_pick_dly$1402$next[0:0]$2822 + attribute \src "libresoc.v:46882.3-46890.6" + wire $1\wr_pick_dly$1418$next[0:0]$2825 + attribute \src "libresoc.v:46920.3-46928.6" + wire $1\wr_pick_dly$1452$next[0:0]$2829 + attribute \src "libresoc.v:46958.3-46966.6" + wire $1\wr_pick_dly$1468$next[0:0]$2833 + attribute \src "libresoc.v:46967.3-46975.6" + wire $1\wr_pick_dly$1484$next[0:0]$2836 + attribute \src "libresoc.v:47005.3-47013.6" + wire $1\wr_pick_dly$1500$next[0:0]$2840 + attribute \src "libresoc.v:47043.3-47051.6" + wire $1\wr_pick_dly$1536$next[0:0]$2844 + attribute \src "libresoc.v:47052.3-47060.6" + wire $1\wr_pick_dly$1552$next[0:0]$2847 + attribute \src "libresoc.v:47091.3-47099.6" + wire $1\wr_pick_dly$1568$next[0:0]$2851 + attribute \src "libresoc.v:47100.3-47108.6" + wire $1\wr_pick_dly$1584$next[0:0]$2854 + attribute \src "libresoc.v:47109.3-47117.6" + wire $1\wr_pick_dly$1626$next[0:0]$2857 + attribute \src "libresoc.v:47147.3-47155.6" + wire $1\wr_pick_dly$1645$next[0:0]$2861 + attribute \src "libresoc.v:47185.3-47193.6" + wire $1\wr_pick_dly$1661$next[0:0]$2865 + attribute \src "libresoc.v:47194.3-47202.6" + wire $1\wr_pick_dly$1677$next[0:0]$2868 + attribute \src "libresoc.v:47232.3-47240.6" + wire $1\wr_pick_dly$1693$next[0:0]$2876 + attribute \src "libresoc.v:47270.3-47278.6" + wire $1\wr_pick_dly$1737$next[0:0]$2884 + attribute \src "libresoc.v:47308.3-47316.6" + wire $1\wr_pick_dly$1753$next[0:0]$2888 + attribute \src "libresoc.v:47317.3-47325.6" + wire $1\wr_pick_dly$1777$next[0:0]$2891 + attribute \src "libresoc.v:47355.3-47363.6" + wire $1\wr_pick_dly$1797$next[0:0]$2895 + attribute \src "libresoc.v:46372.3-46380.6" + wire $1\wr_pick_dly$981$next[0:0]$2751 + attribute \src "libresoc.v:46334.3-46342.6" + wire $1\wr_pick_dly$next[0:0]$2747 + attribute \src "libresoc.v:41341.7-41341.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:45017.3-45037.6" - wire $2\core_terminate_o$next[0:0]$2599 - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45707.3-45727.6" + wire $2\core_terminate_o$next[0:0]$2630 + attribute \src "libresoc.v:45578.3-45668.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:44833.3-44859.6" - wire width 2 $2\counter$next[1:0]$2573 - attribute \src "libresoc.v:46839.3-46867.6" - wire $2\fus_cu_issue_i$10[0:0]$2871 - attribute \src "libresoc.v:47335.3-47363.6" - wire $2\fus_cu_issue_i$13[0:0]$2896 - attribute \src "libresoc.v:42720.3-42748.6" - wire $2\fus_cu_issue_i$16[0:0]$2365 - attribute \src "libresoc.v:43216.3-43244.6" - wire $2\fus_cu_issue_i$19[0:0]$2390 - attribute \src "libresoc.v:43538.3-43566.6" - wire $2\fus_cu_issue_i$22[0:0]$2409 - attribute \src "libresoc.v:43976.3-44004.6" - wire $2\fus_cu_issue_i$25[0:0]$2432 - attribute \src "libresoc.v:44414.3-44442.6" - wire $2\fus_cu_issue_i$28[0:0]$2455 - attribute \src "libresoc.v:46107.3-46135.6" - wire $2\fus_cu_issue_i$4[0:0]$2776 - attribute \src "libresoc.v:46504.3-46532.6" - wire $2\fus_cu_issue_i$7[0:0]$2838 - attribute \src "libresoc.v:45899.3-45927.6" + attribute \src "libresoc.v:45532.3-45558.6" + wire width 2 $2\counter$next[1:0]$2607 + attribute \src "libresoc.v:46806.3-46834.6" + wire $2\fus_cu_issue_i$11[0:0]$2810 + attribute \src "libresoc.v:47203.3-47231.6" + wire $2\fus_cu_issue_i$14[0:0]$2872 + attribute \src "libresoc.v:47567.3-47595.6" + wire $2\fus_cu_issue_i$17[0:0]$2906 + attribute \src "libresoc.v:48063.3-48091.6" + wire $2\fus_cu_issue_i$20[0:0]$2931 + attribute \src "libresoc.v:43390.3-43418.6" + wire $2\fus_cu_issue_i$23[0:0]$2398 + attribute \src "libresoc.v:43886.3-43914.6" + wire $2\fus_cu_issue_i$26[0:0]$2423 + attribute \src "libresoc.v:44208.3-44236.6" + wire $2\fus_cu_issue_i$29[0:0]$2442 + attribute \src "libresoc.v:44675.3-44703.6" + wire $2\fus_cu_issue_i$32[0:0]$2466 + attribute \src "libresoc.v:45113.3-45141.6" + wire $2\fus_cu_issue_i$35[0:0]$2489 + attribute \src "libresoc.v:46598.3-46626.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46868.3-46896.6" - wire width 4 $2\fus_cu_rdmaskn_i$12[3:0]$2876 - attribute \src "libresoc.v:47364.3-47392.6" - wire width 3 $2\fus_cu_rdmaskn_i$15[2:0]$2901 - attribute \src "libresoc.v:42749.3-42777.6" - wire width 6 $2\fus_cu_rdmaskn_i$18[5:0]$2370 - attribute \src "libresoc.v:43245.3-43273.6" - wire width 3 $2\fus_cu_rdmaskn_i$21[2:0]$2395 - attribute \src "libresoc.v:43567.3-43595.6" - wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2414 - attribute \src "libresoc.v:44005.3-44033.6" - wire width 5 $2\fus_cu_rdmaskn_i$27[4:0]$2437 - attribute \src "libresoc.v:44443.3-44471.6" - wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2460 - attribute \src "libresoc.v:46154.3-46182.6" - wire width 6 $2\fus_cu_rdmaskn_i$6[5:0]$2787 - attribute \src "libresoc.v:46542.3-46570.6" - wire width 3 $2\fus_cu_rdmaskn_i$9[2:0]$2846 - attribute \src "libresoc.v:45937.3-45965.6" + attribute \src "libresoc.v:46844.3-46872.6" + wire width 6 $2\fus_cu_rdmaskn_i$13[5:0]$2818 + attribute \src "libresoc.v:47241.3-47269.6" + wire width 3 $2\fus_cu_rdmaskn_i$16[2:0]$2880 + attribute \src "libresoc.v:47596.3-47624.6" + wire width 4 $2\fus_cu_rdmaskn_i$19[3:0]$2911 + attribute \src "libresoc.v:48092.3-48120.6" + wire width 3 $2\fus_cu_rdmaskn_i$22[2:0]$2936 + attribute \src "libresoc.v:43419.3-43447.6" + wire width 6 $2\fus_cu_rdmaskn_i$25[5:0]$2403 + attribute \src "libresoc.v:43915.3-43943.6" + wire width 3 $2\fus_cu_rdmaskn_i$28[2:0]$2428 + attribute \src "libresoc.v:44237.3-44265.6" + wire width 3 $2\fus_cu_rdmaskn_i$31[2:0]$2447 + attribute \src "libresoc.v:44704.3-44732.6" + wire width 5 $2\fus_cu_rdmaskn_i$34[4:0]$2471 + attribute \src "libresoc.v:45142.3-45170.6" + wire width 3 $2\fus_cu_rdmaskn_i$37[2:0]$2494 + attribute \src "libresoc.v:46636.3-46664.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:45814.3-45842.6" + attribute \src "libresoc.v:46513.3-46541.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45134.3-45162.6" + attribute \src "libresoc.v:45823.3-45851.6" wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45653.3-45681.6" + attribute \src "libresoc.v:46343.3-46371.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46560.3-46588.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45076.3-45104.6" + attribute \src "libresoc.v:45766.3-45794.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45443.3-45471.6" + attribute \src "libresoc.v:46142.3-46170.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45558.3-45586.6" + attribute \src "libresoc.v:46257.3-46285.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:45738.3-45766.6" + attribute \src "libresoc.v:46428.3-46456.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:45776.3-45804.6" + attribute \src "libresoc.v:46475.3-46503.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:46390.3-46418.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45606.3-45634.6" + attribute \src "libresoc.v:46305.3-46333.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:45500.3-45528.6" + attribute \src "libresoc.v:46190.3-46218.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46192.3-46220.6" + attribute \src "libresoc.v:46891.3-46919.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46277.3-46305.6" + attribute \src "libresoc.v:46976.3-47004.6" wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46315.3-46343.6" + attribute \src "libresoc.v:47014.3-47042.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46239.3-46267.6" + attribute \src "libresoc.v:46929.3-46957.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46457.3-46485.6" + attribute \src "libresoc.v:47156.3-47184.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46419.3-46447.6" + attribute \src "libresoc.v:47118.3-47146.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46022.3-46050.6" + attribute \src "libresoc.v:46721.3-46749.6" wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46069.3-46097.6" + attribute \src "libresoc.v:46768.3-46796.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:45984.3-46012.6" + attribute \src "libresoc.v:46674.3-46702.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43158.3-43186.6" + attribute \src "libresoc.v:43828.3-43856.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:42807.3-42835.6" + attribute \src "libresoc.v:43477.3-43505.6" wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:42984.3-43012.6" + attribute \src "libresoc.v:43654.3-43682.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43187.3-43215.6" + attribute \src "libresoc.v:43857.3-43885.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:42778.3-42806.6" + attribute \src "libresoc.v:43448.3-43476.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:42926.3-42954.6" + attribute \src "libresoc.v:43596.3-43624.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43013.3-43041.6" + attribute \src "libresoc.v:43683.3-43711.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43100.3-43128.6" + attribute \src "libresoc.v:43770.3-43798.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43129.3-43157.6" + attribute \src "libresoc.v:43799.3-43827.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43071.3-43099.6" + attribute \src "libresoc.v:43741.3-43769.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43042.3-43070.6" + attribute \src "libresoc.v:43712.3-43740.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:42955.3-42983.6" + attribute \src "libresoc.v:43625.3-43653.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47277.3-47305.6" + attribute \src "libresoc.v:48005.3-48033.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:46926.3-46954.6" + attribute \src "libresoc.v:47654.3-47682.6" wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47103.3-47131.6" + attribute \src "libresoc.v:47831.3-47859.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47306.3-47334.6" + attribute \src "libresoc.v:48034.3-48062.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:46897.3-46925.6" + attribute \src "libresoc.v:47625.3-47653.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47045.3-47073.6" + attribute \src "libresoc.v:47773.3-47801.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47132.3-47160.6" + attribute \src "libresoc.v:47860.3-47888.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47219.3-47247.6" + attribute \src "libresoc.v:47947.3-47975.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47248.3-47276.6" + attribute \src "libresoc.v:47976.3-48004.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47190.3-47218.6" + attribute \src "libresoc.v:47918.3-47946.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47161.3-47189.6" + attribute \src "libresoc.v:47889.3-47917.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47074.3-47102.6" + attribute \src "libresoc.v:47802.3-47830.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43303.3-43331.6" + attribute \src "libresoc.v:43973.3-44001.6" wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43509.3-43537.6" + attribute \src "libresoc.v:44179.3-44207.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43274.3-43302.6" + attribute \src "libresoc.v:43944.3-43972.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43451.3-43479.6" + attribute \src "libresoc.v:44121.3-44149.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43480.3-43508.6" + attribute \src "libresoc.v:44150.3-44178.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43422.3-43450.6" + attribute \src "libresoc.v:44092.3-44120.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" + attribute \src "libresoc.v:44295.3-44323.6" wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:43773.3-43801.6" + attribute \src "libresoc.v:44472.3-44500.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:43831.3-43859.6" + attribute \src "libresoc.v:44530.3-44558.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:43947.3-43975.6" + attribute \src "libresoc.v:44646.3-44674.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:43596.3-43624.6" + attribute \src "libresoc.v:44266.3-44294.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:43889.3-43917.6" + attribute \src "libresoc.v:44443.3-44471.6" + wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44588.3-44616.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:43918.3-43946.6" + attribute \src "libresoc.v:44617.3-44645.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:43802.3-43830.6" + attribute \src "libresoc.v:44501.3-44529.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:43860.3-43888.6" + attribute \src "libresoc.v:44559.3-44587.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:43744.3-43772.6" + attribute \src "libresoc.v:44414.3-44442.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47422.3-47450.6" + attribute \src "libresoc.v:48150.3-48178.6" wire width 12 $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47451.3-47479.6" + attribute \src "libresoc.v:43332.3-43360.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:48121.3-48149.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:42691.3-42719.6" + attribute \src "libresoc.v:43361.3-43389.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:46723.3-46751.6" + attribute \src "libresoc.v:47422.3-47450.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:46627.3-46655.6" + attribute \src "libresoc.v:47326.3-47354.6" wire width 12 $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:46665.3-46693.6" + attribute \src "libresoc.v:47364.3-47392.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:46589.3-46617.6" + attribute \src "libresoc.v:47279.3-47307.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:46752.3-46780.6" + attribute \src "libresoc.v:47451.3-47479.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:47538.3-47566.6" + wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47393.3-47421.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:46810.3-46838.6" + attribute \src "libresoc.v:47509.3-47537.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:46781.3-46809.6" - wire width 7 $2\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "libresoc.v:44298.3-44326.6" + attribute \src "libresoc.v:47480.3-47508.6" + wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44997.3-45025.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44269.3-44297.6" + attribute \src "libresoc.v:44968.3-44996.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44063.3-44091.6" + attribute \src "libresoc.v:44762.3-44790.6" wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44385.3-44413.6" + attribute \src "libresoc.v:45084.3-45112.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44034.3-44062.6" + attribute \src "libresoc.v:44733.3-44761.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44211.3-44239.6" + attribute \src "libresoc.v:44910.3-44938.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44240.3-44268.6" + attribute \src "libresoc.v:44939.3-44967.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44356.3-44384.6" + attribute \src "libresoc.v:45055.3-45083.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44327.3-44355.6" + attribute \src "libresoc.v:45026.3-45054.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44122.3-44150.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45017.3-45037.6" - wire $3\core_terminate_o$next[0:0]$2600 - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45707.3-45727.6" + wire $3\core_terminate_o$next[0:0]$2631 + attribute \src "libresoc.v:45578.3-45668.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:44833.3-44859.6" - wire width 2 $3\counter$next[1:0]$2574 - attribute \src "libresoc.v:46839.3-46867.6" - wire $3\fus_cu_issue_i$10[0:0]$2872 - attribute \src "libresoc.v:47335.3-47363.6" - wire $3\fus_cu_issue_i$13[0:0]$2897 - attribute \src "libresoc.v:42720.3-42748.6" - wire $3\fus_cu_issue_i$16[0:0]$2366 - attribute \src "libresoc.v:43216.3-43244.6" - wire $3\fus_cu_issue_i$19[0:0]$2391 - attribute \src "libresoc.v:43538.3-43566.6" - wire $3\fus_cu_issue_i$22[0:0]$2410 - attribute \src "libresoc.v:43976.3-44004.6" - wire $3\fus_cu_issue_i$25[0:0]$2433 - attribute \src "libresoc.v:44414.3-44442.6" - wire $3\fus_cu_issue_i$28[0:0]$2456 - attribute \src "libresoc.v:46107.3-46135.6" - wire $3\fus_cu_issue_i$4[0:0]$2777 - attribute \src "libresoc.v:46504.3-46532.6" - wire $3\fus_cu_issue_i$7[0:0]$2839 - attribute \src "libresoc.v:45899.3-45927.6" + attribute \src "libresoc.v:45532.3-45558.6" + wire width 2 $3\counter$next[1:0]$2608 + attribute \src "libresoc.v:46806.3-46834.6" + wire $3\fus_cu_issue_i$11[0:0]$2811 + attribute \src "libresoc.v:47203.3-47231.6" + wire $3\fus_cu_issue_i$14[0:0]$2873 + attribute \src "libresoc.v:47567.3-47595.6" + wire $3\fus_cu_issue_i$17[0:0]$2907 + attribute \src "libresoc.v:48063.3-48091.6" + wire $3\fus_cu_issue_i$20[0:0]$2932 + attribute \src "libresoc.v:43390.3-43418.6" + wire $3\fus_cu_issue_i$23[0:0]$2399 + attribute \src "libresoc.v:43886.3-43914.6" + wire $3\fus_cu_issue_i$26[0:0]$2424 + attribute \src "libresoc.v:44208.3-44236.6" + wire $3\fus_cu_issue_i$29[0:0]$2443 + attribute \src "libresoc.v:44675.3-44703.6" + wire $3\fus_cu_issue_i$32[0:0]$2467 + attribute \src "libresoc.v:45113.3-45141.6" + wire $3\fus_cu_issue_i$35[0:0]$2490 + attribute \src "libresoc.v:46598.3-46626.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46868.3-46896.6" - wire width 4 $3\fus_cu_rdmaskn_i$12[3:0]$2877 - attribute \src "libresoc.v:47364.3-47392.6" - wire width 3 $3\fus_cu_rdmaskn_i$15[2:0]$2902 - attribute \src "libresoc.v:42749.3-42777.6" - wire width 6 $3\fus_cu_rdmaskn_i$18[5:0]$2371 - attribute \src "libresoc.v:43245.3-43273.6" - wire width 3 $3\fus_cu_rdmaskn_i$21[2:0]$2396 - attribute \src "libresoc.v:43567.3-43595.6" - wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2415 - attribute \src "libresoc.v:44005.3-44033.6" - wire width 5 $3\fus_cu_rdmaskn_i$27[4:0]$2438 - attribute \src "libresoc.v:44443.3-44471.6" - wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2461 - attribute \src "libresoc.v:46154.3-46182.6" - wire width 6 $3\fus_cu_rdmaskn_i$6[5:0]$2788 - attribute \src "libresoc.v:46542.3-46570.6" - wire width 3 $3\fus_cu_rdmaskn_i$9[2:0]$2847 - attribute \src "libresoc.v:45937.3-45965.6" + attribute \src "libresoc.v:46844.3-46872.6" + wire width 6 $3\fus_cu_rdmaskn_i$13[5:0]$2819 + attribute \src "libresoc.v:47241.3-47269.6" + wire width 3 $3\fus_cu_rdmaskn_i$16[2:0]$2881 + attribute \src "libresoc.v:47596.3-47624.6" + wire width 4 $3\fus_cu_rdmaskn_i$19[3:0]$2912 + attribute \src "libresoc.v:48092.3-48120.6" + wire width 3 $3\fus_cu_rdmaskn_i$22[2:0]$2937 + attribute \src "libresoc.v:43419.3-43447.6" + wire width 6 $3\fus_cu_rdmaskn_i$25[5:0]$2404 + attribute \src "libresoc.v:43915.3-43943.6" + wire width 3 $3\fus_cu_rdmaskn_i$28[2:0]$2429 + attribute \src "libresoc.v:44237.3-44265.6" + wire width 3 $3\fus_cu_rdmaskn_i$31[2:0]$2448 + attribute \src "libresoc.v:44704.3-44732.6" + wire width 5 $3\fus_cu_rdmaskn_i$34[4:0]$2472 + attribute \src "libresoc.v:45142.3-45170.6" + wire width 3 $3\fus_cu_rdmaskn_i$37[2:0]$2495 + attribute \src "libresoc.v:46636.3-46664.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:45814.3-45842.6" + attribute \src "libresoc.v:46513.3-46541.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45134.3-45162.6" + attribute \src "libresoc.v:45823.3-45851.6" wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45201.3-45230.6" + attribute \src "libresoc.v:45890.3-45919.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45653.3-45681.6" + attribute \src "libresoc.v:46343.3-46371.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:45861.3-45889.6" + attribute \src "libresoc.v:46560.3-46588.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45076.3-45104.6" + attribute \src "libresoc.v:45766.3-45794.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45443.3-45471.6" + attribute \src "libresoc.v:46142.3-46170.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45558.3-45586.6" + attribute \src "libresoc.v:46257.3-46285.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:45738.3-45766.6" + attribute \src "libresoc.v:46428.3-46456.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:45776.3-45804.6" + attribute \src "libresoc.v:46475.3-46503.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:45356.3-45385.6" + attribute \src "libresoc.v:46055.3-46084.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45691.3-45719.6" + attribute \src "libresoc.v:46390.3-46418.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45269.3-45298.6" + attribute \src "libresoc.v:45968.3-45997.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45606.3-45634.6" + attribute \src "libresoc.v:46305.3-46333.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:45500.3-45528.6" + attribute \src "libresoc.v:46190.3-46218.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46192.3-46220.6" + attribute \src "libresoc.v:46891.3-46919.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46277.3-46305.6" + attribute \src "libresoc.v:46976.3-47004.6" wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:46362.3-46391.6" + attribute \src "libresoc.v:47061.3-47090.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46315.3-46343.6" + attribute \src "libresoc.v:47014.3-47042.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46239.3-46267.6" + attribute \src "libresoc.v:46929.3-46957.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46457.3-46485.6" + attribute \src "libresoc.v:47156.3-47184.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46419.3-46447.6" + attribute \src "libresoc.v:47118.3-47146.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46022.3-46050.6" + attribute \src "libresoc.v:46721.3-46749.6" wire width 12 $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46069.3-46097.6" + attribute \src "libresoc.v:46768.3-46796.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:45984.3-46012.6" + attribute \src "libresoc.v:46674.3-46702.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43158.3-43186.6" + attribute \src "libresoc.v:43828.3-43856.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:42807.3-42835.6" + attribute \src "libresoc.v:43477.3-43505.6" wire width 12 $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:42836.3-42865.6" + attribute \src "libresoc.v:43506.3-43535.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:42984.3-43012.6" + attribute \src "libresoc.v:43654.3-43682.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43187.3-43215.6" + attribute \src "libresoc.v:43857.3-43885.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:42778.3-42806.6" + attribute \src "libresoc.v:43448.3-43476.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:42926.3-42954.6" + attribute \src "libresoc.v:43596.3-43624.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43013.3-43041.6" + attribute \src "libresoc.v:43683.3-43711.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43100.3-43128.6" + attribute \src "libresoc.v:43770.3-43798.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43129.3-43157.6" + attribute \src "libresoc.v:43799.3-43827.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:42896.3-42925.6" + attribute \src "libresoc.v:43566.3-43595.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43071.3-43099.6" + attribute \src "libresoc.v:43741.3-43769.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:42866.3-42895.6" + attribute \src "libresoc.v:43536.3-43565.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43042.3-43070.6" + attribute \src "libresoc.v:43712.3-43740.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:42955.3-42983.6" + attribute \src "libresoc.v:43625.3-43653.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:47277.3-47305.6" + attribute \src "libresoc.v:48005.3-48033.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:46926.3-46954.6" + attribute \src "libresoc.v:47654.3-47682.6" wire width 12 $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:46955.3-46984.6" + attribute \src "libresoc.v:47683.3-47712.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47103.3-47131.6" + attribute \src "libresoc.v:47831.3-47859.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47306.3-47334.6" + attribute \src "libresoc.v:48034.3-48062.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:46897.3-46925.6" + attribute \src "libresoc.v:47625.3-47653.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47045.3-47073.6" + attribute \src "libresoc.v:47773.3-47801.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47132.3-47160.6" + attribute \src "libresoc.v:47860.3-47888.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47219.3-47247.6" + attribute \src "libresoc.v:47947.3-47975.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47248.3-47276.6" + attribute \src "libresoc.v:47976.3-48004.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47015.3-47044.6" + attribute \src "libresoc.v:47743.3-47772.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47190.3-47218.6" + attribute \src "libresoc.v:47918.3-47946.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:46985.3-47014.6" + attribute \src "libresoc.v:47713.3-47742.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47161.3-47189.6" + attribute \src "libresoc.v:47889.3-47917.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47074.3-47102.6" + attribute \src "libresoc.v:47802.3-47830.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43303.3-43331.6" + attribute \src "libresoc.v:43973.3-44001.6" wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:43332.3-43361.6" + attribute \src "libresoc.v:44002.3-44031.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43509.3-43537.6" + attribute \src "libresoc.v:44179.3-44207.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43274.3-43302.6" + attribute \src "libresoc.v:43944.3-43972.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43451.3-43479.6" + attribute \src "libresoc.v:44121.3-44149.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43480.3-43508.6" + attribute \src "libresoc.v:44150.3-44178.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:43392.3-43421.6" + attribute \src "libresoc.v:44062.3-44091.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:43362.3-43391.6" + attribute \src "libresoc.v:44032.3-44061.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43422.3-43450.6" + attribute \src "libresoc.v:44092.3-44120.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" + attribute \src "libresoc.v:44295.3-44323.6" wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:43654.3-43683.6" + attribute \src "libresoc.v:44324.3-44353.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:43773.3-43801.6" + attribute \src "libresoc.v:44472.3-44500.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:43831.3-43859.6" + attribute \src "libresoc.v:44530.3-44558.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:43947.3-43975.6" + attribute \src "libresoc.v:44646.3-44674.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:43596.3-43624.6" + attribute \src "libresoc.v:44266.3-44294.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:43889.3-43917.6" + attribute \src "libresoc.v:44443.3-44471.6" + wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44588.3-44616.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:43918.3-43946.6" + attribute \src "libresoc.v:44617.3-44645.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:43714.3-43743.6" + attribute \src "libresoc.v:44384.3-44413.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:43802.3-43830.6" + attribute \src "libresoc.v:44501.3-44529.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:43860.3-43888.6" + attribute \src "libresoc.v:44559.3-44587.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:43684.3-43713.6" + attribute \src "libresoc.v:44354.3-44383.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:43744.3-43772.6" + attribute \src "libresoc.v:44414.3-44442.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:47422.3-47450.6" + attribute \src "libresoc.v:48150.3-48178.6" wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47451.3-47479.6" + attribute \src "libresoc.v:43332.3-43360.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47393.3-47421.6" + attribute \src "libresoc.v:48121.3-48149.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:42691.3-42719.6" + attribute \src "libresoc.v:43361.3-43389.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:46723.3-46751.6" + attribute \src "libresoc.v:47422.3-47450.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:46627.3-46655.6" + attribute \src "libresoc.v:47326.3-47354.6" wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:46665.3-46693.6" + attribute \src "libresoc.v:47364.3-47392.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:46589.3-46617.6" + attribute \src "libresoc.v:47279.3-47307.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:46752.3-46780.6" + attribute \src "libresoc.v:47451.3-47479.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:47538.3-47566.6" + wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47393.3-47421.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:46810.3-46838.6" + attribute \src "libresoc.v:47509.3-47537.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:46781.3-46809.6" - wire width 7 $3\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "libresoc.v:44298.3-44326.6" + attribute \src "libresoc.v:47480.3-47508.6" + wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:44997.3-45025.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44269.3-44297.6" + attribute \src "libresoc.v:44968.3-44996.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44063.3-44091.6" + attribute \src "libresoc.v:44762.3-44790.6" wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44092.3-44121.6" + attribute \src "libresoc.v:44791.3-44820.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44385.3-44413.6" + attribute \src "libresoc.v:45084.3-45112.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44034.3-44062.6" + attribute \src "libresoc.v:44733.3-44761.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44211.3-44239.6" + attribute \src "libresoc.v:44910.3-44938.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44240.3-44268.6" + attribute \src "libresoc.v:44939.3-44967.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44356.3-44384.6" + attribute \src "libresoc.v:45055.3-45083.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44181.3-44210.6" + attribute \src "libresoc.v:44880.3-44909.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44151.3-44180.6" + attribute \src "libresoc.v:44850.3-44879.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44327.3-44355.6" + attribute \src "libresoc.v:45026.3-45054.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44122.3-44150.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:44833.3-44859.6" - wire width 2 $4\counter$next[1:0]$2575 - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45532.3-45558.6" + wire width 2 $4\counter$next[1:0]$2609 + attribute \src "libresoc.v:45578.3-45668.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:44888.3-44978.6" + attribute \src "libresoc.v:45578.3-45668.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:41098.20-41098.122" - wire $and$libresoc.v:41098$1515_Y - attribute \src "libresoc.v:41099.20-41099.126" - wire $and$libresoc.v:41099$1516_Y - attribute \src "libresoc.v:41101.20-41101.110" - wire $and$libresoc.v:41101$1518_Y - attribute \src "libresoc.v:41102.20-41102.123" - wire $and$libresoc.v:41102$1519_Y - attribute \src "libresoc.v:41104.20-41104.122" - wire $and$libresoc.v:41104$1521_Y - attribute \src "libresoc.v:41105.20-41105.126" - wire $and$libresoc.v:41105$1522_Y - attribute \src "libresoc.v:41107.20-41107.110" - wire $and$libresoc.v:41107$1524_Y - attribute \src "libresoc.v:41108.20-41108.123" - wire $and$libresoc.v:41108$1525_Y - attribute \src "libresoc.v:41110.20-41110.122" - wire $and$libresoc.v:41110$1527_Y - attribute \src "libresoc.v:41111.20-41111.126" - wire $and$libresoc.v:41111$1528_Y - attribute \src "libresoc.v:41113.20-41113.110" - wire $and$libresoc.v:41113$1530_Y - attribute \src "libresoc.v:41114.20-41114.123" - wire $and$libresoc.v:41114$1531_Y - attribute \src "libresoc.v:41116.20-41116.122" - wire $and$libresoc.v:41116$1533_Y - attribute \src "libresoc.v:41117.20-41117.126" - wire $and$libresoc.v:41117$1534_Y - attribute \src "libresoc.v:41119.20-41119.110" - wire $and$libresoc.v:41119$1536_Y - attribute \src "libresoc.v:41120.20-41120.123" - wire $and$libresoc.v:41120$1537_Y - attribute \src "libresoc.v:41122.20-41122.123" - wire $and$libresoc.v:41122$1539_Y - attribute \src "libresoc.v:41123.20-41123.126" - wire $and$libresoc.v:41123$1540_Y - attribute \src "libresoc.v:41125.20-41125.110" - wire $and$libresoc.v:41125$1542_Y - attribute \src "libresoc.v:41126.20-41126.123" - wire $and$libresoc.v:41126$1543_Y - attribute \src "libresoc.v:41128.20-41128.113" - wire $and$libresoc.v:41128$1545_Y - attribute \src "libresoc.v:41129.20-41129.126" - wire $and$libresoc.v:41129$1546_Y - attribute \src "libresoc.v:41131.20-41131.110" - wire $and$libresoc.v:41131$1548_Y - attribute \src "libresoc.v:41132.20-41132.123" - wire $and$libresoc.v:41132$1549_Y - attribute \src "libresoc.v:41134.20-41134.114" - wire $and$libresoc.v:41134$1551_Y - attribute \src "libresoc.v:41135.20-41135.126" - wire $and$libresoc.v:41135$1552_Y - attribute \src "libresoc.v:41137.20-41137.110" - wire $and$libresoc.v:41137$1554_Y - attribute \src "libresoc.v:41138.20-41138.123" - wire $and$libresoc.v:41138$1555_Y - attribute \src "libresoc.v:41167.20-41167.122" - wire $and$libresoc.v:41167$1584_Y - attribute \src "libresoc.v:41168.20-41168.128" - wire $and$libresoc.v:41168$1585_Y - attribute \src "libresoc.v:41169.20-41169.133" - wire $and$libresoc.v:41169$1586_Y - attribute \src "libresoc.v:41171.20-41171.110" - wire $and$libresoc.v:41171$1588_Y - attribute \src "libresoc.v:41172.20-41172.128" - wire $and$libresoc.v:41172$1589_Y - attribute \src "libresoc.v:41174.20-41174.116" - wire $and$libresoc.v:41174$1591_Y - attribute \src "libresoc.v:41175.20-41175.123" - wire $and$libresoc.v:41175$1592_Y - attribute \src "libresoc.v:41176.20-41176.128" - wire $and$libresoc.v:41176$1593_Y - attribute \src "libresoc.v:41177.20-41177.128" - wire $and$libresoc.v:41177$1594_Y - attribute \src "libresoc.v:41178.20-41178.128" - wire $and$libresoc.v:41178$1595_Y - attribute \src "libresoc.v:41179.20-41179.128" - wire $and$libresoc.v:41179$1596_Y - attribute \src "libresoc.v:41180.20-41180.129" - wire $and$libresoc.v:41180$1597_Y - attribute \src "libresoc.v:41181.20-41181.130" - wire $and$libresoc.v:41181$1598_Y - attribute \src "libresoc.v:41183.20-41183.110" - wire $and$libresoc.v:41183$1600_Y - attribute \src "libresoc.v:41184.20-41184.125" - wire $and$libresoc.v:41184$1601_Y - attribute \src "libresoc.v:41188.20-41188.125" - wire $and$libresoc.v:41188$1605_Y - attribute \src "libresoc.v:41189.20-41189.130" - wire $and$libresoc.v:41189$1606_Y - attribute \src "libresoc.v:41191.20-41191.110" - wire $and$libresoc.v:41191$1608_Y - attribute \src "libresoc.v:41192.20-41192.125" - wire $and$libresoc.v:41192$1609_Y - attribute \src "libresoc.v:41196.20-41196.126" - wire $and$libresoc.v:41196$1613_Y - attribute \src "libresoc.v:41197.20-41197.130" - wire $and$libresoc.v:41197$1614_Y - attribute \src "libresoc.v:41199.20-41199.110" - wire $and$libresoc.v:41199$1616_Y - attribute \src "libresoc.v:41200.20-41200.125" - wire $and$libresoc.v:41200$1617_Y - attribute \src "libresoc.v:41204.20-41204.126" - wire $and$libresoc.v:41204$1621_Y - attribute \src "libresoc.v:41205.20-41205.130" - wire $and$libresoc.v:41205$1622_Y - attribute \src "libresoc.v:41207.20-41207.110" - wire $and$libresoc.v:41207$1624_Y - attribute \src "libresoc.v:41208.20-41208.125" - wire $and$libresoc.v:41208$1625_Y - attribute \src "libresoc.v:41212.20-41212.126" - wire $and$libresoc.v:41212$1629_Y - attribute \src "libresoc.v:41213.20-41213.130" - wire $and$libresoc.v:41213$1630_Y - attribute \src "libresoc.v:41215.20-41215.110" - wire $and$libresoc.v:41215$1632_Y - attribute \src "libresoc.v:41216.20-41216.125" - wire $and$libresoc.v:41216$1633_Y - attribute \src "libresoc.v:41220.20-41220.126" - wire $and$libresoc.v:41220$1637_Y - attribute \src "libresoc.v:41221.20-41221.130" - wire $and$libresoc.v:41221$1638_Y - attribute \src "libresoc.v:41223.20-41223.110" - wire $and$libresoc.v:41223$1640_Y - attribute \src "libresoc.v:41224.20-41224.125" - wire $and$libresoc.v:41224$1641_Y - attribute \src "libresoc.v:41238.20-41238.118" - wire $and$libresoc.v:41238$1655_Y - attribute \src "libresoc.v:41239.20-41239.123" - wire $and$libresoc.v:41239$1656_Y - attribute \src "libresoc.v:41240.20-41240.128" - wire $and$libresoc.v:41240$1657_Y - attribute \src "libresoc.v:41241.20-41241.129" - wire $and$libresoc.v:41241$1658_Y - attribute \src "libresoc.v:41242.20-41242.136" - wire $and$libresoc.v:41242$1659_Y - attribute \src "libresoc.v:41244.20-41244.110" - wire $and$libresoc.v:41244$1661_Y - attribute \src "libresoc.v:41245.20-41245.128" - wire $and$libresoc.v:41245$1662_Y - attribute \src "libresoc.v:41247.20-41247.128" - wire $and$libresoc.v:41247$1664_Y - attribute \src "libresoc.v:41248.20-41248.136" - wire $and$libresoc.v:41248$1665_Y - attribute \src "libresoc.v:41250.20-41250.110" - wire $and$libresoc.v:41250$1667_Y - attribute \src "libresoc.v:41251.20-41251.128" - wire $and$libresoc.v:41251$1668_Y - attribute \src "libresoc.v:41253.20-41253.128" - wire $and$libresoc.v:41253$1670_Y - attribute \src "libresoc.v:41254.20-41254.136" - wire $and$libresoc.v:41254$1671_Y - attribute \src "libresoc.v:41256.20-41256.110" - wire $and$libresoc.v:41256$1673_Y - attribute \src "libresoc.v:41257.20-41257.128" - wire $and$libresoc.v:41257$1674_Y - attribute \src "libresoc.v:41264.20-41264.118" - wire $and$libresoc.v:41264$1682_Y - attribute \src "libresoc.v:41265.20-41265.123" - wire $and$libresoc.v:41265$1683_Y - attribute \src "libresoc.v:41266.20-41266.128" - wire $and$libresoc.v:41266$1684_Y - attribute \src "libresoc.v:41267.20-41267.128" - wire $and$libresoc.v:41267$1685_Y - attribute \src "libresoc.v:41268.20-41268.128" - wire $and$libresoc.v:41268$1686_Y - attribute \src "libresoc.v:41269.20-41269.136" - wire $and$libresoc.v:41269$1687_Y - attribute \src "libresoc.v:41271.20-41271.110" - wire $and$libresoc.v:41271$1689_Y - attribute \src "libresoc.v:41272.20-41272.128" - wire $and$libresoc.v:41272$1690_Y - attribute \src "libresoc.v:41274.20-41274.128" - wire $and$libresoc.v:41274$1692_Y - attribute \src "libresoc.v:41275.20-41275.136" - wire $and$libresoc.v:41275$1693_Y - attribute \src "libresoc.v:41277.20-41277.110" - wire $and$libresoc.v:41277$1695_Y - attribute \src "libresoc.v:41278.20-41278.128" - wire $and$libresoc.v:41278$1696_Y - attribute \src "libresoc.v:41280.20-41280.128" - wire $and$libresoc.v:41280$1698_Y - attribute \src "libresoc.v:41281.20-41281.136" - wire $and$libresoc.v:41281$1699_Y - attribute \src "libresoc.v:41283.20-41283.110" - wire $and$libresoc.v:41283$1701_Y - attribute \src "libresoc.v:41284.20-41284.128" - wire $and$libresoc.v:41284$1702_Y - attribute \src "libresoc.v:41286.20-41286.128" - wire $and$libresoc.v:41286$1704_Y - attribute \src "libresoc.v:41287.20-41287.136" - wire $and$libresoc.v:41287$1705_Y - attribute \src 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2 \$1772 + wire \$1780 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - wire width 4 \$1774 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - wire \$1776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - wire \$1778 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire \$1781 + wire \$1783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire width 2 \$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + wire width 4 \$1788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + wire \$1790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + wire \$1792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + wire \$1795 attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - wire width 12 \$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - wire \$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - wire width 12 \$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - wire \$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - wire width 3 \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - wire width 3 \$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - wire \$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 4 \$207 + wire \$1800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + wire \$1803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + wire width 10 \$1806 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire \$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + wire width 12 \$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + wire \$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + wire width 3 \$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + wire width 3 \$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + wire \$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 4 \$221 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$208 + wire \$222 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 \$210 + wire width 3 \$224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$212 + wire \$226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$214 + wire \$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire \$216 + wire \$230 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire \$218 + wire \$232 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire \$220 + wire \$234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 \$222 + wire width 3 \$236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$224 + wire \$238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 6 \$229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 3 \$231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 4 \$233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 3 \$235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire \$246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 6 \$249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 6 \$243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 3 \$245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 4 \$247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 3 \$249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" @@ -60286,37 +61153,37 @@ module \core wire \$258 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 6 \$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$274 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire \$262 + wire \$276 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 3 \$264 + wire width 3 \$278 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire \$266 + wire \$280 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire \$268 + wire \$282 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire \$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 \$272 + wire \$284 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$274 + wire width 3 \$286 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 3 \$279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 \$282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire \$286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" wire \$290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" wire width 3 \$293 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$294 @@ -60330,8 +61197,8 @@ module \core wire \$302 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 5 \$307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 3 \$307 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" wire \$308 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" @@ -60344,834 +61211,858 @@ module \core wire \$316 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" wire \$318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 5 \$321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire width 3 \$324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + wire \$328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire \$332 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire \$320 + wire \$334 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 \$322 + wire width 3 \$336 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$324 + wire \$338 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire \$326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:217" - wire width 3 \$329 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - wire \$335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - wire \$337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - wire \$339 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + wire \$340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" + wire width 3 \$343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$345 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + wire \$353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire width 5 \$355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$357 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire width 5 \$367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$379 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + wire \$377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire width 5 \$379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$387 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - wire \$391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + wire \$389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + wire width 5 \$391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - wire \$573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - wire \$575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - wire \$577 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" wire width 5 \$579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" wire \$581 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$583 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$585 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$587 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" wire \$589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - wire width 5 \$591 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + wire \$591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" wire width 5 \$593 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$595 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" wire \$597 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 \$599 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 16 \addr_en_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 16 \addr_en_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 16 \addr_en_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 8 \addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 5 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" wire \addr_en_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire input 55 \bigendian_i + wire input 63 \bigendian_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 8 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 7 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 input 39 \core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 input 50 \core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 51 \core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 input 52 \core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 input 58 \core_core_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 59 \core_core_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 input 60 \core_core_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 49 \core_core_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 50 \core_core_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 51 \core_core_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 52 \core_core_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 53 \core_core_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 54 \core_core_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 55 \core_core_exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 56 \core_core_exc_$signal$9 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61185,15 +62076,15 @@ module \core attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 input 42 \core_core_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 input 47 \core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 input 40 \core_core_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -61269,70 +62160,68 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 input 41 \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire input 53 \core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire input 61 \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 input 38 \core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 45 \core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 46 \core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 43 \core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 44 \core_core_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 input 57 \core_core_trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 input 49 \core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 input 48 \core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 input 48 \core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 31 \core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 32 \core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 33 \core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 35 \core_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 34 \core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 36 \core_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 37 \core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 input 14 \core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 25 \core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 26 \core_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 27 \core_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 28 \core_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 29 \core_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 30 \core_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 57 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 65 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 input 15 \core_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 16 \core_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 input 17 \core_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 18 \core_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 input 19 \core_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 20 \core_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 input 13 \core_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" - wire input 1 \core_reset_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -61444,9 +62333,9 @@ module \core attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 input 22 \core_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 23 \core_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -61559,23 +62448,23 @@ module \core attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 input 21 \core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire output 12 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_terminate_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 input 24 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 83 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 92 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" wire width 2 \counter$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \cr_data_i @@ -61612,25 +62501,25 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 10 \data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 75 \dbus__ack + wire input 84 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 80 \dbus__adr + wire width 45 output 89 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 74 \dbus__cyc + wire output 83 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 79 \dbus__dat_r + wire width 64 input 88 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 82 \dbus__dat_w + wire width 64 output 91 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 76 \dbus__err + wire input 85 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 78 \dbus__sel + wire width 8 output 87 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 77 \dbus__stb + wire output 86 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 81 \dbus__we + wire output 90 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_ALU_ALU_ALU__data_len + wire width 4 \dec_ALU_ALU__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61645,19 +62534,19 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_ALU_ALU_ALU__fn_unit + wire width 12 \dec_ALU_ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_ALU_ALU_ALU__imm_data__data + wire width 64 \dec_ALU_ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__imm_data__ok + wire \dec_ALU_ALU__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_ALU_ALU_ALU__input_carry + wire width 2 \dec_ALU_ALU__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_ALU_ALU_ALU__insn + wire width 32 \dec_ALU_ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61733,35 +62622,35 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_ALU_ALU_ALU__insn_type + wire width 7 \dec_ALU_ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__invert_in + wire \dec_ALU_ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__invert_out + wire \dec_ALU_ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__is_32bit + wire \dec_ALU_ALU__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__is_signed + wire \dec_ALU_ALU__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__oe__oe + wire \dec_ALU_ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__oe__ok + wire \dec_ALU_ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__output_carry + wire \dec_ALU_ALU__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__rc__ok + wire \dec_ALU_ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__rc__rc + wire \dec_ALU_ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__write_cr0 + wire \dec_ALU_ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_ALU_ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_ALU_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_ALU_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_BRANCH_BRANCH_BRANCH__cia + wire width 64 \dec_BRANCH_BRANCH__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61776,13 +62665,13 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_BRANCH_BRANCH_BRANCH__fn_unit + wire width 12 \dec_BRANCH_BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data + wire width 64 \dec_BRANCH_BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + wire \dec_BRANCH_BRANCH__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn + wire width 32 \dec_BRANCH_BRANCH__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61858,14 +62747,14 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_BRANCH_BRANCH_BRANCH__insn_type + wire width 7 \dec_BRANCH_BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_BRANCH_BRANCH_BRANCH__is_32bit + wire \dec_BRANCH_BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_BRANCH_BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_BRANCH_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -61881,9 +62770,9 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_CR_CR_CR__fn_unit + wire width 12 \dec_CR_CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_CR_CR_CR__insn + wire width 32 \dec_CR_CR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -61959,13 +62848,13 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_CR_CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire width 7 \dec_CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_CR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_CR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_DIV_DIV_DIV__data_len + wire width 4 \dec_DIV_DIV__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -61980,19 +62869,19 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_DIV_DIV_DIV__fn_unit + wire width 12 \dec_DIV_DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_DIV_DIV_DIV__imm_data__data + wire width 64 \dec_DIV_DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__imm_data__ok + wire \dec_DIV_DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_DIV_DIV_DIV__input_carry + wire width 2 \dec_DIV_DIV__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_DIV_DIV_DIV__insn + wire width 32 \dec_DIV_DIV__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62068,37 +62957,37 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_DIV_DIV_DIV__insn_type + wire width 7 \dec_DIV_DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__invert_in + wire \dec_DIV_DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__invert_out + wire \dec_DIV_DIV__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__is_32bit + wire \dec_DIV_DIV__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__is_signed + wire \dec_DIV_DIV__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__oe__oe + wire \dec_DIV_DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__oe__ok + wire \dec_DIV_DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__output_carry + wire \dec_DIV_DIV__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__rc__ok + wire \dec_DIV_DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__rc__rc + wire \dec_DIV_DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__write_cr0 + wire \dec_DIV_DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_DIV_DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_DIV_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_DIV_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__byte_reverse + wire \dec_LDST_LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LDST_LDST_LDST__data_len + wire width 4 \dec_LDST_LDST__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -62113,13 +63002,13 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LDST_LDST_LDST__fn_unit + wire width 12 \dec_LDST_LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LDST_LDST_LDST__imm_data__data + wire width 64 \dec_LDST_LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__imm_data__ok + wire \dec_LDST_LDST__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LDST_LDST_LDST__insn + wire width 32 \dec_LDST_LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62195,36 +63084,36 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LDST_LDST_LDST__insn_type + wire width 7 \dec_LDST_LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__is_32bit + wire \dec_LDST_LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__is_signed + wire \dec_LDST_LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LDST_LDST_LDST__ldst_mode + wire width 2 \dec_LDST_LDST__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__oe__oe + wire \dec_LDST_LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__oe__ok + wire \dec_LDST_LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__rc__ok + wire \dec_LDST_LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__rc__rc + wire \dec_LDST_LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__sign_extend + wire \dec_LDST_LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LDST_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_LDST_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_LDST_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len + wire width 4 \dec_LOGICAL_LOGICAL__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -62239,19 +63128,19 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + wire width 12 \dec_LOGICAL_LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + wire width 64 \dec_LOGICAL_LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + wire \dec_LOGICAL_LOGICAL__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + wire width 2 \dec_LOGICAL_LOGICAL__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn + wire width 32 \dec_LOGICAL_LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62327,32 +63216,32 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + wire width 7 \dec_LOGICAL_LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + wire \dec_LOGICAL_LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + wire \dec_LOGICAL_LOGICAL__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + wire \dec_LOGICAL_LOGICAL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + wire \dec_LOGICAL_LOGICAL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + wire \dec_LOGICAL_LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + wire \dec_LOGICAL_LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + wire \dec_LOGICAL_LOGICAL__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + wire \dec_LOGICAL_LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + wire \dec_LOGICAL_LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + wire \dec_LOGICAL_LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_LOGICAL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_LOGICAL_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -62368,13 +63257,13 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_MUL_MUL_MUL__fn_unit + wire width 12 \dec_MUL_MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_MUL_MUL_MUL__imm_data__data + wire width 64 \dec_MUL_MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__imm_data__ok + wire \dec_MUL_MUL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_MUL_MUL_MUL__insn + wire width 32 \dec_MUL_MUL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62450,24 +63339,24 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_MUL_MUL_MUL__insn_type + wire width 7 \dec_MUL_MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__is_32bit + wire \dec_MUL_MUL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__is_signed + wire \dec_MUL_MUL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__oe__oe + wire \dec_MUL_MUL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__oe__ok + wire \dec_MUL_MUL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__rc__ok + wire \dec_MUL_MUL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__rc__rc + wire \dec_MUL_MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_MUL_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_MUL_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_MUL_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -62483,21 +63372,21 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + wire width 12 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + wire \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + wire \dec_SHIFT_ROT_SHIFT_ROT__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62573,28 +63462,30 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_SHIFT_ROT_raw_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -62610,9 +63501,9 @@ module \core attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SPR_SPR_SPR__fn_unit + wire width 12 \dec_SPR_SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SPR_SPR_SPR__insn + wire width 32 \dec_SPR_SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62688,200 +63579,200 @@ module \core attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SPR_SPR_SPR__insn_type + wire width 7 \dec_SPR_SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SPR_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec_SPR_raw_opcode_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 61 \dmi__addr + wire width 5 input 69 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 63 \dmi__data_o + wire width 64 output 71 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 62 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + wire input 70 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" wire \dp_XER_xer_so_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" wire \en_trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \fast_dest1__addr @@ -62901,257 +63792,255 @@ module \core wire width 64 \fast_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168" wire width 10 \fu_enable attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 65 \full_rd2__data_o + wire width 32 output 73 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 64 \full_rd2__ren + wire width 8 input 72 \full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 output 67 \full_rd__data_o + wire width 6 output 75 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 66 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 input 74 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_cr_a_ok$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_cr_a_ok$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_cr_a_ok$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_cr_a_ok$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire \fus_cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$11 + wire \fus_cu_busy_o$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$14 + wire \fus_cu_busy_o$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$17 + wire \fus_cu_busy_o$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$20 + wire \fus_cu_busy_o$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$23 + wire \fus_cu_busy_o$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$26 + wire \fus_cu_busy_o$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$29 + wire \fus_cu_busy_o$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$5 + wire \fus_cu_busy_o$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire \fus_cu_busy_o$8 + wire \fus_cu_busy_o$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" wire \fus_cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$10 + wire \fus_cu_issue_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$13 + wire \fus_cu_issue_i$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$16 + wire \fus_cu_issue_i$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$19 + wire \fus_cu_issue_i$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$22 + wire \fus_cu_issue_i$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$25 + wire \fus_cu_issue_i$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$28 + wire \fus_cu_issue_i$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$4 + wire \fus_cu_issue_i$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire \fus_cu_issue_i$7 + wire \fus_cu_issue_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$32 + wire width 6 \fus_cu_rd__go_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__go_i$35 + wire width 4 \fus_cu_rd__go_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$38 + wire width 3 \fus_cu_rd__go_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__go_i$41 + wire width 6 \fus_cu_rd__go_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$44 + wire width 3 \fus_cu_rd__go_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$47 + wire width 3 \fus_cu_rd__go_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__go_i$50 + wire width 5 \fus_cu_rd__go_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$53 + wire width 3 \fus_cu_rd__go_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__go_i$73 + wire width 3 \fus_cu_rd__go_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 4 \fus_cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$31 + wire width 6 \fus_cu_rd__rel_o$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_rd__rel_o$34 + wire width 4 \fus_cu_rd__rel_o$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$37 + wire width 3 \fus_cu_rd__rel_o$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_rd__rel_o$40 + wire width 6 \fus_cu_rd__rel_o$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$43 + wire width 3 \fus_cu_rd__rel_o$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$46 + wire width 3 \fus_cu_rd__rel_o$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_rd__rel_o$49 + wire width 5 \fus_cu_rd__rel_o$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$52 + wire width 3 \fus_cu_rd__rel_o$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_rd__rel_o$72 + wire width 3 \fus_cu_rd__rel_o$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" wire width 4 \fus_cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \fus_cu_rdmaskn_i$12 + wire width 6 \fus_cu_rdmaskn_i$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$15 + wire width 3 \fus_cu_rdmaskn_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \fus_cu_rdmaskn_i$18 + wire width 4 \fus_cu_rdmaskn_i$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$21 + wire width 3 \fus_cu_rdmaskn_i$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$24 + wire width 6 \fus_cu_rdmaskn_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 \fus_cu_rdmaskn_i$27 + wire width 3 \fus_cu_rdmaskn_i$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$30 + wire width 3 \fus_cu_rdmaskn_i$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \fus_cu_rdmaskn_i$6 + wire width 5 \fus_cu_rdmaskn_i$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \fus_cu_rdmaskn_i$9 + wire width 3 \fus_cu_rdmaskn_i$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$100 + wire width 6 \fus_cu_wr__go_i$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$103 + wire width 4 \fus_cu_wr__go_i$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__go_i$105 + wire width 4 \fus_cu_wr__go_i$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$140 + wire width 3 \fus_cu_wr__go_i$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$85 + wire width 2 \fus_cu_wr__go_i$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__go_i$88 + wire width 3 \fus_cu_wr__go_i$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__go_i$91 + wire width 3 \fus_cu_wr__go_i$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_wr__go_i$94 + wire width 5 \fus_cu_wr__go_i$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__go_i$97 + wire width 2 \fus_cu_wr__go_i$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire width 5 \fus_cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$102 + wire width 6 \fus_cu_wr__rel_o$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__rel_o$104 + wire width 4 \fus_cu_wr__rel_o$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$139 + wire width 4 \fus_cu_wr__rel_o$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$84 + wire width 3 \fus_cu_wr__rel_o$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__rel_o$87 + wire width 2 \fus_cu_wr__rel_o$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 \fus_cu_wr__rel_o$90 + wire width 3 \fus_cu_wr__rel_o$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 \fus_cu_wr__rel_o$93 + wire width 3 \fus_cu_wr__rel_o$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__rel_o$96 + wire width 5 \fus_cu_wr__rel_o$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 \fus_cu_wr__rel_o$99 + wire width 2 \fus_cu_wr__rel_o$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \fus_dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$106 + wire width 64 \fus_dest1_o$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$107 + wire width 64 \fus_dest1_o$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$108 + wire width 64 \fus_dest1_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$109 + wire width 64 \fus_dest1_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$110 + wire width 64 \fus_dest1_o$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$111 + wire width 64 \fus_dest1_o$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$112 + wire width 64 \fus_dest1_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$144 + wire width 64 \fus_dest1_o$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 32 \fus_dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$118 + wire width 4 \fus_dest2_o$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$119 + wire width 4 \fus_dest2_o$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$120 + wire width 4 \fus_dest2_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$121 + wire width 4 \fus_dest2_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$122 + wire width 4 \fus_dest2_o$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$145 + wire width 64 \fus_dest2_o$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$147 + wire width 64 \fus_dest2_o$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$153 + wire width 64 \fus_dest2_o$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 \fus_dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$125 + wire width 2 \fus_dest3_o$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$126 + wire width 2 \fus_dest3_o$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$130 + wire width 2 \fus_dest3_o$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$131 + wire width 2 \fus_dest3_o$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$146 + wire width 64 \fus_dest3_o$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$148 + wire width 64 \fus_dest3_o$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$150 + wire width 64 \fus_dest3_o$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$136 + wire \fus_dest4_o$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$137 + wire \fus_dest4_o$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest4_o$138 + wire \fus_dest4_o$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest4_o$151 + wire width 64 \fus_dest4_o$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire \fus_dest5_o$135 + wire \fus_dest5_o$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest5_o$152 + wire width 64 \fus_dest5_o$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 \fus_dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fus_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_fast1_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_fast1_ok$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_fast1_ok$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_fast1_ok$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_fast2_ok$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_fast2_ok$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire \fus_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 \fus_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \fus_ldst_port0_addr_ok_o @@ -63159,42 +64048,58 @@ module \core wire \fus_ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 \fus_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \fus_ldst_port0_exc_$signal$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire \fus_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \fus_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fus_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fus_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_nia_ok$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_nia_ok$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fus_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_o_ok$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \fus_oper_i_alu_alu0__data_len attribute \enum_base_type "Function" @@ -63989,6 +64894,8 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \fus_oper_i_alu_shift_rot0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_shift_rot0__is_signed @@ -64199,11 +65106,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \fus_oper_i_alu_trap0__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \fus_oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \fus_oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_trap0__traptype + wire width 8 \fus_oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -64328,111 +65237,111 @@ module \core wire \fus_oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \fus_oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$33 + wire width 64 \fus_src1_i$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$36 + wire width 64 \fus_src1_i$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$39 + wire width 64 \fus_src1_i$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$42 + wire width 64 \fus_src1_i$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$45 + wire width 64 \fus_src1_i$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$48 + wire width 64 \fus_src1_i$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$51 + wire width 64 \fus_src1_i$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$54 + wire width 64 \fus_src1_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src1_i$77 + wire width 64 \fus_src1_i$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$55 + wire width 64 \fus_src2_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$56 + wire width 64 \fus_src2_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$57 + wire width 64 \fus_src2_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$58 + wire width 64 \fus_src2_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$59 + wire width 64 \fus_src2_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$60 + wire width 64 \fus_src2_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$61 + wire width 64 \fus_src2_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$80 + wire width 64 \fus_src2_i$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$82 + wire width 64 \fus_src2_i$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$62 + wire width 64 \fus_src3_i$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$63 + wire \fus_src3_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$64 + wire \fus_src3_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$65 + wire \fus_src3_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src3_i$66 + wire \fus_src3_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 \fus_src3_i$70 + wire width 32 \fus_src3_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src3_i$74 + wire width 4 \fus_src3_i$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$78 + wire width 64 \fus_src3_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src3_i$79 + wire width 64 \fus_src3_i$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire \fus_src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i$67 + wire \fus_src4_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$68 + wire width 2 \fus_src4_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src4_i$71 + wire width 4 \fus_src4_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$81 + wire width 64 \fus_src4_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i$69 + wire width 2 \fus_src5_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src5_i$75 + wire width 4 \fus_src5_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" wire width 2 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src6_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \fus_src6_i$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ca_ok$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ca_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_ca_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_ca_ok$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_ov_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_ov_ok$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_ov_ok$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_ov_ok$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fus_xer_so_ok$134 - attribute \src "libresoc.v:35346.7-35346.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_so_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_so_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fus_xer_so_ok$141 + attribute \src "libresoc.v:35933.7-35933.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 5 \int_dest1__addr @@ -64459,134 +65368,134 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire \int_src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 68 \issue__addr + wire width 3 input 76 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 71 \issue__addr$3 + wire width 3 input 79 \issue__addr$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 73 \issue__data_i + wire width 64 input 81 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 70 \issue__data_o + wire width 64 output 78 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 69 \issue__ren + wire input 77 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 72 \issue__wen + wire input 80 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" - wire input 59 \issue_i + wire input 67 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" - wire input 58 \ivalid_i + wire input 66 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 56 \msr__data_o + wire width 64 output 64 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 11 \msr__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" wire \pick_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 input 54 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + wire width 32 input 62 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" wire \rdflag_XER_xer_so_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \rdpick_CR_cr_a_en_o @@ -64666,90 +65575,90 @@ module \core wire width 6 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" wire \rp_XER_xer_so_spr0_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 7 \spr_spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$159 + wire width 7 \spr_spr1__addr$173 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \spr_spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -64761,456 +65670,458 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \state_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$158 + wire width 64 \state_data_i$172 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 60 \state_nia_wen + wire width 4 output 68 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \state_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 82 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1095 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1559 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1684 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1728 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1744 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1768 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$1788 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$975 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - wire \wp$996 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + wire \wp$1216 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1522 + wire \wr_pick_dly$1500 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1522$next + wire \wr_pick_dly$1500$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1538 + wire \wr_pick_dly$1536 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1538$next + wire \wr_pick_dly$1536$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1554 + wire \wr_pick_dly$1552 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1554$next + wire \wr_pick_dly$1552$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1570 + wire \wr_pick_dly$1568 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1570$next + wire \wr_pick_dly$1568$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1612 + wire \wr_pick_dly$1584 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1612$next + wire \wr_pick_dly$1584$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1631 + wire \wr_pick_dly$1626 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1631$next + wire \wr_pick_dly$1626$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1647 + wire \wr_pick_dly$1645 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1647$next + wire \wr_pick_dly$1645$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1663 + wire \wr_pick_dly$1661 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1663$next + wire \wr_pick_dly$1661$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1679 + wire \wr_pick_dly$1677 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1679$next + wire \wr_pick_dly$1677$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1723 + wire \wr_pick_dly$1693 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1723$next + wire \wr_pick_dly$1693$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1739 + wire \wr_pick_dly$1737 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1739$next + wire \wr_pick_dly$1737$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1763 + wire \wr_pick_dly$1753 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1763$next + wire \wr_pick_dly$1753$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1783 + wire \wr_pick_dly$1777 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1783$next + wire \wr_pick_dly$1777$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$967 + wire \wr_pick_dly$1797 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$967$next + wire \wr_pick_dly$1797$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$986 + wire \wr_pick_dly$981 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$986$next + wire \wr_pick_dly$981$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire \wr_pick_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1001 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1006 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \wr_pick_rise$1007 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$1008 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1013 + wire \wr_pick_rise$1009 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1026 + wire \wr_pick_rise$1022 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1031 + wire \wr_pick_rise$1027 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1032 + wire \wr_pick_rise$1040 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1033 + wire \wr_pick_rise$1045 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1034 + wire \wr_pick_rise$1046 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1035 + wire \wr_pick_rise$1047 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$1048 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1053 + wire \wr_pick_rise$1049 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1054 + wire \wr_pick_rise$1062 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1055 + wire \wr_pick_rise$1067 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$1068 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1073 + wire \wr_pick_rise$1069 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1074 + wire \wr_pick_rise$1082 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1075 + wire \wr_pick_rise$1087 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$1088 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1093 + wire \wr_pick_rise$1089 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1094 + wire \wr_pick_rise$1102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$1107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1112 + wire \wr_pick_rise$1108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1613 + wire \wr_pick_rise$1121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1618 + wire \wr_pick_rise$1126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1619 + wire \wr_pick_rise$1627 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$954 + wire \wr_pick_rise$1632 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$955 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$956 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$957 + wire \wr_pick_rise$1633 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \wr_pick_rise$968 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$973 + wire \wr_pick_rise$969 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$974 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$987 + wire \wr_pick_rise$970 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$992 + wire \wr_pick_rise$971 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$993 + wire \wr_pick_rise$982 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$994 + wire \wr_pick_rise$987 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$995 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + wire \wr_pick_rise$988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \wrflag_trap0_o_0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \wrpick_CR_cr_a_en_o @@ -65275,9 +66186,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$154 + wire width 2 \xer_data_i$168 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$156 + wire width 2 \xer_data_i$170 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -65293,22 +66204,44 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \xer_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$155 + wire width 3 \xer_wen$169 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41098$1515 + wire width 3 \xer_wen$171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:41721$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$997 + connect \B \$1002 + connect \Y $and$libresoc.v:41721$1547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41722$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$89 - connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41098$1515_Y + connect \A \wr_pick$997 + connect \B \wrpick_INT_o_en_o + connect \Y $and$libresoc.v:41722$1548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41099$1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41724$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$96 + connect \B \fus_cu_busy_o$21 + connect \Y $and$libresoc.v:41724$1550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41725$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65316,43 +66249,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41099$1516_Y + connect \Y $and$libresoc.v:41725$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41101$1518 + cell $and $and$libresoc.v:41727$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 - connect \B \$1009 - connect \Y $and$libresoc.v:41101$1518_Y + connect \A \wr_pick$1018 + connect \B \$1023 + connect \Y $and$libresoc.v:41727$1553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41102$1519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41728$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 + connect \A \wr_pick$1018 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41102$1519_Y + connect \Y $and$libresoc.v:41728$1554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41104$1521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41730$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$92 - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41104$1521_Y + connect \A \fus_o_ok$99 + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:41730$1556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41105$1522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41731$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65360,43 +66293,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41105$1522_Y + connect \Y $and$libresoc.v:41731$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41107$1524 + cell $and $and$libresoc.v:41733$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 - connect \B \$1027 - connect \Y $and$libresoc.v:41107$1524_Y + connect \A \wr_pick$1036 + connect \B \$1041 + connect \Y $and$libresoc.v:41733$1559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41108$1525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41734$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 + connect \A \wr_pick$1036 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41108$1525_Y + connect \Y $and$libresoc.v:41734$1560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41110$1527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41736$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$95 - connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41110$1527_Y + connect \A \fus_o_ok$102 + connect \B \fus_cu_busy_o$27 + connect \Y $and$libresoc.v:41736$1562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41111$1528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41737$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65404,43 +66337,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41111$1528_Y + connect \Y $and$libresoc.v:41737$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41113$1530 + cell $and $and$libresoc.v:41739$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 - connect \B \$1049 - connect \Y $and$libresoc.v:41113$1530_Y + connect \A \wr_pick$1058 + connect \B \$1063 + connect \Y $and$libresoc.v:41739$1565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41114$1531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41740$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 + connect \A \wr_pick$1058 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41114$1531_Y + connect \Y $and$libresoc.v:41740$1566_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41116$1533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41742$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$98 - connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41116$1533_Y + connect \A \fus_o_ok$105 + connect \B \fus_cu_busy_o$30 + connect \Y $and$libresoc.v:41742$1568_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41117$1534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41743$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65448,43 +66381,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41117$1534_Y + connect \Y $and$libresoc.v:41743$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41119$1536 + cell $and $and$libresoc.v:41745$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 - connect \B \$1069 - connect \Y $and$libresoc.v:41119$1536_Y + connect \A \wr_pick$1078 + connect \B \$1083 + connect \Y $and$libresoc.v:41745$1571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41120$1537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41746$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 + connect \A \wr_pick$1078 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41120$1537_Y + connect \Y $and$libresoc.v:41746$1572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41122$1539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41748$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$101 - connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41122$1539_Y + connect \A \fus_o_ok$108 + connect \B \fus_cu_busy_o$33 + connect \Y $and$libresoc.v:41748$1574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41123$1540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41749$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65492,43 +66425,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41123$1540_Y + connect \Y $and$libresoc.v:41749$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41125$1542 + cell $and $and$libresoc.v:41751$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 - connect \B \$1089 - connect \Y $and$libresoc.v:41125$1542_Y + connect \A \wr_pick$1098 + connect \B \$1103 + connect \Y $and$libresoc.v:41751$1577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41126$1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41752$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 + connect \A \wr_pick$1098 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41126$1543_Y + connect \Y $and$libresoc.v:41752$1578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41128$1545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41754$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o_ok - connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41128$1545_Y + connect \B \fus_cu_busy_o$36 + connect \Y $and$libresoc.v:41754$1580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41129$1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41755$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65536,43 +66469,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41129$1546_Y + connect \Y $and$libresoc.v:41755$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41131$1548 + cell $and $and$libresoc.v:41757$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B \$1108 - connect \Y $and$libresoc.v:41131$1548_Y + connect \A \wr_pick$1117 + connect \B \$1122 + connect \Y $and$libresoc.v:41757$1583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41132$1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41758$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 + connect \A \wr_pick$1117 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41132$1549_Y + connect \Y $and$libresoc.v:41758$1584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41134$1551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41760$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ea_ok - connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41134$1551_Y + connect \B \fus_cu_busy_o$36 + connect \Y $and$libresoc.v:41760$1586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41135$1552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41761$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65580,54 +66513,54 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41135$1552_Y + connect \Y $and$libresoc.v:41761$1587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41137$1554 + cell $and $and$libresoc.v:41763$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 - connect \B \$1125 - connect \Y $and$libresoc.v:41137$1554_Y + connect \A \wr_pick$1135 + connect \B \$1139 + connect \Y $and$libresoc.v:41763$1589_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41138$1555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41764$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 + connect \A \wr_pick$1135 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41138$1555_Y + connect \Y $and$libresoc.v:41764$1590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41167$1584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41793$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$5 - connect \Y $and$libresoc.v:41167$1584_Y + connect \B \fus_cu_busy_o$12 + connect \Y $and$libresoc.v:41793$1619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41168$1585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41794$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [1] + connect \A \fus_cu_wr__rel_o$91 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41168$1585_Y + connect \Y $and$libresoc.v:41794$1620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41169$1586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41795$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65635,32 +66568,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41169$1586_Y + connect \Y $and$libresoc.v:41795$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41171$1588 + cell $and $and$libresoc.v:41797$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 - connect \B \$1198 - connect \Y $and$libresoc.v:41171$1588_Y + connect \A \wr_pick$1208 + connect \B \$1212 + connect \Y $and$libresoc.v:41797$1623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41172$1589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41798$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 + connect \A \wr_pick$1208 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41172$1589_Y + connect \Y $and$libresoc.v:41798$1624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41174$1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41800$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65668,10 +66601,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41174$1591_Y + connect \Y $and$libresoc.v:41800$1626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41175$1592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41801$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65679,65 +66612,65 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41175$1592_Y + connect \Y $and$libresoc.v:41801$1627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41176$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41802$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [2] + connect \A \fus_cu_wr__rel_o$91 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41176$1593_Y + connect \Y $and$libresoc.v:41802$1628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41177$1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41803$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [1] + connect \A \fus_cu_wr__rel_o$97 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41177$1594_Y + connect \Y $and$libresoc.v:41803$1629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41178$1595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41804$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [1] + connect \A \fus_cu_wr__rel_o$103 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41178$1595_Y + connect \Y $and$libresoc.v:41804$1630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41179$1596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41805$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [1] + connect \A \fus_cu_wr__rel_o$106 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41179$1596_Y + connect \Y $and$libresoc.v:41805$1631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41180$1597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41806$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [1] + connect \A \fus_cu_wr__rel_o$109 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41180$1597_Y + connect \Y $and$libresoc.v:41806$1632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41181$1598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41807$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65745,43 +66678,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41181$1598_Y + connect \Y $and$libresoc.v:41807$1633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41183$1600 + cell $and $and$libresoc.v:41809$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 - connect \B \$1226 - connect \Y $and$libresoc.v:41183$1600_Y + connect \A \wr_pick$1236 + connect \B \$1240 + connect \Y $and$libresoc.v:41809$1635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41184$1601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41810$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 + connect \A \wr_pick$1236 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41184$1601_Y + connect \Y $and$libresoc.v:41810$1636_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41188$1605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41814$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$113 - connect \B \fus_cu_busy_o$5 - connect \Y $and$libresoc.v:41188$1605_Y + connect \A \fus_cr_a_ok$120 + connect \B \fus_cu_busy_o$12 + connect \Y $and$libresoc.v:41814$1640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41189$1606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41815$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65789,43 +66722,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41189$1606_Y + connect \Y $and$libresoc.v:41815$1641_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41191$1608 + cell $and $and$libresoc.v:41817$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B \$1246 - connect \Y $and$libresoc.v:41191$1608_Y + connect \A \wr_pick$1256 + connect \B \$1260 + connect \Y $and$libresoc.v:41817$1643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41192$1609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41818$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 + connect \A \wr_pick$1256 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41192$1609_Y + connect \Y $and$libresoc.v:41818$1644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41196$1613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41822$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$114 - connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41196$1613_Y + connect \A \fus_cr_a_ok$121 + connect \B \fus_cu_busy_o$21 + connect \Y $and$libresoc.v:41822$1648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41197$1614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41823$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65833,43 +66766,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41197$1614_Y + connect \Y $and$libresoc.v:41823$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41199$1616 + cell $and $and$libresoc.v:41825$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B \$1266 - connect \Y $and$libresoc.v:41199$1616_Y + connect \A \wr_pick$1276 + connect \B \$1280 + connect \Y $and$libresoc.v:41825$1651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41200$1617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41826$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 + connect \A \wr_pick$1276 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41200$1617_Y + connect \Y $and$libresoc.v:41826$1652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41204$1621 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41830$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$115 - connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41204$1621_Y + connect \A \fus_cr_a_ok$122 + connect \B \fus_cu_busy_o$27 + connect \Y $and$libresoc.v:41830$1656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41205$1622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41831$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65877,43 +66810,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41205$1622_Y + connect \Y $and$libresoc.v:41831$1657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41207$1624 + cell $and $and$libresoc.v:41833$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B \$1286 - connect \Y $and$libresoc.v:41207$1624_Y + connect \A \wr_pick$1296 + connect \B \$1300 + connect \Y $and$libresoc.v:41833$1659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41208$1625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41834$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 + connect \A \wr_pick$1296 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41208$1625_Y + connect \Y $and$libresoc.v:41834$1660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41212$1629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41838$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$116 - connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41212$1629_Y + connect \A \fus_cr_a_ok$123 + connect \B \fus_cu_busy_o$30 + connect \Y $and$libresoc.v:41838$1664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41213$1630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41839$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65921,43 +66854,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41213$1630_Y + connect \Y $and$libresoc.v:41839$1665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41215$1632 + cell $and $and$libresoc.v:41841$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B \$1306 - connect \Y $and$libresoc.v:41215$1632_Y + connect \A \wr_pick$1316 + connect \B \$1320 + connect \Y $and$libresoc.v:41841$1667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41216$1633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41842$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 + connect \A \wr_pick$1316 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41216$1633_Y + connect \Y $and$libresoc.v:41842$1668_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41220$1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41846$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$117 - connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41220$1637_Y + connect \A \fus_cr_a_ok$124 + connect \B \fus_cu_busy_o$33 + connect \Y $and$libresoc.v:41846$1672_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41221$1638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41847$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65965,32 +66898,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41221$1638_Y + connect \Y $and$libresoc.v:41847$1673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41223$1640 + cell $and $and$libresoc.v:41849$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B \$1326 - connect \Y $and$libresoc.v:41223$1640_Y + connect \A \wr_pick$1336 + connect \B \$1340 + connect \Y $and$libresoc.v:41849$1675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41224$1641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41850$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 + connect \A \wr_pick$1336 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41224$1641_Y + connect \Y $and$libresoc.v:41850$1676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41238$1655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41864$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65998,10 +66931,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41238$1655_Y + connect \Y $and$libresoc.v:41864$1690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41239$1656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41865$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66009,32 +66942,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41239$1656_Y + connect \Y $and$libresoc.v:41865$1691_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41240$1657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41866$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [5] + connect \A \fus_cu_wr__rel_o$100 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41240$1657_Y + connect \Y $and$libresoc.v:41866$1692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41241$1658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41867$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [2] + connect \A \fus_cu_wr__rel_o$109 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41241$1658_Y + connect \Y $and$libresoc.v:41867$1693_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41242$1659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41868$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66042,43 +66975,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41242$1659_Y + connect \Y $and$libresoc.v:41868$1694_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41244$1661 + cell $and $and$libresoc.v:41870$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 - connect \B \$1373 - connect \Y $and$libresoc.v:41244$1661_Y + connect \A \wr_pick$1383 + connect \B \$1387 + connect \Y $and$libresoc.v:41870$1696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41245$1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41871$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 + connect \A \wr_pick$1383 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41245$1662_Y + connect \Y $and$libresoc.v:41871$1697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41247$1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41873$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$123 - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41247$1664_Y + connect \A \fus_xer_ca_ok$130 + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:41873$1699_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41248$1665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41874$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66086,43 +67019,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41248$1665_Y + connect \Y $and$libresoc.v:41874$1700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41250$1667 + cell $and $and$libresoc.v:41876$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 - connect \B \$1389 - connect \Y $and$libresoc.v:41250$1667_Y + connect \A \wr_pick$1399 + connect \B \$1403 + connect \Y $and$libresoc.v:41876$1702_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41251$1668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41877$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 + connect \A \wr_pick$1399 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41251$1668_Y + connect \Y $and$libresoc.v:41877$1703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41253$1670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41879$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$124 - connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41253$1670_Y + connect \A \fus_xer_ca_ok$131 + connect \B \fus_cu_busy_o$33 + connect \Y $and$libresoc.v:41879$1705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41254$1671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41880$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66130,32 +67063,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41254$1671_Y + connect \Y $and$libresoc.v:41880$1706_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41256$1673 + cell $and $and$libresoc.v:41882$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 - connect \B \$1405 - connect \Y $and$libresoc.v:41256$1673_Y + connect \A \wr_pick$1415 + connect \B \$1419 + connect \Y $and$libresoc.v:41882$1708_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41257$1674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41883$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 + connect \A \wr_pick$1415 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41257$1674_Y + connect \Y $and$libresoc.v:41883$1709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41264$1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41890$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66163,10 +67096,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41264$1682_Y + connect \Y $and$libresoc.v:41890$1717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41265$1683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41891$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66174,43 +67107,43 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41265$1683_Y + connect \Y $and$libresoc.v:41891$1718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41266$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41892$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [4] + connect \A \fus_cu_wr__rel_o$100 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41266$1684_Y + connect \Y $and$libresoc.v:41892$1719_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41267$1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41893$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [2] + connect \A \fus_cu_wr__rel_o$103 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41267$1685_Y + connect \Y $and$libresoc.v:41893$1720_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41268$1686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41894$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [2] + connect \A \fus_cu_wr__rel_o$106 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41268$1686_Y + connect \Y $and$libresoc.v:41894$1721_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41269$1687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41895$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66218,43 +67151,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41269$1687_Y + connect \Y $and$libresoc.v:41895$1722_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41271$1689 + cell $and $and$libresoc.v:41897$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 - connect \B \$1439 - connect \Y $and$libresoc.v:41271$1689_Y + connect \A \wr_pick$1449 + connect \B \$1453 + connect \Y $and$libresoc.v:41897$1724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41272$1690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41898$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 + connect \A \wr_pick$1449 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41272$1690_Y + connect \Y $and$libresoc.v:41898$1725_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41274$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41900$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$127 - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41274$1692_Y + connect \A \fus_xer_ov_ok$134 + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:41900$1727_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41275$1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41901$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66262,43 +67195,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41275$1693_Y + connect \Y $and$libresoc.v:41901$1728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41277$1695 + cell $and $and$libresoc.v:41903$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 - connect \B \$1455 - connect \Y $and$libresoc.v:41277$1695_Y + connect \A \wr_pick$1465 + connect \B \$1469 + connect \Y $and$libresoc.v:41903$1730_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41278$1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41904$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 + connect \A \wr_pick$1465 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41278$1696_Y + connect \Y $and$libresoc.v:41904$1731_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41280$1698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41906$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$128 - connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41280$1698_Y + connect \A \fus_xer_ov_ok$135 + connect \B \fus_cu_busy_o$27 + connect \Y $and$libresoc.v:41906$1733_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41281$1699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41907$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66306,43 +67239,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41281$1699_Y + connect \Y $and$libresoc.v:41907$1734_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41283$1701 + cell $and $and$libresoc.v:41909$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 - connect \B \$1471 - connect \Y $and$libresoc.v:41283$1701_Y + connect \A \wr_pick$1481 + connect \B \$1485 + connect \Y $and$libresoc.v:41909$1736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41284$1702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41910$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 + connect \A \wr_pick$1481 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41284$1702_Y + connect \Y $and$libresoc.v:41910$1737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41286$1704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41912$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$129 - connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41286$1704_Y + connect \A \fus_xer_ov_ok$136 + connect \B \fus_cu_busy_o$30 + connect \Y $and$libresoc.v:41912$1739_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41287$1705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41913$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66350,32 +67283,32 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41287$1705_Y + connect \Y $and$libresoc.v:41913$1740_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41289$1707 + cell $and $and$libresoc.v:41915$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 - connect \B \$1487 - connect \Y $and$libresoc.v:41289$1707_Y + connect \A \wr_pick$1497 + connect \B \$1501 + connect \Y $and$libresoc.v:41915$1742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41290$1708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41916$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 + connect \A \wr_pick$1497 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41290$1708_Y + connect \Y $and$libresoc.v:41916$1743_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41298$1716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41924$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66383,10 +67316,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41298$1716_Y + connect \Y $and$libresoc.v:41924$1751_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41299$1717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41925$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66394,43 +67327,43 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41299$1717_Y + connect \Y $and$libresoc.v:41925$1752_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41300$1718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41926$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [3] + connect \A \fus_cu_wr__rel_o$100 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41300$1718_Y + connect \Y $and$libresoc.v:41926$1753_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41301$1719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41927$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [3] + connect \A \fus_cu_wr__rel_o$103 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41301$1719_Y + connect \Y $and$libresoc.v:41927$1754_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41302$1720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41928$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [3] + connect \A \fus_cu_wr__rel_o$106 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41302$1720_Y + connect \Y $and$libresoc.v:41928$1755_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41303$1721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41929$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66438,43 +67371,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41303$1721_Y + connect \Y $and$libresoc.v:41929$1756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41305$1723 + cell $and $and$libresoc.v:41931$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 - connect \B \$1523 - connect \Y $and$libresoc.v:41305$1723_Y + connect \A \wr_pick$1533 + connect \B \$1537 + connect \Y $and$libresoc.v:41931$1758_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41306$1724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41932$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 + connect \A \wr_pick$1533 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41306$1724_Y + connect \Y $and$libresoc.v:41932$1759_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41308$1726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41934$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$132 - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41308$1726_Y + connect \A \fus_xer_so_ok$139 + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:41934$1761_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41309$1727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41935$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66482,43 +67415,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41309$1727_Y + connect \Y $and$libresoc.v:41935$1762_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41311$1729 + cell $and $and$libresoc.v:41937$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 - connect \B \$1539 - connect \Y $and$libresoc.v:41311$1729_Y + connect \A \wr_pick$1549 + connect \B \$1553 + connect \Y $and$libresoc.v:41937$1764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41312$1730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41938$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 + connect \A \wr_pick$1549 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41312$1730_Y + connect \Y $and$libresoc.v:41938$1765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41314$1732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41940$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$133 - connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41314$1732_Y + connect \A \fus_xer_so_ok$140 + connect \B \fus_cu_busy_o$27 + connect \Y $and$libresoc.v:41940$1767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41315$1733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41941$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66526,43 +67459,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41315$1733_Y + connect \Y $and$libresoc.v:41941$1768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41317$1735 + cell $and $and$libresoc.v:41943$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 - connect \B \$1555 - connect \Y $and$libresoc.v:41317$1735_Y + connect \A \wr_pick$1565 + connect \B \$1569 + connect \Y $and$libresoc.v:41943$1770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41318$1736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41944$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 + connect \A \wr_pick$1565 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41318$1736_Y + connect \Y $and$libresoc.v:41944$1771_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41320$1738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41946$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$134 - connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41320$1738_Y + connect \A \fus_xer_so_ok$141 + connect \B \fus_cu_busy_o$30 + connect \Y $and$libresoc.v:41946$1773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41321$1739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41947$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66570,98 +67503,98 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41321$1739_Y + connect \Y $and$libresoc.v:41947$1774_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41323$1741 + cell $and $and$libresoc.v:41949$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 - connect \B \$1571 - connect \Y $and$libresoc.v:41323$1741_Y + connect \A \wr_pick$1581 + connect \B \$1585 + connect \Y $and$libresoc.v:41949$1776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41324$1742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41950$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 + connect \A \wr_pick$1581 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41324$1742_Y + connect \Y $and$libresoc.v:41950$1777_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41334$1754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41960$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$libresoc.v:41334$1754_Y + connect \B \fus_cu_busy_o$15 + connect \Y $and$libresoc.v:41960$1789_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41335$1755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41961$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [0] + connect \A \fus_cu_wr__rel_o$146 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41335$1755_Y + connect \Y $and$libresoc.v:41961$1790_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41336$1756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41962$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [1] + connect \A \fus_cu_wr__rel_o$94 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41336$1756_Y + connect \Y $and$libresoc.v:41962$1791_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41337$1757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41963$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [2] + connect \A \fus_cu_wr__rel_o$100 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41337$1757_Y + connect \Y $and$libresoc.v:41963$1792_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41338$1758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41964$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [1] + connect \A \fus_cu_wr__rel_o$146 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41338$1758_Y + connect \Y $and$libresoc.v:41964$1793_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41339$1759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:41965$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [2] + connect \A \fus_cu_wr__rel_o$94 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41339$1759_Y + connect \Y $and$libresoc.v:41965$1794_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41340$1760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41966$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66669,54 +67602,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41340$1760_Y + connect \Y $and$libresoc.v:41966$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41342$1762 + cell $and $and$libresoc.v:41968$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 - connect \B \$1614 - connect \Y $and$libresoc.v:41342$1762_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41343$1763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 2'10 - connect \Y $and$libresoc.v:41343$1763_Y + connect \A \wr_pick$1623 + connect \B \$1628 + connect \Y $and$libresoc.v:41968$1797_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41344$1764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41969$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 + connect \A \wr_pick$1623 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41344$1764_Y + connect \Y $and$libresoc.v:41969$1798_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41346$1766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41971$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$141 - connect \B \fus_cu_busy_o$11 - connect \Y $and$libresoc.v:41346$1766_Y + connect \A \fus_fast1_ok$148 + connect \B \fus_cu_busy_o$18 + connect \Y $and$libresoc.v:41971$1800_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41348$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41972$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66724,43 +67646,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41348$1768_Y + connect \Y $and$libresoc.v:41972$1801_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41350$1770 + cell $and $and$libresoc.v:41974$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 - connect \B \$1632 - connect \Y $and$libresoc.v:41350$1770_Y + connect \A \wr_pick$1642 + connect \B \$1646 + connect \Y $and$libresoc.v:41974$1803_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41351$1771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41975$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 + connect \A \wr_pick$1642 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41351$1771_Y + connect \Y $and$libresoc.v:41975$1804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41353$1773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41977$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$142 - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41353$1773_Y + connect \A \fus_fast1_ok$149 + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:41977$1806_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41354$1774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41978$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66768,54 +67690,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41354$1774_Y + connect \Y $and$libresoc.v:41978$1807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41356$1776 + cell $and $and$libresoc.v:41980$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 - connect \B \$1648 - connect \Y $and$libresoc.v:41356$1776_Y + connect \A \wr_pick$1658 + connect \B \$1662 + connect \Y $and$libresoc.v:41980$1809_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41357$1777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41981$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 + connect \A \wr_pick$1658 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41357$1777_Y + connect \Y $and$libresoc.v:41981$1810_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41359$1779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41983$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$libresoc.v:41359$1779_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41360$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 7'1000000 - connect \Y $and$libresoc.v:41360$1780_Y + connect \B \fus_cu_busy_o$15 + connect \Y $and$libresoc.v:41983$1812_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41361$1781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41984$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66823,43 +67734,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41361$1781_Y + connect \Y $and$libresoc.v:41984$1813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41363$1783 + cell $and $and$libresoc.v:41986$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 - connect \B \$1664 - connect \Y $and$libresoc.v:41363$1783_Y + connect \A \wr_pick$1674 + connect \B \$1678 + connect \Y $and$libresoc.v:41986$1815_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41365$1785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41987$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 + connect \A \wr_pick$1674 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41365$1785_Y + connect \Y $and$libresoc.v:41987$1816_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41367$1787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:41989$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$143 - connect \B \fus_cu_busy_o$11 - connect \Y $and$libresoc.v:41367$1787_Y + connect \A \fus_fast2_ok$150 + connect \B \fus_cu_busy_o$18 + connect \Y $and$libresoc.v:41989$1818_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41368$1788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:41990$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66867,76 +67778,65 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41368$1788_Y + connect \Y $and$libresoc.v:41990$1819_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41370$1790 + cell $and $and$libresoc.v:41992$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 - connect \B \$1680 - connect \Y $and$libresoc.v:41370$1790_Y + connect \A \wr_pick$1690 + connect \B \$1694 + connect \Y $and$libresoc.v:41992$1821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41371$1791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:41993$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 + connect \A \wr_pick$1690 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41371$1791_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41378$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 6'100000 - connect \Y $and$libresoc.v:41378$1798_Y + connect \Y $and$libresoc.v:41993$1822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41387$1807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42007$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$8 - connect \Y $and$libresoc.v:41387$1807_Y + connect \B \fus_cu_busy_o$15 + connect \Y $and$libresoc.v:42007$1836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41388$1808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42008$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [2] + connect \A \fus_cu_wr__rel_o$146 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41388$1808_Y + connect \Y $and$libresoc.v:42008$1837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41389$1809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42009$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [3] + connect \A \fus_cu_wr__rel_o$94 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41389$1809_Y + connect \Y $and$libresoc.v:42009$1838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41390$1810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42010$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66944,43 +67844,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41390$1810_Y + connect \Y $and$libresoc.v:42010$1839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41392$1812 + cell $and $and$libresoc.v:42012$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 - connect \B \$1724 - connect \Y $and$libresoc.v:41392$1812_Y + connect \A \wr_pick$1734 + connect \B \$1738 + connect \Y $and$libresoc.v:42012$1841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41393$1813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42013$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 + connect \A \wr_pick$1734 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41393$1813_Y + connect \Y $and$libresoc.v:42013$1842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41395$1815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42015$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$149 - connect \B \fus_cu_busy_o$11 - connect \Y $and$libresoc.v:41395$1815_Y + connect \A \fus_nia_ok$156 + connect \B \fus_cu_busy_o$18 + connect \Y $and$libresoc.v:42015$1844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41396$1816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42016$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66988,65 +67888,65 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41396$1816_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41397$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 8'10000000 - connect \Y $and$libresoc.v:41397$1817_Y + connect \Y $and$libresoc.v:42016$1845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41399$1819 + cell $and $and$libresoc.v:42018$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 - connect \B \$1740 - connect \Y $and$libresoc.v:41399$1819_Y + connect \A \wr_pick$1750 + connect \B \$1754 + connect \Y $and$libresoc.v:42018$1847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41400$1820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42019$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 2'10 + connect \Y $and$libresoc.v:42019$1848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42020$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 + connect \A \wr_pick$1750 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:41400$1820_Y + connect \Y $and$libresoc.v:42020$1849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41406$1827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42026$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$11 - connect \Y $and$libresoc.v:41406$1827_Y + connect \B \fus_cu_busy_o$18 + connect \Y $and$libresoc.v:42026$1856_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41407$1828 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42027$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [4] + connect \A \fus_cu_wr__rel_o$94 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41407$1828_Y + connect \Y $and$libresoc.v:42027$1857_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41408$1829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42028$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67054,65 +67954,54 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:41408$1829_Y + connect \Y $and$libresoc.v:42028$1858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41410$1831 + cell $and $and$libresoc.v:42030$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 - connect \B \$1764 - connect \Y $and$libresoc.v:41410$1831_Y + connect \A \wr_pick$1774 + connect \B \$1778 + connect \Y $and$libresoc.v:42030$1860_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41411$1832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42031$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 + connect \A \wr_pick$1774 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:41411$1832_Y + connect \Y $and$libresoc.v:42031$1861_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41414$1836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42034$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:41414$1836_Y + connect \B \fus_cu_busy_o$24 + connect \Y $and$libresoc.v:42034$1865_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41415$1837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42035$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [1] + connect \A \fus_cu_wr__rel_o$100 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41415$1837_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41416$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 5'10000 - connect \Y $and$libresoc.v:41416$1838_Y + connect \Y $and$libresoc.v:42035$1866_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41417$1839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42036$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67120,32 +68009,76 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:41417$1839_Y + connect \Y $and$libresoc.v:42036$1867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42038$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 7'1000000 + connect \Y $and$libresoc.v:42038$1869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41419$1841 + cell $and $and$libresoc.v:42039$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B \$1784 - connect \Y $and$libresoc.v:41419$1841_Y + connect \A \wr_pick$1794 + connect \B \$1798 + connect \Y $and$libresoc.v:42039$1870_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41421$1843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42040$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 + connect \A \wr_pick$1794 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:41421$1843_Y + connect \Y $and$libresoc.v:42040$1871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42043$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 6'100000 + connect \Y $and$libresoc.v:42043$1874_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42045$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 8'10000000 + connect \Y $and$libresoc.v:42045$1876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42047$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 12 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 12 + connect \A \core_core_fn_unit + connect \B 5'10000 + connect \Y $and$libresoc.v:42047$1878_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41423$1845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42049$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \B_SIGNED 0 @@ -67153,10 +68086,10 @@ module \core parameter \Y_WIDTH 12 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:41423$1845_Y + connect \Y $and$libresoc.v:42049$1880_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41425$1847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42051$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \B_SIGNED 0 @@ -67164,10 +68097,10 @@ module \core parameter \Y_WIDTH 12 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:41425$1847_Y + connect \Y $and$libresoc.v:42051$1882_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41427$1849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42053$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \B_SIGNED 0 @@ -67175,10 +68108,10 @@ module \core parameter \Y_WIDTH 12 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:41427$1849_Y + connect \Y $and$libresoc.v:42053$1884_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41429$1851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42055$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \B_SIGNED 0 @@ -67186,10 +68119,10 @@ module \core parameter \Y_WIDTH 12 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:41429$1851_Y + connect \Y $and$libresoc.v:42055$1886_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $and $and$libresoc.v:41431$1853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $and $and$libresoc.v:42057$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \B_SIGNED 0 @@ -67197,10 +68130,10 @@ module \core parameter \Y_WIDTH 12 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:41431$1853_Y + connect \Y $and$libresoc.v:42057$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41436$1858 + cell $and $and$libresoc.v:42062$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67208,10 +68141,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41436$1858_Y + connect \Y $and$libresoc.v:42062$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41437$1859 + cell $and $and$libresoc.v:42063$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67219,10 +68152,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41437$1859_Y + connect \Y $and$libresoc.v:42063$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41440$1862 + cell $and $and$libresoc.v:42066$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67230,10 +68163,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41440$1862_Y + connect \Y $and$libresoc.v:42066$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41443$1865 + cell $and $and$libresoc.v:42069$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67241,10 +68174,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41443$1865_Y + connect \Y $and$libresoc.v:42069$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41450$1872 + cell $and $and$libresoc.v:42076$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67252,10 +68185,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41450$1872_Y + connect \Y $and$libresoc.v:42076$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41451$1873 + cell $and $and$libresoc.v:42077$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67263,10 +68196,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41451$1873_Y + connect \Y $and$libresoc.v:42077$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41454$1876 + cell $and $and$libresoc.v:42080$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67274,10 +68207,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41454$1876_Y + connect \Y $and$libresoc.v:42080$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41457$1879 + cell $and $and$libresoc.v:42083$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67285,10 +68218,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41457$1879_Y + connect \Y $and$libresoc.v:42083$1914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41458$1880 + cell $and $and$libresoc.v:42084$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67296,10 +68229,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41458$1880_Y + connect \Y $and$libresoc.v:42084$1915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41461$1883 + cell $and $and$libresoc.v:42087$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67307,10 +68240,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41461$1883_Y + connect \Y $and$libresoc.v:42087$1918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:41463$1885 + cell $and $and$libresoc.v:42089$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67318,10 +68251,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41463$1885_Y + connect \Y $and$libresoc.v:42089$1920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:41464$1886 + cell $and $and$libresoc.v:42090$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67329,10 +68262,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:41464$1886_Y + connect \Y $and$libresoc.v:42090$1921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41468$1890 + cell $and $and$libresoc.v:42094$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67340,10 +68273,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41468$1890_Y + connect \Y $and$libresoc.v:42094$1925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41472$1894 + cell $and $and$libresoc.v:42098$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67351,10 +68284,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41472$1894_Y + connect \Y $and$libresoc.v:42098$1929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41473$1895 + cell $and $and$libresoc.v:42099$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67362,10 +68295,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41473$1895_Y + connect \Y $and$libresoc.v:42099$1930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41476$1898 + cell $and $and$libresoc.v:42102$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67373,10 +68306,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41476$1898_Y + connect \Y $and$libresoc.v:42102$1933_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41479$1901 + cell $and $and$libresoc.v:42105$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67384,10 +68317,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41479$1901_Y + connect \Y $and$libresoc.v:42105$1936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41480$1902 + cell $and $and$libresoc.v:42106$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67395,10 +68328,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41480$1902_Y + connect \Y $and$libresoc.v:42106$1937_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41483$1905 + cell $and $and$libresoc.v:42109$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67406,10 +68339,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41483$1905_Y + connect \Y $and$libresoc.v:42109$1940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41486$1908 + cell $and $and$libresoc.v:42112$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67417,10 +68350,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41486$1908_Y + connect \Y $and$libresoc.v:42112$1943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41487$1909 + cell $and $and$libresoc.v:42113$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67428,10 +68361,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41487$1909_Y + connect \Y $and$libresoc.v:42113$1944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41490$1912 + cell $and $and$libresoc.v:42116$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67439,10 +68372,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41490$1912_Y + connect \Y $and$libresoc.v:42116$1947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41493$1915 + cell $and $and$libresoc.v:42119$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67450,10 +68383,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41493$1915_Y + connect \Y $and$libresoc.v:42119$1950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41498$1920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42124$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67461,32 +68394,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41498$1920_Y + connect \Y $and$libresoc.v:42124$1955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41499$1921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42125$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$331 + connect \A \$345 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41499$1921_Y + connect \Y $and$libresoc.v:42125$1956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41501$1923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42127$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$333 - connect \B \$335 - connect \Y $and$libresoc.v:41501$1923_Y + connect \A \$347 + connect \B \$349 + connect \Y $and$libresoc.v:42127$1958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41502$1924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42128$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67494,43 +68427,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41502$1924_Y + connect \Y $and$libresoc.v:42128$1959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41504$1926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42130$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [0] + connect \A \fus_cu_rd__rel_o$38 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41504$1926_Y + connect \Y $and$libresoc.v:42130$1961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41505$1927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42131$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$343 + connect \A \$357 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41505$1927_Y + connect \Y $and$libresoc.v:42131$1962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41507$1929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42133$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$345 - connect \B \$347 - connect \Y $and$libresoc.v:41507$1929_Y + connect \A \$359 + connect \B \$361 + connect \Y $and$libresoc.v:42133$1964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41508$1930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42134$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67538,43 +68471,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41508$1930_Y + connect \Y $and$libresoc.v:42134$1965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41510$1932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42136$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [0] + connect \A \fus_cu_rd__rel_o$41 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41510$1932_Y + connect \Y $and$libresoc.v:42136$1967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41511$1933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42137$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$355 + connect \A \$369 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41511$1933_Y + connect \Y $and$libresoc.v:42137$1968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41513$1935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42139$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$357 - connect \B \$359 - connect \Y $and$libresoc.v:41513$1935_Y + connect \A \$371 + connect \B \$373 + connect \Y $and$libresoc.v:42139$1970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41514$1936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42140$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67582,43 +68515,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41514$1936_Y + connect \Y $and$libresoc.v:42140$1971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41516$1938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42142$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [0] + connect \A \fus_cu_rd__rel_o$44 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41516$1938_Y + connect \Y $and$libresoc.v:42142$1973_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41517$1939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42143$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$367 + connect \A \$381 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41517$1939_Y + connect \Y $and$libresoc.v:42143$1974_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41519$1941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42145$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$369 - connect \B \$371 - connect \Y $and$libresoc.v:41519$1941_Y + connect \A \$383 + connect \B \$385 + connect \Y $and$libresoc.v:42145$1976_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41520$1942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42146$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67626,43 +68559,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41520$1942_Y + connect \Y $and$libresoc.v:42146$1977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41522$1944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42148$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [0] + connect \A \fus_cu_rd__rel_o$47 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41522$1944_Y + connect \Y $and$libresoc.v:42148$1979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41523$1945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42149$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$379 + connect \A \$393 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41523$1945_Y + connect \Y $and$libresoc.v:42149$1980_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41525$1947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42151$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \$383 - connect \Y $and$libresoc.v:41525$1947_Y + connect \A \$395 + connect \B \$397 + connect \Y $and$libresoc.v:42151$1982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41526$1948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42152$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67670,43 +68603,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41526$1948_Y + connect \Y $and$libresoc.v:42152$1983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41528$1950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42154$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [0] + connect \A \fus_cu_rd__rel_o$50 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41528$1950_Y + connect \Y $and$libresoc.v:42154$1985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41529$1951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42155$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$391 + connect \A \$405 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41529$1951_Y + connect \Y $and$libresoc.v:42155$1986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41531$1953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42157$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$393 - connect \B \$395 - connect \Y $and$libresoc.v:41531$1953_Y + connect \A \$407 + connect \B \$409 + connect \Y $and$libresoc.v:42157$1988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41532$1954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42158$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67714,43 +68647,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41532$1954_Y + connect \Y $and$libresoc.v:42158$1989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41534$1956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42160$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [0] + connect \A \fus_cu_rd__rel_o$53 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41534$1956_Y + connect \Y $and$libresoc.v:42160$1991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41535$1957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42161$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$403 + connect \A \$417 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41535$1957_Y + connect \Y $and$libresoc.v:42161$1992_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41537$1959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42163$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$405 - connect \B \$407 - connect \Y $and$libresoc.v:41537$1959_Y + connect \A \$419 + connect \B \$421 + connect \Y $and$libresoc.v:42163$1994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41538$1960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42164$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67758,43 +68691,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41538$1960_Y + connect \Y $and$libresoc.v:42164$1995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41540$1962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42166$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [0] + connect \A \fus_cu_rd__rel_o$56 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41540$1962_Y + connect \Y $and$libresoc.v:42166$1997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41541$1963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42167$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$415 + connect \A \$429 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41541$1963_Y + connect \Y $and$libresoc.v:42167$1998_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41543$1965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42169$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$417 - connect \B \$419 - connect \Y $and$libresoc.v:41543$1965_Y + connect \A \$431 + connect \B \$433 + connect \Y $and$libresoc.v:42169$2000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41544$1966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42170$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67802,43 +68735,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41544$1966_Y + connect \Y $and$libresoc.v:42170$2001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41546$1968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42172$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [0] + connect \A \fus_cu_rd__rel_o$59 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41546$1968_Y + connect \Y $and$libresoc.v:42172$2003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41547$1969 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42173$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$427 + connect \A \$441 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:41547$1969_Y + connect \Y $and$libresoc.v:42173$2004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41549$1971 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42175$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 - connect \B \$431 - connect \Y $and$libresoc.v:41549$1971_Y + connect \A \$443 + connect \B \$445 + connect \Y $and$libresoc.v:42175$2006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41550$1972 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42176$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67846,10 +68779,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:41550$1972_Y + connect \Y $and$libresoc.v:42176$2007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41561$1983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42187$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67857,32 +68790,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41561$1983_Y + connect \Y $and$libresoc.v:42187$2018_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41562$1984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42188$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$457 + connect \A \$471 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41562$1984_Y + connect \Y $and$libresoc.v:42188$2019_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41564$1986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42190$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$459 - connect \B \$461 - connect \Y $and$libresoc.v:41564$1986_Y + connect \A \$473 + connect \B \$475 + connect \Y $and$libresoc.v:42190$2021_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41565$1987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42191$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67890,43 +68823,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41565$1987_Y + connect \Y $and$libresoc.v:42191$2022_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41567$1989 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42193$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [1] + connect \A \fus_cu_rd__rel_o$38 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41567$1989_Y + connect \Y $and$libresoc.v:42193$2024_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41568$1990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42194$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$469 + connect \A \$483 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41568$1990_Y + connect \Y $and$libresoc.v:42194$2025_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41570$1992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42196$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 - connect \B \$473 - connect \Y $and$libresoc.v:41570$1992_Y + connect \A \$485 + connect \B \$487 + connect \Y $and$libresoc.v:42196$2027_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41571$1993 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42197$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67934,43 +68867,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41571$1993_Y + connect \Y $and$libresoc.v:42197$2028_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41573$1995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42199$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [1] + connect \A \fus_cu_rd__rel_o$41 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41573$1995_Y + connect \Y $and$libresoc.v:42199$2030_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41574$1996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42200$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$481 + connect \A \$495 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41574$1996_Y + connect \Y $and$libresoc.v:42200$2031_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41576$1998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42202$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$483 - connect \B \$485 - connect \Y $and$libresoc.v:41576$1998_Y + connect \A \$497 + connect \B \$499 + connect \Y $and$libresoc.v:42202$2033_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41577$1999 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42203$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67978,43 +68911,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41577$1999_Y + connect \Y $and$libresoc.v:42203$2034_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41579$2001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42205$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [1] + connect \A \fus_cu_rd__rel_o$44 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41579$2001_Y + connect \Y $and$libresoc.v:42205$2036_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41580$2002 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42206$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$493 + connect \A \$507 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41580$2002_Y + connect \Y $and$libresoc.v:42206$2037_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41582$2004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42208$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$495 - connect \B \$497 - connect \Y $and$libresoc.v:41582$2004_Y + connect \A \$509 + connect \B \$511 + connect \Y $and$libresoc.v:42208$2039_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41583$2005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42209$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68022,43 +68955,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41583$2005_Y + connect \Y $and$libresoc.v:42209$2040_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41585$2007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42211$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [1] + connect \A \fus_cu_rd__rel_o$50 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41585$2007_Y + connect \Y $and$libresoc.v:42211$2042_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41586$2008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42212$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$505 + connect \A \$519 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41586$2008_Y + connect \Y $and$libresoc.v:42212$2043_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41588$2010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42214$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$507 - connect \B \$509 - connect \Y $and$libresoc.v:41588$2010_Y + connect \A \$521 + connect \B \$523 + connect \Y $and$libresoc.v:42214$2045_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41589$2011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42215$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68066,43 +68999,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41589$2011_Y + connect \Y $and$libresoc.v:42215$2046_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41591$2013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42217$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [1] + connect \A \fus_cu_rd__rel_o$53 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41591$2013_Y + connect \Y $and$libresoc.v:42217$2048_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41592$2014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42218$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$517 + connect \A \$531 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41592$2014_Y + connect \Y $and$libresoc.v:42218$2049_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41594$2016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42220$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$519 - connect \B \$521 - connect \Y $and$libresoc.v:41594$2016_Y + connect \A \$533 + connect \B \$535 + connect \Y $and$libresoc.v:42220$2051_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41595$2017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42221$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68110,43 +69043,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41595$2017_Y + connect \Y $and$libresoc.v:42221$2052_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41597$2019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42223$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [1] + connect \A \fus_cu_rd__rel_o$56 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41597$2019_Y + connect \Y $and$libresoc.v:42223$2054_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41598$2020 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42224$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$529 + connect \A \$543 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41598$2020_Y + connect \Y $and$libresoc.v:42224$2055_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41600$2022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42226$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$531 - connect \B \$533 - connect \Y $and$libresoc.v:41600$2022_Y + connect \A \$545 + connect \B \$547 + connect \Y $and$libresoc.v:42226$2057_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41601$2023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42227$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68154,43 +69087,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41601$2023_Y + connect \Y $and$libresoc.v:42227$2058_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41603$2025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42229$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [1] + connect \A \fus_cu_rd__rel_o$59 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41603$2025_Y + connect \Y $and$libresoc.v:42229$2060_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41604$2026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42230$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$541 + connect \A \$555 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:41604$2026_Y + connect \Y $and$libresoc.v:42230$2061_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41606$2028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42232$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$543 - connect \B \$545 - connect \Y $and$libresoc.v:41606$2028_Y + connect \A \$557 + connect \B \$559 + connect \Y $and$libresoc.v:42232$2063_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41607$2029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42233$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68198,43 +69131,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:41607$2029_Y + connect \Y $and$libresoc.v:42233$2064_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41617$2039 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42243$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [2] + connect \A \fus_cu_rd__rel_o$56 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41617$2039_Y + connect \Y $and$libresoc.v:42243$2074_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41618$2040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42244$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$569 + connect \A \$583 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:41618$2040_Y + connect \Y $and$libresoc.v:42244$2075_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41620$2042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42246$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$571 - connect \B \$573 - connect \Y $and$libresoc.v:41620$2042_Y + connect \A \$585 + connect \B \$587 + connect \Y $and$libresoc.v:42246$2077_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41621$2043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42247$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68242,43 +69175,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:41621$2043_Y + connect \Y $and$libresoc.v:42247$2078_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41623$2045 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42249$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [2] + connect \A \fus_cu_rd__rel_o$59 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41623$2045_Y + connect \Y $and$libresoc.v:42249$2080_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41624$2046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42250$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$581 + connect \A \$595 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:41624$2046_Y + connect \Y $and$libresoc.v:42250$2081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41626$2048 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42252$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$583 - connect \B \$585 - connect \Y $and$libresoc.v:41626$2048_Y + connect \A \$597 + connect \B \$599 + connect \Y $and$libresoc.v:42252$2083_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41627$2049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42253$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68286,10 +69219,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:41627$2049_Y + connect \Y $and$libresoc.v:42253$2084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41631$2053 + cell $and $and$libresoc.v:42257$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68297,10 +69230,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41631$2053_Y + connect \Y $and$libresoc.v:42257$2088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:41632$2054 + cell $and $and$libresoc.v:42258$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68308,10 +69241,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:41632$2054_Y + connect \Y $and$libresoc.v:42258$2089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:41635$2057 + cell $and $and$libresoc.v:42261$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68319,10 +69252,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:41635$2057_Y + connect \Y $and$libresoc.v:42261$2092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41637$2059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42263$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68330,32 +69263,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41637$2059_Y + connect \Y $and$libresoc.v:42263$2094_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41638$2060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42264$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$609 + connect \A \$623 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41638$2060_Y + connect \Y $and$libresoc.v:42264$2095_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41640$2062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42266$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$611 - connect \B \$613 - connect \Y $and$libresoc.v:41640$2062_Y + connect \A \$625 + connect \B \$627 + connect \Y $and$libresoc.v:42266$2097_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41641$2063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42267$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68363,43 +69296,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41641$2063_Y + connect \Y $and$libresoc.v:42267$2098_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41643$2065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42269$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [2] + connect \A \fus_cu_rd__rel_o$44 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41643$2065_Y + connect \Y $and$libresoc.v:42269$2100_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41644$2066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42270$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$621 + connect \A \$635 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41644$2066_Y + connect \Y $and$libresoc.v:42270$2101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41646$2068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42272$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$623 - connect \B \$625 - connect \Y $and$libresoc.v:41646$2068_Y + connect \A \$637 + connect \B \$639 + connect \Y $and$libresoc.v:42272$2103_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41647$2069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42273$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68407,43 +69340,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41647$2069_Y + connect \Y $and$libresoc.v:42273$2104_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41649$2071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42275$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [3] + connect \A \fus_cu_rd__rel_o$47 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41649$2071_Y + connect \Y $and$libresoc.v:42275$2106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41650$2072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42276$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$633 + connect \A \$647 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41650$2072_Y + connect \Y $and$libresoc.v:42276$2107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41652$2074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42278$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$635 - connect \B \$637 - connect \Y $and$libresoc.v:41652$2074_Y + connect \A \$649 + connect \B \$651 + connect \Y $and$libresoc.v:42278$2109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41653$2075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42279$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68451,43 +69384,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41653$2075_Y + connect \Y $and$libresoc.v:42279$2110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41655$2077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42281$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [2] + connect \A \fus_cu_rd__rel_o$50 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41655$2077_Y + connect \Y $and$libresoc.v:42281$2112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41656$2078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42282$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$645 + connect \A \$659 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41656$2078_Y + connect \Y $and$libresoc.v:42282$2113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41658$2080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42284$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$647 - connect \B \$649 - connect \Y $and$libresoc.v:41658$2080_Y + connect \A \$661 + connect \B \$663 + connect \Y $and$libresoc.v:42284$2115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41659$2081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42285$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68495,43 +69428,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41659$2081_Y + connect \Y $and$libresoc.v:42285$2116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41661$2083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42287$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [2] + connect \A \fus_cu_rd__rel_o$53 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41661$2083_Y + connect \Y $and$libresoc.v:42287$2118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41662$2084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42288$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$657 + connect \A \$671 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41662$2084_Y + connect \Y $and$libresoc.v:42288$2119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41664$2086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42290$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$659 - connect \B \$661 - connect \Y $and$libresoc.v:41664$2086_Y + connect \A \$673 + connect \B \$675 + connect \Y $and$libresoc.v:42290$2121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41665$2087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42291$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68539,43 +69472,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41665$2087_Y + connect \Y $and$libresoc.v:42291$2122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41667$2089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42293$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [3] + connect \A \fus_cu_rd__rel_o$56 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41667$2089_Y + connect \Y $and$libresoc.v:42293$2124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41668$2090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42294$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$669 + connect \A \$683 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:41668$2090_Y + connect \Y $and$libresoc.v:42294$2125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41670$2092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42296$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$671 - connect \B \$673 - connect \Y $and$libresoc.v:41670$2092_Y + connect \A \$685 + connect \B \$687 + connect \Y $and$libresoc.v:42296$2127_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41671$2093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42297$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68583,10 +69516,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:41671$2093_Y + connect \Y $and$libresoc.v:42297$2128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:41680$2103 + cell $and $and$libresoc.v:42306$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68594,10 +69527,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:41680$2103_Y + connect \Y $and$libresoc.v:42306$2138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41683$2106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42309$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68605,32 +69538,32 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41683$2106_Y + connect \Y $and$libresoc.v:42309$2141_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41684$2107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42310$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$701 + connect \A \$715 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:41684$2107_Y + connect \Y $and$libresoc.v:42310$2142_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41686$2109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42312$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$703 - connect \B \$705 - connect \Y $and$libresoc.v:41686$2109_Y + connect \A \$717 + connect \B \$719 + connect \Y $and$libresoc.v:42312$2144_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41687$2110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42313$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68638,43 +69571,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41687$2110_Y + connect \Y $and$libresoc.v:42313$2145_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41689$2112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42315$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [5] + connect \A \fus_cu_rd__rel_o$47 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41689$2112_Y + connect \Y $and$libresoc.v:42315$2147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41690$2113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42316$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$713 + connect \A \$727 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:41690$2113_Y + connect \Y $and$libresoc.v:42316$2148_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41692$2115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42318$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$715 - connect \B \$717 - connect \Y $and$libresoc.v:41692$2115_Y + connect \A \$729 + connect \B \$731 + connect \Y $and$libresoc.v:42318$2150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41693$2116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42319$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68682,43 +69615,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41693$2116_Y + connect \Y $and$libresoc.v:42319$2151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41695$2118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42321$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [4] + connect \A \fus_cu_rd__rel_o$56 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41695$2118_Y + connect \Y $and$libresoc.v:42321$2153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41696$2119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42322$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$725 + connect \A \$739 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:41696$2119_Y + connect \Y $and$libresoc.v:42322$2154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41698$2121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42324$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$727 - connect \B \$729 - connect \Y $and$libresoc.v:41698$2121_Y + connect \A \$741 + connect \B \$743 + connect \Y $and$libresoc.v:42324$2156_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41699$2122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42325$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68726,10 +69659,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41699$2122_Y + connect \Y $and$libresoc.v:42325$2157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:41704$2128 + cell $and $and$libresoc.v:42330$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68737,10 +69670,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:41704$2128_Y + connect \Y $and$libresoc.v:42330$2163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:41705$2129 + cell $and $and$libresoc.v:42331$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68748,43 +69681,43 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:41705$2129_Y + connect \Y $and$libresoc.v:42331$2164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41708$2132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42334$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [4] + connect \A \fus_cu_rd__rel_o$47 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41708$2132_Y + connect \Y $and$libresoc.v:42334$2167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41709$2133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42335$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$751 + connect \A \$765 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:41709$2133_Y + connect \Y $and$libresoc.v:42335$2168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41711$2135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42337$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$753 - connect \B \$755 - connect \Y $and$libresoc.v:41711$2135_Y + connect \A \$767 + connect \B \$769 + connect \Y $and$libresoc.v:42337$2170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41712$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42338$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68792,43 +69725,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41712$2136_Y + connect \Y $and$libresoc.v:42338$2171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41714$2138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42340$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [2] + connect \A \fus_cu_rd__rel_o$38 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41714$2138_Y + connect \Y $and$libresoc.v:42340$2173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41715$2139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42341$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$763 + connect \A \$777 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:41715$2139_Y + connect \Y $and$libresoc.v:42341$2174_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41717$2141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42343$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$765 - connect \B \$767 - connect \Y $and$libresoc.v:41717$2141_Y + connect \A \$779 + connect \B \$781 + connect \Y $and$libresoc.v:42343$2176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41718$2142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42344$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68836,43 +69769,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41718$2142_Y + connect \Y $and$libresoc.v:42344$2177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41720$2144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42346$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [3] + connect \A \fus_cu_rd__rel_o$38 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41720$2144_Y + connect \Y $and$libresoc.v:42346$2179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41721$2145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42347$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$775 + connect \A \$789 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:41721$2145_Y + connect \Y $and$libresoc.v:42347$2180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41723$2147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42349$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$777 - connect \B \$779 - connect \Y $and$libresoc.v:41723$2147_Y + connect \A \$791 + connect \B \$793 + connect \Y $and$libresoc.v:42349$2182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41724$2148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42350$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68880,43 +69813,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41724$2148_Y + connect \Y $and$libresoc.v:42350$2183_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41728$2152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42354$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [2] + connect \A \fus_cu_rd__rel_o$79 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41728$2152_Y + connect \Y $and$libresoc.v:42354$2187_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41729$2153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42355$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$791 + connect \A \$805 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:41729$2153_Y + connect \Y $and$libresoc.v:42355$2188_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41731$2155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42357$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$793 - connect \B \$795 - connect \Y $and$libresoc.v:41731$2155_Y + connect \A \$807 + connect \B \$809 + connect \Y $and$libresoc.v:42357$2190_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41732$2156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42358$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68924,43 +69857,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41732$2156_Y + connect \Y $and$libresoc.v:42358$2191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41737$2161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42363$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [4] + connect \A \fus_cu_rd__rel_o$38 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41737$2161_Y + connect \Y $and$libresoc.v:42363$2196_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41738$2162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42364$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$810 + connect \A \$824 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:41738$2162_Y + connect \Y $and$libresoc.v:42364$2197_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41740$2164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42366$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$812 - connect \B \$814 - connect \Y $and$libresoc.v:41740$2164_Y + connect \A \$826 + connect \B \$828 + connect \Y $and$libresoc.v:42366$2199_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41741$2165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42367$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68968,43 +69901,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:41741$2165_Y + connect \Y $and$libresoc.v:42367$2200_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41745$2169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42371$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [5] + connect \A \fus_cu_rd__rel_o$38 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41745$2169_Y + connect \Y $and$libresoc.v:42371$2204_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41746$2170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42372$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$826 + connect \A \$840 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:41746$2170_Y + connect \Y $and$libresoc.v:42372$2205_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41748$2172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42374$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$828 - connect \B \$830 - connect \Y $and$libresoc.v:41748$2172_Y + connect \A \$842 + connect \B \$844 + connect \Y $and$libresoc.v:42374$2207_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41749$2173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42375$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69012,43 +69945,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:41749$2173_Y + connect \Y $and$libresoc.v:42375$2208_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41753$2177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42379$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [0] + connect \A \fus_cu_rd__rel_o$79 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41753$2177_Y + connect \Y $and$libresoc.v:42379$2212_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41754$2178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42380$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$842 + connect \A \$856 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:41754$2178_Y + connect \Y $and$libresoc.v:42380$2213_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41756$2180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42382$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$844 - connect \B \$846 - connect \Y $and$libresoc.v:41756$2180_Y + connect \A \$858 + connect \B \$860 + connect \Y $and$libresoc.v:42382$2215_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41757$2181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42383$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69056,43 +69989,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41757$2181_Y + connect \Y $and$libresoc.v:42383$2216_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41759$2183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42385$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [2] + connect \A \fus_cu_rd__rel_o$41 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41759$2183_Y + connect \Y $and$libresoc.v:42385$2218_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41760$2184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42386$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$854 + connect \A \$868 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:41760$2184_Y + connect \Y $and$libresoc.v:42386$2219_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41762$2186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42388$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$856 - connect \B \$858 - connect \Y $and$libresoc.v:41762$2186_Y + connect \A \$870 + connect \B \$872 + connect \Y $and$libresoc.v:42388$2221_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41763$2187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42389$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69100,43 +70033,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41763$2187_Y + connect \Y $and$libresoc.v:42389$2222_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41765$2189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42391$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [2] + connect \A \fus_cu_rd__rel_o$47 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41765$2189_Y + connect \Y $and$libresoc.v:42391$2224_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41766$2190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42392$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$866 + connect \A \$880 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:41766$2190_Y + connect \Y $and$libresoc.v:42392$2225_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41768$2192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42394$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$868 - connect \B \$870 - connect \Y $and$libresoc.v:41768$2192_Y + connect \A \$882 + connect \B \$884 + connect \Y $and$libresoc.v:42394$2227_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41769$2193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42395$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69144,43 +70077,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:41769$2193_Y + connect \Y $and$libresoc.v:42395$2228_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41774$2198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42400$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [1] + connect \A \fus_cu_rd__rel_o$79 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:41774$2198_Y + connect \Y $and$libresoc.v:42400$2233_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41775$2199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42401$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$884 + connect \A \$898 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:41775$2199_Y + connect \Y $and$libresoc.v:42401$2234_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41777$2201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42403$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$886 - connect \B \$888 - connect \Y $and$libresoc.v:41777$2201_Y + connect \A \$900 + connect \B \$902 + connect \Y $and$libresoc.v:42403$2236_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41778$2202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42404$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69188,43 +70121,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:41778$2202_Y + connect \Y $and$libresoc.v:42404$2237_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41780$2204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42406$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [3] + connect \A \fus_cu_rd__rel_o$41 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41780$2204_Y + connect \Y $and$libresoc.v:42406$2239_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41781$2205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42407$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$896 + connect \A \$910 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:41781$2205_Y + connect \Y $and$libresoc.v:42407$2240_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41783$2207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42409$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$898 - connect \B \$900 - connect \Y $and$libresoc.v:41783$2207_Y + connect \A \$912 + connect \B \$914 + connect \Y $and$libresoc.v:42409$2242_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41784$2208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42410$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69232,43 +70165,43 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:41784$2208_Y + connect \Y $and$libresoc.v:42410$2243_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41788$2212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42414$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [1] + connect \A \fus_cu_rd__rel_o$47 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41788$2212_Y + connect \Y $and$libresoc.v:42414$2247_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:278" - cell $and $and$libresoc.v:41789$2213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" + cell $and $and$libresoc.v:42415$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$912 + connect \A \$926 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:41789$2213_Y + connect \Y $and$libresoc.v:42415$2248_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $and $and$libresoc.v:41791$2215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $and $and$libresoc.v:42417$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$914 - connect \B \$916 - connect \Y $and$libresoc.v:41791$2215_Y + connect \A \$928 + connect \B \$930 + connect \Y $and$libresoc.v:42417$2250_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $and $and$libresoc.v:41792$2216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" + cell $and $and$libresoc.v:42418$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69276,10 +70209,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:41792$2216_Y + connect \Y $and$libresoc.v:42418$2251_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41795$2219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42421$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69287,10 +70220,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41795$2219_Y + connect \Y $and$libresoc.v:42421$2254_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41796$2220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42422$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69298,109 +70231,109 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41796$2220_Y + connect \Y $and$libresoc.v:42422$2255_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41797$2221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42423$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [0] + connect \A \fus_cu_wr__rel_o$91 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41797$2221_Y + connect \Y $and$libresoc.v:42423$2256_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41798$2222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42424$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [0] + connect \A \fus_cu_wr__rel_o$94 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:41798$2222_Y + connect \Y $and$libresoc.v:42424$2257_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41799$2223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42425$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [0] + connect \A \fus_cu_wr__rel_o$97 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41799$2223_Y + connect \Y $and$libresoc.v:42425$2258_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41800$2224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42426$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [0] + connect \A \fus_cu_wr__rel_o$100 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41800$2224_Y + connect \Y $and$libresoc.v:42426$2259_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41801$2225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42427$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [0] + connect \A \fus_cu_wr__rel_o$103 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41801$2225_Y + connect \Y $and$libresoc.v:42427$2260_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41802$2226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42428$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [0] + connect \A \fus_cu_wr__rel_o$106 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41802$2226_Y + connect \Y $and$libresoc.v:42428$2261_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41803$2227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42429$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [0] + connect \A \fus_cu_wr__rel_o$109 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41803$2227_Y + connect \Y $and$libresoc.v:42429$2262_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41804$2228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42430$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [0] + connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41804$2228_Y + connect \Y $and$libresoc.v:42430$2263_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:404" - cell $and $and$libresoc.v:41805$2229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:402" + cell $and $and$libresoc.v:42431$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [1] + connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:41805$2229_Y + connect \Y $and$libresoc.v:42431$2264_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41806$2230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42432$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69408,21 +70341,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41806$2230_Y + connect \Y $and$libresoc.v:42432$2265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41808$2232 + cell $and $and$libresoc.v:42434$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick - connect \B \$950 - connect \Y $and$libresoc.v:41808$2232_Y + connect \B \$964 + connect \Y $and$libresoc.v:42434$2267_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41809$2233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42435$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69430,21 +70363,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41809$2233_Y + connect \Y $and$libresoc.v:42435$2268_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41811$2235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42437$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$83 - connect \B \fus_cu_busy_o$5 - connect \Y $and$libresoc.v:41811$2235_Y + connect \A \fus_o_ok$90 + connect \B \fus_cu_busy_o$12 + connect \Y $and$libresoc.v:42437$2270_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41812$2236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42438$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69452,43 +70385,43 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41812$2236_Y + connect \Y $and$libresoc.v:42438$2271_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41814$2238 + cell $and $and$libresoc.v:42440$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B \$969 - connect \Y $and$libresoc.v:41814$2238_Y + connect \A \wr_pick$978 + connect \B \$983 + connect \Y $and$libresoc.v:42440$2273_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41815$2239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $and $and$libresoc.v:42441$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$964 + connect \A \wr_pick$978 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41815$2239_Y + connect \Y $and$libresoc.v:42441$2274_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:400" - cell $and $and$libresoc.v:41817$2241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" + cell $and $and$libresoc.v:42443$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_o_ok$86 - connect \B \fus_cu_busy_o$11 - connect \Y $and$libresoc.v:41817$2241_Y + connect \A \fus_o_ok$93 + connect \B \fus_cu_busy_o$18 + connect \Y $and$libresoc.v:42443$2276_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $and $and$libresoc.v:41818$2242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" + cell $and $and$libresoc.v:42444$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69496,43 +70429,21 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41818$2242_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41820$2244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \$988 - connect \Y $and$libresoc.v:41820$2244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:416" - cell $and $and$libresoc.v:41821$2245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41821$2245_Y + connect \Y $and$libresoc.v:42444$2277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41438$1860 + cell $eq $eq$libresoc.v:42064$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$210 + connect \A \$224 connect \B 1'1 - connect \Y $eq$libresoc.v:41438$1860_Y + connect \Y $eq$libresoc.v:42064$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41442$1864 + cell $eq $eq$libresoc.v:42068$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69540,54 +70451,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41442$1864_Y + connect \Y $eq$libresoc.v:42068$1899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41444$1866 + cell $eq $eq$libresoc.v:42070$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$222 + connect \A \$236 connect \B 3'100 - connect \Y $eq$libresoc.v:41444$1866_Y + connect \Y $eq$libresoc.v:42070$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41452$1874 + cell $eq $eq$libresoc.v:42078$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$238 + connect \A \$252 connect \B 1'1 - connect \Y $eq$libresoc.v:41452$1874_Y + connect \Y $eq$libresoc.v:42078$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41459$1881 + cell $eq $eq$libresoc.v:42085$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$252 + connect \A \$266 connect \B 1'1 - connect \Y $eq$libresoc.v:41459$1881_Y + connect \Y $eq$libresoc.v:42085$1916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:41465$1887 + cell $eq $eq$libresoc.v:42091$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$264 + connect \A \$278 connect \B 2'10 - connect \Y $eq$libresoc.v:41465$1887_Y + connect \Y $eq$libresoc.v:42091$1922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41467$1889 + cell $eq $eq$libresoc.v:42093$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69595,54 +70506,54 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41467$1889_Y + connect \Y $eq$libresoc.v:42093$1924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41469$1891 + cell $eq $eq$libresoc.v:42095$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$272 + connect \A \$286 connect \B 3'100 - connect \Y $eq$libresoc.v:41469$1891_Y + connect \Y $eq$libresoc.v:42095$1926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41474$1896 + cell $eq $eq$libresoc.v:42100$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$282 + connect \A \$296 connect \B 1'1 - connect \Y $eq$libresoc.v:41474$1896_Y + connect \Y $eq$libresoc.v:42100$1931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41481$1903 + cell $eq $eq$libresoc.v:42107$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$296 + connect \A \$310 connect \B 1'1 - connect \Y $eq$libresoc.v:41481$1903_Y + connect \Y $eq$libresoc.v:42107$1938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41488$1910 + cell $eq $eq$libresoc.v:42114$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$310 + connect \A \$324 connect \B 1'1 - connect \Y $eq$libresoc.v:41488$1910_Y + connect \Y $eq$libresoc.v:42114$1945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41492$1914 + cell $eq $eq$libresoc.v:42118$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69650,32 +70561,32 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41492$1914_Y + connect \Y $eq$libresoc.v:42118$1949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41494$1916 + cell $eq $eq$libresoc.v:42120$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$322 + connect \A \$336 connect \B 3'100 - connect \Y $eq$libresoc.v:41494$1916_Y + connect \Y $eq$libresoc.v:42120$1951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:41633$2055 + cell $eq $eq$libresoc.v:42259$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$599 + connect \A \$613 connect \B 1'1 - connect \Y $eq$libresoc.v:41633$2055_Y + connect \Y $eq$libresoc.v:42259$2090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:41679$2102 + cell $eq $eq$libresoc.v:42305$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69683,88 +70594,88 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:41679$2102_Y + connect \Y $eq$libresoc.v:42305$2137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:41681$2104 + cell $eq $eq$libresoc.v:42307$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$695 + connect \A \$709 connect \B 3'100 - connect \Y $eq$libresoc.v:41681$2104_Y + connect \Y $eq$libresoc.v:42307$2139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:41706$2130 + cell $eq $eq$libresoc.v:42332$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$745 + connect \A \$759 connect \B 2'10 - connect \Y $eq$libresoc.v:41706$2130_Y + connect \Y $eq$libresoc.v:42332$2165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41263$1680 + cell $pos $extend$libresoc.v:41889$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$1422 - connect \Y $extend$libresoc.v:41263$1680_Y + connect \A \$1436 + connect \Y $extend$libresoc.v:41889$1715_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41329$1747 + cell $pos $extend$libresoc.v:41955$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 - connect \A \$1586 - connect \Y $extend$libresoc.v:41329$1747_Y + connect \A \$1600 + connect \Y $extend$libresoc.v:41955$1782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41333$1752 + cell $pos $extend$libresoc.v:41959$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$1594 - connect \Y $extend$libresoc.v:41333$1752_Y + connect \A \$1608 + connect \Y $extend$libresoc.v:41959$1787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $extend$libresoc.v:41405$1825 + cell $pos $extend$libresoc.v:42024$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \$1753 - connect \Y $extend$libresoc.v:41405$1825_Y + connect \A \$1767 + connect \Y $extend$libresoc.v:42024$1853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $pos $extend$libresoc.v:41413$1834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + cell $pos $extend$libresoc.v:42033$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 4 - connect \A \addr_en$1771 - connect \Y $extend$libresoc.v:41413$1834_Y + connect \A \addr_en$1785 + connect \Y $extend$libresoc.v:42033$1863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41678$2100 + cell $pos $extend$libresoc.v:42304$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \$690 - connect \Y $extend$libresoc.v:41678$2100_Y + connect \A \$704 + connect \Y $extend$libresoc.v:42304$2135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $extend$libresoc.v:41703$2126 + cell $pos $extend$libresoc.v:42329$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$740 - connect \Y $extend$libresoc.v:41703$2126_Y + connect \A \$754 + connect \Y $extend$libresoc.v:42329$2161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - cell $ne $ne$libresoc.v:41433$1855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $ne $ne$libresoc.v:42059$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69772,10 +70683,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:41433$1855_Y + connect \Y $ne$libresoc.v:42059$1890_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - cell $ne $ne$libresoc.v:41435$1857 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + cell $ne $ne$libresoc.v:42061$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -69783,761 +70694,761 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:41435$1857_Y + connect \Y $ne$libresoc.v:42061$1892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:41720$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1000 + connect \Y $not$libresoc.v:41720$1546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41100$1517 + cell $not $not$libresoc.v:41726$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1007 - connect \Y $not$libresoc.v:41100$1517_Y + connect \A \wr_pick_dly$1021 + connect \Y $not$libresoc.v:41726$1552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41106$1523 + cell $not $not$libresoc.v:41732$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1025 - connect \Y $not$libresoc.v:41106$1523_Y + connect \A \wr_pick_dly$1039 + connect \Y $not$libresoc.v:41732$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41112$1529 + cell $not $not$libresoc.v:41738$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1047 - connect \Y $not$libresoc.v:41112$1529_Y + connect \A \wr_pick_dly$1061 + connect \Y $not$libresoc.v:41738$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41118$1535 + cell $not $not$libresoc.v:41744$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1067 - connect \Y $not$libresoc.v:41118$1535_Y + connect \A \wr_pick_dly$1081 + connect \Y $not$libresoc.v:41744$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41124$1541 + cell $not $not$libresoc.v:41750$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1087 - connect \Y $not$libresoc.v:41124$1541_Y + connect \A \wr_pick_dly$1101 + connect \Y $not$libresoc.v:41750$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41130$1547 + cell $not $not$libresoc.v:41756$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1106 - connect \Y $not$libresoc.v:41130$1547_Y + connect \A \wr_pick_dly$1120 + connect \Y $not$libresoc.v:41756$1582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41136$1553 + cell $not $not$libresoc.v:41762$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1124 - connect \Y $not$libresoc.v:41136$1553_Y + connect \A \wr_pick_dly$1138 + connect \Y $not$libresoc.v:41762$1588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41170$1587 + cell $not $not$libresoc.v:41796$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1197 - connect \Y $not$libresoc.v:41170$1587_Y + connect \A \wr_pick_dly$1211 + connect \Y $not$libresoc.v:41796$1622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41182$1599 + cell $not $not$libresoc.v:41808$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1225 - connect \Y $not$libresoc.v:41182$1599_Y + connect \A \wr_pick_dly$1239 + connect \Y $not$libresoc.v:41808$1634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41190$1607 + cell $not $not$libresoc.v:41816$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1245 - connect \Y $not$libresoc.v:41190$1607_Y + connect \A \wr_pick_dly$1259 + connect \Y $not$libresoc.v:41816$1642_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41198$1615 + cell $not $not$libresoc.v:41824$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1265 - connect \Y $not$libresoc.v:41198$1615_Y + connect \A \wr_pick_dly$1279 + connect \Y $not$libresoc.v:41824$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41206$1623 + cell $not $not$libresoc.v:41832$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1285 - connect \Y $not$libresoc.v:41206$1623_Y + connect \A \wr_pick_dly$1299 + connect \Y $not$libresoc.v:41832$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41214$1631 + cell $not $not$libresoc.v:41840$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1305 - connect \Y $not$libresoc.v:41214$1631_Y + connect \A \wr_pick_dly$1319 + connect \Y $not$libresoc.v:41840$1666_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41222$1639 + cell $not $not$libresoc.v:41848$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1325 - connect \Y $not$libresoc.v:41222$1639_Y + connect \A \wr_pick_dly$1339 + connect \Y $not$libresoc.v:41848$1674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41243$1660 + cell $not $not$libresoc.v:41869$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1372 - connect \Y $not$libresoc.v:41243$1660_Y + connect \A \wr_pick_dly$1386 + connect \Y $not$libresoc.v:41869$1695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41249$1666 + cell $not $not$libresoc.v:41875$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1388 - connect \Y $not$libresoc.v:41249$1666_Y + connect \A \wr_pick_dly$1402 + connect \Y $not$libresoc.v:41875$1701_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41255$1672 + cell $not $not$libresoc.v:41881$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1404 - connect \Y $not$libresoc.v:41255$1672_Y + connect \A \wr_pick_dly$1418 + connect \Y $not$libresoc.v:41881$1707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41270$1688 + cell $not $not$libresoc.v:41896$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1438 - connect \Y $not$libresoc.v:41270$1688_Y + connect \A \wr_pick_dly$1452 + connect \Y $not$libresoc.v:41896$1723_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41276$1694 + cell $not $not$libresoc.v:41902$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1454 - connect \Y $not$libresoc.v:41276$1694_Y + connect \A \wr_pick_dly$1468 + connect \Y $not$libresoc.v:41902$1729_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41282$1700 + cell $not $not$libresoc.v:41908$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1470 - connect \Y $not$libresoc.v:41282$1700_Y + connect \A \wr_pick_dly$1484 + connect \Y $not$libresoc.v:41908$1735_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41288$1706 + cell $not $not$libresoc.v:41914$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1486 - connect \Y $not$libresoc.v:41288$1706_Y + connect \A \wr_pick_dly$1500 + connect \Y $not$libresoc.v:41914$1741_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41304$1722 + cell $not $not$libresoc.v:41930$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1522 - connect \Y $not$libresoc.v:41304$1722_Y + connect \A \wr_pick_dly$1536 + connect \Y $not$libresoc.v:41930$1757_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41310$1728 + cell $not $not$libresoc.v:41936$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1538 - connect \Y $not$libresoc.v:41310$1728_Y + connect \A \wr_pick_dly$1552 + connect \Y $not$libresoc.v:41936$1763_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41316$1734 + cell $not $not$libresoc.v:41942$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1554 - connect \Y $not$libresoc.v:41316$1734_Y + connect \A \wr_pick_dly$1568 + connect \Y $not$libresoc.v:41942$1769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41322$1740 + cell $not $not$libresoc.v:41948$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1570 - connect \Y $not$libresoc.v:41322$1740_Y + connect \A \wr_pick_dly$1584 + connect \Y $not$libresoc.v:41948$1775_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41341$1761 + cell $not $not$libresoc.v:41967$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1612 - connect \Y $not$libresoc.v:41341$1761_Y + connect \A \wr_pick_dly$1626 + connect \Y $not$libresoc.v:41967$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41349$1769 + cell $not $not$libresoc.v:41973$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1631 - connect \Y $not$libresoc.v:41349$1769_Y + connect \A \wr_pick_dly$1645 + connect \Y $not$libresoc.v:41973$1802_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41355$1775 + cell $not $not$libresoc.v:41979$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1647 - connect \Y $not$libresoc.v:41355$1775_Y + connect \A \wr_pick_dly$1661 + connect \Y $not$libresoc.v:41979$1808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41362$1782 + cell $not $not$libresoc.v:41985$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1663 - connect \Y $not$libresoc.v:41362$1782_Y + connect \A \wr_pick_dly$1677 + connect \Y $not$libresoc.v:41985$1814_Y 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\A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:41716$2140_Y + connect \Y $not$libresoc.v:42342$2175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41722$2146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42348$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:41722$2146_Y + connect \Y $not$libresoc.v:42348$2181_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41730$2154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42356$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:41730$2154_Y + connect \Y $not$libresoc.v:42356$2189_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41739$2163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42365$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:41739$2163_Y + connect \Y $not$libresoc.v:42365$2198_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41747$2171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42373$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:41747$2171_Y + connect \Y $not$libresoc.v:42373$2206_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41755$2179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42381$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:41755$2179_Y + connect \Y $not$libresoc.v:42381$2214_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41761$2185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42387$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:41761$2185_Y + connect \Y $not$libresoc.v:42387$2220_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41767$2191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42393$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:41767$2191_Y + connect \Y $not$libresoc.v:42393$2226_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41776$2200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42402$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_branch0_0 - connect \Y $not$libresoc.v:41776$2200_Y + connect \Y $not$libresoc.v:42402$2235_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41782$2206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42408$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_trap0_1 - connect \Y $not$libresoc.v:41782$2206_Y + connect \Y $not$libresoc.v:42408$2241_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279" - cell $not $not$libresoc.v:41790$2214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $not $not$libresoc.v:42416$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:41790$2214_Y + connect \Y $not$libresoc.v:42416$2249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41807$2231 + cell $not $not$libresoc.v:42433$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:41807$2231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41813$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$967 - connect \Y $not$libresoc.v:41813$2237_Y + connect \Y $not$libresoc.v:42433$2266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:41819$2243 + cell $not $not$libresoc.v:42439$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$986 - connect \Y $not$libresoc.v:41819$2243_Y + connect \A \wr_pick_dly$981 + connect \Y $not$libresoc.v:42439$2272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41140$1557 + cell $or $or$libresoc.v:41766$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_dest1_o - connect \B \fus_dest1_o$106 - connect \Y $or$libresoc.v:41140$1557_Y + connect \B \fus_dest1_o$113 + connect \Y $or$libresoc.v:41766$1592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41141$1558 + cell $or $or$libresoc.v:41767$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$108 - connect \B \fus_dest1_o$109 - connect \Y $or$libresoc.v:41141$1558_Y + connect \A \fus_dest1_o$115 + connect \B \fus_dest1_o$116 + connect \Y $or$libresoc.v:41767$1593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41142$1559 + cell $or $or$libresoc.v:41768$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$107 - connect \B \$1138 - connect \Y $or$libresoc.v:41142$1559_Y + connect \A \fus_dest1_o$114 + connect \B \$1152 + connect \Y $or$libresoc.v:41768$1594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41143$1560 + cell $or $or$libresoc.v:41769$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1136 - connect \B \$1140 - connect \Y $or$libresoc.v:41143$1560_Y + connect \A \$1150 + connect \B \$1154 + connect \Y $or$libresoc.v:41769$1595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41144$1561 + cell $or $or$libresoc.v:41770$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$110 - connect \B \fus_dest1_o$111 - connect \Y $or$libresoc.v:41144$1561_Y + connect \A \fus_dest1_o$117 + connect \B \fus_dest1_o$118 + connect \Y $or$libresoc.v:41770$1596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41145$1562 + cell $or $or$libresoc.v:41771$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -70545,395 +71456,395 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:41145$1562_Y + connect \Y $or$libresoc.v:41771$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41146$1563 + cell $or $or$libresoc.v:41772$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \fus_dest1_o$112 - connect \B \$1146 - connect \Y $or$libresoc.v:41146$1563_Y + connect \A \fus_dest1_o$119 + connect \B \$1160 + connect \Y $or$libresoc.v:41772$1598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41147$1564 + cell $or $or$libresoc.v:41773$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1144 - connect \B \$1148 - connect \Y $or$libresoc.v:41147$1564_Y + connect \A \$1158 + connect \B \$1162 + connect \Y $or$libresoc.v:41773$1599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41148$1565 + cell $or $or$libresoc.v:41774$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 65 parameter \Y_WIDTH 65 - connect \A \$1142 - connect \B \$1150 - connect \Y $or$libresoc.v:41148$1565_Y + connect \A \$1156 + connect \B \$1164 + connect \Y $or$libresoc.v:41774$1600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41149$1566 + cell $or $or$libresoc.v:41775$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \addr_en - connect \B \addr_en$978 - connect \Y $or$libresoc.v:41149$1566_Y + connect \B \addr_en$992 + connect \Y $or$libresoc.v:41775$1601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41150$1567 + cell $or $or$libresoc.v:41776$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$1017 - connect \B \addr_en$1039 - connect \Y $or$libresoc.v:41150$1567_Y + connect \A \addr_en$1031 + connect \B \addr_en$1053 + connect \Y $or$libresoc.v:41776$1602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41151$1568 + cell $or $or$libresoc.v:41777$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$999 - connect \B \$1156 - connect \Y $or$libresoc.v:41151$1568_Y + connect \A \addr_en$1013 + connect \B \$1170 + connect \Y $or$libresoc.v:41777$1603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41152$1569 + cell $or $or$libresoc.v:41778$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$1154 - connect \B \$1158 - connect \Y $or$libresoc.v:41152$1569_Y + connect \A \$1168 + connect \B \$1172 + connect \Y $or$libresoc.v:41778$1604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41153$1570 + cell $or $or$libresoc.v:41779$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$1059 - connect \B \addr_en$1079 - connect \Y $or$libresoc.v:41153$1570_Y + connect \A \addr_en$1073 + connect \B \addr_en$1093 + connect \Y $or$libresoc.v:41779$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41154$1571 + cell $or $or$libresoc.v:41780$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$1116 - connect \B \addr_en$1132 - connect \Y $or$libresoc.v:41154$1571_Y + connect \A \addr_en$1130 + connect \B \addr_en$1146 + connect \Y $or$libresoc.v:41780$1606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41155$1572 + cell $or $or$libresoc.v:41781$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \addr_en$1098 - connect \B \$1164 - connect \Y $or$libresoc.v:41155$1572_Y + connect \A \addr_en$1112 + connect \B \$1178 + connect \Y $or$libresoc.v:41781$1607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41156$1573 + cell $or $or$libresoc.v:41782$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$1162 - connect \B \$1166 - connect \Y $or$libresoc.v:41156$1573_Y + connect \A \$1176 + connect \B \$1180 + connect \Y $or$libresoc.v:41782$1608_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41157$1574 + cell $or $or$libresoc.v:41783$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$1160 - connect \B \$1168 - connect \Y $or$libresoc.v:41157$1574_Y + connect \A \$1174 + connect \B \$1182 + connect \Y $or$libresoc.v:41783$1609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41158$1575 + cell $or $or$libresoc.v:41784$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wp - connect \B \wp$975 - connect \Y $or$libresoc.v:41158$1575_Y + connect \B \wp$989 + connect \Y $or$libresoc.v:41784$1610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41159$1576 + cell $or $or$libresoc.v:41785$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1014 - connect \B \wp$1036 - connect \Y $or$libresoc.v:41159$1576_Y + connect \A \wp$1028 + connect \B \wp$1050 + connect \Y $or$libresoc.v:41785$1611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41160$1577 + cell $or $or$libresoc.v:41786$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$996 - connect \B \$1174 - connect \Y $or$libresoc.v:41160$1577_Y + connect \A \wp$1010 + connect \B \$1188 + connect \Y $or$libresoc.v:41786$1612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41161$1578 + cell $or $or$libresoc.v:41787$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1172 - connect \B \$1176 - connect \Y $or$libresoc.v:41161$1578_Y + connect \A \$1186 + connect \B \$1190 + connect \Y $or$libresoc.v:41787$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41162$1579 + cell $or $or$libresoc.v:41788$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1056 - connect \B \wp$1076 - connect \Y $or$libresoc.v:41162$1579_Y + connect \A \wp$1070 + connect \B \wp$1090 + connect \Y $or$libresoc.v:41788$1614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41163$1580 + cell $or $or$libresoc.v:41789$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1113 - connect \B \wp$1129 - connect \Y $or$libresoc.v:41163$1580_Y + connect \A \wp$1127 + connect \B \wp$1143 + connect \Y $or$libresoc.v:41789$1615_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41164$1581 + cell $or $or$libresoc.v:41790$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1095 - connect \B \$1182 - connect \Y $or$libresoc.v:41164$1581_Y + connect \A \wp$1109 + connect \B \$1196 + connect \Y $or$libresoc.v:41790$1616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41165$1582 + cell $or $or$libresoc.v:41791$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1180 - connect \B \$1184 - connect \Y $or$libresoc.v:41165$1582_Y + connect \A \$1194 + connect \B \$1198 + connect \Y $or$libresoc.v:41791$1617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41166$1583 + cell $or $or$libresoc.v:41792$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1178 - connect \B \$1186 - connect \Y $or$libresoc.v:41166$1583_Y + connect \A \$1192 + connect \B \$1200 + connect \Y $or$libresoc.v:41792$1618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41228$1645 + cell $or $or$libresoc.v:41854$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_dest3_o - connect \B \fus_dest2_o$119 - connect \Y $or$libresoc.v:41228$1645_Y + connect \B \fus_dest2_o$126 + connect \Y $or$libresoc.v:41854$1680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41229$1646 + cell $or $or$libresoc.v:41855$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$118 - connect \B \$1340 - connect \Y $or$libresoc.v:41229$1646_Y + connect \A \fus_dest2_o$125 + connect \B \$1354 + connect \Y $or$libresoc.v:41855$1681_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41230$1647 + cell $or $or$libresoc.v:41856$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$121 - connect \B \fus_dest2_o$122 - connect \Y $or$libresoc.v:41230$1647_Y + connect \A \fus_dest2_o$128 + connect \B \fus_dest2_o$129 + connect \Y $or$libresoc.v:41856$1682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41231$1648 + cell $or $or$libresoc.v:41857$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$120 - connect \B \$1344 - connect \Y $or$libresoc.v:41231$1648_Y + connect \A \fus_dest2_o$127 + connect \B \$1358 + connect \Y $or$libresoc.v:41857$1683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41232$1649 + cell $or $or$libresoc.v:41858$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \$1342 - connect \B \$1346 - connect \Y $or$libresoc.v:41232$1649_Y + connect \A \$1356 + connect \B \$1360 + connect \Y $or$libresoc.v:41858$1684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41233$1650 + cell $or $or$libresoc.v:41859$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1253 - connect \B \addr_en$1273 - connect \Y $or$libresoc.v:41233$1650_Y + connect \A \addr_en$1267 + connect \B \addr_en$1287 + connect \Y $or$libresoc.v:41859$1685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41234$1651 + cell $or $or$libresoc.v:41860$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1233 - connect \B \$1351 - connect \Y $or$libresoc.v:41234$1651_Y + connect \A \addr_en$1247 + connect \B \$1365 + connect \Y $or$libresoc.v:41860$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41235$1652 + cell $or $or$libresoc.v:41861$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1313 - connect \B \addr_en$1333 - connect \Y $or$libresoc.v:41235$1652_Y + connect \A \addr_en$1327 + connect \B \addr_en$1347 + connect \Y $or$libresoc.v:41861$1687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41236$1653 + cell $or $or$libresoc.v:41862$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \addr_en$1293 - connect \B \$1355 - connect \Y $or$libresoc.v:41236$1653_Y + connect \A \addr_en$1307 + connect \B \$1369 + connect \Y $or$libresoc.v:41862$1688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41237$1654 + cell $or $or$libresoc.v:41863$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 16 - connect \A \$1353 - connect \B \$1357 - connect \Y $or$libresoc.v:41237$1654_Y + connect \A \$1367 + connect \B \$1371 + connect \Y $or$libresoc.v:41863$1689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41259$1676 + cell $or $or$libresoc.v:41885$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \fus_dest6_o - connect \B \fus_dest3_o$126 - connect \Y $or$libresoc.v:41259$1676_Y + connect \B \fus_dest3_o$133 + connect \Y $or$libresoc.v:41885$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41260$1677 + cell $or $or$libresoc.v:41886$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$125 - connect \B \$1415 - connect \Y $or$libresoc.v:41260$1677_Y + connect \A \fus_dest3_o$132 + connect \B \$1429 + connect \Y $or$libresoc.v:41886$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41261$1678 + cell $or $or$libresoc.v:41887$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1396 - connect \B \addr_en$1412 - connect \Y $or$libresoc.v:41261$1678_Y + connect \A \addr_en$1410 + connect \B \addr_en$1426 + connect \Y $or$libresoc.v:41887$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41262$1679 + cell $or $or$libresoc.v:41888$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \addr_en$1380 - connect \B \$1420 - connect \Y $or$libresoc.v:41262$1679_Y + connect \A \addr_en$1394 + connect \B \$1434 + connect \Y $or$libresoc.v:41888$1714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41292$1710 + cell $or $or$libresoc.v:41918$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70941,461 +71852,461 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:41292$1710_Y + connect \Y $or$libresoc.v:41918$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41293$1711 + cell $or $or$libresoc.v:41919$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$130 - connect \B \fus_dest3_o$131 - connect \Y $or$libresoc.v:41293$1711_Y + connect \A \fus_dest3_o$137 + connect \B \fus_dest3_o$138 + connect \Y $or$libresoc.v:41919$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41294$1712 + cell $or $or$libresoc.v:41920$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \$1497 - connect \B \$1499 - connect \Y $or$libresoc.v:41294$1712_Y + connect \A \$1511 + connect \B \$1513 + connect \Y $or$libresoc.v:41920$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41295$1713 + cell $or $or$libresoc.v:41921$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1446 - connect \B \addr_en$1462 - connect \Y $or$libresoc.v:41295$1713_Y + connect \A \addr_en$1460 + connect \B \addr_en$1476 + connect \Y $or$libresoc.v:41921$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41296$1714 + cell $or $or$libresoc.v:41922$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1478 - connect \B \addr_en$1494 - connect \Y $or$libresoc.v:41296$1714_Y + connect \A \addr_en$1492 + connect \B \addr_en$1508 + connect \Y $or$libresoc.v:41922$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41297$1715 + cell $or $or$libresoc.v:41923$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1503 - connect \B \$1505 - connect \Y $or$libresoc.v:41297$1715_Y + connect \A \$1517 + connect \B \$1519 + connect \Y $or$libresoc.v:41923$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41326$1744 + cell $or $or$libresoc.v:41952$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$135 - connect \B \fus_dest4_o$136 - connect \Y $or$libresoc.v:41326$1744_Y + connect \A \fus_dest5_o$142 + connect \B \fus_dest4_o$143 + connect \Y $or$libresoc.v:41952$1779_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41327$1745 + cell $or $or$libresoc.v:41953$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$137 - connect \B \fus_dest4_o$138 - connect \Y $or$libresoc.v:41327$1745_Y + connect \A \fus_dest4_o$144 + connect \B \fus_dest4_o$145 + connect \Y $or$libresoc.v:41953$1780_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41328$1746 + cell $or $or$libresoc.v:41954$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1582 - connect \B \$1584 - connect \Y $or$libresoc.v:41328$1746_Y + connect \A \$1596 + connect \B \$1598 + connect \Y $or$libresoc.v:41954$1781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41330$1749 + cell $or $or$libresoc.v:41956$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1530 - connect \B \addr_en$1546 - connect \Y $or$libresoc.v:41330$1749_Y + connect \A \addr_en$1544 + connect \B \addr_en$1560 + connect \Y $or$libresoc.v:41956$1784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41331$1750 + cell $or $or$libresoc.v:41957$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1562 - connect \B \addr_en$1578 - connect \Y $or$libresoc.v:41331$1750_Y + connect \A \addr_en$1576 + connect \B \addr_en$1592 + connect \Y $or$libresoc.v:41957$1785_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41332$1751 + cell $or $or$libresoc.v:41958$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1590 - connect \B \$1592 - connect \Y $or$libresoc.v:41332$1751_Y + connect \A \$1604 + connect \B \$1606 + connect \Y $or$libresoc.v:41958$1786_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41373$1793 + cell $or $or$libresoc.v:41995$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$144 - connect \B \fus_dest2_o$145 - connect \Y $or$libresoc.v:41373$1793_Y + connect \A \fus_dest1_o$151 + connect \B \fus_dest2_o$152 + connect \Y $or$libresoc.v:41995$1824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41374$1794 + cell $or $or$libresoc.v:41996$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$147 - connect \B \fus_dest3_o$148 - connect \Y $or$libresoc.v:41374$1794_Y + connect \A \fus_dest2_o$154 + connect \B \fus_dest3_o$155 + connect \Y $or$libresoc.v:41996$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41375$1795 + cell $or $or$libresoc.v:41997$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$146 - connect \B \$1692 - connect \Y $or$libresoc.v:41375$1795_Y + connect \A \fus_dest3_o$153 + connect \B \$1706 + connect \Y $or$libresoc.v:41997$1826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41376$1796 + cell $or $or$libresoc.v:41998$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \$1690 - connect \B \$1694 - connect \Y $or$libresoc.v:41376$1796_Y + connect \A \$1704 + connect \B \$1708 + connect \Y $or$libresoc.v:41998$1827_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41377$1797 + cell $or $or$libresoc.v:41999$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1623 - connect \B \addr_en$1639 - connect \Y $or$libresoc.v:41377$1797_Y + connect \A \addr_en$1637 + connect \B \addr_en$1653 + connect \Y $or$libresoc.v:41999$1828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41379$1799 + cell $or $or$libresoc.v:42000$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1671 - connect \B \addr_en$1687 - connect \Y $or$libresoc.v:41379$1799_Y + connect \A \addr_en$1685 + connect \B \addr_en$1701 + connect \Y $or$libresoc.v:42000$1829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41380$1800 + cell $or $or$libresoc.v:42001$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \addr_en$1655 - connect \B \$1700 - connect \Y $or$libresoc.v:41380$1800_Y + connect \A \addr_en$1669 + connect \B \$1714 + connect \Y $or$libresoc.v:42001$1830_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41381$1801 + cell $or $or$libresoc.v:42002$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$1698 - connect \B \$1702 - connect \Y $or$libresoc.v:41381$1801_Y + connect \A \$1712 + connect \B \$1716 + connect \Y $or$libresoc.v:42002$1831_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41382$1802 + cell $or $or$libresoc.v:42003$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1620 - connect \B \wp$1636 - connect \Y $or$libresoc.v:41382$1802_Y + connect \A \wp$1634 + connect \B \wp$1650 + connect \Y $or$libresoc.v:42003$1832_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41383$1803 + cell $or $or$libresoc.v:42004$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1668 - connect \B \wp$1684 - connect \Y $or$libresoc.v:41383$1803_Y + connect \A \wp$1682 + connect \B \wp$1698 + connect \Y $or$libresoc.v:42004$1833_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41385$1805 + cell $or $or$libresoc.v:42005$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wp$1652 - connect \B \$1708 - connect \Y $or$libresoc.v:41385$1805_Y + connect \A \wp$1666 + connect \B \$1722 + connect \Y $or$libresoc.v:42005$1834_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41386$1806 + cell $or $or$libresoc.v:42006$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$1706 - connect \B \$1710 - connect \Y $or$libresoc.v:41386$1806_Y + connect \A \$1720 + connect \B \$1724 + connect \Y $or$libresoc.v:42006$1835_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41403$1823 + cell $or $or$libresoc.v:42022$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$150 - connect \B \fus_dest4_o$151 - connect \Y $or$libresoc.v:41403$1823_Y + connect \A \fus_dest3_o$157 + connect \B \fus_dest4_o$158 + connect \Y $or$libresoc.v:42022$1851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41404$1824 + cell $or $or$libresoc.v:42023$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_en$1731 - connect \B \addr_en$1747 - connect \Y $or$libresoc.v:41404$1824_Y + connect \A \addr_en$1745 + connect \B \addr_en$1761 + connect \Y $or$libresoc.v:42023$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41439$1861 + cell $or $or$libresoc.v:42065$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$208 - connect \B \$212 - connect \Y $or$libresoc.v:41439$1861_Y + connect \A \$222 + connect \B \$226 + connect \Y $or$libresoc.v:42065$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41441$1863 + cell $or $or$libresoc.v:42067$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$214 - connect \B \$216 - connect \Y $or$libresoc.v:41441$1863_Y + connect \A \$228 + connect \B \$230 + connect \Y $or$libresoc.v:42067$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41445$1867 + cell $or $or$libresoc.v:42071$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$220 - connect \B \$224 - connect \Y $or$libresoc.v:41445$1867_Y + connect \A \$234 + connect \B \$238 + connect \Y $or$libresoc.v:42071$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41453$1875 + cell $or $or$libresoc.v:42079$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$236 - connect \B \$240 - connect \Y $or$libresoc.v:41453$1875_Y + connect \A \$250 + connect \B \$254 + connect \Y $or$libresoc.v:42079$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41455$1877 + cell $or $or$libresoc.v:42081$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$242 - connect \B \$244 - connect \Y $or$libresoc.v:41455$1877_Y + connect \A \$256 + connect \B \$258 + connect \Y $or$libresoc.v:42081$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41460$1882 + cell $or $or$libresoc.v:42086$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$250 - connect \B \$254 - connect \Y $or$libresoc.v:41460$1882_Y + connect \A \$264 + connect \B \$268 + connect \Y $or$libresoc.v:42086$1917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41462$1884 + cell $or $or$libresoc.v:42088$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$256 - connect \B \$258 - connect \Y $or$libresoc.v:41462$1884_Y + connect \A \$270 + connect \B \$272 + connect \Y $or$libresoc.v:42088$1919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:41466$1888 + cell $or $or$libresoc.v:42092$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$262 - connect \B \$266 - connect \Y $or$libresoc.v:41466$1888_Y + connect \A \$276 + connect \B \$280 + connect \Y $or$libresoc.v:42092$1923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41470$1892 + cell $or $or$libresoc.v:42096$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$270 - connect \B \$274 - connect \Y $or$libresoc.v:41470$1892_Y + connect \A \$284 + connect \B \$288 + connect \Y $or$libresoc.v:42096$1927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41475$1897 + cell $or $or$libresoc.v:42101$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$280 - connect \B \$284 - connect \Y $or$libresoc.v:41475$1897_Y + connect \A \$294 + connect \B \$298 + connect \Y $or$libresoc.v:42101$1932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41477$1899 + cell $or $or$libresoc.v:42103$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$286 - connect \B \$288 - connect \Y $or$libresoc.v:41477$1899_Y + connect \A \$300 + connect \B \$302 + connect \Y $or$libresoc.v:42103$1934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41482$1904 + cell $or $or$libresoc.v:42108$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$294 - connect \B \$298 - connect \Y $or$libresoc.v:41482$1904_Y + connect \A \$308 + connect \B \$312 + connect \Y $or$libresoc.v:42108$1939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41484$1906 + cell $or $or$libresoc.v:42110$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$300 - connect \B \$302 - connect \Y $or$libresoc.v:41484$1906_Y + connect \A \$314 + connect \B \$316 + connect \Y $or$libresoc.v:42110$1941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41489$1911 + cell $or $or$libresoc.v:42115$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$308 - connect \B \$312 - connect \Y $or$libresoc.v:41489$1911_Y + connect \A \$322 + connect \B \$326 + connect \Y $or$libresoc.v:42115$1946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41491$1913 + cell $or $or$libresoc.v:42117$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$314 - connect \B \$316 - connect \Y $or$libresoc.v:41491$1913_Y + connect \A \$328 + connect \B \$330 + connect \Y $or$libresoc.v:42117$1948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41495$1917 + cell $or $or$libresoc.v:42121$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$320 - connect \B \$324 - connect \Y $or$libresoc.v:41495$1917_Y + connect \A \$334 + connect \B \$338 + connect \Y $or$libresoc.v:42121$1952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41552$1974 + cell $or $or$libresoc.v:42178$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71403,10 +72314,10 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:41552$1974_Y + connect \Y $or$libresoc.v:42178$2009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41553$1975 + cell $or $or$libresoc.v:42179$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71414,21 +72325,21 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:41553$1975_Y + connect \Y $or$libresoc.v:42179$2010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41554$1976 + cell $or $or$libresoc.v:42180$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$439 - connect \B \$441 - connect \Y $or$libresoc.v:41554$1976_Y + connect \A \$453 + connect \B \$455 + connect \Y $or$libresoc.v:42180$2011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41555$1977 + cell $or $or$libresoc.v:42181$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71436,10 +72347,10 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:41555$1977_Y + connect \Y $or$libresoc.v:42181$2012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41556$1978 + cell $or $or$libresoc.v:42182$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71447,43 +72358,43 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:41556$1978_Y + connect \Y $or$libresoc.v:42182$2013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41557$1979 + cell $or $or$libresoc.v:42183$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 connect \A \addr_en_INT_ra_mul0_6 - connect \B \$447 - connect \Y $or$libresoc.v:41557$1979_Y + connect \B \$461 + connect \Y $or$libresoc.v:42183$2014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41558$1980 + cell $or $or$libresoc.v:42184$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$445 - connect \B \$449 - connect \Y $or$libresoc.v:41558$1980_Y + connect \A \$459 + connect \B \$463 + connect \Y $or$libresoc.v:42184$2015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41559$1981 + cell $or $or$libresoc.v:42185$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$443 - connect \B \$451 - connect \Y $or$libresoc.v:41559$1981_Y + connect \A \$457 + connect \B \$465 + connect \Y $or$libresoc.v:42185$2016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41609$2031 + cell $or $or$libresoc.v:42235$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71491,10 +72402,10 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:41609$2031_Y + connect \Y $or$libresoc.v:42235$2066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41610$2032 + cell $or $or$libresoc.v:42236$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71502,21 +72413,21 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:41610$2032_Y + connect \Y $or$libresoc.v:42236$2067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41611$2033 + cell $or $or$libresoc.v:42237$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$553 - connect \B \$555 - connect \Y $or$libresoc.v:41611$2033_Y + connect \A \$567 + connect \B \$569 + connect \Y $or$libresoc.v:42237$2068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41612$2034 + cell $or $or$libresoc.v:42238$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71524,10 +72435,10 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:41612$2034_Y + connect \Y $or$libresoc.v:42238$2069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41613$2035 + cell $or $or$libresoc.v:42239$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71535,32 +72446,32 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:41613$2035_Y + connect \Y $or$libresoc.v:42239$2070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41614$2036 + cell $or $or$libresoc.v:42240$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$559 - connect \B \$561 - connect \Y $or$libresoc.v:41614$2036_Y + connect \A \$573 + connect \B \$575 + connect \Y $or$libresoc.v:42240$2071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41615$2037 + cell $or $or$libresoc.v:42241$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 5 - connect \A \$557 - connect \B \$563 - connect \Y $or$libresoc.v:41615$2037_Y + connect \A \$571 + connect \B \$577 + connect \Y $or$libresoc.v:42241$2072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41629$2051 + cell $or $or$libresoc.v:42255$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -71568,32 +72479,32 @@ module \core parameter \Y_WIDTH 5 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:41629$2051_Y + connect \Y $or$libresoc.v:42255$2086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:41634$2056 + cell $or $or$libresoc.v:42260$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$597 - connect \B \$601 - connect \Y $or$libresoc.v:41634$2056_Y + connect \A \$611 + connect \B \$615 + connect \Y $or$libresoc.v:42260$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:41636$2058 + cell $or $or$libresoc.v:42262$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$603 - connect \B \$605 - connect \Y $or$libresoc.v:41636$2058_Y + connect \A \$617 + connect \B \$619 + connect \Y $or$libresoc.v:42262$2093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41673$2095 + cell $or $or$libresoc.v:42299$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71601,21 +72512,21 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:41673$2095_Y + connect \Y $or$libresoc.v:42299$2130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41674$2096 + cell $or $or$libresoc.v:42300$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \$682 - connect \Y $or$libresoc.v:41674$2096_Y + connect \B \$696 + connect \Y $or$libresoc.v:42300$2131_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41675$2097 + cell $or $or$libresoc.v:42301$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71623,43 +72534,43 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:41675$2097_Y + connect \Y $or$libresoc.v:42301$2132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41676$2098 + cell $or $or$libresoc.v:42302$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 - connect \B \$686 - connect \Y $or$libresoc.v:41676$2098_Y + connect \B \$700 + connect \Y $or$libresoc.v:42302$2133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41677$2099 + cell $or $or$libresoc.v:42303$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$684 - connect \B \$688 - connect \Y $or$libresoc.v:41677$2099_Y + connect \A \$698 + connect \B \$702 + connect \Y $or$libresoc.v:42303$2134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:41682$2105 + cell $or $or$libresoc.v:42308$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$693 - connect \B \$697 - connect \Y $or$libresoc.v:41682$2105_Y + connect \A \$707 + connect \B \$711 + connect \Y $or$libresoc.v:42308$2140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41701$2124 + cell $or $or$libresoc.v:42327$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71667,32 +72578,32 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:41701$2124_Y + connect \Y $or$libresoc.v:42327$2159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41702$2125 + cell $or $or$libresoc.v:42328$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B \$738 - connect \Y $or$libresoc.v:41702$2125_Y + connect \B \$752 + connect \Y $or$libresoc.v:42328$2160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:41707$2131 + cell $or $or$libresoc.v:42333$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$743 - connect \B \$747 - connect \Y $or$libresoc.v:41707$2131_Y + connect \A \$757 + connect \B \$761 + connect \Y $or$libresoc.v:42333$2166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41736$2160 + cell $or $or$libresoc.v:42362$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -71700,10 +72611,10 @@ module \core parameter \Y_WIDTH 16 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:41736$2160_Y + connect \Y $or$libresoc.v:42362$2195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41771$2195 + cell $or $or$libresoc.v:42397$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71711,21 +72622,21 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:41771$2195_Y + connect \Y $or$libresoc.v:42397$2230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:41772$2196 + cell $or $or$libresoc.v:42398$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \$878 - connect \Y $or$libresoc.v:41772$2196_Y + connect \B \$892 + connect \Y $or$libresoc.v:42398$2231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:41786$2210 + cell $or $or$libresoc.v:42412$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71733,304 +72644,304 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:41786$2210_Y + connect \Y $or$libresoc.v:42412$2245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41263$1681 + cell $pos $pos$libresoc.v:41889$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41263$1680_Y - connect \Y $pos$libresoc.v:41263$1681_Y + connect \A $extend$libresoc.v:41889$1715_Y + connect \Y $pos$libresoc.v:41889$1716_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41329$1748 + cell $pos $pos$libresoc.v:41955$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:41329$1747_Y - connect \Y $pos$libresoc.v:41329$1748_Y + connect \A $extend$libresoc.v:41955$1782_Y + connect \Y $pos$libresoc.v:41955$1783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41333$1753 + cell $pos $pos$libresoc.v:41959$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41333$1752_Y - connect \Y $pos$libresoc.v:41333$1753_Y + connect \A $extend$libresoc.v:41959$1787_Y + connect \Y $pos$libresoc.v:41959$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $pos$libresoc.v:41405$1826 + cell $pos $pos$libresoc.v:42024$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:41405$1825_Y - connect \Y $pos$libresoc.v:41405$1826_Y + connect \A $extend$libresoc.v:42024$1853_Y + connect \Y $pos$libresoc.v:42024$1854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $pos $pos$libresoc.v:41413$1835 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" + cell $pos $pos$libresoc.v:42033$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:41413$1834_Y - connect \Y $pos$libresoc.v:41413$1835_Y + connect \A $extend$libresoc.v:42033$1863_Y + connect \Y $pos$libresoc.v:42033$1864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41678$2101 + cell $pos $pos$libresoc.v:42304$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41678$2100_Y - connect \Y $pos$libresoc.v:41678$2101_Y + connect \A $extend$libresoc.v:42304$2135_Y + connect \Y $pos$libresoc.v:42304$2136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $pos$libresoc.v:41703$2127 + cell $pos $pos$libresoc.v:42329$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41703$2126_Y - connect \Y $pos$libresoc.v:41703$2127_Y + connect \A $extend$libresoc.v:42329$2161_Y + connect \Y $pos$libresoc.v:42329$2162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41347$1767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42025$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$161 - connect \Y $reduce_or$libresoc.v:41347$1767_Y + connect \A \$175 + connect \Y $reduce_or$libresoc.v:42025$1855_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41364$1784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42042$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$165 - connect \Y $reduce_or$libresoc.v:41364$1784_Y + connect \A \$179 + connect \Y $reduce_or$libresoc.v:42042$1873_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41384$1804 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42044$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$169 - connect \Y $reduce_or$libresoc.v:41384$1804_Y + connect \A \$183 + connect \Y $reduce_or$libresoc.v:42044$1875_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41402$1822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42046$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$173 - connect \Y $reduce_or$libresoc.v:41402$1822_Y + connect \A \$187 + connect \Y $reduce_or$libresoc.v:42046$1877_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41420$1842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42048$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$177 - connect \Y $reduce_or$libresoc.v:41420$1842_Y + connect \A \$191 + connect \Y $reduce_or$libresoc.v:42048$1879_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41424$1846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42050$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$181 - connect \Y $reduce_or$libresoc.v:41424$1846_Y + connect \A \$195 + connect \Y $reduce_or$libresoc.v:42050$1881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41426$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42052$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$185 - connect \Y $reduce_or$libresoc.v:41426$1848_Y + connect \A \$199 + connect \Y $reduce_or$libresoc.v:42052$1883_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41428$1850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42054$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$189 - connect \Y $reduce_or$libresoc.v:41428$1850_Y + connect \A \$203 + connect \Y $reduce_or$libresoc.v:42054$1885_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41430$1852 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42056$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$193 - connect \Y $reduce_or$libresoc.v:41430$1852_Y + connect \A \$207 + connect \Y $reduce_or$libresoc.v:42056$1887_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - cell $reduce_or $reduce_or$libresoc.v:41432$1854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" + cell $reduce_or $reduce_or$libresoc.v:42058$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 12 parameter \Y_WIDTH 1 - connect \A \$197 - connect \Y $reduce_or$libresoc.v:41432$1854_Y + connect \A \$211 + connect \Y $reduce_or$libresoc.v:42058$1889_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41560$1982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42186$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:41560$1982_Y + connect \Y $reduce_or$libresoc.v:42186$2017_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41616$2038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42242$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:41616$2038_Y + connect \Y $reduce_or$libresoc.v:42242$2073_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41630$2052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42256$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:41630$2052_Y + connect \Y $reduce_or$libresoc.v:42256$2087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41773$2197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42399$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:41773$2197_Y + connect \Y $reduce_or$libresoc.v:42399$2232_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41787$2211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42413$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:41787$2211_Y + connect \Y $reduce_or$libresoc.v:42413$2246_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:313" - cell $reduce_or $reduce_or$libresoc.v:41794$2218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:311" + cell $reduce_or $reduce_or$libresoc.v:42420$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:41794$2218_Y + connect \Y $reduce_or$libresoc.v:42420$2253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41186$1603 + cell $sshl $sshl$libresoc.v:41812$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1234 - connect \Y $sshl$libresoc.v:41186$1603_Y + connect \B \$1248 + connect \Y $sshl$libresoc.v:41812$1638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41194$1611 + cell $sshl $sshl$libresoc.v:41820$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1254 - connect \Y $sshl$libresoc.v:41194$1611_Y + connect \B \$1268 + connect \Y $sshl$libresoc.v:41820$1646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41202$1619 + cell $sshl $sshl$libresoc.v:41828$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1274 - connect \Y $sshl$libresoc.v:41202$1619_Y + connect \B \$1288 + connect \Y $sshl$libresoc.v:41828$1654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41210$1627 + cell $sshl $sshl$libresoc.v:41836$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1294 - connect \Y $sshl$libresoc.v:41210$1627_Y + connect \B \$1308 + connect \Y $sshl$libresoc.v:41836$1662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41218$1635 + cell $sshl $sshl$libresoc.v:41844$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1314 - connect \Y $sshl$libresoc.v:41218$1635_Y + connect \B \$1328 + connect \Y $sshl$libresoc.v:41844$1670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41226$1643 + cell $sshl $sshl$libresoc.v:41852$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$1334 - connect \Y $sshl$libresoc.v:41226$1643_Y + connect \B \$1348 + connect \Y $sshl$libresoc.v:41852$1678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:41726$2150 + cell $sshl $sshl$libresoc.v:42352$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$785 - connect \Y $sshl$libresoc.v:41726$2150_Y + connect \B \$799 + connect \Y $sshl$libresoc.v:42352$2185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:41734$2158 + cell $sshl $sshl$libresoc.v:42360$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$801 - connect \Y $sshl$libresoc.v:41734$2158_Y + connect \B \$815 + connect \Y $sshl$libresoc.v:42360$2193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:41743$2167 + cell $sshl $sshl$libresoc.v:42369$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$820 - connect \Y $sshl$libresoc.v:41743$2167_Y + connect \B \$834 + connect \Y $sshl$libresoc.v:42369$2202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:41751$2175 + cell $sshl $sshl$libresoc.v:42377$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B \$836 - connect \Y $sshl$libresoc.v:41751$2175_Y + connect \B \$850 + connect \Y $sshl$libresoc.v:42377$2210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41185$1602 + cell $sub $sub$libresoc.v:41811$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72038,10 +72949,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41185$1602_Y + connect \Y $sub$libresoc.v:41811$1637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41193$1610 + cell $sub $sub$libresoc.v:41819$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72049,10 +72960,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41193$1610_Y + connect \Y $sub$libresoc.v:41819$1645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41201$1618 + cell $sub $sub$libresoc.v:41827$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72060,10 +72971,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41201$1618_Y + connect \Y $sub$libresoc.v:41827$1653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41209$1626 + cell $sub $sub$libresoc.v:41835$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72071,10 +72982,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41209$1626_Y + connect \Y $sub$libresoc.v:41835$1661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41217$1634 + cell $sub $sub$libresoc.v:41843$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72082,10 +72993,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41217$1634_Y + connect \Y $sub$libresoc.v:41843$1669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41225$1642 + cell $sub $sub$libresoc.v:41851$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72093,10 +73004,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41225$1642_Y + connect \Y $sub$libresoc.v:41851$1677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - cell $sub $sub$libresoc.v:41434$1856 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:185" + cell $sub $sub$libresoc.v:42060$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72104,10 +73015,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:41434$1856_Y + connect \Y $sub$libresoc.v:42060$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:41725$2149 + cell $sub $sub$libresoc.v:42351$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72115,10 +73026,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:41725$2149_Y + connect \Y $sub$libresoc.v:42351$2184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:41733$2157 + cell $sub $sub$libresoc.v:42359$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72126,10 +73037,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:41733$2157_Y + connect \Y $sub$libresoc.v:42359$2192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:41742$2166 + cell $sub $sub$libresoc.v:42368$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72137,10 +73048,10 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:41742$2166_Y + connect \Y $sub$libresoc.v:42368$2201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:41750$2174 + cell $sub $sub$libresoc.v:42376$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72148,626 +73059,626 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:41750$2174_Y + connect \Y $sub$libresoc.v:42376$2209_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41097$1514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41723$1549 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$996 - connect \Y $ternary$libresoc.v:41097$1514_Y + connect \S \wp$1010 + connect \Y $ternary$libresoc.v:41723$1549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41103$1520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41729$1555 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1014 - connect \Y $ternary$libresoc.v:41103$1520_Y + connect \S \wp$1028 + connect \Y $ternary$libresoc.v:41729$1555_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41109$1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41735$1561 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1036 - connect \Y $ternary$libresoc.v:41109$1526_Y + connect \S \wp$1050 + connect \Y $ternary$libresoc.v:41735$1561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41115$1532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41741$1567 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1056 - connect \Y $ternary$libresoc.v:41115$1532_Y + connect \S \wp$1070 + connect \Y $ternary$libresoc.v:41741$1567_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41121$1538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41747$1573 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1076 - connect \Y $ternary$libresoc.v:41121$1538_Y + connect \S \wp$1090 + connect \Y $ternary$libresoc.v:41747$1573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41127$1544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41753$1579 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1095 - connect \Y $ternary$libresoc.v:41127$1544_Y + connect \S \wp$1109 + connect \Y $ternary$libresoc.v:41753$1579_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41133$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41759$1585 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$1113 - connect \Y $ternary$libresoc.v:41133$1550_Y + connect \S \wp$1127 + connect \Y $ternary$libresoc.v:41759$1585_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41139$1556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41765$1591 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_ea - connect \S \wp$1129 - connect \Y $ternary$libresoc.v:41139$1556_Y + connect \S \wp$1143 + connect \Y $ternary$libresoc.v:41765$1591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41173$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41799$1625 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr - connect \S \wp$1202 - connect \Y $ternary$libresoc.v:41173$1590_Y + connect \S \wp$1216 + connect \Y $ternary$libresoc.v:41799$1625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41187$1604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41813$1639 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1236 - connect \S \wp$1230 - connect \Y $ternary$libresoc.v:41187$1604_Y + connect \B \$1250 + connect \S \wp$1244 + connect \Y $ternary$libresoc.v:41813$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41195$1612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41821$1647 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1256 - connect \S \wp$1250 - connect \Y $ternary$libresoc.v:41195$1612_Y + connect \B \$1270 + connect \S \wp$1264 + connect \Y $ternary$libresoc.v:41821$1647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41203$1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41829$1655 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1276 - connect \S \wp$1270 - connect \Y $ternary$libresoc.v:41203$1620_Y + connect \B \$1290 + connect \S \wp$1284 + connect \Y $ternary$libresoc.v:41829$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41211$1628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41837$1663 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1296 - connect \S \wp$1290 - connect \Y $ternary$libresoc.v:41211$1628_Y + connect \B \$1310 + connect \S \wp$1304 + connect \Y $ternary$libresoc.v:41837$1663_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41219$1636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41845$1671 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1316 - connect \S \wp$1310 - connect \Y $ternary$libresoc.v:41219$1636_Y + connect \B \$1330 + connect \S \wp$1324 + connect \Y $ternary$libresoc.v:41845$1671_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41227$1644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41853$1679 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$1336 - connect \S \wp$1330 - connect \Y $ternary$libresoc.v:41227$1644_Y + connect \B \$1350 + connect \S \wp$1344 + connect \Y $ternary$libresoc.v:41853$1679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41246$1663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41872$1698 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1377 - connect \Y $ternary$libresoc.v:41246$1663_Y + connect \S \wp$1391 + connect \Y $ternary$libresoc.v:41872$1698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41252$1669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41878$1704 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1393 - connect \Y $ternary$libresoc.v:41252$1669_Y + connect \S \wp$1407 + connect \Y $ternary$libresoc.v:41878$1704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41258$1675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41884$1710 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1409 - connect \Y $ternary$libresoc.v:41258$1675_Y + connect \S \wp$1423 + connect \Y $ternary$libresoc.v:41884$1710_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41273$1691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41899$1726 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1443 - connect \Y $ternary$libresoc.v:41273$1691_Y + connect \S \wp$1457 + connect \Y $ternary$libresoc.v:41899$1726_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41279$1697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41905$1732 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1459 - connect \Y $ternary$libresoc.v:41279$1697_Y + connect \S \wp$1473 + connect \Y $ternary$libresoc.v:41905$1732_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41285$1703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41911$1738 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1475 - connect \Y $ternary$libresoc.v:41285$1703_Y + connect \S \wp$1489 + connect \Y $ternary$libresoc.v:41911$1738_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41291$1709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41917$1744 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 - connect \S \wp$1491 - connect \Y $ternary$libresoc.v:41291$1709_Y + connect \S \wp$1505 + connect \Y $ternary$libresoc.v:41917$1744_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41307$1725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41933$1760 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1527 - connect \Y $ternary$libresoc.v:41307$1725_Y + connect \S \wp$1541 + connect \Y $ternary$libresoc.v:41933$1760_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41313$1731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41939$1766 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1543 - connect \Y $ternary$libresoc.v:41313$1731_Y + connect \S \wp$1557 + connect \Y $ternary$libresoc.v:41939$1766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41319$1737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41945$1772 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1559 - connect \Y $ternary$libresoc.v:41319$1737_Y + connect \S \wp$1573 + connect \Y $ternary$libresoc.v:41945$1772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41325$1743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41951$1778 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1575 - connect \Y $ternary$libresoc.v:41325$1743_Y + connect \S \wp$1589 + connect \Y $ternary$libresoc.v:41951$1778_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41345$1765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41970$1799 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1620 - connect \Y $ternary$libresoc.v:41345$1765_Y + connect \S \wp$1634 + connect \Y $ternary$libresoc.v:41970$1799_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41352$1772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41976$1805 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1636 - connect \Y $ternary$libresoc.v:41352$1772_Y + connect \S \wp$1650 + connect \Y $ternary$libresoc.v:41976$1805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41358$1778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41982$1811 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 - connect \S \wp$1652 - connect \Y $ternary$libresoc.v:41358$1778_Y + connect \S \wp$1666 + connect \Y $ternary$libresoc.v:41982$1811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41366$1786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41988$1817 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1668 - connect \Y $ternary$libresoc.v:41366$1786_Y + connect \S \wp$1682 + connect \Y $ternary$libresoc.v:41988$1817_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41372$1792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:41994$1823 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 - connect \S \wp$1684 - connect \Y $ternary$libresoc.v:41372$1792_Y + connect \S \wp$1698 + connect \Y $ternary$libresoc.v:41994$1823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41394$1814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42014$1843 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1728 - connect \Y $ternary$libresoc.v:41394$1814_Y + connect \S \wp$1742 + connect \Y $ternary$libresoc.v:42014$1843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41401$1821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42021$1850 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 - connect \S \wp$1744 - connect \Y $ternary$libresoc.v:41401$1821_Y + connect \S \wp$1758 + connect \Y $ternary$libresoc.v:42021$1850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41412$1833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42032$1862 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 - connect \S \wp$1768 - connect \Y $ternary$libresoc.v:41412$1833_Y + connect \S \wp$1782 + connect \Y $ternary$libresoc.v:42032$1862_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41422$1844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42041$1872 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro - connect \S \wp$1788 - connect \Y $ternary$libresoc.v:41422$1844_Y + connect \S \wp$1802 + connect \Y $ternary$libresoc.v:42041$1872_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41503$1925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42129$1960 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:41503$1925_Y + connect \Y $ternary$libresoc.v:42129$1960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41509$1931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42135$1966 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:41509$1931_Y + connect \Y $ternary$libresoc.v:42135$1966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41515$1937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42141$1972 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:41515$1937_Y + connect \Y $ternary$libresoc.v:42141$1972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41521$1943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42147$1978 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:41521$1943_Y + connect \Y $ternary$libresoc.v:42147$1978_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41527$1949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42153$1984 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:41527$1949_Y + connect \Y $ternary$libresoc.v:42153$1984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41533$1955 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42159$1990 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:41533$1955_Y + connect \Y $ternary$libresoc.v:42159$1990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41539$1961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42165$1996 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:41539$1961_Y + connect \Y $ternary$libresoc.v:42165$1996_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41545$1967 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42171$2002 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:41545$1967_Y + connect \Y $ternary$libresoc.v:42171$2002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41551$1973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42177$2008 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:41551$1973_Y + connect \Y $ternary$libresoc.v:42177$2008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41566$1988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42192$2023 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:41566$1988_Y + connect \Y $ternary$libresoc.v:42192$2023_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41572$1994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42198$2029 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:41572$1994_Y + connect \Y $ternary$libresoc.v:42198$2029_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41578$2000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42204$2035 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:41578$2000_Y + connect \Y $ternary$libresoc.v:42204$2035_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41584$2006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42210$2041 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:41584$2006_Y + connect \Y $ternary$libresoc.v:42210$2041_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41590$2012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42216$2047 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:41590$2012_Y + connect \Y $ternary$libresoc.v:42216$2047_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41596$2018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42222$2053 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:41596$2018_Y + connect \Y $ternary$libresoc.v:42222$2053_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41602$2024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42228$2059 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:41602$2024_Y + connect \Y $ternary$libresoc.v:42228$2059_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41608$2030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42234$2065 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:41608$2030_Y + connect \Y $ternary$libresoc.v:42234$2065_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41622$2044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42248$2079 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:41622$2044_Y + connect \Y $ternary$libresoc.v:42248$2079_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41628$2050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42254$2085 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:41628$2050_Y + connect \Y $ternary$libresoc.v:42254$2085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41642$2064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42268$2099 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:41642$2064_Y + connect \Y $ternary$libresoc.v:42268$2099_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41648$2070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42274$2105 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:41648$2070_Y + connect \Y $ternary$libresoc.v:42274$2105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41654$2076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42280$2111 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:41654$2076_Y + connect \Y $ternary$libresoc.v:42280$2111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41660$2082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42286$2117 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:41660$2082_Y + connect \Y $ternary$libresoc.v:42286$2117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41666$2088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42292$2123 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:41666$2088_Y + connect \Y $ternary$libresoc.v:42292$2123_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41672$2094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42298$2129 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:41672$2094_Y + connect \Y $ternary$libresoc.v:42298$2129_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41688$2111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42314$2146 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:41688$2111_Y + connect \Y $ternary$libresoc.v:42314$2146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41694$2117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42320$2152 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:41694$2117_Y + connect \Y $ternary$libresoc.v:42320$2152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41700$2123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42326$2158 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:41700$2123_Y + connect \Y $ternary$libresoc.v:42326$2158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41713$2137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42339$2172 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:41713$2137_Y + connect \Y $ternary$libresoc.v:42339$2172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41719$2143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42345$2178 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:41719$2143_Y + connect \Y $ternary$libresoc.v:42345$2178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41727$2151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42353$2186 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$787 + connect \B \$801 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:41727$2151_Y + connect \Y $ternary$libresoc.v:42353$2186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41735$2159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42361$2194 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$803 + connect \B \$817 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:41735$2159_Y + connect \Y $ternary$libresoc.v:42361$2194_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41744$2168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42370$2203 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$822 + connect \B \$836 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:41744$2168_Y + connect \Y $ternary$libresoc.v:42370$2203_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41752$2176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42378$2211 parameter \WIDTH 16 connect \A 16'0000000000000000 - connect \B \$838 + connect \B \$852 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:41752$2176_Y + connect \Y $ternary$libresoc.v:42378$2211_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41758$2182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42384$2217 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:41758$2182_Y + connect \Y $ternary$libresoc.v:42384$2217_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41764$2188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42390$2223 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:41764$2188_Y + connect \Y $ternary$libresoc.v:42390$2223_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41770$2194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42396$2229 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:41770$2194_Y + connect \Y $ternary$libresoc.v:42396$2229_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41779$2203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42405$2238 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:41779$2203_Y + connect \Y $ternary$libresoc.v:42405$2238_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41785$2209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42411$2244 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:41785$2209_Y + connect \Y $ternary$libresoc.v:42411$2244_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" - cell $mux $ternary$libresoc.v:41793$2217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" + cell $mux $ternary$libresoc.v:42419$2252 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:41793$2217_Y + connect \Y $ternary$libresoc.v:42419$2252_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41810$2234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42436$2269 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:41810$2234_Y + connect \Y $ternary$libresoc.v:42436$2269_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $mux $ternary$libresoc.v:41816$2240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" + cell $mux $ternary$libresoc.v:42442$2275 parameter \WIDTH 5 connect \A 5'00000 connect \B \core_rego - connect \S \wp$975 - connect \Y $ternary$libresoc.v:41816$2240_Y + connect \S \wp$989 + connect \Y $ternary$libresoc.v:42442$2275_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:41980.6-41997.4" + attribute \src "libresoc.v:42603.6-42620.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -72787,175 +73698,176 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:41998.11-42019.4" + attribute \src "libresoc.v:42621.11-42642.4" cell \dec_ALU \dec_ALU - connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len - connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit - connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data - connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok - connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry - connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn - connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type - connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in - connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out - connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit - connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed - connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe - connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok - connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry - connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok - connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc - connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 - connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a + connect \ALU__data_len \dec_ALU_ALU__data_len + connect \ALU__fn_unit \dec_ALU_ALU__fn_unit + connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data + connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok + connect \ALU__input_carry \dec_ALU_ALU__input_carry + connect \ALU__insn \dec_ALU_ALU__insn + connect \ALU__insn_type \dec_ALU_ALU__insn_type + connect \ALU__invert_in \dec_ALU_ALU__invert_in + connect \ALU__invert_out \dec_ALU_ALU__invert_out + connect \ALU__is_32bit \dec_ALU_ALU__is_32bit + connect \ALU__is_signed \dec_ALU_ALU__is_signed + connect \ALU__oe__oe \dec_ALU_ALU__oe__oe + connect \ALU__oe__ok \dec_ALU_ALU__oe__ok + connect \ALU__output_carry \dec_ALU_ALU__output_carry + connect \ALU__rc__ok \dec_ALU_ALU__rc__ok + connect \ALU__rc__rc \dec_ALU_ALU__rc__rc + connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 + connect \ALU__zero_a \dec_ALU_ALU__zero_a connect \bigendian \dec_ALU_bigendian connect \raw_opcode_in \dec_ALU_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42020.14-42032.4" + attribute \src "libresoc.v:42643.14-42655.4" cell \dec_BRANCH \dec_BRANCH - connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia - connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit - connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data - connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok - connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn - connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type - connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit - connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk + connect \BRANCH__cia \dec_BRANCH_BRANCH__cia + connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit + connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data + connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok + connect \BRANCH__insn \dec_BRANCH_BRANCH__insn + connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type + connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit + connect \BRANCH__lk \dec_BRANCH_BRANCH__lk connect \bigendian \dec_BRANCH_bigendian connect \core_pc \core_pc connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42033.10-42039.4" + attribute \src "libresoc.v:42656.10-42662.4" cell \dec_CR \dec_CR - connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit - connect \CR_CR__insn \dec_CR_CR_CR__insn - connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type + connect \CR__fn_unit \dec_CR_CR__fn_unit + connect \CR__insn \dec_CR_CR__insn + connect \CR__insn_type \dec_CR_CR__insn_type connect \bigendian \dec_CR_bigendian connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42040.11-42061.4" + attribute \src "libresoc.v:42663.11-42684.4" cell \dec_DIV \dec_DIV - connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len - connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit - connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data - connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok - connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry - connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn - connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type - connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in - connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out - connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit - connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed - connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe - connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok - connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry - connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok - connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc - connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 - connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a + connect \DIV__data_len \dec_DIV_DIV__data_len + connect \DIV__fn_unit \dec_DIV_DIV__fn_unit + connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data + connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok + connect \DIV__input_carry \dec_DIV_DIV__input_carry + connect \DIV__insn \dec_DIV_DIV__insn + connect \DIV__insn_type \dec_DIV_DIV__insn_type + connect \DIV__invert_in \dec_DIV_DIV__invert_in + connect \DIV__invert_out \dec_DIV_DIV__invert_out + connect \DIV__is_32bit \dec_DIV_DIV__is_32bit + connect \DIV__is_signed \dec_DIV_DIV__is_signed + connect \DIV__oe__oe \dec_DIV_DIV__oe__oe + connect \DIV__oe__ok \dec_DIV_DIV__oe__ok + connect \DIV__output_carry \dec_DIV_DIV__output_carry + connect \DIV__rc__ok \dec_DIV_DIV__rc__ok + connect \DIV__rc__rc \dec_DIV_DIV__rc__rc + connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 + connect \DIV__zero_a \dec_DIV_DIV__zero_a connect \bigendian \dec_DIV_bigendian connect \raw_opcode_in \dec_DIV_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42062.12-42081.4" + attribute \src "libresoc.v:42685.12-42704.4" cell \dec_LDST \dec_LDST - connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse - connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len - connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit - connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data - connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok - connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn - connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type - connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit - connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed - connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode - connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe - connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok - connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok - connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc - connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend - connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a + connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse + connect \LDST__data_len \dec_LDST_LDST__data_len + connect \LDST__fn_unit \dec_LDST_LDST__fn_unit + connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data + connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok + connect \LDST__insn \dec_LDST_LDST__insn + connect \LDST__insn_type \dec_LDST_LDST__insn_type + connect \LDST__is_32bit \dec_LDST_LDST__is_32bit + connect \LDST__is_signed \dec_LDST_LDST__is_signed + connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode + connect \LDST__oe__oe \dec_LDST_LDST__oe__oe + connect \LDST__oe__ok \dec_LDST_LDST__oe__ok + connect \LDST__rc__ok \dec_LDST_LDST__rc__ok + connect \LDST__rc__rc \dec_LDST_LDST__rc__rc + connect \LDST__sign_extend \dec_LDST_LDST__sign_extend + connect \LDST__zero_a \dec_LDST_LDST__zero_a connect \bigendian \dec_LDST_bigendian connect \raw_opcode_in \dec_LDST_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42082.15-42103.4" + attribute \src "libresoc.v:42705.15-42726.4" cell \dec_LOGICAL \dec_LOGICAL - connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len - connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data - connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok - connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn - connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe - connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok - connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok - connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc - connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len + connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry + connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn + connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type + connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in + connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out + connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed + connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry + connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a connect \bigendian \dec_LOGICAL_bigendian connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42104.11-42119.4" + attribute \src "libresoc.v:42727.11-42742.4" cell \dec_MUL \dec_MUL - connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit - connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data - connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok - connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn - connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type - connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit - connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed - connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe - connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok - connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok - connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc - connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 + connect \MUL__fn_unit \dec_MUL_MUL__fn_unit + connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data + connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok + connect \MUL__insn \dec_MUL_MUL__insn + connect \MUL__insn_type \dec_MUL_MUL__insn_type + connect \MUL__is_32bit \dec_MUL_MUL__is_32bit + connect \MUL__is_signed \dec_MUL_MUL__is_signed + connect \MUL__oe__oe \dec_MUL_MUL__oe__oe + connect \MUL__oe__ok \dec_MUL_MUL__oe__ok + connect \MUL__rc__ok \dec_MUL_MUL__rc__ok + connect \MUL__rc__rc \dec_MUL_MUL__rc__rc + connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 connect \bigendian \dec_MUL_bigendian connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42120.17-42139.4" + attribute \src "libresoc.v:42743.17-42763.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT - connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data - connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok - connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe - connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok - connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok - connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc - connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 connect \bigendian \dec_SHIFT_ROT_bigendian connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42140.11-42147.4" + attribute \src "libresoc.v:42764.11-42771.4" cell \dec_SPR \dec_SPR - connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit - connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn - connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type - connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit + connect \SPR__fn_unit \dec_SPR_SPR__fn_unit + connect \SPR__insn \dec_SPR_SPR__insn + connect \SPR__insn_type \dec_SPR_SPR__insn_type + connect \SPR__is_32bit \dec_SPR_SPR__is_32bit connect \bigendian \dec_SPR_bigendian connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42148.8-42166.4" + attribute \src "libresoc.v:42772.8-42790.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -72963,7 +73875,7 @@ module \core connect \dest1__data_i \fast_dest1__data_i connect \dest1__wen \fast_dest1__wen connect \issue__addr \issue__addr - connect \issue__addr$1 \issue__addr$3 + connect \issue__addr$1 \issue__addr$10 connect \issue__data_i \issue__data_i connect \issue__data_o \issue__data_o connect \issue__ren \issue__ren @@ -72976,138 +73888,145 @@ module \core connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42167.7-42489.4" + attribute \src "libresoc.v:42791.7-43122.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$110 \fus_cr_a_ok$113 - connect \cr_a_ok$111 \fus_cr_a_ok$114 - connect \cr_a_ok$112 \fus_cr_a_ok$115 - connect \cr_a_ok$113 \fus_cr_a_ok$116 - connect \cr_a_ok$114 \fus_cr_a_ok$117 + connect \cr_a_ok$110 \fus_cr_a_ok$120 + connect \cr_a_ok$111 \fus_cr_a_ok$121 + connect \cr_a_ok$112 \fus_cr_a_ok$122 + connect \cr_a_ok$113 \fus_cr_a_ok$123 + connect \cr_a_ok$114 \fus_cr_a_ok$124 connect \cu_ad__go_i \cu_ad__go_i connect \cu_ad__rel_o \cu_ad__rel_o connect \cu_busy_o \fus_cu_busy_o - connect \cu_busy_o$11 \fus_cu_busy_o$14 - connect \cu_busy_o$14 \fus_cu_busy_o$17 - connect \cu_busy_o$17 \fus_cu_busy_o$20 - connect \cu_busy_o$2 \fus_cu_busy_o$5 - connect \cu_busy_o$20 \fus_cu_busy_o$23 - connect \cu_busy_o$23 \fus_cu_busy_o$26 - connect \cu_busy_o$26 \fus_cu_busy_o$29 - connect \cu_busy_o$5 \fus_cu_busy_o$8 - connect \cu_busy_o$8 \fus_cu_busy_o$11 + connect \cu_busy_o$11 \fus_cu_busy_o$21 + connect \cu_busy_o$14 \fus_cu_busy_o$24 + connect \cu_busy_o$17 \fus_cu_busy_o$27 + connect \cu_busy_o$2 \fus_cu_busy_o$12 + connect \cu_busy_o$20 \fus_cu_busy_o$30 + connect \cu_busy_o$23 \fus_cu_busy_o$33 + connect \cu_busy_o$26 \fus_cu_busy_o$36 + connect \cu_busy_o$5 \fus_cu_busy_o$15 + connect \cu_busy_o$8 \fus_cu_busy_o$18 connect \cu_issue_i \fus_cu_issue_i - connect \cu_issue_i$1 \fus_cu_issue_i$4 - connect \cu_issue_i$10 \fus_cu_issue_i$13 - connect \cu_issue_i$13 \fus_cu_issue_i$16 - connect \cu_issue_i$16 \fus_cu_issue_i$19 - connect \cu_issue_i$19 \fus_cu_issue_i$22 - connect \cu_issue_i$22 \fus_cu_issue_i$25 - connect \cu_issue_i$25 \fus_cu_issue_i$28 - connect \cu_issue_i$4 \fus_cu_issue_i$7 - connect \cu_issue_i$7 \fus_cu_issue_i$10 + connect \cu_issue_i$1 \fus_cu_issue_i$11 + connect \cu_issue_i$10 \fus_cu_issue_i$20 + connect \cu_issue_i$13 \fus_cu_issue_i$23 + connect \cu_issue_i$16 \fus_cu_issue_i$26 + connect \cu_issue_i$19 \fus_cu_issue_i$29 + connect \cu_issue_i$22 \fus_cu_issue_i$32 + connect \cu_issue_i$25 \fus_cu_issue_i$35 + connect \cu_issue_i$4 \fus_cu_issue_i$14 + connect \cu_issue_i$7 \fus_cu_issue_i$17 connect \cu_rd__go_i \fus_cu_rd__go_i - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 - connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$39 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$42 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$45 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$48 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$51 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$54 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$57 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$60 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$80 connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 - connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$38 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$41 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$44 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$47 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$50 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$53 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$56 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$59 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$79 connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$22 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$25 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$28 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$31 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$34 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$37 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$13 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$16 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$19 connect \cu_st__go_i \cu_st__go_i connect \cu_st__rel_o \cu_st__rel_o connect \cu_wr__go_i \fus_cu_wr__go_i - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 - connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 - connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 - connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 - connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 - connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 - connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 - connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$110 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$112 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$147 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$92 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$95 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$98 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$101 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$104 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$107 connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 - connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 - connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 - connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 - connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 - connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 - connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$111 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$146 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$91 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$94 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$97 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$100 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$103 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$106 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$109 connect \dest1_o \fus_dest1_o - connect \dest1_o$103 \fus_dest1_o$106 - connect \dest1_o$104 \fus_dest1_o$107 - connect \dest1_o$105 \fus_dest1_o$108 - connect \dest1_o$106 \fus_dest1_o$109 - connect \dest1_o$107 \fus_dest1_o$110 - connect \dest1_o$108 \fus_dest1_o$111 - connect \dest1_o$109 \fus_dest1_o$112 - connect \dest1_o$141 \fus_dest1_o$144 + connect \dest1_o$103 \fus_dest1_o$113 + connect \dest1_o$104 \fus_dest1_o$114 + connect \dest1_o$105 \fus_dest1_o$115 + connect \dest1_o$106 \fus_dest1_o$116 + connect \dest1_o$107 \fus_dest1_o$117 + connect \dest1_o$108 \fus_dest1_o$118 + connect \dest1_o$109 \fus_dest1_o$119 + connect \dest1_o$141 \fus_dest1_o$151 connect \dest2_o \fus_dest2_o - connect \dest2_o$115 \fus_dest2_o$118 - connect \dest2_o$116 \fus_dest2_o$119 - connect \dest2_o$117 \fus_dest2_o$120 - connect \dest2_o$118 \fus_dest2_o$121 - connect \dest2_o$119 \fus_dest2_o$122 - connect \dest2_o$142 \fus_dest2_o$145 - connect \dest2_o$144 \fus_dest2_o$147 - connect \dest2_o$150 \fus_dest2_o$153 + connect \dest2_o$115 \fus_dest2_o$125 + connect \dest2_o$116 \fus_dest2_o$126 + connect \dest2_o$117 \fus_dest2_o$127 + connect \dest2_o$118 \fus_dest2_o$128 + connect \dest2_o$119 \fus_dest2_o$129 + connect \dest2_o$142 \fus_dest2_o$152 + connect \dest2_o$144 \fus_dest2_o$154 + connect \dest2_o$150 \fus_dest2_o$160 connect \dest3_o \fus_dest3_o - connect \dest3_o$122 \fus_dest3_o$125 - connect \dest3_o$123 \fus_dest3_o$126 - connect \dest3_o$127 \fus_dest3_o$130 - connect \dest3_o$128 \fus_dest3_o$131 - connect \dest3_o$143 \fus_dest3_o$146 - connect \dest3_o$145 \fus_dest3_o$148 - connect \dest3_o$147 \fus_dest3_o$150 + connect \dest3_o$122 \fus_dest3_o$132 + connect \dest3_o$123 \fus_dest3_o$133 + connect \dest3_o$127 \fus_dest3_o$137 + connect \dest3_o$128 \fus_dest3_o$138 + connect \dest3_o$143 \fus_dest3_o$153 + connect \dest3_o$145 \fus_dest3_o$155 + connect \dest3_o$147 \fus_dest3_o$157 connect \dest4_o \fus_dest4_o - connect \dest4_o$133 \fus_dest4_o$136 - connect \dest4_o$134 \fus_dest4_o$137 - connect \dest4_o$135 \fus_dest4_o$138 - connect \dest4_o$148 \fus_dest4_o$151 + connect \dest4_o$133 \fus_dest4_o$143 + connect \dest4_o$134 \fus_dest4_o$144 + connect \dest4_o$135 \fus_dest4_o$145 + connect \dest4_o$148 \fus_dest4_o$158 connect \dest5_o \fus_dest5_o - connect \dest5_o$132 \fus_dest5_o$135 - connect \dest5_o$149 \fus_dest5_o$152 + connect \dest5_o$132 \fus_dest5_o$142 + connect \dest5_o$149 \fus_dest5_o$159 connect \dest6_o \fus_dest6_o connect \ea \fus_ea connect \fast1_ok \fus_fast1_ok - connect \fast1_ok$138 \fus_fast1_ok$141 - connect \fast1_ok$139 \fus_fast1_ok$142 + connect \fast1_ok$138 \fus_fast1_ok$148 + connect \fast1_ok$139 \fus_fast1_ok$149 connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$143 + connect \fast2_ok$140 \fus_fast2_ok$150 connect \full_cr_ok \fus_full_cr_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o connect \ldst_port0_addr_i \fus_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$161 + connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$162 + connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$167 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o @@ -73116,16 +74035,16 @@ module \core connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok connect \msr_ok \fus_msr_ok connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$149 + connect \nia_ok$146 \fus_nia_ok$156 connect \o \fus_o connect \o_ok \fus_o_ok - connect \o_ok$80 \fus_o_ok$83 - connect \o_ok$83 \fus_o_ok$86 - connect \o_ok$86 \fus_o_ok$89 - connect \o_ok$89 \fus_o_ok$92 - connect \o_ok$92 \fus_o_ok$95 - connect \o_ok$95 \fus_o_ok$98 - connect \o_ok$98 \fus_o_ok$101 + connect \o_ok$80 \fus_o_ok$90 + connect \o_ok$83 \fus_o_ok$93 + connect \o_ok$86 \fus_o_ok$96 + connect \o_ok$89 \fus_o_ok$99 + connect \o_ok$92 \fus_o_ok$102 + connect \o_ok$95 \fus_o_ok$105 + connect \o_ok$98 \fus_o_ok$108 connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data @@ -73210,6 +74129,7 @@ module \core connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe @@ -73228,6 +74148,7 @@ module \core connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype @@ -73249,59 +74170,59 @@ module \core connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a connect \spr1_ok \fus_spr1_ok connect \src1_i \fus_src1_i - connect \src1_i$30 \fus_src1_i$33 - connect \src1_i$33 \fus_src1_i$36 - connect \src1_i$36 \fus_src1_i$39 - connect \src1_i$39 \fus_src1_i$42 - connect \src1_i$42 \fus_src1_i$45 - connect \src1_i$45 \fus_src1_i$48 - connect \src1_i$48 \fus_src1_i$51 - connect \src1_i$51 \fus_src1_i$54 - connect \src1_i$74 \fus_src1_i$77 + connect \src1_i$30 \fus_src1_i$40 + connect \src1_i$33 \fus_src1_i$43 + connect \src1_i$36 \fus_src1_i$46 + connect \src1_i$39 \fus_src1_i$49 + connect \src1_i$42 \fus_src1_i$52 + connect \src1_i$45 \fus_src1_i$55 + connect \src1_i$48 \fus_src1_i$58 + connect \src1_i$51 \fus_src1_i$61 + connect \src1_i$74 \fus_src1_i$84 connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$55 - connect \src2_i$53 \fus_src2_i$56 - connect \src2_i$54 \fus_src2_i$57 - connect \src2_i$55 \fus_src2_i$58 - connect \src2_i$56 \fus_src2_i$59 - connect \src2_i$57 \fus_src2_i$60 - connect \src2_i$58 \fus_src2_i$61 - connect \src2_i$77 \fus_src2_i$80 - connect \src2_i$79 \fus_src2_i$82 + connect \src2_i$52 \fus_src2_i$62 + connect \src2_i$53 \fus_src2_i$63 + connect \src2_i$54 \fus_src2_i$64 + connect \src2_i$55 \fus_src2_i$65 + connect \src2_i$56 \fus_src2_i$66 + connect \src2_i$57 \fus_src2_i$67 + connect \src2_i$58 \fus_src2_i$68 + connect \src2_i$77 \fus_src2_i$87 + connect \src2_i$79 \fus_src2_i$89 connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$62 - connect \src3_i$60 \fus_src3_i$63 - connect \src3_i$61 \fus_src3_i$64 - connect \src3_i$62 \fus_src3_i$65 - connect \src3_i$63 \fus_src3_i$66 - connect \src3_i$67 \fus_src3_i$70 - connect \src3_i$71 \fus_src3_i$74 - connect \src3_i$75 \fus_src3_i$78 - connect \src3_i$76 \fus_src3_i$79 + connect \src3_i$59 \fus_src3_i$69 + connect \src3_i$60 \fus_src3_i$70 + connect \src3_i$61 \fus_src3_i$71 + connect \src3_i$62 \fus_src3_i$72 + connect \src3_i$63 \fus_src3_i$73 + connect \src3_i$67 \fus_src3_i$77 + connect \src3_i$71 \fus_src3_i$81 + connect \src3_i$75 \fus_src3_i$85 + connect \src3_i$76 \fus_src3_i$86 connect \src4_i \fus_src4_i - connect \src4_i$64 \fus_src4_i$67 - connect \src4_i$65 \fus_src4_i$68 - connect \src4_i$68 \fus_src4_i$71 - connect \src4_i$78 \fus_src4_i$81 + connect \src4_i$64 \fus_src4_i$74 + connect \src4_i$65 \fus_src4_i$75 + connect \src4_i$68 \fus_src4_i$78 + connect \src4_i$78 \fus_src4_i$88 connect \src5_i \fus_src5_i - connect \src5_i$66 \fus_src5_i$69 - connect \src5_i$72 \fus_src5_i$75 + connect \src5_i$66 \fus_src5_i$76 + connect \src5_i$72 \fus_src5_i$82 connect \src6_i \fus_src6_i - connect \src6_i$73 \fus_src6_i$76 + connect \src6_i$73 \fus_src6_i$83 connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$120 \fus_xer_ca_ok$123 - connect \xer_ca_ok$121 \fus_xer_ca_ok$124 + connect \xer_ca_ok$120 \fus_xer_ca_ok$130 + connect \xer_ca_ok$121 \fus_xer_ca_ok$131 connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$127 - connect \xer_ov_ok$125 \fus_xer_ov_ok$128 - connect \xer_ov_ok$126 \fus_xer_ov_ok$129 + connect \xer_ov_ok$124 \fus_xer_ov_ok$134 + connect \xer_ov_ok$125 \fus_xer_ov_ok$135 + connect \xer_ov_ok$126 \fus_xer_ov_ok$136 connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$132 - connect \xer_so_ok$130 \fus_xer_so_ok$133 - connect \xer_so_ok$131 \fus_xer_so_ok$134 + connect \xer_so_ok$129 \fus_xer_so_ok$139 + connect \xer_so_ok$130 \fus_xer_so_ok$140 + connect \xer_so_ok$131 \fus_xer_so_ok$141 end attribute \module_not_derived 1 - attribute \src "libresoc.v:42490.9-42508.4" + attribute \src "libresoc.v:43123.9-43141.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73322,7 +74243,7 @@ module \core connect \src3__ren \int_src3__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42509.6-42533.4" + attribute \src "libresoc.v:43142.6-43174.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73335,124 +74256,132 @@ module \core connect \dbus__sel \dbus__sel connect \dbus__stb \dbus__stb connect \dbus__we \dbus__we - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o connect \ldst_port0_addr_i \fus_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$161 + connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$162 + connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$167 connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:42534.18-42538.4" + attribute \src "libresoc.v:43175.18-43179.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42539.18-42543.4" + attribute \src "libresoc.v:43180.18-43184.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42544.18-42548.4" + attribute \src "libresoc.v:43185.18-43189.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42549.21-42553.4" + attribute \src "libresoc.v:43190.21-43194.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42554.21-42558.4" + attribute \src "libresoc.v:43195.21-43199.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42559.21-42563.4" + attribute \src "libresoc.v:43200.21-43204.4" cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \en_o \rdpick_FAST_fast2_en_o connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42564.17-42568.4" + attribute \src "libresoc.v:43205.17-43209.4" cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42569.17-42573.4" + attribute \src "libresoc.v:43210.17-43214.4" cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42574.17-42578.4" + attribute \src "libresoc.v:43215.17-43219.4" cell \rdpick_INT_rc \rdpick_INT_rc connect \en_o \rdpick_INT_rc_en_o connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42579.19-42583.4" + attribute \src "libresoc.v:43220.19-43224.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42584.21-42588.4" + attribute \src "libresoc.v:43225.21-43229.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42589.21-42593.4" + attribute \src "libresoc.v:43230.21-43234.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42594.21-42598.4" + attribute \src "libresoc.v:43235.21-43239.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42599.7-42608.4" + attribute \src "libresoc.v:43240.7-43249.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \spr1__addr \spr_spr1__addr - connect \spr1__addr$1 \spr_spr1__addr$159 + connect \spr1__addr$1 \spr_spr1__addr$173 connect \spr1__data_i \spr_spr1__data_i connect \spr1__data_o \spr_spr1__data_o connect \spr1__ren \spr_spr1__ren connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:42609.9-42622.4" + attribute \src "libresoc.v:43250.9-43263.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -73460,7 +74389,7 @@ module \core connect \coresync_rst \coresync_rst connect \data_i \data_i connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$158 + connect \data_i$2 \state_data_i$172 connect \msr__data_o \msr__data_o connect \msr__ren \msr__ren connect \state_nia_wen \state_nia_wen @@ -73468,83 +74397,83 @@ module \core connect \wen$3 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:42623.18-42627.4" + attribute \src "libresoc.v:43264.18-43268.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42628.21-42632.4" + attribute \src "libresoc.v:43269.21-43273.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42633.21-42637.4" + attribute \src "libresoc.v:43274.21-43278.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42638.16-42642.4" + attribute \src "libresoc.v:43279.16-43283.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42643.19-42647.4" + attribute \src "libresoc.v:43284.19-43288.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42648.20-42652.4" + attribute \src "libresoc.v:43289.20-43293.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42653.20-42657.4" + attribute \src "libresoc.v:43294.20-43298.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42658.21-42662.4" + attribute \src "libresoc.v:43299.21-43303.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42663.21-42667.4" + attribute \src "libresoc.v:43304.21-43308.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42668.21-42672.4" + attribute \src "libresoc.v:43309.21-43313.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:42673.7-42690.4" + attribute \src "libresoc.v:43314.7-43331.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \data_i \xer_data_i - connect \data_i$1 \xer_data_i$154 - connect \data_i$3 \xer_data_i$156 + connect \data_i$1 \xer_data_i$168 + connect \data_i$3 \xer_data_i$170 connect \full_rd__data_o \full_rd__data_o connect \full_rd__ren \full_rd__ren connect \src1__data_o \xer_src1__data_o @@ -73554,1220 +74483,1265 @@ module \core connect \src3__data_o \xer_src3__data_o connect \src3__ren \xer_src3__ren connect \wen \xer_wen - connect \wen$2 \xer_wen$155 - connect \wen$4 \xer_wen$157 + connect \wen$2 \xer_wen$169 + connect \wen$4 \xer_wen$171 end - attribute \src "libresoc.v:35346.7-35346.20" - process $proc$libresoc.v:35346$2906 + attribute \src "libresoc.v:35933.7-35933.20" + process $proc$libresoc.v:35933$2940 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:37364.7-37364.30" - process $proc$libresoc.v:37364$2907 + attribute \src "libresoc.v:37965.7-37965.30" + process $proc$libresoc.v:37965$2941 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:37377.13-37377.27" - process $proc$libresoc.v:37377$2908 + attribute \src "libresoc.v:37978.13-37978.27" + process $proc$libresoc.v:37978$2942 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:38505.7-38505.34" - process $proc$libresoc.v:38505$2909 + attribute \src "libresoc.v:39108.7-39108.34" + process $proc$libresoc.v:39108$2943 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:38509.7-38509.30" - process $proc$libresoc.v:38509$2910 + attribute \src "libresoc.v:39112.7-39112.30" + process $proc$libresoc.v:39112$2944 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:38513.7-38513.30" - process $proc$libresoc.v:38513$2911 + attribute \src "libresoc.v:39116.7-39116.30" + process $proc$libresoc.v:39116$2945 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:38517.7-38517.30" - process $proc$libresoc.v:38517$2912 + attribute \src "libresoc.v:39120.7-39120.30" + process $proc$libresoc.v:39120$2946 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:38521.7-38521.33" - process $proc$libresoc.v:38521$2913 + attribute \src "libresoc.v:39124.7-39124.33" + process $proc$libresoc.v:39124$2947 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:38525.7-38525.37" - process $proc$libresoc.v:38525$2914 + attribute \src "libresoc.v:39128.7-39128.37" + process $proc$libresoc.v:39128$2948 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:38529.7-38529.34" - process $proc$libresoc.v:38529$2915 + attribute \src "libresoc.v:39132.7-39132.34" + process $proc$libresoc.v:39132$2949 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:38533.7-38533.35" - process $proc$libresoc.v:38533$2916 + attribute \src "libresoc.v:39136.7-39136.35" + process $proc$libresoc.v:39136$2950 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:38537.7-38537.37" - process $proc$libresoc.v:38537$2917 + attribute \src "libresoc.v:39140.7-39140.37" + process $proc$libresoc.v:39140$2951 assign { } { } assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:38541.7-38541.35" - process $proc$libresoc.v:38541$2918 + attribute \src "libresoc.v:39144.7-39144.35" + process $proc$libresoc.v:39144$2952 assign { } { } assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:38545.7-38545.30" - process $proc$libresoc.v:38545$2919 + attribute \src "libresoc.v:39148.7-39148.30" + process $proc$libresoc.v:39148$2953 assign { } { } assign $1\dp_INT_ra_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:38549.7-38549.29" - process $proc$libresoc.v:38549$2920 + attribute \src "libresoc.v:39152.7-39152.29" + process $proc$libresoc.v:39152$2954 assign { } { } assign $1\dp_INT_ra_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:38553.7-38553.30" - process $proc$libresoc.v:38553$2921 + attribute \src "libresoc.v:39156.7-39156.30" + process $proc$libresoc.v:39156$2955 assign { } { } assign $1\dp_INT_ra_div0_5[0:0] 1'0 sync always sync init update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:38557.7-38557.31" - process $proc$libresoc.v:38557$2922 + attribute \src "libresoc.v:39160.7-39160.31" + process $proc$libresoc.v:39160$2956 assign { } { } assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 sync always sync init update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:38561.7-38561.34" - process $proc$libresoc.v:38561$2923 + attribute \src "libresoc.v:39164.7-39164.34" + process $proc$libresoc.v:39164$2957 assign { } { } assign $1\dp_INT_ra_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:38565.7-38565.30" - process $proc$libresoc.v:38565$2924 + attribute \src "libresoc.v:39168.7-39168.30" + process $proc$libresoc.v:39168$2958 assign { } { } assign $1\dp_INT_ra_mul0_6[0:0] 1'0 sync always sync init update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:38569.7-38569.35" - process $proc$libresoc.v:38569$2925 + attribute \src "libresoc.v:39172.7-39172.35" + process $proc$libresoc.v:39172$2959 assign { } { } assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 sync always sync init update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:38573.7-38573.30" - process $proc$libresoc.v:38573$2926 + attribute \src "libresoc.v:39176.7-39176.30" + process $proc$libresoc.v:39176$2960 assign { } { } assign $1\dp_INT_ra_spr0_4[0:0] 1'0 sync always sync init update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:38577.7-38577.31" - process $proc$libresoc.v:38577$2927 + attribute \src "libresoc.v:39180.7-39180.31" + process $proc$libresoc.v:39180$2961 assign { } { } assign $1\dp_INT_ra_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:38581.7-38581.30" - process $proc$libresoc.v:38581$2928 + attribute \src "libresoc.v:39184.7-39184.30" + process $proc$libresoc.v:39184$2962 assign { } { } assign $1\dp_INT_rb_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:38585.7-38585.29" - process $proc$libresoc.v:38585$2929 + attribute \src "libresoc.v:39188.7-39188.29" + process $proc$libresoc.v:39188$2963 assign { } { } assign $1\dp_INT_rb_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:38589.7-38589.30" - process $proc$libresoc.v:38589$2930 + attribute \src "libresoc.v:39192.7-39192.30" + process $proc$libresoc.v:39192$2964 assign { } { } assign $1\dp_INT_rb_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:38593.7-38593.31" - process $proc$libresoc.v:38593$2931 + attribute \src "libresoc.v:39196.7-39196.31" + process $proc$libresoc.v:39196$2965 assign { } { } assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:38597.7-38597.34" - process $proc$libresoc.v:38597$2932 + attribute \src "libresoc.v:39200.7-39200.34" + process $proc$libresoc.v:39200$2966 assign { } { } assign $1\dp_INT_rb_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:38601.7-38601.30" - process $proc$libresoc.v:38601$2933 + attribute \src "libresoc.v:39204.7-39204.30" + process $proc$libresoc.v:39204$2967 assign { } { } assign $1\dp_INT_rb_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:38605.7-38605.35" - process $proc$libresoc.v:38605$2934 + attribute \src "libresoc.v:39208.7-39208.35" + process $proc$libresoc.v:39208$2968 assign { } { } assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:38609.7-38609.31" - process $proc$libresoc.v:38609$2935 + attribute \src "libresoc.v:39212.7-39212.31" + process $proc$libresoc.v:39212$2969 assign { } { } assign $1\dp_INT_rb_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:38613.7-38613.31" - process $proc$libresoc.v:38613$2936 + attribute \src "libresoc.v:39216.7-39216.31" + process $proc$libresoc.v:39216$2970 assign { } { } assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 sync always sync init update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:38617.7-38617.35" - process $proc$libresoc.v:38617$2937 + attribute \src "libresoc.v:39220.7-39220.35" + process $proc$libresoc.v:39220$2971 assign { } { } assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 sync always sync init update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:38621.7-38621.32" - process $proc$libresoc.v:38621$2938 + attribute \src "libresoc.v:39224.7-39224.32" + process $proc$libresoc.v:39224$2972 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:38625.7-38625.34" - process $proc$libresoc.v:38625$2939 + attribute \src "libresoc.v:39228.7-39228.34" + process $proc$libresoc.v:39228$2973 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:38629.7-38629.39" - process $proc$libresoc.v:38629$2940 + attribute \src "libresoc.v:39232.7-39232.39" + process $proc$libresoc.v:39232$2974 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:38633.7-38633.34" - process $proc$libresoc.v:38633$2941 + attribute \src "libresoc.v:39236.7-39236.34" + process $proc$libresoc.v:39236$2975 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:38637.7-38637.34" - process $proc$libresoc.v:38637$2942 + attribute \src "libresoc.v:39240.7-39240.34" + process $proc$libresoc.v:39240$2976 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:38641.7-38641.34" - process $proc$libresoc.v:38641$2943 + attribute \src "libresoc.v:39244.7-39244.34" + process $proc$libresoc.v:39244$2977 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:38645.7-38645.34" - process $proc$libresoc.v:38645$2944 + attribute \src "libresoc.v:39248.7-39248.34" + process $proc$libresoc.v:39248$2978 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:38649.7-38649.38" - process $proc$libresoc.v:38649$2945 + attribute \src "libresoc.v:39252.7-39252.38" + process $proc$libresoc.v:39252$2979 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:38653.7-38653.34" - process $proc$libresoc.v:38653$2946 + attribute \src "libresoc.v:39256.7-39256.34" + process $proc$libresoc.v:39256$2980 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:38657.7-38657.39" - process $proc$libresoc.v:38657$2947 + attribute \src "libresoc.v:39260.7-39260.39" + process $proc$libresoc.v:39260$2981 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:38661.7-38661.34" - process $proc$libresoc.v:38661$2948 + attribute \src "libresoc.v:39264.7-39264.34" + process $proc$libresoc.v:39264$2982 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:40718.7-40718.25" - process $proc$libresoc.v:40718$2949 + attribute \src "libresoc.v:41341.7-41341.25" + process $proc$libresoc.v:41341$2983 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:40720.7-40720.32" - process $proc$libresoc.v:40720$2950 + attribute \src "libresoc.v:41343.7-41343.32" + process $proc$libresoc.v:41343$2984 assign { } { } - assign $0\wr_pick_dly$1007[0:0]$2951 1'0 + assign $0\wr_pick_dly$1000[0:0]$2985 1'0 sync always sync init - update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2951 + update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2985 end - attribute \src "libresoc.v:40724.7-40724.32" - process $proc$libresoc.v:40724$2952 + attribute \src "libresoc.v:41347.7-41347.32" + process $proc$libresoc.v:41347$2986 assign { } { } - assign $0\wr_pick_dly$1025[0:0]$2953 1'0 + assign $0\wr_pick_dly$1021[0:0]$2987 1'0 sync always sync init - update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2953 + update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2987 end - attribute \src "libresoc.v:40728.7-40728.32" - process $proc$libresoc.v:40728$2954 + attribute \src "libresoc.v:41351.7-41351.32" + process $proc$libresoc.v:41351$2988 assign { } { } - assign $0\wr_pick_dly$1047[0:0]$2955 1'0 + assign $0\wr_pick_dly$1039[0:0]$2989 1'0 sync always sync init - update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2955 + update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2989 end - attribute \src "libresoc.v:40732.7-40732.32" - process $proc$libresoc.v:40732$2956 + attribute \src "libresoc.v:41355.7-41355.32" + process $proc$libresoc.v:41355$2990 assign { } { } - assign $0\wr_pick_dly$1067[0:0]$2957 1'0 + assign $0\wr_pick_dly$1061[0:0]$2991 1'0 sync always sync init - update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2957 + update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2991 end - attribute \src "libresoc.v:40736.7-40736.32" - process $proc$libresoc.v:40736$2958 + attribute \src "libresoc.v:41359.7-41359.32" + process $proc$libresoc.v:41359$2992 assign { } { } - assign $0\wr_pick_dly$1087[0:0]$2959 1'0 + assign $0\wr_pick_dly$1081[0:0]$2993 1'0 sync always sync init - update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2959 + update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2993 end - attribute \src "libresoc.v:40740.7-40740.32" - process $proc$libresoc.v:40740$2960 + attribute \src "libresoc.v:41363.7-41363.32" + process $proc$libresoc.v:41363$2994 assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2961 1'0 + assign $0\wr_pick_dly$1101[0:0]$2995 1'0 sync always sync init - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2961 + update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2995 end - attribute \src "libresoc.v:40744.7-40744.32" - process $proc$libresoc.v:40744$2962 + attribute \src "libresoc.v:41367.7-41367.32" + process $proc$libresoc.v:41367$2996 assign { } { } - assign $0\wr_pick_dly$1124[0:0]$2963 1'0 + assign $0\wr_pick_dly$1120[0:0]$2997 1'0 sync always sync init - update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2963 + update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2997 end - attribute \src "libresoc.v:40748.7-40748.32" - process $proc$libresoc.v:40748$2964 + attribute \src "libresoc.v:41371.7-41371.32" + process $proc$libresoc.v:41371$2998 assign { } { } - assign $0\wr_pick_dly$1197[0:0]$2965 1'0 + assign $0\wr_pick_dly$1138[0:0]$2999 1'0 sync always sync init - update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2965 + update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2999 end - attribute \src "libresoc.v:40752.7-40752.32" - process $proc$libresoc.v:40752$2966 + attribute \src "libresoc.v:41375.7-41375.32" + process $proc$libresoc.v:41375$3000 assign { } { } - assign $0\wr_pick_dly$1225[0:0]$2967 1'0 + assign $0\wr_pick_dly$1211[0:0]$3001 1'0 sync always sync init - update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2967 + update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$3001 end - attribute \src "libresoc.v:40756.7-40756.32" - process $proc$libresoc.v:40756$2968 + attribute \src "libresoc.v:41379.7-41379.32" + process $proc$libresoc.v:41379$3002 assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2969 1'0 + assign $0\wr_pick_dly$1239[0:0]$3003 1'0 sync always sync init - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2969 + update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$3003 end - attribute \src "libresoc.v:40760.7-40760.32" - process $proc$libresoc.v:40760$2970 + attribute \src "libresoc.v:41383.7-41383.32" + process $proc$libresoc.v:41383$3004 assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2971 1'0 + assign $0\wr_pick_dly$1259[0:0]$3005 1'0 sync always sync init - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2971 + update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$3005 end - attribute \src "libresoc.v:40764.7-40764.32" - process $proc$libresoc.v:40764$2972 + attribute \src "libresoc.v:41387.7-41387.32" + process $proc$libresoc.v:41387$3006 assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2973 1'0 + assign $0\wr_pick_dly$1279[0:0]$3007 1'0 sync always sync init - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2973 + update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$3007 end - attribute \src "libresoc.v:40768.7-40768.32" - process $proc$libresoc.v:40768$2974 + attribute \src "libresoc.v:41391.7-41391.32" + process $proc$libresoc.v:41391$3008 assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2975 1'0 + assign $0\wr_pick_dly$1299[0:0]$3009 1'0 sync always sync init - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2975 + update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$3009 end - attribute \src "libresoc.v:40772.7-40772.32" - process $proc$libresoc.v:40772$2976 + attribute \src "libresoc.v:41395.7-41395.32" + process $proc$libresoc.v:41395$3010 assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2977 1'0 + assign $0\wr_pick_dly$1319[0:0]$3011 1'0 sync always sync init - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2977 + update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$3011 end - attribute \src "libresoc.v:40776.7-40776.32" - process $proc$libresoc.v:40776$2978 + attribute \src "libresoc.v:41399.7-41399.32" + process $proc$libresoc.v:41399$3012 assign { } { } - assign $0\wr_pick_dly$1372[0:0]$2979 1'0 + assign $0\wr_pick_dly$1339[0:0]$3013 1'0 sync always sync init - update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2979 + update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$3013 end - attribute \src "libresoc.v:40780.7-40780.32" - process $proc$libresoc.v:40780$2980 + attribute \src "libresoc.v:41403.7-41403.32" + process $proc$libresoc.v:41403$3014 assign { } { } - assign $0\wr_pick_dly$1388[0:0]$2981 1'0 + assign $0\wr_pick_dly$1386[0:0]$3015 1'0 sync always sync init - update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2981 + update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$3015 end - attribute \src "libresoc.v:40784.7-40784.32" - process $proc$libresoc.v:40784$2982 + attribute \src "libresoc.v:41407.7-41407.32" + process $proc$libresoc.v:41407$3016 assign { } { } - assign $0\wr_pick_dly$1404[0:0]$2983 1'0 + assign $0\wr_pick_dly$1402[0:0]$3017 1'0 sync always sync init - update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2983 + update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$3017 end - attribute \src "libresoc.v:40788.7-40788.32" - process $proc$libresoc.v:40788$2984 + attribute \src "libresoc.v:41411.7-41411.32" + process $proc$libresoc.v:41411$3018 assign { } { } - assign $0\wr_pick_dly$1438[0:0]$2985 1'0 + assign $0\wr_pick_dly$1418[0:0]$3019 1'0 sync always sync init - update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2985 + update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$3019 end - attribute \src "libresoc.v:40792.7-40792.32" - process $proc$libresoc.v:40792$2986 + attribute \src "libresoc.v:41415.7-41415.32" + process $proc$libresoc.v:41415$3020 assign { } { } - assign $0\wr_pick_dly$1454[0:0]$2987 1'0 + assign $0\wr_pick_dly$1452[0:0]$3021 1'0 sync always sync init - update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2987 + update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$3021 end - attribute \src "libresoc.v:40796.7-40796.32" - process $proc$libresoc.v:40796$2988 + attribute \src "libresoc.v:41419.7-41419.32" + process $proc$libresoc.v:41419$3022 assign { } { } - assign $0\wr_pick_dly$1470[0:0]$2989 1'0 + assign $0\wr_pick_dly$1468[0:0]$3023 1'0 sync always sync init - update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2989 + update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$3023 end - attribute \src "libresoc.v:40800.7-40800.32" - process $proc$libresoc.v:40800$2990 + attribute \src "libresoc.v:41423.7-41423.32" + process $proc$libresoc.v:41423$3024 assign { } { } - assign $0\wr_pick_dly$1486[0:0]$2991 1'0 + assign $0\wr_pick_dly$1484[0:0]$3025 1'0 sync always sync init - update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2991 + update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$3025 end - attribute \src "libresoc.v:40804.7-40804.32" - process $proc$libresoc.v:40804$2992 + attribute \src "libresoc.v:41427.7-41427.32" + process $proc$libresoc.v:41427$3026 assign { } { } - assign $0\wr_pick_dly$1522[0:0]$2993 1'0 + assign $0\wr_pick_dly$1500[0:0]$3027 1'0 sync always sync init - update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2993 + update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$3027 end - attribute \src "libresoc.v:40808.7-40808.32" - process $proc$libresoc.v:40808$2994 + attribute \src "libresoc.v:41431.7-41431.32" + process $proc$libresoc.v:41431$3028 assign { } { } - assign $0\wr_pick_dly$1538[0:0]$2995 1'0 + assign $0\wr_pick_dly$1536[0:0]$3029 1'0 sync always sync init - update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2995 + update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$3029 end - attribute \src "libresoc.v:40812.7-40812.32" - process $proc$libresoc.v:40812$2996 + attribute \src "libresoc.v:41435.7-41435.32" + process $proc$libresoc.v:41435$3030 assign { } { } - assign $0\wr_pick_dly$1554[0:0]$2997 1'0 + assign $0\wr_pick_dly$1552[0:0]$3031 1'0 sync always sync init - update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2997 + update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$3031 end - attribute \src "libresoc.v:40816.7-40816.32" - process $proc$libresoc.v:40816$2998 + attribute \src "libresoc.v:41439.7-41439.32" + process $proc$libresoc.v:41439$3032 assign { } { } - assign $0\wr_pick_dly$1570[0:0]$2999 1'0 + assign $0\wr_pick_dly$1568[0:0]$3033 1'0 sync always sync init - update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2999 + update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$3033 end - attribute \src "libresoc.v:40820.7-40820.32" - process $proc$libresoc.v:40820$3000 + attribute \src "libresoc.v:41443.7-41443.32" + process $proc$libresoc.v:41443$3034 assign { } { } - assign $0\wr_pick_dly$1612[0:0]$3001 1'0 + assign $0\wr_pick_dly$1584[0:0]$3035 1'0 sync always sync init - update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$3001 + update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$3035 end - attribute \src "libresoc.v:40824.7-40824.32" - process $proc$libresoc.v:40824$3002 + attribute \src "libresoc.v:41447.7-41447.32" + process $proc$libresoc.v:41447$3036 assign { } { } - assign $0\wr_pick_dly$1631[0:0]$3003 1'0 + assign $0\wr_pick_dly$1626[0:0]$3037 1'0 sync always sync init - update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$3003 + update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$3037 end - attribute \src "libresoc.v:40828.7-40828.32" - process $proc$libresoc.v:40828$3004 + attribute \src "libresoc.v:41451.7-41451.32" + process $proc$libresoc.v:41451$3038 assign { } { } - assign $0\wr_pick_dly$1647[0:0]$3005 1'0 + assign $0\wr_pick_dly$1645[0:0]$3039 1'0 sync always sync init - update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$3005 + update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$3039 end - attribute \src "libresoc.v:40832.7-40832.32" - process $proc$libresoc.v:40832$3006 + attribute \src "libresoc.v:41455.7-41455.32" + process $proc$libresoc.v:41455$3040 assign { } { } - assign $0\wr_pick_dly$1663[0:0]$3007 1'0 + assign $0\wr_pick_dly$1661[0:0]$3041 1'0 sync always sync init - update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$3007 + update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$3041 end - attribute \src "libresoc.v:40836.7-40836.32" - process $proc$libresoc.v:40836$3008 + attribute \src "libresoc.v:41459.7-41459.32" + process $proc$libresoc.v:41459$3042 assign { } { } - assign $0\wr_pick_dly$1679[0:0]$3009 1'0 + assign $0\wr_pick_dly$1677[0:0]$3043 1'0 sync always sync init - update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$3009 + update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$3043 end - attribute \src "libresoc.v:40840.7-40840.32" - process $proc$libresoc.v:40840$3010 + attribute \src "libresoc.v:41463.7-41463.32" + process $proc$libresoc.v:41463$3044 assign { } { } - assign $0\wr_pick_dly$1723[0:0]$3011 1'0 + assign $0\wr_pick_dly$1693[0:0]$3045 1'0 sync always sync init - update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$3011 + update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$3045 end - attribute \src "libresoc.v:40844.7-40844.32" - process $proc$libresoc.v:40844$3012 + attribute \src "libresoc.v:41467.7-41467.32" + process $proc$libresoc.v:41467$3046 assign { } { } - assign $0\wr_pick_dly$1739[0:0]$3013 1'0 + assign $0\wr_pick_dly$1737[0:0]$3047 1'0 sync always sync init - update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$3013 + update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$3047 end - attribute \src "libresoc.v:40848.7-40848.32" - process $proc$libresoc.v:40848$3014 + attribute \src "libresoc.v:41471.7-41471.32" + process $proc$libresoc.v:41471$3048 assign { } { } - assign $0\wr_pick_dly$1763[0:0]$3015 1'0 + assign $0\wr_pick_dly$1753[0:0]$3049 1'0 sync always sync init - update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$3015 + update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$3049 end - attribute \src "libresoc.v:40852.7-40852.32" - process $proc$libresoc.v:40852$3016 + attribute \src "libresoc.v:41475.7-41475.32" + process $proc$libresoc.v:41475$3050 assign { } { } - assign $0\wr_pick_dly$1783[0:0]$3017 1'0 + assign $0\wr_pick_dly$1777[0:0]$3051 1'0 sync always sync init - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$3017 + update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$3051 end - attribute \src "libresoc.v:40856.7-40856.31" - process $proc$libresoc.v:40856$3018 + attribute \src "libresoc.v:41479.7-41479.32" + process $proc$libresoc.v:41479$3052 assign { } { } - assign $0\wr_pick_dly$967[0:0]$3019 1'0 + assign $0\wr_pick_dly$1797[0:0]$3053 1'0 sync always sync init - update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$3019 + update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$3053 end - attribute \src "libresoc.v:40860.7-40860.31" - process $proc$libresoc.v:40860$3020 + attribute \src "libresoc.v:41483.7-41483.31" + process $proc$libresoc.v:41483$3054 assign { } { } - assign $0\wr_pick_dly$986[0:0]$3021 1'0 + assign $0\wr_pick_dly$981[0:0]$3055 1'0 sync always sync init - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$3021 + update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$3055 end - attribute \src "libresoc.v:41822.3-41823.51" - process $proc$libresoc.v:41822$2246 + attribute \src "libresoc.v:42445.3-42446.51" + process $proc$libresoc.v:42445$2278 assign { } { } - assign $0\wr_pick_dly$1783[0:0]$2247 \wr_pick_dly$1783$next + assign $0\wr_pick_dly$1797[0:0]$2279 \wr_pick_dly$1797$next sync posedge \coresync_clk - update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2247 + update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$2279 end - attribute \src "libresoc.v:41824.3-41825.51" - process $proc$libresoc.v:41824$2248 + attribute \src "libresoc.v:42447.3-42448.51" + process $proc$libresoc.v:42447$2280 assign { } { } - assign $0\wr_pick_dly$1763[0:0]$2249 \wr_pick_dly$1763$next + assign $0\wr_pick_dly$1777[0:0]$2281 \wr_pick_dly$1777$next sync posedge \coresync_clk - update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2249 + update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$2281 end - attribute \src "libresoc.v:41826.3-41827.51" - process $proc$libresoc.v:41826$2250 + attribute \src "libresoc.v:42449.3-42450.51" + process $proc$libresoc.v:42449$2282 assign { } { } - assign $0\wr_pick_dly$1739[0:0]$2251 \wr_pick_dly$1739$next + assign $0\wr_pick_dly$1753[0:0]$2283 \wr_pick_dly$1753$next sync posedge \coresync_clk - update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2251 + update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$2283 end - attribute \src "libresoc.v:41828.3-41829.51" - process $proc$libresoc.v:41828$2252 + attribute \src "libresoc.v:42451.3-42452.51" + process $proc$libresoc.v:42451$2284 assign { } { } - assign $0\wr_pick_dly$1723[0:0]$2253 \wr_pick_dly$1723$next + assign $0\wr_pick_dly$1737[0:0]$2285 \wr_pick_dly$1737$next sync posedge \coresync_clk - update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2253 + update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$2285 end - attribute \src "libresoc.v:41830.3-41831.51" - process $proc$libresoc.v:41830$2254 + attribute \src "libresoc.v:42453.3-42454.51" + process $proc$libresoc.v:42453$2286 assign { } { } - assign $0\wr_pick_dly$1679[0:0]$2255 \wr_pick_dly$1679$next + assign $0\wr_pick_dly$1693[0:0]$2287 \wr_pick_dly$1693$next sync posedge \coresync_clk - update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2255 + update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$2287 end - attribute \src "libresoc.v:41832.3-41833.51" - process $proc$libresoc.v:41832$2256 + attribute \src "libresoc.v:42455.3-42456.51" + process $proc$libresoc.v:42455$2288 assign { } { } - assign $0\wr_pick_dly$1663[0:0]$2257 \wr_pick_dly$1663$next + assign $0\wr_pick_dly$1677[0:0]$2289 \wr_pick_dly$1677$next sync posedge \coresync_clk - update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2257 + update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$2289 end - attribute \src "libresoc.v:41834.3-41835.51" - process $proc$libresoc.v:41834$2258 + attribute \src "libresoc.v:42457.3-42458.51" + process $proc$libresoc.v:42457$2290 assign { } { } - assign $0\wr_pick_dly$1647[0:0]$2259 \wr_pick_dly$1647$next + assign $0\wr_pick_dly$1661[0:0]$2291 \wr_pick_dly$1661$next sync posedge \coresync_clk - update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2259 + update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$2291 end - attribute \src "libresoc.v:41836.3-41837.51" - process $proc$libresoc.v:41836$2260 + attribute \src "libresoc.v:42459.3-42460.51" + process $proc$libresoc.v:42459$2292 assign { } { } - assign $0\wr_pick_dly$1631[0:0]$2261 \wr_pick_dly$1631$next + assign $0\wr_pick_dly$1645[0:0]$2293 \wr_pick_dly$1645$next sync posedge \coresync_clk - update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2261 + update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2293 end - attribute \src "libresoc.v:41838.3-41839.51" - process $proc$libresoc.v:41838$2262 + attribute \src "libresoc.v:42461.3-42462.51" + process $proc$libresoc.v:42461$2294 assign { } { } - assign $0\wr_pick_dly$1612[0:0]$2263 \wr_pick_dly$1612$next + assign $0\wr_pick_dly$1626[0:0]$2295 \wr_pick_dly$1626$next sync posedge \coresync_clk - update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2263 + update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2295 end - attribute \src "libresoc.v:41840.3-41841.51" - process $proc$libresoc.v:41840$2264 + attribute \src "libresoc.v:42463.3-42464.51" + process $proc$libresoc.v:42463$2296 assign { } { } - assign $0\wr_pick_dly$1570[0:0]$2265 \wr_pick_dly$1570$next + assign $0\wr_pick_dly$1584[0:0]$2297 \wr_pick_dly$1584$next sync posedge \coresync_clk - update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2265 + update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2297 end - attribute \src "libresoc.v:41842.3-41843.51" - process $proc$libresoc.v:41842$2266 + attribute \src "libresoc.v:42465.3-42466.51" + process $proc$libresoc.v:42465$2298 assign { } { } - assign $0\wr_pick_dly$1554[0:0]$2267 \wr_pick_dly$1554$next + assign $0\wr_pick_dly$1568[0:0]$2299 \wr_pick_dly$1568$next sync posedge \coresync_clk - update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2267 + update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2299 end - attribute \src "libresoc.v:41844.3-41845.51" - process $proc$libresoc.v:41844$2268 + attribute \src "libresoc.v:42467.3-42468.51" + process $proc$libresoc.v:42467$2300 assign { } { } - assign $0\wr_pick_dly$1538[0:0]$2269 \wr_pick_dly$1538$next + assign $0\wr_pick_dly$1552[0:0]$2301 \wr_pick_dly$1552$next sync posedge \coresync_clk - update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2269 + update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2301 end - attribute \src "libresoc.v:41846.3-41847.51" - process $proc$libresoc.v:41846$2270 + attribute \src "libresoc.v:42469.3-42470.51" + process $proc$libresoc.v:42469$2302 assign { } { } - assign $0\wr_pick_dly$1522[0:0]$2271 \wr_pick_dly$1522$next + assign $0\wr_pick_dly$1536[0:0]$2303 \wr_pick_dly$1536$next sync posedge \coresync_clk - update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2271 + update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2303 end - attribute \src "libresoc.v:41848.3-41849.51" - process $proc$libresoc.v:41848$2272 + attribute \src "libresoc.v:42471.3-42472.51" + process $proc$libresoc.v:42471$2304 assign { } { } - assign $0\wr_pick_dly$1486[0:0]$2273 \wr_pick_dly$1486$next + assign $0\wr_pick_dly$1500[0:0]$2305 \wr_pick_dly$1500$next sync posedge \coresync_clk - update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2273 + update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2305 end - attribute \src "libresoc.v:41850.3-41851.51" - process $proc$libresoc.v:41850$2274 + attribute \src "libresoc.v:42473.3-42474.51" + process $proc$libresoc.v:42473$2306 assign { } { } - assign $0\wr_pick_dly$1470[0:0]$2275 \wr_pick_dly$1470$next + assign $0\wr_pick_dly$1484[0:0]$2307 \wr_pick_dly$1484$next sync posedge \coresync_clk - update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2275 + update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2307 end - attribute \src "libresoc.v:41852.3-41853.51" - process $proc$libresoc.v:41852$2276 + attribute \src "libresoc.v:42475.3-42476.51" + process $proc$libresoc.v:42475$2308 assign { } { } - assign $0\wr_pick_dly$1454[0:0]$2277 \wr_pick_dly$1454$next + assign $0\wr_pick_dly$1468[0:0]$2309 \wr_pick_dly$1468$next sync posedge \coresync_clk - update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2277 + update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2309 end - attribute \src "libresoc.v:41854.3-41855.51" - process $proc$libresoc.v:41854$2278 + attribute \src "libresoc.v:42477.3-42478.51" + process $proc$libresoc.v:42477$2310 assign { } { } - assign $0\wr_pick_dly$1438[0:0]$2279 \wr_pick_dly$1438$next + assign $0\wr_pick_dly$1452[0:0]$2311 \wr_pick_dly$1452$next sync posedge \coresync_clk - update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2279 + update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2311 end - attribute \src "libresoc.v:41856.3-41857.51" - process $proc$libresoc.v:41856$2280 + attribute \src "libresoc.v:42479.3-42480.51" + process $proc$libresoc.v:42479$2312 assign { } { } - assign $0\wr_pick_dly$1404[0:0]$2281 \wr_pick_dly$1404$next + assign $0\wr_pick_dly$1418[0:0]$2313 \wr_pick_dly$1418$next sync posedge \coresync_clk - update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2281 + update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2313 end - attribute \src "libresoc.v:41858.3-41859.51" - process $proc$libresoc.v:41858$2282 + attribute \src "libresoc.v:42481.3-42482.51" + process $proc$libresoc.v:42481$2314 assign { } { } - assign $0\wr_pick_dly$1388[0:0]$2283 \wr_pick_dly$1388$next + assign $0\wr_pick_dly$1402[0:0]$2315 \wr_pick_dly$1402$next sync posedge \coresync_clk - update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2283 + update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2315 end - attribute \src "libresoc.v:41860.3-41861.51" - process $proc$libresoc.v:41860$2284 + attribute \src "libresoc.v:42483.3-42484.51" + process $proc$libresoc.v:42483$2316 assign { } { } - assign $0\wr_pick_dly$1372[0:0]$2285 \wr_pick_dly$1372$next + assign $0\wr_pick_dly$1386[0:0]$2317 \wr_pick_dly$1386$next sync posedge \coresync_clk - update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2285 + update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2317 end - attribute \src "libresoc.v:41862.3-41863.51" - process $proc$libresoc.v:41862$2286 + attribute \src "libresoc.v:42485.3-42486.51" + process $proc$libresoc.v:42485$2318 assign { } { } - assign $0\wr_pick_dly$1325[0:0]$2287 \wr_pick_dly$1325$next + assign $0\wr_pick_dly$1339[0:0]$2319 \wr_pick_dly$1339$next sync posedge \coresync_clk - update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2287 + update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2319 end - attribute \src "libresoc.v:41864.3-41865.51" - process $proc$libresoc.v:41864$2288 + attribute \src "libresoc.v:42487.3-42488.51" + process $proc$libresoc.v:42487$2320 assign { } { } - assign $0\wr_pick_dly$1305[0:0]$2289 \wr_pick_dly$1305$next + assign $0\wr_pick_dly$1319[0:0]$2321 \wr_pick_dly$1319$next sync posedge \coresync_clk - update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2289 + update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2321 end - attribute \src "libresoc.v:41866.3-41867.51" - process $proc$libresoc.v:41866$2290 + attribute \src "libresoc.v:42489.3-42490.51" + process $proc$libresoc.v:42489$2322 assign { } { } - assign $0\wr_pick_dly$1285[0:0]$2291 \wr_pick_dly$1285$next + assign $0\wr_pick_dly$1299[0:0]$2323 \wr_pick_dly$1299$next sync posedge \coresync_clk - update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2291 + update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2323 end - attribute \src "libresoc.v:41868.3-41869.51" - process $proc$libresoc.v:41868$2292 + attribute \src "libresoc.v:42491.3-42492.51" + process $proc$libresoc.v:42491$2324 assign { } { } - assign $0\wr_pick_dly$1265[0:0]$2293 \wr_pick_dly$1265$next + assign $0\wr_pick_dly$1279[0:0]$2325 \wr_pick_dly$1279$next sync posedge \coresync_clk - update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2293 + update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2325 end - attribute \src "libresoc.v:41870.3-41871.51" - process $proc$libresoc.v:41870$2294 + attribute \src "libresoc.v:42493.3-42494.51" + process $proc$libresoc.v:42493$2326 assign { } { } - assign $0\wr_pick_dly$1245[0:0]$2295 \wr_pick_dly$1245$next + assign $0\wr_pick_dly$1259[0:0]$2327 \wr_pick_dly$1259$next sync posedge \coresync_clk - update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2295 + update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2327 end - attribute \src "libresoc.v:41872.3-41873.51" - process $proc$libresoc.v:41872$2296 + attribute \src "libresoc.v:42495.3-42496.51" + process $proc$libresoc.v:42495$2328 assign { } { } - assign $0\wr_pick_dly$1225[0:0]$2297 \wr_pick_dly$1225$next + assign $0\wr_pick_dly$1239[0:0]$2329 \wr_pick_dly$1239$next sync posedge \coresync_clk - update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2297 + update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2329 end - attribute \src "libresoc.v:41874.3-41875.51" - process $proc$libresoc.v:41874$2298 + attribute \src "libresoc.v:42497.3-42498.51" + process $proc$libresoc.v:42497$2330 assign { } { } - assign $0\wr_pick_dly$1197[0:0]$2299 \wr_pick_dly$1197$next + assign $0\wr_pick_dly$1211[0:0]$2331 \wr_pick_dly$1211$next sync posedge \coresync_clk - update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2299 + update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2331 end - attribute \src "libresoc.v:41876.3-41877.51" - process $proc$libresoc.v:41876$2300 + attribute \src "libresoc.v:42499.3-42500.51" + process $proc$libresoc.v:42499$2332 assign { } { } - assign $0\wr_pick_dly$1124[0:0]$2301 \wr_pick_dly$1124$next + assign $0\wr_pick_dly$1138[0:0]$2333 \wr_pick_dly$1138$next sync posedge \coresync_clk - update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2301 + update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2333 end - attribute \src "libresoc.v:41878.3-41879.51" - process $proc$libresoc.v:41878$2302 + attribute \src "libresoc.v:42501.3-42502.51" + process $proc$libresoc.v:42501$2334 assign { } { } - assign $0\wr_pick_dly$1106[0:0]$2303 \wr_pick_dly$1106$next + assign $0\wr_pick_dly$1120[0:0]$2335 \wr_pick_dly$1120$next sync posedge \coresync_clk - update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2303 + update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2335 end - attribute \src "libresoc.v:41880.3-41881.51" - process $proc$libresoc.v:41880$2304 + attribute \src "libresoc.v:42503.3-42504.51" + process $proc$libresoc.v:42503$2336 assign { } { } - assign $0\wr_pick_dly$1087[0:0]$2305 \wr_pick_dly$1087$next + assign $0\wr_pick_dly$1101[0:0]$2337 \wr_pick_dly$1101$next sync posedge \coresync_clk - update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2305 + update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2337 end - attribute \src "libresoc.v:41882.3-41883.51" - process $proc$libresoc.v:41882$2306 + attribute \src "libresoc.v:42505.3-42506.51" + process $proc$libresoc.v:42505$2338 assign { } { } - assign $0\wr_pick_dly$1067[0:0]$2307 \wr_pick_dly$1067$next + assign $0\wr_pick_dly$1081[0:0]$2339 \wr_pick_dly$1081$next sync posedge \coresync_clk - update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2307 + update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2339 end - attribute \src "libresoc.v:41884.3-41885.51" - process $proc$libresoc.v:41884$2308 + attribute \src "libresoc.v:42507.3-42508.51" + process $proc$libresoc.v:42507$2340 assign { } { } - assign $0\wr_pick_dly$1047[0:0]$2309 \wr_pick_dly$1047$next + assign $0\wr_pick_dly$1061[0:0]$2341 \wr_pick_dly$1061$next sync posedge \coresync_clk - update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2309 + update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2341 end - attribute \src "libresoc.v:41886.3-41887.51" - process $proc$libresoc.v:41886$2310 + attribute \src "libresoc.v:42509.3-42510.51" + process $proc$libresoc.v:42509$2342 assign { } { } - assign $0\wr_pick_dly$1025[0:0]$2311 \wr_pick_dly$1025$next + assign $0\wr_pick_dly$1039[0:0]$2343 \wr_pick_dly$1039$next sync posedge \coresync_clk - update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2311 + update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2343 end - attribute \src "libresoc.v:41888.3-41889.51" - process $proc$libresoc.v:41888$2312 + attribute \src "libresoc.v:42511.3-42512.51" + process $proc$libresoc.v:42511$2344 assign { } { } - assign $0\wr_pick_dly$1007[0:0]$2313 \wr_pick_dly$1007$next + assign $0\wr_pick_dly$1021[0:0]$2345 \wr_pick_dly$1021$next sync posedge \coresync_clk - update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2313 + update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2345 end - attribute \src "libresoc.v:41890.3-41891.49" - process $proc$libresoc.v:41890$2314 + attribute \src "libresoc.v:42513.3-42514.51" + process $proc$libresoc.v:42513$2346 assign { } { } - assign $0\wr_pick_dly$986[0:0]$2315 \wr_pick_dly$986$next + assign $0\wr_pick_dly$1000[0:0]$2347 \wr_pick_dly$1000$next sync posedge \coresync_clk - update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2315 + update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2347 end - attribute \src "libresoc.v:41892.3-41893.49" - process $proc$libresoc.v:41892$2316 + attribute \src "libresoc.v:42515.3-42516.49" + process $proc$libresoc.v:42515$2348 assign { } { } - assign $0\wr_pick_dly$967[0:0]$2317 \wr_pick_dly$967$next + assign $0\wr_pick_dly$981[0:0]$2349 \wr_pick_dly$981$next sync posedge \coresync_clk - update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2317 + update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$2349 end - attribute \src "libresoc.v:41894.3-41895.39" - process $proc$libresoc.v:41894$2318 + attribute \src "libresoc.v:42517.3-42518.39" + process $proc$libresoc.v:42517$2350 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41896.3-41897.53" - process $proc$libresoc.v:41896$2319 + attribute \src "libresoc.v:42519.3-42520.53" + process $proc$libresoc.v:42519$2351 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:41898.3-41899.59" - process $proc$libresoc.v:41898$2320 + attribute \src "libresoc.v:42521.3-42522.59" + process $proc$libresoc.v:42521$2352 assign { } { } assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:41900.3-41901.63" - process $proc$libresoc.v:41900$2321 + attribute \src "libresoc.v:42523.3-42524.63" + process $proc$libresoc.v:42523$2353 assign { } { } assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:41902.3-41903.57" - process $proc$libresoc.v:41902$2322 + attribute \src "libresoc.v:42525.3-42526.57" + process $proc$libresoc.v:42525$2354 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:41904.3-41905.59" - process $proc$libresoc.v:41904$2323 + attribute \src "libresoc.v:42527.3-42528.59" + process $proc$libresoc.v:42527$2355 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:41906.3-41907.63" - process $proc$libresoc.v:41906$2324 + attribute \src "libresoc.v:42529.3-42530.63" + process $proc$libresoc.v:42529$2356 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:41908.3-41909.49" - process $proc$libresoc.v:41908$2325 + attribute \src "libresoc.v:42531.3-42532.49" + process $proc$libresoc.v:42531$2357 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:41910.3-41911.49" - process $proc$libresoc.v:41910$2326 + attribute \src "libresoc.v:42533.3-42534.49" + process $proc$libresoc.v:42533$2358 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:41912.3-41913.57" - process $proc$libresoc.v:41912$2327 + attribute \src "libresoc.v:42535.3-42536.57" + process $proc$libresoc.v:42535$2359 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:41914.3-41915.49" - process $proc$libresoc.v:41914$2328 + attribute \src "libresoc.v:42537.3-42538.49" + process $proc$libresoc.v:42537$2360 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:41916.3-41917.55" - process $proc$libresoc.v:41916$2329 + attribute \src "libresoc.v:42539.3-42540.55" + process $proc$libresoc.v:42539$2361 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:41918.3-41919.57" - process $proc$libresoc.v:41918$2330 + attribute \src "libresoc.v:42541.3-42542.57" + process $proc$libresoc.v:42541$2362 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:41920.3-41921.67" - process $proc$libresoc.v:41920$2331 + attribute \src "libresoc.v:42543.3-42544.67" + process $proc$libresoc.v:42543$2363 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:41922.3-41923.57" - process $proc$libresoc.v:41922$2332 + attribute \src "libresoc.v:42545.3-42546.57" + process $proc$libresoc.v:42545$2364 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:41924.3-41925.57" - process $proc$libresoc.v:41924$2333 + attribute \src "libresoc.v:42547.3-42548.57" + process $proc$libresoc.v:42547$2365 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:41926.3-41927.67" - process $proc$libresoc.v:41926$2334 + attribute \src "libresoc.v:42549.3-42550.67" + process $proc$libresoc.v:42549$2366 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:41928.3-41929.57" - process $proc$libresoc.v:41928$2335 + attribute \src "libresoc.v:42551.3-42552.57" + process $proc$libresoc.v:42551$2367 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:41930.3-41931.57" - process $proc$libresoc.v:41930$2336 + attribute \src "libresoc.v:42553.3-42554.57" + process $proc$libresoc.v:42553$2368 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:41932.3-41933.57" - process $proc$libresoc.v:41932$2337 + attribute \src "libresoc.v:42555.3-42556.57" + process $proc$libresoc.v:42555$2369 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41934.3-41935.65" - process $proc$libresoc.v:41934$2338 + attribute \src "libresoc.v:42557.3-42558.65" + process $proc$libresoc.v:42557$2370 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:41936.3-41937.57" - process $proc$libresoc.v:41936$2339 + attribute \src "libresoc.v:42559.3-42560.57" + process $proc$libresoc.v:42559$2371 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:41938.3-41939.51" - process $proc$libresoc.v:41938$2340 + attribute \src "libresoc.v:42561.3-42562.51" + process $proc$libresoc.v:42561$2372 assign { } { } assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:41940.3-41941.59" - process $proc$libresoc.v:41940$2341 + attribute \src "libresoc.v:42563.3-42564.59" + process $proc$libresoc.v:42563$2373 assign { } { } assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:41942.3-41943.51" - process $proc$libresoc.v:41942$2342 + attribute \src "libresoc.v:42565.3-42566.51" + process $proc$libresoc.v:42565$2374 assign { } { } assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:41944.3-41945.59" - process $proc$libresoc.v:41944$2343 + attribute \src "libresoc.v:42567.3-42568.59" + process $proc$libresoc.v:42567$2375 assign { } { } assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:41946.3-41947.49" - process $proc$libresoc.v:41946$2344 + attribute \src "libresoc.v:42569.3-42570.49" + process $proc$libresoc.v:42569$2376 assign { } { } assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next sync posedge \coresync_clk update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:41948.3-41949.49" - process $proc$libresoc.v:41948$2345 + attribute \src "libresoc.v:42571.3-42572.49" + process $proc$libresoc.v:42571$2377 assign { } { } assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next sync posedge \coresync_clk update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:41950.3-41951.57" - process $proc$libresoc.v:41950$2346 + attribute \src "libresoc.v:42573.3-42574.57" + process $proc$libresoc.v:42573$2378 assign { } { } assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next sync posedge \coresync_clk update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:41952.3-41953.51" - process $proc$libresoc.v:41952$2347 + attribute \src "libresoc.v:42575.3-42576.51" + process $proc$libresoc.v:42575$2379 assign { } { } assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next sync posedge \coresync_clk update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:41954.3-41955.47" - process $proc$libresoc.v:41954$2348 + attribute \src "libresoc.v:42577.3-42578.47" + process $proc$libresoc.v:42577$2380 assign { } { } assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next sync posedge \coresync_clk update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:41956.3-41957.49" - process $proc$libresoc.v:41956$2349 + attribute \src "libresoc.v:42579.3-42580.49" + process $proc$libresoc.v:42579$2381 assign { } { } assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next sync posedge \coresync_clk update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:41958.3-41959.51" - process $proc$libresoc.v:41958$2350 + attribute \src "libresoc.v:42581.3-42582.51" + process $proc$libresoc.v:42581$2382 assign { } { } assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:41960.3-41961.59" - process $proc$libresoc.v:41960$2351 + attribute \src "libresoc.v:42583.3-42584.59" + process $proc$libresoc.v:42583$2383 assign { } { } assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:41962.3-41963.49" - process $proc$libresoc.v:41962$2352 + attribute \src "libresoc.v:42585.3-42586.49" + process $proc$libresoc.v:42585$2384 assign { } { } assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next sync posedge \coresync_clk update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:41964.3-41965.49" - process $proc$libresoc.v:41964$2353 + attribute \src "libresoc.v:42587.3-42588.49" + process $proc$libresoc.v:42587$2385 assign { } { } assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next sync posedge \coresync_clk update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:41966.3-41967.49" - process $proc$libresoc.v:41966$2354 + attribute \src "libresoc.v:42589.3-42590.49" + process $proc$libresoc.v:42589$2386 assign { } { } assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next sync posedge \coresync_clk update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:41968.3-41969.57" - process $proc$libresoc.v:41968$2355 + attribute \src "libresoc.v:42591.3-42592.57" + process $proc$libresoc.v:42591$2387 assign { } { } assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next sync posedge \coresync_clk update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:41970.3-41971.51" - process $proc$libresoc.v:41970$2356 + attribute \src "libresoc.v:42593.3-42594.51" + process $proc$libresoc.v:42593$2388 assign { } { } assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next sync posedge \coresync_clk update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:41972.3-41973.47" - process $proc$libresoc.v:41972$2357 + attribute \src "libresoc.v:42595.3-42596.47" + process $proc$libresoc.v:42595$2389 assign { } { } assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next sync posedge \coresync_clk update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:41974.3-41975.49" - process $proc$libresoc.v:41974$2358 + attribute \src "libresoc.v:42597.3-42598.49" + process $proc$libresoc.v:42597$2390 assign { } { } assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next sync posedge \coresync_clk update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:41976.3-41977.49" - process $proc$libresoc.v:41976$2359 + attribute \src "libresoc.v:42599.3-42600.49" + process $proc$libresoc.v:42599$2391 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:41978.3-41979.31" - process $proc$libresoc.v:41978$2360 + attribute \src "libresoc.v:42601.3-42602.31" + process $proc$libresoc.v:42601$2392 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:42691.3-42719.6" - process $proc$libresoc.v:42691$2361 + attribute \src "libresoc.v:43332.3-43360.6" + process $proc$libresoc.v:43332$2393 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43333.5-43333.29" + switch \initial + attribute \src "libresoc.v:43333.9-43333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:43361.3-43389.6" + process $proc$libresoc.v:43361$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:42692.5-42692.29" + attribute \src "libresoc.v:43362.5-43362.29" switch \initial - attribute \src "libresoc.v:42692.9-42692.17" + attribute \src "libresoc.v:43362.9-43362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -74779,12 +75753,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR_SPR__is_32bit + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit case assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 end @@ -74795,114 +75769,114 @@ module \core sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end - attribute \src "libresoc.v:42720.3-42748.6" - process $proc$libresoc.v:42720$2362 + attribute \src "libresoc.v:43390.3-43418.6" + process $proc$libresoc.v:43390$2395 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$16[0:0]$2363 $1\fus_cu_issue_i$16[0:0]$2364 - attribute \src "libresoc.v:42721.5-42721.29" + assign $0\fus_cu_issue_i$23[0:0]$2396 $1\fus_cu_issue_i$23[0:0]$2397 + attribute \src "libresoc.v:43391.5-43391.29" switch \initial - attribute \src "libresoc.v:42721.9-42721.17" + attribute \src "libresoc.v:43391.9-43391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$16[0:0]$2364 $2\fus_cu_issue_i$16[0:0]$2365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$23[0:0]$2397 $2\fus_cu_issue_i$23[0:0]$2398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$16[0:0]$2365 1'0 + assign $2\fus_cu_issue_i$23[0:0]$2398 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$16[0:0]$2365 1'0 + assign $2\fus_cu_issue_i$23[0:0]$2398 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$16[0:0]$2365 $3\fus_cu_issue_i$16[0:0]$2366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$23[0:0]$2398 $3\fus_cu_issue_i$23[0:0]$2399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$16[0:0]$2366 \issue_i + assign $3\fus_cu_issue_i$23[0:0]$2399 \issue_i case - assign $3\fus_cu_issue_i$16[0:0]$2366 1'0 + assign $3\fus_cu_issue_i$23[0:0]$2399 1'0 end end case - assign $1\fus_cu_issue_i$16[0:0]$2364 1'0 + assign $1\fus_cu_issue_i$23[0:0]$2397 1'0 end sync always - update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2363 + update \fus_cu_issue_i$23 $0\fus_cu_issue_i$23[0:0]$2396 end - attribute \src "libresoc.v:42749.3-42777.6" - process $proc$libresoc.v:42749$2367 + attribute \src "libresoc.v:43419.3-43447.6" + process $proc$libresoc.v:43419$2400 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$18[5:0]$2368 $1\fus_cu_rdmaskn_i$18[5:0]$2369 - attribute \src "libresoc.v:42750.5-42750.29" + assign $0\fus_cu_rdmaskn_i$25[5:0]$2401 $1\fus_cu_rdmaskn_i$25[5:0]$2402 + attribute \src "libresoc.v:43420.5-43420.29" switch \initial - attribute \src "libresoc.v:42750.9-42750.17" + attribute \src "libresoc.v:43420.9-43420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$18[5:0]$2369 $2\fus_cu_rdmaskn_i$18[5:0]$2370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$25[5:0]$2402 $2\fus_cu_rdmaskn_i$25[5:0]$2403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 6'000000 + assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 6'000000 + assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$18[5:0]$2370 $3\fus_cu_rdmaskn_i$18[5:0]$2371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 $3\fus_cu_rdmaskn_i$25[5:0]$2404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$18[5:0]$2371 \$249 + assign $3\fus_cu_rdmaskn_i$25[5:0]$2404 \$263 case - assign $3\fus_cu_rdmaskn_i$18[5:0]$2371 6'000000 + assign $3\fus_cu_rdmaskn_i$25[5:0]$2404 6'000000 end end case - assign $1\fus_cu_rdmaskn_i$18[5:0]$2369 6'000000 + assign $1\fus_cu_rdmaskn_i$25[5:0]$2402 6'000000 end sync always - update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[5:0]$2368 + update \fus_cu_rdmaskn_i$25 $0\fus_cu_rdmaskn_i$25[5:0]$2401 end - attribute \src "libresoc.v:42778.3-42806.6" - process $proc$libresoc.v:42778$2372 + attribute \src "libresoc.v:43448.3-43476.6" + process $proc$libresoc.v:43448$2405 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:42779.5-42779.29" + attribute \src "libresoc.v:43449.5-43449.29" switch \initial - attribute \src "libresoc.v:42779.9-42779.17" + attribute \src "libresoc.v:43449.9-43449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -74914,12 +75888,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV_DIV__insn_type + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type case assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 end @@ -74930,24 +75904,24 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:42807.3-42835.6" - process $proc$libresoc.v:42807$2373 + attribute \src "libresoc.v:43477.3-43505.6" + process $proc$libresoc.v:43477$2406 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:42808.5-42808.29" + attribute \src "libresoc.v:43478.5-43478.29" switch \initial - attribute \src "libresoc.v:42808.9-42808.17" + attribute \src "libresoc.v:43478.9-43478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -74959,12 +75933,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV_DIV__fn_unit + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV__fn_unit case assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 end @@ -74975,21 +75949,21 @@ module \core sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] end - attribute \src "libresoc.v:42836.3-42865.6" - process $proc$libresoc.v:42836$2374 + attribute \src "libresoc.v:43506.3-43535.6" + process $proc$libresoc.v:43506$2407 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:42837.5-42837.29" + attribute \src "libresoc.v:43507.5-43507.29" switch \initial - attribute \src "libresoc.v:42837.9-42837.17" + attribute \src "libresoc.v:43507.9-43507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -74997,7 +75971,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75013,13 +75987,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } case assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 @@ -75033,21 +76007,21 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:42866.3-42895.6" - process $proc$libresoc.v:42866$2375 + attribute \src "libresoc.v:43536.3-43565.6" + process $proc$libresoc.v:43536$2408 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:42867.5-42867.29" + attribute \src "libresoc.v:43537.5-43537.29" switch \initial - attribute \src "libresoc.v:42867.9-42867.17" + attribute \src "libresoc.v:43537.9-43537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75055,7 +76029,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75071,13 +76045,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } case assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 @@ -75091,21 +76065,21 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:42896.3-42925.6" - process $proc$libresoc.v:42896$2376 + attribute \src "libresoc.v:43566.3-43595.6" + process $proc$libresoc.v:43566$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:42897.5-42897.29" + attribute \src "libresoc.v:43567.5-43567.29" switch \initial - attribute \src "libresoc.v:42897.9-42897.17" + attribute \src "libresoc.v:43567.9-43567.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75113,7 +76087,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75129,13 +76103,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } case assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 @@ -75149,24 +76123,24 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:42926.3-42954.6" - process $proc$libresoc.v:42926$2377 + attribute \src "libresoc.v:43596.3-43624.6" + process $proc$libresoc.v:43596$2410 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:42927.5-42927.29" + attribute \src "libresoc.v:43597.5-43597.29" switch \initial - attribute \src "libresoc.v:42927.9-42927.17" + attribute \src "libresoc.v:43597.9-43597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75178,12 +76152,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV_DIV__invert_in + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in case assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 end @@ -75194,24 +76168,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:42955.3-42983.6" - process $proc$libresoc.v:42955$2378 + attribute \src "libresoc.v:43625.3-43653.6" + process $proc$libresoc.v:43625$2411 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:42956.5-42956.29" + attribute \src "libresoc.v:43626.5-43626.29" switch \initial - attribute \src "libresoc.v:42956.9-42956.17" + attribute \src "libresoc.v:43626.9-43626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75223,12 +76197,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV_DIV__zero_a + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a case assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 end @@ -75239,24 +76213,24 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:42984.3-43012.6" - process $proc$libresoc.v:42984$2379 + attribute \src "libresoc.v:43654.3-43682.6" + process $proc$libresoc.v:43654$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:42985.5-42985.29" + attribute \src "libresoc.v:43655.5-43655.29" switch \initial - attribute \src "libresoc.v:42985.9-42985.17" + attribute \src "libresoc.v:43655.9-43655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75268,12 +76242,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV_DIV__input_carry + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry case assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 end @@ -75284,24 +76258,24 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:43013.3-43041.6" - process $proc$libresoc.v:43013$2380 + attribute \src "libresoc.v:43683.3-43711.6" + process $proc$libresoc.v:43683$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43014.5-43014.29" + attribute \src "libresoc.v:43684.5-43684.29" switch \initial - attribute \src "libresoc.v:43014.9-43014.17" + attribute \src "libresoc.v:43684.9-43684.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75313,12 +76287,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV_DIV__invert_out + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out case assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 end @@ -75329,24 +76303,24 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:43042.3-43070.6" - process $proc$libresoc.v:43042$2381 + attribute \src "libresoc.v:43712.3-43740.6" + process $proc$libresoc.v:43712$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43043.5-43043.29" + attribute \src "libresoc.v:43713.5-43713.29" switch \initial - attribute \src "libresoc.v:43043.9-43043.17" + attribute \src "libresoc.v:43713.9-43713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75358,12 +76332,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV_DIV__write_cr0 + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 case assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 end @@ -75374,24 +76348,24 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:43071.3-43099.6" - process $proc$libresoc.v:43071$2382 + attribute \src "libresoc.v:43741.3-43769.6" + process $proc$libresoc.v:43741$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43072.5-43072.29" + attribute \src "libresoc.v:43742.5-43742.29" switch \initial - attribute \src "libresoc.v:43072.9-43072.17" + attribute \src "libresoc.v:43742.9-43742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75403,12 +76377,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV_DIV__output_carry + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry case assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 end @@ -75419,24 +76393,24 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:43100.3-43128.6" - process $proc$libresoc.v:43100$2383 + attribute \src "libresoc.v:43770.3-43798.6" + process $proc$libresoc.v:43770$2416 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43101.5-43101.29" + attribute \src "libresoc.v:43771.5-43771.29" switch \initial - attribute \src "libresoc.v:43101.9-43101.17" + attribute \src "libresoc.v:43771.9-43771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75448,12 +76422,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV_DIV__is_32bit + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit case assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 end @@ -75464,24 +76438,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:43129.3-43157.6" - process $proc$libresoc.v:43129$2384 + attribute \src "libresoc.v:43799.3-43827.6" + process $proc$libresoc.v:43799$2417 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43130.5-43130.29" + attribute \src "libresoc.v:43800.5-43800.29" switch \initial - attribute \src "libresoc.v:43130.9-43130.17" + attribute \src "libresoc.v:43800.9-43800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75493,12 +76467,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV_DIV__is_signed + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed case assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 end @@ -75509,24 +76483,24 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:43158.3-43186.6" - process $proc$libresoc.v:43158$2385 + attribute \src "libresoc.v:43828.3-43856.6" + process $proc$libresoc.v:43828$2418 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43159.5-43159.29" + attribute \src "libresoc.v:43829.5-43829.29" switch \initial - attribute \src "libresoc.v:43159.9-43159.17" + attribute \src "libresoc.v:43829.9-43829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75538,12 +76512,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV_DIV__data_len + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len case assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 end @@ -75554,24 +76528,24 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:43187.3-43215.6" - process $proc$libresoc.v:43187$2386 + attribute \src "libresoc.v:43857.3-43885.6" + process $proc$libresoc.v:43857$2419 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43188.5-43188.29" + attribute \src "libresoc.v:43858.5-43858.29" switch \initial - attribute \src "libresoc.v:43188.9-43188.17" + attribute \src "libresoc.v:43858.9-43858.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75583,12 +76557,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV_DIV__insn + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn case assign $3\fus_oper_i_alu_div0__insn[31:0] 0 end @@ -75599,114 +76573,114 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:43216.3-43244.6" - process $proc$libresoc.v:43216$2387 + attribute \src "libresoc.v:43886.3-43914.6" + process $proc$libresoc.v:43886$2420 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$19[0:0]$2388 $1\fus_cu_issue_i$19[0:0]$2389 - attribute \src "libresoc.v:43217.5-43217.29" + assign $0\fus_cu_issue_i$26[0:0]$2421 $1\fus_cu_issue_i$26[0:0]$2422 + attribute \src "libresoc.v:43887.5-43887.29" switch \initial - attribute \src "libresoc.v:43217.9-43217.17" + attribute \src "libresoc.v:43887.9-43887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$19[0:0]$2389 $2\fus_cu_issue_i$19[0:0]$2390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$26[0:0]$2422 $2\fus_cu_issue_i$26[0:0]$2423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$19[0:0]$2390 1'0 + assign $2\fus_cu_issue_i$26[0:0]$2423 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$19[0:0]$2390 1'0 + assign $2\fus_cu_issue_i$26[0:0]$2423 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$19[0:0]$2390 $3\fus_cu_issue_i$19[0:0]$2391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$26[0:0]$2423 $3\fus_cu_issue_i$26[0:0]$2424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$19[0:0]$2391 \issue_i + assign $3\fus_cu_issue_i$26[0:0]$2424 \issue_i case - assign $3\fus_cu_issue_i$19[0:0]$2391 1'0 + assign $3\fus_cu_issue_i$26[0:0]$2424 1'0 end end case - assign $1\fus_cu_issue_i$19[0:0]$2389 1'0 + assign $1\fus_cu_issue_i$26[0:0]$2422 1'0 end sync always - update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2388 + update \fus_cu_issue_i$26 $0\fus_cu_issue_i$26[0:0]$2421 end - attribute \src "libresoc.v:43245.3-43273.6" - process $proc$libresoc.v:43245$2392 + attribute \src "libresoc.v:43915.3-43943.6" + process $proc$libresoc.v:43915$2425 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$21[2:0]$2393 $1\fus_cu_rdmaskn_i$21[2:0]$2394 - attribute \src "libresoc.v:43246.5-43246.29" + assign $0\fus_cu_rdmaskn_i$28[2:0]$2426 $1\fus_cu_rdmaskn_i$28[2:0]$2427 + attribute \src "libresoc.v:43916.5-43916.29" switch \initial - attribute \src "libresoc.v:43246.9-43246.17" + attribute \src "libresoc.v:43916.9-43916.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$21[2:0]$2394 $2\fus_cu_rdmaskn_i$21[2:0]$2395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$28[2:0]$2427 $2\fus_cu_rdmaskn_i$28[2:0]$2428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 3'000 + assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 3'000 + assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$21[2:0]$2395 $3\fus_cu_rdmaskn_i$21[2:0]$2396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 $3\fus_cu_rdmaskn_i$28[2:0]$2429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$21[2:0]$2396 \$279 + assign $3\fus_cu_rdmaskn_i$28[2:0]$2429 \$293 case - assign $3\fus_cu_rdmaskn_i$21[2:0]$2396 3'000 + assign $3\fus_cu_rdmaskn_i$28[2:0]$2429 3'000 end end case - assign $1\fus_cu_rdmaskn_i$21[2:0]$2394 3'000 + assign $1\fus_cu_rdmaskn_i$28[2:0]$2427 3'000 end sync always - update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[2:0]$2393 + update \fus_cu_rdmaskn_i$28 $0\fus_cu_rdmaskn_i$28[2:0]$2426 end - attribute \src "libresoc.v:43274.3-43302.6" - process $proc$libresoc.v:43274$2397 + attribute \src "libresoc.v:43944.3-43972.6" + process $proc$libresoc.v:43944$2430 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43275.5-43275.29" + attribute \src "libresoc.v:43945.5-43945.29" switch \initial - attribute \src "libresoc.v:43275.9-43275.17" + attribute \src "libresoc.v:43945.9-43945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75718,12 +76692,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL_MUL__insn_type + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type case assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 end @@ -75734,24 +76708,24 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:43303.3-43331.6" - process $proc$libresoc.v:43303$2398 + attribute \src "libresoc.v:43973.3-44001.6" + process $proc$libresoc.v:43973$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43304.5-43304.29" + attribute \src "libresoc.v:43974.5-43974.29" switch \initial - attribute \src "libresoc.v:43304.9-43304.17" + attribute \src "libresoc.v:43974.9-43974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75763,12 +76737,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL_MUL__fn_unit + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL__fn_unit case assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 end @@ -75779,21 +76753,21 @@ module \core sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] end - attribute \src "libresoc.v:43332.3-43361.6" - process $proc$libresoc.v:43332$2399 + attribute \src "libresoc.v:44002.3-44031.6" + process $proc$libresoc.v:44002$2432 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:43333.5-43333.29" + attribute \src "libresoc.v:44003.5-44003.29" switch \initial - attribute \src "libresoc.v:43333.9-43333.17" + attribute \src "libresoc.v:44003.9-44003.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75801,7 +76775,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75817,13 +76791,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } case assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 @@ -75837,21 +76811,21 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43362.3-43391.6" - process $proc$libresoc.v:43362$2400 + attribute \src "libresoc.v:44032.3-44061.6" + process $proc$libresoc.v:44032$2433 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:43363.5-43363.29" + attribute \src "libresoc.v:44033.5-44033.29" switch \initial - attribute \src "libresoc.v:43363.9-43363.17" + attribute \src "libresoc.v:44033.9-44033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75859,7 +76833,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75875,13 +76849,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } case assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 @@ -75895,21 +76869,21 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:43392.3-43421.6" - process $proc$libresoc.v:43392$2401 + attribute \src "libresoc.v:44062.3-44091.6" + process $proc$libresoc.v:44062$2434 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:43393.5-43393.29" + attribute \src "libresoc.v:44063.5-44063.29" switch \initial - attribute \src "libresoc.v:43393.9-43393.17" + attribute \src "libresoc.v:44063.9-44063.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -75917,7 +76891,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75933,13 +76907,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } case assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 @@ -75953,24 +76927,24 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:43422.3-43450.6" - process $proc$libresoc.v:43422$2402 + attribute \src "libresoc.v:44092.3-44120.6" + process $proc$libresoc.v:44092$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:43423.5-43423.29" + attribute \src "libresoc.v:44093.5-44093.29" switch \initial - attribute \src "libresoc.v:43423.9-43423.17" + attribute \src "libresoc.v:44093.9-44093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -75982,12 +76956,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL_MUL__write_cr0 + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 case assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 end @@ -75998,24 +76972,24 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:43451.3-43479.6" - process $proc$libresoc.v:43451$2403 + attribute \src "libresoc.v:44121.3-44149.6" + process $proc$libresoc.v:44121$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:43452.5-43452.29" + attribute \src "libresoc.v:44122.5-44122.29" switch \initial - attribute \src "libresoc.v:43452.9-43452.17" + attribute \src "libresoc.v:44122.9-44122.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76027,12 +77001,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL_MUL__is_32bit + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit case assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 end @@ -76043,24 +77017,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:43480.3-43508.6" - process $proc$libresoc.v:43480$2404 + attribute \src "libresoc.v:44150.3-44178.6" + process $proc$libresoc.v:44150$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:43481.5-43481.29" + attribute \src "libresoc.v:44151.5-44151.29" switch \initial - attribute \src "libresoc.v:43481.9-43481.17" + attribute \src "libresoc.v:44151.9-44151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76072,12 +77046,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL_MUL__is_signed + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed case assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 end @@ -76088,24 +77062,24 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:43509.3-43537.6" - process $proc$libresoc.v:43509$2405 + attribute \src "libresoc.v:44179.3-44207.6" + process $proc$libresoc.v:44179$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43510.5-43510.29" + attribute \src "libresoc.v:44180.5-44180.29" switch \initial - attribute \src "libresoc.v:43510.9-43510.17" + attribute \src "libresoc.v:44180.9-44180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76117,12 +77091,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL_MUL__insn + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn case assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 end @@ -76133,114 +77107,114 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:43538.3-43566.6" - process $proc$libresoc.v:43538$2406 + attribute \src "libresoc.v:44208.3-44236.6" + process $proc$libresoc.v:44208$2439 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$22[0:0]$2407 $1\fus_cu_issue_i$22[0:0]$2408 - attribute \src "libresoc.v:43539.5-43539.29" + assign $0\fus_cu_issue_i$29[0:0]$2440 $1\fus_cu_issue_i$29[0:0]$2441 + attribute \src "libresoc.v:44209.5-44209.29" switch \initial - attribute \src "libresoc.v:43539.9-43539.17" + attribute \src "libresoc.v:44209.9-44209.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$22[0:0]$2408 $2\fus_cu_issue_i$22[0:0]$2409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$29[0:0]$2441 $2\fus_cu_issue_i$29[0:0]$2442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$22[0:0]$2409 1'0 + assign $2\fus_cu_issue_i$29[0:0]$2442 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$22[0:0]$2409 1'0 + assign $2\fus_cu_issue_i$29[0:0]$2442 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$22[0:0]$2409 $3\fus_cu_issue_i$22[0:0]$2410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$29[0:0]$2442 $3\fus_cu_issue_i$29[0:0]$2443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$22[0:0]$2410 \issue_i + assign $3\fus_cu_issue_i$29[0:0]$2443 \issue_i case - assign $3\fus_cu_issue_i$22[0:0]$2410 1'0 + assign $3\fus_cu_issue_i$29[0:0]$2443 1'0 end end case - assign $1\fus_cu_issue_i$22[0:0]$2408 1'0 + assign $1\fus_cu_issue_i$29[0:0]$2441 1'0 end sync always - update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2407 + update \fus_cu_issue_i$29 $0\fus_cu_issue_i$29[0:0]$2440 end - attribute \src "libresoc.v:43567.3-43595.6" - process $proc$libresoc.v:43567$2411 + attribute \src "libresoc.v:44237.3-44265.6" + process $proc$libresoc.v:44237$2444 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$24[2:0]$2412 $1\fus_cu_rdmaskn_i$24[2:0]$2413 - attribute \src "libresoc.v:43568.5-43568.29" + assign $0\fus_cu_rdmaskn_i$31[2:0]$2445 $1\fus_cu_rdmaskn_i$31[2:0]$2446 + attribute \src "libresoc.v:44238.5-44238.29" switch \initial - attribute \src "libresoc.v:43568.9-43568.17" + attribute \src "libresoc.v:44238.9-44238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$24[2:0]$2413 $2\fus_cu_rdmaskn_i$24[2:0]$2414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$31[2:0]$2446 $2\fus_cu_rdmaskn_i$31[2:0]$2447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 3'000 + assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 3'000 + assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$24[2:0]$2414 $3\fus_cu_rdmaskn_i$24[2:0]$2415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 $3\fus_cu_rdmaskn_i$31[2:0]$2448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$24[2:0]$2415 \$293 + assign $3\fus_cu_rdmaskn_i$31[2:0]$2448 \$307 case - assign $3\fus_cu_rdmaskn_i$24[2:0]$2415 3'000 + assign $3\fus_cu_rdmaskn_i$31[2:0]$2448 3'000 end end case - assign $1\fus_cu_rdmaskn_i$24[2:0]$2413 3'000 + assign $1\fus_cu_rdmaskn_i$31[2:0]$2446 3'000 end sync always - update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2412 + update \fus_cu_rdmaskn_i$31 $0\fus_cu_rdmaskn_i$31[2:0]$2445 end - attribute \src "libresoc.v:43596.3-43624.6" - process $proc$libresoc.v:43596$2416 + attribute \src "libresoc.v:44266.3-44294.6" + process $proc$libresoc.v:44266$2449 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:43597.5-43597.29" + attribute \src "libresoc.v:44267.5-44267.29" switch \initial - attribute \src "libresoc.v:43597.9-43597.17" + attribute \src "libresoc.v:44267.9-44267.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76252,12 +77226,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type case assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 end @@ -76268,24 +77242,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:43625.3-43653.6" - process $proc$libresoc.v:43625$2417 + attribute \src "libresoc.v:44295.3-44323.6" + process $proc$libresoc.v:44295$2450 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:43626.5-43626.29" + attribute \src "libresoc.v:44296.5-44296.29" switch \initial - attribute \src "libresoc.v:43626.9-43626.17" + attribute \src "libresoc.v:44296.9-44296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76297,12 +77271,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit case assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 end @@ -76313,21 +77287,21 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] end - attribute \src "libresoc.v:43654.3-43683.6" - process $proc$libresoc.v:43654$2418 + attribute \src "libresoc.v:44324.3-44353.6" + process $proc$libresoc.v:44324$2451 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:43655.5-43655.29" + attribute \src "libresoc.v:44325.5-44325.29" switch \initial - attribute \src "libresoc.v:43655.9-43655.17" + attribute \src "libresoc.v:44325.9-44325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76335,7 +77309,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76351,13 +77325,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } case assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 @@ -76371,21 +77345,21 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43684.3-43713.6" - process $proc$libresoc.v:43684$2419 + attribute \src "libresoc.v:44354.3-44383.6" + process $proc$libresoc.v:44354$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:43685.5-43685.29" + attribute \src "libresoc.v:44355.5-44355.29" switch \initial - attribute \src "libresoc.v:43685.9-43685.17" + attribute \src "libresoc.v:44355.9-44355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76393,7 +77367,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76409,13 +77383,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } case assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 @@ -76429,21 +77403,21 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:43714.3-43743.6" - process $proc$libresoc.v:43714$2420 + attribute \src "libresoc.v:44384.3-44413.6" + process $proc$libresoc.v:44384$2453 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:43715.5-43715.29" + attribute \src "libresoc.v:44385.5-44385.29" switch \initial - attribute \src "libresoc.v:43715.9-43715.17" + attribute \src "libresoc.v:44385.9-44385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -76451,7 +77425,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76467,13 +77441,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } case assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 @@ -76487,24 +77461,24 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:43744.3-43772.6" - process $proc$libresoc.v:43744$2421 + attribute \src "libresoc.v:44414.3-44442.6" + process $proc$libresoc.v:44414$2454 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43745.5-43745.29" + attribute \src "libresoc.v:44415.5-44415.29" switch \initial - attribute \src "libresoc.v:43745.9-43745.17" + attribute \src "libresoc.v:44415.9-44415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76516,12 +77490,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 case assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 end @@ -76532,24 +77506,69 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:43773.3-43801.6" - process $proc$libresoc.v:43773$2422 + attribute \src "libresoc.v:44443.3-44471.6" + process $proc$libresoc.v:44443$2455 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44444.5-44444.29" + switch \initial + attribute \src "libresoc.v:44444.9-44444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in + case + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + end + attribute \src "libresoc.v:44472.3-44500.6" + process $proc$libresoc.v:44472$2456 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:43774.5-43774.29" + attribute \src "libresoc.v:44473.5-44473.29" switch \initial - attribute \src "libresoc.v:43774.9-43774.17" + attribute \src "libresoc.v:44473.9-44473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76561,12 +77580,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry case assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 end @@ -76577,24 +77596,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:43802.3-43830.6" - process $proc$libresoc.v:43802$2423 + attribute \src "libresoc.v:44501.3-44529.6" + process $proc$libresoc.v:44501$2457 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:43803.5-43803.29" + attribute \src "libresoc.v:44502.5-44502.29" switch \initial - attribute \src "libresoc.v:43803.9-43803.17" + attribute \src "libresoc.v:44502.9-44502.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76606,12 +77625,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry case assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 end @@ -76622,24 +77641,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:43831.3-43859.6" - process $proc$libresoc.v:43831$2424 + attribute \src "libresoc.v:44530.3-44558.6" + process $proc$libresoc.v:44530$2458 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:43832.5-43832.29" + attribute \src "libresoc.v:44531.5-44531.29" switch \initial - attribute \src "libresoc.v:43832.9-43832.17" + attribute \src "libresoc.v:44531.9-44531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76651,12 +77670,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr case assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 end @@ -76667,24 +77686,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:43860.3-43888.6" - process $proc$libresoc.v:43860$2425 + attribute \src "libresoc.v:44559.3-44587.6" + process $proc$libresoc.v:44559$2459 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:43861.5-43861.29" + attribute \src "libresoc.v:44560.5-44560.29" switch \initial - attribute \src "libresoc.v:43861.9-43861.17" + attribute \src "libresoc.v:44560.9-44560.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76696,12 +77715,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr case assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 end @@ -76712,24 +77731,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:43889.3-43917.6" - process $proc$libresoc.v:43889$2426 + attribute \src "libresoc.v:44588.3-44616.6" + process $proc$libresoc.v:44588$2460 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:43890.5-43890.29" + attribute \src "libresoc.v:44589.5-44589.29" switch \initial - attribute \src "libresoc.v:43890.9-43890.17" + attribute \src "libresoc.v:44589.9-44589.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76741,12 +77760,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit case assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 end @@ -76757,24 +77776,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:43918.3-43946.6" - process $proc$libresoc.v:43918$2427 + attribute \src "libresoc.v:44617.3-44645.6" + process $proc$libresoc.v:44617$2461 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:43919.5-43919.29" + attribute \src "libresoc.v:44618.5-44618.29" switch \initial - attribute \src "libresoc.v:43919.9-43919.17" + attribute \src "libresoc.v:44618.9-44618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76786,12 +77805,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed case assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 end @@ -76802,24 +77821,24 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:43947.3-43975.6" - process $proc$libresoc.v:43947$2428 + attribute \src "libresoc.v:44646.3-44674.6" + process $proc$libresoc.v:44646$2462 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:43948.5-43948.29" + attribute \src "libresoc.v:44647.5-44647.29" switch \initial - attribute \src "libresoc.v:43948.9-43948.17" + attribute \src "libresoc.v:44647.9-44647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76831,12 +77850,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn case assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 end @@ -76847,114 +77866,114 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:43976.3-44004.6" - process $proc$libresoc.v:43976$2429 + attribute \src "libresoc.v:44675.3-44703.6" + process $proc$libresoc.v:44675$2463 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$25[0:0]$2430 $1\fus_cu_issue_i$25[0:0]$2431 - attribute \src "libresoc.v:43977.5-43977.29" + assign $0\fus_cu_issue_i$32[0:0]$2464 $1\fus_cu_issue_i$32[0:0]$2465 + attribute \src "libresoc.v:44676.5-44676.29" switch \initial - attribute \src "libresoc.v:43977.9-43977.17" + attribute \src "libresoc.v:44676.9-44676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$25[0:0]$2431 $2\fus_cu_issue_i$25[0:0]$2432 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$32[0:0]$2465 $2\fus_cu_issue_i$32[0:0]$2466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$25[0:0]$2432 1'0 + assign $2\fus_cu_issue_i$32[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$25[0:0]$2432 1'0 + assign $2\fus_cu_issue_i$32[0:0]$2466 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$25[0:0]$2432 $3\fus_cu_issue_i$25[0:0]$2433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$32[0:0]$2466 $3\fus_cu_issue_i$32[0:0]$2467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$25[0:0]$2433 \issue_i + assign $3\fus_cu_issue_i$32[0:0]$2467 \issue_i case - assign $3\fus_cu_issue_i$25[0:0]$2433 1'0 + assign $3\fus_cu_issue_i$32[0:0]$2467 1'0 end end case - assign $1\fus_cu_issue_i$25[0:0]$2431 1'0 + assign $1\fus_cu_issue_i$32[0:0]$2465 1'0 end sync always - update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2430 + update \fus_cu_issue_i$32 $0\fus_cu_issue_i$32[0:0]$2464 end - attribute \src "libresoc.v:44005.3-44033.6" - process $proc$libresoc.v:44005$2434 + attribute \src "libresoc.v:44704.3-44732.6" + process $proc$libresoc.v:44704$2468 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$27[4:0]$2435 $1\fus_cu_rdmaskn_i$27[4:0]$2436 - attribute \src "libresoc.v:44006.5-44006.29" + assign $0\fus_cu_rdmaskn_i$34[4:0]$2469 $1\fus_cu_rdmaskn_i$34[4:0]$2470 + attribute \src "libresoc.v:44705.5-44705.29" switch \initial - attribute \src "libresoc.v:44006.9-44006.17" + attribute \src "libresoc.v:44705.9-44705.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$27[4:0]$2436 $2\fus_cu_rdmaskn_i$27[4:0]$2437 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$34[4:0]$2470 $2\fus_cu_rdmaskn_i$34[4:0]$2471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 5'00000 + assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 5'00000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 5'00000 + assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 5'00000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$27[4:0]$2437 $3\fus_cu_rdmaskn_i$27[4:0]$2438 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 $3\fus_cu_rdmaskn_i$34[4:0]$2472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$27[4:0]$2438 \$307 + assign $3\fus_cu_rdmaskn_i$34[4:0]$2472 \$321 case - assign $3\fus_cu_rdmaskn_i$27[4:0]$2438 5'00000 + assign $3\fus_cu_rdmaskn_i$34[4:0]$2472 5'00000 end end case - assign $1\fus_cu_rdmaskn_i$27[4:0]$2436 5'00000 + assign $1\fus_cu_rdmaskn_i$34[4:0]$2470 5'00000 end sync always - update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[4:0]$2435 + update \fus_cu_rdmaskn_i$34 $0\fus_cu_rdmaskn_i$34[4:0]$2469 end - attribute \src "libresoc.v:44034.3-44062.6" - process $proc$libresoc.v:44034$2439 + attribute \src "libresoc.v:44733.3-44761.6" + process $proc$libresoc.v:44733$2473 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44035.5-44035.29" + attribute \src "libresoc.v:44734.5-44734.29" switch \initial - attribute \src "libresoc.v:44035.9-44035.17" + attribute \src "libresoc.v:44734.9-44734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -76966,12 +77985,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST_LDST__insn_type + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type case assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 end @@ -76982,24 +78001,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:44063.3-44091.6" - process $proc$libresoc.v:44063$2440 + attribute \src "libresoc.v:44762.3-44790.6" + process $proc$libresoc.v:44762$2474 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44064.5-44064.29" + attribute \src "libresoc.v:44763.5-44763.29" switch \initial - attribute \src "libresoc.v:44064.9-44064.17" + attribute \src "libresoc.v:44763.9-44763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77011,12 +78030,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST_LDST__fn_unit + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST__fn_unit case assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 end @@ -77027,21 +78046,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] end - attribute \src "libresoc.v:44092.3-44121.6" - process $proc$libresoc.v:44092$2441 + attribute \src "libresoc.v:44791.3-44820.6" + process $proc$libresoc.v:44791$2475 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44093.5-44093.29" + attribute \src "libresoc.v:44792.5-44792.29" switch \initial - attribute \src "libresoc.v:44093.9-44093.17" + attribute \src "libresoc.v:44792.9-44792.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77049,7 +78068,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77065,13 +78084,13 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } case assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 @@ -77085,24 +78104,24 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44122.3-44150.6" - process $proc$libresoc.v:44122$2442 + attribute \src "libresoc.v:44821.3-44849.6" + process $proc$libresoc.v:44821$2476 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44123.5-44123.29" + attribute \src "libresoc.v:44822.5-44822.29" switch \initial - attribute \src "libresoc.v:44123.9-44123.17" + attribute \src "libresoc.v:44822.9-44822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77114,12 +78133,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST_LDST__zero_a + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a case assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 end @@ -77130,21 +78149,21 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:44151.3-44180.6" - process $proc$libresoc.v:44151$2443 + attribute \src "libresoc.v:44850.3-44879.6" + process $proc$libresoc.v:44850$2477 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44152.5-44152.29" + attribute \src "libresoc.v:44851.5-44851.29" switch \initial - attribute \src "libresoc.v:44152.9-44152.17" + attribute \src "libresoc.v:44851.9-44851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77152,7 +78171,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77168,13 +78187,13 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } case assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 @@ -77188,21 +78207,21 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:44181.3-44210.6" - process $proc$libresoc.v:44181$2444 + attribute \src "libresoc.v:44880.3-44909.6" + process $proc$libresoc.v:44880$2478 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44182.5-44182.29" + attribute \src "libresoc.v:44881.5-44881.29" switch \initial - attribute \src "libresoc.v:44182.9-44182.17" + attribute \src "libresoc.v:44881.9-44881.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77210,7 +78229,7 @@ module \core assign { } { } assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77226,13 +78245,13 @@ module \core assign { } { } assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } case assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 @@ -77246,24 +78265,24 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:44211.3-44239.6" - process $proc$libresoc.v:44211$2445 + attribute \src "libresoc.v:44910.3-44938.6" + process $proc$libresoc.v:44910$2479 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44212.5-44212.29" + attribute \src "libresoc.v:44911.5-44911.29" switch \initial - attribute \src "libresoc.v:44212.9-44212.17" + attribute \src "libresoc.v:44911.9-44911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77275,12 +78294,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST_LDST__is_32bit + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit case assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 end @@ -77291,24 +78310,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:44240.3-44268.6" - process $proc$libresoc.v:44240$2446 + attribute \src "libresoc.v:44939.3-44967.6" + process $proc$libresoc.v:44939$2480 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44241.5-44241.29" + attribute \src "libresoc.v:44940.5-44940.29" switch \initial - attribute \src "libresoc.v:44241.9-44241.17" + attribute \src "libresoc.v:44940.9-44940.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77320,12 +78339,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST_LDST__is_signed + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed case assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 end @@ -77336,24 +78355,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:44269.3-44297.6" - process $proc$libresoc.v:44269$2447 + attribute \src "libresoc.v:44968.3-44996.6" + process $proc$libresoc.v:44968$2481 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44270.5-44270.29" + attribute \src "libresoc.v:44969.5-44969.29" switch \initial - attribute \src "libresoc.v:44270.9-44270.17" + attribute \src "libresoc.v:44969.9-44969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77365,12 +78384,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST_LDST__data_len + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len case assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 end @@ -77381,24 +78400,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:44298.3-44326.6" - process $proc$libresoc.v:44298$2448 + attribute \src "libresoc.v:44997.3-45025.6" + process $proc$libresoc.v:44997$2482 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44299.5-44299.29" + attribute \src "libresoc.v:44998.5-44998.29" switch \initial - attribute \src "libresoc.v:44299.9-44299.17" + attribute \src "libresoc.v:44998.9-44998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77410,12 +78429,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST_LDST__byte_reverse + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse case assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 end @@ -77426,24 +78445,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:44327.3-44355.6" - process $proc$libresoc.v:44327$2449 + attribute \src "libresoc.v:45026.3-45054.6" + process $proc$libresoc.v:45026$2483 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44328.5-44328.29" + attribute \src "libresoc.v:45027.5-45027.29" switch \initial - attribute \src "libresoc.v:44328.9-44328.17" + attribute \src "libresoc.v:45027.9-45027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77455,12 +78474,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST_LDST__sign_extend + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend case assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 end @@ -77471,24 +78490,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:44356.3-44384.6" - process $proc$libresoc.v:44356$2450 + attribute \src "libresoc.v:45055.3-45083.6" + process $proc$libresoc.v:45055$2484 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44357.5-44357.29" + attribute \src "libresoc.v:45056.5-45056.29" switch \initial - attribute \src "libresoc.v:44357.9-44357.17" + attribute \src "libresoc.v:45056.9-45056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77500,12 +78519,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST_LDST__ldst_mode + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode case assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 end @@ -77516,24 +78535,24 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:44385.3-44413.6" - process $proc$libresoc.v:44385$2451 + attribute \src "libresoc.v:45084.3-45112.6" + process $proc$libresoc.v:45084$2485 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44386.5-44386.29" + attribute \src "libresoc.v:45085.5-45085.29" switch \initial - attribute \src "libresoc.v:44386.9-44386.17" + attribute \src "libresoc.v:45085.9-45085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -77545,12 +78564,12 @@ module \core case assign { } { } assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST_LDST__insn + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn case assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 end @@ -77561,104 +78580,104 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:44414.3-44442.6" - process $proc$libresoc.v:44414$2452 + attribute \src "libresoc.v:45113.3-45141.6" + process $proc$libresoc.v:45113$2486 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$28[0:0]$2453 $1\fus_cu_issue_i$28[0:0]$2454 - attribute \src "libresoc.v:44415.5-44415.29" + assign $0\fus_cu_issue_i$35[0:0]$2487 $1\fus_cu_issue_i$35[0:0]$2488 + attribute \src "libresoc.v:45114.5-45114.29" switch \initial - attribute \src "libresoc.v:44415.9-44415.17" + attribute \src "libresoc.v:45114.9-45114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$28[0:0]$2454 $2\fus_cu_issue_i$28[0:0]$2455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$35[0:0]$2488 $2\fus_cu_issue_i$35[0:0]$2489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$28[0:0]$2455 1'0 + assign $2\fus_cu_issue_i$35[0:0]$2489 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$28[0:0]$2455 1'0 + assign $2\fus_cu_issue_i$35[0:0]$2489 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$28[0:0]$2455 $3\fus_cu_issue_i$28[0:0]$2456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$35[0:0]$2489 $3\fus_cu_issue_i$35[0:0]$2490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$28[0:0]$2456 \issue_i + assign $3\fus_cu_issue_i$35[0:0]$2490 \issue_i case - assign $3\fus_cu_issue_i$28[0:0]$2456 1'0 + assign $3\fus_cu_issue_i$35[0:0]$2490 1'0 end end case - assign $1\fus_cu_issue_i$28[0:0]$2454 1'0 + assign $1\fus_cu_issue_i$35[0:0]$2488 1'0 end sync always - update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2453 + update \fus_cu_issue_i$35 $0\fus_cu_issue_i$35[0:0]$2487 end - attribute \src "libresoc.v:44443.3-44471.6" - process $proc$libresoc.v:44443$2457 + attribute \src "libresoc.v:45142.3-45170.6" + process $proc$libresoc.v:45142$2491 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$30[2:0]$2458 $1\fus_cu_rdmaskn_i$30[2:0]$2459 - attribute \src "libresoc.v:44444.5-44444.29" + assign $0\fus_cu_rdmaskn_i$37[2:0]$2492 $1\fus_cu_rdmaskn_i$37[2:0]$2493 + attribute \src "libresoc.v:45143.5-45143.29" switch \initial - attribute \src "libresoc.v:44444.9-44444.17" + attribute \src "libresoc.v:45143.9-45143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$30[2:0]$2459 $2\fus_cu_rdmaskn_i$30[2:0]$2460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$37[2:0]$2493 $2\fus_cu_rdmaskn_i$37[2:0]$2494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 3'000 + assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 3'000 + assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$30[2:0]$2460 $3\fus_cu_rdmaskn_i$30[2:0]$2461 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 $3\fus_cu_rdmaskn_i$37[2:0]$2495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$30[2:0]$2461 \$329 + assign $3\fus_cu_rdmaskn_i$37[2:0]$2495 \$343 case - assign $3\fus_cu_rdmaskn_i$30[2:0]$2461 3'000 + assign $3\fus_cu_rdmaskn_i$37[2:0]$2495 3'000 end end case - assign $1\fus_cu_rdmaskn_i$30[2:0]$2459 3'000 + assign $1\fus_cu_rdmaskn_i$37[2:0]$2493 3'000 end sync always - update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2458 + update \fus_cu_rdmaskn_i$37 $0\fus_cu_rdmaskn_i$37[2:0]$2492 end - attribute \src "libresoc.v:44472.3-44480.6" - process $proc$libresoc.v:44472$2462 + attribute \src "libresoc.v:45171.3-45179.6" + process $proc$libresoc.v:45171$2496 assign { } { } assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2463 $1\dp_INT_ra_alu0_0$next[0:0]$2464 - attribute \src "libresoc.v:44473.5-44473.29" + assign $0\dp_INT_ra_alu0_0$next[0:0]$2497 $1\dp_INT_ra_alu0_0$next[0:0]$2498 + attribute \src "libresoc.v:45172.5-45172.29" switch \initial - attribute \src "libresoc.v:44473.9-44473.17" + attribute \src "libresoc.v:45172.9-45172.17" case 1'1 case end @@ -77667,25 +78686,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2464 1'0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2498 1'0 case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2464 \rp_INT_ra_alu0_0 + assign $1\dp_INT_ra_alu0_0$next[0:0]$2498 \rp_INT_ra_alu0_0 end sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2463 + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2497 end - attribute \src "libresoc.v:44481.3-44490.6" - process $proc$libresoc.v:44481$2465 + attribute \src "libresoc.v:45180.3-45189.6" + process $proc$libresoc.v:45180$2499 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:44482.5-44482.29" + attribute \src "libresoc.v:45181.5-45181.29" switch \initial - attribute \src "libresoc.v:44482.9-44482.17" + attribute \src "libresoc.v:45181.9-45181.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -77697,14 +78716,14 @@ module \core sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:44491.3-44499.6" - process $proc$libresoc.v:44491$2466 + attribute \src "libresoc.v:45190.3-45198.6" + process $proc$libresoc.v:45190$2500 assign { } { } assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2467 $1\dp_INT_ra_cr0_1$next[0:0]$2468 - attribute \src "libresoc.v:44492.5-44492.29" + assign $0\dp_INT_ra_cr0_1$next[0:0]$2501 $1\dp_INT_ra_cr0_1$next[0:0]$2502 + attribute \src "libresoc.v:45191.5-45191.29" switch \initial - attribute \src "libresoc.v:44492.9-44492.17" + attribute \src "libresoc.v:45191.9-45191.17" case 1'1 case end @@ -77713,44 +78732,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2468 1'0 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2502 1'0 case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2468 \rp_INT_ra_cr0_1 + assign $1\dp_INT_ra_cr0_1$next[0:0]$2502 \rp_INT_ra_cr0_1 end sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2467 + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2501 end - attribute \src "libresoc.v:44500.3-44509.6" - process $proc$libresoc.v:44500$2469 + attribute \src "libresoc.v:45199.3-45208.6" + process $proc$libresoc.v:45199$2503 assign { } { } assign { } { } - assign $0\fus_src1_i$33[63:0]$2470 $1\fus_src1_i$33[63:0]$2471 - attribute \src "libresoc.v:44501.5-44501.29" + assign $0\fus_src1_i$40[63:0]$2504 $1\fus_src1_i$40[63:0]$2505 + attribute \src "libresoc.v:45200.5-45200.29" switch \initial - attribute \src "libresoc.v:44501.9-44501.17" + attribute \src "libresoc.v:45200.9-45200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$33[63:0]$2471 \int_src1__data_o + assign $1\fus_src1_i$40[63:0]$2505 \int_src1__data_o case - assign $1\fus_src1_i$33[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$40[63:0]$2505 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$33 $0\fus_src1_i$33[63:0]$2470 + update \fus_src1_i$40 $0\fus_src1_i$40[63:0]$2504 end - attribute \src "libresoc.v:44510.3-44518.6" - process $proc$libresoc.v:44510$2472 + attribute \src "libresoc.v:45209.3-45217.6" + process $proc$libresoc.v:45209$2506 assign { } { } assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2473 $1\dp_INT_ra_trap0_2$next[0:0]$2474 - attribute \src "libresoc.v:44511.5-44511.29" + assign $0\dp_INT_ra_trap0_2$next[0:0]$2507 $1\dp_INT_ra_trap0_2$next[0:0]$2508 + attribute \src "libresoc.v:45210.5-45210.29" switch \initial - attribute \src "libresoc.v:44511.9-44511.17" + attribute \src "libresoc.v:45210.9-45210.17" case 1'1 case end @@ -77759,44 +78778,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2474 1'0 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2508 1'0 case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2474 \rp_INT_ra_trap0_2 + assign $1\dp_INT_ra_trap0_2$next[0:0]$2508 \rp_INT_ra_trap0_2 end sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2473 + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2507 end - attribute \src "libresoc.v:44519.3-44528.6" - process $proc$libresoc.v:44519$2475 + attribute \src "libresoc.v:45218.3-45227.6" + process $proc$libresoc.v:45218$2509 assign { } { } assign { } { } - assign $0\fus_src1_i$36[63:0]$2476 $1\fus_src1_i$36[63:0]$2477 - attribute \src "libresoc.v:44520.5-44520.29" + assign $0\fus_src1_i$43[63:0]$2510 $1\fus_src1_i$43[63:0]$2511 + attribute \src "libresoc.v:45219.5-45219.29" switch \initial - attribute \src "libresoc.v:44520.9-44520.17" + attribute \src "libresoc.v:45219.9-45219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$36[63:0]$2477 \int_src1__data_o + assign $1\fus_src1_i$43[63:0]$2511 \int_src1__data_o case - assign $1\fus_src1_i$36[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$43[63:0]$2511 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$36 $0\fus_src1_i$36[63:0]$2476 + update \fus_src1_i$43 $0\fus_src1_i$43[63:0]$2510 end - attribute \src "libresoc.v:44529.3-44537.6" - process $proc$libresoc.v:44529$2478 + attribute \src "libresoc.v:45228.3-45236.6" + process $proc$libresoc.v:45228$2512 assign { } { } assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2479 $1\dp_INT_ra_logical0_3$next[0:0]$2480 - attribute \src "libresoc.v:44530.5-44530.29" + assign $0\dp_INT_ra_logical0_3$next[0:0]$2513 $1\dp_INT_ra_logical0_3$next[0:0]$2514 + attribute \src "libresoc.v:45229.5-45229.29" switch \initial - attribute \src "libresoc.v:44530.9-44530.17" + attribute \src "libresoc.v:45229.9-45229.17" case 1'1 case end @@ -77805,44 +78824,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2480 1'0 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2514 1'0 case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2480 \rp_INT_ra_logical0_3 + assign $1\dp_INT_ra_logical0_3$next[0:0]$2514 \rp_INT_ra_logical0_3 end sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2479 + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2513 end - attribute \src "libresoc.v:44538.3-44547.6" - process $proc$libresoc.v:44538$2481 + attribute \src "libresoc.v:45237.3-45246.6" + process $proc$libresoc.v:45237$2515 assign { } { } assign { } { } - assign $0\fus_src1_i$39[63:0]$2482 $1\fus_src1_i$39[63:0]$2483 - attribute \src "libresoc.v:44539.5-44539.29" + assign $0\fus_src1_i$46[63:0]$2516 $1\fus_src1_i$46[63:0]$2517 + attribute \src "libresoc.v:45238.5-45238.29" switch \initial - attribute \src "libresoc.v:44539.9-44539.17" + attribute \src "libresoc.v:45238.9-45238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$39[63:0]$2483 \int_src1__data_o + assign $1\fus_src1_i$46[63:0]$2517 \int_src1__data_o case - assign $1\fus_src1_i$39[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$46[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$39 $0\fus_src1_i$39[63:0]$2482 + update \fus_src1_i$46 $0\fus_src1_i$46[63:0]$2516 end - attribute \src "libresoc.v:44548.3-44556.6" - process $proc$libresoc.v:44548$2484 + attribute \src "libresoc.v:45247.3-45255.6" + process $proc$libresoc.v:45247$2518 assign { } { } assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2485 $1\dp_INT_ra_spr0_4$next[0:0]$2486 - attribute \src "libresoc.v:44549.5-44549.29" + assign $0\dp_INT_ra_spr0_4$next[0:0]$2519 $1\dp_INT_ra_spr0_4$next[0:0]$2520 + attribute \src "libresoc.v:45248.5-45248.29" switch \initial - attribute \src "libresoc.v:44549.9-44549.17" + attribute \src "libresoc.v:45248.9-45248.17" case 1'1 case end @@ -77851,44 +78870,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2486 1'0 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2520 1'0 case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2486 \rp_INT_ra_spr0_4 + assign $1\dp_INT_ra_spr0_4$next[0:0]$2520 \rp_INT_ra_spr0_4 end sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2485 + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2519 end - attribute \src "libresoc.v:44557.3-44566.6" - process $proc$libresoc.v:44557$2487 + attribute \src "libresoc.v:45256.3-45265.6" + process $proc$libresoc.v:45256$2521 assign { } { } assign { } { } - assign $0\fus_src1_i$42[63:0]$2488 $1\fus_src1_i$42[63:0]$2489 - attribute \src "libresoc.v:44558.5-44558.29" + assign $0\fus_src1_i$49[63:0]$2522 $1\fus_src1_i$49[63:0]$2523 + attribute \src "libresoc.v:45257.5-45257.29" switch \initial - attribute \src "libresoc.v:44558.9-44558.17" + attribute \src "libresoc.v:45257.9-45257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_spr0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$42[63:0]$2489 \int_src1__data_o + assign $1\fus_src1_i$49[63:0]$2523 \int_src1__data_o case - assign $1\fus_src1_i$42[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$49[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2488 + update \fus_src1_i$49 $0\fus_src1_i$49[63:0]$2522 end - attribute \src "libresoc.v:44567.3-44575.6" - process $proc$libresoc.v:44567$2490 + attribute \src "libresoc.v:45266.3-45274.6" + process $proc$libresoc.v:45266$2524 assign { } { } assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2491 $1\dp_INT_ra_div0_5$next[0:0]$2492 - attribute \src "libresoc.v:44568.5-44568.29" + assign $0\dp_INT_ra_div0_5$next[0:0]$2525 $1\dp_INT_ra_div0_5$next[0:0]$2526 + attribute \src "libresoc.v:45267.5-45267.29" switch \initial - attribute \src "libresoc.v:44568.9-44568.17" + attribute \src "libresoc.v:45267.9-45267.17" case 1'1 case end @@ -77897,44 +78916,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2492 1'0 + assign $1\dp_INT_ra_div0_5$next[0:0]$2526 1'0 case - assign $1\dp_INT_ra_div0_5$next[0:0]$2492 \rp_INT_ra_div0_5 + assign $1\dp_INT_ra_div0_5$next[0:0]$2526 \rp_INT_ra_div0_5 end sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2491 + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2525 end - attribute \src "libresoc.v:44576.3-44585.6" - process $proc$libresoc.v:44576$2493 + attribute \src "libresoc.v:45275.3-45284.6" + process $proc$libresoc.v:45275$2527 assign { } { } assign { } { } - assign $0\fus_src1_i$45[63:0]$2494 $1\fus_src1_i$45[63:0]$2495 - attribute \src "libresoc.v:44577.5-44577.29" + assign $0\fus_src1_i$52[63:0]$2528 $1\fus_src1_i$52[63:0]$2529 + attribute \src "libresoc.v:45276.5-45276.29" switch \initial - attribute \src "libresoc.v:44577.9-44577.17" + attribute \src "libresoc.v:45276.9-45276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_div0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$45[63:0]$2495 \int_src1__data_o + assign $1\fus_src1_i$52[63:0]$2529 \int_src1__data_o case - assign $1\fus_src1_i$45[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$52[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2494 + update \fus_src1_i$52 $0\fus_src1_i$52[63:0]$2528 end - attribute \src "libresoc.v:44586.3-44594.6" - process $proc$libresoc.v:44586$2496 + attribute \src "libresoc.v:45285.3-45293.6" + process $proc$libresoc.v:45285$2530 assign { } { } assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2497 $1\dp_INT_ra_mul0_6$next[0:0]$2498 - attribute \src "libresoc.v:44587.5-44587.29" + assign $0\dp_INT_ra_mul0_6$next[0:0]$2531 $1\dp_INT_ra_mul0_6$next[0:0]$2532 + attribute \src "libresoc.v:45286.5-45286.29" switch \initial - attribute \src "libresoc.v:44587.9-44587.17" + attribute \src "libresoc.v:45286.9-45286.17" case 1'1 case end @@ -77943,44 +78962,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2498 1'0 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2532 1'0 case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2498 \rp_INT_ra_mul0_6 + assign $1\dp_INT_ra_mul0_6$next[0:0]$2532 \rp_INT_ra_mul0_6 end sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2497 + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2531 end - attribute \src "libresoc.v:44595.3-44604.6" - process $proc$libresoc.v:44595$2499 + attribute \src "libresoc.v:45294.3-45303.6" + process $proc$libresoc.v:45294$2533 assign { } { } assign { } { } - assign $0\fus_src1_i$48[63:0]$2500 $1\fus_src1_i$48[63:0]$2501 - attribute \src "libresoc.v:44596.5-44596.29" + assign $0\fus_src1_i$55[63:0]$2534 $1\fus_src1_i$55[63:0]$2535 + attribute \src "libresoc.v:45295.5-45295.29" switch \initial - attribute \src "libresoc.v:44596.9-44596.17" + attribute \src "libresoc.v:45295.9-45295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_mul0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$48[63:0]$2501 \int_src1__data_o + assign $1\fus_src1_i$55[63:0]$2535 \int_src1__data_o case - assign $1\fus_src1_i$48[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$55[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2500 + update \fus_src1_i$55 $0\fus_src1_i$55[63:0]$2534 end - attribute \src "libresoc.v:44605.3-44613.6" - process $proc$libresoc.v:44605$2502 + attribute \src "libresoc.v:45304.3-45312.6" + process $proc$libresoc.v:45304$2536 assign { } { } assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 - attribute \src "libresoc.v:44606.5-44606.29" + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 + attribute \src "libresoc.v:45305.5-45305.29" switch \initial - attribute \src "libresoc.v:44606.9-44606.17" + attribute \src "libresoc.v:45305.9-45305.17" case 1'1 case end @@ -77989,44 +79008,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 1'0 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 1'0 case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2504 \rp_INT_ra_shiftrot0_7 + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 \rp_INT_ra_shiftrot0_7 end sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2503 + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 end - attribute \src "libresoc.v:44614.3-44623.6" - process $proc$libresoc.v:44614$2505 + attribute \src "libresoc.v:45313.3-45322.6" + process $proc$libresoc.v:45313$2539 assign { } { } assign { } { } - assign $0\fus_src1_i$51[63:0]$2506 $1\fus_src1_i$51[63:0]$2507 - attribute \src "libresoc.v:44615.5-44615.29" + assign $0\fus_src1_i$58[63:0]$2540 $1\fus_src1_i$58[63:0]$2541 + attribute \src "libresoc.v:45314.5-45314.29" switch \initial - attribute \src "libresoc.v:44615.9-44615.17" + attribute \src "libresoc.v:45314.9-45314.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_shiftrot0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$51[63:0]$2507 \int_src1__data_o + assign $1\fus_src1_i$58[63:0]$2541 \int_src1__data_o case - assign $1\fus_src1_i$51[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$58[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2506 + update \fus_src1_i$58 $0\fus_src1_i$58[63:0]$2540 end - attribute \src "libresoc.v:44624.3-44632.6" - process $proc$libresoc.v:44624$2508 + attribute \src "libresoc.v:45323.3-45331.6" + process $proc$libresoc.v:45323$2542 assign { } { } assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2509 $1\dp_INT_ra_ldst0_8$next[0:0]$2510 - attribute \src "libresoc.v:44625.5-44625.29" + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2543 $1\dp_INT_ra_ldst0_8$next[0:0]$2544 + attribute \src "libresoc.v:45324.5-45324.29" switch \initial - attribute \src "libresoc.v:44625.9-44625.17" + attribute \src "libresoc.v:45324.9-45324.17" case 1'1 case end @@ -78035,44 +79054,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2510 1'0 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2544 1'0 case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2510 \rp_INT_ra_ldst0_8 + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2544 \rp_INT_ra_ldst0_8 end sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2509 + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2543 end - attribute \src "libresoc.v:44633.3-44642.6" - process $proc$libresoc.v:44633$2511 + attribute \src "libresoc.v:45332.3-45341.6" + process $proc$libresoc.v:45332$2545 assign { } { } assign { } { } - assign $0\fus_src1_i$54[63:0]$2512 $1\fus_src1_i$54[63:0]$2513 - attribute \src "libresoc.v:44634.5-44634.29" + assign $0\fus_src1_i$61[63:0]$2546 $1\fus_src1_i$61[63:0]$2547 + attribute \src "libresoc.v:45333.5-45333.29" switch \initial - attribute \src "libresoc.v:44634.9-44634.17" + attribute \src "libresoc.v:45333.9-45333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_ra_ldst0_8 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$54[63:0]$2513 \int_src1__data_o + assign $1\fus_src1_i$61[63:0]$2547 \int_src1__data_o case - assign $1\fus_src1_i$54[63:0]$2513 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$61[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2512 + update \fus_src1_i$61 $0\fus_src1_i$61[63:0]$2546 end - attribute \src "libresoc.v:44643.3-44651.6" - process $proc$libresoc.v:44643$2514 + attribute \src "libresoc.v:45342.3-45350.6" + process $proc$libresoc.v:45342$2548 assign { } { } assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2515 $1\dp_INT_rb_alu0_0$next[0:0]$2516 - attribute \src "libresoc.v:44644.5-44644.29" + assign $0\dp_INT_rb_alu0_0$next[0:0]$2549 $1\dp_INT_rb_alu0_0$next[0:0]$2550 + attribute \src "libresoc.v:45343.5-45343.29" switch \initial - attribute \src "libresoc.v:44644.9-44644.17" + attribute \src "libresoc.v:45343.9-45343.17" case 1'1 case end @@ -78081,25 +79100,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2516 1'0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2550 1'0 case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2516 \rp_INT_rb_alu0_0 + assign $1\dp_INT_rb_alu0_0$next[0:0]$2550 \rp_INT_rb_alu0_0 end sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2515 + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2549 end - attribute \src "libresoc.v:44652.3-44661.6" - process $proc$libresoc.v:44652$2517 + attribute \src "libresoc.v:45351.3-45360.6" + process $proc$libresoc.v:45351$2551 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:44653.5-44653.29" + attribute \src "libresoc.v:45352.5-45352.29" switch \initial - attribute \src "libresoc.v:44653.9-44653.17" + attribute \src "libresoc.v:45352.9-45352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78111,14 +79130,14 @@ module \core sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:44662.3-44670.6" - process $proc$libresoc.v:44662$2518 + attribute \src "libresoc.v:45361.3-45369.6" + process $proc$libresoc.v:45361$2552 assign { } { } assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2519 $1\dp_INT_rb_cr0_1$next[0:0]$2520 - attribute \src "libresoc.v:44663.5-44663.29" + assign $0\dp_INT_rb_cr0_1$next[0:0]$2553 $1\dp_INT_rb_cr0_1$next[0:0]$2554 + attribute \src "libresoc.v:45362.5-45362.29" switch \initial - attribute \src "libresoc.v:44663.9-44663.17" + attribute \src "libresoc.v:45362.9-45362.17" case 1'1 case end @@ -78127,44 +79146,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2520 1'0 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2554 1'0 case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2520 \rp_INT_rb_cr0_1 + assign $1\dp_INT_rb_cr0_1$next[0:0]$2554 \rp_INT_rb_cr0_1 end sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2519 + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2553 end - attribute \src "libresoc.v:44671.3-44680.6" - process $proc$libresoc.v:44671$2521 + attribute \src "libresoc.v:45370.3-45379.6" + process $proc$libresoc.v:45370$2555 assign { } { } assign { } { } - assign $0\fus_src2_i$55[63:0]$2522 $1\fus_src2_i$55[63:0]$2523 - attribute \src "libresoc.v:44672.5-44672.29" + assign $0\fus_src2_i$62[63:0]$2556 $1\fus_src2_i$62[63:0]$2557 + attribute \src "libresoc.v:45371.5-45371.29" switch \initial - attribute \src "libresoc.v:44672.9-44672.17" + attribute \src "libresoc.v:45371.9-45371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_cr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$55[63:0]$2523 \int_src2__data_o + assign $1\fus_src2_i$62[63:0]$2557 \int_src2__data_o case - assign $1\fus_src2_i$55[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$62[63:0]$2557 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$55 $0\fus_src2_i$55[63:0]$2522 + update \fus_src2_i$62 $0\fus_src2_i$62[63:0]$2556 end - attribute \src "libresoc.v:44681.3-44689.6" - process $proc$libresoc.v:44681$2524 + attribute \src "libresoc.v:45380.3-45388.6" + process $proc$libresoc.v:45380$2558 assign { } { } assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2525 $1\dp_INT_rb_trap0_2$next[0:0]$2526 - attribute \src "libresoc.v:44682.5-44682.29" + assign $0\dp_INT_rb_trap0_2$next[0:0]$2559 $1\dp_INT_rb_trap0_2$next[0:0]$2560 + attribute \src "libresoc.v:45381.5-45381.29" switch \initial - attribute \src "libresoc.v:44682.9-44682.17" + attribute \src "libresoc.v:45381.9-45381.17" case 1'1 case end @@ -78173,44 +79192,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2526 1'0 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2560 1'0 case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2526 \rp_INT_rb_trap0_2 + assign $1\dp_INT_rb_trap0_2$next[0:0]$2560 \rp_INT_rb_trap0_2 end sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2525 + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2559 end - attribute \src "libresoc.v:44690.3-44699.6" - process $proc$libresoc.v:44690$2527 + attribute \src "libresoc.v:45389.3-45398.6" + process $proc$libresoc.v:45389$2561 assign { } { } assign { } { } - assign $0\fus_src2_i$56[63:0]$2528 $1\fus_src2_i$56[63:0]$2529 - attribute \src "libresoc.v:44691.5-44691.29" + assign $0\fus_src2_i$63[63:0]$2562 $1\fus_src2_i$63[63:0]$2563 + attribute \src "libresoc.v:45390.5-45390.29" switch \initial - attribute \src "libresoc.v:44691.9-44691.17" + attribute \src "libresoc.v:45390.9-45390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_trap0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$56[63:0]$2529 \int_src2__data_o + assign $1\fus_src2_i$63[63:0]$2563 \int_src2__data_o case - assign $1\fus_src2_i$56[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$63[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$56 $0\fus_src2_i$56[63:0]$2528 + update \fus_src2_i$63 $0\fus_src2_i$63[63:0]$2562 end - attribute \src "libresoc.v:44700.3-44708.6" - process $proc$libresoc.v:44700$2530 + attribute \src "libresoc.v:45399.3-45407.6" + process $proc$libresoc.v:45399$2564 assign { } { } assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2531 $1\dp_INT_rb_logical0_3$next[0:0]$2532 - attribute \src "libresoc.v:44701.5-44701.29" + assign $0\dp_INT_rb_logical0_3$next[0:0]$2565 $1\dp_INT_rb_logical0_3$next[0:0]$2566 + attribute \src "libresoc.v:45400.5-45400.29" switch \initial - attribute \src "libresoc.v:44701.9-44701.17" + attribute \src "libresoc.v:45400.9-45400.17" case 1'1 case end @@ -78219,44 +79238,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2532 1'0 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2566 1'0 case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2532 \rp_INT_rb_logical0_3 + assign $1\dp_INT_rb_logical0_3$next[0:0]$2566 \rp_INT_rb_logical0_3 end sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2531 + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2565 end - attribute \src "libresoc.v:44709.3-44718.6" - process $proc$libresoc.v:44709$2533 + attribute \src "libresoc.v:45408.3-45417.6" + process $proc$libresoc.v:45408$2567 assign { } { } assign { } { } - assign $0\fus_src2_i$57[63:0]$2534 $1\fus_src2_i$57[63:0]$2535 - attribute \src "libresoc.v:44710.5-44710.29" + assign $0\fus_src2_i$64[63:0]$2568 $1\fus_src2_i$64[63:0]$2569 + attribute \src "libresoc.v:45409.5-45409.29" switch \initial - attribute \src "libresoc.v:44710.9-44710.17" + attribute \src "libresoc.v:45409.9-45409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_logical0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$57[63:0]$2535 \int_src2__data_o + assign $1\fus_src2_i$64[63:0]$2569 \int_src2__data_o case - assign $1\fus_src2_i$57[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$64[63:0]$2569 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2534 + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2568 end - attribute \src "libresoc.v:44719.3-44727.6" - process $proc$libresoc.v:44719$2536 + attribute \src "libresoc.v:45418.3-45426.6" + process $proc$libresoc.v:45418$2570 assign { } { } assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2537 $1\dp_INT_rb_div0_4$next[0:0]$2538 - attribute \src "libresoc.v:44720.5-44720.29" + assign $0\dp_INT_rb_div0_4$next[0:0]$2571 $1\dp_INT_rb_div0_4$next[0:0]$2572 + attribute \src "libresoc.v:45419.5-45419.29" switch \initial - attribute \src "libresoc.v:44720.9-44720.17" + attribute \src "libresoc.v:45419.9-45419.17" case 1'1 case end @@ -78265,44 +79284,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2538 1'0 + assign $1\dp_INT_rb_div0_4$next[0:0]$2572 1'0 case - assign $1\dp_INT_rb_div0_4$next[0:0]$2538 \rp_INT_rb_div0_4 + assign $1\dp_INT_rb_div0_4$next[0:0]$2572 \rp_INT_rb_div0_4 end sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2537 + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2571 end - attribute \src "libresoc.v:44728.3-44737.6" - process $proc$libresoc.v:44728$2539 + attribute \src "libresoc.v:45427.3-45436.6" + process $proc$libresoc.v:45427$2573 assign { } { } assign { } { } - assign $0\fus_src2_i$58[63:0]$2540 $1\fus_src2_i$58[63:0]$2541 - attribute \src "libresoc.v:44729.5-44729.29" + assign $0\fus_src2_i$65[63:0]$2574 $1\fus_src2_i$65[63:0]$2575 + attribute \src "libresoc.v:45428.5-45428.29" switch \initial - attribute \src "libresoc.v:44729.9-44729.17" + attribute \src "libresoc.v:45428.9-45428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_div0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$58[63:0]$2541 \int_src2__data_o + assign $1\fus_src2_i$65[63:0]$2575 \int_src2__data_o case - assign $1\fus_src2_i$58[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$65[63:0]$2575 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$58 $0\fus_src2_i$58[63:0]$2540 + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2574 end - attribute \src "libresoc.v:44738.3-44746.6" - process $proc$libresoc.v:44738$2542 + attribute \src "libresoc.v:45437.3-45445.6" + process $proc$libresoc.v:45437$2576 assign { } { } assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2543 $1\dp_INT_rb_mul0_5$next[0:0]$2544 - attribute \src "libresoc.v:44739.5-44739.29" + assign $0\dp_INT_rb_mul0_5$next[0:0]$2577 $1\dp_INT_rb_mul0_5$next[0:0]$2578 + attribute \src "libresoc.v:45438.5-45438.29" switch \initial - attribute \src "libresoc.v:44739.9-44739.17" + attribute \src "libresoc.v:45438.9-45438.17" case 1'1 case end @@ -78311,44 +79330,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2544 1'0 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2578 1'0 case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2544 \rp_INT_rb_mul0_5 + assign $1\dp_INT_rb_mul0_5$next[0:0]$2578 \rp_INT_rb_mul0_5 end sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2543 + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2577 end - attribute \src "libresoc.v:44747.3-44756.6" - process $proc$libresoc.v:44747$2545 + attribute \src "libresoc.v:45446.3-45455.6" + process $proc$libresoc.v:45446$2579 assign { } { } assign { } { } - assign $0\fus_src2_i$59[63:0]$2546 $1\fus_src2_i$59[63:0]$2547 - attribute \src "libresoc.v:44748.5-44748.29" + assign $0\fus_src2_i$66[63:0]$2580 $1\fus_src2_i$66[63:0]$2581 + attribute \src "libresoc.v:45447.5-45447.29" switch \initial - attribute \src "libresoc.v:44748.9-44748.17" + attribute \src "libresoc.v:45447.9-45447.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_mul0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$59[63:0]$2547 \int_src2__data_o + assign $1\fus_src2_i$66[63:0]$2581 \int_src2__data_o case - assign $1\fus_src2_i$59[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$66[63:0]$2581 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$59 $0\fus_src2_i$59[63:0]$2546 + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2580 end - attribute \src "libresoc.v:44757.3-44765.6" - process $proc$libresoc.v:44757$2548 + attribute \src "libresoc.v:45456.3-45464.6" + process $proc$libresoc.v:45456$2582 assign { } { } assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 - attribute \src "libresoc.v:44758.5-44758.29" + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 + attribute \src "libresoc.v:45457.5-45457.29" switch \initial - attribute \src "libresoc.v:44758.9-44758.17" + attribute \src "libresoc.v:45457.9-45457.17" case 1'1 case end @@ -78357,44 +79376,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 1'0 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 1'0 case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2550 \rp_INT_rb_shiftrot0_6 + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 \rp_INT_rb_shiftrot0_6 end sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2549 + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 end - attribute \src "libresoc.v:44766.3-44775.6" - process $proc$libresoc.v:44766$2551 + attribute \src "libresoc.v:45465.3-45474.6" + process $proc$libresoc.v:45465$2585 assign { } { } assign { } { } - assign $0\fus_src2_i$60[63:0]$2552 $1\fus_src2_i$60[63:0]$2553 - attribute \src "libresoc.v:44767.5-44767.29" + assign $0\fus_src2_i$67[63:0]$2586 $1\fus_src2_i$67[63:0]$2587 + attribute \src "libresoc.v:45466.5-45466.29" switch \initial - attribute \src "libresoc.v:44767.9-44767.17" + attribute \src "libresoc.v:45466.9-45466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_shiftrot0_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$60[63:0]$2553 \int_src2__data_o + assign $1\fus_src2_i$67[63:0]$2587 \int_src2__data_o case - assign $1\fus_src2_i$60[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$67[63:0]$2587 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2552 + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2586 end - attribute \src "libresoc.v:44776.3-44784.6" - process $proc$libresoc.v:44776$2554 + attribute \src "libresoc.v:45475.3-45483.6" + process $proc$libresoc.v:45475$2588 assign { } { } assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2555 $1\dp_INT_rb_ldst0_7$next[0:0]$2556 - attribute \src "libresoc.v:44777.5-44777.29" + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2589 $1\dp_INT_rb_ldst0_7$next[0:0]$2590 + attribute \src "libresoc.v:45476.5-45476.29" switch \initial - attribute \src "libresoc.v:44777.9-44777.17" + attribute \src "libresoc.v:45476.9-45476.17" case 1'1 case end @@ -78403,44 +79422,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2556 1'0 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2590 1'0 case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2556 \rp_INT_rb_ldst0_7 + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2590 \rp_INT_rb_ldst0_7 end sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2555 + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2589 end - attribute \src "libresoc.v:44785.3-44794.6" - process $proc$libresoc.v:44785$2557 + attribute \src "libresoc.v:45484.3-45493.6" + process $proc$libresoc.v:45484$2591 assign { } { } assign { } { } - assign $0\fus_src2_i$61[63:0]$2558 $1\fus_src2_i$61[63:0]$2559 - attribute \src "libresoc.v:44786.5-44786.29" + assign $0\fus_src2_i$68[63:0]$2592 $1\fus_src2_i$68[63:0]$2593 + attribute \src "libresoc.v:45485.5-45485.29" switch \initial - attribute \src "libresoc.v:44786.9-44786.17" + attribute \src "libresoc.v:45485.9-45485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rb_ldst0_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$61[63:0]$2559 \int_src2__data_o + assign $1\fus_src2_i$68[63:0]$2593 \int_src2__data_o case - assign $1\fus_src2_i$61[63:0]$2559 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$68[63:0]$2593 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$61 $0\fus_src2_i$61[63:0]$2558 + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2592 end - attribute \src "libresoc.v:44795.3-44803.6" - process $proc$libresoc.v:44795$2560 + attribute \src "libresoc.v:45494.3-45502.6" + process $proc$libresoc.v:45494$2594 assign { } { } assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 - attribute \src "libresoc.v:44796.5-44796.29" + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 + attribute \src "libresoc.v:45495.5-45495.29" switch \initial - attribute \src "libresoc.v:44796.9-44796.17" + attribute \src "libresoc.v:45495.9-45495.17" case 1'1 case end @@ -78449,25 +79468,25 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 1'0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 1'0 case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2562 \rp_INT_rc_shiftrot0_0 + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 \rp_INT_rc_shiftrot0_0 end sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2561 + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 end - attribute \src "libresoc.v:44804.3-44813.6" - process $proc$libresoc.v:44804$2563 + attribute \src "libresoc.v:45503.3-45512.6" + process $proc$libresoc.v:45503$2597 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:44805.5-44805.29" + attribute \src "libresoc.v:45504.5-45504.29" switch \initial - attribute \src "libresoc.v:44805.9-44805.17" + attribute \src "libresoc.v:45504.9-45504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rc_shiftrot0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78479,14 +79498,14 @@ module \core sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:44814.3-44822.6" - process $proc$libresoc.v:44814$2564 + attribute \src "libresoc.v:45513.3-45521.6" + process $proc$libresoc.v:45513$2598 assign { } { } assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2565 $1\dp_INT_rc_ldst0_1$next[0:0]$2566 - attribute \src "libresoc.v:44815.5-44815.29" + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2599 $1\dp_INT_rc_ldst0_1$next[0:0]$2600 + attribute \src "libresoc.v:45514.5-45514.29" switch \initial - attribute \src "libresoc.v:44815.9-44815.17" + attribute \src "libresoc.v:45514.9-45514.17" case 1'1 case end @@ -78495,96 +79514,96 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2566 1'0 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2600 1'0 case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2566 \rp_INT_rc_ldst0_1 + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2600 \rp_INT_rc_ldst0_1 end sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2565 + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2599 end - attribute \src "libresoc.v:44823.3-44832.6" - process $proc$libresoc.v:44823$2567 + attribute \src "libresoc.v:45522.3-45531.6" + process $proc$libresoc.v:45522$2601 assign { } { } assign { } { } - assign $0\fus_src3_i$62[63:0]$2568 $1\fus_src3_i$62[63:0]$2569 - attribute \src "libresoc.v:44824.5-44824.29" + assign $0\fus_src3_i$69[63:0]$2602 $1\fus_src3_i$69[63:0]$2603 + attribute \src "libresoc.v:45523.5-45523.29" switch \initial - attribute \src "libresoc.v:44824.9-44824.17" + attribute \src "libresoc.v:45523.9-45523.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_INT_rc_ldst0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$62[63:0]$2569 \int_src3__data_o + assign $1\fus_src3_i$69[63:0]$2603 \int_src3__data_o case - assign $1\fus_src3_i$62[63:0]$2569 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$69[63:0]$2603 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$62 $0\fus_src3_i$62[63:0]$2568 + update \fus_src3_i$69 $0\fus_src3_i$69[63:0]$2602 end - attribute \src "libresoc.v:44833.3-44859.6" - process $proc$libresoc.v:44833$2570 + attribute \src "libresoc.v:45532.3-45558.6" + process $proc$libresoc.v:45532$2604 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\counter$next[1:0]$2571 $4\counter$next[1:0]$2575 - attribute \src "libresoc.v:44834.5-44834.29" + assign $0\counter$next[1:0]$2605 $4\counter$next[1:0]$2609 + attribute \src "libresoc.v:45533.5-45533.29" switch \initial - attribute \src "libresoc.v:44834.9-44834.17" + attribute \src "libresoc.v:45533.9-45533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - switch \$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + switch \$214 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\counter$next[1:0]$2572 \$202 [1:0] + assign $1\counter$next[1:0]$2606 \$216 [1:0] case - assign $1\counter$next[1:0]$2572 \counter + assign $1\counter$next[1:0]$2606 \counter end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\counter$next[1:0]$2573 $3\counter$next[1:0]$2574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $2\counter$next[1:0]$2607 $3\counter$next[1:0]$2608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign { } { } - assign $3\counter$next[1:0]$2574 2'10 + assign $3\counter$next[1:0]$2608 2'10 case - assign $3\counter$next[1:0]$2574 $1\counter$next[1:0]$2572 + assign $3\counter$next[1:0]$2608 $1\counter$next[1:0]$2606 end case - assign $2\counter$next[1:0]$2573 $1\counter$next[1:0]$2572 + assign $2\counter$next[1:0]$2607 $1\counter$next[1:0]$2606 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\counter$next[1:0]$2575 2'00 + assign $4\counter$next[1:0]$2609 2'00 case - assign $4\counter$next[1:0]$2575 $2\counter$next[1:0]$2573 + assign $4\counter$next[1:0]$2609 $2\counter$next[1:0]$2607 end sync always - update \counter$next $0\counter$next[1:0]$2571 + update \counter$next $0\counter$next[1:0]$2605 end - attribute \src "libresoc.v:44860.3-44868.6" - process $proc$libresoc.v:44860$2576 + attribute \src "libresoc.v:45559.3-45567.6" + process $proc$libresoc.v:45559$2610 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 - attribute \src "libresoc.v:44861.5-44861.29" + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 + attribute \src "libresoc.v:45560.5-45560.29" switch \initial - attribute \src "libresoc.v:44861.9-44861.17" + attribute \src "libresoc.v:45560.9-45560.17" case 1'1 case end @@ -78593,73 +79612,50 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 1'0 + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 1'0 case - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2578 \rp_XER_xer_so_alu0_0 + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 \rp_XER_xer_so_alu0_0 end sync always - update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2577 + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 end - attribute \src "libresoc.v:44869.3-44878.6" - process $proc$libresoc.v:44869$2579 + attribute \src "libresoc.v:45568.3-45577.6" + process $proc$libresoc.v:45568$2613 assign { } { } assign { } { } - assign $0\fus_src3_i$63[0:0]$2580 $1\fus_src3_i$63[0:0]$2581 - attribute \src "libresoc.v:44870.5-44870.29" + assign $0\fus_src3_i$70[0:0]$2614 $1\fus_src3_i$70[0:0]$2615 + attribute \src "libresoc.v:45569.5-45569.29" switch \initial - attribute \src "libresoc.v:44870.9-44870.17" + attribute \src "libresoc.v:45569.9-45569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_XER_xer_so_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$63[0:0]$2581 \xer_src1__data_o [0] + assign $1\fus_src3_i$70[0:0]$2615 \xer_src1__data_o [0] case - assign $1\fus_src3_i$63[0:0]$2581 1'0 + assign $1\fus_src3_i$70[0:0]$2615 1'0 end sync always - update \fus_src3_i$63 $0\fus_src3_i$63[0:0]$2580 + update \fus_src3_i$70 $0\fus_src3_i$70[0:0]$2614 end - attribute \src "libresoc.v:44879.3-44887.6" - process $proc$libresoc.v:44879$2582 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 - attribute \src "libresoc.v:44880.5-44880.29" - switch \initial - attribute \src "libresoc.v:44880.9-44880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 1'0 - case - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2584 \rp_XER_xer_so_logical0_1 - end - sync always - update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2583 - end - attribute \src "libresoc.v:44888.3-44978.6" - process $proc$libresoc.v:44888$2585 + attribute \src "libresoc.v:45578.3-45668.6" + process $proc$libresoc.v:45578$2616 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:44889.5-44889.29" + attribute \src "libresoc.v:45579.5-45579.29" switch \initial - attribute \src "libresoc.v:44889.9-44889.17" + attribute \src "libresoc.v:45579.9-45579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:186" - switch \$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" + switch \$219 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -78667,13 +79663,13 @@ module \core case assign $1\corebusy_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -78695,7 +79691,7 @@ module \core assign { } { } assign { } { } assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -78704,84 +79700,84 @@ module \core case assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\corebusy_o[0:0] \fus_cu_busy_o$5 + assign $5\corebusy_o[0:0] \fus_cu_busy_o$12 case assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\corebusy_o[0:0] \fus_cu_busy_o$8 + assign $6\corebusy_o[0:0] \fus_cu_busy_o$15 case assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\corebusy_o[0:0] \fus_cu_busy_o$11 + assign $7\corebusy_o[0:0] \fus_cu_busy_o$18 case assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\corebusy_o[0:0] \fus_cu_busy_o$14 + assign $8\corebusy_o[0:0] \fus_cu_busy_o$21 case assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\corebusy_o[0:0] \fus_cu_busy_o$17 + assign $9\corebusy_o[0:0] \fus_cu_busy_o$24 case assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [6] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\corebusy_o[0:0] \fus_cu_busy_o$20 + assign $10\corebusy_o[0:0] \fus_cu_busy_o$27 case assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [7] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $11\corebusy_o[0:0] \fus_cu_busy_o$23 + assign $11\corebusy_o[0:0] \fus_cu_busy_o$30 case assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [8] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $12\corebusy_o[0:0] \fus_cu_busy_o$26 + assign $12\corebusy_o[0:0] \fus_cu_busy_o$33 case assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [9] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $13\corebusy_o[0:0] \fus_cu_busy_o$29 + assign $13\corebusy_o[0:0] \fus_cu_busy_o$36 case assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] end @@ -78792,250 +79788,250 @@ module \core sync always update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:44979.3-44988.6" - process $proc$libresoc.v:44979$2586 + attribute \src "libresoc.v:45669.3-45677.6" + process $proc$libresoc.v:45669$2617 assign { } { } assign { } { } - assign $0\fus_src3_i$64[0:0]$2587 $1\fus_src3_i$64[0:0]$2588 - attribute \src "libresoc.v:44980.5-44980.29" + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 + attribute \src "libresoc.v:45670.5-45670.29" switch \initial - attribute \src "libresoc.v:44980.9-44980.17" + attribute \src "libresoc.v:45670.9-45670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$64[0:0]$2588 \xer_src1__data_o [0] + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 1'0 case - assign $1\fus_src3_i$64[0:0]$2588 1'0 + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 \rp_XER_xer_so_logical0_1 end sync always - update \fus_src3_i$64 $0\fus_src3_i$64[0:0]$2587 + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 end - attribute \src "libresoc.v:44989.3-44997.6" - process $proc$libresoc.v:44989$2589 + attribute \src "libresoc.v:45678.3-45687.6" + process $proc$libresoc.v:45678$2620 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 - attribute \src "libresoc.v:44990.5-44990.29" + assign $0\fus_src3_i$71[0:0]$2621 $1\fus_src3_i$71[0:0]$2622 + attribute \src "libresoc.v:45679.5-45679.29" switch \initial - attribute \src "libresoc.v:44990.9-44990.17" + attribute \src "libresoc.v:45679.9-45679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_logical0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 1'0 + assign $1\fus_src3_i$71[0:0]$2622 \xer_src1__data_o [0] case - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2591 \rp_XER_xer_so_spr0_2 + assign $1\fus_src3_i$71[0:0]$2622 1'0 end sync always - update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2590 + update \fus_src3_i$71 $0\fus_src3_i$71[0:0]$2621 end - attribute \src "libresoc.v:44998.3-45007.6" - process $proc$libresoc.v:44998$2592 + attribute \src "libresoc.v:45688.3-45696.6" + process $proc$libresoc.v:45688$2623 assign { } { } assign { } { } - assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:44999.5-44999.29" + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 + attribute \src "libresoc.v:45689.5-45689.29" switch \initial - attribute \src "libresoc.v:44999.9-44999.17" + attribute \src "libresoc.v:45689.9-45689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 1'0 case - assign $1\fus_src4_i[0:0] 1'0 + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 \rp_XER_xer_so_spr0_2 end sync always - update \fus_src4_i $0\fus_src4_i[0:0] + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 end - attribute \src "libresoc.v:45008.3-45016.6" - process $proc$libresoc.v:45008$2593 + attribute \src "libresoc.v:45697.3-45706.6" + process $proc$libresoc.v:45697$2626 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_div0_3$next[0:0]$2594 $1\dp_XER_xer_so_div0_3$next[0:0]$2595 - attribute \src "libresoc.v:45009.5-45009.29" + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:45698.5-45698.29" switch \initial - attribute \src "libresoc.v:45009.9-45009.17" + attribute \src "libresoc.v:45698.9-45698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2595 1'0 + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] case - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2595 \rp_XER_xer_so_div0_3 + assign $1\fus_src4_i[0:0] 1'0 end sync always - update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2594 + update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:45017.3-45037.6" - process $proc$libresoc.v:45017$2596 + attribute \src "libresoc.v:45707.3-45727.6" + process $proc$libresoc.v:45707$2627 assign { } { } assign { } { } assign { } { } - assign $0\core_terminate_o$next[0:0]$2597 $3\core_terminate_o$next[0:0]$2600 - attribute \src "libresoc.v:45018.5-45018.29" + assign $0\core_terminate_o$next[0:0]$2628 $3\core_terminate_o$next[0:0]$2631 + attribute \src "libresoc.v:45708.5-45708.29" switch \initial - attribute \src "libresoc.v:45018.9-45018.17" + attribute \src "libresoc.v:45708.9-45708.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_terminate_o$next[0:0]$2598 $2\core_terminate_o$next[0:0]$2599 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\core_terminate_o$next[0:0]$2629 $2\core_terminate_o$next[0:0]$2630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 assign { } { } - assign $2\core_terminate_o$next[0:0]$2599 1'1 + assign $2\core_terminate_o$next[0:0]$2630 1'1 case - assign $2\core_terminate_o$next[0:0]$2599 \core_terminate_o + assign $2\core_terminate_o$next[0:0]$2630 \core_terminate_o end case - assign $1\core_terminate_o$next[0:0]$2598 \core_terminate_o + assign $1\core_terminate_o$next[0:0]$2629 \core_terminate_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_terminate_o$next[0:0]$2600 1'0 + assign $3\core_terminate_o$next[0:0]$2631 1'0 case - assign $3\core_terminate_o$next[0:0]$2600 $1\core_terminate_o$next[0:0]$2598 + assign $3\core_terminate_o$next[0:0]$2631 $1\core_terminate_o$next[0:0]$2629 end sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2597 + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2628 end - attribute \src "libresoc.v:45038.3-45047.6" - process $proc$libresoc.v:45038$2601 + attribute \src "libresoc.v:45728.3-45736.6" + process $proc$libresoc.v:45728$2632 assign { } { } assign { } { } - assign $0\fus_src3_i$65[0:0]$2602 $1\fus_src3_i$65[0:0]$2603 - attribute \src "libresoc.v:45039.5-45039.29" + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2633 $1\dp_XER_xer_so_div0_3$next[0:0]$2634 + attribute \src "libresoc.v:45729.5-45729.29" switch \initial - attribute \src "libresoc.v:45039.9-45039.17" + attribute \src "libresoc.v:45729.9-45729.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$65[0:0]$2603 \xer_src1__data_o [0] + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2634 1'0 case - assign $1\fus_src3_i$65[0:0]$2603 1'0 + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2634 \rp_XER_xer_so_div0_3 end sync always - update \fus_src3_i$65 $0\fus_src3_i$65[0:0]$2602 + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2633 end - attribute \src "libresoc.v:45048.3-45056.6" - process $proc$libresoc.v:45048$2604 + attribute \src "libresoc.v:45737.3-45746.6" + process $proc$libresoc.v:45737$2635 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 - attribute \src "libresoc.v:45049.5-45049.29" + assign $0\fus_src3_i$72[0:0]$2636 $1\fus_src3_i$72[0:0]$2637 + attribute \src "libresoc.v:45738.5-45738.29" switch \initial - attribute \src "libresoc.v:45049.9-45049.17" + attribute \src "libresoc.v:45738.9-45738.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_div0_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 1'0 + assign $1\fus_src3_i$72[0:0]$2637 \xer_src1__data_o [0] case - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2606 \rp_XER_xer_so_mul0_4 + assign $1\fus_src3_i$72[0:0]$2637 1'0 end sync always - update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2605 + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2636 end - attribute \src "libresoc.v:45057.3-45066.6" - process $proc$libresoc.v:45057$2607 + attribute \src "libresoc.v:45747.3-45755.6" + process $proc$libresoc.v:45747$2638 assign { } { } assign { } { } - assign $0\fus_src3_i$66[0:0]$2608 $1\fus_src3_i$66[0:0]$2609 - attribute \src "libresoc.v:45058.5-45058.29" + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 + attribute \src "libresoc.v:45748.5-45748.29" switch \initial - attribute \src "libresoc.v:45058.9-45058.17" + attribute \src "libresoc.v:45748.9-45748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$66[0:0]$2609 \xer_src1__data_o [0] + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 1'0 case - assign $1\fus_src3_i$66[0:0]$2609 1'0 + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 \rp_XER_xer_so_mul0_4 end sync always - update \fus_src3_i$66 $0\fus_src3_i$66[0:0]$2608 + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 end - attribute \src "libresoc.v:45067.3-45075.6" - process $proc$libresoc.v:45067$2610 + attribute \src "libresoc.v:45756.3-45765.6" + process $proc$libresoc.v:45756$2641 assign { } { } assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 - attribute \src "libresoc.v:45068.5-45068.29" + assign $0\fus_src3_i$73[0:0]$2642 $1\fus_src3_i$73[0:0]$2643 + attribute \src "libresoc.v:45757.5-45757.29" switch \initial - attribute \src "libresoc.v:45068.9-45068.17" + attribute \src "libresoc.v:45757.9-45757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_mul0_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 1'0 + assign $1\fus_src3_i$73[0:0]$2643 \xer_src1__data_o [0] case - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2612 \rp_XER_xer_so_shiftrot0_5 + assign $1\fus_src3_i$73[0:0]$2643 1'0 end sync always - update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2642 end - attribute \src "libresoc.v:45076.3-45104.6" - process $proc$libresoc.v:45076$2613 + attribute \src "libresoc.v:45766.3-45794.6" + process $proc$libresoc.v:45766$2644 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45077.5-45077.29" + attribute \src "libresoc.v:45767.5-45767.29" switch \initial - attribute \src "libresoc.v:45077.9-45077.17" + attribute \src "libresoc.v:45767.9-45767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79047,12 +80043,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU_ALU__insn_type + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type case assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 end @@ -79063,93 +80059,93 @@ module \core sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:45105.3-45114.6" - process $proc$libresoc.v:45105$2614 + attribute \src "libresoc.v:45795.3-45803.6" + process $proc$libresoc.v:45795$2645 assign { } { } assign { } { } - assign $0\fus_src4_i$67[0:0]$2615 $1\fus_src4_i$67[0:0]$2616 - attribute \src "libresoc.v:45106.5-45106.29" + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 + attribute \src "libresoc.v:45796.5-45796.29" switch \initial - attribute \src "libresoc.v:45106.9-45106.17" + attribute \src "libresoc.v:45796.9-45796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$67[0:0]$2616 \xer_src1__data_o [0] + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 1'0 case - assign $1\fus_src4_i$67[0:0]$2616 1'0 + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 \rp_XER_xer_so_shiftrot0_5 end sync always - update \fus_src4_i$67 $0\fus_src4_i$67[0:0]$2615 + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 end - attribute \src "libresoc.v:45115.3-45123.6" - process $proc$libresoc.v:45115$2617 + attribute \src "libresoc.v:45804.3-45813.6" + process $proc$libresoc.v:45804$2648 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 - attribute \src "libresoc.v:45116.5-45116.29" + assign $0\fus_src4_i$74[0:0]$2649 $1\fus_src4_i$74[0:0]$2650 + attribute \src "libresoc.v:45805.5-45805.29" switch \initial - attribute \src "libresoc.v:45116.9-45116.17" + attribute \src "libresoc.v:45805.9-45805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_so_shiftrot0_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 1'0 + assign $1\fus_src4_i$74[0:0]$2650 \xer_src1__data_o [0] case - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2619 \rp_XER_xer_ca_alu0_0 + assign $1\fus_src4_i$74[0:0]$2650 1'0 end sync always - update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2618 + update \fus_src4_i$74 $0\fus_src4_i$74[0:0]$2649 end - attribute \src "libresoc.v:45124.3-45133.6" - process $proc$libresoc.v:45124$2620 + attribute \src "libresoc.v:45814.3-45822.6" + process $proc$libresoc.v:45814$2651 assign { } { } assign { } { } - assign $0\fus_src4_i$68[1:0]$2621 $1\fus_src4_i$68[1:0]$2622 - attribute \src "libresoc.v:45125.5-45125.29" + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 + attribute \src "libresoc.v:45815.5-45815.29" switch \initial - attribute \src "libresoc.v:45125.9-45125.17" + attribute \src "libresoc.v:45815.9-45815.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$68[1:0]$2622 \xer_src2__data_o + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 1'0 case - assign $1\fus_src4_i$68[1:0]$2622 2'00 + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 \rp_XER_xer_ca_alu0_0 end sync always - update \fus_src4_i$68 $0\fus_src4_i$68[1:0]$2621 + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 end - attribute \src "libresoc.v:45134.3-45162.6" - process $proc$libresoc.v:45134$2623 + attribute \src "libresoc.v:45823.3-45851.6" + process $proc$libresoc.v:45823$2654 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45135.5-45135.29" + attribute \src "libresoc.v:45824.5-45824.29" switch \initial - attribute \src "libresoc.v:45135.9-45135.17" + attribute \src "libresoc.v:45824.9-45824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79161,12 +80157,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU_ALU__fn_unit + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU__fn_unit case assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 end @@ -79177,113 +80173,113 @@ module \core sync always update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] end - attribute \src "libresoc.v:45163.3-45171.6" - process $proc$libresoc.v:45163$2624 + attribute \src "libresoc.v:45852.3-45861.6" + process $proc$libresoc.v:45852$2655 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 - attribute \src "libresoc.v:45164.5-45164.29" + assign $0\fus_src4_i$75[1:0]$2656 $1\fus_src4_i$75[1:0]$2657 + attribute \src "libresoc.v:45853.5-45853.29" switch \initial - attribute \src "libresoc.v:45164.9-45164.17" + attribute \src "libresoc.v:45853.9-45853.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_alu0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 1'0 + assign $1\fus_src4_i$75[1:0]$2657 \xer_src2__data_o case - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2626 \rp_XER_xer_ca_spr0_1 + assign $1\fus_src4_i$75[1:0]$2657 2'00 end sync always - update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2625 + update \fus_src4_i$75 $0\fus_src4_i$75[1:0]$2656 end - attribute \src "libresoc.v:45172.3-45181.6" - process $proc$libresoc.v:45172$2627 + attribute \src "libresoc.v:45862.3-45870.6" + process $proc$libresoc.v:45862$2658 assign { } { } assign { } { } - assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45173.5-45173.29" + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 + attribute \src "libresoc.v:45863.5-45863.29" switch \initial - attribute \src "libresoc.v:45173.9-45173.17" + attribute \src "libresoc.v:45863.9-45863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i[1:0] \xer_src2__data_o + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 1'0 case - assign $1\fus_src6_i[1:0] 2'00 + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 \rp_XER_xer_ca_spr0_1 end sync always - update \fus_src6_i $0\fus_src6_i[1:0] + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 end - attribute \src "libresoc.v:45182.3-45190.6" - process $proc$libresoc.v:45182$2628 + attribute \src "libresoc.v:45871.3-45880.6" + process $proc$libresoc.v:45871$2661 assign { } { } assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 - attribute \src "libresoc.v:45183.5-45183.29" + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:45872.5-45872.29" switch \initial - attribute \src "libresoc.v:45183.9-45183.17" + attribute \src "libresoc.v:45872.9-45872.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_spr0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 1'0 + assign $1\fus_src6_i[1:0] \xer_src2__data_o case - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2630 \rp_XER_xer_ca_shiftrot0_2 + assign $1\fus_src6_i[1:0] 2'00 end sync always - update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2629 + update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:45191.3-45200.6" - process $proc$libresoc.v:45191$2631 + attribute \src "libresoc.v:45881.3-45889.6" + process $proc$libresoc.v:45881$2662 assign { } { } assign { } { } - assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:45192.5-45192.29" + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 + attribute \src "libresoc.v:45882.5-45882.29" switch \initial - attribute \src "libresoc.v:45192.9-45192.17" + attribute \src "libresoc.v:45882.9-45882.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" - switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i[1:0] \xer_src2__data_o + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 1'0 case - assign $1\fus_src5_i[1:0] 2'00 + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 \rp_XER_xer_ca_shiftrot0_2 end sync always - update \fus_src5_i $0\fus_src5_i[1:0] + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 end - attribute \src "libresoc.v:45201.3-45230.6" - process $proc$libresoc.v:45201$2632 + attribute \src "libresoc.v:45890.3-45919.6" + process $proc$libresoc.v:45890$2665 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45202.5-45202.29" + attribute \src "libresoc.v:45891.5-45891.29" switch \initial - attribute \src "libresoc.v:45202.9-45202.17" + attribute \src "libresoc.v:45891.9-45891.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79291,7 +80287,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79307,13 +80303,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } case assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 @@ -79327,14 +80323,37 @@ module \core update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45231.3-45239.6" - process $proc$libresoc.v:45231$2633 + attribute \src "libresoc.v:45920.3-45929.6" + process $proc$libresoc.v:45920$2666 assign { } { } assign { } { } - assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 - attribute \src "libresoc.v:45232.5-45232.29" + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:45921.5-45921.29" switch \initial - attribute \src "libresoc.v:45232.9-45232.17" + attribute \src "libresoc.v:45921.9-45921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "libresoc.v:45930.3-45938.6" + process $proc$libresoc.v:45930$2667 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 + attribute \src "libresoc.v:45931.5-45931.29" + switch \initial + attribute \src "libresoc.v:45931.9-45931.17" case 1'1 case end @@ -79343,44 +80362,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 1'0 + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 1'0 case - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2635 \rp_XER_xer_ov_spr0_0 + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 \rp_XER_xer_ov_spr0_0 end sync always - update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2634 + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 end - attribute \src "libresoc.v:45240.3-45249.6" - process $proc$libresoc.v:45240$2636 + attribute \src "libresoc.v:45939.3-45948.6" + process $proc$libresoc.v:45939$2670 assign { } { } assign { } { } - assign $0\fus_src5_i$69[1:0]$2637 $1\fus_src5_i$69[1:0]$2638 - attribute \src "libresoc.v:45241.5-45241.29" + assign $0\fus_src5_i$76[1:0]$2671 $1\fus_src5_i$76[1:0]$2672 + attribute \src "libresoc.v:45940.5-45940.29" switch \initial - attribute \src "libresoc.v:45241.9-45241.17" + attribute \src "libresoc.v:45940.9-45940.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_XER_xer_ov_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$69[1:0]$2638 \xer_src3__data_o + assign $1\fus_src5_i$76[1:0]$2672 \xer_src3__data_o case - assign $1\fus_src5_i$69[1:0]$2638 2'00 + assign $1\fus_src5_i$76[1:0]$2672 2'00 end sync always - update \fus_src5_i$69 $0\fus_src5_i$69[1:0]$2637 + update \fus_src5_i$76 $0\fus_src5_i$76[1:0]$2671 end - attribute \src "libresoc.v:45250.3-45258.6" - process $proc$libresoc.v:45250$2639 + attribute \src "libresoc.v:45949.3-45957.6" + process $proc$libresoc.v:45949$2673 assign { } { } assign { } { } - assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 - attribute \src "libresoc.v:45251.5-45251.29" + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 + attribute \src "libresoc.v:45950.5-45950.29" switch \initial - attribute \src "libresoc.v:45251.9-45251.17" + attribute \src "libresoc.v:45950.9-45950.17" case 1'1 case end @@ -79389,51 +80408,51 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 1'0 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 1'0 case - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2641 \rp_CR_full_cr_cr0_0 + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 \rp_CR_full_cr_cr0_0 end sync always - update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2640 + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 end - attribute \src "libresoc.v:45259.3-45268.6" - process $proc$libresoc.v:45259$2642 + attribute \src "libresoc.v:45958.3-45967.6" + process $proc$libresoc.v:45958$2676 assign { } { } assign { } { } - assign $0\fus_src3_i$70[31:0]$2643 $1\fus_src3_i$70[31:0]$2644 - attribute \src "libresoc.v:45260.5-45260.29" + assign $0\fus_src3_i$77[31:0]$2677 $1\fus_src3_i$77[31:0]$2678 + attribute \src "libresoc.v:45959.5-45959.29" switch \initial - attribute \src "libresoc.v:45260.9-45260.17" + attribute \src "libresoc.v:45959.9-45959.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_CR_full_cr_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$70[31:0]$2644 \cr_full_rd__data_o + assign $1\fus_src3_i$77[31:0]$2678 \cr_full_rd__data_o case - assign $1\fus_src3_i$70[31:0]$2644 0 + assign $1\fus_src3_i$77[31:0]$2678 0 end sync always - update \fus_src3_i$70 $0\fus_src3_i$70[31:0]$2643 + update \fus_src3_i$77 $0\fus_src3_i$77[31:0]$2677 end - attribute \src "libresoc.v:45269.3-45298.6" - process $proc$libresoc.v:45269$2645 + attribute \src "libresoc.v:45968.3-45997.6" + process $proc$libresoc.v:45968$2679 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45270.5-45270.29" + attribute \src "libresoc.v:45969.5-45969.29" switch \initial - attribute \src "libresoc.v:45270.9-45270.17" + attribute \src "libresoc.v:45969.9-45969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79441,7 +80460,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79457,13 +80476,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } case assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 @@ -79477,14 +80496,14 @@ module \core update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:45299.3-45307.6" - process $proc$libresoc.v:45299$2646 + attribute \src "libresoc.v:45998.3-46006.6" + process $proc$libresoc.v:45998$2680 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 - attribute \src "libresoc.v:45300.5-45300.29" + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 + attribute \src "libresoc.v:45999.5-45999.29" switch \initial - attribute \src "libresoc.v:45300.9-45300.17" + attribute \src "libresoc.v:45999.9-45999.17" case 1'1 case end @@ -79493,44 +80512,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 1'0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 1'0 case - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2648 \rp_CR_cr_a_cr0_0 + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 \rp_CR_cr_a_cr0_0 end sync always - update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2647 + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 end - attribute \src "libresoc.v:45308.3-45317.6" - process $proc$libresoc.v:45308$2649 + attribute \src "libresoc.v:46007.3-46016.6" + process $proc$libresoc.v:46007$2683 assign { } { } assign { } { } - assign $0\fus_src4_i$71[3:0]$2650 $1\fus_src4_i$71[3:0]$2651 - attribute \src "libresoc.v:45309.5-45309.29" + assign $0\fus_src4_i$78[3:0]$2684 $1\fus_src4_i$78[3:0]$2685 + attribute \src "libresoc.v:46008.5-46008.29" switch \initial - attribute \src "libresoc.v:45309.9-45309.17" + attribute \src "libresoc.v:46008.9-46008.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_CR_cr_a_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$71[3:0]$2651 \cr_src1__data_o + assign $1\fus_src4_i$78[3:0]$2685 \cr_src1__data_o case - assign $1\fus_src4_i$71[3:0]$2651 4'0000 + assign $1\fus_src4_i$78[3:0]$2685 4'0000 end sync always - update \fus_src4_i$71 $0\fus_src4_i$71[3:0]$2650 + update \fus_src4_i$78 $0\fus_src4_i$78[3:0]$2684 end - attribute \src "libresoc.v:45318.3-45326.6" - process $proc$libresoc.v:45318$2652 + attribute \src "libresoc.v:46017.3-46025.6" + process $proc$libresoc.v:46017$2686 assign { } { } assign { } { } - assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 - attribute \src "libresoc.v:45319.5-45319.29" + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 + attribute \src "libresoc.v:46018.5-46018.29" switch \initial - attribute \src "libresoc.v:45319.9-45319.17" + attribute \src "libresoc.v:46018.9-46018.17" case 1'1 case end @@ -79539,44 +80558,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 1'0 + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 1'0 case - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2654 \rp_CR_cr_a_branch0_1 + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 \rp_CR_cr_a_branch0_1 end sync always - update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2653 + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 end - attribute \src "libresoc.v:45327.3-45336.6" - process $proc$libresoc.v:45327$2655 + attribute \src "libresoc.v:46026.3-46035.6" + process $proc$libresoc.v:46026$2689 assign { } { } assign { } { } - assign $0\fus_src3_i$74[3:0]$2656 $1\fus_src3_i$74[3:0]$2657 - attribute \src "libresoc.v:45328.5-45328.29" + assign $0\fus_src3_i$81[3:0]$2690 $1\fus_src3_i$81[3:0]$2691 + attribute \src "libresoc.v:46027.5-46027.29" switch \initial - attribute \src "libresoc.v:45328.9-45328.17" + attribute \src "libresoc.v:46027.9-46027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_CR_cr_a_branch0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$74[3:0]$2657 \cr_src1__data_o + assign $1\fus_src3_i$81[3:0]$2691 \cr_src1__data_o case - assign $1\fus_src3_i$74[3:0]$2657 4'0000 + assign $1\fus_src3_i$81[3:0]$2691 4'0000 end sync always - update \fus_src3_i$74 $0\fus_src3_i$74[3:0]$2656 + update \fus_src3_i$81 $0\fus_src3_i$81[3:0]$2690 end - attribute \src "libresoc.v:45337.3-45345.6" - process $proc$libresoc.v:45337$2658 + attribute \src "libresoc.v:46036.3-46044.6" + process $proc$libresoc.v:46036$2692 assign { } { } assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:45338.5-45338.29" + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 + attribute \src "libresoc.v:46037.5-46037.29" switch \initial - attribute \src "libresoc.v:45338.9-45338.17" + attribute \src "libresoc.v:46037.9-46037.17" case 1'1 case end @@ -79585,51 +80604,51 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 1'0 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 1'0 case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2660 \rp_CR_cr_b_cr0_0 + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 \rp_CR_cr_b_cr0_0 end sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2659 + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 end - attribute \src "libresoc.v:45346.3-45355.6" - process $proc$libresoc.v:45346$2661 + attribute \src "libresoc.v:46045.3-46054.6" + process $proc$libresoc.v:46045$2695 assign { } { } assign { } { } - assign $0\fus_src5_i$75[3:0]$2662 $1\fus_src5_i$75[3:0]$2663 - attribute \src "libresoc.v:45347.5-45347.29" + assign $0\fus_src5_i$82[3:0]$2696 $1\fus_src5_i$82[3:0]$2697 + attribute \src "libresoc.v:46046.5-46046.29" switch \initial - attribute \src "libresoc.v:45347.9-45347.17" + attribute \src "libresoc.v:46046.9-46046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_CR_cr_b_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src5_i$75[3:0]$2663 \cr_src2__data_o + assign $1\fus_src5_i$82[3:0]$2697 \cr_src2__data_o case - assign $1\fus_src5_i$75[3:0]$2663 4'0000 + assign $1\fus_src5_i$82[3:0]$2697 4'0000 end sync always - update \fus_src5_i$75 $0\fus_src5_i$75[3:0]$2662 + update \fus_src5_i$82 $0\fus_src5_i$82[3:0]$2696 end - attribute \src "libresoc.v:45356.3-45385.6" - process $proc$libresoc.v:45356$2664 + attribute \src "libresoc.v:46055.3-46084.6" + process $proc$libresoc.v:46055$2698 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:45357.5-45357.29" + attribute \src "libresoc.v:46056.5-46056.29" switch \initial - attribute \src "libresoc.v:45357.9-45357.17" + attribute \src "libresoc.v:46056.9-46056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -79637,7 +80656,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79653,13 +80672,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } case assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 @@ -79673,14 +80692,14 @@ module \core update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:45386.3-45394.6" - process $proc$libresoc.v:45386$2665 + attribute \src "libresoc.v:46085.3-46093.6" + process $proc$libresoc.v:46085$2699 assign { } { } assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:45387.5-45387.29" + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 + attribute \src "libresoc.v:46086.5-46086.29" switch \initial - attribute \src "libresoc.v:45387.9-45387.17" + attribute \src "libresoc.v:46086.9-46086.17" case 1'1 case end @@ -79689,44 +80708,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 1'0 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 1'0 case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2667 \rp_CR_cr_c_cr0_0 + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 \rp_CR_cr_c_cr0_0 end sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2666 + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 end - attribute \src "libresoc.v:45395.3-45404.6" - process $proc$libresoc.v:45395$2668 + attribute \src "libresoc.v:46094.3-46103.6" + process $proc$libresoc.v:46094$2702 assign { } { } assign { } { } - assign $0\fus_src6_i$76[3:0]$2669 $1\fus_src6_i$76[3:0]$2670 - attribute \src "libresoc.v:45396.5-45396.29" + assign $0\fus_src6_i$83[3:0]$2703 $1\fus_src6_i$83[3:0]$2704 + attribute \src "libresoc.v:46095.5-46095.29" switch \initial - attribute \src "libresoc.v:45396.9-45396.17" + attribute \src "libresoc.v:46095.9-46095.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_CR_cr_c_cr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src6_i$76[3:0]$2670 \cr_src3__data_o + assign $1\fus_src6_i$83[3:0]$2704 \cr_src3__data_o case - assign $1\fus_src6_i$76[3:0]$2670 4'0000 + assign $1\fus_src6_i$83[3:0]$2704 4'0000 end sync always - update \fus_src6_i$76 $0\fus_src6_i$76[3:0]$2669 + update \fus_src6_i$83 $0\fus_src6_i$83[3:0]$2703 end - attribute \src "libresoc.v:45405.3-45413.6" - process $proc$libresoc.v:45405$2671 + attribute \src "libresoc.v:46104.3-46112.6" + process $proc$libresoc.v:46104$2705 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 - attribute \src "libresoc.v:45406.5-45406.29" + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 + attribute \src "libresoc.v:46105.5-46105.29" switch \initial - attribute \src "libresoc.v:45406.9-45406.17" + attribute \src "libresoc.v:46105.9-46105.17" case 1'1 case end @@ -79735,44 +80754,44 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 1'0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 1'0 case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2673 \rp_FAST_fast1_branch0_0 + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 \rp_FAST_fast1_branch0_0 end sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2672 + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 end - attribute \src "libresoc.v:45414.3-45423.6" - process $proc$libresoc.v:45414$2674 + attribute \src "libresoc.v:46113.3-46122.6" + process $proc$libresoc.v:46113$2708 assign { } { } assign { } { } - assign $0\fus_src1_i$77[63:0]$2675 $1\fus_src1_i$77[63:0]$2676 - attribute \src "libresoc.v:45415.5-45415.29" + assign $0\fus_src1_i$84[63:0]$2709 $1\fus_src1_i$84[63:0]$2710 + attribute \src "libresoc.v:46114.5-46114.29" switch \initial - attribute \src "libresoc.v:45415.9-45415.17" + attribute \src "libresoc.v:46114.9-46114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_FAST_fast1_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src1_i$77[63:0]$2676 \fast_src1__data_o + assign $1\fus_src1_i$84[63:0]$2710 \fast_src1__data_o case - assign $1\fus_src1_i$77[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src1_i$84[63:0]$2710 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src1_i$77 $0\fus_src1_i$77[63:0]$2675 + update \fus_src1_i$84 $0\fus_src1_i$84[63:0]$2709 end - attribute \src "libresoc.v:45424.3-45432.6" - process $proc$libresoc.v:45424$2677 + attribute \src "libresoc.v:46123.3-46131.6" + process $proc$libresoc.v:46123$2711 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 - attribute \src "libresoc.v:45425.5-45425.29" + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 + attribute \src "libresoc.v:46124.5-46124.29" switch \initial - attribute \src "libresoc.v:45425.9-45425.17" + attribute \src "libresoc.v:46124.9-46124.17" case 1'1 case end @@ -79781,54 +80800,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 1'0 + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 1'0 case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2679 \rp_FAST_fast1_trap0_1 + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 \rp_FAST_fast1_trap0_1 end sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2678 + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 end - attribute \src "libresoc.v:45433.3-45442.6" - process $proc$libresoc.v:45433$2680 + attribute \src "libresoc.v:46132.3-46141.6" + process $proc$libresoc.v:46132$2714 assign { } { } assign { } { } - assign $0\fus_src3_i$78[63:0]$2681 $1\fus_src3_i$78[63:0]$2682 - attribute \src "libresoc.v:45434.5-45434.29" + assign $0\fus_src3_i$85[63:0]$2715 $1\fus_src3_i$85[63:0]$2716 + attribute \src "libresoc.v:46133.5-46133.29" switch \initial - attribute \src "libresoc.v:45434.9-45434.17" + attribute \src "libresoc.v:46133.9-46133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_FAST_fast1_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$78[63:0]$2682 \fast_src1__data_o + assign $1\fus_src3_i$85[63:0]$2716 \fast_src1__data_o case - assign $1\fus_src3_i$78[63:0]$2682 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src3_i$85[63:0]$2716 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src3_i$78 $0\fus_src3_i$78[63:0]$2681 + update \fus_src3_i$85 $0\fus_src3_i$85[63:0]$2715 end - attribute \src "libresoc.v:45443.3-45471.6" - process $proc$libresoc.v:45443$2683 + attribute \src "libresoc.v:46142.3-46170.6" + process $proc$libresoc.v:46142$2717 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:45444.5-45444.29" + attribute \src "libresoc.v:46143.5-46143.29" switch \initial - attribute \src "libresoc.v:45444.9-45444.17" + attribute \src "libresoc.v:46143.9-46143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79840,12 +80859,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU_ALU__invert_in + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in case assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 end @@ -79856,14 +80875,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:45472.3-45480.6" - process $proc$libresoc.v:45472$2684 + attribute \src "libresoc.v:46171.3-46179.6" + process $proc$libresoc.v:46171$2718 assign { } { } assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 - attribute \src "libresoc.v:45473.5-45473.29" + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 + attribute \src "libresoc.v:46172.5-46172.29" switch \initial - attribute \src "libresoc.v:45473.9-45473.17" + attribute \src "libresoc.v:46172.9-46172.17" case 1'1 case end @@ -79872,77 +80891,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 1'0 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 1'0 case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2686 \rp_FAST_fast1_spr0_2 + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 \rp_FAST_fast1_spr0_2 end sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2685 + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 end - attribute \src "libresoc.v:45481.3-45490.6" - process $proc$libresoc.v:45481$2687 + attribute \src "libresoc.v:46180.3-46189.6" + process $proc$libresoc.v:46180$2721 assign { } { } assign { } { } - assign $0\fus_src3_i$79[63:0]$2688 $1\fus_src3_i$79[63:0]$2689 - attribute \src "libresoc.v:45482.5-45482.29" + assign $0\fus_src3_i$86[63:0]$2722 $1\fus_src3_i$86[63:0]$2723 + attribute \src "libresoc.v:46181.5-46181.29" switch \initial - attribute \src "libresoc.v:45482.9-45482.17" + attribute \src "libresoc.v:46181.9-46181.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_FAST_fast1_spr0_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src3_i$79[63:0]$2689 \fast_src1__data_o - case - assign $1\fus_src3_i$79[63:0]$2689 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$79 $0\fus_src3_i$79[63:0]$2688 - end - attribute \src "libresoc.v:45491.3-45499.6" - process $proc$libresoc.v:45491$2690 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 - attribute \src "libresoc.v:45492.5-45492.29" - switch \initial - attribute \src "libresoc.v:45492.9-45492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 1'0 + assign $1\fus_src3_i$86[63:0]$2723 \fast_src1__data_o case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2692 \rp_FAST_fast2_branch0_0 + assign $1\fus_src3_i$86[63:0]$2723 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2691 + update \fus_src3_i$86 $0\fus_src3_i$86[63:0]$2722 end - attribute \src "libresoc.v:45500.3-45528.6" - process $proc$libresoc.v:45500$2693 + attribute \src "libresoc.v:46190.3-46218.6" + process $proc$libresoc.v:46190$2724 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:45501.5-45501.29" + attribute \src "libresoc.v:46191.5-46191.29" switch \initial - attribute \src "libresoc.v:45501.9-45501.17" + attribute \src "libresoc.v:46191.9-46191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -79954,12 +80950,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU_ALU__zero_a + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a case assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 end @@ -79970,37 +80966,60 @@ module \core sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:45529.3-45538.6" - process $proc$libresoc.v:45529$2694 + attribute \src "libresoc.v:46219.3-46227.6" + process $proc$libresoc.v:46219$2725 assign { } { } assign { } { } - assign $0\fus_src2_i$80[63:0]$2695 $1\fus_src2_i$80[63:0]$2696 - attribute \src "libresoc.v:45530.5-45530.29" + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 + attribute \src "libresoc.v:46220.5-46220.29" switch \initial - attribute \src "libresoc.v:45530.9-45530.17" + attribute \src "libresoc.v:46220.9-46220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 + end + attribute \src "libresoc.v:46228.3-46237.6" + process $proc$libresoc.v:46228$2728 + assign { } { } + assign { } { } + assign $0\fus_src2_i$87[63:0]$2729 $1\fus_src2_i$87[63:0]$2730 + attribute \src "libresoc.v:46229.5-46229.29" + switch \initial + attribute \src "libresoc.v:46229.9-46229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_FAST_fast2_branch0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$80[63:0]$2696 \fast_src2__data_o + assign $1\fus_src2_i$87[63:0]$2730 \fast_src2__data_o case - assign $1\fus_src2_i$80[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$87[63:0]$2730 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$80 $0\fus_src2_i$80[63:0]$2695 + update \fus_src2_i$87 $0\fus_src2_i$87[63:0]$2729 end - attribute \src "libresoc.v:45539.3-45547.6" - process $proc$libresoc.v:45539$2697 + attribute \src "libresoc.v:46238.3-46246.6" + process $proc$libresoc.v:46238$2731 assign { } { } assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 - attribute \src "libresoc.v:45540.5-45540.29" + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 + attribute \src "libresoc.v:46239.5-46239.29" switch \initial - attribute \src "libresoc.v:45540.9-45540.17" + attribute \src "libresoc.v:46239.9-46239.17" case 1'1 case end @@ -80009,54 +81028,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 1'0 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 1'0 case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2699 \rp_FAST_fast2_trap0_1 + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 \rp_FAST_fast2_trap0_1 end sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2698 + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 end - attribute \src "libresoc.v:45548.3-45557.6" - process $proc$libresoc.v:45548$2700 + attribute \src "libresoc.v:46247.3-46256.6" + process $proc$libresoc.v:46247$2734 assign { } { } assign { } { } - assign $0\fus_src4_i$81[63:0]$2701 $1\fus_src4_i$81[63:0]$2702 - attribute \src "libresoc.v:45549.5-45549.29" + assign $0\fus_src4_i$88[63:0]$2735 $1\fus_src4_i$88[63:0]$2736 + attribute \src "libresoc.v:46248.5-46248.29" switch \initial - attribute \src "libresoc.v:45549.9-45549.17" + attribute \src "libresoc.v:46248.9-46248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_FAST_fast2_trap0_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src4_i$81[63:0]$2702 \fast_src2__data_o + assign $1\fus_src4_i$88[63:0]$2736 \fast_src2__data_o case - assign $1\fus_src4_i$81[63:0]$2702 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src4_i$88[63:0]$2736 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src4_i$81 $0\fus_src4_i$81[63:0]$2701 + update \fus_src4_i$88 $0\fus_src4_i$88[63:0]$2735 end - attribute \src "libresoc.v:45558.3-45586.6" - process $proc$libresoc.v:45558$2703 + attribute \src "libresoc.v:46257.3-46285.6" + process $proc$libresoc.v:46257$2737 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:45559.5-45559.29" + attribute \src "libresoc.v:46258.5-46258.29" switch \initial - attribute \src "libresoc.v:45559.9-45559.17" + attribute \src "libresoc.v:46258.9-46258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80068,12 +81087,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU_ALU__invert_out + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out case assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 end @@ -80084,14 +81103,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:45587.3-45595.6" - process $proc$libresoc.v:45587$2704 + attribute \src "libresoc.v:46286.3-46294.6" + process $proc$libresoc.v:46286$2738 assign { } { } assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 - attribute \src "libresoc.v:45588.5-45588.29" + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 + attribute \src "libresoc.v:46287.5-46287.29" switch \initial - attribute \src "libresoc.v:45588.9-45588.17" + attribute \src "libresoc.v:46287.9-46287.17" case 1'1 case end @@ -80100,54 +81119,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 1'0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 1'0 case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2706 \rp_SPR_spr1_spr0_0 + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 \rp_SPR_spr1_spr0_0 end sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2705 + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 end - attribute \src "libresoc.v:45596.3-45605.6" - process $proc$libresoc.v:45596$2707 + attribute \src "libresoc.v:46295.3-46304.6" + process $proc$libresoc.v:46295$2741 assign { } { } assign { } { } - assign $0\fus_src2_i$82[63:0]$2708 $1\fus_src2_i$82[63:0]$2709 - attribute \src "libresoc.v:45597.5-45597.29" + assign $0\fus_src2_i$89[63:0]$2742 $1\fus_src2_i$89[63:0]$2743 + attribute \src "libresoc.v:46296.5-46296.29" switch \initial - attribute \src "libresoc.v:45597.9-45597.17" + attribute \src "libresoc.v:46296.9-46296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" switch \dp_SPR_spr1_spr0_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_src2_i$82[63:0]$2709 \spr_spr1__data_o + assign $1\fus_src2_i$89[63:0]$2743 \spr_spr1__data_o case - assign $1\fus_src2_i$82[63:0]$2709 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_src2_i$89[63:0]$2743 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fus_src2_i$82 $0\fus_src2_i$82[63:0]$2708 + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2742 end - attribute \src "libresoc.v:45606.3-45634.6" - process $proc$libresoc.v:45606$2710 + attribute \src "libresoc.v:46305.3-46333.6" + process $proc$libresoc.v:46305$2744 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:45607.5-45607.29" + attribute \src "libresoc.v:46306.5-46306.29" switch \initial - attribute \src "libresoc.v:45607.9-45607.17" + attribute \src "libresoc.v:46306.9-46306.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80159,12 +81178,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU_ALU__write_cr0 + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 case assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 end @@ -80175,14 +81194,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:45635.3-45643.6" - process $proc$libresoc.v:45635$2711 + attribute \src "libresoc.v:46334.3-46342.6" + process $proc$libresoc.v:46334$2745 assign { } { } assign { } { } - assign $0\wr_pick_dly$next[0:0]$2712 $1\wr_pick_dly$next[0:0]$2713 - attribute \src "libresoc.v:45636.5-45636.29" + assign $0\wr_pick_dly$next[0:0]$2746 $1\wr_pick_dly$next[0:0]$2747 + attribute \src "libresoc.v:46335.5-46335.29" switch \initial - attribute \src "libresoc.v:45636.9-45636.17" + attribute \src "libresoc.v:46335.9-46335.17" case 1'1 case end @@ -80191,54 +81210,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$next[0:0]$2713 1'0 + assign $1\wr_pick_dly$next[0:0]$2747 1'0 case - assign $1\wr_pick_dly$next[0:0]$2713 \wr_pick + assign $1\wr_pick_dly$next[0:0]$2747 \wr_pick end sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2712 + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2746 end - attribute \src "libresoc.v:45644.3-45652.6" - process $proc$libresoc.v:45644$2714 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$967$next[0:0]$2715 $1\wr_pick_dly$967$next[0:0]$2716 - attribute \src "libresoc.v:45645.5-45645.29" - switch \initial - attribute \src "libresoc.v:45645.9-45645.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$967$next[0:0]$2716 1'0 - case - assign $1\wr_pick_dly$967$next[0:0]$2716 \wr_pick$964 - end - sync always - update \wr_pick_dly$967$next $0\wr_pick_dly$967$next[0:0]$2715 - end - attribute \src "libresoc.v:45653.3-45681.6" - process $proc$libresoc.v:45653$2717 + attribute \src "libresoc.v:46343.3-46371.6" + process $proc$libresoc.v:46343$2748 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:45654.5-45654.29" + attribute \src "libresoc.v:46344.5-46344.29" switch \initial - attribute \src "libresoc.v:45654.9-45654.17" + attribute \src "libresoc.v:46344.9-46344.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80250,12 +81246,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU_ALU__input_carry + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry case assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 end @@ -80266,14 +81262,37 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:45682.3-45690.6" - process $proc$libresoc.v:45682$2718 + attribute \src "libresoc.v:46372.3-46380.6" + process $proc$libresoc.v:46372$2749 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$981$next[0:0]$2750 $1\wr_pick_dly$981$next[0:0]$2751 + attribute \src "libresoc.v:46373.5-46373.29" + switch \initial + attribute \src "libresoc.v:46373.9-46373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$981$next[0:0]$2751 1'0 + case + assign $1\wr_pick_dly$981$next[0:0]$2751 \wr_pick$978 + end + sync always + update \wr_pick_dly$981$next $0\wr_pick_dly$981$next[0:0]$2750 + end + attribute \src "libresoc.v:46381.3-46389.6" + process $proc$libresoc.v:46381$2752 assign { } { } assign { } { } - assign $0\wr_pick_dly$986$next[0:0]$2719 $1\wr_pick_dly$986$next[0:0]$2720 - attribute \src "libresoc.v:45683.5-45683.29" + assign $0\wr_pick_dly$1000$next[0:0]$2753 $1\wr_pick_dly$1000$next[0:0]$2754 + attribute \src "libresoc.v:46382.5-46382.29" switch \initial - attribute \src "libresoc.v:45683.9-45683.17" + attribute \src "libresoc.v:46382.9-46382.17" case 1'1 case end @@ -80282,31 +81301,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$986$next[0:0]$2720 1'0 + assign $1\wr_pick_dly$1000$next[0:0]$2754 1'0 case - assign $1\wr_pick_dly$986$next[0:0]$2720 \wr_pick$983 + assign $1\wr_pick_dly$1000$next[0:0]$2754 \wr_pick$997 end sync always - update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2719 + update \wr_pick_dly$1000$next $0\wr_pick_dly$1000$next[0:0]$2753 end - attribute \src "libresoc.v:45691.3-45719.6" - process $proc$libresoc.v:45691$2721 + attribute \src "libresoc.v:46390.3-46418.6" + process $proc$libresoc.v:46390$2755 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45692.5-45692.29" + attribute \src "libresoc.v:46391.5-46391.29" switch \initial - attribute \src "libresoc.v:45692.9-45692.17" + attribute \src "libresoc.v:46391.9-46391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80318,12 +81337,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU_ALU__output_carry + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry case assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 end @@ -80334,37 +81353,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:45720.3-45728.6" - process $proc$libresoc.v:45720$2722 + attribute \src "libresoc.v:46419.3-46427.6" + process $proc$libresoc.v:46419$2756 assign { } { } assign { } { } - assign $0\wr_pick_dly$1007$next[0:0]$2723 $1\wr_pick_dly$1007$next[0:0]$2724 - attribute \src "libresoc.v:45721.5-45721.29" - switch \initial - attribute \src "libresoc.v:45721.9-45721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1007$next[0:0]$2724 1'0 - case - assign $1\wr_pick_dly$1007$next[0:0]$2724 \wr_pick$1004 - end - sync always - update \wr_pick_dly$1007$next $0\wr_pick_dly$1007$next[0:0]$2723 - end - attribute \src "libresoc.v:45729.3-45737.6" - process $proc$libresoc.v:45729$2725 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1025$next[0:0]$2726 $1\wr_pick_dly$1025$next[0:0]$2727 - attribute \src "libresoc.v:45730.5-45730.29" + assign $0\wr_pick_dly$1021$next[0:0]$2757 $1\wr_pick_dly$1021$next[0:0]$2758 + attribute \src "libresoc.v:46420.5-46420.29" switch \initial - attribute \src "libresoc.v:45730.9-45730.17" + attribute \src "libresoc.v:46420.9-46420.17" case 1'1 case end @@ -80373,31 +81369,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1025$next[0:0]$2727 1'0 + assign $1\wr_pick_dly$1021$next[0:0]$2758 1'0 case - assign $1\wr_pick_dly$1025$next[0:0]$2727 \wr_pick$1022 + assign $1\wr_pick_dly$1021$next[0:0]$2758 \wr_pick$1018 end sync always - update \wr_pick_dly$1025$next $0\wr_pick_dly$1025$next[0:0]$2726 + update \wr_pick_dly$1021$next $0\wr_pick_dly$1021$next[0:0]$2757 end - attribute \src "libresoc.v:45738.3-45766.6" - process $proc$libresoc.v:45738$2728 + attribute \src "libresoc.v:46428.3-46456.6" + process $proc$libresoc.v:46428$2759 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:45739.5-45739.29" + attribute \src "libresoc.v:46429.5-46429.29" switch \initial - attribute \src "libresoc.v:45739.9-45739.17" + attribute \src "libresoc.v:46429.9-46429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80409,12 +81405,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU_ALU__is_32bit + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit case assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 end @@ -80425,14 +81421,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:45767.3-45775.6" - process $proc$libresoc.v:45767$2729 + attribute \src "libresoc.v:46457.3-46465.6" + process $proc$libresoc.v:46457$2760 assign { } { } assign { } { } - assign $0\wr_pick_dly$1047$next[0:0]$2730 $1\wr_pick_dly$1047$next[0:0]$2731 - attribute \src "libresoc.v:45768.5-45768.29" + assign $0\wr_pick_dly$1039$next[0:0]$2761 $1\wr_pick_dly$1039$next[0:0]$2762 + attribute \src "libresoc.v:46458.5-46458.29" switch \initial - attribute \src "libresoc.v:45768.9-45768.17" + attribute \src "libresoc.v:46458.9-46458.17" case 1'1 case end @@ -80441,31 +81437,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1047$next[0:0]$2731 1'0 + assign $1\wr_pick_dly$1039$next[0:0]$2762 1'0 case - assign $1\wr_pick_dly$1047$next[0:0]$2731 \wr_pick$1044 + assign $1\wr_pick_dly$1039$next[0:0]$2762 \wr_pick$1036 end sync always - update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2730 + update \wr_pick_dly$1039$next $0\wr_pick_dly$1039$next[0:0]$2761 end - attribute \src "libresoc.v:45776.3-45804.6" - process $proc$libresoc.v:45776$2732 + attribute \src "libresoc.v:46466.3-46474.6" + process $proc$libresoc.v:46466$2763 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1061$next[0:0]$2764 $1\wr_pick_dly$1061$next[0:0]$2765 + attribute \src "libresoc.v:46467.5-46467.29" + switch \initial + attribute \src "libresoc.v:46467.9-46467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1061$next[0:0]$2765 1'0 + case + assign $1\wr_pick_dly$1061$next[0:0]$2765 \wr_pick$1058 + end + sync always + update \wr_pick_dly$1061$next $0\wr_pick_dly$1061$next[0:0]$2764 + end + attribute \src "libresoc.v:46475.3-46503.6" + process $proc$libresoc.v:46475$2766 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:45777.5-45777.29" + attribute \src "libresoc.v:46476.5-46476.29" switch \initial - attribute \src "libresoc.v:45777.9-45777.17" + attribute \src "libresoc.v:46476.9-46476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80477,12 +81496,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU_ALU__is_signed + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed case assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 end @@ -80493,14 +81512,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:45805.3-45813.6" - process $proc$libresoc.v:45805$2733 + attribute \src "libresoc.v:46504.3-46512.6" + process $proc$libresoc.v:46504$2767 assign { } { } assign { } { } - assign $0\wr_pick_dly$1067$next[0:0]$2734 $1\wr_pick_dly$1067$next[0:0]$2735 - attribute \src "libresoc.v:45806.5-45806.29" + assign $0\wr_pick_dly$1081$next[0:0]$2768 $1\wr_pick_dly$1081$next[0:0]$2769 + attribute \src "libresoc.v:46505.5-46505.29" switch \initial - attribute \src "libresoc.v:45806.9-45806.17" + attribute \src "libresoc.v:46505.9-46505.17" case 1'1 case end @@ -80509,31 +81528,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1067$next[0:0]$2735 1'0 + assign $1\wr_pick_dly$1081$next[0:0]$2769 1'0 case - assign $1\wr_pick_dly$1067$next[0:0]$2735 \wr_pick$1064 + assign $1\wr_pick_dly$1081$next[0:0]$2769 \wr_pick$1078 end sync always - update \wr_pick_dly$1067$next $0\wr_pick_dly$1067$next[0:0]$2734 + update \wr_pick_dly$1081$next $0\wr_pick_dly$1081$next[0:0]$2768 end - attribute \src "libresoc.v:45814.3-45842.6" - process $proc$libresoc.v:45814$2736 + attribute \src "libresoc.v:46513.3-46541.6" + process $proc$libresoc.v:46513$2770 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45815.5-45815.29" + attribute \src "libresoc.v:46514.5-46514.29" switch \initial - attribute \src "libresoc.v:45815.9-45815.17" + attribute \src "libresoc.v:46514.9-46514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80545,12 +81564,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU_ALU__data_len + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len case assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 end @@ -80561,14 +81580,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:45843.3-45851.6" - process $proc$libresoc.v:45843$2737 + attribute \src "libresoc.v:46542.3-46550.6" + process $proc$libresoc.v:46542$2771 assign { } { } assign { } { } - assign $0\wr_pick_dly$1087$next[0:0]$2738 $1\wr_pick_dly$1087$next[0:0]$2739 - attribute \src "libresoc.v:45844.5-45844.29" + assign $0\wr_pick_dly$1101$next[0:0]$2772 $1\wr_pick_dly$1101$next[0:0]$2773 + attribute \src "libresoc.v:46543.5-46543.29" switch \initial - attribute \src "libresoc.v:45844.9-45844.17" + attribute \src "libresoc.v:46543.9-46543.17" case 1'1 case end @@ -80577,21 +81596,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1087$next[0:0]$2739 1'0 + assign $1\wr_pick_dly$1101$next[0:0]$2773 1'0 case - assign $1\wr_pick_dly$1087$next[0:0]$2739 \wr_pick$1084 + assign $1\wr_pick_dly$1101$next[0:0]$2773 \wr_pick$1098 end sync always - update \wr_pick_dly$1087$next $0\wr_pick_dly$1087$next[0:0]$2738 + update \wr_pick_dly$1101$next $0\wr_pick_dly$1101$next[0:0]$2772 end - attribute \src "libresoc.v:45852.3-45860.6" - process $proc$libresoc.v:45852$2740 + attribute \src "libresoc.v:46551.3-46559.6" + process $proc$libresoc.v:46551$2774 assign { } { } assign { } { } - assign $0\wr_pick_dly$1106$next[0:0]$2741 $1\wr_pick_dly$1106$next[0:0]$2742 - attribute \src "libresoc.v:45853.5-45853.29" + assign $0\wr_pick_dly$1120$next[0:0]$2775 $1\wr_pick_dly$1120$next[0:0]$2776 + attribute \src "libresoc.v:46552.5-46552.29" switch \initial - attribute \src "libresoc.v:45853.9-45853.17" + attribute \src "libresoc.v:46552.9-46552.17" case 1'1 case end @@ -80600,31 +81619,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1106$next[0:0]$2742 1'0 + assign $1\wr_pick_dly$1120$next[0:0]$2776 1'0 case - assign $1\wr_pick_dly$1106$next[0:0]$2742 \wr_pick$1103 + assign $1\wr_pick_dly$1120$next[0:0]$2776 \wr_pick$1117 end sync always - update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2741 + update \wr_pick_dly$1120$next $0\wr_pick_dly$1120$next[0:0]$2775 end - attribute \src "libresoc.v:45861.3-45889.6" - process $proc$libresoc.v:45861$2743 + attribute \src "libresoc.v:46560.3-46588.6" + process $proc$libresoc.v:46560$2777 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45862.5-45862.29" + attribute \src "libresoc.v:46561.5-46561.29" switch \initial - attribute \src "libresoc.v:45862.9-45862.17" + attribute \src "libresoc.v:46561.9-46561.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80636,12 +81655,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU_ALU__insn + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn case assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 end @@ -80652,14 +81671,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:45890.3-45898.6" - process $proc$libresoc.v:45890$2744 + attribute \src "libresoc.v:46589.3-46597.6" + process $proc$libresoc.v:46589$2778 assign { } { } assign { } { } - assign $0\wr_pick_dly$1124$next[0:0]$2745 $1\wr_pick_dly$1124$next[0:0]$2746 - attribute \src "libresoc.v:45891.5-45891.29" + assign $0\wr_pick_dly$1138$next[0:0]$2779 $1\wr_pick_dly$1138$next[0:0]$2780 + attribute \src "libresoc.v:46590.5-46590.29" switch \initial - attribute \src "libresoc.v:45891.9-45891.17" + attribute \src "libresoc.v:46590.9-46590.17" case 1'1 case end @@ -80668,31 +81687,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1124$next[0:0]$2746 1'0 + assign $1\wr_pick_dly$1138$next[0:0]$2780 1'0 case - assign $1\wr_pick_dly$1124$next[0:0]$2746 \wr_pick$1121 + assign $1\wr_pick_dly$1138$next[0:0]$2780 \wr_pick$1135 end sync always - update \wr_pick_dly$1124$next $0\wr_pick_dly$1124$next[0:0]$2745 + update \wr_pick_dly$1138$next $0\wr_pick_dly$1138$next[0:0]$2779 end - attribute \src "libresoc.v:45899.3-45927.6" - process $proc$libresoc.v:45899$2747 + attribute \src "libresoc.v:46598.3-46626.6" + process $proc$libresoc.v:46598$2781 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:45900.5-45900.29" + attribute \src "libresoc.v:46599.5-46599.29" switch \initial - attribute \src "libresoc.v:45900.9-45900.17" + attribute \src "libresoc.v:46599.9-46599.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80704,7 +81723,7 @@ module \core case assign { } { } assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -80720,14 +81739,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:45928.3-45936.6" - process $proc$libresoc.v:45928$2748 + attribute \src "libresoc.v:46627.3-46635.6" + process $proc$libresoc.v:46627$2782 assign { } { } assign { } { } - assign $0\wr_pick_dly$1197$next[0:0]$2749 $1\wr_pick_dly$1197$next[0:0]$2750 - attribute \src "libresoc.v:45929.5-45929.29" + assign $0\wr_pick_dly$1211$next[0:0]$2783 $1\wr_pick_dly$1211$next[0:0]$2784 + attribute \src "libresoc.v:46628.5-46628.29" switch \initial - attribute \src "libresoc.v:45929.9-45929.17" + attribute \src "libresoc.v:46628.9-46628.17" case 1'1 case end @@ -80736,31 +81755,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1197$next[0:0]$2750 1'0 + assign $1\wr_pick_dly$1211$next[0:0]$2784 1'0 case - assign $1\wr_pick_dly$1197$next[0:0]$2750 \wr_pick$1194 + assign $1\wr_pick_dly$1211$next[0:0]$2784 \wr_pick$1208 end sync always - update \wr_pick_dly$1197$next $0\wr_pick_dly$1197$next[0:0]$2749 + update \wr_pick_dly$1211$next $0\wr_pick_dly$1211$next[0:0]$2783 end - attribute \src "libresoc.v:45937.3-45965.6" - process $proc$libresoc.v:45937$2751 + attribute \src "libresoc.v:46636.3-46664.6" + process $proc$libresoc.v:46636$2785 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:45938.5-45938.29" + attribute \src "libresoc.v:46637.5-46637.29" switch \initial - attribute \src "libresoc.v:45938.9-45938.17" + attribute \src "libresoc.v:46637.9-46637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80772,12 +81791,12 @@ module \core case assign { } { } assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i[3:0] \$207 + assign $3\fus_cu_rdmaskn_i[3:0] \$221 case assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 end @@ -80788,37 +81807,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:45966.3-45974.6" - process $proc$libresoc.v:45966$2752 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1225$next[0:0]$2753 $1\wr_pick_dly$1225$next[0:0]$2754 - attribute \src "libresoc.v:45967.5-45967.29" - switch \initial - attribute \src "libresoc.v:45967.9-45967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1225$next[0:0]$2754 1'0 - case - assign $1\wr_pick_dly$1225$next[0:0]$2754 \wr_pick$1222 - end - sync always - update \wr_pick_dly$1225$next $0\wr_pick_dly$1225$next[0:0]$2753 - end - attribute \src "libresoc.v:45975.3-45983.6" - process $proc$libresoc.v:45975$2755 + attribute \src "libresoc.v:46665.3-46673.6" + process $proc$libresoc.v:46665$2786 assign { } { } assign { } { } - assign $0\wr_pick_dly$1245$next[0:0]$2756 $1\wr_pick_dly$1245$next[0:0]$2757 - attribute \src "libresoc.v:45976.5-45976.29" + assign $0\wr_pick_dly$1239$next[0:0]$2787 $1\wr_pick_dly$1239$next[0:0]$2788 + attribute \src "libresoc.v:46666.5-46666.29" switch \initial - attribute \src "libresoc.v:45976.9-45976.17" + attribute \src "libresoc.v:46666.9-46666.17" case 1'1 case end @@ -80827,31 +81823,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1245$next[0:0]$2757 1'0 + assign $1\wr_pick_dly$1239$next[0:0]$2788 1'0 case - assign $1\wr_pick_dly$1245$next[0:0]$2757 \wr_pick$1242 + assign $1\wr_pick_dly$1239$next[0:0]$2788 \wr_pick$1236 end sync always - update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2756 + update \wr_pick_dly$1239$next $0\wr_pick_dly$1239$next[0:0]$2787 end - attribute \src "libresoc.v:45984.3-46012.6" - process $proc$libresoc.v:45984$2758 + attribute \src "libresoc.v:46674.3-46702.6" + process $proc$libresoc.v:46674$2789 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:45985.5-45985.29" + attribute \src "libresoc.v:46675.5-46675.29" switch \initial - attribute \src "libresoc.v:45985.9-45985.17" + attribute \src "libresoc.v:46675.9-46675.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80863,12 +81859,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR_CR__insn_type + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type case assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 end @@ -80879,14 +81875,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:46013.3-46021.6" - process $proc$libresoc.v:46013$2759 + attribute \src "libresoc.v:46703.3-46711.6" + process $proc$libresoc.v:46703$2790 assign { } { } assign { } { } - assign $0\wr_pick_dly$1265$next[0:0]$2760 $1\wr_pick_dly$1265$next[0:0]$2761 - attribute \src "libresoc.v:46014.5-46014.29" + assign $0\wr_pick_dly$1259$next[0:0]$2791 $1\wr_pick_dly$1259$next[0:0]$2792 + attribute \src "libresoc.v:46704.5-46704.29" switch \initial - attribute \src "libresoc.v:46014.9-46014.17" + attribute \src "libresoc.v:46704.9-46704.17" case 1'1 case end @@ -80895,31 +81891,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1265$next[0:0]$2761 1'0 + assign $1\wr_pick_dly$1259$next[0:0]$2792 1'0 case - assign $1\wr_pick_dly$1265$next[0:0]$2761 \wr_pick$1262 + assign $1\wr_pick_dly$1259$next[0:0]$2792 \wr_pick$1256 end sync always - update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2760 + update \wr_pick_dly$1259$next $0\wr_pick_dly$1259$next[0:0]$2791 end - attribute \src "libresoc.v:46022.3-46050.6" - process $proc$libresoc.v:46022$2762 + attribute \src "libresoc.v:46712.3-46720.6" + process $proc$libresoc.v:46712$2793 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1279$next[0:0]$2794 $1\wr_pick_dly$1279$next[0:0]$2795 + attribute \src "libresoc.v:46713.5-46713.29" + switch \initial + attribute \src "libresoc.v:46713.9-46713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1279$next[0:0]$2795 1'0 + case + assign $1\wr_pick_dly$1279$next[0:0]$2795 \wr_pick$1276 + end + sync always + update \wr_pick_dly$1279$next $0\wr_pick_dly$1279$next[0:0]$2794 + end + attribute \src "libresoc.v:46721.3-46749.6" + process $proc$libresoc.v:46721$2796 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46023.5-46023.29" + attribute \src "libresoc.v:46722.5-46722.29" switch \initial - attribute \src "libresoc.v:46023.9-46023.17" + attribute \src "libresoc.v:46722.9-46722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -80931,12 +81950,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR_CR__fn_unit + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR__fn_unit case assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 end @@ -80947,14 +81966,14 @@ module \core sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] end - attribute \src "libresoc.v:46051.3-46059.6" - process $proc$libresoc.v:46051$2763 + attribute \src "libresoc.v:46750.3-46758.6" + process $proc$libresoc.v:46750$2797 assign { } { } assign { } { } - assign $0\wr_pick_dly$1285$next[0:0]$2764 $1\wr_pick_dly$1285$next[0:0]$2765 - attribute \src "libresoc.v:46052.5-46052.29" + assign $0\wr_pick_dly$1299$next[0:0]$2798 $1\wr_pick_dly$1299$next[0:0]$2799 + attribute \src "libresoc.v:46751.5-46751.29" switch \initial - attribute \src "libresoc.v:46052.9-46052.17" + attribute \src "libresoc.v:46751.9-46751.17" case 1'1 case end @@ -80963,21 +81982,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1285$next[0:0]$2765 1'0 + assign $1\wr_pick_dly$1299$next[0:0]$2799 1'0 case - assign $1\wr_pick_dly$1285$next[0:0]$2765 \wr_pick$1282 + assign $1\wr_pick_dly$1299$next[0:0]$2799 \wr_pick$1296 end sync always - update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2764 + update \wr_pick_dly$1299$next $0\wr_pick_dly$1299$next[0:0]$2798 end - attribute \src "libresoc.v:46060.3-46068.6" - process $proc$libresoc.v:46060$2766 + attribute \src "libresoc.v:46759.3-46767.6" + process $proc$libresoc.v:46759$2800 assign { } { } assign { } { } - assign $0\wr_pick_dly$1305$next[0:0]$2767 $1\wr_pick_dly$1305$next[0:0]$2768 - attribute \src "libresoc.v:46061.5-46061.29" + assign $0\wr_pick_dly$1319$next[0:0]$2801 $1\wr_pick_dly$1319$next[0:0]$2802 + attribute \src "libresoc.v:46760.5-46760.29" switch \initial - attribute \src "libresoc.v:46061.9-46061.17" + attribute \src "libresoc.v:46760.9-46760.17" case 1'1 case end @@ -80986,31 +82005,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1305$next[0:0]$2768 1'0 + assign $1\wr_pick_dly$1319$next[0:0]$2802 1'0 case - assign $1\wr_pick_dly$1305$next[0:0]$2768 \wr_pick$1302 + assign $1\wr_pick_dly$1319$next[0:0]$2802 \wr_pick$1316 end sync always - update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2767 + update \wr_pick_dly$1319$next $0\wr_pick_dly$1319$next[0:0]$2801 end - attribute \src "libresoc.v:46069.3-46097.6" - process $proc$libresoc.v:46069$2769 + attribute \src "libresoc.v:46768.3-46796.6" + process $proc$libresoc.v:46768$2803 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46070.5-46070.29" + attribute \src "libresoc.v:46769.5-46769.29" switch \initial - attribute \src "libresoc.v:46070.9-46070.17" + attribute \src "libresoc.v:46769.9-46769.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81022,12 +82041,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR_CR__insn + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn case assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 end @@ -81038,14 +82057,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:46098.3-46106.6" - process $proc$libresoc.v:46098$2770 + attribute \src "libresoc.v:46797.3-46805.6" + process $proc$libresoc.v:46797$2804 assign { } { } assign { } { } - assign $0\wr_pick_dly$1325$next[0:0]$2771 $1\wr_pick_dly$1325$next[0:0]$2772 - attribute \src "libresoc.v:46099.5-46099.29" + assign $0\wr_pick_dly$1339$next[0:0]$2805 $1\wr_pick_dly$1339$next[0:0]$2806 + attribute \src "libresoc.v:46798.5-46798.29" switch \initial - attribute \src "libresoc.v:46099.9-46099.17" + attribute \src "libresoc.v:46798.9-46798.17" case 1'1 case end @@ -81054,89 +82073,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1325$next[0:0]$2772 1'0 + assign $1\wr_pick_dly$1339$next[0:0]$2806 1'0 case - assign $1\wr_pick_dly$1325$next[0:0]$2772 \wr_pick$1322 + assign $1\wr_pick_dly$1339$next[0:0]$2806 \wr_pick$1336 end sync always - update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2771 + update \wr_pick_dly$1339$next $0\wr_pick_dly$1339$next[0:0]$2805 end - attribute \src "libresoc.v:46107.3-46135.6" - process $proc$libresoc.v:46107$2773 + attribute \src "libresoc.v:46806.3-46834.6" + process $proc$libresoc.v:46806$2807 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$4[0:0]$2774 $1\fus_cu_issue_i$4[0:0]$2775 - attribute \src "libresoc.v:46108.5-46108.29" + assign $0\fus_cu_issue_i$11[0:0]$2808 $1\fus_cu_issue_i$11[0:0]$2809 + attribute \src "libresoc.v:46807.5-46807.29" switch \initial - attribute \src "libresoc.v:46108.9-46108.17" + attribute \src "libresoc.v:46807.9-46807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$4[0:0]$2775 $2\fus_cu_issue_i$4[0:0]$2776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$11[0:0]$2809 $2\fus_cu_issue_i$11[0:0]$2810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$4[0:0]$2776 1'0 + assign $2\fus_cu_issue_i$11[0:0]$2810 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$4[0:0]$2776 1'0 + assign $2\fus_cu_issue_i$11[0:0]$2810 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$4[0:0]$2776 $3\fus_cu_issue_i$4[0:0]$2777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$11[0:0]$2810 $3\fus_cu_issue_i$11[0:0]$2811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$4[0:0]$2777 \issue_i + assign $3\fus_cu_issue_i$11[0:0]$2811 \issue_i case - assign $3\fus_cu_issue_i$4[0:0]$2777 1'0 + assign $3\fus_cu_issue_i$11[0:0]$2811 1'0 end end case - assign $1\fus_cu_issue_i$4[0:0]$2775 1'0 - end - sync always - update \fus_cu_issue_i$4 $0\fus_cu_issue_i$4[0:0]$2774 - end - attribute \src "libresoc.v:46136.3-46144.6" - process $proc$libresoc.v:46136$2778 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1372$next[0:0]$2779 $1\wr_pick_dly$1372$next[0:0]$2780 - attribute \src "libresoc.v:46137.5-46137.29" - switch \initial - attribute \src "libresoc.v:46137.9-46137.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1372$next[0:0]$2780 1'0 - case - assign $1\wr_pick_dly$1372$next[0:0]$2780 \wr_pick$1369 + assign $1\fus_cu_issue_i$11[0:0]$2809 1'0 end sync always - update \wr_pick_dly$1372$next $0\wr_pick_dly$1372$next[0:0]$2779 + update \fus_cu_issue_i$11 $0\fus_cu_issue_i$11[0:0]$2808 end - attribute \src "libresoc.v:46145.3-46153.6" - process $proc$libresoc.v:46145$2781 + attribute \src "libresoc.v:46835.3-46843.6" + process $proc$libresoc.v:46835$2812 assign { } { } assign { } { } - assign $0\wr_pick_dly$1388$next[0:0]$2782 $1\wr_pick_dly$1388$next[0:0]$2783 - attribute \src "libresoc.v:46146.5-46146.29" + assign $0\wr_pick_dly$1386$next[0:0]$2813 $1\wr_pick_dly$1386$next[0:0]$2814 + attribute \src "libresoc.v:46836.5-46836.29" switch \initial - attribute \src "libresoc.v:46146.9-46146.17" + attribute \src "libresoc.v:46836.9-46836.17" case 1'1 case end @@ -81145,66 +82141,89 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1388$next[0:0]$2783 1'0 + assign $1\wr_pick_dly$1386$next[0:0]$2814 1'0 case - assign $1\wr_pick_dly$1388$next[0:0]$2783 \wr_pick$1385 + assign $1\wr_pick_dly$1386$next[0:0]$2814 \wr_pick$1383 end sync always - update \wr_pick_dly$1388$next $0\wr_pick_dly$1388$next[0:0]$2782 + update \wr_pick_dly$1386$next $0\wr_pick_dly$1386$next[0:0]$2813 end - attribute \src "libresoc.v:46154.3-46182.6" - process $proc$libresoc.v:46154$2784 + attribute \src "libresoc.v:46844.3-46872.6" + process $proc$libresoc.v:46844$2815 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$6[5:0]$2785 $1\fus_cu_rdmaskn_i$6[5:0]$2786 - attribute \src "libresoc.v:46155.5-46155.29" + assign $0\fus_cu_rdmaskn_i$13[5:0]$2816 $1\fus_cu_rdmaskn_i$13[5:0]$2817 + attribute \src "libresoc.v:46845.5-46845.29" switch \initial - attribute \src "libresoc.v:46155.9-46155.17" + attribute \src "libresoc.v:46845.9-46845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$6[5:0]$2786 $2\fus_cu_rdmaskn_i$6[5:0]$2787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$13[5:0]$2817 $2\fus_cu_rdmaskn_i$13[5:0]$2818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 6'000000 + assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 6'000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 6'000000 + assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 6'000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$6[5:0]$2787 $3\fus_cu_rdmaskn_i$6[5:0]$2788 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 $3\fus_cu_rdmaskn_i$13[5:0]$2819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$6[5:0]$2788 \$229 + assign $3\fus_cu_rdmaskn_i$13[5:0]$2819 \$243 case - assign $3\fus_cu_rdmaskn_i$6[5:0]$2788 6'000000 + assign $3\fus_cu_rdmaskn_i$13[5:0]$2819 6'000000 end end case - assign $1\fus_cu_rdmaskn_i$6[5:0]$2786 6'000000 + assign $1\fus_cu_rdmaskn_i$13[5:0]$2817 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$13 $0\fus_cu_rdmaskn_i$13[5:0]$2816 + end + attribute \src "libresoc.v:46873.3-46881.6" + process $proc$libresoc.v:46873$2820 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1402$next[0:0]$2821 $1\wr_pick_dly$1402$next[0:0]$2822 + attribute \src "libresoc.v:46874.5-46874.29" + switch \initial + attribute \src "libresoc.v:46874.9-46874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1402$next[0:0]$2822 1'0 + case + assign $1\wr_pick_dly$1402$next[0:0]$2822 \wr_pick$1399 end sync always - update \fus_cu_rdmaskn_i$6 $0\fus_cu_rdmaskn_i$6[5:0]$2785 + update \wr_pick_dly$1402$next $0\wr_pick_dly$1402$next[0:0]$2821 end - attribute \src "libresoc.v:46183.3-46191.6" - process $proc$libresoc.v:46183$2789 + attribute \src "libresoc.v:46882.3-46890.6" + process $proc$libresoc.v:46882$2823 assign { } { } assign { } { } - assign $0\wr_pick_dly$1404$next[0:0]$2790 $1\wr_pick_dly$1404$next[0:0]$2791 - attribute \src "libresoc.v:46184.5-46184.29" + assign $0\wr_pick_dly$1418$next[0:0]$2824 $1\wr_pick_dly$1418$next[0:0]$2825 + attribute \src "libresoc.v:46883.5-46883.29" switch \initial - attribute \src "libresoc.v:46184.9-46184.17" + attribute \src "libresoc.v:46883.9-46883.17" case 1'1 case end @@ -81213,31 +82232,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1404$next[0:0]$2791 1'0 + assign $1\wr_pick_dly$1418$next[0:0]$2825 1'0 case - assign $1\wr_pick_dly$1404$next[0:0]$2791 \wr_pick$1401 + assign $1\wr_pick_dly$1418$next[0:0]$2825 \wr_pick$1415 end sync always - update \wr_pick_dly$1404$next $0\wr_pick_dly$1404$next[0:0]$2790 + update \wr_pick_dly$1418$next $0\wr_pick_dly$1418$next[0:0]$2824 end - attribute \src "libresoc.v:46192.3-46220.6" - process $proc$libresoc.v:46192$2792 + attribute \src "libresoc.v:46891.3-46919.6" + process $proc$libresoc.v:46891$2826 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46193.5-46193.29" + attribute \src "libresoc.v:46892.5-46892.29" switch \initial - attribute \src "libresoc.v:46193.9-46193.17" + attribute \src "libresoc.v:46892.9-46892.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81249,12 +82268,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH_BRANCH__cia + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia case assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end @@ -81265,37 +82284,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:46221.3-46229.6" - process $proc$libresoc.v:46221$2793 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1438$next[0:0]$2794 $1\wr_pick_dly$1438$next[0:0]$2795 - attribute \src "libresoc.v:46222.5-46222.29" - switch \initial - attribute \src "libresoc.v:46222.9-46222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1438$next[0:0]$2795 1'0 - case - assign $1\wr_pick_dly$1438$next[0:0]$2795 \wr_pick$1435 - end - sync always - update \wr_pick_dly$1438$next $0\wr_pick_dly$1438$next[0:0]$2794 - end - attribute \src "libresoc.v:46230.3-46238.6" - process $proc$libresoc.v:46230$2796 + attribute \src "libresoc.v:46920.3-46928.6" + process $proc$libresoc.v:46920$2827 assign { } { } assign { } { } - assign $0\wr_pick_dly$1454$next[0:0]$2797 $1\wr_pick_dly$1454$next[0:0]$2798 - attribute \src "libresoc.v:46231.5-46231.29" + assign $0\wr_pick_dly$1452$next[0:0]$2828 $1\wr_pick_dly$1452$next[0:0]$2829 + attribute \src "libresoc.v:46921.5-46921.29" switch \initial - attribute \src "libresoc.v:46231.9-46231.17" + attribute \src "libresoc.v:46921.9-46921.17" case 1'1 case end @@ -81304,31 +82300,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1454$next[0:0]$2798 1'0 + assign $1\wr_pick_dly$1452$next[0:0]$2829 1'0 case - assign $1\wr_pick_dly$1454$next[0:0]$2798 \wr_pick$1451 + assign $1\wr_pick_dly$1452$next[0:0]$2829 \wr_pick$1449 end sync always - update \wr_pick_dly$1454$next $0\wr_pick_dly$1454$next[0:0]$2797 + update \wr_pick_dly$1452$next $0\wr_pick_dly$1452$next[0:0]$2828 end - attribute \src "libresoc.v:46239.3-46267.6" - process $proc$libresoc.v:46239$2799 + attribute \src "libresoc.v:46929.3-46957.6" + process $proc$libresoc.v:46929$2830 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46240.5-46240.29" + attribute \src "libresoc.v:46930.5-46930.29" switch \initial - attribute \src "libresoc.v:46240.9-46240.17" + attribute \src "libresoc.v:46930.9-46930.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81340,12 +82336,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH_BRANCH__insn_type + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type case assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 end @@ -81356,14 +82352,37 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:46268.3-46276.6" - process $proc$libresoc.v:46268$2800 + attribute \src "libresoc.v:46958.3-46966.6" + process $proc$libresoc.v:46958$2831 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1468$next[0:0]$2832 $1\wr_pick_dly$1468$next[0:0]$2833 + attribute \src "libresoc.v:46959.5-46959.29" + switch \initial + attribute \src "libresoc.v:46959.9-46959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1468$next[0:0]$2833 1'0 + case + assign $1\wr_pick_dly$1468$next[0:0]$2833 \wr_pick$1465 + end + sync always + update \wr_pick_dly$1468$next $0\wr_pick_dly$1468$next[0:0]$2832 + end + attribute \src "libresoc.v:46967.3-46975.6" + process $proc$libresoc.v:46967$2834 assign { } { } assign { } { } - assign $0\wr_pick_dly$1470$next[0:0]$2801 $1\wr_pick_dly$1470$next[0:0]$2802 - attribute \src "libresoc.v:46269.5-46269.29" + assign $0\wr_pick_dly$1484$next[0:0]$2835 $1\wr_pick_dly$1484$next[0:0]$2836 + attribute \src "libresoc.v:46968.5-46968.29" switch \initial - attribute \src "libresoc.v:46269.9-46269.17" + attribute \src "libresoc.v:46968.9-46968.17" case 1'1 case end @@ -81372,31 +82391,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1470$next[0:0]$2802 1'0 + assign $1\wr_pick_dly$1484$next[0:0]$2836 1'0 case - assign $1\wr_pick_dly$1470$next[0:0]$2802 \wr_pick$1467 + assign $1\wr_pick_dly$1484$next[0:0]$2836 \wr_pick$1481 end sync always - update \wr_pick_dly$1470$next $0\wr_pick_dly$1470$next[0:0]$2801 + update \wr_pick_dly$1484$next $0\wr_pick_dly$1484$next[0:0]$2835 end - attribute \src "libresoc.v:46277.3-46305.6" - process $proc$libresoc.v:46277$2803 + attribute \src "libresoc.v:46976.3-47004.6" + process $proc$libresoc.v:46976$2837 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46278.5-46278.29" + attribute \src "libresoc.v:46977.5-46977.29" switch \initial - attribute \src "libresoc.v:46278.9-46278.17" + attribute \src "libresoc.v:46977.9-46977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81408,12 +82427,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH_BRANCH__fn_unit + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH__fn_unit case assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 end @@ -81424,14 +82443,14 @@ module \core sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] end - attribute \src "libresoc.v:46306.3-46314.6" - process $proc$libresoc.v:46306$2804 + attribute \src "libresoc.v:47005.3-47013.6" + process $proc$libresoc.v:47005$2838 assign { } { } assign { } { } - assign $0\wr_pick_dly$1486$next[0:0]$2805 $1\wr_pick_dly$1486$next[0:0]$2806 - attribute \src "libresoc.v:46307.5-46307.29" + assign $0\wr_pick_dly$1500$next[0:0]$2839 $1\wr_pick_dly$1500$next[0:0]$2840 + attribute \src "libresoc.v:47006.5-47006.29" switch \initial - attribute \src "libresoc.v:46307.9-46307.17" + attribute \src "libresoc.v:47006.9-47006.17" case 1'1 case end @@ -81440,31 +82459,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1486$next[0:0]$2806 1'0 + assign $1\wr_pick_dly$1500$next[0:0]$2840 1'0 case - assign $1\wr_pick_dly$1486$next[0:0]$2806 \wr_pick$1483 + assign $1\wr_pick_dly$1500$next[0:0]$2840 \wr_pick$1497 end sync always - update \wr_pick_dly$1486$next $0\wr_pick_dly$1486$next[0:0]$2805 + update \wr_pick_dly$1500$next $0\wr_pick_dly$1500$next[0:0]$2839 end - attribute \src "libresoc.v:46315.3-46343.6" - process $proc$libresoc.v:46315$2807 + attribute \src "libresoc.v:47014.3-47042.6" + process $proc$libresoc.v:47014$2841 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46316.5-46316.29" + attribute \src "libresoc.v:47015.5-47015.29" switch \initial - attribute \src "libresoc.v:46316.9-46316.17" + attribute \src "libresoc.v:47015.9-47015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81476,12 +82495,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH_BRANCH__insn + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn case assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 end @@ -81492,14 +82511,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:46344.3-46352.6" - process $proc$libresoc.v:46344$2808 + attribute \src "libresoc.v:47043.3-47051.6" + process $proc$libresoc.v:47043$2842 assign { } { } assign { } { } - assign $0\wr_pick_dly$1522$next[0:0]$2809 $1\wr_pick_dly$1522$next[0:0]$2810 - attribute \src "libresoc.v:46345.5-46345.29" + assign $0\wr_pick_dly$1536$next[0:0]$2843 $1\wr_pick_dly$1536$next[0:0]$2844 + attribute \src "libresoc.v:47044.5-47044.29" switch \initial - attribute \src "libresoc.v:46345.9-46345.17" + attribute \src "libresoc.v:47044.9-47044.17" case 1'1 case end @@ -81508,21 +82527,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1522$next[0:0]$2810 1'0 + assign $1\wr_pick_dly$1536$next[0:0]$2844 1'0 case - assign $1\wr_pick_dly$1522$next[0:0]$2810 \wr_pick$1519 + assign $1\wr_pick_dly$1536$next[0:0]$2844 \wr_pick$1533 end sync always - update \wr_pick_dly$1522$next $0\wr_pick_dly$1522$next[0:0]$2809 + update \wr_pick_dly$1536$next $0\wr_pick_dly$1536$next[0:0]$2843 end - attribute \src "libresoc.v:46353.3-46361.6" - process $proc$libresoc.v:46353$2811 + attribute \src "libresoc.v:47052.3-47060.6" + process $proc$libresoc.v:47052$2845 assign { } { } assign { } { } - assign $0\wr_pick_dly$1538$next[0:0]$2812 $1\wr_pick_dly$1538$next[0:0]$2813 - attribute \src "libresoc.v:46354.5-46354.29" + assign $0\wr_pick_dly$1552$next[0:0]$2846 $1\wr_pick_dly$1552$next[0:0]$2847 + attribute \src "libresoc.v:47053.5-47053.29" switch \initial - attribute \src "libresoc.v:46354.9-46354.17" + attribute \src "libresoc.v:47053.9-47053.17" case 1'1 case end @@ -81531,28 +82550,28 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1538$next[0:0]$2813 1'0 + assign $1\wr_pick_dly$1552$next[0:0]$2847 1'0 case - assign $1\wr_pick_dly$1538$next[0:0]$2813 \wr_pick$1535 + assign $1\wr_pick_dly$1552$next[0:0]$2847 \wr_pick$1549 end sync always - update \wr_pick_dly$1538$next $0\wr_pick_dly$1538$next[0:0]$2812 + update \wr_pick_dly$1552$next $0\wr_pick_dly$1552$next[0:0]$2846 end - attribute \src "libresoc.v:46362.3-46391.6" - process $proc$libresoc.v:46362$2814 + attribute \src "libresoc.v:47061.3-47090.6" + process $proc$libresoc.v:47061$2848 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:46363.5-46363.29" + attribute \src "libresoc.v:47062.5-47062.29" switch \initial - attribute \src "libresoc.v:46363.9-46363.17" + attribute \src "libresoc.v:47062.9-47062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -81560,7 +82579,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81576,13 +82595,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } case assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 @@ -81596,14 +82615,14 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46392.3-46400.6" - process $proc$libresoc.v:46392$2815 + attribute \src "libresoc.v:47091.3-47099.6" + process $proc$libresoc.v:47091$2849 assign { } { } assign { } { } - assign $0\wr_pick_dly$1554$next[0:0]$2816 $1\wr_pick_dly$1554$next[0:0]$2817 - attribute \src "libresoc.v:46393.5-46393.29" + assign $0\wr_pick_dly$1568$next[0:0]$2850 $1\wr_pick_dly$1568$next[0:0]$2851 + attribute \src "libresoc.v:47092.5-47092.29" switch \initial - attribute \src "libresoc.v:46393.9-46393.17" + attribute \src "libresoc.v:47092.9-47092.17" case 1'1 case end @@ -81612,21 +82631,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1554$next[0:0]$2817 1'0 + assign $1\wr_pick_dly$1568$next[0:0]$2851 1'0 case - assign $1\wr_pick_dly$1554$next[0:0]$2817 \wr_pick$1551 + assign $1\wr_pick_dly$1568$next[0:0]$2851 \wr_pick$1565 end sync always - update \wr_pick_dly$1554$next $0\wr_pick_dly$1554$next[0:0]$2816 + update \wr_pick_dly$1568$next $0\wr_pick_dly$1568$next[0:0]$2850 end - attribute \src "libresoc.v:46401.3-46409.6" - process $proc$libresoc.v:46401$2818 + attribute \src "libresoc.v:47100.3-47108.6" + process $proc$libresoc.v:47100$2852 assign { } { } assign { } { } - assign $0\wr_pick_dly$1570$next[0:0]$2819 $1\wr_pick_dly$1570$next[0:0]$2820 - attribute \src "libresoc.v:46402.5-46402.29" + assign $0\wr_pick_dly$1584$next[0:0]$2853 $1\wr_pick_dly$1584$next[0:0]$2854 + attribute \src "libresoc.v:47101.5-47101.29" switch \initial - attribute \src "libresoc.v:46402.9-46402.17" + attribute \src "libresoc.v:47101.9-47101.17" case 1'1 case end @@ -81635,21 +82654,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1570$next[0:0]$2820 1'0 + assign $1\wr_pick_dly$1584$next[0:0]$2854 1'0 case - assign $1\wr_pick_dly$1570$next[0:0]$2820 \wr_pick$1567 + assign $1\wr_pick_dly$1584$next[0:0]$2854 \wr_pick$1581 end sync always - update \wr_pick_dly$1570$next $0\wr_pick_dly$1570$next[0:0]$2819 + update \wr_pick_dly$1584$next $0\wr_pick_dly$1584$next[0:0]$2853 end - attribute \src "libresoc.v:46410.3-46418.6" - process $proc$libresoc.v:46410$2821 + attribute \src "libresoc.v:47109.3-47117.6" + process $proc$libresoc.v:47109$2855 assign { } { } assign { } { } - assign $0\wr_pick_dly$1612$next[0:0]$2822 $1\wr_pick_dly$1612$next[0:0]$2823 - attribute \src "libresoc.v:46411.5-46411.29" + assign $0\wr_pick_dly$1626$next[0:0]$2856 $1\wr_pick_dly$1626$next[0:0]$2857 + attribute \src "libresoc.v:47110.5-47110.29" switch \initial - attribute \src "libresoc.v:46411.9-46411.17" + attribute \src "libresoc.v:47110.9-47110.17" case 1'1 case end @@ -81658,31 +82677,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1612$next[0:0]$2823 1'0 + assign $1\wr_pick_dly$1626$next[0:0]$2857 1'0 case - assign $1\wr_pick_dly$1612$next[0:0]$2823 \wr_pick$1609 + assign $1\wr_pick_dly$1626$next[0:0]$2857 \wr_pick$1623 end sync always - update \wr_pick_dly$1612$next $0\wr_pick_dly$1612$next[0:0]$2822 + update \wr_pick_dly$1626$next $0\wr_pick_dly$1626$next[0:0]$2856 end - attribute \src "libresoc.v:46419.3-46447.6" - process $proc$libresoc.v:46419$2824 + attribute \src "libresoc.v:47118.3-47146.6" + process $proc$libresoc.v:47118$2858 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46420.5-46420.29" + attribute \src "libresoc.v:47119.5-47119.29" switch \initial - attribute \src "libresoc.v:46420.9-46420.17" + attribute \src "libresoc.v:47119.9-47119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81694,12 +82713,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH_BRANCH__lk + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk case assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 end @@ -81710,14 +82729,14 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:46448.3-46456.6" - process $proc$libresoc.v:46448$2825 + attribute \src "libresoc.v:47147.3-47155.6" + process $proc$libresoc.v:47147$2859 assign { } { } assign { } { } - assign $0\wr_pick_dly$1631$next[0:0]$2826 $1\wr_pick_dly$1631$next[0:0]$2827 - attribute \src "libresoc.v:46449.5-46449.29" + assign $0\wr_pick_dly$1645$next[0:0]$2860 $1\wr_pick_dly$1645$next[0:0]$2861 + attribute \src "libresoc.v:47148.5-47148.29" switch \initial - attribute \src "libresoc.v:46449.9-46449.17" + attribute \src "libresoc.v:47148.9-47148.17" case 1'1 case end @@ -81726,31 +82745,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1631$next[0:0]$2827 1'0 + assign $1\wr_pick_dly$1645$next[0:0]$2861 1'0 case - assign $1\wr_pick_dly$1631$next[0:0]$2827 \wr_pick$1628 + assign $1\wr_pick_dly$1645$next[0:0]$2861 \wr_pick$1642 end sync always - update \wr_pick_dly$1631$next $0\wr_pick_dly$1631$next[0:0]$2826 + update \wr_pick_dly$1645$next $0\wr_pick_dly$1645$next[0:0]$2860 end - attribute \src "libresoc.v:46457.3-46485.6" - process $proc$libresoc.v:46457$2828 + attribute \src "libresoc.v:47156.3-47184.6" + process $proc$libresoc.v:47156$2862 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:46458.5-46458.29" + attribute \src "libresoc.v:47157.5-47157.29" switch \initial - attribute \src "libresoc.v:46458.9-46458.17" + attribute \src "libresoc.v:47157.9-47157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -81762,12 +82781,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH_BRANCH__is_32bit + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit case assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 end @@ -81778,14 +82797,14 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:46486.3-46494.6" - process $proc$libresoc.v:46486$2829 + attribute \src "libresoc.v:47185.3-47193.6" + process $proc$libresoc.v:47185$2863 assign { } { } assign { } { } - assign $0\wr_pick_dly$1647$next[0:0]$2830 $1\wr_pick_dly$1647$next[0:0]$2831 - attribute \src "libresoc.v:46487.5-46487.29" + assign $0\wr_pick_dly$1661$next[0:0]$2864 $1\wr_pick_dly$1661$next[0:0]$2865 + attribute \src "libresoc.v:47186.5-47186.29" switch \initial - attribute \src "libresoc.v:46487.9-46487.17" + attribute \src "libresoc.v:47186.9-47186.17" case 1'1 case end @@ -81794,21 +82813,21 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1647$next[0:0]$2831 1'0 + assign $1\wr_pick_dly$1661$next[0:0]$2865 1'0 case - assign $1\wr_pick_dly$1647$next[0:0]$2831 \wr_pick$1644 + assign $1\wr_pick_dly$1661$next[0:0]$2865 \wr_pick$1658 end sync always - update \wr_pick_dly$1647$next $0\wr_pick_dly$1647$next[0:0]$2830 + update \wr_pick_dly$1661$next $0\wr_pick_dly$1661$next[0:0]$2864 end - attribute \src "libresoc.v:46495.3-46503.6" - process $proc$libresoc.v:46495$2832 + attribute \src "libresoc.v:47194.3-47202.6" + process $proc$libresoc.v:47194$2866 assign { } { } assign { } { } - assign $0\wr_pick_dly$1663$next[0:0]$2833 $1\wr_pick_dly$1663$next[0:0]$2834 - attribute \src "libresoc.v:46496.5-46496.29" + assign $0\wr_pick_dly$1677$next[0:0]$2867 $1\wr_pick_dly$1677$next[0:0]$2868 + attribute \src "libresoc.v:47195.5-47195.29" switch \initial - attribute \src "libresoc.v:46496.9-46496.17" + attribute \src "libresoc.v:47195.9-47195.17" case 1'1 case end @@ -81817,66 +82836,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1663$next[0:0]$2834 1'0 + assign $1\wr_pick_dly$1677$next[0:0]$2868 1'0 case - assign $1\wr_pick_dly$1663$next[0:0]$2834 \wr_pick$1660 + assign $1\wr_pick_dly$1677$next[0:0]$2868 \wr_pick$1674 end sync always - update \wr_pick_dly$1663$next $0\wr_pick_dly$1663$next[0:0]$2833 + update \wr_pick_dly$1677$next $0\wr_pick_dly$1677$next[0:0]$2867 end - attribute \src "libresoc.v:46504.3-46532.6" - process $proc$libresoc.v:46504$2835 + attribute \src "libresoc.v:47203.3-47231.6" + process $proc$libresoc.v:47203$2869 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$7[0:0]$2836 $1\fus_cu_issue_i$7[0:0]$2837 - attribute \src "libresoc.v:46505.5-46505.29" + assign $0\fus_cu_issue_i$14[0:0]$2870 $1\fus_cu_issue_i$14[0:0]$2871 + attribute \src "libresoc.v:47204.5-47204.29" switch \initial - attribute \src "libresoc.v:46505.9-46505.17" + attribute \src "libresoc.v:47204.9-47204.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$7[0:0]$2837 $2\fus_cu_issue_i$7[0:0]$2838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$14[0:0]$2871 $2\fus_cu_issue_i$14[0:0]$2872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$7[0:0]$2838 1'0 + assign $2\fus_cu_issue_i$14[0:0]$2872 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$7[0:0]$2838 1'0 + assign $2\fus_cu_issue_i$14[0:0]$2872 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$7[0:0]$2838 $3\fus_cu_issue_i$7[0:0]$2839 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$14[0:0]$2872 $3\fus_cu_issue_i$14[0:0]$2873 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$7[0:0]$2839 \issue_i + assign $3\fus_cu_issue_i$14[0:0]$2873 \issue_i case - assign $3\fus_cu_issue_i$7[0:0]$2839 1'0 + assign $3\fus_cu_issue_i$14[0:0]$2873 1'0 end end case - assign $1\fus_cu_issue_i$7[0:0]$2837 1'0 + assign $1\fus_cu_issue_i$14[0:0]$2871 1'0 end sync always - update \fus_cu_issue_i$7 $0\fus_cu_issue_i$7[0:0]$2836 + update \fus_cu_issue_i$14 $0\fus_cu_issue_i$14[0:0]$2870 end - attribute \src "libresoc.v:46533.3-46541.6" - process $proc$libresoc.v:46533$2840 + attribute \src "libresoc.v:47232.3-47240.6" + process $proc$libresoc.v:47232$2874 assign { } { } assign { } { } - assign $0\wr_pick_dly$1679$next[0:0]$2841 $1\wr_pick_dly$1679$next[0:0]$2842 - attribute \src "libresoc.v:46534.5-46534.29" + assign $0\wr_pick_dly$1693$next[0:0]$2875 $1\wr_pick_dly$1693$next[0:0]$2876 + attribute \src "libresoc.v:47233.5-47233.29" switch \initial - attribute \src "libresoc.v:46534.9-46534.17" + attribute \src "libresoc.v:47233.9-47233.17" case 1'1 case end @@ -81885,66 +82904,66 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1679$next[0:0]$2842 1'0 + assign $1\wr_pick_dly$1693$next[0:0]$2876 1'0 case - assign $1\wr_pick_dly$1679$next[0:0]$2842 \wr_pick$1676 + assign $1\wr_pick_dly$1693$next[0:0]$2876 \wr_pick$1690 end sync always - update \wr_pick_dly$1679$next $0\wr_pick_dly$1679$next[0:0]$2841 + update \wr_pick_dly$1693$next $0\wr_pick_dly$1693$next[0:0]$2875 end - attribute \src "libresoc.v:46542.3-46570.6" - process $proc$libresoc.v:46542$2843 + attribute \src "libresoc.v:47241.3-47269.6" + process $proc$libresoc.v:47241$2877 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$9[2:0]$2844 $1\fus_cu_rdmaskn_i$9[2:0]$2845 - attribute \src "libresoc.v:46543.5-46543.29" + assign $0\fus_cu_rdmaskn_i$16[2:0]$2878 $1\fus_cu_rdmaskn_i$16[2:0]$2879 + attribute \src "libresoc.v:47242.5-47242.29" switch \initial - attribute \src "libresoc.v:46543.9-46543.17" + attribute \src "libresoc.v:47242.9-47242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$9[2:0]$2845 $2\fus_cu_rdmaskn_i$9[2:0]$2846 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$16[2:0]$2879 $2\fus_cu_rdmaskn_i$16[2:0]$2880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 3'000 + assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 3'000 + assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$9[2:0]$2846 $3\fus_cu_rdmaskn_i$9[2:0]$2847 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 $3\fus_cu_rdmaskn_i$16[2:0]$2881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$9[2:0]$2847 \$231 + assign $3\fus_cu_rdmaskn_i$16[2:0]$2881 \$245 case - assign $3\fus_cu_rdmaskn_i$9[2:0]$2847 3'000 + assign $3\fus_cu_rdmaskn_i$16[2:0]$2881 3'000 end end case - assign $1\fus_cu_rdmaskn_i$9[2:0]$2845 3'000 + assign $1\fus_cu_rdmaskn_i$16[2:0]$2879 3'000 end sync always - update \fus_cu_rdmaskn_i$9 $0\fus_cu_rdmaskn_i$9[2:0]$2844 + update \fus_cu_rdmaskn_i$16 $0\fus_cu_rdmaskn_i$16[2:0]$2878 end - attribute \src "libresoc.v:46571.3-46579.6" - process $proc$libresoc.v:46571$2848 + attribute \src "libresoc.v:47270.3-47278.6" + process $proc$libresoc.v:47270$2882 assign { } { } assign { } { } - assign $0\wr_pick_dly$1723$next[0:0]$2849 $1\wr_pick_dly$1723$next[0:0]$2850 - attribute \src "libresoc.v:46572.5-46572.29" + assign $0\wr_pick_dly$1737$next[0:0]$2883 $1\wr_pick_dly$1737$next[0:0]$2884 + attribute \src "libresoc.v:47271.5-47271.29" switch \initial - attribute \src "libresoc.v:46572.9-46572.17" + attribute \src "libresoc.v:47271.9-47271.17" case 1'1 case end @@ -81953,54 +82972,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1723$next[0:0]$2850 1'0 + assign $1\wr_pick_dly$1737$next[0:0]$2884 1'0 case - assign $1\wr_pick_dly$1723$next[0:0]$2850 \wr_pick$1720 + assign $1\wr_pick_dly$1737$next[0:0]$2884 \wr_pick$1734 end sync always - update \wr_pick_dly$1723$next $0\wr_pick_dly$1723$next[0:0]$2849 + update \wr_pick_dly$1737$next $0\wr_pick_dly$1737$next[0:0]$2883 end - attribute \src "libresoc.v:46580.3-46588.6" - process $proc$libresoc.v:46580$2851 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1739$next[0:0]$2852 $1\wr_pick_dly$1739$next[0:0]$2853 - attribute \src "libresoc.v:46581.5-46581.29" - switch \initial - attribute \src "libresoc.v:46581.9-46581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1739$next[0:0]$2853 1'0 - case - assign $1\wr_pick_dly$1739$next[0:0]$2853 \wr_pick$1736 - end - sync always - update \wr_pick_dly$1739$next $0\wr_pick_dly$1739$next[0:0]$2852 - end - attribute \src "libresoc.v:46589.3-46617.6" - process $proc$libresoc.v:46589$2854 + attribute \src "libresoc.v:47279.3-47307.6" + process $proc$libresoc.v:47279$2885 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:46590.5-46590.29" + attribute \src "libresoc.v:47280.5-47280.29" switch \initial - attribute \src "libresoc.v:46590.9-46590.17" + attribute \src "libresoc.v:47280.9-47280.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82012,7 +83008,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82028,14 +83024,14 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:46618.3-46626.6" - process $proc$libresoc.v:46618$2855 + attribute \src "libresoc.v:47308.3-47316.6" + process $proc$libresoc.v:47308$2886 assign { } { } assign { } { } - assign $0\wr_pick_dly$1763$next[0:0]$2856 $1\wr_pick_dly$1763$next[0:0]$2857 - attribute \src "libresoc.v:46619.5-46619.29" + assign $0\wr_pick_dly$1753$next[0:0]$2887 $1\wr_pick_dly$1753$next[0:0]$2888 + attribute \src "libresoc.v:47309.5-47309.29" switch \initial - attribute \src "libresoc.v:46619.9-46619.17" + attribute \src "libresoc.v:47309.9-47309.17" case 1'1 case end @@ -82044,31 +83040,54 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1763$next[0:0]$2857 1'0 + assign $1\wr_pick_dly$1753$next[0:0]$2888 1'0 case - assign $1\wr_pick_dly$1763$next[0:0]$2857 \wr_pick$1760 + assign $1\wr_pick_dly$1753$next[0:0]$2888 \wr_pick$1750 end sync always - update \wr_pick_dly$1763$next $0\wr_pick_dly$1763$next[0:0]$2856 + update \wr_pick_dly$1753$next $0\wr_pick_dly$1753$next[0:0]$2887 end - attribute \src "libresoc.v:46627.3-46655.6" - process $proc$libresoc.v:46627$2858 + attribute \src "libresoc.v:47317.3-47325.6" + process $proc$libresoc.v:47317$2889 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1777$next[0:0]$2890 $1\wr_pick_dly$1777$next[0:0]$2891 + attribute \src "libresoc.v:47318.5-47318.29" + switch \initial + attribute \src "libresoc.v:47318.9-47318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1777$next[0:0]$2891 1'0 + case + assign $1\wr_pick_dly$1777$next[0:0]$2891 \wr_pick$1774 + end + sync always + update \wr_pick_dly$1777$next $0\wr_pick_dly$1777$next[0:0]$2890 + end + attribute \src "libresoc.v:47326.3-47354.6" + process $proc$libresoc.v:47326$2892 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:46628.5-46628.29" + attribute \src "libresoc.v:47327.5-47327.29" switch \initial - attribute \src "libresoc.v:46628.9-46628.17" + attribute \src "libresoc.v:47327.9-47327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82080,7 +83099,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82096,14 +83115,14 @@ module \core sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] end - attribute \src "libresoc.v:46656.3-46664.6" - process $proc$libresoc.v:46656$2859 + attribute \src "libresoc.v:47355.3-47363.6" + process $proc$libresoc.v:47355$2893 assign { } { } assign { } { } - assign $0\wr_pick_dly$1783$next[0:0]$2860 $1\wr_pick_dly$1783$next[0:0]$2861 - attribute \src "libresoc.v:46657.5-46657.29" + assign $0\wr_pick_dly$1797$next[0:0]$2894 $1\wr_pick_dly$1797$next[0:0]$2895 + attribute \src "libresoc.v:47356.5-47356.29" switch \initial - attribute \src "libresoc.v:46657.9-46657.17" + attribute \src "libresoc.v:47356.9-47356.17" case 1'1 case end @@ -82112,31 +83131,31 @@ module \core attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wr_pick_dly$1783$next[0:0]$2861 1'0 + assign $1\wr_pick_dly$1797$next[0:0]$2895 1'0 case - assign $1\wr_pick_dly$1783$next[0:0]$2861 \wr_pick$1780 + assign $1\wr_pick_dly$1797$next[0:0]$2895 \wr_pick$1794 end sync always - update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2860 + update \wr_pick_dly$1797$next $0\wr_pick_dly$1797$next[0:0]$2894 end - attribute \src "libresoc.v:46665.3-46693.6" - process $proc$libresoc.v:46665$2862 + attribute \src "libresoc.v:47364.3-47392.6" + process $proc$libresoc.v:47364$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:46666.5-46666.29" + attribute \src "libresoc.v:47365.5-47365.29" switch \initial - attribute \src "libresoc.v:46666.9-46666.17" + attribute \src "libresoc.v:47365.9-47365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82148,7 +83167,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82164,24 +83183,24 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:46694.3-46722.6" - process $proc$libresoc.v:46694$2863 + attribute \src "libresoc.v:47393.3-47421.6" + process $proc$libresoc.v:47393$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:46695.5-46695.29" + attribute \src "libresoc.v:47394.5-47394.29" switch \initial - attribute \src "libresoc.v:46695.9-46695.17" + attribute \src "libresoc.v:47394.9-47394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82193,7 +83212,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82209,24 +83228,24 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:46723.3-46751.6" - process $proc$libresoc.v:46723$2864 + attribute \src "libresoc.v:47422.3-47450.6" + process $proc$libresoc.v:47422$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:46724.5-46724.29" + attribute \src "libresoc.v:47423.5-47423.29" switch \initial - attribute \src "libresoc.v:46724.9-46724.17" + attribute \src "libresoc.v:47423.9-47423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82238,7 +83257,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82254,24 +83273,24 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:46752.3-46780.6" - process $proc$libresoc.v:46752$2865 + attribute \src "libresoc.v:47451.3-47479.6" + process $proc$libresoc.v:47451$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:46753.5-46753.29" + attribute \src "libresoc.v:47452.5-47452.29" switch \initial - attribute \src "libresoc.v:46753.9-46753.17" + attribute \src "libresoc.v:47452.9-47452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82283,7 +83302,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82299,69 +83318,69 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:46781.3-46809.6" - process $proc$libresoc.v:46781$2866 + attribute \src "libresoc.v:47480.3-47508.6" + process $proc$libresoc.v:47480$2900 assign { } { } assign { } { } - assign $0\fus_oper_i_alu_trap0__traptype[6:0] $1\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "libresoc.v:46782.5-46782.29" + assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:47481.5-47481.29" switch \initial - attribute \src "libresoc.v:46782.9-46782.17" + attribute \src "libresoc.v:47481.9-47481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_oper_i_alu_trap0__traptype[6:0] $2\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_oper_i_alu_trap0__traptype[6:0] $3\fus_oper_i_alu_trap0__traptype[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_trap0__traptype[6:0] \core_core_traptype + assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype case - assign $3\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end end case - assign $1\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 end sync always - update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[6:0] + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:46810.3-46838.6" - process $proc$libresoc.v:46810$2867 + attribute \src "libresoc.v:47509.3-47537.6" + process $proc$libresoc.v:47509$2901 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:46811.5-46811.29" + attribute \src "libresoc.v:47510.5-47510.29" switch \initial - attribute \src "libresoc.v:46811.9-46811.17" + attribute \src "libresoc.v:47510.9-47510.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82373,7 +83392,7 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82389,114 +83408,159 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:46839.3-46867.6" - process $proc$libresoc.v:46839$2868 + attribute \src "libresoc.v:47538.3-47566.6" + process $proc$libresoc.v:47538$2902 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$10[0:0]$2869 $1\fus_cu_issue_i$10[0:0]$2870 - attribute \src "libresoc.v:46840.5-46840.29" + assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47539.5-47539.29" switch \initial - attribute \src "libresoc.v:46840.9-46840.17" + attribute \src "libresoc.v:47539.9-47539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$10[0:0]$2870 $2\fus_cu_issue_i$10[0:0]$2871 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$10[0:0]$2871 1'0 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$10[0:0]$2871 1'0 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$10[0:0]$2871 $3\fus_cu_issue_i$10[0:0]$2872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$10[0:0]$2872 \issue_i + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } case - assign $3\fus_cu_issue_i$10[0:0]$2872 1'0 + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 end end case - assign $1\fus_cu_issue_i$10[0:0]$2870 1'0 + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 end sync always - update \fus_cu_issue_i$10 $0\fus_cu_issue_i$10[0:0]$2869 + update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:46868.3-46896.6" - process $proc$libresoc.v:46868$2873 + attribute \src "libresoc.v:47567.3-47595.6" + process $proc$libresoc.v:47567$2903 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$12[3:0]$2874 $1\fus_cu_rdmaskn_i$12[3:0]$2875 - attribute \src "libresoc.v:46869.5-46869.29" + assign $0\fus_cu_issue_i$17[0:0]$2904 $1\fus_cu_issue_i$17[0:0]$2905 + attribute \src "libresoc.v:47568.5-47568.29" switch \initial - attribute \src "libresoc.v:46869.9-46869.17" + attribute \src "libresoc.v:47568.9-47568.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$12[3:0]$2875 $2\fus_cu_rdmaskn_i$12[3:0]$2876 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$17[0:0]$2905 $2\fus_cu_issue_i$17[0:0]$2906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 4'0000 + assign $2\fus_cu_issue_i$17[0:0]$2906 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 4'0000 + assign $2\fus_cu_issue_i$17[0:0]$2906 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$12[3:0]$2876 $3\fus_cu_rdmaskn_i$12[3:0]$2877 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$17[0:0]$2906 $3\fus_cu_issue_i$17[0:0]$2907 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$12[3:0]$2877 \$233 + assign $3\fus_cu_issue_i$17[0:0]$2907 \issue_i case - assign $3\fus_cu_rdmaskn_i$12[3:0]$2877 4'0000 + assign $3\fus_cu_issue_i$17[0:0]$2907 1'0 end end case - assign $1\fus_cu_rdmaskn_i$12[3:0]$2875 4'0000 + assign $1\fus_cu_issue_i$17[0:0]$2905 1'0 end sync always - update \fus_cu_rdmaskn_i$12 $0\fus_cu_rdmaskn_i$12[3:0]$2874 + update \fus_cu_issue_i$17 $0\fus_cu_issue_i$17[0:0]$2904 end - attribute \src "libresoc.v:46897.3-46925.6" - process $proc$libresoc.v:46897$2878 + attribute \src "libresoc.v:47596.3-47624.6" + process $proc$libresoc.v:47596$2908 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$19[3:0]$2909 $1\fus_cu_rdmaskn_i$19[3:0]$2910 + attribute \src "libresoc.v:47597.5-47597.29" + switch \initial + attribute \src "libresoc.v:47597.9-47597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$19[3:0]$2910 $2\fus_cu_rdmaskn_i$19[3:0]$2911 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 $3\fus_cu_rdmaskn_i$19[3:0]$2912 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$19[3:0]$2912 \$247 + case + assign $3\fus_cu_rdmaskn_i$19[3:0]$2912 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$19[3:0]$2910 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$19 $0\fus_cu_rdmaskn_i$19[3:0]$2909 + end + attribute \src "libresoc.v:47625.3-47653.6" + process $proc$libresoc.v:47625$2913 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:46898.5-46898.29" + attribute \src "libresoc.v:47626.5-47626.29" switch \initial - attribute \src "libresoc.v:46898.9-46898.17" + attribute \src "libresoc.v:47626.9-47626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82508,12 +83572,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type case assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 end @@ -82524,24 +83588,24 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:46926.3-46954.6" - process $proc$libresoc.v:46926$2879 + attribute \src "libresoc.v:47654.3-47682.6" + process $proc$libresoc.v:47654$2914 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:46927.5-46927.29" + attribute \src "libresoc.v:47655.5-47655.29" switch \initial - attribute \src "libresoc.v:46927.9-46927.17" + attribute \src "libresoc.v:47655.9-47655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82553,12 +83617,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL__fn_unit case assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 end @@ -82569,21 +83633,21 @@ module \core sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] end - attribute \src "libresoc.v:46955.3-46984.6" - process $proc$libresoc.v:46955$2880 + attribute \src "libresoc.v:47683.3-47712.6" + process $proc$libresoc.v:47683$2915 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:46956.5-46956.29" + attribute \src "libresoc.v:47684.5-47684.29" switch \initial - attribute \src "libresoc.v:46956.9-46956.17" + attribute \src "libresoc.v:47684.9-47684.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82591,7 +83655,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82607,13 +83671,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } case assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 @@ -82627,21 +83691,21 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46985.3-47014.6" - process $proc$libresoc.v:46985$2881 + attribute \src "libresoc.v:47713.3-47742.6" + process $proc$libresoc.v:47713$2916 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:46986.5-46986.29" + attribute \src "libresoc.v:47714.5-47714.29" switch \initial - attribute \src "libresoc.v:46986.9-46986.17" + attribute \src "libresoc.v:47714.9-47714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82649,7 +83713,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82665,13 +83729,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } case assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 @@ -82685,21 +83749,21 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:47015.3-47044.6" - process $proc$libresoc.v:47015$2882 + attribute \src "libresoc.v:47743.3-47772.6" + process $proc$libresoc.v:47743$2917 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47016.5-47016.29" + attribute \src "libresoc.v:47744.5-47744.29" switch \initial - attribute \src "libresoc.v:47016.9-47016.17" + attribute \src "libresoc.v:47744.9-47744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -82707,7 +83771,7 @@ module \core assign { } { } assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82723,13 +83787,13 @@ module \core assign { } { } assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } case assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 @@ -82743,24 +83807,24 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:47045.3-47073.6" - process $proc$libresoc.v:47045$2883 + attribute \src "libresoc.v:47773.3-47801.6" + process $proc$libresoc.v:47773$2918 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47046.5-47046.29" + attribute \src "libresoc.v:47774.5-47774.29" switch \initial - attribute \src "libresoc.v:47046.9-47046.17" + attribute \src "libresoc.v:47774.9-47774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82772,12 +83836,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in case assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 end @@ -82788,24 +83852,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:47074.3-47102.6" - process $proc$libresoc.v:47074$2884 + attribute \src "libresoc.v:47802.3-47830.6" + process $proc$libresoc.v:47802$2919 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:47075.5-47075.29" + attribute \src "libresoc.v:47803.5-47803.29" switch \initial - attribute \src "libresoc.v:47075.9-47075.17" + attribute \src "libresoc.v:47803.9-47803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82817,12 +83881,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a case assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 end @@ -82833,24 +83897,24 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:47103.3-47131.6" - process $proc$libresoc.v:47103$2885 + attribute \src "libresoc.v:47831.3-47859.6" + process $proc$libresoc.v:47831$2920 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47104.5-47104.29" + attribute \src "libresoc.v:47832.5-47832.29" switch \initial - attribute \src "libresoc.v:47104.9-47104.17" + attribute \src "libresoc.v:47832.9-47832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82862,12 +83926,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry case assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 end @@ -82878,24 +83942,24 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:47132.3-47160.6" - process $proc$libresoc.v:47132$2886 + attribute \src "libresoc.v:47860.3-47888.6" + process $proc$libresoc.v:47860$2921 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47133.5-47133.29" + attribute \src "libresoc.v:47861.5-47861.29" switch \initial - attribute \src "libresoc.v:47133.9-47133.17" + attribute \src "libresoc.v:47861.9-47861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82907,12 +83971,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out case assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 end @@ -82923,24 +83987,24 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:47161.3-47189.6" - process $proc$libresoc.v:47161$2887 + attribute \src "libresoc.v:47889.3-47917.6" + process $proc$libresoc.v:47889$2922 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47162.5-47162.29" + attribute \src "libresoc.v:47890.5-47890.29" switch \initial - attribute \src "libresoc.v:47162.9-47162.17" + attribute \src "libresoc.v:47890.9-47890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82952,12 +84016,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 case assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 end @@ -82968,24 +84032,24 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - attribute \src "libresoc.v:47190.3-47218.6" - process $proc$libresoc.v:47190$2888 + attribute \src "libresoc.v:47918.3-47946.6" + process $proc$libresoc.v:47918$2923 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47191.5-47191.29" + attribute \src "libresoc.v:47919.5-47919.29" switch \initial - attribute \src "libresoc.v:47191.9-47191.17" + attribute \src "libresoc.v:47919.9-47919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -82997,12 +84061,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry case assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 end @@ -83013,24 +84077,24 @@ module \core sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:47219.3-47247.6" - process $proc$libresoc.v:47219$2889 + attribute \src "libresoc.v:47947.3-47975.6" + process $proc$libresoc.v:47947$2924 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47220.5-47220.29" + attribute \src "libresoc.v:47948.5-47948.29" switch \initial - attribute \src "libresoc.v:47220.9-47220.17" + attribute \src "libresoc.v:47948.9-47948.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83042,12 +84106,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit case assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 end @@ -83058,24 +84122,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end - attribute \src "libresoc.v:47248.3-47276.6" - process $proc$libresoc.v:47248$2890 + attribute \src "libresoc.v:47976.3-48004.6" + process $proc$libresoc.v:47976$2925 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47249.5-47249.29" + attribute \src "libresoc.v:47977.5-47977.29" switch \initial - attribute \src "libresoc.v:47249.9-47249.17" + attribute \src "libresoc.v:47977.9-47977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83087,12 +84151,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed case assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 end @@ -83103,24 +84167,24 @@ module \core sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:47277.3-47305.6" - process $proc$libresoc.v:47277$2891 + attribute \src "libresoc.v:48005.3-48033.6" + process $proc$libresoc.v:48005$2926 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47278.5-47278.29" + attribute \src "libresoc.v:48006.5-48006.29" switch \initial - attribute \src "libresoc.v:47278.9-47278.17" + attribute \src "libresoc.v:48006.9-48006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83132,12 +84196,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL_LOGICAL__data_len + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len case assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 end @@ -83148,24 +84212,24 @@ module \core sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end - attribute \src "libresoc.v:47306.3-47334.6" - process $proc$libresoc.v:47306$2892 + attribute \src "libresoc.v:48034.3-48062.6" + process $proc$libresoc.v:48034$2927 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47307.5-47307.29" + attribute \src "libresoc.v:48035.5-48035.29" switch \initial - attribute \src "libresoc.v:47307.9-47307.17" + attribute \src "libresoc.v:48035.9-48035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83177,12 +84241,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn case assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 end @@ -83193,114 +84257,114 @@ module \core sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:47335.3-47363.6" - process $proc$libresoc.v:47335$2893 + attribute \src "libresoc.v:48063.3-48091.6" + process $proc$libresoc.v:48063$2928 assign { } { } assign { } { } - assign $0\fus_cu_issue_i$13[0:0]$2894 $1\fus_cu_issue_i$13[0:0]$2895 - attribute \src "libresoc.v:47336.5-47336.29" + assign $0\fus_cu_issue_i$20[0:0]$2929 $1\fus_cu_issue_i$20[0:0]$2930 + attribute \src "libresoc.v:48064.5-48064.29" switch \initial - attribute \src "libresoc.v:47336.9-47336.17" + attribute \src "libresoc.v:48064.9-48064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_issue_i$13[0:0]$2895 $2\fus_cu_issue_i$13[0:0]$2896 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_issue_i$20[0:0]$2930 $2\fus_cu_issue_i$20[0:0]$2931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_issue_i$13[0:0]$2896 1'0 + assign $2\fus_cu_issue_i$20[0:0]$2931 1'0 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_issue_i$13[0:0]$2896 1'0 + assign $2\fus_cu_issue_i$20[0:0]$2931 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_issue_i$13[0:0]$2896 $3\fus_cu_issue_i$13[0:0]$2897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_issue_i$20[0:0]$2931 $3\fus_cu_issue_i$20[0:0]$2932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_issue_i$13[0:0]$2897 \issue_i + assign $3\fus_cu_issue_i$20[0:0]$2932 \issue_i case - assign $3\fus_cu_issue_i$13[0:0]$2897 1'0 + assign $3\fus_cu_issue_i$20[0:0]$2932 1'0 end end case - assign $1\fus_cu_issue_i$13[0:0]$2895 1'0 + assign $1\fus_cu_issue_i$20[0:0]$2930 1'0 end sync always - update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2894 + update \fus_cu_issue_i$20 $0\fus_cu_issue_i$20[0:0]$2929 end - attribute \src "libresoc.v:47364.3-47392.6" - process $proc$libresoc.v:47364$2898 + attribute \src "libresoc.v:48092.3-48120.6" + process $proc$libresoc.v:48092$2933 assign { } { } assign { } { } - assign $0\fus_cu_rdmaskn_i$15[2:0]$2899 $1\fus_cu_rdmaskn_i$15[2:0]$2900 - attribute \src "libresoc.v:47365.5-47365.29" + assign $0\fus_cu_rdmaskn_i$22[2:0]$2934 $1\fus_cu_rdmaskn_i$22[2:0]$2935 + attribute \src "libresoc.v:48093.5-48093.29" switch \initial - attribute \src "libresoc.v:47365.9-47365.17" + attribute \src "libresoc.v:48093.9-48093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fus_cu_rdmaskn_i$15[2:0]$2900 $2\fus_cu_rdmaskn_i$15[2:0]$2901 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + assign $1\fus_cu_rdmaskn_i$22[2:0]$2935 $2\fus_cu_rdmaskn_i$22[2:0]$2936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 - assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 3'000 + assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 3'000 attribute \src "libresoc.v:0.0-0.0" case 7'0000001 - assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 3'000 + assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fus_cu_rdmaskn_i$15[2:0]$2901 $3\fus_cu_rdmaskn_i$15[2:0]$2902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 $3\fus_cu_rdmaskn_i$22[2:0]$2937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_cu_rdmaskn_i$15[2:0]$2902 \$235 + assign $3\fus_cu_rdmaskn_i$22[2:0]$2937 \$249 case - assign $3\fus_cu_rdmaskn_i$15[2:0]$2902 3'000 + assign $3\fus_cu_rdmaskn_i$22[2:0]$2937 3'000 end end case - assign $1\fus_cu_rdmaskn_i$15[2:0]$2900 3'000 + assign $1\fus_cu_rdmaskn_i$22[2:0]$2935 3'000 end sync always - update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[2:0]$2899 + update \fus_cu_rdmaskn_i$22 $0\fus_cu_rdmaskn_i$22[2:0]$2934 end - attribute \src "libresoc.v:47393.3-47421.6" - process $proc$libresoc.v:47393$2903 + attribute \src "libresoc.v:48121.3-48149.6" + process $proc$libresoc.v:48121$2938 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:47394.5-47394.29" + attribute \src "libresoc.v:48122.5-48122.29" switch \initial - attribute \src "libresoc.v:47394.9-47394.17" + attribute \src "libresoc.v:48122.9-48122.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83312,12 +84376,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR_SPR__insn_type + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type case assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 end @@ -83328,24 +84392,24 @@ module \core sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:47422.3-47450.6" - process $proc$libresoc.v:47422$2904 + attribute \src "libresoc.v:48150.3-48178.6" + process $proc$libresoc.v:48150$2939 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:47423.5-47423.29" + attribute \src "libresoc.v:48151.5-48151.29" switch \initial - attribute \src "libresoc.v:47423.9-47423.17" + attribute \src "libresoc.v:48151.9-48151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" switch \ivalid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000101 @@ -83357,12 +84421,12 @@ module \core case assign { } { } assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" switch \fu_enable [5] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR_SPR__fn_unit + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR__fn_unit case assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 end @@ -83373,1211 +84437,1165 @@ module \core sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] end - attribute \src "libresoc.v:47451.3-47479.6" - process $proc$libresoc.v:47451$2905 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:47452.5-47452.29" - switch \initial - attribute \src "libresoc.v:47452.9-47452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR_SPR__insn - case - assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] - end - connect \$1000 $ternary$libresoc.v:41097$1514_Y - connect \$1002 $and$libresoc.v:41098$1515_Y - connect \$1005 $and$libresoc.v:41099$1516_Y - connect \$1009 $not$libresoc.v:41100$1517_Y - connect \$1011 $and$libresoc.v:41101$1518_Y - connect \$1015 $and$libresoc.v:41102$1519_Y - connect \$1018 $ternary$libresoc.v:41103$1520_Y - connect \$1020 $and$libresoc.v:41104$1521_Y - connect \$1023 $and$libresoc.v:41105$1522_Y - connect \$1027 $not$libresoc.v:41106$1523_Y - connect \$1029 $and$libresoc.v:41107$1524_Y - connect \$1037 $and$libresoc.v:41108$1525_Y - connect \$1040 $ternary$libresoc.v:41109$1526_Y - connect \$1042 $and$libresoc.v:41110$1527_Y - connect \$1045 $and$libresoc.v:41111$1528_Y - connect \$1049 $not$libresoc.v:41112$1529_Y - connect \$1051 $and$libresoc.v:41113$1530_Y - connect \$1057 $and$libresoc.v:41114$1531_Y - connect \$1060 $ternary$libresoc.v:41115$1532_Y - connect \$1062 $and$libresoc.v:41116$1533_Y - connect \$1065 $and$libresoc.v:41117$1534_Y - connect \$1069 $not$libresoc.v:41118$1535_Y - connect \$1071 $and$libresoc.v:41119$1536_Y - connect \$1077 $and$libresoc.v:41120$1537_Y - connect \$1080 $ternary$libresoc.v:41121$1538_Y - connect \$1082 $and$libresoc.v:41122$1539_Y - connect \$1085 $and$libresoc.v:41123$1540_Y - connect \$1089 $not$libresoc.v:41124$1541_Y - connect \$1091 $and$libresoc.v:41125$1542_Y - connect \$1096 $and$libresoc.v:41126$1543_Y - connect \$1099 $ternary$libresoc.v:41127$1544_Y - connect \$1101 $and$libresoc.v:41128$1545_Y - connect \$1104 $and$libresoc.v:41129$1546_Y - connect \$1108 $not$libresoc.v:41130$1547_Y - connect \$1110 $and$libresoc.v:41131$1548_Y - connect \$1114 $and$libresoc.v:41132$1549_Y - connect \$1117 $ternary$libresoc.v:41133$1550_Y - connect \$1119 $and$libresoc.v:41134$1551_Y - connect \$1122 $and$libresoc.v:41135$1552_Y - connect \$1125 $not$libresoc.v:41136$1553_Y - connect \$1127 $and$libresoc.v:41137$1554_Y - connect \$1130 $and$libresoc.v:41138$1555_Y - connect \$1133 $ternary$libresoc.v:41139$1556_Y - connect \$1136 $or$libresoc.v:41140$1557_Y - connect \$1138 $or$libresoc.v:41141$1558_Y - connect \$1140 $or$libresoc.v:41142$1559_Y - connect \$1142 $or$libresoc.v:41143$1560_Y - connect \$1144 $or$libresoc.v:41144$1561_Y - connect \$1146 $or$libresoc.v:41145$1562_Y - connect \$1148 $or$libresoc.v:41146$1563_Y - connect \$1150 $or$libresoc.v:41147$1564_Y - connect \$1152 $or$libresoc.v:41148$1565_Y - connect \$1154 $or$libresoc.v:41149$1566_Y - connect \$1156 $or$libresoc.v:41150$1567_Y - connect \$1158 $or$libresoc.v:41151$1568_Y - connect \$1160 $or$libresoc.v:41152$1569_Y - connect \$1162 $or$libresoc.v:41153$1570_Y - connect \$1164 $or$libresoc.v:41154$1571_Y - connect \$1166 $or$libresoc.v:41155$1572_Y - connect \$1168 $or$libresoc.v:41156$1573_Y - connect \$1170 $or$libresoc.v:41157$1574_Y - connect \$1172 $or$libresoc.v:41158$1575_Y - connect \$1174 $or$libresoc.v:41159$1576_Y - connect \$1176 $or$libresoc.v:41160$1577_Y - connect \$1178 $or$libresoc.v:41161$1578_Y - connect \$1180 $or$libresoc.v:41162$1579_Y - connect \$1182 $or$libresoc.v:41163$1580_Y - connect \$1184 $or$libresoc.v:41164$1581_Y - connect \$1186 $or$libresoc.v:41165$1582_Y - connect \$1188 $or$libresoc.v:41166$1583_Y - connect \$1190 $and$libresoc.v:41167$1584_Y - connect \$1192 $and$libresoc.v:41168$1585_Y - connect \$1195 $and$libresoc.v:41169$1586_Y - connect \$1198 $not$libresoc.v:41170$1587_Y - connect \$1200 $and$libresoc.v:41171$1588_Y - connect \$1203 $and$libresoc.v:41172$1589_Y - connect \$1206 $ternary$libresoc.v:41173$1590_Y - connect \$1208 $and$libresoc.v:41174$1591_Y - connect \$1210 $and$libresoc.v:41175$1592_Y - connect \$1212 $and$libresoc.v:41176$1593_Y - connect \$1214 $and$libresoc.v:41177$1594_Y - connect \$1216 $and$libresoc.v:41178$1595_Y - connect \$1218 $and$libresoc.v:41179$1596_Y - connect \$1220 $and$libresoc.v:41180$1597_Y - connect \$1223 $and$libresoc.v:41181$1598_Y - connect \$1226 $not$libresoc.v:41182$1599_Y - connect \$1228 $and$libresoc.v:41183$1600_Y - connect \$1231 $and$libresoc.v:41184$1601_Y - connect \$1234 $sub$libresoc.v:41185$1602_Y - connect \$1236 $sshl$libresoc.v:41186$1603_Y - connect \$1238 $ternary$libresoc.v:41187$1604_Y - connect \$1240 $and$libresoc.v:41188$1605_Y - connect \$1243 $and$libresoc.v:41189$1606_Y - connect \$1246 $not$libresoc.v:41190$1607_Y - connect \$1248 $and$libresoc.v:41191$1608_Y - connect \$1251 $and$libresoc.v:41192$1609_Y - connect \$1254 $sub$libresoc.v:41193$1610_Y - connect \$1256 $sshl$libresoc.v:41194$1611_Y - connect \$1258 $ternary$libresoc.v:41195$1612_Y - connect \$1260 $and$libresoc.v:41196$1613_Y - connect \$1263 $and$libresoc.v:41197$1614_Y - connect \$1266 $not$libresoc.v:41198$1615_Y - connect \$1268 $and$libresoc.v:41199$1616_Y - connect \$1271 $and$libresoc.v:41200$1617_Y - connect \$1274 $sub$libresoc.v:41201$1618_Y - connect \$1276 $sshl$libresoc.v:41202$1619_Y - connect \$1278 $ternary$libresoc.v:41203$1620_Y - connect \$1280 $and$libresoc.v:41204$1621_Y - connect \$1283 $and$libresoc.v:41205$1622_Y - connect \$1286 $not$libresoc.v:41206$1623_Y - connect \$1288 $and$libresoc.v:41207$1624_Y - connect \$1291 $and$libresoc.v:41208$1625_Y - connect \$1294 $sub$libresoc.v:41209$1626_Y - connect \$1296 $sshl$libresoc.v:41210$1627_Y - connect \$1298 $ternary$libresoc.v:41211$1628_Y - connect \$1300 $and$libresoc.v:41212$1629_Y - connect \$1303 $and$libresoc.v:41213$1630_Y - connect \$1306 $not$libresoc.v:41214$1631_Y - connect \$1308 $and$libresoc.v:41215$1632_Y - connect \$1311 $and$libresoc.v:41216$1633_Y - connect \$1314 $sub$libresoc.v:41217$1634_Y - connect \$1316 $sshl$libresoc.v:41218$1635_Y - connect \$1318 $ternary$libresoc.v:41219$1636_Y - connect \$1320 $and$libresoc.v:41220$1637_Y - connect \$1323 $and$libresoc.v:41221$1638_Y - connect \$1326 $not$libresoc.v:41222$1639_Y - connect \$1328 $and$libresoc.v:41223$1640_Y - connect \$1331 $and$libresoc.v:41224$1641_Y - connect \$1334 $sub$libresoc.v:41225$1642_Y - connect \$1336 $sshl$libresoc.v:41226$1643_Y - connect \$1338 $ternary$libresoc.v:41227$1644_Y - connect \$1340 $or$libresoc.v:41228$1645_Y - connect \$1342 $or$libresoc.v:41229$1646_Y - connect \$1344 $or$libresoc.v:41230$1647_Y - connect \$1346 $or$libresoc.v:41231$1648_Y - connect \$1348 $or$libresoc.v:41232$1649_Y - connect \$1351 $or$libresoc.v:41233$1650_Y - connect \$1353 $or$libresoc.v:41234$1651_Y - connect \$1355 $or$libresoc.v:41235$1652_Y - connect \$1357 $or$libresoc.v:41236$1653_Y - connect \$1359 $or$libresoc.v:41237$1654_Y - connect \$1361 $and$libresoc.v:41238$1655_Y - connect \$1363 $and$libresoc.v:41239$1656_Y - connect \$1365 $and$libresoc.v:41240$1657_Y - connect \$1367 $and$libresoc.v:41241$1658_Y - connect \$1370 $and$libresoc.v:41242$1659_Y - connect \$1373 $not$libresoc.v:41243$1660_Y - connect \$1375 $and$libresoc.v:41244$1661_Y - connect \$1378 $and$libresoc.v:41245$1662_Y - connect \$1381 $ternary$libresoc.v:41246$1663_Y - connect \$1383 $and$libresoc.v:41247$1664_Y - connect \$1386 $and$libresoc.v:41248$1665_Y - connect \$1389 $not$libresoc.v:41249$1666_Y - connect \$1391 $and$libresoc.v:41250$1667_Y - connect \$1394 $and$libresoc.v:41251$1668_Y - connect \$1397 $ternary$libresoc.v:41252$1669_Y - connect \$1399 $and$libresoc.v:41253$1670_Y - connect \$1402 $and$libresoc.v:41254$1671_Y - connect \$1405 $not$libresoc.v:41255$1672_Y - connect \$1407 $and$libresoc.v:41256$1673_Y - connect \$1410 $and$libresoc.v:41257$1674_Y - connect \$1413 $ternary$libresoc.v:41258$1675_Y - connect \$1415 $or$libresoc.v:41259$1676_Y - connect \$1417 $or$libresoc.v:41260$1677_Y - connect \$1420 $or$libresoc.v:41261$1678_Y - connect \$1422 $or$libresoc.v:41262$1679_Y - connect \$1419 $pos$libresoc.v:41263$1681_Y - connect \$1425 $and$libresoc.v:41264$1682_Y - connect \$1427 $and$libresoc.v:41265$1683_Y - connect \$1429 $and$libresoc.v:41266$1684_Y - connect \$1431 $and$libresoc.v:41267$1685_Y - connect \$1433 $and$libresoc.v:41268$1686_Y - connect \$1436 $and$libresoc.v:41269$1687_Y - connect \$1439 $not$libresoc.v:41270$1688_Y - connect \$1441 $and$libresoc.v:41271$1689_Y - connect \$1444 $and$libresoc.v:41272$1690_Y - connect \$1447 $ternary$libresoc.v:41273$1691_Y - connect \$1449 $and$libresoc.v:41274$1692_Y - connect \$1452 $and$libresoc.v:41275$1693_Y - connect \$1455 $not$libresoc.v:41276$1694_Y - connect \$1457 $and$libresoc.v:41277$1695_Y - connect \$1460 $and$libresoc.v:41278$1696_Y - connect \$1463 $ternary$libresoc.v:41279$1697_Y - connect \$1465 $and$libresoc.v:41280$1698_Y - connect \$1468 $and$libresoc.v:41281$1699_Y - connect \$1471 $not$libresoc.v:41282$1700_Y - connect \$1473 $and$libresoc.v:41283$1701_Y - connect \$1476 $and$libresoc.v:41284$1702_Y - connect \$1479 $ternary$libresoc.v:41285$1703_Y - connect \$1481 $and$libresoc.v:41286$1704_Y - connect \$1484 $and$libresoc.v:41287$1705_Y - connect \$1487 $not$libresoc.v:41288$1706_Y - connect \$1489 $and$libresoc.v:41289$1707_Y - connect \$1492 $and$libresoc.v:41290$1708_Y - connect \$1495 $ternary$libresoc.v:41291$1709_Y - connect \$1497 $or$libresoc.v:41292$1710_Y - connect \$1499 $or$libresoc.v:41293$1711_Y - connect \$1501 $or$libresoc.v:41294$1712_Y - connect \$1503 $or$libresoc.v:41295$1713_Y - connect \$1505 $or$libresoc.v:41296$1714_Y - connect \$1507 $or$libresoc.v:41297$1715_Y - connect \$1509 $and$libresoc.v:41298$1716_Y - connect \$1511 $and$libresoc.v:41299$1717_Y - connect \$1513 $and$libresoc.v:41300$1718_Y - connect \$1515 $and$libresoc.v:41301$1719_Y - connect \$1517 $and$libresoc.v:41302$1720_Y - connect \$1520 $and$libresoc.v:41303$1721_Y - connect \$1523 $not$libresoc.v:41304$1722_Y - connect \$1525 $and$libresoc.v:41305$1723_Y - connect \$1528 $and$libresoc.v:41306$1724_Y - connect \$1531 $ternary$libresoc.v:41307$1725_Y - connect \$1533 $and$libresoc.v:41308$1726_Y - connect \$1536 $and$libresoc.v:41309$1727_Y - connect \$1539 $not$libresoc.v:41310$1728_Y - connect \$1541 $and$libresoc.v:41311$1729_Y - connect \$1544 $and$libresoc.v:41312$1730_Y - connect \$1547 $ternary$libresoc.v:41313$1731_Y - connect \$1549 $and$libresoc.v:41314$1732_Y - connect \$1552 $and$libresoc.v:41315$1733_Y - connect \$1555 $not$libresoc.v:41316$1734_Y - connect \$1557 $and$libresoc.v:41317$1735_Y - connect \$1560 $and$libresoc.v:41318$1736_Y - connect \$1563 $ternary$libresoc.v:41319$1737_Y - connect \$1565 $and$libresoc.v:41320$1738_Y - connect \$1568 $and$libresoc.v:41321$1739_Y - connect \$1571 $not$libresoc.v:41322$1740_Y - connect \$1573 $and$libresoc.v:41323$1741_Y - connect \$1576 $and$libresoc.v:41324$1742_Y - connect \$1579 $ternary$libresoc.v:41325$1743_Y - connect \$1582 $or$libresoc.v:41326$1744_Y - connect \$1584 $or$libresoc.v:41327$1745_Y - connect \$1586 $or$libresoc.v:41328$1746_Y - connect \$1581 $pos$libresoc.v:41329$1748_Y - connect \$1590 $or$libresoc.v:41330$1749_Y - connect \$1592 $or$libresoc.v:41331$1750_Y - connect \$1594 $or$libresoc.v:41332$1751_Y - connect \$1589 $pos$libresoc.v:41333$1753_Y - connect \$1597 $and$libresoc.v:41334$1754_Y - connect \$1599 $and$libresoc.v:41335$1755_Y - connect \$1601 $and$libresoc.v:41336$1756_Y - connect \$1603 $and$libresoc.v:41337$1757_Y - connect \$1605 $and$libresoc.v:41338$1758_Y - connect \$1607 $and$libresoc.v:41339$1759_Y - connect \$1610 $and$libresoc.v:41340$1760_Y - connect \$1614 $not$libresoc.v:41341$1761_Y - connect \$1616 $and$libresoc.v:41342$1762_Y - connect \$161 $and$libresoc.v:41343$1763_Y - connect \$1621 $and$libresoc.v:41344$1764_Y - connect \$1624 $ternary$libresoc.v:41345$1765_Y - connect \$1626 $and$libresoc.v:41346$1766_Y - connect \$160 $reduce_or$libresoc.v:41347$1767_Y - connect \$1629 $and$libresoc.v:41348$1768_Y - connect \$1632 $not$libresoc.v:41349$1769_Y - connect \$1634 $and$libresoc.v:41350$1770_Y - connect \$1637 $and$libresoc.v:41351$1771_Y - connect \$1640 $ternary$libresoc.v:41352$1772_Y - connect \$1642 $and$libresoc.v:41353$1773_Y - connect \$1645 $and$libresoc.v:41354$1774_Y - connect \$1648 $not$libresoc.v:41355$1775_Y - connect \$1650 $and$libresoc.v:41356$1776_Y - connect \$1653 $and$libresoc.v:41357$1777_Y - connect \$1656 $ternary$libresoc.v:41358$1778_Y - connect \$1658 $and$libresoc.v:41359$1779_Y - connect \$165 $and$libresoc.v:41360$1780_Y - connect \$1661 $and$libresoc.v:41361$1781_Y - connect \$1664 $not$libresoc.v:41362$1782_Y - connect \$1666 $and$libresoc.v:41363$1783_Y - connect \$164 $reduce_or$libresoc.v:41364$1784_Y - connect \$1669 $and$libresoc.v:41365$1785_Y - connect \$1672 $ternary$libresoc.v:41366$1786_Y - connect \$1674 $and$libresoc.v:41367$1787_Y - connect \$1677 $and$libresoc.v:41368$1788_Y - connect \$1680 $not$libresoc.v:41369$1789_Y - connect \$1682 $and$libresoc.v:41370$1790_Y - connect \$1685 $and$libresoc.v:41371$1791_Y - connect \$1688 $ternary$libresoc.v:41372$1792_Y - connect \$1690 $or$libresoc.v:41373$1793_Y - connect \$1692 $or$libresoc.v:41374$1794_Y - connect \$1694 $or$libresoc.v:41375$1795_Y - connect \$1696 $or$libresoc.v:41376$1796_Y - connect \$1698 $or$libresoc.v:41377$1797_Y - connect \$169 $and$libresoc.v:41378$1798_Y - connect \$1700 $or$libresoc.v:41379$1799_Y - connect \$1702 $or$libresoc.v:41380$1800_Y - connect \$1704 $or$libresoc.v:41381$1801_Y - connect \$1706 $or$libresoc.v:41382$1802_Y - connect \$1708 $or$libresoc.v:41383$1803_Y - connect \$168 $reduce_or$libresoc.v:41384$1804_Y - connect \$1710 $or$libresoc.v:41385$1805_Y - connect \$1712 $or$libresoc.v:41386$1806_Y - connect \$1714 $and$libresoc.v:41387$1807_Y - connect \$1716 $and$libresoc.v:41388$1808_Y - connect \$1718 $and$libresoc.v:41389$1809_Y - connect \$1721 $and$libresoc.v:41390$1810_Y - connect \$1724 $not$libresoc.v:41391$1811_Y - connect \$1726 $and$libresoc.v:41392$1812_Y - connect \$1729 $and$libresoc.v:41393$1813_Y - connect \$1732 $ternary$libresoc.v:41394$1814_Y - connect \$1734 $and$libresoc.v:41395$1815_Y - connect \$1737 $and$libresoc.v:41396$1816_Y - connect \$173 $and$libresoc.v:41397$1817_Y - connect \$1740 $not$libresoc.v:41398$1818_Y - connect \$1742 $and$libresoc.v:41399$1819_Y - connect \$1745 $and$libresoc.v:41400$1820_Y - connect \$1748 $ternary$libresoc.v:41401$1821_Y - connect \$172 $reduce_or$libresoc.v:41402$1822_Y - connect \$1750 $or$libresoc.v:41403$1823_Y - connect \$1753 $or$libresoc.v:41404$1824_Y - connect \$1752 $pos$libresoc.v:41405$1826_Y - connect \$1756 $and$libresoc.v:41406$1827_Y - connect \$1758 $and$libresoc.v:41407$1828_Y - connect \$1761 $and$libresoc.v:41408$1829_Y - connect \$1764 $not$libresoc.v:41409$1830_Y - connect \$1766 $and$libresoc.v:41410$1831_Y - connect \$1769 $and$libresoc.v:41411$1832_Y - connect \$1772 $ternary$libresoc.v:41412$1833_Y - connect \$1774 $pos$libresoc.v:41413$1835_Y - connect \$1776 $and$libresoc.v:41414$1836_Y - connect \$1778 $and$libresoc.v:41415$1837_Y - connect \$177 $and$libresoc.v:41416$1838_Y - connect \$1781 $and$libresoc.v:41417$1839_Y - connect \$1784 $not$libresoc.v:41418$1840_Y - connect \$1786 $and$libresoc.v:41419$1841_Y - connect \$176 $reduce_or$libresoc.v:41420$1842_Y - connect \$1789 $and$libresoc.v:41421$1843_Y - connect \$1792 $ternary$libresoc.v:41422$1844_Y - connect \$181 $and$libresoc.v:41423$1845_Y - connect \$180 $reduce_or$libresoc.v:41424$1846_Y - connect \$185 $and$libresoc.v:41425$1847_Y - connect \$184 $reduce_or$libresoc.v:41426$1848_Y - connect \$189 $and$libresoc.v:41427$1849_Y - connect \$188 $reduce_or$libresoc.v:41428$1850_Y - connect \$193 $and$libresoc.v:41429$1851_Y - connect \$192 $reduce_or$libresoc.v:41430$1852_Y - connect \$197 $and$libresoc.v:41431$1853_Y - connect \$196 $reduce_or$libresoc.v:41432$1854_Y - connect \$200 $ne$libresoc.v:41433$1855_Y - connect \$203 $sub$libresoc.v:41434$1856_Y - connect \$205 $ne$libresoc.v:41435$1857_Y - connect \$208 $and$libresoc.v:41436$1858_Y - connect \$210 $and$libresoc.v:41437$1859_Y - connect \$212 $eq$libresoc.v:41438$1860_Y - connect \$214 $or$libresoc.v:41439$1861_Y - connect \$216 $and$libresoc.v:41440$1862_Y - connect \$218 $or$libresoc.v:41441$1863_Y - connect \$220 $eq$libresoc.v:41442$1864_Y - connect \$222 $and$libresoc.v:41443$1865_Y - connect \$224 $eq$libresoc.v:41444$1866_Y - connect \$226 $or$libresoc.v:41445$1867_Y - connect \$207 $not$libresoc.v:41446$1868_Y - connect \$229 $not$libresoc.v:41447$1869_Y - connect \$231 $not$libresoc.v:41448$1870_Y - connect \$233 $not$libresoc.v:41449$1871_Y - connect \$236 $and$libresoc.v:41450$1872_Y - connect \$238 $and$libresoc.v:41451$1873_Y - connect \$240 $eq$libresoc.v:41452$1874_Y - connect \$242 $or$libresoc.v:41453$1875_Y - connect \$244 $and$libresoc.v:41454$1876_Y - connect \$246 $or$libresoc.v:41455$1877_Y - connect \$235 $not$libresoc.v:41456$1878_Y - connect \$250 $and$libresoc.v:41457$1879_Y - connect \$252 $and$libresoc.v:41458$1880_Y - connect \$254 $eq$libresoc.v:41459$1881_Y - connect \$256 $or$libresoc.v:41460$1882_Y - connect \$258 $and$libresoc.v:41461$1883_Y - connect \$260 $or$libresoc.v:41462$1884_Y - connect \$262 $and$libresoc.v:41463$1885_Y - connect \$264 $and$libresoc.v:41464$1886_Y - connect \$266 $eq$libresoc.v:41465$1887_Y - connect \$268 $or$libresoc.v:41466$1888_Y - connect \$270 $eq$libresoc.v:41467$1889_Y - connect \$272 $and$libresoc.v:41468$1890_Y - connect \$274 $eq$libresoc.v:41469$1891_Y - connect \$276 $or$libresoc.v:41470$1892_Y - connect \$249 $not$libresoc.v:41471$1893_Y - connect \$280 $and$libresoc.v:41472$1894_Y - connect \$282 $and$libresoc.v:41473$1895_Y - connect \$284 $eq$libresoc.v:41474$1896_Y - connect \$286 $or$libresoc.v:41475$1897_Y - connect \$288 $and$libresoc.v:41476$1898_Y - connect \$290 $or$libresoc.v:41477$1899_Y - connect \$279 $not$libresoc.v:41478$1900_Y - connect \$294 $and$libresoc.v:41479$1901_Y - connect \$296 $and$libresoc.v:41480$1902_Y - connect \$298 $eq$libresoc.v:41481$1903_Y - connect \$300 $or$libresoc.v:41482$1904_Y - connect \$302 $and$libresoc.v:41483$1905_Y - connect \$304 $or$libresoc.v:41484$1906_Y - connect \$293 $not$libresoc.v:41485$1907_Y - connect \$308 $and$libresoc.v:41486$1908_Y - connect \$310 $and$libresoc.v:41487$1909_Y - connect \$312 $eq$libresoc.v:41488$1910_Y - connect \$314 $or$libresoc.v:41489$1911_Y - connect \$316 $and$libresoc.v:41490$1912_Y - connect \$318 $or$libresoc.v:41491$1913_Y - connect \$320 $eq$libresoc.v:41492$1914_Y - connect \$322 $and$libresoc.v:41493$1915_Y - connect \$324 $eq$libresoc.v:41494$1916_Y - connect \$326 $or$libresoc.v:41495$1917_Y - connect \$307 $not$libresoc.v:41496$1918_Y - connect \$329 $not$libresoc.v:41497$1919_Y - connect \$331 $and$libresoc.v:41498$1920_Y - connect \$333 $and$libresoc.v:41499$1921_Y - connect \$335 $not$libresoc.v:41500$1922_Y - connect \$337 $and$libresoc.v:41501$1923_Y - connect \$339 $and$libresoc.v:41502$1924_Y - connect \$341 $ternary$libresoc.v:41503$1925_Y - connect \$343 $and$libresoc.v:41504$1926_Y - connect \$345 $and$libresoc.v:41505$1927_Y - connect \$347 $not$libresoc.v:41506$1928_Y - connect \$349 $and$libresoc.v:41507$1929_Y - connect \$351 $and$libresoc.v:41508$1930_Y - connect \$353 $ternary$libresoc.v:41509$1931_Y - connect \$355 $and$libresoc.v:41510$1932_Y - connect \$357 $and$libresoc.v:41511$1933_Y - connect \$359 $not$libresoc.v:41512$1934_Y - connect \$361 $and$libresoc.v:41513$1935_Y - connect \$363 $and$libresoc.v:41514$1936_Y - connect \$365 $ternary$libresoc.v:41515$1937_Y - connect \$367 $and$libresoc.v:41516$1938_Y - connect \$369 $and$libresoc.v:41517$1939_Y - connect \$371 $not$libresoc.v:41518$1940_Y - connect \$373 $and$libresoc.v:41519$1941_Y - connect \$375 $and$libresoc.v:41520$1942_Y - connect \$377 $ternary$libresoc.v:41521$1943_Y - connect \$379 $and$libresoc.v:41522$1944_Y - connect \$381 $and$libresoc.v:41523$1945_Y - connect \$383 $not$libresoc.v:41524$1946_Y - connect \$385 $and$libresoc.v:41525$1947_Y - connect \$387 $and$libresoc.v:41526$1948_Y - connect \$389 $ternary$libresoc.v:41527$1949_Y - connect \$391 $and$libresoc.v:41528$1950_Y - connect \$393 $and$libresoc.v:41529$1951_Y - connect \$395 $not$libresoc.v:41530$1952_Y - connect \$397 $and$libresoc.v:41531$1953_Y - connect \$399 $and$libresoc.v:41532$1954_Y - connect \$401 $ternary$libresoc.v:41533$1955_Y - connect \$403 $and$libresoc.v:41534$1956_Y - connect \$405 $and$libresoc.v:41535$1957_Y - connect \$407 $not$libresoc.v:41536$1958_Y - connect \$409 $and$libresoc.v:41537$1959_Y - connect \$411 $and$libresoc.v:41538$1960_Y - connect \$413 $ternary$libresoc.v:41539$1961_Y - connect \$415 $and$libresoc.v:41540$1962_Y - connect \$417 $and$libresoc.v:41541$1963_Y - connect \$419 $not$libresoc.v:41542$1964_Y - connect \$421 $and$libresoc.v:41543$1965_Y - connect \$423 $and$libresoc.v:41544$1966_Y - connect \$425 $ternary$libresoc.v:41545$1967_Y - connect \$427 $and$libresoc.v:41546$1968_Y - connect \$429 $and$libresoc.v:41547$1969_Y - connect \$431 $not$libresoc.v:41548$1970_Y - connect \$433 $and$libresoc.v:41549$1971_Y - connect \$435 $and$libresoc.v:41550$1972_Y - connect \$437 $ternary$libresoc.v:41551$1973_Y - connect \$439 $or$libresoc.v:41552$1974_Y - connect \$441 $or$libresoc.v:41553$1975_Y - connect \$443 $or$libresoc.v:41554$1976_Y - connect \$445 $or$libresoc.v:41555$1977_Y - connect \$447 $or$libresoc.v:41556$1978_Y - connect \$449 $or$libresoc.v:41557$1979_Y - connect \$451 $or$libresoc.v:41558$1980_Y - connect \$453 $or$libresoc.v:41559$1981_Y - connect \$455 $reduce_or$libresoc.v:41560$1982_Y - connect \$457 $and$libresoc.v:41561$1983_Y - connect \$459 $and$libresoc.v:41562$1984_Y - connect \$461 $not$libresoc.v:41563$1985_Y - connect \$463 $and$libresoc.v:41564$1986_Y - connect \$465 $and$libresoc.v:41565$1987_Y - connect \$467 $ternary$libresoc.v:41566$1988_Y - connect \$469 $and$libresoc.v:41567$1989_Y - connect \$471 $and$libresoc.v:41568$1990_Y - connect \$473 $not$libresoc.v:41569$1991_Y - connect \$475 $and$libresoc.v:41570$1992_Y - connect \$477 $and$libresoc.v:41571$1993_Y - connect \$479 $ternary$libresoc.v:41572$1994_Y - connect \$481 $and$libresoc.v:41573$1995_Y - connect \$483 $and$libresoc.v:41574$1996_Y - connect \$485 $not$libresoc.v:41575$1997_Y - connect \$487 $and$libresoc.v:41576$1998_Y - connect \$489 $and$libresoc.v:41577$1999_Y - connect \$491 $ternary$libresoc.v:41578$2000_Y - connect \$493 $and$libresoc.v:41579$2001_Y - connect \$495 $and$libresoc.v:41580$2002_Y - connect \$497 $not$libresoc.v:41581$2003_Y - connect \$499 $and$libresoc.v:41582$2004_Y - connect \$501 $and$libresoc.v:41583$2005_Y - connect \$503 $ternary$libresoc.v:41584$2006_Y - connect \$505 $and$libresoc.v:41585$2007_Y - connect \$507 $and$libresoc.v:41586$2008_Y - connect \$509 $not$libresoc.v:41587$2009_Y - connect \$511 $and$libresoc.v:41588$2010_Y - connect \$513 $and$libresoc.v:41589$2011_Y - connect \$515 $ternary$libresoc.v:41590$2012_Y - connect \$517 $and$libresoc.v:41591$2013_Y - connect \$519 $and$libresoc.v:41592$2014_Y - connect \$521 $not$libresoc.v:41593$2015_Y - connect \$523 $and$libresoc.v:41594$2016_Y - connect \$525 $and$libresoc.v:41595$2017_Y - connect \$527 $ternary$libresoc.v:41596$2018_Y - connect \$529 $and$libresoc.v:41597$2019_Y - connect \$531 $and$libresoc.v:41598$2020_Y - connect \$533 $not$libresoc.v:41599$2021_Y - connect \$535 $and$libresoc.v:41600$2022_Y - connect \$537 $and$libresoc.v:41601$2023_Y - connect \$539 $ternary$libresoc.v:41602$2024_Y - connect \$541 $and$libresoc.v:41603$2025_Y - connect \$543 $and$libresoc.v:41604$2026_Y - connect \$545 $not$libresoc.v:41605$2027_Y - connect \$547 $and$libresoc.v:41606$2028_Y - connect \$549 $and$libresoc.v:41607$2029_Y - connect \$551 $ternary$libresoc.v:41608$2030_Y - connect \$553 $or$libresoc.v:41609$2031_Y - connect \$555 $or$libresoc.v:41610$2032_Y - connect \$557 $or$libresoc.v:41611$2033_Y - connect \$559 $or$libresoc.v:41612$2034_Y - connect \$561 $or$libresoc.v:41613$2035_Y - connect \$563 $or$libresoc.v:41614$2036_Y - connect \$565 $or$libresoc.v:41615$2037_Y - connect \$567 $reduce_or$libresoc.v:41616$2038_Y - connect \$569 $and$libresoc.v:41617$2039_Y - connect \$571 $and$libresoc.v:41618$2040_Y - connect \$573 $not$libresoc.v:41619$2041_Y - connect \$575 $and$libresoc.v:41620$2042_Y - connect \$577 $and$libresoc.v:41621$2043_Y - connect \$579 $ternary$libresoc.v:41622$2044_Y - connect \$581 $and$libresoc.v:41623$2045_Y - connect \$583 $and$libresoc.v:41624$2046_Y - connect \$585 $not$libresoc.v:41625$2047_Y - connect \$587 $and$libresoc.v:41626$2048_Y - connect \$589 $and$libresoc.v:41627$2049_Y - connect \$591 $ternary$libresoc.v:41628$2050_Y - connect \$593 $or$libresoc.v:41629$2051_Y - connect \$595 $reduce_or$libresoc.v:41630$2052_Y - connect \$597 $and$libresoc.v:41631$2053_Y - connect \$599 $and$libresoc.v:41632$2054_Y - connect \$601 $eq$libresoc.v:41633$2055_Y - connect \$603 $or$libresoc.v:41634$2056_Y - connect \$605 $and$libresoc.v:41635$2057_Y - connect \$607 $or$libresoc.v:41636$2058_Y - connect \$609 $and$libresoc.v:41637$2059_Y - connect \$611 $and$libresoc.v:41638$2060_Y - connect \$613 $not$libresoc.v:41639$2061_Y - connect \$615 $and$libresoc.v:41640$2062_Y - connect \$617 $and$libresoc.v:41641$2063_Y - connect \$619 $ternary$libresoc.v:41642$2064_Y - connect \$621 $and$libresoc.v:41643$2065_Y - connect \$623 $and$libresoc.v:41644$2066_Y - connect \$625 $not$libresoc.v:41645$2067_Y - connect \$627 $and$libresoc.v:41646$2068_Y - connect \$629 $and$libresoc.v:41647$2069_Y - connect \$631 $ternary$libresoc.v:41648$2070_Y - connect \$633 $and$libresoc.v:41649$2071_Y - connect \$635 $and$libresoc.v:41650$2072_Y - connect \$637 $not$libresoc.v:41651$2073_Y - connect \$639 $and$libresoc.v:41652$2074_Y - connect \$641 $and$libresoc.v:41653$2075_Y - connect \$643 $ternary$libresoc.v:41654$2076_Y - connect \$645 $and$libresoc.v:41655$2077_Y - connect \$647 $and$libresoc.v:41656$2078_Y - connect \$649 $not$libresoc.v:41657$2079_Y - connect \$651 $and$libresoc.v:41658$2080_Y - connect \$653 $and$libresoc.v:41659$2081_Y - connect \$655 $ternary$libresoc.v:41660$2082_Y - connect \$657 $and$libresoc.v:41661$2083_Y - connect \$659 $and$libresoc.v:41662$2084_Y - connect \$661 $not$libresoc.v:41663$2085_Y - connect \$663 $and$libresoc.v:41664$2086_Y - connect \$665 $and$libresoc.v:41665$2087_Y - connect \$667 $ternary$libresoc.v:41666$2088_Y - connect \$669 $and$libresoc.v:41667$2089_Y - connect \$671 $and$libresoc.v:41668$2090_Y - connect \$673 $not$libresoc.v:41669$2091_Y - connect \$675 $and$libresoc.v:41670$2092_Y - connect \$677 $and$libresoc.v:41671$2093_Y - connect \$679 $ternary$libresoc.v:41672$2094_Y - connect \$682 $or$libresoc.v:41673$2095_Y - connect \$684 $or$libresoc.v:41674$2096_Y - connect \$686 $or$libresoc.v:41675$2097_Y - connect \$688 $or$libresoc.v:41676$2098_Y - connect \$690 $or$libresoc.v:41677$2099_Y - connect \$681 $pos$libresoc.v:41678$2101_Y - connect \$693 $eq$libresoc.v:41679$2102_Y - connect \$695 $and$libresoc.v:41680$2103_Y - connect \$697 $eq$libresoc.v:41681$2104_Y - connect \$699 $or$libresoc.v:41682$2105_Y - connect \$701 $and$libresoc.v:41683$2106_Y - connect \$703 $and$libresoc.v:41684$2107_Y - connect \$705 $not$libresoc.v:41685$2108_Y - connect \$707 $and$libresoc.v:41686$2109_Y - connect \$709 $and$libresoc.v:41687$2110_Y - connect \$711 $ternary$libresoc.v:41688$2111_Y - connect \$713 $and$libresoc.v:41689$2112_Y - connect \$715 $and$libresoc.v:41690$2113_Y - connect \$717 $not$libresoc.v:41691$2114_Y - connect \$719 $and$libresoc.v:41692$2115_Y - connect \$721 $and$libresoc.v:41693$2116_Y - connect \$723 $ternary$libresoc.v:41694$2117_Y - connect \$725 $and$libresoc.v:41695$2118_Y - connect \$727 $and$libresoc.v:41696$2119_Y - connect \$729 $not$libresoc.v:41697$2120_Y - connect \$731 $and$libresoc.v:41698$2121_Y - connect \$733 $and$libresoc.v:41699$2122_Y - connect \$735 $ternary$libresoc.v:41700$2123_Y - connect \$738 $or$libresoc.v:41701$2124_Y - connect \$740 $or$libresoc.v:41702$2125_Y - connect \$737 $pos$libresoc.v:41703$2127_Y - connect \$743 $and$libresoc.v:41704$2128_Y - connect \$745 $and$libresoc.v:41705$2129_Y - connect \$747 $eq$libresoc.v:41706$2130_Y - connect \$749 $or$libresoc.v:41707$2131_Y - connect \$751 $and$libresoc.v:41708$2132_Y - connect \$753 $and$libresoc.v:41709$2133_Y - connect \$755 $not$libresoc.v:41710$2134_Y - connect \$757 $and$libresoc.v:41711$2135_Y - connect \$759 $and$libresoc.v:41712$2136_Y - connect \$761 $ternary$libresoc.v:41713$2137_Y - connect \$763 $and$libresoc.v:41714$2138_Y - connect \$765 $and$libresoc.v:41715$2139_Y - connect \$767 $not$libresoc.v:41716$2140_Y - connect \$769 $and$libresoc.v:41717$2141_Y - connect \$771 $and$libresoc.v:41718$2142_Y - connect \$773 $ternary$libresoc.v:41719$2143_Y - connect \$775 $and$libresoc.v:41720$2144_Y - connect \$777 $and$libresoc.v:41721$2145_Y - connect \$779 $not$libresoc.v:41722$2146_Y - connect \$781 $and$libresoc.v:41723$2147_Y - connect \$783 $and$libresoc.v:41724$2148_Y - connect \$785 $sub$libresoc.v:41725$2149_Y - connect \$787 $sshl$libresoc.v:41726$2150_Y - connect \$789 $ternary$libresoc.v:41727$2151_Y - connect \$791 $and$libresoc.v:41728$2152_Y - connect \$793 $and$libresoc.v:41729$2153_Y - connect \$795 $not$libresoc.v:41730$2154_Y - connect \$797 $and$libresoc.v:41731$2155_Y - connect \$799 $and$libresoc.v:41732$2156_Y - connect \$801 $sub$libresoc.v:41733$2157_Y - connect \$803 $sshl$libresoc.v:41734$2158_Y - connect \$805 $ternary$libresoc.v:41735$2159_Y - connect \$808 $or$libresoc.v:41736$2160_Y - connect \$810 $and$libresoc.v:41737$2161_Y - connect \$812 $and$libresoc.v:41738$2162_Y - connect \$814 $not$libresoc.v:41739$2163_Y - connect \$816 $and$libresoc.v:41740$2164_Y - connect \$818 $and$libresoc.v:41741$2165_Y - connect \$820 $sub$libresoc.v:41742$2166_Y - connect \$822 $sshl$libresoc.v:41743$2167_Y - connect \$824 $ternary$libresoc.v:41744$2168_Y - connect \$826 $and$libresoc.v:41745$2169_Y - connect \$828 $and$libresoc.v:41746$2170_Y - connect \$830 $not$libresoc.v:41747$2171_Y - connect \$832 $and$libresoc.v:41748$2172_Y - connect \$834 $and$libresoc.v:41749$2173_Y - connect \$836 $sub$libresoc.v:41750$2174_Y - connect \$838 $sshl$libresoc.v:41751$2175_Y - connect \$840 $ternary$libresoc.v:41752$2176_Y - connect \$842 $and$libresoc.v:41753$2177_Y - connect \$844 $and$libresoc.v:41754$2178_Y - connect \$846 $not$libresoc.v:41755$2179_Y - connect \$848 $and$libresoc.v:41756$2180_Y - connect \$850 $and$libresoc.v:41757$2181_Y - connect \$852 $ternary$libresoc.v:41758$2182_Y - connect \$854 $and$libresoc.v:41759$2183_Y - connect \$856 $and$libresoc.v:41760$2184_Y - connect \$858 $not$libresoc.v:41761$2185_Y - connect \$860 $and$libresoc.v:41762$2186_Y - connect \$862 $and$libresoc.v:41763$2187_Y - connect \$864 $ternary$libresoc.v:41764$2188_Y - connect \$866 $and$libresoc.v:41765$2189_Y - connect \$868 $and$libresoc.v:41766$2190_Y - connect \$870 $not$libresoc.v:41767$2191_Y - connect \$872 $and$libresoc.v:41768$2192_Y - connect \$874 $and$libresoc.v:41769$2193_Y - connect \$876 $ternary$libresoc.v:41770$2194_Y - connect \$878 $or$libresoc.v:41771$2195_Y - connect \$880 $or$libresoc.v:41772$2196_Y - connect \$882 $reduce_or$libresoc.v:41773$2197_Y - connect \$884 $and$libresoc.v:41774$2198_Y - connect \$886 $and$libresoc.v:41775$2199_Y - connect \$888 $not$libresoc.v:41776$2200_Y - connect \$890 $and$libresoc.v:41777$2201_Y - connect \$892 $and$libresoc.v:41778$2202_Y - connect \$894 $ternary$libresoc.v:41779$2203_Y - connect \$896 $and$libresoc.v:41780$2204_Y - connect \$898 $and$libresoc.v:41781$2205_Y - connect \$900 $not$libresoc.v:41782$2206_Y - connect \$902 $and$libresoc.v:41783$2207_Y - connect \$904 $and$libresoc.v:41784$2208_Y - connect \$906 $ternary$libresoc.v:41785$2209_Y - connect \$908 $or$libresoc.v:41786$2210_Y - connect \$910 $reduce_or$libresoc.v:41787$2211_Y - connect \$912 $and$libresoc.v:41788$2212_Y - connect \$914 $and$libresoc.v:41789$2213_Y - connect \$916 $not$libresoc.v:41790$2214_Y - connect \$918 $and$libresoc.v:41791$2215_Y - connect \$920 $and$libresoc.v:41792$2216_Y - connect \$922 $ternary$libresoc.v:41793$2217_Y - connect \$924 $reduce_or$libresoc.v:41794$2218_Y - connect \$926 $and$libresoc.v:41795$2219_Y - connect \$928 $and$libresoc.v:41796$2220_Y - connect \$930 $and$libresoc.v:41797$2221_Y - connect \$932 $and$libresoc.v:41798$2222_Y - connect \$934 $and$libresoc.v:41799$2223_Y - connect \$936 $and$libresoc.v:41800$2224_Y - connect \$938 $and$libresoc.v:41801$2225_Y - connect \$940 $and$libresoc.v:41802$2226_Y - connect \$942 $and$libresoc.v:41803$2227_Y - connect \$944 $and$libresoc.v:41804$2228_Y - connect \$946 $and$libresoc.v:41805$2229_Y - connect \$948 $and$libresoc.v:41806$2230_Y - connect \$950 $not$libresoc.v:41807$2231_Y - connect \$952 $and$libresoc.v:41808$2232_Y - connect \$958 $and$libresoc.v:41809$2233_Y - connect \$960 $ternary$libresoc.v:41810$2234_Y - connect \$962 $and$libresoc.v:41811$2235_Y - connect \$965 $and$libresoc.v:41812$2236_Y - connect \$969 $not$libresoc.v:41813$2237_Y - connect \$971 $and$libresoc.v:41814$2238_Y - connect \$976 $and$libresoc.v:41815$2239_Y - connect \$979 $ternary$libresoc.v:41816$2240_Y - connect \$981 $and$libresoc.v:41817$2241_Y - connect \$984 $and$libresoc.v:41818$2242_Y - connect \$988 $not$libresoc.v:41819$2243_Y - connect \$990 $and$libresoc.v:41820$2244_Y - connect \$997 $and$libresoc.v:41821$2245_Y - connect \$202 \$203 - connect \$807 \$808 - connect \$1135 \$1152 - connect \$1350 \$1359 + connect \$1002 $not$libresoc.v:41720$1546_Y + connect \$1004 $and$libresoc.v:41721$1547_Y + connect \$1011 $and$libresoc.v:41722$1548_Y + connect \$1014 $ternary$libresoc.v:41723$1549_Y + connect \$1016 $and$libresoc.v:41724$1550_Y + connect \$1019 $and$libresoc.v:41725$1551_Y + connect \$1023 $not$libresoc.v:41726$1552_Y + connect \$1025 $and$libresoc.v:41727$1553_Y + connect \$1029 $and$libresoc.v:41728$1554_Y + connect \$1032 $ternary$libresoc.v:41729$1555_Y + connect \$1034 $and$libresoc.v:41730$1556_Y + connect \$1037 $and$libresoc.v:41731$1557_Y + connect \$1041 $not$libresoc.v:41732$1558_Y + connect \$1043 $and$libresoc.v:41733$1559_Y + connect \$1051 $and$libresoc.v:41734$1560_Y + connect \$1054 $ternary$libresoc.v:41735$1561_Y + connect \$1056 $and$libresoc.v:41736$1562_Y + connect \$1059 $and$libresoc.v:41737$1563_Y + connect \$1063 $not$libresoc.v:41738$1564_Y + connect \$1065 $and$libresoc.v:41739$1565_Y + connect \$1071 $and$libresoc.v:41740$1566_Y + connect \$1074 $ternary$libresoc.v:41741$1567_Y + connect \$1076 $and$libresoc.v:41742$1568_Y + connect \$1079 $and$libresoc.v:41743$1569_Y + connect \$1083 $not$libresoc.v:41744$1570_Y + connect \$1085 $and$libresoc.v:41745$1571_Y + connect \$1091 $and$libresoc.v:41746$1572_Y + connect \$1094 $ternary$libresoc.v:41747$1573_Y + connect \$1096 $and$libresoc.v:41748$1574_Y + connect \$1099 $and$libresoc.v:41749$1575_Y + connect \$1103 $not$libresoc.v:41750$1576_Y + connect \$1105 $and$libresoc.v:41751$1577_Y + connect \$1110 $and$libresoc.v:41752$1578_Y + connect \$1113 $ternary$libresoc.v:41753$1579_Y + connect \$1115 $and$libresoc.v:41754$1580_Y + connect \$1118 $and$libresoc.v:41755$1581_Y + connect \$1122 $not$libresoc.v:41756$1582_Y + connect \$1124 $and$libresoc.v:41757$1583_Y + connect \$1128 $and$libresoc.v:41758$1584_Y + connect \$1131 $ternary$libresoc.v:41759$1585_Y + connect \$1133 $and$libresoc.v:41760$1586_Y + connect \$1136 $and$libresoc.v:41761$1587_Y + connect \$1139 $not$libresoc.v:41762$1588_Y + connect \$1141 $and$libresoc.v:41763$1589_Y + connect \$1144 $and$libresoc.v:41764$1590_Y + connect \$1147 $ternary$libresoc.v:41765$1591_Y + connect \$1150 $or$libresoc.v:41766$1592_Y + connect \$1152 $or$libresoc.v:41767$1593_Y + connect \$1154 $or$libresoc.v:41768$1594_Y + connect \$1156 $or$libresoc.v:41769$1595_Y + connect \$1158 $or$libresoc.v:41770$1596_Y + connect \$1160 $or$libresoc.v:41771$1597_Y + connect \$1162 $or$libresoc.v:41772$1598_Y + connect \$1164 $or$libresoc.v:41773$1599_Y + connect \$1166 $or$libresoc.v:41774$1600_Y + connect \$1168 $or$libresoc.v:41775$1601_Y + connect \$1170 $or$libresoc.v:41776$1602_Y + connect \$1172 $or$libresoc.v:41777$1603_Y + connect \$1174 $or$libresoc.v:41778$1604_Y + connect \$1176 $or$libresoc.v:41779$1605_Y + connect \$1178 $or$libresoc.v:41780$1606_Y + connect \$1180 $or$libresoc.v:41781$1607_Y + connect \$1182 $or$libresoc.v:41782$1608_Y + connect \$1184 $or$libresoc.v:41783$1609_Y + connect \$1186 $or$libresoc.v:41784$1610_Y + connect \$1188 $or$libresoc.v:41785$1611_Y + connect \$1190 $or$libresoc.v:41786$1612_Y + connect \$1192 $or$libresoc.v:41787$1613_Y + connect \$1194 $or$libresoc.v:41788$1614_Y + connect \$1196 $or$libresoc.v:41789$1615_Y + connect \$1198 $or$libresoc.v:41790$1616_Y + connect \$1200 $or$libresoc.v:41791$1617_Y + connect \$1202 $or$libresoc.v:41792$1618_Y + connect \$1204 $and$libresoc.v:41793$1619_Y + connect \$1206 $and$libresoc.v:41794$1620_Y + connect \$1209 $and$libresoc.v:41795$1621_Y + connect \$1212 $not$libresoc.v:41796$1622_Y + connect \$1214 $and$libresoc.v:41797$1623_Y + connect \$1217 $and$libresoc.v:41798$1624_Y + connect \$1220 $ternary$libresoc.v:41799$1625_Y + connect \$1222 $and$libresoc.v:41800$1626_Y + connect \$1224 $and$libresoc.v:41801$1627_Y + connect \$1226 $and$libresoc.v:41802$1628_Y + connect \$1228 $and$libresoc.v:41803$1629_Y + connect \$1230 $and$libresoc.v:41804$1630_Y + connect \$1232 $and$libresoc.v:41805$1631_Y + connect \$1234 $and$libresoc.v:41806$1632_Y + connect \$1237 $and$libresoc.v:41807$1633_Y + connect \$1240 $not$libresoc.v:41808$1634_Y + connect \$1242 $and$libresoc.v:41809$1635_Y + connect \$1245 $and$libresoc.v:41810$1636_Y + connect \$1248 $sub$libresoc.v:41811$1637_Y + connect \$1250 $sshl$libresoc.v:41812$1638_Y + connect \$1252 $ternary$libresoc.v:41813$1639_Y + connect \$1254 $and$libresoc.v:41814$1640_Y + connect \$1257 $and$libresoc.v:41815$1641_Y + connect \$1260 $not$libresoc.v:41816$1642_Y + connect \$1262 $and$libresoc.v:41817$1643_Y + connect \$1265 $and$libresoc.v:41818$1644_Y + connect \$1268 $sub$libresoc.v:41819$1645_Y + connect \$1270 $sshl$libresoc.v:41820$1646_Y + connect \$1272 $ternary$libresoc.v:41821$1647_Y + connect \$1274 $and$libresoc.v:41822$1648_Y + connect \$1277 $and$libresoc.v:41823$1649_Y + connect \$1280 $not$libresoc.v:41824$1650_Y + connect \$1282 $and$libresoc.v:41825$1651_Y + connect \$1285 $and$libresoc.v:41826$1652_Y + connect \$1288 $sub$libresoc.v:41827$1653_Y + connect \$1290 $sshl$libresoc.v:41828$1654_Y + connect \$1292 $ternary$libresoc.v:41829$1655_Y + connect \$1294 $and$libresoc.v:41830$1656_Y + connect \$1297 $and$libresoc.v:41831$1657_Y + connect \$1300 $not$libresoc.v:41832$1658_Y + connect \$1302 $and$libresoc.v:41833$1659_Y + connect \$1305 $and$libresoc.v:41834$1660_Y + connect \$1308 $sub$libresoc.v:41835$1661_Y + connect \$1310 $sshl$libresoc.v:41836$1662_Y + connect \$1312 $ternary$libresoc.v:41837$1663_Y + connect \$1314 $and$libresoc.v:41838$1664_Y + connect \$1317 $and$libresoc.v:41839$1665_Y + connect \$1320 $not$libresoc.v:41840$1666_Y + connect \$1322 $and$libresoc.v:41841$1667_Y + connect \$1325 $and$libresoc.v:41842$1668_Y + connect \$1328 $sub$libresoc.v:41843$1669_Y + connect \$1330 $sshl$libresoc.v:41844$1670_Y + connect \$1332 $ternary$libresoc.v:41845$1671_Y + connect \$1334 $and$libresoc.v:41846$1672_Y + connect \$1337 $and$libresoc.v:41847$1673_Y + connect \$1340 $not$libresoc.v:41848$1674_Y + connect \$1342 $and$libresoc.v:41849$1675_Y + connect \$1345 $and$libresoc.v:41850$1676_Y + connect \$1348 $sub$libresoc.v:41851$1677_Y + connect \$1350 $sshl$libresoc.v:41852$1678_Y + connect \$1352 $ternary$libresoc.v:41853$1679_Y + connect \$1354 $or$libresoc.v:41854$1680_Y + connect \$1356 $or$libresoc.v:41855$1681_Y + connect \$1358 $or$libresoc.v:41856$1682_Y + connect \$1360 $or$libresoc.v:41857$1683_Y + connect \$1362 $or$libresoc.v:41858$1684_Y + connect \$1365 $or$libresoc.v:41859$1685_Y + connect \$1367 $or$libresoc.v:41860$1686_Y + connect \$1369 $or$libresoc.v:41861$1687_Y + connect \$1371 $or$libresoc.v:41862$1688_Y + connect \$1373 $or$libresoc.v:41863$1689_Y + connect \$1375 $and$libresoc.v:41864$1690_Y + connect \$1377 $and$libresoc.v:41865$1691_Y + connect \$1379 $and$libresoc.v:41866$1692_Y + connect \$1381 $and$libresoc.v:41867$1693_Y + connect \$1384 $and$libresoc.v:41868$1694_Y + connect \$1387 $not$libresoc.v:41869$1695_Y + connect \$1389 $and$libresoc.v:41870$1696_Y + connect \$1392 $and$libresoc.v:41871$1697_Y + connect \$1395 $ternary$libresoc.v:41872$1698_Y + connect \$1397 $and$libresoc.v:41873$1699_Y + connect \$1400 $and$libresoc.v:41874$1700_Y + connect \$1403 $not$libresoc.v:41875$1701_Y + connect \$1405 $and$libresoc.v:41876$1702_Y + connect \$1408 $and$libresoc.v:41877$1703_Y + connect \$1411 $ternary$libresoc.v:41878$1704_Y + connect \$1413 $and$libresoc.v:41879$1705_Y + connect \$1416 $and$libresoc.v:41880$1706_Y + connect \$1419 $not$libresoc.v:41881$1707_Y + connect \$1421 $and$libresoc.v:41882$1708_Y + connect \$1424 $and$libresoc.v:41883$1709_Y + connect \$1427 $ternary$libresoc.v:41884$1710_Y + connect \$1429 $or$libresoc.v:41885$1711_Y + connect \$1431 $or$libresoc.v:41886$1712_Y + connect \$1434 $or$libresoc.v:41887$1713_Y + connect \$1436 $or$libresoc.v:41888$1714_Y + connect \$1433 $pos$libresoc.v:41889$1716_Y + connect \$1439 $and$libresoc.v:41890$1717_Y + connect \$1441 $and$libresoc.v:41891$1718_Y + connect \$1443 $and$libresoc.v:41892$1719_Y + connect \$1445 $and$libresoc.v:41893$1720_Y + connect \$1447 $and$libresoc.v:41894$1721_Y + connect \$1450 $and$libresoc.v:41895$1722_Y + connect \$1453 $not$libresoc.v:41896$1723_Y + connect \$1455 $and$libresoc.v:41897$1724_Y + connect \$1458 $and$libresoc.v:41898$1725_Y + connect \$1461 $ternary$libresoc.v:41899$1726_Y + connect \$1463 $and$libresoc.v:41900$1727_Y + connect \$1466 $and$libresoc.v:41901$1728_Y + connect \$1469 $not$libresoc.v:41902$1729_Y + connect \$1471 $and$libresoc.v:41903$1730_Y + connect \$1474 $and$libresoc.v:41904$1731_Y + connect \$1477 $ternary$libresoc.v:41905$1732_Y + connect \$1479 $and$libresoc.v:41906$1733_Y + connect \$1482 $and$libresoc.v:41907$1734_Y + connect \$1485 $not$libresoc.v:41908$1735_Y + connect \$1487 $and$libresoc.v:41909$1736_Y + connect \$1490 $and$libresoc.v:41910$1737_Y + connect \$1493 $ternary$libresoc.v:41911$1738_Y + connect \$1495 $and$libresoc.v:41912$1739_Y + connect \$1498 $and$libresoc.v:41913$1740_Y + connect \$1501 $not$libresoc.v:41914$1741_Y + connect \$1503 $and$libresoc.v:41915$1742_Y + connect \$1506 $and$libresoc.v:41916$1743_Y + connect \$1509 $ternary$libresoc.v:41917$1744_Y + connect \$1511 $or$libresoc.v:41918$1745_Y + connect \$1513 $or$libresoc.v:41919$1746_Y + connect \$1515 $or$libresoc.v:41920$1747_Y + connect \$1517 $or$libresoc.v:41921$1748_Y + connect \$1519 $or$libresoc.v:41922$1749_Y + connect \$1521 $or$libresoc.v:41923$1750_Y + connect \$1523 $and$libresoc.v:41924$1751_Y + connect \$1525 $and$libresoc.v:41925$1752_Y + connect \$1527 $and$libresoc.v:41926$1753_Y + connect \$1529 $and$libresoc.v:41927$1754_Y + connect \$1531 $and$libresoc.v:41928$1755_Y + connect \$1534 $and$libresoc.v:41929$1756_Y + connect \$1537 $not$libresoc.v:41930$1757_Y + connect \$1539 $and$libresoc.v:41931$1758_Y + connect \$1542 $and$libresoc.v:41932$1759_Y + connect \$1545 $ternary$libresoc.v:41933$1760_Y + connect \$1547 $and$libresoc.v:41934$1761_Y + connect \$1550 $and$libresoc.v:41935$1762_Y + connect \$1553 $not$libresoc.v:41936$1763_Y + connect \$1555 $and$libresoc.v:41937$1764_Y + connect \$1558 $and$libresoc.v:41938$1765_Y + connect \$1561 $ternary$libresoc.v:41939$1766_Y + connect \$1563 $and$libresoc.v:41940$1767_Y + connect \$1566 $and$libresoc.v:41941$1768_Y + connect \$1569 $not$libresoc.v:41942$1769_Y + connect \$1571 $and$libresoc.v:41943$1770_Y + connect \$1574 $and$libresoc.v:41944$1771_Y + connect \$1577 $ternary$libresoc.v:41945$1772_Y + connect \$1579 $and$libresoc.v:41946$1773_Y + connect \$1582 $and$libresoc.v:41947$1774_Y + connect \$1585 $not$libresoc.v:41948$1775_Y + connect \$1587 $and$libresoc.v:41949$1776_Y + connect \$1590 $and$libresoc.v:41950$1777_Y + connect \$1593 $ternary$libresoc.v:41951$1778_Y + connect \$1596 $or$libresoc.v:41952$1779_Y + connect \$1598 $or$libresoc.v:41953$1780_Y + connect \$1600 $or$libresoc.v:41954$1781_Y + connect \$1595 $pos$libresoc.v:41955$1783_Y + connect \$1604 $or$libresoc.v:41956$1784_Y + connect \$1606 $or$libresoc.v:41957$1785_Y + connect \$1608 $or$libresoc.v:41958$1786_Y + connect \$1603 $pos$libresoc.v:41959$1788_Y + connect \$1611 $and$libresoc.v:41960$1789_Y + connect \$1613 $and$libresoc.v:41961$1790_Y + connect \$1615 $and$libresoc.v:41962$1791_Y + connect \$1617 $and$libresoc.v:41963$1792_Y + connect \$1619 $and$libresoc.v:41964$1793_Y + connect \$1621 $and$libresoc.v:41965$1794_Y + connect \$1624 $and$libresoc.v:41966$1795_Y + connect \$1628 $not$libresoc.v:41967$1796_Y + connect \$1630 $and$libresoc.v:41968$1797_Y + connect \$1635 $and$libresoc.v:41969$1798_Y + connect \$1638 $ternary$libresoc.v:41970$1799_Y + connect \$1640 $and$libresoc.v:41971$1800_Y + connect \$1643 $and$libresoc.v:41972$1801_Y + connect \$1646 $not$libresoc.v:41973$1802_Y + connect \$1648 $and$libresoc.v:41974$1803_Y + connect \$1651 $and$libresoc.v:41975$1804_Y + connect \$1654 $ternary$libresoc.v:41976$1805_Y + connect \$1656 $and$libresoc.v:41977$1806_Y + connect \$1659 $and$libresoc.v:41978$1807_Y + connect \$1662 $not$libresoc.v:41979$1808_Y + connect \$1664 $and$libresoc.v:41980$1809_Y + connect \$1667 $and$libresoc.v:41981$1810_Y + connect \$1670 $ternary$libresoc.v:41982$1811_Y + connect \$1672 $and$libresoc.v:41983$1812_Y + connect \$1675 $and$libresoc.v:41984$1813_Y + connect \$1678 $not$libresoc.v:41985$1814_Y + connect \$1680 $and$libresoc.v:41986$1815_Y + connect \$1683 $and$libresoc.v:41987$1816_Y + connect \$1686 $ternary$libresoc.v:41988$1817_Y + connect \$1688 $and$libresoc.v:41989$1818_Y + connect \$1691 $and$libresoc.v:41990$1819_Y + connect \$1694 $not$libresoc.v:41991$1820_Y + connect \$1696 $and$libresoc.v:41992$1821_Y + connect \$1699 $and$libresoc.v:41993$1822_Y + connect \$1702 $ternary$libresoc.v:41994$1823_Y + connect \$1704 $or$libresoc.v:41995$1824_Y + connect \$1706 $or$libresoc.v:41996$1825_Y + connect \$1708 $or$libresoc.v:41997$1826_Y + connect \$1710 $or$libresoc.v:41998$1827_Y + connect \$1712 $or$libresoc.v:41999$1828_Y + connect \$1714 $or$libresoc.v:42000$1829_Y + connect \$1716 $or$libresoc.v:42001$1830_Y + connect \$1718 $or$libresoc.v:42002$1831_Y + connect \$1720 $or$libresoc.v:42003$1832_Y + connect \$1722 $or$libresoc.v:42004$1833_Y + connect \$1724 $or$libresoc.v:42005$1834_Y + connect \$1726 $or$libresoc.v:42006$1835_Y + connect \$1728 $and$libresoc.v:42007$1836_Y + connect \$1730 $and$libresoc.v:42008$1837_Y + connect \$1732 $and$libresoc.v:42009$1838_Y + connect \$1735 $and$libresoc.v:42010$1839_Y + connect \$1738 $not$libresoc.v:42011$1840_Y + connect \$1740 $and$libresoc.v:42012$1841_Y + connect \$1743 $and$libresoc.v:42013$1842_Y + connect \$1746 $ternary$libresoc.v:42014$1843_Y + connect \$1748 $and$libresoc.v:42015$1844_Y + connect \$1751 $and$libresoc.v:42016$1845_Y + connect \$1754 $not$libresoc.v:42017$1846_Y + connect \$1756 $and$libresoc.v:42018$1847_Y + connect \$175 $and$libresoc.v:42019$1848_Y + connect \$1759 $and$libresoc.v:42020$1849_Y + connect \$1762 $ternary$libresoc.v:42021$1850_Y + connect \$1764 $or$libresoc.v:42022$1851_Y + connect \$1767 $or$libresoc.v:42023$1852_Y + connect \$1766 $pos$libresoc.v:42024$1854_Y + connect \$174 $reduce_or$libresoc.v:42025$1855_Y + connect \$1770 $and$libresoc.v:42026$1856_Y + connect \$1772 $and$libresoc.v:42027$1857_Y + connect \$1775 $and$libresoc.v:42028$1858_Y + connect \$1778 $not$libresoc.v:42029$1859_Y + connect \$1780 $and$libresoc.v:42030$1860_Y + connect \$1783 $and$libresoc.v:42031$1861_Y + connect \$1786 $ternary$libresoc.v:42032$1862_Y + connect \$1788 $pos$libresoc.v:42033$1864_Y + connect \$1790 $and$libresoc.v:42034$1865_Y + connect \$1792 $and$libresoc.v:42035$1866_Y + connect \$1795 $and$libresoc.v:42036$1867_Y + connect \$1798 $not$libresoc.v:42037$1868_Y + connect \$179 $and$libresoc.v:42038$1869_Y + connect \$1800 $and$libresoc.v:42039$1870_Y + connect \$1803 $and$libresoc.v:42040$1871_Y + connect \$1806 $ternary$libresoc.v:42041$1872_Y + connect \$178 $reduce_or$libresoc.v:42042$1873_Y + connect \$183 $and$libresoc.v:42043$1874_Y + connect \$182 $reduce_or$libresoc.v:42044$1875_Y + connect \$187 $and$libresoc.v:42045$1876_Y + connect \$186 $reduce_or$libresoc.v:42046$1877_Y + connect \$191 $and$libresoc.v:42047$1878_Y + connect \$190 $reduce_or$libresoc.v:42048$1879_Y + connect \$195 $and$libresoc.v:42049$1880_Y + connect \$194 $reduce_or$libresoc.v:42050$1881_Y + connect \$199 $and$libresoc.v:42051$1882_Y + connect \$198 $reduce_or$libresoc.v:42052$1883_Y + connect \$203 $and$libresoc.v:42053$1884_Y + connect \$202 $reduce_or$libresoc.v:42054$1885_Y + connect \$207 $and$libresoc.v:42055$1886_Y + connect \$206 $reduce_or$libresoc.v:42056$1887_Y + connect \$211 $and$libresoc.v:42057$1888_Y + connect \$210 $reduce_or$libresoc.v:42058$1889_Y + connect \$214 $ne$libresoc.v:42059$1890_Y + connect \$217 $sub$libresoc.v:42060$1891_Y + connect \$219 $ne$libresoc.v:42061$1892_Y + connect \$222 $and$libresoc.v:42062$1893_Y + connect \$224 $and$libresoc.v:42063$1894_Y + connect \$226 $eq$libresoc.v:42064$1895_Y + connect \$228 $or$libresoc.v:42065$1896_Y + connect \$230 $and$libresoc.v:42066$1897_Y + connect \$232 $or$libresoc.v:42067$1898_Y + connect \$234 $eq$libresoc.v:42068$1899_Y + connect \$236 $and$libresoc.v:42069$1900_Y + connect \$238 $eq$libresoc.v:42070$1901_Y + connect \$240 $or$libresoc.v:42071$1902_Y + connect \$221 $not$libresoc.v:42072$1903_Y + connect \$243 $not$libresoc.v:42073$1904_Y + connect \$245 $not$libresoc.v:42074$1905_Y + connect \$247 $not$libresoc.v:42075$1906_Y + connect \$250 $and$libresoc.v:42076$1907_Y + connect \$252 $and$libresoc.v:42077$1908_Y + connect \$254 $eq$libresoc.v:42078$1909_Y + connect \$256 $or$libresoc.v:42079$1910_Y + connect \$258 $and$libresoc.v:42080$1911_Y + connect \$260 $or$libresoc.v:42081$1912_Y + connect \$249 $not$libresoc.v:42082$1913_Y + connect \$264 $and$libresoc.v:42083$1914_Y + connect \$266 $and$libresoc.v:42084$1915_Y + connect \$268 $eq$libresoc.v:42085$1916_Y + connect \$270 $or$libresoc.v:42086$1917_Y + connect \$272 $and$libresoc.v:42087$1918_Y + connect \$274 $or$libresoc.v:42088$1919_Y + connect \$276 $and$libresoc.v:42089$1920_Y + connect \$278 $and$libresoc.v:42090$1921_Y + connect \$280 $eq$libresoc.v:42091$1922_Y + connect \$282 $or$libresoc.v:42092$1923_Y + connect \$284 $eq$libresoc.v:42093$1924_Y + connect \$286 $and$libresoc.v:42094$1925_Y + connect \$288 $eq$libresoc.v:42095$1926_Y + connect \$290 $or$libresoc.v:42096$1927_Y + connect \$263 $not$libresoc.v:42097$1928_Y + connect \$294 $and$libresoc.v:42098$1929_Y + connect \$296 $and$libresoc.v:42099$1930_Y + connect \$298 $eq$libresoc.v:42100$1931_Y + connect \$300 $or$libresoc.v:42101$1932_Y + connect \$302 $and$libresoc.v:42102$1933_Y + connect \$304 $or$libresoc.v:42103$1934_Y + connect \$293 $not$libresoc.v:42104$1935_Y + connect \$308 $and$libresoc.v:42105$1936_Y + connect \$310 $and$libresoc.v:42106$1937_Y + connect \$312 $eq$libresoc.v:42107$1938_Y + connect \$314 $or$libresoc.v:42108$1939_Y + connect \$316 $and$libresoc.v:42109$1940_Y + connect \$318 $or$libresoc.v:42110$1941_Y + connect \$307 $not$libresoc.v:42111$1942_Y + connect \$322 $and$libresoc.v:42112$1943_Y + connect \$324 $and$libresoc.v:42113$1944_Y + connect \$326 $eq$libresoc.v:42114$1945_Y + connect \$328 $or$libresoc.v:42115$1946_Y + connect \$330 $and$libresoc.v:42116$1947_Y + connect \$332 $or$libresoc.v:42117$1948_Y + connect \$334 $eq$libresoc.v:42118$1949_Y + connect \$336 $and$libresoc.v:42119$1950_Y + connect \$338 $eq$libresoc.v:42120$1951_Y + connect \$340 $or$libresoc.v:42121$1952_Y + connect \$321 $not$libresoc.v:42122$1953_Y + connect \$343 $not$libresoc.v:42123$1954_Y + connect \$345 $and$libresoc.v:42124$1955_Y + connect \$347 $and$libresoc.v:42125$1956_Y + connect \$349 $not$libresoc.v:42126$1957_Y + connect \$351 $and$libresoc.v:42127$1958_Y + connect \$353 $and$libresoc.v:42128$1959_Y + connect \$355 $ternary$libresoc.v:42129$1960_Y + connect \$357 $and$libresoc.v:42130$1961_Y + connect \$359 $and$libresoc.v:42131$1962_Y + connect \$361 $not$libresoc.v:42132$1963_Y + connect \$363 $and$libresoc.v:42133$1964_Y + connect \$365 $and$libresoc.v:42134$1965_Y + connect \$367 $ternary$libresoc.v:42135$1966_Y + connect \$369 $and$libresoc.v:42136$1967_Y + connect \$371 $and$libresoc.v:42137$1968_Y + connect \$373 $not$libresoc.v:42138$1969_Y + connect \$375 $and$libresoc.v:42139$1970_Y + connect \$377 $and$libresoc.v:42140$1971_Y + connect \$379 $ternary$libresoc.v:42141$1972_Y + connect \$381 $and$libresoc.v:42142$1973_Y + connect \$383 $and$libresoc.v:42143$1974_Y + connect \$385 $not$libresoc.v:42144$1975_Y + connect \$387 $and$libresoc.v:42145$1976_Y + connect \$389 $and$libresoc.v:42146$1977_Y + connect \$391 $ternary$libresoc.v:42147$1978_Y + connect \$393 $and$libresoc.v:42148$1979_Y + connect \$395 $and$libresoc.v:42149$1980_Y + connect \$397 $not$libresoc.v:42150$1981_Y + connect \$399 $and$libresoc.v:42151$1982_Y + connect \$401 $and$libresoc.v:42152$1983_Y + connect \$403 $ternary$libresoc.v:42153$1984_Y + connect \$405 $and$libresoc.v:42154$1985_Y + connect \$407 $and$libresoc.v:42155$1986_Y + connect \$409 $not$libresoc.v:42156$1987_Y + connect \$411 $and$libresoc.v:42157$1988_Y + connect \$413 $and$libresoc.v:42158$1989_Y + connect \$415 $ternary$libresoc.v:42159$1990_Y + connect \$417 $and$libresoc.v:42160$1991_Y + connect \$419 $and$libresoc.v:42161$1992_Y + connect \$421 $not$libresoc.v:42162$1993_Y + connect \$423 $and$libresoc.v:42163$1994_Y + connect \$425 $and$libresoc.v:42164$1995_Y + connect \$427 $ternary$libresoc.v:42165$1996_Y + connect \$429 $and$libresoc.v:42166$1997_Y + connect \$431 $and$libresoc.v:42167$1998_Y + connect \$433 $not$libresoc.v:42168$1999_Y + connect \$435 $and$libresoc.v:42169$2000_Y + connect \$437 $and$libresoc.v:42170$2001_Y + connect \$439 $ternary$libresoc.v:42171$2002_Y + connect \$441 $and$libresoc.v:42172$2003_Y + connect \$443 $and$libresoc.v:42173$2004_Y + connect \$445 $not$libresoc.v:42174$2005_Y + connect \$447 $and$libresoc.v:42175$2006_Y + connect \$449 $and$libresoc.v:42176$2007_Y + connect \$451 $ternary$libresoc.v:42177$2008_Y + connect \$453 $or$libresoc.v:42178$2009_Y + connect \$455 $or$libresoc.v:42179$2010_Y + connect \$457 $or$libresoc.v:42180$2011_Y + connect \$459 $or$libresoc.v:42181$2012_Y + connect \$461 $or$libresoc.v:42182$2013_Y + connect \$463 $or$libresoc.v:42183$2014_Y + connect \$465 $or$libresoc.v:42184$2015_Y + connect \$467 $or$libresoc.v:42185$2016_Y + connect \$469 $reduce_or$libresoc.v:42186$2017_Y + connect \$471 $and$libresoc.v:42187$2018_Y + connect \$473 $and$libresoc.v:42188$2019_Y + connect \$475 $not$libresoc.v:42189$2020_Y + connect \$477 $and$libresoc.v:42190$2021_Y + connect \$479 $and$libresoc.v:42191$2022_Y + connect \$481 $ternary$libresoc.v:42192$2023_Y + connect \$483 $and$libresoc.v:42193$2024_Y + connect \$485 $and$libresoc.v:42194$2025_Y + connect \$487 $not$libresoc.v:42195$2026_Y + connect \$489 $and$libresoc.v:42196$2027_Y + connect \$491 $and$libresoc.v:42197$2028_Y + connect \$493 $ternary$libresoc.v:42198$2029_Y + connect \$495 $and$libresoc.v:42199$2030_Y + connect \$497 $and$libresoc.v:42200$2031_Y + connect \$499 $not$libresoc.v:42201$2032_Y + connect \$501 $and$libresoc.v:42202$2033_Y + connect \$503 $and$libresoc.v:42203$2034_Y + connect \$505 $ternary$libresoc.v:42204$2035_Y + connect \$507 $and$libresoc.v:42205$2036_Y + connect \$509 $and$libresoc.v:42206$2037_Y + connect \$511 $not$libresoc.v:42207$2038_Y + connect \$513 $and$libresoc.v:42208$2039_Y + connect \$515 $and$libresoc.v:42209$2040_Y + connect \$517 $ternary$libresoc.v:42210$2041_Y + connect \$519 $and$libresoc.v:42211$2042_Y + connect \$521 $and$libresoc.v:42212$2043_Y + connect \$523 $not$libresoc.v:42213$2044_Y + connect \$525 $and$libresoc.v:42214$2045_Y + connect \$527 $and$libresoc.v:42215$2046_Y + connect \$529 $ternary$libresoc.v:42216$2047_Y + connect \$531 $and$libresoc.v:42217$2048_Y + connect \$533 $and$libresoc.v:42218$2049_Y + connect \$535 $not$libresoc.v:42219$2050_Y + connect \$537 $and$libresoc.v:42220$2051_Y + connect \$539 $and$libresoc.v:42221$2052_Y + connect \$541 $ternary$libresoc.v:42222$2053_Y + connect \$543 $and$libresoc.v:42223$2054_Y + connect \$545 $and$libresoc.v:42224$2055_Y + connect \$547 $not$libresoc.v:42225$2056_Y + connect \$549 $and$libresoc.v:42226$2057_Y + connect \$551 $and$libresoc.v:42227$2058_Y + connect \$553 $ternary$libresoc.v:42228$2059_Y + connect \$555 $and$libresoc.v:42229$2060_Y + connect \$557 $and$libresoc.v:42230$2061_Y + connect \$559 $not$libresoc.v:42231$2062_Y + connect \$561 $and$libresoc.v:42232$2063_Y + connect \$563 $and$libresoc.v:42233$2064_Y + connect \$565 $ternary$libresoc.v:42234$2065_Y + connect \$567 $or$libresoc.v:42235$2066_Y + connect \$569 $or$libresoc.v:42236$2067_Y + connect \$571 $or$libresoc.v:42237$2068_Y + connect \$573 $or$libresoc.v:42238$2069_Y + connect \$575 $or$libresoc.v:42239$2070_Y + connect \$577 $or$libresoc.v:42240$2071_Y + connect \$579 $or$libresoc.v:42241$2072_Y + connect \$581 $reduce_or$libresoc.v:42242$2073_Y + connect \$583 $and$libresoc.v:42243$2074_Y + connect \$585 $and$libresoc.v:42244$2075_Y + connect \$587 $not$libresoc.v:42245$2076_Y + connect \$589 $and$libresoc.v:42246$2077_Y + connect \$591 $and$libresoc.v:42247$2078_Y + connect \$593 $ternary$libresoc.v:42248$2079_Y + connect \$595 $and$libresoc.v:42249$2080_Y + connect \$597 $and$libresoc.v:42250$2081_Y + connect \$599 $not$libresoc.v:42251$2082_Y + connect \$601 $and$libresoc.v:42252$2083_Y + connect \$603 $and$libresoc.v:42253$2084_Y + connect \$605 $ternary$libresoc.v:42254$2085_Y + connect \$607 $or$libresoc.v:42255$2086_Y + connect \$609 $reduce_or$libresoc.v:42256$2087_Y + connect \$611 $and$libresoc.v:42257$2088_Y + connect \$613 $and$libresoc.v:42258$2089_Y + connect \$615 $eq$libresoc.v:42259$2090_Y + connect \$617 $or$libresoc.v:42260$2091_Y + connect \$619 $and$libresoc.v:42261$2092_Y + connect \$621 $or$libresoc.v:42262$2093_Y + connect \$623 $and$libresoc.v:42263$2094_Y + connect \$625 $and$libresoc.v:42264$2095_Y + connect \$627 $not$libresoc.v:42265$2096_Y + connect \$629 $and$libresoc.v:42266$2097_Y + connect \$631 $and$libresoc.v:42267$2098_Y + connect \$633 $ternary$libresoc.v:42268$2099_Y + connect \$635 $and$libresoc.v:42269$2100_Y + connect \$637 $and$libresoc.v:42270$2101_Y + connect \$639 $not$libresoc.v:42271$2102_Y + connect \$641 $and$libresoc.v:42272$2103_Y + connect \$643 $and$libresoc.v:42273$2104_Y + connect \$645 $ternary$libresoc.v:42274$2105_Y + connect \$647 $and$libresoc.v:42275$2106_Y + connect \$649 $and$libresoc.v:42276$2107_Y + connect \$651 $not$libresoc.v:42277$2108_Y + connect \$653 $and$libresoc.v:42278$2109_Y + connect \$655 $and$libresoc.v:42279$2110_Y + connect \$657 $ternary$libresoc.v:42280$2111_Y + connect \$659 $and$libresoc.v:42281$2112_Y + connect \$661 $and$libresoc.v:42282$2113_Y + connect \$663 $not$libresoc.v:42283$2114_Y + connect \$665 $and$libresoc.v:42284$2115_Y + connect \$667 $and$libresoc.v:42285$2116_Y + connect \$669 $ternary$libresoc.v:42286$2117_Y + connect \$671 $and$libresoc.v:42287$2118_Y + connect \$673 $and$libresoc.v:42288$2119_Y + connect \$675 $not$libresoc.v:42289$2120_Y + connect \$677 $and$libresoc.v:42290$2121_Y + connect \$679 $and$libresoc.v:42291$2122_Y + connect \$681 $ternary$libresoc.v:42292$2123_Y + connect \$683 $and$libresoc.v:42293$2124_Y + connect \$685 $and$libresoc.v:42294$2125_Y + connect \$687 $not$libresoc.v:42295$2126_Y + connect \$689 $and$libresoc.v:42296$2127_Y + connect \$691 $and$libresoc.v:42297$2128_Y + connect \$693 $ternary$libresoc.v:42298$2129_Y + connect \$696 $or$libresoc.v:42299$2130_Y + connect \$698 $or$libresoc.v:42300$2131_Y + connect \$700 $or$libresoc.v:42301$2132_Y + connect \$702 $or$libresoc.v:42302$2133_Y + connect \$704 $or$libresoc.v:42303$2134_Y + connect \$695 $pos$libresoc.v:42304$2136_Y + connect \$707 $eq$libresoc.v:42305$2137_Y + connect \$709 $and$libresoc.v:42306$2138_Y + connect \$711 $eq$libresoc.v:42307$2139_Y + connect \$713 $or$libresoc.v:42308$2140_Y + connect \$715 $and$libresoc.v:42309$2141_Y + connect \$717 $and$libresoc.v:42310$2142_Y + connect \$719 $not$libresoc.v:42311$2143_Y + connect \$721 $and$libresoc.v:42312$2144_Y + connect \$723 $and$libresoc.v:42313$2145_Y + connect \$725 $ternary$libresoc.v:42314$2146_Y + connect \$727 $and$libresoc.v:42315$2147_Y + connect \$729 $and$libresoc.v:42316$2148_Y + connect \$731 $not$libresoc.v:42317$2149_Y + connect \$733 $and$libresoc.v:42318$2150_Y + connect \$735 $and$libresoc.v:42319$2151_Y + connect \$737 $ternary$libresoc.v:42320$2152_Y + connect \$739 $and$libresoc.v:42321$2153_Y + connect \$741 $and$libresoc.v:42322$2154_Y + connect \$743 $not$libresoc.v:42323$2155_Y + connect \$745 $and$libresoc.v:42324$2156_Y + connect \$747 $and$libresoc.v:42325$2157_Y + connect \$749 $ternary$libresoc.v:42326$2158_Y + connect \$752 $or$libresoc.v:42327$2159_Y + connect \$754 $or$libresoc.v:42328$2160_Y + connect \$751 $pos$libresoc.v:42329$2162_Y + connect \$757 $and$libresoc.v:42330$2163_Y + connect \$759 $and$libresoc.v:42331$2164_Y + connect \$761 $eq$libresoc.v:42332$2165_Y + connect \$763 $or$libresoc.v:42333$2166_Y + connect \$765 $and$libresoc.v:42334$2167_Y + connect \$767 $and$libresoc.v:42335$2168_Y + connect \$769 $not$libresoc.v:42336$2169_Y + connect \$771 $and$libresoc.v:42337$2170_Y + connect \$773 $and$libresoc.v:42338$2171_Y + connect \$775 $ternary$libresoc.v:42339$2172_Y + connect \$777 $and$libresoc.v:42340$2173_Y + connect \$779 $and$libresoc.v:42341$2174_Y + connect \$781 $not$libresoc.v:42342$2175_Y + connect \$783 $and$libresoc.v:42343$2176_Y + connect \$785 $and$libresoc.v:42344$2177_Y + connect \$787 $ternary$libresoc.v:42345$2178_Y + connect \$789 $and$libresoc.v:42346$2179_Y + connect \$791 $and$libresoc.v:42347$2180_Y + connect \$793 $not$libresoc.v:42348$2181_Y + connect \$795 $and$libresoc.v:42349$2182_Y + connect \$797 $and$libresoc.v:42350$2183_Y + connect \$799 $sub$libresoc.v:42351$2184_Y + connect \$801 $sshl$libresoc.v:42352$2185_Y + connect \$803 $ternary$libresoc.v:42353$2186_Y + connect \$805 $and$libresoc.v:42354$2187_Y + connect \$807 $and$libresoc.v:42355$2188_Y + connect \$809 $not$libresoc.v:42356$2189_Y + connect \$811 $and$libresoc.v:42357$2190_Y + connect \$813 $and$libresoc.v:42358$2191_Y + connect \$815 $sub$libresoc.v:42359$2192_Y + connect \$817 $sshl$libresoc.v:42360$2193_Y + connect \$819 $ternary$libresoc.v:42361$2194_Y + connect \$822 $or$libresoc.v:42362$2195_Y + connect \$824 $and$libresoc.v:42363$2196_Y + connect \$826 $and$libresoc.v:42364$2197_Y + connect \$828 $not$libresoc.v:42365$2198_Y + connect \$830 $and$libresoc.v:42366$2199_Y + connect \$832 $and$libresoc.v:42367$2200_Y + connect \$834 $sub$libresoc.v:42368$2201_Y + connect \$836 $sshl$libresoc.v:42369$2202_Y + connect \$838 $ternary$libresoc.v:42370$2203_Y + connect \$840 $and$libresoc.v:42371$2204_Y + connect \$842 $and$libresoc.v:42372$2205_Y + connect \$844 $not$libresoc.v:42373$2206_Y + connect \$846 $and$libresoc.v:42374$2207_Y + connect \$848 $and$libresoc.v:42375$2208_Y + connect \$850 $sub$libresoc.v:42376$2209_Y + connect \$852 $sshl$libresoc.v:42377$2210_Y + connect \$854 $ternary$libresoc.v:42378$2211_Y + connect \$856 $and$libresoc.v:42379$2212_Y + connect \$858 $and$libresoc.v:42380$2213_Y + connect \$860 $not$libresoc.v:42381$2214_Y + connect \$862 $and$libresoc.v:42382$2215_Y + connect \$864 $and$libresoc.v:42383$2216_Y + connect \$866 $ternary$libresoc.v:42384$2217_Y + connect \$868 $and$libresoc.v:42385$2218_Y + connect \$870 $and$libresoc.v:42386$2219_Y + connect \$872 $not$libresoc.v:42387$2220_Y + connect \$874 $and$libresoc.v:42388$2221_Y + connect \$876 $and$libresoc.v:42389$2222_Y + connect \$878 $ternary$libresoc.v:42390$2223_Y + connect \$880 $and$libresoc.v:42391$2224_Y + connect \$882 $and$libresoc.v:42392$2225_Y + connect \$884 $not$libresoc.v:42393$2226_Y + connect \$886 $and$libresoc.v:42394$2227_Y + connect \$888 $and$libresoc.v:42395$2228_Y + connect \$890 $ternary$libresoc.v:42396$2229_Y + connect \$892 $or$libresoc.v:42397$2230_Y + connect \$894 $or$libresoc.v:42398$2231_Y + connect \$896 $reduce_or$libresoc.v:42399$2232_Y + connect \$898 $and$libresoc.v:42400$2233_Y + connect \$900 $and$libresoc.v:42401$2234_Y + connect \$902 $not$libresoc.v:42402$2235_Y + connect \$904 $and$libresoc.v:42403$2236_Y + connect \$906 $and$libresoc.v:42404$2237_Y + connect \$908 $ternary$libresoc.v:42405$2238_Y + connect \$910 $and$libresoc.v:42406$2239_Y + connect \$912 $and$libresoc.v:42407$2240_Y + connect \$914 $not$libresoc.v:42408$2241_Y + connect \$916 $and$libresoc.v:42409$2242_Y + connect \$918 $and$libresoc.v:42410$2243_Y + connect \$920 $ternary$libresoc.v:42411$2244_Y + connect \$922 $or$libresoc.v:42412$2245_Y + connect \$924 $reduce_or$libresoc.v:42413$2246_Y + connect \$926 $and$libresoc.v:42414$2247_Y + connect \$928 $and$libresoc.v:42415$2248_Y + connect \$930 $not$libresoc.v:42416$2249_Y + connect \$932 $and$libresoc.v:42417$2250_Y + connect \$934 $and$libresoc.v:42418$2251_Y + connect \$936 $ternary$libresoc.v:42419$2252_Y + connect \$938 $reduce_or$libresoc.v:42420$2253_Y + connect \$940 $and$libresoc.v:42421$2254_Y + connect \$942 $and$libresoc.v:42422$2255_Y + connect \$944 $and$libresoc.v:42423$2256_Y + connect \$946 $and$libresoc.v:42424$2257_Y + connect \$948 $and$libresoc.v:42425$2258_Y + connect \$950 $and$libresoc.v:42426$2259_Y + connect \$952 $and$libresoc.v:42427$2260_Y + connect \$954 $and$libresoc.v:42428$2261_Y + connect \$956 $and$libresoc.v:42429$2262_Y + connect \$958 $and$libresoc.v:42430$2263_Y + connect \$960 $and$libresoc.v:42431$2264_Y + connect \$962 $and$libresoc.v:42432$2265_Y + connect \$964 $not$libresoc.v:42433$2266_Y + connect \$966 $and$libresoc.v:42434$2267_Y + connect \$972 $and$libresoc.v:42435$2268_Y + connect \$974 $ternary$libresoc.v:42436$2269_Y + connect \$976 $and$libresoc.v:42437$2270_Y + connect \$979 $and$libresoc.v:42438$2271_Y + connect \$983 $not$libresoc.v:42439$2272_Y + connect \$985 $and$libresoc.v:42440$2273_Y + connect \$990 $and$libresoc.v:42441$2274_Y + connect \$993 $ternary$libresoc.v:42442$2275_Y + connect \$995 $and$libresoc.v:42443$2276_Y + connect \$998 $and$libresoc.v:42444$2277_Y + connect \$216 \$217 + connect \$821 \$822 + connect \$1149 \$1166 + connect \$1364 \$1373 connect \o_ok 1'0 connect \ea_ok 1'0 - connect \coresync_rst \core_reset_i - connect \spr_spr1__wen \wp$1788 - connect \spr_spr1__addr$159 \addr_en$1791 [6:0] - connect \spr_spr1__data_i \fus_dest2_o$153 - connect \addr_en$1791 \$1792 - connect \wp$1788 \$1789 - connect \wr_pick_rise$1035 \$1786 - connect \wr_pick$1780 \$1781 - connect \wrpick_SPR_spr1_i \$1778 - connect \wrflag_spr0_spr1_1 \$1776 - connect \state_wen \$1774 - connect \state_data_i$158 \fus_dest5_o$152 - connect \addr_en$1771 \$1772 - connect \wp$1768 \$1769 - connect \wr_pick_rise$995 \$1766 - connect \wr_pick$1760 \$1761 - connect \wrpick_STATE_msr_i \$1758 - connect \wrflag_trap0_msr_4 \$1756 - connect \state_nia_wen \$1752 - connect \state_data_i \$1750 - connect \addr_en$1747 \$1748 - connect \wp$1744 \$1745 - connect \wr_pick_rise$994 \$1742 - connect \wr_pick$1736 \$1737 - connect \wrflag_trap0_nia_3 \$1734 - connect \addr_en$1731 \$1732 - connect \wp$1728 \$1729 - connect \wr_pick_rise$1619 \$1726 - connect \wr_pick$1720 \$1721 - connect \wrpick_STATE_nia_i [1] \$1718 - connect \wrpick_STATE_nia_i [0] \$1716 - connect \wrflag_branch0_nia_2 \$1714 - connect \fast_dest1__wen \$1712 - connect \fast_dest1__addr \$1704 - connect \fast_dest1__data_i \$1696 - connect \addr_en$1687 \$1688 - connect \wp$1684 \$1685 - connect \wr_pick_rise$993 \$1682 - connect \wr_pick$1676 \$1677 - connect \wrflag_trap0_fast1_2 \$1674 - connect \addr_en$1671 \$1672 - connect \wp$1668 \$1669 - connect \wr_pick_rise$1618 \$1666 - connect \wr_pick$1660 \$1661 - connect \wrflag_branch0_fast1_1 \$1658 - connect \addr_en$1655 \$1656 - connect \wp$1652 \$1653 - connect \wr_pick_rise$1034 \$1650 - connect \wr_pick$1644 \$1645 - connect \wrflag_spr0_fast1_2 \$1642 - connect \addr_en$1639 \$1640 - connect \wp$1636 \$1637 - connect \wr_pick_rise$992 \$1634 - connect \wr_pick$1628 \$1629 - connect \wrflag_trap0_fast1_1 \$1626 - connect \addr_en$1623 \$1624 - connect \wp$1620 \$1621 - connect \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 - connect \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 - connect \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 - connect \wr_pick_rise$1613 \$1616 - connect \wr_pick$1609 \$1610 - connect \wrpick_FAST_fast1_i [4] \$1607 - connect \wrpick_FAST_fast1_i [3] \$1605 - connect \wrpick_FAST_fast1_i [2] \$1603 - connect \wrpick_FAST_fast1_i [1] \$1601 - connect \wrpick_FAST_fast1_i [0] \$1599 - connect \wrflag_branch0_fast1_0 \$1597 - connect \xer_wen$157 \$1589 - connect \xer_data_i$156 \$1581 - connect \addr_en$1578 \$1579 - connect \wp$1575 \$1576 - connect \wr_pick_rise$1075 \$1573 - connect \wr_pick$1567 \$1568 - connect \wrflag_mul0_xer_so_3 \$1565 - connect \addr_en$1562 \$1563 - connect \wp$1559 \$1560 - connect \wr_pick_rise$1055 \$1557 - connect \wr_pick$1551 \$1552 - connect \wrflag_div0_xer_so_3 \$1549 - connect \addr_en$1546 \$1547 - connect \wp$1543 \$1544 - connect \wr_pick_rise$1033 \$1541 - connect \wr_pick$1535 \$1536 - connect \wrflag_spr0_xer_so_3 \$1533 - connect \addr_en$1530 \$1531 - connect \wp$1527 \$1528 - connect \wr_pick_rise$957 \$1525 - connect \wr_pick$1519 \$1520 - connect \wrpick_XER_xer_so_i [3] \$1517 - connect \wrpick_XER_xer_so_i [2] \$1515 - connect \wrpick_XER_xer_so_i [1] \$1513 - connect \wrpick_XER_xer_so_i [0] \$1511 - connect \wrflag_alu0_xer_so_4 \$1509 - connect \xer_wen$155 \$1507 - connect \xer_data_i$154 \$1501 - connect \addr_en$1494 \$1495 - connect \wp$1491 \$1492 - connect \wr_pick_rise$1074 \$1489 - connect \wr_pick$1483 \$1484 - connect \wrflag_mul0_xer_ov_2 \$1481 - connect \addr_en$1478 \$1479 - connect \wp$1475 \$1476 - connect \wr_pick_rise$1054 \$1473 - connect \wr_pick$1467 \$1468 - connect \wrflag_div0_xer_ov_2 \$1465 - connect \addr_en$1462 \$1463 - connect \wp$1459 \$1460 - connect \wr_pick_rise$1032 \$1457 - connect \wr_pick$1451 \$1452 - connect \wrflag_spr0_xer_ov_4 \$1449 - connect \addr_en$1446 \$1447 - connect \wp$1443 \$1444 - connect \wr_pick_rise$956 \$1441 - connect \wr_pick$1435 \$1436 - connect \wrpick_XER_xer_ov_i [3] \$1433 - connect \wrpick_XER_xer_ov_i [2] \$1431 - connect \wrpick_XER_xer_ov_i [1] \$1429 - connect \wrpick_XER_xer_ov_i [0] \$1427 - connect \wrflag_alu0_xer_ov_3 \$1425 - connect \xer_wen \$1419 - connect \xer_data_i \$1417 - connect \addr_en$1412 \$1413 - connect \wp$1409 \$1410 - connect \wr_pick_rise$1094 \$1407 - connect \wr_pick$1401 \$1402 - connect \wrflag_shiftrot0_xer_ca_2 \$1399 - connect \addr_en$1396 \$1397 - connect \wp$1393 \$1394 - connect \wr_pick_rise$1031 \$1391 - connect \wr_pick$1385 \$1386 - connect \wrflag_spr0_xer_ca_5 \$1383 - connect \addr_en$1380 \$1381 - connect \wp$1377 \$1378 - connect \wr_pick_rise$955 \$1375 - connect \wr_pick$1369 \$1370 - connect \wrpick_XER_xer_ca_i [2] \$1367 - connect \wrpick_XER_xer_ca_i [1] \$1365 - connect \wrpick_XER_xer_ca_i [0] \$1363 - connect \wrflag_alu0_xer_ca_2 \$1361 - connect \cr_wen \$1359 [7:0] - connect \cr_data_i \$1348 - connect \addr_en$1333 \$1338 - connect \wp$1330 \$1331 - connect \wr_pick_rise$1093 \$1328 - connect \wr_pick$1322 \$1323 - connect \wrflag_shiftrot0_cr_a_1 \$1320 - connect \addr_en$1313 \$1318 - connect \wp$1310 \$1311 - connect \wr_pick_rise$1073 \$1308 - connect \wr_pick$1302 \$1303 - connect \wrflag_mul0_cr_a_1 \$1300 - connect \addr_en$1293 \$1298 - connect \wp$1290 \$1291 - connect \wr_pick_rise$1053 \$1288 - connect \wr_pick$1282 \$1283 - connect \wrflag_div0_cr_a_1 \$1280 - connect \addr_en$1273 \$1278 - connect \wp$1270 \$1271 - connect \wr_pick_rise$1013 \$1268 - connect \wr_pick$1262 \$1263 - connect \wrflag_logical0_cr_a_1 \$1260 - connect \addr_en$1253 \$1258 - connect \wp$1250 \$1251 - connect \wr_pick_rise$974 \$1248 - connect \wr_pick$1242 \$1243 - connect \wrflag_cr0_cr_a_2 \$1240 - connect \addr_en$1233 \$1238 - connect \wp$1230 \$1231 - connect \wr_pick_rise$954 \$1228 - connect \wr_pick$1222 \$1223 - connect \wrpick_CR_cr_a_i [5] \$1220 - connect \wrpick_CR_cr_a_i [4] \$1218 - connect \wrpick_CR_cr_a_i [3] \$1216 - connect \wrpick_CR_cr_a_i [2] \$1214 - connect \wrpick_CR_cr_a_i [1] \$1212 - connect \wrpick_CR_cr_a_i [0] \$1210 - connect \wrflag_alu0_cr_a_1 \$1208 - connect \cr_full_wr__wen \addr_en$1205 + connect \spr_spr1__wen \wp$1802 + connect \spr_spr1__addr$173 \addr_en$1805 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$160 + connect \addr_en$1805 \$1806 + connect \wp$1802 \$1803 + connect \wr_pick_rise$1049 \$1800 + connect \wr_pick$1794 \$1795 + connect \wrpick_SPR_spr1_i \$1792 + connect \wrflag_spr0_spr1_1 \$1790 + connect \state_wen \$1788 + connect \state_data_i$172 \fus_dest5_o$159 + connect \addr_en$1785 \$1786 + connect \wp$1782 \$1783 + connect \wr_pick_rise$1009 \$1780 + connect \wr_pick$1774 \$1775 + connect \wrpick_STATE_msr_i \$1772 + connect \wrflag_trap0_msr_4 \$1770 + connect \state_nia_wen \$1766 + connect \state_data_i \$1764 + connect \addr_en$1761 \$1762 + connect \wp$1758 \$1759 + connect \wr_pick_rise$1008 \$1756 + connect \wr_pick$1750 \$1751 + connect \wrflag_trap0_nia_3 \$1748 + connect \addr_en$1745 \$1746 + connect \wp$1742 \$1743 + connect \wr_pick_rise$1633 \$1740 + connect \wr_pick$1734 \$1735 + connect \wrpick_STATE_nia_i [1] \$1732 + connect \wrpick_STATE_nia_i [0] \$1730 + connect \wrflag_branch0_nia_2 \$1728 + connect \fast_dest1__wen \$1726 + connect \fast_dest1__addr \$1718 + connect \fast_dest1__data_i \$1710 + connect \addr_en$1701 \$1702 + connect \wp$1698 \$1699 + connect \wr_pick_rise$1007 \$1696 + connect \wr_pick$1690 \$1691 + connect \wrflag_trap0_fast1_2 \$1688 + connect \addr_en$1685 \$1686 + connect \wp$1682 \$1683 + connect \wr_pick_rise$1632 \$1680 + connect \wr_pick$1674 \$1675 + connect \wrflag_branch0_fast1_1 \$1672 + connect \addr_en$1669 \$1670 + connect \wp$1666 \$1667 + connect \wr_pick_rise$1048 \$1664 + connect \wr_pick$1658 \$1659 + connect \wrflag_spr0_fast1_2 \$1656 + connect \addr_en$1653 \$1654 + connect \wp$1650 \$1651 + connect \wr_pick_rise$1006 \$1648 + connect \wr_pick$1642 \$1643 + connect \wrflag_trap0_fast1_1 \$1640 + connect \addr_en$1637 \$1638 + connect \wp$1634 \$1635 + connect \fus_cu_wr__go_i$147 [2] \wr_pick_rise$1633 + connect \fus_cu_wr__go_i$147 [1] \wr_pick_rise$1632 + connect \fus_cu_wr__go_i$147 [0] \wr_pick_rise$1627 + connect \wr_pick_rise$1627 \$1630 + connect \wr_pick$1623 \$1624 + connect \wrpick_FAST_fast1_i [4] \$1621 + connect \wrpick_FAST_fast1_i [3] \$1619 + connect \wrpick_FAST_fast1_i [2] \$1617 + connect \wrpick_FAST_fast1_i [1] \$1615 + connect \wrpick_FAST_fast1_i [0] \$1613 + connect \wrflag_branch0_fast1_0 \$1611 + connect \xer_wen$171 \$1603 + connect \xer_data_i$170 \$1595 + connect \addr_en$1592 \$1593 + connect \wp$1589 \$1590 + connect \wr_pick_rise$1089 \$1587 + connect \wr_pick$1581 \$1582 + connect \wrflag_mul0_xer_so_3 \$1579 + connect \addr_en$1576 \$1577 + connect \wp$1573 \$1574 + connect \wr_pick_rise$1069 \$1571 + connect \wr_pick$1565 \$1566 + connect \wrflag_div0_xer_so_3 \$1563 + connect \addr_en$1560 \$1561 + connect \wp$1557 \$1558 + connect \wr_pick_rise$1047 \$1555 + connect \wr_pick$1549 \$1550 + connect \wrflag_spr0_xer_so_3 \$1547 + connect \addr_en$1544 \$1545 + connect \wp$1541 \$1542 + connect \wr_pick_rise$971 \$1539 + connect \wr_pick$1533 \$1534 + connect \wrpick_XER_xer_so_i [3] \$1531 + connect \wrpick_XER_xer_so_i [2] \$1529 + connect \wrpick_XER_xer_so_i [1] \$1527 + connect \wrpick_XER_xer_so_i [0] \$1525 + connect \wrflag_alu0_xer_so_4 \$1523 + connect \xer_wen$169 \$1521 + connect \xer_data_i$168 \$1515 + connect \addr_en$1508 \$1509 + connect \wp$1505 \$1506 + connect \wr_pick_rise$1088 \$1503 + connect \wr_pick$1497 \$1498 + connect \wrflag_mul0_xer_ov_2 \$1495 + connect \addr_en$1492 \$1493 + connect \wp$1489 \$1490 + connect \wr_pick_rise$1068 \$1487 + connect \wr_pick$1481 \$1482 + connect \wrflag_div0_xer_ov_2 \$1479 + connect \addr_en$1476 \$1477 + connect \wp$1473 \$1474 + connect \wr_pick_rise$1046 \$1471 + connect \wr_pick$1465 \$1466 + connect \wrflag_spr0_xer_ov_4 \$1463 + connect \addr_en$1460 \$1461 + connect \wp$1457 \$1458 + connect \wr_pick_rise$970 \$1455 + connect \wr_pick$1449 \$1450 + connect \wrpick_XER_xer_ov_i [3] \$1447 + connect \wrpick_XER_xer_ov_i [2] \$1445 + connect \wrpick_XER_xer_ov_i [1] \$1443 + connect \wrpick_XER_xer_ov_i [0] \$1441 + connect \wrflag_alu0_xer_ov_3 \$1439 + connect \xer_wen \$1433 + connect \xer_data_i \$1431 + connect \addr_en$1426 \$1427 + connect \wp$1423 \$1424 + connect \wr_pick_rise$1108 \$1421 + connect \wr_pick$1415 \$1416 + connect \wrflag_shiftrot0_xer_ca_2 \$1413 + connect \addr_en$1410 \$1411 + connect \wp$1407 \$1408 + connect \wr_pick_rise$1045 \$1405 + connect \wr_pick$1399 \$1400 + connect \wrflag_spr0_xer_ca_5 \$1397 + connect \addr_en$1394 \$1395 + connect \wp$1391 \$1392 + connect \wr_pick_rise$969 \$1389 + connect \wr_pick$1383 \$1384 + connect \wrpick_XER_xer_ca_i [2] \$1381 + connect \wrpick_XER_xer_ca_i [1] \$1379 + connect \wrpick_XER_xer_ca_i [0] \$1377 + connect \wrflag_alu0_xer_ca_2 \$1375 + connect \cr_wen \$1373 [7:0] + connect \cr_data_i \$1362 + connect \addr_en$1347 \$1352 + connect \wp$1344 \$1345 + connect \wr_pick_rise$1107 \$1342 + connect \wr_pick$1336 \$1337 + connect \wrflag_shiftrot0_cr_a_1 \$1334 + connect \addr_en$1327 \$1332 + connect \wp$1324 \$1325 + connect \wr_pick_rise$1087 \$1322 + connect \wr_pick$1316 \$1317 + connect \wrflag_mul0_cr_a_1 \$1314 + connect \addr_en$1307 \$1312 + connect \wp$1304 \$1305 + connect \wr_pick_rise$1067 \$1302 + connect \wr_pick$1296 \$1297 + connect \wrflag_div0_cr_a_1 \$1294 + connect \addr_en$1287 \$1292 + connect \wp$1284 \$1285 + connect \wr_pick_rise$1027 \$1282 + connect \wr_pick$1276 \$1277 + connect \wrflag_logical0_cr_a_1 \$1274 + connect \addr_en$1267 \$1272 + connect \wp$1264 \$1265 + connect \wr_pick_rise$988 \$1262 + connect \wr_pick$1256 \$1257 + connect \wrflag_cr0_cr_a_2 \$1254 + connect \addr_en$1247 \$1252 + connect \wp$1244 \$1245 + connect \wr_pick_rise$968 \$1242 + connect \wr_pick$1236 \$1237 + connect \wrpick_CR_cr_a_i [5] \$1234 + connect \wrpick_CR_cr_a_i [4] \$1232 + connect \wrpick_CR_cr_a_i [3] \$1230 + connect \wrpick_CR_cr_a_i [2] \$1228 + connect \wrpick_CR_cr_a_i [1] \$1226 + connect \wrpick_CR_cr_a_i [0] \$1224 + connect \wrflag_alu0_cr_a_1 \$1222 + connect \cr_full_wr__wen \addr_en$1219 connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1205 \$1206 - connect \wp$1202 \$1203 - connect \wr_pick_rise$973 \$1200 - connect \wr_pick$1194 \$1195 - connect \wrpick_CR_full_cr_i \$1192 - connect \wrflag_cr0_full_cr_1 \$1190 - connect \int_dest1__wen \$1188 - connect \int_dest1__addr \$1170 - connect \int_dest1__data_i \$1152 [63:0] - connect \addr_en$1132 \$1133 - connect \wp$1129 \$1130 - connect \wr_pick_rise$1112 \$1127 - connect \wr_pick$1121 \$1122 - connect \wrflag_ldst0_o_1 \$1119 - connect \addr_en$1116 \$1117 - connect \wp$1113 \$1114 - connect \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 - connect \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 - connect \wr_pick_rise$1107 \$1110 - connect \wr_pick$1103 \$1104 - connect \wrflag_ldst0_o_0 \$1101 - connect \addr_en$1098 \$1099 - connect \wp$1095 \$1096 - connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 - connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 - connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 - connect \wr_pick_rise$1088 \$1091 - connect \wr_pick$1084 \$1085 - connect \wrflag_shiftrot0_o_0 \$1082 - connect \addr_en$1079 \$1080 - connect \wp$1076 \$1077 - connect \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 - connect \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 - connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 - connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 - connect \wr_pick_rise$1068 \$1071 - connect \wr_pick$1064 \$1065 - connect \wrflag_mul0_o_0 \$1062 - connect \addr_en$1059 \$1060 - connect \wp$1056 \$1057 - connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 - connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 - connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 - connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 - connect \wr_pick_rise$1048 \$1051 - connect \wr_pick$1044 \$1045 - connect \wrflag_div0_o_0 \$1042 - connect \addr_en$1039 \$1040 - connect \wp$1036 \$1037 - connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 - connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 - connect \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 - connect \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 - connect \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 - connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 - connect \wr_pick_rise$1026 \$1029 - connect \wr_pick$1022 \$1023 - connect \wrflag_spr0_o_0 \$1020 - connect \addr_en$1017 \$1018 - connect \wp$1014 \$1015 - connect \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 - connect \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 - connect \wr_pick_rise$1008 \$1011 - connect \wr_pick$1004 \$1005 - connect \wrflag_logical0_o_0 \$1002 - connect \addr_en$999 \$1000 - connect \wp$996 \$997 - connect \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 - connect \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 - connect \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 - connect \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 - connect \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 - connect \wr_pick_rise$987 \$990 - connect \wr_pick$983 \$984 - connect \wrflag_trap0_o_0 \$981 - connect \addr_en$978 \$979 - connect \wp$975 \$976 - connect \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 - connect \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 - connect \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 - connect \wr_pick_rise$968 \$971 - connect \wr_pick$964 \$965 - connect \wrflag_cr0_o_0 \$962 - connect \addr_en \$960 - connect \wp \$958 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$957 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$956 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$955 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$954 + connect \addr_en$1219 \$1220 + connect \wp$1216 \$1217 + connect \wr_pick_rise$987 \$1214 + connect \wr_pick$1208 \$1209 + connect \wrpick_CR_full_cr_i \$1206 + connect \wrflag_cr0_full_cr_1 \$1204 + connect \int_dest1__wen \$1202 + connect \int_dest1__addr \$1184 + connect \int_dest1__data_i \$1166 [63:0] + connect \addr_en$1146 \$1147 + connect \wp$1143 \$1144 + connect \wr_pick_rise$1126 \$1141 + connect \wr_pick$1135 \$1136 + connect \wrflag_ldst0_o_1 \$1133 + connect \addr_en$1130 \$1131 + connect \wp$1127 \$1128 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1126 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1121 + connect \wr_pick_rise$1121 \$1124 + connect \wr_pick$1117 \$1118 + connect \wrflag_ldst0_o_0 \$1115 + connect \addr_en$1112 \$1113 + connect \wp$1109 \$1110 + connect \fus_cu_wr__go_i$110 [2] \wr_pick_rise$1108 + connect \fus_cu_wr__go_i$110 [1] \wr_pick_rise$1107 + connect \fus_cu_wr__go_i$110 [0] \wr_pick_rise$1102 + connect \wr_pick_rise$1102 \$1105 + connect \wr_pick$1098 \$1099 + connect \wrflag_shiftrot0_o_0 \$1096 + connect \addr_en$1093 \$1094 + connect \wp$1090 \$1091 + connect \fus_cu_wr__go_i$107 [3] \wr_pick_rise$1089 + connect \fus_cu_wr__go_i$107 [2] \wr_pick_rise$1088 + connect \fus_cu_wr__go_i$107 [1] \wr_pick_rise$1087 + connect \fus_cu_wr__go_i$107 [0] \wr_pick_rise$1082 + connect \wr_pick_rise$1082 \$1085 + connect \wr_pick$1078 \$1079 + connect \wrflag_mul0_o_0 \$1076 + connect \addr_en$1073 \$1074 + connect \wp$1070 \$1071 + connect \fus_cu_wr__go_i$104 [3] \wr_pick_rise$1069 + connect \fus_cu_wr__go_i$104 [2] \wr_pick_rise$1068 + connect \fus_cu_wr__go_i$104 [1] \wr_pick_rise$1067 + connect \fus_cu_wr__go_i$104 [0] \wr_pick_rise$1062 + connect \wr_pick_rise$1062 \$1065 + connect \wr_pick$1058 \$1059 + connect \wrflag_div0_o_0 \$1056 + connect \addr_en$1053 \$1054 + connect \wp$1050 \$1051 + connect \fus_cu_wr__go_i$101 [1] \wr_pick_rise$1049 + connect \fus_cu_wr__go_i$101 [2] \wr_pick_rise$1048 + connect \fus_cu_wr__go_i$101 [3] \wr_pick_rise$1047 + connect \fus_cu_wr__go_i$101 [4] \wr_pick_rise$1046 + connect \fus_cu_wr__go_i$101 [5] \wr_pick_rise$1045 + connect \fus_cu_wr__go_i$101 [0] \wr_pick_rise$1040 + connect \wr_pick_rise$1040 \$1043 + connect \wr_pick$1036 \$1037 + connect \wrflag_spr0_o_0 \$1034 + connect \addr_en$1031 \$1032 + connect \wp$1028 \$1029 + connect \fus_cu_wr__go_i$98 [1] \wr_pick_rise$1027 + connect \fus_cu_wr__go_i$98 [0] \wr_pick_rise$1022 + connect \wr_pick_rise$1022 \$1025 + connect \wr_pick$1018 \$1019 + connect \wrflag_logical0_o_0 \$1016 + connect \addr_en$1013 \$1014 + connect \wp$1010 \$1011 + connect \fus_cu_wr__go_i$95 [4] \wr_pick_rise$1009 + connect \fus_cu_wr__go_i$95 [3] \wr_pick_rise$1008 + connect \fus_cu_wr__go_i$95 [2] \wr_pick_rise$1007 + connect \fus_cu_wr__go_i$95 [1] \wr_pick_rise$1006 + connect \fus_cu_wr__go_i$95 [0] \wr_pick_rise$1001 + connect \wr_pick_rise$1001 \$1004 + connect \wr_pick$997 \$998 + connect \wrflag_trap0_o_0 \$995 + connect \addr_en$992 \$993 + connect \wp$989 \$990 + connect \fus_cu_wr__go_i$92 [2] \wr_pick_rise$988 + connect \fus_cu_wr__go_i$92 [1] \wr_pick_rise$987 + connect \fus_cu_wr__go_i$92 [0] \wr_pick_rise$982 + connect \wr_pick_rise$982 \$985 + connect \wr_pick$978 \$979 + connect \wrflag_cr0_o_0 \$976 + connect \addr_en \$974 + connect \wp \$972 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$971 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$970 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$969 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$968 connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$952 - connect \wr_pick \$948 - connect \wrpick_INT_o_i [9] \$946 - connect \wrpick_INT_o_i [8] \$944 - connect \wrpick_INT_o_i [7] \$942 - connect \wrpick_INT_o_i [6] \$940 - connect \wrpick_INT_o_i [5] \$938 - connect \wrpick_INT_o_i [4] \$936 - connect \wrpick_INT_o_i [3] \$934 - connect \wrpick_INT_o_i [2] \$932 - connect \wrpick_INT_o_i [1] \$930 - connect \wrpick_INT_o_i [0] \$928 - connect \wrflag_alu0_o_0 \$926 - connect \spr_spr1__ren \$924 + connect \wr_pick_rise \$966 + connect \wr_pick \$962 + connect \wrpick_INT_o_i [9] \$960 + connect \wrpick_INT_o_i [8] \$958 + connect \wrpick_INT_o_i [7] \$956 + connect \wrpick_INT_o_i [6] \$954 + connect \wrpick_INT_o_i [5] \$952 + connect \wrpick_INT_o_i [4] \$950 + connect \wrpick_INT_o_i [3] \$948 + connect \wrpick_INT_o_i [2] \$946 + connect \wrpick_INT_o_i [1] \$944 + connect \wrpick_INT_o_i [0] \$942 + connect \wrflag_alu0_o_0 \$940 + connect \spr_spr1__ren \$938 connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$922 - connect \rp_SPR_spr1_spr0_0 \$920 + connect \addr_en_SPR_spr1_spr0_0 \$936 + connect \rp_SPR_spr1_spr0_0 \$934 connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$918 + connect \pick_SPR_spr1_spr0_0 \$932 connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$910 - connect \fast_src2__addr \$908 - connect \addr_en_FAST_fast2_trap0_1 \$906 - connect \rp_FAST_fast2_trap0_1 \$904 - connect \pick_FAST_fast2_trap0_1 \$902 - connect \addr_en_FAST_fast2_branch0_0 \$894 - connect \rp_FAST_fast2_branch0_0 \$892 + connect \fast_src2__ren \$924 + connect \fast_src2__addr \$922 + connect \addr_en_FAST_fast2_trap0_1 \$920 + connect \rp_FAST_fast2_trap0_1 \$918 + connect \pick_FAST_fast2_trap0_1 \$916 + connect \addr_en_FAST_fast2_branch0_0 \$908 + connect \rp_FAST_fast2_branch0_0 \$906 connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$890 + connect \pick_FAST_fast2_branch0_0 \$904 connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$882 - connect \fast_src1__addr \$880 - connect \addr_en_FAST_fast1_spr0_2 \$876 - connect \rp_FAST_fast1_spr0_2 \$874 - connect \pick_FAST_fast1_spr0_2 \$872 - connect \addr_en_FAST_fast1_trap0_1 \$864 - connect \rp_FAST_fast1_trap0_1 \$862 - connect \pick_FAST_fast1_trap0_1 \$860 - connect \addr_en_FAST_fast1_branch0_0 \$852 - connect \rp_FAST_fast1_branch0_0 \$850 + connect \fast_src1__ren \$896 + connect \fast_src1__addr \$894 + connect \addr_en_FAST_fast1_spr0_2 \$890 + connect \rp_FAST_fast1_spr0_2 \$888 + connect \pick_FAST_fast1_spr0_2 \$886 + connect \addr_en_FAST_fast1_trap0_1 \$878 + connect \rp_FAST_fast1_trap0_1 \$876 + connect \pick_FAST_fast1_trap0_1 \$874 + connect \addr_en_FAST_fast1_branch0_0 \$866 + connect \rp_FAST_fast1_branch0_0 \$864 connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$848 + connect \pick_FAST_fast1_branch0_0 \$862 connect \rdflag_FAST_fast1_0 \core_fast1_ok connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$840 - connect \rp_CR_cr_c_cr0_0 \$834 + connect \addr_en_CR_cr_c_cr0_0 \$854 + connect \rp_CR_cr_c_cr0_0 \$848 connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$832 + connect \pick_CR_cr_c_cr0_0 \$846 connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$824 - connect \rp_CR_cr_b_cr0_0 \$818 + connect \addr_en_CR_cr_b_cr0_0 \$838 + connect \rp_CR_cr_b_cr0_0 \$832 connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$816 + connect \pick_CR_cr_b_cr0_0 \$830 connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$808 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$805 - connect \rp_CR_cr_a_branch0_1 \$799 - connect \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 - connect \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 - connect \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$797 - connect \addr_en_CR_cr_a_cr0_0 \$789 - connect \rp_CR_cr_a_cr0_0 \$783 + connect \cr_src1__ren \$822 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$819 + connect \rp_CR_cr_a_branch0_1 \$813 + connect \fus_cu_rd__go_i$80 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$80 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$80 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$811 + connect \addr_en_CR_cr_a_cr0_0 \$803 + connect \rp_CR_cr_a_cr0_0 \$797 connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$781 + connect \pick_CR_cr_a_cr0_0 \$795 connect \rdflag_CR_cr_a_0 \core_cr_in1_ok connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$773 - connect \rp_CR_full_cr_cr0_0 \$771 + connect \addr_en_CR_full_cr_cr0_0 \$787 + connect \rp_CR_full_cr_cr0_0 \$785 connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$769 + connect \pick_CR_full_cr_cr0_0 \$783 connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$761 - connect \rp_XER_xer_ov_spr0_0 \$759 + connect \addr_en_XER_xer_ov_spr0_0 \$775 + connect \rp_XER_xer_ov_spr0_0 \$773 connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$757 - connect \rdflag_XER_xer_ov_0 \$749 - connect \xer_src2__ren \$737 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$735 - connect \rp_XER_xer_ca_shiftrot0_2 \$733 - connect \pick_XER_xer_ca_shiftrot0_2 \$731 - connect \addr_en_XER_xer_ca_spr0_1 \$723 - connect \rp_XER_xer_ca_spr0_1 \$721 - connect \pick_XER_xer_ca_spr0_1 \$719 - connect \addr_en_XER_xer_ca_alu0_0 \$711 - connect \rp_XER_xer_ca_alu0_0 \$709 + connect \pick_XER_xer_ov_spr0_0 \$771 + connect \rdflag_XER_xer_ov_0 \$763 + connect \xer_src2__ren \$751 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$749 + connect \rp_XER_xer_ca_shiftrot0_2 \$747 + connect \pick_XER_xer_ca_shiftrot0_2 \$745 + connect \addr_en_XER_xer_ca_spr0_1 \$737 + connect \rp_XER_xer_ca_spr0_1 \$735 + connect \pick_XER_xer_ca_spr0_1 \$733 + connect \addr_en_XER_xer_ca_alu0_0 \$725 + connect \rp_XER_xer_ca_alu0_0 \$723 connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$707 - connect \rdflag_XER_xer_ca_0 \$699 - connect \xer_src1__ren \$681 - connect \addr_en_XER_xer_so_shiftrot0_5 \$679 - connect \rp_XER_xer_so_shiftrot0_5 \$677 - connect \pick_XER_xer_so_shiftrot0_5 \$675 - connect \addr_en_XER_xer_so_mul0_4 \$667 - connect \rp_XER_xer_so_mul0_4 \$665 - connect \pick_XER_xer_so_mul0_4 \$663 - connect \addr_en_XER_xer_so_div0_3 \$655 - connect \rp_XER_xer_so_div0_3 \$653 - connect \pick_XER_xer_so_div0_3 \$651 - connect \addr_en_XER_xer_so_spr0_2 \$643 - connect \rp_XER_xer_so_spr0_2 \$641 - connect \pick_XER_xer_so_spr0_2 \$639 - connect \addr_en_XER_xer_so_logical0_1 \$631 - connect \rp_XER_xer_so_logical0_1 \$629 - connect \pick_XER_xer_so_logical0_1 \$627 - connect \addr_en_XER_xer_so_alu0_0 \$619 - connect \rp_XER_xer_so_alu0_0 \$617 + connect \pick_XER_xer_ca_alu0_0 \$721 + connect \rdflag_XER_xer_ca_0 \$713 + connect \xer_src1__ren \$695 + connect \addr_en_XER_xer_so_shiftrot0_5 \$693 + connect \rp_XER_xer_so_shiftrot0_5 \$691 + connect \pick_XER_xer_so_shiftrot0_5 \$689 + connect \addr_en_XER_xer_so_mul0_4 \$681 + connect \rp_XER_xer_so_mul0_4 \$679 + connect \pick_XER_xer_so_mul0_4 \$677 + connect \addr_en_XER_xer_so_div0_3 \$669 + connect \rp_XER_xer_so_div0_3 \$667 + connect \pick_XER_xer_so_div0_3 \$665 + connect \addr_en_XER_xer_so_spr0_2 \$657 + connect \rp_XER_xer_so_spr0_2 \$655 + connect \pick_XER_xer_so_spr0_2 \$653 + connect \addr_en_XER_xer_so_logical0_1 \$645 + connect \rp_XER_xer_so_logical0_1 \$643 + connect \pick_XER_xer_so_logical0_1 \$641 + connect \addr_en_XER_xer_so_alu0_0 \$633 + connect \rp_XER_xer_so_alu0_0 \$631 connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$615 - connect \rdflag_XER_xer_so_0 \$607 - connect \int_src3__ren \$595 - connect \int_src3__addr \$593 - connect \addr_en_INT_rc_ldst0_1 \$591 - connect \rp_INT_rc_ldst0_1 \$589 - connect \pick_INT_rc_ldst0_1 \$587 - connect \addr_en_INT_rc_shiftrot0_0 \$579 - connect \rp_INT_rc_shiftrot0_0 \$577 + connect \pick_XER_xer_so_alu0_0 \$629 + connect \rdflag_XER_xer_so_0 \$621 + connect \int_src3__ren \$609 + connect \int_src3__addr \$607 + connect \addr_en_INT_rc_ldst0_1 \$605 + connect \rp_INT_rc_ldst0_1 \$603 + connect \pick_INT_rc_ldst0_1 \$601 + connect \addr_en_INT_rc_shiftrot0_0 \$593 + connect \rp_INT_rc_shiftrot0_0 \$591 connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$575 + connect \pick_INT_rc_shiftrot0_0 \$589 connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$567 - connect \int_src2__addr \$565 - connect \addr_en_INT_rb_ldst0_7 \$551 - connect \rp_INT_rb_ldst0_7 \$549 - connect \pick_INT_rb_ldst0_7 \$547 - connect \addr_en_INT_rb_shiftrot0_6 \$539 - connect \rp_INT_rb_shiftrot0_6 \$537 - connect \pick_INT_rb_shiftrot0_6 \$535 - connect \addr_en_INT_rb_mul0_5 \$527 - connect \rp_INT_rb_mul0_5 \$525 - connect \pick_INT_rb_mul0_5 \$523 - connect \addr_en_INT_rb_div0_4 \$515 - connect \rp_INT_rb_div0_4 \$513 - connect \pick_INT_rb_div0_4 \$511 - connect \addr_en_INT_rb_logical0_3 \$503 - connect \rp_INT_rb_logical0_3 \$501 - connect \pick_INT_rb_logical0_3 \$499 - connect \addr_en_INT_rb_trap0_2 \$491 - connect \rp_INT_rb_trap0_2 \$489 - connect \pick_INT_rb_trap0_2 \$487 - connect \addr_en_INT_rb_cr0_1 \$479 - connect \rp_INT_rb_cr0_1 \$477 - connect \pick_INT_rb_cr0_1 \$475 - connect \addr_en_INT_rb_alu0_0 \$467 - connect \rp_INT_rb_alu0_0 \$465 + connect \int_src2__ren \$581 + connect \int_src2__addr \$579 + connect \addr_en_INT_rb_ldst0_7 \$565 + connect \rp_INT_rb_ldst0_7 \$563 + connect \pick_INT_rb_ldst0_7 \$561 + connect \addr_en_INT_rb_shiftrot0_6 \$553 + connect \rp_INT_rb_shiftrot0_6 \$551 + connect \pick_INT_rb_shiftrot0_6 \$549 + connect \addr_en_INT_rb_mul0_5 \$541 + connect \rp_INT_rb_mul0_5 \$539 + connect \pick_INT_rb_mul0_5 \$537 + connect \addr_en_INT_rb_div0_4 \$529 + connect \rp_INT_rb_div0_4 \$527 + connect \pick_INT_rb_div0_4 \$525 + connect \addr_en_INT_rb_logical0_3 \$517 + connect \rp_INT_rb_logical0_3 \$515 + connect \pick_INT_rb_logical0_3 \$513 + connect \addr_en_INT_rb_trap0_2 \$505 + connect \rp_INT_rb_trap0_2 \$503 + connect \pick_INT_rb_trap0_2 \$501 + connect \addr_en_INT_rb_cr0_1 \$493 + connect \rp_INT_rb_cr0_1 \$491 + connect \pick_INT_rb_cr0_1 \$489 + connect \addr_en_INT_rb_alu0_0 \$481 + connect \rp_INT_rb_alu0_0 \$479 connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 @@ -84586,69 +85604,69 @@ module \core connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$463 + connect \pick_INT_rb_alu0_0 \$477 connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$455 - connect \int_src1__addr \$453 - connect \addr_en_INT_ra_ldst0_8 \$437 - connect \rp_INT_ra_ldst0_8 \$435 - connect \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 - connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 - connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$433 - connect \addr_en_INT_ra_shiftrot0_7 \$425 - connect \rp_INT_ra_shiftrot0_7 \$423 - connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 - connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 - connect \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 - connect \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 - connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$421 - connect \addr_en_INT_ra_mul0_6 \$413 - connect \rp_INT_ra_mul0_6 \$411 - connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 - connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 - connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$409 - connect \addr_en_INT_ra_div0_5 \$401 - connect \rp_INT_ra_div0_5 \$399 - connect \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 - connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 - connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$397 - connect \addr_en_INT_ra_spr0_4 \$389 - connect \rp_INT_ra_spr0_4 \$387 - connect \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 - connect \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 - connect \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 - connect \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 - connect \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 - connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$385 - connect \addr_en_INT_ra_logical0_3 \$377 - connect \rp_INT_ra_logical0_3 \$375 - connect \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 - connect \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 - connect \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$373 - connect \addr_en_INT_ra_trap0_2 \$365 - connect \rp_INT_ra_trap0_2 \$363 - connect \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 - connect \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 - connect \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 - connect \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$361 - connect \addr_en_INT_ra_cr0_1 \$353 - connect \rp_INT_ra_cr0_1 \$351 - connect \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 - connect \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 - connect \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 - connect \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 - connect \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 - connect \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$349 - connect \addr_en_INT_ra_alu0_0 \$341 - connect \rp_INT_ra_alu0_0 \$339 + connect \int_src1__ren \$469 + connect \int_src1__addr \$467 + connect \addr_en_INT_ra_ldst0_8 \$451 + connect \rp_INT_ra_ldst0_8 \$449 + connect \fus_cu_rd__go_i$60 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$60 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$60 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$447 + connect \addr_en_INT_ra_shiftrot0_7 \$439 + connect \rp_INT_ra_shiftrot0_7 \$437 + connect \fus_cu_rd__go_i$57 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$57 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$57 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$57 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$57 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$435 + connect \addr_en_INT_ra_mul0_6 \$427 + connect \rp_INT_ra_mul0_6 \$425 + connect \fus_cu_rd__go_i$54 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$54 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$54 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$423 + connect \addr_en_INT_ra_div0_5 \$415 + connect \rp_INT_ra_div0_5 \$413 + connect \fus_cu_rd__go_i$51 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$51 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$51 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$411 + connect \addr_en_INT_ra_spr0_4 \$403 + connect \rp_INT_ra_spr0_4 \$401 + connect \fus_cu_rd__go_i$48 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$48 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$48 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$48 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$48 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$48 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$399 + connect \addr_en_INT_ra_logical0_3 \$391 + connect \rp_INT_ra_logical0_3 \$389 + connect \fus_cu_rd__go_i$45 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$45 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$45 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$387 + connect \addr_en_INT_ra_trap0_2 \$379 + connect \rp_INT_ra_trap0_2 \$377 + connect \fus_cu_rd__go_i$42 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$42 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$42 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$42 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$375 + connect \addr_en_INT_ra_cr0_1 \$367 + connect \rp_INT_ra_cr0_1 \$365 + connect \fus_cu_rd__go_i$39 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$39 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$39 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$39 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$39 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$39 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$363 + connect \addr_en_INT_ra_alu0_0 \$355 + connect \rp_INT_ra_alu0_0 \$353 connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 @@ -84662,17 +85680,17 @@ module \core connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$337 + connect \pick_INT_ra_alu0_0 \$351 connect \rdflag_INT_ra_0 \core_reg1_ok - connect \en_ldst0 \$196 - connect \en_shiftrot0 \$192 - connect \en_mul0 \$188 - connect \en_div0 \$184 - connect \en_spr0 \$180 - connect \en_logical0 \$176 - connect \en_trap0 \$172 - connect \en_branch0 \$168 - connect \en_cr0 \$164 + connect \en_ldst0 \$210 + connect \en_shiftrot0 \$206 + connect \en_mul0 \$202 + connect \en_div0 \$198 + connect \en_spr0 \$194 + connect \en_logical0 \$190 + connect \en_trap0 \$186 + connect \en_branch0 \$182 + connect \en_cr0 \$178 connect \fu_enable [9] \en_ldst0 connect \fu_enable [8] \en_shiftrot0 connect \fu_enable [7] \en_mul0 @@ -84683,7 +85701,7 @@ module \core connect \fu_enable [2] \en_branch0 connect \fu_enable [1] \en_cr0 connect \fu_enable [0] \en_alu0 - connect \en_alu0 \$160 + connect \en_alu0 \$174 connect \dec_LDST_bigendian \bigendian_i connect \dec_LDST_raw_opcode_in \raw_insn_i connect \dec_SHIFT_ROT_bigendian \bigendian_i @@ -84703,97 +85721,97 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:48043.1-48676.10" +attribute \src "libresoc.v:48741.1-49374.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:48044.7-48044.20" + attribute \src "libresoc.v:48742.7-48742.20" wire $0\initial[0:0] - attribute \src "libresoc.v:48590.3-48598.6" - wire width 8 $0\ren_delay$17$next[7:0]$3052 - attribute \src "libresoc.v:48426.3-48427.43" - wire width 8 $0\ren_delay$17[7:0]$3049 - attribute \src "libresoc.v:48372.13-48372.35" - wire width 8 $0\ren_delay$17[7:0]$3066 - attribute \src "libresoc.v:48609.3-48617.6" - wire width 8 $0\ren_delay$34$next[7:0]$3056 - attribute \src "libresoc.v:48424.3-48425.43" - wire width 8 $0\ren_delay$34[7:0]$3047 - attribute \src "libresoc.v:48376.13-48376.35" - wire width 8 $0\ren_delay$34[7:0]$3068 - attribute \src "libresoc.v:48628.3-48636.6" - wire width 8 $0\ren_delay$next[7:0]$3060 - attribute \src "libresoc.v:48428.3-48429.35" + attribute \src "libresoc.v:49288.3-49296.6" + wire width 8 $0\ren_delay$17$next[7:0]$3086 + attribute \src "libresoc.v:49124.3-49125.43" + wire width 8 $0\ren_delay$17[7:0]$3083 + attribute \src "libresoc.v:49070.13-49070.35" + wire width 8 $0\ren_delay$17[7:0]$3100 + attribute \src "libresoc.v:49307.3-49315.6" + wire width 8 $0\ren_delay$34$next[7:0]$3090 + attribute \src "libresoc.v:49122.3-49123.43" + wire width 8 $0\ren_delay$34[7:0]$3081 + attribute \src "libresoc.v:49074.13-49074.35" + wire width 8 $0\ren_delay$34[7:0]$3102 + attribute \src "libresoc.v:49326.3-49334.6" + wire width 8 $0\ren_delay$next[7:0]$3094 + attribute \src "libresoc.v:49126.3-49127.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:48637.3-48646.6" + attribute \src "libresoc.v:49335.3-49344.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:48599.3-48608.6" + attribute \src "libresoc.v:49297.3-49306.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:48618.3-48627.6" + attribute \src "libresoc.v:49316.3-49325.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:48590.3-48598.6" - wire width 8 $1\ren_delay$17$next[7:0]$3053 - attribute \src "libresoc.v:48609.3-48617.6" - wire width 8 $1\ren_delay$34$next[7:0]$3057 - attribute \src "libresoc.v:48628.3-48636.6" - wire width 8 $1\ren_delay$next[7:0]$3061 - attribute \src "libresoc.v:48370.13-48370.30" + attribute \src "libresoc.v:49288.3-49296.6" + wire width 8 $1\ren_delay$17$next[7:0]$3087 + attribute \src "libresoc.v:49307.3-49315.6" + wire width 8 $1\ren_delay$34$next[7:0]$3091 + attribute \src "libresoc.v:49326.3-49334.6" + wire width 8 $1\ren_delay$next[7:0]$3095 + attribute \src "libresoc.v:49068.13-49068.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:48637.3-48646.6" + attribute \src "libresoc.v:49335.3-49344.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:48599.3-48608.6" + attribute \src "libresoc.v:49297.3-49306.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:48618.3-48627.6" + attribute \src "libresoc.v:49316.3-49325.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:48400.17-48400.125" - wire width 4 $or$libresoc.v:48400$3022_Y - attribute \src "libresoc.v:48401.18-48401.126" - wire width 4 $or$libresoc.v:48401$3023_Y - attribute \src "libresoc.v:48402.18-48402.96" - wire width 4 $or$libresoc.v:48402$3024_Y - attribute \src "libresoc.v:48403.18-48403.96" - wire width 4 $or$libresoc.v:48403$3025_Y - attribute \src "libresoc.v:48406.18-48406.126" - wire width 4 $or$libresoc.v:48406$3028_Y - attribute \src "libresoc.v:48407.18-48407.126" - wire width 4 $or$libresoc.v:48407$3029_Y - attribute \src "libresoc.v:48408.18-48408.97" - wire width 4 $or$libresoc.v:48408$3030_Y - attribute \src "libresoc.v:48409.18-48409.126" - wire width 4 $or$libresoc.v:48409$3031_Y - attribute \src "libresoc.v:48410.18-48410.126" - wire width 4 $or$libresoc.v:48410$3032_Y - attribute \src "libresoc.v:48411.18-48411.97" - wire width 4 $or$libresoc.v:48411$3033_Y - attribute \src "libresoc.v:48412.18-48412.97" - wire width 4 $or$libresoc.v:48412$3034_Y - attribute \src "libresoc.v:48414.18-48414.126" - wire width 4 $or$libresoc.v:48414$3036_Y - attribute \src "libresoc.v:48415.17-48415.125" - wire width 4 $or$libresoc.v:48415$3037_Y - attribute \src "libresoc.v:48416.18-48416.126" - wire width 4 $or$libresoc.v:48416$3038_Y - attribute \src "libresoc.v:48417.18-48417.97" - wire width 4 $or$libresoc.v:48417$3039_Y - attribute \src "libresoc.v:48418.18-48418.126" - wire width 4 $or$libresoc.v:48418$3040_Y - attribute \src "libresoc.v:48419.18-48419.126" - wire width 4 $or$libresoc.v:48419$3041_Y - attribute \src "libresoc.v:48420.18-48420.97" - wire width 4 $or$libresoc.v:48420$3042_Y - attribute \src "libresoc.v:48421.18-48421.97" - wire width 4 $or$libresoc.v:48421$3043_Y - attribute \src "libresoc.v:48422.17-48422.125" - wire width 4 $or$libresoc.v:48422$3044_Y - attribute \src "libresoc.v:48423.17-48423.94" - wire width 4 $or$libresoc.v:48423$3045_Y - attribute \src "libresoc.v:48404.18-48404.100" - wire $reduce_or$libresoc.v:48404$3026_Y - attribute \src "libresoc.v:48405.17-48405.95" - wire $reduce_or$libresoc.v:48405$3027_Y - attribute \src "libresoc.v:48413.18-48413.100" - wire $reduce_or$libresoc.v:48413$3035_Y + attribute \src "libresoc.v:49098.17-49098.125" + wire width 4 $or$libresoc.v:49098$3056_Y + attribute \src "libresoc.v:49099.18-49099.126" + wire width 4 $or$libresoc.v:49099$3057_Y + attribute \src "libresoc.v:49100.18-49100.96" + wire width 4 $or$libresoc.v:49100$3058_Y + attribute \src "libresoc.v:49101.18-49101.96" + wire width 4 $or$libresoc.v:49101$3059_Y + attribute \src "libresoc.v:49104.18-49104.126" + wire width 4 $or$libresoc.v:49104$3062_Y + attribute \src "libresoc.v:49105.18-49105.126" + wire width 4 $or$libresoc.v:49105$3063_Y + attribute \src "libresoc.v:49106.18-49106.97" + wire width 4 $or$libresoc.v:49106$3064_Y + attribute \src "libresoc.v:49107.18-49107.126" + wire width 4 $or$libresoc.v:49107$3065_Y + attribute \src "libresoc.v:49108.18-49108.126" + wire width 4 $or$libresoc.v:49108$3066_Y + attribute \src "libresoc.v:49109.18-49109.97" + wire width 4 $or$libresoc.v:49109$3067_Y + attribute \src "libresoc.v:49110.18-49110.97" + wire width 4 $or$libresoc.v:49110$3068_Y + attribute \src "libresoc.v:49112.18-49112.126" + wire width 4 $or$libresoc.v:49112$3070_Y + attribute \src "libresoc.v:49113.17-49113.125" + wire width 4 $or$libresoc.v:49113$3071_Y + attribute \src "libresoc.v:49114.18-49114.126" + wire width 4 $or$libresoc.v:49114$3072_Y + attribute \src "libresoc.v:49115.18-49115.97" + wire width 4 $or$libresoc.v:49115$3073_Y + attribute \src "libresoc.v:49116.18-49116.126" + wire width 4 $or$libresoc.v:49116$3074_Y + attribute \src "libresoc.v:49117.18-49117.126" + wire width 4 $or$libresoc.v:49117$3075_Y + attribute \src "libresoc.v:49118.18-49118.97" + wire width 4 $or$libresoc.v:49118$3076_Y + attribute \src "libresoc.v:49119.18-49119.97" + wire width 4 $or$libresoc.v:49119$3077_Y + attribute \src "libresoc.v:49120.17-49120.125" + wire width 4 $or$libresoc.v:49120$3078_Y + attribute \src "libresoc.v:49121.17-49121.94" + wire width 4 $or$libresoc.v:49121$3079_Y + attribute \src "libresoc.v:49102.18-49102.100" + wire $reduce_or$libresoc.v:49102$3060_Y + attribute \src "libresoc.v:49103.17-49103.95" + wire $reduce_or$libresoc.v:49103$3061_Y + attribute \src "libresoc.v:49111.18-49111.100" + wire $reduce_or$libresoc.v:49111$3069_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" @@ -84842,27 +85860,27 @@ module \cr wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 15 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 13 \data_i + wire width 4 input 14 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \data_i$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 2 \full_rd2__data_o + wire width 32 output 3 \full_rd2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 1 \full_rd2__ren + wire width 8 input 2 \full_rd2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 3 \full_rd__data_o + wire width 32 output 4 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 4 \full_rd__ren + wire width 8 input 5 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 11 \full_wr__data_i + wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 12 \full_wr__wen - attribute \src "libresoc.v:48044.7-48044.15" + wire width 8 input 13 \full_wr__wen + attribute \src "libresoc.v:48742.7-48742.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \reg_0_dest10__data_i @@ -85133,23 +86151,23 @@ module \cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 8 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src1__data_o + wire width 4 output 6 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 6 \src1__ren + wire width 8 input 7 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src2__data_o + wire width 4 output 8 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 8 \src2__ren + wire width 8 input 9 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 9 \src3__data_o + wire width 4 output 10 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 10 \src3__ren + wire width 8 input 11 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 14 \wen + wire width 8 input 15 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48400$3022 + cell $or $or$libresoc.v:49098$3056 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85157,10 +86175,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:48400$3022_Y + connect \Y $or$libresoc.v:49098$3056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48401$3023 + cell $or $or$libresoc.v:49099$3057 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85168,10 +86186,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:48401$3023_Y + connect \Y $or$libresoc.v:49099$3057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48402$3024 + cell $or $or$libresoc.v:49100$3058 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85179,10 +86197,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:48402$3024_Y + connect \Y $or$libresoc.v:49100$3058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48403$3025 + cell $or $or$libresoc.v:49101$3059 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85190,10 +86208,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:48403$3025_Y + connect \Y $or$libresoc.v:49101$3059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48406$3028 + cell $or $or$libresoc.v:49104$3062 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85201,10 +86219,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:48406$3028_Y + connect \Y $or$libresoc.v:49104$3062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48407$3029 + cell $or $or$libresoc.v:49105$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85212,10 +86230,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:48407$3029_Y + connect \Y $or$libresoc.v:49105$3063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48408$3030 + cell $or $or$libresoc.v:49106$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85223,10 +86241,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:48408$3030_Y + connect \Y $or$libresoc.v:49106$3064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48409$3031 + cell $or $or$libresoc.v:49107$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85234,10 +86252,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:48409$3031_Y + connect \Y $or$libresoc.v:49107$3065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48410$3032 + cell $or $or$libresoc.v:49108$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85245,10 +86263,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:48410$3032_Y + connect \Y $or$libresoc.v:49108$3066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48411$3033 + cell $or $or$libresoc.v:49109$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85256,10 +86274,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:48411$3033_Y + connect \Y $or$libresoc.v:49109$3067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48412$3034 + cell $or $or$libresoc.v:49110$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85267,10 +86285,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:48412$3034_Y + connect \Y $or$libresoc.v:49110$3068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48414$3036 + cell $or $or$libresoc.v:49112$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85278,10 +86296,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:48414$3036_Y + connect \Y $or$libresoc.v:49112$3070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48415$3037 + cell $or $or$libresoc.v:49113$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85289,10 +86307,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:48415$3037_Y + connect \Y $or$libresoc.v:49113$3071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48416$3038 + cell $or $or$libresoc.v:49114$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85300,10 +86318,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:48416$3038_Y + connect \Y $or$libresoc.v:49114$3072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48417$3039 + cell $or $or$libresoc.v:49115$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85311,10 +86329,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:48417$3039_Y + connect \Y $or$libresoc.v:49115$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48418$3040 + cell $or $or$libresoc.v:49116$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85322,10 +86340,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:48418$3040_Y + connect \Y $or$libresoc.v:49116$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48419$3041 + cell $or $or$libresoc.v:49117$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85333,10 +86351,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:48419$3041_Y + connect \Y $or$libresoc.v:49117$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48420$3042 + cell $or $or$libresoc.v:49118$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85344,10 +86362,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:48420$3042_Y + connect \Y $or$libresoc.v:49118$3076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48421$3043 + cell $or $or$libresoc.v:49119$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85355,10 +86373,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:48421$3043_Y + connect \Y $or$libresoc.v:49119$3077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:48422$3044 + cell $or $or$libresoc.v:49120$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85366,10 +86384,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:48422$3044_Y + connect \Y $or$libresoc.v:49120$3078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:48423$3045 + cell $or $or$libresoc.v:49121$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85377,34 +86395,34 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:48423$3045_Y + connect \Y $or$libresoc.v:49121$3079_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48404$3026 + cell $reduce_or $reduce_or$libresoc.v:49102$3060 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:48404$3026_Y + connect \Y $reduce_or$libresoc.v:49102$3060_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48405$3027 + cell $reduce_or $reduce_or$libresoc.v:49103$3061 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:48405$3027_Y + connect \Y $reduce_or$libresoc.v:49103$3061_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:48413$3035 + cell $reduce_or $reduce_or$libresoc.v:49111$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:48413$3035_Y + connect \Y $reduce_or$libresoc.v:49111$3069_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:48430.9-48449.4" + attribute \src "libresoc.v:49128.9-49147.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85426,7 +86444,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48450.9-48469.4" + attribute \src "libresoc.v:49148.9-49167.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85448,7 +86466,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48470.9-48489.4" + attribute \src "libresoc.v:49168.9-49187.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85470,7 +86488,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48490.9-48509.4" + attribute \src "libresoc.v:49188.9-49207.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85492,7 +86510,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48510.9-48529.4" + attribute \src "libresoc.v:49208.9-49227.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85514,7 +86532,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48530.9-48549.4" + attribute \src "libresoc.v:49228.9-49247.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85536,7 +86554,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48550.9-48569.4" + attribute \src "libresoc.v:49248.9-49267.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85558,7 +86576,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:48570.9-48589.4" + attribute \src "libresoc.v:49268.9-49287.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -85579,67 +86597,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:48044.7-48044.20" - process $proc$libresoc.v:48044$3063 + attribute \src "libresoc.v:48742.7-48742.20" + process $proc$libresoc.v:48742$3097 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:48370.13-48370.30" - process $proc$libresoc.v:48370$3064 + attribute \src "libresoc.v:49068.13-49068.30" + process $proc$libresoc.v:49068$3098 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:48372.13-48372.35" - process $proc$libresoc.v:48372$3065 + attribute \src "libresoc.v:49070.13-49070.35" + process $proc$libresoc.v:49070$3099 assign { } { } - assign $0\ren_delay$17[7:0]$3066 8'00000000 + assign $0\ren_delay$17[7:0]$3100 8'00000000 sync always sync init - update \ren_delay$17 $0\ren_delay$17[7:0]$3066 + update \ren_delay$17 $0\ren_delay$17[7:0]$3100 end - attribute \src "libresoc.v:48376.13-48376.35" - process $proc$libresoc.v:48376$3067 + attribute \src "libresoc.v:49074.13-49074.35" + process $proc$libresoc.v:49074$3101 assign { } { } - assign $0\ren_delay$34[7:0]$3068 8'00000000 + assign $0\ren_delay$34[7:0]$3102 8'00000000 sync always sync init - update \ren_delay$34 $0\ren_delay$34[7:0]$3068 + update \ren_delay$34 $0\ren_delay$34[7:0]$3102 end - attribute \src "libresoc.v:48424.3-48425.43" - process $proc$libresoc.v:48424$3046 + attribute \src "libresoc.v:49122.3-49123.43" + process $proc$libresoc.v:49122$3080 assign { } { } - assign $0\ren_delay$34[7:0]$3047 \ren_delay$34$next + assign $0\ren_delay$34[7:0]$3081 \ren_delay$34$next sync posedge \coresync_clk - update \ren_delay$34 $0\ren_delay$34[7:0]$3047 + update \ren_delay$34 $0\ren_delay$34[7:0]$3081 end - attribute \src "libresoc.v:48426.3-48427.43" - process $proc$libresoc.v:48426$3048 + attribute \src "libresoc.v:49124.3-49125.43" + process $proc$libresoc.v:49124$3082 assign { } { } - assign $0\ren_delay$17[7:0]$3049 \ren_delay$17$next + assign $0\ren_delay$17[7:0]$3083 \ren_delay$17$next sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$3049 + update \ren_delay$17 $0\ren_delay$17[7:0]$3083 end - attribute \src "libresoc.v:48428.3-48429.35" - process $proc$libresoc.v:48428$3050 + attribute \src "libresoc.v:49126.3-49127.35" + process $proc$libresoc.v:49126$3084 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:48590.3-48598.6" - process $proc$libresoc.v:48590$3051 + attribute \src "libresoc.v:49288.3-49296.6" + process $proc$libresoc.v:49288$3085 assign { } { } assign { } { } - assign $0\ren_delay$17$next[7:0]$3052 $1\ren_delay$17$next[7:0]$3053 - attribute \src "libresoc.v:48591.5-48591.29" + assign $0\ren_delay$17$next[7:0]$3086 $1\ren_delay$17$next[7:0]$3087 + attribute \src "libresoc.v:49289.5-49289.29" switch \initial - attribute \src "libresoc.v:48591.9-48591.17" + attribute \src "libresoc.v:49289.9-49289.17" case 1'1 case end @@ -85648,21 +86666,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$17$next[7:0]$3053 8'00000000 + assign $1\ren_delay$17$next[7:0]$3087 8'00000000 case - assign $1\ren_delay$17$next[7:0]$3053 \src2__ren + assign $1\ren_delay$17$next[7:0]$3087 \src2__ren end sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3052 + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3086 end - attribute \src "libresoc.v:48599.3-48608.6" - process $proc$libresoc.v:48599$3054 + attribute \src "libresoc.v:49297.3-49306.6" + process $proc$libresoc.v:49297$3088 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:48600.5-48600.29" + attribute \src "libresoc.v:49298.5-49298.29" switch \initial - attribute \src "libresoc.v:48600.9-48600.17" + attribute \src "libresoc.v:49298.9-49298.17" case 1'1 case end @@ -85678,14 +86696,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:48609.3-48617.6" - process $proc$libresoc.v:48609$3055 + attribute \src "libresoc.v:49307.3-49315.6" + process $proc$libresoc.v:49307$3089 assign { } { } assign { } { } - assign $0\ren_delay$34$next[7:0]$3056 $1\ren_delay$34$next[7:0]$3057 - attribute \src "libresoc.v:48610.5-48610.29" + assign $0\ren_delay$34$next[7:0]$3090 $1\ren_delay$34$next[7:0]$3091 + attribute \src "libresoc.v:49308.5-49308.29" switch \initial - attribute \src "libresoc.v:48610.9-48610.17" + attribute \src "libresoc.v:49308.9-49308.17" case 1'1 case end @@ -85694,21 +86712,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$34$next[7:0]$3057 8'00000000 + assign $1\ren_delay$34$next[7:0]$3091 8'00000000 case - assign $1\ren_delay$34$next[7:0]$3057 \src3__ren + assign $1\ren_delay$34$next[7:0]$3091 \src3__ren end sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3056 + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3090 end - attribute \src "libresoc.v:48618.3-48627.6" - process $proc$libresoc.v:48618$3058 + attribute \src "libresoc.v:49316.3-49325.6" + process $proc$libresoc.v:49316$3092 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:48619.5-48619.29" + attribute \src "libresoc.v:49317.5-49317.29" switch \initial - attribute \src "libresoc.v:48619.9-48619.17" + attribute \src "libresoc.v:49317.9-49317.17" case 1'1 case end @@ -85724,14 +86742,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:48628.3-48636.6" - process $proc$libresoc.v:48628$3059 + attribute \src "libresoc.v:49326.3-49334.6" + process $proc$libresoc.v:49326$3093 assign { } { } assign { } { } - assign $0\ren_delay$next[7:0]$3060 $1\ren_delay$next[7:0]$3061 - attribute \src "libresoc.v:48629.5-48629.29" + assign $0\ren_delay$next[7:0]$3094 $1\ren_delay$next[7:0]$3095 + attribute \src "libresoc.v:49327.5-49327.29" switch \initial - attribute \src "libresoc.v:48629.9-48629.17" + attribute \src "libresoc.v:49327.9-49327.17" case 1'1 case end @@ -85740,21 +86758,21 @@ module \cr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[7:0]$3061 8'00000000 + assign $1\ren_delay$next[7:0]$3095 8'00000000 case - assign $1\ren_delay$next[7:0]$3061 \src1__ren + assign $1\ren_delay$next[7:0]$3095 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[7:0]$3060 + update \ren_delay$next $0\ren_delay$next[7:0]$3094 end - attribute \src "libresoc.v:48637.3-48646.6" - process $proc$libresoc.v:48637$3062 + attribute \src "libresoc.v:49335.3-49344.6" + process $proc$libresoc.v:49335$3096 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:48638.5-48638.29" + attribute \src "libresoc.v:49336.5-49336.29" switch \initial - attribute \src "libresoc.v:48638.9-48638.17" + attribute \src "libresoc.v:49336.9-49336.17" case 1'1 case end @@ -85770,30 +86788,30 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - connect \$9 $or$libresoc.v:48400$3022_Y - connect \$11 $or$libresoc.v:48401$3023_Y - connect \$13 $or$libresoc.v:48402$3024_Y - connect \$15 $or$libresoc.v:48403$3025_Y - connect \$18 $reduce_or$libresoc.v:48404$3026_Y - connect \$1 $reduce_or$libresoc.v:48405$3027_Y - connect \$20 $or$libresoc.v:48406$3028_Y - connect \$22 $or$libresoc.v:48407$3029_Y - connect \$24 $or$libresoc.v:48408$3030_Y - connect \$26 $or$libresoc.v:48409$3031_Y - connect \$28 $or$libresoc.v:48410$3032_Y - connect \$30 $or$libresoc.v:48411$3033_Y - connect \$32 $or$libresoc.v:48412$3034_Y - connect \$35 $reduce_or$libresoc.v:48413$3035_Y - connect \$37 $or$libresoc.v:48414$3036_Y - connect \$3 $or$libresoc.v:48415$3037_Y - connect \$39 $or$libresoc.v:48416$3038_Y - connect \$41 $or$libresoc.v:48417$3039_Y - connect \$43 $or$libresoc.v:48418$3040_Y - connect \$45 $or$libresoc.v:48419$3041_Y - connect \$47 $or$libresoc.v:48420$3042_Y - connect \$49 $or$libresoc.v:48421$3043_Y - connect \$5 $or$libresoc.v:48422$3044_Y - connect \$7 $or$libresoc.v:48423$3045_Y + connect \$9 $or$libresoc.v:49098$3056_Y + connect \$11 $or$libresoc.v:49099$3057_Y + connect \$13 $or$libresoc.v:49100$3058_Y + connect \$15 $or$libresoc.v:49101$3059_Y + connect \$18 $reduce_or$libresoc.v:49102$3060_Y + connect \$1 $reduce_or$libresoc.v:49103$3061_Y + connect \$20 $or$libresoc.v:49104$3062_Y + connect \$22 $or$libresoc.v:49105$3063_Y + connect \$24 $or$libresoc.v:49106$3064_Y + connect \$26 $or$libresoc.v:49107$3065_Y + connect \$28 $or$libresoc.v:49108$3066_Y + connect \$30 $or$libresoc.v:49109$3067_Y + connect \$32 $or$libresoc.v:49110$3068_Y + connect \$35 $reduce_or$libresoc.v:49111$3069_Y + connect \$37 $or$libresoc.v:49112$3070_Y + connect \$3 $or$libresoc.v:49113$3071_Y + connect \$39 $or$libresoc.v:49114$3072_Y + connect \$41 $or$libresoc.v:49115$3073_Y + connect \$43 $or$libresoc.v:49116$3074_Y + connect \$45 $or$libresoc.v:49117$3075_Y + connect \$47 $or$libresoc.v:49118$3076_Y + connect \$49 $or$libresoc.v:49119$3077_Y + connect \$5 $or$libresoc.v:49120$3078_Y + connect \$7 $or$libresoc.v:49121$3079_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen @@ -85824,393 +86842,393 @@ module \cr connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:48680.1-49731.10" +attribute \src "libresoc.v:49378.1-50429.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:49332.3-49333.25" + attribute \src "libresoc.v:50030.3-50031.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 - attribute \src "libresoc.v:49304.3-49305.61" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 + attribute \src "libresoc.v:50002.3-50003.61" wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3189 - attribute \src "libresoc.v:49306.3-49307.55" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3223 + attribute \src "libresoc.v:50004.3-50005.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 - attribute \src "libresoc.v:49302.3-49303.65" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 + attribute \src "libresoc.v:50000.3-50001.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:49330.3-49331.39" + attribute \src "libresoc.v:50028.3-50029.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:49652.3-49660.6" - wire $0\alu_l_r_alu$next[0:0]$3240 - attribute \src "libresoc.v:49274.3-49275.39" + attribute \src "libresoc.v:50350.3-50358.6" + wire $0\alu_l_r_alu$next[0:0]$3274 + attribute \src "libresoc.v:49972.3-49973.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:49643.3-49651.6" - wire $0\alui_l_r_alui$next[0:0]$3237 - attribute \src "libresoc.v:49276.3-49277.43" + attribute \src "libresoc.v:50341.3-50349.6" + wire $0\alui_l_r_alui$next[0:0]$3271 + attribute \src "libresoc.v:49974.3-49975.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:49517.3-49538.6" - wire width 64 $0\data_r0__o$next[63:0]$3195 - attribute \src "libresoc.v:49298.3-49299.37" + attribute \src "libresoc.v:50215.3-50236.6" + wire width 64 $0\data_r0__o$next[63:0]$3229 + attribute \src "libresoc.v:49996.3-49997.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:49517.3-49538.6" - wire $0\data_r0__o_ok$next[0:0]$3196 - attribute \src "libresoc.v:49300.3-49301.43" + attribute \src "libresoc.v:50215.3-50236.6" + wire $0\data_r0__o_ok$next[0:0]$3230 + attribute \src "libresoc.v:49998.3-49999.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:49539.3-49560.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3203 - attribute \src "libresoc.v:49294.3-49295.49" + attribute \src "libresoc.v:50237.3-50258.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3237 + attribute \src "libresoc.v:49992.3-49993.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:49539.3-49560.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3204 - attribute \src "libresoc.v:49296.3-49297.55" + attribute \src "libresoc.v:50237.3-50258.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3238 + attribute \src "libresoc.v:49994.3-49995.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:49561.3-49582.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3211 - attribute \src "libresoc.v:49290.3-49291.43" + attribute \src "libresoc.v:50259.3-50280.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3245 + attribute \src "libresoc.v:49988.3-49989.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:49561.3-49582.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3212 - attribute \src "libresoc.v:49292.3-49293.49" + attribute \src "libresoc.v:50259.3-50280.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3246 + attribute \src "libresoc.v:49990.3-49991.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:49661.3-49670.6" + attribute \src "libresoc.v:50359.3-50368.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:49671.3-49680.6" + attribute \src "libresoc.v:50369.3-50378.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:49681.3-49690.6" + attribute \src "libresoc.v:50379.3-50388.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:48681.7-48681.20" + attribute \src "libresoc.v:49379.7-49379.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49460.3-49468.6" - wire $0\opc_l_r_opc$next[0:0]$3173 - attribute \src "libresoc.v:49316.3-49317.39" + attribute \src "libresoc.v:50158.3-50166.6" + wire $0\opc_l_r_opc$next[0:0]$3207 + attribute \src "libresoc.v:50014.3-50015.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:49451.3-49459.6" - wire $0\opc_l_s_opc$next[0:0]$3170 - attribute \src "libresoc.v:49318.3-49319.39" + attribute \src "libresoc.v:50149.3-50157.6" + wire $0\opc_l_s_opc$next[0:0]$3204 + attribute \src "libresoc.v:50016.3-50017.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:49691.3-49699.6" - wire width 3 $0\prev_wr_go$next[2:0]$3246 - attribute \src "libresoc.v:49328.3-49329.37" + attribute \src "libresoc.v:50389.3-50397.6" + wire width 3 $0\prev_wr_go$next[2:0]$3280 + attribute \src "libresoc.v:50026.3-50027.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:49405.3-49414.6" + attribute \src "libresoc.v:50103.3-50112.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:49496.3-49504.6" - wire width 3 $0\req_l_r_req$next[2:0]$3185 - attribute \src "libresoc.v:49308.3-49309.39" + attribute \src "libresoc.v:50194.3-50202.6" + wire width 3 $0\req_l_r_req$next[2:0]$3219 + attribute \src "libresoc.v:50006.3-50007.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:49487.3-49495.6" - wire width 3 $0\req_l_s_req$next[2:0]$3182 - attribute \src "libresoc.v:49310.3-49311.39" + attribute \src "libresoc.v:50185.3-50193.6" + wire width 3 $0\req_l_s_req$next[2:0]$3216 + attribute \src "libresoc.v:50008.3-50009.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:49424.3-49432.6" - wire $0\rok_l_r_rdok$next[0:0]$3161 - attribute \src "libresoc.v:49324.3-49325.41" + attribute \src "libresoc.v:50122.3-50130.6" + wire $0\rok_l_r_rdok$next[0:0]$3195 + attribute \src "libresoc.v:50022.3-50023.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:49415.3-49423.6" - wire $0\rok_l_s_rdok$next[0:0]$3158 - attribute \src "libresoc.v:49326.3-49327.41" + attribute \src "libresoc.v:50113.3-50121.6" + wire $0\rok_l_s_rdok$next[0:0]$3192 + attribute \src "libresoc.v:50024.3-50025.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:49442.3-49450.6" - wire $0\rst_l_r_rst$next[0:0]$3167 - attribute \src "libresoc.v:49320.3-49321.39" + attribute \src "libresoc.v:50140.3-50148.6" + wire $0\rst_l_r_rst$next[0:0]$3201 + attribute \src "libresoc.v:50018.3-50019.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:49433.3-49441.6" - wire $0\rst_l_s_rst$next[0:0]$3164 - attribute \src "libresoc.v:49322.3-49323.39" + attribute \src "libresoc.v:50131.3-50139.6" + wire $0\rst_l_s_rst$next[0:0]$3198 + attribute \src "libresoc.v:50020.3-50021.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:49478.3-49486.6" - wire width 6 $0\src_l_r_src$next[5:0]$3179 - attribute \src "libresoc.v:49312.3-49313.39" + attribute \src "libresoc.v:50176.3-50184.6" + wire width 6 $0\src_l_r_src$next[5:0]$3213 + attribute \src "libresoc.v:50010.3-50011.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:49469.3-49477.6" - wire width 6 $0\src_l_s_src$next[5:0]$3176 - attribute \src "libresoc.v:49314.3-49315.39" + attribute \src "libresoc.v:50167.3-50175.6" + wire width 6 $0\src_l_s_src$next[5:0]$3210 + attribute \src "libresoc.v:50012.3-50013.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:49583.3-49592.6" - wire width 64 $0\src_r0$next[63:0]$3219 - attribute \src "libresoc.v:49288.3-49289.29" + attribute \src "libresoc.v:50281.3-50290.6" + wire width 64 $0\src_r0$next[63:0]$3253 + attribute \src "libresoc.v:49986.3-49987.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:49593.3-49602.6" - wire width 64 $0\src_r1$next[63:0]$3222 - attribute \src "libresoc.v:49286.3-49287.29" + attribute \src "libresoc.v:50291.3-50300.6" + wire width 64 $0\src_r1$next[63:0]$3256 + attribute \src "libresoc.v:49984.3-49985.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:49603.3-49612.6" - wire width 32 $0\src_r2$next[31:0]$3225 - attribute \src "libresoc.v:49284.3-49285.29" + attribute \src "libresoc.v:50301.3-50310.6" + wire width 32 $0\src_r2$next[31:0]$3259 + attribute \src "libresoc.v:49982.3-49983.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:49613.3-49622.6" - wire width 4 $0\src_r3$next[3:0]$3228 - attribute \src "libresoc.v:49282.3-49283.29" + attribute \src "libresoc.v:50311.3-50320.6" + wire width 4 $0\src_r3$next[3:0]$3262 + attribute \src "libresoc.v:49980.3-49981.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:49623.3-49632.6" - wire width 4 $0\src_r4$next[3:0]$3231 - attribute \src "libresoc.v:49280.3-49281.29" + attribute \src "libresoc.v:50321.3-50330.6" + wire width 4 $0\src_r4$next[3:0]$3265 + attribute \src "libresoc.v:49978.3-49979.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:49633.3-49642.6" - wire width 4 $0\src_r5$next[3:0]$3234 - attribute \src "libresoc.v:49278.3-49279.29" + attribute \src "libresoc.v:50331.3-50340.6" + wire width 4 $0\src_r5$next[3:0]$3268 + attribute \src "libresoc.v:49976.3-49977.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:48799.7-48799.24" + attribute \src "libresoc.v:49497.7-49497.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 - attribute \src "libresoc.v:48828.14-48828.46" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 12 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 + attribute \src "libresoc.v:49526.14-49526.46" wire width 12 $1\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3192 - attribute \src "libresoc.v:48832.14-48832.41" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3226 + attribute \src "libresoc.v:49530.14-49530.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:49505.3-49516.6" - wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 - attribute \src "libresoc.v:48910.13-48910.45" + attribute \src "libresoc.v:50203.3-50214.6" + wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 + attribute \src "libresoc.v:49608.13-49608.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:48934.7-48934.26" + attribute \src "libresoc.v:49632.7-49632.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:49652.3-49660.6" - wire $1\alu_l_r_alu$next[0:0]$3241 - attribute \src "libresoc.v:48942.7-48942.25" + attribute \src "libresoc.v:50350.3-50358.6" + wire $1\alu_l_r_alu$next[0:0]$3275 + attribute \src "libresoc.v:49640.7-49640.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:49643.3-49651.6" - wire $1\alui_l_r_alui$next[0:0]$3238 - attribute \src "libresoc.v:48954.7-48954.27" + attribute \src "libresoc.v:50341.3-50349.6" + wire $1\alui_l_r_alui$next[0:0]$3272 + attribute \src "libresoc.v:49652.7-49652.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:49517.3-49538.6" - wire width 64 $1\data_r0__o$next[63:0]$3197 - attribute \src "libresoc.v:48988.14-48988.47" + attribute \src "libresoc.v:50215.3-50236.6" + wire width 64 $1\data_r0__o$next[63:0]$3231 + attribute \src "libresoc.v:49686.14-49686.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:49517.3-49538.6" - wire $1\data_r0__o_ok$next[0:0]$3198 - attribute \src "libresoc.v:48992.7-48992.27" + attribute \src "libresoc.v:50215.3-50236.6" + wire $1\data_r0__o_ok$next[0:0]$3232 + attribute \src "libresoc.v:49690.7-49690.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:49539.3-49560.6" - wire width 32 $1\data_r1__full_cr$next[31:0]$3205 - attribute \src "libresoc.v:48996.14-48996.38" + attribute \src "libresoc.v:50237.3-50258.6" + wire width 32 $1\data_r1__full_cr$next[31:0]$3239 + attribute \src "libresoc.v:49694.14-49694.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:49539.3-49560.6" - wire $1\data_r1__full_cr_ok$next[0:0]$3206 - attribute \src "libresoc.v:49000.7-49000.33" + attribute \src "libresoc.v:50237.3-50258.6" + wire $1\data_r1__full_cr_ok$next[0:0]$3240 + attribute \src "libresoc.v:49698.7-49698.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:49561.3-49582.6" - wire width 4 $1\data_r2__cr_a$next[3:0]$3213 - attribute \src "libresoc.v:49004.13-49004.33" + attribute \src "libresoc.v:50259.3-50280.6" + wire width 4 $1\data_r2__cr_a$next[3:0]$3247 + attribute \src "libresoc.v:49702.13-49702.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:49561.3-49582.6" - wire $1\data_r2__cr_a_ok$next[0:0]$3214 - attribute \src "libresoc.v:49008.7-49008.30" + attribute \src "libresoc.v:50259.3-50280.6" + wire $1\data_r2__cr_a_ok$next[0:0]$3248 + attribute \src "libresoc.v:49706.7-49706.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:49661.3-49670.6" + attribute \src "libresoc.v:50359.3-50368.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:49671.3-49680.6" + attribute \src "libresoc.v:50369.3-50378.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:49681.3-49690.6" + attribute \src "libresoc.v:50379.3-50388.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:49460.3-49468.6" - wire $1\opc_l_r_opc$next[0:0]$3174 - attribute \src "libresoc.v:49027.7-49027.25" + attribute \src "libresoc.v:50158.3-50166.6" + wire $1\opc_l_r_opc$next[0:0]$3208 + attribute \src "libresoc.v:49725.7-49725.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:49451.3-49459.6" - wire $1\opc_l_s_opc$next[0:0]$3171 - attribute \src "libresoc.v:49031.7-49031.25" + attribute \src "libresoc.v:50149.3-50157.6" + wire $1\opc_l_s_opc$next[0:0]$3205 + attribute \src "libresoc.v:49729.7-49729.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:49691.3-49699.6" - wire width 3 $1\prev_wr_go$next[2:0]$3247 - attribute \src "libresoc.v:49128.13-49128.30" + attribute \src "libresoc.v:50389.3-50397.6" + wire width 3 $1\prev_wr_go$next[2:0]$3281 + attribute \src "libresoc.v:49826.13-49826.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:49405.3-49414.6" + attribute \src "libresoc.v:50103.3-50112.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:49496.3-49504.6" - wire width 3 $1\req_l_r_req$next[2:0]$3186 - attribute \src "libresoc.v:49136.13-49136.31" + attribute \src "libresoc.v:50194.3-50202.6" + wire width 3 $1\req_l_r_req$next[2:0]$3220 + attribute \src "libresoc.v:49834.13-49834.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:49487.3-49495.6" - wire width 3 $1\req_l_s_req$next[2:0]$3183 - attribute \src "libresoc.v:49140.13-49140.31" + attribute \src "libresoc.v:50185.3-50193.6" + wire width 3 $1\req_l_s_req$next[2:0]$3217 + attribute \src "libresoc.v:49838.13-49838.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:49424.3-49432.6" - wire $1\rok_l_r_rdok$next[0:0]$3162 - attribute \src "libresoc.v:49152.7-49152.26" + attribute \src "libresoc.v:50122.3-50130.6" + wire $1\rok_l_r_rdok$next[0:0]$3196 + attribute \src "libresoc.v:49850.7-49850.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:49415.3-49423.6" - wire $1\rok_l_s_rdok$next[0:0]$3159 - attribute \src "libresoc.v:49156.7-49156.26" + attribute \src "libresoc.v:50113.3-50121.6" + wire $1\rok_l_s_rdok$next[0:0]$3193 + attribute \src "libresoc.v:49854.7-49854.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:49442.3-49450.6" - wire $1\rst_l_r_rst$next[0:0]$3168 - attribute \src "libresoc.v:49160.7-49160.25" + attribute \src "libresoc.v:50140.3-50148.6" + wire $1\rst_l_r_rst$next[0:0]$3202 + attribute \src "libresoc.v:49858.7-49858.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:49433.3-49441.6" - wire $1\rst_l_s_rst$next[0:0]$3165 - attribute \src "libresoc.v:49164.7-49164.25" + attribute \src "libresoc.v:50131.3-50139.6" + wire $1\rst_l_s_rst$next[0:0]$3199 + attribute \src "libresoc.v:49862.7-49862.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:49478.3-49486.6" - wire width 6 $1\src_l_r_src$next[5:0]$3180 - attribute \src "libresoc.v:49184.13-49184.32" + attribute \src "libresoc.v:50176.3-50184.6" + wire width 6 $1\src_l_r_src$next[5:0]$3214 + attribute \src "libresoc.v:49882.13-49882.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:49469.3-49477.6" - wire width 6 $1\src_l_s_src$next[5:0]$3177 - attribute \src "libresoc.v:49188.13-49188.32" + attribute \src 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wire $and$libresoc.v:49959$3147_Y + attribute \src "libresoc.v:49967.18-49967.133" + wire $and$libresoc.v:49967$3155_Y + attribute \src "libresoc.v:49968.18-49968.131" + wire $and$libresoc.v:49968$3156_Y + attribute \src "libresoc.v:49969.18-49969.182" + wire width 6 $and$libresoc.v:49969$3157_Y + attribute \src "libresoc.v:49970.18-49970.113" + wire width 6 $and$libresoc.v:49970$3158_Y + attribute \src "libresoc.v:49943.18-49943.113" + wire $eq$libresoc.v:49943$3131_Y + attribute \src "libresoc.v:49945.18-49945.119" + wire $eq$libresoc.v:49945$3133_Y + attribute \src "libresoc.v:49926.18-49926.97" + wire $not$libresoc.v:49926$3114_Y + attribute \src "libresoc.v:49928.18-49928.99" + wire $not$libresoc.v:49928$3116_Y + attribute \src "libresoc.v:49931.18-49931.113" + wire width 3 $not$libresoc.v:49931$3119_Y + attribute \src "libresoc.v:49934.18-49934.106" + wire $not$libresoc.v:49934$3122_Y + attribute \src "libresoc.v:49940.18-49940.119" + wire $not$libresoc.v:49940$3128_Y + attribute \src "libresoc.v:49955.17-49955.113" + wire width 6 $not$libresoc.v:49955$3143_Y + attribute \src "libresoc.v:49971.18-49971.114" + wire width 6 $not$libresoc.v:49971$3159_Y + attribute \src "libresoc.v:49938.18-49938.112" + wire $or$libresoc.v:49938$3126_Y + attribute \src "libresoc.v:49949.18-49949.122" + wire $or$libresoc.v:49949$3137_Y + attribute \src "libresoc.v:49950.18-49950.124" + wire $or$libresoc.v:49950$3138_Y + attribute \src "libresoc.v:49951.18-49951.155" + wire width 3 $or$libresoc.v:49951$3139_Y + attribute \src "libresoc.v:49952.18-49952.194" + wire width 6 $or$libresoc.v:49952$3140_Y + attribute \src "libresoc.v:49956.18-49956.120" + wire width 3 $or$libresoc.v:49956$3144_Y + attribute \src "libresoc.v:49966.17-49966.117" + wire width 6 $or$libresoc.v:49966$3154_Y + attribute \src "libresoc.v:49915.17-49915.104" + wire $reduce_and$libresoc.v:49915$3103_Y + attribute \src "libresoc.v:49933.18-49933.106" + wire $reduce_or$libresoc.v:49933$3121_Y + attribute \src "libresoc.v:49936.18-49936.113" + wire $reduce_or$libresoc.v:49936$3124_Y + attribute \src "libresoc.v:49937.18-49937.112" + wire $reduce_or$libresoc.v:49937$3125_Y + attribute \src "libresoc.v:49960.18-49960.118" + wire width 64 $ternary$libresoc.v:49960$3148_Y + attribute \src "libresoc.v:49961.18-49961.118" + wire width 64 $ternary$libresoc.v:49961$3149_Y + attribute \src "libresoc.v:49962.18-49962.118" + wire width 32 $ternary$libresoc.v:49962$3150_Y + attribute \src "libresoc.v:49963.18-49963.118" + wire width 4 $ternary$libresoc.v:49963$3151_Y + attribute \src "libresoc.v:49964.18-49964.118" + wire width 4 $ternary$libresoc.v:49964$3152_Y + attribute \src "libresoc.v:49965.18-49965.118" + wire width 4 $ternary$libresoc.v:49965$3153_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -86335,7 +87353,7 @@ module \cr0 wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_cr0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \alu_cr0_cr_a$2 @@ -86442,7 +87460,7 @@ module \cr0 wire width 7 \alu_cr0_cr_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_cr0_cr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \alu_cr0_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \alu_cr0_full_cr$1 @@ -86450,7 +87468,7 @@ module \cr0 wire \alu_cr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_cr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_cr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_cr0_p_ready_o @@ -86488,32 +87506,32 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 23 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 21 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 5 \cu_busy_o + wire output 6 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 4 \cu_issue_i + wire input 5 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 8 \cu_rd__go_i + wire width 6 input 9 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 7 \cu_rd__rel_o + wire width 6 output 8 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 6 \cu_rdmaskn_i + wire width 6 input 7 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 17 \cu_wr__go_i + wire width 3 input 18 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 16 \cu_wr__rel_o + wire width 3 output 17 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -86541,17 +87559,17 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 18 \dest1_o + wire width 64 output 19 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 20 \dest2_o + wire width 32 output 21 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 22 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 19 \full_cr_ok - attribute \src "libresoc.v:48681.7-48681.15" + wire width 4 output 23 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 20 \full_cr_ok + attribute \src "libresoc.v:49379.7-49379.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 16 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -86576,9 +87594,9 @@ module \cr0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_cr0__fn_unit + wire width 12 input 3 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_cr0__insn + wire width 32 input 4 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -86654,7 +87672,7 @@ module \cr0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_cr0__insn_type + wire width 7 input 2 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -86698,17 +87716,17 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 9 \src1_i + wire width 64 input 10 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 10 \src2_i + wire width 64 input 11 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 11 \src3_i + wire width 32 input 12 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 12 \src4_i + wire width 4 input 13 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 13 \src5_i + wire width 4 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src6_i + wire width 4 input 15 \src6_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -86746,7 +87764,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49218$3070 + cell $and $and$libresoc.v:49916$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -86754,10 +87772,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:49218$3070_Y + connect \Y $and$libresoc.v:49916$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49219$3071 + cell $and $and$libresoc.v:49917$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86765,10 +87783,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49219$3071_Y + connect \Y $and$libresoc.v:49917$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49220$3072 + cell $and $and$libresoc.v:49918$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86776,10 +87794,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49220$3072_Y + connect \Y $and$libresoc.v:49918$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:49221$3073 + cell $and $and$libresoc.v:49919$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86787,10 +87805,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:49221$3073_Y + connect \Y $and$libresoc.v:49919$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:49222$3074 + cell $and $and$libresoc.v:49920$3108 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -86798,10 +87816,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:49222$3074_Y + connect \Y $and$libresoc.v:49920$3108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:49223$3075 + cell $and $and$libresoc.v:49921$3109 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -86809,10 +87827,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49223$3075_Y + connect \Y $and$libresoc.v:49921$3109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49224$3076 + cell $and $and$libresoc.v:49922$3110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86820,10 +87838,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49224$3076_Y + connect \Y $and$libresoc.v:49922$3110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49225$3077 + cell $and $and$libresoc.v:49923$3111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86831,10 +87849,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49225$3077_Y + connect \Y $and$libresoc.v:49923$3111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:49226$3078 + cell $and $and$libresoc.v:49924$3112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86842,10 +87860,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:49226$3078_Y + connect \Y $and$libresoc.v:49924$3112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:49227$3079 + cell $and $and$libresoc.v:49925$3113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86853,10 +87871,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:49227$3079_Y + connect \Y $and$libresoc.v:49925$3113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:49229$3081 + cell $and $and$libresoc.v:49927$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86864,10 +87882,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:49229$3081_Y + connect \Y $and$libresoc.v:49927$3115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:49231$3083 + cell $and $and$libresoc.v:49929$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86875,10 +87893,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:49231$3083_Y + connect \Y $and$libresoc.v:49929$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:49232$3084 + cell $and $and$libresoc.v:49930$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -86886,10 +87904,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:49232$3084_Y + connect \Y $and$libresoc.v:49930$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:49234$3086 + cell $and $and$libresoc.v:49932$3120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -86897,10 +87915,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:49234$3086_Y + connect \Y $and$libresoc.v:49932$3120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:49237$3089 + cell $and $and$libresoc.v:49935$3123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86908,10 +87926,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:49237$3089_Y + connect \Y $and$libresoc.v:49935$3123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:49241$3093 + cell $and $and$libresoc.v:49939$3127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86919,10 +87937,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:49241$3093_Y + connect \Y $and$libresoc.v:49939$3127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:49243$3095 + cell $and $and$libresoc.v:49941$3129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86930,10 +87948,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:49243$3095_Y + connect \Y $and$libresoc.v:49941$3129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:49244$3096 + cell $and $and$libresoc.v:49942$3130 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -86941,10 +87959,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49244$3096_Y + connect \Y $and$libresoc.v:49942$3130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:49246$3098 + cell $and $and$libresoc.v:49944$3132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86952,10 +87970,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:49246$3098_Y + connect \Y $and$libresoc.v:49944$3132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49248$3100 + cell $and $and$libresoc.v:49946$3134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86963,10 +87981,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:49248$3100_Y + connect \Y $and$libresoc.v:49946$3134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49249$3101 + cell $and $and$libresoc.v:49947$3135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86974,10 +87992,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:49249$3101_Y + connect \Y $and$libresoc.v:49947$3135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:49250$3102 + cell $and $and$libresoc.v:49948$3136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86985,10 +88003,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:49250$3102_Y + connect \Y $and$libresoc.v:49948$3136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:49255$3107 + cell $and $and$libresoc.v:49953$3141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -86996,10 +88014,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:49255$3107_Y + connect \Y $and$libresoc.v:49953$3141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:49256$3108 + cell $and $and$libresoc.v:49954$3142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87007,10 +88025,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:49256$3108_Y + connect \Y $and$libresoc.v:49954$3142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49259$3111 + cell $and $and$libresoc.v:49957$3145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87018,10 +88036,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49259$3111_Y + connect \Y $and$libresoc.v:49957$3145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49260$3112 + cell $and $and$libresoc.v:49958$3146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87029,10 +88047,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49260$3112_Y + connect \Y $and$libresoc.v:49958$3146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:49261$3113 + cell $and $and$libresoc.v:49959$3147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87040,10 +88058,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:49261$3113_Y + connect \Y $and$libresoc.v:49959$3147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:49269$3121 + cell $and $and$libresoc.v:49967$3155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87051,10 +88069,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:49269$3121_Y + connect \Y $and$libresoc.v:49967$3155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:49270$3122 + cell $and $and$libresoc.v:49968$3156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87062,10 +88080,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:49270$3122_Y + connect \Y $and$libresoc.v:49968$3156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49271$3123 + cell $and $and$libresoc.v:49969$3157 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87073,10 +88091,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:49271$3123_Y + connect \Y $and$libresoc.v:49969$3157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:49272$3124 + cell $and $and$libresoc.v:49970$3158 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87084,10 +88102,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:49272$3124_Y + connect \Y $and$libresoc.v:49970$3158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:49245$3097 + cell $eq $eq$libresoc.v:49943$3131 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87095,10 +88113,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:49245$3097_Y + connect \Y $eq$libresoc.v:49943$3131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:49247$3099 + cell $eq $eq$libresoc.v:49945$3133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87106,66 +88124,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:49247$3099_Y + connect \Y $eq$libresoc.v:49945$3133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:49228$3080 + cell $not $not$libresoc.v:49926$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:49228$3080_Y + connect \Y $not$libresoc.v:49926$3114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:49230$3082 + cell $not $not$libresoc.v:49928$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:49230$3082_Y + connect \Y $not$libresoc.v:49928$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:49233$3085 + cell $not $not$libresoc.v:49931$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:49233$3085_Y + connect \Y $not$libresoc.v:49931$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:49236$3088 + cell $not $not$libresoc.v:49934$3122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:49236$3088_Y + connect \Y $not$libresoc.v:49934$3122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:49242$3094 + cell $not $not$libresoc.v:49940$3128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:49242$3094_Y + connect \Y $not$libresoc.v:49940$3128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:49257$3109 + cell $not $not$libresoc.v:49955$3143 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:49257$3109_Y + connect \Y $not$libresoc.v:49955$3143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:49273$3125 + cell $not $not$libresoc.v:49971$3159 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:49273$3125_Y + connect \Y $not$libresoc.v:49971$3159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:49240$3092 + cell $or $or$libresoc.v:49938$3126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87173,10 +88191,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:49240$3092_Y + connect \Y $or$libresoc.v:49938$3126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:49251$3103 + cell $or $or$libresoc.v:49949$3137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87184,10 +88202,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49251$3103_Y + connect \Y $or$libresoc.v:49949$3137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:49252$3104 + cell $or $or$libresoc.v:49950$3138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87195,10 +88213,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49252$3104_Y + connect \Y $or$libresoc.v:49950$3138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:49253$3105 + cell $or $or$libresoc.v:49951$3139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87206,10 +88224,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49253$3105_Y + connect \Y $or$libresoc.v:49951$3139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:49254$3106 + cell $or $or$libresoc.v:49952$3140 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87217,10 +88235,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49254$3106_Y + connect \Y $or$libresoc.v:49952$3140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:49258$3110 + cell $or $or$libresoc.v:49956$3144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87228,10 +88246,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:49258$3110_Y + connect \Y $or$libresoc.v:49956$3144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:49268$3120 + cell $or $or$libresoc.v:49966$3154 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87239,90 +88257,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:49268$3120_Y + connect \Y $or$libresoc.v:49966$3154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:49217$3069 + cell $reduce_and $reduce_and$libresoc.v:49915$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:49217$3069_Y + connect \Y $reduce_and$libresoc.v:49915$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:49235$3087 + cell $reduce_or $reduce_or$libresoc.v:49933$3121 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:49235$3087_Y + connect \Y $reduce_or$libresoc.v:49933$3121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49238$3090 + cell $reduce_or $reduce_or$libresoc.v:49936$3124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:49238$3090_Y + connect \Y $reduce_or$libresoc.v:49936$3124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49239$3091 + cell $reduce_or $reduce_or$libresoc.v:49937$3125 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:49239$3091_Y + connect \Y $reduce_or$libresoc.v:49937$3125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49262$3114 + cell $mux $ternary$libresoc.v:49960$3148 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:49262$3114_Y + connect \Y $ternary$libresoc.v:49960$3148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49263$3115 + cell $mux $ternary$libresoc.v:49961$3149 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:49263$3115_Y + connect \Y $ternary$libresoc.v:49961$3149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49264$3116 + cell $mux $ternary$libresoc.v:49962$3150 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:49264$3116_Y + connect \Y $ternary$libresoc.v:49962$3150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49265$3117 + cell $mux $ternary$libresoc.v:49963$3151 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:49265$3117_Y + connect \Y $ternary$libresoc.v:49963$3151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49266$3118 + cell $mux $ternary$libresoc.v:49964$3152 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:49266$3118_Y + connect \Y $ternary$libresoc.v:49964$3152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49267$3119 + cell $mux $ternary$libresoc.v:49965$3153 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:49267$3119_Y + connect \Y $ternary$libresoc.v:49965$3153_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49334.11-49356.4" + attribute \src "libresoc.v:50032.11-50054.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87347,7 +88365,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:49357.14-49363.4" + attribute \src "libresoc.v:50055.14-50061.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87356,7 +88374,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:49364.15-49370.4" + attribute \src "libresoc.v:50062.15-50068.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87365,7 +88383,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:49371.14-49377.4" + attribute \src "libresoc.v:50069.14-50075.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87374,7 +88392,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:49378.14-49384.4" + attribute \src "libresoc.v:50076.14-50082.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87383,7 +88401,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:49385.14-49391.4" + attribute \src "libresoc.v:50083.14-50089.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87392,7 +88410,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:49392.14-49397.4" + attribute \src "libresoc.v:50090.14-50095.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87400,7 +88418,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:49398.14-49404.4" + attribute \src "libresoc.v:50096.14-50102.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -87408,472 +88426,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:48681.7-48681.20" - process $proc$libresoc.v:48681$3248 + attribute \src "libresoc.v:49379.7-49379.20" + process $proc$libresoc.v:49379$3282 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:48799.7-48799.24" - process $proc$libresoc.v:48799$3249 + attribute \src "libresoc.v:49497.7-49497.24" + process $proc$libresoc.v:49497$3283 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:48828.14-48828.46" - process $proc$libresoc.v:48828$3250 + attribute \src "libresoc.v:49526.14-49526.46" + process $proc$libresoc.v:49526$3284 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] end - attribute \src "libresoc.v:48832.14-48832.41" - process $proc$libresoc.v:48832$3251 + attribute \src "libresoc.v:49530.14-49530.41" + process $proc$libresoc.v:49530$3285 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:48910.13-48910.45" - process $proc$libresoc.v:48910$3252 + attribute \src "libresoc.v:49608.13-49608.45" + process $proc$libresoc.v:49608$3286 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:48934.7-48934.26" - process $proc$libresoc.v:48934$3253 + attribute \src "libresoc.v:49632.7-49632.26" + process $proc$libresoc.v:49632$3287 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:48942.7-48942.25" - process $proc$libresoc.v:48942$3254 + attribute \src "libresoc.v:49640.7-49640.25" + process $proc$libresoc.v:49640$3288 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:48954.7-48954.27" - process $proc$libresoc.v:48954$3255 + attribute \src "libresoc.v:49652.7-49652.27" + process $proc$libresoc.v:49652$3289 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:48988.14-48988.47" - process $proc$libresoc.v:48988$3256 + attribute \src "libresoc.v:49686.14-49686.47" + process $proc$libresoc.v:49686$3290 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:48992.7-48992.27" - process $proc$libresoc.v:48992$3257 + attribute \src "libresoc.v:49690.7-49690.27" + process $proc$libresoc.v:49690$3291 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:48996.14-48996.38" - process $proc$libresoc.v:48996$3258 + attribute \src "libresoc.v:49694.14-49694.38" + process $proc$libresoc.v:49694$3292 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49000.7-49000.33" - process $proc$libresoc.v:49000$3259 + attribute \src "libresoc.v:49698.7-49698.33" + process $proc$libresoc.v:49698$3293 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49004.13-49004.33" - process $proc$libresoc.v:49004$3260 + attribute \src "libresoc.v:49702.13-49702.33" + process $proc$libresoc.v:49702$3294 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49008.7-49008.30" - process $proc$libresoc.v:49008$3261 + attribute \src "libresoc.v:49706.7-49706.30" + process $proc$libresoc.v:49706$3295 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49027.7-49027.25" - process $proc$libresoc.v:49027$3262 + attribute \src "libresoc.v:49725.7-49725.25" + process $proc$libresoc.v:49725$3296 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49031.7-49031.25" - process $proc$libresoc.v:49031$3263 + attribute \src "libresoc.v:49729.7-49729.25" + process $proc$libresoc.v:49729$3297 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49128.13-49128.30" - process $proc$libresoc.v:49128$3264 + attribute \src "libresoc.v:49826.13-49826.30" + process $proc$libresoc.v:49826$3298 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:49136.13-49136.31" - process $proc$libresoc.v:49136$3265 + attribute \src "libresoc.v:49834.13-49834.31" + process $proc$libresoc.v:49834$3299 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:49140.13-49140.31" - process $proc$libresoc.v:49140$3266 + attribute \src "libresoc.v:49838.13-49838.31" + process $proc$libresoc.v:49838$3300 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:49152.7-49152.26" - process $proc$libresoc.v:49152$3267 + attribute \src "libresoc.v:49850.7-49850.26" + process $proc$libresoc.v:49850$3301 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49156.7-49156.26" - process $proc$libresoc.v:49156$3268 + attribute \src "libresoc.v:49854.7-49854.26" + process $proc$libresoc.v:49854$3302 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49160.7-49160.25" - process $proc$libresoc.v:49160$3269 + attribute \src "libresoc.v:49858.7-49858.25" + process $proc$libresoc.v:49858$3303 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49164.7-49164.25" - process $proc$libresoc.v:49164$3270 + attribute \src "libresoc.v:49862.7-49862.25" + process $proc$libresoc.v:49862$3304 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49184.13-49184.32" - process $proc$libresoc.v:49184$3271 + attribute \src "libresoc.v:49882.13-49882.32" + process $proc$libresoc.v:49882$3305 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:49188.13-49188.32" - process $proc$libresoc.v:49188$3272 + attribute \src "libresoc.v:49886.13-49886.32" + process $proc$libresoc.v:49886$3306 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:49192.14-49192.43" - process $proc$libresoc.v:49192$3273 + attribute \src "libresoc.v:49890.14-49890.43" + process $proc$libresoc.v:49890$3307 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:49196.14-49196.43" - process $proc$libresoc.v:49196$3274 + attribute \src "libresoc.v:49894.14-49894.43" + process $proc$libresoc.v:49894$3308 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:49200.14-49200.28" - process $proc$libresoc.v:49200$3275 + attribute \src "libresoc.v:49898.14-49898.28" + process $proc$libresoc.v:49898$3309 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:49204.13-49204.26" - process $proc$libresoc.v:49204$3276 + attribute \src "libresoc.v:49902.13-49902.26" + process $proc$libresoc.v:49902$3310 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:49208.13-49208.26" - process $proc$libresoc.v:49208$3277 + attribute \src "libresoc.v:49906.13-49906.26" + process $proc$libresoc.v:49906$3311 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:49212.13-49212.26" - process $proc$libresoc.v:49212$3278 + attribute \src "libresoc.v:49910.13-49910.26" + process $proc$libresoc.v:49910$3312 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:49274.3-49275.39" - process $proc$libresoc.v:49274$3126 + attribute \src "libresoc.v:49972.3-49973.39" + process $proc$libresoc.v:49972$3160 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49276.3-49277.43" - process $proc$libresoc.v:49276$3127 + attribute \src "libresoc.v:49974.3-49975.43" + process $proc$libresoc.v:49974$3161 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49278.3-49279.29" - process $proc$libresoc.v:49278$3128 + attribute \src "libresoc.v:49976.3-49977.29" + process $proc$libresoc.v:49976$3162 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:49280.3-49281.29" - process $proc$libresoc.v:49280$3129 + attribute \src "libresoc.v:49978.3-49979.29" + process $proc$libresoc.v:49978$3163 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:49282.3-49283.29" - process $proc$libresoc.v:49282$3130 + attribute \src "libresoc.v:49980.3-49981.29" + process $proc$libresoc.v:49980$3164 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:49284.3-49285.29" - process $proc$libresoc.v:49284$3131 + attribute \src "libresoc.v:49982.3-49983.29" + process $proc$libresoc.v:49982$3165 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:49286.3-49287.29" - process $proc$libresoc.v:49286$3132 + attribute \src "libresoc.v:49984.3-49985.29" + process $proc$libresoc.v:49984$3166 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:49288.3-49289.29" - process $proc$libresoc.v:49288$3133 + attribute \src "libresoc.v:49986.3-49987.29" + process $proc$libresoc.v:49986$3167 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:49290.3-49291.43" - process $proc$libresoc.v:49290$3134 + attribute \src "libresoc.v:49988.3-49989.43" + process $proc$libresoc.v:49988$3168 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49292.3-49293.49" - process $proc$libresoc.v:49292$3135 + attribute \src "libresoc.v:49990.3-49991.49" + process $proc$libresoc.v:49990$3169 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49294.3-49295.49" - process $proc$libresoc.v:49294$3136 + attribute \src "libresoc.v:49992.3-49993.49" + process $proc$libresoc.v:49992$3170 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49296.3-49297.55" - process $proc$libresoc.v:49296$3137 + attribute \src "libresoc.v:49994.3-49995.55" + process $proc$libresoc.v:49994$3171 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49298.3-49299.37" - process $proc$libresoc.v:49298$3138 + attribute \src "libresoc.v:49996.3-49997.37" + process $proc$libresoc.v:49996$3172 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:49300.3-49301.43" - process $proc$libresoc.v:49300$3139 + attribute \src "libresoc.v:49998.3-49999.43" + process $proc$libresoc.v:49998$3173 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49302.3-49303.65" - process $proc$libresoc.v:49302$3140 + attribute \src "libresoc.v:50000.3-50001.65" + process $proc$libresoc.v:50000$3174 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:49304.3-49305.61" - process $proc$libresoc.v:49304$3141 + attribute \src "libresoc.v:50002.3-50003.61" + process $proc$libresoc.v:50002$3175 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] end - attribute \src "libresoc.v:49306.3-49307.55" - process $proc$libresoc.v:49306$3142 + attribute \src "libresoc.v:50004.3-50005.55" + process $proc$libresoc.v:50004$3176 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49308.3-49309.39" - process $proc$libresoc.v:49308$3143 + attribute \src "libresoc.v:50006.3-50007.39" + process $proc$libresoc.v:50006$3177 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:49310.3-49311.39" - process $proc$libresoc.v:49310$3144 + attribute \src "libresoc.v:50008.3-50009.39" + process $proc$libresoc.v:50008$3178 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:49312.3-49313.39" - process $proc$libresoc.v:49312$3145 + attribute \src "libresoc.v:50010.3-50011.39" + process $proc$libresoc.v:50010$3179 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:49314.3-49315.39" - process $proc$libresoc.v:49314$3146 + attribute \src "libresoc.v:50012.3-50013.39" + process $proc$libresoc.v:50012$3180 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:49316.3-49317.39" - process $proc$libresoc.v:49316$3147 + attribute \src "libresoc.v:50014.3-50015.39" + process $proc$libresoc.v:50014$3181 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49318.3-49319.39" - process $proc$libresoc.v:49318$3148 + attribute \src "libresoc.v:50016.3-50017.39" + process $proc$libresoc.v:50016$3182 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49320.3-49321.39" - process $proc$libresoc.v:49320$3149 + attribute \src "libresoc.v:50018.3-50019.39" + process $proc$libresoc.v:50018$3183 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49322.3-49323.39" - process $proc$libresoc.v:49322$3150 + attribute \src "libresoc.v:50020.3-50021.39" + process $proc$libresoc.v:50020$3184 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49324.3-49325.41" - process $proc$libresoc.v:49324$3151 + attribute \src "libresoc.v:50022.3-50023.41" + process $proc$libresoc.v:50022$3185 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49326.3-49327.41" - process $proc$libresoc.v:49326$3152 + attribute \src "libresoc.v:50024.3-50025.41" + process $proc$libresoc.v:50024$3186 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49328.3-49329.37" - process $proc$libresoc.v:49328$3153 + attribute \src "libresoc.v:50026.3-50027.37" + process $proc$libresoc.v:50026$3187 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:49330.3-49331.39" - process $proc$libresoc.v:49330$3154 + attribute \src "libresoc.v:50028.3-50029.39" + process $proc$libresoc.v:50028$3188 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:49332.3-49333.25" - process $proc$libresoc.v:49332$3155 + attribute \src "libresoc.v:50030.3-50031.25" + process $proc$libresoc.v:50030$3189 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:49405.3-49414.6" - process $proc$libresoc.v:49405$3156 + attribute \src "libresoc.v:50103.3-50112.6" + process $proc$libresoc.v:50103$3190 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:49406.5-49406.29" + attribute \src "libresoc.v:50104.5-50104.29" switch \initial - attribute \src "libresoc.v:49406.9-49406.17" + attribute \src "libresoc.v:50104.9-50104.17" case 1'1 case end @@ -87889,14 +88907,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:49415.3-49423.6" - process $proc$libresoc.v:49415$3157 + attribute \src "libresoc.v:50113.3-50121.6" + process $proc$libresoc.v:50113$3191 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3158 $1\rok_l_s_rdok$next[0:0]$3159 - attribute \src "libresoc.v:49416.5-49416.29" + assign $0\rok_l_s_rdok$next[0:0]$3192 $1\rok_l_s_rdok$next[0:0]$3193 + attribute \src "libresoc.v:50114.5-50114.29" switch \initial - attribute \src "libresoc.v:49416.9-49416.17" + attribute \src "libresoc.v:50114.9-50114.17" case 1'1 case end @@ -87905,21 +88923,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3159 1'0 + assign $1\rok_l_s_rdok$next[0:0]$3193 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$3159 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$3193 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3158 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3192 end - attribute \src "libresoc.v:49424.3-49432.6" - process $proc$libresoc.v:49424$3160 + attribute \src "libresoc.v:50122.3-50130.6" + process $proc$libresoc.v:50122$3194 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3161 $1\rok_l_r_rdok$next[0:0]$3162 - attribute \src "libresoc.v:49425.5-49425.29" + assign $0\rok_l_r_rdok$next[0:0]$3195 $1\rok_l_r_rdok$next[0:0]$3196 + attribute \src "libresoc.v:50123.5-50123.29" switch \initial - attribute \src "libresoc.v:49425.9-49425.17" + attribute \src "libresoc.v:50123.9-50123.17" case 1'1 case end @@ -87928,21 +88946,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3162 1'1 + assign $1\rok_l_r_rdok$next[0:0]$3196 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$3162 \$65 + assign $1\rok_l_r_rdok$next[0:0]$3196 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3161 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3195 end - attribute \src "libresoc.v:49433.3-49441.6" - process $proc$libresoc.v:49433$3163 + attribute \src "libresoc.v:50131.3-50139.6" + process $proc$libresoc.v:50131$3197 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3164 $1\rst_l_s_rst$next[0:0]$3165 - attribute \src "libresoc.v:49434.5-49434.29" + assign $0\rst_l_s_rst$next[0:0]$3198 $1\rst_l_s_rst$next[0:0]$3199 + attribute \src "libresoc.v:50132.5-50132.29" switch \initial - attribute \src "libresoc.v:49434.9-49434.17" + attribute \src "libresoc.v:50132.9-50132.17" case 1'1 case end @@ -87951,21 +88969,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3165 1'0 + assign $1\rst_l_s_rst$next[0:0]$3199 1'0 case - assign $1\rst_l_s_rst$next[0:0]$3165 \all_rd + assign $1\rst_l_s_rst$next[0:0]$3199 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3164 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3198 end - attribute \src "libresoc.v:49442.3-49450.6" - process $proc$libresoc.v:49442$3166 + attribute \src "libresoc.v:50140.3-50148.6" + process $proc$libresoc.v:50140$3200 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3167 $1\rst_l_r_rst$next[0:0]$3168 - attribute \src "libresoc.v:49443.5-49443.29" + assign $0\rst_l_r_rst$next[0:0]$3201 $1\rst_l_r_rst$next[0:0]$3202 + attribute \src "libresoc.v:50141.5-50141.29" switch \initial - attribute \src "libresoc.v:49443.9-49443.17" + attribute \src "libresoc.v:50141.9-50141.17" case 1'1 case end @@ -87974,21 +88992,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3168 1'1 + assign $1\rst_l_r_rst$next[0:0]$3202 1'1 case - assign $1\rst_l_r_rst$next[0:0]$3168 \rst_r + assign $1\rst_l_r_rst$next[0:0]$3202 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3167 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3201 end - attribute \src "libresoc.v:49451.3-49459.6" - process $proc$libresoc.v:49451$3169 + attribute \src "libresoc.v:50149.3-50157.6" + process $proc$libresoc.v:50149$3203 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3170 $1\opc_l_s_opc$next[0:0]$3171 - attribute \src "libresoc.v:49452.5-49452.29" + assign $0\opc_l_s_opc$next[0:0]$3204 $1\opc_l_s_opc$next[0:0]$3205 + attribute \src "libresoc.v:50150.5-50150.29" switch \initial - attribute \src "libresoc.v:49452.9-49452.17" + attribute \src "libresoc.v:50150.9-50150.17" case 1'1 case end @@ -87997,21 +89015,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3171 1'0 + assign $1\opc_l_s_opc$next[0:0]$3205 1'0 case - assign $1\opc_l_s_opc$next[0:0]$3171 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$3205 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3170 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3204 end - attribute \src "libresoc.v:49460.3-49468.6" - process $proc$libresoc.v:49460$3172 + attribute \src "libresoc.v:50158.3-50166.6" + process $proc$libresoc.v:50158$3206 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3173 $1\opc_l_r_opc$next[0:0]$3174 - attribute \src "libresoc.v:49461.5-49461.29" + assign $0\opc_l_r_opc$next[0:0]$3207 $1\opc_l_r_opc$next[0:0]$3208 + attribute \src "libresoc.v:50159.5-50159.29" switch \initial - attribute \src "libresoc.v:49461.9-49461.17" + attribute \src "libresoc.v:50159.9-50159.17" case 1'1 case end @@ -88020,21 +89038,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3174 1'1 + assign $1\opc_l_r_opc$next[0:0]$3208 1'1 case - assign $1\opc_l_r_opc$next[0:0]$3174 \req_done + assign $1\opc_l_r_opc$next[0:0]$3208 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3173 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3207 end - attribute \src "libresoc.v:49469.3-49477.6" - process $proc$libresoc.v:49469$3175 + attribute \src "libresoc.v:50167.3-50175.6" + process $proc$libresoc.v:50167$3209 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$3176 $1\src_l_s_src$next[5:0]$3177 - attribute \src "libresoc.v:49470.5-49470.29" + assign $0\src_l_s_src$next[5:0]$3210 $1\src_l_s_src$next[5:0]$3211 + attribute \src "libresoc.v:50168.5-50168.29" switch \initial - attribute \src "libresoc.v:49470.9-49470.17" + attribute \src "libresoc.v:50168.9-50168.17" case 1'1 case end @@ -88043,21 +89061,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$3177 6'000000 + assign $1\src_l_s_src$next[5:0]$3211 6'000000 case - assign $1\src_l_s_src$next[5:0]$3177 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$3211 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3176 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3210 end - attribute \src "libresoc.v:49478.3-49486.6" - process $proc$libresoc.v:49478$3178 + attribute \src "libresoc.v:50176.3-50184.6" + process $proc$libresoc.v:50176$3212 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$3179 $1\src_l_r_src$next[5:0]$3180 - attribute \src "libresoc.v:49479.5-49479.29" + assign $0\src_l_r_src$next[5:0]$3213 $1\src_l_r_src$next[5:0]$3214 + attribute \src "libresoc.v:50177.5-50177.29" switch \initial - attribute \src "libresoc.v:49479.9-49479.17" + attribute \src "libresoc.v:50177.9-50177.17" case 1'1 case end @@ -88066,21 +89084,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$3180 6'111111 + assign $1\src_l_r_src$next[5:0]$3214 6'111111 case - assign $1\src_l_r_src$next[5:0]$3180 \reset_r + assign $1\src_l_r_src$next[5:0]$3214 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3179 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3213 end - attribute \src "libresoc.v:49487.3-49495.6" - process $proc$libresoc.v:49487$3181 + attribute \src "libresoc.v:50185.3-50193.6" + process $proc$libresoc.v:50185$3215 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$3182 $1\req_l_s_req$next[2:0]$3183 - attribute \src "libresoc.v:49488.5-49488.29" + assign $0\req_l_s_req$next[2:0]$3216 $1\req_l_s_req$next[2:0]$3217 + attribute \src "libresoc.v:50186.5-50186.29" switch \initial - attribute \src "libresoc.v:49488.9-49488.17" + attribute \src "libresoc.v:50186.9-50186.17" case 1'1 case end @@ -88089,21 +89107,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$3183 3'000 + assign $1\req_l_s_req$next[2:0]$3217 3'000 case - assign $1\req_l_s_req$next[2:0]$3183 \$67 + assign $1\req_l_s_req$next[2:0]$3217 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3182 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3216 end - attribute \src "libresoc.v:49496.3-49504.6" - process $proc$libresoc.v:49496$3184 + attribute \src "libresoc.v:50194.3-50202.6" + process $proc$libresoc.v:50194$3218 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$3185 $1\req_l_r_req$next[2:0]$3186 - attribute \src "libresoc.v:49497.5-49497.29" + assign $0\req_l_r_req$next[2:0]$3219 $1\req_l_r_req$next[2:0]$3220 + attribute \src "libresoc.v:50195.5-50195.29" switch \initial - attribute \src "libresoc.v:49497.9-49497.17" + attribute \src "libresoc.v:50195.9-50195.17" case 1'1 case end @@ -88112,27 +89130,27 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$3186 3'111 + assign $1\req_l_r_req$next[2:0]$3220 3'111 case - assign $1\req_l_r_req$next[2:0]$3186 \$69 + assign $1\req_l_r_req$next[2:0]$3220 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3185 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3219 end - attribute \src "libresoc.v:49505.3-49516.6" - process $proc$libresoc.v:49505$3187 + attribute \src "libresoc.v:50203.3-50214.6" + process $proc$libresoc.v:50203$3221 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3189 $1\alu_cr0_cr_op__insn$next[31:0]$3192 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 - attribute \src "libresoc.v:49506.5-49506.29" + assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3223 $1\alu_cr0_cr_op__insn$next[31:0]$3226 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 + attribute \src "libresoc.v:50204.5-50204.29" switch \initial - attribute \src "libresoc.v:49506.9-49506.17" + attribute \src "libresoc.v:50204.9-50204.17" case 1'1 case end @@ -88143,31 +89161,31 @@ module \cr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3192 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3226 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } case - assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3191 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3192 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3193 \alu_cr0_cr_op__insn_type + assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3226 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 \alu_cr0_cr_op__insn_type end sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3188 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3189 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3190 + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3223 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 end - attribute \src "libresoc.v:49517.3-49538.6" - process $proc$libresoc.v:49517$3194 + attribute \src "libresoc.v:50215.3-50236.6" + process $proc$libresoc.v:50215$3228 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$3195 $2\data_r0__o$next[63:0]$3199 + assign $0\data_r0__o$next[63:0]$3229 $2\data_r0__o$next[63:0]$3233 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3196 $3\data_r0__o_ok$next[0:0]$3201 - attribute \src "libresoc.v:49518.5-49518.29" + assign $0\data_r0__o_ok$next[0:0]$3230 $3\data_r0__o_ok$next[0:0]$3235 + attribute \src "libresoc.v:50216.5-50216.29" switch \initial - attribute \src "libresoc.v:49518.9-49518.17" + attribute \src "libresoc.v:50216.9-50216.17" case 1'1 case end @@ -88177,10 +89195,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3198 $1\data_r0__o$next[63:0]$3197 } { \o_ok \alu_cr0_o } + assign { $1\data_r0__o_ok$next[0:0]$3232 $1\data_r0__o$next[63:0]$3231 } { \o_ok \alu_cr0_o } case - assign $1\data_r0__o$next[63:0]$3197 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3198 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$3231 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3232 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -88188,38 +89206,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3200 $2\data_r0__o$next[63:0]$3199 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$3234 $2\data_r0__o$next[63:0]$3233 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$3199 $1\data_r0__o$next[63:0]$3197 - assign $2\data_r0__o_ok$next[0:0]$3200 $1\data_r0__o_ok$next[0:0]$3198 + assign $2\data_r0__o$next[63:0]$3233 $1\data_r0__o$next[63:0]$3231 + assign $2\data_r0__o_ok$next[0:0]$3234 $1\data_r0__o_ok$next[0:0]$3232 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3201 1'0 + assign $3\data_r0__o_ok$next[0:0]$3235 1'0 case - assign $3\data_r0__o_ok$next[0:0]$3201 $2\data_r0__o_ok$next[0:0]$3200 + assign $3\data_r0__o_ok$next[0:0]$3235 $2\data_r0__o_ok$next[0:0]$3234 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3195 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3196 + update \data_r0__o$next $0\data_r0__o$next[63:0]$3229 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3230 end - attribute \src "libresoc.v:49539.3-49560.6" - process $proc$libresoc.v:49539$3202 + attribute \src "libresoc.v:50237.3-50258.6" + process $proc$libresoc.v:50237$3236 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3203 $2\data_r1__full_cr$next[31:0]$3207 + assign $0\data_r1__full_cr$next[31:0]$3237 $2\data_r1__full_cr$next[31:0]$3241 assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3204 $3\data_r1__full_cr_ok$next[0:0]$3209 - attribute \src "libresoc.v:49540.5-49540.29" + assign $0\data_r1__full_cr_ok$next[0:0]$3238 $3\data_r1__full_cr_ok$next[0:0]$3243 + attribute \src "libresoc.v:50238.5-50238.29" switch \initial - attribute \src "libresoc.v:49540.9-49540.17" + attribute \src "libresoc.v:50238.9-50238.17" case 1'1 case end @@ -88229,10 +89247,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3206 $1\data_r1__full_cr$next[31:0]$3205 } { \full_cr_ok \alu_cr0_full_cr } + assign { $1\data_r1__full_cr_ok$next[0:0]$3240 $1\data_r1__full_cr$next[31:0]$3239 } { \full_cr_ok \alu_cr0_full_cr } case - assign $1\data_r1__full_cr$next[31:0]$3205 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3206 \data_r1__full_cr_ok + assign $1\data_r1__full_cr$next[31:0]$3239 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3240 \data_r1__full_cr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -88240,38 +89258,38 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3208 $2\data_r1__full_cr$next[31:0]$3207 } 33'000000000000000000000000000000000 + assign { $2\data_r1__full_cr_ok$next[0:0]$3242 $2\data_r1__full_cr$next[31:0]$3241 } 33'000000000000000000000000000000000 case - assign $2\data_r1__full_cr$next[31:0]$3207 $1\data_r1__full_cr$next[31:0]$3205 - assign $2\data_r1__full_cr_ok$next[0:0]$3208 $1\data_r1__full_cr_ok$next[0:0]$3206 + assign $2\data_r1__full_cr$next[31:0]$3241 $1\data_r1__full_cr$next[31:0]$3239 + assign $2\data_r1__full_cr_ok$next[0:0]$3242 $1\data_r1__full_cr_ok$next[0:0]$3240 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3209 1'0 + assign $3\data_r1__full_cr_ok$next[0:0]$3243 1'0 case - assign $3\data_r1__full_cr_ok$next[0:0]$3209 $2\data_r1__full_cr_ok$next[0:0]$3208 + assign $3\data_r1__full_cr_ok$next[0:0]$3243 $2\data_r1__full_cr_ok$next[0:0]$3242 end sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3203 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3204 + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3237 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3238 end - attribute \src "libresoc.v:49561.3-49582.6" - process $proc$libresoc.v:49561$3210 + attribute \src "libresoc.v:50259.3-50280.6" + process $proc$libresoc.v:50259$3244 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3211 $2\data_r2__cr_a$next[3:0]$3215 + assign $0\data_r2__cr_a$next[3:0]$3245 $2\data_r2__cr_a$next[3:0]$3249 assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3212 $3\data_r2__cr_a_ok$next[0:0]$3217 - attribute \src "libresoc.v:49562.5-49562.29" + assign $0\data_r2__cr_a_ok$next[0:0]$3246 $3\data_r2__cr_a_ok$next[0:0]$3251 + attribute \src "libresoc.v:50260.5-50260.29" switch \initial - attribute \src "libresoc.v:49562.9-49562.17" + attribute \src "libresoc.v:50260.9-50260.17" case 1'1 case end @@ -88281,10 +89299,10 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3214 $1\data_r2__cr_a$next[3:0]$3213 } { \cr_a_ok \alu_cr0_cr_a } + assign { $1\data_r2__cr_a_ok$next[0:0]$3248 $1\data_r2__cr_a$next[3:0]$3247 } { \cr_a_ok \alu_cr0_cr_a } case - assign $1\data_r2__cr_a$next[3:0]$3213 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3214 \data_r2__cr_a_ok + assign $1\data_r2__cr_a$next[3:0]$3247 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3248 \data_r2__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -88292,32 +89310,32 @@ module \cr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3216 $2\data_r2__cr_a$next[3:0]$3215 } 5'00000 + assign { $2\data_r2__cr_a_ok$next[0:0]$3250 $2\data_r2__cr_a$next[3:0]$3249 } 5'00000 case - assign $2\data_r2__cr_a$next[3:0]$3215 $1\data_r2__cr_a$next[3:0]$3213 - assign $2\data_r2__cr_a_ok$next[0:0]$3216 $1\data_r2__cr_a_ok$next[0:0]$3214 + assign $2\data_r2__cr_a$next[3:0]$3249 $1\data_r2__cr_a$next[3:0]$3247 + assign $2\data_r2__cr_a_ok$next[0:0]$3250 $1\data_r2__cr_a_ok$next[0:0]$3248 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3217 1'0 + assign $3\data_r2__cr_a_ok$next[0:0]$3251 1'0 case - assign $3\data_r2__cr_a_ok$next[0:0]$3217 $2\data_r2__cr_a_ok$next[0:0]$3216 + assign $3\data_r2__cr_a_ok$next[0:0]$3251 $2\data_r2__cr_a_ok$next[0:0]$3250 end sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3211 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3212 + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3245 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3246 end - attribute \src "libresoc.v:49583.3-49592.6" - process $proc$libresoc.v:49583$3218 + attribute \src "libresoc.v:50281.3-50290.6" + process $proc$libresoc.v:50281$3252 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$3219 $1\src_r0$next[63:0]$3220 - attribute \src "libresoc.v:49584.5-49584.29" + assign $0\src_r0$next[63:0]$3253 $1\src_r0$next[63:0]$3254 + attribute \src "libresoc.v:50282.5-50282.29" switch \initial - attribute \src "libresoc.v:49584.9-49584.17" + attribute \src "libresoc.v:50282.9-50282.17" case 1'1 case end @@ -88326,21 +89344,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$3220 \src1_i + assign $1\src_r0$next[63:0]$3254 \src1_i case - assign $1\src_r0$next[63:0]$3220 \src_r0 + assign $1\src_r0$next[63:0]$3254 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$3219 + update \src_r0$next $0\src_r0$next[63:0]$3253 end - attribute \src "libresoc.v:49593.3-49602.6" - process $proc$libresoc.v:49593$3221 + attribute \src "libresoc.v:50291.3-50300.6" + process $proc$libresoc.v:50291$3255 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$3222 $1\src_r1$next[63:0]$3223 - attribute \src "libresoc.v:49594.5-49594.29" + assign $0\src_r1$next[63:0]$3256 $1\src_r1$next[63:0]$3257 + attribute \src "libresoc.v:50292.5-50292.29" switch \initial - attribute \src "libresoc.v:49594.9-49594.17" + attribute \src "libresoc.v:50292.9-50292.17" case 1'1 case end @@ -88349,21 +89367,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$3223 \src2_i + assign $1\src_r1$next[63:0]$3257 \src2_i case - assign $1\src_r1$next[63:0]$3223 \src_r1 + assign $1\src_r1$next[63:0]$3257 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$3222 + update \src_r1$next $0\src_r1$next[63:0]$3256 end - attribute \src "libresoc.v:49603.3-49612.6" - process $proc$libresoc.v:49603$3224 + attribute \src "libresoc.v:50301.3-50310.6" + process $proc$libresoc.v:50301$3258 assign { } { } assign { } { } - assign $0\src_r2$next[31:0]$3225 $1\src_r2$next[31:0]$3226 - attribute \src "libresoc.v:49604.5-49604.29" + assign $0\src_r2$next[31:0]$3259 $1\src_r2$next[31:0]$3260 + attribute \src "libresoc.v:50302.5-50302.29" switch \initial - attribute \src "libresoc.v:49604.9-49604.17" + attribute \src "libresoc.v:50302.9-50302.17" case 1'1 case end @@ -88372,21 +89390,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[31:0]$3226 \src3_i + assign $1\src_r2$next[31:0]$3260 \src3_i case - assign $1\src_r2$next[31:0]$3226 \src_r2 + assign $1\src_r2$next[31:0]$3260 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[31:0]$3225 + update \src_r2$next $0\src_r2$next[31:0]$3259 end - attribute \src "libresoc.v:49613.3-49622.6" - process $proc$libresoc.v:49613$3227 + attribute \src "libresoc.v:50311.3-50320.6" + process $proc$libresoc.v:50311$3261 assign { } { } assign { } { } - assign $0\src_r3$next[3:0]$3228 $1\src_r3$next[3:0]$3229 - attribute \src "libresoc.v:49614.5-49614.29" + assign $0\src_r3$next[3:0]$3262 $1\src_r3$next[3:0]$3263 + attribute \src "libresoc.v:50312.5-50312.29" switch \initial - attribute \src "libresoc.v:49614.9-49614.17" + attribute \src "libresoc.v:50312.9-50312.17" case 1'1 case end @@ -88395,21 +89413,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[3:0]$3229 \src4_i + assign $1\src_r3$next[3:0]$3263 \src4_i case - assign $1\src_r3$next[3:0]$3229 \src_r3 + assign $1\src_r3$next[3:0]$3263 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[3:0]$3228 + update \src_r3$next $0\src_r3$next[3:0]$3262 end - attribute \src "libresoc.v:49623.3-49632.6" - process $proc$libresoc.v:49623$3230 + attribute \src "libresoc.v:50321.3-50330.6" + process $proc$libresoc.v:50321$3264 assign { } { } assign { } { } - assign $0\src_r4$next[3:0]$3231 $1\src_r4$next[3:0]$3232 - attribute \src "libresoc.v:49624.5-49624.29" + assign $0\src_r4$next[3:0]$3265 $1\src_r4$next[3:0]$3266 + attribute \src "libresoc.v:50322.5-50322.29" switch \initial - attribute \src "libresoc.v:49624.9-49624.17" + attribute \src "libresoc.v:50322.9-50322.17" case 1'1 case end @@ -88418,21 +89436,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[3:0]$3232 \src5_i + assign $1\src_r4$next[3:0]$3266 \src5_i case - assign $1\src_r4$next[3:0]$3232 \src_r4 + assign $1\src_r4$next[3:0]$3266 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[3:0]$3231 + update \src_r4$next $0\src_r4$next[3:0]$3265 end - attribute \src "libresoc.v:49633.3-49642.6" - process $proc$libresoc.v:49633$3233 + attribute \src "libresoc.v:50331.3-50340.6" + process $proc$libresoc.v:50331$3267 assign { } { } assign { } { } - assign $0\src_r5$next[3:0]$3234 $1\src_r5$next[3:0]$3235 - attribute \src "libresoc.v:49634.5-49634.29" + assign $0\src_r5$next[3:0]$3268 $1\src_r5$next[3:0]$3269 + attribute \src "libresoc.v:50332.5-50332.29" switch \initial - attribute \src "libresoc.v:49634.9-49634.17" + attribute \src "libresoc.v:50332.9-50332.17" case 1'1 case end @@ -88441,21 +89459,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[3:0]$3235 \src6_i + assign $1\src_r5$next[3:0]$3269 \src6_i case - assign $1\src_r5$next[3:0]$3235 \src_r5 + assign $1\src_r5$next[3:0]$3269 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[3:0]$3234 + update \src_r5$next $0\src_r5$next[3:0]$3268 end - attribute \src "libresoc.v:49643.3-49651.6" - process $proc$libresoc.v:49643$3236 + attribute \src "libresoc.v:50341.3-50349.6" + process $proc$libresoc.v:50341$3270 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3237 $1\alui_l_r_alui$next[0:0]$3238 - attribute \src "libresoc.v:49644.5-49644.29" + assign $0\alui_l_r_alui$next[0:0]$3271 $1\alui_l_r_alui$next[0:0]$3272 + attribute \src "libresoc.v:50342.5-50342.29" switch \initial - attribute \src "libresoc.v:49644.9-49644.17" + attribute \src "libresoc.v:50342.9-50342.17" case 1'1 case end @@ -88464,21 +89482,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3238 1'1 + assign $1\alui_l_r_alui$next[0:0]$3272 1'1 case - assign $1\alui_l_r_alui$next[0:0]$3238 \$89 + assign $1\alui_l_r_alui$next[0:0]$3272 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3237 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3271 end - attribute \src "libresoc.v:49652.3-49660.6" - process $proc$libresoc.v:49652$3239 + attribute \src "libresoc.v:50350.3-50358.6" + process $proc$libresoc.v:50350$3273 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3240 $1\alu_l_r_alu$next[0:0]$3241 - attribute \src "libresoc.v:49653.5-49653.29" + assign $0\alu_l_r_alu$next[0:0]$3274 $1\alu_l_r_alu$next[0:0]$3275 + attribute \src "libresoc.v:50351.5-50351.29" switch \initial - attribute \src "libresoc.v:49653.9-49653.17" + attribute \src "libresoc.v:50351.9-50351.17" case 1'1 case end @@ -88487,21 +89505,21 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3241 1'1 + assign $1\alu_l_r_alu$next[0:0]$3275 1'1 case - assign $1\alu_l_r_alu$next[0:0]$3241 \$91 + assign $1\alu_l_r_alu$next[0:0]$3275 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3240 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3274 end - attribute \src "libresoc.v:49661.3-49670.6" - process $proc$libresoc.v:49661$3242 + attribute \src "libresoc.v:50359.3-50368.6" + process $proc$libresoc.v:50359$3276 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:49662.5-49662.29" + attribute \src "libresoc.v:50360.5-50360.29" switch \initial - attribute \src "libresoc.v:49662.9-49662.17" + attribute \src "libresoc.v:50360.9-50360.17" case 1'1 case end @@ -88517,14 +89535,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:49671.3-49680.6" - process $proc$libresoc.v:49671$3243 + attribute \src "libresoc.v:50369.3-50378.6" + process $proc$libresoc.v:50369$3277 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:49672.5-49672.29" + attribute \src "libresoc.v:50370.5-50370.29" switch \initial - attribute \src "libresoc.v:49672.9-49672.17" + attribute \src "libresoc.v:50370.9-50370.17" case 1'1 case end @@ -88540,14 +89558,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:49681.3-49690.6" - process $proc$libresoc.v:49681$3244 + attribute \src "libresoc.v:50379.3-50388.6" + process $proc$libresoc.v:50379$3278 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:49682.5-49682.29" + attribute \src "libresoc.v:50380.5-50380.29" switch \initial - attribute \src "libresoc.v:49682.9-49682.17" + attribute \src "libresoc.v:50380.9-50380.17" case 1'1 case end @@ -88563,14 +89581,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:49691.3-49699.6" - process $proc$libresoc.v:49691$3245 + attribute \src "libresoc.v:50389.3-50397.6" + process $proc$libresoc.v:50389$3279 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$3246 $1\prev_wr_go$next[2:0]$3247 - attribute \src "libresoc.v:49692.5-49692.29" + assign $0\prev_wr_go$next[2:0]$3280 $1\prev_wr_go$next[2:0]$3281 + attribute \src "libresoc.v:50390.5-50390.29" switch \initial - attribute \src "libresoc.v:49692.9-49692.17" + attribute \src "libresoc.v:50390.9-50390.17" case 1'1 case end @@ -88579,70 +89597,70 @@ module \cr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$3247 3'000 - case - assign $1\prev_wr_go$next[2:0]$3247 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3246 - end - connect \$5 $reduce_and$libresoc.v:49217$3069_Y - connect \$99 $and$libresoc.v:49218$3070_Y - connect \$101 $and$libresoc.v:49219$3071_Y - connect \$103 $and$libresoc.v:49220$3072_Y - connect \$105 $and$libresoc.v:49221$3073_Y - connect \$107 $and$libresoc.v:49222$3074_Y - connect \$109 $and$libresoc.v:49223$3075_Y - connect \$111 $and$libresoc.v:49224$3076_Y - connect \$113 $and$libresoc.v:49225$3077_Y - connect \$115 $and$libresoc.v:49226$3078_Y - connect \$11 $and$libresoc.v:49227$3079_Y - connect \$13 $not$libresoc.v:49228$3080_Y - connect \$15 $and$libresoc.v:49229$3081_Y - connect \$17 $not$libresoc.v:49230$3082_Y - connect \$19 $and$libresoc.v:49231$3083_Y - connect \$21 $and$libresoc.v:49232$3084_Y - connect \$25 $not$libresoc.v:49233$3085_Y - connect \$27 $and$libresoc.v:49234$3086_Y - connect \$24 $reduce_or$libresoc.v:49235$3087_Y - connect \$23 $not$libresoc.v:49236$3088_Y - connect \$31 $and$libresoc.v:49237$3089_Y - connect \$33 $reduce_or$libresoc.v:49238$3090_Y - connect \$35 $reduce_or$libresoc.v:49239$3091_Y - connect \$37 $or$libresoc.v:49240$3092_Y - connect \$3 $and$libresoc.v:49241$3093_Y - connect \$39 $not$libresoc.v:49242$3094_Y - connect \$41 $and$libresoc.v:49243$3095_Y - connect \$43 $and$libresoc.v:49244$3096_Y - connect \$45 $eq$libresoc.v:49245$3097_Y - connect \$47 $and$libresoc.v:49246$3098_Y - connect \$49 $eq$libresoc.v:49247$3099_Y - connect \$51 $and$libresoc.v:49248$3100_Y - connect \$53 $and$libresoc.v:49249$3101_Y - connect \$55 $and$libresoc.v:49250$3102_Y - connect \$57 $or$libresoc.v:49251$3103_Y - connect \$59 $or$libresoc.v:49252$3104_Y - connect \$61 $or$libresoc.v:49253$3105_Y - connect \$63 $or$libresoc.v:49254$3106_Y - connect \$65 $and$libresoc.v:49255$3107_Y - connect \$67 $and$libresoc.v:49256$3108_Y - connect \$6 $not$libresoc.v:49257$3109_Y - connect \$69 $or$libresoc.v:49258$3110_Y - connect \$71 $and$libresoc.v:49259$3111_Y - connect \$73 $and$libresoc.v:49260$3112_Y - connect \$75 $and$libresoc.v:49261$3113_Y - connect \$77 $ternary$libresoc.v:49262$3114_Y - connect \$79 $ternary$libresoc.v:49263$3115_Y - connect \$81 $ternary$libresoc.v:49264$3116_Y - connect \$83 $ternary$libresoc.v:49265$3117_Y - connect \$85 $ternary$libresoc.v:49266$3118_Y - connect \$87 $ternary$libresoc.v:49267$3119_Y - connect \$8 $or$libresoc.v:49268$3120_Y - connect \$89 $and$libresoc.v:49269$3121_Y - connect \$91 $and$libresoc.v:49270$3122_Y - connect \$93 $and$libresoc.v:49271$3123_Y - connect \$95 $and$libresoc.v:49272$3124_Y - connect \$97 $not$libresoc.v:49273$3125_Y + assign $1\prev_wr_go$next[2:0]$3281 3'000 + case + assign $1\prev_wr_go$next[2:0]$3281 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3280 + end + connect \$5 $reduce_and$libresoc.v:49915$3103_Y + connect \$99 $and$libresoc.v:49916$3104_Y + connect \$101 $and$libresoc.v:49917$3105_Y + connect \$103 $and$libresoc.v:49918$3106_Y + connect \$105 $and$libresoc.v:49919$3107_Y + connect \$107 $and$libresoc.v:49920$3108_Y + connect \$109 $and$libresoc.v:49921$3109_Y + connect \$111 $and$libresoc.v:49922$3110_Y + connect \$113 $and$libresoc.v:49923$3111_Y + connect \$115 $and$libresoc.v:49924$3112_Y + connect \$11 $and$libresoc.v:49925$3113_Y + connect \$13 $not$libresoc.v:49926$3114_Y + connect \$15 $and$libresoc.v:49927$3115_Y + connect \$17 $not$libresoc.v:49928$3116_Y + connect \$19 $and$libresoc.v:49929$3117_Y + connect \$21 $and$libresoc.v:49930$3118_Y + connect \$25 $not$libresoc.v:49931$3119_Y + connect \$27 $and$libresoc.v:49932$3120_Y + connect \$24 $reduce_or$libresoc.v:49933$3121_Y + connect \$23 $not$libresoc.v:49934$3122_Y + connect \$31 $and$libresoc.v:49935$3123_Y + connect \$33 $reduce_or$libresoc.v:49936$3124_Y + connect \$35 $reduce_or$libresoc.v:49937$3125_Y + connect \$37 $or$libresoc.v:49938$3126_Y + connect \$3 $and$libresoc.v:49939$3127_Y + connect \$39 $not$libresoc.v:49940$3128_Y + connect \$41 $and$libresoc.v:49941$3129_Y + connect \$43 $and$libresoc.v:49942$3130_Y + connect \$45 $eq$libresoc.v:49943$3131_Y + connect \$47 $and$libresoc.v:49944$3132_Y + connect \$49 $eq$libresoc.v:49945$3133_Y + connect \$51 $and$libresoc.v:49946$3134_Y + connect \$53 $and$libresoc.v:49947$3135_Y + connect \$55 $and$libresoc.v:49948$3136_Y + connect \$57 $or$libresoc.v:49949$3137_Y + connect \$59 $or$libresoc.v:49950$3138_Y + connect \$61 $or$libresoc.v:49951$3139_Y + connect \$63 $or$libresoc.v:49952$3140_Y + connect \$65 $and$libresoc.v:49953$3141_Y + connect \$67 $and$libresoc.v:49954$3142_Y + connect \$6 $not$libresoc.v:49955$3143_Y + connect \$69 $or$libresoc.v:49956$3144_Y + connect \$71 $and$libresoc.v:49957$3145_Y + connect \$73 $and$libresoc.v:49958$3146_Y + connect \$75 $and$libresoc.v:49959$3147_Y + connect \$77 $ternary$libresoc.v:49960$3148_Y + connect \$79 $ternary$libresoc.v:49961$3149_Y + connect \$81 $ternary$libresoc.v:49962$3150_Y + connect \$83 $ternary$libresoc.v:49963$3151_Y + connect \$85 $ternary$libresoc.v:49964$3152_Y + connect \$87 $ternary$libresoc.v:49965$3153_Y + connect \$8 $or$libresoc.v:49966$3154_Y + connect \$89 $and$libresoc.v:49967$3155_Y + connect \$91 $and$libresoc.v:49968$3156_Y + connect \$93 $and$libresoc.v:49969$3157_Y + connect \$95 $and$libresoc.v:49970$3158_Y + connect \$97 $not$libresoc.v:49971$3159_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -88675,31 +89693,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:49735.1-49784.10" +attribute \src "libresoc.v:50433.1-50482.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:49736.7-49736.20" + attribute \src "libresoc.v:50434.7-50434.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49772.3-49780.6" - wire $0\q_int$next[0:0]$3286 - attribute \src "libresoc.v:49770.3-49771.27" + attribute \src "libresoc.v:50470.3-50478.6" + wire $0\q_int$next[0:0]$3320 + attribute \src "libresoc.v:50468.3-50469.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:49772.3-49780.6" - wire $1\q_int$next[0:0]$3287 - attribute \src "libresoc.v:49754.7-49754.19" + attribute \src "libresoc.v:50470.3-50478.6" + wire $1\q_int$next[0:0]$3321 + attribute \src "libresoc.v:50452.7-50452.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:49767.17-49767.96" - wire $and$libresoc.v:49767$3281_Y - attribute \src "libresoc.v:49766.17-49766.92" - wire $not$libresoc.v:49766$3280_Y - attribute \src "libresoc.v:49769.17-49769.92" - wire $not$libresoc.v:49769$3283_Y - attribute \src "libresoc.v:49765.17-49765.98" - wire $or$libresoc.v:49765$3279_Y - attribute \src "libresoc.v:49768.17-49768.97" - wire $or$libresoc.v:49768$3282_Y + attribute \src "libresoc.v:50465.17-50465.96" + wire $and$libresoc.v:50465$3315_Y + attribute \src "libresoc.v:50464.17-50464.92" + wire $not$libresoc.v:50464$3314_Y + attribute \src "libresoc.v:50467.17-50467.92" + wire $not$libresoc.v:50467$3317_Y + attribute \src "libresoc.v:50463.17-50463.98" + wire $or$libresoc.v:50463$3313_Y + attribute \src "libresoc.v:50466.17-50466.97" + wire $or$libresoc.v:50466$3316_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" @@ -88710,11 +89728,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:49736.7-49736.15" + attribute \src "libresoc.v:50434.7-50434.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 4 \q_cyc @@ -88731,7 +89749,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:49767$3281 + cell $and $and$libresoc.v:50465$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88739,26 +89757,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:49767$3281_Y + connect \Y $and$libresoc.v:50465$3315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:49766$3280 + cell $not $not$libresoc.v:50464$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:49766$3280_Y + connect \Y $not$libresoc.v:50464$3314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:49769$3283 + cell $not $not$libresoc.v:50467$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:49769$3283_Y + connect \Y $not$libresoc.v:50467$3317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:49765$3279 + cell $or $or$libresoc.v:50463$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88766,10 +89784,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:49765$3279_Y + connect \Y $or$libresoc.v:50463$3313_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:49768$3282 + cell $or $or$libresoc.v:50466$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88777,39 +89795,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:49768$3282_Y + connect \Y $or$libresoc.v:50466$3316_Y end - attribute \src "libresoc.v:49736.7-49736.20" - process $proc$libresoc.v:49736$3288 + attribute \src "libresoc.v:50434.7-50434.20" + process $proc$libresoc.v:50434$3322 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49754.7-49754.19" - process $proc$libresoc.v:49754$3289 + attribute \src "libresoc.v:50452.7-50452.19" + process $proc$libresoc.v:50452$3323 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:49770.3-49771.27" - process $proc$libresoc.v:49770$3284 + attribute \src "libresoc.v:50468.3-50469.27" + process $proc$libresoc.v:50468$3318 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:49772.3-49780.6" - process $proc$libresoc.v:49772$3285 + attribute \src "libresoc.v:50470.3-50478.6" + process $proc$libresoc.v:50470$3319 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$3286 $1\q_int$next[0:0]$3287 - attribute \src "libresoc.v:49773.5-49773.29" + assign $0\q_int$next[0:0]$3320 $1\q_int$next[0:0]$3321 + attribute \src "libresoc.v:50471.5-50471.29" switch \initial - attribute \src "libresoc.v:49773.9-49773.17" + attribute \src "libresoc.v:50471.9-50471.17" case 1'1 case end @@ -88818,329 +89836,329 @@ module \cyc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$3287 1'0 + assign $1\q_int$next[0:0]$3321 1'0 case - assign $1\q_int$next[0:0]$3287 \$5 + assign $1\q_int$next[0:0]$3321 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$3286 + update \q_int$next $0\q_int$next[0:0]$3320 end - connect \$9 $or$libresoc.v:49765$3279_Y - connect \$1 $not$libresoc.v:49766$3280_Y - connect \$3 $and$libresoc.v:49767$3281_Y - connect \$5 $or$libresoc.v:49768$3282_Y - connect \$7 $not$libresoc.v:49769$3283_Y + connect \$9 $or$libresoc.v:50463$3313_Y + connect \$1 $not$libresoc.v:50464$3314_Y + connect \$3 $and$libresoc.v:50465$3315_Y + connect \$5 $or$libresoc.v:50466$3316_Y + connect \$7 $not$libresoc.v:50467$3317_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:49788.1-50502.10" +attribute \src "libresoc.v:50486.1-51200.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dbg" +attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:50318.3-50327.6" + attribute \src "libresoc.v:51016.3-51025.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:50125.3-50134.6" + attribute \src "libresoc.v:50823.3-50832.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:50328.3-50337.6" + attribute \src "libresoc.v:51026.3-51035.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:50107.3-50124.6" + attribute \src "libresoc.v:50805.3-50822.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:50338.3-50368.6" + attribute \src "libresoc.v:51036.3-51066.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:50309.3-50317.6" - wire $0\dmi_read_log_data$next[0:0]$3403 - attribute \src "libresoc.v:50085.3-50086.51" + attribute \src "libresoc.v:51007.3-51015.6" + wire $0\dmi_read_log_data$next[0:0]$3437 + attribute \src "libresoc.v:50783.3-50784.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50300.3-50308.6" - wire $0\dmi_read_log_data_1$next[0:0]$3400 - attribute \src "libresoc.v:50087.3-50088.55" + attribute \src "libresoc.v:50998.3-51006.6" + wire $0\dmi_read_log_data_1$next[0:0]$3434 + attribute \src "libresoc.v:50785.3-50786.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50135.3-50143.6" - wire $0\dmi_req_i_1$next[0:0]$3366 - attribute \src "libresoc.v:50097.3-50098.39" + attribute \src "libresoc.v:50833.3-50841.6" + wire $0\dmi_req_i_1$next[0:0]$3400 + attribute \src "libresoc.v:50795.3-50796.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:50459.3-50492.6" - wire $0\do_dmi_log_rd$next[0:0]$3430 - attribute \src "libresoc.v:50099.3-50100.43" + attribute \src "libresoc.v:51157.3-51190.6" + wire $0\do_dmi_log_rd$next[0:0]$3464 + attribute \src "libresoc.v:50797.3-50798.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:50429.3-50458.6" - wire $0\do_icreset$next[0:0]$3423 - attribute \src "libresoc.v:50101.3-50102.37" + attribute \src "libresoc.v:51127.3-51156.6" + wire $0\do_icreset$next[0:0]$3457 + attribute \src "libresoc.v:50799.3-50800.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:50399.3-50428.6" - wire $0\do_reset$next[0:0]$3416 - attribute \src "libresoc.v:50103.3-50104.33" + attribute \src "libresoc.v:51097.3-51126.6" + wire $0\do_reset$next[0:0]$3450 + attribute \src "libresoc.v:50801.3-50802.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:50369.3-50398.6" - wire $0\do_step$next[0:0]$3409 - attribute \src "libresoc.v:50105.3-50106.31" + attribute \src "libresoc.v:51067.3-51096.6" + wire $0\do_step$next[0:0]$3443 + attribute \src "libresoc.v:50803.3-50804.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:50238.3-50265.6" - wire width 7 $0\gspr_index$next[6:0]$3388 - attribute \src "libresoc.v:50091.3-50092.37" + attribute \src "libresoc.v:50936.3-50963.6" + wire width 7 $0\gspr_index$next[6:0]$3422 + attribute \src "libresoc.v:50789.3-50790.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:49789.7-49789.20" + attribute \src "libresoc.v:50487.7-50487.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50266.3-50299.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3394 - attribute \src "libresoc.v:50089.3-50090.41" + attribute \src "libresoc.v:50964.3-50997.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3428 + attribute \src "libresoc.v:50787.3-50788.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:50194.3-50237.6" - wire $0\stopping$next[0:0]$3379 - attribute \src "libresoc.v:50093.3-50094.33" + attribute \src "libresoc.v:50892.3-50935.6" + wire $0\stopping$next[0:0]$3413 + attribute \src "libresoc.v:50791.3-50792.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:50144.3-50193.6" - wire $0\terminated$next[0:0]$3369 - attribute \src "libresoc.v:50095.3-50096.37" + attribute \src "libresoc.v:50842.3-50891.6" + wire $0\terminated$next[0:0]$3403 + attribute \src "libresoc.v:50793.3-50794.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:50318.3-50327.6" + attribute \src "libresoc.v:51016.3-51025.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:50125.3-50134.6" + attribute \src "libresoc.v:50823.3-50832.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50328.3-50337.6" + attribute \src "libresoc.v:51026.3-51035.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:50107.3-50124.6" + attribute \src "libresoc.v:50805.3-50822.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50338.3-50368.6" + attribute \src "libresoc.v:51036.3-51066.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:50309.3-50317.6" - wire $1\dmi_read_log_data$next[0:0]$3404 - attribute \src "libresoc.v:49962.7-49962.31" + attribute \src "libresoc.v:51007.3-51015.6" + wire $1\dmi_read_log_data$next[0:0]$3438 + attribute \src "libresoc.v:50660.7-50660.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50300.3-50308.6" - wire $1\dmi_read_log_data_1$next[0:0]$3401 - attribute \src "libresoc.v:49966.7-49966.33" + attribute \src "libresoc.v:50998.3-51006.6" + wire $1\dmi_read_log_data_1$next[0:0]$3435 + attribute \src "libresoc.v:50664.7-50664.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50135.3-50143.6" - wire $1\dmi_req_i_1$next[0:0]$3367 - attribute \src "libresoc.v:49972.7-49972.25" + attribute \src "libresoc.v:50833.3-50841.6" + wire $1\dmi_req_i_1$next[0:0]$3401 + attribute \src "libresoc.v:50670.7-50670.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:50459.3-50492.6" - wire $1\do_dmi_log_rd$next[0:0]$3431 - attribute \src "libresoc.v:49978.7-49978.27" + attribute \src "libresoc.v:51157.3-51190.6" + wire $1\do_dmi_log_rd$next[0:0]$3465 + attribute \src "libresoc.v:50676.7-50676.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:50429.3-50458.6" - wire $1\do_icreset$next[0:0]$3424 - attribute \src "libresoc.v:49982.7-49982.24" + attribute \src "libresoc.v:51127.3-51156.6" + wire $1\do_icreset$next[0:0]$3458 + attribute \src "libresoc.v:50680.7-50680.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:50399.3-50428.6" - wire $1\do_reset$next[0:0]$3417 - attribute \src "libresoc.v:49986.7-49986.22" + attribute \src "libresoc.v:51097.3-51126.6" + wire $1\do_reset$next[0:0]$3451 + attribute \src "libresoc.v:50684.7-50684.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:50369.3-50398.6" - wire $1\do_step$next[0:0]$3410 - attribute \src "libresoc.v:49990.7-49990.21" + attribute \src "libresoc.v:51067.3-51096.6" + wire $1\do_step$next[0:0]$3444 + attribute \src "libresoc.v:50688.7-50688.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:50238.3-50265.6" - wire width 7 $1\gspr_index$next[6:0]$3389 - attribute \src "libresoc.v:49994.13-49994.31" + attribute \src "libresoc.v:50936.3-50963.6" + wire width 7 $1\gspr_index$next[6:0]$3423 + attribute \src "libresoc.v:50692.13-50692.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:50266.3-50299.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3395 - attribute \src "libresoc.v:50000.14-50000.34" + attribute \src "libresoc.v:50964.3-50997.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3429 + attribute \src "libresoc.v:50698.14-50698.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:50194.3-50237.6" - wire $1\stopping$next[0:0]$3380 - attribute \src "libresoc.v:50012.7-50012.22" + attribute \src "libresoc.v:50892.3-50935.6" + wire $1\stopping$next[0:0]$3414 + attribute \src "libresoc.v:50710.7-50710.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:50144.3-50193.6" - wire $1\terminated$next[0:0]$3370 - attribute \src "libresoc.v:50018.7-50018.24" + attribute \src "libresoc.v:50842.3-50891.6" + wire $1\terminated$next[0:0]$3404 + attribute \src "libresoc.v:50716.7-50716.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:50459.3-50492.6" - wire $2\do_dmi_log_rd$next[0:0]$3432 - attribute \src "libresoc.v:50429.3-50458.6" - wire $2\do_icreset$next[0:0]$3425 - attribute \src "libresoc.v:50399.3-50428.6" - wire $2\do_reset$next[0:0]$3418 - attribute \src "libresoc.v:50369.3-50398.6" - wire $2\do_step$next[0:0]$3411 - attribute \src "libresoc.v:50238.3-50265.6" - wire width 7 $2\gspr_index$next[6:0]$3390 - attribute \src "libresoc.v:50266.3-50299.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3396 - attribute \src "libresoc.v:50194.3-50237.6" - wire $2\stopping$next[0:0]$3381 - attribute \src "libresoc.v:50144.3-50193.6" - wire $2\terminated$next[0:0]$3371 - attribute \src "libresoc.v:50459.3-50492.6" - wire $3\do_dmi_log_rd$next[0:0]$3433 - attribute \src "libresoc.v:50429.3-50458.6" - wire $3\do_icreset$next[0:0]$3426 - attribute \src "libresoc.v:50399.3-50428.6" - wire $3\do_reset$next[0:0]$3419 - attribute \src "libresoc.v:50369.3-50398.6" - wire $3\do_step$next[0:0]$3412 - attribute \src "libresoc.v:50238.3-50265.6" - wire width 7 $3\gspr_index$next[6:0]$3391 - attribute \src "libresoc.v:50266.3-50299.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3397 - attribute \src "libresoc.v:50194.3-50237.6" - wire $3\stopping$next[0:0]$3382 - attribute \src "libresoc.v:50144.3-50193.6" - wire $3\terminated$next[0:0]$3372 - attribute \src "libresoc.v:50459.3-50492.6" - wire $4\do_dmi_log_rd$next[0:0]$3434 - attribute \src "libresoc.v:50429.3-50458.6" - wire $4\do_icreset$next[0:0]$3427 - attribute \src "libresoc.v:50399.3-50428.6" - wire $4\do_reset$next[0:0]$3420 - attribute \src "libresoc.v:50369.3-50398.6" - wire $4\do_step$next[0:0]$3413 - attribute \src "libresoc.v:50238.3-50265.6" - wire width 7 $4\gspr_index$next[6:0]$3392 - attribute \src "libresoc.v:50266.3-50299.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3398 - attribute \src "libresoc.v:50194.3-50237.6" - wire $4\stopping$next[0:0]$3383 - attribute \src "libresoc.v:50144.3-50193.6" - wire $4\terminated$next[0:0]$3373 - attribute \src "libresoc.v:50429.3-50458.6" - wire $5\do_icreset$next[0:0]$3428 - attribute \src "libresoc.v:50399.3-50428.6" - wire $5\do_reset$next[0:0]$3421 - attribute \src "libresoc.v:50369.3-50398.6" - wire $5\do_step$next[0:0]$3414 - attribute \src "libresoc.v:50194.3-50237.6" - wire $5\stopping$next[0:0]$3384 - attribute \src "libresoc.v:50144.3-50193.6" - wire $5\terminated$next[0:0]$3374 - attribute \src "libresoc.v:50194.3-50237.6" - wire $6\stopping$next[0:0]$3385 - attribute \src "libresoc.v:50144.3-50193.6" - wire $6\terminated$next[0:0]$3375 - attribute \src "libresoc.v:50194.3-50237.6" - wire $7\stopping$next[0:0]$3386 - attribute \src "libresoc.v:50144.3-50193.6" - wire $7\terminated$next[0:0]$3376 - attribute \src "libresoc.v:50144.3-50193.6" - wire $8\terminated$next[0:0]$3377 - attribute \src "libresoc.v:50032.19-50032.110" - wire width 3 $add$libresoc.v:50032$3299_Y - attribute \src "libresoc.v:50023.17-50023.109" - wire $and$libresoc.v:50023$3290_Y - attribute \src "libresoc.v:50026.19-50026.103" - wire $and$libresoc.v:50026$3293_Y - attribute \src "libresoc.v:50028.19-50028.113" - wire $and$libresoc.v:50028$3295_Y - attribute \src "libresoc.v:50035.19-50035.103" - wire $and$libresoc.v:50035$3302_Y - attribute \src "libresoc.v:50037.19-50037.102" - wire $and$libresoc.v:50037$3304_Y - attribute \src "libresoc.v:50042.18-50042.101" - wire $and$libresoc.v:50042$3309_Y - attribute \src "libresoc.v:50044.18-50044.111" - wire $and$libresoc.v:50044$3311_Y - attribute \src "libresoc.v:50049.18-50049.101" - wire $and$libresoc.v:50049$3316_Y - attribute \src "libresoc.v:50051.18-50051.111" - wire $and$libresoc.v:50051$3318_Y - attribute \src "libresoc.v:50057.18-50057.101" - wire $and$libresoc.v:50057$3324_Y - attribute \src "libresoc.v:50059.18-50059.111" - wire $and$libresoc.v:50059$3326_Y - attribute \src "libresoc.v:50063.17-50063.99" - wire $and$libresoc.v:50063$3330_Y - attribute \src "libresoc.v:50065.18-50065.101" - wire $and$libresoc.v:50065$3332_Y - attribute \src "libresoc.v:50067.18-50067.111" - wire $and$libresoc.v:50067$3334_Y - attribute \src "libresoc.v:50072.18-50072.101" - wire $and$libresoc.v:50072$3339_Y - attribute \src "libresoc.v:50075.18-50075.111" - wire $and$libresoc.v:50075$3342_Y - attribute \src "libresoc.v:50080.18-50080.101" - wire $and$libresoc.v:50080$3347_Y - attribute \src "libresoc.v:50082.18-50082.111" - wire $and$libresoc.v:50082$3349_Y - attribute \src "libresoc.v:50024.18-50024.103" - wire $eq$libresoc.v:50024$3291_Y - attribute \src "libresoc.v:50029.19-50029.104" - wire $eq$libresoc.v:50029$3296_Y - attribute \src "libresoc.v:50030.19-50030.104" - wire $eq$libresoc.v:50030$3297_Y - attribute \src "libresoc.v:50031.19-50031.104" - wire $eq$libresoc.v:50031$3298_Y - attribute \src "libresoc.v:50033.19-50033.104" - wire $eq$libresoc.v:50033$3300_Y - attribute \src "libresoc.v:50034.18-50034.103" - wire $eq$libresoc.v:50034$3301_Y - attribute \src "libresoc.v:50038.18-50038.103" - wire $eq$libresoc.v:50038$3305_Y - attribute \src "libresoc.v:50039.18-50039.103" - wire $eq$libresoc.v:50039$3306_Y - attribute \src "libresoc.v:50045.18-50045.103" - wire $eq$libresoc.v:50045$3312_Y - attribute \src "libresoc.v:50046.18-50046.103" - wire $eq$libresoc.v:50046$3313_Y - attribute \src "libresoc.v:50047.18-50047.103" - wire $eq$libresoc.v:50047$3314_Y - attribute \src "libresoc.v:50053.18-50053.103" - wire $eq$libresoc.v:50053$3320_Y - attribute \src "libresoc.v:50054.18-50054.103" - wire $eq$libresoc.v:50054$3321_Y - attribute \src "libresoc.v:50055.18-50055.103" - wire $eq$libresoc.v:50055$3322_Y - attribute \src "libresoc.v:50060.18-50060.103" - wire $eq$libresoc.v:50060$3327_Y - attribute \src "libresoc.v:50061.18-50061.103" - wire $eq$libresoc.v:50061$3328_Y - attribute \src "libresoc.v:50062.18-50062.103" - wire $eq$libresoc.v:50062$3329_Y - attribute \src "libresoc.v:50068.18-50068.103" - wire $eq$libresoc.v:50068$3335_Y - attribute \src "libresoc.v:50069.18-50069.103" - wire $eq$libresoc.v:50069$3336_Y - attribute \src "libresoc.v:50070.18-50070.103" - wire $eq$libresoc.v:50070$3337_Y - attribute \src "libresoc.v:50076.18-50076.103" - wire $eq$libresoc.v:50076$3343_Y - attribute \src "libresoc.v:50077.18-50077.103" - wire $eq$libresoc.v:50077$3344_Y - attribute \src "libresoc.v:50078.18-50078.103" - wire $eq$libresoc.v:50078$3345_Y - attribute \src "libresoc.v:50083.18-50083.103" - wire $eq$libresoc.v:50083$3350_Y - attribute \src "libresoc.v:50084.18-50084.103" - wire $eq$libresoc.v:50084$3351_Y - attribute \src "libresoc.v:50025.19-50025.99" - wire $not$libresoc.v:50025$3292_Y - attribute \src "libresoc.v:50027.19-50027.105" - wire $not$libresoc.v:50027$3294_Y - attribute \src "libresoc.v:50036.19-50036.95" - wire $not$libresoc.v:50036$3303_Y - attribute \src "libresoc.v:50040.18-50040.98" - wire $not$libresoc.v:50040$3307_Y - attribute \src "libresoc.v:50043.18-50043.104" - wire $not$libresoc.v:50043$3310_Y - attribute \src "libresoc.v:50048.18-50048.98" - wire $not$libresoc.v:50048$3315_Y - attribute \src "libresoc.v:50050.18-50050.104" - wire $not$libresoc.v:50050$3317_Y - attribute \src "libresoc.v:50052.17-50052.97" - wire $not$libresoc.v:50052$3319_Y - attribute \src "libresoc.v:50056.18-50056.98" - wire $not$libresoc.v:50056$3323_Y - attribute \src "libresoc.v:50058.18-50058.104" - wire $not$libresoc.v:50058$3325_Y - attribute \src "libresoc.v:50064.18-50064.98" - wire $not$libresoc.v:50064$3331_Y - attribute \src "libresoc.v:50066.18-50066.104" - wire $not$libresoc.v:50066$3333_Y - attribute \src "libresoc.v:50071.18-50071.98" - wire $not$libresoc.v:50071$3338_Y - attribute \src "libresoc.v:50073.18-50073.104" - wire $not$libresoc.v:50073$3340_Y - attribute \src "libresoc.v:50074.17-50074.103" - wire $not$libresoc.v:50074$3341_Y - attribute \src "libresoc.v:50079.18-50079.98" - wire $not$libresoc.v:50079$3346_Y - attribute \src "libresoc.v:50081.18-50081.104" - wire $not$libresoc.v:50081$3348_Y - attribute \src "libresoc.v:50041.17-50041.126" - wire width 64 $pos$libresoc.v:50041$3308_Y + attribute \src "libresoc.v:51157.3-51190.6" + wire $2\do_dmi_log_rd$next[0:0]$3466 + attribute \src "libresoc.v:51127.3-51156.6" + wire $2\do_icreset$next[0:0]$3459 + attribute \src "libresoc.v:51097.3-51126.6" + wire $2\do_reset$next[0:0]$3452 + attribute \src "libresoc.v:51067.3-51096.6" + wire $2\do_step$next[0:0]$3445 + attribute \src "libresoc.v:50936.3-50963.6" + wire width 7 $2\gspr_index$next[6:0]$3424 + attribute \src "libresoc.v:50964.3-50997.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3430 + attribute \src "libresoc.v:50892.3-50935.6" + wire $2\stopping$next[0:0]$3415 + attribute \src "libresoc.v:50842.3-50891.6" + wire $2\terminated$next[0:0]$3405 + attribute \src "libresoc.v:51157.3-51190.6" + wire $3\do_dmi_log_rd$next[0:0]$3467 + attribute \src "libresoc.v:51127.3-51156.6" + wire $3\do_icreset$next[0:0]$3460 + attribute \src "libresoc.v:51097.3-51126.6" + wire $3\do_reset$next[0:0]$3453 + attribute \src "libresoc.v:51067.3-51096.6" + wire $3\do_step$next[0:0]$3446 + attribute \src "libresoc.v:50936.3-50963.6" + wire width 7 $3\gspr_index$next[6:0]$3425 + attribute \src "libresoc.v:50964.3-50997.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3431 + attribute \src "libresoc.v:50892.3-50935.6" + wire $3\stopping$next[0:0]$3416 + attribute \src "libresoc.v:50842.3-50891.6" + wire $3\terminated$next[0:0]$3406 + attribute \src "libresoc.v:51157.3-51190.6" + wire $4\do_dmi_log_rd$next[0:0]$3468 + attribute \src "libresoc.v:51127.3-51156.6" + wire $4\do_icreset$next[0:0]$3461 + attribute \src "libresoc.v:51097.3-51126.6" + wire $4\do_reset$next[0:0]$3454 + attribute \src "libresoc.v:51067.3-51096.6" + wire $4\do_step$next[0:0]$3447 + attribute \src "libresoc.v:50936.3-50963.6" + wire width 7 $4\gspr_index$next[6:0]$3426 + attribute \src "libresoc.v:50964.3-50997.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3432 + attribute \src "libresoc.v:50892.3-50935.6" + wire $4\stopping$next[0:0]$3417 + attribute \src "libresoc.v:50842.3-50891.6" + wire $4\terminated$next[0:0]$3407 + attribute \src "libresoc.v:51127.3-51156.6" + wire $5\do_icreset$next[0:0]$3462 + attribute \src "libresoc.v:51097.3-51126.6" + wire $5\do_reset$next[0:0]$3455 + attribute \src "libresoc.v:51067.3-51096.6" + wire $5\do_step$next[0:0]$3448 + attribute \src "libresoc.v:50892.3-50935.6" + wire $5\stopping$next[0:0]$3418 + attribute \src "libresoc.v:50842.3-50891.6" + wire $5\terminated$next[0:0]$3408 + attribute \src "libresoc.v:50892.3-50935.6" + wire $6\stopping$next[0:0]$3419 + attribute \src "libresoc.v:50842.3-50891.6" + wire $6\terminated$next[0:0]$3409 + attribute \src "libresoc.v:50892.3-50935.6" + wire $7\stopping$next[0:0]$3420 + attribute \src "libresoc.v:50842.3-50891.6" + wire $7\terminated$next[0:0]$3410 + attribute \src "libresoc.v:50842.3-50891.6" + wire $8\terminated$next[0:0]$3411 + attribute \src "libresoc.v:50730.19-50730.110" + wire width 3 $add$libresoc.v:50730$3333_Y + attribute \src "libresoc.v:50721.17-50721.109" + wire $and$libresoc.v:50721$3324_Y + attribute \src "libresoc.v:50724.19-50724.103" + wire $and$libresoc.v:50724$3327_Y + attribute \src "libresoc.v:50726.19-50726.113" + wire $and$libresoc.v:50726$3329_Y + attribute \src "libresoc.v:50733.19-50733.103" + wire $and$libresoc.v:50733$3336_Y + attribute \src "libresoc.v:50735.19-50735.102" + wire $and$libresoc.v:50735$3338_Y + attribute \src "libresoc.v:50740.18-50740.101" + wire $and$libresoc.v:50740$3343_Y + attribute \src "libresoc.v:50742.18-50742.111" + wire $and$libresoc.v:50742$3345_Y + attribute \src "libresoc.v:50747.18-50747.101" + wire $and$libresoc.v:50747$3350_Y + attribute \src "libresoc.v:50749.18-50749.111" + wire $and$libresoc.v:50749$3352_Y + attribute \src "libresoc.v:50755.18-50755.101" + wire $and$libresoc.v:50755$3358_Y + attribute \src "libresoc.v:50757.18-50757.111" + wire $and$libresoc.v:50757$3360_Y + attribute \src "libresoc.v:50761.17-50761.99" + wire $and$libresoc.v:50761$3364_Y + attribute \src "libresoc.v:50763.18-50763.101" + wire $and$libresoc.v:50763$3366_Y + attribute \src "libresoc.v:50765.18-50765.111" + wire $and$libresoc.v:50765$3368_Y + attribute \src "libresoc.v:50770.18-50770.101" + wire $and$libresoc.v:50770$3373_Y + attribute \src "libresoc.v:50773.18-50773.111" + wire $and$libresoc.v:50773$3376_Y + attribute \src "libresoc.v:50778.18-50778.101" + wire $and$libresoc.v:50778$3381_Y + attribute \src "libresoc.v:50780.18-50780.111" + wire $and$libresoc.v:50780$3383_Y + attribute \src "libresoc.v:50722.18-50722.103" + wire $eq$libresoc.v:50722$3325_Y + attribute \src "libresoc.v:50727.19-50727.104" + wire $eq$libresoc.v:50727$3330_Y + attribute \src "libresoc.v:50728.19-50728.104" + wire $eq$libresoc.v:50728$3331_Y + attribute \src "libresoc.v:50729.19-50729.104" + wire $eq$libresoc.v:50729$3332_Y + attribute \src "libresoc.v:50731.19-50731.104" + wire $eq$libresoc.v:50731$3334_Y + attribute \src "libresoc.v:50732.18-50732.103" + wire $eq$libresoc.v:50732$3335_Y + attribute \src "libresoc.v:50736.18-50736.103" + wire $eq$libresoc.v:50736$3339_Y + attribute \src "libresoc.v:50737.18-50737.103" + wire $eq$libresoc.v:50737$3340_Y + attribute \src "libresoc.v:50743.18-50743.103" + wire $eq$libresoc.v:50743$3346_Y + attribute \src "libresoc.v:50744.18-50744.103" + wire $eq$libresoc.v:50744$3347_Y + attribute \src "libresoc.v:50745.18-50745.103" + wire $eq$libresoc.v:50745$3348_Y + attribute \src "libresoc.v:50751.18-50751.103" + wire $eq$libresoc.v:50751$3354_Y + attribute \src "libresoc.v:50752.18-50752.103" + wire $eq$libresoc.v:50752$3355_Y + attribute \src "libresoc.v:50753.18-50753.103" + wire $eq$libresoc.v:50753$3356_Y + attribute \src "libresoc.v:50758.18-50758.103" + wire $eq$libresoc.v:50758$3361_Y + attribute \src "libresoc.v:50759.18-50759.103" + wire $eq$libresoc.v:50759$3362_Y + attribute \src "libresoc.v:50760.18-50760.103" + wire $eq$libresoc.v:50760$3363_Y + attribute \src "libresoc.v:50766.18-50766.103" + wire $eq$libresoc.v:50766$3369_Y + attribute \src "libresoc.v:50767.18-50767.103" + wire $eq$libresoc.v:50767$3370_Y + attribute \src "libresoc.v:50768.18-50768.103" + wire $eq$libresoc.v:50768$3371_Y + attribute \src "libresoc.v:50774.18-50774.103" + wire $eq$libresoc.v:50774$3377_Y + attribute \src "libresoc.v:50775.18-50775.103" + wire $eq$libresoc.v:50775$3378_Y + attribute \src "libresoc.v:50776.18-50776.103" + wire $eq$libresoc.v:50776$3379_Y + attribute \src "libresoc.v:50781.18-50781.103" + wire $eq$libresoc.v:50781$3384_Y + attribute \src "libresoc.v:50782.18-50782.103" + wire $eq$libresoc.v:50782$3385_Y + attribute \src "libresoc.v:50723.19-50723.99" + wire $not$libresoc.v:50723$3326_Y + attribute \src "libresoc.v:50725.19-50725.105" + wire $not$libresoc.v:50725$3328_Y + attribute \src "libresoc.v:50734.19-50734.95" + wire $not$libresoc.v:50734$3337_Y + attribute \src "libresoc.v:50738.18-50738.98" + wire $not$libresoc.v:50738$3341_Y + attribute \src "libresoc.v:50741.18-50741.104" + wire $not$libresoc.v:50741$3344_Y + attribute \src "libresoc.v:50746.18-50746.98" + wire $not$libresoc.v:50746$3349_Y + attribute \src "libresoc.v:50748.18-50748.104" + wire $not$libresoc.v:50748$3351_Y + attribute \src "libresoc.v:50750.17-50750.97" + wire $not$libresoc.v:50750$3353_Y + attribute \src "libresoc.v:50754.18-50754.98" + wire $not$libresoc.v:50754$3357_Y + attribute \src "libresoc.v:50756.18-50756.104" + wire $not$libresoc.v:50756$3359_Y + attribute \src "libresoc.v:50762.18-50762.98" + wire $not$libresoc.v:50762$3365_Y + attribute \src "libresoc.v:50764.18-50764.104" + wire $not$libresoc.v:50764$3367_Y + attribute \src "libresoc.v:50769.18-50769.98" + wire $not$libresoc.v:50769$3372_Y + attribute \src "libresoc.v:50771.18-50771.104" + wire $not$libresoc.v:50771$3374_Y + attribute \src "libresoc.v:50772.17-50772.103" + wire $not$libresoc.v:50772$3375_Y + attribute \src "libresoc.v:50777.18-50777.98" + wire $not$libresoc.v:50777$3380_Y + attribute \src "libresoc.v:50779.18-50779.104" + wire $not$libresoc.v:50779$3382_Y + attribute \src "libresoc.v:50739.17-50739.126" + wire width 64 $pos$libresoc.v:50739$3342_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" @@ -89267,46 +90285,46 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 6 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 24 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 10 \core_dbg_msr + wire width 64 input 11 \core_dbg_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 9 \core_dbg_pc + wire width 64 input 10 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire output 7 \core_rst_o + wire output 8 \core_rst_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire output 11 \core_stop_o + wire output 12 \core_stop_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire input 12 \core_stopped_i + wire input 13 \core_stopped_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 19 \d_cr_ack + wire input 20 \d_cr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 18 \d_cr_data + wire width 64 input 19 \d_cr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 17 \d_cr_req + wire output 18 \d_cr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 16 \d_gpr_ack + wire input 17 \d_gpr_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 output 14 \d_gpr_addr + wire width 7 output 15 \d_gpr_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 15 \d_gpr_data + wire width 64 input 16 \d_gpr_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 13 \d_gpr_req + wire output 14 \d_gpr_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 22 \d_xer_ack + wire input 23 \d_xer_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 21 \d_xer_data + wire width 64 input 22 \d_xer_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 20 \d_xer_req + wire output 21 \d_xer_req attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire output 4 \dmi_ack_o + wire output 6 \dmi_ack_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 24 \dmi_addr_i + wire width 4 input 2 \dmi_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 3 \dmi_din + wire width 64 input 5 \dmi_din attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 output 5 \dmi_dout + wire width 64 output 7 \dmi_dout attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" wire \dmi_read_log_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" @@ -89316,13 +90334,13 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" wire \dmi_read_log_data_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire input 1 \dmi_req_i + wire input 3 \dmi_req_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" wire \dmi_req_i_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" wire \dmi_req_i_1$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 2 \dmi_we_i + wire input 4 \dmi_we_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" wire \do_dmi_log_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" @@ -89345,7 +90363,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire \icache_rst_o - attribute \src "libresoc.v:49789.7-49789.15" + attribute \src "libresoc.v:50487.7-50487.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" wire width 32 \log_dmi_addr @@ -89355,8 +90373,8 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 23 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" wire width 64 \stat_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" @@ -89364,7 +90382,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" wire \stopping$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire input 8 \terminate_i + wire input 9 \terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" wire \terminated attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" @@ -89372,7 +90390,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:50032$3299 + cell $add $add$libresoc.v:50730$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -89380,10 +90398,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:50032$3299_Y + connect \Y $add$libresoc.v:50730$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50023$3290 + cell $and $and$libresoc.v:50721$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89391,10 +90409,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$7 - connect \Y $and$libresoc.v:50023$3290_Y + connect \Y $and$libresoc.v:50721$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50026$3293 + cell $and $and$libresoc.v:50724$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89402,10 +90420,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$101 - connect \Y $and$libresoc.v:50026$3293_Y + connect \Y $and$libresoc.v:50724$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50028$3295 + cell $and $and$libresoc.v:50726$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89413,10 +90431,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$105 - connect \Y $and$libresoc.v:50028$3295_Y + connect \Y $and$libresoc.v:50726$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:50035$3302 + cell $and $and$libresoc.v:50733$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89424,10 +90442,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$118 - connect \Y $and$libresoc.v:50035$3302_Y + connect \Y $and$libresoc.v:50733$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:50037$3304 + cell $and $and$libresoc.v:50735$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89435,10 +90453,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$122 - connect \Y $and$libresoc.v:50037$3304_Y + connect \Y $and$libresoc.v:50735$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50042$3309 + cell $and $and$libresoc.v:50740$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89446,10 +90464,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$17 - connect \Y $and$libresoc.v:50042$3309_Y + connect \Y $and$libresoc.v:50740$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50044$3311 + cell $and $and$libresoc.v:50742$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89457,10 +90475,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$21 - connect \Y $and$libresoc.v:50044$3311_Y + connect \Y $and$libresoc.v:50742$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50049$3316 + cell $and $and$libresoc.v:50747$3350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89468,10 +90486,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$31 - connect \Y $and$libresoc.v:50049$3316_Y + connect \Y $and$libresoc.v:50747$3350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50051$3318 + cell $and $and$libresoc.v:50749$3352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89479,10 +90497,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$35 - connect \Y $and$libresoc.v:50051$3318_Y + connect \Y $and$libresoc.v:50749$3352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50057$3324 + cell $and $and$libresoc.v:50755$3358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89490,10 +90508,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$45 - connect \Y $and$libresoc.v:50057$3324_Y + connect \Y $and$libresoc.v:50755$3358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50059$3326 + cell $and $and$libresoc.v:50757$3360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89501,10 +90519,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$49 - connect \Y $and$libresoc.v:50059$3326_Y + connect \Y $and$libresoc.v:50757$3360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50063$3330 + cell $and $and$libresoc.v:50761$3364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89512,10 +90530,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$3 - connect \Y $and$libresoc.v:50063$3330_Y + connect \Y $and$libresoc.v:50761$3364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50065$3332 + cell $and $and$libresoc.v:50763$3366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89523,10 +90541,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$59 - connect \Y $and$libresoc.v:50065$3332_Y + connect \Y $and$libresoc.v:50763$3366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50067$3334 + cell $and $and$libresoc.v:50765$3368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89534,10 +90552,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$63 - connect \Y $and$libresoc.v:50067$3334_Y + connect \Y $and$libresoc.v:50765$3368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50072$3339 + cell $and $and$libresoc.v:50770$3373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89545,10 +90563,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$73 - connect \Y $and$libresoc.v:50072$3339_Y + connect \Y $and$libresoc.v:50770$3373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50075$3342 + cell $and $and$libresoc.v:50773$3376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89556,10 +90574,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$77 - connect \Y $and$libresoc.v:50075$3342_Y + connect \Y $and$libresoc.v:50773$3376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50080$3347 + cell $and $and$libresoc.v:50778$3381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89567,10 +90585,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$87 - connect \Y $and$libresoc.v:50080$3347_Y + connect \Y $and$libresoc.v:50778$3381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50082$3349 + cell $and $and$libresoc.v:50780$3383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -89578,10 +90596,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$91 - connect \Y $and$libresoc.v:50082$3349_Y + connect \Y $and$libresoc.v:50780$3383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50024$3291 + cell $eq $eq$libresoc.v:50722$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89589,10 +90607,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50024$3291_Y + connect \Y $eq$libresoc.v:50722$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50029$3296 + cell $eq $eq$libresoc.v:50727$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89600,10 +90618,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50029$3296_Y + connect \Y $eq$libresoc.v:50727$3330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50030$3297 + cell $eq $eq$libresoc.v:50728$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89611,10 +90629,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50030$3297_Y + connect \Y $eq$libresoc.v:50728$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50031$3298 + cell $eq $eq$libresoc.v:50729$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89622,10 +90640,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50031$3298_Y + connect \Y $eq$libresoc.v:50729$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $eq $eq$libresoc.v:50033$3300 + cell $eq $eq$libresoc.v:50731$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89633,10 +90651,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:50033$3300_Y + connect \Y $eq$libresoc.v:50731$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50034$3301 + cell $eq $eq$libresoc.v:50732$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89644,10 +90662,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50034$3301_Y + connect \Y $eq$libresoc.v:50732$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50038$3305 + cell $eq $eq$libresoc.v:50736$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89655,10 +90673,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50038$3305_Y + connect \Y $eq$libresoc.v:50736$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50039$3306 + cell $eq $eq$libresoc.v:50737$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89666,10 +90684,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50039$3306_Y + connect \Y $eq$libresoc.v:50737$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50045$3312 + cell $eq $eq$libresoc.v:50743$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89677,10 +90695,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50045$3312_Y + connect \Y $eq$libresoc.v:50743$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50046$3313 + cell $eq $eq$libresoc.v:50744$3347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89688,10 +90706,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50046$3313_Y + connect \Y $eq$libresoc.v:50744$3347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50047$3314 + cell $eq $eq$libresoc.v:50745$3348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89699,10 +90717,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50047$3314_Y + connect \Y $eq$libresoc.v:50745$3348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50053$3320 + cell $eq $eq$libresoc.v:50751$3354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89710,10 +90728,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50053$3320_Y + connect \Y $eq$libresoc.v:50751$3354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50054$3321 + cell $eq $eq$libresoc.v:50752$3355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89721,10 +90739,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50054$3321_Y + connect \Y $eq$libresoc.v:50752$3355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50055$3322 + cell $eq $eq$libresoc.v:50753$3356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89732,10 +90750,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50055$3322_Y + connect \Y $eq$libresoc.v:50753$3356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50060$3327 + cell $eq $eq$libresoc.v:50758$3361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89743,10 +90761,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50060$3327_Y + connect \Y $eq$libresoc.v:50758$3361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50061$3328 + cell $eq $eq$libresoc.v:50759$3362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89754,10 +90772,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50061$3328_Y + connect \Y $eq$libresoc.v:50759$3362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50062$3329 + cell $eq $eq$libresoc.v:50760$3363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89765,10 +90783,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50062$3329_Y + connect \Y $eq$libresoc.v:50760$3363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50068$3335 + cell $eq $eq$libresoc.v:50766$3369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89776,10 +90794,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50068$3335_Y + connect \Y $eq$libresoc.v:50766$3369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50069$3336 + cell $eq $eq$libresoc.v:50767$3370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89787,10 +90805,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50069$3336_Y + connect \Y $eq$libresoc.v:50767$3370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50070$3337 + cell $eq $eq$libresoc.v:50768$3371 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89798,10 +90816,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50070$3337_Y + connect \Y $eq$libresoc.v:50768$3371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50076$3343 + cell $eq $eq$libresoc.v:50774$3377 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89809,10 +90827,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50076$3343_Y + connect \Y $eq$libresoc.v:50774$3377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50077$3344 + cell $eq $eq$libresoc.v:50775$3378 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89820,10 +90838,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50077$3344_Y + connect \Y $eq$libresoc.v:50775$3378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:50078$3345 + cell $eq $eq$libresoc.v:50776$3379 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89831,10 +90849,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:50078$3345_Y + connect \Y $eq$libresoc.v:50776$3379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:50083$3350 + cell $eq $eq$libresoc.v:50781$3384 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89842,10 +90860,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:50083$3350_Y + connect \Y $eq$libresoc.v:50781$3384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:50084$3351 + cell $eq $eq$libresoc.v:50782$3385 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -89853,332 +90871,332 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:50084$3351_Y + connect \Y $eq$libresoc.v:50782$3385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50025$3292 + cell $not $not$libresoc.v:50723$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50025$3292_Y + connect \Y $not$libresoc.v:50723$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50027$3294 + cell $not $not$libresoc.v:50725$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50027$3294_Y + connect \Y $not$libresoc.v:50725$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $not $not$libresoc.v:50036$3303 + cell $not $not$libresoc.v:50734$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:50036$3303_Y + connect \Y $not$libresoc.v:50734$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50040$3307 + cell $not $not$libresoc.v:50738$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50040$3307_Y + connect \Y $not$libresoc.v:50738$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50043$3310 + cell $not $not$libresoc.v:50741$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50043$3310_Y + connect \Y $not$libresoc.v:50741$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50048$3315 + cell $not $not$libresoc.v:50746$3349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50048$3315_Y + connect \Y $not$libresoc.v:50746$3349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50050$3317 + cell $not $not$libresoc.v:50748$3351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50050$3317_Y + connect \Y $not$libresoc.v:50748$3351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50052$3319 + cell $not $not$libresoc.v:50750$3353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50052$3319_Y + connect \Y $not$libresoc.v:50750$3353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50056$3323 + cell $not $not$libresoc.v:50754$3357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50056$3323_Y + connect \Y $not$libresoc.v:50754$3357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50058$3325 + cell $not $not$libresoc.v:50756$3359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50058$3325_Y + connect \Y $not$libresoc.v:50756$3359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50064$3331 + cell $not $not$libresoc.v:50762$3365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50064$3331_Y + connect \Y $not$libresoc.v:50762$3365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50066$3333 + cell $not $not$libresoc.v:50764$3367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50066$3333_Y + connect \Y $not$libresoc.v:50764$3367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50071$3338 + cell $not $not$libresoc.v:50769$3372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50071$3338_Y + connect \Y $not$libresoc.v:50769$3372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50073$3340 + cell $not $not$libresoc.v:50771$3374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50073$3340_Y + connect \Y $not$libresoc.v:50771$3374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50074$3341 + cell $not $not$libresoc.v:50772$3375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50074$3341_Y + connect \Y $not$libresoc.v:50772$3375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:50079$3346 + cell $not $not$libresoc.v:50777$3380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:50079$3346_Y + connect \Y $not$libresoc.v:50777$3380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:50081$3348 + cell $not $not$libresoc.v:50779$3382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:50081$3348_Y + connect \Y $not$libresoc.v:50779$3382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - cell $pos $pos$libresoc.v:50041$3308 + cell $pos $pos$libresoc.v:50739$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:50041$3308_Y + connect \Y $pos$libresoc.v:50739$3342_Y end - attribute \src "libresoc.v:49789.7-49789.20" - process $proc$libresoc.v:49789$3435 + attribute \src "libresoc.v:50487.7-50487.20" + process $proc$libresoc.v:50487$3469 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49962.7-49962.31" - process $proc$libresoc.v:49962$3436 + attribute \src "libresoc.v:50660.7-50660.31" + process $proc$libresoc.v:50660$3470 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:49966.7-49966.33" - process $proc$libresoc.v:49966$3437 + attribute \src "libresoc.v:50664.7-50664.33" + process $proc$libresoc.v:50664$3471 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:49972.7-49972.25" - process $proc$libresoc.v:49972$3438 + attribute \src "libresoc.v:50670.7-50670.25" + process $proc$libresoc.v:50670$3472 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:49978.7-49978.27" - process $proc$libresoc.v:49978$3439 + attribute \src "libresoc.v:50676.7-50676.27" + process $proc$libresoc.v:50676$3473 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:49982.7-49982.24" - process $proc$libresoc.v:49982$3440 + attribute \src "libresoc.v:50680.7-50680.24" + process $proc$libresoc.v:50680$3474 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:49986.7-49986.22" - process $proc$libresoc.v:49986$3441 + attribute \src "libresoc.v:50684.7-50684.22" + process $proc$libresoc.v:50684$3475 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:49990.7-49990.21" - process $proc$libresoc.v:49990$3442 + attribute \src "libresoc.v:50688.7-50688.21" + process $proc$libresoc.v:50688$3476 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:49994.13-49994.31" - process $proc$libresoc.v:49994$3443 + attribute \src "libresoc.v:50692.13-50692.31" + process $proc$libresoc.v:50692$3477 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:50000.14-50000.34" - process $proc$libresoc.v:50000$3444 + attribute \src "libresoc.v:50698.14-50698.34" + process $proc$libresoc.v:50698$3478 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50012.7-50012.22" - process $proc$libresoc.v:50012$3445 + attribute \src "libresoc.v:50710.7-50710.22" + process $proc$libresoc.v:50710$3479 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:50018.7-50018.24" - process $proc$libresoc.v:50018$3446 + attribute \src "libresoc.v:50716.7-50716.24" + process $proc$libresoc.v:50716$3480 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:50085.3-50086.51" - process $proc$libresoc.v:50085$3352 + attribute \src "libresoc.v:50783.3-50784.51" + process $proc$libresoc.v:50783$3386 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:50087.3-50088.55" - process $proc$libresoc.v:50087$3353 + attribute \src "libresoc.v:50785.3-50786.55" + process $proc$libresoc.v:50785$3387 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:50089.3-50090.41" - process $proc$libresoc.v:50089$3354 + attribute \src "libresoc.v:50787.3-50788.41" + process $proc$libresoc.v:50787$3388 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:50091.3-50092.37" - process $proc$libresoc.v:50091$3355 + attribute \src "libresoc.v:50789.3-50790.37" + process $proc$libresoc.v:50789$3389 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:50093.3-50094.33" - process $proc$libresoc.v:50093$3356 + attribute \src "libresoc.v:50791.3-50792.33" + process $proc$libresoc.v:50791$3390 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:50095.3-50096.37" - process $proc$libresoc.v:50095$3357 + attribute \src "libresoc.v:50793.3-50794.37" + process $proc$libresoc.v:50793$3391 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:50097.3-50098.39" - process $proc$libresoc.v:50097$3358 + attribute \src "libresoc.v:50795.3-50796.39" + process $proc$libresoc.v:50795$3392 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:50099.3-50100.43" - process $proc$libresoc.v:50099$3359 + attribute \src "libresoc.v:50797.3-50798.43" + process $proc$libresoc.v:50797$3393 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:50101.3-50102.37" - process $proc$libresoc.v:50101$3360 + attribute \src "libresoc.v:50799.3-50800.37" + process $proc$libresoc.v:50799$3394 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:50103.3-50104.33" - process $proc$libresoc.v:50103$3361 + attribute \src "libresoc.v:50801.3-50802.33" + process $proc$libresoc.v:50801$3395 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:50105.3-50106.31" - process $proc$libresoc.v:50105$3362 + attribute \src "libresoc.v:50803.3-50804.31" + process $proc$libresoc.v:50803$3396 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:50107.3-50124.6" - process $proc$libresoc.v:50107$3363 + attribute \src "libresoc.v:50805.3-50822.6" + process $proc$libresoc.v:50805$3397 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50108.5-50108.29" + attribute \src "libresoc.v:50806.5-50806.29" switch \initial - attribute \src "libresoc.v:50108.9-50108.17" + attribute \src "libresoc.v:50806.9-50806.17" case 1'1 case end @@ -90204,14 +91222,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:50125.3-50134.6" - process $proc$libresoc.v:50125$3364 + attribute \src "libresoc.v:50823.3-50832.6" + process $proc$libresoc.v:50823$3398 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50126.5-50126.29" + attribute \src "libresoc.v:50824.5-50824.29" switch \initial - attribute \src "libresoc.v:50126.9-50126.17" + attribute \src "libresoc.v:50824.9-50824.17" case 1'1 case end @@ -90227,14 +91245,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:50135.3-50143.6" - process $proc$libresoc.v:50135$3365 + attribute \src "libresoc.v:50833.3-50841.6" + process $proc$libresoc.v:50833$3399 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3366 $1\dmi_req_i_1$next[0:0]$3367 - attribute \src "libresoc.v:50136.5-50136.29" + assign $0\dmi_req_i_1$next[0:0]$3400 $1\dmi_req_i_1$next[0:0]$3401 + attribute \src "libresoc.v:50834.5-50834.29" switch \initial - attribute \src "libresoc.v:50136.9-50136.17" + attribute \src "libresoc.v:50834.9-50834.17" case 1'1 case end @@ -90243,23 +91261,23 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3367 1'0 + assign $1\dmi_req_i_1$next[0:0]$3401 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3367 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3401 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3366 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3400 end - attribute \src "libresoc.v:50144.3-50193.6" - process $proc$libresoc.v:50144$3368 + attribute \src "libresoc.v:50842.3-50891.6" + process $proc$libresoc.v:50842$3402 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3369 $8\terminated$next[0:0]$3377 - attribute \src "libresoc.v:50145.5-50145.29" + assign $0\terminated$next[0:0]$3403 $8\terminated$next[0:0]$3411 + attribute \src "libresoc.v:50843.5-50843.29" switch \initial - attribute \src "libresoc.v:50145.9-50145.17" + attribute \src "libresoc.v:50843.9-50843.17" case 1'1 case end @@ -90268,13 +91286,13 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3370 $2\terminated$next[0:0]$3371 + assign $1\terminated$next[0:0]$3404 $2\terminated$next[0:0]$3405 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3371 $3\terminated$next[0:0]$3372 + assign $2\terminated$next[0:0]$3405 $3\terminated$next[0:0]$3406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$71 \$69 \$67 } attribute \src "libresoc.v:0.0-0.0" @@ -90282,74 +91300,74 @@ module \dbg assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3372 $6\terminated$next[0:0]$3375 + assign $3\terminated$next[0:0]$3406 $6\terminated$next[0:0]$3409 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3373 1'0 + assign $4\terminated$next[0:0]$3407 1'0 case - assign $4\terminated$next[0:0]$3373 \terminated + assign $4\terminated$next[0:0]$3407 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3374 1'0 + assign $5\terminated$next[0:0]$3408 1'0 case - assign $5\terminated$next[0:0]$3374 $4\terminated$next[0:0]$3373 + assign $5\terminated$next[0:0]$3408 $4\terminated$next[0:0]$3407 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3375 1'0 + assign $6\terminated$next[0:0]$3409 1'0 case - assign $6\terminated$next[0:0]$3375 $5\terminated$next[0:0]$3374 + assign $6\terminated$next[0:0]$3409 $5\terminated$next[0:0]$3408 end case - assign $3\terminated$next[0:0]$3372 \terminated + assign $3\terminated$next[0:0]$3406 \terminated end case - assign $2\terminated$next[0:0]$3371 \terminated + assign $2\terminated$next[0:0]$3405 \terminated end case - assign $1\terminated$next[0:0]$3370 \terminated + assign $1\terminated$next[0:0]$3404 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3376 1'1 + assign $7\terminated$next[0:0]$3410 1'1 case - assign $7\terminated$next[0:0]$3376 $1\terminated$next[0:0]$3370 + assign $7\terminated$next[0:0]$3410 $1\terminated$next[0:0]$3404 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3377 1'0 + assign $8\terminated$next[0:0]$3411 1'0 case - assign $8\terminated$next[0:0]$3377 $7\terminated$next[0:0]$3376 + assign $8\terminated$next[0:0]$3411 $7\terminated$next[0:0]$3410 end sync always - update \terminated$next $0\terminated$next[0:0]$3369 + update \terminated$next $0\terminated$next[0:0]$3403 end - attribute \src "libresoc.v:50194.3-50237.6" - process $proc$libresoc.v:50194$3378 + attribute \src "libresoc.v:50892.3-50935.6" + process $proc$libresoc.v:50892$3412 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3379 $7\stopping$next[0:0]$3386 - attribute \src "libresoc.v:50195.5-50195.29" + assign $0\stopping$next[0:0]$3413 $7\stopping$next[0:0]$3420 + attribute \src "libresoc.v:50893.5-50893.29" switch \initial - attribute \src "libresoc.v:50195.9-50195.17" + attribute \src "libresoc.v:50893.9-50893.17" case 1'1 case end @@ -90358,77 +91376,77 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3380 $2\stopping$next[0:0]$3381 + assign $1\stopping$next[0:0]$3414 $2\stopping$next[0:0]$3415 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3381 $3\stopping$next[0:0]$3382 + assign $2\stopping$next[0:0]$3415 $3\stopping$next[0:0]$3416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$85 \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3382 $5\stopping$next[0:0]$3384 + assign $3\stopping$next[0:0]$3416 $5\stopping$next[0:0]$3418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3383 1'1 + assign $4\stopping$next[0:0]$3417 1'1 case - assign $4\stopping$next[0:0]$3383 \stopping + assign $4\stopping$next[0:0]$3417 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3384 1'0 + assign $5\stopping$next[0:0]$3418 1'0 case - assign $5\stopping$next[0:0]$3384 $4\stopping$next[0:0]$3383 + assign $5\stopping$next[0:0]$3418 $4\stopping$next[0:0]$3417 end case - assign $3\stopping$next[0:0]$3382 \stopping + assign $3\stopping$next[0:0]$3416 \stopping end case - assign $2\stopping$next[0:0]$3381 \stopping + assign $2\stopping$next[0:0]$3415 \stopping end case - assign $1\stopping$next[0:0]$3380 \stopping + assign $1\stopping$next[0:0]$3414 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3385 1'1 + assign $6\stopping$next[0:0]$3419 1'1 case - assign $6\stopping$next[0:0]$3385 $1\stopping$next[0:0]$3380 + assign $6\stopping$next[0:0]$3419 $1\stopping$next[0:0]$3414 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3386 1'0 + assign $7\stopping$next[0:0]$3420 1'0 case - assign $7\stopping$next[0:0]$3386 $6\stopping$next[0:0]$3385 + assign $7\stopping$next[0:0]$3420 $6\stopping$next[0:0]$3419 end sync always - update \stopping$next $0\stopping$next[0:0]$3379 + update \stopping$next $0\stopping$next[0:0]$3413 end - attribute \src "libresoc.v:50238.3-50265.6" - process $proc$libresoc.v:50238$3387 + attribute \src "libresoc.v:50936.3-50963.6" + process $proc$libresoc.v:50936$3421 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3388 $4\gspr_index$next[6:0]$3392 - attribute \src "libresoc.v:50239.5-50239.29" + assign $0\gspr_index$next[6:0]$3422 $4\gspr_index$next[6:0]$3426 + attribute \src "libresoc.v:50937.5-50937.29" switch \initial - attribute \src "libresoc.v:50239.9-50239.17" + attribute \src "libresoc.v:50937.9-50937.17" case 1'1 case end @@ -90437,52 +91455,52 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3389 $2\gspr_index$next[6:0]$3390 + assign $1\gspr_index$next[6:0]$3423 $2\gspr_index$next[6:0]$3424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3390 $3\gspr_index$next[6:0]$3391 + assign $2\gspr_index$next[6:0]$3424 $3\gspr_index$next[6:0]$3425 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$99 \$97 \$95 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3391 \gspr_index + assign $3\gspr_index$next[6:0]$3425 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3391 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3425 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3391 \gspr_index + assign $3\gspr_index$next[6:0]$3425 \gspr_index end case - assign $2\gspr_index$next[6:0]$3390 \gspr_index + assign $2\gspr_index$next[6:0]$3424 \gspr_index end case - assign $1\gspr_index$next[6:0]$3389 \gspr_index + assign $1\gspr_index$next[6:0]$3423 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3392 7'0000000 + assign $4\gspr_index$next[6:0]$3426 7'0000000 case - assign $4\gspr_index$next[6:0]$3392 $1\gspr_index$next[6:0]$3389 + assign $4\gspr_index$next[6:0]$3426 $1\gspr_index$next[6:0]$3423 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3388 + update \gspr_index$next $0\gspr_index$next[6:0]$3422 end - attribute \src "libresoc.v:50266.3-50299.6" - process $proc$libresoc.v:50266$3393 + attribute \src "libresoc.v:50964.3-50997.6" + process $proc$libresoc.v:50964$3427 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3394 $4\log_dmi_addr$next[31:0]$3398 - attribute \src "libresoc.v:50267.5-50267.29" + assign $0\log_dmi_addr$next[31:0]$3428 $4\log_dmi_addr$next[31:0]$3432 + attribute \src "libresoc.v:50965.5-50965.29" switch \initial - attribute \src "libresoc.v:50267.9-50267.17" + attribute \src "libresoc.v:50965.9-50965.17" case 1'1 case end @@ -90491,58 +91509,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3395 $2\log_dmi_addr$next[31:0]$3396 + assign $1\log_dmi_addr$next[31:0]$3429 $2\log_dmi_addr$next[31:0]$3430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3396 $3\log_dmi_addr$next[31:0]$3397 + assign $2\log_dmi_addr$next[31:0]$3430 $3\log_dmi_addr$next[31:0]$3431 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$113 \$111 \$109 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3397 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3431 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3397 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3396 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3430 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3395 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3395 [1:0] \$115 [1:0] + assign $1\log_dmi_addr$next[31:0]$3429 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3429 [1:0] \$115 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3395 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3429 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3398 0 + assign $4\log_dmi_addr$next[31:0]$3432 0 case - assign $4\log_dmi_addr$next[31:0]$3398 $1\log_dmi_addr$next[31:0]$3395 + assign $4\log_dmi_addr$next[31:0]$3432 $1\log_dmi_addr$next[31:0]$3429 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3394 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3428 end - attribute \src "libresoc.v:50300.3-50308.6" - process $proc$libresoc.v:50300$3399 + attribute \src "libresoc.v:50998.3-51006.6" + process $proc$libresoc.v:50998$3433 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3400 $1\dmi_read_log_data_1$next[0:0]$3401 - attribute \src "libresoc.v:50301.5-50301.29" + assign $0\dmi_read_log_data_1$next[0:0]$3434 $1\dmi_read_log_data_1$next[0:0]$3435 + attribute \src "libresoc.v:50999.5-50999.29" switch \initial - attribute \src "libresoc.v:50301.9-50301.17" + attribute \src "libresoc.v:50999.9-50999.17" case 1'1 case end @@ -90551,21 +91569,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3401 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3435 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3401 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3435 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3400 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3434 end - attribute \src "libresoc.v:50309.3-50317.6" - process $proc$libresoc.v:50309$3402 + attribute \src "libresoc.v:51007.3-51015.6" + process $proc$libresoc.v:51007$3436 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3403 $1\dmi_read_log_data$next[0:0]$3404 - attribute \src "libresoc.v:50310.5-50310.29" + assign $0\dmi_read_log_data$next[0:0]$3437 $1\dmi_read_log_data$next[0:0]$3438 + attribute \src "libresoc.v:51008.5-51008.29" switch \initial - attribute \src "libresoc.v:50310.9-50310.17" + attribute \src "libresoc.v:51008.9-51008.17" case 1'1 case end @@ -90574,21 +91592,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3404 1'0 + assign $1\dmi_read_log_data$next[0:0]$3438 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3404 \$120 + assign $1\dmi_read_log_data$next[0:0]$3438 \$120 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3403 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3437 end - attribute \src "libresoc.v:50318.3-50327.6" - process $proc$libresoc.v:50318$3405 + attribute \src "libresoc.v:51016.3-51025.6" + process $proc$libresoc.v:51016$3439 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:50319.5-50319.29" + attribute \src "libresoc.v:51017.5-51017.29" switch \initial - attribute \src "libresoc.v:50319.9-50319.17" + attribute \src "libresoc.v:51017.9-51017.17" case 1'1 case end @@ -90604,14 +91622,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:50328.3-50337.6" - process $proc$libresoc.v:50328$3406 + attribute \src "libresoc.v:51026.3-51035.6" + process $proc$libresoc.v:51026$3440 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:50329.5-50329.29" + attribute \src "libresoc.v:51027.5-51027.29" switch \initial - attribute \src "libresoc.v:50329.9-50329.17" + attribute \src "libresoc.v:51027.9-51027.17" case 1'1 case end @@ -90627,14 +91645,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:50338.3-50368.6" - process $proc$libresoc.v:50338$3407 + attribute \src "libresoc.v:51036.3-51066.6" + process $proc$libresoc.v:51036$3441 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:50339.5-50339.29" + attribute \src "libresoc.v:51037.5-51037.29" switch \initial - attribute \src "libresoc.v:50339.9-50339.17" + attribute \src "libresoc.v:51037.9-51037.17" case 1'1 case end @@ -90678,15 +91696,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:50369.3-50398.6" - process $proc$libresoc.v:50369$3408 + attribute \src "libresoc.v:51067.3-51096.6" + process $proc$libresoc.v:51067$3442 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3409 $5\do_step$next[0:0]$3414 - attribute \src "libresoc.v:50370.5-50370.29" + assign $0\do_step$next[0:0]$3443 $5\do_step$next[0:0]$3448 + attribute \src "libresoc.v:51068.5-51068.29" switch \initial - attribute \src "libresoc.v:50370.9-50370.17" + attribute \src "libresoc.v:51068.9-51068.17" case 1'1 case end @@ -90695,58 +91713,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3410 $2\do_step$next[0:0]$3411 + assign $1\do_step$next[0:0]$3444 $2\do_step$next[0:0]$3445 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3411 $3\do_step$next[0:0]$3412 + assign $2\do_step$next[0:0]$3445 $3\do_step$next[0:0]$3446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$15 \$13 \$11 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3412 $4\do_step$next[0:0]$3413 + assign $3\do_step$next[0:0]$3446 $4\do_step$next[0:0]$3447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3413 1'1 + assign $4\do_step$next[0:0]$3447 1'1 case - assign $4\do_step$next[0:0]$3413 1'0 + assign $4\do_step$next[0:0]$3447 1'0 end case - assign $3\do_step$next[0:0]$3412 1'0 + assign $3\do_step$next[0:0]$3446 1'0 end case - assign $2\do_step$next[0:0]$3411 1'0 + assign $2\do_step$next[0:0]$3445 1'0 end case - assign $1\do_step$next[0:0]$3410 1'0 + assign $1\do_step$next[0:0]$3444 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3414 1'0 + assign $5\do_step$next[0:0]$3448 1'0 case - assign $5\do_step$next[0:0]$3414 $1\do_step$next[0:0]$3410 + assign $5\do_step$next[0:0]$3448 $1\do_step$next[0:0]$3444 end sync always - update \do_step$next $0\do_step$next[0:0]$3409 + update \do_step$next $0\do_step$next[0:0]$3443 end - attribute \src "libresoc.v:50399.3-50428.6" - process $proc$libresoc.v:50399$3415 + attribute \src "libresoc.v:51097.3-51126.6" + process $proc$libresoc.v:51097$3449 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3416 $5\do_reset$next[0:0]$3421 - attribute \src "libresoc.v:50400.5-50400.29" + assign $0\do_reset$next[0:0]$3450 $5\do_reset$next[0:0]$3455 + attribute \src "libresoc.v:51098.5-51098.29" switch \initial - attribute \src "libresoc.v:50400.9-50400.17" + attribute \src "libresoc.v:51098.9-51098.17" case 1'1 case end @@ -90755,58 +91773,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3417 $2\do_reset$next[0:0]$3418 + assign $1\do_reset$next[0:0]$3451 $2\do_reset$next[0:0]$3452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3418 $3\do_reset$next[0:0]$3419 + assign $2\do_reset$next[0:0]$3452 $3\do_reset$next[0:0]$3453 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$29 \$27 \$25 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3419 $4\do_reset$next[0:0]$3420 + assign $3\do_reset$next[0:0]$3453 $4\do_reset$next[0:0]$3454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3420 1'1 + assign $4\do_reset$next[0:0]$3454 1'1 case - assign $4\do_reset$next[0:0]$3420 1'0 + assign $4\do_reset$next[0:0]$3454 1'0 end case - assign $3\do_reset$next[0:0]$3419 1'0 + assign $3\do_reset$next[0:0]$3453 1'0 end case - assign $2\do_reset$next[0:0]$3418 1'0 + assign $2\do_reset$next[0:0]$3452 1'0 end case - assign $1\do_reset$next[0:0]$3417 1'0 + assign $1\do_reset$next[0:0]$3451 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3421 1'0 + assign $5\do_reset$next[0:0]$3455 1'0 case - assign $5\do_reset$next[0:0]$3421 $1\do_reset$next[0:0]$3417 + assign $5\do_reset$next[0:0]$3455 $1\do_reset$next[0:0]$3451 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3416 + update \do_reset$next $0\do_reset$next[0:0]$3450 end - attribute \src "libresoc.v:50429.3-50458.6" - process $proc$libresoc.v:50429$3422 + attribute \src "libresoc.v:51127.3-51156.6" + process $proc$libresoc.v:51127$3456 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3423 $5\do_icreset$next[0:0]$3428 - attribute \src "libresoc.v:50430.5-50430.29" + assign $0\do_icreset$next[0:0]$3457 $5\do_icreset$next[0:0]$3462 + attribute \src "libresoc.v:51128.5-51128.29" switch \initial - attribute \src "libresoc.v:50430.9-50430.17" + attribute \src "libresoc.v:51128.9-51128.17" case 1'1 case end @@ -90815,58 +91833,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3424 $2\do_icreset$next[0:0]$3425 + assign $1\do_icreset$next[0:0]$3458 $2\do_icreset$next[0:0]$3459 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3425 $3\do_icreset$next[0:0]$3426 + assign $2\do_icreset$next[0:0]$3459 $3\do_icreset$next[0:0]$3460 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$43 \$41 \$39 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3426 $4\do_icreset$next[0:0]$3427 + assign $3\do_icreset$next[0:0]$3460 $4\do_icreset$next[0:0]$3461 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3427 1'1 + assign $4\do_icreset$next[0:0]$3461 1'1 case - assign $4\do_icreset$next[0:0]$3427 1'0 + assign $4\do_icreset$next[0:0]$3461 1'0 end case - assign $3\do_icreset$next[0:0]$3426 1'0 + assign $3\do_icreset$next[0:0]$3460 1'0 end case - assign $2\do_icreset$next[0:0]$3425 1'0 + assign $2\do_icreset$next[0:0]$3459 1'0 end case - assign $1\do_icreset$next[0:0]$3424 1'0 + assign $1\do_icreset$next[0:0]$3458 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3428 1'0 + assign $5\do_icreset$next[0:0]$3462 1'0 case - assign $5\do_icreset$next[0:0]$3428 $1\do_icreset$next[0:0]$3424 + assign $5\do_icreset$next[0:0]$3462 $1\do_icreset$next[0:0]$3458 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3423 + update \do_icreset$next $0\do_icreset$next[0:0]$3457 end - attribute \src "libresoc.v:50459.3-50492.6" - process $proc$libresoc.v:50459$3429 + attribute \src "libresoc.v:51157.3-51190.6" + process $proc$libresoc.v:51157$3463 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3430 $4\do_dmi_log_rd$next[0:0]$3434 - attribute \src "libresoc.v:50460.5-50460.29" + assign $0\do_dmi_log_rd$next[0:0]$3464 $4\do_dmi_log_rd$next[0:0]$3468 + attribute \src "libresoc.v:51158.5-51158.29" switch \initial - attribute \src "libresoc.v:50460.9-50460.17" + attribute \src "libresoc.v:51158.9-51158.17" case 1'1 case end @@ -90875,112 +91893,112 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3431 $2\do_dmi_log_rd$next[0:0]$3432 + assign $1\do_dmi_log_rd$next[0:0]$3465 $2\do_dmi_log_rd$next[0:0]$3466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3432 $3\do_dmi_log_rd$next[0:0]$3433 + assign $2\do_dmi_log_rd$next[0:0]$3466 $3\do_dmi_log_rd$next[0:0]$3467 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$57 \$55 \$53 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3433 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3467 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3433 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3432 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3466 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3431 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3465 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3431 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3465 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3434 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3434 $1\do_dmi_log_rd$next[0:0]$3431 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3430 - end - connect \$9 $and$libresoc.v:50023$3290_Y - connect \$99 $eq$libresoc.v:50024$3291_Y - connect \$101 $not$libresoc.v:50025$3292_Y - connect \$103 $and$libresoc.v:50026$3293_Y - connect \$105 $not$libresoc.v:50027$3294_Y - connect \$107 $and$libresoc.v:50028$3295_Y - connect \$109 $eq$libresoc.v:50029$3296_Y - connect \$111 $eq$libresoc.v:50030$3297_Y - connect \$113 $eq$libresoc.v:50031$3298_Y - connect \$116 $add$libresoc.v:50032$3299_Y - connect \$118 $eq$libresoc.v:50033$3300_Y - connect \$11 $eq$libresoc.v:50034$3301_Y - connect \$120 $and$libresoc.v:50035$3302_Y - connect \$122 $not$libresoc.v:50036$3303_Y - connect \$124 $and$libresoc.v:50037$3304_Y - connect \$13 $eq$libresoc.v:50038$3305_Y - connect \$15 $eq$libresoc.v:50039$3306_Y - connect \$17 $not$libresoc.v:50040$3307_Y - connect \$1 $pos$libresoc.v:50041$3308_Y - connect \$19 $and$libresoc.v:50042$3309_Y - connect \$21 $not$libresoc.v:50043$3310_Y - connect \$23 $and$libresoc.v:50044$3311_Y - connect \$25 $eq$libresoc.v:50045$3312_Y - connect \$27 $eq$libresoc.v:50046$3313_Y - connect \$29 $eq$libresoc.v:50047$3314_Y - connect \$31 $not$libresoc.v:50048$3315_Y - connect \$33 $and$libresoc.v:50049$3316_Y - connect \$35 $not$libresoc.v:50050$3317_Y - connect \$37 $and$libresoc.v:50051$3318_Y - connect \$3 $not$libresoc.v:50052$3319_Y - connect \$39 $eq$libresoc.v:50053$3320_Y - connect \$41 $eq$libresoc.v:50054$3321_Y - connect \$43 $eq$libresoc.v:50055$3322_Y - connect \$45 $not$libresoc.v:50056$3323_Y - connect \$47 $and$libresoc.v:50057$3324_Y - connect \$49 $not$libresoc.v:50058$3325_Y - connect \$51 $and$libresoc.v:50059$3326_Y - connect \$53 $eq$libresoc.v:50060$3327_Y - connect \$55 $eq$libresoc.v:50061$3328_Y - connect \$57 $eq$libresoc.v:50062$3329_Y - connect \$5 $and$libresoc.v:50063$3330_Y - connect \$59 $not$libresoc.v:50064$3331_Y - connect \$61 $and$libresoc.v:50065$3332_Y - connect \$63 $not$libresoc.v:50066$3333_Y - connect \$65 $and$libresoc.v:50067$3334_Y - connect \$67 $eq$libresoc.v:50068$3335_Y - connect \$69 $eq$libresoc.v:50069$3336_Y - connect \$71 $eq$libresoc.v:50070$3337_Y - connect \$73 $not$libresoc.v:50071$3338_Y - connect \$75 $and$libresoc.v:50072$3339_Y - connect \$77 $not$libresoc.v:50073$3340_Y - connect \$7 $not$libresoc.v:50074$3341_Y - connect \$79 $and$libresoc.v:50075$3342_Y - connect \$81 $eq$libresoc.v:50076$3343_Y - connect \$83 $eq$libresoc.v:50077$3344_Y - connect \$85 $eq$libresoc.v:50078$3345_Y - connect \$87 $not$libresoc.v:50079$3346_Y - connect \$89 $and$libresoc.v:50080$3347_Y - connect \$91 $not$libresoc.v:50081$3348_Y - connect \$93 $and$libresoc.v:50082$3349_Y - connect \$95 $eq$libresoc.v:50083$3350_Y - connect \$97 $eq$libresoc.v:50084$3351_Y + assign $4\do_dmi_log_rd$next[0:0]$3468 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3468 $1\do_dmi_log_rd$next[0:0]$3465 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3464 + end + connect \$9 $and$libresoc.v:50721$3324_Y + connect \$99 $eq$libresoc.v:50722$3325_Y + connect \$101 $not$libresoc.v:50723$3326_Y + connect \$103 $and$libresoc.v:50724$3327_Y + connect \$105 $not$libresoc.v:50725$3328_Y + connect \$107 $and$libresoc.v:50726$3329_Y + connect \$109 $eq$libresoc.v:50727$3330_Y + connect \$111 $eq$libresoc.v:50728$3331_Y + connect \$113 $eq$libresoc.v:50729$3332_Y + connect \$116 $add$libresoc.v:50730$3333_Y + connect \$118 $eq$libresoc.v:50731$3334_Y + connect \$11 $eq$libresoc.v:50732$3335_Y + connect \$120 $and$libresoc.v:50733$3336_Y + connect \$122 $not$libresoc.v:50734$3337_Y + connect \$124 $and$libresoc.v:50735$3338_Y + connect \$13 $eq$libresoc.v:50736$3339_Y + connect \$15 $eq$libresoc.v:50737$3340_Y + connect \$17 $not$libresoc.v:50738$3341_Y + connect \$1 $pos$libresoc.v:50739$3342_Y + connect \$19 $and$libresoc.v:50740$3343_Y + connect \$21 $not$libresoc.v:50741$3344_Y + connect \$23 $and$libresoc.v:50742$3345_Y + connect \$25 $eq$libresoc.v:50743$3346_Y + connect \$27 $eq$libresoc.v:50744$3347_Y + connect \$29 $eq$libresoc.v:50745$3348_Y + connect \$31 $not$libresoc.v:50746$3349_Y + connect \$33 $and$libresoc.v:50747$3350_Y + connect \$35 $not$libresoc.v:50748$3351_Y + connect \$37 $and$libresoc.v:50749$3352_Y + connect \$3 $not$libresoc.v:50750$3353_Y + connect \$39 $eq$libresoc.v:50751$3354_Y + connect \$41 $eq$libresoc.v:50752$3355_Y + connect \$43 $eq$libresoc.v:50753$3356_Y + connect \$45 $not$libresoc.v:50754$3357_Y + connect \$47 $and$libresoc.v:50755$3358_Y + connect \$49 $not$libresoc.v:50756$3359_Y + connect \$51 $and$libresoc.v:50757$3360_Y + connect \$53 $eq$libresoc.v:50758$3361_Y + connect \$55 $eq$libresoc.v:50759$3362_Y + connect \$57 $eq$libresoc.v:50760$3363_Y + connect \$5 $and$libresoc.v:50761$3364_Y + connect \$59 $not$libresoc.v:50762$3365_Y + connect \$61 $and$libresoc.v:50763$3366_Y + connect \$63 $not$libresoc.v:50764$3367_Y + connect \$65 $and$libresoc.v:50765$3368_Y + connect \$67 $eq$libresoc.v:50766$3369_Y + connect \$69 $eq$libresoc.v:50767$3370_Y + connect \$71 $eq$libresoc.v:50768$3371_Y + connect \$73 $not$libresoc.v:50769$3372_Y + connect \$75 $and$libresoc.v:50770$3373_Y + connect \$77 $not$libresoc.v:50771$3374_Y + connect \$7 $not$libresoc.v:50772$3375_Y + connect \$79 $and$libresoc.v:50773$3376_Y + connect \$81 $eq$libresoc.v:50774$3377_Y + connect \$83 $eq$libresoc.v:50775$3378_Y + connect \$85 $eq$libresoc.v:50776$3379_Y + connect \$87 $not$libresoc.v:50777$3380_Y + connect \$89 $and$libresoc.v:50778$3381_Y + connect \$91 $not$libresoc.v:50779$3382_Y + connect \$93 $and$libresoc.v:50780$3383_Y + connect \$95 $eq$libresoc.v:50781$3384_Y + connect \$97 $eq$libresoc.v:50782$3385_Y connect \$115 \$116 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -90991,138 +92009,138 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:50506.1-52521.10" +attribute \src "libresoc.v:51204.1-53219.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:52089.3-52122.6" + attribute \src "libresoc.v:52787.3-52820.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:52123.3-52156.6" + attribute \src "libresoc.v:52821.3-52854.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:51749.3-51782.6" + attribute \src "libresoc.v:52447.3-52480.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:51851.3-51884.6" + attribute \src "libresoc.v:52549.3-52582.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:51953.3-51986.6" + attribute \src "libresoc.v:52651.3-52684.6" wire width 12 $0\ALU_function_unit[11:0] - attribute \src "libresoc.v:52021.3-52054.6" + attribute \src "libresoc.v:52719.3-52752.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52055.3-52088.6" + attribute \src "libresoc.v:52753.3-52786.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:51987.3-52020.6" + attribute \src "libresoc.v:52685.3-52718.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:51783.3-51816.6" + attribute \src "libresoc.v:52481.3-52514.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:51817.3-51850.6" + attribute \src "libresoc.v:52515.3-52548.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:51885.3-51918.6" + attribute \src "libresoc.v:52583.3-52616.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:52157.3-52190.6" + attribute \src "libresoc.v:52855.3-52888.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:51715.3-51748.6" + attribute \src "libresoc.v:52413.3-52446.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:51919.3-51952.6" + attribute \src "libresoc.v:52617.3-52650.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:50507.7-50507.20" + attribute \src "libresoc.v:51205.7-51205.20" wire $0\initial[0:0] - attribute \src "libresoc.v:52089.3-52122.6" + attribute \src "libresoc.v:52787.3-52820.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52123.3-52156.6" + attribute \src "libresoc.v:52821.3-52854.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:51749.3-51782.6" + attribute \src "libresoc.v:52447.3-52480.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:51851.3-51884.6" + attribute \src "libresoc.v:52549.3-52582.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:51953.3-51986.6" + attribute \src "libresoc.v:52651.3-52684.6" wire width 12 $1\ALU_function_unit[11:0] - attribute \src "libresoc.v:52021.3-52054.6" + attribute \src "libresoc.v:52719.3-52752.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52055.3-52088.6" + attribute \src "libresoc.v:52753.3-52786.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:51987.3-52020.6" + attribute \src "libresoc.v:52685.3-52718.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:51783.3-51816.6" + attribute \src "libresoc.v:52481.3-52514.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:51817.3-51850.6" + attribute \src "libresoc.v:52515.3-52548.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:51885.3-51918.6" + attribute \src "libresoc.v:52583.3-52616.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52157.3-52190.6" + attribute \src "libresoc.v:52855.3-52888.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:51715.3-51748.6" + attribute \src "libresoc.v:52413.3-52446.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:51919.3-51952.6" + attribute \src "libresoc.v:52617.3-52650.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:51680.17-51680.211" - wire width 32 $ternary$libresoc.v:51680$3447_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:52378.17-52378.211" + wire width 32 $ternary$libresoc.v:52378$3481_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \ALU_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 27 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 32 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 25 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \ALU_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \ALU_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 30 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 28 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \ALU_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \ALU_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 31 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 29 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \ALU_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 22 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \ALU_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 24 \ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 17 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 23 \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 18 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \ALU_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ALU_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91132,7 +92150,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -91140,15 +92158,15 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91158,7 +92176,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec19_ALU_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -91166,15 +92184,15 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec19_ALU_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec19_ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec19_ALU_dec19_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -91189,7 +92207,7 @@ module \dec attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec19_ALU_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -91197,7 +92215,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec19_ALU_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -91214,7 +92232,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec19_ALU_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -91290,13 +92308,13 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec19_ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec19_ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec19_ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec19_ALU_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -91304,17 +92322,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec19_ALU_dec19_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec19_ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec19_ALU_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -91324,7 +92342,7 @@ module \dec attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_ALU_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -91332,15 +92350,15 @@ module \dec attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_ALU_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_ALU_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -91355,7 +92373,7 @@ module \dec attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \ALU_dec31_ALU_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -91363,7 +92381,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \ALU_dec31_ALU_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -91380,7 +92398,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_ALU_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -91456,13 +92474,13 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \ALU_dec31_ALU_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_ALU_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_ALU_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_ALU_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -91470,17 +92488,17 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ALU_dec31_ALU_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \ALU_dec31_ALU_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \ALU_dec31_ALU_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \ALU_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -91495,7 +92513,7 @@ module \dec attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -91503,7 +92521,7 @@ module \dec attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 8 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -91520,7 +92538,7 @@ module \dec attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 9 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -91596,13 +92614,13 @@ module \dec attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -91610,622 +92628,622 @@ module \dec attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:50507.7-50507.15" + attribute \src "libresoc.v:51205.7-51205.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:51680$3447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:52378$3481 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:51680$3447_Y + connect \Y $ternary$libresoc.v:52378$3481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:51681.13-51697.4" + attribute \src "libresoc.v:52379.13-52395.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -92244,7 +93262,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:51698.13-51714.4" + attribute \src "libresoc.v:52396.13-52412.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -92262,26 +93280,26 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:50507.7-50507.20" - process $proc$libresoc.v:50507$3462 + attribute \src "libresoc.v:51205.7-51205.20" + process $proc$libresoc.v:51205$3496 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51715.3-51748.6" - process $proc$libresoc.v:51715$3448 + attribute \src "libresoc.v:52413.3-52446.6" + process $proc$libresoc.v:52413$3482 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:51716.5-51716.29" + attribute \src "libresoc.v:52414.5-52414.29" switch \initial - attribute \src "libresoc.v:51716.9-51716.17" + attribute \src "libresoc.v:52414.9-52414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92325,18 +93343,18 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:51749.3-51782.6" - process $proc$libresoc.v:51749$3449 + attribute \src "libresoc.v:52447.3-52480.6" + process $proc$libresoc.v:52447$3483 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:51750.5-51750.29" + attribute \src "libresoc.v:52448.5-52448.29" switch \initial - attribute \src "libresoc.v:51750.9-51750.17" + attribute \src "libresoc.v:52448.9-52448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92380,18 +93398,18 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:51783.3-51816.6" - process $proc$libresoc.v:51783$3450 + attribute \src "libresoc.v:52481.3-52514.6" + process $proc$libresoc.v:52481$3484 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:51784.5-51784.29" + attribute \src "libresoc.v:52482.5-52482.29" switch \initial - attribute \src "libresoc.v:51784.9-51784.17" + attribute \src "libresoc.v:52482.9-52482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92435,18 +93453,18 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:51817.3-51850.6" - process $proc$libresoc.v:51817$3451 + attribute \src "libresoc.v:52515.3-52548.6" + process $proc$libresoc.v:52515$3485 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:51818.5-51818.29" + attribute \src "libresoc.v:52516.5-52516.29" switch \initial - attribute \src "libresoc.v:51818.9-51818.17" + attribute \src "libresoc.v:52516.9-52516.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92490,18 +93508,18 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:51851.3-51884.6" - process $proc$libresoc.v:51851$3452 + attribute \src "libresoc.v:52549.3-52582.6" + process $proc$libresoc.v:52549$3486 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:51852.5-51852.29" + attribute \src "libresoc.v:52550.5-52550.29" switch \initial - attribute \src "libresoc.v:51852.9-51852.17" + attribute \src "libresoc.v:52550.9-52550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92545,18 +93563,18 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:51885.3-51918.6" - process $proc$libresoc.v:51885$3453 + attribute \src "libresoc.v:52583.3-52616.6" + process $proc$libresoc.v:52583$3487 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:51886.5-51886.29" + attribute \src "libresoc.v:52584.5-52584.29" switch \initial - attribute \src "libresoc.v:51886.9-51886.17" + attribute \src "libresoc.v:52584.9-52584.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92600,18 +93618,18 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:51919.3-51952.6" - process $proc$libresoc.v:51919$3454 + attribute \src "libresoc.v:52617.3-52650.6" + process $proc$libresoc.v:52617$3488 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:51920.5-51920.29" + attribute \src "libresoc.v:52618.5-52618.29" switch \initial - attribute \src "libresoc.v:51920.9-51920.17" + attribute \src "libresoc.v:52618.9-52618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92655,18 +93673,18 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:51953.3-51986.6" - process $proc$libresoc.v:51953$3455 + attribute \src "libresoc.v:52651.3-52684.6" + process $proc$libresoc.v:52651$3489 assign { } { } assign { } { } assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] - attribute \src "libresoc.v:51954.5-51954.29" + attribute \src "libresoc.v:52652.5-52652.29" switch \initial - attribute \src "libresoc.v:51954.9-51954.17" + attribute \src "libresoc.v:52652.9-52652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92710,18 +93728,18 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[11:0] end - attribute \src "libresoc.v:51987.3-52020.6" - process $proc$libresoc.v:51987$3456 + attribute \src "libresoc.v:52685.3-52718.6" + process $proc$libresoc.v:52685$3490 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:51988.5-51988.29" + attribute \src "libresoc.v:52686.5-52686.29" switch \initial - attribute \src "libresoc.v:51988.9-51988.17" + attribute \src "libresoc.v:52686.9-52686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92765,18 +93783,18 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:52021.3-52054.6" - process $proc$libresoc.v:52021$3457 + attribute \src "libresoc.v:52719.3-52752.6" + process $proc$libresoc.v:52719$3491 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52022.5-52022.29" + attribute \src "libresoc.v:52720.5-52720.29" switch \initial - attribute \src "libresoc.v:52022.9-52022.17" + attribute \src "libresoc.v:52720.9-52720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92820,18 +93838,18 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:52055.3-52088.6" - process $proc$libresoc.v:52055$3458 + attribute \src "libresoc.v:52753.3-52786.6" + process $proc$libresoc.v:52753$3492 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52056.5-52056.29" + attribute \src "libresoc.v:52754.5-52754.29" switch \initial - attribute \src "libresoc.v:52056.9-52056.17" + attribute \src "libresoc.v:52754.9-52754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92875,18 +93893,18 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:52089.3-52122.6" - process $proc$libresoc.v:52089$3459 + attribute \src "libresoc.v:52787.3-52820.6" + process $proc$libresoc.v:52787$3493 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52090.5-52090.29" + attribute \src "libresoc.v:52788.5-52788.29" switch \initial - attribute \src "libresoc.v:52090.9-52090.17" + attribute \src "libresoc.v:52788.9-52788.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92930,18 +93948,18 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:52123.3-52156.6" - process $proc$libresoc.v:52123$3460 + attribute \src "libresoc.v:52821.3-52854.6" + process $proc$libresoc.v:52821$3494 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52124.5-52124.29" + attribute \src "libresoc.v:52822.5-52822.29" switch \initial - attribute \src "libresoc.v:52124.9-52124.17" + attribute \src "libresoc.v:52822.9-52822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -92985,18 +94003,18 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:52157.3-52190.6" - process $proc$libresoc.v:52157$3461 + attribute \src "libresoc.v:52855.3-52888.6" + process $proc$libresoc.v:52855$3495 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52158.5-52158.29" + attribute \src "libresoc.v:52856.5-52856.29" switch \initial - attribute \src "libresoc.v:52158.9-52158.17" + attribute \src "libresoc.v:52856.9-52856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -93040,7 +94058,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:51680$3447_Y + connect \$1 $ternary$libresoc.v:52378$3481_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -93372,132 +94390,132 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:52525.1-53955.10" +attribute \src "libresoc.v:53223.1-54653.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" -module \dec$137 - attribute \src "libresoc.v:53586.3-53598.6" +module \dec$140 + attribute \src "libresoc.v:54284.3-54296.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:53599.3-53611.6" + attribute \src "libresoc.v:54297.3-54309.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:53560.3-53572.6" + attribute \src "libresoc.v:54258.3-54270.6" wire width 12 $0\CR_function_unit[11:0] - attribute \src "libresoc.v:53573.3-53585.6" + attribute \src "libresoc.v:54271.3-54283.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:53612.3-53624.6" + attribute \src "libresoc.v:54310.3-54322.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:52526.7-52526.20" + attribute \src "libresoc.v:53224.7-53224.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53586.3-53598.6" + attribute \src "libresoc.v:54284.3-54296.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:53599.3-53611.6" + attribute \src "libresoc.v:54297.3-54309.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:53560.3-53572.6" + attribute \src "libresoc.v:54258.3-54270.6" wire width 12 $1\CR_function_unit[11:0] - attribute \src "libresoc.v:53573.3-53585.6" + attribute \src "libresoc.v:54271.3-54283.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:53612.3-53624.6" + attribute \src "libresoc.v:54310.3-54322.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:53543.17-53543.211" - wire width 32 $ternary$libresoc.v:53543$3463_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:54241.17-54241.211" + wire width 32 $ternary$libresoc.v:54241$3497_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \CR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 11 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 10 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 15 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \CR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \CR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \CR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 14 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 12 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \CR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \CR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \CR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 13 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \CR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \CR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \CR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 9 \CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 8 \CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \CR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \CR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \CR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \CR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -93507,7 +94525,7 @@ module \dec$137 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -93515,7 +94533,7 @@ module \dec$137 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \CR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -93525,7 +94543,7 @@ module \dec$137 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec19_CR_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -93533,7 +94551,7 @@ module \dec$137 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec19_CR_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -93548,7 +94566,7 @@ module \dec$137 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec19_CR_dec19_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -93624,15 +94642,15 @@ module \dec$137 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec19_CR_dec19_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec19_CR_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec19_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -93642,7 +94660,7 @@ module \dec$137 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_CR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -93650,7 +94668,7 @@ module \dec$137 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \CR_dec31_CR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -93665,7 +94683,7 @@ module \dec$137 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \CR_dec31_CR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -93741,15 +94759,15 @@ module \dec$137 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \CR_dec31_CR_dec31_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \CR_dec31_CR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \CR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -93764,7 +94782,7 @@ module \dec$137 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -93840,590 +94858,590 @@ module \dec$137 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \CR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 18 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 16 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:52526.7-52526.15" + attribute \src "libresoc.v:53224.7-53224.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:53543$3463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:54241$3497 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:53543$3463_Y + connect \Y $ternary$libresoc.v:54241$3497_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:53544.12-53551.4" + attribute \src "libresoc.v:54242.12-54249.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -94433,7 +95451,7 @@ module \dec$137 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:53552.12-53559.4" + attribute \src "libresoc.v:54250.12-54257.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -94442,26 +95460,26 @@ module \dec$137 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:52526.7-52526.20" - process $proc$libresoc.v:52526$3469 + attribute \src "libresoc.v:53224.7-53224.20" + process $proc$libresoc.v:53224$3503 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:53560.3-53572.6" - process $proc$libresoc.v:53560$3464 + attribute \src "libresoc.v:54258.3-54270.6" + process $proc$libresoc.v:54258$3498 assign { } { } assign { } { } assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] - attribute \src "libresoc.v:53561.5-53561.29" + attribute \src "libresoc.v:54259.5-54259.29" switch \initial - attribute \src "libresoc.v:53561.9-53561.17" + attribute \src "libresoc.v:54259.9-54259.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94477,18 +95495,18 @@ module \dec$137 sync always update \CR_function_unit $0\CR_function_unit[11:0] end - attribute \src "libresoc.v:53573.3-53585.6" - process $proc$libresoc.v:53573$3465 + attribute \src "libresoc.v:54271.3-54283.6" + process $proc$libresoc.v:54271$3499 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:53574.5-53574.29" + attribute \src "libresoc.v:54272.5-54272.29" switch \initial - attribute \src "libresoc.v:53574.9-53574.17" + attribute \src "libresoc.v:54272.9-54272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94504,18 +95522,18 @@ module \dec$137 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:53586.3-53598.6" - process $proc$libresoc.v:53586$3466 + attribute \src "libresoc.v:54284.3-54296.6" + process $proc$libresoc.v:54284$3500 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:53587.5-53587.29" + attribute \src "libresoc.v:54285.5-54285.29" switch \initial - attribute \src "libresoc.v:53587.9-53587.17" + attribute \src "libresoc.v:54285.9-54285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94531,18 +95549,18 @@ module \dec$137 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:53599.3-53611.6" - process $proc$libresoc.v:53599$3467 + attribute \src "libresoc.v:54297.3-54309.6" + process $proc$libresoc.v:54297$3501 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:53600.5-53600.29" + attribute \src "libresoc.v:54298.5-54298.29" switch \initial - attribute \src "libresoc.v:53600.9-53600.17" + attribute \src "libresoc.v:54298.9-54298.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94558,18 +95576,18 @@ module \dec$137 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:53612.3-53624.6" - process $proc$libresoc.v:53612$3468 + attribute \src "libresoc.v:54310.3-54322.6" + process $proc$libresoc.v:54310$3502 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:53613.5-53613.29" + attribute \src "libresoc.v:54311.5-54311.29" switch \initial - attribute \src "libresoc.v:53613.9-53613.17" + attribute \src "libresoc.v:54311.9-54311.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -94585,7 +95603,7 @@ module \dec$137 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:53543$3463_Y + connect \$1 $ternary$libresoc.v:54241$3497_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94917,134 +95935,134 @@ module \dec$137 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53959.1-55374.10" +attribute \src "libresoc.v:54657.1-56072.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" -module \dec$144 - attribute \src "libresoc.v:54965.3-54980.6" +module \dec$147 + attribute \src "libresoc.v:55663.3-55678.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:54981.3-54996.6" + attribute \src "libresoc.v:55679.3-55694.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:54917.3-54932.6" + attribute \src "libresoc.v:55615.3-55630.6" wire width 12 $0\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:54949.3-54964.6" + attribute \src "libresoc.v:55647.3-55662.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:54933.3-54948.6" + attribute \src "libresoc.v:55631.3-55646.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55013.3-55028.6" + attribute \src "libresoc.v:55711.3-55726.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55029.3-55044.6" + attribute \src "libresoc.v:55727.3-55742.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:54997.3-55012.6" + attribute \src "libresoc.v:55695.3-55710.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:53960.7-53960.20" + attribute \src "libresoc.v:54658.7-54658.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54965.3-54980.6" + attribute \src "libresoc.v:55663.3-55678.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:54981.3-54996.6" + attribute \src "libresoc.v:55679.3-55694.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:54917.3-54932.6" + attribute \src "libresoc.v:55615.3-55630.6" wire width 12 $1\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:54949.3-54964.6" + attribute \src "libresoc.v:55647.3-55662.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:54933.3-54948.6" + attribute \src "libresoc.v:55631.3-55646.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55013.3-55028.6" + attribute \src "libresoc.v:55711.3-55726.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55029.3-55044.6" + attribute \src "libresoc.v:55727.3-55742.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:54997.3-55012.6" + attribute \src "libresoc.v:55695.3-55710.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:54905.17-54905.211" - wire width 32 $ternary$libresoc.v:54905$3470_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:55603.17-55603.211" + wire width 32 $ternary$libresoc.v:55603$3504_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \BRANCH_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 21 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 19 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \BRANCH_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \BRANCH_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 24 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 22 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \BRANCH_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \BRANCH_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 25 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 23 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \BRANCH_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 16 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 11 \BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 18 \BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 17 \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 14 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 12 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \BRANCH_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \BRANCH_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -95054,7 +96072,7 @@ module \dec$144 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -95062,7 +96080,7 @@ module \dec$144 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -95072,7 +96090,7 @@ module \dec$144 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -95080,7 +96098,7 @@ module \dec$144 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -95095,7 +96113,7 @@ module \dec$144 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \BRANCH_dec19_BRANCH_dec19_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -95112,7 +96130,7 @@ module \dec$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -95188,19 +96206,19 @@ module \dec$144 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \BRANCH_dec19_BRANCH_dec19_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \BRANCH_dec19_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -95215,7 +96233,7 @@ module \dec$144 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -95232,7 +96250,7 @@ module \dec$144 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 8 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -95308,604 +96326,604 @@ module \dec$144 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 9 \BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 15 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 29 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 27 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 28 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:53960.7-53960.15" + attribute \src "libresoc.v:54658.7-54658.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 30 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:54905$3470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:55603$3504 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54905$3470_Y + connect \Y $ternary$libresoc.v:55603$3504_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54906.16-54916.4" + attribute \src "libresoc.v:55604.16-55614.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -95917,26 +96935,26 @@ module \dec$144 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:53960.7-53960.20" - process $proc$libresoc.v:53960$3479 + attribute \src "libresoc.v:54658.7-54658.20" + process $proc$libresoc.v:54658$3513 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54917.3-54932.6" - process $proc$libresoc.v:54917$3471 + attribute \src "libresoc.v:55615.3-55630.6" + process $proc$libresoc.v:55615$3505 assign { } { } assign { } { } assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:54918.5-54918.29" + attribute \src "libresoc.v:55616.5-55616.29" switch \initial - attribute \src "libresoc.v:54918.9-54918.17" + attribute \src "libresoc.v:55616.9-55616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95956,18 +96974,18 @@ module \dec$144 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] end - attribute \src "libresoc.v:54933.3-54948.6" - process $proc$libresoc.v:54933$3472 + attribute \src "libresoc.v:55631.3-55646.6" + process $proc$libresoc.v:55631$3506 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:54934.5-54934.29" + attribute \src "libresoc.v:55632.5-55632.29" switch \initial - attribute \src "libresoc.v:54934.9-54934.17" + attribute \src "libresoc.v:55632.9-55632.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -95987,18 +97005,18 @@ module \dec$144 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:54949.3-54964.6" - process $proc$libresoc.v:54949$3473 + attribute \src "libresoc.v:55647.3-55662.6" + process $proc$libresoc.v:55647$3507 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:54950.5-54950.29" + attribute \src "libresoc.v:55648.5-55648.29" switch \initial - attribute \src "libresoc.v:54950.9-54950.17" + attribute \src "libresoc.v:55648.9-55648.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96018,18 +97036,18 @@ module \dec$144 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:54965.3-54980.6" - process $proc$libresoc.v:54965$3474 + attribute \src "libresoc.v:55663.3-55678.6" + process $proc$libresoc.v:55663$3508 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:54966.5-54966.29" + attribute \src "libresoc.v:55664.5-55664.29" switch \initial - attribute \src "libresoc.v:54966.9-54966.17" + attribute \src "libresoc.v:55664.9-55664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96049,18 +97067,18 @@ module \dec$144 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:54981.3-54996.6" - process $proc$libresoc.v:54981$3475 + attribute \src "libresoc.v:55679.3-55694.6" + process $proc$libresoc.v:55679$3509 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:54982.5-54982.29" + attribute \src "libresoc.v:55680.5-55680.29" switch \initial - attribute \src "libresoc.v:54982.9-54982.17" + attribute \src "libresoc.v:55680.9-55680.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96080,18 +97098,18 @@ module \dec$144 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:54997.3-55012.6" - process $proc$libresoc.v:54997$3476 + attribute \src "libresoc.v:55695.3-55710.6" + process $proc$libresoc.v:55695$3510 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:54998.5-54998.29" + attribute \src "libresoc.v:55696.5-55696.29" switch \initial - attribute \src "libresoc.v:54998.9-54998.17" + attribute \src "libresoc.v:55696.9-55696.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96111,18 +97129,18 @@ module \dec$144 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:55013.3-55028.6" - process $proc$libresoc.v:55013$3477 + attribute \src "libresoc.v:55711.3-55726.6" + process $proc$libresoc.v:55711$3511 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55014.5-55014.29" + attribute \src "libresoc.v:55712.5-55712.29" switch \initial - attribute \src "libresoc.v:55014.9-55014.17" + attribute \src "libresoc.v:55712.9-55712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96142,18 +97160,18 @@ module \dec$144 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:55029.3-55044.6" - process $proc$libresoc.v:55029$3478 + attribute \src "libresoc.v:55727.3-55742.6" + process $proc$libresoc.v:55727$3512 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55030.5-55030.29" + attribute \src "libresoc.v:55728.5-55728.29" switch \initial - attribute \src "libresoc.v:55030.9-55030.17" + attribute \src "libresoc.v:55728.9-55728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -96173,7 +97191,7 @@ module \dec$144 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:54905$3470_Y + connect \$1 $ternary$libresoc.v:55603$3504_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96504,258 +97522,258 @@ module \dec$144 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55378.1-57125.10" +attribute \src "libresoc.v:56076.1-57823.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" -module \dec$152 - attribute \src "libresoc.v:56684.3-56711.6" +module \dec$155 + attribute \src "libresoc.v:57382.3-57409.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:56712.3-56739.6" + attribute \src "libresoc.v:57410.3-57437.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:56404.3-56431.6" + attribute \src "libresoc.v:57102.3-57129.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56488.3-56515.6" + attribute \src "libresoc.v:57186.3-57213.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:56572.3-56599.6" + attribute \src "libresoc.v:57270.3-57297.6" wire width 12 $0\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:56628.3-56655.6" + attribute \src "libresoc.v:57326.3-57353.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:56656.3-56683.6" + attribute \src "libresoc.v:57354.3-57381.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:56600.3-56627.6" + attribute \src "libresoc.v:57298.3-57325.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:56432.3-56459.6" + attribute \src "libresoc.v:57130.3-57157.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56460.3-56487.6" + attribute \src "libresoc.v:57158.3-57185.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:56516.3-56543.6" + attribute \src "libresoc.v:57214.3-57241.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:56740.3-56767.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:56768.3-56795.6" + attribute \src "libresoc.v:57466.3-57493.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:56544.3-56571.6" + attribute \src "libresoc.v:57242.3-57269.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:55379.7-55379.20" + attribute \src "libresoc.v:56077.7-56077.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56684.3-56711.6" + attribute \src "libresoc.v:57382.3-57409.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:56712.3-56739.6" + attribute \src "libresoc.v:57410.3-57437.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:56404.3-56431.6" + attribute \src "libresoc.v:57102.3-57129.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56488.3-56515.6" + attribute \src "libresoc.v:57186.3-57213.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:56572.3-56599.6" + attribute \src "libresoc.v:57270.3-57297.6" wire width 12 $1\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:56628.3-56655.6" + attribute \src "libresoc.v:57326.3-57353.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:56656.3-56683.6" + attribute \src "libresoc.v:57354.3-57381.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:56600.3-56627.6" + attribute \src "libresoc.v:57298.3-57325.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:56432.3-56459.6" + attribute \src "libresoc.v:57130.3-57157.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56460.3-56487.6" + attribute \src "libresoc.v:57158.3-57185.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:56516.3-56543.6" + attribute \src "libresoc.v:57214.3-57241.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:56740.3-56767.6" + attribute \src "libresoc.v:57438.3-57465.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:56768.3-56795.6" + attribute \src "libresoc.v:57466.3-57493.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:56544.3-56571.6" + attribute \src "libresoc.v:57242.3-57269.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56386.17-56386.211" - wire width 32 $ternary$libresoc.v:56386$3480_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:57084.17-57084.211" + wire width 32 $ternary$libresoc.v:57084$3514_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LOGICAL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 27 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 32 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 25 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \LOGICAL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \LOGICAL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 30 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 28 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \LOGICAL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \LOGICAL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 31 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 29 \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LOGICAL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 22 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LOGICAL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 24 \LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 17 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 23 \LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 18 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \LOGICAL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LOGICAL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96765,7 +97783,7 @@ module \dec$152 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96773,15 +97791,15 @@ module \dec$152 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -96791,7 +97809,7 @@ module \dec$152 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -96799,15 +97817,15 @@ module \dec$152 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_LOGICAL_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -96822,7 +97840,7 @@ module \dec$152 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LOGICAL_dec31_LOGICAL_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -96830,7 +97848,7 @@ module \dec$152 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96847,7 +97865,7 @@ module \dec$152 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -96923,13 +97941,13 @@ module \dec$152 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_LOGICAL_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -96937,17 +97955,17 @@ module \dec$152 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LOGICAL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -96962,7 +97980,7 @@ module \dec$152 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -96970,7 +97988,7 @@ module \dec$152 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 8 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -96987,7 +98005,7 @@ module \dec$152 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 9 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -97063,13 +98081,13 @@ module \dec$152 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -97077,502 +98095,502 @@ module \dec$152 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 21 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:55379.7-55379.15" + attribute \src "libresoc.v:56077.7-56077.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:56386$3480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:57084$3514 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56386$3480_Y + connect \Y $ternary$libresoc.v:57084$3514_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56387.17-56403.4" + attribute \src "libresoc.v:57085.17-57101.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -97590,26 +98608,26 @@ module \dec$152 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:55379.7-55379.20" - process $proc$libresoc.v:55379$3495 + attribute \src "libresoc.v:56077.7-56077.20" + process $proc$libresoc.v:56077$3529 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56404.3-56431.6" - process $proc$libresoc.v:56404$3481 + attribute \src "libresoc.v:57102.3-57129.6" + process $proc$libresoc.v:57102$3515 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:56405.5-56405.29" + attribute \src "libresoc.v:57103.5-57103.29" switch \initial - attribute \src "libresoc.v:56405.9-56405.17" + attribute \src "libresoc.v:57103.9-57103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97645,18 +98663,18 @@ module \dec$152 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:56432.3-56459.6" - process $proc$libresoc.v:56432$3482 + attribute \src "libresoc.v:57130.3-57157.6" + process $proc$libresoc.v:57130$3516 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:56433.5-56433.29" + attribute \src "libresoc.v:57131.5-57131.29" switch \initial - attribute \src "libresoc.v:56433.9-56433.17" + attribute \src "libresoc.v:57131.9-57131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97692,18 +98710,18 @@ module \dec$152 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:56460.3-56487.6" - process $proc$libresoc.v:56460$3483 + attribute \src "libresoc.v:57158.3-57185.6" + process $proc$libresoc.v:57158$3517 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:56461.5-56461.29" + attribute \src "libresoc.v:57159.5-57159.29" switch \initial - attribute \src "libresoc.v:56461.9-56461.17" + attribute \src "libresoc.v:57159.9-57159.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97739,18 +98757,18 @@ module \dec$152 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:56488.3-56515.6" - process $proc$libresoc.v:56488$3484 + attribute \src "libresoc.v:57186.3-57213.6" + process $proc$libresoc.v:57186$3518 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:56489.5-56489.29" + attribute \src "libresoc.v:57187.5-57187.29" switch \initial - attribute \src "libresoc.v:56489.9-56489.17" + attribute \src "libresoc.v:57187.9-57187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97786,18 +98804,18 @@ module \dec$152 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:56516.3-56543.6" - process $proc$libresoc.v:56516$3485 + attribute \src "libresoc.v:57214.3-57241.6" + process $proc$libresoc.v:57214$3519 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:56517.5-56517.29" + attribute \src "libresoc.v:57215.5-57215.29" switch \initial - attribute \src "libresoc.v:56517.9-56517.17" + attribute \src "libresoc.v:57215.9-57215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97833,18 +98851,18 @@ module \dec$152 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:56544.3-56571.6" - process $proc$libresoc.v:56544$3486 + attribute \src "libresoc.v:57242.3-57269.6" + process $proc$libresoc.v:57242$3520 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56545.5-56545.29" + attribute \src "libresoc.v:57243.5-57243.29" switch \initial - attribute \src "libresoc.v:56545.9-56545.17" + attribute \src "libresoc.v:57243.9-57243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97880,18 +98898,18 @@ module \dec$152 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:56572.3-56599.6" - process $proc$libresoc.v:56572$3487 + attribute \src "libresoc.v:57270.3-57297.6" + process $proc$libresoc.v:57270$3521 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:56573.5-56573.29" + attribute \src "libresoc.v:57271.5-57271.29" switch \initial - attribute \src "libresoc.v:56573.9-56573.17" + attribute \src "libresoc.v:57271.9-57271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97927,18 +98945,18 @@ module \dec$152 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] end - attribute \src "libresoc.v:56600.3-56627.6" - process $proc$libresoc.v:56600$3488 + attribute \src "libresoc.v:57298.3-57325.6" + process $proc$libresoc.v:57298$3522 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:56601.5-56601.29" + attribute \src "libresoc.v:57299.5-57299.29" switch \initial - attribute \src "libresoc.v:56601.9-56601.17" + attribute \src "libresoc.v:57299.9-57299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -97974,18 +98992,18 @@ module \dec$152 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:56628.3-56655.6" - process $proc$libresoc.v:56628$3489 + attribute \src "libresoc.v:57326.3-57353.6" + process $proc$libresoc.v:57326$3523 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:56629.5-56629.29" + attribute \src "libresoc.v:57327.5-57327.29" switch \initial - attribute \src "libresoc.v:56629.9-56629.17" + attribute \src "libresoc.v:57327.9-57327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98021,18 +99039,18 @@ module \dec$152 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:56656.3-56683.6" - process $proc$libresoc.v:56656$3490 + attribute \src "libresoc.v:57354.3-57381.6" + process $proc$libresoc.v:57354$3524 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:56657.5-56657.29" + attribute \src "libresoc.v:57355.5-57355.29" switch \initial - attribute \src "libresoc.v:56657.9-56657.17" + attribute \src "libresoc.v:57355.9-57355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98068,18 +99086,18 @@ module \dec$152 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:56684.3-56711.6" - process $proc$libresoc.v:56684$3491 + attribute \src "libresoc.v:57382.3-57409.6" + process $proc$libresoc.v:57382$3525 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:56685.5-56685.29" + attribute \src "libresoc.v:57383.5-57383.29" switch \initial - attribute \src "libresoc.v:56685.9-56685.17" + attribute \src "libresoc.v:57383.9-57383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98115,18 +99133,18 @@ module \dec$152 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:56712.3-56739.6" - process $proc$libresoc.v:56712$3492 + attribute \src "libresoc.v:57410.3-57437.6" + process $proc$libresoc.v:57410$3526 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:56713.5-56713.29" + attribute \src "libresoc.v:57411.5-57411.29" switch \initial - attribute \src "libresoc.v:56713.9-56713.17" + attribute \src "libresoc.v:57411.9-57411.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98162,18 +99180,18 @@ module \dec$152 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:56740.3-56767.6" - process $proc$libresoc.v:56740$3493 + attribute \src "libresoc.v:57438.3-57465.6" + process $proc$libresoc.v:57438$3527 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:56741.5-56741.29" + attribute \src "libresoc.v:57439.5-57439.29" switch \initial - attribute \src "libresoc.v:56741.9-56741.17" + attribute \src "libresoc.v:57439.9-57439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98209,18 +99227,18 @@ module \dec$152 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:56768.3-56795.6" - process $proc$libresoc.v:56768$3494 + attribute \src "libresoc.v:57466.3-57493.6" + process $proc$libresoc.v:57466$3528 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:56769.5-56769.29" + attribute \src "libresoc.v:57467.5-57467.29" switch \initial - attribute \src "libresoc.v:56769.9-56769.17" + attribute \src "libresoc.v:57467.9-57467.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -98256,7 +99274,7 @@ module \dec$152 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:56386$3480_Y + connect \$1 $ternary$libresoc.v:57084$3514_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -98587,282 +99605,282 @@ module \dec$152 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:57129.1-58434.10" +attribute \src "libresoc.v:57827.1-59132.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" -module \dec$161 - attribute \src "libresoc.v:58065.3-58074.6" +module \dec$164 + attribute \src "libresoc.v:58763.3-58772.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:58075.3-58084.6" + attribute \src "libresoc.v:58773.3-58782.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:58045.3-58054.6" + attribute \src "libresoc.v:58743.3-58752.6" wire width 12 $0\SPR_function_unit[11:0] - attribute \src "libresoc.v:58055.3-58064.6" + attribute \src "libresoc.v:58753.3-58762.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:58095.3-58104.6" + attribute \src "libresoc.v:58793.3-58802.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:58085.3-58094.6" + attribute \src "libresoc.v:58783.3-58792.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:57130.7-57130.20" + attribute \src "libresoc.v:57828.7-57828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:58065.3-58074.6" + attribute \src "libresoc.v:58763.3-58772.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58075.3-58084.6" + attribute \src "libresoc.v:58773.3-58782.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58045.3-58054.6" + attribute \src "libresoc.v:58743.3-58752.6" wire width 12 $1\SPR_function_unit[11:0] - attribute \src "libresoc.v:58055.3-58064.6" + attribute \src "libresoc.v:58753.3-58762.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:58095.3-58104.6" + attribute \src "libresoc.v:58793.3-58802.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:58085.3-58094.6" + attribute \src "libresoc.v:58783.3-58792.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58035.17-58035.211" - wire width 32 $ternary$libresoc.v:58035$3496_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:58733.17-58733.211" + wire width 32 $ternary$libresoc.v:58733$3530_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SPR_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 12 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 11 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 16 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \SPR_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \SPR_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \SPR_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 15 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 13 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \SPR_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \SPR_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \SPR_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 14 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SPR_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \SPR_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SPR_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 10 \SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 9 \SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \SPR_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \SPR_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SPR_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \SPR_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98872,7 +99890,7 @@ module \dec$161 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98880,7 +99898,7 @@ module \dec$161 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -98890,7 +99908,7 @@ module \dec$161 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SPR_dec31_SPR_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -98898,7 +99916,7 @@ module \dec$161 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SPR_dec31_SPR_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -98913,7 +99931,7 @@ module \dec$161 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SPR_dec31_SPR_dec31_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -98989,17 +100007,17 @@ module \dec$161 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SPR_dec31_SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SPR_dec31_SPR_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SPR_dec31_SPR_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SPR_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -99014,7 +100032,7 @@ module \dec$161 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -99090,446 +100108,446 @@ module \dec$161 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \SPR_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 19 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 17 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 18 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:57130.7-57130.15" + attribute \src "libresoc.v:57828.7-57828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:58035$3496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:58733$3530 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:58035$3496_Y + connect \Y $ternary$libresoc.v:58733$3530_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:58036.13-58044.4" + attribute \src "libresoc.v:58734.13-58742.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -99539,26 +100557,26 @@ module \dec$161 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:57130.7-57130.20" - process $proc$libresoc.v:57130$3503 + attribute \src "libresoc.v:57828.7-57828.20" + process $proc$libresoc.v:57828$3537 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:58045.3-58054.6" - process $proc$libresoc.v:58045$3497 + attribute \src "libresoc.v:58743.3-58752.6" + process $proc$libresoc.v:58743$3531 assign { } { } assign { } { } assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] - attribute \src "libresoc.v:58046.5-58046.29" + attribute \src "libresoc.v:58744.5-58744.29" switch \initial - attribute \src "libresoc.v:58046.9-58046.17" + attribute \src "libresoc.v:58744.9-58744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99570,18 +100588,18 @@ module \dec$161 sync always update \SPR_function_unit $0\SPR_function_unit[11:0] end - attribute \src "libresoc.v:58055.3-58064.6" - process $proc$libresoc.v:58055$3498 + attribute \src "libresoc.v:58753.3-58762.6" + process $proc$libresoc.v:58753$3532 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:58056.5-58056.29" + attribute \src "libresoc.v:58754.5-58754.29" switch \initial - attribute \src "libresoc.v:58056.9-58056.17" + attribute \src "libresoc.v:58754.9-58754.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99593,18 +100611,18 @@ module \dec$161 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:58065.3-58074.6" - process $proc$libresoc.v:58065$3499 + attribute \src "libresoc.v:58763.3-58772.6" + process $proc$libresoc.v:58763$3533 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58066.5-58066.29" + attribute \src "libresoc.v:58764.5-58764.29" switch \initial - attribute \src "libresoc.v:58066.9-58066.17" + attribute \src "libresoc.v:58764.9-58764.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99616,18 +100634,18 @@ module \dec$161 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:58075.3-58084.6" - process $proc$libresoc.v:58075$3500 + attribute \src "libresoc.v:58773.3-58782.6" + process $proc$libresoc.v:58773$3534 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58076.5-58076.29" + attribute \src "libresoc.v:58774.5-58774.29" switch \initial - attribute \src "libresoc.v:58076.9-58076.17" + attribute \src "libresoc.v:58774.9-58774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99639,18 +100657,18 @@ module \dec$161 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:58085.3-58094.6" - process $proc$libresoc.v:58085$3501 + attribute \src "libresoc.v:58783.3-58792.6" + process $proc$libresoc.v:58783$3535 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58086.5-58086.29" + attribute \src "libresoc.v:58784.5-58784.29" switch \initial - attribute \src "libresoc.v:58086.9-58086.17" + attribute \src "libresoc.v:58784.9-58784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99662,18 +100680,18 @@ module \dec$161 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:58095.3-58104.6" - process $proc$libresoc.v:58095$3502 + attribute \src "libresoc.v:58793.3-58802.6" + process $proc$libresoc.v:58793$3536 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:58096.5-58096.29" + attribute \src "libresoc.v:58794.5-58794.29" switch \initial - attribute \src "libresoc.v:58096.9-58096.17" + attribute \src "libresoc.v:58794.9-58794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -99685,7 +100703,7 @@ module \dec$161 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:58035$3496_Y + connect \$1 $ternary$libresoc.v:58733$3530_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100016,168 +101034,168 @@ module \dec$161 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58438.1-59933.10" +attribute \src "libresoc.v:59136.1-60631.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" -module \dec$168 - attribute \src "libresoc.v:59564.3-59573.6" +module \dec$171 + attribute \src "libresoc.v:60262.3-60271.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:59574.3-59583.6" + attribute \src "libresoc.v:60272.3-60281.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:59464.3-59473.6" + attribute \src "libresoc.v:60162.3-60171.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:59494.3-59503.6" + attribute \src "libresoc.v:60192.3-60201.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:59524.3-59533.6" + attribute \src "libresoc.v:60222.3-60231.6" wire width 12 $0\DIV_function_unit[11:0] - attribute \src "libresoc.v:59544.3-59553.6" + attribute \src "libresoc.v:60242.3-60251.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:59554.3-59563.6" + attribute \src "libresoc.v:60252.3-60261.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:59534.3-59543.6" + attribute \src "libresoc.v:60232.3-60241.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:59474.3-59483.6" + attribute \src "libresoc.v:60172.3-60181.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:59484.3-59493.6" + attribute \src "libresoc.v:60182.3-60191.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:59504.3-59513.6" + attribute \src "libresoc.v:60202.3-60211.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:59584.3-59593.6" + attribute \src "libresoc.v:60282.3-60291.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:59594.3-59603.6" + attribute \src "libresoc.v:60292.3-60301.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:59514.3-59523.6" + attribute \src "libresoc.v:60212.3-60221.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:58439.7-58439.20" + attribute \src "libresoc.v:59137.7-59137.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59564.3-59573.6" + attribute \src "libresoc.v:60262.3-60271.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:59574.3-59583.6" + attribute \src "libresoc.v:60272.3-60281.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:59464.3-59473.6" + attribute \src "libresoc.v:60162.3-60171.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:59494.3-59503.6" + attribute \src "libresoc.v:60192.3-60201.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:59524.3-59533.6" + attribute \src "libresoc.v:60222.3-60231.6" wire width 12 $1\DIV_function_unit[11:0] - attribute \src "libresoc.v:59544.3-59553.6" + attribute \src "libresoc.v:60242.3-60251.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:59554.3-59563.6" + attribute \src "libresoc.v:60252.3-60261.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:59534.3-59543.6" + attribute \src "libresoc.v:60232.3-60241.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:59474.3-59483.6" + attribute \src "libresoc.v:60172.3-60181.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:59484.3-59493.6" + attribute \src "libresoc.v:60182.3-60191.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:59504.3-59513.6" + attribute \src "libresoc.v:60202.3-60211.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:59584.3-59593.6" + attribute \src "libresoc.v:60282.3-60291.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:59594.3-59603.6" + attribute \src "libresoc.v:60292.3-60301.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:59514.3-59523.6" + attribute \src "libresoc.v:60212.3-60221.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:59446.17-59446.211" - wire width 32 $ternary$libresoc.v:59446$3504_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:60144.17-60144.211" + wire width 32 $ternary$libresoc.v:60144$3538_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \DIV_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 27 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 32 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 30 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 28 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 31 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 29 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100187,7 +101205,7 @@ module \dec$168 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100195,15 +101213,15 @@ module \dec$168 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -100213,7 +101231,7 @@ module \dec$168 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_DIV_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -100221,15 +101239,15 @@ module \dec$168 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_DIV_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_DIV_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -100244,7 +101262,7 @@ module \dec$168 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \DIV_dec31_DIV_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -100252,7 +101270,7 @@ module \dec$168 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \DIV_dec31_DIV_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -100269,7 +101287,7 @@ module \dec$168 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_DIV_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100345,13 +101363,13 @@ module \dec$168 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_DIV_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -100359,17 +101377,17 @@ module \dec$168 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \DIV_dec31_DIV_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \DIV_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -100384,7 +101402,7 @@ module \dec$168 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -100392,7 +101410,7 @@ module \dec$168 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 8 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -100409,7 +101427,7 @@ module \dec$168 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 9 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -100485,13 +101503,13 @@ module \dec$168 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -100499,592 +101517,592 @@ module \dec$168 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:58439.7-58439.15" + attribute \src "libresoc.v:59137.7-59137.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:59446$3504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:60144$3538 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59446$3504_Y + connect \Y $ternary$libresoc.v:60144$3538_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59447.13-59463.4" + attribute \src "libresoc.v:60145.13-60161.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -101102,26 +102120,26 @@ module \dec$168 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:58439.7-58439.20" - process $proc$libresoc.v:58439$3519 + attribute \src "libresoc.v:59137.7-59137.20" + process $proc$libresoc.v:59137$3553 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59464.3-59473.6" - process $proc$libresoc.v:59464$3505 + attribute \src "libresoc.v:60162.3-60171.6" + process $proc$libresoc.v:60162$3539 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:59465.5-59465.29" + attribute \src "libresoc.v:60163.5-60163.29" switch \initial - attribute \src "libresoc.v:59465.9-59465.17" + attribute \src "libresoc.v:60163.9-60163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101133,18 +102151,18 @@ module \dec$168 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:59474.3-59483.6" - process $proc$libresoc.v:59474$3506 + attribute \src "libresoc.v:60172.3-60181.6" + process $proc$libresoc.v:60172$3540 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:59475.5-59475.29" + attribute \src "libresoc.v:60173.5-60173.29" switch \initial - attribute \src "libresoc.v:59475.9-59475.17" + attribute \src "libresoc.v:60173.9-60173.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101156,18 +102174,18 @@ module \dec$168 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:59484.3-59493.6" - process $proc$libresoc.v:59484$3507 + attribute \src "libresoc.v:60182.3-60191.6" + process $proc$libresoc.v:60182$3541 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:59485.5-59485.29" + attribute \src "libresoc.v:60183.5-60183.29" switch \initial - attribute \src "libresoc.v:59485.9-59485.17" + attribute \src "libresoc.v:60183.9-60183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101179,18 +102197,18 @@ module \dec$168 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:59494.3-59503.6" - process $proc$libresoc.v:59494$3508 + attribute \src "libresoc.v:60192.3-60201.6" + process $proc$libresoc.v:60192$3542 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:59495.5-59495.29" + attribute \src "libresoc.v:60193.5-60193.29" switch \initial - attribute \src "libresoc.v:59495.9-59495.17" + attribute \src "libresoc.v:60193.9-60193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101202,18 +102220,18 @@ module \dec$168 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:59504.3-59513.6" - process $proc$libresoc.v:59504$3509 + attribute \src "libresoc.v:60202.3-60211.6" + process $proc$libresoc.v:60202$3543 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:59505.5-59505.29" + attribute \src "libresoc.v:60203.5-60203.29" switch \initial - attribute \src "libresoc.v:59505.9-59505.17" + attribute \src "libresoc.v:60203.9-60203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101225,18 +102243,18 @@ module \dec$168 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:59514.3-59523.6" - process $proc$libresoc.v:59514$3510 + attribute \src "libresoc.v:60212.3-60221.6" + process $proc$libresoc.v:60212$3544 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:59515.5-59515.29" + attribute \src "libresoc.v:60213.5-60213.29" switch \initial - attribute \src "libresoc.v:59515.9-59515.17" + attribute \src "libresoc.v:60213.9-60213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101248,18 +102266,18 @@ module \dec$168 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:59524.3-59533.6" - process $proc$libresoc.v:59524$3511 + attribute \src "libresoc.v:60222.3-60231.6" + process $proc$libresoc.v:60222$3545 assign { } { } assign { } { } assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] - attribute \src "libresoc.v:59525.5-59525.29" + attribute \src "libresoc.v:60223.5-60223.29" switch \initial - attribute \src "libresoc.v:59525.9-59525.17" + attribute \src "libresoc.v:60223.9-60223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101271,18 +102289,18 @@ module \dec$168 sync always update \DIV_function_unit $0\DIV_function_unit[11:0] end - attribute \src "libresoc.v:59534.3-59543.6" - process $proc$libresoc.v:59534$3512 + attribute \src "libresoc.v:60232.3-60241.6" + process $proc$libresoc.v:60232$3546 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:59535.5-59535.29" + attribute \src "libresoc.v:60233.5-60233.29" switch \initial - attribute \src "libresoc.v:59535.9-59535.17" + attribute \src "libresoc.v:60233.9-60233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101294,18 +102312,18 @@ module \dec$168 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:59544.3-59553.6" - process $proc$libresoc.v:59544$3513 + attribute \src "libresoc.v:60242.3-60251.6" + process $proc$libresoc.v:60242$3547 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:59545.5-59545.29" + attribute \src "libresoc.v:60243.5-60243.29" switch \initial - attribute \src "libresoc.v:59545.9-59545.17" + attribute \src "libresoc.v:60243.9-60243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101317,18 +102335,18 @@ module \dec$168 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:59554.3-59563.6" - process $proc$libresoc.v:59554$3514 + attribute \src "libresoc.v:60252.3-60261.6" + process $proc$libresoc.v:60252$3548 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:59555.5-59555.29" + attribute \src "libresoc.v:60253.5-60253.29" switch \initial - attribute \src "libresoc.v:59555.9-59555.17" + attribute \src "libresoc.v:60253.9-60253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101340,18 +102358,18 @@ module \dec$168 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:59564.3-59573.6" - process $proc$libresoc.v:59564$3515 + attribute \src "libresoc.v:60262.3-60271.6" + process $proc$libresoc.v:60262$3549 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:59565.5-59565.29" + attribute \src "libresoc.v:60263.5-60263.29" switch \initial - attribute \src "libresoc.v:59565.9-59565.17" + attribute \src "libresoc.v:60263.9-60263.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101363,18 +102381,18 @@ module \dec$168 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:59574.3-59583.6" - process $proc$libresoc.v:59574$3516 + attribute \src "libresoc.v:60272.3-60281.6" + process $proc$libresoc.v:60272$3550 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:59575.5-59575.29" + attribute \src "libresoc.v:60273.5-60273.29" switch \initial - attribute \src "libresoc.v:59575.9-59575.17" + attribute \src "libresoc.v:60273.9-60273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101386,18 +102404,18 @@ module \dec$168 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:59584.3-59593.6" - process $proc$libresoc.v:59584$3517 + attribute \src "libresoc.v:60282.3-60291.6" + process $proc$libresoc.v:60282$3551 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:59585.5-59585.29" + attribute \src "libresoc.v:60283.5-60283.29" switch \initial - attribute \src "libresoc.v:59585.9-59585.17" + attribute \src "libresoc.v:60283.9-60283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101409,18 +102427,18 @@ module \dec$168 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:59594.3-59603.6" - process $proc$libresoc.v:59594$3518 + attribute \src "libresoc.v:60292.3-60301.6" + process $proc$libresoc.v:60292$3552 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:59595.5-59595.29" + attribute \src "libresoc.v:60293.5-60293.29" switch \initial - attribute \src "libresoc.v:59595.9-59595.17" + attribute \src "libresoc.v:60293.9-60293.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -101432,7 +102450,7 @@ module \dec$168 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:59446$3504_Y + connect \$1 $ternary$libresoc.v:60144$3538_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101763,270 +102781,270 @@ module \dec$168 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59937.1-61328.10" +attribute \src "libresoc.v:60635.1-62026.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" -module \dec$177 - attribute \src "libresoc.v:60934.3-60946.6" +module \dec$180 + attribute \src "libresoc.v:61632.3-61644.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:60947.3-60959.6" + attribute \src "libresoc.v:61645.3-61657.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:60895.3-60907.6" + attribute \src "libresoc.v:61593.3-61605.6" wire width 12 $0\MUL_function_unit[11:0] - attribute \src "libresoc.v:60921.3-60933.6" + attribute \src "libresoc.v:61619.3-61631.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:60908.3-60920.6" + attribute \src "libresoc.v:61606.3-61618.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:60973.3-60985.6" + attribute \src "libresoc.v:61671.3-61683.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:60960.3-60972.6" + attribute \src "libresoc.v:61658.3-61670.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:60986.3-60998.6" + attribute \src "libresoc.v:61684.3-61696.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:59938.7-59938.20" + attribute \src "libresoc.v:60636.7-60636.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60934.3-60946.6" + attribute \src "libresoc.v:61632.3-61644.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:60947.3-60959.6" + attribute \src "libresoc.v:61645.3-61657.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:60895.3-60907.6" + attribute \src "libresoc.v:61593.3-61605.6" wire width 12 $1\MUL_function_unit[11:0] - attribute \src "libresoc.v:60921.3-60933.6" + attribute \src "libresoc.v:61619.3-61631.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:60908.3-60920.6" + attribute \src "libresoc.v:61606.3-61618.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:60973.3-60985.6" + attribute \src "libresoc.v:61671.3-61683.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:60960.3-60972.6" + attribute \src "libresoc.v:61658.3-61670.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:60986.3-60998.6" + attribute \src "libresoc.v:61684.3-61696.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:60883.17-60883.211" - wire width 32 $ternary$libresoc.v:60883$3520_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:61581.17-61581.211" + wire width 32 $ternary$libresoc.v:61581$3554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \MUL_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 19 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 25 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 18 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \MUL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \MUL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 23 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 21 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \MUL_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \MUL_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 24 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 22 \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \MUL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 15 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \MUL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 17 \MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 16 \MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 13 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 11 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \MUL_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MUL_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -102036,7 +103054,7 @@ module \dec$177 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -102044,7 +103062,7 @@ module \dec$177 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -102054,7 +103072,7 @@ module \dec$177 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_MUL_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -102062,7 +103080,7 @@ module \dec$177 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \MUL_dec31_MUL_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -102077,7 +103095,7 @@ module \dec$177 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \MUL_dec31_MUL_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -102094,7 +103112,7 @@ module \dec$177 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \MUL_dec31_MUL_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -102170,19 +103188,19 @@ module \dec$177 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \MUL_dec31_MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_MUL_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \MUL_dec31_MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \MUL_dec31_MUL_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \MUL_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -102197,7 +103215,7 @@ module \dec$177 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -102214,7 +103232,7 @@ module \dec$177 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 8 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -102290,468 +103308,468 @@ module \dec$177 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 28 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 26 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 27 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:59938.7-59938.15" + attribute \src "libresoc.v:60636.7-60636.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 29 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:60883$3520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:61581$3554 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60883$3520_Y + connect \Y $ternary$libresoc.v:61581$3554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60884.13-60894.4" + attribute \src "libresoc.v:61582.13-61592.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -102763,26 +103781,26 @@ module \dec$177 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:59938.7-59938.20" - process $proc$libresoc.v:59938$3529 + attribute \src "libresoc.v:60636.7-60636.20" + process $proc$libresoc.v:60636$3563 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60895.3-60907.6" - process $proc$libresoc.v:60895$3521 + attribute \src "libresoc.v:61593.3-61605.6" + process $proc$libresoc.v:61593$3555 assign { } { } assign { } { } assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] - attribute \src "libresoc.v:60896.5-60896.29" + attribute \src "libresoc.v:61594.5-61594.29" switch \initial - attribute \src "libresoc.v:60896.9-60896.17" + attribute \src "libresoc.v:61594.9-61594.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102798,18 +103816,18 @@ module \dec$177 sync always update \MUL_function_unit $0\MUL_function_unit[11:0] end - attribute \src "libresoc.v:60908.3-60920.6" - process $proc$libresoc.v:60908$3522 + attribute \src "libresoc.v:61606.3-61618.6" + process $proc$libresoc.v:61606$3556 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:60909.5-60909.29" + attribute \src "libresoc.v:61607.5-61607.29" switch \initial - attribute \src "libresoc.v:60909.9-60909.17" + attribute \src "libresoc.v:61607.9-61607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102825,18 +103843,18 @@ module \dec$177 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:60921.3-60933.6" - process $proc$libresoc.v:60921$3523 + attribute \src "libresoc.v:61619.3-61631.6" + process $proc$libresoc.v:61619$3557 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:60922.5-60922.29" + attribute \src "libresoc.v:61620.5-61620.29" switch \initial - attribute \src "libresoc.v:60922.9-60922.17" + attribute \src "libresoc.v:61620.9-61620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102852,18 +103870,18 @@ module \dec$177 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:60934.3-60946.6" - process $proc$libresoc.v:60934$3524 + attribute \src "libresoc.v:61632.3-61644.6" + process $proc$libresoc.v:61632$3558 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:60935.5-60935.29" + attribute \src "libresoc.v:61633.5-61633.29" switch \initial - attribute \src "libresoc.v:60935.9-60935.17" + attribute \src "libresoc.v:61633.9-61633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102879,18 +103897,18 @@ module \dec$177 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:60947.3-60959.6" - process $proc$libresoc.v:60947$3525 + attribute \src "libresoc.v:61645.3-61657.6" + process $proc$libresoc.v:61645$3559 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:60948.5-60948.29" + attribute \src "libresoc.v:61646.5-61646.29" switch \initial - attribute \src "libresoc.v:60948.9-60948.17" + attribute \src "libresoc.v:61646.9-61646.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102906,18 +103924,18 @@ module \dec$177 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:60960.3-60972.6" - process $proc$libresoc.v:60960$3526 + attribute \src "libresoc.v:61658.3-61670.6" + process $proc$libresoc.v:61658$3560 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:60961.5-60961.29" + attribute \src "libresoc.v:61659.5-61659.29" switch \initial - attribute \src "libresoc.v:60961.9-60961.17" + attribute \src "libresoc.v:61659.9-61659.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102933,18 +103951,18 @@ module \dec$177 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:60973.3-60985.6" - process $proc$libresoc.v:60973$3527 + attribute \src "libresoc.v:61671.3-61683.6" + process $proc$libresoc.v:61671$3561 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:60974.5-60974.29" + attribute \src "libresoc.v:61672.5-61672.29" switch \initial - attribute \src "libresoc.v:60974.9-60974.17" + attribute \src "libresoc.v:61672.9-61672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102960,18 +103978,18 @@ module \dec$177 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:60986.3-60998.6" - process $proc$libresoc.v:60986$3528 + attribute \src "libresoc.v:61684.3-61696.6" + process $proc$libresoc.v:61684$3562 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:60987.5-60987.29" + attribute \src "libresoc.v:61685.5-61685.29" switch \initial - attribute \src "libresoc.v:60987.9-60987.17" + attribute \src "libresoc.v:61685.9-61685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -102987,7 +104005,7 @@ module \dec$177 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:60883$3520_Y + connect \$1 $ternary$libresoc.v:61581$3554_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103318,299 +104336,303 @@ module \dec$177 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61332.1-63019.10" +attribute \src "libresoc.v:62030.1-63748.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" -module \dec$185 - attribute \src "libresoc.v:62601.3-62622.6" +module \dec$188 + attribute \src "libresoc.v:63330.3-63351.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:62623.3-62644.6" + attribute \src "libresoc.v:63352.3-63373.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:62667.3-62688.6" + attribute \src "libresoc.v:63396.3-63417.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:62469.3-62490.6" + attribute \src "libresoc.v:63198.3-63219.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:62535.3-62556.6" + attribute \src "libresoc.v:63264.3-63285.6" wire width 12 $0\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:62579.3-62600.6" + attribute \src "libresoc.v:63308.3-63329.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:62557.3-62578.6" + attribute \src "libresoc.v:63286.3-63307.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:62491.3-62512.6" + attribute \src "libresoc.v:63176.3-63197.6" + wire $0\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63220.3-63241.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:62645.3-62666.6" + attribute \src "libresoc.v:63374.3-63395.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:62513.3-62534.6" + attribute \src "libresoc.v:63242.3-63263.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:61333.7-61333.20" + attribute \src "libresoc.v:62031.7-62031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62601.3-62622.6" + attribute \src "libresoc.v:63330.3-63351.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:62623.3-62644.6" + attribute \src "libresoc.v:63352.3-63373.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:62667.3-62688.6" + attribute \src "libresoc.v:63396.3-63417.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:62469.3-62490.6" + attribute \src "libresoc.v:63198.3-63219.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:62535.3-62556.6" + attribute \src "libresoc.v:63264.3-63285.6" wire width 12 $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:62579.3-62600.6" + attribute \src "libresoc.v:63308.3-63329.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:62557.3-62578.6" + attribute \src "libresoc.v:63286.3-63307.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:62491.3-62512.6" + attribute \src "libresoc.v:63176.3-63197.6" + wire $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63220.3-63241.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:62645.3-62666.6" + attribute \src "libresoc.v:63374.3-63395.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:62513.3-62534.6" + attribute \src "libresoc.v:63242.3-63263.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62442.17-62442.211" - wire width 32 $ternary$libresoc.v:62442$3530_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:63147.17-63147.211" + wire width 32 $ternary$libresoc.v:63147$3564_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 22 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 21 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 27 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 20 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 23 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 22 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 28 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 21 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 25 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 26 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 23 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 24 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \SHIFT_ROT_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \SHIFT_ROT_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 14 output 26 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 8 output 24 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 14 output 27 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 25 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SHIFT_ROT_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 24 output 17 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 output 18 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \SHIFT_ROT_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 19 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 20 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire output 18 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 19 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 5 output 15 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 13 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 16 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 14 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 16 output 14 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 output 15 \SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -103619,7 +104641,7 @@ module \dec$185 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103627,16 +104649,16 @@ module \dec$185 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" - wire width 2 output 9 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 10 \SHIFT_ROT_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 10 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 11 \SHIFT_ROT_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -103645,7 +104667,7 @@ module \dec$185 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103653,15 +104675,15 @@ module \dec$185 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -103676,7 +104698,7 @@ module \dec$185 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103693,7 +104715,7 @@ module \dec$185 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103769,19 +104791,21 @@ module \dec$185 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SHIFT_ROT_dec30_opcode_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -103791,7 +104815,7 @@ module \dec$185 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -103799,15 +104823,15 @@ module \dec$185 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -103822,7 +104846,7 @@ module \dec$185 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103839,7 +104863,7 @@ module \dec$185 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -103915,19 +104939,21 @@ module \dec$185 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \SHIFT_ROT_dec31_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -103942,7 +104968,7 @@ module \dec$185 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -103959,7 +104985,7 @@ module \dec$185 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 8 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -104035,448 +105061,450 @@ module \dec$185 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 11 \SHIFT_ROT_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 12 \SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" - wire output 12 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - wire width 6 output 16 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 13 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 output 17 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 5 output 30 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 31 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 28 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" - wire width 3 output 29 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 29 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 30 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:61333.7-61333.15" + attribute \src "libresoc.v:62031.7-62031.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 31 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:62442$3530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 32 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:63147$3564 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62442$3530_Y + connect \Y $ternary$libresoc.v:63147$3564_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62443.19-62455.4" + attribute \src "libresoc.v:63148.19-63161.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -104485,13 +105513,14 @@ module \dec$185 connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:62456.19-62468.4" + attribute \src "libresoc.v:63162.19-63175.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -104500,31 +105529,71 @@ module \dec$185 connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:61333.7-61333.20" - process $proc$libresoc.v:61333$3541 + attribute \src "libresoc.v:62031.7-62031.20" + process $proc$libresoc.v:62031$3576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62469.3-62490.6" - process $proc$libresoc.v:62469$3531 + attribute \src "libresoc.v:63176.3-63197.6" + process $proc$libresoc.v:63176$3565 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63177.5-63177.29" + switch \initial + attribute \src "libresoc.v:63177.9-63177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] + end + attribute \src "libresoc.v:63198.3-63219.6" + process $proc$libresoc.v:63198$3566 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:62470.5-62470.29" + attribute \src "libresoc.v:63199.5-63199.29" switch \initial - attribute \src "libresoc.v:62470.9-62470.17" + attribute \src "libresoc.v:63199.9-63199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104552,18 +105621,18 @@ module \dec$185 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:62491.3-62512.6" - process $proc$libresoc.v:62491$3532 + attribute \src "libresoc.v:63220.3-63241.6" + process $proc$libresoc.v:63220$3567 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:62492.5-62492.29" + attribute \src "libresoc.v:63221.5-63221.29" switch \initial - attribute \src "libresoc.v:62492.9-62492.17" + attribute \src "libresoc.v:63221.9-63221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104591,18 +105660,18 @@ module \dec$185 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:62513.3-62534.6" - process $proc$libresoc.v:62513$3533 + attribute \src "libresoc.v:63242.3-63263.6" + process $proc$libresoc.v:63242$3568 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62514.5-62514.29" + attribute \src "libresoc.v:63243.5-63243.29" switch \initial - attribute \src "libresoc.v:62514.9-62514.17" + attribute \src "libresoc.v:63243.9-63243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104630,18 +105699,18 @@ module \dec$185 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:62535.3-62556.6" - process $proc$libresoc.v:62535$3534 + attribute \src "libresoc.v:63264.3-63285.6" + process $proc$libresoc.v:63264$3569 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:62536.5-62536.29" + attribute \src "libresoc.v:63265.5-63265.29" switch \initial - attribute \src "libresoc.v:62536.9-62536.17" + attribute \src "libresoc.v:63265.9-63265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104669,18 +105738,18 @@ module \dec$185 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] end - attribute \src "libresoc.v:62557.3-62578.6" - process $proc$libresoc.v:62557$3535 + attribute \src "libresoc.v:63286.3-63307.6" + process $proc$libresoc.v:63286$3570 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:62558.5-62558.29" + attribute \src "libresoc.v:63287.5-63287.29" switch \initial - attribute \src "libresoc.v:62558.9-62558.17" + attribute \src "libresoc.v:63287.9-63287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104708,18 +105777,18 @@ module \dec$185 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:62579.3-62600.6" - process $proc$libresoc.v:62579$3536 + attribute \src "libresoc.v:63308.3-63329.6" + process $proc$libresoc.v:63308$3571 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:62580.5-62580.29" + attribute \src "libresoc.v:63309.5-63309.29" switch \initial - attribute \src "libresoc.v:62580.9-62580.17" + attribute \src "libresoc.v:63309.9-63309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104747,18 +105816,18 @@ module \dec$185 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:62601.3-62622.6" - process $proc$libresoc.v:62601$3537 + attribute \src "libresoc.v:63330.3-63351.6" + process $proc$libresoc.v:63330$3572 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:62602.5-62602.29" + attribute \src "libresoc.v:63331.5-63331.29" switch \initial - attribute \src "libresoc.v:62602.9-62602.17" + attribute \src "libresoc.v:63331.9-63331.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104786,18 +105855,18 @@ module \dec$185 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:62623.3-62644.6" - process $proc$libresoc.v:62623$3538 + attribute \src "libresoc.v:63352.3-63373.6" + process $proc$libresoc.v:63352$3573 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:62624.5-62624.29" + attribute \src "libresoc.v:63353.5-63353.29" switch \initial - attribute \src "libresoc.v:62624.9-62624.17" + attribute \src "libresoc.v:63353.9-63353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104810,33 +105879,33 @@ module \dec$185 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 case assign $1\SHIFT_ROT_cr_out[2:0] 3'000 end sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:62645.3-62666.6" - process $proc$libresoc.v:62645$3539 + attribute \src "libresoc.v:63374.3-63395.6" + process $proc$libresoc.v:63374$3574 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:62646.5-62646.29" + attribute \src "libresoc.v:63375.5-63375.29" switch \initial - attribute \src "libresoc.v:62646.9-62646.17" + attribute \src "libresoc.v:63375.9-63375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104864,18 +105933,18 @@ module \dec$185 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:62667.3-62688.6" - process $proc$libresoc.v:62667$3540 + attribute \src "libresoc.v:63396.3-63417.6" + process $proc$libresoc.v:63396$3575 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:62668.5-62668.29" + attribute \src "libresoc.v:63397.5-63397.29" switch \initial - attribute \src "libresoc.v:62668.9-62668.17" + attribute \src "libresoc.v:63397.9-63397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011110 @@ -104903,7 +105972,7 @@ module \dec$185 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:62442$3530_Y + connect \$1 $ternary$libresoc.v:63147$3564_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -105235,256 +106304,256 @@ module \dec$185 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:63023.1-65492.10" +attribute \src "libresoc.v:63752.1-66221.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" -module \dec$193 - attribute \src "libresoc.v:64581.3-64638.6" +module \dec$196 + attribute \src "libresoc.v:65310.3-65367.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:65045.3-65102.6" + attribute \src "libresoc.v:65774.3-65831.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:65103.3-65160.6" + attribute \src "libresoc.v:65832.3-65889.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:64813.3-64870.6" + attribute \src "libresoc.v:65542.3-65599.6" wire width 12 $0\LDST_function_unit[11:0] - attribute \src "libresoc.v:64929.3-64986.6" + attribute \src "libresoc.v:65658.3-65715.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:64987.3-65044.6" + attribute \src "libresoc.v:65716.3-65773.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:64871.3-64928.6" + attribute \src "libresoc.v:65600.3-65657.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:64697.3-64754.6" + attribute \src "libresoc.v:65426.3-65483.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:64407.3-64464.6" + attribute \src "libresoc.v:65136.3-65193.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:64523.3-64580.6" + attribute \src "libresoc.v:65252.3-65309.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:64755.3-64812.6" + attribute \src "libresoc.v:65484.3-65541.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:64639.3-64696.6" + attribute \src "libresoc.v:65368.3-65425.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:64465.3-64522.6" + attribute \src "libresoc.v:65194.3-65251.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:63024.7-63024.20" + attribute \src "libresoc.v:63753.7-63753.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64581.3-64638.6" + attribute \src "libresoc.v:65310.3-65367.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:65045.3-65102.6" + attribute \src "libresoc.v:65774.3-65831.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65103.3-65160.6" + attribute \src "libresoc.v:65832.3-65889.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:64813.3-64870.6" + attribute \src "libresoc.v:65542.3-65599.6" wire width 12 $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:64929.3-64986.6" + attribute \src "libresoc.v:65658.3-65715.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:64987.3-65044.6" + attribute \src "libresoc.v:65716.3-65773.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:64871.3-64928.6" + attribute \src "libresoc.v:65600.3-65657.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:64697.3-64754.6" + attribute \src "libresoc.v:65426.3-65483.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:64407.3-64464.6" + attribute \src "libresoc.v:65136.3-65193.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:64523.3-64580.6" + attribute \src "libresoc.v:65252.3-65309.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:64755.3-64812.6" + attribute \src "libresoc.v:65484.3-65541.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:64639.3-64696.6" + attribute \src "libresoc.v:65368.3-65425.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:64465.3-64522.6" + attribute \src "libresoc.v:65194.3-65251.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:64358.17-64358.211" - wire width 32 $ternary$libresoc.v:64358$3542_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:65087.17-65087.211" + wire width 32 $ternary$libresoc.v:65087$3577_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LDST_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 25 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 31 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 24 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \LDST_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \LDST_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 29 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 27 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \LDST_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \LDST_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 output 30 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 28 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LDST_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 output 21 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \LDST_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 23 \LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 16 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 22 \LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 19 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 17 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \LDST_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \LDST_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 output 18 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105494,7 +106563,7 @@ module \dec$193 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105502,9 +106571,9 @@ module \dec$193 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105514,7 +106583,7 @@ module \dec$193 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_LDST_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105522,7 +106591,7 @@ module \dec$193 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_LDST_dec31_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -105537,7 +106606,7 @@ module \dec$193 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec31_LDST_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -105545,7 +106614,7 @@ module \dec$193 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec31_LDST_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105562,7 +106631,7 @@ module \dec$193 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_LDST_dec31_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105638,9 +106707,9 @@ module \dec$193 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec31_LDST_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_LDST_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -105648,28 +106717,28 @@ module \dec$193 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec31_LDST_dec31_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_LDST_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_LDST_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec31_LDST_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec31_LDST_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec58_LDST_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105679,7 +106748,7 @@ module \dec$193 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec58_LDST_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105687,7 +106756,7 @@ module \dec$193 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec58_LDST_dec58_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -105702,7 +106771,7 @@ module \dec$193 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec58_LDST_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -105710,7 +106779,7 @@ module \dec$193 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec58_LDST_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105727,7 +106796,7 @@ module \dec$193 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec58_LDST_dec58_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105803,9 +106872,9 @@ module \dec$193 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec58_LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec58_LDST_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -105813,28 +106882,28 @@ module \dec$193 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec58_LDST_dec58_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec58_LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec58_LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec58_LDST_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec58_LDST_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec62_LDST_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -105844,7 +106913,7 @@ module \dec$193 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec62_LDST_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -105852,7 +106921,7 @@ module \dec$193 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec62_LDST_dec62_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -105867,7 +106936,7 @@ module \dec$193 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \LDST_dec62_LDST_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -105875,7 +106944,7 @@ module \dec$193 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \LDST_dec62_LDST_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -105892,7 +106961,7 @@ module \dec$193 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec62_LDST_dec62_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -105968,9 +107037,9 @@ module \dec$193 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \LDST_dec62_LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec62_LDST_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -105978,26 +107047,26 @@ module \dec$193 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \LDST_dec62_LDST_dec62_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec62_LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec62_LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \LDST_dec62_LDST_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \LDST_dec62_LDST_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \LDST_dec62_opcode_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -106012,7 +107081,7 @@ module \dec$193 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -106020,7 +107089,7 @@ module \dec$193 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 8 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -106037,7 +107106,7 @@ module \dec$193 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 9 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -106113,9 +107182,9 @@ module \dec$193 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -106123,511 +107192,511 @@ module \dec$193 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 12 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 14 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 15 \LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "libresoc.v:63024.7-63024.15" + attribute \src "libresoc.v:63753.7-63753.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 35 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:64358$3542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:65087$3577 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:64358$3542_Y + connect \Y $ternary$libresoc.v:65087$3577_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:64359.14-64374.4" + attribute \src "libresoc.v:65088.14-65103.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -106645,7 +107714,7 @@ module \dec$193 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:64375.14-64390.4" + attribute \src "libresoc.v:65104.14-65119.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -106663,7 +107732,7 @@ module \dec$193 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:64391.14-64406.4" + attribute \src "libresoc.v:65120.14-65135.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -106680,26 +107749,26 @@ module \dec$193 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:63024.7-63024.20" - process $proc$libresoc.v:63024$3556 + attribute \src "libresoc.v:63753.7-63753.20" + process $proc$libresoc.v:63753$3591 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:64407.3-64464.6" - process $proc$libresoc.v:64407$3543 + attribute \src "libresoc.v:65136.3-65193.6" + process $proc$libresoc.v:65136$3578 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:64408.5-64408.29" + attribute \src "libresoc.v:65137.5-65137.29" switch \initial - attribute \src "libresoc.v:64408.9-64408.17" + attribute \src "libresoc.v:65137.9-65137.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -106775,18 +107844,18 @@ module \dec$193 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:64465.3-64522.6" - process $proc$libresoc.v:64465$3544 + attribute \src "libresoc.v:65194.3-65251.6" + process $proc$libresoc.v:65194$3579 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:64466.5-64466.29" + attribute \src "libresoc.v:65195.5-65195.29" switch \initial - attribute \src "libresoc.v:64466.9-64466.17" + attribute \src "libresoc.v:65195.9-65195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -106862,18 +107931,18 @@ module \dec$193 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:64523.3-64580.6" - process $proc$libresoc.v:64523$3545 + attribute \src "libresoc.v:65252.3-65309.6" + process $proc$libresoc.v:65252$3580 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:64524.5-64524.29" + attribute \src "libresoc.v:65253.5-65253.29" switch \initial - attribute \src "libresoc.v:64524.9-64524.17" + attribute \src "libresoc.v:65253.9-65253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -106949,18 +108018,18 @@ module \dec$193 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:64581.3-64638.6" - process $proc$libresoc.v:64581$3546 + attribute \src "libresoc.v:65310.3-65367.6" + process $proc$libresoc.v:65310$3581 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:64582.5-64582.29" + attribute \src "libresoc.v:65311.5-65311.29" switch \initial - attribute \src "libresoc.v:64582.9-64582.17" + attribute \src "libresoc.v:65311.9-65311.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107036,18 +108105,18 @@ module \dec$193 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:64639.3-64696.6" - process $proc$libresoc.v:64639$3547 + attribute \src "libresoc.v:65368.3-65425.6" + process $proc$libresoc.v:65368$3582 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:64640.5-64640.29" + attribute \src "libresoc.v:65369.5-65369.29" switch \initial - attribute \src "libresoc.v:64640.9-64640.17" + attribute \src "libresoc.v:65369.9-65369.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107123,18 +108192,18 @@ module \dec$193 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:64697.3-64754.6" - process $proc$libresoc.v:64697$3548 + attribute \src "libresoc.v:65426.3-65483.6" + process $proc$libresoc.v:65426$3583 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:64698.5-64698.29" + attribute \src "libresoc.v:65427.5-65427.29" switch \initial - attribute \src "libresoc.v:64698.9-64698.17" + attribute \src "libresoc.v:65427.9-65427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107210,18 +108279,18 @@ module \dec$193 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:64755.3-64812.6" - process $proc$libresoc.v:64755$3549 + attribute \src "libresoc.v:65484.3-65541.6" + process $proc$libresoc.v:65484$3584 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:64756.5-64756.29" + attribute \src "libresoc.v:65485.5-65485.29" switch \initial - attribute \src "libresoc.v:64756.9-64756.17" + attribute \src "libresoc.v:65485.9-65485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107297,18 +108366,18 @@ module \dec$193 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:64813.3-64870.6" - process $proc$libresoc.v:64813$3550 + attribute \src "libresoc.v:65542.3-65599.6" + process $proc$libresoc.v:65542$3585 assign { } { } assign { } { } assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:64814.5-64814.29" + attribute \src "libresoc.v:65543.5-65543.29" switch \initial - attribute \src "libresoc.v:64814.9-64814.17" + attribute \src "libresoc.v:65543.9-65543.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107384,18 +108453,18 @@ module \dec$193 sync always update \LDST_function_unit $0\LDST_function_unit[11:0] end - attribute \src "libresoc.v:64871.3-64928.6" - process $proc$libresoc.v:64871$3551 + attribute \src "libresoc.v:65600.3-65657.6" + process $proc$libresoc.v:65600$3586 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:64872.5-64872.29" + attribute \src "libresoc.v:65601.5-65601.29" switch \initial - attribute \src "libresoc.v:64872.9-64872.17" + attribute \src "libresoc.v:65601.9-65601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107471,18 +108540,18 @@ module \dec$193 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:64929.3-64986.6" - process $proc$libresoc.v:64929$3552 + attribute \src "libresoc.v:65658.3-65715.6" + process $proc$libresoc.v:65658$3587 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:64930.5-64930.29" + attribute \src "libresoc.v:65659.5-65659.29" switch \initial - attribute \src "libresoc.v:64930.9-64930.17" + attribute \src "libresoc.v:65659.9-65659.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107558,18 +108627,18 @@ module \dec$193 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:64987.3-65044.6" - process $proc$libresoc.v:64987$3553 + attribute \src "libresoc.v:65716.3-65773.6" + process $proc$libresoc.v:65716$3588 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:64988.5-64988.29" + attribute \src "libresoc.v:65717.5-65717.29" switch \initial - attribute \src "libresoc.v:64988.9-64988.17" + attribute \src "libresoc.v:65717.9-65717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107645,18 +108714,18 @@ module \dec$193 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:65045.3-65102.6" - process $proc$libresoc.v:65045$3554 + attribute \src "libresoc.v:65774.3-65831.6" + process $proc$libresoc.v:65774$3589 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65046.5-65046.29" + attribute \src "libresoc.v:65775.5-65775.29" switch \initial - attribute \src "libresoc.v:65046.9-65046.17" + attribute \src "libresoc.v:65775.9-65775.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107732,18 +108801,18 @@ module \dec$193 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:65103.3-65160.6" - process $proc$libresoc.v:65103$3555 + attribute \src "libresoc.v:65832.3-65889.6" + process $proc$libresoc.v:65832$3590 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65104.5-65104.29" + attribute \src "libresoc.v:65833.5-65833.29" switch \initial - attribute \src "libresoc.v:65104.9-65104.17" + attribute \src "libresoc.v:65833.9-65833.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'011111 @@ -107819,7 +108888,7 @@ module \dec$193 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:64358$3542_Y + connect \$1 $ternary$libresoc.v:65087$3577_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -108152,816 +109221,816 @@ module \dec$193 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:65496.1-71429.10" +attribute \src "libresoc.v:66225.1-72158.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" -module \dec$202 - attribute \src "libresoc.v:67690.3-67828.6" +module \dec$205 + attribute \src "libresoc.v:68419.3-68557.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:69675.3-69816.6" + attribute \src "libresoc.v:70404.3-70545.6" wire $0\br[0:0] - attribute \src "libresoc.v:68397.3-68538.6" + attribute \src "libresoc.v:69126.3-69267.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:68539.3-68680.6" + attribute \src "libresoc.v:69268.3-69409.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:69107.3-69248.6" + attribute \src "libresoc.v:69836.3-69977.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:69533.3-69674.6" + attribute \src "libresoc.v:70262.3-70403.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:70953.3-71094.6" + attribute \src "libresoc.v:71682.3-71823.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:70669.3-70810.6" + attribute \src "libresoc.v:71398.3-71539.6" wire width 12 $0\function_unit[11:0] - attribute \src "libresoc.v:67829.3-67970.6" + attribute \src "libresoc.v:68558.3-68699.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:67971.3-68112.6" + attribute \src "libresoc.v:68700.3-68841.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:68113.3-68254.6" + attribute \src "libresoc.v:68842.3-68983.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:65497.7-65497.20" + attribute \src "libresoc.v:66226.7-66226.20" wire $0\initial[0:0] - attribute \src "libresoc.v:70811.3-70952.6" + attribute \src "libresoc.v:71540.3-71681.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:69249.3-69390.6" + attribute \src "libresoc.v:69978.3-70119.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:69391.3-69532.6" + attribute \src "libresoc.v:70120.3-70261.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:70101.3-70242.6" + attribute \src "libresoc.v:70830.3-70971.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:68681.3-68822.6" + attribute \src "libresoc.v:69410.3-69551.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:70385.3-70526.6" + attribute \src "libresoc.v:71114.3-71255.6" wire $0\lk[0:0] - attribute \src "libresoc.v:68255.3-68396.6" + attribute \src "libresoc.v:68984.3-69125.6" wire width 2 $0\out_sel[1:0] - attribute \src "libresoc.v:68965.3-69106.6" + attribute \src "libresoc.v:69694.3-69835.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:69959.3-70100.6" + attribute \src "libresoc.v:70688.3-70829.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:70527.3-70668.6" + attribute \src "libresoc.v:71256.3-71397.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:70243.3-70384.6" + attribute \src "libresoc.v:70972.3-71113.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:69817.3-69958.6" + attribute \src "libresoc.v:70546.3-70687.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:68823.3-68964.6" + attribute \src "libresoc.v:69552.3-69693.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:67690.3-67828.6" + attribute \src "libresoc.v:68419.3-68557.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:69675.3-69816.6" + attribute \src "libresoc.v:70404.3-70545.6" wire $1\br[0:0] - attribute \src "libresoc.v:68397.3-68538.6" + attribute \src "libresoc.v:69126.3-69267.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:68539.3-68680.6" + attribute \src "libresoc.v:69268.3-69409.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:69107.3-69248.6" + attribute \src "libresoc.v:69836.3-69977.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:69533.3-69674.6" + attribute \src "libresoc.v:70262.3-70403.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:70953.3-71094.6" + attribute \src "libresoc.v:71682.3-71823.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:70669.3-70810.6" + attribute \src "libresoc.v:71398.3-71539.6" wire width 12 $1\function_unit[11:0] - attribute \src "libresoc.v:67829.3-67970.6" + attribute \src "libresoc.v:68558.3-68699.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:67971.3-68112.6" + attribute \src "libresoc.v:68700.3-68841.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:68113.3-68254.6" + attribute \src "libresoc.v:68842.3-68983.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:70811.3-70952.6" + attribute \src "libresoc.v:71540.3-71681.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:69249.3-69390.6" + attribute \src "libresoc.v:69978.3-70119.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:69391.3-69532.6" + attribute \src "libresoc.v:70120.3-70261.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:70101.3-70242.6" + attribute \src "libresoc.v:70830.3-70971.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:68681.3-68822.6" + attribute \src "libresoc.v:69410.3-69551.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:70385.3-70526.6" + attribute \src "libresoc.v:71114.3-71255.6" wire $1\lk[0:0] - attribute \src "libresoc.v:68255.3-68396.6" + attribute \src "libresoc.v:68984.3-69125.6" wire width 2 $1\out_sel[1:0] - attribute \src "libresoc.v:68965.3-69106.6" + attribute \src "libresoc.v:69694.3-69835.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:69959.3-70100.6" + attribute \src "libresoc.v:70688.3-70829.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:70527.3-70668.6" + attribute \src "libresoc.v:71256.3-71397.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:70243.3-70384.6" + attribute \src "libresoc.v:70972.3-71113.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:69817.3-69958.6" + attribute \src "libresoc.v:70546.3-70687.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:68823.3-68964.6" + attribute \src "libresoc.v:69552.3-69693.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:67690.3-67828.6" + attribute \src "libresoc.v:68419.3-68557.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:69675.3-69816.6" + attribute \src "libresoc.v:70404.3-70545.6" wire $2\br[0:0] - attribute \src "libresoc.v:68397.3-68538.6" + attribute \src "libresoc.v:69126.3-69267.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:68539.3-68680.6" + attribute \src "libresoc.v:69268.3-69409.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:69107.3-69248.6" + attribute \src "libresoc.v:69836.3-69977.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:69533.3-69674.6" + attribute \src "libresoc.v:70262.3-70403.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:70953.3-71094.6" + attribute \src "libresoc.v:71682.3-71823.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:70669.3-70810.6" + attribute \src "libresoc.v:71398.3-71539.6" wire width 12 $2\function_unit[11:0] - attribute \src "libresoc.v:67829.3-67970.6" + attribute \src "libresoc.v:68558.3-68699.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:67971.3-68112.6" + attribute \src "libresoc.v:68700.3-68841.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:68113.3-68254.6" + attribute \src "libresoc.v:68842.3-68983.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:70811.3-70952.6" + attribute \src "libresoc.v:71540.3-71681.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:69249.3-69390.6" + attribute \src "libresoc.v:69978.3-70119.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:69391.3-69532.6" + attribute \src "libresoc.v:70120.3-70261.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:70101.3-70242.6" + attribute \src "libresoc.v:70830.3-70971.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:68681.3-68822.6" + attribute \src "libresoc.v:69410.3-69551.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:70385.3-70526.6" + attribute \src "libresoc.v:71114.3-71255.6" wire $2\lk[0:0] - attribute \src "libresoc.v:68255.3-68396.6" + attribute \src "libresoc.v:68984.3-69125.6" wire width 2 $2\out_sel[1:0] - attribute \src "libresoc.v:68965.3-69106.6" + attribute \src "libresoc.v:69694.3-69835.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:69959.3-70100.6" + attribute \src "libresoc.v:70688.3-70829.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:70527.3-70668.6" + attribute \src "libresoc.v:71256.3-71397.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:70243.3-70384.6" + attribute \src "libresoc.v:70972.3-71113.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:69817.3-69958.6" + attribute \src "libresoc.v:70546.3-70687.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:68823.3-68964.6" + attribute \src "libresoc.v:69552.3-69693.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:67554.17-67554.211" - wire width 32 $ternary$libresoc.v:67554$3557_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + attribute \src "libresoc.v:68283.17-68283.211" + wire width 32 $ternary$libresoc.v:68283$3592_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" wire width 32 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 25 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 24 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 30 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 3 \BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 2 \BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 29 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 28 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 26 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 output 27 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 23 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 20 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 21 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 18 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 output 19 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire output 22 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 output 31 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 16 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 36 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -108971,7 +110040,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 4 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -108979,19 +110048,19 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec19_dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109001,7 +110070,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec19_dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109009,15 +110078,15 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec19_dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec19_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109049,7 +110118,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -109064,7 +110133,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec19_dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -109072,7 +110141,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec19_dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -109089,13 +110158,13 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec19_dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -109171,13 +110240,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec19_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -109185,43 +110254,43 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec19_dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec19_dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec19_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec19_dec19_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec19_dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec30_dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109231,7 +110300,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec30_dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109239,15 +110308,15 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec30_dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec30_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109279,7 +110348,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -109294,7 +110363,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec30_dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -109302,7 +110371,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec30_dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -109319,13 +110388,13 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec30_dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -109401,13 +110470,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec30_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -109415,43 +110484,43 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec30_dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec30_dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec30_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec30_dec30_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec30_dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec30_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109461,7 +110530,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109469,15 +110538,15 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109509,7 +110578,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -109524,7 +110593,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -109532,7 +110601,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -109549,13 +110618,13 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -109631,13 +110700,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -109645,43 +110714,43 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec58_dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109691,7 +110760,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec58_dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109699,15 +110768,15 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec58_dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec58_dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109739,7 +110808,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -109754,7 +110823,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec58_dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -109762,7 +110831,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec58_dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -109779,13 +110848,13 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec58_dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec58_dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -109861,13 +110930,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec58_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -109875,43 +110944,43 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec58_dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec58_dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec58_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec58_dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec58_dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec58_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec62_dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -109921,7 +110990,7 @@ module \dec$202 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec62_dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -109929,15 +110998,15 @@ module \dec$202 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec62_dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec62_dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -109969,7 +111038,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -109984,7 +111053,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec62_dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -109992,7 +111061,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec62_dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110009,13 +111078,13 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec62_dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110091,13 +111160,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec62_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110105,39 +111174,39 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec62_dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec62_dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec62_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec62_dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec62_dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec62_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -110169,7 +111238,7 @@ module \dec$202 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -110184,7 +111253,7 @@ module \dec$202 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 7 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -110192,7 +111261,7 @@ module \dec$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 12 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -110209,15 +111278,15 @@ module \dec$202 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 13 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \in3_sel - attribute \src "libresoc.v:65497.7-65497.15" + attribute \src "libresoc.v:66226.7-66226.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -110293,13 +111362,13 @@ module \dec$202 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 6 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -110307,58 +111376,58 @@ module \dec$202 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 32 \opcode_switch$1 attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 15 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 17 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" - cell $mux $ternary$libresoc.v:67554$3557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:68283$3592 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:67554$3557_Y + connect \Y $ternary$libresoc.v:68283$3592_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:67555.9-67581.4" + attribute \src "libresoc.v:68284.9-68310.4" cell \dec19 \dec19 connect \dec19_asmcode \dec19_dec19_asmcode connect \dec19_br \dec19_dec19_br @@ -110387,7 +111456,7 @@ module \dec$202 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:67582.9-67608.4" + attribute \src "libresoc.v:68311.9-68337.4" cell \dec30 \dec30 connect \dec30_asmcode \dec30_dec30_asmcode connect \dec30_br \dec30_dec30_br @@ -110416,7 +111485,7 @@ module \dec$202 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:67609.9-67635.4" + attribute \src "libresoc.v:68338.9-68364.4" cell \dec31 \dec31 connect \dec31_asmcode \dec31_dec31_asmcode connect \dec31_br \dec31_dec31_br @@ -110445,7 +111514,7 @@ module \dec$202 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:67636.9-67662.4" + attribute \src "libresoc.v:68365.9-68391.4" cell \dec58 \dec58 connect \dec58_asmcode \dec58_dec58_asmcode connect \dec58_br \dec58_dec58_br @@ -110474,7 +111543,7 @@ module \dec$202 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:67663.9-67689.4" + attribute \src "libresoc.v:68392.9-68418.4" cell \dec62 \dec62 connect \dec62_asmcode \dec62_dec62_asmcode connect \dec62_br \dec62_dec62_br @@ -110502,27 +111571,27 @@ module \dec$202 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:65497.7-65497.20" - process $proc$libresoc.v:65497$3582 + attribute \src "libresoc.v:66226.7-66226.20" + process $proc$libresoc.v:66226$3617 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:67690.3-67828.6" - process $proc$libresoc.v:67690$3558 + attribute \src "libresoc.v:68419.3-68557.6" + process $proc$libresoc.v:68419$3593 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:67691.5-67691.29" + attribute \src "libresoc.v:68420.5-68420.29" switch \initial - attribute \src "libresoc.v:67691.9-67691.17" + attribute \src "libresoc.v:68420.9-68420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -110687,7 +111756,7 @@ module \dec$202 case assign $1\asmcode[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -110707,19 +111776,19 @@ module \dec$202 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:67829.3-67970.6" - process $proc$libresoc.v:67829$3559 + attribute \src "libresoc.v:68558.3-68699.6" + process $proc$libresoc.v:68558$3594 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:67830.5-67830.29" + attribute \src "libresoc.v:68559.5-68559.29" switch \initial - attribute \src "libresoc.v:67830.9-67830.17" + attribute \src "libresoc.v:68559.9-68559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -110888,7 +111957,7 @@ module \dec$202 case assign $1\in1_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -110908,19 +111977,19 @@ module \dec$202 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:67971.3-68112.6" - process $proc$libresoc.v:67971$3560 + attribute \src "libresoc.v:68700.3-68841.6" + process $proc$libresoc.v:68700$3595 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:67972.5-67972.29" + attribute \src "libresoc.v:68701.5-68701.29" switch \initial - attribute \src "libresoc.v:67972.9-67972.17" + attribute \src "libresoc.v:68701.9-68701.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111089,7 +112158,7 @@ module \dec$202 case assign $1\in2_sel[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111109,19 +112178,19 @@ module \dec$202 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:68113.3-68254.6" - process $proc$libresoc.v:68113$3561 + attribute \src "libresoc.v:68842.3-68983.6" + process $proc$libresoc.v:68842$3596 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:68114.5-68114.29" + attribute \src "libresoc.v:68843.5-68843.29" switch \initial - attribute \src "libresoc.v:68114.9-68114.17" + attribute \src "libresoc.v:68843.9-68843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111290,7 +112359,7 @@ module \dec$202 case assign $1\in3_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111310,19 +112379,19 @@ module \dec$202 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:68255.3-68396.6" - process $proc$libresoc.v:68255$3562 + attribute \src "libresoc.v:68984.3-69125.6" + process $proc$libresoc.v:68984$3597 assign { } { } assign { } { } assign { } { } assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:68256.5-68256.29" + attribute \src "libresoc.v:68985.5-68985.29" switch \initial - attribute \src "libresoc.v:68256.9-68256.17" + attribute \src "libresoc.v:68985.9-68985.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111491,7 +112560,7 @@ module \dec$202 case assign $1\out_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111511,19 +112580,19 @@ module \dec$202 sync always update \out_sel $0\out_sel[1:0] end - attribute \src "libresoc.v:68397.3-68538.6" - process $proc$libresoc.v:68397$3563 + attribute \src "libresoc.v:69126.3-69267.6" + process $proc$libresoc.v:69126$3598 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:68398.5-68398.29" + attribute \src "libresoc.v:69127.5-69127.29" switch \initial - attribute \src "libresoc.v:68398.9-68398.17" + attribute \src "libresoc.v:69127.9-69127.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111692,7 +112761,7 @@ module \dec$202 case assign $1\cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111712,19 +112781,19 @@ module \dec$202 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:68539.3-68680.6" - process $proc$libresoc.v:68539$3564 + attribute \src "libresoc.v:69268.3-69409.6" + process $proc$libresoc.v:69268$3599 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:68540.5-68540.29" + attribute \src "libresoc.v:69269.5-69269.29" switch \initial - attribute \src "libresoc.v:68540.9-68540.17" + attribute \src "libresoc.v:69269.9-69269.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -111837,15 +112906,15 @@ module \dec$202 attribute \src "libresoc.v:0.0-0.0" case 6'010100 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010101 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'010111 assign { } { } - assign $1\cr_out[2:0] 3'000 + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" case 6'100110 assign { } { } @@ -111893,7 +112962,7 @@ module \dec$202 case assign $1\cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -111913,19 +112982,19 @@ module \dec$202 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:68681.3-68822.6" - process $proc$libresoc.v:68681$3565 + attribute \src "libresoc.v:69410.3-69551.6" + process $proc$libresoc.v:69410$3600 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:68682.5-68682.29" + attribute \src "libresoc.v:69411.5-69411.29" switch \initial - attribute \src "libresoc.v:68682.9-68682.17" + attribute \src "libresoc.v:69411.9-69411.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112094,7 +113163,7 @@ module \dec$202 case assign $1\ldst_len[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112114,19 +113183,19 @@ module \dec$202 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:68823.3-68964.6" - process $proc$libresoc.v:68823$3566 + attribute \src "libresoc.v:69552.3-69693.6" + process $proc$libresoc.v:69552$3601 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:68824.5-68824.29" + attribute \src "libresoc.v:69553.5-69553.29" switch \initial - attribute \src "libresoc.v:68824.9-68824.17" + attribute \src "libresoc.v:69553.9-69553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112295,7 +113364,7 @@ module \dec$202 case assign $1\upd[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112315,19 +113384,19 @@ module \dec$202 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:68965.3-69106.6" - process $proc$libresoc.v:68965$3567 + attribute \src "libresoc.v:69694.3-69835.6" + process $proc$libresoc.v:69694$3602 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:68966.5-68966.29" + attribute \src "libresoc.v:69695.5-69695.29" switch \initial - attribute \src "libresoc.v:68966.9-68966.17" + attribute \src "libresoc.v:69695.9-69695.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112496,7 +113565,7 @@ module \dec$202 case assign $1\rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112516,19 +113585,19 @@ module \dec$202 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:69107.3-69248.6" - process $proc$libresoc.v:69107$3568 + attribute \src "libresoc.v:69836.3-69977.6" + process $proc$libresoc.v:69836$3603 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:69108.5-69108.29" + attribute \src "libresoc.v:69837.5-69837.29" switch \initial - attribute \src "libresoc.v:69108.9-69108.17" + attribute \src "libresoc.v:69837.9-69837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112697,7 +113766,7 @@ module \dec$202 case assign $1\cry_in[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112717,19 +113786,19 @@ module \dec$202 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:69249.3-69390.6" - process $proc$libresoc.v:69249$3569 + attribute \src "libresoc.v:69978.3-70119.6" + process $proc$libresoc.v:69978$3604 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:69250.5-69250.29" + attribute \src "libresoc.v:69979.5-69979.29" switch \initial - attribute \src "libresoc.v:69250.9-69250.17" + attribute \src "libresoc.v:69979.9-69979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -112898,7 +113967,7 @@ module \dec$202 case assign $1\inv_a[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -112918,19 +113987,19 @@ module \dec$202 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:69391.3-69532.6" - process $proc$libresoc.v:69391$3570 + attribute \src "libresoc.v:70120.3-70261.6" + process $proc$libresoc.v:70120$3605 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:69392.5-69392.29" + attribute \src "libresoc.v:70121.5-70121.29" switch \initial - attribute \src "libresoc.v:69392.9-69392.17" + attribute \src "libresoc.v:70121.9-70121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113099,7 +114168,7 @@ module \dec$202 case assign $1\inv_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113119,19 +114188,19 @@ module \dec$202 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:69533.3-69674.6" - process $proc$libresoc.v:69533$3571 + attribute \src "libresoc.v:70262.3-70403.6" + process $proc$libresoc.v:70262$3606 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:69534.5-69534.29" + attribute \src "libresoc.v:70263.5-70263.29" switch \initial - attribute \src "libresoc.v:69534.9-69534.17" + attribute \src "libresoc.v:70263.9-70263.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113300,7 +114369,7 @@ module \dec$202 case assign $1\cry_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113320,19 +114389,19 @@ module \dec$202 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:69675.3-69816.6" - process $proc$libresoc.v:69675$3572 + attribute \src "libresoc.v:70404.3-70545.6" + process $proc$libresoc.v:70404$3607 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:69676.5-69676.29" + attribute \src "libresoc.v:70405.5-70405.29" switch \initial - attribute \src "libresoc.v:69676.9-69676.17" + attribute \src "libresoc.v:70405.9-70405.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113501,7 +114570,7 @@ module \dec$202 case assign $1\br[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113521,19 +114590,19 @@ module \dec$202 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:69817.3-69958.6" - process $proc$libresoc.v:69817$3573 + attribute \src "libresoc.v:70546.3-70687.6" + process $proc$libresoc.v:70546$3608 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:69818.5-69818.29" + attribute \src "libresoc.v:70547.5-70547.29" switch \initial - attribute \src "libresoc.v:69818.9-69818.17" + attribute \src "libresoc.v:70547.9-70547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113702,7 +114771,7 @@ module \dec$202 case assign $1\sgn_ext[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113722,19 +114791,19 @@ module \dec$202 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:69959.3-70100.6" - process $proc$libresoc.v:69959$3574 + attribute \src "libresoc.v:70688.3-70829.6" + process $proc$libresoc.v:70688$3609 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:69960.5-69960.29" + attribute \src "libresoc.v:70689.5-70689.29" switch \initial - attribute \src "libresoc.v:69960.9-69960.17" + attribute \src "libresoc.v:70689.9-70689.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -113903,7 +114972,7 @@ module \dec$202 case assign $1\rsrv[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -113923,19 +114992,19 @@ module \dec$202 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:70101.3-70242.6" - process $proc$libresoc.v:70101$3575 + attribute \src "libresoc.v:70830.3-70971.6" + process $proc$libresoc.v:70830$3610 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:70102.5-70102.29" + attribute \src "libresoc.v:70831.5-70831.29" switch \initial - attribute \src "libresoc.v:70102.9-70102.17" + attribute \src "libresoc.v:70831.9-70831.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114104,7 +115173,7 @@ module \dec$202 case assign $1\is_32b[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114124,19 +115193,19 @@ module \dec$202 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:70243.3-70384.6" - process $proc$libresoc.v:70243$3576 + attribute \src "libresoc.v:70972.3-71113.6" + process $proc$libresoc.v:70972$3611 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:70244.5-70244.29" + attribute \src "libresoc.v:70973.5-70973.29" switch \initial - attribute \src "libresoc.v:70244.9-70244.17" + attribute \src "libresoc.v:70973.9-70973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114305,7 +115374,7 @@ module \dec$202 case assign $1\sgn[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114325,19 +115394,19 @@ module \dec$202 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:70385.3-70526.6" - process $proc$libresoc.v:70385$3577 + attribute \src "libresoc.v:71114.3-71255.6" + process $proc$libresoc.v:71114$3612 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:70386.5-70386.29" + attribute \src "libresoc.v:71115.5-71115.29" switch \initial - attribute \src "libresoc.v:70386.9-70386.17" + attribute \src "libresoc.v:71115.9-71115.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114506,7 +115575,7 @@ module \dec$202 case assign $1\lk[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114526,19 +115595,19 @@ module \dec$202 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:70527.3-70668.6" - process $proc$libresoc.v:70527$3578 + attribute \src "libresoc.v:71256.3-71397.6" + process $proc$libresoc.v:71256$3613 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:70528.5-70528.29" + attribute \src "libresoc.v:71257.5-71257.29" switch \initial - attribute \src "libresoc.v:70528.9-70528.17" + attribute \src "libresoc.v:71257.9-71257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114707,7 +115776,7 @@ module \dec$202 case assign $1\sgl_pipe[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114727,19 +115796,19 @@ module \dec$202 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:70669.3-70810.6" - process $proc$libresoc.v:70669$3579 + attribute \src "libresoc.v:71398.3-71539.6" + process $proc$libresoc.v:71398$3614 assign { } { } assign { } { } assign { } { } assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "libresoc.v:70670.5-70670.29" + attribute \src "libresoc.v:71399.5-71399.29" switch \initial - attribute \src "libresoc.v:70670.9-70670.17" + attribute \src "libresoc.v:71399.9-71399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -114908,7 +115977,7 @@ module \dec$202 case assign $1\function_unit[11:0] 12'000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -114928,19 +115997,19 @@ module \dec$202 sync always update \function_unit $0\function_unit[11:0] end - attribute \src "libresoc.v:70811.3-70952.6" - process $proc$libresoc.v:70811$3580 + attribute \src "libresoc.v:71540.3-71681.6" + process $proc$libresoc.v:71540$3615 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:70812.5-70812.29" + attribute \src "libresoc.v:71541.5-71541.29" switch \initial - attribute \src "libresoc.v:70812.9-70812.17" + attribute \src "libresoc.v:71541.9-71541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115109,7 +116178,7 @@ module \dec$202 case assign $1\internal_op[6:0] 7'0000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115129,19 +116198,19 @@ module \dec$202 sync always update \internal_op $0\internal_op[6:0] end - attribute \src "libresoc.v:70953.3-71094.6" - process $proc$libresoc.v:70953$3581 + attribute \src "libresoc.v:71682.3-71823.6" + process $proc$libresoc.v:71682$3616 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:70954.5-70954.29" + attribute \src "libresoc.v:71683.5-71683.29" switch \initial - attribute \src "libresoc.v:70954.9-70954.17" + attribute \src "libresoc.v:71683.9-71683.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 6'010011 @@ -115310,7 +116379,7 @@ module \dec$202 case assign $1\form[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" case 32'000000---------------0100000000- @@ -115330,7 +116399,7 @@ module \dec$202 sync always update \form $0\form[4:0] end - connect \$2 $ternary$libresoc.v:67554$3557_Y + connect \$2 $ternary$libresoc.v:68283$3592_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -115666,112 +116735,112 @@ module \dec$202 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:71433.1-72940.10" +attribute \src "libresoc.v:72162.1-73669.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:71951.3-72002.6" + attribute \src "libresoc.v:72680.3-72731.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:72159.3-72210.6" + attribute \src "libresoc.v:72888.3-72939.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:72835.3-72886.6" + attribute \src "libresoc.v:73564.3-73615.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:72887.3-72938.6" + attribute \src "libresoc.v:73616.3-73667.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:71899.3-71950.6" + attribute \src "libresoc.v:72628.3-72679.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:72107.3-72158.6" + attribute \src "libresoc.v:72836.3-72887.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:72575.3-72626.6" + attribute \src "libresoc.v:73304.3-73355.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:71691.3-71742.6" + attribute \src "libresoc.v:72420.3-72471.6" wire width 12 $0\dec19_function_unit[11:0] - attribute \src "libresoc.v:72627.3-72678.6" + attribute \src "libresoc.v:73356.3-73407.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:72679.3-72730.6" + attribute \src "libresoc.v:73408.3-73459.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:72731.3-72782.6" + attribute \src "libresoc.v:73460.3-73511.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72263.3-72314.6" + attribute \src "libresoc.v:72992.3-73043.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:72003.3-72054.6" + attribute \src "libresoc.v:72732.3-72783.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:72055.3-72106.6" + attribute \src "libresoc.v:72784.3-72835.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:72367.3-72418.6" + attribute \src "libresoc.v:73096.3-73147.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:71743.3-71794.6" + attribute \src "libresoc.v:72472.3-72523.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:72471.3-72522.6" + attribute \src "libresoc.v:73200.3-73251.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:72783.3-72834.6" + attribute \src "libresoc.v:73512.3-73563.6" wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:71847.3-71898.6" + attribute \src "libresoc.v:72576.3-72627.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72315.3-72366.6" + attribute \src "libresoc.v:73044.3-73095.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:72523.3-72574.6" + attribute \src "libresoc.v:73252.3-73303.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:72419.3-72470.6" + attribute \src "libresoc.v:73148.3-73199.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:72211.3-72262.6" + attribute \src "libresoc.v:72940.3-72991.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:71795.3-71846.6" + attribute \src "libresoc.v:72524.3-72575.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:71434.7-71434.20" + attribute \src "libresoc.v:72163.7-72163.20" wire $0\initial[0:0] - attribute \src "libresoc.v:71951.3-72002.6" + attribute \src "libresoc.v:72680.3-72731.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:72159.3-72210.6" + attribute \src "libresoc.v:72888.3-72939.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:72835.3-72886.6" + attribute \src "libresoc.v:73564.3-73615.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:72887.3-72938.6" + attribute \src "libresoc.v:73616.3-73667.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:71899.3-71950.6" + attribute \src "libresoc.v:72628.3-72679.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:72107.3-72158.6" + attribute \src "libresoc.v:72836.3-72887.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:72575.3-72626.6" + attribute \src "libresoc.v:73304.3-73355.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:71691.3-71742.6" + attribute \src "libresoc.v:72420.3-72471.6" wire width 12 $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:72627.3-72678.6" + attribute \src "libresoc.v:73356.3-73407.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:72679.3-72730.6" + attribute \src "libresoc.v:73408.3-73459.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:72731.3-72782.6" + attribute \src "libresoc.v:73460.3-73511.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72263.3-72314.6" + attribute \src "libresoc.v:72992.3-73043.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72003.3-72054.6" + attribute \src "libresoc.v:72732.3-72783.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72055.3-72106.6" + attribute \src "libresoc.v:72784.3-72835.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:72367.3-72418.6" + attribute \src "libresoc.v:73096.3-73147.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:71743.3-71794.6" + attribute \src "libresoc.v:72472.3-72523.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:72471.3-72522.6" + attribute \src "libresoc.v:73200.3-73251.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:72783.3-72834.6" + attribute \src "libresoc.v:73512.3-73563.6" wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:71847.3-71898.6" + attribute \src "libresoc.v:72576.3-72627.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72315.3-72366.6" + attribute \src "libresoc.v:73044.3-73095.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:72523.3-72574.6" + attribute \src "libresoc.v:73252.3-73303.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:72419.3-72470.6" + attribute \src "libresoc.v:73148.3-73199.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:72211.3-72262.6" + attribute \src "libresoc.v:72940.3-72991.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:71795.3-71846.6" + attribute \src "libresoc.v:72524.3-72575.6" wire width 2 $1\dec19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -115781,7 +116850,7 @@ module \dec19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -115789,15 +116858,15 @@ module \dec19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -115829,7 +116898,7 @@ module \dec19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -115844,7 +116913,7 @@ module \dec19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -115852,7 +116921,7 @@ module \dec19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -115869,13 +116938,13 @@ module \dec19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -115951,13 +117020,13 @@ module \dec19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -115965,64 +117034,64 @@ module \dec19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec19_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec19_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec19_upd - attribute \src "libresoc.v:71434.7-71434.15" + attribute \src "libresoc.v:72163.7-72163.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch - attribute \src "libresoc.v:71434.7-71434.20" - process $proc$libresoc.v:71434$3607 + attribute \src "libresoc.v:72163.7-72163.20" + process $proc$libresoc.v:72163$3642 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:71691.3-71742.6" - process $proc$libresoc.v:71691$3583 + attribute \src "libresoc.v:72420.3-72471.6" + process $proc$libresoc.v:72420$3618 assign { } { } assign { } { } assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:71692.5-71692.29" + attribute \src "libresoc.v:72421.5-72421.29" switch \initial - attribute \src "libresoc.v:71692.9-71692.17" + attribute \src "libresoc.v:72421.9-72421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116090,18 +117159,18 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[11:0] end - attribute \src "libresoc.v:71743.3-71794.6" - process $proc$libresoc.v:71743$3584 + attribute \src "libresoc.v:72472.3-72523.6" + process $proc$libresoc.v:72472$3619 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:71744.5-71744.29" + attribute \src "libresoc.v:72473.5-72473.29" switch \initial - attribute \src "libresoc.v:71744.9-71744.17" + attribute \src "libresoc.v:72473.9-72473.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116169,18 +117238,18 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:71795.3-71846.6" - process $proc$libresoc.v:71795$3585 + attribute \src "libresoc.v:72524.3-72575.6" + process $proc$libresoc.v:72524$3620 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:71796.5-71796.29" + attribute \src "libresoc.v:72525.5-72525.29" switch \initial - attribute \src "libresoc.v:71796.9-71796.17" + attribute \src "libresoc.v:72525.9-72525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116248,18 +117317,18 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:71847.3-71898.6" - process $proc$libresoc.v:71847$3586 + attribute \src "libresoc.v:72576.3-72627.6" + process $proc$libresoc.v:72576$3621 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:71848.5-71848.29" + attribute \src "libresoc.v:72577.5-72577.29" switch \initial - attribute \src "libresoc.v:71848.9-71848.17" + attribute \src "libresoc.v:72577.9-72577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116327,18 +117396,18 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:71899.3-71950.6" - process $proc$libresoc.v:71899$3587 + attribute \src "libresoc.v:72628.3-72679.6" + process $proc$libresoc.v:72628$3622 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:71900.5-71900.29" + attribute \src "libresoc.v:72629.5-72629.29" switch \initial - attribute \src "libresoc.v:71900.9-71900.17" + attribute \src "libresoc.v:72629.9-72629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116406,18 +117475,18 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:71951.3-72002.6" - process $proc$libresoc.v:71951$3588 + attribute \src "libresoc.v:72680.3-72731.6" + process $proc$libresoc.v:72680$3623 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:71952.5-71952.29" + attribute \src "libresoc.v:72681.5-72681.29" switch \initial - attribute \src "libresoc.v:71952.9-71952.17" + attribute \src "libresoc.v:72681.9-72681.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116485,18 +117554,18 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:72003.3-72054.6" - process $proc$libresoc.v:72003$3589 + attribute \src "libresoc.v:72732.3-72783.6" + process $proc$libresoc.v:72732$3624 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72004.5-72004.29" + attribute \src "libresoc.v:72733.5-72733.29" switch \initial - attribute \src "libresoc.v:72004.9-72004.17" + attribute \src "libresoc.v:72733.9-72733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116564,18 +117633,18 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:72055.3-72106.6" - process $proc$libresoc.v:72055$3590 + attribute \src "libresoc.v:72784.3-72835.6" + process $proc$libresoc.v:72784$3625 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:72056.5-72056.29" + attribute \src "libresoc.v:72785.5-72785.29" switch \initial - attribute \src "libresoc.v:72056.9-72056.17" + attribute \src "libresoc.v:72785.9-72785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116643,18 +117712,18 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:72107.3-72158.6" - process $proc$libresoc.v:72107$3591 + attribute \src "libresoc.v:72836.3-72887.6" + process $proc$libresoc.v:72836$3626 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:72108.5-72108.29" + attribute \src "libresoc.v:72837.5-72837.29" switch \initial - attribute \src "libresoc.v:72108.9-72108.17" + attribute \src "libresoc.v:72837.9-72837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116722,18 +117791,18 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:72159.3-72210.6" - process $proc$libresoc.v:72159$3592 + attribute \src "libresoc.v:72888.3-72939.6" + process $proc$libresoc.v:72888$3627 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:72160.5-72160.29" + attribute \src "libresoc.v:72889.5-72889.29" switch \initial - attribute \src "libresoc.v:72160.9-72160.17" + attribute \src "libresoc.v:72889.9-72889.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116801,18 +117870,18 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:72211.3-72262.6" - process $proc$libresoc.v:72211$3593 + attribute \src "libresoc.v:72940.3-72991.6" + process $proc$libresoc.v:72940$3628 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72212.5-72212.29" + attribute \src "libresoc.v:72941.5-72941.29" switch \initial - attribute \src "libresoc.v:72212.9-72212.17" + attribute \src "libresoc.v:72941.9-72941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116880,18 +117949,18 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:72263.3-72314.6" - process $proc$libresoc.v:72263$3594 + attribute \src "libresoc.v:72992.3-73043.6" + process $proc$libresoc.v:72992$3629 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72264.5-72264.29" + attribute \src "libresoc.v:72993.5-72993.29" switch \initial - attribute \src "libresoc.v:72264.9-72264.17" + attribute \src "libresoc.v:72993.9-72993.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -116959,18 +118028,18 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:72315.3-72366.6" - process $proc$libresoc.v:72315$3595 + attribute \src "libresoc.v:73044.3-73095.6" + process $proc$libresoc.v:73044$3630 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:72316.5-72316.29" + attribute \src "libresoc.v:73045.5-73045.29" switch \initial - attribute \src "libresoc.v:72316.9-72316.17" + attribute \src "libresoc.v:73045.9-73045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117038,18 +118107,18 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:72367.3-72418.6" - process $proc$libresoc.v:72367$3596 + attribute \src "libresoc.v:73096.3-73147.6" + process $proc$libresoc.v:73096$3631 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:72368.5-72368.29" + attribute \src "libresoc.v:73097.5-73097.29" switch \initial - attribute \src "libresoc.v:72368.9-72368.17" + attribute \src "libresoc.v:73097.9-73097.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117117,18 +118186,18 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:72419.3-72470.6" - process $proc$libresoc.v:72419$3597 + attribute \src "libresoc.v:73148.3-73199.6" + process $proc$libresoc.v:73148$3632 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:72420.5-72420.29" + attribute \src "libresoc.v:73149.5-73149.29" switch \initial - attribute \src "libresoc.v:72420.9-72420.17" + attribute \src "libresoc.v:73149.9-73149.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117196,18 +118265,18 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:72471.3-72522.6" - process $proc$libresoc.v:72471$3598 + attribute \src "libresoc.v:73200.3-73251.6" + process $proc$libresoc.v:73200$3633 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:72472.5-72472.29" + attribute \src "libresoc.v:73201.5-73201.29" switch \initial - attribute \src "libresoc.v:72472.9-72472.17" + attribute \src "libresoc.v:73201.9-73201.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117275,18 +118344,18 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:72523.3-72574.6" - process $proc$libresoc.v:72523$3599 + attribute \src "libresoc.v:73252.3-73303.6" + process $proc$libresoc.v:73252$3634 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:72524.5-72524.29" + attribute \src "libresoc.v:73253.5-73253.29" switch \initial - attribute \src "libresoc.v:72524.9-72524.17" + attribute \src "libresoc.v:73253.9-73253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117354,18 +118423,18 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:72575.3-72626.6" - process $proc$libresoc.v:72575$3600 + attribute \src "libresoc.v:73304.3-73355.6" + process $proc$libresoc.v:73304$3635 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:72576.5-72576.29" + attribute \src "libresoc.v:73305.5-73305.29" switch \initial - attribute \src "libresoc.v:72576.9-72576.17" + attribute \src "libresoc.v:73305.9-73305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117433,18 +118502,18 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:72627.3-72678.6" - process $proc$libresoc.v:72627$3601 + attribute \src "libresoc.v:73356.3-73407.6" + process $proc$libresoc.v:73356$3636 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:72628.5-72628.29" + attribute \src "libresoc.v:73357.5-73357.29" switch \initial - attribute \src "libresoc.v:72628.9-72628.17" + attribute \src "libresoc.v:73357.9-73357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117512,18 +118581,18 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:72679.3-72730.6" - process $proc$libresoc.v:72679$3602 + attribute \src "libresoc.v:73408.3-73459.6" + process $proc$libresoc.v:73408$3637 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:72680.5-72680.29" + attribute \src "libresoc.v:73409.5-73409.29" switch \initial - attribute \src "libresoc.v:72680.9-72680.17" + attribute \src "libresoc.v:73409.9-73409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117591,18 +118660,18 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:72731.3-72782.6" - process $proc$libresoc.v:72731$3603 + attribute \src "libresoc.v:73460.3-73511.6" + process $proc$libresoc.v:73460$3638 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72732.5-72732.29" + attribute \src "libresoc.v:73461.5-73461.29" switch \initial - attribute \src "libresoc.v:72732.9-72732.17" + attribute \src "libresoc.v:73461.9-73461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117670,18 +118739,18 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:72783.3-72834.6" - process $proc$libresoc.v:72783$3604 + attribute \src "libresoc.v:73512.3-73563.6" + process $proc$libresoc.v:73512$3639 assign { } { } assign { } { } assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:72784.5-72784.29" + attribute \src "libresoc.v:73513.5-73513.29" switch \initial - attribute \src "libresoc.v:72784.9-72784.17" + attribute \src "libresoc.v:73513.9-73513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117749,18 +118818,18 @@ module \dec19 sync always update \dec19_out_sel $0\dec19_out_sel[1:0] end - attribute \src "libresoc.v:72835.3-72886.6" - process $proc$libresoc.v:72835$3605 + attribute \src "libresoc.v:73564.3-73615.6" + process $proc$libresoc.v:73564$3640 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:72836.5-72836.29" + attribute \src "libresoc.v:73565.5-73565.29" switch \initial - attribute \src "libresoc.v:72836.9-72836.17" + attribute \src "libresoc.v:73565.9-73565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117828,18 +118897,18 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:72887.3-72938.6" - process $proc$libresoc.v:72887$3606 + attribute \src "libresoc.v:73616.3-73667.6" + process $proc$libresoc.v:73616$3641 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:72888.5-72888.29" + attribute \src "libresoc.v:73617.5-73617.29" switch \initial - attribute \src "libresoc.v:72888.9-72888.17" + attribute \src "libresoc.v:73617.9-73617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 10'0000000000 @@ -117909,388 +118978,790 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:72944.1-74833.10" +attribute \src "libresoc.v:73673.1-75710.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2" +attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\cr_in1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire width 3 $0\cr_in2$1[2:0]$3626 - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $0\cr_in2$1[2:0]$3661 + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\cr_in2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire $0\cr_in2_ok$2[0:0]$3627 - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\cr_in2_ok$2[0:0]$3662 + attribute \src "libresoc.v:75484.3-75641.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $0\ea[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$3[0:0]$3664 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$4[0:0]$3665 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$5[0:0]$3666 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$6[0:0]$3667 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$7[0:0]$3668 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$8[0:0]$3669 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal$9[0:0]$3670 + attribute \src "libresoc.v:75484.3-75641.6" + wire $0\exc_$signal[0:0]$3663 + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 12 $0\fn_unit[11:0] - attribute \src "libresoc.v:72945.7-72945.20" + attribute \src "libresoc.v:73674.7-73674.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:74679.3-74698.6" + attribute \src "libresoc.v:75464.3-75483.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\lk[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\oe[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\rc[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $0\reg1[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $0\reg2[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $0\reg3[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $0\rego[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:74633.3-74642.6" + attribute \src "libresoc.v:75418.3-75427.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:74669.3-74678.6" + attribute \src "libresoc.v:75454.3-75463.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:74643.3-74658.6" + attribute \src "libresoc.v:75428.3-75443.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:74659.3-74668.6" + attribute \src "libresoc.v:75444.3-75453.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire width 7 $0\traptype[6:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\cr_in1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire width 3 $1\cr_in2$1[2:0]$3628 - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $1\cr_in2$1[2:0]$3671 + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\cr_in2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire $1\cr_in2_ok$2[0:0]$3629 - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\cr_in2_ok$2[0:0]$3672 + attribute \src "libresoc.v:75484.3-75641.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $1\ea[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$3[0:0]$3674 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$4[0:0]$3675 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$5[0:0]$3676 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$6[0:0]$3677 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$7[0:0]$3678 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$8[0:0]$3679 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal$9[0:0]$3680 + attribute \src "libresoc.v:75484.3-75641.6" + wire $1\exc_$signal[0:0]$3673 + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 12 $1\fn_unit[11:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:74679.3-74698.6" + attribute \src "libresoc.v:75464.3-75483.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\lk[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\oe[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\rc[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $1\reg1[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $1\reg2[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $1\reg3[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 5 $1\rego[4:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:74633.3-74642.6" + attribute \src "libresoc.v:75418.3-75427.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:74669.3-74678.6" + attribute \src "libresoc.v:75454.3-75463.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:74643.3-74658.6" + attribute \src "libresoc.v:75428.3-75443.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:74659.3-74668.6" + attribute \src "libresoc.v:75444.3-75453.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:74699.3-74780.6" - wire width 7 $1\traptype[6:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:75484.3-75641.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:74699.3-74780.6" + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $2\cr_in1[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $2\cr_in2$1[2:0]$3681 + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $2\cr_in2[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_in2_ok$2[0:0]$3682 + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $2\ea[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\exc_$signal$3[0:0]$3684 + attribute \src "libresoc.v:75484.3-75641.6" + wire $2\exc_$signal$4[0:0]$3685 + attribute \src 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attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $4\cr_rd[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\cr_rd_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $4\cr_wr[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\cr_wr_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $4\ea[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\ea_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$3[0:0]$3704 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$4[0:0]$3705 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$5[0:0]$3706 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$6[0:0]$3707 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$7[0:0]$3708 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$8[0:0]$3709 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal$9[0:0]$3710 + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\exc_$signal[0:0]$3703 + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $4\fast1[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\fast1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $4\fast2[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\fast2_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $4\fasto1[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\fasto1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $4\fasto2[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\fasto2_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 12 $4\fn_unit[11:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 2 $4\input_carry[1:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 32 $4\insn[31:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 7 $4\insn_type[6:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\is_32bit[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\lk[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 64 $4\msr[63:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\oe[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\oe_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\rc[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\rc_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $4\reg1[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\reg1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $4\reg2[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\reg2_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $4\reg3[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\reg3_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 5 $4\rego[4:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\rego_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 10 $4\spr1[9:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\spr1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 10 $4\spro[9:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\spro_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 13 $4\trapaddr[12:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 8 $4\traptype[7:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $4\xer_in[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $4\xer_out[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $5\fast1[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $5\fast1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $5\fast2[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $5\fast2_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $5\fasto1[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $5\fasto1_ok[0:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire width 3 $5\fasto2[2:0] + attribute \src "libresoc.v:75484.3-75641.6" + wire $5\fasto2_ok[0:0] + attribute \src "libresoc.v:75273.18-75273.120" + wire $and$libresoc.v:75273$3651_Y + attribute \src "libresoc.v:75274.18-75274.123" + wire $and$libresoc.v:75274$3652_Y + attribute \src "libresoc.v:75275.18-75275.124" + wire $and$libresoc.v:75275$3653_Y + attribute \src "libresoc.v:75265.18-75265.116" + wire $eq$libresoc.v:75265$3643_Y + attribute \src "libresoc.v:75266.18-75266.116" + wire $eq$libresoc.v:75266$3644_Y + attribute \src "libresoc.v:75268.18-75268.116" + wire $eq$libresoc.v:75268$3646_Y + attribute \src "libresoc.v:75269.18-75269.122" + wire $eq$libresoc.v:75269$3647_Y + attribute \src "libresoc.v:75270.18-75270.122" + wire $eq$libresoc.v:75270$3648_Y + attribute \src "libresoc.v:75271.18-75271.122" + wire $eq$libresoc.v:75271$3649_Y + attribute \src "libresoc.v:75272.18-75272.122" + wire $eq$libresoc.v:75272$3650_Y + attribute \src "libresoc.v:75276.18-75276.122" + wire $eq$libresoc.v:75276$3654_Y + attribute \src "libresoc.v:75267.18-75267.110" + wire $or$libresoc.v:75267$3645_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + wire \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 output 5 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 output 39 \cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 30 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 31 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 32 \cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 34 \cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 36 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 37 \cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 51 \cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 52 \cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 53 \cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 54 \cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 59 \cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 60 \cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 61 \cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 input 56 \cur_dec + wire width 64 input 64 \cur_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire input 57 \cur_eint + wire input 65 \cur_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" wire width 64 input 3 \cur_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 input 2 \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 \dec_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 \dec_XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_a_fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_fast_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_a_reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_reg_a_ok attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -118298,7 +119769,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -118411,19 +119882,19 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \dec_a_spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_b_fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_b_reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -118440,17 +119911,17 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_c_reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -118460,25 +119931,25 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \dec_cr_in_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -118488,7 +119959,7 @@ module \dec2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -118496,19 +119967,19 @@ module \dec2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \dec_cr_out_cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -118516,13 +119987,13 @@ module \dec2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_cry_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -118537,7 +120008,7 @@ module \dec2 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -118545,7 +120016,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -118562,13 +120033,13 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -118644,38 +120115,38 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:885" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904" wire \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_o2_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" wire \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o2_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o_reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" wire width 2 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -118788,73 +120259,89 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_rc_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 8 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 9 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 50 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 51 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" wire \ext_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 22 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 24 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 26 \fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 28 \fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -118869,34 +120356,34 @@ module \dec2 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 output 42 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" wire \illeg_ok - attribute \src "libresoc.v:72945.7-72945.15" + attribute \src "libresoc.v:73674.7-73674.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 output 48 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 40 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - wire width 32 \insn_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" - wire width 32 \insn_in$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" - wire width 32 \insn_in$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - wire width 32 \insn_in$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" - wire width 32 \insn_in$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" - wire width 32 \insn_in$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 32 \insn_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" + wire width 32 \insn_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" + wire width 32 \insn_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" + wire width 32 \insn_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" + wire width 32 \insn_in$41 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -118971,50 +120458,50 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 output 41 \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire output 55 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 63 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" wire \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 43 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" wire \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 4 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 10 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 11 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 12 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 13 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 14 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 15 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 6 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \rego_ok attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" wire width 2 \sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -119127,9 +120614,9 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 18 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -119242,63 +120729,63 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 16 \spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \tmp_cr_in2_ok$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \tmp_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \tmp_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \tmp_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \tmp_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \tmp_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \tmp_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -119411,9 +120898,9 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \tmp_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -119526,20 +121013,36 @@ module \dec2 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \tmp_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \tmp_tmp_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \tmp_tmp_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \tmp_tmp_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$27 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -119553,15 +121056,15 @@ module \dec2 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 \tmp_tmp_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 \tmp_tmp_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 \tmp_tmp_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -119637,40 +121140,40 @@ module \dec2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \tmp_tmp_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire \tmp_tmp_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire \tmp_tmp_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 \tmp_tmp_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \tmp_tmp_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 output 58 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 output 50 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 output 49 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 8 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 output 20 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - cell $and $and$libresoc.v:74484$3612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" + cell $and $and$libresoc.v:75273$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -119678,10 +121181,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:74484$3612_Y + connect \Y $and$libresoc.v:75273$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:890" - cell $and $and$libresoc.v:74485$3613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + cell $and $and$libresoc.v:75274$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -119689,10 +121192,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:74485$3613_Y + connect \Y $and$libresoc.v:75274$3652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:891" - cell $and $and$libresoc.v:74486$3614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + cell $and $and$libresoc.v:75275$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -119700,110 +121203,110 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:74486$3614_Y + connect \Y $and$libresoc.v:75275$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" - cell $eq $eq$libresoc.v:74480$3608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" + cell $eq $eq$libresoc.v:75265$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $eq$libresoc.v:74480$3608_Y + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:75265$3643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" - cell $eq $eq$libresoc.v:74481$3609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $eq $eq$libresoc.v:75266$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0001010 - connect \Y $eq$libresoc.v:74481$3609_Y + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:75266$3644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" - cell $eq $eq$libresoc.v:74482$3610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + cell $eq $eq$libresoc.v:75268$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:74482$3610_Y + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:75268$3646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" - cell $eq $eq$libresoc.v:74483$3611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + cell $eq $eq$libresoc.v:75269$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $eq$libresoc.v:74483$3611_Y + connect \B 7'0101110 + connect \Y $eq$libresoc.v:75269$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - cell $eq $eq$libresoc.v:74487$3615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + cell $eq $eq$libresoc.v:75270$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$libresoc.v:74487$3615_Y + connect \B 7'0001010 + connect \Y $eq$libresoc.v:75270$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:923" - cell $eq $eq$libresoc.v:74488$3616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + cell $eq $eq$libresoc.v:75271$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$libresoc.v:74488$3616_Y + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:75271$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - cell $eq $eq$libresoc.v:74489$3617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $eq $eq$libresoc.v:75272$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$libresoc.v:74489$3617_Y + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:75272$3650_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" - cell $eq $eq$libresoc.v:74491$3619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" + cell $eq $eq$libresoc.v:75276$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$libresoc.v:74491$3619_Y + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:75276$3654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - cell $or $or$libresoc.v:74490$3618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $or $or$libresoc.v:75267$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \$31 - connect \Y $or$libresoc.v:74490$3618_Y + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:75267$3645_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:74492.13-74529.4" - cell \dec$202 \dec + attribute \src "libresoc.v:75277.13-75314.4" + cell \dec$205 \dec connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -119842,7 +121345,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:74530.9-74544.4" + attribute \src "libresoc.v:75315.9-75329.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -119859,7 +121362,7 @@ module \dec2 connect \spr_a_ok \dec_a_spr_a_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:74545.9-74555.4" + attribute \src "libresoc.v:75330.9-75340.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -119872,7 +121375,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:74556.9-74562.4" + attribute \src "libresoc.v:75341.9-75347.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -119881,8 +121384,8 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:74563.19-74582.4" - cell \dec_cr_in$205 \dec_cr_in$3 + attribute \src "libresoc.v:75348.19-75367.4" + cell \dec_cr_in$208 \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -119903,8 +121406,8 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:74583.20-74595.4" - cell \dec_cr_out$207 \dec_cr_out$4 + attribute \src "libresoc.v:75368.20-75380.4" + cell \dec_cr_out$210 \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT connect \X_BF \dec_X_BF @@ -119918,7 +121421,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:74596.9-74609.4" + attribute \src "libresoc.v:75381.9-75394.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -119934,7 +121437,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:74610.10-74619.4" + attribute \src "libresoc.v:75395.10-75404.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o \dec_o2_fast_o @@ -119946,8 +121449,8 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:74620.16-74626.4" - cell \dec_oe$204 \dec_oe + attribute \src "libresoc.v:75405.16-75411.4" + cell \dec_oe$207 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op connect \oe \dec_oe_oe @@ -119955,33 +121458,33 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:74627.16-74632.4" - cell \dec_rc$203 \dec_rc + attribute \src "libresoc.v:75412.16-75417.4" + cell \dec_rc$206 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:72945.7-72945.20" - process $proc$libresoc.v:72945$3630 + attribute \src "libresoc.v:73674.7-73674.20" + process $proc$libresoc.v:73674$3711 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:74633.3-74642.6" - process $proc$libresoc.v:74633$3620 + attribute \src "libresoc.v:75418.3-75427.6" + process $proc$libresoc.v:75418$3655 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:74634.5-74634.29" + attribute \src "libresoc.v:75419.5-75419.29" switch \initial - attribute \src "libresoc.v:74634.9-74634.17" + attribute \src "libresoc.v:75419.9-75419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -119993,20 +121496,20 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:74643.3-74658.6" - process $proc$libresoc.v:74643$3621 + attribute \src "libresoc.v:75428.3-75443.6" + process $proc$libresoc.v:75428$3656 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:74644.5-74644.29" + attribute \src "libresoc.v:75429.5-75429.29" switch \initial - attribute \src "libresoc.v:74644.9-74644.17" + attribute \src "libresoc.v:75429.9-75429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:859" - switch \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -120014,8 +121517,8 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:861" - switch \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -120026,19 +121529,19 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:74659.3-74668.6" - process $proc$libresoc.v:74659$3622 + attribute \src "libresoc.v:75444.3-75453.6" + process $proc$libresoc.v:75444$3657 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:74660.5-74660.29" + attribute \src "libresoc.v:75445.5-75445.29" switch \initial - attribute \src "libresoc.v:74660.9-74660.17" + attribute \src "libresoc.v:75445.9-75445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:863" - switch \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -120049,19 +121552,19 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:74669.3-74678.6" - process $proc$libresoc.v:74669$3623 + attribute \src "libresoc.v:75454.3-75463.6" + process $proc$libresoc.v:75454$3658 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:74670.5-74670.29" + attribute \src "libresoc.v:75455.5-75455.29" switch \initial - attribute \src "libresoc.v:74670.9-74670.17" + attribute \src "libresoc.v:75455.9-75455.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:867" - switch \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -120072,18 +121575,18 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:74679.3-74698.6" - process $proc$libresoc.v:74679$3624 + attribute \src "libresoc.v:75464.3-75483.6" + process $proc$libresoc.v:75464$3659 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:74680.5-74680.29" + attribute \src "libresoc.v:75465.5-75465.29" switch \initial - attribute \src "libresoc.v:74680.9-74680.17" + attribute \src "libresoc.v:75465.9-75465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 @@ -120093,7 +121596,7 @@ module \dec2 case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -120108,8 +121611,16 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:74699.3-74780.6" - process $proc$libresoc.v:74699$3625 + attribute \src "libresoc.v:75484.3-75641.6" + process $proc$libresoc.v:75484$3660 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -120178,14 +121689,22 @@ module \dec2 assign $0\cr_in1[2:0] $1\cr_in1[2:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$3626 $1\cr_in2$1[2:0]$3628 + assign $0\cr_in2$1[2:0]$3661 $1\cr_in2$1[2:0]$3671 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3627 $1\cr_in2_ok$2[0:0]$3629 + assign $0\cr_in2_ok$2[0:0]$3662 $1\cr_in2_ok$2[0:0]$3672 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\exc_$signal[0:0]$3663 $1\exc_$signal[0:0]$3673 + assign $0\exc_$signal$3[0:0]$3664 $1\exc_$signal$3[0:0]$3674 + assign $0\exc_$signal$4[0:0]$3665 $1\exc_$signal$4[0:0]$3675 + assign $0\exc_$signal$5[0:0]$3666 $1\exc_$signal$5[0:0]$3676 + assign $0\exc_$signal$6[0:0]$3667 $1\exc_$signal$6[0:0]$3677 + assign $0\exc_$signal$7[0:0]$3668 $1\exc_$signal$7[0:0]$3678 + assign $0\exc_$signal$8[0:0]$3669 $1\exc_$signal$8[0:0]$3679 + assign $0\exc_$signal$9[0:0]$3670 $1\exc_$signal$9[0:0]$3680 assign { } { } assign { } { } assign { } { } @@ -120209,28 +121728,28 @@ module \dec2 assign $0\spro[9:0] $1\spro[9:0] assign $0\spro_ok[0:0] $1\spro_ok[0:0] assign $0\trapaddr[12:0] $1\trapaddr[12:0] - assign $0\traptype[6:0] $1\traptype[6:0] + assign $0\traptype[7:0] $1\traptype[7:0] assign $0\xer_in[2:0] $1\xer_in[2:0] assign $0\xer_out[0:0] $1\xer_out[0:0] - assign $0\fasto1[2:0] $2\fasto1[2:0] - assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] - assign $0\fasto2[2:0] $2\fasto2[2:0] - assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $0\fast1[2:0] $2\fast1[2:0] - assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] - assign $0\fast2[2:0] $2\fast2[2:0] - assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:74700.5-74700.29" + attribute \src "libresoc.v:75485.5-75485.29" switch \initial - attribute \src "libresoc.v:74700.9-74700.17" + attribute \src "libresoc.v:75485.9-75485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:895" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" - case 4'---1 + case 5'----1 assign { } { } assign { } { } assign { } { } @@ -120282,16 +121801,6 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000010010000 - assign $1\traptype[6:0] 7'0100000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'--1- assign { } { } assign { } { } assign { } { } @@ -120300,6 +121809,662 @@ module \dec2 assign { } { } assign { } { } assign { } { } + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\ea[4:0] $2\ea[4:0] + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\cr_out[2:0] $2\cr_out[2:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[2:0] $2\cr_in1[2:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[2:0] $2\cr_in2[2:0] + assign $1\cr_in2$1[2:0]$3671 $2\cr_in2$1[2:0]$3681 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$3672 $2\cr_in2_ok$2[0:0]$3682 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\exc_$signal[0:0]$3673 $2\exc_$signal[0:0]$3683 + assign $1\exc_$signal$3[0:0]$3674 $2\exc_$signal$3[0:0]$3684 + assign $1\exc_$signal$4[0:0]$3675 $2\exc_$signal$4[0:0]$3685 + assign $1\exc_$signal$5[0:0]$3676 $2\exc_$signal$5[0:0]$3686 + assign $1\exc_$signal$6[0:0]$3677 $2\exc_$signal$6[0:0]$3687 + assign $1\exc_$signal$7[0:0]$3678 $2\exc_$signal$7[0:0]$3688 + assign $1\exc_$signal$8[0:0]$3679 $2\exc_$signal$8[0:0]$3689 + assign $1\exc_$signal$9[0:0]$3680 $2\exc_$signal$9[0:0]$3690 + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[11:0] $2\fn_unit[11:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[4:0] $2\reg1[4:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[4:0] $2\reg2[4:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[4:0] $2\reg3[4:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[4:0] $2\rego[4:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3690 $2\exc_$signal$8[0:0]$3689 $2\exc_$signal$7[0:0]$3688 $2\exc_$signal$6[0:0]$3687 $2\exc_$signal$5[0:0]$3686 $2\exc_$signal$4[0:0]$3685 $2\exc_$signal$3[0:0]$3684 $2\exc_$signal[0:0]$3683 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$3682 $2\cr_in2$1[2:0]$3681 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[11:0] 12'000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\ea[4:0] $3\ea[4:0] + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\cr_out[2:0] $3\cr_out[2:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[2:0] $3\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $3\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$3681 $3\cr_in2$1[2:0]$3691 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3682 $3\cr_in2_ok$2[0:0]$3692 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3683 $3\exc_$signal[0:0]$3693 + assign $2\exc_$signal$3[0:0]$3684 $3\exc_$signal$3[0:0]$3694 + assign $2\exc_$signal$4[0:0]$3685 $3\exc_$signal$4[0:0]$3695 + assign $2\exc_$signal$5[0:0]$3686 $3\exc_$signal$5[0:0]$3696 + assign $2\exc_$signal$6[0:0]$3687 $3\exc_$signal$6[0:0]$3697 + assign $2\exc_$signal$7[0:0]$3688 $3\exc_$signal$7[0:0]$3698 + assign $2\exc_$signal$8[0:0]$3689 $3\exc_$signal$8[0:0]$3699 + assign $2\exc_$signal$9[0:0]$3690 $3\exc_$signal$9[0:0]$3700 + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $3\fn_unit[11:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[4:0] $3\reg1[4:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[4:0] $3\reg2[4:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[4:0] $3\reg3[4:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[4:0] $3\rego[4:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3700 $3\exc_$signal$8[0:0]$3699 $3\exc_$signal$7[0:0]$3698 $3\exc_$signal$6[0:0]$3697 $3\exc_$signal$5[0:0]$3696 $3\exc_$signal$4[0:0]$3695 $3\exc_$signal$3[0:0]$3694 $3\exc_$signal[0:0]$3693 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3692 $3\cr_in2$1[2:0]$3691 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3692 $3\cr_in2$1[2:0]$3691 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$3700 $3\exc_$signal$8[0:0]$3699 $3\exc_$signal$7[0:0]$3698 $3\exc_$signal$6[0:0]$3697 $3\exc_$signal$5[0:0]$3696 $3\exc_$signal$4[0:0]$3695 $3\exc_$signal$3[0:0]$3694 $3\exc_$signal[0:0]$3693 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\ea[4:0] $4\ea[4:0] + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\cr_out[2:0] $4\cr_out[2:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[2:0] $4\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $4\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$3681 $4\cr_in2$1[2:0]$3701 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3682 $4\cr_in2_ok$2[0:0]$3702 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3683 $4\exc_$signal[0:0]$3703 + assign $2\exc_$signal$3[0:0]$3684 $4\exc_$signal$3[0:0]$3704 + assign $2\exc_$signal$4[0:0]$3685 $4\exc_$signal$4[0:0]$3705 + assign $2\exc_$signal$5[0:0]$3686 $4\exc_$signal$5[0:0]$3706 + assign $2\exc_$signal$6[0:0]$3687 $4\exc_$signal$6[0:0]$3707 + assign $2\exc_$signal$7[0:0]$3688 $4\exc_$signal$7[0:0]$3708 + assign $2\exc_$signal$8[0:0]$3689 $4\exc_$signal$8[0:0]$3709 + assign $2\exc_$signal$9[0:0]$3690 $4\exc_$signal$9[0:0]$3710 + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $4\fn_unit[11:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[4:0] $4\reg1[4:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[4:0] $4\reg2[4:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[4:0] $4\reg3[4:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[4:0] $4\rego[4:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3710 $4\exc_$signal$8[0:0]$3709 $4\exc_$signal$7[0:0]$3708 $4\exc_$signal$6[0:0]$3707 $4\exc_$signal$5[0:0]$3706 $4\exc_$signal$4[0:0]$3705 $4\exc_$signal$3[0:0]$3704 $4\exc_$signal[0:0]$3703 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3702 $4\cr_in2$1[2:0]$3701 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3710 $4\exc_$signal$8[0:0]$3709 $4\exc_$signal$7[0:0]$3708 $4\exc_$signal$6[0:0]$3707 $4\exc_$signal$5[0:0]$3706 $4\exc_$signal$4[0:0]$3705 $4\exc_$signal$3[0:0]$3704 $4\exc_$signal[0:0]$3703 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3702 $4\cr_in2$1[2:0]$3701 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- assign { } { } assign { } { } assign { } { } @@ -120343,16 +122508,108 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[11:0] 12'000010000000 assign $1\trapaddr[12:0] 13'0000001010000 - assign $1\traptype[6:0] 7'0010000 + assign $1\traptype[7:0] 8'00010000 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" - case 4'-1-- + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -120404,16 +122661,23 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[11:0] 12'000010000000 assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'0000010 + assign $1\traptype[7:0] 8'00000010 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" - case 4'1--- + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -120465,12 +122729,14 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[11:0] 12'000010000000 assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[6:0] 7'1000000 + assign $1\traptype[7:0] 8'10000000 assign $1\msr[63:0] \cur_msr assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" @@ -120526,43 +122792,51 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3629 $1\cr_in2$1[2:0]$3628 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:924" - switch \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $2\fasto1[2:0] 3'011 - assign $2\fasto1_ok[0:0] 1'1 - assign $2\fasto2[2:0] 3'100 - assign $2\fasto2_ok[0:0] 1'1 + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 case - assign $2\fasto1[2:0] $1\fasto1[2:0] - assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] - assign $2\fasto2[2:0] $1\fasto2[2:0] - assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:933" - switch \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } - assign $2\fast1[2:0] 3'011 - assign $2\fast1_ok[0:0] 1'1 - assign $2\fast2[2:0] 3'100 - assign $2\fast2_ok[0:0] 1'1 + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 case - assign $2\fast1[2:0] $1\fast1[2:0] - assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] - assign $2\fast2[2:0] $1\fast2[2:0] - assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] end sync always update \fast1 $0\fast1[2:0] @@ -120582,14 +122856,22 @@ module \dec2 update \cr_in1 $0\cr_in1[2:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$3626 + update \cr_in2$1 $0\cr_in2$1[2:0]$3661 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3627 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3662 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$3663 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3664 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3665 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3666 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3667 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3668 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3669 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3670 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] @@ -120613,30 +122895,46 @@ module \dec2 update \spro $0\spro[9:0] update \spro_ok $0\spro_ok[0:0] update \trapaddr $0\trapaddr[12:0] - update \traptype $0\traptype[6:0] + update \traptype $0\traptype[7:0] update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$13 $eq$libresoc.v:74480$3608_Y - connect \$15 $eq$libresoc.v:74481$3609_Y - connect \$17 $eq$libresoc.v:74482$3610_Y - connect \$19 $eq$libresoc.v:74483$3611_Y - connect \$21 $and$libresoc.v:74484$3612_Y - connect \$23 $and$libresoc.v:74485$3613_Y - connect \$25 $and$libresoc.v:74486$3614_Y - connect \$27 $eq$libresoc.v:74487$3615_Y - connect \$29 $eq$libresoc.v:74488$3616_Y - connect \$31 $eq$libresoc.v:74489$3617_Y - connect \$33 $or$libresoc.v:74490$3618_Y - connect \$35 $eq$libresoc.v:74491$3619_Y + connect \$28 $eq$libresoc.v:75265$3643_Y + connect \$30 $eq$libresoc.v:75266$3644_Y + connect \$32 $or$libresoc.v:75267$3645_Y + connect \$34 $eq$libresoc.v:75268$3646_Y + connect \$42 $eq$libresoc.v:75269$3647_Y + connect \$44 $eq$libresoc.v:75270$3648_Y + connect \$46 $eq$libresoc.v:75271$3649_Y + connect \$48 $eq$libresoc.v:75272$3650_Y + connect \$50 $and$libresoc.v:75273$3651_Y + connect \$52 $and$libresoc.v:75274$3652_Y + connect \$54 $and$libresoc.v:75275$3653_Y + connect \$56 $eq$libresoc.v:75276$3654_Y + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 connect \tmp_asmcode 8'00000000 - connect \tmp_tmp_traptype 7'0000000 - connect \illeg_ok \$27 - connect \priv_ok \$25 - connect \dec_irq_ok \$23 - connect \ext_irq_ok \$21 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$56 + connect \priv_ok \$54 + connect \dec_irq_ok \$52 + connect \ext_irq_ok \$50 connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } @@ -120656,11 +122954,12 @@ module \dec2 connect \dec_c_sel_in \dec_in3_sel connect \dec_b_sel_in \dec_in2_sel connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$10 \dec_opcode_in - connect \insn_in$9 \dec_opcode_in - connect \insn_in$8 \dec_opcode_in - connect \insn_in$7 \dec_opcode_in - connect \insn_in$6 \dec_opcode_in + connect \insn_in$41 \dec_opcode_in + connect \insn_in$40 \dec_opcode_in + connect \insn_in$39 \dec_opcode_in + connect \insn_in$38 \dec_opcode_in + connect \insn_in$37 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in connect \tmp_tmp_is_32bit \dec_is_32b connect \tmp_tmp_input_carry \dec_cry_in connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } @@ -120678,116 +122977,115 @@ module \dec2 connect \dec_rc_sel_in \dec_rc_sel connect \dec_cr_out_insn_in \dec_opcode_in connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$5 \dec_opcode_in + connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \tmp_tmp_insn \dec_opcode_in end -attribute \src "libresoc.v:74837.1-75984.10" +attribute \src "libresoc.v:75714.1-76861.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:75280.3-75316.6" + attribute \src "libresoc.v:76157.3-76193.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:75428.3-75464.6" + attribute \src "libresoc.v:76305.3-76341.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:75909.3-75945.6" + attribute \src "libresoc.v:76786.3-76822.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:75946.3-75982.6" + attribute \src "libresoc.v:76823.3-76859.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:75243.3-75279.6" + attribute \src "libresoc.v:76120.3-76156.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:75391.3-75427.6" + attribute \src "libresoc.v:76268.3-76304.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:75724.3-75760.6" + attribute \src "libresoc.v:76601.3-76637.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:75095.3-75131.6" + attribute \src "libresoc.v:75972.3-76008.6" wire width 12 $0\dec30_function_unit[11:0] - attribute \src "libresoc.v:75761.3-75797.6" + attribute \src "libresoc.v:76638.3-76674.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:75798.3-75834.6" + attribute \src "libresoc.v:76675.3-76711.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:75835.3-75871.6" + attribute \src "libresoc.v:76712.3-76748.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:75502.3-75538.6" + attribute \src "libresoc.v:76379.3-76415.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:75317.3-75353.6" + attribute \src "libresoc.v:76194.3-76230.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:75354.3-75390.6" + attribute \src "libresoc.v:76231.3-76267.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:75576.3-75612.6" + attribute \src "libresoc.v:76453.3-76489.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:75132.3-75168.6" + attribute \src "libresoc.v:76009.3-76045.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:75650.3-75686.6" + attribute \src "libresoc.v:76527.3-76563.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:75872.3-75908.6" + attribute \src "libresoc.v:76749.3-76785.6" wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:75206.3-75242.6" + attribute \src "libresoc.v:76083.3-76119.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:75539.3-75575.6" + attribute \src "libresoc.v:76416.3-76452.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:75687.3-75723.6" + attribute \src "libresoc.v:76564.3-76600.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:75613.3-75649.6" + attribute \src "libresoc.v:76490.3-76526.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:75465.3-75501.6" + attribute \src "libresoc.v:76342.3-76378.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:75169.3-75205.6" + attribute \src "libresoc.v:76046.3-76082.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:74838.7-74838.20" + attribute \src "libresoc.v:75715.7-75715.20" wire $0\initial[0:0] - attribute \src "libresoc.v:75280.3-75316.6" + attribute \src "libresoc.v:76157.3-76193.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:75428.3-75464.6" + attribute \src "libresoc.v:76305.3-76341.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:75909.3-75945.6" + attribute \src "libresoc.v:76786.3-76822.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:75946.3-75982.6" + attribute \src "libresoc.v:76823.3-76859.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:75243.3-75279.6" + attribute \src "libresoc.v:76120.3-76156.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:75391.3-75427.6" + attribute \src "libresoc.v:76268.3-76304.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:75724.3-75760.6" + attribute \src "libresoc.v:76601.3-76637.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:75095.3-75131.6" + attribute \src "libresoc.v:75972.3-76008.6" wire width 12 $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:75761.3-75797.6" + attribute \src "libresoc.v:76638.3-76674.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:75798.3-75834.6" + attribute \src "libresoc.v:76675.3-76711.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:75835.3-75871.6" + attribute \src "libresoc.v:76712.3-76748.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:75502.3-75538.6" + attribute \src "libresoc.v:76379.3-76415.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:75317.3-75353.6" + attribute \src "libresoc.v:76194.3-76230.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:75354.3-75390.6" + attribute \src "libresoc.v:76231.3-76267.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:75576.3-75612.6" + attribute \src "libresoc.v:76453.3-76489.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:75132.3-75168.6" + attribute \src "libresoc.v:76009.3-76045.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:75650.3-75686.6" + attribute \src "libresoc.v:76527.3-76563.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:75872.3-75908.6" + attribute \src "libresoc.v:76749.3-76785.6" wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:75206.3-75242.6" + attribute \src "libresoc.v:76083.3-76119.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:75539.3-75575.6" + attribute \src "libresoc.v:76416.3-76452.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:75687.3-75723.6" + attribute \src "libresoc.v:76564.3-76600.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:75613.3-75649.6" + attribute \src "libresoc.v:76490.3-76526.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:75465.3-75501.6" + attribute \src "libresoc.v:76342.3-76378.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:75169.3-75205.6" + attribute \src "libresoc.v:76046.3-76082.6" wire width 2 $1\dec30_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec30_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -120797,7 +123095,7 @@ module \dec30 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec30_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -120805,15 +123103,15 @@ module \dec30 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec30_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -120845,7 +123143,7 @@ module \dec30 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -120860,7 +123158,7 @@ module \dec30 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec30_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -120868,7 +123166,7 @@ module \dec30 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec30_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -120885,13 +123183,13 @@ module \dec30 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec30_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -120967,13 +123265,13 @@ module \dec30 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec30_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -120981,64 +123279,64 @@ module \dec30 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec30_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec30_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec30_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec30_upd - attribute \src "libresoc.v:74838.7-74838.15" + attribute \src "libresoc.v:75715.7-75715.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 4 \opcode_switch - attribute \src "libresoc.v:74838.7-74838.20" - process $proc$libresoc.v:74838$3655 + attribute \src "libresoc.v:75715.7-75715.20" + process $proc$libresoc.v:75715$3736 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75095.3-75131.6" - process $proc$libresoc.v:75095$3631 + attribute \src "libresoc.v:75972.3-76008.6" + process $proc$libresoc.v:75972$3712 assign { } { } assign { } { } assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:75096.5-75096.29" + attribute \src "libresoc.v:75973.5-75973.29" switch \initial - attribute \src "libresoc.v:75096.9-75096.17" + attribute \src "libresoc.v:75973.9-75973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121086,18 +123384,18 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[11:0] end - attribute \src "libresoc.v:75132.3-75168.6" - process $proc$libresoc.v:75132$3632 + attribute \src "libresoc.v:76009.3-76045.6" + process $proc$libresoc.v:76009$3713 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:75133.5-75133.29" + attribute \src "libresoc.v:76010.5-76010.29" switch \initial - attribute \src "libresoc.v:75133.9-75133.17" + attribute \src "libresoc.v:76010.9-76010.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121145,18 +123443,18 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:75169.3-75205.6" - process $proc$libresoc.v:75169$3633 + attribute \src "libresoc.v:76046.3-76082.6" + process $proc$libresoc.v:76046$3714 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:75170.5-75170.29" + attribute \src "libresoc.v:76047.5-76047.29" switch \initial - attribute \src "libresoc.v:75170.9-75170.17" + attribute \src "libresoc.v:76047.9-76047.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121204,18 +123502,18 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:75206.3-75242.6" - process $proc$libresoc.v:75206$3634 + attribute \src "libresoc.v:76083.3-76119.6" + process $proc$libresoc.v:76083$3715 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:75207.5-75207.29" + attribute \src "libresoc.v:76084.5-76084.29" switch \initial - attribute \src "libresoc.v:75207.9-75207.17" + attribute \src "libresoc.v:76084.9-76084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121263,18 +123561,18 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:75243.3-75279.6" - process $proc$libresoc.v:75243$3635 + attribute \src "libresoc.v:76120.3-76156.6" + process $proc$libresoc.v:76120$3716 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:75244.5-75244.29" + attribute \src "libresoc.v:76121.5-76121.29" switch \initial - attribute \src "libresoc.v:75244.9-75244.17" + attribute \src "libresoc.v:76121.9-76121.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121322,18 +123620,18 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:75280.3-75316.6" - process $proc$libresoc.v:75280$3636 + attribute \src "libresoc.v:76157.3-76193.6" + process $proc$libresoc.v:76157$3717 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:75281.5-75281.29" + attribute \src "libresoc.v:76158.5-76158.29" switch \initial - attribute \src "libresoc.v:75281.9-75281.17" + attribute \src "libresoc.v:76158.9-76158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121381,18 +123679,18 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:75317.3-75353.6" - process $proc$libresoc.v:75317$3637 + attribute \src "libresoc.v:76194.3-76230.6" + process $proc$libresoc.v:76194$3718 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:75318.5-75318.29" + attribute \src "libresoc.v:76195.5-76195.29" switch \initial - attribute \src "libresoc.v:75318.9-75318.17" + attribute \src "libresoc.v:76195.9-76195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121440,18 +123738,18 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:75354.3-75390.6" - process $proc$libresoc.v:75354$3638 + attribute \src "libresoc.v:76231.3-76267.6" + process $proc$libresoc.v:76231$3719 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:75355.5-75355.29" + attribute \src "libresoc.v:76232.5-76232.29" switch \initial - attribute \src "libresoc.v:75355.9-75355.17" + attribute \src "libresoc.v:76232.9-76232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121499,18 +123797,18 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:75391.3-75427.6" - process $proc$libresoc.v:75391$3639 + attribute \src "libresoc.v:76268.3-76304.6" + process $proc$libresoc.v:76268$3720 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:75392.5-75392.29" + attribute \src "libresoc.v:76269.5-76269.29" switch \initial - attribute \src "libresoc.v:75392.9-75392.17" + attribute \src "libresoc.v:76269.9-76269.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121558,18 +123856,18 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:75428.3-75464.6" - process $proc$libresoc.v:75428$3640 + attribute \src "libresoc.v:76305.3-76341.6" + process $proc$libresoc.v:76305$3721 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:75429.5-75429.29" + attribute \src "libresoc.v:76306.5-76306.29" switch \initial - attribute \src "libresoc.v:75429.9-75429.17" + attribute \src "libresoc.v:76306.9-76306.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121617,18 +123915,18 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:75465.3-75501.6" - process $proc$libresoc.v:75465$3641 + attribute \src "libresoc.v:76342.3-76378.6" + process $proc$libresoc.v:76342$3722 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:75466.5-75466.29" + attribute \src "libresoc.v:76343.5-76343.29" switch \initial - attribute \src "libresoc.v:75466.9-75466.17" + attribute \src "libresoc.v:76343.9-76343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121676,18 +123974,18 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:75502.3-75538.6" - process $proc$libresoc.v:75502$3642 + attribute \src "libresoc.v:76379.3-76415.6" + process $proc$libresoc.v:76379$3723 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:75503.5-75503.29" + attribute \src "libresoc.v:76380.5-76380.29" switch \initial - attribute \src "libresoc.v:75503.9-75503.17" + attribute \src "libresoc.v:76380.9-76380.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121735,18 +124033,18 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:75539.3-75575.6" - process $proc$libresoc.v:75539$3643 + attribute \src "libresoc.v:76416.3-76452.6" + process $proc$libresoc.v:76416$3724 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:75540.5-75540.29" + attribute \src "libresoc.v:76417.5-76417.29" switch \initial - attribute \src "libresoc.v:75540.9-75540.17" + attribute \src "libresoc.v:76417.9-76417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121794,18 +124092,18 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:75576.3-75612.6" - process $proc$libresoc.v:75576$3644 + attribute \src "libresoc.v:76453.3-76489.6" + process $proc$libresoc.v:76453$3725 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:75577.5-75577.29" + attribute \src "libresoc.v:76454.5-76454.29" switch \initial - attribute \src "libresoc.v:75577.9-75577.17" + attribute \src "libresoc.v:76454.9-76454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121853,18 +124151,18 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:75613.3-75649.6" - process $proc$libresoc.v:75613$3645 + attribute \src "libresoc.v:76490.3-76526.6" + process $proc$libresoc.v:76490$3726 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:75614.5-75614.29" + attribute \src "libresoc.v:76491.5-76491.29" switch \initial - attribute \src "libresoc.v:75614.9-75614.17" + attribute \src "libresoc.v:76491.9-76491.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121912,18 +124210,18 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:75650.3-75686.6" - process $proc$libresoc.v:75650$3646 + attribute \src "libresoc.v:76527.3-76563.6" + process $proc$libresoc.v:76527$3727 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:75651.5-75651.29" + attribute \src "libresoc.v:76528.5-76528.29" switch \initial - attribute \src "libresoc.v:75651.9-75651.17" + attribute \src "libresoc.v:76528.9-76528.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -121971,18 +124269,18 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:75687.3-75723.6" - process $proc$libresoc.v:75687$3647 + attribute \src "libresoc.v:76564.3-76600.6" + process $proc$libresoc.v:76564$3728 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:75688.5-75688.29" + attribute \src "libresoc.v:76565.5-76565.29" switch \initial - attribute \src "libresoc.v:75688.9-75688.17" + attribute \src "libresoc.v:76565.9-76565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122030,18 +124328,18 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:75724.3-75760.6" - process $proc$libresoc.v:75724$3648 + attribute \src "libresoc.v:76601.3-76637.6" + process $proc$libresoc.v:76601$3729 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:75725.5-75725.29" + attribute \src "libresoc.v:76602.5-76602.29" switch \initial - attribute \src "libresoc.v:75725.9-75725.17" + attribute \src "libresoc.v:76602.9-76602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122089,18 +124387,18 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:75761.3-75797.6" - process $proc$libresoc.v:75761$3649 + attribute \src "libresoc.v:76638.3-76674.6" + process $proc$libresoc.v:76638$3730 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:75762.5-75762.29" + attribute \src "libresoc.v:76639.5-76639.29" switch \initial - attribute \src "libresoc.v:75762.9-75762.17" + attribute \src "libresoc.v:76639.9-76639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122148,18 +124446,18 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:75798.3-75834.6" - process $proc$libresoc.v:75798$3650 + attribute \src "libresoc.v:76675.3-76711.6" + process $proc$libresoc.v:76675$3731 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:75799.5-75799.29" + attribute \src "libresoc.v:76676.5-76676.29" switch \initial - attribute \src "libresoc.v:75799.9-75799.17" + attribute \src "libresoc.v:76676.9-76676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122207,18 +124505,18 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:75835.3-75871.6" - process $proc$libresoc.v:75835$3651 + attribute \src "libresoc.v:76712.3-76748.6" + process $proc$libresoc.v:76712$3732 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:75836.5-75836.29" + attribute \src "libresoc.v:76713.5-76713.29" switch \initial - attribute \src "libresoc.v:75836.9-75836.17" + attribute \src "libresoc.v:76713.9-76713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122266,18 +124564,18 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:75872.3-75908.6" - process $proc$libresoc.v:75872$3652 + attribute \src "libresoc.v:76749.3-76785.6" + process $proc$libresoc.v:76749$3733 assign { } { } assign { } { } assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:75873.5-75873.29" + attribute \src "libresoc.v:76750.5-76750.29" switch \initial - attribute \src "libresoc.v:75873.9-75873.17" + attribute \src "libresoc.v:76750.9-76750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122325,18 +124623,18 @@ module \dec30 sync always update \dec30_out_sel $0\dec30_out_sel[1:0] end - attribute \src "libresoc.v:75909.3-75945.6" - process $proc$libresoc.v:75909$3653 + attribute \src "libresoc.v:76786.3-76822.6" + process $proc$libresoc.v:76786$3734 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:75910.5-75910.29" + attribute \src "libresoc.v:76787.5-76787.29" switch \initial - attribute \src "libresoc.v:75910.9-75910.17" + attribute \src "libresoc.v:76787.9-76787.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122384,18 +124682,18 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:75946.3-75982.6" - process $proc$libresoc.v:75946$3654 + attribute \src "libresoc.v:76823.3-76859.6" + process $proc$libresoc.v:76823$3735 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:75947.5-75947.29" + attribute \src "libresoc.v:76824.5-76824.29" switch \initial - attribute \src "libresoc.v:75947.9-75947.17" + attribute \src "libresoc.v:76824.9-76824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -122445,112 +124743,112 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:75988.1-82358.10" +attribute \src "libresoc.v:76865.1-83235.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:81057.3-81117.6" + attribute \src "libresoc.v:81934.3-81994.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:81911.3-81971.6" + attribute \src "libresoc.v:82788.3-82848.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:81362.3-81422.6" + attribute \src "libresoc.v:82239.3-82299.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:81423.3-81483.6" + attribute \src "libresoc.v:82300.3-82360.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:81667.3-81727.6" + attribute \src "libresoc.v:82544.3-82604.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:81850.3-81910.6" + attribute \src "libresoc.v:82727.3-82787.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:80996.3-81056.6" + attribute \src "libresoc.v:81873.3-81933.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:80874.3-80934.6" + attribute \src "libresoc.v:81751.3-81811.6" wire width 12 $0\dec31_function_unit[11:0] - attribute \src "libresoc.v:81118.3-81178.6" + attribute \src "libresoc.v:81995.3-82055.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81179.3-81239.6" + attribute \src "libresoc.v:82056.3-82116.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81240.3-81300.6" + attribute \src "libresoc.v:82117.3-82177.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:80935.3-80995.6" + attribute \src "libresoc.v:81812.3-81872.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:81728.3-81788.6" + attribute \src "libresoc.v:82605.3-82665.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:81789.3-81849.6" + attribute \src "libresoc.v:82666.3-82726.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:82094.3-82154.6" + attribute \src "libresoc.v:82971.3-83031.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:81484.3-81544.6" + attribute \src "libresoc.v:82361.3-82421.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82216.3-82276.6" + attribute \src "libresoc.v:83093.3-83153.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:81301.3-81361.6" + attribute \src "libresoc.v:82178.3-82238.6" wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:81606.3-81666.6" + attribute \src "libresoc.v:82483.3-82543.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82033.3-82093.6" + attribute \src "libresoc.v:82910.3-82970.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:82277.3-82337.6" + attribute \src "libresoc.v:83154.3-83214.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82155.3-82215.6" + attribute \src "libresoc.v:83032.3-83092.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:81972.3-82032.6" + attribute \src "libresoc.v:82849.3-82909.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:81545.3-81605.6" + attribute \src "libresoc.v:82422.3-82482.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:75989.7-75989.20" + attribute \src "libresoc.v:76866.7-76866.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81057.3-81117.6" + attribute \src "libresoc.v:81934.3-81994.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:81911.3-81971.6" + attribute \src "libresoc.v:82788.3-82848.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:81362.3-81422.6" + attribute \src "libresoc.v:82239.3-82299.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:81423.3-81483.6" + attribute \src "libresoc.v:82300.3-82360.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:81667.3-81727.6" + attribute \src "libresoc.v:82544.3-82604.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:81850.3-81910.6" + attribute \src "libresoc.v:82727.3-82787.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:80996.3-81056.6" + attribute \src "libresoc.v:81873.3-81933.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:80874.3-80934.6" + attribute \src "libresoc.v:81751.3-81811.6" wire width 12 $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:81118.3-81178.6" + attribute \src "libresoc.v:81995.3-82055.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81179.3-81239.6" + attribute \src "libresoc.v:82056.3-82116.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81240.3-81300.6" + attribute \src "libresoc.v:82117.3-82177.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:80935.3-80995.6" + attribute \src "libresoc.v:81812.3-81872.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:81728.3-81788.6" + attribute \src "libresoc.v:82605.3-82665.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:81789.3-81849.6" + attribute \src "libresoc.v:82666.3-82726.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:82094.3-82154.6" + attribute \src "libresoc.v:82971.3-83031.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:81484.3-81544.6" + attribute \src "libresoc.v:82361.3-82421.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82216.3-82276.6" + attribute \src "libresoc.v:83093.3-83153.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:81301.3-81361.6" + attribute \src "libresoc.v:82178.3-82238.6" wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:81606.3-81666.6" + attribute \src "libresoc.v:82483.3-82543.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82033.3-82093.6" + attribute \src "libresoc.v:82910.3-82970.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:82277.3-82337.6" + attribute \src "libresoc.v:83154.3-83214.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82155.3-82215.6" + attribute \src "libresoc.v:83032.3-83092.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:81972.3-82032.6" + attribute \src "libresoc.v:82849.3-82909.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:81545.3-81605.6" + attribute \src "libresoc.v:82422.3-82482.6" wire width 2 $1\dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -122560,7 +124858,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -122568,19 +124866,19 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -122590,7 +124888,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -122598,15 +124896,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -122638,7 +124936,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -122653,7 +124951,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -122661,7 +124959,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -122678,13 +124976,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -122760,13 +125058,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -122774,43 +125072,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub0_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -122820,7 +125118,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -122828,15 +125126,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -122868,7 +125166,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -122883,7 +125181,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -122891,7 +125189,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -122908,13 +125206,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -122990,13 +125288,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -123004,43 +125302,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub10_dec31_dec_sub10_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub10_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123050,7 +125348,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123058,15 +125356,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -123098,7 +125396,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -123113,7 +125411,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub11_dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123121,7 +125419,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub11_dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123138,13 +125436,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -123220,13 +125518,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -123234,43 +125532,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub11_dec31_dec_sub11_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub11_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123280,7 +125578,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123288,15 +125586,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -123328,7 +125626,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -123343,7 +125641,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub15_dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123351,7 +125649,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub15_dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123368,13 +125666,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -123450,13 +125748,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -123464,43 +125762,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub15_dec31_dec_sub15_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub15_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123510,7 +125808,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123518,15 +125816,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -123558,7 +125856,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -123573,7 +125871,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub16_dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123581,7 +125879,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub16_dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123598,13 +125896,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -123680,13 +125978,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -123694,43 +125992,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub16_dec31_dec_sub16_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub16_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123740,7 +126038,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123748,15 +126046,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -123788,7 +126086,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -123803,7 +126101,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub18_dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -123811,7 +126109,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub18_dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -123828,13 +126126,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -123910,13 +126208,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -123924,43 +126222,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub18_dec31_dec_sub18_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub18_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123970,7 +126268,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123978,15 +126276,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124018,7 +126316,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -124033,7 +126331,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub19_dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124041,7 +126339,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub19_dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124058,13 +126356,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124140,13 +126438,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124154,43 +126452,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub19_dec31_dec_sub19_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub19_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124200,7 +126498,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124208,15 +126506,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124248,7 +126546,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -124263,7 +126561,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub20_dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124271,7 +126569,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub20_dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124288,13 +126586,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124370,13 +126668,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124384,43 +126682,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub20_dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub20_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124430,7 +126728,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124438,15 +126736,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124478,7 +126776,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -124493,7 +126791,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub21_dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124501,7 +126799,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub21_dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124518,13 +126816,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124600,13 +126898,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124614,43 +126912,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub21_dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub21_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124660,7 +126958,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124668,15 +126966,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124708,7 +127006,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -124723,7 +127021,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub22_dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124731,7 +127029,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub22_dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124748,13 +127046,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -124830,13 +127128,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -124844,43 +127142,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub22_dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub22_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -124890,7 +127188,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -124898,15 +127196,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -124938,7 +127236,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -124953,7 +127251,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub23_dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -124961,7 +127259,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub23_dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -124978,13 +127276,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125060,13 +127358,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125074,43 +127372,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub23_dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub23_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125120,7 +127418,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125128,15 +127426,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125168,7 +127466,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -125183,7 +127481,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub24_dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -125191,7 +127489,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub24_dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125208,13 +127506,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125290,13 +127588,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125304,43 +127602,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub24_dec31_dec_sub24_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub24_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125350,7 +127648,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125358,15 +127656,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125398,7 +127696,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -125413,7 +127711,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub26_dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -125421,7 +127719,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub26_dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125438,13 +127736,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125520,13 +127818,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125534,43 +127832,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub26_dec31_dec_sub26_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub26_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125580,7 +127878,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125588,15 +127886,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125628,7 +127926,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -125643,7 +127941,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub27_dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -125651,7 +127949,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub27_dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125668,13 +127966,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125750,13 +128048,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125764,43 +128062,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub27_dec31_dec_sub27_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub27_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -125810,7 +128108,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -125818,15 +128116,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -125858,7 +128156,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -125873,7 +128171,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub28_dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -125881,7 +128179,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub28_dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -125898,13 +128196,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -125980,13 +128278,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -125994,43 +128292,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub28_dec31_dec_sub28_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub28_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub4_dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126040,7 +128338,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126048,15 +128346,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126088,7 +128386,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -126103,7 +128401,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub4_dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -126111,7 +128409,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub4_dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126128,13 +128426,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126210,13 +128508,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub4_dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126224,43 +128522,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub4_dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub4_dec31_dec_sub4_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub4_dec31_dec_sub4_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub4_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126270,7 +128568,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126278,15 +128576,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126318,7 +128616,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -126333,7 +128631,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub8_dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -126341,7 +128639,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub8_dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126358,13 +128656,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126440,13 +128738,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126454,43 +128752,43 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub8_dec31_dec_sub8_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub8_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -126500,7 +128798,7 @@ module \dec31 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -126508,15 +128806,15 @@ module \dec31 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126548,7 +128846,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -126563,7 +128861,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec31_dec_sub9_dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -126571,7 +128869,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec31_dec_sub9_dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126588,13 +128886,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126670,13 +128968,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126684,39 +128982,39 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec31_dec_sub9_opcode_in attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -126748,7 +129046,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -126763,7 +129061,7 @@ module \dec31 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -126771,7 +129069,7 @@ module \dec31 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -126788,13 +129086,13 @@ module \dec31 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -126870,13 +129168,13 @@ module \dec31 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -126884,48 +129182,48 @@ module \dec31 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_upd - attribute \src "libresoc.v:75989.7-75989.15" + attribute \src "libresoc.v:76866.7-76866.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:80388.18-80414.4" + attribute \src "libresoc.v:81265.18-81291.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br @@ -126954,7 +129252,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80415.19-80441.4" + attribute \src "libresoc.v:81292.19-81318.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br @@ -126983,7 +129281,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80442.19-80468.4" + attribute \src "libresoc.v:81319.19-81345.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br @@ -127012,7 +129310,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80469.19-80495.4" + attribute \src "libresoc.v:81346.19-81372.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br @@ -127041,7 +129339,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80496.19-80522.4" + attribute \src "libresoc.v:81373.19-81399.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br @@ -127070,7 +129368,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80523.19-80549.4" + attribute \src "libresoc.v:81400.19-81426.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br @@ -127099,7 +129397,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80550.19-80576.4" + attribute \src "libresoc.v:81427.19-81453.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br @@ -127128,7 +129426,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80577.19-80603.4" + attribute \src "libresoc.v:81454.19-81480.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br @@ -127157,7 +129455,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80604.19-80630.4" + attribute \src "libresoc.v:81481.19-81507.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br @@ -127186,7 +129484,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80631.19-80657.4" + attribute \src "libresoc.v:81508.19-81534.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br @@ -127215,7 +129513,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80658.19-80684.4" + attribute \src "libresoc.v:81535.19-81561.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br @@ -127244,7 +129542,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80685.19-80711.4" + attribute \src "libresoc.v:81562.19-81588.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br @@ -127273,7 +129571,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80712.19-80738.4" + attribute \src "libresoc.v:81589.19-81615.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br @@ -127302,7 +129600,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80739.19-80765.4" + attribute \src "libresoc.v:81616.19-81642.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br @@ -127331,7 +129629,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80766.19-80792.4" + attribute \src "libresoc.v:81643.19-81669.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br @@ -127360,7 +129658,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80793.18-80819.4" + attribute \src "libresoc.v:81670.18-81696.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br @@ -127389,7 +129687,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80820.18-80846.4" + attribute \src "libresoc.v:81697.18-81723.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br @@ -127418,7 +129716,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:80847.18-80873.4" + attribute \src "libresoc.v:81724.18-81750.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br @@ -127446,26 +129744,26 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:75989.7-75989.20" - process $proc$libresoc.v:75989$3680 + attribute \src "libresoc.v:76866.7-76866.20" + process $proc$libresoc.v:76866$3761 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80874.3-80934.6" - process $proc$libresoc.v:80874$3656 + attribute \src "libresoc.v:81751.3-81811.6" + process $proc$libresoc.v:81751$3737 assign { } { } assign { } { } assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:80875.5-80875.29" + attribute \src "libresoc.v:81752.5-81752.29" switch \initial - attribute \src "libresoc.v:80875.9-80875.17" + attribute \src "libresoc.v:81752.9-81752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -127545,18 +129843,18 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[11:0] end - attribute \src "libresoc.v:80935.3-80995.6" - process $proc$libresoc.v:80935$3657 + attribute \src "libresoc.v:81812.3-81872.6" + process $proc$libresoc.v:81812$3738 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:80936.5-80936.29" + attribute \src "libresoc.v:81813.5-81813.29" switch \initial - attribute \src "libresoc.v:80936.9-80936.17" + attribute \src "libresoc.v:81813.9-81813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -127636,18 +129934,18 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:80996.3-81056.6" - process $proc$libresoc.v:80996$3658 + attribute \src "libresoc.v:81873.3-81933.6" + process $proc$libresoc.v:81873$3739 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:80997.5-80997.29" + attribute \src "libresoc.v:81874.5-81874.29" switch \initial - attribute \src "libresoc.v:80997.9-80997.17" + attribute \src "libresoc.v:81874.9-81874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -127727,18 +130025,18 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:81057.3-81117.6" - process $proc$libresoc.v:81057$3659 + attribute \src "libresoc.v:81934.3-81994.6" + process $proc$libresoc.v:81934$3740 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:81058.5-81058.29" + attribute \src "libresoc.v:81935.5-81935.29" switch \initial - attribute \src "libresoc.v:81058.9-81058.17" + attribute \src "libresoc.v:81935.9-81935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -127818,18 +130116,18 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:81118.3-81178.6" - process $proc$libresoc.v:81118$3660 + attribute \src "libresoc.v:81995.3-82055.6" + process $proc$libresoc.v:81995$3741 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81119.5-81119.29" + attribute \src "libresoc.v:81996.5-81996.29" switch \initial - attribute \src "libresoc.v:81119.9-81119.17" + attribute \src "libresoc.v:81996.9-81996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -127909,18 +130207,18 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:81179.3-81239.6" - process $proc$libresoc.v:81179$3661 + attribute \src "libresoc.v:82056.3-82116.6" + process $proc$libresoc.v:82056$3742 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:81180.5-81180.29" + attribute \src "libresoc.v:82057.5-82057.29" switch \initial - attribute \src "libresoc.v:81180.9-81180.17" + attribute \src "libresoc.v:82057.9-82057.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128000,18 +130298,18 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:81240.3-81300.6" - process $proc$libresoc.v:81240$3662 + attribute \src "libresoc.v:82117.3-82177.6" + process $proc$libresoc.v:82117$3743 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81241.5-81241.29" + attribute \src "libresoc.v:82118.5-82118.29" switch \initial - attribute \src "libresoc.v:81241.9-81241.17" + attribute \src "libresoc.v:82118.9-82118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128091,18 +130389,18 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:81301.3-81361.6" - process $proc$libresoc.v:81301$3663 + attribute \src "libresoc.v:82178.3-82238.6" + process $proc$libresoc.v:82178$3744 assign { } { } assign { } { } assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:81302.5-81302.29" + attribute \src "libresoc.v:82179.5-82179.29" switch \initial - attribute \src "libresoc.v:81302.9-81302.17" + attribute \src "libresoc.v:82179.9-82179.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128182,18 +130480,18 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[1:0] end - attribute \src "libresoc.v:81362.3-81422.6" - process $proc$libresoc.v:81362$3664 + attribute \src "libresoc.v:82239.3-82299.6" + process $proc$libresoc.v:82239$3745 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:81363.5-81363.29" + attribute \src "libresoc.v:82240.5-82240.29" switch \initial - attribute \src "libresoc.v:81363.9-81363.17" + attribute \src "libresoc.v:82240.9-82240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128273,18 +130571,18 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:81423.3-81483.6" - process $proc$libresoc.v:81423$3665 + attribute \src "libresoc.v:82300.3-82360.6" + process $proc$libresoc.v:82300$3746 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:81424.5-81424.29" + attribute \src "libresoc.v:82301.5-82301.29" switch \initial - attribute \src "libresoc.v:81424.9-81424.17" + attribute \src "libresoc.v:82301.9-82301.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128364,18 +130662,18 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:81484.3-81544.6" - process $proc$libresoc.v:81484$3666 + attribute \src "libresoc.v:82361.3-82421.6" + process $proc$libresoc.v:82361$3747 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:81485.5-81485.29" + attribute \src "libresoc.v:82362.5-82362.29" switch \initial - attribute \src "libresoc.v:81485.9-81485.17" + attribute \src "libresoc.v:82362.9-82362.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128455,18 +130753,18 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:81545.3-81605.6" - process $proc$libresoc.v:81545$3667 + attribute \src "libresoc.v:82422.3-82482.6" + process $proc$libresoc.v:82422$3748 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:81546.5-81546.29" + attribute \src "libresoc.v:82423.5-82423.29" switch \initial - attribute \src "libresoc.v:81546.9-81546.17" + attribute \src "libresoc.v:82423.9-82423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128546,18 +130844,18 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:81606.3-81666.6" - process $proc$libresoc.v:81606$3668 + attribute \src "libresoc.v:82483.3-82543.6" + process $proc$libresoc.v:82483$3749 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:81607.5-81607.29" + attribute \src "libresoc.v:82484.5-82484.29" switch \initial - attribute \src "libresoc.v:81607.9-81607.17" + attribute \src "libresoc.v:82484.9-82484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128637,18 +130935,18 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:81667.3-81727.6" - process $proc$libresoc.v:81667$3669 + attribute \src "libresoc.v:82544.3-82604.6" + process $proc$libresoc.v:82544$3750 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:81668.5-81668.29" + attribute \src "libresoc.v:82545.5-82545.29" switch \initial - attribute \src "libresoc.v:81668.9-81668.17" + attribute \src "libresoc.v:82545.9-82545.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128728,18 +131026,18 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:81728.3-81788.6" - process $proc$libresoc.v:81728$3670 + attribute \src "libresoc.v:82605.3-82665.6" + process $proc$libresoc.v:82605$3751 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:81729.5-81729.29" + attribute \src "libresoc.v:82606.5-82606.29" switch \initial - attribute \src "libresoc.v:81729.9-81729.17" + attribute \src "libresoc.v:82606.9-82606.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128819,18 +131117,18 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:81789.3-81849.6" - process $proc$libresoc.v:81789$3671 + attribute \src "libresoc.v:82666.3-82726.6" + process $proc$libresoc.v:82666$3752 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:81790.5-81790.29" + attribute \src "libresoc.v:82667.5-82667.29" switch \initial - attribute \src "libresoc.v:81790.9-81790.17" + attribute \src "libresoc.v:82667.9-82667.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -128910,18 +131208,18 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:81850.3-81910.6" - process $proc$libresoc.v:81850$3672 + attribute \src "libresoc.v:82727.3-82787.6" + process $proc$libresoc.v:82727$3753 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:81851.5-81851.29" + attribute \src "libresoc.v:82728.5-82728.29" switch \initial - attribute \src "libresoc.v:81851.9-81851.17" + attribute \src "libresoc.v:82728.9-82728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129001,18 +131299,18 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:81911.3-81971.6" - process $proc$libresoc.v:81911$3673 + attribute \src "libresoc.v:82788.3-82848.6" + process $proc$libresoc.v:82788$3754 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:81912.5-81912.29" + attribute \src "libresoc.v:82789.5-82789.29" switch \initial - attribute \src "libresoc.v:81912.9-81912.17" + attribute \src "libresoc.v:82789.9-82789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129092,18 +131390,18 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:81972.3-82032.6" - process $proc$libresoc.v:81972$3674 + attribute \src "libresoc.v:82849.3-82909.6" + process $proc$libresoc.v:82849$3755 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:81973.5-81973.29" + attribute \src "libresoc.v:82850.5-82850.29" switch \initial - attribute \src "libresoc.v:81973.9-81973.17" + attribute \src "libresoc.v:82850.9-82850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129183,18 +131481,18 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:82033.3-82093.6" - process $proc$libresoc.v:82033$3675 + attribute \src "libresoc.v:82910.3-82970.6" + process $proc$libresoc.v:82910$3756 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:82034.5-82034.29" + attribute \src "libresoc.v:82911.5-82911.29" switch \initial - attribute \src "libresoc.v:82034.9-82034.17" + attribute \src "libresoc.v:82911.9-82911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129274,18 +131572,18 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:82094.3-82154.6" - process $proc$libresoc.v:82094$3676 + attribute \src "libresoc.v:82971.3-83031.6" + process $proc$libresoc.v:82971$3757 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:82095.5-82095.29" + attribute \src "libresoc.v:82972.5-82972.29" switch \initial - attribute \src "libresoc.v:82095.9-82095.17" + attribute \src "libresoc.v:82972.9-82972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129365,18 +131663,18 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:82155.3-82215.6" - process $proc$libresoc.v:82155$3677 + attribute \src "libresoc.v:83032.3-83092.6" + process $proc$libresoc.v:83032$3758 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:82156.5-82156.29" + attribute \src "libresoc.v:83033.5-83033.29" switch \initial - attribute \src "libresoc.v:82156.9-82156.17" + attribute \src "libresoc.v:83033.9-83033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129456,18 +131754,18 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:82216.3-82276.6" - process $proc$libresoc.v:82216$3678 + attribute \src "libresoc.v:83093.3-83153.6" + process $proc$libresoc.v:83093$3759 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:82217.5-82217.29" + attribute \src "libresoc.v:83094.5-83094.29" switch \initial - attribute \src "libresoc.v:82217.9-82217.17" + attribute \src "libresoc.v:83094.9-83094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129547,18 +131845,18 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:82277.3-82337.6" - process $proc$libresoc.v:82277$3679 + attribute \src "libresoc.v:83154.3-83214.6" + process $proc$libresoc.v:83154$3760 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:82278.5-82278.29" + attribute \src "libresoc.v:83155.5-83155.29" switch \initial - attribute \src "libresoc.v:82278.9-82278.17" + attribute \src "libresoc.v:83155.9-83155.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opc_in attribute \src "libresoc.v:0.0-0.0" case 5'01010 @@ -129659,112 +131957,112 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:82362.1-83077.10" +attribute \src "libresoc.v:83239.1-83954.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:82715.3-82733.6" + attribute \src "libresoc.v:83592.3-83610.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:82791.3-82809.6" + attribute \src "libresoc.v:83668.3-83686.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83038.3-83056.6" + attribute \src "libresoc.v:83915.3-83933.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83057.3-83075.6" + attribute \src "libresoc.v:83934.3-83952.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:82696.3-82714.6" + attribute \src "libresoc.v:83573.3-83591.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:82772.3-82790.6" + attribute \src "libresoc.v:83649.3-83667.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:82943.3-82961.6" + attribute \src "libresoc.v:83820.3-83838.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:82620.3-82638.6" + attribute \src "libresoc.v:83497.3-83515.6" wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:82962.3-82980.6" + attribute \src "libresoc.v:83839.3-83857.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:82981.3-82999.6" + attribute \src "libresoc.v:83858.3-83876.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83000.3-83018.6" + attribute \src "libresoc.v:83877.3-83895.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:82829.3-82847.6" + attribute \src "libresoc.v:83706.3-83724.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:82734.3-82752.6" + attribute \src "libresoc.v:83611.3-83629.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:82753.3-82771.6" + attribute \src "libresoc.v:83630.3-83648.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:82867.3-82885.6" + attribute \src "libresoc.v:83744.3-83762.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:82639.3-82657.6" + attribute \src "libresoc.v:83516.3-83534.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:82905.3-82923.6" + attribute \src "libresoc.v:83782.3-83800.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83019.3-83037.6" + attribute \src "libresoc.v:83896.3-83914.6" wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:82677.3-82695.6" + attribute \src "libresoc.v:83554.3-83572.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:82848.3-82866.6" + attribute \src "libresoc.v:83725.3-83743.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:82924.3-82942.6" + attribute \src "libresoc.v:83801.3-83819.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:82886.3-82904.6" + attribute \src "libresoc.v:83763.3-83781.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:82810.3-82828.6" + attribute \src "libresoc.v:83687.3-83705.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:82658.3-82676.6" + attribute \src "libresoc.v:83535.3-83553.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:82363.7-82363.20" + attribute \src "libresoc.v:83240.7-83240.20" wire $0\initial[0:0] - attribute \src "libresoc.v:82715.3-82733.6" + attribute \src "libresoc.v:83592.3-83610.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:82791.3-82809.6" + attribute \src "libresoc.v:83668.3-83686.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83038.3-83056.6" + attribute \src "libresoc.v:83915.3-83933.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83057.3-83075.6" + attribute \src "libresoc.v:83934.3-83952.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:82696.3-82714.6" + attribute \src "libresoc.v:83573.3-83591.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:82772.3-82790.6" + attribute \src "libresoc.v:83649.3-83667.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:82943.3-82961.6" + attribute \src "libresoc.v:83820.3-83838.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:82620.3-82638.6" + attribute \src "libresoc.v:83497.3-83515.6" wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:82962.3-82980.6" + attribute \src "libresoc.v:83839.3-83857.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:82981.3-82999.6" + attribute \src "libresoc.v:83858.3-83876.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83000.3-83018.6" + attribute \src "libresoc.v:83877.3-83895.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:82829.3-82847.6" + attribute \src "libresoc.v:83706.3-83724.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:82734.3-82752.6" + attribute \src "libresoc.v:83611.3-83629.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:82753.3-82771.6" + attribute \src "libresoc.v:83630.3-83648.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:82867.3-82885.6" + attribute \src "libresoc.v:83744.3-83762.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:82639.3-82657.6" + attribute \src "libresoc.v:83516.3-83534.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:82905.3-82923.6" + attribute \src "libresoc.v:83782.3-83800.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83019.3-83037.6" + attribute \src "libresoc.v:83896.3-83914.6" wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:82677.3-82695.6" + attribute \src "libresoc.v:83554.3-83572.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:82848.3-82866.6" + attribute \src "libresoc.v:83725.3-83743.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:82924.3-82942.6" + attribute \src "libresoc.v:83801.3-83819.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:82886.3-82904.6" + attribute \src "libresoc.v:83763.3-83781.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:82810.3-82828.6" + attribute \src "libresoc.v:83687.3-83705.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:82658.3-82676.6" + attribute \src "libresoc.v:83535.3-83553.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub0_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -129774,7 +132072,7 @@ module \dec31_dec_sub0 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub0_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -129782,15 +132080,15 @@ module \dec31_dec_sub0 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub0_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub0_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -129822,7 +132120,7 @@ module \dec31_dec_sub0 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -129837,7 +132135,7 @@ module \dec31_dec_sub0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub0_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -129845,7 +132143,7 @@ module \dec31_dec_sub0 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub0_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -129862,13 +132160,13 @@ module \dec31_dec_sub0 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub0_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub0_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -129944,13 +132242,13 @@ module \dec31_dec_sub0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub0_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -129958,64 +132256,64 @@ module \dec31_dec_sub0 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub0_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub0_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub0_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub0_upd - attribute \src "libresoc.v:82363.7-82363.15" + attribute \src "libresoc.v:83240.7-83240.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:82363.7-82363.20" - process $proc$libresoc.v:82363$3705 + attribute \src "libresoc.v:83240.7-83240.20" + process $proc$libresoc.v:83240$3786 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:82620.3-82638.6" - process $proc$libresoc.v:82620$3681 + attribute \src "libresoc.v:83497.3-83515.6" + process $proc$libresoc.v:83497$3762 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:82621.5-82621.29" + attribute \src "libresoc.v:83498.5-83498.29" switch \initial - attribute \src "libresoc.v:82621.9-82621.17" + attribute \src "libresoc.v:83498.9-83498.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130039,18 +132337,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] end - attribute \src "libresoc.v:82639.3-82657.6" - process $proc$libresoc.v:82639$3682 + attribute \src "libresoc.v:83516.3-83534.6" + process $proc$libresoc.v:83516$3763 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:82640.5-82640.29" + attribute \src "libresoc.v:83517.5-83517.29" switch \initial - attribute \src "libresoc.v:82640.9-82640.17" + attribute \src "libresoc.v:83517.9-83517.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130074,18 +132372,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:82658.3-82676.6" - process $proc$libresoc.v:82658$3683 + attribute \src "libresoc.v:83535.3-83553.6" + process $proc$libresoc.v:83535$3764 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:82659.5-82659.29" + attribute \src "libresoc.v:83536.5-83536.29" switch \initial - attribute \src "libresoc.v:82659.9-82659.17" + attribute \src "libresoc.v:83536.9-83536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130109,18 +132407,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:82677.3-82695.6" - process $proc$libresoc.v:82677$3684 + attribute \src "libresoc.v:83554.3-83572.6" + process $proc$libresoc.v:83554$3765 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:82678.5-82678.29" + attribute \src "libresoc.v:83555.5-83555.29" switch \initial - attribute \src "libresoc.v:82678.9-82678.17" + attribute \src "libresoc.v:83555.9-83555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130144,18 +132442,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:82696.3-82714.6" - process $proc$libresoc.v:82696$3685 + attribute \src "libresoc.v:83573.3-83591.6" + process $proc$libresoc.v:83573$3766 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:82697.5-82697.29" + attribute \src "libresoc.v:83574.5-83574.29" switch \initial - attribute \src "libresoc.v:82697.9-82697.17" + attribute \src "libresoc.v:83574.9-83574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130179,18 +132477,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:82715.3-82733.6" - process $proc$libresoc.v:82715$3686 + attribute \src "libresoc.v:83592.3-83610.6" + process $proc$libresoc.v:83592$3767 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:82716.5-82716.29" + attribute \src "libresoc.v:83593.5-83593.29" switch \initial - attribute \src "libresoc.v:82716.9-82716.17" + attribute \src "libresoc.v:83593.9-83593.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130214,18 +132512,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:82734.3-82752.6" - process $proc$libresoc.v:82734$3687 + attribute \src "libresoc.v:83611.3-83629.6" + process $proc$libresoc.v:83611$3768 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:82735.5-82735.29" + attribute \src "libresoc.v:83612.5-83612.29" switch \initial - attribute \src "libresoc.v:82735.9-82735.17" + attribute \src "libresoc.v:83612.9-83612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130249,18 +132547,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:82753.3-82771.6" - process $proc$libresoc.v:82753$3688 + attribute \src "libresoc.v:83630.3-83648.6" + process $proc$libresoc.v:83630$3769 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:82754.5-82754.29" + attribute \src "libresoc.v:83631.5-83631.29" switch \initial - attribute \src "libresoc.v:82754.9-82754.17" + attribute \src "libresoc.v:83631.9-83631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130284,18 +132582,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:82772.3-82790.6" - process $proc$libresoc.v:82772$3689 + attribute \src "libresoc.v:83649.3-83667.6" + process $proc$libresoc.v:83649$3770 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:82773.5-82773.29" + attribute \src "libresoc.v:83650.5-83650.29" switch \initial - attribute \src "libresoc.v:82773.9-82773.17" + attribute \src "libresoc.v:83650.9-83650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130319,18 +132617,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:82791.3-82809.6" - process $proc$libresoc.v:82791$3690 + attribute \src "libresoc.v:83668.3-83686.6" + process $proc$libresoc.v:83668$3771 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:82792.5-82792.29" + attribute \src "libresoc.v:83669.5-83669.29" switch \initial - attribute \src "libresoc.v:82792.9-82792.17" + attribute \src "libresoc.v:83669.9-83669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130354,18 +132652,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:82810.3-82828.6" - process $proc$libresoc.v:82810$3691 + attribute \src "libresoc.v:83687.3-83705.6" + process $proc$libresoc.v:83687$3772 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:82811.5-82811.29" + attribute \src "libresoc.v:83688.5-83688.29" switch \initial - attribute \src "libresoc.v:82811.9-82811.17" + attribute \src "libresoc.v:83688.9-83688.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130389,18 +132687,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:82829.3-82847.6" - process $proc$libresoc.v:82829$3692 + attribute \src "libresoc.v:83706.3-83724.6" + process $proc$libresoc.v:83706$3773 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:82830.5-82830.29" + attribute \src "libresoc.v:83707.5-83707.29" switch \initial - attribute \src "libresoc.v:82830.9-82830.17" + attribute \src "libresoc.v:83707.9-83707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130424,18 +132722,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:82848.3-82866.6" - process $proc$libresoc.v:82848$3693 + attribute \src "libresoc.v:83725.3-83743.6" + process $proc$libresoc.v:83725$3774 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:82849.5-82849.29" + attribute \src "libresoc.v:83726.5-83726.29" switch \initial - attribute \src "libresoc.v:82849.9-82849.17" + attribute \src "libresoc.v:83726.9-83726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130459,18 +132757,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:82867.3-82885.6" - process $proc$libresoc.v:82867$3694 + attribute \src "libresoc.v:83744.3-83762.6" + process $proc$libresoc.v:83744$3775 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:82868.5-82868.29" + attribute \src "libresoc.v:83745.5-83745.29" switch \initial - attribute \src "libresoc.v:82868.9-82868.17" + attribute \src "libresoc.v:83745.9-83745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130494,18 +132792,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:82886.3-82904.6" - process $proc$libresoc.v:82886$3695 + attribute \src "libresoc.v:83763.3-83781.6" + process $proc$libresoc.v:83763$3776 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:82887.5-82887.29" + attribute \src "libresoc.v:83764.5-83764.29" switch \initial - attribute \src "libresoc.v:82887.9-82887.17" + attribute \src "libresoc.v:83764.9-83764.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130529,18 +132827,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:82905.3-82923.6" - process $proc$libresoc.v:82905$3696 + attribute \src "libresoc.v:83782.3-83800.6" + process $proc$libresoc.v:83782$3777 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:82906.5-82906.29" + attribute \src "libresoc.v:83783.5-83783.29" switch \initial - attribute \src "libresoc.v:82906.9-82906.17" + attribute \src "libresoc.v:83783.9-83783.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130564,18 +132862,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:82924.3-82942.6" - process $proc$libresoc.v:82924$3697 + attribute \src "libresoc.v:83801.3-83819.6" + process $proc$libresoc.v:83801$3778 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:82925.5-82925.29" + attribute \src "libresoc.v:83802.5-83802.29" switch \initial - attribute \src "libresoc.v:82925.9-82925.17" + attribute \src "libresoc.v:83802.9-83802.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130599,18 +132897,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:82943.3-82961.6" - process $proc$libresoc.v:82943$3698 + attribute \src "libresoc.v:83820.3-83838.6" + process $proc$libresoc.v:83820$3779 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:82944.5-82944.29" + attribute \src "libresoc.v:83821.5-83821.29" switch \initial - attribute \src "libresoc.v:82944.9-82944.17" + attribute \src "libresoc.v:83821.9-83821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130634,18 +132932,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:82962.3-82980.6" - process $proc$libresoc.v:82962$3699 + attribute \src "libresoc.v:83839.3-83857.6" + process $proc$libresoc.v:83839$3780 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:82963.5-82963.29" + attribute \src "libresoc.v:83840.5-83840.29" switch \initial - attribute \src "libresoc.v:82963.9-82963.17" + attribute \src "libresoc.v:83840.9-83840.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130669,18 +132967,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:82981.3-82999.6" - process $proc$libresoc.v:82981$3700 + attribute \src "libresoc.v:83858.3-83876.6" + process $proc$libresoc.v:83858$3781 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:82982.5-82982.29" + attribute \src "libresoc.v:83859.5-83859.29" switch \initial - attribute \src "libresoc.v:82982.9-82982.17" + attribute \src "libresoc.v:83859.9-83859.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130704,18 +133002,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:83000.3-83018.6" - process $proc$libresoc.v:83000$3701 + attribute \src "libresoc.v:83877.3-83895.6" + process $proc$libresoc.v:83877$3782 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83001.5-83001.29" + attribute \src "libresoc.v:83878.5-83878.29" switch \initial - attribute \src "libresoc.v:83001.9-83001.17" + attribute \src "libresoc.v:83878.9-83878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130739,18 +133037,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:83019.3-83037.6" - process $proc$libresoc.v:83019$3702 + attribute \src "libresoc.v:83896.3-83914.6" + process $proc$libresoc.v:83896$3783 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83020.5-83020.29" + attribute \src "libresoc.v:83897.5-83897.29" switch \initial - attribute \src "libresoc.v:83020.9-83020.17" + attribute \src "libresoc.v:83897.9-83897.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130774,18 +133072,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] end - attribute \src "libresoc.v:83038.3-83056.6" - process $proc$libresoc.v:83038$3703 + attribute \src "libresoc.v:83915.3-83933.6" + process $proc$libresoc.v:83915$3784 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83039.5-83039.29" + attribute \src "libresoc.v:83916.5-83916.29" switch \initial - attribute \src "libresoc.v:83039.9-83039.17" + attribute \src "libresoc.v:83916.9-83916.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130809,18 +133107,18 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:83057.3-83075.6" - process $proc$libresoc.v:83057$3704 + attribute \src "libresoc.v:83934.3-83952.6" + process $proc$libresoc.v:83934$3785 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83058.5-83058.29" + attribute \src "libresoc.v:83935.5-83935.29" switch \initial - attribute \src "libresoc.v:83058.9-83058.17" + attribute \src "libresoc.v:83935.9-83935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -130846,112 +133144,112 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:83081.1-84228.10" +attribute \src "libresoc.v:83958.1-85105.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:83524.3-83560.6" + attribute \src "libresoc.v:84401.3-84437.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:83672.3-83708.6" + attribute \src "libresoc.v:84549.3-84585.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84153.3-84189.6" + attribute \src "libresoc.v:85030.3-85066.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84190.3-84226.6" + attribute \src "libresoc.v:85067.3-85103.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:83487.3-83523.6" + attribute \src "libresoc.v:84364.3-84400.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:83635.3-83671.6" + attribute \src "libresoc.v:84512.3-84548.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:83968.3-84004.6" + attribute \src "libresoc.v:84845.3-84881.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:83339.3-83375.6" + attribute \src "libresoc.v:84216.3-84252.6" wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84005.3-84041.6" + attribute \src "libresoc.v:84882.3-84918.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84042.3-84078.6" + attribute \src "libresoc.v:84919.3-84955.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84079.3-84115.6" + attribute \src "libresoc.v:84956.3-84992.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:83746.3-83782.6" + attribute \src "libresoc.v:84623.3-84659.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:83561.3-83597.6" + attribute \src "libresoc.v:84438.3-84474.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:83598.3-83634.6" + attribute \src "libresoc.v:84475.3-84511.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:83820.3-83856.6" + attribute \src "libresoc.v:84697.3-84733.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:83376.3-83412.6" + attribute \src "libresoc.v:84253.3-84289.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:83894.3-83930.6" + attribute \src "libresoc.v:84771.3-84807.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84116.3-84152.6" + attribute \src "libresoc.v:84993.3-85029.6" wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:83450.3-83486.6" + attribute \src "libresoc.v:84327.3-84363.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:83783.3-83819.6" + attribute \src "libresoc.v:84660.3-84696.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:83931.3-83967.6" + attribute \src "libresoc.v:84808.3-84844.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:83857.3-83893.6" + attribute \src "libresoc.v:84734.3-84770.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:83709.3-83745.6" + attribute \src "libresoc.v:84586.3-84622.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:83413.3-83449.6" + attribute \src "libresoc.v:84290.3-84326.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:83082.7-83082.20" + attribute \src "libresoc.v:83959.7-83959.20" wire $0\initial[0:0] - attribute \src "libresoc.v:83524.3-83560.6" + attribute \src "libresoc.v:84401.3-84437.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:83672.3-83708.6" + attribute \src "libresoc.v:84549.3-84585.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84153.3-84189.6" + attribute \src "libresoc.v:85030.3-85066.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84190.3-84226.6" + attribute \src "libresoc.v:85067.3-85103.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:83487.3-83523.6" + attribute \src "libresoc.v:84364.3-84400.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:83635.3-83671.6" + attribute \src "libresoc.v:84512.3-84548.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:83968.3-84004.6" + attribute \src "libresoc.v:84845.3-84881.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:83339.3-83375.6" + attribute \src "libresoc.v:84216.3-84252.6" wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84005.3-84041.6" + attribute \src "libresoc.v:84882.3-84918.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84042.3-84078.6" + attribute \src "libresoc.v:84919.3-84955.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84079.3-84115.6" + attribute \src "libresoc.v:84956.3-84992.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:83746.3-83782.6" + attribute \src "libresoc.v:84623.3-84659.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:83561.3-83597.6" + attribute \src "libresoc.v:84438.3-84474.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:83598.3-83634.6" + attribute \src "libresoc.v:84475.3-84511.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:83820.3-83856.6" + attribute \src "libresoc.v:84697.3-84733.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:83376.3-83412.6" + attribute \src "libresoc.v:84253.3-84289.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:83894.3-83930.6" + attribute \src "libresoc.v:84771.3-84807.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84116.3-84152.6" + attribute \src "libresoc.v:84993.3-85029.6" wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:83450.3-83486.6" + attribute \src "libresoc.v:84327.3-84363.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:83783.3-83819.6" + attribute \src "libresoc.v:84660.3-84696.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:83931.3-83967.6" + attribute \src "libresoc.v:84808.3-84844.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:83857.3-83893.6" + attribute \src "libresoc.v:84734.3-84770.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:83709.3-83745.6" + attribute \src "libresoc.v:84586.3-84622.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:83413.3-83449.6" + attribute \src "libresoc.v:84290.3-84326.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub10_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -130961,7 +133259,7 @@ module \dec31_dec_sub10 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub10_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -130969,15 +133267,15 @@ module \dec31_dec_sub10 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub10_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub10_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -131009,7 +133307,7 @@ module \dec31_dec_sub10 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -131024,7 +133322,7 @@ module \dec31_dec_sub10 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub10_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -131032,7 +133330,7 @@ module \dec31_dec_sub10 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub10_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -131049,13 +133347,13 @@ module \dec31_dec_sub10 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub10_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub10_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -131131,13 +133429,13 @@ module \dec31_dec_sub10 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub10_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -131145,64 +133443,64 @@ module \dec31_dec_sub10 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub10_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub10_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub10_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "libresoc.v:83082.7-83082.15" + attribute \src "libresoc.v:83959.7-83959.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:83082.7-83082.20" - process $proc$libresoc.v:83082$3730 + attribute \src "libresoc.v:83959.7-83959.20" + process $proc$libresoc.v:83959$3811 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:83339.3-83375.6" - process $proc$libresoc.v:83339$3706 + attribute \src "libresoc.v:84216.3-84252.6" + process $proc$libresoc.v:84216$3787 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:83340.5-83340.29" + attribute \src "libresoc.v:84217.5-84217.29" switch \initial - attribute \src "libresoc.v:83340.9-83340.17" + attribute \src "libresoc.v:84217.9-84217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131250,18 +133548,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] end - attribute \src "libresoc.v:83376.3-83412.6" - process $proc$libresoc.v:83376$3707 + attribute \src "libresoc.v:84253.3-84289.6" + process $proc$libresoc.v:84253$3788 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:83377.5-83377.29" + attribute \src "libresoc.v:84254.5-84254.29" switch \initial - attribute \src "libresoc.v:83377.9-83377.17" + attribute \src "libresoc.v:84254.9-84254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131309,18 +133607,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:83413.3-83449.6" - process $proc$libresoc.v:83413$3708 + attribute \src "libresoc.v:84290.3-84326.6" + process $proc$libresoc.v:84290$3789 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:83414.5-83414.29" + attribute \src "libresoc.v:84291.5-84291.29" switch \initial - attribute \src "libresoc.v:83414.9-83414.17" + attribute \src "libresoc.v:84291.9-84291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131368,18 +133666,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:83450.3-83486.6" - process $proc$libresoc.v:83450$3709 + attribute \src "libresoc.v:84327.3-84363.6" + process $proc$libresoc.v:84327$3790 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:83451.5-83451.29" + attribute \src "libresoc.v:84328.5-84328.29" switch \initial - attribute \src "libresoc.v:83451.9-83451.17" + attribute \src "libresoc.v:84328.9-84328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131427,18 +133725,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:83487.3-83523.6" - process $proc$libresoc.v:83487$3710 + attribute \src "libresoc.v:84364.3-84400.6" + process $proc$libresoc.v:84364$3791 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:83488.5-83488.29" + attribute \src "libresoc.v:84365.5-84365.29" switch \initial - attribute \src "libresoc.v:83488.9-83488.17" + attribute \src "libresoc.v:84365.9-84365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131486,18 +133784,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:83524.3-83560.6" - process $proc$libresoc.v:83524$3711 + attribute \src "libresoc.v:84401.3-84437.6" + process $proc$libresoc.v:84401$3792 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:83525.5-83525.29" + attribute \src "libresoc.v:84402.5-84402.29" switch \initial - attribute \src "libresoc.v:83525.9-83525.17" + attribute \src "libresoc.v:84402.9-84402.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131545,18 +133843,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:83561.3-83597.6" - process $proc$libresoc.v:83561$3712 + attribute \src "libresoc.v:84438.3-84474.6" + process $proc$libresoc.v:84438$3793 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:83562.5-83562.29" + attribute \src "libresoc.v:84439.5-84439.29" switch \initial - attribute \src "libresoc.v:83562.9-83562.17" + attribute \src "libresoc.v:84439.9-84439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131604,18 +133902,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:83598.3-83634.6" - process $proc$libresoc.v:83598$3713 + attribute \src "libresoc.v:84475.3-84511.6" + process $proc$libresoc.v:84475$3794 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:83599.5-83599.29" + attribute \src "libresoc.v:84476.5-84476.29" switch \initial - attribute \src "libresoc.v:83599.9-83599.17" + attribute \src "libresoc.v:84476.9-84476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131663,18 +133961,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:83635.3-83671.6" - process $proc$libresoc.v:83635$3714 + attribute \src "libresoc.v:84512.3-84548.6" + process $proc$libresoc.v:84512$3795 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:83636.5-83636.29" + attribute \src "libresoc.v:84513.5-84513.29" switch \initial - attribute \src "libresoc.v:83636.9-83636.17" + attribute \src "libresoc.v:84513.9-84513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131722,18 +134020,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:83672.3-83708.6" - process $proc$libresoc.v:83672$3715 + attribute \src "libresoc.v:84549.3-84585.6" + process $proc$libresoc.v:84549$3796 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:83673.5-83673.29" + attribute \src "libresoc.v:84550.5-84550.29" switch \initial - attribute \src "libresoc.v:83673.9-83673.17" + attribute \src "libresoc.v:84550.9-84550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131781,18 +134079,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:83709.3-83745.6" - process $proc$libresoc.v:83709$3716 + attribute \src "libresoc.v:84586.3-84622.6" + process $proc$libresoc.v:84586$3797 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:83710.5-83710.29" + attribute \src "libresoc.v:84587.5-84587.29" switch \initial - attribute \src "libresoc.v:83710.9-83710.17" + attribute \src "libresoc.v:84587.9-84587.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131840,18 +134138,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:83746.3-83782.6" - process $proc$libresoc.v:83746$3717 + attribute \src "libresoc.v:84623.3-84659.6" + process $proc$libresoc.v:84623$3798 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:83747.5-83747.29" + attribute \src "libresoc.v:84624.5-84624.29" switch \initial - attribute \src "libresoc.v:83747.9-83747.17" + attribute \src "libresoc.v:84624.9-84624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131899,18 +134197,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:83783.3-83819.6" - process $proc$libresoc.v:83783$3718 + attribute \src "libresoc.v:84660.3-84696.6" + process $proc$libresoc.v:84660$3799 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:83784.5-83784.29" + attribute \src "libresoc.v:84661.5-84661.29" switch \initial - attribute \src "libresoc.v:83784.9-83784.17" + attribute \src "libresoc.v:84661.9-84661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -131958,18 +134256,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:83820.3-83856.6" - process $proc$libresoc.v:83820$3719 + attribute \src "libresoc.v:84697.3-84733.6" + process $proc$libresoc.v:84697$3800 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:83821.5-83821.29" + attribute \src "libresoc.v:84698.5-84698.29" switch \initial - attribute \src "libresoc.v:83821.9-83821.17" + attribute \src "libresoc.v:84698.9-84698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132017,18 +134315,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:83857.3-83893.6" - process $proc$libresoc.v:83857$3720 + attribute \src "libresoc.v:84734.3-84770.6" + process $proc$libresoc.v:84734$3801 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:83858.5-83858.29" + attribute \src "libresoc.v:84735.5-84735.29" switch \initial - attribute \src "libresoc.v:83858.9-83858.17" + attribute \src "libresoc.v:84735.9-84735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132076,18 +134374,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:83894.3-83930.6" - process $proc$libresoc.v:83894$3721 + attribute \src "libresoc.v:84771.3-84807.6" + process $proc$libresoc.v:84771$3802 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:83895.5-83895.29" + attribute \src "libresoc.v:84772.5-84772.29" switch \initial - attribute \src "libresoc.v:83895.9-83895.17" + attribute \src "libresoc.v:84772.9-84772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132135,18 +134433,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:83931.3-83967.6" - process $proc$libresoc.v:83931$3722 + attribute \src "libresoc.v:84808.3-84844.6" + process $proc$libresoc.v:84808$3803 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:83932.5-83932.29" + attribute \src "libresoc.v:84809.5-84809.29" switch \initial - attribute \src "libresoc.v:83932.9-83932.17" + attribute \src "libresoc.v:84809.9-84809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132194,18 +134492,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:83968.3-84004.6" - process $proc$libresoc.v:83968$3723 + attribute \src "libresoc.v:84845.3-84881.6" + process $proc$libresoc.v:84845$3804 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:83969.5-83969.29" + attribute \src "libresoc.v:84846.5-84846.29" switch \initial - attribute \src "libresoc.v:83969.9-83969.17" + attribute \src "libresoc.v:84846.9-84846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132253,18 +134551,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:84005.3-84041.6" - process $proc$libresoc.v:84005$3724 + attribute \src "libresoc.v:84882.3-84918.6" + process $proc$libresoc.v:84882$3805 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84006.5-84006.29" + attribute \src "libresoc.v:84883.5-84883.29" switch \initial - attribute \src "libresoc.v:84006.9-84006.17" + attribute \src "libresoc.v:84883.9-84883.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132312,18 +134610,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:84042.3-84078.6" - process $proc$libresoc.v:84042$3725 + attribute \src "libresoc.v:84919.3-84955.6" + process $proc$libresoc.v:84919$3806 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84043.5-84043.29" + attribute \src "libresoc.v:84920.5-84920.29" switch \initial - attribute \src "libresoc.v:84043.9-84043.17" + attribute \src "libresoc.v:84920.9-84920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132371,18 +134669,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:84079.3-84115.6" - process $proc$libresoc.v:84079$3726 + attribute \src "libresoc.v:84956.3-84992.6" + process $proc$libresoc.v:84956$3807 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84080.5-84080.29" + attribute \src "libresoc.v:84957.5-84957.29" switch \initial - attribute \src "libresoc.v:84080.9-84080.17" + attribute \src "libresoc.v:84957.9-84957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132430,18 +134728,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:84116.3-84152.6" - process $proc$libresoc.v:84116$3727 + attribute \src "libresoc.v:84993.3-85029.6" + process $proc$libresoc.v:84993$3808 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84117.5-84117.29" + attribute \src "libresoc.v:84994.5-84994.29" switch \initial - attribute \src "libresoc.v:84117.9-84117.17" + attribute \src "libresoc.v:84994.9-84994.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132489,18 +134787,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] end - attribute \src "libresoc.v:84153.3-84189.6" - process $proc$libresoc.v:84153$3728 + attribute \src "libresoc.v:85030.3-85066.6" + process $proc$libresoc.v:85030$3809 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:84154.5-84154.29" + attribute \src "libresoc.v:85031.5-85031.29" switch \initial - attribute \src "libresoc.v:84154.9-84154.17" + attribute \src "libresoc.v:85031.9-85031.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132548,18 +134846,18 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:84190.3-84226.6" - process $proc$libresoc.v:84190$3729 + attribute \src "libresoc.v:85067.3-85103.6" + process $proc$libresoc.v:85067$3810 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84191.5-84191.29" + attribute \src "libresoc.v:85068.5-85068.29" switch \initial - attribute \src "libresoc.v:84191.9-84191.17" + attribute \src "libresoc.v:85068.9-85068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01000 @@ -132609,112 +134907,112 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:84232.1-85811.10" +attribute \src "libresoc.v:85109.1-86688.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:84765.3-84819.6" + attribute \src "libresoc.v:85642.3-85696.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:84985.3-85039.6" + attribute \src "libresoc.v:85862.3-85916.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:85700.3-85754.6" + attribute \src "libresoc.v:86577.3-86631.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:85755.3-85809.6" + attribute \src "libresoc.v:86632.3-86686.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:84710.3-84764.6" + attribute \src "libresoc.v:85587.3-85641.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:84930.3-84984.6" + attribute \src "libresoc.v:85807.3-85861.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:85425.3-85479.6" + attribute \src "libresoc.v:86302.3-86356.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:84490.3-84544.6" + attribute \src "libresoc.v:85367.3-85421.6" wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:85480.3-85534.6" + attribute \src "libresoc.v:86357.3-86411.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:85535.3-85589.6" + attribute \src "libresoc.v:86412.3-86466.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:85590.3-85644.6" + attribute \src "libresoc.v:86467.3-86521.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85095.3-85149.6" + attribute \src "libresoc.v:85972.3-86026.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:84820.3-84874.6" + attribute \src "libresoc.v:85697.3-85751.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:84875.3-84929.6" + attribute \src "libresoc.v:85752.3-85806.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85205.3-85259.6" + attribute \src "libresoc.v:86082.3-86136.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:84545.3-84599.6" + attribute \src "libresoc.v:85422.3-85476.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:85315.3-85369.6" + attribute \src "libresoc.v:86192.3-86246.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:85645.3-85699.6" + attribute \src "libresoc.v:86522.3-86576.6" wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:84655.3-84709.6" + attribute \src "libresoc.v:85532.3-85586.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85150.3-85204.6" + attribute \src "libresoc.v:86027.3-86081.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:85370.3-85424.6" + attribute \src "libresoc.v:86247.3-86301.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:85260.3-85314.6" + attribute \src "libresoc.v:86137.3-86191.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85040.3-85094.6" + attribute \src "libresoc.v:85917.3-85971.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:84600.3-84654.6" + attribute \src "libresoc.v:85477.3-85531.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:84233.7-84233.20" + attribute \src "libresoc.v:85110.7-85110.20" wire $0\initial[0:0] - attribute \src "libresoc.v:84765.3-84819.6" + attribute \src "libresoc.v:85642.3-85696.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:84985.3-85039.6" + attribute \src "libresoc.v:85862.3-85916.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:85700.3-85754.6" + attribute \src "libresoc.v:86577.3-86631.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:85755.3-85809.6" + attribute \src "libresoc.v:86632.3-86686.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:84710.3-84764.6" + attribute \src "libresoc.v:85587.3-85641.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:84930.3-84984.6" + attribute \src "libresoc.v:85807.3-85861.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:85425.3-85479.6" + attribute \src "libresoc.v:86302.3-86356.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:84490.3-84544.6" + attribute \src "libresoc.v:85367.3-85421.6" wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:85480.3-85534.6" + attribute \src "libresoc.v:86357.3-86411.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:85535.3-85589.6" + attribute \src "libresoc.v:86412.3-86466.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:85590.3-85644.6" + attribute \src "libresoc.v:86467.3-86521.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85095.3-85149.6" + attribute \src "libresoc.v:85972.3-86026.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:84820.3-84874.6" + attribute \src "libresoc.v:85697.3-85751.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:84875.3-84929.6" + attribute \src "libresoc.v:85752.3-85806.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85205.3-85259.6" + attribute \src "libresoc.v:86082.3-86136.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:84545.3-84599.6" + attribute \src "libresoc.v:85422.3-85476.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:85315.3-85369.6" + attribute \src "libresoc.v:86192.3-86246.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:85645.3-85699.6" + attribute \src "libresoc.v:86522.3-86576.6" wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:84655.3-84709.6" + attribute \src "libresoc.v:85532.3-85586.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85150.3-85204.6" + attribute \src "libresoc.v:86027.3-86081.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:85370.3-85424.6" + attribute \src "libresoc.v:86247.3-86301.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:85260.3-85314.6" + attribute \src "libresoc.v:86137.3-86191.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85040.3-85094.6" + attribute \src "libresoc.v:85917.3-85971.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:84600.3-84654.6" + attribute \src "libresoc.v:85477.3-85531.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub11_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -132724,7 +135022,7 @@ module \dec31_dec_sub11 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub11_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -132732,15 +135030,15 @@ module \dec31_dec_sub11 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub11_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub11_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -132772,7 +135070,7 @@ module \dec31_dec_sub11 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -132787,7 +135085,7 @@ module \dec31_dec_sub11 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub11_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -132795,7 +135093,7 @@ module \dec31_dec_sub11 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub11_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -132812,13 +135110,13 @@ module \dec31_dec_sub11 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub11_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub11_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -132894,13 +135192,13 @@ module \dec31_dec_sub11 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub11_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -132908,64 +135206,64 @@ module \dec31_dec_sub11 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub11_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub11_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub11_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "libresoc.v:84233.7-84233.15" + attribute \src "libresoc.v:85110.7-85110.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:84233.7-84233.20" - process $proc$libresoc.v:84233$3755 + attribute \src "libresoc.v:85110.7-85110.20" + process $proc$libresoc.v:85110$3836 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:84490.3-84544.6" - process $proc$libresoc.v:84490$3731 + attribute \src "libresoc.v:85367.3-85421.6" + process $proc$libresoc.v:85367$3812 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:84491.5-84491.29" + attribute \src "libresoc.v:85368.5-85368.29" switch \initial - attribute \src "libresoc.v:84491.9-84491.17" + attribute \src "libresoc.v:85368.9-85368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133037,18 +135335,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] end - attribute \src "libresoc.v:84545.3-84599.6" - process $proc$libresoc.v:84545$3732 + attribute \src "libresoc.v:85422.3-85476.6" + process $proc$libresoc.v:85422$3813 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:84546.5-84546.29" + attribute \src "libresoc.v:85423.5-85423.29" switch \initial - attribute \src "libresoc.v:84546.9-84546.17" + attribute \src "libresoc.v:85423.9-85423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133120,18 +135418,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:84600.3-84654.6" - process $proc$libresoc.v:84600$3733 + attribute \src "libresoc.v:85477.3-85531.6" + process $proc$libresoc.v:85477$3814 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:84601.5-84601.29" + attribute \src "libresoc.v:85478.5-85478.29" switch \initial - attribute \src "libresoc.v:84601.9-84601.17" + attribute \src "libresoc.v:85478.9-85478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133203,18 +135501,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:84655.3-84709.6" - process $proc$libresoc.v:84655$3734 + attribute \src "libresoc.v:85532.3-85586.6" + process $proc$libresoc.v:85532$3815 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:84656.5-84656.29" + attribute \src "libresoc.v:85533.5-85533.29" switch \initial - attribute \src "libresoc.v:84656.9-84656.17" + attribute \src "libresoc.v:85533.9-85533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133286,18 +135584,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:84710.3-84764.6" - process $proc$libresoc.v:84710$3735 + attribute \src "libresoc.v:85587.3-85641.6" + process $proc$libresoc.v:85587$3816 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:84711.5-84711.29" + attribute \src "libresoc.v:85588.5-85588.29" switch \initial - attribute \src "libresoc.v:84711.9-84711.17" + attribute \src "libresoc.v:85588.9-85588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133369,18 +135667,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:84765.3-84819.6" - process $proc$libresoc.v:84765$3736 + attribute \src "libresoc.v:85642.3-85696.6" + process $proc$libresoc.v:85642$3817 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:84766.5-84766.29" + attribute \src "libresoc.v:85643.5-85643.29" switch \initial - attribute \src "libresoc.v:84766.9-84766.17" + attribute \src "libresoc.v:85643.9-85643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133452,18 +135750,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:84820.3-84874.6" - process $proc$libresoc.v:84820$3737 + attribute \src "libresoc.v:85697.3-85751.6" + process $proc$libresoc.v:85697$3818 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:84821.5-84821.29" + attribute \src "libresoc.v:85698.5-85698.29" switch \initial - attribute \src "libresoc.v:84821.9-84821.17" + attribute \src "libresoc.v:85698.9-85698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133535,18 +135833,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:84875.3-84929.6" - process $proc$libresoc.v:84875$3738 + attribute \src "libresoc.v:85752.3-85806.6" + process $proc$libresoc.v:85752$3819 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:84876.5-84876.29" + attribute \src "libresoc.v:85753.5-85753.29" switch \initial - attribute \src "libresoc.v:84876.9-84876.17" + attribute \src "libresoc.v:85753.9-85753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133618,18 +135916,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:84930.3-84984.6" - process $proc$libresoc.v:84930$3739 + attribute \src "libresoc.v:85807.3-85861.6" + process $proc$libresoc.v:85807$3820 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:84931.5-84931.29" + attribute \src "libresoc.v:85808.5-85808.29" switch \initial - attribute \src "libresoc.v:84931.9-84931.17" + attribute \src "libresoc.v:85808.9-85808.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133701,18 +135999,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:84985.3-85039.6" - process $proc$libresoc.v:84985$3740 + attribute \src "libresoc.v:85862.3-85916.6" + process $proc$libresoc.v:85862$3821 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:84986.5-84986.29" + attribute \src "libresoc.v:85863.5-85863.29" switch \initial - attribute \src "libresoc.v:84986.9-84986.17" + attribute \src "libresoc.v:85863.9-85863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133784,18 +136082,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:85040.3-85094.6" - process $proc$libresoc.v:85040$3741 + attribute \src "libresoc.v:85917.3-85971.6" + process $proc$libresoc.v:85917$3822 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85041.5-85041.29" + attribute \src "libresoc.v:85918.5-85918.29" switch \initial - attribute \src "libresoc.v:85041.9-85041.17" + attribute \src "libresoc.v:85918.9-85918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133867,18 +136165,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:85095.3-85149.6" - process $proc$libresoc.v:85095$3742 + attribute \src "libresoc.v:85972.3-86026.6" + process $proc$libresoc.v:85972$3823 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85096.5-85096.29" + attribute \src "libresoc.v:85973.5-85973.29" switch \initial - attribute \src "libresoc.v:85096.9-85096.17" + attribute \src "libresoc.v:85973.9-85973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -133950,18 +136248,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:85150.3-85204.6" - process $proc$libresoc.v:85150$3743 + attribute \src "libresoc.v:86027.3-86081.6" + process $proc$libresoc.v:86027$3824 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:85151.5-85151.29" + attribute \src "libresoc.v:86028.5-86028.29" switch \initial - attribute \src "libresoc.v:85151.9-85151.17" + attribute \src "libresoc.v:86028.9-86028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134033,18 +136331,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:85205.3-85259.6" - process $proc$libresoc.v:85205$3744 + attribute \src "libresoc.v:86082.3-86136.6" + process $proc$libresoc.v:86082$3825 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85206.5-85206.29" + attribute \src "libresoc.v:86083.5-86083.29" switch \initial - attribute \src "libresoc.v:85206.9-85206.17" + attribute \src "libresoc.v:86083.9-86083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134116,18 +136414,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:85260.3-85314.6" - process $proc$libresoc.v:85260$3745 + attribute \src "libresoc.v:86137.3-86191.6" + process $proc$libresoc.v:86137$3826 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85261.5-85261.29" + attribute \src "libresoc.v:86138.5-86138.29" switch \initial - attribute \src "libresoc.v:85261.9-85261.17" + attribute \src "libresoc.v:86138.9-86138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134199,18 +136497,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:85315.3-85369.6" - process $proc$libresoc.v:85315$3746 + attribute \src "libresoc.v:86192.3-86246.6" + process $proc$libresoc.v:86192$3827 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:85316.5-85316.29" + attribute \src "libresoc.v:86193.5-86193.29" switch \initial - attribute \src "libresoc.v:85316.9-85316.17" + attribute \src "libresoc.v:86193.9-86193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134282,18 +136580,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:85370.3-85424.6" - process $proc$libresoc.v:85370$3747 + attribute \src "libresoc.v:86247.3-86301.6" + process $proc$libresoc.v:86247$3828 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:85371.5-85371.29" + attribute \src "libresoc.v:86248.5-86248.29" switch \initial - attribute \src "libresoc.v:85371.9-85371.17" + attribute \src "libresoc.v:86248.9-86248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134365,18 +136663,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:85425.3-85479.6" - process $proc$libresoc.v:85425$3748 + attribute \src "libresoc.v:86302.3-86356.6" + process $proc$libresoc.v:86302$3829 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:85426.5-85426.29" + attribute \src "libresoc.v:86303.5-86303.29" switch \initial - attribute \src "libresoc.v:85426.9-85426.17" + attribute \src "libresoc.v:86303.9-86303.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134448,18 +136746,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:85480.3-85534.6" - process $proc$libresoc.v:85480$3749 + attribute \src "libresoc.v:86357.3-86411.6" + process $proc$libresoc.v:86357$3830 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:85481.5-85481.29" + attribute \src "libresoc.v:86358.5-86358.29" switch \initial - attribute \src "libresoc.v:85481.9-85481.17" + attribute \src "libresoc.v:86358.9-86358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134531,18 +136829,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:85535.3-85589.6" - process $proc$libresoc.v:85535$3750 + attribute \src "libresoc.v:86412.3-86466.6" + process $proc$libresoc.v:86412$3831 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:85536.5-85536.29" + attribute \src "libresoc.v:86413.5-86413.29" switch \initial - attribute \src "libresoc.v:85536.9-85536.17" + attribute \src "libresoc.v:86413.9-86413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134614,18 +136912,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:85590.3-85644.6" - process $proc$libresoc.v:85590$3751 + attribute \src "libresoc.v:86467.3-86521.6" + process $proc$libresoc.v:86467$3832 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85591.5-85591.29" + attribute \src "libresoc.v:86468.5-86468.29" switch \initial - attribute \src "libresoc.v:85591.9-85591.17" + attribute \src "libresoc.v:86468.9-86468.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134697,18 +136995,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:85645.3-85699.6" - process $proc$libresoc.v:85645$3752 + attribute \src "libresoc.v:86522.3-86576.6" + process $proc$libresoc.v:86522$3833 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:85646.5-85646.29" + attribute \src "libresoc.v:86523.5-86523.29" switch \initial - attribute \src "libresoc.v:85646.9-85646.17" + attribute \src "libresoc.v:86523.9-86523.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134780,18 +137078,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] end - attribute \src "libresoc.v:85700.3-85754.6" - process $proc$libresoc.v:85700$3753 + attribute \src "libresoc.v:86577.3-86631.6" + process $proc$libresoc.v:86577$3834 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:85701.5-85701.29" + attribute \src "libresoc.v:86578.5-86578.29" switch \initial - attribute \src "libresoc.v:85701.9-85701.17" + attribute \src "libresoc.v:86578.9-86578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134863,18 +137161,18 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:85755.3-85809.6" - process $proc$libresoc.v:85755$3754 + attribute \src "libresoc.v:86632.3-86686.6" + process $proc$libresoc.v:86632$3835 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:85756.5-85756.29" + attribute \src "libresoc.v:86633.5-86633.29" switch \initial - attribute \src "libresoc.v:85756.9-85756.17" + attribute \src "libresoc.v:86633.9-86633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -134948,112 +137246,112 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:85815.1-88546.10" +attribute \src "libresoc.v:86692.1-89423.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:86588.3-86690.6" + attribute \src "libresoc.v:87465.3-87567.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87000.3-87102.6" + attribute \src "libresoc.v:87877.3-87979.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:88339.3-88441.6" + attribute \src "libresoc.v:89216.3-89318.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:88442.3-88544.6" + attribute \src "libresoc.v:89319.3-89421.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:86485.3-86587.6" + attribute \src "libresoc.v:87362.3-87464.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:86897.3-86999.6" + attribute \src "libresoc.v:87774.3-87876.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:87824.3-87926.6" + attribute \src "libresoc.v:88701.3-88803.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86073.3-86175.6" + attribute \src "libresoc.v:86950.3-87052.6" wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:87927.3-88029.6" + attribute \src "libresoc.v:88804.3-88906.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88030.3-88132.6" + attribute \src "libresoc.v:88907.3-89009.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88133.3-88235.6" + attribute \src "libresoc.v:89010.3-89112.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:87206.3-87308.6" + attribute \src "libresoc.v:88083.3-88185.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:86691.3-86793.6" + attribute \src "libresoc.v:87568.3-87670.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:86794.3-86896.6" + attribute \src "libresoc.v:87671.3-87773.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:87412.3-87514.6" + attribute \src "libresoc.v:88289.3-88391.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:86176.3-86278.6" + attribute \src "libresoc.v:87053.3-87155.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:87618.3-87720.6" + attribute \src "libresoc.v:88495.3-88597.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88236.3-88338.6" + attribute \src "libresoc.v:89113.3-89215.6" wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:86382.3-86484.6" + attribute \src "libresoc.v:87259.3-87361.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87309.3-87411.6" + attribute \src "libresoc.v:88186.3-88288.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:87721.3-87823.6" + attribute \src "libresoc.v:88598.3-88700.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:87515.3-87617.6" + attribute \src "libresoc.v:88392.3-88494.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87103.3-87205.6" + attribute \src "libresoc.v:87980.3-88082.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:86279.3-86381.6" + attribute \src "libresoc.v:87156.3-87258.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:85816.7-85816.20" + attribute \src "libresoc.v:86693.7-86693.20" wire $0\initial[0:0] - attribute \src "libresoc.v:86588.3-86690.6" + attribute \src "libresoc.v:87465.3-87567.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87000.3-87102.6" + attribute \src "libresoc.v:87877.3-87979.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:88339.3-88441.6" + attribute \src "libresoc.v:89216.3-89318.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:88442.3-88544.6" + attribute \src "libresoc.v:89319.3-89421.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:86485.3-86587.6" + attribute \src "libresoc.v:87362.3-87464.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:86897.3-86999.6" + attribute \src "libresoc.v:87774.3-87876.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:87824.3-87926.6" + attribute \src "libresoc.v:88701.3-88803.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86073.3-86175.6" + attribute \src "libresoc.v:86950.3-87052.6" wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:87927.3-88029.6" + attribute \src "libresoc.v:88804.3-88906.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88030.3-88132.6" + attribute \src "libresoc.v:88907.3-89009.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88133.3-88235.6" + attribute \src "libresoc.v:89010.3-89112.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:87206.3-87308.6" + attribute \src "libresoc.v:88083.3-88185.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:86691.3-86793.6" + attribute \src "libresoc.v:87568.3-87670.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:86794.3-86896.6" + attribute \src "libresoc.v:87671.3-87773.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:87412.3-87514.6" + attribute \src "libresoc.v:88289.3-88391.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:86176.3-86278.6" + attribute \src "libresoc.v:87053.3-87155.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:87618.3-87720.6" + attribute \src "libresoc.v:88495.3-88597.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88236.3-88338.6" + attribute \src "libresoc.v:89113.3-89215.6" wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:86382.3-86484.6" + attribute \src "libresoc.v:87259.3-87361.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87309.3-87411.6" + attribute \src "libresoc.v:88186.3-88288.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:87721.3-87823.6" + attribute \src "libresoc.v:88598.3-88700.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:87515.3-87617.6" + attribute \src "libresoc.v:88392.3-88494.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87103.3-87205.6" + attribute \src "libresoc.v:87980.3-88082.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:86279.3-86381.6" + attribute \src "libresoc.v:87156.3-87258.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub15_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -135063,7 +137361,7 @@ module \dec31_dec_sub15 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub15_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -135071,15 +137369,15 @@ module \dec31_dec_sub15 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub15_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub15_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -135111,7 +137409,7 @@ module \dec31_dec_sub15 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -135126,7 +137424,7 @@ module \dec31_dec_sub15 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub15_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -135134,7 +137432,7 @@ module \dec31_dec_sub15 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub15_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -135151,13 +137449,13 @@ module \dec31_dec_sub15 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub15_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub15_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -135233,13 +137531,13 @@ module \dec31_dec_sub15 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub15_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -135247,64 +137545,64 @@ module \dec31_dec_sub15 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub15_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub15_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub15_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "libresoc.v:85816.7-85816.15" + attribute \src "libresoc.v:86693.7-86693.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:85816.7-85816.20" - process $proc$libresoc.v:85816$3780 + attribute \src "libresoc.v:86693.7-86693.20" + process $proc$libresoc.v:86693$3861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:86073.3-86175.6" - process $proc$libresoc.v:86073$3756 + attribute \src "libresoc.v:86950.3-87052.6" + process $proc$libresoc.v:86950$3837 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:86074.5-86074.29" + attribute \src "libresoc.v:86951.5-86951.29" switch \initial - attribute \src "libresoc.v:86074.9-86074.17" + attribute \src "libresoc.v:86951.9-86951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -135440,18 +137738,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] end - attribute \src "libresoc.v:86176.3-86278.6" - process $proc$libresoc.v:86176$3757 + attribute \src "libresoc.v:87053.3-87155.6" + process $proc$libresoc.v:87053$3838 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:86177.5-86177.29" + attribute \src "libresoc.v:87054.5-87054.29" switch \initial - attribute \src "libresoc.v:86177.9-86177.17" + attribute \src "libresoc.v:87054.9-87054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -135587,18 +137885,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:86279.3-86381.6" - process $proc$libresoc.v:86279$3758 + attribute \src "libresoc.v:87156.3-87258.6" + process $proc$libresoc.v:87156$3839 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:86280.5-86280.29" + attribute \src "libresoc.v:87157.5-87157.29" switch \initial - attribute \src "libresoc.v:86280.9-86280.17" + attribute \src "libresoc.v:87157.9-87157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -135734,18 +138032,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:86382.3-86484.6" - process $proc$libresoc.v:86382$3759 + attribute \src "libresoc.v:87259.3-87361.6" + process $proc$libresoc.v:87259$3840 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:86383.5-86383.29" + attribute \src "libresoc.v:87260.5-87260.29" switch \initial - attribute \src "libresoc.v:86383.9-86383.17" + attribute \src "libresoc.v:87260.9-87260.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -135881,18 +138179,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:86485.3-86587.6" - process $proc$libresoc.v:86485$3760 + attribute \src "libresoc.v:87362.3-87464.6" + process $proc$libresoc.v:87362$3841 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:86486.5-86486.29" + attribute \src "libresoc.v:87363.5-87363.29" switch \initial - attribute \src "libresoc.v:86486.9-86486.17" + attribute \src "libresoc.v:87363.9-87363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136028,18 +138326,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:86588.3-86690.6" - process $proc$libresoc.v:86588$3761 + attribute \src "libresoc.v:87465.3-87567.6" + process $proc$libresoc.v:87465$3842 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:86589.5-86589.29" + attribute \src "libresoc.v:87466.5-87466.29" switch \initial - attribute \src "libresoc.v:86589.9-86589.17" + attribute \src "libresoc.v:87466.9-87466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136175,18 +138473,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:86691.3-86793.6" - process $proc$libresoc.v:86691$3762 + attribute \src "libresoc.v:87568.3-87670.6" + process $proc$libresoc.v:87568$3843 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:86692.5-86692.29" + attribute \src "libresoc.v:87569.5-87569.29" switch \initial - attribute \src "libresoc.v:86692.9-86692.17" + attribute \src "libresoc.v:87569.9-87569.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136322,18 +138620,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:86794.3-86896.6" - process $proc$libresoc.v:86794$3763 + attribute \src "libresoc.v:87671.3-87773.6" + process $proc$libresoc.v:87671$3844 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:86795.5-86795.29" + attribute \src "libresoc.v:87672.5-87672.29" switch \initial - attribute \src "libresoc.v:86795.9-86795.17" + attribute \src "libresoc.v:87672.9-87672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136469,18 +138767,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:86897.3-86999.6" - process $proc$libresoc.v:86897$3764 + attribute \src "libresoc.v:87774.3-87876.6" + process $proc$libresoc.v:87774$3845 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:86898.5-86898.29" + attribute \src "libresoc.v:87775.5-87775.29" switch \initial - attribute \src "libresoc.v:86898.9-86898.17" + attribute \src "libresoc.v:87775.9-87775.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136616,18 +138914,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:87000.3-87102.6" - process $proc$libresoc.v:87000$3765 + attribute \src "libresoc.v:87877.3-87979.6" + process $proc$libresoc.v:87877$3846 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:87001.5-87001.29" + attribute \src "libresoc.v:87878.5-87878.29" switch \initial - attribute \src "libresoc.v:87001.9-87001.17" + attribute \src "libresoc.v:87878.9-87878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136763,18 +139061,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:87103.3-87205.6" - process $proc$libresoc.v:87103$3766 + attribute \src "libresoc.v:87980.3-88082.6" + process $proc$libresoc.v:87980$3847 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:87104.5-87104.29" + attribute \src "libresoc.v:87981.5-87981.29" switch \initial - attribute \src "libresoc.v:87104.9-87104.17" + attribute \src "libresoc.v:87981.9-87981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -136910,18 +139208,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:87206.3-87308.6" - process $proc$libresoc.v:87206$3767 + attribute \src "libresoc.v:88083.3-88185.6" + process $proc$libresoc.v:88083$3848 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87207.5-87207.29" + attribute \src "libresoc.v:88084.5-88084.29" switch \initial - attribute \src "libresoc.v:87207.9-87207.17" + attribute \src "libresoc.v:88084.9-88084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137057,18 +139355,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:87309.3-87411.6" - process $proc$libresoc.v:87309$3768 + attribute \src "libresoc.v:88186.3-88288.6" + process $proc$libresoc.v:88186$3849 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:87310.5-87310.29" + attribute \src "libresoc.v:88187.5-88187.29" switch \initial - attribute \src "libresoc.v:87310.9-87310.17" + attribute \src "libresoc.v:88187.9-88187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137204,18 +139502,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:87412.3-87514.6" - process $proc$libresoc.v:87412$3769 + attribute \src "libresoc.v:88289.3-88391.6" + process $proc$libresoc.v:88289$3850 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:87413.5-87413.29" + attribute \src "libresoc.v:88290.5-88290.29" switch \initial - attribute \src "libresoc.v:87413.9-87413.17" + attribute \src "libresoc.v:88290.9-88290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137351,18 +139649,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:87515.3-87617.6" - process $proc$libresoc.v:87515$3770 + attribute \src "libresoc.v:88392.3-88494.6" + process $proc$libresoc.v:88392$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87516.5-87516.29" + attribute \src "libresoc.v:88393.5-88393.29" switch \initial - attribute \src "libresoc.v:87516.9-87516.17" + attribute \src "libresoc.v:88393.9-88393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137498,18 +139796,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:87618.3-87720.6" - process $proc$libresoc.v:87618$3771 + attribute \src "libresoc.v:88495.3-88597.6" + process $proc$libresoc.v:88495$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:87619.5-87619.29" + attribute \src "libresoc.v:88496.5-88496.29" switch \initial - attribute \src "libresoc.v:87619.9-87619.17" + attribute \src "libresoc.v:88496.9-88496.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137645,18 +139943,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:87721.3-87823.6" - process $proc$libresoc.v:87721$3772 + attribute \src "libresoc.v:88598.3-88700.6" + process $proc$libresoc.v:88598$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:87722.5-87722.29" + attribute \src "libresoc.v:88599.5-88599.29" switch \initial - attribute \src "libresoc.v:87722.9-87722.17" + attribute \src "libresoc.v:88599.9-88599.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137792,18 +140090,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:87824.3-87926.6" - process $proc$libresoc.v:87824$3773 + attribute \src "libresoc.v:88701.3-88803.6" + process $proc$libresoc.v:88701$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:87825.5-87825.29" + attribute \src "libresoc.v:88702.5-88702.29" switch \initial - attribute \src "libresoc.v:87825.9-87825.17" + attribute \src "libresoc.v:88702.9-88702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -137939,18 +140237,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:87927.3-88029.6" - process $proc$libresoc.v:87927$3774 + attribute \src "libresoc.v:88804.3-88906.6" + process $proc$libresoc.v:88804$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:87928.5-87928.29" + attribute \src "libresoc.v:88805.5-88805.29" switch \initial - attribute \src "libresoc.v:87928.9-87928.17" + attribute \src "libresoc.v:88805.9-88805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138086,18 +140384,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:88030.3-88132.6" - process $proc$libresoc.v:88030$3775 + attribute \src "libresoc.v:88907.3-89009.6" + process $proc$libresoc.v:88907$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88031.5-88031.29" + attribute \src "libresoc.v:88908.5-88908.29" switch \initial - attribute \src "libresoc.v:88031.9-88031.17" + attribute \src "libresoc.v:88908.9-88908.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138233,18 +140531,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:88133.3-88235.6" - process $proc$libresoc.v:88133$3776 + attribute \src "libresoc.v:89010.3-89112.6" + process $proc$libresoc.v:89010$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:88134.5-88134.29" + attribute \src "libresoc.v:89011.5-89011.29" switch \initial - attribute \src "libresoc.v:88134.9-88134.17" + attribute \src "libresoc.v:89011.9-89011.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138380,18 +140678,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:88236.3-88338.6" - process $proc$libresoc.v:88236$3777 + attribute \src "libresoc.v:89113.3-89215.6" + process $proc$libresoc.v:89113$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:88237.5-88237.29" + attribute \src "libresoc.v:89114.5-89114.29" switch \initial - attribute \src "libresoc.v:88237.9-88237.17" + attribute \src "libresoc.v:89114.9-89114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138527,18 +140825,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] end - attribute \src "libresoc.v:88339.3-88441.6" - process $proc$libresoc.v:88339$3778 + attribute \src "libresoc.v:89216.3-89318.6" + process $proc$libresoc.v:89216$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:88340.5-88340.29" + attribute \src "libresoc.v:89217.5-89217.29" switch \initial - attribute \src "libresoc.v:88340.9-88340.17" + attribute \src "libresoc.v:89217.9-89217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138674,18 +140972,18 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:88442.3-88544.6" - process $proc$libresoc.v:88442$3779 + attribute \src "libresoc.v:89319.3-89421.6" + process $proc$libresoc.v:89319$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:88443.5-88443.29" + attribute \src "libresoc.v:89320.5-89320.29" switch \initial - attribute \src "libresoc.v:88443.9-88443.17" + attribute \src "libresoc.v:89320.9-89320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -138823,112 +141121,112 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:88550.1-89049.10" +attribute \src "libresoc.v:89427.1-89926.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:88858.3-88867.6" + attribute \src "libresoc.v:89735.3-89744.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:88898.3-88907.6" + attribute \src "libresoc.v:89775.3-89784.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89028.3-89037.6" + attribute \src "libresoc.v:89905.3-89914.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89038.3-89047.6" + attribute \src "libresoc.v:89915.3-89924.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:88848.3-88857.6" + attribute \src "libresoc.v:89725.3-89734.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:88888.3-88897.6" + attribute \src "libresoc.v:89765.3-89774.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:88978.3-88987.6" + attribute \src "libresoc.v:89855.3-89864.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:88808.3-88817.6" + attribute \src "libresoc.v:89685.3-89694.6" wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:88988.3-88997.6" + attribute \src "libresoc.v:89865.3-89874.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:88998.3-89007.6" + attribute \src "libresoc.v:89875.3-89884.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89008.3-89017.6" + attribute \src "libresoc.v:89885.3-89894.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:88918.3-88927.6" + attribute \src "libresoc.v:89795.3-89804.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:88868.3-88877.6" + attribute \src "libresoc.v:89745.3-89754.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:88878.3-88887.6" + attribute \src "libresoc.v:89755.3-89764.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:88938.3-88947.6" + attribute \src "libresoc.v:89815.3-89824.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:88818.3-88827.6" + attribute \src "libresoc.v:89695.3-89704.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:88958.3-88967.6" + attribute \src "libresoc.v:89835.3-89844.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89018.3-89027.6" + attribute \src "libresoc.v:89895.3-89904.6" wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:88838.3-88847.6" + attribute \src "libresoc.v:89715.3-89724.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:88928.3-88937.6" + attribute \src "libresoc.v:89805.3-89814.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:88968.3-88977.6" + attribute \src "libresoc.v:89845.3-89854.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:88948.3-88957.6" + attribute \src "libresoc.v:89825.3-89834.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:88908.3-88917.6" + attribute \src "libresoc.v:89785.3-89794.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:88828.3-88837.6" + attribute \src "libresoc.v:89705.3-89714.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:88551.7-88551.20" + attribute \src "libresoc.v:89428.7-89428.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88858.3-88867.6" + attribute \src "libresoc.v:89735.3-89744.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:88898.3-88907.6" + attribute \src "libresoc.v:89775.3-89784.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89028.3-89037.6" + attribute \src "libresoc.v:89905.3-89914.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89038.3-89047.6" + attribute \src "libresoc.v:89915.3-89924.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:88848.3-88857.6" + attribute \src "libresoc.v:89725.3-89734.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:88888.3-88897.6" + attribute \src "libresoc.v:89765.3-89774.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:88978.3-88987.6" + attribute \src "libresoc.v:89855.3-89864.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:88808.3-88817.6" + attribute \src "libresoc.v:89685.3-89694.6" wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:88988.3-88997.6" + attribute \src "libresoc.v:89865.3-89874.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:88998.3-89007.6" + attribute \src "libresoc.v:89875.3-89884.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89008.3-89017.6" + attribute \src "libresoc.v:89885.3-89894.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:88918.3-88927.6" + attribute \src "libresoc.v:89795.3-89804.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:88868.3-88877.6" + attribute \src "libresoc.v:89745.3-89754.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:88878.3-88887.6" + attribute \src "libresoc.v:89755.3-89764.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:88938.3-88947.6" + attribute \src "libresoc.v:89815.3-89824.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:88818.3-88827.6" + attribute \src "libresoc.v:89695.3-89704.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:88958.3-88967.6" + attribute \src "libresoc.v:89835.3-89844.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89018.3-89027.6" + attribute \src "libresoc.v:89895.3-89904.6" wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:88838.3-88847.6" + attribute \src "libresoc.v:89715.3-89724.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:88928.3-88937.6" + attribute \src "libresoc.v:89805.3-89814.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:88968.3-88977.6" + attribute \src "libresoc.v:89845.3-89854.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:88948.3-88957.6" + attribute \src "libresoc.v:89825.3-89834.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:88908.3-88917.6" + attribute \src "libresoc.v:89785.3-89794.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:88828.3-88837.6" + attribute \src "libresoc.v:89705.3-89714.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub16_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -138938,7 +141236,7 @@ module \dec31_dec_sub16 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub16_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -138946,15 +141244,15 @@ module \dec31_dec_sub16 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub16_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub16_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -138986,7 +141284,7 @@ module \dec31_dec_sub16 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -139001,7 +141299,7 @@ module \dec31_dec_sub16 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub16_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -139009,7 +141307,7 @@ module \dec31_dec_sub16 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub16_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -139026,13 +141324,13 @@ module \dec31_dec_sub16 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub16_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub16_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -139108,13 +141406,13 @@ module \dec31_dec_sub16 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub16_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -139122,64 +141420,64 @@ module \dec31_dec_sub16 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub16_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub16_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub16_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "libresoc.v:88551.7-88551.15" + attribute \src "libresoc.v:89428.7-89428.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:88551.7-88551.20" - process $proc$libresoc.v:88551$3805 + attribute \src "libresoc.v:89428.7-89428.20" + process $proc$libresoc.v:89428$3886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:88808.3-88817.6" - process $proc$libresoc.v:88808$3781 + attribute \src "libresoc.v:89685.3-89694.6" + process $proc$libresoc.v:89685$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:88809.5-88809.29" + attribute \src "libresoc.v:89686.5-89686.29" switch \initial - attribute \src "libresoc.v:88809.9-88809.17" + attribute \src "libresoc.v:89686.9-89686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139191,18 +141489,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] end - attribute \src "libresoc.v:88818.3-88827.6" - process $proc$libresoc.v:88818$3782 + attribute \src "libresoc.v:89695.3-89704.6" + process $proc$libresoc.v:89695$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:88819.5-88819.29" + attribute \src "libresoc.v:89696.5-89696.29" switch \initial - attribute \src "libresoc.v:88819.9-88819.17" + attribute \src "libresoc.v:89696.9-89696.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139214,18 +141512,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:88828.3-88837.6" - process $proc$libresoc.v:88828$3783 + attribute \src "libresoc.v:89705.3-89714.6" + process $proc$libresoc.v:89705$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:88829.5-88829.29" + attribute \src "libresoc.v:89706.5-89706.29" switch \initial - attribute \src "libresoc.v:88829.9-88829.17" + attribute \src "libresoc.v:89706.9-89706.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139237,18 +141535,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:88838.3-88847.6" - process $proc$libresoc.v:88838$3784 + attribute \src "libresoc.v:89715.3-89724.6" + process $proc$libresoc.v:89715$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:88839.5-88839.29" + attribute \src "libresoc.v:89716.5-89716.29" switch \initial - attribute \src "libresoc.v:88839.9-88839.17" + attribute \src "libresoc.v:89716.9-89716.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139260,18 +141558,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:88848.3-88857.6" - process $proc$libresoc.v:88848$3785 + attribute \src "libresoc.v:89725.3-89734.6" + process $proc$libresoc.v:89725$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:88849.5-88849.29" + attribute \src "libresoc.v:89726.5-89726.29" switch \initial - attribute \src "libresoc.v:88849.9-88849.17" + attribute \src "libresoc.v:89726.9-89726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139283,18 +141581,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:88858.3-88867.6" - process $proc$libresoc.v:88858$3786 + attribute \src "libresoc.v:89735.3-89744.6" + process $proc$libresoc.v:89735$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:88859.5-88859.29" + attribute \src "libresoc.v:89736.5-89736.29" switch \initial - attribute \src "libresoc.v:88859.9-88859.17" + attribute \src "libresoc.v:89736.9-89736.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139306,18 +141604,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:88868.3-88877.6" - process $proc$libresoc.v:88868$3787 + attribute \src "libresoc.v:89745.3-89754.6" + process $proc$libresoc.v:89745$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:88869.5-88869.29" + attribute \src "libresoc.v:89746.5-89746.29" switch \initial - attribute \src "libresoc.v:88869.9-88869.17" + attribute \src "libresoc.v:89746.9-89746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139329,18 +141627,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:88878.3-88887.6" - process $proc$libresoc.v:88878$3788 + attribute \src "libresoc.v:89755.3-89764.6" + process $proc$libresoc.v:89755$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:88879.5-88879.29" + attribute \src "libresoc.v:89756.5-89756.29" switch \initial - attribute \src "libresoc.v:88879.9-88879.17" + attribute \src "libresoc.v:89756.9-89756.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139352,18 +141650,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:88888.3-88897.6" - process $proc$libresoc.v:88888$3789 + attribute \src "libresoc.v:89765.3-89774.6" + process $proc$libresoc.v:89765$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:88889.5-88889.29" + attribute \src "libresoc.v:89766.5-89766.29" switch \initial - attribute \src "libresoc.v:88889.9-88889.17" + attribute \src "libresoc.v:89766.9-89766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139375,18 +141673,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:88898.3-88907.6" - process $proc$libresoc.v:88898$3790 + attribute \src "libresoc.v:89775.3-89784.6" + process $proc$libresoc.v:89775$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:88899.5-88899.29" + attribute \src "libresoc.v:89776.5-89776.29" switch \initial - attribute \src "libresoc.v:88899.9-88899.17" + attribute \src "libresoc.v:89776.9-89776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139398,18 +141696,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:88908.3-88917.6" - process $proc$libresoc.v:88908$3791 + attribute \src "libresoc.v:89785.3-89794.6" + process $proc$libresoc.v:89785$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:88909.5-88909.29" + attribute \src "libresoc.v:89786.5-89786.29" switch \initial - attribute \src "libresoc.v:88909.9-88909.17" + attribute \src "libresoc.v:89786.9-89786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139421,18 +141719,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:88918.3-88927.6" - process $proc$libresoc.v:88918$3792 + attribute \src "libresoc.v:89795.3-89804.6" + process $proc$libresoc.v:89795$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:88919.5-88919.29" + attribute \src "libresoc.v:89796.5-89796.29" switch \initial - attribute \src "libresoc.v:88919.9-88919.17" + attribute \src "libresoc.v:89796.9-89796.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139444,18 +141742,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:88928.3-88937.6" - process $proc$libresoc.v:88928$3793 + attribute \src "libresoc.v:89805.3-89814.6" + process $proc$libresoc.v:89805$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:88929.5-88929.29" + attribute \src "libresoc.v:89806.5-89806.29" switch \initial - attribute \src "libresoc.v:88929.9-88929.17" + attribute \src "libresoc.v:89806.9-89806.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139467,18 +141765,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:88938.3-88947.6" - process $proc$libresoc.v:88938$3794 + attribute \src "libresoc.v:89815.3-89824.6" + process $proc$libresoc.v:89815$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:88939.5-88939.29" + attribute \src "libresoc.v:89816.5-89816.29" switch \initial - attribute \src "libresoc.v:88939.9-88939.17" + attribute \src "libresoc.v:89816.9-89816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139490,18 +141788,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:88948.3-88957.6" - process $proc$libresoc.v:88948$3795 + attribute \src "libresoc.v:89825.3-89834.6" + process $proc$libresoc.v:89825$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:88949.5-88949.29" + attribute \src "libresoc.v:89826.5-89826.29" switch \initial - attribute \src "libresoc.v:88949.9-88949.17" + attribute \src "libresoc.v:89826.9-89826.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139513,18 +141811,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:88958.3-88967.6" - process $proc$libresoc.v:88958$3796 + attribute \src "libresoc.v:89835.3-89844.6" + process $proc$libresoc.v:89835$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:88959.5-88959.29" + attribute \src "libresoc.v:89836.5-89836.29" switch \initial - attribute \src "libresoc.v:88959.9-88959.17" + attribute \src "libresoc.v:89836.9-89836.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139536,18 +141834,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:88968.3-88977.6" - process $proc$libresoc.v:88968$3797 + attribute \src "libresoc.v:89845.3-89854.6" + process $proc$libresoc.v:89845$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:88969.5-88969.29" + attribute \src "libresoc.v:89846.5-89846.29" switch \initial - attribute \src "libresoc.v:88969.9-88969.17" + attribute \src "libresoc.v:89846.9-89846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139559,18 +141857,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:88978.3-88987.6" - process $proc$libresoc.v:88978$3798 + attribute \src "libresoc.v:89855.3-89864.6" + process $proc$libresoc.v:89855$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:88979.5-88979.29" + attribute \src "libresoc.v:89856.5-89856.29" switch \initial - attribute \src "libresoc.v:88979.9-88979.17" + attribute \src "libresoc.v:89856.9-89856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139582,18 +141880,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:88988.3-88997.6" - process $proc$libresoc.v:88988$3799 + attribute \src "libresoc.v:89865.3-89874.6" + process $proc$libresoc.v:89865$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:88989.5-88989.29" + attribute \src "libresoc.v:89866.5-89866.29" switch \initial - attribute \src "libresoc.v:88989.9-88989.17" + attribute \src "libresoc.v:89866.9-89866.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139605,18 +141903,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:88998.3-89007.6" - process $proc$libresoc.v:88998$3800 + attribute \src "libresoc.v:89875.3-89884.6" + process $proc$libresoc.v:89875$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:88999.5-88999.29" + attribute \src "libresoc.v:89876.5-89876.29" switch \initial - attribute \src "libresoc.v:88999.9-88999.17" + attribute \src "libresoc.v:89876.9-89876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139628,18 +141926,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:89008.3-89017.6" - process $proc$libresoc.v:89008$3801 + attribute \src "libresoc.v:89885.3-89894.6" + process $proc$libresoc.v:89885$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89009.5-89009.29" + attribute \src "libresoc.v:89886.5-89886.29" switch \initial - attribute \src "libresoc.v:89009.9-89009.17" + attribute \src "libresoc.v:89886.9-89886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139651,18 +141949,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:89018.3-89027.6" - process $proc$libresoc.v:89018$3802 + attribute \src "libresoc.v:89895.3-89904.6" + process $proc$libresoc.v:89895$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89019.5-89019.29" + attribute \src "libresoc.v:89896.5-89896.29" switch \initial - attribute \src "libresoc.v:89019.9-89019.17" + attribute \src "libresoc.v:89896.9-89896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139674,18 +141972,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] end - attribute \src "libresoc.v:89028.3-89037.6" - process $proc$libresoc.v:89028$3803 + attribute \src "libresoc.v:89905.3-89914.6" + process $proc$libresoc.v:89905$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89029.5-89029.29" + attribute \src "libresoc.v:89906.5-89906.29" switch \initial - attribute \src "libresoc.v:89029.9-89029.17" + attribute \src "libresoc.v:89906.9-89906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139697,18 +141995,18 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:89038.3-89047.6" - process $proc$libresoc.v:89038$3804 + attribute \src "libresoc.v:89915.3-89924.6" + process $proc$libresoc.v:89915$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89039.5-89039.29" + attribute \src "libresoc.v:89916.5-89916.29" switch \initial - attribute \src "libresoc.v:89039.9-89039.17" + attribute \src "libresoc.v:89916.9-89916.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00100 @@ -139722,112 +142020,112 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:89053.1-89840.10" +attribute \src "libresoc.v:89930.1-90717.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:89421.3-89442.6" + attribute \src "libresoc.v:90298.3-90319.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:89509.3-89530.6" + attribute \src "libresoc.v:90386.3-90407.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:89795.3-89816.6" + attribute \src "libresoc.v:90672.3-90693.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:89817.3-89838.6" + attribute \src "libresoc.v:90694.3-90715.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:89399.3-89420.6" + attribute \src "libresoc.v:90276.3-90297.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:89487.3-89508.6" + attribute \src "libresoc.v:90364.3-90385.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:89685.3-89706.6" + attribute \src "libresoc.v:90562.3-90583.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:89311.3-89332.6" + attribute \src "libresoc.v:90188.3-90209.6" wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:89707.3-89728.6" + attribute \src "libresoc.v:90584.3-90605.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:89729.3-89750.6" + attribute \src "libresoc.v:90606.3-90627.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:89751.3-89772.6" + attribute \src "libresoc.v:90628.3-90649.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:89553.3-89574.6" + attribute \src "libresoc.v:90430.3-90451.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:89443.3-89464.6" + attribute \src "libresoc.v:90320.3-90341.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:89465.3-89486.6" + attribute \src "libresoc.v:90342.3-90363.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:89597.3-89618.6" + attribute \src "libresoc.v:90474.3-90495.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:89333.3-89354.6" + attribute \src "libresoc.v:90210.3-90231.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:89641.3-89662.6" + attribute \src "libresoc.v:90518.3-90539.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:89773.3-89794.6" + attribute \src "libresoc.v:90650.3-90671.6" wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:89377.3-89398.6" + attribute \src "libresoc.v:90254.3-90275.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:89575.3-89596.6" + attribute \src "libresoc.v:90452.3-90473.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:89663.3-89684.6" + attribute \src "libresoc.v:90540.3-90561.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:89619.3-89640.6" + attribute \src "libresoc.v:90496.3-90517.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:89531.3-89552.6" + attribute \src "libresoc.v:90408.3-90429.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:89355.3-89376.6" + attribute \src "libresoc.v:90232.3-90253.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:89054.7-89054.20" + attribute \src "libresoc.v:89931.7-89931.20" wire $0\initial[0:0] - attribute \src "libresoc.v:89421.3-89442.6" + attribute \src "libresoc.v:90298.3-90319.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:89509.3-89530.6" + attribute \src "libresoc.v:90386.3-90407.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:89795.3-89816.6" + attribute \src "libresoc.v:90672.3-90693.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:89817.3-89838.6" + attribute \src "libresoc.v:90694.3-90715.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:89399.3-89420.6" + attribute \src "libresoc.v:90276.3-90297.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:89487.3-89508.6" + attribute \src "libresoc.v:90364.3-90385.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:89685.3-89706.6" + attribute \src "libresoc.v:90562.3-90583.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:89311.3-89332.6" + attribute \src "libresoc.v:90188.3-90209.6" wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:89707.3-89728.6" + attribute \src "libresoc.v:90584.3-90605.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:89729.3-89750.6" + attribute \src "libresoc.v:90606.3-90627.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:89751.3-89772.6" + attribute \src "libresoc.v:90628.3-90649.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:89553.3-89574.6" + attribute \src "libresoc.v:90430.3-90451.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:89443.3-89464.6" + attribute \src "libresoc.v:90320.3-90341.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:89465.3-89486.6" + attribute \src "libresoc.v:90342.3-90363.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:89597.3-89618.6" + attribute \src "libresoc.v:90474.3-90495.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:89333.3-89354.6" + attribute \src "libresoc.v:90210.3-90231.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:89641.3-89662.6" + attribute \src "libresoc.v:90518.3-90539.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:89773.3-89794.6" + attribute \src "libresoc.v:90650.3-90671.6" wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:89377.3-89398.6" + attribute \src "libresoc.v:90254.3-90275.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:89575.3-89596.6" + attribute \src "libresoc.v:90452.3-90473.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:89663.3-89684.6" + attribute \src "libresoc.v:90540.3-90561.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:89619.3-89640.6" + attribute \src "libresoc.v:90496.3-90517.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:89531.3-89552.6" + attribute \src "libresoc.v:90408.3-90429.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:89355.3-89376.6" + attribute \src "libresoc.v:90232.3-90253.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub18_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -139837,7 +142135,7 @@ module \dec31_dec_sub18 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub18_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -139845,15 +142143,15 @@ module \dec31_dec_sub18 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub18_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub18_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -139885,7 +142183,7 @@ module \dec31_dec_sub18 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -139900,7 +142198,7 @@ module \dec31_dec_sub18 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub18_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -139908,7 +142206,7 @@ module \dec31_dec_sub18 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub18_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -139925,13 +142223,13 @@ module \dec31_dec_sub18 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub18_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub18_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -140007,13 +142305,13 @@ module \dec31_dec_sub18 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub18_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -140021,64 +142319,64 @@ module \dec31_dec_sub18 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub18_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub18_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub18_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "libresoc.v:89054.7-89054.15" + attribute \src "libresoc.v:89931.7-89931.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:89054.7-89054.20" - process $proc$libresoc.v:89054$3830 + attribute \src "libresoc.v:89931.7-89931.20" + process $proc$libresoc.v:89931$3911 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:89311.3-89332.6" - process $proc$libresoc.v:89311$3806 + attribute \src "libresoc.v:90188.3-90209.6" + process $proc$libresoc.v:90188$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:89312.5-89312.29" + attribute \src "libresoc.v:90189.5-90189.29" switch \initial - attribute \src "libresoc.v:89312.9-89312.17" + attribute \src "libresoc.v:90189.9-90189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140106,18 +142404,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] end - attribute \src "libresoc.v:89333.3-89354.6" - process $proc$libresoc.v:89333$3807 + attribute \src "libresoc.v:90210.3-90231.6" + process $proc$libresoc.v:90210$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:89334.5-89334.29" + attribute \src "libresoc.v:90211.5-90211.29" switch \initial - attribute \src "libresoc.v:89334.9-89334.17" + attribute \src "libresoc.v:90211.9-90211.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140145,18 +142443,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:89355.3-89376.6" - process $proc$libresoc.v:89355$3808 + attribute \src "libresoc.v:90232.3-90253.6" + process $proc$libresoc.v:90232$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:89356.5-89356.29" + attribute \src "libresoc.v:90233.5-90233.29" switch \initial - attribute \src "libresoc.v:89356.9-89356.17" + attribute \src "libresoc.v:90233.9-90233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140184,18 +142482,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:89377.3-89398.6" - process $proc$libresoc.v:89377$3809 + attribute \src "libresoc.v:90254.3-90275.6" + process $proc$libresoc.v:90254$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:89378.5-89378.29" + attribute \src "libresoc.v:90255.5-90255.29" switch \initial - attribute \src "libresoc.v:89378.9-89378.17" + attribute \src "libresoc.v:90255.9-90255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140223,18 +142521,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:89399.3-89420.6" - process $proc$libresoc.v:89399$3810 + attribute \src "libresoc.v:90276.3-90297.6" + process $proc$libresoc.v:90276$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:89400.5-89400.29" + attribute \src "libresoc.v:90277.5-90277.29" switch \initial - attribute \src "libresoc.v:89400.9-89400.17" + attribute \src "libresoc.v:90277.9-90277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140262,18 +142560,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:89421.3-89442.6" - process $proc$libresoc.v:89421$3811 + attribute \src "libresoc.v:90298.3-90319.6" + process $proc$libresoc.v:90298$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:89422.5-89422.29" + attribute \src "libresoc.v:90299.5-90299.29" switch \initial - attribute \src "libresoc.v:89422.9-89422.17" + attribute \src "libresoc.v:90299.9-90299.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140301,18 +142599,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:89443.3-89464.6" - process $proc$libresoc.v:89443$3812 + attribute \src "libresoc.v:90320.3-90341.6" + process $proc$libresoc.v:90320$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:89444.5-89444.29" + attribute \src "libresoc.v:90321.5-90321.29" switch \initial - attribute \src "libresoc.v:89444.9-89444.17" + attribute \src "libresoc.v:90321.9-90321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140340,18 +142638,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:89465.3-89486.6" - process $proc$libresoc.v:89465$3813 + attribute \src "libresoc.v:90342.3-90363.6" + process $proc$libresoc.v:90342$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:89466.5-89466.29" + attribute \src "libresoc.v:90343.5-90343.29" switch \initial - attribute \src "libresoc.v:89466.9-89466.17" + attribute \src "libresoc.v:90343.9-90343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140379,18 +142677,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:89487.3-89508.6" - process $proc$libresoc.v:89487$3814 + attribute \src "libresoc.v:90364.3-90385.6" + process $proc$libresoc.v:90364$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:89488.5-89488.29" + attribute \src "libresoc.v:90365.5-90365.29" switch \initial - attribute \src "libresoc.v:89488.9-89488.17" + attribute \src "libresoc.v:90365.9-90365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140418,18 +142716,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:89509.3-89530.6" - process $proc$libresoc.v:89509$3815 + attribute \src "libresoc.v:90386.3-90407.6" + process $proc$libresoc.v:90386$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:89510.5-89510.29" + attribute \src "libresoc.v:90387.5-90387.29" switch \initial - attribute \src "libresoc.v:89510.9-89510.17" + attribute \src "libresoc.v:90387.9-90387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140457,18 +142755,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:89531.3-89552.6" - process $proc$libresoc.v:89531$3816 + attribute \src "libresoc.v:90408.3-90429.6" + process $proc$libresoc.v:90408$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:89532.5-89532.29" + attribute \src "libresoc.v:90409.5-90409.29" switch \initial - attribute \src "libresoc.v:89532.9-89532.17" + attribute \src "libresoc.v:90409.9-90409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140496,18 +142794,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:89553.3-89574.6" - process $proc$libresoc.v:89553$3817 + attribute \src "libresoc.v:90430.3-90451.6" + process $proc$libresoc.v:90430$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:89554.5-89554.29" + attribute \src "libresoc.v:90431.5-90431.29" switch \initial - attribute \src "libresoc.v:89554.9-89554.17" + attribute \src "libresoc.v:90431.9-90431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140535,18 +142833,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:89575.3-89596.6" - process $proc$libresoc.v:89575$3818 + attribute \src "libresoc.v:90452.3-90473.6" + process $proc$libresoc.v:90452$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:89576.5-89576.29" + attribute \src "libresoc.v:90453.5-90453.29" switch \initial - attribute \src "libresoc.v:89576.9-89576.17" + attribute \src "libresoc.v:90453.9-90453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140574,18 +142872,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:89597.3-89618.6" - process $proc$libresoc.v:89597$3819 + attribute \src "libresoc.v:90474.3-90495.6" + process $proc$libresoc.v:90474$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:89598.5-89598.29" + attribute \src "libresoc.v:90475.5-90475.29" switch \initial - attribute \src "libresoc.v:89598.9-89598.17" + attribute \src "libresoc.v:90475.9-90475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140613,18 +142911,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:89619.3-89640.6" - process $proc$libresoc.v:89619$3820 + attribute \src "libresoc.v:90496.3-90517.6" + process $proc$libresoc.v:90496$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:89620.5-89620.29" + attribute \src "libresoc.v:90497.5-90497.29" switch \initial - attribute \src "libresoc.v:89620.9-89620.17" + attribute \src "libresoc.v:90497.9-90497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140652,18 +142950,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:89641.3-89662.6" - process $proc$libresoc.v:89641$3821 + attribute \src "libresoc.v:90518.3-90539.6" + process $proc$libresoc.v:90518$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:89642.5-89642.29" + attribute \src "libresoc.v:90519.5-90519.29" switch \initial - attribute \src "libresoc.v:89642.9-89642.17" + attribute \src "libresoc.v:90519.9-90519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140691,18 +142989,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:89663.3-89684.6" - process $proc$libresoc.v:89663$3822 + attribute \src "libresoc.v:90540.3-90561.6" + process $proc$libresoc.v:90540$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:89664.5-89664.29" + attribute \src "libresoc.v:90541.5-90541.29" switch \initial - attribute \src "libresoc.v:89664.9-89664.17" + attribute \src "libresoc.v:90541.9-90541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140730,18 +143028,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:89685.3-89706.6" - process $proc$libresoc.v:89685$3823 + attribute \src "libresoc.v:90562.3-90583.6" + process $proc$libresoc.v:90562$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:89686.5-89686.29" + attribute \src "libresoc.v:90563.5-90563.29" switch \initial - attribute \src "libresoc.v:89686.9-89686.17" + attribute \src "libresoc.v:90563.9-90563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140769,18 +143067,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:89707.3-89728.6" - process $proc$libresoc.v:89707$3824 + attribute \src "libresoc.v:90584.3-90605.6" + process $proc$libresoc.v:90584$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:89708.5-89708.29" + attribute \src "libresoc.v:90585.5-90585.29" switch \initial - attribute \src "libresoc.v:89708.9-89708.17" + attribute \src "libresoc.v:90585.9-90585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140808,18 +143106,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:89729.3-89750.6" - process $proc$libresoc.v:89729$3825 + attribute \src "libresoc.v:90606.3-90627.6" + process $proc$libresoc.v:90606$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:89730.5-89730.29" + attribute \src "libresoc.v:90607.5-90607.29" switch \initial - attribute \src "libresoc.v:89730.9-89730.17" + attribute \src "libresoc.v:90607.9-90607.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140847,18 +143145,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:89751.3-89772.6" - process $proc$libresoc.v:89751$3826 + attribute \src "libresoc.v:90628.3-90649.6" + process $proc$libresoc.v:90628$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:89752.5-89752.29" + attribute \src "libresoc.v:90629.5-90629.29" switch \initial - attribute \src "libresoc.v:89752.9-89752.17" + attribute \src "libresoc.v:90629.9-90629.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140886,18 +143184,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:89773.3-89794.6" - process $proc$libresoc.v:89773$3827 + attribute \src "libresoc.v:90650.3-90671.6" + process $proc$libresoc.v:90650$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:89774.5-89774.29" + attribute \src "libresoc.v:90651.5-90651.29" switch \initial - attribute \src "libresoc.v:89774.9-89774.17" + attribute \src "libresoc.v:90651.9-90651.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140925,18 +143223,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] end - attribute \src "libresoc.v:89795.3-89816.6" - process $proc$libresoc.v:89795$3828 + attribute \src "libresoc.v:90672.3-90693.6" + process $proc$libresoc.v:90672$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:89796.5-89796.29" + attribute \src "libresoc.v:90673.5-90673.29" switch \initial - attribute \src "libresoc.v:89796.9-89796.17" + attribute \src "libresoc.v:90673.9-90673.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -140964,18 +143262,18 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:89817.3-89838.6" - process $proc$libresoc.v:89817$3829 + attribute \src "libresoc.v:90694.3-90715.6" + process $proc$libresoc.v:90694$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:89818.5-89818.29" + attribute \src "libresoc.v:90695.5-90695.29" switch \initial - attribute \src "libresoc.v:89818.9-89818.17" + attribute \src "libresoc.v:90695.9-90695.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00101 @@ -141005,112 +143303,112 @@ module \dec31_dec_sub18 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:89844.1-90559.10" +attribute \src "libresoc.v:90721.1-91436.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:91074.3-91092.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:91150.3-91168.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91397.3-91415.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91416.3-91434.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:91055.3-91073.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:91131.3-91149.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91302.3-91320.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90102.3-90120.6" + attribute \src "libresoc.v:90979.3-90997.6" wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91321.3-91339.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91340.3-91358.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91359.3-91377.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91188.3-91206.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:91093.3-91111.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:91112.3-91130.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91226.3-91244.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90998.3-91016.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91264.3-91282.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91378.3-91396.6" wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:91036.3-91054.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91207.3-91225.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91283.3-91301.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91245.3-91263.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91169.3-91187.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:91017.3-91035.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:89845.7-89845.20" + attribute \src "libresoc.v:90722.7-90722.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90197.3-90215.6" + attribute \src "libresoc.v:91074.3-91092.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90273.3-90291.6" + attribute \src "libresoc.v:91150.3-91168.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:90520.3-90538.6" + attribute \src "libresoc.v:91397.3-91415.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:90539.3-90557.6" + attribute \src "libresoc.v:91416.3-91434.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:90178.3-90196.6" + attribute \src "libresoc.v:91055.3-91073.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90254.3-90272.6" + attribute \src "libresoc.v:91131.3-91149.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:90425.3-90443.6" + attribute \src "libresoc.v:91302.3-91320.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90102.3-90120.6" + attribute \src "libresoc.v:90979.3-90997.6" wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:90444.3-90462.6" + attribute \src "libresoc.v:91321.3-91339.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:90463.3-90481.6" + attribute \src "libresoc.v:91340.3-91358.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:90482.3-90500.6" + attribute \src "libresoc.v:91359.3-91377.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:90311.3-90329.6" + attribute \src "libresoc.v:91188.3-91206.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:90216.3-90234.6" + attribute \src "libresoc.v:91093.3-91111.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90235.3-90253.6" + attribute \src "libresoc.v:91112.3-91130.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:90349.3-90367.6" + attribute \src "libresoc.v:91226.3-91244.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90121.3-90139.6" + attribute \src "libresoc.v:90998.3-91016.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:90387.3-90405.6" + attribute \src "libresoc.v:91264.3-91282.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:90501.3-90519.6" + attribute \src "libresoc.v:91378.3-91396.6" wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:90159.3-90177.6" + attribute \src "libresoc.v:91036.3-91054.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:90330.3-90348.6" + attribute \src "libresoc.v:91207.3-91225.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:90406.3-90424.6" + attribute \src "libresoc.v:91283.3-91301.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:90368.3-90386.6" + attribute \src "libresoc.v:91245.3-91263.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:90292.3-90310.6" + attribute \src "libresoc.v:91169.3-91187.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90140.3-90158.6" + attribute \src "libresoc.v:91017.3-91035.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub19_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -141120,7 +143418,7 @@ module \dec31_dec_sub19 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub19_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -141128,15 +143426,15 @@ module \dec31_dec_sub19 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub19_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub19_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -141168,7 +143466,7 @@ module \dec31_dec_sub19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -141183,7 +143481,7 @@ module \dec31_dec_sub19 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub19_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -141191,7 +143489,7 @@ module \dec31_dec_sub19 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub19_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -141208,13 +143506,13 @@ module \dec31_dec_sub19 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub19_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -141290,13 +143588,13 @@ module \dec31_dec_sub19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub19_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -141304,64 +143602,64 @@ module \dec31_dec_sub19 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub19_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub19_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub19_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "libresoc.v:89845.7-89845.15" + attribute \src "libresoc.v:90722.7-90722.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:89845.7-89845.20" - process $proc$libresoc.v:89845$3855 + attribute \src "libresoc.v:90722.7-90722.20" + process $proc$libresoc.v:90722$3936 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90102.3-90120.6" - process $proc$libresoc.v:90102$3831 + attribute \src "libresoc.v:90979.3-90997.6" + process $proc$libresoc.v:90979$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:90103.5-90103.29" + attribute \src "libresoc.v:90980.5-90980.29" switch \initial - attribute \src "libresoc.v:90103.9-90103.17" + attribute \src "libresoc.v:90980.9-90980.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141385,18 +143683,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] end - attribute \src "libresoc.v:90121.3-90139.6" - process $proc$libresoc.v:90121$3832 + attribute \src "libresoc.v:90998.3-91016.6" + process $proc$libresoc.v:90998$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:90122.5-90122.29" + attribute \src "libresoc.v:90999.5-90999.29" switch \initial - attribute \src "libresoc.v:90122.9-90122.17" + attribute \src "libresoc.v:90999.9-90999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141420,18 +143718,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:90140.3-90158.6" - process $proc$libresoc.v:90140$3833 + attribute \src "libresoc.v:91017.3-91035.6" + process $proc$libresoc.v:91017$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:90141.5-90141.29" + attribute \src "libresoc.v:91018.5-91018.29" switch \initial - attribute \src "libresoc.v:90141.9-90141.17" + attribute \src "libresoc.v:91018.9-91018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141455,18 +143753,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:90159.3-90177.6" - process $proc$libresoc.v:90159$3834 + attribute \src "libresoc.v:91036.3-91054.6" + process $proc$libresoc.v:91036$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:90160.5-90160.29" + attribute \src "libresoc.v:91037.5-91037.29" switch \initial - attribute \src "libresoc.v:90160.9-90160.17" + attribute \src "libresoc.v:91037.9-91037.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141490,18 +143788,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:90178.3-90196.6" - process $proc$libresoc.v:90178$3835 + attribute \src "libresoc.v:91055.3-91073.6" + process $proc$libresoc.v:91055$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:90179.5-90179.29" + attribute \src "libresoc.v:91056.5-91056.29" switch \initial - attribute \src "libresoc.v:90179.9-90179.17" + attribute \src "libresoc.v:91056.9-91056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141525,18 +143823,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:90197.3-90215.6" - process $proc$libresoc.v:90197$3836 + attribute \src "libresoc.v:91074.3-91092.6" + process $proc$libresoc.v:91074$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:90198.5-90198.29" + attribute \src "libresoc.v:91075.5-91075.29" switch \initial - attribute \src "libresoc.v:90198.9-90198.17" + attribute \src "libresoc.v:91075.9-91075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141560,18 +143858,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:90216.3-90234.6" - process $proc$libresoc.v:90216$3837 + attribute \src "libresoc.v:91093.3-91111.6" + process $proc$libresoc.v:91093$3918 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:90217.5-90217.29" + attribute \src "libresoc.v:91094.5-91094.29" switch \initial - attribute \src "libresoc.v:90217.9-90217.17" + attribute \src "libresoc.v:91094.9-91094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141595,18 +143893,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:90235.3-90253.6" - process $proc$libresoc.v:90235$3838 + attribute \src "libresoc.v:91112.3-91130.6" + process $proc$libresoc.v:91112$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:90236.5-90236.29" + attribute \src "libresoc.v:91113.5-91113.29" switch \initial - attribute \src "libresoc.v:90236.9-90236.17" + attribute \src "libresoc.v:91113.9-91113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141630,18 +143928,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:90254.3-90272.6" - process $proc$libresoc.v:90254$3839 + attribute \src "libresoc.v:91131.3-91149.6" + process $proc$libresoc.v:91131$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:90255.5-90255.29" + attribute \src "libresoc.v:91132.5-91132.29" switch \initial - attribute \src "libresoc.v:90255.9-90255.17" + attribute \src "libresoc.v:91132.9-91132.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141665,18 +143963,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:90273.3-90291.6" - process $proc$libresoc.v:90273$3840 + attribute \src "libresoc.v:91150.3-91168.6" + process $proc$libresoc.v:91150$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:90274.5-90274.29" + attribute \src "libresoc.v:91151.5-91151.29" switch \initial - attribute \src "libresoc.v:90274.9-90274.17" + attribute \src "libresoc.v:91151.9-91151.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141700,18 +143998,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:90292.3-90310.6" - process $proc$libresoc.v:90292$3841 + attribute \src "libresoc.v:91169.3-91187.6" + process $proc$libresoc.v:91169$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:90293.5-90293.29" + attribute \src "libresoc.v:91170.5-91170.29" switch \initial - attribute \src "libresoc.v:90293.9-90293.17" + attribute \src "libresoc.v:91170.9-91170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141735,18 +144033,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:90311.3-90329.6" - process $proc$libresoc.v:90311$3842 + attribute \src "libresoc.v:91188.3-91206.6" + process $proc$libresoc.v:91188$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:90312.5-90312.29" + attribute \src "libresoc.v:91189.5-91189.29" switch \initial - attribute \src "libresoc.v:90312.9-90312.17" + attribute \src "libresoc.v:91189.9-91189.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141770,18 +144068,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:90330.3-90348.6" - process $proc$libresoc.v:90330$3843 + attribute \src "libresoc.v:91207.3-91225.6" + process $proc$libresoc.v:91207$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:90331.5-90331.29" + attribute \src "libresoc.v:91208.5-91208.29" switch \initial - attribute \src "libresoc.v:90331.9-90331.17" + attribute \src "libresoc.v:91208.9-91208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141805,18 +144103,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:90349.3-90367.6" - process $proc$libresoc.v:90349$3844 + attribute \src "libresoc.v:91226.3-91244.6" + process $proc$libresoc.v:91226$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90350.5-90350.29" + attribute \src "libresoc.v:91227.5-91227.29" switch \initial - attribute \src "libresoc.v:90350.9-90350.17" + attribute \src "libresoc.v:91227.9-91227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141840,18 +144138,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:90368.3-90386.6" - process $proc$libresoc.v:90368$3845 + attribute \src "libresoc.v:91245.3-91263.6" + process $proc$libresoc.v:91245$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:90369.5-90369.29" + attribute \src "libresoc.v:91246.5-91246.29" switch \initial - attribute \src "libresoc.v:90369.9-90369.17" + attribute \src "libresoc.v:91246.9-91246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141875,18 +144173,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:90387.3-90405.6" - process $proc$libresoc.v:90387$3846 + attribute \src "libresoc.v:91264.3-91282.6" + process $proc$libresoc.v:91264$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:90388.5-90388.29" + attribute \src "libresoc.v:91265.5-91265.29" switch \initial - attribute \src "libresoc.v:90388.9-90388.17" + attribute \src "libresoc.v:91265.9-91265.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141910,18 +144208,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:90406.3-90424.6" - process $proc$libresoc.v:90406$3847 + attribute \src "libresoc.v:91283.3-91301.6" + process $proc$libresoc.v:91283$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:90407.5-90407.29" + attribute \src "libresoc.v:91284.5-91284.29" switch \initial - attribute \src "libresoc.v:90407.9-90407.17" + attribute \src "libresoc.v:91284.9-91284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141945,18 +144243,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:90425.3-90443.6" - process $proc$libresoc.v:90425$3848 + attribute \src "libresoc.v:91302.3-91320.6" + process $proc$libresoc.v:91302$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90426.5-90426.29" + attribute \src "libresoc.v:91303.5-91303.29" switch \initial - attribute \src "libresoc.v:90426.9-90426.17" + attribute \src "libresoc.v:91303.9-91303.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -141980,18 +144278,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:90444.3-90462.6" - process $proc$libresoc.v:90444$3849 + attribute \src "libresoc.v:91321.3-91339.6" + process $proc$libresoc.v:91321$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:90445.5-90445.29" + attribute \src "libresoc.v:91322.5-91322.29" switch \initial - attribute \src "libresoc.v:90445.9-90445.17" + attribute \src "libresoc.v:91322.9-91322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142015,18 +144313,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:90463.3-90481.6" - process $proc$libresoc.v:90463$3850 + attribute \src "libresoc.v:91340.3-91358.6" + process $proc$libresoc.v:91340$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:90464.5-90464.29" + attribute \src "libresoc.v:91341.5-91341.29" switch \initial - attribute \src "libresoc.v:90464.9-90464.17" + attribute \src "libresoc.v:91341.9-91341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142050,18 +144348,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:90482.3-90500.6" - process $proc$libresoc.v:90482$3851 + attribute \src "libresoc.v:91359.3-91377.6" + process $proc$libresoc.v:91359$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:90483.5-90483.29" + attribute \src "libresoc.v:91360.5-91360.29" switch \initial - attribute \src "libresoc.v:90483.9-90483.17" + attribute \src "libresoc.v:91360.9-91360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142085,18 +144383,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:90501.3-90519.6" - process $proc$libresoc.v:90501$3852 + attribute \src "libresoc.v:91378.3-91396.6" + process $proc$libresoc.v:91378$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:90502.5-90502.29" + attribute \src "libresoc.v:91379.5-91379.29" switch \initial - attribute \src "libresoc.v:90502.9-90502.17" + attribute \src "libresoc.v:91379.9-91379.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142120,18 +144418,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] end - attribute \src "libresoc.v:90520.3-90538.6" - process $proc$libresoc.v:90520$3853 + attribute \src "libresoc.v:91397.3-91415.6" + process $proc$libresoc.v:91397$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:90521.5-90521.29" + attribute \src "libresoc.v:91398.5-91398.29" switch \initial - attribute \src "libresoc.v:90521.9-90521.17" + attribute \src "libresoc.v:91398.9-91398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142155,18 +144453,18 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:90539.3-90557.6" - process $proc$libresoc.v:90539$3854 + attribute \src "libresoc.v:91416.3-91434.6" + process $proc$libresoc.v:91416$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:90540.5-90540.29" + attribute \src "libresoc.v:91417.5-91417.29" switch \initial - attribute \src "libresoc.v:90540.9-90540.17" + attribute \src "libresoc.v:91417.9-91417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -142192,112 +144490,112 @@ module \dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90563.1-91422.10" +attribute \src "libresoc.v:91440.1-92299.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:90946.3-90970.6" + attribute \src "libresoc.v:91823.3-91847.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91046.3-91070.6" + attribute \src "libresoc.v:91923.3-91947.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:91371.3-91395.6" + attribute \src "libresoc.v:92248.3-92272.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:91396.3-91420.6" + attribute \src "libresoc.v:92273.3-92297.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:90921.3-90945.6" + attribute \src "libresoc.v:91798.3-91822.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91021.3-91045.6" + attribute \src "libresoc.v:91898.3-91922.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91270.6" + attribute \src "libresoc.v:92123.3-92147.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:90821.3-90845.6" + attribute \src "libresoc.v:91698.3-91722.6" wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91271.3-91295.6" + attribute \src "libresoc.v:92148.3-92172.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91296.3-91320.6" + attribute \src "libresoc.v:92173.3-92197.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:91321.3-91345.6" + attribute \src "libresoc.v:92198.3-92222.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91096.3-91120.6" + attribute \src "libresoc.v:91973.3-91997.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:90971.3-90995.6" + attribute \src "libresoc.v:91848.3-91872.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:90996.3-91020.6" + attribute \src "libresoc.v:91873.3-91897.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91146.3-91170.6" + attribute \src "libresoc.v:92023.3-92047.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:90846.3-90870.6" + attribute \src "libresoc.v:91723.3-91747.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91196.3-91220.6" + attribute \src "libresoc.v:92073.3-92097.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:91346.3-91370.6" + attribute \src "libresoc.v:92223.3-92247.6" wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:90896.3-90920.6" + attribute \src "libresoc.v:91773.3-91797.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91121.3-91145.6" + attribute \src "libresoc.v:91998.3-92022.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91221.3-91245.6" + attribute \src "libresoc.v:92098.3-92122.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91171.3-91195.6" + attribute \src "libresoc.v:92048.3-92072.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91071.3-91095.6" + attribute \src "libresoc.v:91948.3-91972.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:90871.3-90895.6" + attribute \src "libresoc.v:91748.3-91772.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:90564.7-90564.20" + attribute \src "libresoc.v:91441.7-91441.20" wire $0\initial[0:0] - attribute \src "libresoc.v:90946.3-90970.6" + attribute \src "libresoc.v:91823.3-91847.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91046.3-91070.6" + attribute \src "libresoc.v:91923.3-91947.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:91371.3-91395.6" + attribute \src "libresoc.v:92248.3-92272.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:91396.3-91420.6" + attribute \src "libresoc.v:92273.3-92297.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:90921.3-90945.6" + attribute \src "libresoc.v:91798.3-91822.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91021.3-91045.6" + attribute \src "libresoc.v:91898.3-91922.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91270.6" + attribute \src "libresoc.v:92123.3-92147.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:90821.3-90845.6" + attribute \src "libresoc.v:91698.3-91722.6" wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91271.3-91295.6" + attribute \src "libresoc.v:92148.3-92172.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91296.3-91320.6" + attribute \src "libresoc.v:92173.3-92197.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:91321.3-91345.6" + attribute \src "libresoc.v:92198.3-92222.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91096.3-91120.6" + attribute \src "libresoc.v:91973.3-91997.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:90971.3-90995.6" + attribute \src "libresoc.v:91848.3-91872.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:90996.3-91020.6" + attribute \src "libresoc.v:91873.3-91897.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91146.3-91170.6" + attribute \src "libresoc.v:92023.3-92047.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:90846.3-90870.6" + attribute \src "libresoc.v:91723.3-91747.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91196.3-91220.6" + attribute \src "libresoc.v:92073.3-92097.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:91346.3-91370.6" + attribute \src "libresoc.v:92223.3-92247.6" wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:90896.3-90920.6" + attribute \src "libresoc.v:91773.3-91797.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91121.3-91145.6" + attribute \src "libresoc.v:91998.3-92022.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91221.3-91245.6" + attribute \src "libresoc.v:92098.3-92122.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91171.3-91195.6" + attribute \src "libresoc.v:92048.3-92072.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91071.3-91095.6" + attribute \src "libresoc.v:91948.3-91972.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:90871.3-90895.6" + attribute \src "libresoc.v:91748.3-91772.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub20_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -142307,7 +144605,7 @@ module \dec31_dec_sub20 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub20_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -142315,15 +144613,15 @@ module \dec31_dec_sub20 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub20_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub20_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -142355,7 +144653,7 @@ module \dec31_dec_sub20 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -142370,7 +144668,7 @@ module \dec31_dec_sub20 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub20_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -142378,7 +144676,7 @@ module \dec31_dec_sub20 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub20_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -142395,13 +144693,13 @@ module \dec31_dec_sub20 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub20_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub20_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -142477,13 +144775,13 @@ module \dec31_dec_sub20 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub20_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -142491,64 +144789,64 @@ module \dec31_dec_sub20 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub20_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub20_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub20_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "libresoc.v:90564.7-90564.15" + attribute \src "libresoc.v:91441.7-91441.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:90564.7-90564.20" - process $proc$libresoc.v:90564$3880 + attribute \src "libresoc.v:91441.7-91441.20" + process $proc$libresoc.v:91441$3961 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90821.3-90845.6" - process $proc$libresoc.v:90821$3856 + attribute \src "libresoc.v:91698.3-91722.6" + process $proc$libresoc.v:91698$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:90822.5-90822.29" + attribute \src "libresoc.v:91699.5-91699.29" switch \initial - attribute \src "libresoc.v:90822.9-90822.17" + attribute \src "libresoc.v:91699.9-91699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142580,18 +144878,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] end - attribute \src "libresoc.v:90846.3-90870.6" - process $proc$libresoc.v:90846$3857 + attribute \src "libresoc.v:91723.3-91747.6" + process $proc$libresoc.v:91723$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:90847.5-90847.29" + attribute \src "libresoc.v:91724.5-91724.29" switch \initial - attribute \src "libresoc.v:90847.9-90847.17" + attribute \src "libresoc.v:91724.9-91724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142623,18 +144921,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:90871.3-90895.6" - process $proc$libresoc.v:90871$3858 + attribute \src "libresoc.v:91748.3-91772.6" + process $proc$libresoc.v:91748$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:90872.5-90872.29" + attribute \src "libresoc.v:91749.5-91749.29" switch \initial - attribute \src "libresoc.v:90872.9-90872.17" + attribute \src "libresoc.v:91749.9-91749.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142666,18 +144964,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:90896.3-90920.6" - process $proc$libresoc.v:90896$3859 + attribute \src "libresoc.v:91773.3-91797.6" + process $proc$libresoc.v:91773$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:90897.5-90897.29" + attribute \src "libresoc.v:91774.5-91774.29" switch \initial - attribute \src "libresoc.v:90897.9-90897.17" + attribute \src "libresoc.v:91774.9-91774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142709,18 +145007,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:90921.3-90945.6" - process $proc$libresoc.v:90921$3860 + attribute \src "libresoc.v:91798.3-91822.6" + process $proc$libresoc.v:91798$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:90922.5-90922.29" + attribute \src "libresoc.v:91799.5-91799.29" switch \initial - attribute \src "libresoc.v:90922.9-90922.17" + attribute \src "libresoc.v:91799.9-91799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142752,18 +145050,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:90946.3-90970.6" - process $proc$libresoc.v:90946$3861 + attribute \src "libresoc.v:91823.3-91847.6" + process $proc$libresoc.v:91823$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:90947.5-90947.29" + attribute \src "libresoc.v:91824.5-91824.29" switch \initial - attribute \src "libresoc.v:90947.9-90947.17" + attribute \src "libresoc.v:91824.9-91824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142795,18 +145093,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:90971.3-90995.6" - process $proc$libresoc.v:90971$3862 + attribute \src "libresoc.v:91848.3-91872.6" + process $proc$libresoc.v:91848$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:90972.5-90972.29" + attribute \src "libresoc.v:91849.5-91849.29" switch \initial - attribute \src "libresoc.v:90972.9-90972.17" + attribute \src "libresoc.v:91849.9-91849.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142838,18 +145136,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:90996.3-91020.6" - process $proc$libresoc.v:90996$3863 + attribute \src "libresoc.v:91873.3-91897.6" + process $proc$libresoc.v:91873$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:90997.5-90997.29" + attribute \src "libresoc.v:91874.5-91874.29" switch \initial - attribute \src "libresoc.v:90997.9-90997.17" + attribute \src "libresoc.v:91874.9-91874.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142881,18 +145179,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:91021.3-91045.6" - process $proc$libresoc.v:91021$3864 + attribute \src "libresoc.v:91898.3-91922.6" + process $proc$libresoc.v:91898$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91022.5-91022.29" + attribute \src "libresoc.v:91899.5-91899.29" switch \initial - attribute \src "libresoc.v:91022.9-91022.17" + attribute \src "libresoc.v:91899.9-91899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142924,18 +145222,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:91046.3-91070.6" - process $proc$libresoc.v:91046$3865 + attribute \src "libresoc.v:91923.3-91947.6" + process $proc$libresoc.v:91923$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:91047.5-91047.29" + attribute \src "libresoc.v:91924.5-91924.29" switch \initial - attribute \src "libresoc.v:91047.9-91047.17" + attribute \src "libresoc.v:91924.9-91924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -142967,18 +145265,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:91071.3-91095.6" - process $proc$libresoc.v:91071$3866 + attribute \src "libresoc.v:91948.3-91972.6" + process $proc$libresoc.v:91948$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91072.5-91072.29" + attribute \src "libresoc.v:91949.5-91949.29" switch \initial - attribute \src "libresoc.v:91072.9-91072.17" + attribute \src "libresoc.v:91949.9-91949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143010,18 +145308,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:91096.3-91120.6" - process $proc$libresoc.v:91096$3867 + attribute \src "libresoc.v:91973.3-91997.6" + process $proc$libresoc.v:91973$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91097.5-91097.29" + attribute \src "libresoc.v:91974.5-91974.29" switch \initial - attribute \src "libresoc.v:91097.9-91097.17" + attribute \src "libresoc.v:91974.9-91974.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143053,18 +145351,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:91121.3-91145.6" - process $proc$libresoc.v:91121$3868 + attribute \src "libresoc.v:91998.3-92022.6" + process $proc$libresoc.v:91998$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91122.5-91122.29" + attribute \src "libresoc.v:91999.5-91999.29" switch \initial - attribute \src "libresoc.v:91122.9-91122.17" + attribute \src "libresoc.v:91999.9-91999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143096,18 +145394,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:91146.3-91170.6" - process $proc$libresoc.v:91146$3869 + attribute \src "libresoc.v:92023.3-92047.6" + process $proc$libresoc.v:92023$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91147.5-91147.29" + attribute \src "libresoc.v:92024.5-92024.29" switch \initial - attribute \src "libresoc.v:91147.9-91147.17" + attribute \src "libresoc.v:92024.9-92024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143139,18 +145437,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:91171.3-91195.6" - process $proc$libresoc.v:91171$3870 + attribute \src "libresoc.v:92048.3-92072.6" + process $proc$libresoc.v:92048$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91172.5-91172.29" + attribute \src "libresoc.v:92049.5-92049.29" switch \initial - attribute \src "libresoc.v:91172.9-91172.17" + attribute \src "libresoc.v:92049.9-92049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143182,18 +145480,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:91196.3-91220.6" - process $proc$libresoc.v:91196$3871 + attribute \src "libresoc.v:92073.3-92097.6" + process $proc$libresoc.v:92073$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:91197.5-91197.29" + attribute \src "libresoc.v:92074.5-92074.29" switch \initial - attribute \src "libresoc.v:91197.9-91197.17" + attribute \src "libresoc.v:92074.9-92074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143225,18 +145523,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:91221.3-91245.6" - process $proc$libresoc.v:91221$3872 + attribute \src "libresoc.v:92098.3-92122.6" + process $proc$libresoc.v:92098$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:91222.5-91222.29" + attribute \src "libresoc.v:92099.5-92099.29" switch \initial - attribute \src "libresoc.v:91222.9-91222.17" + attribute \src "libresoc.v:92099.9-92099.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143268,18 +145566,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:91246.3-91270.6" - process $proc$libresoc.v:91246$3873 + attribute \src "libresoc.v:92123.3-92147.6" + process $proc$libresoc.v:92123$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91247.5-91247.29" + attribute \src "libresoc.v:92124.5-92124.29" switch \initial - attribute \src "libresoc.v:91247.9-91247.17" + attribute \src "libresoc.v:92124.9-92124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143311,18 +145609,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:91271.3-91295.6" - process $proc$libresoc.v:91271$3874 + attribute \src "libresoc.v:92148.3-92172.6" + process $proc$libresoc.v:92148$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:91272.5-91272.29" + attribute \src "libresoc.v:92149.5-92149.29" switch \initial - attribute \src "libresoc.v:91272.9-91272.17" + attribute \src "libresoc.v:92149.9-92149.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143354,18 +145652,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:91296.3-91320.6" - process $proc$libresoc.v:91296$3875 + attribute \src "libresoc.v:92173.3-92197.6" + process $proc$libresoc.v:92173$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:91297.5-91297.29" + attribute \src "libresoc.v:92174.5-92174.29" switch \initial - attribute \src "libresoc.v:91297.9-91297.17" + attribute \src "libresoc.v:92174.9-92174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143397,18 +145695,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:91321.3-91345.6" - process $proc$libresoc.v:91321$3876 + attribute \src "libresoc.v:92198.3-92222.6" + process $proc$libresoc.v:92198$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91322.5-91322.29" + attribute \src "libresoc.v:92199.5-92199.29" switch \initial - attribute \src "libresoc.v:91322.9-91322.17" + attribute \src "libresoc.v:92199.9-92199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143440,18 +145738,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:91346.3-91370.6" - process $proc$libresoc.v:91346$3877 + attribute \src "libresoc.v:92223.3-92247.6" + process $proc$libresoc.v:92223$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:91347.5-91347.29" + attribute \src "libresoc.v:92224.5-92224.29" switch \initial - attribute \src "libresoc.v:91347.9-91347.17" + attribute \src "libresoc.v:92224.9-92224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143483,18 +145781,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] end - attribute \src "libresoc.v:91371.3-91395.6" - process $proc$libresoc.v:91371$3878 + attribute \src "libresoc.v:92248.3-92272.6" + process $proc$libresoc.v:92248$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:91372.5-91372.29" + attribute \src "libresoc.v:92249.5-92249.29" switch \initial - attribute \src "libresoc.v:91372.9-91372.17" + attribute \src "libresoc.v:92249.9-92249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143526,18 +145824,18 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:91396.3-91420.6" - process $proc$libresoc.v:91396$3879 + attribute \src "libresoc.v:92273.3-92297.6" + process $proc$libresoc.v:92273$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:91397.5-91397.29" + attribute \src "libresoc.v:92274.5-92274.29" switch \initial - attribute \src "libresoc.v:91397.9-91397.17" + attribute \src "libresoc.v:92274.9-92274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -143571,112 +145869,112 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91426.1-92843.10" +attribute \src "libresoc.v:92303.1-93720.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:92468.3-92498.6" + attribute \src "libresoc.v:93345.3-93375.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92076.3-92124.6" + attribute \src "libresoc.v:92953.3-93001.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:92744.3-92792.6" + attribute \src "libresoc.v:93621.3-93669.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:92793.3-92841.6" + attribute \src "libresoc.v:93670.3-93718.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:91880.3-91928.6" + attribute \src "libresoc.v:92757.3-92805.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92027.3-92075.6" + attribute \src "libresoc.v:92904.3-92952.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:92499.3-92547.6" + attribute \src "libresoc.v:93376.3-93424.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:91684.3-91732.6" + attribute \src "libresoc.v:92561.3-92609.6" wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:92548.3-92596.6" + attribute \src "libresoc.v:93425.3-93473.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:92597.3-92645.6" + attribute \src "libresoc.v:93474.3-93522.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:92646.3-92694.6" + attribute \src "libresoc.v:93523.3-93571.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:92223.3-92271.6" + attribute \src "libresoc.v:93100.3-93148.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:91929.3-91977.6" + attribute \src "libresoc.v:92806.3-92854.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:91978.3-92026.6" + attribute \src "libresoc.v:92855.3-92903.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92272.3-92320.6" + attribute \src "libresoc.v:93149.3-93197.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:91733.3-91781.6" + attribute \src "libresoc.v:92610.3-92658.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:92370.3-92418.6" + attribute \src "libresoc.v:93247.3-93295.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:92695.3-92743.6" + attribute \src "libresoc.v:93572.3-93620.6" wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:91831.3-91879.6" + attribute \src "libresoc.v:92708.3-92756.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92174.3-92222.6" + attribute \src "libresoc.v:93051.3-93099.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:92419.3-92467.6" + attribute \src "libresoc.v:93296.3-93344.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:92321.3-92369.6" + attribute \src "libresoc.v:93198.3-93246.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:92125.3-92173.6" + attribute \src "libresoc.v:93002.3-93050.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:91782.3-91830.6" + attribute \src "libresoc.v:92659.3-92707.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:91427.7-91427.20" + attribute \src "libresoc.v:92304.7-92304.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92468.3-92498.6" + attribute \src "libresoc.v:93345.3-93375.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92076.3-92124.6" + attribute \src "libresoc.v:92953.3-93001.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:92744.3-92792.6" + attribute \src "libresoc.v:93621.3-93669.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:92793.3-92841.6" + attribute \src "libresoc.v:93670.3-93718.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:91880.3-91928.6" + attribute \src "libresoc.v:92757.3-92805.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92027.3-92075.6" + attribute \src "libresoc.v:92904.3-92952.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:92499.3-92547.6" + attribute \src "libresoc.v:93376.3-93424.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:91684.3-91732.6" + attribute \src "libresoc.v:92561.3-92609.6" wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:92548.3-92596.6" + attribute \src "libresoc.v:93425.3-93473.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:92597.3-92645.6" + attribute \src "libresoc.v:93474.3-93522.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:92646.3-92694.6" + attribute \src "libresoc.v:93523.3-93571.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:92223.3-92271.6" + attribute \src "libresoc.v:93100.3-93148.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:91929.3-91977.6" + attribute \src "libresoc.v:92806.3-92854.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:91978.3-92026.6" + attribute \src "libresoc.v:92855.3-92903.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92272.3-92320.6" + attribute \src "libresoc.v:93149.3-93197.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:91733.3-91781.6" + attribute \src "libresoc.v:92610.3-92658.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:92370.3-92418.6" + attribute \src "libresoc.v:93247.3-93295.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:92695.3-92743.6" + attribute \src "libresoc.v:93572.3-93620.6" wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:91831.3-91879.6" + attribute \src "libresoc.v:92708.3-92756.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92174.3-92222.6" + attribute \src "libresoc.v:93051.3-93099.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:92419.3-92467.6" + attribute \src "libresoc.v:93296.3-93344.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:92321.3-92369.6" + attribute \src "libresoc.v:93198.3-93246.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:92125.3-92173.6" + attribute \src "libresoc.v:93002.3-93050.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:91782.3-91830.6" + attribute \src "libresoc.v:92659.3-92707.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub21_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -143686,7 +145984,7 @@ module \dec31_dec_sub21 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub21_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -143694,15 +145992,15 @@ module \dec31_dec_sub21 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub21_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub21_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -143734,7 +146032,7 @@ module \dec31_dec_sub21 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -143749,7 +146047,7 @@ module \dec31_dec_sub21 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub21_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -143757,7 +146055,7 @@ module \dec31_dec_sub21 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub21_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -143774,13 +146072,13 @@ module \dec31_dec_sub21 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub21_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub21_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -143856,13 +146154,13 @@ module \dec31_dec_sub21 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub21_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -143870,64 +146168,64 @@ module \dec31_dec_sub21 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub21_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub21_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub21_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "libresoc.v:91427.7-91427.15" + attribute \src "libresoc.v:92304.7-92304.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:91427.7-91427.20" - process $proc$libresoc.v:91427$3905 + attribute \src "libresoc.v:92304.7-92304.20" + process $proc$libresoc.v:92304$3986 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91684.3-91732.6" - process $proc$libresoc.v:91684$3881 + attribute \src "libresoc.v:92561.3-92609.6" + process $proc$libresoc.v:92561$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:91685.5-91685.29" + attribute \src "libresoc.v:92562.5-92562.29" switch \initial - attribute \src "libresoc.v:91685.9-91685.17" + attribute \src "libresoc.v:92562.9-92562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -143991,18 +146289,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] end - attribute \src "libresoc.v:91733.3-91781.6" - process $proc$libresoc.v:91733$3882 + attribute \src "libresoc.v:92610.3-92658.6" + process $proc$libresoc.v:92610$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:91734.5-91734.29" + attribute \src "libresoc.v:92611.5-92611.29" switch \initial - attribute \src "libresoc.v:91734.9-91734.17" + attribute \src "libresoc.v:92611.9-92611.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144066,18 +146364,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:91782.3-91830.6" - process $proc$libresoc.v:91782$3883 + attribute \src "libresoc.v:92659.3-92707.6" + process $proc$libresoc.v:92659$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:91783.5-91783.29" + attribute \src "libresoc.v:92660.5-92660.29" switch \initial - attribute \src "libresoc.v:91783.9-91783.17" + attribute \src "libresoc.v:92660.9-92660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144141,18 +146439,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:91831.3-91879.6" - process $proc$libresoc.v:91831$3884 + attribute \src "libresoc.v:92708.3-92756.6" + process $proc$libresoc.v:92708$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:91832.5-91832.29" + attribute \src "libresoc.v:92709.5-92709.29" switch \initial - attribute \src "libresoc.v:91832.9-91832.17" + attribute \src "libresoc.v:92709.9-92709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144216,18 +146514,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:91880.3-91928.6" - process $proc$libresoc.v:91880$3885 + attribute \src "libresoc.v:92757.3-92805.6" + process $proc$libresoc.v:92757$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:91881.5-91881.29" + attribute \src "libresoc.v:92758.5-92758.29" switch \initial - attribute \src "libresoc.v:91881.9-91881.17" + attribute \src "libresoc.v:92758.9-92758.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144291,18 +146589,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:91929.3-91977.6" - process $proc$libresoc.v:91929$3886 + attribute \src "libresoc.v:92806.3-92854.6" + process $proc$libresoc.v:92806$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:91930.5-91930.29" + attribute \src "libresoc.v:92807.5-92807.29" switch \initial - attribute \src "libresoc.v:91930.9-91930.17" + attribute \src "libresoc.v:92807.9-92807.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144366,18 +146664,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:91978.3-92026.6" - process $proc$libresoc.v:91978$3887 + attribute \src "libresoc.v:92855.3-92903.6" + process $proc$libresoc.v:92855$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:91979.5-91979.29" + attribute \src "libresoc.v:92856.5-92856.29" switch \initial - attribute \src "libresoc.v:91979.9-91979.17" + attribute \src "libresoc.v:92856.9-92856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144441,18 +146739,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:92027.3-92075.6" - process $proc$libresoc.v:92027$3888 + attribute \src "libresoc.v:92904.3-92952.6" + process $proc$libresoc.v:92904$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:92028.5-92028.29" + attribute \src "libresoc.v:92905.5-92905.29" switch \initial - attribute \src "libresoc.v:92028.9-92028.17" + attribute \src "libresoc.v:92905.9-92905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144516,18 +146814,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:92076.3-92124.6" - process $proc$libresoc.v:92076$3889 + attribute \src "libresoc.v:92953.3-93001.6" + process $proc$libresoc.v:92953$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:92077.5-92077.29" + attribute \src "libresoc.v:92954.5-92954.29" switch \initial - attribute \src "libresoc.v:92077.9-92077.17" + attribute \src "libresoc.v:92954.9-92954.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144591,18 +146889,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:92125.3-92173.6" - process $proc$libresoc.v:92125$3890 + attribute \src "libresoc.v:93002.3-93050.6" + process $proc$libresoc.v:93002$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92126.5-92126.29" + attribute \src "libresoc.v:93003.5-93003.29" switch \initial - attribute \src "libresoc.v:92126.9-92126.17" + attribute \src "libresoc.v:93003.9-93003.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144666,18 +146964,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:92174.3-92222.6" - process $proc$libresoc.v:92174$3891 + attribute \src "libresoc.v:93051.3-93099.6" + process $proc$libresoc.v:93051$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:92175.5-92175.29" + attribute \src "libresoc.v:93052.5-93052.29" switch \initial - attribute \src "libresoc.v:92175.9-92175.17" + attribute \src "libresoc.v:93052.9-93052.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144741,18 +147039,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:92223.3-92271.6" - process $proc$libresoc.v:92223$3892 + attribute \src "libresoc.v:93100.3-93148.6" + process $proc$libresoc.v:93100$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92224.5-92224.29" + attribute \src "libresoc.v:93101.5-93101.29" switch \initial - attribute \src "libresoc.v:92224.9-92224.17" + attribute \src "libresoc.v:93101.9-93101.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144816,18 +147114,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:92272.3-92320.6" - process $proc$libresoc.v:92272$3893 + attribute \src "libresoc.v:93149.3-93197.6" + process $proc$libresoc.v:93149$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92273.5-92273.29" + attribute \src "libresoc.v:93150.5-93150.29" switch \initial - attribute \src "libresoc.v:92273.9-92273.17" + attribute \src "libresoc.v:93150.9-93150.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144891,18 +147189,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:92321.3-92369.6" - process $proc$libresoc.v:92321$3894 + attribute \src "libresoc.v:93198.3-93246.6" + process $proc$libresoc.v:93198$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:92322.5-92322.29" + attribute \src "libresoc.v:93199.5-93199.29" switch \initial - attribute \src "libresoc.v:92322.9-92322.17" + attribute \src "libresoc.v:93199.9-93199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -144966,18 +147264,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:92370.3-92418.6" - process $proc$libresoc.v:92370$3895 + attribute \src "libresoc.v:93247.3-93295.6" + process $proc$libresoc.v:93247$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:92371.5-92371.29" + attribute \src "libresoc.v:93248.5-93248.29" switch \initial - attribute \src "libresoc.v:92371.9-92371.17" + attribute \src "libresoc.v:93248.9-93248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145041,18 +147339,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:92419.3-92467.6" - process $proc$libresoc.v:92419$3896 + attribute \src "libresoc.v:93296.3-93344.6" + process $proc$libresoc.v:93296$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:92420.5-92420.29" + attribute \src "libresoc.v:93297.5-93297.29" switch \initial - attribute \src "libresoc.v:92420.9-92420.17" + attribute \src "libresoc.v:93297.9-93297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145116,18 +147414,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:92468.3-92498.6" - process $proc$libresoc.v:92468$3897 + attribute \src "libresoc.v:93345.3-93375.6" + process $proc$libresoc.v:93345$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92469.5-92469.29" + attribute \src "libresoc.v:93346.5-93346.29" switch \initial - attribute \src "libresoc.v:92469.9-92469.17" + attribute \src "libresoc.v:93346.9-93346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -145167,18 +147465,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:92499.3-92547.6" - process $proc$libresoc.v:92499$3898 + attribute \src "libresoc.v:93376.3-93424.6" + process $proc$libresoc.v:93376$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:92500.5-92500.29" + attribute \src "libresoc.v:93377.5-93377.29" switch \initial - attribute \src "libresoc.v:92500.9-92500.17" + attribute \src "libresoc.v:93377.9-93377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145242,18 +147540,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:92548.3-92596.6" - process $proc$libresoc.v:92548$3899 + attribute \src "libresoc.v:93425.3-93473.6" + process $proc$libresoc.v:93425$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:92549.5-92549.29" + attribute \src "libresoc.v:93426.5-93426.29" switch \initial - attribute \src "libresoc.v:92549.9-92549.17" + attribute \src "libresoc.v:93426.9-93426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145317,18 +147615,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:92597.3-92645.6" - process $proc$libresoc.v:92597$3900 + attribute \src "libresoc.v:93474.3-93522.6" + process $proc$libresoc.v:93474$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:92598.5-92598.29" + attribute \src "libresoc.v:93475.5-93475.29" switch \initial - attribute \src "libresoc.v:92598.9-92598.17" + attribute \src "libresoc.v:93475.9-93475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145392,18 +147690,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:92646.3-92694.6" - process $proc$libresoc.v:92646$3901 + attribute \src "libresoc.v:93523.3-93571.6" + process $proc$libresoc.v:93523$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:92647.5-92647.29" + attribute \src "libresoc.v:93524.5-93524.29" switch \initial - attribute \src "libresoc.v:92647.9-92647.17" + attribute \src "libresoc.v:93524.9-93524.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145467,18 +147765,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:92695.3-92743.6" - process $proc$libresoc.v:92695$3902 + attribute \src "libresoc.v:93572.3-93620.6" + process $proc$libresoc.v:93572$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:92696.5-92696.29" + attribute \src "libresoc.v:93573.5-93573.29" switch \initial - attribute \src "libresoc.v:92696.9-92696.17" + attribute \src "libresoc.v:93573.9-93573.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145542,18 +147840,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] end - attribute \src "libresoc.v:92744.3-92792.6" - process $proc$libresoc.v:92744$3903 + attribute \src "libresoc.v:93621.3-93669.6" + process $proc$libresoc.v:93621$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:92745.5-92745.29" + attribute \src "libresoc.v:93622.5-93622.29" switch \initial - attribute \src "libresoc.v:92745.9-92745.17" + attribute \src "libresoc.v:93622.9-93622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145617,18 +147915,18 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:92793.3-92841.6" - process $proc$libresoc.v:92793$3904 + attribute \src "libresoc.v:93670.3-93718.6" + process $proc$libresoc.v:93670$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:92794.5-92794.29" + attribute \src "libresoc.v:93671.5-93671.29" switch \initial - attribute \src "libresoc.v:92794.9-92794.17" + attribute \src "libresoc.v:93671.9-93671.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11010 @@ -145694,112 +147992,112 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:92847.1-94426.10" +attribute \src "libresoc.v:93724.1-95303.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:93380.3-93434.6" + attribute \src "libresoc.v:94257.3-94311.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:93600.3-93654.6" + attribute \src "libresoc.v:94477.3-94531.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:94315.3-94369.6" + attribute \src "libresoc.v:95192.3-95246.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:94370.3-94424.6" + attribute \src "libresoc.v:95247.3-95301.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:93325.3-93379.6" + attribute \src "libresoc.v:94202.3-94256.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:93545.3-93599.6" + attribute \src "libresoc.v:94422.3-94476.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94040.3-94094.6" + attribute \src "libresoc.v:94917.3-94971.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93105.3-93159.6" + attribute \src "libresoc.v:93982.3-94036.6" wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94095.3-94149.6" + attribute \src "libresoc.v:94972.3-95026.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94150.3-94204.6" + attribute \src "libresoc.v:95027.3-95081.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94205.3-94259.6" + attribute \src "libresoc.v:95082.3-95136.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:93710.3-93764.6" + attribute \src "libresoc.v:94587.3-94641.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:93435.3-93489.6" + attribute \src "libresoc.v:94312.3-94366.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:93490.3-93544.6" + attribute \src "libresoc.v:94367.3-94421.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:93820.3-93874.6" + attribute \src "libresoc.v:94697.3-94751.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:93160.3-93214.6" + attribute \src "libresoc.v:94037.3-94091.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:93930.3-93984.6" + attribute \src "libresoc.v:94807.3-94861.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94260.3-94314.6" + attribute \src "libresoc.v:95137.3-95191.6" wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:93270.3-93324.6" + attribute \src "libresoc.v:94147.3-94201.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:93765.3-93819.6" + attribute \src "libresoc.v:94642.3-94696.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:93985.3-94039.6" + attribute \src "libresoc.v:94862.3-94916.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:93875.3-93929.6" + attribute \src "libresoc.v:94752.3-94806.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:93655.3-93709.6" + attribute \src "libresoc.v:94532.3-94586.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:93215.3-93269.6" + attribute \src "libresoc.v:94092.3-94146.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:92848.7-92848.20" + attribute \src "libresoc.v:93725.7-93725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:93380.3-93434.6" + attribute \src "libresoc.v:94257.3-94311.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:93600.3-93654.6" + attribute \src "libresoc.v:94477.3-94531.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:94315.3-94369.6" + attribute \src "libresoc.v:95192.3-95246.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:94370.3-94424.6" + attribute \src "libresoc.v:95247.3-95301.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:93325.3-93379.6" + attribute \src "libresoc.v:94202.3-94256.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:93545.3-93599.6" + attribute \src "libresoc.v:94422.3-94476.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94040.3-94094.6" + attribute \src "libresoc.v:94917.3-94971.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93105.3-93159.6" + attribute \src "libresoc.v:93982.3-94036.6" wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94095.3-94149.6" + attribute \src "libresoc.v:94972.3-95026.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94150.3-94204.6" + attribute \src "libresoc.v:95027.3-95081.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94205.3-94259.6" + attribute \src "libresoc.v:95082.3-95136.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:93710.3-93764.6" + attribute \src "libresoc.v:94587.3-94641.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:93435.3-93489.6" + attribute \src "libresoc.v:94312.3-94366.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:93490.3-93544.6" + attribute \src "libresoc.v:94367.3-94421.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:93820.3-93874.6" + attribute \src "libresoc.v:94697.3-94751.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:93160.3-93214.6" + attribute \src "libresoc.v:94037.3-94091.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:93930.3-93984.6" + attribute \src "libresoc.v:94807.3-94861.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94260.3-94314.6" + attribute \src "libresoc.v:95137.3-95191.6" wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:93270.3-93324.6" + attribute \src "libresoc.v:94147.3-94201.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:93765.3-93819.6" + attribute \src "libresoc.v:94642.3-94696.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:93985.3-94039.6" + attribute \src "libresoc.v:94862.3-94916.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:93875.3-93929.6" + attribute \src "libresoc.v:94752.3-94806.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:93655.3-93709.6" + attribute \src "libresoc.v:94532.3-94586.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:93215.3-93269.6" + attribute \src "libresoc.v:94092.3-94146.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub22_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -145809,7 +148107,7 @@ module \dec31_dec_sub22 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub22_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -145817,15 +148115,15 @@ module \dec31_dec_sub22 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub22_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub22_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -145857,7 +148155,7 @@ module \dec31_dec_sub22 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -145872,7 +148170,7 @@ module \dec31_dec_sub22 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub22_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -145880,7 +148178,7 @@ module \dec31_dec_sub22 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub22_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -145897,13 +148195,13 @@ module \dec31_dec_sub22 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub22_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub22_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -145979,13 +148277,13 @@ module \dec31_dec_sub22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub22_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -145993,64 +148291,64 @@ module \dec31_dec_sub22 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub22_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub22_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub22_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "libresoc.v:92848.7-92848.15" + attribute \src "libresoc.v:93725.7-93725.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:92848.7-92848.20" - process $proc$libresoc.v:92848$3930 + attribute \src "libresoc.v:93725.7-93725.20" + process $proc$libresoc.v:93725$4011 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93105.3-93159.6" - process $proc$libresoc.v:93105$3906 + attribute \src "libresoc.v:93982.3-94036.6" + process $proc$libresoc.v:93982$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:93106.5-93106.29" + attribute \src "libresoc.v:93983.5-93983.29" switch \initial - attribute \src "libresoc.v:93106.9-93106.17" + attribute \src "libresoc.v:93983.9-93983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146122,18 +148420,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] end - attribute \src "libresoc.v:93160.3-93214.6" - process $proc$libresoc.v:93160$3907 + attribute \src "libresoc.v:94037.3-94091.6" + process $proc$libresoc.v:94037$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:93161.5-93161.29" + attribute \src "libresoc.v:94038.5-94038.29" switch \initial - attribute \src "libresoc.v:93161.9-93161.17" + attribute \src "libresoc.v:94038.9-94038.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146205,18 +148503,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:93215.3-93269.6" - process $proc$libresoc.v:93215$3908 + attribute \src "libresoc.v:94092.3-94146.6" + process $proc$libresoc.v:94092$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:93216.5-93216.29" + attribute \src "libresoc.v:94093.5-94093.29" switch \initial - attribute \src "libresoc.v:93216.9-93216.17" + attribute \src "libresoc.v:94093.9-94093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146288,18 +148586,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:93270.3-93324.6" - process $proc$libresoc.v:93270$3909 + attribute \src "libresoc.v:94147.3-94201.6" + process $proc$libresoc.v:94147$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:93271.5-93271.29" + attribute \src "libresoc.v:94148.5-94148.29" switch \initial - attribute \src "libresoc.v:93271.9-93271.17" + attribute \src "libresoc.v:94148.9-94148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146371,18 +148669,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:93325.3-93379.6" - process $proc$libresoc.v:93325$3910 + attribute \src "libresoc.v:94202.3-94256.6" + process $proc$libresoc.v:94202$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:93326.5-93326.29" + attribute \src "libresoc.v:94203.5-94203.29" switch \initial - attribute \src "libresoc.v:93326.9-93326.17" + attribute \src "libresoc.v:94203.9-94203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146454,18 +148752,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:93380.3-93434.6" - process $proc$libresoc.v:93380$3911 + attribute \src "libresoc.v:94257.3-94311.6" + process $proc$libresoc.v:94257$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:93381.5-93381.29" + attribute \src "libresoc.v:94258.5-94258.29" switch \initial - attribute \src "libresoc.v:93381.9-93381.17" + attribute \src "libresoc.v:94258.9-94258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146537,18 +148835,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:93435.3-93489.6" - process $proc$libresoc.v:93435$3912 + attribute \src "libresoc.v:94312.3-94366.6" + process $proc$libresoc.v:94312$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:93436.5-93436.29" + attribute \src "libresoc.v:94313.5-94313.29" switch \initial - attribute \src "libresoc.v:93436.9-93436.17" + attribute \src "libresoc.v:94313.9-94313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146620,18 +148918,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:93490.3-93544.6" - process $proc$libresoc.v:93490$3913 + attribute \src "libresoc.v:94367.3-94421.6" + process $proc$libresoc.v:94367$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:93491.5-93491.29" + attribute \src "libresoc.v:94368.5-94368.29" switch \initial - attribute \src "libresoc.v:93491.9-93491.17" + attribute \src "libresoc.v:94368.9-94368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146703,18 +149001,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:93545.3-93599.6" - process $proc$libresoc.v:93545$3914 + attribute \src "libresoc.v:94422.3-94476.6" + process $proc$libresoc.v:94422$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:93546.5-93546.29" + attribute \src "libresoc.v:94423.5-94423.29" switch \initial - attribute \src "libresoc.v:93546.9-93546.17" + attribute \src "libresoc.v:94423.9-94423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146786,18 +149084,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:93600.3-93654.6" - process $proc$libresoc.v:93600$3915 + attribute \src "libresoc.v:94477.3-94531.6" + process $proc$libresoc.v:94477$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:93601.5-93601.29" + attribute \src "libresoc.v:94478.5-94478.29" switch \initial - attribute \src "libresoc.v:93601.9-93601.17" + attribute \src "libresoc.v:94478.9-94478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146869,18 +149167,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:93655.3-93709.6" - process $proc$libresoc.v:93655$3916 + attribute \src "libresoc.v:94532.3-94586.6" + process $proc$libresoc.v:94532$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:93656.5-93656.29" + attribute \src "libresoc.v:94533.5-94533.29" switch \initial - attribute \src "libresoc.v:93656.9-93656.17" + attribute \src "libresoc.v:94533.9-94533.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -146952,18 +149250,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:93710.3-93764.6" - process $proc$libresoc.v:93710$3917 + attribute \src "libresoc.v:94587.3-94641.6" + process $proc$libresoc.v:94587$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:93711.5-93711.29" + attribute \src "libresoc.v:94588.5-94588.29" switch \initial - attribute \src "libresoc.v:93711.9-93711.17" + attribute \src "libresoc.v:94588.9-94588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147035,18 +149333,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:93765.3-93819.6" - process $proc$libresoc.v:93765$3918 + attribute \src "libresoc.v:94642.3-94696.6" + process $proc$libresoc.v:94642$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:93766.5-93766.29" + attribute \src "libresoc.v:94643.5-94643.29" switch \initial - attribute \src "libresoc.v:93766.9-93766.17" + attribute \src "libresoc.v:94643.9-94643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147118,18 +149416,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:93820.3-93874.6" - process $proc$libresoc.v:93820$3919 + attribute \src "libresoc.v:94697.3-94751.6" + process $proc$libresoc.v:94697$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:93821.5-93821.29" + attribute \src "libresoc.v:94698.5-94698.29" switch \initial - attribute \src "libresoc.v:93821.9-93821.17" + attribute \src "libresoc.v:94698.9-94698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147201,18 +149499,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:93875.3-93929.6" - process $proc$libresoc.v:93875$3920 + attribute \src "libresoc.v:94752.3-94806.6" + process $proc$libresoc.v:94752$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:93876.5-93876.29" + attribute \src "libresoc.v:94753.5-94753.29" switch \initial - attribute \src "libresoc.v:93876.9-93876.17" + attribute \src "libresoc.v:94753.9-94753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147284,18 +149582,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:93930.3-93984.6" - process $proc$libresoc.v:93930$3921 + attribute \src "libresoc.v:94807.3-94861.6" + process $proc$libresoc.v:94807$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:93931.5-93931.29" + attribute \src "libresoc.v:94808.5-94808.29" switch \initial - attribute \src "libresoc.v:93931.9-93931.17" + attribute \src "libresoc.v:94808.9-94808.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147367,18 +149665,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:93985.3-94039.6" - process $proc$libresoc.v:93985$3922 + attribute \src "libresoc.v:94862.3-94916.6" + process $proc$libresoc.v:94862$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:93986.5-93986.29" + attribute \src "libresoc.v:94863.5-94863.29" switch \initial - attribute \src "libresoc.v:93986.9-93986.17" + attribute \src "libresoc.v:94863.9-94863.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147450,18 +149748,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:94040.3-94094.6" - process $proc$libresoc.v:94040$3923 + attribute \src "libresoc.v:94917.3-94971.6" + process $proc$libresoc.v:94917$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:94041.5-94041.29" + attribute \src "libresoc.v:94918.5-94918.29" switch \initial - attribute \src "libresoc.v:94041.9-94041.17" + attribute \src "libresoc.v:94918.9-94918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147533,18 +149831,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:94095.3-94149.6" - process $proc$libresoc.v:94095$3924 + attribute \src "libresoc.v:94972.3-95026.6" + process $proc$libresoc.v:94972$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94096.5-94096.29" + attribute \src "libresoc.v:94973.5-94973.29" switch \initial - attribute \src "libresoc.v:94096.9-94096.17" + attribute \src "libresoc.v:94973.9-94973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147616,18 +149914,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:94150.3-94204.6" - process $proc$libresoc.v:94150$3925 + attribute \src "libresoc.v:95027.3-95081.6" + process $proc$libresoc.v:95027$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:94151.5-94151.29" + attribute \src "libresoc.v:95028.5-95028.29" switch \initial - attribute \src "libresoc.v:94151.9-94151.17" + attribute \src "libresoc.v:95028.9-95028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147699,18 +149997,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:94205.3-94259.6" - process $proc$libresoc.v:94205$3926 + attribute \src "libresoc.v:95082.3-95136.6" + process $proc$libresoc.v:95082$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94206.5-94206.29" + attribute \src "libresoc.v:95083.5-95083.29" switch \initial - attribute \src "libresoc.v:94206.9-94206.17" + attribute \src "libresoc.v:95083.9-95083.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147782,18 +150080,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:94260.3-94314.6" - process $proc$libresoc.v:94260$3927 + attribute \src "libresoc.v:95137.3-95191.6" + process $proc$libresoc.v:95137$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:94261.5-94261.29" + attribute \src "libresoc.v:95138.5-95138.29" switch \initial - attribute \src "libresoc.v:94261.9-94261.17" + attribute \src "libresoc.v:95138.9-95138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147865,18 +150163,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] end - attribute \src "libresoc.v:94315.3-94369.6" - process $proc$libresoc.v:94315$3928 + attribute \src "libresoc.v:95192.3-95246.6" + process $proc$libresoc.v:95192$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:94316.5-94316.29" + attribute \src "libresoc.v:95193.5-95193.29" switch \initial - attribute \src "libresoc.v:94316.9-94316.17" + attribute \src "libresoc.v:95193.9-95193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -147948,18 +150246,18 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:94370.3-94424.6" - process $proc$libresoc.v:94370$3929 + attribute \src "libresoc.v:95247.3-95301.6" + process $proc$libresoc.v:95247$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:94371.5-94371.29" + attribute \src "libresoc.v:95248.5-95248.29" switch \initial - attribute \src "libresoc.v:94371.9-94371.17" + attribute \src "libresoc.v:95248.9-95248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -148033,112 +150331,112 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:94430.1-95865.10" +attribute \src "libresoc.v:95307.1-96742.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:94933.3-94981.6" + attribute \src "libresoc.v:95810.3-95858.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95129.3-95177.6" + attribute \src "libresoc.v:96006.3-96054.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:95766.3-95814.6" + attribute \src "libresoc.v:96643.3-96691.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:95815.3-95863.6" + attribute \src "libresoc.v:96692.3-96740.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:94884.3-94932.6" + attribute \src "libresoc.v:95761.3-95809.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95080.3-95128.6" + attribute \src "libresoc.v:95957.3-96005.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:95521.3-95569.6" + attribute \src "libresoc.v:96398.3-96446.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:94688.3-94736.6" + attribute \src "libresoc.v:95565.3-95613.6" wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:95570.3-95618.6" + attribute \src "libresoc.v:96447.3-96495.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:95619.3-95667.6" + attribute \src "libresoc.v:96496.3-96544.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:95668.3-95716.6" + attribute \src "libresoc.v:96545.3-96593.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:95227.3-95275.6" + attribute \src "libresoc.v:96104.3-96152.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:94982.3-95030.6" + attribute \src "libresoc.v:95859.3-95907.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95031.3-95079.6" + attribute \src "libresoc.v:95908.3-95956.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:95325.3-95373.6" + attribute \src "libresoc.v:96202.3-96250.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:94737.3-94785.6" + attribute \src "libresoc.v:95614.3-95662.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:95423.3-95471.6" + attribute \src "libresoc.v:96300.3-96348.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:95717.3-95765.6" + attribute \src "libresoc.v:96594.3-96642.6" wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:94835.3-94883.6" + attribute \src "libresoc.v:95712.3-95760.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95276.3-95324.6" + attribute \src "libresoc.v:96153.3-96201.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:95472.3-95520.6" + attribute \src "libresoc.v:96349.3-96397.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:95374.3-95422.6" + attribute \src "libresoc.v:96251.3-96299.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:95178.3-95226.6" + attribute \src "libresoc.v:96055.3-96103.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:94786.3-94834.6" + attribute \src "libresoc.v:95663.3-95711.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:94431.7-94431.20" + attribute \src "libresoc.v:95308.7-95308.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94933.3-94981.6" + attribute \src "libresoc.v:95810.3-95858.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95129.3-95177.6" + attribute \src "libresoc.v:96006.3-96054.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:95766.3-95814.6" + attribute \src "libresoc.v:96643.3-96691.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:95815.3-95863.6" + attribute \src "libresoc.v:96692.3-96740.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:94884.3-94932.6" + attribute \src "libresoc.v:95761.3-95809.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95080.3-95128.6" + attribute \src "libresoc.v:95957.3-96005.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:95521.3-95569.6" + attribute \src "libresoc.v:96398.3-96446.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:94688.3-94736.6" + attribute \src "libresoc.v:95565.3-95613.6" wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:95570.3-95618.6" + attribute \src "libresoc.v:96447.3-96495.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:95619.3-95667.6" + attribute \src "libresoc.v:96496.3-96544.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:95668.3-95716.6" + attribute \src "libresoc.v:96545.3-96593.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:95227.3-95275.6" + attribute \src "libresoc.v:96104.3-96152.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:94982.3-95030.6" + attribute \src "libresoc.v:95859.3-95907.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95031.3-95079.6" + attribute \src "libresoc.v:95908.3-95956.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:95325.3-95373.6" + attribute \src "libresoc.v:96202.3-96250.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:94737.3-94785.6" + attribute \src "libresoc.v:95614.3-95662.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:95423.3-95471.6" + attribute \src "libresoc.v:96300.3-96348.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:95717.3-95765.6" + attribute \src "libresoc.v:96594.3-96642.6" wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:94835.3-94883.6" + attribute \src "libresoc.v:95712.3-95760.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95276.3-95324.6" + attribute \src "libresoc.v:96153.3-96201.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:95472.3-95520.6" + attribute \src "libresoc.v:96349.3-96397.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:95374.3-95422.6" + attribute \src "libresoc.v:96251.3-96299.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:95178.3-95226.6" + attribute \src "libresoc.v:96055.3-96103.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:94786.3-94834.6" + attribute \src "libresoc.v:95663.3-95711.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub23_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -148148,7 +150446,7 @@ module \dec31_dec_sub23 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub23_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -148156,15 +150454,15 @@ module \dec31_dec_sub23 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub23_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub23_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -148196,7 +150494,7 @@ module \dec31_dec_sub23 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -148211,7 +150509,7 @@ module \dec31_dec_sub23 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub23_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -148219,7 +150517,7 @@ module \dec31_dec_sub23 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub23_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -148236,13 +150534,13 @@ module \dec31_dec_sub23 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub23_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub23_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -148318,13 +150616,13 @@ module \dec31_dec_sub23 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub23_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -148332,64 +150630,64 @@ module \dec31_dec_sub23 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub23_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub23_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub23_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "libresoc.v:94431.7-94431.15" + attribute \src "libresoc.v:95308.7-95308.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:94431.7-94431.20" - process $proc$libresoc.v:94431$3955 + attribute \src "libresoc.v:95308.7-95308.20" + process $proc$libresoc.v:95308$4036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:94688.3-94736.6" - process $proc$libresoc.v:94688$3931 + attribute \src "libresoc.v:95565.3-95613.6" + process $proc$libresoc.v:95565$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:94689.5-94689.29" + attribute \src "libresoc.v:95566.5-95566.29" switch \initial - attribute \src "libresoc.v:94689.9-94689.17" + attribute \src "libresoc.v:95566.9-95566.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148453,18 +150751,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] end - attribute \src "libresoc.v:94737.3-94785.6" - process $proc$libresoc.v:94737$3932 + attribute \src "libresoc.v:95614.3-95662.6" + process $proc$libresoc.v:95614$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:94738.5-94738.29" + attribute \src "libresoc.v:95615.5-95615.29" switch \initial - attribute \src "libresoc.v:94738.9-94738.17" + attribute \src "libresoc.v:95615.9-95615.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148528,18 +150826,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:94786.3-94834.6" - process $proc$libresoc.v:94786$3933 + attribute \src "libresoc.v:95663.3-95711.6" + process $proc$libresoc.v:95663$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:94787.5-94787.29" + attribute \src "libresoc.v:95664.5-95664.29" switch \initial - attribute \src "libresoc.v:94787.9-94787.17" + attribute \src "libresoc.v:95664.9-95664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148603,18 +150901,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:94835.3-94883.6" - process $proc$libresoc.v:94835$3934 + attribute \src "libresoc.v:95712.3-95760.6" + process $proc$libresoc.v:95712$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:94836.5-94836.29" + attribute \src "libresoc.v:95713.5-95713.29" switch \initial - attribute \src "libresoc.v:94836.9-94836.17" + attribute \src "libresoc.v:95713.9-95713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148678,18 +150976,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:94884.3-94932.6" - process $proc$libresoc.v:94884$3935 + attribute \src "libresoc.v:95761.3-95809.6" + process $proc$libresoc.v:95761$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:94885.5-94885.29" + attribute \src "libresoc.v:95762.5-95762.29" switch \initial - attribute \src "libresoc.v:94885.9-94885.17" + attribute \src "libresoc.v:95762.9-95762.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148753,18 +151051,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:94933.3-94981.6" - process $proc$libresoc.v:94933$3936 + attribute \src "libresoc.v:95810.3-95858.6" + process $proc$libresoc.v:95810$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:94934.5-94934.29" + attribute \src "libresoc.v:95811.5-95811.29" switch \initial - attribute \src "libresoc.v:94934.9-94934.17" + attribute \src "libresoc.v:95811.9-95811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148828,18 +151126,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:94982.3-95030.6" - process $proc$libresoc.v:94982$3937 + attribute \src "libresoc.v:95859.3-95907.6" + process $proc$libresoc.v:95859$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:94983.5-94983.29" + attribute \src "libresoc.v:95860.5-95860.29" switch \initial - attribute \src "libresoc.v:94983.9-94983.17" + attribute \src "libresoc.v:95860.9-95860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148903,18 +151201,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:95031.3-95079.6" - process $proc$libresoc.v:95031$3938 + attribute \src "libresoc.v:95908.3-95956.6" + process $proc$libresoc.v:95908$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:95032.5-95032.29" + attribute \src "libresoc.v:95909.5-95909.29" switch \initial - attribute \src "libresoc.v:95032.9-95032.17" + attribute \src "libresoc.v:95909.9-95909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -148978,18 +151276,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:95080.3-95128.6" - process $proc$libresoc.v:95080$3939 + attribute \src "libresoc.v:95957.3-96005.6" + process $proc$libresoc.v:95957$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:95081.5-95081.29" + attribute \src "libresoc.v:95958.5-95958.29" switch \initial - attribute \src "libresoc.v:95081.9-95081.17" + attribute \src "libresoc.v:95958.9-95958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149053,18 +151351,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:95129.3-95177.6" - process $proc$libresoc.v:95129$3940 + attribute \src "libresoc.v:96006.3-96054.6" + process $proc$libresoc.v:96006$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:95130.5-95130.29" + attribute \src "libresoc.v:96007.5-96007.29" switch \initial - attribute \src "libresoc.v:95130.9-95130.17" + attribute \src "libresoc.v:96007.9-96007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149128,18 +151426,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:95178.3-95226.6" - process $proc$libresoc.v:95178$3941 + attribute \src "libresoc.v:96055.3-96103.6" + process $proc$libresoc.v:96055$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95179.5-95179.29" + attribute \src "libresoc.v:96056.5-96056.29" switch \initial - attribute \src "libresoc.v:95179.9-95179.17" + attribute \src "libresoc.v:96056.9-96056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149203,18 +151501,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:95227.3-95275.6" - process $proc$libresoc.v:95227$3942 + attribute \src "libresoc.v:96104.3-96152.6" + process $proc$libresoc.v:96104$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95228.5-95228.29" + attribute \src "libresoc.v:96105.5-96105.29" switch \initial - attribute \src "libresoc.v:95228.9-95228.17" + attribute \src "libresoc.v:96105.9-96105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149278,18 +151576,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:95276.3-95324.6" - process $proc$libresoc.v:95276$3943 + attribute \src "libresoc.v:96153.3-96201.6" + process $proc$libresoc.v:96153$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:95277.5-95277.29" + attribute \src "libresoc.v:96154.5-96154.29" switch \initial - attribute \src "libresoc.v:95277.9-95277.17" + attribute \src "libresoc.v:96154.9-96154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149353,18 +151651,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:95325.3-95373.6" - process $proc$libresoc.v:95325$3944 + attribute \src "libresoc.v:96202.3-96250.6" + process $proc$libresoc.v:96202$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:95326.5-95326.29" + attribute \src "libresoc.v:96203.5-96203.29" switch \initial - attribute \src "libresoc.v:95326.9-95326.17" + attribute \src "libresoc.v:96203.9-96203.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149428,18 +151726,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:95374.3-95422.6" - process $proc$libresoc.v:95374$3945 + attribute \src "libresoc.v:96251.3-96299.6" + process $proc$libresoc.v:96251$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:95375.5-95375.29" + attribute \src "libresoc.v:96252.5-96252.29" switch \initial - attribute \src "libresoc.v:95375.9-95375.17" + attribute \src "libresoc.v:96252.9-96252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149503,18 +151801,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:95423.3-95471.6" - process $proc$libresoc.v:95423$3946 + attribute \src "libresoc.v:96300.3-96348.6" + process $proc$libresoc.v:96300$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:95424.5-95424.29" + attribute \src "libresoc.v:96301.5-96301.29" switch \initial - attribute \src "libresoc.v:95424.9-95424.17" + attribute \src "libresoc.v:96301.9-96301.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149578,18 +151876,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:95472.3-95520.6" - process $proc$libresoc.v:95472$3947 + attribute \src "libresoc.v:96349.3-96397.6" + process $proc$libresoc.v:96349$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:95473.5-95473.29" + attribute \src "libresoc.v:96350.5-96350.29" switch \initial - attribute \src "libresoc.v:95473.9-95473.17" + attribute \src "libresoc.v:96350.9-96350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149653,18 +151951,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:95521.3-95569.6" - process $proc$libresoc.v:95521$3948 + attribute \src "libresoc.v:96398.3-96446.6" + process $proc$libresoc.v:96398$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:95522.5-95522.29" + attribute \src "libresoc.v:96399.5-96399.29" switch \initial - attribute \src "libresoc.v:95522.9-95522.17" + attribute \src "libresoc.v:96399.9-96399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149728,18 +152026,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:95570.3-95618.6" - process $proc$libresoc.v:95570$3949 + attribute \src "libresoc.v:96447.3-96495.6" + process $proc$libresoc.v:96447$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:95571.5-95571.29" + attribute \src "libresoc.v:96448.5-96448.29" switch \initial - attribute \src "libresoc.v:95571.9-95571.17" + attribute \src "libresoc.v:96448.9-96448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149803,18 +152101,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:95619.3-95667.6" - process $proc$libresoc.v:95619$3950 + attribute \src "libresoc.v:96496.3-96544.6" + process $proc$libresoc.v:96496$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:95620.5-95620.29" + attribute \src "libresoc.v:96497.5-96497.29" switch \initial - attribute \src "libresoc.v:95620.9-95620.17" + attribute \src "libresoc.v:96497.9-96497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149878,18 +152176,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:95668.3-95716.6" - process $proc$libresoc.v:95668$3951 + attribute \src "libresoc.v:96545.3-96593.6" + process $proc$libresoc.v:96545$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:95669.5-95669.29" + attribute \src "libresoc.v:96546.5-96546.29" switch \initial - attribute \src "libresoc.v:95669.9-95669.17" + attribute \src "libresoc.v:96546.9-96546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -149953,18 +152251,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:95717.3-95765.6" - process $proc$libresoc.v:95717$3952 + attribute \src "libresoc.v:96594.3-96642.6" + process $proc$libresoc.v:96594$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:95718.5-95718.29" + attribute \src "libresoc.v:96595.5-96595.29" switch \initial - attribute \src "libresoc.v:95718.9-95718.17" + attribute \src "libresoc.v:96595.9-96595.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -150028,18 +152326,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] end - attribute \src "libresoc.v:95766.3-95814.6" - process $proc$libresoc.v:95766$3953 + attribute \src "libresoc.v:96643.3-96691.6" + process $proc$libresoc.v:96643$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:95767.5-95767.29" + attribute \src "libresoc.v:96644.5-96644.29" switch \initial - attribute \src "libresoc.v:95767.9-95767.17" + attribute \src "libresoc.v:96644.9-96644.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -150103,18 +152401,18 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:95815.3-95863.6" - process $proc$libresoc.v:95815$3954 + attribute \src "libresoc.v:96692.3-96740.6" + process $proc$libresoc.v:96692$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:95816.5-95816.29" + attribute \src "libresoc.v:96693.5-96693.29" switch \initial - attribute \src "libresoc.v:95816.9-95816.17" + attribute \src "libresoc.v:96693.9-96693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -150151,7 +152449,7 @@ module \dec31_dec_sub23 attribute \src "libresoc.v:0.0-0.0" case 5'00111 assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 5'00110 assign { } { } @@ -150180,112 +152478,112 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:95869.1-96584.10" +attribute \src "libresoc.v:96746.1-97461.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:96222.3-96240.6" + attribute \src "libresoc.v:97099.3-97117.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96298.3-96316.6" + attribute \src "libresoc.v:97175.3-97193.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:96545.3-96563.6" + attribute \src "libresoc.v:97422.3-97440.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:96564.3-96582.6" + attribute \src "libresoc.v:97441.3-97459.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:96203.3-96221.6" + attribute \src "libresoc.v:97080.3-97098.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96279.3-96297.6" + attribute \src "libresoc.v:97156.3-97174.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:96450.3-96468.6" + attribute \src "libresoc.v:97327.3-97345.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:96127.3-96145.6" + attribute \src "libresoc.v:97004.3-97022.6" wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:96469.3-96487.6" + attribute \src "libresoc.v:97346.3-97364.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:96488.3-96506.6" + attribute \src "libresoc.v:97365.3-97383.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:96507.3-96525.6" + attribute \src "libresoc.v:97384.3-97402.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:96336.3-96354.6" + attribute \src "libresoc.v:97213.3-97231.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:96241.3-96259.6" + attribute \src "libresoc.v:97118.3-97136.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96260.3-96278.6" + attribute \src "libresoc.v:97137.3-97155.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:96374.3-96392.6" + attribute \src "libresoc.v:97251.3-97269.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:96146.3-96164.6" + attribute \src "libresoc.v:97023.3-97041.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:96412.3-96430.6" + attribute \src "libresoc.v:97289.3-97307.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:96526.3-96544.6" + attribute \src "libresoc.v:97403.3-97421.6" wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:96184.3-96202.6" + attribute \src "libresoc.v:97061.3-97079.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:96355.3-96373.6" + attribute \src "libresoc.v:97232.3-97250.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:96431.3-96449.6" + attribute \src "libresoc.v:97308.3-97326.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:96393.3-96411.6" + attribute \src "libresoc.v:97270.3-97288.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:96317.3-96335.6" + attribute \src "libresoc.v:97194.3-97212.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:96165.3-96183.6" + attribute \src "libresoc.v:97042.3-97060.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:95870.7-95870.20" + attribute \src "libresoc.v:96747.7-96747.20" wire $0\initial[0:0] - attribute \src "libresoc.v:96222.3-96240.6" + attribute \src "libresoc.v:97099.3-97117.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96298.3-96316.6" + attribute \src "libresoc.v:97175.3-97193.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:96545.3-96563.6" + attribute \src "libresoc.v:97422.3-97440.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:96564.3-96582.6" + attribute \src "libresoc.v:97441.3-97459.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:96203.3-96221.6" + attribute \src "libresoc.v:97080.3-97098.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96279.3-96297.6" + attribute \src "libresoc.v:97156.3-97174.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:96450.3-96468.6" + attribute \src "libresoc.v:97327.3-97345.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:96127.3-96145.6" + attribute \src "libresoc.v:97004.3-97022.6" wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:96469.3-96487.6" + attribute \src "libresoc.v:97346.3-97364.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:96488.3-96506.6" + attribute \src "libresoc.v:97365.3-97383.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:96507.3-96525.6" + attribute \src "libresoc.v:97384.3-97402.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:96336.3-96354.6" + attribute \src "libresoc.v:97213.3-97231.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:96241.3-96259.6" + attribute \src "libresoc.v:97118.3-97136.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96260.3-96278.6" + attribute \src "libresoc.v:97137.3-97155.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:96374.3-96392.6" + attribute \src "libresoc.v:97251.3-97269.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:96146.3-96164.6" + attribute \src "libresoc.v:97023.3-97041.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:96412.3-96430.6" + attribute \src "libresoc.v:97289.3-97307.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:96526.3-96544.6" + attribute \src "libresoc.v:97403.3-97421.6" wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:96184.3-96202.6" + attribute \src "libresoc.v:97061.3-97079.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:96355.3-96373.6" + attribute \src "libresoc.v:97232.3-97250.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:96431.3-96449.6" + attribute \src "libresoc.v:97308.3-97326.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:96393.3-96411.6" + attribute \src "libresoc.v:97270.3-97288.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:96317.3-96335.6" + attribute \src "libresoc.v:97194.3-97212.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:96165.3-96183.6" + attribute \src "libresoc.v:97042.3-97060.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub24_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -150295,7 +152593,7 @@ module \dec31_dec_sub24 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub24_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -150303,15 +152601,15 @@ module \dec31_dec_sub24 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub24_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub24_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -150343,7 +152641,7 @@ module \dec31_dec_sub24 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -150358,7 +152656,7 @@ module \dec31_dec_sub24 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub24_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -150366,7 +152664,7 @@ module \dec31_dec_sub24 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub24_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -150383,13 +152681,13 @@ module \dec31_dec_sub24 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub24_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub24_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -150465,13 +152763,13 @@ module \dec31_dec_sub24 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub24_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -150479,64 +152777,64 @@ module \dec31_dec_sub24 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub24_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub24_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub24_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "libresoc.v:95870.7-95870.15" + attribute \src "libresoc.v:96747.7-96747.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:95870.7-95870.20" - process $proc$libresoc.v:95870$3980 + attribute \src "libresoc.v:96747.7-96747.20" + process $proc$libresoc.v:96747$4061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:96127.3-96145.6" - process $proc$libresoc.v:96127$3956 + attribute \src "libresoc.v:97004.3-97022.6" + process $proc$libresoc.v:97004$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:96128.5-96128.29" + attribute \src "libresoc.v:97005.5-97005.29" switch \initial - attribute \src "libresoc.v:96128.9-96128.17" + attribute \src "libresoc.v:97005.9-97005.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150560,18 +152858,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] end - attribute \src "libresoc.v:96146.3-96164.6" - process $proc$libresoc.v:96146$3957 + attribute \src "libresoc.v:97023.3-97041.6" + process $proc$libresoc.v:97023$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:96147.5-96147.29" + attribute \src "libresoc.v:97024.5-97024.29" switch \initial - attribute \src "libresoc.v:96147.9-96147.17" + attribute \src "libresoc.v:97024.9-97024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150595,18 +152893,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:96165.3-96183.6" - process $proc$libresoc.v:96165$3958 + attribute \src "libresoc.v:97042.3-97060.6" + process $proc$libresoc.v:97042$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:96166.5-96166.29" + attribute \src "libresoc.v:97043.5-97043.29" switch \initial - attribute \src "libresoc.v:96166.9-96166.17" + attribute \src "libresoc.v:97043.9-97043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150630,18 +152928,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:96184.3-96202.6" - process $proc$libresoc.v:96184$3959 + attribute \src "libresoc.v:97061.3-97079.6" + process $proc$libresoc.v:97061$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:96185.5-96185.29" + attribute \src "libresoc.v:97062.5-97062.29" switch \initial - attribute \src "libresoc.v:96185.9-96185.17" + attribute \src "libresoc.v:97062.9-97062.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150665,18 +152963,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:96203.3-96221.6" - process $proc$libresoc.v:96203$3960 + attribute \src "libresoc.v:97080.3-97098.6" + process $proc$libresoc.v:97080$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:96204.5-96204.29" + attribute \src "libresoc.v:97081.5-97081.29" switch \initial - attribute \src "libresoc.v:96204.9-96204.17" + attribute \src "libresoc.v:97081.9-97081.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150700,18 +152998,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:96222.3-96240.6" - process $proc$libresoc.v:96222$3961 + attribute \src "libresoc.v:97099.3-97117.6" + process $proc$libresoc.v:97099$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:96223.5-96223.29" + attribute \src "libresoc.v:97100.5-97100.29" switch \initial - attribute \src "libresoc.v:96223.9-96223.17" + attribute \src "libresoc.v:97100.9-97100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150735,18 +153033,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:96241.3-96259.6" - process $proc$libresoc.v:96241$3962 + attribute \src "libresoc.v:97118.3-97136.6" + process $proc$libresoc.v:97118$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:96242.5-96242.29" + attribute \src "libresoc.v:97119.5-97119.29" switch \initial - attribute \src "libresoc.v:96242.9-96242.17" + attribute \src "libresoc.v:97119.9-97119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150770,18 +153068,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:96260.3-96278.6" - process $proc$libresoc.v:96260$3963 + attribute \src "libresoc.v:97137.3-97155.6" + process $proc$libresoc.v:97137$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:96261.5-96261.29" + attribute \src "libresoc.v:97138.5-97138.29" switch \initial - attribute \src "libresoc.v:96261.9-96261.17" + attribute \src "libresoc.v:97138.9-97138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150805,18 +153103,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:96279.3-96297.6" - process $proc$libresoc.v:96279$3964 + attribute \src "libresoc.v:97156.3-97174.6" + process $proc$libresoc.v:97156$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:96280.5-96280.29" + attribute \src "libresoc.v:97157.5-97157.29" switch \initial - attribute \src "libresoc.v:96280.9-96280.17" + attribute \src "libresoc.v:97157.9-97157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150840,18 +153138,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:96298.3-96316.6" - process $proc$libresoc.v:96298$3965 + attribute \src "libresoc.v:97175.3-97193.6" + process $proc$libresoc.v:97175$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:96299.5-96299.29" + attribute \src "libresoc.v:97176.5-97176.29" switch \initial - attribute \src "libresoc.v:96299.9-96299.17" + attribute \src "libresoc.v:97176.9-97176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150875,18 +153173,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:96317.3-96335.6" - process $proc$libresoc.v:96317$3966 + attribute \src "libresoc.v:97194.3-97212.6" + process $proc$libresoc.v:97194$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:96318.5-96318.29" + attribute \src "libresoc.v:97195.5-97195.29" switch \initial - attribute \src "libresoc.v:96318.9-96318.17" + attribute \src "libresoc.v:97195.9-97195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150910,18 +153208,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:96336.3-96354.6" - process $proc$libresoc.v:96336$3967 + attribute \src "libresoc.v:97213.3-97231.6" + process $proc$libresoc.v:97213$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:96337.5-96337.29" + attribute \src "libresoc.v:97214.5-97214.29" switch \initial - attribute \src "libresoc.v:96337.9-96337.17" + attribute \src "libresoc.v:97214.9-97214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150945,18 +153243,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:96355.3-96373.6" - process $proc$libresoc.v:96355$3968 + attribute \src "libresoc.v:97232.3-97250.6" + process $proc$libresoc.v:97232$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:96356.5-96356.29" + attribute \src "libresoc.v:97233.5-97233.29" switch \initial - attribute \src "libresoc.v:96356.9-96356.17" + attribute \src "libresoc.v:97233.9-97233.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -150980,18 +153278,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:96374.3-96392.6" - process $proc$libresoc.v:96374$3969 + attribute \src "libresoc.v:97251.3-97269.6" + process $proc$libresoc.v:97251$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:96375.5-96375.29" + attribute \src "libresoc.v:97252.5-97252.29" switch \initial - attribute \src "libresoc.v:96375.9-96375.17" + attribute \src "libresoc.v:97252.9-97252.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151015,18 +153313,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:96393.3-96411.6" - process $proc$libresoc.v:96393$3970 + attribute \src "libresoc.v:97270.3-97288.6" + process $proc$libresoc.v:97270$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:96394.5-96394.29" + attribute \src "libresoc.v:97271.5-97271.29" switch \initial - attribute \src "libresoc.v:96394.9-96394.17" + attribute \src "libresoc.v:97271.9-97271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151050,18 +153348,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:96412.3-96430.6" - process $proc$libresoc.v:96412$3971 + attribute \src "libresoc.v:97289.3-97307.6" + process $proc$libresoc.v:97289$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:96413.5-96413.29" + attribute \src "libresoc.v:97290.5-97290.29" switch \initial - attribute \src "libresoc.v:96413.9-96413.17" + attribute \src "libresoc.v:97290.9-97290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151085,18 +153383,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:96431.3-96449.6" - process $proc$libresoc.v:96431$3972 + attribute \src "libresoc.v:97308.3-97326.6" + process $proc$libresoc.v:97308$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:96432.5-96432.29" + attribute \src "libresoc.v:97309.5-97309.29" switch \initial - attribute \src "libresoc.v:96432.9-96432.17" + attribute \src "libresoc.v:97309.9-97309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151120,18 +153418,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:96450.3-96468.6" - process $proc$libresoc.v:96450$3973 + attribute \src "libresoc.v:97327.3-97345.6" + process $proc$libresoc.v:97327$4054 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:96451.5-96451.29" + attribute \src "libresoc.v:97328.5-97328.29" switch \initial - attribute \src "libresoc.v:96451.9-96451.17" + attribute \src "libresoc.v:97328.9-97328.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151155,18 +153453,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:96469.3-96487.6" - process $proc$libresoc.v:96469$3974 + attribute \src "libresoc.v:97346.3-97364.6" + process $proc$libresoc.v:97346$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:96470.5-96470.29" + attribute \src "libresoc.v:97347.5-97347.29" switch \initial - attribute \src "libresoc.v:96470.9-96470.17" + attribute \src "libresoc.v:97347.9-97347.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151190,18 +153488,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:96488.3-96506.6" - process $proc$libresoc.v:96488$3975 + attribute \src "libresoc.v:97365.3-97383.6" + process $proc$libresoc.v:97365$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:96489.5-96489.29" + attribute \src "libresoc.v:97366.5-97366.29" switch \initial - attribute \src "libresoc.v:96489.9-96489.17" + attribute \src "libresoc.v:97366.9-97366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151225,18 +153523,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:96507.3-96525.6" - process $proc$libresoc.v:96507$3976 + attribute \src "libresoc.v:97384.3-97402.6" + process $proc$libresoc.v:97384$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:96508.5-96508.29" + attribute \src "libresoc.v:97385.5-97385.29" switch \initial - attribute \src "libresoc.v:96508.9-96508.17" + attribute \src "libresoc.v:97385.9-97385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151260,18 +153558,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:96526.3-96544.6" - process $proc$libresoc.v:96526$3977 + attribute \src "libresoc.v:97403.3-97421.6" + process $proc$libresoc.v:97403$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:96527.5-96527.29" + attribute \src "libresoc.v:97404.5-97404.29" switch \initial - attribute \src "libresoc.v:96527.9-96527.17" + attribute \src "libresoc.v:97404.9-97404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151295,18 +153593,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] end - attribute \src "libresoc.v:96545.3-96563.6" - process $proc$libresoc.v:96545$3978 + attribute \src "libresoc.v:97422.3-97440.6" + process $proc$libresoc.v:97422$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:96546.5-96546.29" + attribute \src "libresoc.v:97423.5-97423.29" switch \initial - attribute \src "libresoc.v:96546.9-96546.17" + attribute \src "libresoc.v:97423.9-97423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151330,18 +153628,18 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:96564.3-96582.6" - process $proc$libresoc.v:96564$3979 + attribute \src "libresoc.v:97441.3-97459.6" + process $proc$libresoc.v:97441$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:96565.5-96565.29" + attribute \src "libresoc.v:97442.5-97442.29" switch \initial - attribute \src "libresoc.v:96565.9-96565.17" + attribute \src "libresoc.v:97442.9-97442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -151367,112 +153665,112 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:96588.1-98095.10" +attribute \src "libresoc.v:97465.1-98972.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:97106.3-97157.6" + attribute \src "libresoc.v:97983.3-98034.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:97314.3-97365.6" + attribute \src "libresoc.v:98191.3-98242.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:97990.3-98041.6" + attribute \src "libresoc.v:98867.3-98918.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98042.3-98093.6" + attribute \src "libresoc.v:98919.3-98970.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97054.3-97105.6" + attribute \src "libresoc.v:97931.3-97982.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97262.3-97313.6" + attribute \src "libresoc.v:98139.3-98190.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:97730.3-97781.6" + attribute \src "libresoc.v:98607.3-98658.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:96846.3-96897.6" + attribute \src "libresoc.v:97723.3-97774.6" wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:97782.3-97833.6" + attribute \src "libresoc.v:98659.3-98710.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:97834.3-97885.6" + attribute \src "libresoc.v:98711.3-98762.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:97886.3-97937.6" + attribute \src "libresoc.v:98763.3-98814.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:97418.3-97469.6" + attribute \src "libresoc.v:98295.3-98346.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:97158.3-97209.6" + attribute \src "libresoc.v:98035.3-98086.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97210.3-97261.6" + attribute \src "libresoc.v:98087.3-98138.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:97522.3-97573.6" + attribute \src "libresoc.v:98399.3-98450.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:96898.3-96949.6" + attribute \src "libresoc.v:97775.3-97826.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:97626.3-97677.6" + attribute \src "libresoc.v:98503.3-98554.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:97938.3-97989.6" + attribute \src "libresoc.v:98815.3-98866.6" wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97002.3-97053.6" + attribute \src "libresoc.v:97879.3-97930.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:97470.3-97521.6" + attribute \src "libresoc.v:98347.3-98398.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:97678.3-97729.6" + attribute \src "libresoc.v:98555.3-98606.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:97574.3-97625.6" + attribute \src "libresoc.v:98451.3-98502.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:97366.3-97417.6" + attribute \src "libresoc.v:98243.3-98294.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:96950.3-97001.6" + attribute \src "libresoc.v:97827.3-97878.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:96589.7-96589.20" + attribute \src "libresoc.v:97466.7-97466.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97106.3-97157.6" + attribute \src "libresoc.v:97983.3-98034.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:97314.3-97365.6" + attribute \src "libresoc.v:98191.3-98242.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:97990.3-98041.6" + attribute \src "libresoc.v:98867.3-98918.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98042.3-98093.6" + attribute \src "libresoc.v:98919.3-98970.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97054.3-97105.6" + attribute \src "libresoc.v:97931.3-97982.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97262.3-97313.6" + attribute \src "libresoc.v:98139.3-98190.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:97730.3-97781.6" + attribute \src "libresoc.v:98607.3-98658.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:96846.3-96897.6" + attribute \src "libresoc.v:97723.3-97774.6" wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:97782.3-97833.6" + attribute \src "libresoc.v:98659.3-98710.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:97834.3-97885.6" + attribute \src "libresoc.v:98711.3-98762.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:97886.3-97937.6" + attribute \src "libresoc.v:98763.3-98814.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:97418.3-97469.6" + attribute \src "libresoc.v:98295.3-98346.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:97158.3-97209.6" + attribute \src "libresoc.v:98035.3-98086.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97210.3-97261.6" + attribute \src "libresoc.v:98087.3-98138.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:97522.3-97573.6" + attribute \src "libresoc.v:98399.3-98450.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:96898.3-96949.6" + attribute \src "libresoc.v:97775.3-97826.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:97626.3-97677.6" + attribute \src "libresoc.v:98503.3-98554.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:97938.3-97989.6" + attribute \src "libresoc.v:98815.3-98866.6" wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97002.3-97053.6" + attribute \src "libresoc.v:97879.3-97930.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:97470.3-97521.6" + attribute \src "libresoc.v:98347.3-98398.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:97678.3-97729.6" + attribute \src "libresoc.v:98555.3-98606.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:97574.3-97625.6" + attribute \src "libresoc.v:98451.3-98502.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:97366.3-97417.6" + attribute \src "libresoc.v:98243.3-98294.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:96950.3-97001.6" + attribute \src "libresoc.v:97827.3-97878.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub26_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -151482,7 +153780,7 @@ module \dec31_dec_sub26 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub26_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -151490,15 +153788,15 @@ module \dec31_dec_sub26 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub26_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub26_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -151530,7 +153828,7 @@ module \dec31_dec_sub26 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -151545,7 +153843,7 @@ module \dec31_dec_sub26 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub26_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -151553,7 +153851,7 @@ module \dec31_dec_sub26 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub26_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -151570,13 +153868,13 @@ module \dec31_dec_sub26 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub26_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub26_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -151652,13 +153950,13 @@ module \dec31_dec_sub26 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub26_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -151666,64 +153964,64 @@ module \dec31_dec_sub26 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub26_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub26_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub26_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "libresoc.v:96589.7-96589.15" + attribute \src "libresoc.v:97466.7-97466.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:96589.7-96589.20" - process $proc$libresoc.v:96589$4005 + attribute \src "libresoc.v:97466.7-97466.20" + process $proc$libresoc.v:97466$4086 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:96846.3-96897.6" - process $proc$libresoc.v:96846$3981 + attribute \src "libresoc.v:97723.3-97774.6" + process $proc$libresoc.v:97723$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:96847.5-96847.29" + attribute \src "libresoc.v:97724.5-97724.29" switch \initial - attribute \src "libresoc.v:96847.9-96847.17" + attribute \src "libresoc.v:97724.9-97724.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -151791,18 +154089,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] end - attribute \src "libresoc.v:96898.3-96949.6" - process $proc$libresoc.v:96898$3982 + attribute \src "libresoc.v:97775.3-97826.6" + process $proc$libresoc.v:97775$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:96899.5-96899.29" + attribute \src "libresoc.v:97776.5-97776.29" switch \initial - attribute \src "libresoc.v:96899.9-96899.17" + attribute \src "libresoc.v:97776.9-97776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -151870,18 +154168,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:96950.3-97001.6" - process $proc$libresoc.v:96950$3983 + attribute \src "libresoc.v:97827.3-97878.6" + process $proc$libresoc.v:97827$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:96951.5-96951.29" + attribute \src "libresoc.v:97828.5-97828.29" switch \initial - attribute \src "libresoc.v:96951.9-96951.17" + attribute \src "libresoc.v:97828.9-97828.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -151949,18 +154247,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:97002.3-97053.6" - process $proc$libresoc.v:97002$3984 + attribute \src "libresoc.v:97879.3-97930.6" + process $proc$libresoc.v:97879$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:97003.5-97003.29" + attribute \src "libresoc.v:97880.5-97880.29" switch \initial - attribute \src "libresoc.v:97003.9-97003.17" + attribute \src "libresoc.v:97880.9-97880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152028,18 +154326,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:97054.3-97105.6" - process $proc$libresoc.v:97054$3985 + attribute \src "libresoc.v:97931.3-97982.6" + process $proc$libresoc.v:97931$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97055.5-97055.29" + attribute \src "libresoc.v:97932.5-97932.29" switch \initial - attribute \src "libresoc.v:97055.9-97055.17" + attribute \src "libresoc.v:97932.9-97932.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152107,18 +154405,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:97106.3-97157.6" - process $proc$libresoc.v:97106$3986 + attribute \src "libresoc.v:97983.3-98034.6" + process $proc$libresoc.v:97983$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:97107.5-97107.29" + attribute \src "libresoc.v:97984.5-97984.29" switch \initial - attribute \src "libresoc.v:97107.9-97107.17" + attribute \src "libresoc.v:97984.9-97984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152186,18 +154484,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:97158.3-97209.6" - process $proc$libresoc.v:97158$3987 + attribute \src "libresoc.v:98035.3-98086.6" + process $proc$libresoc.v:98035$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:97159.5-97159.29" + attribute \src "libresoc.v:98036.5-98036.29" switch \initial - attribute \src "libresoc.v:97159.9-97159.17" + attribute \src "libresoc.v:98036.9-98036.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152265,18 +154563,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:97210.3-97261.6" - process $proc$libresoc.v:97210$3988 + attribute \src "libresoc.v:98087.3-98138.6" + process $proc$libresoc.v:98087$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:97211.5-97211.29" + attribute \src "libresoc.v:98088.5-98088.29" switch \initial - attribute \src "libresoc.v:97211.9-97211.17" + attribute \src "libresoc.v:98088.9-98088.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152344,18 +154642,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:97262.3-97313.6" - process $proc$libresoc.v:97262$3989 + attribute \src "libresoc.v:98139.3-98190.6" + process $proc$libresoc.v:98139$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:97263.5-97263.29" + attribute \src "libresoc.v:98140.5-98140.29" switch \initial - attribute \src "libresoc.v:97263.9-97263.17" + attribute \src "libresoc.v:98140.9-98140.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152423,18 +154721,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:97314.3-97365.6" - process $proc$libresoc.v:97314$3990 + attribute \src "libresoc.v:98191.3-98242.6" + process $proc$libresoc.v:98191$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:97315.5-97315.29" + attribute \src "libresoc.v:98192.5-98192.29" switch \initial - attribute \src "libresoc.v:97315.9-97315.17" + attribute \src "libresoc.v:98192.9-98192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152502,18 +154800,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:97366.3-97417.6" - process $proc$libresoc.v:97366$3991 + attribute \src "libresoc.v:98243.3-98294.6" + process $proc$libresoc.v:98243$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:97367.5-97367.29" + attribute \src "libresoc.v:98244.5-98244.29" switch \initial - attribute \src "libresoc.v:97367.9-97367.17" + attribute \src "libresoc.v:98244.9-98244.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152581,18 +154879,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:97418.3-97469.6" - process $proc$libresoc.v:97418$3992 + attribute \src "libresoc.v:98295.3-98346.6" + process $proc$libresoc.v:98295$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:97419.5-97419.29" + attribute \src "libresoc.v:98296.5-98296.29" switch \initial - attribute \src "libresoc.v:97419.9-97419.17" + attribute \src "libresoc.v:98296.9-98296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152660,18 +154958,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:97470.3-97521.6" - process $proc$libresoc.v:97470$3993 + attribute \src "libresoc.v:98347.3-98398.6" + process $proc$libresoc.v:98347$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:97471.5-97471.29" + attribute \src "libresoc.v:98348.5-98348.29" switch \initial - attribute \src "libresoc.v:97471.9-97471.17" + attribute \src "libresoc.v:98348.9-98348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152739,18 +155037,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:97522.3-97573.6" - process $proc$libresoc.v:97522$3994 + attribute \src "libresoc.v:98399.3-98450.6" + process $proc$libresoc.v:98399$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:97523.5-97523.29" + attribute \src "libresoc.v:98400.5-98400.29" switch \initial - attribute \src "libresoc.v:97523.9-97523.17" + attribute \src "libresoc.v:98400.9-98400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152818,18 +155116,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:97574.3-97625.6" - process $proc$libresoc.v:97574$3995 + attribute \src "libresoc.v:98451.3-98502.6" + process $proc$libresoc.v:98451$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:97575.5-97575.29" + attribute \src "libresoc.v:98452.5-98452.29" switch \initial - attribute \src "libresoc.v:97575.9-97575.17" + attribute \src "libresoc.v:98452.9-98452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152897,18 +155195,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:97626.3-97677.6" - process $proc$libresoc.v:97626$3996 + attribute \src "libresoc.v:98503.3-98554.6" + process $proc$libresoc.v:98503$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:97627.5-97627.29" + attribute \src "libresoc.v:98504.5-98504.29" switch \initial - attribute \src "libresoc.v:97627.9-97627.17" + attribute \src "libresoc.v:98504.9-98504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -152976,18 +155274,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:97678.3-97729.6" - process $proc$libresoc.v:97678$3997 + attribute \src "libresoc.v:98555.3-98606.6" + process $proc$libresoc.v:98555$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:97679.5-97679.29" + attribute \src "libresoc.v:98556.5-98556.29" switch \initial - attribute \src "libresoc.v:97679.9-97679.17" + attribute \src "libresoc.v:98556.9-98556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153055,18 +155353,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:97730.3-97781.6" - process $proc$libresoc.v:97730$3998 + attribute \src "libresoc.v:98607.3-98658.6" + process $proc$libresoc.v:98607$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:97731.5-97731.29" + attribute \src "libresoc.v:98608.5-98608.29" switch \initial - attribute \src "libresoc.v:97731.9-97731.17" + attribute \src "libresoc.v:98608.9-98608.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153134,18 +155432,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:97782.3-97833.6" - process $proc$libresoc.v:97782$3999 + attribute \src "libresoc.v:98659.3-98710.6" + process $proc$libresoc.v:98659$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:97783.5-97783.29" + attribute \src "libresoc.v:98660.5-98660.29" switch \initial - attribute \src "libresoc.v:97783.9-97783.17" + attribute \src "libresoc.v:98660.9-98660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153213,18 +155511,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:97834.3-97885.6" - process $proc$libresoc.v:97834$4000 + attribute \src "libresoc.v:98711.3-98762.6" + process $proc$libresoc.v:98711$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:97835.5-97835.29" + attribute \src "libresoc.v:98712.5-98712.29" switch \initial - attribute \src "libresoc.v:97835.9-97835.17" + attribute \src "libresoc.v:98712.9-98712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153292,18 +155590,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:97886.3-97937.6" - process $proc$libresoc.v:97886$4001 + attribute \src "libresoc.v:98763.3-98814.6" + process $proc$libresoc.v:98763$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:97887.5-97887.29" + attribute \src "libresoc.v:98764.5-98764.29" switch \initial - attribute \src "libresoc.v:97887.9-97887.17" + attribute \src "libresoc.v:98764.9-98764.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153371,18 +155669,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:97938.3-97989.6" - process $proc$libresoc.v:97938$4002 + attribute \src "libresoc.v:98815.3-98866.6" + process $proc$libresoc.v:98815$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97939.5-97939.29" + attribute \src "libresoc.v:98816.5-98816.29" switch \initial - attribute \src "libresoc.v:97939.9-97939.17" + attribute \src "libresoc.v:98816.9-98816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153450,18 +155748,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] end - attribute \src "libresoc.v:97990.3-98041.6" - process $proc$libresoc.v:97990$4003 + attribute \src "libresoc.v:98867.3-98918.6" + process $proc$libresoc.v:98867$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:97991.5-97991.29" + attribute \src "libresoc.v:98868.5-98868.29" switch \initial - attribute \src "libresoc.v:97991.9-97991.17" + attribute \src "libresoc.v:98868.9-98868.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153529,18 +155827,18 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:98042.3-98093.6" - process $proc$libresoc.v:98042$4004 + attribute \src "libresoc.v:98919.3-98970.6" + process $proc$libresoc.v:98919$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:98043.5-98043.29" + attribute \src "libresoc.v:98920.5-98920.29" switch \initial - attribute \src "libresoc.v:98043.9-98043.17" + attribute \src "libresoc.v:98920.9-98920.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00001 @@ -153610,112 +155908,112 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98099.1-98814.10" +attribute \src "libresoc.v:98976.1-99691.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:98452.3-98470.6" + attribute \src "libresoc.v:99329.3-99347.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:98528.3-98546.6" + attribute \src "libresoc.v:99405.3-99423.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:98775.3-98793.6" + attribute \src "libresoc.v:99652.3-99670.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:98794.3-98812.6" + attribute \src "libresoc.v:99671.3-99689.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:98433.3-98451.6" + attribute \src "libresoc.v:99310.3-99328.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:98509.3-98527.6" + attribute \src "libresoc.v:99386.3-99404.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:98680.3-98698.6" + attribute \src "libresoc.v:99557.3-99575.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:98357.3-98375.6" + attribute \src "libresoc.v:99234.3-99252.6" wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:98699.3-98717.6" + attribute \src "libresoc.v:99576.3-99594.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:98718.3-98736.6" + attribute \src "libresoc.v:99595.3-99613.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:98737.3-98755.6" + attribute \src "libresoc.v:99614.3-99632.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:98566.3-98584.6" + attribute \src "libresoc.v:99443.3-99461.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:98471.3-98489.6" + attribute \src "libresoc.v:99348.3-99366.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:98490.3-98508.6" + attribute \src "libresoc.v:99367.3-99385.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:98604.3-98622.6" + attribute \src "libresoc.v:99481.3-99499.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:98376.3-98394.6" + attribute \src "libresoc.v:99253.3-99271.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:98642.3-98660.6" + attribute \src "libresoc.v:99519.3-99537.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:98756.3-98774.6" + attribute \src "libresoc.v:99633.3-99651.6" wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:98414.3-98432.6" + attribute \src "libresoc.v:99291.3-99309.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:98585.3-98603.6" + attribute \src "libresoc.v:99462.3-99480.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:98661.3-98679.6" + attribute \src "libresoc.v:99538.3-99556.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:98623.3-98641.6" + attribute \src "libresoc.v:99500.3-99518.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:98547.3-98565.6" + attribute \src "libresoc.v:99424.3-99442.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:98395.3-98413.6" + attribute \src "libresoc.v:99272.3-99290.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:98100.7-98100.20" + attribute \src "libresoc.v:98977.7-98977.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98452.3-98470.6" + attribute \src "libresoc.v:99329.3-99347.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:98528.3-98546.6" + attribute \src "libresoc.v:99405.3-99423.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:98775.3-98793.6" + attribute \src "libresoc.v:99652.3-99670.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:98794.3-98812.6" + attribute \src "libresoc.v:99671.3-99689.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:98433.3-98451.6" + attribute \src "libresoc.v:99310.3-99328.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:98509.3-98527.6" + attribute \src "libresoc.v:99386.3-99404.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:98680.3-98698.6" + attribute \src "libresoc.v:99557.3-99575.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:98357.3-98375.6" + attribute \src "libresoc.v:99234.3-99252.6" wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:98699.3-98717.6" + attribute \src "libresoc.v:99576.3-99594.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:98718.3-98736.6" + attribute \src "libresoc.v:99595.3-99613.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:98737.3-98755.6" + attribute \src "libresoc.v:99614.3-99632.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:98566.3-98584.6" + attribute \src "libresoc.v:99443.3-99461.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:98471.3-98489.6" + attribute \src "libresoc.v:99348.3-99366.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:98490.3-98508.6" + attribute \src "libresoc.v:99367.3-99385.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:98604.3-98622.6" + attribute \src "libresoc.v:99481.3-99499.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:98376.3-98394.6" + attribute \src "libresoc.v:99253.3-99271.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:98642.3-98660.6" + attribute \src "libresoc.v:99519.3-99537.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:98756.3-98774.6" + attribute \src "libresoc.v:99633.3-99651.6" wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:98414.3-98432.6" + attribute \src "libresoc.v:99291.3-99309.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:98585.3-98603.6" + attribute \src "libresoc.v:99462.3-99480.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:98661.3-98679.6" + attribute \src "libresoc.v:99538.3-99556.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:98623.3-98641.6" + attribute \src "libresoc.v:99500.3-99518.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:98547.3-98565.6" + attribute \src "libresoc.v:99424.3-99442.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:98395.3-98413.6" + attribute \src "libresoc.v:99272.3-99290.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub27_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -153725,7 +156023,7 @@ module \dec31_dec_sub27 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub27_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -153733,15 +156031,15 @@ module \dec31_dec_sub27 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub27_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub27_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -153773,7 +156071,7 @@ module \dec31_dec_sub27 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -153788,7 +156086,7 @@ module \dec31_dec_sub27 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub27_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -153796,7 +156094,7 @@ module \dec31_dec_sub27 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub27_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -153813,13 +156111,13 @@ module \dec31_dec_sub27 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub27_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub27_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -153895,13 +156193,13 @@ module \dec31_dec_sub27 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub27_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -153909,64 +156207,64 @@ module \dec31_dec_sub27 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub27_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub27_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub27_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "libresoc.v:98100.7-98100.15" + attribute \src "libresoc.v:98977.7-98977.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:98100.7-98100.20" - process $proc$libresoc.v:98100$4030 + attribute \src "libresoc.v:98977.7-98977.20" + process $proc$libresoc.v:98977$4111 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:98357.3-98375.6" - process $proc$libresoc.v:98357$4006 + attribute \src "libresoc.v:99234.3-99252.6" + process $proc$libresoc.v:99234$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:98358.5-98358.29" + attribute \src "libresoc.v:99235.5-99235.29" switch \initial - attribute \src "libresoc.v:98358.9-98358.17" + attribute \src "libresoc.v:99235.9-99235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -153990,18 +156288,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] end - attribute \src "libresoc.v:98376.3-98394.6" - process $proc$libresoc.v:98376$4007 + attribute \src "libresoc.v:99253.3-99271.6" + process $proc$libresoc.v:99253$4088 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:98377.5-98377.29" + attribute \src "libresoc.v:99254.5-99254.29" switch \initial - attribute \src "libresoc.v:98377.9-98377.17" + attribute \src "libresoc.v:99254.9-99254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154025,18 +156323,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:98395.3-98413.6" - process $proc$libresoc.v:98395$4008 + attribute \src "libresoc.v:99272.3-99290.6" + process $proc$libresoc.v:99272$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:98396.5-98396.29" + attribute \src "libresoc.v:99273.5-99273.29" switch \initial - attribute \src "libresoc.v:98396.9-98396.17" + attribute \src "libresoc.v:99273.9-99273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154060,18 +156358,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:98414.3-98432.6" - process $proc$libresoc.v:98414$4009 + attribute \src "libresoc.v:99291.3-99309.6" + process $proc$libresoc.v:99291$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:98415.5-98415.29" + attribute \src "libresoc.v:99292.5-99292.29" switch \initial - attribute \src "libresoc.v:98415.9-98415.17" + attribute \src "libresoc.v:99292.9-99292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154095,18 +156393,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:98433.3-98451.6" - process $proc$libresoc.v:98433$4010 + attribute \src "libresoc.v:99310.3-99328.6" + process $proc$libresoc.v:99310$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:98434.5-98434.29" + attribute \src "libresoc.v:99311.5-99311.29" switch \initial - attribute \src "libresoc.v:98434.9-98434.17" + attribute \src "libresoc.v:99311.9-99311.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154130,18 +156428,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:98452.3-98470.6" - process $proc$libresoc.v:98452$4011 + attribute \src "libresoc.v:99329.3-99347.6" + process $proc$libresoc.v:99329$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:98453.5-98453.29" + attribute \src "libresoc.v:99330.5-99330.29" switch \initial - attribute \src "libresoc.v:98453.9-98453.17" + attribute \src "libresoc.v:99330.9-99330.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154165,18 +156463,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:98471.3-98489.6" - process $proc$libresoc.v:98471$4012 + attribute \src "libresoc.v:99348.3-99366.6" + process $proc$libresoc.v:99348$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:98472.5-98472.29" + attribute \src "libresoc.v:99349.5-99349.29" switch \initial - attribute \src "libresoc.v:98472.9-98472.17" + attribute \src "libresoc.v:99349.9-99349.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154200,18 +156498,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:98490.3-98508.6" - process $proc$libresoc.v:98490$4013 + attribute \src "libresoc.v:99367.3-99385.6" + process $proc$libresoc.v:99367$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:98491.5-98491.29" + attribute \src "libresoc.v:99368.5-99368.29" switch \initial - attribute \src "libresoc.v:98491.9-98491.17" + attribute \src "libresoc.v:99368.9-99368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154235,18 +156533,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:98509.3-98527.6" - process $proc$libresoc.v:98509$4014 + attribute \src "libresoc.v:99386.3-99404.6" + process $proc$libresoc.v:99386$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:98510.5-98510.29" + attribute \src "libresoc.v:99387.5-99387.29" switch \initial - attribute \src "libresoc.v:98510.9-98510.17" + attribute \src "libresoc.v:99387.9-99387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154270,18 +156568,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:98528.3-98546.6" - process $proc$libresoc.v:98528$4015 + attribute \src "libresoc.v:99405.3-99423.6" + process $proc$libresoc.v:99405$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:98529.5-98529.29" + attribute \src "libresoc.v:99406.5-99406.29" switch \initial - attribute \src "libresoc.v:98529.9-98529.17" + attribute \src "libresoc.v:99406.9-99406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154305,18 +156603,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:98547.3-98565.6" - process $proc$libresoc.v:98547$4016 + attribute \src "libresoc.v:99424.3-99442.6" + process $proc$libresoc.v:99424$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:98548.5-98548.29" + attribute \src "libresoc.v:99425.5-99425.29" switch \initial - attribute \src "libresoc.v:98548.9-98548.17" + attribute \src "libresoc.v:99425.9-99425.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154340,18 +156638,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:98566.3-98584.6" - process $proc$libresoc.v:98566$4017 + attribute \src "libresoc.v:99443.3-99461.6" + process $proc$libresoc.v:99443$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:98567.5-98567.29" + attribute \src "libresoc.v:99444.5-99444.29" switch \initial - attribute \src "libresoc.v:98567.9-98567.17" + attribute \src "libresoc.v:99444.9-99444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154375,18 +156673,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:98585.3-98603.6" - process $proc$libresoc.v:98585$4018 + attribute \src "libresoc.v:99462.3-99480.6" + process $proc$libresoc.v:99462$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:98586.5-98586.29" + attribute \src "libresoc.v:99463.5-99463.29" switch \initial - attribute \src "libresoc.v:98586.9-98586.17" + attribute \src "libresoc.v:99463.9-99463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154410,18 +156708,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:98604.3-98622.6" - process $proc$libresoc.v:98604$4019 + attribute \src "libresoc.v:99481.3-99499.6" + process $proc$libresoc.v:99481$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:98605.5-98605.29" + attribute \src "libresoc.v:99482.5-99482.29" switch \initial - attribute \src "libresoc.v:98605.9-98605.17" + attribute \src "libresoc.v:99482.9-99482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154445,18 +156743,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:98623.3-98641.6" - process $proc$libresoc.v:98623$4020 + attribute \src "libresoc.v:99500.3-99518.6" + process $proc$libresoc.v:99500$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:98624.5-98624.29" + attribute \src "libresoc.v:99501.5-99501.29" switch \initial - attribute \src "libresoc.v:98624.9-98624.17" + attribute \src "libresoc.v:99501.9-99501.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154480,18 +156778,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:98642.3-98660.6" - process $proc$libresoc.v:98642$4021 + attribute \src "libresoc.v:99519.3-99537.6" + process $proc$libresoc.v:99519$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:98643.5-98643.29" + attribute \src "libresoc.v:99520.5-99520.29" switch \initial - attribute \src "libresoc.v:98643.9-98643.17" + attribute \src "libresoc.v:99520.9-99520.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154515,18 +156813,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:98661.3-98679.6" - process $proc$libresoc.v:98661$4022 + attribute \src "libresoc.v:99538.3-99556.6" + process $proc$libresoc.v:99538$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:98662.5-98662.29" + attribute \src "libresoc.v:99539.5-99539.29" switch \initial - attribute \src "libresoc.v:98662.9-98662.17" + attribute \src "libresoc.v:99539.9-99539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154550,18 +156848,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:98680.3-98698.6" - process $proc$libresoc.v:98680$4023 + attribute \src "libresoc.v:99557.3-99575.6" + process $proc$libresoc.v:99557$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:98681.5-98681.29" + attribute \src "libresoc.v:99558.5-99558.29" switch \initial - attribute \src "libresoc.v:98681.9-98681.17" + attribute \src "libresoc.v:99558.9-99558.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154585,18 +156883,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:98699.3-98717.6" - process $proc$libresoc.v:98699$4024 + attribute \src "libresoc.v:99576.3-99594.6" + process $proc$libresoc.v:99576$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:98700.5-98700.29" + attribute \src "libresoc.v:99577.5-99577.29" switch \initial - attribute \src "libresoc.v:98700.9-98700.17" + attribute \src "libresoc.v:99577.9-99577.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154620,18 +156918,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:98718.3-98736.6" - process $proc$libresoc.v:98718$4025 + attribute \src "libresoc.v:99595.3-99613.6" + process $proc$libresoc.v:99595$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:98719.5-98719.29" + attribute \src "libresoc.v:99596.5-99596.29" switch \initial - attribute \src "libresoc.v:98719.9-98719.17" + attribute \src "libresoc.v:99596.9-99596.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154655,18 +156953,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:98737.3-98755.6" - process $proc$libresoc.v:98737$4026 + attribute \src "libresoc.v:99614.3-99632.6" + process $proc$libresoc.v:99614$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:98738.5-98738.29" + attribute \src "libresoc.v:99615.5-99615.29" switch \initial - attribute \src "libresoc.v:98738.9-98738.17" + attribute \src "libresoc.v:99615.9-99615.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154690,18 +156988,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:98756.3-98774.6" - process $proc$libresoc.v:98756$4027 + attribute \src "libresoc.v:99633.3-99651.6" + process $proc$libresoc.v:99633$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:98757.5-98757.29" + attribute \src "libresoc.v:99634.5-99634.29" switch \initial - attribute \src "libresoc.v:98757.9-98757.17" + attribute \src "libresoc.v:99634.9-99634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154725,18 +157023,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] end - attribute \src "libresoc.v:98775.3-98793.6" - process $proc$libresoc.v:98775$4028 + attribute \src "libresoc.v:99652.3-99670.6" + process $proc$libresoc.v:99652$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:98776.5-98776.29" + attribute \src "libresoc.v:99653.5-99653.29" switch \initial - attribute \src "libresoc.v:98776.9-98776.17" + attribute \src "libresoc.v:99653.9-99653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154760,18 +157058,18 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:98794.3-98812.6" - process $proc$libresoc.v:98794$4029 + attribute \src "libresoc.v:99671.3-99689.6" + process $proc$libresoc.v:99671$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:98795.5-98795.29" + attribute \src "libresoc.v:99672.5-99672.29" switch \initial - attribute \src "libresoc.v:98795.9-98795.17" + attribute \src "libresoc.v:99672.9-99672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'11011 @@ -154797,112 +157095,112 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98818.1-99965.10" +attribute \src "libresoc.v:99695.1-100842.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:99261.3-99297.6" + attribute \src "libresoc.v:100138.3-100174.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:99409.3-99445.6" + attribute \src "libresoc.v:100286.3-100322.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:99890.3-99926.6" + attribute \src "libresoc.v:100767.3-100803.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:99927.3-99963.6" + attribute \src "libresoc.v:100804.3-100840.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:99224.3-99260.6" + attribute \src "libresoc.v:100101.3-100137.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:99372.3-99408.6" + attribute \src "libresoc.v:100249.3-100285.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:99705.3-99741.6" + attribute \src "libresoc.v:100582.3-100618.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99076.3-99112.6" + attribute \src "libresoc.v:99953.3-99989.6" wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:99742.3-99778.6" + attribute \src "libresoc.v:100619.3-100655.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:99779.3-99815.6" + attribute \src "libresoc.v:100656.3-100692.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:99816.3-99852.6" + attribute \src "libresoc.v:100693.3-100729.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:99483.3-99519.6" + attribute \src "libresoc.v:100360.3-100396.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:99298.3-99334.6" + attribute \src "libresoc.v:100175.3-100211.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:99335.3-99371.6" + attribute \src "libresoc.v:100212.3-100248.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:99557.3-99593.6" + attribute \src "libresoc.v:100434.3-100470.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99113.3-99149.6" + attribute \src "libresoc.v:99990.3-100026.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:99631.3-99667.6" + attribute \src "libresoc.v:100508.3-100544.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:99853.3-99889.6" + attribute \src "libresoc.v:100730.3-100766.6" wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:99187.3-99223.6" + attribute \src "libresoc.v:100064.3-100100.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:99520.3-99556.6" + attribute \src "libresoc.v:100397.3-100433.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:99668.3-99704.6" + attribute \src "libresoc.v:100545.3-100581.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:99594.3-99630.6" + attribute \src "libresoc.v:100471.3-100507.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:99446.3-99482.6" + attribute \src "libresoc.v:100323.3-100359.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:99150.3-99186.6" + attribute \src "libresoc.v:100027.3-100063.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:98819.7-98819.20" + attribute \src "libresoc.v:99696.7-99696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99261.3-99297.6" + attribute \src "libresoc.v:100138.3-100174.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:99409.3-99445.6" + attribute \src "libresoc.v:100286.3-100322.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:99890.3-99926.6" + attribute \src "libresoc.v:100767.3-100803.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:99927.3-99963.6" + attribute \src "libresoc.v:100804.3-100840.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:99224.3-99260.6" + attribute \src "libresoc.v:100101.3-100137.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:99372.3-99408.6" + attribute \src "libresoc.v:100249.3-100285.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:99705.3-99741.6" + attribute \src "libresoc.v:100582.3-100618.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99076.3-99112.6" + attribute \src "libresoc.v:99953.3-99989.6" wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:99742.3-99778.6" + attribute \src "libresoc.v:100619.3-100655.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:99779.3-99815.6" + attribute \src "libresoc.v:100656.3-100692.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:99816.3-99852.6" + attribute \src "libresoc.v:100693.3-100729.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:99483.3-99519.6" + attribute \src "libresoc.v:100360.3-100396.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:99298.3-99334.6" + attribute \src "libresoc.v:100175.3-100211.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:99335.3-99371.6" + attribute \src "libresoc.v:100212.3-100248.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:99557.3-99593.6" + attribute \src "libresoc.v:100434.3-100470.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99113.3-99149.6" + attribute \src "libresoc.v:99990.3-100026.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:99631.3-99667.6" + attribute \src "libresoc.v:100508.3-100544.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:99853.3-99889.6" + attribute \src "libresoc.v:100730.3-100766.6" wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:99187.3-99223.6" + attribute \src "libresoc.v:100064.3-100100.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:99520.3-99556.6" + attribute \src "libresoc.v:100397.3-100433.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:99668.3-99704.6" + attribute \src "libresoc.v:100545.3-100581.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:99594.3-99630.6" + attribute \src "libresoc.v:100471.3-100507.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:99446.3-99482.6" + attribute \src "libresoc.v:100323.3-100359.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:99150.3-99186.6" + attribute \src "libresoc.v:100027.3-100063.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub28_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -154912,7 +157210,7 @@ module \dec31_dec_sub28 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub28_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -154920,15 +157218,15 @@ module \dec31_dec_sub28 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub28_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub28_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -154960,7 +157258,7 @@ module \dec31_dec_sub28 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -154975,7 +157273,7 @@ module \dec31_dec_sub28 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub28_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -154983,7 +157281,7 @@ module \dec31_dec_sub28 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub28_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -155000,13 +157298,13 @@ module \dec31_dec_sub28 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub28_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub28_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -155082,13 +157380,13 @@ module \dec31_dec_sub28 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub28_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -155096,182 +157394,56 @@ module \dec31_dec_sub28 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub28_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub28_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub28_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "libresoc.v:98819.7-98819.15" + attribute \src "libresoc.v:99696.7-99696.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:98819.7-98819.20" - process $proc$libresoc.v:98819$4055 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99076.3-99112.6" - process $proc$libresoc.v:99076$4031 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:99077.5-99077.29" - switch \initial - attribute \src "libresoc.v:99077.9-99077.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] - end - attribute \src "libresoc.v:99113.3-99149.6" - process $proc$libresoc.v:99113$4032 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:99114.5-99114.29" - switch \initial - attribute \src "libresoc.v:99114.9-99114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] - end - attribute \src "libresoc.v:99150.3-99186.6" - process $proc$libresoc.v:99150$4033 + attribute \src "libresoc.v:100027.3-100063.6" + process $proc$libresoc.v:100027$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:99151.5-99151.29" + attribute \src "libresoc.v:100028.5-100028.29" switch \initial - attribute \src "libresoc.v:99151.9-99151.17" + attribute \src "libresoc.v:100028.9-100028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155319,18 +157491,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:99187.3-99223.6" - process $proc$libresoc.v:99187$4034 + attribute \src "libresoc.v:100064.3-100100.6" + process $proc$libresoc.v:100064$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:99188.5-99188.29" + attribute \src "libresoc.v:100065.5-100065.29" switch \initial - attribute \src "libresoc.v:99188.9-99188.17" + attribute \src "libresoc.v:100065.9-100065.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155378,18 +157550,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:99224.3-99260.6" - process $proc$libresoc.v:99224$4035 + attribute \src "libresoc.v:100101.3-100137.6" + process $proc$libresoc.v:100101$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:99225.5-99225.29" + attribute \src "libresoc.v:100102.5-100102.29" switch \initial - attribute \src "libresoc.v:99225.9-99225.17" + attribute \src "libresoc.v:100102.9-100102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155437,18 +157609,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:99261.3-99297.6" - process $proc$libresoc.v:99261$4036 + attribute \src "libresoc.v:100138.3-100174.6" + process $proc$libresoc.v:100138$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:99262.5-99262.29" + attribute \src "libresoc.v:100139.5-100139.29" switch \initial - attribute \src "libresoc.v:99262.9-99262.17" + attribute \src "libresoc.v:100139.9-100139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155496,18 +157668,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:99298.3-99334.6" - process $proc$libresoc.v:99298$4037 + attribute \src "libresoc.v:100175.3-100211.6" + process $proc$libresoc.v:100175$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:99299.5-99299.29" + attribute \src "libresoc.v:100176.5-100176.29" switch \initial - attribute \src "libresoc.v:99299.9-99299.17" + attribute \src "libresoc.v:100176.9-100176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155555,18 +157727,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:99335.3-99371.6" - process $proc$libresoc.v:99335$4038 + attribute \src "libresoc.v:100212.3-100248.6" + process $proc$libresoc.v:100212$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:99336.5-99336.29" + attribute \src "libresoc.v:100213.5-100213.29" switch \initial - attribute \src "libresoc.v:99336.9-99336.17" + attribute \src "libresoc.v:100213.9-100213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155614,18 +157786,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:99372.3-99408.6" - process $proc$libresoc.v:99372$4039 + attribute \src "libresoc.v:100249.3-100285.6" + process $proc$libresoc.v:100249$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:99373.5-99373.29" + attribute \src "libresoc.v:100250.5-100250.29" switch \initial - attribute \src "libresoc.v:99373.9-99373.17" + attribute \src "libresoc.v:100250.9-100250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155673,18 +157845,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:99409.3-99445.6" - process $proc$libresoc.v:99409$4040 + attribute \src "libresoc.v:100286.3-100322.6" + process $proc$libresoc.v:100286$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:99410.5-99410.29" + attribute \src "libresoc.v:100287.5-100287.29" switch \initial - attribute \src "libresoc.v:99410.9-99410.17" + attribute \src "libresoc.v:100287.9-100287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155732,18 +157904,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:99446.3-99482.6" - process $proc$libresoc.v:99446$4041 + attribute \src "libresoc.v:100323.3-100359.6" + process $proc$libresoc.v:100323$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:99447.5-99447.29" + attribute \src "libresoc.v:100324.5-100324.29" switch \initial - attribute \src "libresoc.v:99447.9-99447.17" + attribute \src "libresoc.v:100324.9-100324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155791,18 +157963,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:99483.3-99519.6" - process $proc$libresoc.v:99483$4042 + attribute \src "libresoc.v:100360.3-100396.6" + process $proc$libresoc.v:100360$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:99484.5-99484.29" + attribute \src "libresoc.v:100361.5-100361.29" switch \initial - attribute \src "libresoc.v:99484.9-99484.17" + attribute \src "libresoc.v:100361.9-100361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155850,18 +158022,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:99520.3-99556.6" - process $proc$libresoc.v:99520$4043 + attribute \src "libresoc.v:100397.3-100433.6" + process $proc$libresoc.v:100397$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:99521.5-99521.29" + attribute \src "libresoc.v:100398.5-100398.29" switch \initial - attribute \src "libresoc.v:99521.9-99521.17" + attribute \src "libresoc.v:100398.9-100398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155909,18 +158081,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:99557.3-99593.6" - process $proc$libresoc.v:99557$4044 + attribute \src "libresoc.v:100434.3-100470.6" + process $proc$libresoc.v:100434$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99558.5-99558.29" + attribute \src "libresoc.v:100435.5-100435.29" switch \initial - attribute \src "libresoc.v:99558.9-99558.17" + attribute \src "libresoc.v:100435.9-100435.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -155968,18 +158140,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:99594.3-99630.6" - process $proc$libresoc.v:99594$4045 + attribute \src "libresoc.v:100471.3-100507.6" + process $proc$libresoc.v:100471$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:99595.5-99595.29" + attribute \src "libresoc.v:100472.5-100472.29" switch \initial - attribute \src "libresoc.v:99595.9-99595.17" + attribute \src "libresoc.v:100472.9-100472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156027,18 +158199,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:99631.3-99667.6" - process $proc$libresoc.v:99631$4046 + attribute \src "libresoc.v:100508.3-100544.6" + process $proc$libresoc.v:100508$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:99632.5-99632.29" + attribute \src "libresoc.v:100509.5-100509.29" switch \initial - attribute \src "libresoc.v:99632.9-99632.17" + attribute \src "libresoc.v:100509.9-100509.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156086,18 +158258,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:99668.3-99704.6" - process $proc$libresoc.v:99668$4047 + attribute \src "libresoc.v:100545.3-100581.6" + process $proc$libresoc.v:100545$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:99669.5-99669.29" + attribute \src "libresoc.v:100546.5-100546.29" switch \initial - attribute \src "libresoc.v:99669.9-99669.17" + attribute \src "libresoc.v:100546.9-100546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156145,18 +158317,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:99705.3-99741.6" - process $proc$libresoc.v:99705$4048 + attribute \src "libresoc.v:100582.3-100618.6" + process $proc$libresoc.v:100582$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99706.5-99706.29" + attribute \src "libresoc.v:100583.5-100583.29" switch \initial - attribute \src "libresoc.v:99706.9-99706.17" + attribute \src "libresoc.v:100583.9-100583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156204,18 +158376,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:99742.3-99778.6" - process $proc$libresoc.v:99742$4049 + attribute \src "libresoc.v:100619.3-100655.6" + process $proc$libresoc.v:100619$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:99743.5-99743.29" + attribute \src "libresoc.v:100620.5-100620.29" switch \initial - attribute \src "libresoc.v:99743.9-99743.17" + attribute \src "libresoc.v:100620.9-100620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156263,18 +158435,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:99779.3-99815.6" - process $proc$libresoc.v:99779$4050 + attribute \src "libresoc.v:100656.3-100692.6" + process $proc$libresoc.v:100656$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:99780.5-99780.29" + attribute \src "libresoc.v:100657.5-100657.29" switch \initial - attribute \src "libresoc.v:99780.9-99780.17" + attribute \src "libresoc.v:100657.9-100657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156322,18 +158494,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:99816.3-99852.6" - process $proc$libresoc.v:99816$4051 + attribute \src "libresoc.v:100693.3-100729.6" + process $proc$libresoc.v:100693$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:99817.5-99817.29" + attribute \src "libresoc.v:100694.5-100694.29" switch \initial - attribute \src "libresoc.v:99817.9-99817.17" + attribute \src "libresoc.v:100694.9-100694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156381,18 +158553,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:99853.3-99889.6" - process $proc$libresoc.v:99853$4052 + attribute \src "libresoc.v:100730.3-100766.6" + process $proc$libresoc.v:100730$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:99854.5-99854.29" + attribute \src "libresoc.v:100731.5-100731.29" switch \initial - attribute \src "libresoc.v:99854.9-99854.17" + attribute \src "libresoc.v:100731.9-100731.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156440,18 +158612,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] end - attribute \src "libresoc.v:99890.3-99926.6" - process $proc$libresoc.v:99890$4053 + attribute \src "libresoc.v:100767.3-100803.6" + process $proc$libresoc.v:100767$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:99891.5-99891.29" + attribute \src "libresoc.v:100768.5-100768.29" switch \initial - attribute \src "libresoc.v:99891.9-99891.17" + attribute \src "libresoc.v:100768.9-100768.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156499,18 +158671,18 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:99927.3-99963.6" - process $proc$libresoc.v:99927$4054 + attribute \src "libresoc.v:100804.3-100840.6" + process $proc$libresoc.v:100804$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:99928.5-99928.29" + attribute \src "libresoc.v:100805.5-100805.29" switch \initial - attribute \src "libresoc.v:99928.9-99928.17" + attribute \src "libresoc.v:100805.9-100805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00000 @@ -156558,114 +158730,240 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end + attribute \src "libresoc.v:99696.7-99696.20" + process $proc$libresoc.v:99696$4136 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99953.3-99989.6" + process $proc$libresoc.v:99953$4112 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:99954.5-99954.29" + switch \initial + attribute \src "libresoc.v:99954.9-99954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:99990.3-100026.6" + process $proc$libresoc.v:99990$4113 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:99991.5-99991.29" + switch \initial + attribute \src "libresoc.v:99991.9-99991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99969.1-100540.10" +attribute \src "libresoc.v:100846.1-101417.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:100292.3-100304.6" + attribute \src "libresoc.v:101169.3-101181.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:100344.3-100356.6" + attribute \src "libresoc.v:101221.3-101233.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:100513.3-100525.6" + attribute \src "libresoc.v:101390.3-101402.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:100526.3-100538.6" + attribute \src "libresoc.v:101403.3-101415.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:100279.3-100291.6" + attribute \src "libresoc.v:101156.3-101168.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:100331.3-100343.6" + attribute \src "libresoc.v:101208.3-101220.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:100448.3-100460.6" + attribute \src "libresoc.v:101325.3-101337.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:100227.3-100239.6" + attribute \src "libresoc.v:101104.3-101116.6" wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:100461.3-100473.6" + attribute \src "libresoc.v:101338.3-101350.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:100474.3-100486.6" + attribute \src "libresoc.v:101351.3-101363.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:100487.3-100499.6" + attribute \src "libresoc.v:101364.3-101376.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:100370.3-100382.6" + attribute \src "libresoc.v:101247.3-101259.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:100305.3-100317.6" + attribute \src "libresoc.v:101182.3-101194.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:100318.3-100330.6" + attribute \src "libresoc.v:101195.3-101207.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:100396.3-100408.6" + attribute \src "libresoc.v:101273.3-101285.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:100240.3-100252.6" + attribute \src "libresoc.v:101117.3-101129.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:100422.3-100434.6" + attribute \src "libresoc.v:101299.3-101311.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:100500.3-100512.6" + attribute \src "libresoc.v:101377.3-101389.6" wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:100266.3-100278.6" + attribute \src "libresoc.v:101143.3-101155.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:100383.3-100395.6" + attribute \src "libresoc.v:101260.3-101272.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:100435.3-100447.6" + attribute \src "libresoc.v:101312.3-101324.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:100409.3-100421.6" + attribute \src "libresoc.v:101286.3-101298.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:100357.3-100369.6" + attribute \src "libresoc.v:101234.3-101246.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:100253.3-100265.6" + attribute \src "libresoc.v:101130.3-101142.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:99970.7-99970.20" + attribute \src "libresoc.v:100847.7-100847.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100292.3-100304.6" + attribute \src "libresoc.v:101169.3-101181.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:100344.3-100356.6" + attribute \src "libresoc.v:101221.3-101233.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:100513.3-100525.6" + attribute \src "libresoc.v:101390.3-101402.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:100526.3-100538.6" + attribute \src "libresoc.v:101403.3-101415.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:100279.3-100291.6" + attribute \src "libresoc.v:101156.3-101168.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:100331.3-100343.6" + attribute \src "libresoc.v:101208.3-101220.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:100448.3-100460.6" + attribute \src "libresoc.v:101325.3-101337.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:100227.3-100239.6" + attribute \src "libresoc.v:101104.3-101116.6" wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:100461.3-100473.6" + attribute \src "libresoc.v:101338.3-101350.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:100474.3-100486.6" + attribute \src "libresoc.v:101351.3-101363.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:100487.3-100499.6" + attribute \src "libresoc.v:101364.3-101376.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:100370.3-100382.6" + attribute \src "libresoc.v:101247.3-101259.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:100305.3-100317.6" + attribute \src "libresoc.v:101182.3-101194.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:100318.3-100330.6" + attribute \src "libresoc.v:101195.3-101207.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:100396.3-100408.6" + attribute \src "libresoc.v:101273.3-101285.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:100240.3-100252.6" + attribute \src "libresoc.v:101117.3-101129.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:100422.3-100434.6" + attribute \src "libresoc.v:101299.3-101311.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:100500.3-100512.6" + attribute \src "libresoc.v:101377.3-101389.6" wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:100266.3-100278.6" + attribute \src "libresoc.v:101143.3-101155.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:100383.3-100395.6" + attribute \src "libresoc.v:101260.3-101272.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:100435.3-100447.6" + attribute \src "libresoc.v:101312.3-101324.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:100409.3-100421.6" + attribute \src "libresoc.v:101286.3-101298.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:100357.3-100369.6" + attribute \src "libresoc.v:101234.3-101246.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:100253.3-100265.6" + attribute \src "libresoc.v:101130.3-101142.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub4_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -156675,7 +158973,7 @@ module \dec31_dec_sub4 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub4_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -156683,15 +158981,15 @@ module \dec31_dec_sub4 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub4_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub4_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -156723,7 +159021,7 @@ module \dec31_dec_sub4 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -156738,7 +159036,7 @@ module \dec31_dec_sub4 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub4_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -156746,7 +159044,7 @@ module \dec31_dec_sub4 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub4_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -156763,13 +159061,13 @@ module \dec31_dec_sub4 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub4_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -156845,13 +159143,13 @@ module \dec31_dec_sub4 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub4_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -156859,56 +159157,64 @@ module \dec31_dec_sub4 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub4_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub4_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub4_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "libresoc.v:99970.7-99970.15" + attribute \src "libresoc.v:100847.7-100847.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:100227.3-100239.6" - process $proc$libresoc.v:100227$4056 + attribute \src "libresoc.v:100847.7-100847.20" + process $proc$libresoc.v:100847$4161 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101104.3-101116.6" + process $proc$libresoc.v:101104$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:100228.5-100228.29" + attribute \src "libresoc.v:101105.5-101105.29" switch \initial - attribute \src "libresoc.v:100228.9-100228.17" + attribute \src "libresoc.v:101105.9-101105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -156924,18 +159230,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] end - attribute \src "libresoc.v:100240.3-100252.6" - process $proc$libresoc.v:100240$4057 + attribute \src "libresoc.v:101117.3-101129.6" + process $proc$libresoc.v:101117$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:100241.5-100241.29" + attribute \src "libresoc.v:101118.5-101118.29" switch \initial - attribute \src "libresoc.v:100241.9-100241.17" + attribute \src "libresoc.v:101118.9-101118.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -156951,18 +159257,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:100253.3-100265.6" - process $proc$libresoc.v:100253$4058 + attribute \src "libresoc.v:101130.3-101142.6" + process $proc$libresoc.v:101130$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:100254.5-100254.29" + attribute \src "libresoc.v:101131.5-101131.29" switch \initial - attribute \src "libresoc.v:100254.9-100254.17" + attribute \src "libresoc.v:101131.9-101131.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -156978,18 +159284,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:100266.3-100278.6" - process $proc$libresoc.v:100266$4059 + attribute \src "libresoc.v:101143.3-101155.6" + process $proc$libresoc.v:101143$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:100267.5-100267.29" + attribute \src "libresoc.v:101144.5-101144.29" switch \initial - attribute \src "libresoc.v:100267.9-100267.17" + attribute \src "libresoc.v:101144.9-101144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157005,18 +159311,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:100279.3-100291.6" - process $proc$libresoc.v:100279$4060 + attribute \src "libresoc.v:101156.3-101168.6" + process $proc$libresoc.v:101156$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:100280.5-100280.29" + attribute \src "libresoc.v:101157.5-101157.29" switch \initial - attribute \src "libresoc.v:100280.9-100280.17" + attribute \src "libresoc.v:101157.9-101157.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157032,18 +159338,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:100292.3-100304.6" - process $proc$libresoc.v:100292$4061 + attribute \src "libresoc.v:101169.3-101181.6" + process $proc$libresoc.v:101169$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:100293.5-100293.29" + attribute \src "libresoc.v:101170.5-101170.29" switch \initial - attribute \src "libresoc.v:100293.9-100293.17" + attribute \src "libresoc.v:101170.9-101170.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157059,18 +159365,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:100305.3-100317.6" - process $proc$libresoc.v:100305$4062 + attribute \src "libresoc.v:101182.3-101194.6" + process $proc$libresoc.v:101182$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:100306.5-100306.29" + attribute \src "libresoc.v:101183.5-101183.29" switch \initial - attribute \src "libresoc.v:100306.9-100306.17" + attribute \src "libresoc.v:101183.9-101183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157086,18 +159392,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:100318.3-100330.6" - process $proc$libresoc.v:100318$4063 + attribute \src "libresoc.v:101195.3-101207.6" + process $proc$libresoc.v:101195$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:100319.5-100319.29" + attribute \src "libresoc.v:101196.5-101196.29" switch \initial - attribute \src "libresoc.v:100319.9-100319.17" + attribute \src "libresoc.v:101196.9-101196.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157113,18 +159419,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:100331.3-100343.6" - process $proc$libresoc.v:100331$4064 + attribute \src "libresoc.v:101208.3-101220.6" + process $proc$libresoc.v:101208$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:100332.5-100332.29" + attribute \src "libresoc.v:101209.5-101209.29" switch \initial - attribute \src "libresoc.v:100332.9-100332.17" + attribute \src "libresoc.v:101209.9-101209.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157140,18 +159446,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:100344.3-100356.6" - process $proc$libresoc.v:100344$4065 + attribute \src "libresoc.v:101221.3-101233.6" + process $proc$libresoc.v:101221$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:100345.5-100345.29" + attribute \src "libresoc.v:101222.5-101222.29" switch \initial - attribute \src "libresoc.v:100345.9-100345.17" + attribute \src "libresoc.v:101222.9-101222.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157167,18 +159473,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:100357.3-100369.6" - process $proc$libresoc.v:100357$4066 + attribute \src "libresoc.v:101234.3-101246.6" + process $proc$libresoc.v:101234$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:100358.5-100358.29" + attribute \src "libresoc.v:101235.5-101235.29" switch \initial - attribute \src "libresoc.v:100358.9-100358.17" + attribute \src "libresoc.v:101235.9-101235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157194,18 +159500,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:100370.3-100382.6" - process $proc$libresoc.v:100370$4067 + attribute \src "libresoc.v:101247.3-101259.6" + process $proc$libresoc.v:101247$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:100371.5-100371.29" + attribute \src "libresoc.v:101248.5-101248.29" switch \initial - attribute \src "libresoc.v:100371.9-100371.17" + attribute \src "libresoc.v:101248.9-101248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157221,18 +159527,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:100383.3-100395.6" - process $proc$libresoc.v:100383$4068 + attribute \src "libresoc.v:101260.3-101272.6" + process $proc$libresoc.v:101260$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:100384.5-100384.29" + attribute \src "libresoc.v:101261.5-101261.29" switch \initial - attribute \src "libresoc.v:100384.9-100384.17" + attribute \src "libresoc.v:101261.9-101261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157248,18 +159554,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:100396.3-100408.6" - process $proc$libresoc.v:100396$4069 + attribute \src "libresoc.v:101273.3-101285.6" + process $proc$libresoc.v:101273$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:100397.5-100397.29" + attribute \src "libresoc.v:101274.5-101274.29" switch \initial - attribute \src "libresoc.v:100397.9-100397.17" + attribute \src "libresoc.v:101274.9-101274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157275,18 +159581,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:100409.3-100421.6" - process $proc$libresoc.v:100409$4070 + attribute \src "libresoc.v:101286.3-101298.6" + process $proc$libresoc.v:101286$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:100410.5-100410.29" + attribute \src "libresoc.v:101287.5-101287.29" switch \initial - attribute \src "libresoc.v:100410.9-100410.17" + attribute \src "libresoc.v:101287.9-101287.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157302,18 +159608,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:100422.3-100434.6" - process $proc$libresoc.v:100422$4071 + attribute \src "libresoc.v:101299.3-101311.6" + process $proc$libresoc.v:101299$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:100423.5-100423.29" + attribute \src "libresoc.v:101300.5-101300.29" switch \initial - attribute \src "libresoc.v:100423.9-100423.17" + attribute \src "libresoc.v:101300.9-101300.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157329,18 +159635,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:100435.3-100447.6" - process $proc$libresoc.v:100435$4072 + attribute \src "libresoc.v:101312.3-101324.6" + process $proc$libresoc.v:101312$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:100436.5-100436.29" + attribute \src "libresoc.v:101313.5-101313.29" switch \initial - attribute \src "libresoc.v:100436.9-100436.17" + attribute \src "libresoc.v:101313.9-101313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157356,18 +159662,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:100448.3-100460.6" - process $proc$libresoc.v:100448$4073 + attribute \src "libresoc.v:101325.3-101337.6" + process $proc$libresoc.v:101325$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:100449.5-100449.29" + attribute \src "libresoc.v:101326.5-101326.29" switch \initial - attribute \src "libresoc.v:100449.9-100449.17" + attribute \src "libresoc.v:101326.9-101326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157383,18 +159689,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:100461.3-100473.6" - process $proc$libresoc.v:100461$4074 + attribute \src "libresoc.v:101338.3-101350.6" + process $proc$libresoc.v:101338$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:100462.5-100462.29" + attribute \src "libresoc.v:101339.5-101339.29" switch \initial - attribute \src "libresoc.v:100462.9-100462.17" + attribute \src "libresoc.v:101339.9-101339.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157410,18 +159716,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:100474.3-100486.6" - process $proc$libresoc.v:100474$4075 + attribute \src "libresoc.v:101351.3-101363.6" + process $proc$libresoc.v:101351$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:100475.5-100475.29" + attribute \src "libresoc.v:101352.5-101352.29" switch \initial - attribute \src "libresoc.v:100475.9-100475.17" + attribute \src "libresoc.v:101352.9-101352.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157437,18 +159743,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:100487.3-100499.6" - process $proc$libresoc.v:100487$4076 + attribute \src "libresoc.v:101364.3-101376.6" + process $proc$libresoc.v:101364$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:100488.5-100488.29" + attribute \src "libresoc.v:101365.5-101365.29" switch \initial - attribute \src "libresoc.v:100488.9-100488.17" + attribute \src "libresoc.v:101365.9-101365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157464,18 +159770,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:100500.3-100512.6" - process $proc$libresoc.v:100500$4077 + attribute \src "libresoc.v:101377.3-101389.6" + process $proc$libresoc.v:101377$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:100501.5-100501.29" + attribute \src "libresoc.v:101378.5-101378.29" switch \initial - attribute \src "libresoc.v:100501.9-100501.17" + attribute \src "libresoc.v:101378.9-101378.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157491,18 +159797,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] end - attribute \src "libresoc.v:100513.3-100525.6" - process $proc$libresoc.v:100513$4078 + attribute \src "libresoc.v:101390.3-101402.6" + process $proc$libresoc.v:101390$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:100514.5-100514.29" + attribute \src "libresoc.v:101391.5-101391.29" switch \initial - attribute \src "libresoc.v:100514.9-100514.17" + attribute \src "libresoc.v:101391.9-101391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157518,18 +159824,18 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:100526.3-100538.6" - process $proc$libresoc.v:100526$4079 + attribute \src "libresoc.v:101403.3-101415.6" + process $proc$libresoc.v:101403$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:100527.5-100527.29" + attribute \src "libresoc.v:101404.5-101404.29" switch \initial - attribute \src "libresoc.v:100527.9-100527.17" + attribute \src "libresoc.v:101404.9-101404.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00010 @@ -157545,122 +159851,114 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:99970.7-99970.20" - process $proc$libresoc.v:99970$4080 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100544.1-101835.10" +attribute \src "libresoc.v:101421.1-102712.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:101017.3-101059.6" + attribute \src "libresoc.v:101894.3-101936.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101189.3-101231.6" + attribute \src "libresoc.v:102066.3-102108.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:101748.3-101790.6" + attribute \src "libresoc.v:102625.3-102667.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:101791.3-101833.6" + attribute \src "libresoc.v:102668.3-102710.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:100974.3-101016.6" + attribute \src "libresoc.v:101851.3-101893.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101146.3-101188.6" + attribute \src "libresoc.v:102023.3-102065.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:101533.3-101575.6" + attribute \src "libresoc.v:102410.3-102452.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:100802.3-100844.6" + attribute \src "libresoc.v:101679.3-101721.6" wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:101576.3-101618.6" + attribute \src "libresoc.v:102453.3-102495.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:101619.3-101661.6" + attribute \src "libresoc.v:102496.3-102538.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:101662.3-101704.6" + attribute \src "libresoc.v:102539.3-102581.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:101275.3-101317.6" + attribute \src "libresoc.v:102152.3-102194.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101060.3-101102.6" + attribute \src "libresoc.v:101937.3-101979.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101103.3-101145.6" + attribute \src "libresoc.v:101980.3-102022.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:101361.3-101403.6" + attribute \src "libresoc.v:102238.3-102280.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:100845.3-100887.6" + attribute \src "libresoc.v:101722.3-101764.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:101447.3-101489.6" + attribute \src "libresoc.v:102324.3-102366.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:101705.3-101747.6" + attribute \src "libresoc.v:102582.3-102624.6" wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:100931.3-100973.6" + attribute \src "libresoc.v:101808.3-101850.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:101318.3-101360.6" + attribute \src "libresoc.v:102195.3-102237.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:101490.3-101532.6" + attribute \src "libresoc.v:102367.3-102409.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:101404.3-101446.6" + attribute \src "libresoc.v:102281.3-102323.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:101232.3-101274.6" + attribute \src "libresoc.v:102109.3-102151.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:100888.3-100930.6" + attribute \src "libresoc.v:101765.3-101807.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:100545.7-100545.20" + attribute \src "libresoc.v:101422.7-101422.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101017.3-101059.6" + attribute \src "libresoc.v:101894.3-101936.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101189.3-101231.6" + attribute \src "libresoc.v:102066.3-102108.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:101748.3-101790.6" + attribute \src "libresoc.v:102625.3-102667.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:101791.3-101833.6" + attribute \src "libresoc.v:102668.3-102710.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:100974.3-101016.6" + attribute \src "libresoc.v:101851.3-101893.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101146.3-101188.6" + attribute \src "libresoc.v:102023.3-102065.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:101533.3-101575.6" + attribute \src "libresoc.v:102410.3-102452.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:100802.3-100844.6" + attribute \src "libresoc.v:101679.3-101721.6" wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:101576.3-101618.6" + attribute \src "libresoc.v:102453.3-102495.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:101619.3-101661.6" + attribute \src "libresoc.v:102496.3-102538.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:101662.3-101704.6" + attribute \src "libresoc.v:102539.3-102581.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:101275.3-101317.6" + attribute \src "libresoc.v:102152.3-102194.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101060.3-101102.6" + attribute \src "libresoc.v:101937.3-101979.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101103.3-101145.6" + attribute \src "libresoc.v:101980.3-102022.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:101361.3-101403.6" + attribute \src "libresoc.v:102238.3-102280.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:100845.3-100887.6" + attribute \src "libresoc.v:101722.3-101764.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:101447.3-101489.6" + attribute \src "libresoc.v:102324.3-102366.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:101705.3-101747.6" + attribute \src "libresoc.v:102582.3-102624.6" wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:100931.3-100973.6" + attribute \src "libresoc.v:101808.3-101850.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:101318.3-101360.6" + attribute \src "libresoc.v:102195.3-102237.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:101490.3-101532.6" + attribute \src "libresoc.v:102367.3-102409.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:101404.3-101446.6" + attribute \src "libresoc.v:102281.3-102323.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:101232.3-101274.6" + attribute \src "libresoc.v:102109.3-102151.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:100888.3-100930.6" + attribute \src "libresoc.v:101765.3-101807.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub8_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -157670,7 +159968,7 @@ module \dec31_dec_sub8 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub8_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -157678,15 +159976,15 @@ module \dec31_dec_sub8 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub8_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -157718,7 +160016,7 @@ module \dec31_dec_sub8 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -157733,7 +160031,7 @@ module \dec31_dec_sub8 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub8_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -157741,7 +160039,7 @@ module \dec31_dec_sub8 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub8_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -157758,13 +160056,13 @@ module \dec31_dec_sub8 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub8_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -157840,13 +160138,13 @@ module \dec31_dec_sub8 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub8_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -157854,64 +160152,64 @@ module \dec31_dec_sub8 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub8_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub8_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub8_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "libresoc.v:100545.7-100545.15" + attribute \src "libresoc.v:101422.7-101422.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:100545.7-100545.20" - process $proc$libresoc.v:100545$4105 + attribute \src "libresoc.v:101422.7-101422.20" + process $proc$libresoc.v:101422$4186 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:100802.3-100844.6" - process $proc$libresoc.v:100802$4081 + attribute \src "libresoc.v:101679.3-101721.6" + process $proc$libresoc.v:101679$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:100803.5-100803.29" + attribute \src "libresoc.v:101680.5-101680.29" switch \initial - attribute \src "libresoc.v:100803.9-100803.17" + attribute \src "libresoc.v:101680.9-101680.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -157967,18 +160265,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] end - attribute \src "libresoc.v:100845.3-100887.6" - process $proc$libresoc.v:100845$4082 + attribute \src "libresoc.v:101722.3-101764.6" + process $proc$libresoc.v:101722$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:100846.5-100846.29" + attribute \src "libresoc.v:101723.5-101723.29" switch \initial - attribute \src "libresoc.v:100846.9-100846.17" + attribute \src "libresoc.v:101723.9-101723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158034,18 +160332,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:100888.3-100930.6" - process $proc$libresoc.v:100888$4083 + attribute \src "libresoc.v:101765.3-101807.6" + process $proc$libresoc.v:101765$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:100889.5-100889.29" + attribute \src "libresoc.v:101766.5-101766.29" switch \initial - attribute \src "libresoc.v:100889.9-100889.17" + attribute \src "libresoc.v:101766.9-101766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158101,18 +160399,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:100931.3-100973.6" - process $proc$libresoc.v:100931$4084 + attribute \src "libresoc.v:101808.3-101850.6" + process $proc$libresoc.v:101808$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:100932.5-100932.29" + attribute \src "libresoc.v:101809.5-101809.29" switch \initial - attribute \src "libresoc.v:100932.9-100932.17" + attribute \src "libresoc.v:101809.9-101809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158168,18 +160466,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:100974.3-101016.6" - process $proc$libresoc.v:100974$4085 + attribute \src "libresoc.v:101851.3-101893.6" + process $proc$libresoc.v:101851$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:100975.5-100975.29" + attribute \src "libresoc.v:101852.5-101852.29" switch \initial - attribute \src "libresoc.v:100975.9-100975.17" + attribute \src "libresoc.v:101852.9-101852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158235,18 +160533,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:101017.3-101059.6" - process $proc$libresoc.v:101017$4086 + attribute \src "libresoc.v:101894.3-101936.6" + process $proc$libresoc.v:101894$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101018.5-101018.29" + attribute \src "libresoc.v:101895.5-101895.29" switch \initial - attribute \src "libresoc.v:101018.9-101018.17" + attribute \src "libresoc.v:101895.9-101895.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158302,18 +160600,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:101060.3-101102.6" - process $proc$libresoc.v:101060$4087 + attribute \src "libresoc.v:101937.3-101979.6" + process $proc$libresoc.v:101937$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101061.5-101061.29" + attribute \src "libresoc.v:101938.5-101938.29" switch \initial - attribute \src "libresoc.v:101061.9-101061.17" + attribute \src "libresoc.v:101938.9-101938.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158369,18 +160667,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:101103.3-101145.6" - process $proc$libresoc.v:101103$4088 + attribute \src "libresoc.v:101980.3-102022.6" + process $proc$libresoc.v:101980$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:101104.5-101104.29" + attribute \src "libresoc.v:101981.5-101981.29" switch \initial - attribute \src "libresoc.v:101104.9-101104.17" + attribute \src "libresoc.v:101981.9-101981.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158436,18 +160734,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:101146.3-101188.6" - process $proc$libresoc.v:101146$4089 + attribute \src "libresoc.v:102023.3-102065.6" + process $proc$libresoc.v:102023$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:101147.5-101147.29" + attribute \src "libresoc.v:102024.5-102024.29" switch \initial - attribute \src "libresoc.v:101147.9-101147.17" + attribute \src "libresoc.v:102024.9-102024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158503,18 +160801,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:101189.3-101231.6" - process $proc$libresoc.v:101189$4090 + attribute \src "libresoc.v:102066.3-102108.6" + process $proc$libresoc.v:102066$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:101190.5-101190.29" + attribute \src "libresoc.v:102067.5-102067.29" switch \initial - attribute \src "libresoc.v:101190.9-101190.17" + attribute \src "libresoc.v:102067.9-102067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158570,18 +160868,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:101232.3-101274.6" - process $proc$libresoc.v:101232$4091 + attribute \src "libresoc.v:102109.3-102151.6" + process $proc$libresoc.v:102109$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101233.5-101233.29" + attribute \src "libresoc.v:102110.5-102110.29" switch \initial - attribute \src "libresoc.v:101233.9-101233.17" + attribute \src "libresoc.v:102110.9-102110.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158637,18 +160935,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:101275.3-101317.6" - process $proc$libresoc.v:101275$4092 + attribute \src "libresoc.v:102152.3-102194.6" + process $proc$libresoc.v:102152$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101276.5-101276.29" + attribute \src "libresoc.v:102153.5-102153.29" switch \initial - attribute \src "libresoc.v:101276.9-101276.17" + attribute \src "libresoc.v:102153.9-102153.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158704,18 +161002,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:101318.3-101360.6" - process $proc$libresoc.v:101318$4093 + attribute \src "libresoc.v:102195.3-102237.6" + process $proc$libresoc.v:102195$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:101319.5-101319.29" + attribute \src "libresoc.v:102196.5-102196.29" switch \initial - attribute \src "libresoc.v:101319.9-101319.17" + attribute \src "libresoc.v:102196.9-102196.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158771,18 +161069,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:101361.3-101403.6" - process $proc$libresoc.v:101361$4094 + attribute \src "libresoc.v:102238.3-102280.6" + process $proc$libresoc.v:102238$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:101362.5-101362.29" + attribute \src "libresoc.v:102239.5-102239.29" switch \initial - attribute \src "libresoc.v:101362.9-101362.17" + attribute \src "libresoc.v:102239.9-102239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158838,18 +161136,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:101404.3-101446.6" - process $proc$libresoc.v:101404$4095 + attribute \src "libresoc.v:102281.3-102323.6" + process $proc$libresoc.v:102281$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:101405.5-101405.29" + attribute \src "libresoc.v:102282.5-102282.29" switch \initial - attribute \src "libresoc.v:101405.9-101405.17" + attribute \src "libresoc.v:102282.9-102282.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158905,18 +161203,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:101447.3-101489.6" - process $proc$libresoc.v:101447$4096 + attribute \src "libresoc.v:102324.3-102366.6" + process $proc$libresoc.v:102324$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:101448.5-101448.29" + attribute \src "libresoc.v:102325.5-102325.29" switch \initial - attribute \src "libresoc.v:101448.9-101448.17" + attribute \src "libresoc.v:102325.9-102325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -158972,18 +161270,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:101490.3-101532.6" - process $proc$libresoc.v:101490$4097 + attribute \src "libresoc.v:102367.3-102409.6" + process $proc$libresoc.v:102367$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:101491.5-101491.29" + attribute \src "libresoc.v:102368.5-102368.29" switch \initial - attribute \src "libresoc.v:101491.9-101491.17" + attribute \src "libresoc.v:102368.9-102368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159039,18 +161337,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:101533.3-101575.6" - process $proc$libresoc.v:101533$4098 + attribute \src "libresoc.v:102410.3-102452.6" + process $proc$libresoc.v:102410$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:101534.5-101534.29" + attribute \src "libresoc.v:102411.5-102411.29" switch \initial - attribute \src "libresoc.v:101534.9-101534.17" + attribute \src "libresoc.v:102411.9-102411.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159106,18 +161404,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:101576.3-101618.6" - process $proc$libresoc.v:101576$4099 + attribute \src "libresoc.v:102453.3-102495.6" + process $proc$libresoc.v:102453$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:101577.5-101577.29" + attribute \src "libresoc.v:102454.5-102454.29" switch \initial - attribute \src "libresoc.v:101577.9-101577.17" + attribute \src "libresoc.v:102454.9-102454.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159173,18 +161471,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:101619.3-101661.6" - process $proc$libresoc.v:101619$4100 + attribute \src "libresoc.v:102496.3-102538.6" + process $proc$libresoc.v:102496$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:101620.5-101620.29" + attribute \src "libresoc.v:102497.5-102497.29" switch \initial - attribute \src "libresoc.v:101620.9-101620.17" + attribute \src "libresoc.v:102497.9-102497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159240,18 +161538,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:101662.3-101704.6" - process $proc$libresoc.v:101662$4101 + attribute \src "libresoc.v:102539.3-102581.6" + process $proc$libresoc.v:102539$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:101663.5-101663.29" + attribute \src "libresoc.v:102540.5-102540.29" switch \initial - attribute \src "libresoc.v:101663.9-101663.17" + attribute \src "libresoc.v:102540.9-102540.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159307,18 +161605,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:101705.3-101747.6" - process $proc$libresoc.v:101705$4102 + attribute \src "libresoc.v:102582.3-102624.6" + process $proc$libresoc.v:102582$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:101706.5-101706.29" + attribute \src "libresoc.v:102583.5-102583.29" switch \initial - attribute \src "libresoc.v:101706.9-101706.17" + attribute \src "libresoc.v:102583.9-102583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159374,18 +161672,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] end - attribute \src "libresoc.v:101748.3-101790.6" - process $proc$libresoc.v:101748$4103 + attribute \src "libresoc.v:102625.3-102667.6" + process $proc$libresoc.v:102625$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:101749.5-101749.29" + attribute \src "libresoc.v:102626.5-102626.29" switch \initial - attribute \src "libresoc.v:101749.9-101749.17" + attribute \src "libresoc.v:102626.9-102626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159441,18 +161739,18 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:101791.3-101833.6" - process $proc$libresoc.v:101791$4104 + attribute \src "libresoc.v:102668.3-102710.6" + process $proc$libresoc.v:102668$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:101792.5-101792.29" + attribute \src "libresoc.v:102669.5-102669.29" switch \initial - attribute \src "libresoc.v:101792.9-101792.17" + attribute \src "libresoc.v:102669.9-102669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'00011 @@ -159510,112 +161808,112 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101839.1-103418.10" +attribute \src "libresoc.v:102716.1-104295.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:102372.3-102426.6" + attribute \src "libresoc.v:103249.3-103303.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:102592.3-102646.6" + attribute \src "libresoc.v:103469.3-103523.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103307.3-103361.6" + attribute \src "libresoc.v:104184.3-104238.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:103362.3-103416.6" + attribute \src "libresoc.v:104239.3-104293.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:102317.3-102371.6" + attribute \src "libresoc.v:103194.3-103248.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:102537.3-102591.6" + attribute \src "libresoc.v:103414.3-103468.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103032.3-103086.6" + attribute \src "libresoc.v:103909.3-103963.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102097.3-102151.6" + attribute \src "libresoc.v:102974.3-103028.6" wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103087.3-103141.6" + attribute \src "libresoc.v:103964.3-104018.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103142.3-103196.6" + attribute \src "libresoc.v:104019.3-104073.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103197.3-103251.6" + attribute \src "libresoc.v:104074.3-104128.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:102702.3-102756.6" + attribute \src "libresoc.v:103579.3-103633.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:102427.3-102481.6" + attribute \src "libresoc.v:103304.3-103358.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:102482.3-102536.6" + attribute \src "libresoc.v:103359.3-103413.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:102812.3-102866.6" + attribute \src "libresoc.v:103689.3-103743.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:102152.3-102206.6" + attribute \src "libresoc.v:103029.3-103083.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:102922.3-102976.6" + attribute \src "libresoc.v:103799.3-103853.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103252.3-103306.6" + attribute \src "libresoc.v:104129.3-104183.6" wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:102262.3-102316.6" + attribute \src "libresoc.v:103139.3-103193.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:102757.3-102811.6" + attribute \src "libresoc.v:103634.3-103688.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:102977.3-103031.6" + attribute \src "libresoc.v:103854.3-103908.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:102867.3-102921.6" + attribute \src "libresoc.v:103744.3-103798.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:102647.3-102701.6" + attribute \src "libresoc.v:103524.3-103578.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:102207.3-102261.6" + attribute \src "libresoc.v:103084.3-103138.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:101840.7-101840.20" + attribute \src "libresoc.v:102717.7-102717.20" wire $0\initial[0:0] - attribute \src "libresoc.v:102372.3-102426.6" + attribute \src "libresoc.v:103249.3-103303.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:102592.3-102646.6" + attribute \src "libresoc.v:103469.3-103523.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103307.3-103361.6" + attribute \src "libresoc.v:104184.3-104238.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:103362.3-103416.6" + attribute \src "libresoc.v:104239.3-104293.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:102317.3-102371.6" + attribute \src "libresoc.v:103194.3-103248.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:102537.3-102591.6" + attribute \src "libresoc.v:103414.3-103468.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103032.3-103086.6" + attribute \src "libresoc.v:103909.3-103963.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102097.3-102151.6" + attribute \src "libresoc.v:102974.3-103028.6" wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103087.3-103141.6" + attribute \src "libresoc.v:103964.3-104018.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103142.3-103196.6" + attribute \src "libresoc.v:104019.3-104073.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103197.3-103251.6" + attribute \src "libresoc.v:104074.3-104128.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:102702.3-102756.6" + attribute \src "libresoc.v:103579.3-103633.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:102427.3-102481.6" + attribute \src "libresoc.v:103304.3-103358.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:102482.3-102536.6" + attribute \src "libresoc.v:103359.3-103413.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:102812.3-102866.6" + attribute \src "libresoc.v:103689.3-103743.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:102152.3-102206.6" + attribute \src "libresoc.v:103029.3-103083.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:102922.3-102976.6" + attribute \src "libresoc.v:103799.3-103853.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103252.3-103306.6" + attribute \src "libresoc.v:104129.3-104183.6" wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:102262.3-102316.6" + attribute \src "libresoc.v:103139.3-103193.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:102757.3-102811.6" + attribute \src "libresoc.v:103634.3-103688.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:102977.3-103031.6" + attribute \src "libresoc.v:103854.3-103908.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:102867.3-102921.6" + attribute \src "libresoc.v:103744.3-103798.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:102647.3-102701.6" + attribute \src "libresoc.v:103524.3-103578.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:102207.3-102261.6" + attribute \src "libresoc.v:103084.3-103138.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec31_dec_sub9_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -159625,7 +161923,7 @@ module \dec31_dec_sub9 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec31_dec_sub9_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -159633,15 +161931,15 @@ module \dec31_dec_sub9 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec31_dec_sub9_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec31_dec_sub9_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -159673,7 +161971,7 @@ module \dec31_dec_sub9 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -159688,7 +161986,7 @@ module \dec31_dec_sub9 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec31_dec_sub9_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -159696,7 +161994,7 @@ module \dec31_dec_sub9 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec31_dec_sub9_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -159713,13 +162011,13 @@ module \dec31_dec_sub9 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec31_dec_sub9_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec31_dec_sub9_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -159795,13 +162093,13 @@ module \dec31_dec_sub9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec31_dec_sub9_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -159809,64 +162107,64 @@ module \dec31_dec_sub9 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec31_dec_sub9_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec31_dec_sub9_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec31_dec_sub9_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "libresoc.v:101840.7-101840.15" + attribute \src "libresoc.v:102717.7-102717.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 \opcode_switch - attribute \src "libresoc.v:101840.7-101840.20" - process $proc$libresoc.v:101840$4130 + attribute \src "libresoc.v:102717.7-102717.20" + process $proc$libresoc.v:102717$4211 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102097.3-102151.6" - process $proc$libresoc.v:102097$4106 + attribute \src "libresoc.v:102974.3-103028.6" + process $proc$libresoc.v:102974$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:102098.5-102098.29" + attribute \src "libresoc.v:102975.5-102975.29" switch \initial - attribute \src "libresoc.v:102098.9-102098.17" + attribute \src "libresoc.v:102975.9-102975.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -159938,18 +162236,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] end - attribute \src "libresoc.v:102152.3-102206.6" - process $proc$libresoc.v:102152$4107 + attribute \src "libresoc.v:103029.3-103083.6" + process $proc$libresoc.v:103029$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:102153.5-102153.29" + attribute \src "libresoc.v:103030.5-103030.29" switch \initial - attribute \src "libresoc.v:102153.9-102153.17" + attribute \src "libresoc.v:103030.9-103030.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160021,18 +162319,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:102207.3-102261.6" - process $proc$libresoc.v:102207$4108 + attribute \src "libresoc.v:103084.3-103138.6" + process $proc$libresoc.v:103084$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:102208.5-102208.29" + attribute \src "libresoc.v:103085.5-103085.29" switch \initial - attribute \src "libresoc.v:102208.9-102208.17" + attribute \src "libresoc.v:103085.9-103085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160104,18 +162402,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:102262.3-102316.6" - process $proc$libresoc.v:102262$4109 + attribute \src "libresoc.v:103139.3-103193.6" + process $proc$libresoc.v:103139$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:102263.5-102263.29" + attribute \src "libresoc.v:103140.5-103140.29" switch \initial - attribute \src "libresoc.v:102263.9-102263.17" + attribute \src "libresoc.v:103140.9-103140.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160187,18 +162485,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:102317.3-102371.6" - process $proc$libresoc.v:102317$4110 + attribute \src "libresoc.v:103194.3-103248.6" + process $proc$libresoc.v:103194$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:102318.5-102318.29" + attribute \src "libresoc.v:103195.5-103195.29" switch \initial - attribute \src "libresoc.v:102318.9-102318.17" + attribute \src "libresoc.v:103195.9-103195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160270,18 +162568,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:102372.3-102426.6" - process $proc$libresoc.v:102372$4111 + attribute \src "libresoc.v:103249.3-103303.6" + process $proc$libresoc.v:103249$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:102373.5-102373.29" + attribute \src "libresoc.v:103250.5-103250.29" switch \initial - attribute \src "libresoc.v:102373.9-102373.17" + attribute \src "libresoc.v:103250.9-103250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160353,18 +162651,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:102427.3-102481.6" - process $proc$libresoc.v:102427$4112 + attribute \src "libresoc.v:103304.3-103358.6" + process $proc$libresoc.v:103304$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:102428.5-102428.29" + attribute \src "libresoc.v:103305.5-103305.29" switch \initial - attribute \src "libresoc.v:102428.9-102428.17" + attribute \src "libresoc.v:103305.9-103305.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160436,18 +162734,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:102482.3-102536.6" - process $proc$libresoc.v:102482$4113 + attribute \src "libresoc.v:103359.3-103413.6" + process $proc$libresoc.v:103359$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:102483.5-102483.29" + attribute \src "libresoc.v:103360.5-103360.29" switch \initial - attribute \src "libresoc.v:102483.9-102483.17" + attribute \src "libresoc.v:103360.9-103360.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160519,18 +162817,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:102537.3-102591.6" - process $proc$libresoc.v:102537$4114 + attribute \src "libresoc.v:103414.3-103468.6" + process $proc$libresoc.v:103414$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:102538.5-102538.29" + attribute \src "libresoc.v:103415.5-103415.29" switch \initial - attribute \src "libresoc.v:102538.9-102538.17" + attribute \src "libresoc.v:103415.9-103415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160602,18 +162900,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:102592.3-102646.6" - process $proc$libresoc.v:102592$4115 + attribute \src "libresoc.v:103469.3-103523.6" + process $proc$libresoc.v:103469$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:102593.5-102593.29" + attribute \src "libresoc.v:103470.5-103470.29" switch \initial - attribute \src "libresoc.v:102593.9-102593.17" + attribute \src "libresoc.v:103470.9-103470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160685,18 +162983,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:102647.3-102701.6" - process $proc$libresoc.v:102647$4116 + attribute \src "libresoc.v:103524.3-103578.6" + process $proc$libresoc.v:103524$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:102648.5-102648.29" + attribute \src "libresoc.v:103525.5-103525.29" switch \initial - attribute \src "libresoc.v:102648.9-102648.17" + attribute \src "libresoc.v:103525.9-103525.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160768,18 +163066,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:102702.3-102756.6" - process $proc$libresoc.v:102702$4117 + attribute \src "libresoc.v:103579.3-103633.6" + process $proc$libresoc.v:103579$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:102703.5-102703.29" + attribute \src "libresoc.v:103580.5-103580.29" switch \initial - attribute \src "libresoc.v:102703.9-102703.17" + attribute \src "libresoc.v:103580.9-103580.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160851,18 +163149,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:102757.3-102811.6" - process $proc$libresoc.v:102757$4118 + attribute \src "libresoc.v:103634.3-103688.6" + process $proc$libresoc.v:103634$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:102758.5-102758.29" + attribute \src "libresoc.v:103635.5-103635.29" switch \initial - attribute \src "libresoc.v:102758.9-102758.17" + attribute \src "libresoc.v:103635.9-103635.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -160934,18 +163232,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:102812.3-102866.6" - process $proc$libresoc.v:102812$4119 + attribute \src "libresoc.v:103689.3-103743.6" + process $proc$libresoc.v:103689$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:102813.5-102813.29" + attribute \src "libresoc.v:103690.5-103690.29" switch \initial - attribute \src "libresoc.v:102813.9-102813.17" + attribute \src "libresoc.v:103690.9-103690.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161017,18 +163315,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:102867.3-102921.6" - process $proc$libresoc.v:102867$4120 + attribute \src "libresoc.v:103744.3-103798.6" + process $proc$libresoc.v:103744$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:102868.5-102868.29" + attribute \src "libresoc.v:103745.5-103745.29" switch \initial - attribute \src "libresoc.v:102868.9-102868.17" + attribute \src "libresoc.v:103745.9-103745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161100,18 +163398,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:102922.3-102976.6" - process $proc$libresoc.v:102922$4121 + attribute \src "libresoc.v:103799.3-103853.6" + process $proc$libresoc.v:103799$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:102923.5-102923.29" + attribute \src "libresoc.v:103800.5-103800.29" switch \initial - attribute \src "libresoc.v:102923.9-102923.17" + attribute \src "libresoc.v:103800.9-103800.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161183,18 +163481,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:102977.3-103031.6" - process $proc$libresoc.v:102977$4122 + attribute \src "libresoc.v:103854.3-103908.6" + process $proc$libresoc.v:103854$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:102978.5-102978.29" + attribute \src "libresoc.v:103855.5-103855.29" switch \initial - attribute \src "libresoc.v:102978.9-102978.17" + attribute \src "libresoc.v:103855.9-103855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161266,18 +163564,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:103032.3-103086.6" - process $proc$libresoc.v:103032$4123 + attribute \src "libresoc.v:103909.3-103963.6" + process $proc$libresoc.v:103909$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:103033.5-103033.29" + attribute \src "libresoc.v:103910.5-103910.29" switch \initial - attribute \src "libresoc.v:103033.9-103033.17" + attribute \src "libresoc.v:103910.9-103910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161349,18 +163647,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:103087.3-103141.6" - process $proc$libresoc.v:103087$4124 + attribute \src "libresoc.v:103964.3-104018.6" + process $proc$libresoc.v:103964$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103088.5-103088.29" + attribute \src "libresoc.v:103965.5-103965.29" switch \initial - attribute \src "libresoc.v:103088.9-103088.17" + attribute \src "libresoc.v:103965.9-103965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161432,18 +163730,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:103142.3-103196.6" - process $proc$libresoc.v:103142$4125 + attribute \src "libresoc.v:104019.3-104073.6" + process $proc$libresoc.v:104019$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:103143.5-103143.29" + attribute \src "libresoc.v:104020.5-104020.29" switch \initial - attribute \src "libresoc.v:103143.9-103143.17" + attribute \src "libresoc.v:104020.9-104020.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161515,18 +163813,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:103197.3-103251.6" - process $proc$libresoc.v:103197$4126 + attribute \src "libresoc.v:104074.3-104128.6" + process $proc$libresoc.v:104074$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103198.5-103198.29" + attribute \src "libresoc.v:104075.5-104075.29" switch \initial - attribute \src "libresoc.v:103198.9-103198.17" + attribute \src "libresoc.v:104075.9-104075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161598,18 +163896,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:103252.3-103306.6" - process $proc$libresoc.v:103252$4127 + attribute \src "libresoc.v:104129.3-104183.6" + process $proc$libresoc.v:104129$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:103253.5-103253.29" + attribute \src "libresoc.v:104130.5-104130.29" switch \initial - attribute \src "libresoc.v:103253.9-103253.17" + attribute \src "libresoc.v:104130.9-104130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161681,18 +163979,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] end - attribute \src "libresoc.v:103307.3-103361.6" - process $proc$libresoc.v:103307$4128 + attribute \src "libresoc.v:104184.3-104238.6" + process $proc$libresoc.v:104184$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:103308.5-103308.29" + attribute \src "libresoc.v:104185.5-104185.29" switch \initial - attribute \src "libresoc.v:103308.9-103308.17" + attribute \src "libresoc.v:104185.9-104185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161764,18 +164062,18 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:103362.3-103416.6" - process $proc$libresoc.v:103362$4129 + attribute \src "libresoc.v:104239.3-104293.6" + process $proc$libresoc.v:104239$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:103363.5-103363.29" + attribute \src "libresoc.v:104240.5-104240.29" switch \initial - attribute \src "libresoc.v:103363.9-103363.17" + attribute \src "libresoc.v:104240.9-104240.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 5'01100 @@ -161849,112 +164147,112 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:103422.1-104065.10" +attribute \src "libresoc.v:104299.1-104942.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:103760.3-103775.6" + attribute \src "libresoc.v:104637.3-104652.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:103824.3-103839.6" + attribute \src "libresoc.v:104701.3-104716.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:104032.3-104047.6" + attribute \src "libresoc.v:104909.3-104924.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:104048.3-104063.6" + attribute \src "libresoc.v:104925.3-104940.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:103744.3-103759.6" + attribute \src "libresoc.v:104621.3-104636.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:103808.3-103823.6" + attribute \src "libresoc.v:104685.3-104700.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:103952.3-103967.6" + attribute \src "libresoc.v:104829.3-104844.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:103680.3-103695.6" + attribute \src "libresoc.v:104557.3-104572.6" wire width 12 $0\dec58_function_unit[11:0] - attribute \src "libresoc.v:103968.3-103983.6" + attribute \src "libresoc.v:104845.3-104860.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:103984.3-103999.6" + attribute \src "libresoc.v:104861.3-104876.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104000.3-104015.6" + attribute \src "libresoc.v:104877.3-104892.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:103856.3-103871.6" + attribute \src "libresoc.v:104733.3-104748.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:103776.3-103791.6" + attribute \src "libresoc.v:104653.3-104668.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:103792.3-103807.6" + attribute \src "libresoc.v:104669.3-104684.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:103888.3-103903.6" + attribute \src "libresoc.v:104765.3-104780.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:103696.3-103711.6" + attribute \src "libresoc.v:104573.3-104588.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:103920.3-103935.6" + attribute \src "libresoc.v:104797.3-104812.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:104016.3-104031.6" + attribute \src "libresoc.v:104893.3-104908.6" wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:103728.3-103743.6" + attribute \src "libresoc.v:104605.3-104620.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:103872.3-103887.6" + attribute \src "libresoc.v:104749.3-104764.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:103936.3-103951.6" + attribute \src "libresoc.v:104813.3-104828.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:103904.3-103919.6" + attribute \src "libresoc.v:104781.3-104796.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:103840.3-103855.6" + attribute \src "libresoc.v:104717.3-104732.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:103712.3-103727.6" + attribute \src "libresoc.v:104589.3-104604.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:103423.7-103423.20" + attribute \src "libresoc.v:104300.7-104300.20" wire $0\initial[0:0] - attribute \src "libresoc.v:103760.3-103775.6" + attribute \src "libresoc.v:104637.3-104652.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:103824.3-103839.6" + attribute \src "libresoc.v:104701.3-104716.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:104032.3-104047.6" + attribute \src "libresoc.v:104909.3-104924.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104048.3-104063.6" + attribute \src "libresoc.v:104925.3-104940.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:103744.3-103759.6" + attribute \src "libresoc.v:104621.3-104636.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:103808.3-103823.6" + attribute \src "libresoc.v:104685.3-104700.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:103952.3-103967.6" + attribute \src "libresoc.v:104829.3-104844.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:103680.3-103695.6" + attribute \src "libresoc.v:104557.3-104572.6" wire width 12 $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:103968.3-103983.6" + attribute \src "libresoc.v:104845.3-104860.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:103984.3-103999.6" + attribute \src "libresoc.v:104861.3-104876.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104000.3-104015.6" + attribute \src "libresoc.v:104877.3-104892.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:103856.3-103871.6" + attribute \src "libresoc.v:104733.3-104748.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:103776.3-103791.6" + attribute \src "libresoc.v:104653.3-104668.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:103792.3-103807.6" + attribute \src "libresoc.v:104669.3-104684.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:103888.3-103903.6" + attribute \src "libresoc.v:104765.3-104780.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:103696.3-103711.6" + attribute \src "libresoc.v:104573.3-104588.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:103920.3-103935.6" + attribute \src "libresoc.v:104797.3-104812.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:104016.3-104031.6" + attribute \src "libresoc.v:104893.3-104908.6" wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:103728.3-103743.6" + attribute \src "libresoc.v:104605.3-104620.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:103872.3-103887.6" + attribute \src "libresoc.v:104749.3-104764.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:103936.3-103951.6" + attribute \src "libresoc.v:104813.3-104828.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:103904.3-103919.6" + attribute \src "libresoc.v:104781.3-104796.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:103840.3-103855.6" + attribute \src "libresoc.v:104717.3-104732.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:103712.3-103727.6" + attribute \src "libresoc.v:104589.3-104604.6" wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec58_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -161964,7 +164262,7 @@ module \dec58 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec58_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -161972,15 +164270,15 @@ module \dec58 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec58_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec58_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -162012,7 +164310,7 @@ module \dec58 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -162027,7 +164325,7 @@ module \dec58 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec58_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -162035,7 +164333,7 @@ module \dec58 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec58_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -162052,13 +164350,13 @@ module \dec58 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec58_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec58_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -162134,13 +164432,13 @@ module \dec58 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec58_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -162148,64 +164446,64 @@ module \dec58 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec58_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec58_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec58_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec58_upd - attribute \src "libresoc.v:103423.7-103423.15" + attribute \src "libresoc.v:104300.7-104300.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 2 \opcode_switch - attribute \src "libresoc.v:103423.7-103423.20" - process $proc$libresoc.v:103423$4155 + attribute \src "libresoc.v:104300.7-104300.20" + process $proc$libresoc.v:104300$4236 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:103680.3-103695.6" - process $proc$libresoc.v:103680$4131 + attribute \src "libresoc.v:104557.3-104572.6" + process $proc$libresoc.v:104557$4212 assign { } { } assign { } { } assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:103681.5-103681.29" + attribute \src "libresoc.v:104558.5-104558.29" switch \initial - attribute \src "libresoc.v:103681.9-103681.17" + attribute \src "libresoc.v:104558.9-104558.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162225,18 +164523,18 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[11:0] end - attribute \src "libresoc.v:103696.3-103711.6" - process $proc$libresoc.v:103696$4132 + attribute \src "libresoc.v:104573.3-104588.6" + process $proc$libresoc.v:104573$4213 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:103697.5-103697.29" + attribute \src "libresoc.v:104574.5-104574.29" switch \initial - attribute \src "libresoc.v:103697.9-103697.17" + attribute \src "libresoc.v:104574.9-104574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162256,18 +164554,18 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:103712.3-103727.6" - process $proc$libresoc.v:103712$4133 + attribute \src "libresoc.v:104589.3-104604.6" + process $proc$libresoc.v:104589$4214 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:103713.5-103713.29" + attribute \src "libresoc.v:104590.5-104590.29" switch \initial - attribute \src "libresoc.v:103713.9-103713.17" + attribute \src "libresoc.v:104590.9-104590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162287,18 +164585,18 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:103728.3-103743.6" - process $proc$libresoc.v:103728$4134 + attribute \src "libresoc.v:104605.3-104620.6" + process $proc$libresoc.v:104605$4215 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:103729.5-103729.29" + attribute \src "libresoc.v:104606.5-104606.29" switch \initial - attribute \src "libresoc.v:103729.9-103729.17" + attribute \src "libresoc.v:104606.9-104606.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162318,18 +164616,18 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:103744.3-103759.6" - process $proc$libresoc.v:103744$4135 + attribute \src "libresoc.v:104621.3-104636.6" + process $proc$libresoc.v:104621$4216 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:103745.5-103745.29" + attribute \src "libresoc.v:104622.5-104622.29" switch \initial - attribute \src "libresoc.v:103745.9-103745.17" + attribute \src "libresoc.v:104622.9-104622.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162349,18 +164647,18 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:103760.3-103775.6" - process $proc$libresoc.v:103760$4136 + attribute \src "libresoc.v:104637.3-104652.6" + process $proc$libresoc.v:104637$4217 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:103761.5-103761.29" + attribute \src "libresoc.v:104638.5-104638.29" switch \initial - attribute \src "libresoc.v:103761.9-103761.17" + attribute \src "libresoc.v:104638.9-104638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162380,18 +164678,18 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:103776.3-103791.6" - process $proc$libresoc.v:103776$4137 + attribute \src "libresoc.v:104653.3-104668.6" + process $proc$libresoc.v:104653$4218 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:103777.5-103777.29" + attribute \src "libresoc.v:104654.5-104654.29" switch \initial - attribute \src "libresoc.v:103777.9-103777.17" + attribute \src "libresoc.v:104654.9-104654.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162411,18 +164709,18 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:103792.3-103807.6" - process $proc$libresoc.v:103792$4138 + attribute \src "libresoc.v:104669.3-104684.6" + process $proc$libresoc.v:104669$4219 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:103793.5-103793.29" + attribute \src "libresoc.v:104670.5-104670.29" switch \initial - attribute \src "libresoc.v:103793.9-103793.17" + attribute \src "libresoc.v:104670.9-104670.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162442,18 +164740,18 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:103808.3-103823.6" - process $proc$libresoc.v:103808$4139 + attribute \src "libresoc.v:104685.3-104700.6" + process $proc$libresoc.v:104685$4220 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:103809.5-103809.29" + attribute \src "libresoc.v:104686.5-104686.29" switch \initial - attribute \src "libresoc.v:103809.9-103809.17" + attribute \src "libresoc.v:104686.9-104686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162473,18 +164771,18 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:103824.3-103839.6" - process $proc$libresoc.v:103824$4140 + attribute \src "libresoc.v:104701.3-104716.6" + process $proc$libresoc.v:104701$4221 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:103825.5-103825.29" + attribute \src "libresoc.v:104702.5-104702.29" switch \initial - attribute \src "libresoc.v:103825.9-103825.17" + attribute \src "libresoc.v:104702.9-104702.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162504,18 +164802,18 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:103840.3-103855.6" - process $proc$libresoc.v:103840$4141 + attribute \src "libresoc.v:104717.3-104732.6" + process $proc$libresoc.v:104717$4222 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:103841.5-103841.29" + attribute \src "libresoc.v:104718.5-104718.29" switch \initial - attribute \src "libresoc.v:103841.9-103841.17" + attribute \src "libresoc.v:104718.9-104718.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162535,18 +164833,18 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:103856.3-103871.6" - process $proc$libresoc.v:103856$4142 + attribute \src "libresoc.v:104733.3-104748.6" + process $proc$libresoc.v:104733$4223 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:103857.5-103857.29" + attribute \src "libresoc.v:104734.5-104734.29" switch \initial - attribute \src "libresoc.v:103857.9-103857.17" + attribute \src "libresoc.v:104734.9-104734.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162566,18 +164864,18 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:103872.3-103887.6" - process $proc$libresoc.v:103872$4143 + attribute \src "libresoc.v:104749.3-104764.6" + process $proc$libresoc.v:104749$4224 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:103873.5-103873.29" + attribute \src "libresoc.v:104750.5-104750.29" switch \initial - attribute \src "libresoc.v:103873.9-103873.17" + attribute \src "libresoc.v:104750.9-104750.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162597,18 +164895,18 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:103888.3-103903.6" - process $proc$libresoc.v:103888$4144 + attribute \src "libresoc.v:104765.3-104780.6" + process $proc$libresoc.v:104765$4225 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:103889.5-103889.29" + attribute \src "libresoc.v:104766.5-104766.29" switch \initial - attribute \src "libresoc.v:103889.9-103889.17" + attribute \src "libresoc.v:104766.9-104766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162628,18 +164926,18 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:103904.3-103919.6" - process $proc$libresoc.v:103904$4145 + attribute \src "libresoc.v:104781.3-104796.6" + process $proc$libresoc.v:104781$4226 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:103905.5-103905.29" + attribute \src "libresoc.v:104782.5-104782.29" switch \initial - attribute \src "libresoc.v:103905.9-103905.17" + attribute \src "libresoc.v:104782.9-104782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162659,18 +164957,18 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:103920.3-103935.6" - process $proc$libresoc.v:103920$4146 + attribute \src "libresoc.v:104797.3-104812.6" + process $proc$libresoc.v:104797$4227 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:103921.5-103921.29" + attribute \src "libresoc.v:104798.5-104798.29" switch \initial - attribute \src "libresoc.v:103921.9-103921.17" + attribute \src "libresoc.v:104798.9-104798.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162690,18 +164988,18 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:103936.3-103951.6" - process $proc$libresoc.v:103936$4147 + attribute \src "libresoc.v:104813.3-104828.6" + process $proc$libresoc.v:104813$4228 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:103937.5-103937.29" + attribute \src "libresoc.v:104814.5-104814.29" switch \initial - attribute \src "libresoc.v:103937.9-103937.17" + attribute \src "libresoc.v:104814.9-104814.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162721,18 +165019,18 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:103952.3-103967.6" - process $proc$libresoc.v:103952$4148 + attribute \src "libresoc.v:104829.3-104844.6" + process $proc$libresoc.v:104829$4229 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:103953.5-103953.29" + attribute \src "libresoc.v:104830.5-104830.29" switch \initial - attribute \src "libresoc.v:103953.9-103953.17" + attribute \src "libresoc.v:104830.9-104830.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162752,18 +165050,18 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:103968.3-103983.6" - process $proc$libresoc.v:103968$4149 + attribute \src "libresoc.v:104845.3-104860.6" + process $proc$libresoc.v:104845$4230 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:103969.5-103969.29" + attribute \src "libresoc.v:104846.5-104846.29" switch \initial - attribute \src "libresoc.v:103969.9-103969.17" + attribute \src "libresoc.v:104846.9-104846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162783,18 +165081,18 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:103984.3-103999.6" - process $proc$libresoc.v:103984$4150 + attribute \src "libresoc.v:104861.3-104876.6" + process $proc$libresoc.v:104861$4231 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:103985.5-103985.29" + attribute \src "libresoc.v:104862.5-104862.29" switch \initial - attribute \src "libresoc.v:103985.9-103985.17" + attribute \src "libresoc.v:104862.9-104862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162814,18 +165112,18 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:104000.3-104015.6" - process $proc$libresoc.v:104000$4151 + attribute \src "libresoc.v:104877.3-104892.6" + process $proc$libresoc.v:104877$4232 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104001.5-104001.29" + attribute \src "libresoc.v:104878.5-104878.29" switch \initial - attribute \src "libresoc.v:104001.9-104001.17" + attribute \src "libresoc.v:104878.9-104878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162845,18 +165143,18 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:104016.3-104031.6" - process $proc$libresoc.v:104016$4152 + attribute \src "libresoc.v:104893.3-104908.6" + process $proc$libresoc.v:104893$4233 assign { } { } assign { } { } assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:104017.5-104017.29" + attribute \src "libresoc.v:104894.5-104894.29" switch \initial - attribute \src "libresoc.v:104017.9-104017.17" + attribute \src "libresoc.v:104894.9-104894.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162876,18 +165174,18 @@ module \dec58 sync always update \dec58_out_sel $0\dec58_out_sel[1:0] end - attribute \src "libresoc.v:104032.3-104047.6" - process $proc$libresoc.v:104032$4153 + attribute \src "libresoc.v:104909.3-104924.6" + process $proc$libresoc.v:104909$4234 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104033.5-104033.29" + attribute \src "libresoc.v:104910.5-104910.29" switch \initial - attribute \src "libresoc.v:104033.9-104033.17" + attribute \src "libresoc.v:104910.9-104910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162907,18 +165205,18 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:104048.3-104063.6" - process $proc$libresoc.v:104048$4154 + attribute \src "libresoc.v:104925.3-104940.6" + process $proc$libresoc.v:104925$4235 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:104049.5-104049.29" + attribute \src "libresoc.v:104926.5-104926.29" switch \initial - attribute \src "libresoc.v:104049.9-104049.17" + attribute \src "libresoc.v:104926.9-104926.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -162940,112 +165238,112 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:104069.1-104640.10" +attribute \src "libresoc.v:104946.1-105517.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:104392.3-104404.6" + attribute \src "libresoc.v:105269.3-105281.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:104444.3-104456.6" + attribute \src "libresoc.v:105321.3-105333.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:104613.3-104625.6" + attribute \src "libresoc.v:105490.3-105502.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:104626.3-104638.6" + attribute \src "libresoc.v:105503.3-105515.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:104379.3-104391.6" + attribute \src "libresoc.v:105256.3-105268.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:104431.3-104443.6" + attribute \src "libresoc.v:105308.3-105320.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:104548.3-104560.6" + attribute \src "libresoc.v:105425.3-105437.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:104327.3-104339.6" + attribute \src "libresoc.v:105204.3-105216.6" wire width 12 $0\dec62_function_unit[11:0] - attribute \src "libresoc.v:104561.3-104573.6" + attribute \src "libresoc.v:105438.3-105450.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:104574.3-104586.6" + attribute \src "libresoc.v:105451.3-105463.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:104587.3-104599.6" + attribute \src "libresoc.v:105464.3-105476.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:104470.3-104482.6" + attribute \src "libresoc.v:105347.3-105359.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:104405.3-104417.6" + attribute \src "libresoc.v:105282.3-105294.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:104418.3-104430.6" + attribute \src "libresoc.v:105295.3-105307.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:104496.3-104508.6" + attribute \src "libresoc.v:105373.3-105385.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:104340.3-104352.6" + attribute \src "libresoc.v:105217.3-105229.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:104522.3-104534.6" + attribute \src "libresoc.v:105399.3-105411.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:104600.3-104612.6" + attribute \src "libresoc.v:105477.3-105489.6" wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:104366.3-104378.6" + attribute \src "libresoc.v:105243.3-105255.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:104483.3-104495.6" + attribute \src "libresoc.v:105360.3-105372.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:104535.3-104547.6" + attribute \src "libresoc.v:105412.3-105424.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:104509.3-104521.6" + attribute \src "libresoc.v:105386.3-105398.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:104457.3-104469.6" + attribute \src "libresoc.v:105334.3-105346.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:104353.3-104365.6" + attribute \src "libresoc.v:105230.3-105242.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:104070.7-104070.20" + attribute \src "libresoc.v:104947.7-104947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:104392.3-104404.6" + attribute \src "libresoc.v:105269.3-105281.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:104444.3-104456.6" + attribute \src "libresoc.v:105321.3-105333.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:104613.3-104625.6" + attribute \src "libresoc.v:105490.3-105502.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:104626.3-104638.6" + attribute \src "libresoc.v:105503.3-105515.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:104379.3-104391.6" + attribute \src "libresoc.v:105256.3-105268.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:104431.3-104443.6" + attribute \src "libresoc.v:105308.3-105320.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:104548.3-104560.6" + attribute \src "libresoc.v:105425.3-105437.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:104327.3-104339.6" + attribute \src "libresoc.v:105204.3-105216.6" wire width 12 $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:104561.3-104573.6" + attribute \src "libresoc.v:105438.3-105450.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:104574.3-104586.6" + attribute \src "libresoc.v:105451.3-105463.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:104587.3-104599.6" + attribute \src "libresoc.v:105464.3-105476.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:104470.3-104482.6" + attribute \src "libresoc.v:105347.3-105359.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:104405.3-104417.6" + attribute \src "libresoc.v:105282.3-105294.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:104418.3-104430.6" + attribute \src "libresoc.v:105295.3-105307.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:104496.3-104508.6" + attribute \src "libresoc.v:105373.3-105385.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:104340.3-104352.6" + attribute \src "libresoc.v:105217.3-105229.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:104522.3-104534.6" + attribute \src "libresoc.v:105399.3-105411.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:104600.3-104612.6" + attribute \src "libresoc.v:105477.3-105489.6" wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:104366.3-104378.6" + attribute \src "libresoc.v:105243.3-105255.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:104483.3-104495.6" + attribute \src "libresoc.v:105360.3-105372.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:104535.3-104547.6" + attribute \src "libresoc.v:105412.3-105424.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:104509.3-104521.6" + attribute \src "libresoc.v:105386.3-105398.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:104457.3-104469.6" + attribute \src "libresoc.v:105334.3-105346.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:104353.3-104365.6" + attribute \src "libresoc.v:105230.3-105242.6" wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 18 \dec62_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -163055,7 +165353,7 @@ module \dec62 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 9 \dec62_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -163063,15 +165361,15 @@ module \dec62 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 10 \dec62_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 17 \dec62_cry_out attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" @@ -163103,7 +165401,7 @@ module \dec62 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -163118,7 +165416,7 @@ module \dec62 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 output 1 \dec62_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -163126,7 +165424,7 @@ module \dec62 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 output 5 \dec62_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -163143,13 +165441,13 @@ module \dec62 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 6 \dec62_in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 7 \dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -163225,13 +165523,13 @@ module \dec62 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 21 \dec62_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -163239,64 +165537,64 @@ module \dec62 attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 23 \dec62_lk attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 8 \dec62_out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire output 19 \dec62_sgn_ext attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 output 12 \dec62_upd - attribute \src "libresoc.v:104070.7-104070.15" + attribute \src "libresoc.v:104947.7-104947.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 2 \opcode_switch - attribute \src "libresoc.v:104070.7-104070.20" - process $proc$libresoc.v:104070$4180 + attribute \src "libresoc.v:104947.7-104947.20" + process $proc$libresoc.v:104947$4261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:104327.3-104339.6" - process $proc$libresoc.v:104327$4156 + attribute \src "libresoc.v:105204.3-105216.6" + process $proc$libresoc.v:105204$4237 assign { } { } assign { } { } assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:104328.5-104328.29" + attribute \src "libresoc.v:105205.5-105205.29" switch \initial - attribute \src "libresoc.v:104328.9-104328.17" + attribute \src "libresoc.v:105205.9-105205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163312,18 +165610,18 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[11:0] end - attribute \src "libresoc.v:104340.3-104352.6" - process $proc$libresoc.v:104340$4157 + attribute \src "libresoc.v:105217.3-105229.6" + process $proc$libresoc.v:105217$4238 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:104341.5-104341.29" + attribute \src "libresoc.v:105218.5-105218.29" switch \initial - attribute \src "libresoc.v:104341.9-104341.17" + attribute \src "libresoc.v:105218.9-105218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163339,18 +165637,18 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:104353.3-104365.6" - process $proc$libresoc.v:104353$4158 + attribute \src "libresoc.v:105230.3-105242.6" + process $proc$libresoc.v:105230$4239 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:104354.5-104354.29" + attribute \src "libresoc.v:105231.5-105231.29" switch \initial - attribute \src "libresoc.v:104354.9-104354.17" + attribute \src "libresoc.v:105231.9-105231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163366,18 +165664,18 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:104366.3-104378.6" - process $proc$libresoc.v:104366$4159 + attribute \src "libresoc.v:105243.3-105255.6" + process $proc$libresoc.v:105243$4240 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:104367.5-104367.29" + attribute \src "libresoc.v:105244.5-105244.29" switch \initial - attribute \src "libresoc.v:104367.9-104367.17" + attribute \src "libresoc.v:105244.9-105244.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163393,18 +165691,18 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:104379.3-104391.6" - process $proc$libresoc.v:104379$4160 + attribute \src "libresoc.v:105256.3-105268.6" + process $proc$libresoc.v:105256$4241 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:104380.5-104380.29" + attribute \src "libresoc.v:105257.5-105257.29" switch \initial - attribute \src "libresoc.v:104380.9-104380.17" + attribute \src "libresoc.v:105257.9-105257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163420,18 +165718,18 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:104392.3-104404.6" - process $proc$libresoc.v:104392$4161 + attribute \src "libresoc.v:105269.3-105281.6" + process $proc$libresoc.v:105269$4242 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:104393.5-104393.29" + attribute \src "libresoc.v:105270.5-105270.29" switch \initial - attribute \src "libresoc.v:104393.9-104393.17" + attribute \src "libresoc.v:105270.9-105270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163447,18 +165745,18 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:104405.3-104417.6" - process $proc$libresoc.v:104405$4162 + attribute \src "libresoc.v:105282.3-105294.6" + process $proc$libresoc.v:105282$4243 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:104406.5-104406.29" + attribute \src "libresoc.v:105283.5-105283.29" switch \initial - attribute \src "libresoc.v:104406.9-104406.17" + attribute \src "libresoc.v:105283.9-105283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163474,18 +165772,18 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:104418.3-104430.6" - process $proc$libresoc.v:104418$4163 + attribute \src "libresoc.v:105295.3-105307.6" + process $proc$libresoc.v:105295$4244 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:104419.5-104419.29" + attribute \src "libresoc.v:105296.5-105296.29" switch \initial - attribute \src "libresoc.v:104419.9-104419.17" + attribute \src "libresoc.v:105296.9-105296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163501,18 +165799,18 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:104431.3-104443.6" - process $proc$libresoc.v:104431$4164 + attribute \src "libresoc.v:105308.3-105320.6" + process $proc$libresoc.v:105308$4245 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:104432.5-104432.29" + attribute \src "libresoc.v:105309.5-105309.29" switch \initial - attribute \src "libresoc.v:104432.9-104432.17" + attribute \src "libresoc.v:105309.9-105309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163528,18 +165826,18 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:104444.3-104456.6" - process $proc$libresoc.v:104444$4165 + attribute \src "libresoc.v:105321.3-105333.6" + process $proc$libresoc.v:105321$4246 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:104445.5-104445.29" + attribute \src "libresoc.v:105322.5-105322.29" switch \initial - attribute \src "libresoc.v:104445.9-104445.17" + attribute \src "libresoc.v:105322.9-105322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163555,18 +165853,18 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:104457.3-104469.6" - process $proc$libresoc.v:104457$4166 + attribute \src "libresoc.v:105334.3-105346.6" + process $proc$libresoc.v:105334$4247 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:104458.5-104458.29" + attribute \src "libresoc.v:105335.5-105335.29" switch \initial - attribute \src "libresoc.v:104458.9-104458.17" + attribute \src "libresoc.v:105335.9-105335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163582,18 +165880,18 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:104470.3-104482.6" - process $proc$libresoc.v:104470$4167 + attribute \src "libresoc.v:105347.3-105359.6" + process $proc$libresoc.v:105347$4248 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:104471.5-104471.29" + attribute \src "libresoc.v:105348.5-105348.29" switch \initial - attribute \src "libresoc.v:104471.9-104471.17" + attribute \src "libresoc.v:105348.9-105348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163609,18 +165907,18 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:104483.3-104495.6" - process $proc$libresoc.v:104483$4168 + attribute \src "libresoc.v:105360.3-105372.6" + process $proc$libresoc.v:105360$4249 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:104484.5-104484.29" + attribute \src "libresoc.v:105361.5-105361.29" switch \initial - attribute \src "libresoc.v:104484.9-104484.17" + attribute \src "libresoc.v:105361.9-105361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163636,18 +165934,18 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:104496.3-104508.6" - process $proc$libresoc.v:104496$4169 + attribute \src "libresoc.v:105373.3-105385.6" + process $proc$libresoc.v:105373$4250 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:104497.5-104497.29" + attribute \src "libresoc.v:105374.5-105374.29" switch \initial - attribute \src "libresoc.v:104497.9-104497.17" + attribute \src "libresoc.v:105374.9-105374.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163663,18 +165961,18 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:104509.3-104521.6" - process $proc$libresoc.v:104509$4170 + attribute \src "libresoc.v:105386.3-105398.6" + process $proc$libresoc.v:105386$4251 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:104510.5-104510.29" + attribute \src "libresoc.v:105387.5-105387.29" switch \initial - attribute \src "libresoc.v:104510.9-104510.17" + attribute \src "libresoc.v:105387.9-105387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163690,18 +165988,18 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:104522.3-104534.6" - process $proc$libresoc.v:104522$4171 + attribute \src "libresoc.v:105399.3-105411.6" + process $proc$libresoc.v:105399$4252 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:104523.5-104523.29" + attribute \src "libresoc.v:105400.5-105400.29" switch \initial - attribute \src "libresoc.v:104523.9-104523.17" + attribute \src "libresoc.v:105400.9-105400.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163717,18 +166015,18 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:104535.3-104547.6" - process $proc$libresoc.v:104535$4172 + attribute \src "libresoc.v:105412.3-105424.6" + process $proc$libresoc.v:105412$4253 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:104536.5-104536.29" + attribute \src "libresoc.v:105413.5-105413.29" switch \initial - attribute \src "libresoc.v:104536.9-104536.17" + attribute \src "libresoc.v:105413.9-105413.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163744,18 +166042,18 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:104548.3-104560.6" - process $proc$libresoc.v:104548$4173 + attribute \src "libresoc.v:105425.3-105437.6" + process $proc$libresoc.v:105425$4254 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:104549.5-104549.29" + attribute \src "libresoc.v:105426.5-105426.29" switch \initial - attribute \src "libresoc.v:104549.9-104549.17" + attribute \src "libresoc.v:105426.9-105426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163771,18 +166069,18 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:104561.3-104573.6" - process $proc$libresoc.v:104561$4174 + attribute \src "libresoc.v:105438.3-105450.6" + process $proc$libresoc.v:105438$4255 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:104562.5-104562.29" + attribute \src "libresoc.v:105439.5-105439.29" switch \initial - attribute \src "libresoc.v:104562.9-104562.17" + attribute \src "libresoc.v:105439.9-105439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163798,18 +166096,18 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:104574.3-104586.6" - process $proc$libresoc.v:104574$4175 + attribute \src "libresoc.v:105451.3-105463.6" + process $proc$libresoc.v:105451$4256 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:104575.5-104575.29" + attribute \src "libresoc.v:105452.5-105452.29" switch \initial - attribute \src "libresoc.v:104575.9-104575.17" + attribute \src "libresoc.v:105452.9-105452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163825,18 +166123,18 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:104587.3-104599.6" - process $proc$libresoc.v:104587$4176 + attribute \src "libresoc.v:105464.3-105476.6" + process $proc$libresoc.v:105464$4257 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:104588.5-104588.29" + attribute \src "libresoc.v:105465.5-105465.29" switch \initial - attribute \src "libresoc.v:104588.9-104588.17" + attribute \src "libresoc.v:105465.9-105465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163852,18 +166150,18 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:104600.3-104612.6" - process $proc$libresoc.v:104600$4177 + attribute \src "libresoc.v:105477.3-105489.6" + process $proc$libresoc.v:105477$4258 assign { } { } assign { } { } assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:104601.5-104601.29" + attribute \src "libresoc.v:105478.5-105478.29" switch \initial - attribute \src "libresoc.v:104601.9-104601.17" + attribute \src "libresoc.v:105478.9-105478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163879,18 +166177,18 @@ module \dec62 sync always update \dec62_out_sel $0\dec62_out_sel[1:0] end - attribute \src "libresoc.v:104613.3-104625.6" - process $proc$libresoc.v:104613$4178 + attribute \src "libresoc.v:105490.3-105502.6" + process $proc$libresoc.v:105490$4259 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:104614.5-104614.29" + attribute \src "libresoc.v:105491.5-105491.29" switch \initial - attribute \src "libresoc.v:104614.9-104614.17" + attribute \src "libresoc.v:105491.9-105491.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163906,18 +166204,18 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:104626.3-104638.6" - process $proc$libresoc.v:104626$4179 + attribute \src "libresoc.v:105503.3-105515.6" + process $proc$libresoc.v:105503$4260 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:104627.5-104627.29" + attribute \src "libresoc.v:105504.5-105504.29" switch \initial - attribute \src "libresoc.v:104627.9-104627.17" + attribute \src "libresoc.v:105504.9-105504.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -163935,13 +166233,13 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:104644.1-105177.10" +attribute \src "libresoc.v:105521.1-106054.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \ALU_ALU__data_len + wire width 4 output 18 \ALU__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -163956,19 +166254,19 @@ module \dec_ALU attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \ALU_ALU__fn_unit + wire width 12 output 3 \ALU__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \ALU_ALU__imm_data__data + wire width 64 output 4 \ALU__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \ALU_ALU__imm_data__ok + wire output 5 \ALU__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \ALU_ALU__input_carry + wire width 2 output 14 \ALU__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \ALU_ALU__insn + wire width 32 output 19 \ALU__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -164044,60 +166342,60 @@ module \dec_ALU attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \ALU_ALU__insn_type + wire width 7 output 2 \ALU__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \ALU_ALU__invert_in + wire output 10 \ALU__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \ALU_ALU__invert_out + wire output 12 \ALU__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \ALU_ALU__is_32bit + wire output 16 \ALU__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \ALU_ALU__is_signed + wire output 17 \ALU__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \ALU_ALU__oe__oe + wire output 8 \ALU__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \ALU_ALU__oe__ok + wire output 9 \ALU__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \ALU_ALU__output_carry + wire output 15 \ALU__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \ALU_ALU__rc__ok + wire output 7 \ALU__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \ALU_ALU__rc__rc + wire output 6 \ALU__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \ALU_ALU__write_cr0 + wire output 13 \ALU__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 11 \ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -164107,7 +166405,7 @@ module \dec_ALU attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -164115,15 +166413,15 @@ module \dec_ALU attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_ALU_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -164138,7 +166436,7 @@ module \dec_ALU attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -164146,7 +166444,7 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -164163,7 +166461,7 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -164239,13 +166537,13 @@ module \dec_ALU attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -164253,25 +166551,25 @@ module \dec_ALU attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -164279,11 +166577,11 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -164300,9 +166598,9 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -164312,13 +166610,13 @@ module \dec_ALU attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -164326,38 +166624,38 @@ module \dec_ALU attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 20 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:105061.7-105098.4" + attribute \src "libresoc.v:105938.7-105975.4" cell \dec \dec connect \ALU_BA \dec_ALU_BA connect \ALU_BB \dec_ALU_BB @@ -164397,14 +166695,14 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105099.10-105103.4" + attribute \src "libresoc.v:105976.10-105980.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105104.10-105115.4" + attribute \src "libresoc.v:105981.10-105992.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -164418,7 +166716,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105116.13-105127.4" + attribute \src "libresoc.v:105993.13-106004.4" cell \dec_cr_in \dec_cr_in connect \ALU_BA \dec_ALU_BA connect \ALU_BB \dec_ALU_BB @@ -164432,7 +166730,7 @@ module \dec_ALU connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105128.14-105137.4" + attribute \src "libresoc.v:106005.14-106014.4" cell \dec_cr_out \dec_cr_out connect \ALU_FXM \dec_ALU_FXM connect \ALU_internal_op \dec_ALU_internal_op @@ -164444,7 +166742,7 @@ module \dec_ALU connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105138.10-105144.4" + attribute \src "libresoc.v:106015.10-106021.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -164453,29 +166751,29 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105145.10-105150.4" + attribute \src "libresoc.v:106022.10-106027.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \ALU_ALU__is_signed \dec_ALU_sgn - connect \ALU_ALU__is_32bit \dec_ALU_is_32b - connect \ALU_ALU__output_carry \dec_ALU_cry_out - connect \ALU_ALU__input_carry \dec_ALU_cry_in - connect \ALU_ALU__invert_out \dec_ALU_inv_out - connect \ALU_ALU__invert_in \dec_ALU_inv_a - connect \ALU_ALU__data_len \dec_ALU_ldst_len - connect \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \ALU__is_signed \dec_ALU_sgn + connect \ALU__is_32bit \dec_ALU_is_32b + connect \ALU__output_carry \dec_ALU_cry_out + connect \ALU__input_carry \dec_ALU_cry_in + connect \ALU__invert_out \dec_ALU_inv_out + connect \ALU__invert_in \dec_ALU_inv_a + connect \ALU__data_len \dec_ALU_ldst_len + connect \ALU__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_ALU_in2_sel - connect \ALU_ALU__zero_a \dec_ai_immz_out + connect \ALU__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_ALU_in1_sel - connect \ALU_ALU__fn_unit \dec_ALU_function_unit - connect \ALU_ALU__insn_type \dec_ALU_internal_op + connect \ALU__fn_unit \dec_ALU_function_unit + connect \ALU__insn_type \dec_ALU_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_ALU_cr_out connect \dec_cr_in_sel_in \dec_ALU_cr_in @@ -164485,21 +166783,21 @@ module \dec_ALU connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \ALU_ALU__insn \dec_opcode_in + connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:105181.1-105633.10" +attribute \src "libresoc.v:106058.1-106510.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:105607.3-105616.6" - wire $0\BRANCH_BRANCH__lk[0:0] - attribute \src "libresoc.v:105182.7-105182.20" + attribute \src "libresoc.v:106484.3-106493.6" + wire $0\BRANCH__lk[0:0] + attribute \src "libresoc.v:106059.7-106059.20" wire $0\initial[0:0] - attribute \src "libresoc.v:105607.3-105616.6" - wire $1\BRANCH_BRANCH__lk[0:0] + attribute \src "libresoc.v:106484.3-106493.6" + wire $1\BRANCH__lk[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 3 \BRANCH_BRANCH__cia + wire width 64 output 3 \BRANCH__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -164514,13 +166812,13 @@ module \dec_BRANCH attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 5 \BRANCH_BRANCH__fn_unit + wire width 12 output 5 \BRANCH__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \BRANCH_BRANCH__imm_data__data + wire width 64 output 7 \BRANCH__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \BRANCH_BRANCH__imm_data__ok + wire output 8 \BRANCH__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 6 \BRANCH_BRANCH__insn + wire width 32 output 6 \BRANCH__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -164596,44 +166894,44 @@ module \dec_BRANCH attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 4 \BRANCH_BRANCH__insn_type + wire width 7 output 4 \BRANCH__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \BRANCH_BRANCH__is_32bit + wire output 10 \BRANCH__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 9 \BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 2 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -164643,7 +166941,7 @@ module \dec_BRANCH attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -164651,7 +166949,7 @@ module \dec_BRANCH attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_BRANCH_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -164666,7 +166964,7 @@ module \dec_BRANCH attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -164683,7 +166981,7 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -164759,29 +167057,29 @@ module \dec_BRANCH attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -164798,9 +167096,9 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -164810,11 +167108,11 @@ module \dec_BRANCH attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -164822,35 +167120,35 @@ module \dec_BRANCH attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:105182.7-105182.15" + attribute \src "libresoc.v:106059.7-106059.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 1 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:105532.13-105563.4" - cell \dec$144 \dec + attribute \src "libresoc.v:106409.13-106440.4" + cell \dec$147 \dec connect \BRANCH_BA \dec_BRANCH_BA connect \BRANCH_BB \dec_BRANCH_BB connect \BRANCH_BC \dec_BRANCH_BC @@ -164883,8 +167181,8 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105564.16-105575.4" - cell \dec_bi$151 \dec_bi + attribute \src "libresoc.v:106441.16-106452.4" + cell \dec_bi$154 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS connect \BRANCH_LI \dec_BRANCH_LI @@ -164897,8 +167195,8 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105576.19-105587.4" - cell \dec_cr_in$147 \dec_cr_in + attribute \src "libresoc.v:106453.19-106464.4" + cell \dec_cr_in$150 \dec_cr_in connect \BRANCH_BA \dec_BRANCH_BA connect \BRANCH_BB \dec_BRANCH_BB connect \BRANCH_BC \dec_BRANCH_BC @@ -164911,8 +167209,8 @@ module \dec_BRANCH connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105588.20-105596.4" - cell \dec_cr_out$149 \dec_cr_out + attribute \src "libresoc.v:106465.20-106473.4" + cell \dec_cr_out$152 \dec_cr_out connect \BRANCH_FXM \dec_BRANCH_FXM connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \XL_BT \dec_XL_BT @@ -164922,56 +167220,56 @@ module \dec_BRANCH connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105597.16-105601.4" - cell \dec_oe$146 \dec_oe + attribute \src "libresoc.v:106474.16-106478.4" + cell \dec_oe$149 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105602.16-105606.4" - cell \dec_rc$145 \dec_rc + attribute \src "libresoc.v:106479.16-106483.4" + cell \dec_rc$148 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:105182.7-105182.20" - process $proc$libresoc.v:105182$4182 + attribute \src "libresoc.v:106059.7-106059.20" + process $proc$libresoc.v:106059$4263 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105607.3-105616.6" - process $proc$libresoc.v:105607$4181 + attribute \src "libresoc.v:106484.3-106493.6" + process $proc$libresoc.v:106484$4262 assign { } { } assign { } { } - assign $0\BRANCH_BRANCH__lk[0:0] $1\BRANCH_BRANCH__lk[0:0] - attribute \src "libresoc.v:105608.5-105608.29" + assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:106485.5-106485.29" switch \initial - attribute \src "libresoc.v:105608.9-105608.17" + attribute \src "libresoc.v:106485.9-106485.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:758" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\BRANCH_BRANCH__lk[0:0] \dec_BRANCH_LK + assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK case - assign $1\BRANCH_BRANCH__lk[0:0] 1'0 + assign $1\BRANCH__lk[0:0] 1'0 end sync always - update \BRANCH_BRANCH__lk $0\BRANCH_BRANCH__lk[0:0] + update \BRANCH__lk $0\BRANCH__lk[0:0] end - connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b - connect { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel - connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit - connect \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op - connect \BRANCH_BRANCH__cia \core_pc + connect \BRANCH__fn_unit \dec_BRANCH_function_unit + connect \BRANCH__insn_type \dec_BRANCH_internal_op + connect \BRANCH__cia \core_pc connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_BRANCH_cr_out connect \dec_cr_in_sel_in \dec_BRANCH_cr_in @@ -164981,11 +167279,11 @@ module \dec_BRANCH connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \BRANCH_BRANCH__insn \dec_opcode_in + connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:105637.1-105980.10" +attribute \src "libresoc.v:106514.1-106857.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR attribute \enum_base_type "Function" @@ -165002,9 +167300,9 @@ module \dec_CR attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \CR_CR__fn_unit + wire width 12 output 3 \CR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \CR_CR__insn + wire width 32 output 4 \CR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -165080,24 +167378,24 @@ module \dec_CR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \CR_CR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire width 7 output 2 \CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_CR_Rc attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -165107,7 +167405,7 @@ module \dec_CR attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165115,7 +167413,7 @@ module \dec_CR attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_CR_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -165130,7 +167428,7 @@ module \dec_CR attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -165206,21 +167504,21 @@ module \dec_CR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -165230,11 +167528,11 @@ module \dec_CR attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165242,33 +167540,33 @@ module \dec_CR attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 5 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:105916.13-105936.4" - cell \dec$137 \dec + attribute \src "libresoc.v:106793.13-106813.4" + cell \dec$140 \dec connect \CR_BA \dec_CR_BA connect \CR_BB \dec_CR_BB connect \CR_BC \dec_CR_BC @@ -165290,8 +167588,8 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105937.19-105948.4" - cell \dec_cr_in$140 \dec_cr_in + attribute \src "libresoc.v:106814.19-106825.4" + cell \dec_cr_in$143 \dec_cr_in connect \CR_BA \dec_CR_BA connect \CR_BB \dec_CR_BB connect \CR_BC \dec_CR_BC @@ -165304,8 +167602,8 @@ module \dec_CR connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105949.20-105957.4" - cell \dec_cr_out$142 \dec_cr_out + attribute \src "libresoc.v:106826.20-106834.4" + cell \dec_cr_out$145 \dec_cr_out connect \CR_FXM \dec_CR_FXM connect \CR_internal_op \dec_CR_internal_op connect \XL_BT \dec_XL_BT @@ -165315,21 +167613,21 @@ module \dec_CR connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105958.16-105962.4" - cell \dec_oe$139 \dec_oe + attribute \src "libresoc.v:106835.16-106839.4" + cell \dec_oe$142 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:105963.16-105967.4" - cell \dec_rc$138 \dec_rc + attribute \src "libresoc.v:106840.16-106844.4" + cell \dec_rc$141 \dec_rc connect \CR_Rc \dec_CR_Rc connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - connect \CR_CR__fn_unit \dec_CR_function_unit - connect \CR_CR__insn_type \dec_CR_internal_op + connect \CR__fn_unit \dec_CR_function_unit + connect \CR__insn_type \dec_CR_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_CR_cr_out connect \dec_cr_in_sel_in \dec_CR_cr_in @@ -165339,15 +167637,15 @@ module \dec_CR connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \CR_CR__insn \dec_opcode_in + connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:105984.1-106517.10" +attribute \src "libresoc.v:106861.1-107394.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \DIV_DIV__data_len + wire width 4 output 18 \DIV__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -165362,19 +167660,19 @@ module \dec_DIV attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \DIV_DIV__fn_unit + wire width 12 output 3 \DIV__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \DIV_DIV__imm_data__data + wire width 64 output 4 \DIV__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \DIV_DIV__imm_data__ok + wire output 5 \DIV__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \DIV_DIV__input_carry + wire width 2 output 12 \DIV__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \DIV_DIV__insn + wire width 32 output 19 \DIV__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -165450,60 +167748,60 @@ module \dec_DIV attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \DIV_DIV__insn_type + wire width 7 output 2 \DIV__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \DIV_DIV__invert_in + wire output 10 \DIV__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \DIV_DIV__invert_out + wire output 13 \DIV__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \DIV_DIV__is_32bit + wire output 16 \DIV__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \DIV_DIV__is_signed + wire output 17 \DIV__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \DIV_DIV__oe__oe + wire output 8 \DIV__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \DIV_DIV__oe__ok + wire output 9 \DIV__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \DIV_DIV__output_carry + wire output 15 \DIV__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \DIV_DIV__rc__ok + wire output 7 \DIV__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \DIV_DIV__rc__rc + wire output 6 \DIV__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \DIV_DIV__write_cr0 + wire output 14 \DIV__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \DIV_DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 11 \DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -165513,7 +167811,7 @@ module \dec_DIV attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165521,15 +167819,15 @@ module \dec_DIV attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_DIV_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -165544,7 +167842,7 @@ module \dec_DIV attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -165552,7 +167850,7 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -165569,7 +167867,7 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -165645,13 +167943,13 @@ module \dec_DIV attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -165659,25 +167957,25 @@ module \dec_DIV attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -165685,11 +167983,11 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -165706,9 +168004,9 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -165718,13 +168016,13 @@ module \dec_DIV attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -165732,39 +168030,39 @@ module \dec_DIV attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 20 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:106401.13-106438.4" - cell \dec$168 \dec + attribute \src "libresoc.v:107278.13-107315.4" + cell \dec$171 \dec connect \DIV_BA \dec_DIV_BA connect \DIV_BB \dec_DIV_BB connect \DIV_BC \dec_DIV_BC @@ -165803,15 +168101,15 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106439.16-106443.4" - cell \dec_ai$175 \dec_ai + attribute \src "libresoc.v:107316.16-107320.4" + cell \dec_ai$178 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106444.16-106455.4" - cell \dec_bi$176 \dec_bi + attribute \src "libresoc.v:107321.16-107332.4" + cell \dec_bi$179 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS connect \DIV_LI \dec_DIV_LI @@ -165824,8 +168122,8 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106456.19-106467.4" - cell \dec_cr_in$171 \dec_cr_in + attribute \src "libresoc.v:107333.19-107344.4" + cell \dec_cr_in$174 \dec_cr_in connect \DIV_BA \dec_DIV_BA connect \DIV_BB \dec_DIV_BB connect \DIV_BC \dec_DIV_BC @@ -165838,8 +168136,8 @@ module \dec_DIV connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106468.20-106477.4" - cell \dec_cr_out$173 \dec_cr_out + attribute \src "libresoc.v:107345.20-107354.4" + cell \dec_cr_out$176 \dec_cr_out connect \DIV_FXM \dec_DIV_FXM connect \DIV_internal_op \dec_DIV_internal_op connect \XL_BT \dec_XL_BT @@ -165850,8 +168148,8 @@ module \dec_DIV connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106478.16-106484.4" - cell \dec_oe$170 \dec_oe + attribute \src "libresoc.v:107355.16-107361.4" + cell \dec_oe$173 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op connect \oe \dec_oe_oe @@ -165859,29 +168157,29 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106485.16-106490.4" - cell \dec_rc$169 \dec_rc + attribute \src "libresoc.v:107362.16-107367.4" + cell \dec_rc$172 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \DIV_DIV__is_signed \dec_DIV_sgn - connect \DIV_DIV__is_32bit \dec_DIV_is_32b - connect \DIV_DIV__output_carry \dec_DIV_cry_out - connect \DIV_DIV__input_carry \dec_DIV_cry_in - connect \DIV_DIV__invert_out \dec_DIV_inv_out - connect \DIV_DIV__invert_in \dec_DIV_inv_a - connect \DIV_DIV__data_len \dec_DIV_ldst_len - connect \DIV_DIV__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \DIV_DIV__oe__ok \DIV_DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \DIV_DIV__rc__ok \DIV_DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \DIV_DIV__imm_data__ok \DIV_DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \DIV__is_signed \dec_DIV_sgn + connect \DIV__is_32bit \dec_DIV_is_32b + connect \DIV__output_carry \dec_DIV_cry_out + connect \DIV__input_carry \dec_DIV_cry_in + connect \DIV__invert_out \dec_DIV_inv_out + connect \DIV__invert_in \dec_DIV_inv_a + connect \DIV__data_len \dec_DIV_ldst_len + connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_DIV_in2_sel - connect \DIV_DIV__zero_a \dec_ai_immz_out + connect \DIV__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_DIV_in1_sel - connect \DIV_DIV__fn_unit \dec_DIV_function_unit - connect \DIV_DIV__insn_type \dec_DIV_internal_op + connect \DIV__fn_unit \dec_DIV_function_unit + connect \DIV__insn_type \dec_DIV_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_DIV_cr_out connect \dec_cr_in_sel_in \dec_DIV_cr_in @@ -165891,17 +168189,17 @@ module \dec_DIV connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \DIV_DIV__insn \dec_opcode_in + connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:106521.1-107044.10" +attribute \src "libresoc.v:107398.1-107921.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LDST_LDST__byte_reverse + wire output 14 \LDST__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 13 \LDST_LDST__data_len + wire width 4 output 13 \LDST__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -165916,13 +168214,13 @@ module \dec_LDST attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LDST_LDST__fn_unit + wire width 12 output 3 \LDST__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LDST_LDST__imm_data__data + wire width 64 output 4 \LDST__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LDST_LDST__imm_data__ok + wire output 5 \LDST__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \LDST_LDST__insn + wire width 32 output 17 \LDST__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -165998,63 +168296,63 @@ module \dec_LDST attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LDST_LDST__insn_type + wire width 7 output 2 \LDST__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LDST_LDST__is_32bit + wire output 11 \LDST__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \LDST_LDST__is_signed + wire output 12 \LDST__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 16 \LDST_LDST__ldst_mode + wire width 2 output 16 \LDST__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LDST_LDST__oe__oe + wire output 9 \LDST__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LDST_LDST__oe__ok + wire output 10 \LDST__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LDST_LDST__rc__ok + wire output 8 \LDST__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LDST_LDST__rc__rc + wire output 7 \LDST__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LDST_LDST__sign_extend + wire output 15 \LDST__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 6 \LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -166064,7 +168362,7 @@ module \dec_LDST attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -166072,7 +168370,7 @@ module \dec_LDST attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LDST_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -166087,7 +168385,7 @@ module \dec_LDST attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -166095,7 +168393,7 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -166112,7 +168410,7 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -166188,9 +168486,9 @@ module \dec_LDST attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -166198,34 +168496,34 @@ module \dec_LDST attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -166233,11 +168531,11 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -166254,9 +168552,9 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -166266,11 +168564,11 @@ module \dec_LDST attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -166278,39 +168576,39 @@ module \dec_LDST attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 18 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:106932.13-106968.4" - cell \dec$193 \dec + attribute \src "libresoc.v:107809.13-107845.4" + cell \dec$196 \dec connect \LDST_BA \dec_LDST_BA connect \LDST_BB \dec_LDST_BB connect \LDST_BC \dec_LDST_BC @@ -166348,15 +168646,15 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106969.16-106973.4" - cell \dec_ai$200 \dec_ai + attribute \src "libresoc.v:107846.16-107850.4" + cell \dec_ai$203 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106974.16-106985.4" - cell \dec_bi$201 \dec_bi + attribute \src "libresoc.v:107851.16-107862.4" + cell \dec_bi$204 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS connect \LDST_LI \dec_LDST_LI @@ -166369,8 +168667,8 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106986.19-106997.4" - cell \dec_cr_in$196 \dec_cr_in + attribute \src "libresoc.v:107863.19-107874.4" + cell \dec_cr_in$199 \dec_cr_in connect \LDST_BA \dec_LDST_BA connect \LDST_BB \dec_LDST_BB connect \LDST_BC \dec_LDST_BC @@ -166383,8 +168681,8 @@ module \dec_LDST connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:106998.20-107006.4" - cell \dec_cr_out$198 \dec_cr_out + attribute \src "libresoc.v:107875.20-107883.4" + cell \dec_cr_out$201 \dec_cr_out connect \LDST_FXM \dec_LDST_FXM connect \LDST_internal_op \dec_LDST_internal_op connect \XL_BT \dec_XL_BT @@ -166394,8 +168692,8 @@ module \dec_LDST connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107007.16-107013.4" - cell \dec_oe$195 \dec_oe + attribute \src "libresoc.v:107884.16-107890.4" + cell \dec_oe$198 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op connect \oe \dec_oe_oe @@ -166403,27 +168701,27 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107014.16-107019.4" - cell \dec_rc$194 \dec_rc + attribute \src "libresoc.v:107891.16-107896.4" + cell \dec_rc$197 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \LDST_LDST__ldst_mode \dec_LDST_upd - connect \LDST_LDST__sign_extend \dec_LDST_sgn_ext - connect \LDST_LDST__byte_reverse \dec_LDST_br - connect \LDST_LDST__is_signed \dec_LDST_sgn - connect \LDST_LDST__is_32bit \dec_LDST_is_32b - connect \LDST_LDST__data_len \dec_LDST_ldst_len - connect { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \LDST__ldst_mode \dec_LDST_upd + connect \LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST__byte_reverse \dec_LDST_br + connect \LDST__is_signed \dec_LDST_sgn + connect \LDST__is_32bit \dec_LDST_is_32b + connect \LDST__data_len \dec_LDST_ldst_len + connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_LDST_in2_sel - connect \LDST_LDST__zero_a \dec_ai_immz_out + connect \LDST__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LDST_in1_sel - connect \LDST_LDST__fn_unit \dec_LDST_function_unit - connect \LDST_LDST__insn_type \dec_LDST_internal_op + connect \LDST__fn_unit \dec_LDST_function_unit + connect \LDST__insn_type \dec_LDST_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_LDST_cr_out connect \dec_cr_in_sel_in \dec_LDST_cr_in @@ -166433,15 +168731,15 @@ module \dec_LDST connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \LDST_LDST__insn \dec_opcode_in + connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:107048.1-107581.10" +attribute \src "libresoc.v:107925.1-108458.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \LOGICAL_LOGICAL__data_len + wire width 4 output 18 \LOGICAL__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -166456,19 +168754,19 @@ module \dec_LOGICAL attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LOGICAL_LOGICAL__fn_unit + wire width 12 output 3 \LOGICAL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LOGICAL_LOGICAL__imm_data__data + wire width 64 output 4 \LOGICAL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LOGICAL_LOGICAL__imm_data__ok + wire output 5 \LOGICAL__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \LOGICAL_LOGICAL__input_carry + wire width 2 output 12 \LOGICAL__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \LOGICAL_LOGICAL__insn + wire width 32 output 19 \LOGICAL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -166544,60 +168842,60 @@ module \dec_LOGICAL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LOGICAL_LOGICAL__insn_type + wire width 7 output 2 \LOGICAL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LOGICAL_LOGICAL__invert_in + wire output 10 \LOGICAL__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \LOGICAL_LOGICAL__invert_out + wire output 13 \LOGICAL__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \LOGICAL_LOGICAL__is_32bit + wire output 16 \LOGICAL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \LOGICAL_LOGICAL__is_signed + wire output 17 \LOGICAL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LOGICAL_LOGICAL__oe__oe + wire output 8 \LOGICAL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LOGICAL_LOGICAL__oe__ok + wire output 9 \LOGICAL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LOGICAL_LOGICAL__output_carry + wire output 15 \LOGICAL__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LOGICAL_LOGICAL__rc__ok + wire output 7 \LOGICAL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LOGICAL_LOGICAL__rc__rc + wire output 6 \LOGICAL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LOGICAL_LOGICAL__write_cr0 + wire output 14 \LOGICAL__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LOGICAL_LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 11 \LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -166607,7 +168905,7 @@ module \dec_LOGICAL attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -166615,15 +168913,15 @@ module \dec_LOGICAL attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LOGICAL_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -166638,7 +168936,7 @@ module \dec_LOGICAL attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -166646,7 +168944,7 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -166663,7 +168961,7 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -166739,13 +169037,13 @@ module \dec_LOGICAL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" @@ -166753,25 +169051,25 @@ module \dec_LOGICAL attribute \enum_value_0010 "is2B" attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -166779,11 +169077,11 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -166800,9 +169098,9 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -166812,13 +169110,13 @@ module \dec_LOGICAL attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -166826,39 +169124,39 @@ module \dec_LOGICAL attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 20 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:107465.13-107502.4" - cell \dec$152 \dec + attribute \src "libresoc.v:108342.13-108379.4" + cell \dec$155 \dec connect \LOGICAL_BA \dec_LOGICAL_BA connect \LOGICAL_BB \dec_LOGICAL_BB connect \LOGICAL_BC \dec_LOGICAL_BC @@ -166897,15 +169195,15 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107503.16-107507.4" - cell \dec_ai$159 \dec_ai + attribute \src "libresoc.v:108380.16-108384.4" + cell \dec_ai$162 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107508.16-107519.4" - cell \dec_bi$160 \dec_bi + attribute \src "libresoc.v:108385.16-108396.4" + cell \dec_bi$163 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS connect \LOGICAL_LI \dec_LOGICAL_LI @@ -166918,8 +169216,8 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107520.19-107531.4" - cell \dec_cr_in$155 \dec_cr_in + attribute \src "libresoc.v:108397.19-108408.4" + cell \dec_cr_in$158 \dec_cr_in connect \LOGICAL_BA \dec_LOGICAL_BA connect \LOGICAL_BB \dec_LOGICAL_BB connect \LOGICAL_BC \dec_LOGICAL_BC @@ -166932,8 +169230,8 @@ module \dec_LOGICAL connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107532.20-107541.4" - cell \dec_cr_out$157 \dec_cr_out + attribute \src "libresoc.v:108409.20-108418.4" + cell \dec_cr_out$160 \dec_cr_out connect \LOGICAL_FXM \dec_LOGICAL_FXM connect \LOGICAL_internal_op \dec_LOGICAL_internal_op connect \XL_BT \dec_XL_BT @@ -166944,8 +169242,8 @@ module \dec_LOGICAL connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107542.16-107548.4" - cell \dec_oe$154 \dec_oe + attribute \src "libresoc.v:108419.16-108425.4" + cell \dec_oe$157 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op connect \oe \dec_oe_oe @@ -166953,29 +169251,29 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107549.16-107554.4" - cell \dec_rc$153 \dec_rc + attribute \src "libresoc.v:108426.16-108431.4" + cell \dec_rc$156 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_sgn - connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_is_32b - connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_cry_out - connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_cry_in - connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_inv_out - connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_inv_a - connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_ldst_len - connect \LOGICAL_LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \LOGICAL_LOGICAL__oe__ok \LOGICAL_LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LOGICAL_LOGICAL__rc__ok \LOGICAL_LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LOGICAL_LOGICAL__imm_data__ok \LOGICAL_LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL__data_len \dec_LOGICAL_ldst_len + connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_LOGICAL_in2_sel - connect \LOGICAL_LOGICAL__zero_a \dec_ai_immz_out + connect \LOGICAL__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LOGICAL_in1_sel - connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_function_unit - connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_internal_op + connect \LOGICAL__fn_unit \dec_LOGICAL_function_unit + connect \LOGICAL__insn_type \dec_LOGICAL_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in @@ -166985,11 +169283,11 @@ module \dec_LOGICAL connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \LOGICAL_LOGICAL__insn \dec_opcode_in + connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:107585.1-108043.10" +attribute \src "libresoc.v:108462.1-108920.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL attribute \enum_base_type "Function" @@ -167006,13 +169304,13 @@ module \dec_MUL attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \MUL_MUL__fn_unit + wire width 12 output 3 \MUL__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \MUL_MUL__imm_data__data + wire width 64 output 4 \MUL__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \MUL_MUL__imm_data__ok + wire output 5 \MUL__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \MUL_MUL__insn + wire width 32 output 13 \MUL__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -167088,50 +169386,50 @@ module \dec_MUL attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \MUL_MUL__insn_type + wire width 7 output 2 \MUL__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \MUL_MUL__is_32bit + wire output 11 \MUL__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \MUL_MUL__is_signed + wire output 12 \MUL__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \MUL_MUL__oe__oe + wire output 8 \MUL__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \MUL_MUL__oe__ok + wire output 9 \MUL__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \MUL_MUL__rc__ok + wire output 7 \MUL__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \MUL_MUL__rc__rc + wire output 6 \MUL__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 10 \MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -167141,7 +169439,7 @@ module \dec_MUL attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167149,7 +169447,7 @@ module \dec_MUL attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_MUL_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -167164,7 +169462,7 @@ module \dec_MUL attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167181,7 +169479,7 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -167257,29 +169555,29 @@ module \dec_MUL attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167296,9 +169594,9 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -167308,13 +169606,13 @@ module \dec_MUL attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167322,39 +169620,39 @@ module \dec_MUL attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 14 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:107946.13-107976.4" - cell \dec$177 \dec + attribute \src "libresoc.v:108823.13-108853.4" + cell \dec$180 \dec connect \MUL_BA \dec_MUL_BA connect \MUL_BB \dec_MUL_BB connect \MUL_BC \dec_MUL_BC @@ -167386,8 +169684,8 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107977.16-107988.4" - cell \dec_bi$184 \dec_bi + attribute \src "libresoc.v:108854.16-108865.4" + cell \dec_bi$187 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS connect \MUL_LI \dec_MUL_LI @@ -167400,8 +169698,8 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:107989.19-108000.4" - cell \dec_cr_in$180 \dec_cr_in + attribute \src "libresoc.v:108866.19-108877.4" + cell \dec_cr_in$183 \dec_cr_in connect \MUL_BA \dec_MUL_BA connect \MUL_BB \dec_MUL_BB connect \MUL_BC \dec_MUL_BC @@ -167414,8 +169712,8 @@ module \dec_MUL connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108001.20-108010.4" - cell \dec_cr_out$182 \dec_cr_out + attribute \src "libresoc.v:108878.20-108887.4" + cell \dec_cr_out$185 \dec_cr_out connect \MUL_FXM \dec_MUL_FXM connect \MUL_internal_op \dec_MUL_internal_op connect \XL_BT \dec_XL_BT @@ -167426,8 +169724,8 @@ module \dec_MUL connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108011.16-108017.4" - cell \dec_oe$179 \dec_oe + attribute \src "libresoc.v:108888.16-108894.4" + cell \dec_oe$182 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op connect \oe \dec_oe_oe @@ -167435,22 +169733,22 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108018.16-108023.4" - cell \dec_rc$178 \dec_rc + attribute \src "libresoc.v:108895.16-108900.4" + cell \dec_rc$181 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \MUL_MUL__is_signed \dec_MUL_sgn - connect \MUL_MUL__is_32bit \dec_MUL_is_32b - connect \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \MUL__is_signed \dec_MUL_sgn + connect \MUL__is_32bit \dec_MUL_is_32b + connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_MUL_in2_sel - connect \MUL_MUL__fn_unit \dec_MUL_function_unit - connect \MUL_MUL__insn_type \dec_MUL_internal_op + connect \MUL__fn_unit \dec_MUL_function_unit + connect \MUL__insn_type \dec_MUL_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_MUL_cr_out connect \dec_cr_in_sel_in \dec_MUL_cr_in @@ -167460,11 +169758,11 @@ module \dec_MUL connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \MUL_MUL__insn \dec_opcode_in + connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:108047.1-108531.10" +attribute \src "libresoc.v:108924.1-109414.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT attribute \enum_base_type "Function" @@ -167481,21 +169779,21 @@ module \dec_SHIFT_ROT attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit + wire width 12 output 3 \SHIFT_ROT__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data + wire width 64 output 4 \SHIFT_ROT__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok + wire output 5 \SHIFT_ROT__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry + wire width 2 output 12 \SHIFT_ROT__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \SHIFT_ROT_SHIFT_ROT__input_cr + wire output 14 \SHIFT_ROT__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn + wire width 32 output 18 \SHIFT_ROT__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -167571,54 +169869,56 @@ module \dec_SHIFT_ROT attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type + wire width 7 output 2 \SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \SHIFT_ROT__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit + wire output 16 \SHIFT_ROT__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \SHIFT_ROT_SHIFT_ROT__is_signed + wire output 17 \SHIFT_ROT__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe + wire output 8 \SHIFT_ROT__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok + wire output 9 \SHIFT_ROT__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \SHIFT_ROT_SHIFT_ROT__output_carry + wire output 13 \SHIFT_ROT__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \SHIFT_ROT_SHIFT_ROT__output_cr + wire output 15 \SHIFT_ROT__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok + wire output 7 \SHIFT_ROT__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc + wire output 6 \SHIFT_ROT__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 10 \SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 \dec_SHIFT_ROT_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -167628,7 +169928,7 @@ module \dec_SHIFT_ROT attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167636,15 +169936,15 @@ module \dec_SHIFT_ROT attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_SHIFT_ROT_cry_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -167659,7 +169959,7 @@ module \dec_SHIFT_ROT attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167676,7 +169976,7 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 4 \dec_SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -167752,29 +170052,31 @@ module \dec_SHIFT_ROT attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_SHIFT_ROT_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_bi_imm_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -167791,9 +170093,9 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -167803,13 +170105,13 @@ module \dec_SHIFT_ROT attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -167817,39 +170119,39 @@ module \dec_SHIFT_ROT attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" - wire width 32 input 18 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 19 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:108428.13-108460.4" - cell \dec$185 \dec + attribute \src "libresoc.v:109309.13-109342.4" + cell \dec$188 \dec connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC @@ -167871,6 +170173,7 @@ module \dec_SHIFT_ROT connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn @@ -167883,8 +170186,8 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108461.16-108472.4" - cell \dec_bi$192 \dec_bi + attribute \src "libresoc.v:109343.16-109354.4" + cell \dec_bi$195 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI @@ -167897,8 +170200,8 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108473.19-108484.4" - cell \dec_cr_in$188 \dec_cr_in + attribute \src "libresoc.v:109355.19-109366.4" + cell \dec_cr_in$191 \dec_cr_in connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC @@ -167911,8 +170214,8 @@ module \dec_SHIFT_ROT connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108485.20-108494.4" - cell \dec_cr_out$190 \dec_cr_out + attribute \src "libresoc.v:109367.20-109376.4" + cell \dec_cr_out$193 \dec_cr_out connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op connect \XL_BT \dec_XL_BT @@ -167923,8 +170226,8 @@ module \dec_SHIFT_ROT connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108495.16-108501.4" - cell \dec_oe$187 \dec_oe + attribute \src "libresoc.v:109377.16-109383.4" + cell \dec_oe$190 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op connect \oe \dec_oe_oe @@ -167932,26 +170235,27 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108502.16-108507.4" - cell \dec_rc$186 \dec_rc + attribute \src "libresoc.v:109384.16-109389.4" + cell \dec_rc$189 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] - connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in @@ -167961,11 +170265,11 @@ module \dec_SHIFT_ROT connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in + connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:108535.1-108884.10" +attribute \src "libresoc.v:109418.1-109767.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR attribute \enum_base_type "Function" @@ -167982,9 +170286,9 @@ module \dec_SPR attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SPR_SPR__fn_unit + wire width 12 output 3 \SPR__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \SPR_SPR__insn + wire width 32 output 4 \SPR__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -168060,26 +170364,26 @@ module \dec_SPR attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SPR_SPR__insn_type + wire width 7 output 2 \SPR__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire output 5 \SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 \dec_SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 \dec_SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire \dec_SPR_Rc attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -168089,7 +170393,7 @@ module \dec_SPR attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -168097,7 +170401,7 @@ module \dec_SPR attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 3 \dec_SPR_cr_out attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -168112,7 +170416,7 @@ module \dec_SPR attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 12 \dec_SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -168188,23 +170492,23 @@ module \dec_SPR attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 \dec_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" wire \dec_SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 \dec_SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -168214,11 +170518,11 @@ module \dec_SPR attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -168226,33 +170530,33 @@ module \dec_SPR attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 input 6 \raw_opcode_in attribute \module_not_derived 1 - attribute \src "libresoc.v:108818.13-108839.4" - cell \dec$161 \dec + attribute \src "libresoc.v:109701.13-109722.4" + cell \dec$164 \dec connect \SPR_BA \dec_SPR_BA connect \SPR_BB \dec_SPR_BB connect \SPR_BC \dec_SPR_BC @@ -168275,8 +170579,8 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108840.19-108851.4" - cell \dec_cr_in$164 \dec_cr_in + attribute \src "libresoc.v:109723.19-109734.4" + cell \dec_cr_in$167 \dec_cr_in connect \SPR_BA \dec_SPR_BA connect \SPR_BB \dec_SPR_BB connect \SPR_BC \dec_SPR_BC @@ -168289,8 +170593,8 @@ module \dec_SPR connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108852.20-108860.4" - cell \dec_cr_out$166 \dec_cr_out + attribute \src "libresoc.v:109735.20-109743.4" + cell \dec_cr_out$169 \dec_cr_out connect \SPR_FXM \dec_SPR_FXM connect \SPR_internal_op \dec_SPR_internal_op connect \XL_BT \dec_XL_BT @@ -168300,22 +170604,22 @@ module \dec_SPR connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108861.16-108865.4" - cell \dec_oe$163 \dec_oe + attribute \src "libresoc.v:109744.16-109748.4" + cell \dec_oe$166 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:108866.16-108870.4" - cell \dec_rc$162 \dec_rc + attribute \src "libresoc.v:109749.16-109753.4" + cell \dec_rc$165 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - connect \SPR_SPR__is_32bit \dec_SPR_is_32b - connect \SPR_SPR__fn_unit \dec_SPR_function_unit - connect \SPR_SPR__insn_type \dec_SPR_internal_op + connect \SPR__is_32bit \dec_SPR_is_32b + connect \SPR__fn_unit \dec_SPR_function_unit + connect \SPR__insn_type \dec_SPR_internal_op connect \dec_cr_out_rc_in \dec_rc_rc connect \dec_cr_out_sel_in \dec_SPR_cr_out connect \dec_cr_in_sel_in \dec_SPR_cr_in @@ -168325,134 +170629,134 @@ module \dec_SPR connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in - connect \SPR_SPR__insn \dec_opcode_in + connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:108888.1-109393.10" +attribute \src "libresoc.v:109771.1-110276.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_a" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:108889.7-108889.20" + attribute \src "libresoc.v:109772.7-109772.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109290.3-109305.6" + attribute \src "libresoc.v:110173.3-110188.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:109306.3-109321.6" + attribute \src "libresoc.v:110189.3-110204.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:109358.3-109368.6" + attribute \src "libresoc.v:110241.3-110251.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:109380.3-109391.6" + attribute \src "libresoc.v:110263.3-110274.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:109380.3-109391.6" + attribute \src "libresoc.v:110263.3-110274.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:109369.3-109379.6" + attribute \src "libresoc.v:110252.3-110262.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:109290.3-109305.6" + attribute \src "libresoc.v:110173.3-110188.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:109306.3-109321.6" + attribute \src "libresoc.v:110189.3-110204.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:109358.3-109368.6" + attribute \src "libresoc.v:110241.3-110251.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:109380.3-109391.6" + attribute \src "libresoc.v:110263.3-110274.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:109380.3-109391.6" + attribute \src "libresoc.v:110263.3-110274.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:109369.3-109379.6" + attribute \src "libresoc.v:110252.3-110262.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:109290.3-109305.6" + attribute \src "libresoc.v:110173.3-110188.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:109306.3-109321.6" + attribute \src "libresoc.v:110189.3-110204.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:109322.3-109357.6" + attribute \src "libresoc.v:110205.3-110240.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:109274.18-109274.110" - wire $and$libresoc.v:109274$4189_Y - attribute \src "libresoc.v:109279.18-109279.113" - wire $and$libresoc.v:109279$4194_Y - attribute \src "libresoc.v:109282.17-109282.107" - wire $and$libresoc.v:109282$4197_Y - attribute \src "libresoc.v:109269.18-109269.112" - wire $eq$libresoc.v:109269$4184_Y - attribute \src "libresoc.v:109270.18-109270.111" - wire $eq$libresoc.v:109270$4185_Y - attribute \src "libresoc.v:109271.18-109271.112" - wire $eq$libresoc.v:109271$4186_Y - attribute \src "libresoc.v:109273.17-109273.110" - wire $eq$libresoc.v:109273$4188_Y - attribute \src "libresoc.v:109276.18-109276.112" - wire $eq$libresoc.v:109276$4191_Y - attribute \src "libresoc.v:109280.17-109280.111" - wire $eq$libresoc.v:109280$4195_Y - attribute \src "libresoc.v:109272.18-109272.109" - wire $ne$libresoc.v:109272$4187_Y - attribute \src "libresoc.v:109281.17-109281.108" - wire $ne$libresoc.v:109281$4196_Y - attribute \src "libresoc.v:109277.18-109277.105" - wire $not$libresoc.v:109277$4192_Y - attribute \src "libresoc.v:109278.18-109278.108" - wire $not$libresoc.v:109278$4193_Y - attribute \src "libresoc.v:109268.17-109268.107" - wire $or$libresoc.v:109268$4183_Y - attribute \src "libresoc.v:109275.18-109275.110" - wire $or$libresoc.v:109275$4190_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "libresoc.v:110157.18-110157.110" + wire $and$libresoc.v:110157$4270_Y + attribute \src "libresoc.v:110162.18-110162.113" + wire $and$libresoc.v:110162$4275_Y + attribute \src "libresoc.v:110165.17-110165.107" + wire $and$libresoc.v:110165$4278_Y + attribute \src "libresoc.v:110152.18-110152.112" + wire $eq$libresoc.v:110152$4265_Y + attribute \src "libresoc.v:110153.18-110153.112" + wire $eq$libresoc.v:110153$4266_Y + attribute \src "libresoc.v:110154.18-110154.112" + wire $eq$libresoc.v:110154$4267_Y + attribute \src "libresoc.v:110156.17-110156.111" + wire $eq$libresoc.v:110156$4269_Y + attribute \src "libresoc.v:110159.18-110159.112" + wire $eq$libresoc.v:110159$4272_Y + attribute \src "libresoc.v:110163.17-110163.111" + wire $eq$libresoc.v:110163$4276_Y + attribute \src "libresoc.v:110155.18-110155.109" + wire $ne$libresoc.v:110155$4268_Y + attribute \src "libresoc.v:110164.17-110164.108" + wire $ne$libresoc.v:110164$4277_Y + attribute \src "libresoc.v:110160.18-110160.105" + wire $not$libresoc.v:110160$4273_Y + attribute \src "libresoc.v:110161.18-110161.108" + wire $not$libresoc.v:110161$4274_Y + attribute \src "libresoc.v:110151.17-110151.107" + wire $or$libresoc.v:110151$4264_Y + attribute \src "libresoc.v:110158.18-110158.110" + wire $or$libresoc.v:110158$4271_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 input 12 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \fast_a_ok - attribute \src "libresoc.v:108889.7-108889.15" + attribute \src "libresoc.v:109772.7-109772.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -168528,13 +170832,13 @@ module \dec_a attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 13 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire width 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \reg_a_ok attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -168542,9 +170846,9 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -168657,15 +170961,15 @@ module \dec_a attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 4 \spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -168778,12 +171082,12 @@ module \dec_a attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $and $and$libresoc.v:109274$4189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:110157$4270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -168791,10 +171095,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $and$libresoc.v:109274$4189_Y + connect \Y $and$libresoc.v:110157$4270_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $and $and$libresoc.v:109279$4194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $and $and$libresoc.v:110162$4275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -168802,10 +171106,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$27 - connect \Y $and$libresoc.v:109279$4194_Y + connect \Y $and$libresoc.v:110162$4275_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $and $and$libresoc.v:109282$4197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:110165$4278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -168813,10 +171117,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:109282$4197_Y + connect \Y $and$libresoc.v:110165$4278_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - cell $eq $eq$libresoc.v:109269$4184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:110152$4265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168824,10 +171128,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:109269$4184_Y + connect \Y $eq$libresoc.v:110152$4265_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $eq$libresoc.v:109270$4185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:110153$4266 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168835,10 +171139,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:109270$4185_Y + connect \Y $eq$libresoc.v:110153$4266_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $eq$libresoc.v:109271$4186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:110154$4267 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168846,10 +171150,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109271$4186_Y + connect \Y $eq$libresoc.v:110154$4267_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $eq$libresoc.v:109273$4188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:110156$4269 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168857,10 +171161,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:109273$4188_Y + connect \Y $eq$libresoc.v:110156$4269_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - cell $eq $eq$libresoc.v:109276$4191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:110159$4272 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168868,10 +171172,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:109276$4191_Y + connect \Y $eq$libresoc.v:110159$4272_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $eq$libresoc.v:109280$4195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:110163$4276 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -168879,10 +171183,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109280$4195_Y + connect \Y $eq$libresoc.v:110163$4276_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $ne $ne$libresoc.v:109272$4187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:110155$4268 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -168890,10 +171194,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:109272$4187_Y + connect \Y $ne$libresoc.v:110155$4268_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $ne $ne$libresoc.v:109281$4196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:110164$4277 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -168901,26 +171205,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:109281$4196_Y + connect \Y $ne$libresoc.v:110164$4277_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - cell $not $not$libresoc.v:109277$4192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + cell $not $not$libresoc.v:110160$4273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:109277$4192_Y + connect \Y $not$libresoc.v:110160$4273_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $not $not$libresoc.v:109278$4193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $not $not$libresoc.v:110161$4274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:109278$4193_Y + connect \Y $not$libresoc.v:110161$4274_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $or $or$libresoc.v:109268$4183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:110151$4264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -168928,10 +171232,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$7 - connect \Y $or$libresoc.v:109268$4183_Y + connect \Y $or$libresoc.v:110151$4264_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $or $or$libresoc.v:109275$4190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:110158$4271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -168939,10 +171243,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$13 connect \B \$19 - connect \Y $or$libresoc.v:109275$4190_Y + connect \Y $or$libresoc.v:110158$4271_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:109283.10-109289.4" + attribute \src "libresoc.v:110166.10-110172.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -168950,27 +171254,27 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:108889.7-108889.20" - process $proc$libresoc.v:108889$4204 + attribute \src "libresoc.v:109772.7-109772.20" + process $proc$libresoc.v:109772$4285 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109290.3-109305.6" - process $proc$libresoc.v:109290$4198 + attribute \src "libresoc.v:110173.3-110188.6" + process $proc$libresoc.v:110173$4279 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:109291.5-109291.29" + attribute \src "libresoc.v:110174.5-110174.29" switch \initial - attribute \src "libresoc.v:109291.9-109291.17" + attribute \src "libresoc.v:110174.9-110174.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -168979,7 +171283,7 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -168991,19 +171295,19 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:109306.3-109321.6" - process $proc$libresoc.v:109306$4199 + attribute \src "libresoc.v:110189.3-110204.6" + process $proc$libresoc.v:110189$4280 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:109307.5-109307.29" + attribute \src "libresoc.v:110190.5-110190.29" switch \initial - attribute \src "libresoc.v:109307.9-109307.17" + attribute \src "libresoc.v:110190.9-110190.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169012,7 +171316,7 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169024,21 +171328,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:109322.3-109357.6" - process $proc$libresoc.v:109322$4200 + attribute \src "libresoc.v:110205.3-110240.6" + process $proc$libresoc.v:110205$4281 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:109323.5-109323.29" + attribute \src "libresoc.v:110206.5-110206.29" switch \initial - attribute \src "libresoc.v:109323.9-109323.17" + attribute \src "libresoc.v:110206.9-110206.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -169046,7 +171350,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169064,7 +171368,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169089,18 +171393,18 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:109358.3-109368.6" - process $proc$libresoc.v:109358$4201 + attribute \src "libresoc.v:110241.3-110251.6" + process $proc$libresoc.v:110241$4282 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:109359.5-109359.29" + attribute \src "libresoc.v:110242.5-110242.29" switch \initial - attribute \src "libresoc.v:109359.9-109359.17" + attribute \src "libresoc.v:110242.9-110242.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -169112,18 +171416,18 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:109369.3-109379.6" - process $proc$libresoc.v:109369$4202 + attribute \src "libresoc.v:110252.3-110262.6" + process $proc$libresoc.v:110252$4283 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:109370.5-109370.29" + attribute \src "libresoc.v:110253.5-110253.29" switch \initial - attribute \src "libresoc.v:109370.9-109370.17" + attribute \src "libresoc.v:110253.9-110253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -169135,21 +171439,21 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:109380.3-109391.6" - process $proc$libresoc.v:109380$4203 + attribute \src "libresoc.v:110263.3-110274.6" + process $proc$libresoc.v:110263$4284 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:109381.5-109381.29" + attribute \src "libresoc.v:110264.5-110264.29" switch \initial - attribute \src "libresoc.v:109381.9-109381.17" + attribute \src "libresoc.v:110264.9-110264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -169164,53 +171468,53 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:109268$4183_Y - connect \$11 $eq$libresoc.v:109269$4184_Y - connect \$13 $eq$libresoc.v:109270$4185_Y - connect \$15 $eq$libresoc.v:109271$4186_Y - connect \$17 $ne$libresoc.v:109272$4187_Y - connect \$1 $eq$libresoc.v:109273$4188_Y - connect \$19 $and$libresoc.v:109274$4189_Y - connect \$21 $or$libresoc.v:109275$4190_Y - connect \$23 $eq$libresoc.v:109276$4191_Y - connect \$25 $not$libresoc.v:109277$4192_Y - connect \$27 $not$libresoc.v:109278$4193_Y - connect \$29 $and$libresoc.v:109279$4194_Y - connect \$3 $eq$libresoc.v:109280$4195_Y - connect \$5 $ne$libresoc.v:109281$4196_Y - connect \$7 $and$libresoc.v:109282$4197_Y + connect \$9 $or$libresoc.v:110151$4264_Y + connect \$11 $eq$libresoc.v:110152$4265_Y + connect \$13 $eq$libresoc.v:110153$4266_Y + connect \$15 $eq$libresoc.v:110154$4267_Y + connect \$17 $ne$libresoc.v:110155$4268_Y + connect \$1 $eq$libresoc.v:110156$4269_Y + connect \$19 $and$libresoc.v:110157$4270_Y + connect \$21 $or$libresoc.v:110158$4271_Y + connect \$23 $eq$libresoc.v:110159$4272_Y + connect \$25 $not$libresoc.v:110160$4273_Y + connect \$27 $not$libresoc.v:110161$4274_Y + connect \$29 $and$libresoc.v:110162$4275_Y + connect \$3 $eq$libresoc.v:110163$4276_Y + connect \$5 $ne$libresoc.v:110164$4277_Y + connect \$7 $and$libresoc.v:110165$4278_Y connect \ra \RA end -attribute \src "libresoc.v:109397.1-109434.10" +attribute \src "libresoc.v:110280.1-110317.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_ai" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:109423.3-109432.6" + attribute \src "libresoc.v:110306.3-110315.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:109398.7-109398.20" + attribute \src "libresoc.v:110281.7-110281.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109423.3-109432.6" + attribute \src "libresoc.v:110306.3-110315.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:109422.17-109422.107" - wire $and$libresoc.v:109422$4207_Y - attribute \src "libresoc.v:109420.17-109420.111" - wire $eq$libresoc.v:109420$4205_Y - attribute \src "libresoc.v:109421.17-109421.108" - wire $eq$libresoc.v:109421$4206_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "libresoc.v:110305.17-110305.107" + wire $and$libresoc.v:110305$4288_Y + attribute \src "libresoc.v:110303.17-110303.111" + wire $eq$libresoc.v:110303$4286_Y + attribute \src "libresoc.v:110304.17-110304.108" + wire $eq$libresoc.v:110304$4287_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire output 1 \immz_out - attribute \src "libresoc.v:109398.7-109398.15" + attribute \src "libresoc.v:110281.7-110281.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169218,10 +171522,10 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$libresoc.v:109422$4207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110305$4288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -169229,10 +171533,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:109422$4207_Y + connect \Y $and$libresoc.v:110305$4288_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109420$4205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110303$4286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -169240,10 +171544,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109420$4205_Y + connect \Y $eq$libresoc.v:110303$4286_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109421$4206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110304$4287 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -169251,28 +171555,28 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:109421$4206_Y + connect \Y $eq$libresoc.v:110304$4287_Y end - attribute \src "libresoc.v:109398.7-109398.20" - process $proc$libresoc.v:109398$4209 + attribute \src "libresoc.v:110281.7-110281.20" + process $proc$libresoc.v:110281$4290 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109423.3-109432.6" - process $proc$libresoc.v:109423$4208 + attribute \src "libresoc.v:110306.3-110315.6" + process $proc$libresoc.v:110306$4289 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:109424.5-109424.29" + attribute \src "libresoc.v:110307.5-110307.29" switch \initial - attribute \src "libresoc.v:109424.9-109424.17" + attribute \src "libresoc.v:110307.9-110307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169284,41 +171588,41 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:109420$4205_Y - connect \$3 $eq$libresoc.v:109421$4206_Y - connect \$5 $and$libresoc.v:109422$4207_Y + connect \$1 $eq$libresoc.v:110303$4286_Y + connect \$3 $eq$libresoc.v:110304$4287_Y + connect \$5 $and$libresoc.v:110305$4288_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:109438.1-109475.10" +attribute \src "libresoc.v:110321.1-110358.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" -module \dec_ai$159 - attribute \src "libresoc.v:109464.3-109473.6" +module \dec_ai$162 + attribute \src "libresoc.v:110347.3-110356.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:109439.7-109439.20" + attribute \src "libresoc.v:110322.7-110322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109464.3-109473.6" + attribute \src "libresoc.v:110347.3-110356.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:109463.17-109463.107" - wire $and$libresoc.v:109463$4212_Y - attribute \src "libresoc.v:109461.17-109461.111" - wire $eq$libresoc.v:109461$4210_Y - attribute \src "libresoc.v:109462.17-109462.108" - wire $eq$libresoc.v:109462$4211_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "libresoc.v:110346.17-110346.107" + wire $and$libresoc.v:110346$4293_Y + attribute \src "libresoc.v:110344.17-110344.111" + wire $eq$libresoc.v:110344$4291_Y + attribute \src "libresoc.v:110345.17-110345.108" + wire $eq$libresoc.v:110345$4292_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire output 1 \immz_out - attribute \src "libresoc.v:109439.7-109439.15" + attribute \src "libresoc.v:110322.7-110322.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169326,10 +171630,10 @@ module \dec_ai$159 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$libresoc.v:109463$4212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110346$4293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -169337,10 +171641,10 @@ module \dec_ai$159 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:109463$4212_Y + connect \Y $and$libresoc.v:110346$4293_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109461$4210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110344$4291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -169348,10 +171652,10 @@ module \dec_ai$159 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109461$4210_Y + connect \Y $eq$libresoc.v:110344$4291_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109462$4211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110345$4292 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -169359,28 +171663,28 @@ module \dec_ai$159 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:109462$4211_Y + connect \Y $eq$libresoc.v:110345$4292_Y end - attribute \src "libresoc.v:109439.7-109439.20" - process $proc$libresoc.v:109439$4214 + attribute \src "libresoc.v:110322.7-110322.20" + process $proc$libresoc.v:110322$4295 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109464.3-109473.6" - process $proc$libresoc.v:109464$4213 + attribute \src "libresoc.v:110347.3-110356.6" + process $proc$libresoc.v:110347$4294 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:109465.5-109465.29" + attribute \src "libresoc.v:110348.5-110348.29" switch \initial - attribute \src "libresoc.v:109465.9-109465.17" + attribute \src "libresoc.v:110348.9-110348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169392,41 +171696,41 @@ module \dec_ai$159 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:109461$4210_Y - connect \$3 $eq$libresoc.v:109462$4211_Y - connect \$5 $and$libresoc.v:109463$4212_Y + connect \$1 $eq$libresoc.v:110344$4291_Y + connect \$3 $eq$libresoc.v:110345$4292_Y + connect \$5 $and$libresoc.v:110346$4293_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:109479.1-109516.10" +attribute \src "libresoc.v:110362.1-110399.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_ai" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" -module \dec_ai$175 - attribute \src "libresoc.v:109505.3-109514.6" +module \dec_ai$178 + attribute \src "libresoc.v:110388.3-110397.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:109480.7-109480.20" + attribute \src "libresoc.v:110363.7-110363.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109505.3-109514.6" + attribute \src "libresoc.v:110388.3-110397.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:109504.17-109504.107" - wire $and$libresoc.v:109504$4217_Y - attribute \src "libresoc.v:109502.17-109502.111" - wire $eq$libresoc.v:109502$4215_Y - attribute \src "libresoc.v:109503.17-109503.108" - wire $eq$libresoc.v:109503$4216_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "libresoc.v:110387.17-110387.107" + wire $and$libresoc.v:110387$4298_Y + attribute \src "libresoc.v:110385.17-110385.111" + wire $eq$libresoc.v:110385$4296_Y + attribute \src "libresoc.v:110386.17-110386.108" + wire $eq$libresoc.v:110386$4297_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire output 1 \immz_out - attribute \src "libresoc.v:109480.7-109480.15" + attribute \src "libresoc.v:110363.7-110363.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169434,10 +171738,10 @@ module \dec_ai$175 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$libresoc.v:109504$4217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110387$4298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -169445,10 +171749,10 @@ module \dec_ai$175 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:109504$4217_Y + connect \Y $and$libresoc.v:110387$4298_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109502$4215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110385$4296 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -169456,10 +171760,10 @@ module \dec_ai$175 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109502$4215_Y + connect \Y $eq$libresoc.v:110385$4296_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109503$4216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110386$4297 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -169467,28 +171771,28 @@ module \dec_ai$175 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:109503$4216_Y + connect \Y $eq$libresoc.v:110386$4297_Y end - attribute \src "libresoc.v:109480.7-109480.20" - process $proc$libresoc.v:109480$4219 + attribute \src "libresoc.v:110363.7-110363.20" + process $proc$libresoc.v:110363$4300 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109505.3-109514.6" - process $proc$libresoc.v:109505$4218 + attribute \src "libresoc.v:110388.3-110397.6" + process $proc$libresoc.v:110388$4299 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:109506.5-109506.29" + attribute \src "libresoc.v:110389.5-110389.29" switch \initial - attribute \src "libresoc.v:109506.9-109506.17" + attribute \src "libresoc.v:110389.9-110389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169500,41 +171804,41 @@ module \dec_ai$175 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:109502$4215_Y - connect \$3 $eq$libresoc.v:109503$4216_Y - connect \$5 $and$libresoc.v:109504$4217_Y + connect \$1 $eq$libresoc.v:110385$4296_Y + connect \$3 $eq$libresoc.v:110386$4297_Y + connect \$5 $and$libresoc.v:110387$4298_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:109520.1-109557.10" +attribute \src "libresoc.v:110403.1-110440.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_ai" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" -module \dec_ai$200 - attribute \src "libresoc.v:109546.3-109555.6" +module \dec_ai$203 + attribute \src "libresoc.v:110429.3-110438.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:109521.7-109521.20" + attribute \src "libresoc.v:110404.7-110404.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109546.3-109555.6" + attribute \src "libresoc.v:110429.3-110438.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:109545.17-109545.107" - wire $and$libresoc.v:109545$4222_Y - attribute \src "libresoc.v:109543.17-109543.111" - wire $eq$libresoc.v:109543$4220_Y - attribute \src "libresoc.v:109544.17-109544.108" - wire $eq$libresoc.v:109544$4221_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "libresoc.v:110428.17-110428.107" + wire $and$libresoc.v:110428$4303_Y + attribute \src "libresoc.v:110426.17-110426.111" + wire $eq$libresoc.v:110426$4301_Y + attribute \src "libresoc.v:110427.17-110427.108" + wire $eq$libresoc.v:110427$4302_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 2 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" wire output 1 \immz_out - attribute \src "libresoc.v:109521.7-109521.15" + attribute \src "libresoc.v:110404.7-110404.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:159" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -169542,10 +171846,10 @@ module \dec_ai$200 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $and$libresoc.v:109545$4222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $and $and$libresoc.v:110428$4303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -169553,10 +171857,10 @@ module \dec_ai$200 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:109545$4222_Y + connect \Y $and$libresoc.v:110428$4303_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109543$4220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110426$4301 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -169564,10 +171868,10 @@ module \dec_ai$200 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:109543$4220_Y + connect \Y $eq$libresoc.v:110426$4301_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $eq$libresoc.v:109544$4221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + cell $eq $eq$libresoc.v:110427$4302 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -169575,28 +171879,28 @@ module \dec_ai$200 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:109544$4221_Y + connect \Y $eq$libresoc.v:110427$4302_Y end - attribute \src "libresoc.v:109521.7-109521.20" - process $proc$libresoc.v:109521$4224 + attribute \src "libresoc.v:110404.7-110404.20" + process $proc$libresoc.v:110404$4305 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109546.3-109555.6" - process $proc$libresoc.v:109546$4223 + attribute \src "libresoc.v:110429.3-110438.6" + process $proc$libresoc.v:110429$4304 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:109547.5-109547.29" + attribute \src "libresoc.v:110430.5-110430.29" switch \initial - attribute \src "libresoc.v:109547.9-109547.17" + attribute \src "libresoc.v:110430.9-110430.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -169608,65 +171912,65 @@ module \dec_ai$200 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:109543$4220_Y - connect \$3 $eq$libresoc.v:109544$4221_Y - connect \$5 $and$libresoc.v:109545$4222_Y + connect \$1 $eq$libresoc.v:110426$4301_Y + connect \$3 $eq$libresoc.v:110427$4302_Y + connect \$5 $and$libresoc.v:110428$4303_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:109561.1-109752.10" +attribute \src "libresoc.v:110444.1-110635.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_b" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:109716.3-109733.6" + attribute \src "libresoc.v:110599.3-110616.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:109734.3-109751.6" + attribute \src "libresoc.v:110617.3-110634.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:109562.7-109562.20" + attribute \src "libresoc.v:110445.7-110445.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109686.3-109700.6" + attribute \src "libresoc.v:110569.3-110583.6" wire width 5 $0\reg_b[4:0] - attribute \src "libresoc.v:109701.3-109715.6" + attribute \src "libresoc.v:110584.3-110598.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:109716.3-109733.6" + attribute \src "libresoc.v:110599.3-110616.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:109734.3-109751.6" + attribute \src "libresoc.v:110617.3-110634.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:109686.3-109700.6" + attribute \src "libresoc.v:110569.3-110583.6" wire width 5 $1\reg_b[4:0] - attribute \src "libresoc.v:109701.3-109715.6" + attribute \src "libresoc.v:110584.3-110598.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:109716.3-109733.6" + attribute \src "libresoc.v:110599.3-110616.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:109734.3-109751.6" + attribute \src "libresoc.v:110617.3-110634.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:109682.17-109682.117" - wire $eq$libresoc.v:109682$4225_Y - attribute \src "libresoc.v:109684.17-109684.117" - wire $eq$libresoc.v:109684$4227_Y - attribute \src "libresoc.v:109683.17-109683.107" - wire $not$libresoc.v:109683$4226_Y - attribute \src "libresoc.v:109685.17-109685.107" - wire $not$libresoc.v:109685$4228_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$1 + attribute \src "libresoc.v:110565.17-110565.117" + wire $eq$libresoc.v:110565$4306_Y + attribute \src "libresoc.v:110567.17-110567.117" + wire $eq$libresoc.v:110567$4308_Y + attribute \src "libresoc.v:110566.17-110566.107" + wire $not$libresoc.v:110566$4307_Y + attribute \src "libresoc.v:110568.17-110568.107" + wire $not$libresoc.v:110568$4309_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 10 input 8 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:109562.7-109562.15" + attribute \src "libresoc.v:110445.7-110445.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -169742,11 +172046,11 @@ module \dec_b attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 9 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \reg_b_ok attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -169763,10 +172067,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$libresoc.v:109682$4225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:110565$4306 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -169774,10 +172078,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:109682$4225_Y + connect \Y $eq$libresoc.v:110565$4306_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $eq$libresoc.v:109684$4227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:110567$4308 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -169785,44 +172089,44 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:109684$4227_Y + connect \Y $eq$libresoc.v:110567$4308_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$libresoc.v:109683$4226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:110566$4307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:109683$4226_Y + connect \Y $not$libresoc.v:110566$4307_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $not$libresoc.v:109685$4228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:110568$4309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:109685$4228_Y + connect \Y $not$libresoc.v:110568$4309_Y end - attribute \src "libresoc.v:109562.7-109562.20" - process $proc$libresoc.v:109562$4233 + attribute \src "libresoc.v:110445.7-110445.20" + process $proc$libresoc.v:110445$4314 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109686.3-109700.6" - process $proc$libresoc.v:109686$4229 + attribute \src "libresoc.v:110569.3-110583.6" + process $proc$libresoc.v:110569$4310 assign { } { } assign { } { } assign $0\reg_b[4:0] $1\reg_b[4:0] - attribute \src "libresoc.v:109687.5-109687.29" + attribute \src "libresoc.v:110570.5-110570.29" switch \initial - attribute \src "libresoc.v:109687.9-109687.17" + attribute \src "libresoc.v:110570.9-110570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -169838,18 +172142,18 @@ module \dec_b sync always update \reg_b $0\reg_b[4:0] end - attribute \src "libresoc.v:109701.3-109715.6" - process $proc$libresoc.v:109701$4230 + attribute \src "libresoc.v:110584.3-110598.6" + process $proc$libresoc.v:110584$4311 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:109702.5-109702.29" + attribute \src "libresoc.v:110585.5-110585.29" switch \initial - attribute \src "libresoc.v:109702.9-109702.17" + attribute \src "libresoc.v:110585.9-110585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -169865,24 +172169,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:109716.3-109733.6" - process $proc$libresoc.v:109716$4231 + attribute \src "libresoc.v:110599.3-110616.6" + process $proc$libresoc.v:110599$4312 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:109717.5-109717.29" + attribute \src "libresoc.v:110600.5-110600.29" switch \initial - attribute \src "libresoc.v:109717.9-109717.17" + attribute \src "libresoc.v:110600.9-110600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" switch { \XL_XO [5] \$3 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -169901,24 +172205,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:109734.3-109751.6" - process $proc$libresoc.v:109734$4232 + attribute \src "libresoc.v:110617.3-110634.6" + process $proc$libresoc.v:110617$4313 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:109735.5-109735.29" + attribute \src "libresoc.v:110618.5-110618.29" switch \initial - attribute \src "libresoc.v:109735.9-109735.17" + attribute \src "libresoc.v:110618.9-110618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -169937,129 +172241,129 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$1 $eq$libresoc.v:109682$4225_Y - connect \$3 $not$libresoc.v:109683$4226_Y - connect \$5 $eq$libresoc.v:109684$4227_Y - connect \$7 $not$libresoc.v:109685$4228_Y + connect \$1 $eq$libresoc.v:110565$4306_Y + connect \$3 $not$libresoc.v:110566$4307_Y + connect \$5 $eq$libresoc.v:110567$4308_Y + connect \$7 $not$libresoc.v:110568$4309_Y end -attribute \src "libresoc.v:109756.1-110009.10" +attribute \src "libresoc.v:110639.1-110892.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:109983.3-109993.6" + attribute \src "libresoc.v:110866.3-110876.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:109994.3-110004.6" + attribute \src "libresoc.v:110877.3-110887.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:109845.3-109891.6" + attribute \src "libresoc.v:110728.3-110774.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:109892.3-109938.6" + attribute \src "libresoc.v:110775.3-110821.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:109757.7-109757.20" + attribute \src "libresoc.v:110640.7-110640.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109972.3-109982.6" + attribute \src "libresoc.v:110855.3-110865.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:109939.3-109949.6" + attribute \src "libresoc.v:110822.3-110832.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:109950.3-109960.6" + attribute \src "libresoc.v:110833.3-110843.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:109961.3-109971.6" + attribute \src "libresoc.v:110844.3-110854.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:109983.3-109993.6" + attribute \src "libresoc.v:110866.3-110876.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:109994.3-110004.6" + attribute \src "libresoc.v:110877.3-110887.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:109845.3-109891.6" + attribute \src "libresoc.v:110728.3-110774.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:109892.3-109938.6" + attribute \src "libresoc.v:110775.3-110821.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:109972.3-109982.6" + attribute \src "libresoc.v:110855.3-110865.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:109939.3-109949.6" + attribute \src "libresoc.v:110822.3-110832.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:109950.3-109960.6" + attribute \src "libresoc.v:110833.3-110843.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:109961.3-109971.6" + attribute \src "libresoc.v:110844.3-110854.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:109835.17-109835.104" - wire width 64 $extend$libresoc.v:109835$4234_Y - attribute \src "libresoc.v:109836.18-109836.107" - wire width 64 $extend$libresoc.v:109836$4236_Y - attribute \src "libresoc.v:109839.17-109839.104" - wire width 64 $extend$libresoc.v:109839$4240_Y - attribute \src "libresoc.v:109843.17-109843.102" - wire width 64 $extend$libresoc.v:109843$4245_Y - attribute \src "libresoc.v:109835.17-109835.104" - wire width 64 $pos$libresoc.v:109835$4235_Y - attribute \src "libresoc.v:109836.18-109836.107" - wire width 64 $pos$libresoc.v:109836$4237_Y - attribute \src "libresoc.v:109839.17-109839.104" - wire width 64 $pos$libresoc.v:109839$4241_Y - attribute \src "libresoc.v:109843.17-109843.102" - wire width 64 $pos$libresoc.v:109843$4246_Y - attribute \src "libresoc.v:109837.18-109837.114" - wire width 47 $sshl$libresoc.v:109837$4238_Y - attribute \src "libresoc.v:109838.18-109838.113" - wire width 27 $sshl$libresoc.v:109838$4239_Y - attribute \src "libresoc.v:109840.18-109840.113" - wire width 17 $sshl$libresoc.v:109840$4242_Y - attribute \src "libresoc.v:109841.18-109841.113" - wire width 17 $sshl$libresoc.v:109841$4243_Y - attribute \src "libresoc.v:109842.17-109842.109" - wire width 47 $sshl$libresoc.v:109842$4244_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:110718.17-110718.104" + wire width 64 $extend$libresoc.v:110718$4315_Y + attribute \src "libresoc.v:110719.18-110719.107" + wire width 64 $extend$libresoc.v:110719$4317_Y + attribute \src "libresoc.v:110722.17-110722.104" + wire width 64 $extend$libresoc.v:110722$4321_Y + attribute \src "libresoc.v:110726.17-110726.102" + wire width 64 $extend$libresoc.v:110726$4326_Y + attribute \src "libresoc.v:110718.17-110718.104" + wire width 64 $pos$libresoc.v:110718$4316_Y + attribute \src "libresoc.v:110719.18-110719.107" + wire width 64 $pos$libresoc.v:110719$4318_Y + attribute \src "libresoc.v:110722.17-110722.104" + wire width 64 $pos$libresoc.v:110722$4322_Y + attribute \src "libresoc.v:110726.17-110726.102" + wire width 64 $pos$libresoc.v:110726$4327_Y + attribute \src "libresoc.v:110720.18-110720.114" + wire width 47 $sshl$libresoc.v:110720$4319_Y + attribute \src "libresoc.v:110721.18-110721.113" + wire width 27 $sshl$libresoc.v:110721$4320_Y + attribute \src "libresoc.v:110723.18-110723.113" + wire width 17 $sshl$libresoc.v:110723$4323_Y + attribute \src "libresoc.v:110724.18-110724.113" + wire width 17 $sshl$libresoc.v:110724$4324_Y + attribute \src "libresoc.v:110725.17-110725.109" + wire width 47 $sshl$libresoc.v:110725$4325_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:109757.7-109757.15" + attribute \src "libresoc.v:110640.7-110640.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -170076,80 +172380,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:109835$4234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110718$4315 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:109835$4234_Y + connect \Y $extend$libresoc.v:110718$4315_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:109836$4236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110719$4317 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:109836$4236_Y + connect \Y $extend$libresoc.v:110719$4317_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:109839$4240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110722$4321 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:109839$4240_Y + connect \Y $extend$libresoc.v:110722$4321_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:109843$4245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:110726$4326 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:109843$4245_Y + connect \Y $extend$libresoc.v:110726$4326_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:109835$4235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110718$4316 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:109835$4234_Y - connect \Y $pos$libresoc.v:109835$4235_Y + connect \A $extend$libresoc.v:110718$4315_Y + connect \Y $pos$libresoc.v:110718$4316_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:109836$4237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110719$4318 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:109836$4236_Y - connect \Y $pos$libresoc.v:109836$4237_Y + connect \A $extend$libresoc.v:110719$4317_Y + connect \Y $pos$libresoc.v:110719$4318_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:109839$4241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110722$4322 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:109839$4240_Y - connect \Y $pos$libresoc.v:109839$4241_Y + connect \A $extend$libresoc.v:110722$4321_Y + connect \Y $pos$libresoc.v:110722$4322_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:109843$4246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:110726$4327 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:109843$4245_Y - connect \Y $pos$libresoc.v:109843$4246_Y + connect \A $extend$libresoc.v:110726$4326_Y + connect \Y $pos$libresoc.v:110726$4327_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:109837$4238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:110720$4319 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -170157,10 +172461,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:109837$4238_Y + connect \Y $sshl$libresoc.v:110720$4319_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:109838$4239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:110721$4320 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -170168,10 +172472,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:109838$4239_Y + connect \Y $sshl$libresoc.v:110721$4320_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:109840$4242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:110723$4323 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -170179,10 +172483,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:109840$4242_Y + connect \Y $sshl$libresoc.v:110723$4323_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:109841$4243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:110724$4324 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -170190,10 +172494,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:109841$4243_Y + connect \Y $sshl$libresoc.v:110724$4324_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:109842$4244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:110725$4325 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -170201,28 +172505,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:109842$4244_Y + connect \Y $sshl$libresoc.v:110725$4325_Y end - attribute \src "libresoc.v:109757.7-109757.20" - process $proc$libresoc.v:109757$4255 + attribute \src "libresoc.v:110640.7-110640.20" + process $proc$libresoc.v:110640$4336 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109845.3-109891.6" - process $proc$libresoc.v:109845$4247 + attribute \src "libresoc.v:110728.3-110774.6" + process $proc$libresoc.v:110728$4328 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:109846.5-109846.29" + attribute \src "libresoc.v:110729.5-110729.29" switch \initial - attribute \src "libresoc.v:109846.9-109846.17" + attribute \src "libresoc.v:110729.9-110729.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -170270,18 +172574,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:109892.3-109938.6" - process $proc$libresoc.v:109892$4248 + attribute \src "libresoc.v:110775.3-110821.6" + process $proc$libresoc.v:110775$4329 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:109893.5-109893.29" + attribute \src "libresoc.v:110776.5-110776.29" switch \initial - attribute \src "libresoc.v:109893.9-109893.17" + attribute \src "libresoc.v:110776.9-110776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -170329,18 +172633,18 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:109939.3-109949.6" - process $proc$libresoc.v:109939$4249 + attribute \src "libresoc.v:110822.3-110832.6" + process $proc$libresoc.v:110822$4330 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:109940.5-109940.29" + attribute \src "libresoc.v:110823.5-110823.29" switch \initial - attribute \src "libresoc.v:109940.9-109940.17" + attribute \src "libresoc.v:110823.9-110823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -170352,18 +172656,18 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:109950.3-109960.6" - process $proc$libresoc.v:109950$4250 + attribute \src "libresoc.v:110833.3-110843.6" + process $proc$libresoc.v:110833$4331 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:109951.5-109951.29" + attribute \src "libresoc.v:110834.5-110834.29" switch \initial - attribute \src "libresoc.v:109951.9-109951.17" + attribute \src "libresoc.v:110834.9-110834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -170375,18 +172679,18 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:109961.3-109971.6" - process $proc$libresoc.v:109961$4251 + attribute \src "libresoc.v:110844.3-110854.6" + process $proc$libresoc.v:110844$4332 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:109962.5-109962.29" + attribute \src "libresoc.v:110845.5-110845.29" switch \initial - attribute \src "libresoc.v:109962.9-109962.17" + attribute \src "libresoc.v:110845.9-110845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -170398,18 +172702,18 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:109972.3-109982.6" - process $proc$libresoc.v:109972$4252 + attribute \src "libresoc.v:110855.3-110865.6" + process $proc$libresoc.v:110855$4333 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:109973.5-109973.29" + attribute \src "libresoc.v:110856.5-110856.29" switch \initial - attribute \src "libresoc.v:109973.9-109973.17" + attribute \src "libresoc.v:110856.9-110856.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -170421,18 +172725,18 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:109983.3-109993.6" - process $proc$libresoc.v:109983$4253 + attribute \src "libresoc.v:110866.3-110876.6" + process $proc$libresoc.v:110866$4334 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:109984.5-109984.29" + attribute \src "libresoc.v:110867.5-110867.29" switch \initial - attribute \src "libresoc.v:109984.9-109984.17" + attribute \src "libresoc.v:110867.9-110867.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -170444,18 +172748,18 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:109994.3-110004.6" - process $proc$libresoc.v:109994$4254 + attribute \src "libresoc.v:110877.3-110887.6" + process $proc$libresoc.v:110877$4335 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:109995.5-109995.29" + attribute \src "libresoc.v:110878.5-110878.29" switch \initial - attribute \src "libresoc.v:109995.9-109995.17" + attribute \src "libresoc.v:110878.9-110878.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -170467,139 +172771,139 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:109835$4235_Y - connect \$11 $pos$libresoc.v:109836$4237_Y - connect \$14 $sshl$libresoc.v:109837$4238_Y - connect \$17 $sshl$libresoc.v:109838$4239_Y - connect \$1 $pos$libresoc.v:109839$4241_Y - connect \$20 $sshl$libresoc.v:109840$4242_Y - connect \$23 $sshl$libresoc.v:109841$4243_Y - connect \$4 $sshl$libresoc.v:109842$4244_Y - connect \$3 $pos$libresoc.v:109843$4246_Y + connect \$9 $pos$libresoc.v:110718$4316_Y + connect \$11 $pos$libresoc.v:110719$4318_Y + connect \$14 $sshl$libresoc.v:110720$4319_Y + connect \$17 $sshl$libresoc.v:110721$4320_Y + connect \$1 $pos$libresoc.v:110722$4322_Y + connect \$20 $sshl$libresoc.v:110723$4323_Y + connect \$23 $sshl$libresoc.v:110724$4324_Y + connect \$4 $sshl$libresoc.v:110725$4325_Y + connect \$3 $pos$libresoc.v:110726$4327_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:110013.1-110266.10" +attribute \src "libresoc.v:110896.1-111149.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" -module \dec_bi$151 - attribute \src "libresoc.v:110240.3-110250.6" +module \dec_bi$154 + attribute \src "libresoc.v:111123.3-111133.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:110251.3-110261.6" + attribute \src "libresoc.v:111134.3-111144.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110102.3-110148.6" + attribute \src "libresoc.v:110985.3-111031.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110149.3-110195.6" + attribute \src "libresoc.v:111032.3-111078.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110014.7-110014.20" + attribute \src "libresoc.v:110897.7-110897.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110229.3-110239.6" + attribute \src "libresoc.v:111112.3-111122.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110196.3-110206.6" + attribute \src "libresoc.v:111079.3-111089.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110207.3-110217.6" + attribute \src "libresoc.v:111090.3-111100.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110218.3-110228.6" + attribute \src "libresoc.v:111101.3-111111.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:110240.3-110250.6" + attribute \src "libresoc.v:111123.3-111133.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:110251.3-110261.6" + attribute \src "libresoc.v:111134.3-111144.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110102.3-110148.6" + attribute \src "libresoc.v:110985.3-111031.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110149.3-110195.6" + attribute \src "libresoc.v:111032.3-111078.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110229.3-110239.6" + attribute \src "libresoc.v:111112.3-111122.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110196.3-110206.6" + attribute \src "libresoc.v:111079.3-111089.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110207.3-110217.6" + attribute \src "libresoc.v:111090.3-111100.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110218.3-110228.6" + attribute \src "libresoc.v:111101.3-111111.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110092.17-110092.107" - wire width 64 $extend$libresoc.v:110092$4256_Y - attribute \src "libresoc.v:110093.18-110093.110" - wire width 64 $extend$libresoc.v:110093$4258_Y - attribute \src "libresoc.v:110096.17-110096.107" - wire width 64 $extend$libresoc.v:110096$4262_Y - attribute \src "libresoc.v:110100.17-110100.102" - wire width 64 $extend$libresoc.v:110100$4267_Y - attribute \src "libresoc.v:110092.17-110092.107" - wire width 64 $pos$libresoc.v:110092$4257_Y - attribute \src "libresoc.v:110093.18-110093.110" - wire width 64 $pos$libresoc.v:110093$4259_Y - attribute \src "libresoc.v:110096.17-110096.107" - wire width 64 $pos$libresoc.v:110096$4263_Y - attribute \src "libresoc.v:110100.17-110100.102" - wire width 64 $pos$libresoc.v:110100$4268_Y - attribute \src "libresoc.v:110094.18-110094.117" - wire width 47 $sshl$libresoc.v:110094$4260_Y - attribute \src "libresoc.v:110095.18-110095.116" - wire width 27 $sshl$libresoc.v:110095$4261_Y - attribute \src "libresoc.v:110097.18-110097.116" - wire width 17 $sshl$libresoc.v:110097$4264_Y - attribute \src "libresoc.v:110098.18-110098.116" - wire width 17 $sshl$libresoc.v:110098$4265_Y - attribute \src "libresoc.v:110099.17-110099.109" - wire width 47 $sshl$libresoc.v:110099$4266_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:110975.17-110975.107" + wire width 64 $extend$libresoc.v:110975$4337_Y + attribute \src "libresoc.v:110976.18-110976.110" + wire width 64 $extend$libresoc.v:110976$4339_Y + attribute \src "libresoc.v:110979.17-110979.107" + wire width 64 $extend$libresoc.v:110979$4343_Y + attribute \src "libresoc.v:110983.17-110983.102" + wire width 64 $extend$libresoc.v:110983$4348_Y + attribute \src "libresoc.v:110975.17-110975.107" + wire width 64 $pos$libresoc.v:110975$4338_Y + attribute \src "libresoc.v:110976.18-110976.110" + wire width 64 $pos$libresoc.v:110976$4340_Y + attribute \src "libresoc.v:110979.17-110979.107" + wire width 64 $pos$libresoc.v:110979$4344_Y + attribute \src "libresoc.v:110983.17-110983.102" + wire width 64 $pos$libresoc.v:110983$4349_Y + attribute \src "libresoc.v:110977.18-110977.117" + wire width 47 $sshl$libresoc.v:110977$4341_Y + attribute \src "libresoc.v:110978.18-110978.116" + wire width 27 $sshl$libresoc.v:110978$4342_Y + attribute \src "libresoc.v:110980.18-110980.116" + wire width 17 $sshl$libresoc.v:110980$4345_Y + attribute \src "libresoc.v:110981.18-110981.116" + wire width 17 $sshl$libresoc.v:110981$4346_Y + attribute \src "libresoc.v:110982.17-110982.109" + wire width 47 $sshl$libresoc.v:110982$4347_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:110014.7-110014.15" + attribute \src "libresoc.v:110897.7-110897.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -170616,80 +172920,80 @@ module \dec_bi$151 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110092$4256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110975$4337 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:110092$4256_Y + connect \Y $extend$libresoc.v:110975$4337_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110093$4258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110976$4339 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:110093$4258_Y + connect \Y $extend$libresoc.v:110976$4339_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110096$4262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:110979$4343 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:110096$4262_Y + connect \Y $extend$libresoc.v:110979$4343_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:110100$4267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:110983$4348 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:110100$4267_Y + connect \Y $extend$libresoc.v:110983$4348_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110092$4257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110975$4338 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110092$4256_Y - connect \Y $pos$libresoc.v:110092$4257_Y + connect \A $extend$libresoc.v:110975$4337_Y + connect \Y $pos$libresoc.v:110975$4338_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110093$4259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110976$4340 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110093$4258_Y - connect \Y $pos$libresoc.v:110093$4259_Y + connect \A $extend$libresoc.v:110976$4339_Y + connect \Y $pos$libresoc.v:110976$4340_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110096$4263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:110979$4344 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110096$4262_Y - connect \Y $pos$libresoc.v:110096$4263_Y + connect \A $extend$libresoc.v:110979$4343_Y + connect \Y $pos$libresoc.v:110979$4344_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:110100$4268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:110983$4349 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110100$4267_Y - connect \Y $pos$libresoc.v:110100$4268_Y + connect \A $extend$libresoc.v:110983$4348_Y + connect \Y $pos$libresoc.v:110983$4349_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:110094$4260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:110977$4341 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -170697,10 +173001,10 @@ module \dec_bi$151 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:110094$4260_Y + connect \Y $sshl$libresoc.v:110977$4341_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:110095$4261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:110978$4342 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -170708,10 +173012,10 @@ module \dec_bi$151 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:110095$4261_Y + connect \Y $sshl$libresoc.v:110978$4342_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:110097$4264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:110980$4345 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -170719,10 +173023,10 @@ module \dec_bi$151 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:110097$4264_Y + connect \Y $sshl$libresoc.v:110980$4345_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:110098$4265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:110981$4346 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -170730,10 +173034,10 @@ module \dec_bi$151 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:110098$4265_Y + connect \Y $sshl$libresoc.v:110981$4346_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:110099$4266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:110982$4347 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -170741,28 +173045,28 @@ module \dec_bi$151 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:110099$4266_Y + connect \Y $sshl$libresoc.v:110982$4347_Y end - attribute \src "libresoc.v:110014.7-110014.20" - process $proc$libresoc.v:110014$4277 + attribute \src "libresoc.v:110897.7-110897.20" + process $proc$libresoc.v:110897$4358 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110102.3-110148.6" - process $proc$libresoc.v:110102$4269 + attribute \src "libresoc.v:110985.3-111031.6" + process $proc$libresoc.v:110985$4350 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110103.5-110103.29" + attribute \src "libresoc.v:110986.5-110986.29" switch \initial - attribute \src "libresoc.v:110103.9-110103.17" + attribute \src "libresoc.v:110986.9-110986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -170810,18 +173114,18 @@ module \dec_bi$151 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:110149.3-110195.6" - process $proc$libresoc.v:110149$4270 + attribute \src "libresoc.v:111032.3-111078.6" + process $proc$libresoc.v:111032$4351 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110150.5-110150.29" + attribute \src "libresoc.v:111033.5-111033.29" switch \initial - attribute \src "libresoc.v:110150.9-110150.17" + attribute \src "libresoc.v:111033.9-111033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -170869,18 +173173,18 @@ module \dec_bi$151 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:110196.3-110206.6" - process $proc$libresoc.v:110196$4271 + attribute \src "libresoc.v:111079.3-111089.6" + process $proc$libresoc.v:111079$4352 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110197.5-110197.29" + attribute \src "libresoc.v:111080.5-111080.29" switch \initial - attribute \src "libresoc.v:110197.9-110197.17" + attribute \src "libresoc.v:111080.9-111080.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -170892,18 +173196,18 @@ module \dec_bi$151 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:110207.3-110217.6" - process $proc$libresoc.v:110207$4272 + attribute \src "libresoc.v:111090.3-111100.6" + process $proc$libresoc.v:111090$4353 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110208.5-110208.29" + attribute \src "libresoc.v:111091.5-111091.29" switch \initial - attribute \src "libresoc.v:110208.9-110208.17" + attribute \src "libresoc.v:111091.9-111091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -170915,18 +173219,18 @@ module \dec_bi$151 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:110218.3-110228.6" - process $proc$libresoc.v:110218$4273 + attribute \src "libresoc.v:111101.3-111111.6" + process $proc$libresoc.v:111101$4354 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110219.5-110219.29" + attribute \src "libresoc.v:111102.5-111102.29" switch \initial - attribute \src "libresoc.v:110219.9-110219.17" + attribute \src "libresoc.v:111102.9-111102.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -170938,18 +173242,18 @@ module \dec_bi$151 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:110229.3-110239.6" - process $proc$libresoc.v:110229$4274 + attribute \src "libresoc.v:111112.3-111122.6" + process $proc$libresoc.v:111112$4355 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:110230.5-110230.29" + attribute \src "libresoc.v:111113.5-111113.29" switch \initial - attribute \src "libresoc.v:110230.9-110230.17" + attribute \src "libresoc.v:111113.9-111113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -170961,18 +173265,18 @@ module \dec_bi$151 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:110240.3-110250.6" - process $proc$libresoc.v:110240$4275 + attribute \src "libresoc.v:111123.3-111133.6" + process $proc$libresoc.v:111123$4356 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:110241.5-110241.29" + attribute \src "libresoc.v:111124.5-111124.29" switch \initial - attribute \src "libresoc.v:110241.9-110241.17" + attribute \src "libresoc.v:111124.9-111124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -170984,18 +173288,18 @@ module \dec_bi$151 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:110251.3-110261.6" - process $proc$libresoc.v:110251$4276 + attribute \src "libresoc.v:111134.3-111144.6" + process $proc$libresoc.v:111134$4357 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:110252.5-110252.29" + attribute \src "libresoc.v:111135.5-111135.29" switch \initial - attribute \src "libresoc.v:110252.9-110252.17" + attribute \src "libresoc.v:111135.9-111135.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -171007,139 +173311,139 @@ module \dec_bi$151 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:110092$4257_Y - connect \$11 $pos$libresoc.v:110093$4259_Y - connect \$14 $sshl$libresoc.v:110094$4260_Y - connect \$17 $sshl$libresoc.v:110095$4261_Y - connect \$1 $pos$libresoc.v:110096$4263_Y - connect \$20 $sshl$libresoc.v:110097$4264_Y - connect \$23 $sshl$libresoc.v:110098$4265_Y - connect \$4 $sshl$libresoc.v:110099$4266_Y - connect \$3 $pos$libresoc.v:110100$4268_Y + connect \$9 $pos$libresoc.v:110975$4338_Y + connect \$11 $pos$libresoc.v:110976$4340_Y + connect \$14 $sshl$libresoc.v:110977$4341_Y + connect \$17 $sshl$libresoc.v:110978$4342_Y + connect \$1 $pos$libresoc.v:110979$4344_Y + connect \$20 $sshl$libresoc.v:110980$4345_Y + connect \$23 $sshl$libresoc.v:110981$4346_Y + connect \$4 $sshl$libresoc.v:110982$4347_Y + connect \$3 $pos$libresoc.v:110983$4349_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:110270.1-110523.10" +attribute \src "libresoc.v:111153.1-111406.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" -module \dec_bi$160 - attribute \src "libresoc.v:110497.3-110507.6" +module \dec_bi$163 + attribute \src "libresoc.v:111380.3-111390.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:110508.3-110518.6" + attribute \src "libresoc.v:111391.3-111401.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110359.3-110405.6" + attribute \src "libresoc.v:111242.3-111288.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110406.3-110452.6" + attribute \src "libresoc.v:111289.3-111335.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110271.7-110271.20" + attribute \src "libresoc.v:111154.7-111154.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110486.3-110496.6" + attribute \src "libresoc.v:111369.3-111379.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110453.3-110463.6" + attribute \src "libresoc.v:111336.3-111346.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110464.3-110474.6" + attribute \src "libresoc.v:111347.3-111357.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110475.3-110485.6" + attribute \src "libresoc.v:111358.3-111368.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:110497.3-110507.6" + attribute \src "libresoc.v:111380.3-111390.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:110508.3-110518.6" + attribute \src "libresoc.v:111391.3-111401.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110359.3-110405.6" + attribute \src "libresoc.v:111242.3-111288.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110406.3-110452.6" + attribute \src "libresoc.v:111289.3-111335.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110486.3-110496.6" + attribute \src "libresoc.v:111369.3-111379.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110453.3-110463.6" + attribute \src "libresoc.v:111336.3-111346.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110464.3-110474.6" + attribute \src "libresoc.v:111347.3-111357.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110475.3-110485.6" + attribute \src "libresoc.v:111358.3-111368.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110349.17-110349.108" - wire width 64 $extend$libresoc.v:110349$4278_Y - attribute \src "libresoc.v:110350.18-110350.111" - wire width 64 $extend$libresoc.v:110350$4280_Y - attribute \src "libresoc.v:110353.17-110353.108" - wire width 64 $extend$libresoc.v:110353$4284_Y - attribute \src "libresoc.v:110357.17-110357.102" - wire width 64 $extend$libresoc.v:110357$4289_Y - attribute \src "libresoc.v:110349.17-110349.108" - wire width 64 $pos$libresoc.v:110349$4279_Y - attribute \src "libresoc.v:110350.18-110350.111" - wire width 64 $pos$libresoc.v:110350$4281_Y - attribute \src "libresoc.v:110353.17-110353.108" - wire width 64 $pos$libresoc.v:110353$4285_Y - attribute \src "libresoc.v:110357.17-110357.102" - wire width 64 $pos$libresoc.v:110357$4290_Y - attribute \src "libresoc.v:110351.18-110351.118" - wire width 47 $sshl$libresoc.v:110351$4282_Y - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:110271.7-110271.15" + attribute \src "libresoc.v:111154.7-111154.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -171156,80 +173460,80 @@ module \dec_bi$160 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110349$4278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111232$4359 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:110349$4278_Y + connect \Y $extend$libresoc.v:111232$4359_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110350$4280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111233$4361 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:110350$4280_Y + connect \Y $extend$libresoc.v:111233$4361_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110353$4284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111236$4365 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:110353$4284_Y + connect \Y $extend$libresoc.v:111236$4365_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:110357$4289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111240$4370 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:110357$4289_Y + connect \Y $extend$libresoc.v:111240$4370_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110349$4279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111232$4360 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110349$4278_Y - connect \Y $pos$libresoc.v:110349$4279_Y + connect \A $extend$libresoc.v:111232$4359_Y + connect \Y $pos$libresoc.v:111232$4360_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110350$4281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111233$4362 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110350$4280_Y - connect \Y $pos$libresoc.v:110350$4281_Y + connect \A $extend$libresoc.v:111233$4361_Y + connect \Y $pos$libresoc.v:111233$4362_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110353$4285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111236$4366 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110353$4284_Y - connect \Y $pos$libresoc.v:110353$4285_Y + connect \A $extend$libresoc.v:111236$4365_Y + connect \Y $pos$libresoc.v:111236$4366_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:110357$4290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111240$4371 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110357$4289_Y - connect \Y $pos$libresoc.v:110357$4290_Y + connect \A $extend$libresoc.v:111240$4370_Y + connect \Y $pos$libresoc.v:111240$4371_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:110351$4282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111234$4363 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -171237,10 +173541,10 @@ module \dec_bi$160 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:110351$4282_Y + connect \Y $sshl$libresoc.v:111234$4363_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:110352$4283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111235$4364 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -171248,10 +173552,10 @@ module \dec_bi$160 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:110352$4283_Y + connect \Y $sshl$libresoc.v:111235$4364_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:110354$4286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111237$4367 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -171259,10 +173563,10 @@ module \dec_bi$160 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:110354$4286_Y + connect \Y $sshl$libresoc.v:111237$4367_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:110355$4287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111238$4368 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -171270,10 +173574,10 @@ module \dec_bi$160 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:110355$4287_Y + connect \Y $sshl$libresoc.v:111238$4368_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:110356$4288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111239$4369 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -171281,28 +173585,28 @@ module \dec_bi$160 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:110356$4288_Y + connect \Y $sshl$libresoc.v:111239$4369_Y end - attribute \src "libresoc.v:110271.7-110271.20" - process $proc$libresoc.v:110271$4299 + attribute \src "libresoc.v:111154.7-111154.20" + process $proc$libresoc.v:111154$4380 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110359.3-110405.6" - process $proc$libresoc.v:110359$4291 + attribute \src "libresoc.v:111242.3-111288.6" + process $proc$libresoc.v:111242$4372 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110360.5-110360.29" + attribute \src "libresoc.v:111243.5-111243.29" switch \initial - attribute \src "libresoc.v:110360.9-110360.17" + attribute \src "libresoc.v:111243.9-111243.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -171350,18 +173654,18 @@ module \dec_bi$160 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:110406.3-110452.6" - process $proc$libresoc.v:110406$4292 + attribute \src "libresoc.v:111289.3-111335.6" + process $proc$libresoc.v:111289$4373 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110407.5-110407.29" + attribute \src "libresoc.v:111290.5-111290.29" switch \initial - attribute \src "libresoc.v:110407.9-110407.17" + attribute \src "libresoc.v:111290.9-111290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -171409,18 +173713,18 @@ module \dec_bi$160 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:110453.3-110463.6" - process $proc$libresoc.v:110453$4293 + attribute \src "libresoc.v:111336.3-111346.6" + process $proc$libresoc.v:111336$4374 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110454.5-110454.29" + attribute \src "libresoc.v:111337.5-111337.29" switch \initial - attribute \src "libresoc.v:110454.9-110454.17" + attribute \src "libresoc.v:111337.9-111337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -171432,18 +173736,18 @@ module \dec_bi$160 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:110464.3-110474.6" - process $proc$libresoc.v:110464$4294 + attribute \src "libresoc.v:111347.3-111357.6" + process $proc$libresoc.v:111347$4375 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110465.5-110465.29" + attribute \src "libresoc.v:111348.5-111348.29" switch \initial - attribute \src "libresoc.v:110465.9-110465.17" + attribute \src "libresoc.v:111348.9-111348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -171455,18 +173759,18 @@ module \dec_bi$160 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:110475.3-110485.6" - process $proc$libresoc.v:110475$4295 + attribute \src "libresoc.v:111358.3-111368.6" + process $proc$libresoc.v:111358$4376 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110476.5-110476.29" + attribute \src "libresoc.v:111359.5-111359.29" switch \initial - attribute \src "libresoc.v:110476.9-110476.17" + attribute \src "libresoc.v:111359.9-111359.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -171478,18 +173782,18 @@ module \dec_bi$160 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:110486.3-110496.6" - process $proc$libresoc.v:110486$4296 + attribute \src "libresoc.v:111369.3-111379.6" + process $proc$libresoc.v:111369$4377 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:110487.5-110487.29" + attribute \src "libresoc.v:111370.5-111370.29" switch \initial - attribute \src "libresoc.v:110487.9-110487.17" + attribute \src "libresoc.v:111370.9-111370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -171501,18 +173805,18 @@ module \dec_bi$160 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:110497.3-110507.6" - process $proc$libresoc.v:110497$4297 + attribute \src "libresoc.v:111380.3-111390.6" + process $proc$libresoc.v:111380$4378 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:110498.5-110498.29" + attribute \src "libresoc.v:111381.5-111381.29" switch \initial - attribute \src "libresoc.v:110498.9-110498.17" + attribute \src "libresoc.v:111381.9-111381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -171524,18 +173828,18 @@ module \dec_bi$160 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:110508.3-110518.6" - process $proc$libresoc.v:110508$4298 + attribute \src "libresoc.v:111391.3-111401.6" + process $proc$libresoc.v:111391$4379 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:110509.5-110509.29" + attribute \src "libresoc.v:111392.5-111392.29" switch \initial - attribute \src "libresoc.v:110509.9-110509.17" + attribute \src "libresoc.v:111392.9-111392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -171547,139 +173851,139 @@ module \dec_bi$160 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:110349$4279_Y - connect \$11 $pos$libresoc.v:110350$4281_Y - connect \$14 $sshl$libresoc.v:110351$4282_Y - connect \$17 $sshl$libresoc.v:110352$4283_Y - connect \$1 $pos$libresoc.v:110353$4285_Y - connect \$20 $sshl$libresoc.v:110354$4286_Y - connect \$23 $sshl$libresoc.v:110355$4287_Y - connect \$4 $sshl$libresoc.v:110356$4288_Y - connect \$3 $pos$libresoc.v:110357$4290_Y + connect \$9 $pos$libresoc.v:111232$4360_Y + connect \$11 $pos$libresoc.v:111233$4362_Y + connect \$14 $sshl$libresoc.v:111234$4363_Y + connect \$17 $sshl$libresoc.v:111235$4364_Y + connect \$1 $pos$libresoc.v:111236$4366_Y + connect \$20 $sshl$libresoc.v:111237$4367_Y + connect \$23 $sshl$libresoc.v:111238$4368_Y + connect \$4 $sshl$libresoc.v:111239$4369_Y + connect \$3 $pos$libresoc.v:111240$4371_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:110527.1-110780.10" +attribute \src "libresoc.v:111410.1-111663.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" -module \dec_bi$176 - attribute \src "libresoc.v:110754.3-110764.6" +module \dec_bi$179 + attribute \src "libresoc.v:111637.3-111647.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:110765.3-110775.6" + attribute \src "libresoc.v:111648.3-111658.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110616.3-110662.6" + attribute \src "libresoc.v:111499.3-111545.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110663.3-110709.6" + attribute \src "libresoc.v:111546.3-111592.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110528.7-110528.20" + attribute \src "libresoc.v:111411.7-111411.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110743.3-110753.6" + attribute \src "libresoc.v:111626.3-111636.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110710.3-110720.6" + attribute \src "libresoc.v:111593.3-111603.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110721.3-110731.6" + attribute \src "libresoc.v:111604.3-111614.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110732.3-110742.6" + attribute \src "libresoc.v:111615.3-111625.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:110754.3-110764.6" + attribute \src "libresoc.v:111637.3-111647.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:110765.3-110775.6" + attribute \src "libresoc.v:111648.3-111658.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110616.3-110662.6" + attribute \src "libresoc.v:111499.3-111545.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110663.3-110709.6" + attribute \src "libresoc.v:111546.3-111592.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110743.3-110753.6" + attribute \src "libresoc.v:111626.3-111636.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110710.3-110720.6" + attribute \src "libresoc.v:111593.3-111603.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110721.3-110731.6" + attribute \src "libresoc.v:111604.3-111614.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110732.3-110742.6" + attribute \src "libresoc.v:111615.3-111625.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110606.17-110606.104" - wire width 64 $extend$libresoc.v:110606$4300_Y - attribute \src "libresoc.v:110607.18-110607.107" - wire width 64 $extend$libresoc.v:110607$4302_Y - attribute \src "libresoc.v:110610.17-110610.104" - wire width 64 $extend$libresoc.v:110610$4306_Y - attribute \src "libresoc.v:110614.17-110614.102" - wire width 64 $extend$libresoc.v:110614$4311_Y - attribute \src "libresoc.v:110606.17-110606.104" - wire width 64 $pos$libresoc.v:110606$4301_Y - attribute \src "libresoc.v:110607.18-110607.107" - wire width 64 $pos$libresoc.v:110607$4303_Y - attribute \src "libresoc.v:110610.17-110610.104" - wire width 64 $pos$libresoc.v:110610$4307_Y - attribute \src "libresoc.v:110614.17-110614.102" - wire width 64 $pos$libresoc.v:110614$4312_Y - attribute \src "libresoc.v:110608.18-110608.114" - wire width 47 $sshl$libresoc.v:110608$4304_Y - attribute \src "libresoc.v:110609.18-110609.113" - wire width 27 $sshl$libresoc.v:110609$4305_Y - attribute \src "libresoc.v:110611.18-110611.113" - wire width 17 $sshl$libresoc.v:110611$4308_Y - attribute \src "libresoc.v:110612.18-110612.113" - wire width 17 $sshl$libresoc.v:110612$4309_Y - attribute \src "libresoc.v:110613.17-110613.109" - wire width 47 $sshl$libresoc.v:110613$4310_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:111489.17-111489.104" + wire width 64 $extend$libresoc.v:111489$4381_Y + attribute \src "libresoc.v:111490.18-111490.107" + wire width 64 $extend$libresoc.v:111490$4383_Y + attribute \src "libresoc.v:111493.17-111493.104" + wire width 64 $extend$libresoc.v:111493$4387_Y + attribute \src "libresoc.v:111497.17-111497.102" + wire width 64 $extend$libresoc.v:111497$4392_Y + attribute \src "libresoc.v:111489.17-111489.104" + wire width 64 $pos$libresoc.v:111489$4382_Y + attribute \src "libresoc.v:111490.18-111490.107" + wire width 64 $pos$libresoc.v:111490$4384_Y + attribute \src "libresoc.v:111493.17-111493.104" + wire width 64 $pos$libresoc.v:111493$4388_Y + attribute \src "libresoc.v:111497.17-111497.102" + wire width 64 $pos$libresoc.v:111497$4393_Y + attribute \src "libresoc.v:111491.18-111491.114" + wire width 47 $sshl$libresoc.v:111491$4385_Y + attribute \src "libresoc.v:111492.18-111492.113" + wire width 27 $sshl$libresoc.v:111492$4386_Y + attribute \src "libresoc.v:111494.18-111494.113" + wire width 17 $sshl$libresoc.v:111494$4389_Y + attribute \src "libresoc.v:111495.18-111495.113" + wire width 17 $sshl$libresoc.v:111495$4390_Y + attribute \src "libresoc.v:111496.17-111496.109" + wire width 47 $sshl$libresoc.v:111496$4391_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:110528.7-110528.15" + attribute \src "libresoc.v:111411.7-111411.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -171696,80 +174000,80 @@ module \dec_bi$176 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110606$4300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111489$4381 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:110606$4300_Y + connect \Y $extend$libresoc.v:111489$4381_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110607$4302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111490$4383 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:110607$4302_Y + connect \Y $extend$libresoc.v:111490$4383_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110610$4306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111493$4387 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:110610$4306_Y + connect \Y $extend$libresoc.v:111493$4387_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:110614$4311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111497$4392 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:110614$4311_Y + connect \Y $extend$libresoc.v:111497$4392_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110606$4301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111489$4382 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110606$4300_Y - connect \Y $pos$libresoc.v:110606$4301_Y + connect \A $extend$libresoc.v:111489$4381_Y + connect \Y $pos$libresoc.v:111489$4382_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110607$4303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111490$4384 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110607$4302_Y - connect \Y $pos$libresoc.v:110607$4303_Y + connect \A $extend$libresoc.v:111490$4383_Y + connect \Y $pos$libresoc.v:111490$4384_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110610$4307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111493$4388 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110610$4306_Y - connect \Y $pos$libresoc.v:110610$4307_Y + connect \A $extend$libresoc.v:111493$4387_Y + connect \Y $pos$libresoc.v:111493$4388_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:110614$4312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111497$4393 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110614$4311_Y - connect \Y $pos$libresoc.v:110614$4312_Y + connect \A $extend$libresoc.v:111497$4392_Y + connect \Y $pos$libresoc.v:111497$4393_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:110608$4304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111491$4385 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -171777,10 +174081,10 @@ module \dec_bi$176 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:110608$4304_Y + connect \Y $sshl$libresoc.v:111491$4385_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:110609$4305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111492$4386 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -171788,10 +174092,10 @@ module \dec_bi$176 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:110609$4305_Y + connect \Y $sshl$libresoc.v:111492$4386_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:110611$4308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111494$4389 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -171799,10 +174103,10 @@ module \dec_bi$176 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:110611$4308_Y + connect \Y $sshl$libresoc.v:111494$4389_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:110612$4309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111495$4390 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -171810,10 +174114,10 @@ module \dec_bi$176 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:110612$4309_Y + connect \Y $sshl$libresoc.v:111495$4390_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:110613$4310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111496$4391 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -171821,28 +174125,28 @@ module \dec_bi$176 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:110613$4310_Y + connect \Y $sshl$libresoc.v:111496$4391_Y end - attribute \src "libresoc.v:110528.7-110528.20" - process $proc$libresoc.v:110528$4321 + attribute \src "libresoc.v:111411.7-111411.20" + process $proc$libresoc.v:111411$4402 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110616.3-110662.6" - process $proc$libresoc.v:110616$4313 + attribute \src "libresoc.v:111499.3-111545.6" + process $proc$libresoc.v:111499$4394 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110617.5-110617.29" + attribute \src "libresoc.v:111500.5-111500.29" switch \initial - attribute \src "libresoc.v:110617.9-110617.17" + attribute \src "libresoc.v:111500.9-111500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -171890,18 +174194,18 @@ module \dec_bi$176 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:110663.3-110709.6" - process $proc$libresoc.v:110663$4314 + attribute \src "libresoc.v:111546.3-111592.6" + process $proc$libresoc.v:111546$4395 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110664.5-110664.29" + attribute \src "libresoc.v:111547.5-111547.29" switch \initial - attribute \src "libresoc.v:110664.9-110664.17" + attribute \src "libresoc.v:111547.9-111547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -171949,18 +174253,18 @@ module \dec_bi$176 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:110710.3-110720.6" - process $proc$libresoc.v:110710$4315 + attribute \src "libresoc.v:111593.3-111603.6" + process $proc$libresoc.v:111593$4396 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110711.5-110711.29" + attribute \src "libresoc.v:111594.5-111594.29" switch \initial - attribute \src "libresoc.v:110711.9-110711.17" + attribute \src "libresoc.v:111594.9-111594.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -171972,18 +174276,18 @@ module \dec_bi$176 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:110721.3-110731.6" - process $proc$libresoc.v:110721$4316 + attribute \src "libresoc.v:111604.3-111614.6" + process $proc$libresoc.v:111604$4397 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110722.5-110722.29" + attribute \src "libresoc.v:111605.5-111605.29" switch \initial - attribute \src "libresoc.v:110722.9-110722.17" + attribute \src "libresoc.v:111605.9-111605.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -171995,18 +174299,18 @@ module \dec_bi$176 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:110732.3-110742.6" - process $proc$libresoc.v:110732$4317 + attribute \src "libresoc.v:111615.3-111625.6" + process $proc$libresoc.v:111615$4398 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110733.5-110733.29" + attribute \src "libresoc.v:111616.5-111616.29" switch \initial - attribute \src "libresoc.v:110733.9-110733.17" + attribute \src "libresoc.v:111616.9-111616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -172018,18 +174322,18 @@ module \dec_bi$176 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:110743.3-110753.6" - process $proc$libresoc.v:110743$4318 + attribute \src "libresoc.v:111626.3-111636.6" + process $proc$libresoc.v:111626$4399 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:110744.5-110744.29" + attribute \src "libresoc.v:111627.5-111627.29" switch \initial - attribute \src "libresoc.v:110744.9-110744.17" + attribute \src "libresoc.v:111627.9-111627.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -172041,18 +174345,18 @@ module \dec_bi$176 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:110754.3-110764.6" - process $proc$libresoc.v:110754$4319 + attribute \src "libresoc.v:111637.3-111647.6" + process $proc$libresoc.v:111637$4400 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:110755.5-110755.29" + attribute \src "libresoc.v:111638.5-111638.29" switch \initial - attribute \src "libresoc.v:110755.9-110755.17" + attribute \src "libresoc.v:111638.9-111638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -172064,18 +174368,18 @@ module \dec_bi$176 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:110765.3-110775.6" - process $proc$libresoc.v:110765$4320 + attribute \src "libresoc.v:111648.3-111658.6" + process $proc$libresoc.v:111648$4401 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:110766.5-110766.29" + attribute \src "libresoc.v:111649.5-111649.29" switch \initial - attribute \src "libresoc.v:110766.9-110766.17" + attribute \src "libresoc.v:111649.9-111649.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -172087,139 +174391,139 @@ module \dec_bi$176 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:110606$4301_Y - connect \$11 $pos$libresoc.v:110607$4303_Y - connect \$14 $sshl$libresoc.v:110608$4304_Y - connect \$17 $sshl$libresoc.v:110609$4305_Y - connect \$1 $pos$libresoc.v:110610$4307_Y - connect \$20 $sshl$libresoc.v:110611$4308_Y - connect \$23 $sshl$libresoc.v:110612$4309_Y - connect \$4 $sshl$libresoc.v:110613$4310_Y - connect \$3 $pos$libresoc.v:110614$4312_Y + connect \$9 $pos$libresoc.v:111489$4382_Y + connect \$11 $pos$libresoc.v:111490$4384_Y + connect \$14 $sshl$libresoc.v:111491$4385_Y + connect \$17 $sshl$libresoc.v:111492$4386_Y + connect \$1 $pos$libresoc.v:111493$4388_Y + connect \$20 $sshl$libresoc.v:111494$4389_Y + connect \$23 $sshl$libresoc.v:111495$4390_Y + connect \$4 $sshl$libresoc.v:111496$4391_Y + connect \$3 $pos$libresoc.v:111497$4393_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:110784.1-111037.10" +attribute \src "libresoc.v:111667.1-111920.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" -module \dec_bi$184 - attribute \src "libresoc.v:111011.3-111021.6" +module \dec_bi$187 + attribute \src "libresoc.v:111894.3-111904.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111022.3-111032.6" + attribute \src "libresoc.v:111905.3-111915.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110873.3-110919.6" + attribute \src "libresoc.v:111756.3-111802.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110920.3-110966.6" + attribute \src "libresoc.v:111803.3-111849.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110785.7-110785.20" + attribute \src "libresoc.v:111668.7-111668.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111000.3-111010.6" + attribute \src "libresoc.v:111883.3-111893.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110967.3-110977.6" + attribute \src "libresoc.v:111850.3-111860.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110978.3-110988.6" + attribute \src "libresoc.v:111861.3-111871.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110989.3-110999.6" + attribute \src "libresoc.v:111872.3-111882.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111011.3-111021.6" + attribute \src "libresoc.v:111894.3-111904.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111022.3-111032.6" + attribute \src "libresoc.v:111905.3-111915.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110873.3-110919.6" + attribute \src "libresoc.v:111756.3-111802.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110920.3-110966.6" + attribute \src "libresoc.v:111803.3-111849.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111000.3-111010.6" + attribute \src "libresoc.v:111883.3-111893.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110967.3-110977.6" + attribute \src "libresoc.v:111850.3-111860.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110978.3-110988.6" + attribute \src "libresoc.v:111861.3-111871.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110989.3-110999.6" + attribute \src "libresoc.v:111872.3-111882.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110863.17-110863.104" - wire width 64 $extend$libresoc.v:110863$4322_Y - attribute \src "libresoc.v:110864.18-110864.107" - wire width 64 $extend$libresoc.v:110864$4324_Y - attribute \src "libresoc.v:110867.17-110867.104" - wire width 64 $extend$libresoc.v:110867$4328_Y - attribute \src "libresoc.v:110871.17-110871.102" - wire width 64 $extend$libresoc.v:110871$4333_Y - attribute \src "libresoc.v:110863.17-110863.104" - wire width 64 $pos$libresoc.v:110863$4323_Y - attribute \src "libresoc.v:110864.18-110864.107" - wire width 64 $pos$libresoc.v:110864$4325_Y - attribute \src "libresoc.v:110867.17-110867.104" - wire width 64 $pos$libresoc.v:110867$4329_Y - attribute \src "libresoc.v:110871.17-110871.102" - wire width 64 $pos$libresoc.v:110871$4334_Y - attribute \src "libresoc.v:110865.18-110865.114" - wire width 47 $sshl$libresoc.v:110865$4326_Y - attribute \src "libresoc.v:110866.18-110866.113" - wire width 27 $sshl$libresoc.v:110866$4327_Y - attribute \src "libresoc.v:110868.18-110868.113" - wire width 17 $sshl$libresoc.v:110868$4330_Y - attribute \src "libresoc.v:110869.18-110869.113" - wire width 17 $sshl$libresoc.v:110869$4331_Y - attribute \src "libresoc.v:110870.17-110870.109" - wire width 47 $sshl$libresoc.v:110870$4332_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:111746.17-111746.104" + wire width 64 $extend$libresoc.v:111746$4403_Y + attribute \src "libresoc.v:111747.18-111747.107" + wire width 64 $extend$libresoc.v:111747$4405_Y + attribute \src "libresoc.v:111750.17-111750.104" + wire width 64 $extend$libresoc.v:111750$4409_Y + attribute \src "libresoc.v:111754.17-111754.102" + wire width 64 $extend$libresoc.v:111754$4414_Y + attribute \src "libresoc.v:111746.17-111746.104" + wire width 64 $pos$libresoc.v:111746$4404_Y + attribute \src "libresoc.v:111747.18-111747.107" + wire width 64 $pos$libresoc.v:111747$4406_Y + attribute \src "libresoc.v:111750.17-111750.104" + wire width 64 $pos$libresoc.v:111750$4410_Y + attribute \src "libresoc.v:111754.17-111754.102" + wire width 64 $pos$libresoc.v:111754$4415_Y + attribute \src "libresoc.v:111748.18-111748.114" + wire width 47 $sshl$libresoc.v:111748$4407_Y + attribute \src "libresoc.v:111749.18-111749.113" + wire width 27 $sshl$libresoc.v:111749$4408_Y + attribute \src "libresoc.v:111751.18-111751.113" + wire width 17 $sshl$libresoc.v:111751$4411_Y + attribute \src "libresoc.v:111752.18-111752.113" + wire width 17 $sshl$libresoc.v:111752$4412_Y + attribute \src "libresoc.v:111753.17-111753.109" + wire width 47 $sshl$libresoc.v:111753$4413_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:110785.7-110785.15" + attribute \src "libresoc.v:111668.7-111668.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -172236,80 +174540,80 @@ module \dec_bi$184 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110863$4322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111746$4403 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:110863$4322_Y + connect \Y $extend$libresoc.v:111746$4403_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110864$4324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111747$4405 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:110864$4324_Y + connect \Y $extend$libresoc.v:111747$4405_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:110867$4328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:111750$4409 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:110867$4328_Y + connect \Y $extend$libresoc.v:111750$4409_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:110871$4333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:111754$4414 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:110871$4333_Y + connect \Y $extend$libresoc.v:111754$4414_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110863$4323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111746$4404 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110863$4322_Y - connect \Y $pos$libresoc.v:110863$4323_Y + connect \A $extend$libresoc.v:111746$4403_Y + connect \Y $pos$libresoc.v:111746$4404_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110864$4325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111747$4406 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110864$4324_Y - connect \Y $pos$libresoc.v:110864$4325_Y + connect \A $extend$libresoc.v:111747$4405_Y + connect \Y $pos$libresoc.v:111747$4406_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:110867$4329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:111750$4410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110867$4328_Y - connect \Y $pos$libresoc.v:110867$4329_Y + connect \A $extend$libresoc.v:111750$4409_Y + connect \Y $pos$libresoc.v:111750$4410_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:110871$4334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:111754$4415 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110871$4333_Y - connect \Y $pos$libresoc.v:110871$4334_Y + connect \A $extend$libresoc.v:111754$4414_Y + connect \Y $pos$libresoc.v:111754$4415_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:110865$4326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:111748$4407 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -172317,10 +174621,10 @@ module \dec_bi$184 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:110865$4326_Y + connect \Y $sshl$libresoc.v:111748$4407_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:110866$4327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:111749$4408 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -172328,10 +174632,10 @@ module \dec_bi$184 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:110866$4327_Y + connect \Y $sshl$libresoc.v:111749$4408_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:110868$4330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:111751$4411 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -172339,10 +174643,10 @@ module \dec_bi$184 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:110868$4330_Y + connect \Y $sshl$libresoc.v:111751$4411_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:110869$4331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:111752$4412 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -172350,10 +174654,10 @@ module \dec_bi$184 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:110869$4331_Y + connect \Y $sshl$libresoc.v:111752$4412_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:110870$4332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:111753$4413 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -172361,28 +174665,28 @@ module \dec_bi$184 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:110870$4332_Y + connect \Y $sshl$libresoc.v:111753$4413_Y end - attribute \src "libresoc.v:110785.7-110785.20" - process $proc$libresoc.v:110785$4343 + attribute \src "libresoc.v:111668.7-111668.20" + process $proc$libresoc.v:111668$4424 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110873.3-110919.6" - process $proc$libresoc.v:110873$4335 + attribute \src "libresoc.v:111756.3-111802.6" + process $proc$libresoc.v:111756$4416 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110874.5-110874.29" + attribute \src "libresoc.v:111757.5-111757.29" switch \initial - attribute \src "libresoc.v:110874.9-110874.17" + attribute \src "libresoc.v:111757.9-111757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -172430,18 +174734,18 @@ module \dec_bi$184 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:110920.3-110966.6" - process $proc$libresoc.v:110920$4336 + attribute \src "libresoc.v:111803.3-111849.6" + process $proc$libresoc.v:111803$4417 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110921.5-110921.29" + attribute \src "libresoc.v:111804.5-111804.29" switch \initial - attribute \src "libresoc.v:110921.9-110921.17" + attribute \src "libresoc.v:111804.9-111804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -172489,18 +174793,18 @@ module \dec_bi$184 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:110967.3-110977.6" - process $proc$libresoc.v:110967$4337 + attribute \src "libresoc.v:111850.3-111860.6" + process $proc$libresoc.v:111850$4418 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:110968.5-110968.29" + attribute \src "libresoc.v:111851.5-111851.29" switch \initial - attribute \src "libresoc.v:110968.9-110968.17" + attribute \src "libresoc.v:111851.9-111851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -172512,18 +174816,18 @@ module \dec_bi$184 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:110978.3-110988.6" - process $proc$libresoc.v:110978$4338 + attribute \src "libresoc.v:111861.3-111871.6" + process $proc$libresoc.v:111861$4419 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:110979.5-110979.29" + attribute \src "libresoc.v:111862.5-111862.29" switch \initial - attribute \src "libresoc.v:110979.9-110979.17" + attribute \src "libresoc.v:111862.9-111862.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -172535,18 +174839,18 @@ module \dec_bi$184 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:110989.3-110999.6" - process $proc$libresoc.v:110989$4339 + attribute \src "libresoc.v:111872.3-111882.6" + process $proc$libresoc.v:111872$4420 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:110990.5-110990.29" + attribute \src "libresoc.v:111873.5-111873.29" switch \initial - attribute \src "libresoc.v:110990.9-110990.17" + attribute \src "libresoc.v:111873.9-111873.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -172558,18 +174862,18 @@ module \dec_bi$184 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:111000.3-111010.6" - process $proc$libresoc.v:111000$4340 + attribute \src "libresoc.v:111883.3-111893.6" + process $proc$libresoc.v:111883$4421 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111001.5-111001.29" + attribute \src "libresoc.v:111884.5-111884.29" switch \initial - attribute \src "libresoc.v:111001.9-111001.17" + attribute \src "libresoc.v:111884.9-111884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -172581,18 +174885,18 @@ module \dec_bi$184 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:111011.3-111021.6" - process $proc$libresoc.v:111011$4341 + attribute \src "libresoc.v:111894.3-111904.6" + process $proc$libresoc.v:111894$4422 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111012.5-111012.29" + attribute \src "libresoc.v:111895.5-111895.29" switch \initial - attribute \src "libresoc.v:111012.9-111012.17" + attribute \src "libresoc.v:111895.9-111895.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -172604,18 +174908,18 @@ module \dec_bi$184 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:111022.3-111032.6" - process $proc$libresoc.v:111022$4342 + attribute \src "libresoc.v:111905.3-111915.6" + process $proc$libresoc.v:111905$4423 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111023.5-111023.29" + attribute \src "libresoc.v:111906.5-111906.29" switch \initial - attribute \src "libresoc.v:111023.9-111023.17" + attribute \src "libresoc.v:111906.9-111906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -172627,139 +174931,139 @@ module \dec_bi$184 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:110863$4323_Y - connect \$11 $pos$libresoc.v:110864$4325_Y - connect \$14 $sshl$libresoc.v:110865$4326_Y - connect \$17 $sshl$libresoc.v:110866$4327_Y - connect \$1 $pos$libresoc.v:110867$4329_Y - connect \$20 $sshl$libresoc.v:110868$4330_Y - connect \$23 $sshl$libresoc.v:110869$4331_Y - connect \$4 $sshl$libresoc.v:110870$4332_Y - connect \$3 $pos$libresoc.v:110871$4334_Y + connect \$9 $pos$libresoc.v:111746$4404_Y + connect \$11 $pos$libresoc.v:111747$4406_Y + connect \$14 $sshl$libresoc.v:111748$4407_Y + connect \$17 $sshl$libresoc.v:111749$4408_Y + connect \$1 $pos$libresoc.v:111750$4410_Y + connect \$20 $sshl$libresoc.v:111751$4411_Y + connect \$23 $sshl$libresoc.v:111752$4412_Y + connect \$4 $sshl$libresoc.v:111753$4413_Y + connect \$3 $pos$libresoc.v:111754$4415_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:111041.1-111294.10" +attribute \src "libresoc.v:111924.1-112177.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" -module \dec_bi$192 - attribute \src "libresoc.v:111268.3-111278.6" +module \dec_bi$195 + attribute \src "libresoc.v:112151.3-112161.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111279.3-111289.6" + attribute \src "libresoc.v:112162.3-112172.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111130.3-111176.6" + attribute \src "libresoc.v:112013.3-112059.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111177.3-111223.6" + attribute \src "libresoc.v:112060.3-112106.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111042.7-111042.20" + attribute \src "libresoc.v:111925.7-111925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111257.3-111267.6" + attribute \src "libresoc.v:112140.3-112150.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111224.3-111234.6" + attribute \src "libresoc.v:112107.3-112117.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111235.3-111245.6" + attribute \src "libresoc.v:112118.3-112128.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111246.3-111256.6" + attribute \src "libresoc.v:112129.3-112139.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111268.3-111278.6" + attribute \src "libresoc.v:112151.3-112161.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111279.3-111289.6" + attribute \src "libresoc.v:112162.3-112172.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:111130.3-111176.6" + attribute \src "libresoc.v:112013.3-112059.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:111177.3-111223.6" + attribute \src "libresoc.v:112060.3-112106.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111257.3-111267.6" + attribute \src "libresoc.v:112140.3-112150.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:111224.3-111234.6" + attribute \src "libresoc.v:112107.3-112117.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:111235.3-111245.6" + attribute \src "libresoc.v:112118.3-112128.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:111246.3-111256.6" + attribute \src "libresoc.v:112129.3-112139.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:111120.17-111120.110" - wire width 64 $extend$libresoc.v:111120$4344_Y - attribute \src "libresoc.v:111121.18-111121.113" - wire width 64 $extend$libresoc.v:111121$4346_Y - attribute \src "libresoc.v:111124.17-111124.110" - wire width 64 $extend$libresoc.v:111124$4350_Y - attribute \src "libresoc.v:111128.17-111128.102" - wire width 64 $extend$libresoc.v:111128$4355_Y - attribute \src "libresoc.v:111120.17-111120.110" - wire width 64 $pos$libresoc.v:111120$4345_Y - attribute \src "libresoc.v:111121.18-111121.113" - wire width 64 $pos$libresoc.v:111121$4347_Y - attribute \src "libresoc.v:111124.17-111124.110" - wire width 64 $pos$libresoc.v:111124$4351_Y - attribute \src "libresoc.v:111128.17-111128.102" - wire width 64 $pos$libresoc.v:111128$4356_Y - attribute \src "libresoc.v:111122.18-111122.120" - wire width 47 $sshl$libresoc.v:111122$4348_Y - attribute \src "libresoc.v:111123.18-111123.119" - wire width 27 $sshl$libresoc.v:111123$4349_Y - attribute \src "libresoc.v:111125.18-111125.119" - wire width 17 $sshl$libresoc.v:111125$4352_Y - attribute \src "libresoc.v:111126.18-111126.119" - wire width 17 $sshl$libresoc.v:111126$4353_Y - attribute \src "libresoc.v:111127.17-111127.109" - wire width 47 $sshl$libresoc.v:111127$4354_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:112003.17-112003.110" + wire width 64 $extend$libresoc.v:112003$4425_Y + attribute \src "libresoc.v:112004.18-112004.113" + wire width 64 $extend$libresoc.v:112004$4427_Y + attribute \src "libresoc.v:112007.17-112007.110" + wire width 64 $extend$libresoc.v:112007$4431_Y + attribute \src "libresoc.v:112011.17-112011.102" + wire width 64 $extend$libresoc.v:112011$4436_Y + attribute \src "libresoc.v:112003.17-112003.110" + wire width 64 $pos$libresoc.v:112003$4426_Y + attribute \src "libresoc.v:112004.18-112004.113" + wire width 64 $pos$libresoc.v:112004$4428_Y + attribute \src "libresoc.v:112007.17-112007.110" + wire width 64 $pos$libresoc.v:112007$4432_Y + attribute \src "libresoc.v:112011.17-112011.102" + wire width 64 $pos$libresoc.v:112011$4437_Y + attribute \src "libresoc.v:112005.18-112005.120" + wire width 47 $sshl$libresoc.v:112005$4429_Y + attribute \src "libresoc.v:112006.18-112006.119" + wire width 27 $sshl$libresoc.v:112006$4430_Y + attribute \src "libresoc.v:112008.18-112008.119" + wire width 17 $sshl$libresoc.v:112008$4433_Y + attribute \src "libresoc.v:112009.18-112009.119" + wire width 17 $sshl$libresoc.v:112009$4434_Y + attribute \src "libresoc.v:112010.17-112010.109" + wire width 47 $sshl$libresoc.v:112010$4435_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:111042.7-111042.15" + attribute \src "libresoc.v:111925.7-111925.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -172776,80 +175080,80 @@ module \dec_bi$192 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111120$4344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112003$4425 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:111120$4344_Y + connect \Y $extend$libresoc.v:112003$4425_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111121$4346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112004$4427 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:111121$4346_Y + connect \Y $extend$libresoc.v:112004$4427_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111124$4350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112007$4431 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:111124$4350_Y + connect \Y $extend$libresoc.v:112007$4431_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:111128$4355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:112011$4436 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:111128$4355_Y + connect \Y $extend$libresoc.v:112011$4436_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111120$4345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112003$4426 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111120$4344_Y - connect \Y $pos$libresoc.v:111120$4345_Y + connect \A $extend$libresoc.v:112003$4425_Y + connect \Y $pos$libresoc.v:112003$4426_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111121$4347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112004$4428 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111121$4346_Y - connect \Y $pos$libresoc.v:111121$4347_Y + connect \A $extend$libresoc.v:112004$4427_Y + connect \Y $pos$libresoc.v:112004$4428_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111124$4351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112007$4432 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111124$4350_Y - connect \Y $pos$libresoc.v:111124$4351_Y + connect \A $extend$libresoc.v:112007$4431_Y + connect \Y $pos$libresoc.v:112007$4432_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:111128$4356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:112011$4437 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111128$4355_Y - connect \Y $pos$libresoc.v:111128$4356_Y + connect \A $extend$libresoc.v:112011$4436_Y + connect \Y $pos$libresoc.v:112011$4437_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:111122$4348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:112005$4429 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -172857,10 +175161,10 @@ module \dec_bi$192 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:111122$4348_Y + connect \Y $sshl$libresoc.v:112005$4429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:111123$4349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:112006$4430 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -172868,10 +175172,10 @@ module \dec_bi$192 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:111123$4349_Y + connect \Y $sshl$libresoc.v:112006$4430_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:111125$4352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:112008$4433 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -172879,10 +175183,10 @@ module \dec_bi$192 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:111125$4352_Y + connect \Y $sshl$libresoc.v:112008$4433_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:111126$4353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:112009$4434 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -172890,10 +175194,10 @@ module \dec_bi$192 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:111126$4353_Y + connect \Y $sshl$libresoc.v:112009$4434_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:111127$4354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:112010$4435 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -172901,28 +175205,28 @@ module \dec_bi$192 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:111127$4354_Y + connect \Y $sshl$libresoc.v:112010$4435_Y end - attribute \src "libresoc.v:111042.7-111042.20" - process $proc$libresoc.v:111042$4365 + attribute \src "libresoc.v:111925.7-111925.20" + process $proc$libresoc.v:111925$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111130.3-111176.6" - process $proc$libresoc.v:111130$4357 + attribute \src "libresoc.v:112013.3-112059.6" + process $proc$libresoc.v:112013$4438 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111131.5-111131.29" + attribute \src "libresoc.v:112014.5-112014.29" switch \initial - attribute \src "libresoc.v:111131.9-111131.17" + attribute \src "libresoc.v:112014.9-112014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -172970,18 +175274,18 @@ module \dec_bi$192 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:111177.3-111223.6" - process $proc$libresoc.v:111177$4358 + attribute \src "libresoc.v:112060.3-112106.6" + process $proc$libresoc.v:112060$4439 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111178.5-111178.29" + attribute \src "libresoc.v:112061.5-112061.29" switch \initial - attribute \src "libresoc.v:111178.9-111178.17" + attribute \src "libresoc.v:112061.9-112061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -173029,18 +175333,18 @@ module \dec_bi$192 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:111224.3-111234.6" - process $proc$libresoc.v:111224$4359 + attribute \src "libresoc.v:112107.3-112117.6" + process $proc$libresoc.v:112107$4440 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111225.5-111225.29" + attribute \src "libresoc.v:112108.5-112108.29" switch \initial - attribute \src "libresoc.v:111225.9-111225.17" + attribute \src "libresoc.v:112108.9-112108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -173052,18 +175356,18 @@ module \dec_bi$192 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:111235.3-111245.6" - process $proc$libresoc.v:111235$4360 + attribute \src "libresoc.v:112118.3-112128.6" + process $proc$libresoc.v:112118$4441 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111236.5-111236.29" + attribute \src "libresoc.v:112119.5-112119.29" switch \initial - attribute \src "libresoc.v:111236.9-111236.17" + attribute \src "libresoc.v:112119.9-112119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -173075,18 +175379,18 @@ module \dec_bi$192 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:111246.3-111256.6" - process $proc$libresoc.v:111246$4361 + attribute \src "libresoc.v:112129.3-112139.6" + process $proc$libresoc.v:112129$4442 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111247.5-111247.29" + attribute \src "libresoc.v:112130.5-112130.29" switch \initial - attribute \src "libresoc.v:111247.9-111247.17" + attribute \src "libresoc.v:112130.9-112130.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -173098,18 +175402,18 @@ module \dec_bi$192 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:111257.3-111267.6" - process $proc$libresoc.v:111257$4362 + attribute \src "libresoc.v:112140.3-112150.6" + process $proc$libresoc.v:112140$4443 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111258.5-111258.29" + attribute \src "libresoc.v:112141.5-112141.29" switch \initial - attribute \src "libresoc.v:111258.9-111258.17" + attribute \src "libresoc.v:112141.9-112141.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -173121,18 +175425,18 @@ module \dec_bi$192 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:111268.3-111278.6" - process $proc$libresoc.v:111268$4363 + attribute \src "libresoc.v:112151.3-112161.6" + process $proc$libresoc.v:112151$4444 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111269.5-111269.29" + attribute \src "libresoc.v:112152.5-112152.29" switch \initial - attribute \src "libresoc.v:111269.9-111269.17" + attribute \src "libresoc.v:112152.9-112152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -173144,18 +175448,18 @@ module \dec_bi$192 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:111279.3-111289.6" - process $proc$libresoc.v:111279$4364 + attribute \src "libresoc.v:112162.3-112172.6" + process $proc$libresoc.v:112162$4445 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111280.5-111280.29" + attribute \src "libresoc.v:112163.5-112163.29" switch \initial - attribute \src "libresoc.v:111280.9-111280.17" + attribute \src "libresoc.v:112163.9-112163.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -173167,139 +175471,139 @@ module \dec_bi$192 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:111120$4345_Y - connect \$11 $pos$libresoc.v:111121$4347_Y - connect \$14 $sshl$libresoc.v:111122$4348_Y - connect \$17 $sshl$libresoc.v:111123$4349_Y - connect \$1 $pos$libresoc.v:111124$4351_Y - connect \$20 $sshl$libresoc.v:111125$4352_Y - connect \$23 $sshl$libresoc.v:111126$4353_Y - connect \$4 $sshl$libresoc.v:111127$4354_Y - connect \$3 $pos$libresoc.v:111128$4356_Y + connect \$9 $pos$libresoc.v:112003$4426_Y + connect \$11 $pos$libresoc.v:112004$4428_Y + connect \$14 $sshl$libresoc.v:112005$4429_Y + connect \$17 $sshl$libresoc.v:112006$4430_Y + connect \$1 $pos$libresoc.v:112007$4432_Y + connect \$20 $sshl$libresoc.v:112008$4433_Y + connect \$23 $sshl$libresoc.v:112009$4434_Y + connect \$4 $sshl$libresoc.v:112010$4435_Y + connect \$3 $pos$libresoc.v:112011$4437_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:111298.1-111551.10" +attribute \src "libresoc.v:112181.1-112434.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_bi" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" -module \dec_bi$201 - attribute \src "libresoc.v:111525.3-111535.6" +module \dec_bi$204 + attribute \src "libresoc.v:112408.3-112418.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111536.3-111546.6" + attribute \src "libresoc.v:112419.3-112429.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111387.3-111433.6" + attribute \src "libresoc.v:112270.3-112316.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111434.3-111480.6" + attribute \src "libresoc.v:112317.3-112363.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111299.7-111299.20" + attribute \src "libresoc.v:112182.7-112182.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111514.3-111524.6" + attribute \src "libresoc.v:112397.3-112407.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111481.3-111491.6" + attribute \src "libresoc.v:112364.3-112374.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111492.3-111502.6" + attribute \src "libresoc.v:112375.3-112385.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111503.3-111513.6" + attribute \src "libresoc.v:112386.3-112396.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111525.3-111535.6" + attribute \src "libresoc.v:112408.3-112418.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111536.3-111546.6" + attribute \src "libresoc.v:112419.3-112429.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:111387.3-111433.6" + attribute \src "libresoc.v:112270.3-112316.6" wire width 64 $1\imm_b[63:0] - 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$extend$libresoc.v:111385$4377_Y - attribute \src "libresoc.v:111377.17-111377.105" - wire width 64 $pos$libresoc.v:111377$4367_Y - attribute \src "libresoc.v:111378.18-111378.108" - wire width 64 $pos$libresoc.v:111378$4369_Y - attribute \src "libresoc.v:111381.17-111381.105" - wire width 64 $pos$libresoc.v:111381$4373_Y - attribute \src "libresoc.v:111385.17-111385.102" - wire width 64 $pos$libresoc.v:111385$4378_Y - attribute \src "libresoc.v:111379.18-111379.115" - wire width 47 $sshl$libresoc.v:111379$4370_Y - attribute \src "libresoc.v:111380.18-111380.114" - wire width 27 $sshl$libresoc.v:111380$4371_Y - attribute \src "libresoc.v:111382.18-111382.114" - wire width 17 $sshl$libresoc.v:111382$4374_Y - attribute \src "libresoc.v:111383.18-111383.114" - wire width 17 $sshl$libresoc.v:111383$4375_Y - attribute \src "libresoc.v:111384.17-111384.109" - wire width 47 $sshl$libresoc.v:111384$4376_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "libresoc.v:112260.17-112260.105" + wire width 64 $extend$libresoc.v:112260$4447_Y + attribute \src "libresoc.v:112261.18-112261.108" + wire width 64 $extend$libresoc.v:112261$4449_Y + attribute \src "libresoc.v:112264.17-112264.105" + wire width 64 $extend$libresoc.v:112264$4453_Y + attribute \src "libresoc.v:112268.17-112268.102" + wire width 64 $extend$libresoc.v:112268$4458_Y + attribute \src "libresoc.v:112260.17-112260.105" + wire width 64 $pos$libresoc.v:112260$4448_Y + attribute \src "libresoc.v:112261.18-112261.108" + wire width 64 $pos$libresoc.v:112261$4450_Y + attribute \src "libresoc.v:112264.17-112264.105" + wire width 64 $pos$libresoc.v:112264$4454_Y + attribute \src "libresoc.v:112268.17-112268.102" + wire width 64 $pos$libresoc.v:112268$4459_Y + attribute \src "libresoc.v:112262.18-112262.115" + wire width 47 $sshl$libresoc.v:112262$4451_Y + attribute \src "libresoc.v:112263.18-112263.114" + wire width 27 $sshl$libresoc.v:112263$4452_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 8 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 14 input 9 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 24 input 7 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 3 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 16 input 4 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:111299.7-111299.15" + attribute \src "libresoc.v:112182.7-112182.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -173316,80 +175620,80 @@ module \dec_bi$201 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111377$4366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112260$4447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:111377$4366_Y + connect \Y $extend$libresoc.v:112260$4447_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111378$4368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112261$4449 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:111378$4368_Y + connect \Y $extend$libresoc.v:112261$4449_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:111381$4372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:112264$4453 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:111381$4372_Y + connect \Y $extend$libresoc.v:112264$4453_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $extend$libresoc.v:111385$4377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $extend$libresoc.v:112268$4458 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:111385$4377_Y + connect \Y $extend$libresoc.v:112268$4458_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111377$4367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112260$4448 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111377$4366_Y - connect \Y $pos$libresoc.v:111377$4367_Y + connect \A $extend$libresoc.v:112260$4447_Y + connect \Y $pos$libresoc.v:112260$4448_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111378$4369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112261$4450 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111378$4368_Y - connect \Y $pos$libresoc.v:111378$4369_Y + connect \A $extend$libresoc.v:112261$4449_Y + connect \Y $pos$libresoc.v:112261$4450_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:111381$4373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:112264$4454 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111381$4372_Y - connect \Y $pos$libresoc.v:111381$4373_Y + connect \A $extend$libresoc.v:112264$4453_Y + connect \Y $pos$libresoc.v:112264$4454_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $pos$libresoc.v:111385$4378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $pos $pos$libresoc.v:112268$4459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111385$4377_Y - connect \Y $pos$libresoc.v:111385$4378_Y + connect \A $extend$libresoc.v:112268$4458_Y + connect \Y $pos$libresoc.v:112268$4459_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $sshl$libresoc.v:111379$4370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + cell $sshl $sshl$libresoc.v:112262$4451 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -173397,10 +175701,10 @@ module \dec_bi$201 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:111379$4370_Y + connect \Y $sshl$libresoc.v:112262$4451_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $sshl$libresoc.v:111380$4371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + cell $sshl $sshl$libresoc.v:112263$4452 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -173408,10 +175712,10 @@ module \dec_bi$201 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:111380$4371_Y + connect \Y $sshl$libresoc.v:112263$4452_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $sshl$libresoc.v:111382$4374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" + cell $sshl $sshl$libresoc.v:112265$4455 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -173419,10 +175723,10 @@ module \dec_bi$201 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:111382$4374_Y + connect \Y $sshl$libresoc.v:112265$4455_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:111383$4375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + cell $sshl $sshl$libresoc.v:112266$4456 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -173430,10 +175734,10 @@ module \dec_bi$201 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:111383$4375_Y + connect \Y $sshl$libresoc.v:112266$4456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $sshl$libresoc.v:111384$4376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + cell $sshl $sshl$libresoc.v:112267$4457 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -173441,28 +175745,28 @@ module \dec_bi$201 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:111384$4376_Y + connect \Y $sshl$libresoc.v:112267$4457_Y end - attribute \src "libresoc.v:111299.7-111299.20" - process $proc$libresoc.v:111299$4387 + attribute \src "libresoc.v:112182.7-112182.20" + process $proc$libresoc.v:112182$4468 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111387.3-111433.6" - process $proc$libresoc.v:111387$4379 + attribute \src "libresoc.v:112270.3-112316.6" + process $proc$libresoc.v:112270$4460 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111388.5-111388.29" + attribute \src "libresoc.v:112271.5-112271.29" switch \initial - attribute \src "libresoc.v:111388.9-111388.17" + attribute \src "libresoc.v:112271.9-112271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -173510,18 +175814,18 @@ module \dec_bi$201 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:111434.3-111480.6" - process $proc$libresoc.v:111434$4380 + attribute \src "libresoc.v:112317.3-112363.6" + process $proc$libresoc.v:112317$4461 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111435.5-111435.29" + attribute \src "libresoc.v:112318.5-112318.29" switch \initial - attribute \src "libresoc.v:111435.9-111435.17" + attribute \src "libresoc.v:112318.9-112318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -173569,18 +175873,18 @@ module \dec_bi$201 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:111481.3-111491.6" - process $proc$libresoc.v:111481$4381 + attribute \src "libresoc.v:112364.3-112374.6" + process $proc$libresoc.v:112364$4462 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111482.5-111482.29" + attribute \src "libresoc.v:112365.5-112365.29" switch \initial - attribute \src "libresoc.v:111482.9-111482.17" + attribute \src "libresoc.v:112365.9-112365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -173592,18 +175896,18 @@ module \dec_bi$201 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:111492.3-111502.6" - process $proc$libresoc.v:111492$4382 + attribute \src "libresoc.v:112375.3-112385.6" + process $proc$libresoc.v:112375$4463 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111493.5-111493.29" + attribute \src "libresoc.v:112376.5-112376.29" switch \initial - attribute \src "libresoc.v:111493.9-111493.17" + attribute \src "libresoc.v:112376.9-112376.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -173615,18 +175919,18 @@ module \dec_bi$201 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:111503.3-111513.6" - process $proc$libresoc.v:111503$4383 + attribute \src "libresoc.v:112386.3-112396.6" + process $proc$libresoc.v:112386$4464 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111504.5-111504.29" + attribute \src "libresoc.v:112387.5-112387.29" switch \initial - attribute \src "libresoc.v:111504.9-111504.17" + attribute \src "libresoc.v:112387.9-112387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -173638,18 +175942,18 @@ module \dec_bi$201 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:111514.3-111524.6" - process $proc$libresoc.v:111514$4384 + attribute \src "libresoc.v:112397.3-112407.6" + process $proc$libresoc.v:112397$4465 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111515.5-111515.29" + attribute \src "libresoc.v:112398.5-112398.29" switch \initial - attribute \src "libresoc.v:111515.9-111515.17" + attribute \src "libresoc.v:112398.9-112398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -173661,18 +175965,18 @@ module \dec_bi$201 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:111525.3-111535.6" - process $proc$libresoc.v:111525$4385 + attribute \src "libresoc.v:112408.3-112418.6" + process $proc$libresoc.v:112408$4466 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111526.5-111526.29" + attribute \src "libresoc.v:112409.5-112409.29" switch \initial - attribute \src "libresoc.v:111526.9-111526.17" + attribute \src "libresoc.v:112409.9-112409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -173684,18 +175988,18 @@ module \dec_bi$201 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:111536.3-111546.6" - process $proc$libresoc.v:111536$4386 + attribute \src "libresoc.v:112419.3-112429.6" + process $proc$libresoc.v:112419$4467 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111537.5-111537.29" + attribute \src "libresoc.v:112420.5-112420.29" switch \initial - attribute \src "libresoc.v:111537.9-111537.17" + attribute \src "libresoc.v:112420.9-112420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -173707,72 +176011,72 @@ module \dec_bi$201 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:111377$4367_Y - connect \$11 $pos$libresoc.v:111378$4369_Y - connect \$14 $sshl$libresoc.v:111379$4370_Y - connect \$17 $sshl$libresoc.v:111380$4371_Y - connect \$1 $pos$libresoc.v:111381$4373_Y - connect \$20 $sshl$libresoc.v:111382$4374_Y - connect \$23 $sshl$libresoc.v:111383$4375_Y - connect \$4 $sshl$libresoc.v:111384$4376_Y - connect \$3 $pos$libresoc.v:111385$4378_Y + connect \$9 $pos$libresoc.v:112260$4448_Y + connect \$11 $pos$libresoc.v:112261$4450_Y + connect \$14 $sshl$libresoc.v:112262$4451_Y + connect \$17 $sshl$libresoc.v:112263$4452_Y + connect \$1 $pos$libresoc.v:112264$4454_Y + connect \$20 $sshl$libresoc.v:112265$4455_Y + connect \$23 $sshl$libresoc.v:112266$4456_Y + connect \$4 $sshl$libresoc.v:112267$4457_Y + connect \$3 $pos$libresoc.v:112268$4459_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:111555.1-111603.10" +attribute \src "libresoc.v:112438.1-112486.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_c" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:111556.7-111556.20" + attribute \src "libresoc.v:112439.7-112439.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111573.3-111587.6" + attribute \src "libresoc.v:112456.3-112470.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:111588.3-111602.6" + attribute \src "libresoc.v:112471.3-112485.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:111573.3-111587.6" + attribute \src "libresoc.v:112456.3-112470.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:111588.3-111602.6" + attribute \src "libresoc.v:112471.3-112485.6" wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \RS - attribute \src "libresoc.v:111556.7-111556.15" + attribute \src "libresoc.v:112439.7-112439.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \reg_c_ok attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:111556.7-111556.20" - process $proc$libresoc.v:111556$4390 + attribute \src "libresoc.v:112439.7-112439.20" + process $proc$libresoc.v:112439$4471 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111573.3-111587.6" - process $proc$libresoc.v:111573$4388 + attribute \src "libresoc.v:112456.3-112470.6" + process $proc$libresoc.v:112456$4469 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:111574.5-111574.29" + attribute \src "libresoc.v:112457.5-112457.29" switch \initial - attribute \src "libresoc.v:111574.9-111574.17" + attribute \src "libresoc.v:112457.9-112457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -173788,18 +176092,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:111588.3-111602.6" - process $proc$libresoc.v:111588$4389 + attribute \src "libresoc.v:112471.3-112485.6" + process $proc$libresoc.v:112471$4470 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:111589.5-111589.29" + attribute \src "libresoc.v:112472.5-112472.29" switch \initial - attribute \src "libresoc.v:111589.9-111589.17" + attribute \src "libresoc.v:112472.9-112472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -173816,84 +176120,84 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:111607.1-111904.10" +attribute \src "libresoc.v:112490.1-112787.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:111798.3-111824.6" + attribute \src "libresoc.v:112681.3-112707.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:111825.3-111835.6" + attribute \src "libresoc.v:112708.3-112718.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:111776.3-111786.6" + attribute \src "libresoc.v:112659.3-112669.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:111836.3-111846.6" + attribute \src "libresoc.v:112719.3-112729.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:111847.3-111857.6" + attribute \src "libresoc.v:112730.3-112740.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:111749.3-111775.6" + attribute \src "libresoc.v:112632.3-112658.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:111885.3-111903.6" + attribute \src "libresoc.v:112768.3-112786.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:111787.3-111797.6" + attribute \src "libresoc.v:112670.3-112680.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:111608.7-111608.20" + attribute \src "libresoc.v:112491.7-112491.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111858.3-111868.6" + attribute \src "libresoc.v:112741.3-112751.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:111869.3-111884.6" + attribute \src "libresoc.v:112752.3-112767.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:111798.3-111824.6" + attribute \src "libresoc.v:112681.3-112707.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:111825.3-111835.6" + attribute \src "libresoc.v:112708.3-112718.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:111776.3-111786.6" + attribute \src "libresoc.v:112659.3-112669.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:111836.3-111846.6" + attribute \src "libresoc.v:112719.3-112729.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:111847.3-111857.6" + attribute \src "libresoc.v:112730.3-112740.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:111749.3-111775.6" + attribute \src "libresoc.v:112632.3-112658.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:111885.3-111903.6" + attribute \src "libresoc.v:112768.3-112786.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:111787.3-111797.6" + attribute \src "libresoc.v:112670.3-112680.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:111858.3-111868.6" + attribute \src "libresoc.v:112741.3-112751.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:111869.3-111884.6" + attribute \src "libresoc.v:112752.3-112767.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:111885.3-111903.6" + attribute \src "libresoc.v:112768.3-112786.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:111869.3-111884.6" + attribute \src "libresoc.v:112752.3-112767.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:111742.17-111742.112" - wire $and$libresoc.v:111742$4392_Y - attribute \src "libresoc.v:111744.17-111744.112" - wire $and$libresoc.v:111744$4394_Y - attribute \src "libresoc.v:111741.17-111741.121" - wire $eq$libresoc.v:111741$4391_Y - attribute \src "libresoc.v:111743.17-111743.121" - wire $eq$libresoc.v:111743$4393_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:112625.17-112625.112" + wire $and$libresoc.v:112625$4473_Y + attribute \src "libresoc.v:112627.17-112627.112" + wire $and$libresoc.v:112627$4475_Y + attribute \src "libresoc.v:112624.17-112624.121" + wire $eq$libresoc.v:112624$4472_Y + attribute \src "libresoc.v:112626.17-112626.121" + wire $eq$libresoc.v:112626$4474_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \ALU_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -173969,31 +176273,31 @@ module \dec_cr_in attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:111608.7-111608.15" + attribute \src "libresoc.v:112491.7-112491.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -174007,10 +176311,10 @@ module \dec_cr_in attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:111742$4392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112625$4473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -174018,10 +176322,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:111742$4392_Y + connect \Y $and$libresoc.v:112625$4473_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:111744$4394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112627$4475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -174029,10 +176333,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:111744$4394_Y + connect \Y $and$libresoc.v:112627$4475_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:111741$4391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112624$4472 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -174040,10 +176344,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \ALU_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:111741$4391_Y + connect \Y $eq$libresoc.v:112624$4472_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:111743$4393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112626$4474 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -174051,34 +176355,34 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \ALU_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:111743$4393_Y + connect \Y $eq$libresoc.v:112626$4474_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:111745.9-111748.4" + attribute \src "libresoc.v:112628.9-112631.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:111608.7-111608.20" - process $proc$libresoc.v:111608$4405 + attribute \src "libresoc.v:112491.7-112491.20" + process $proc$libresoc.v:112491$4486 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111749.3-111775.6" - process $proc$libresoc.v:111749$4395 + attribute \src "libresoc.v:112632.3-112658.6" + process $proc$libresoc.v:112632$4476 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:111750.5-111750.29" + attribute \src "libresoc.v:112633.5-112633.29" switch \initial - attribute \src "libresoc.v:111750.9-111750.17" + attribute \src "libresoc.v:112633.9-112633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -174106,18 +176410,18 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:111776.3-111786.6" - process $proc$libresoc.v:111776$4396 + attribute \src "libresoc.v:112659.3-112669.6" + process $proc$libresoc.v:112659$4477 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:111777.5-111777.29" + attribute \src "libresoc.v:112660.5-112660.29" switch \initial - attribute \src "libresoc.v:111777.9-111777.17" + attribute \src "libresoc.v:112660.9-112660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174129,18 +176433,18 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:111787.3-111797.6" - process $proc$libresoc.v:111787$4397 + attribute \src "libresoc.v:112670.3-112680.6" + process $proc$libresoc.v:112670$4478 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:111788.5-111788.29" + attribute \src "libresoc.v:112671.5-112671.29" switch \initial - attribute \src "libresoc.v:111788.9-111788.17" + attribute \src "libresoc.v:112671.9-112671.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -174152,18 +176456,18 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:111798.3-111824.6" - process $proc$libresoc.v:111798$4398 + attribute \src "libresoc.v:112681.3-112707.6" + process $proc$libresoc.v:112681$4479 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:111799.5-111799.29" + attribute \src "libresoc.v:112682.5-112682.29" switch \initial - attribute \src "libresoc.v:111799.9-111799.17" + attribute \src "libresoc.v:112682.9-112682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -174191,18 +176495,18 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:111825.3-111835.6" - process $proc$libresoc.v:111825$4399 + attribute \src "libresoc.v:112708.3-112718.6" + process $proc$libresoc.v:112708$4480 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:111826.5-111826.29" + attribute \src "libresoc.v:112709.5-112709.29" switch \initial - attribute \src "libresoc.v:111826.9-111826.17" + attribute \src "libresoc.v:112709.9-112709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174214,18 +176518,18 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:111836.3-111846.6" - process $proc$libresoc.v:111836$4400 + attribute \src "libresoc.v:112719.3-112729.6" + process $proc$libresoc.v:112719$4481 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:111837.5-111837.29" + attribute \src "libresoc.v:112720.5-112720.29" switch \initial - attribute \src "libresoc.v:111837.9-111837.17" + attribute \src "libresoc.v:112720.9-112720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174237,18 +176541,18 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:111847.3-111857.6" - process $proc$libresoc.v:111847$4401 + attribute \src "libresoc.v:112730.3-112740.6" + process $proc$libresoc.v:112730$4482 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:111848.5-111848.29" + attribute \src "libresoc.v:112731.5-112731.29" switch \initial - attribute \src "libresoc.v:111848.9-111848.17" + attribute \src "libresoc.v:112731.9-112731.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174260,18 +176564,18 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:111858.3-111868.6" - process $proc$libresoc.v:111858$4402 + attribute \src "libresoc.v:112741.3-112751.6" + process $proc$libresoc.v:112741$4483 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:111859.5-111859.29" + attribute \src "libresoc.v:112742.5-112742.29" switch \initial - attribute \src "libresoc.v:111859.9-111859.17" + attribute \src "libresoc.v:112742.9-112742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -174283,24 +176587,24 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:111869.3-111884.6" - process $proc$libresoc.v:111869$4403 + attribute \src "libresoc.v:112752.3-112767.6" + process $proc$libresoc.v:112752$4484 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:111870.5-111870.29" + attribute \src "libresoc.v:112753.5-112753.29" switch \initial - attribute \src "libresoc.v:111870.9-111870.17" + attribute \src "libresoc.v:112753.9-112753.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -174315,24 +176619,24 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:111885.3-111903.6" - process $proc$libresoc.v:111885$4404 + attribute \src "libresoc.v:112768.3-112786.6" + process $proc$libresoc.v:112768$4485 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:111886.5-111886.29" + attribute \src "libresoc.v:112769.5-112769.29" switch \initial - attribute \src "libresoc.v:111886.9-111886.17" + attribute \src "libresoc.v:112769.9-112769.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -174349,89 +176653,89 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:111741$4391_Y - connect \$3 $and$libresoc.v:111742$4392_Y - connect \$5 $eq$libresoc.v:111743$4393_Y - connect \$7 $and$libresoc.v:111744$4394_Y + connect \$1 $eq$libresoc.v:112624$4472_Y + connect \$3 $and$libresoc.v:112625$4473_Y + connect \$5 $eq$libresoc.v:112626$4474_Y + connect \$7 $and$libresoc.v:112627$4475_Y end -attribute \src "libresoc.v:111908.1-112205.10" +attribute \src "libresoc.v:112791.1-113088.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$140 - attribute \src "libresoc.v:112099.3-112125.6" +module \dec_cr_in$143 + attribute \src "libresoc.v:112982.3-113008.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112126.3-112136.6" + attribute \src "libresoc.v:113009.3-113019.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112077.3-112087.6" + attribute \src "libresoc.v:112960.3-112970.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112137.3-112147.6" + attribute \src "libresoc.v:113020.3-113030.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112148.3-112158.6" + attribute \src "libresoc.v:113031.3-113041.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112050.3-112076.6" + attribute \src "libresoc.v:112933.3-112959.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112186.3-112204.6" + attribute \src "libresoc.v:113069.3-113087.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112088.3-112098.6" + attribute \src "libresoc.v:112971.3-112981.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:111909.7-111909.20" + attribute \src "libresoc.v:112792.7-112792.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112159.3-112169.6" + attribute \src "libresoc.v:113042.3-113052.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:112170.3-112185.6" + attribute \src "libresoc.v:113053.3-113068.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112099.3-112125.6" + attribute \src "libresoc.v:112982.3-113008.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112126.3-112136.6" + attribute \src "libresoc.v:113009.3-113019.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112077.3-112087.6" + attribute \src "libresoc.v:112960.3-112970.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112137.3-112147.6" + attribute \src "libresoc.v:113020.3-113030.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112148.3-112158.6" + attribute \src "libresoc.v:113031.3-113041.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112050.3-112076.6" + attribute \src "libresoc.v:112933.3-112959.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112186.3-112204.6" + attribute \src "libresoc.v:113069.3-113087.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112088.3-112098.6" + attribute \src "libresoc.v:112971.3-112981.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112159.3-112169.6" + attribute \src "libresoc.v:113042.3-113052.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:112170.3-112185.6" + attribute \src "libresoc.v:113053.3-113068.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112186.3-112204.6" + attribute \src "libresoc.v:113069.3-113087.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112170.3-112185.6" + attribute \src "libresoc.v:113053.3-113068.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112043.17-112043.112" - wire $and$libresoc.v:112043$4407_Y - attribute \src "libresoc.v:112045.17-112045.112" - wire $and$libresoc.v:112045$4409_Y - attribute \src "libresoc.v:112042.17-112042.120" - wire $eq$libresoc.v:112042$4406_Y - attribute \src "libresoc.v:112044.17-112044.120" - wire $eq$libresoc.v:112044$4408_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:112926.17-112926.112" + wire $and$libresoc.v:112926$4488_Y + attribute \src "libresoc.v:112928.17-112928.112" + wire $and$libresoc.v:112928$4490_Y + attribute \src "libresoc.v:112925.17-112925.120" + wire $eq$libresoc.v:112925$4487_Y + attribute \src "libresoc.v:112927.17-112927.120" + wire $eq$libresoc.v:112927$4489_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \CR_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -174507,31 +176811,31 @@ module \dec_cr_in$140 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:111909.7-111909.15" + attribute \src "libresoc.v:112792.7-112792.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -174545,10 +176849,10 @@ module \dec_cr_in$140 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112043$4407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112926$4488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -174556,10 +176860,10 @@ module \dec_cr_in$140 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:112043$4407_Y + connect \Y $and$libresoc.v:112926$4488_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112045$4409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:112928$4490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -174567,10 +176871,10 @@ module \dec_cr_in$140 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:112045$4409_Y + connect \Y $and$libresoc.v:112928$4490_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112042$4406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112925$4487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -174578,10 +176882,10 @@ module \dec_cr_in$140 parameter \Y_WIDTH 1 connect \A \CR_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112042$4406_Y + connect \Y $eq$libresoc.v:112925$4487_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112044$4408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:112927$4489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -174589,34 +176893,34 @@ module \dec_cr_in$140 parameter \Y_WIDTH 1 connect \A \CR_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112044$4408_Y + connect \Y $eq$libresoc.v:112927$4489_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:112046.15-112049.4" - cell \ppick$141 \ppick + attribute \src "libresoc.v:112929.15-112932.4" + cell \ppick$144 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:111909.7-111909.20" - process $proc$libresoc.v:111909$4420 + attribute \src "libresoc.v:112792.7-112792.20" + process $proc$libresoc.v:112792$4501 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112050.3-112076.6" - process $proc$libresoc.v:112050$4410 + attribute \src "libresoc.v:112933.3-112959.6" + process $proc$libresoc.v:112933$4491 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112051.5-112051.29" + attribute \src "libresoc.v:112934.5-112934.29" switch \initial - attribute \src "libresoc.v:112051.9-112051.17" + attribute \src "libresoc.v:112934.9-112934.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -174644,18 +176948,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:112077.3-112087.6" - process $proc$libresoc.v:112077$4411 + attribute \src "libresoc.v:112960.3-112970.6" + process $proc$libresoc.v:112960$4492 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112078.5-112078.29" + attribute \src "libresoc.v:112961.5-112961.29" switch \initial - attribute \src "libresoc.v:112078.9-112078.17" + attribute \src "libresoc.v:112961.9-112961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174667,18 +176971,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:112088.3-112098.6" - process $proc$libresoc.v:112088$4412 + attribute \src "libresoc.v:112971.3-112981.6" + process $proc$libresoc.v:112971$4493 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112089.5-112089.29" + attribute \src "libresoc.v:112972.5-112972.29" switch \initial - attribute \src "libresoc.v:112089.9-112089.17" + attribute \src "libresoc.v:112972.9-112972.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -174690,18 +176994,18 @@ module \dec_cr_in$140 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:112099.3-112125.6" - process $proc$libresoc.v:112099$4413 + attribute \src "libresoc.v:112982.3-113008.6" + process $proc$libresoc.v:112982$4494 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112100.5-112100.29" + attribute \src "libresoc.v:112983.5-112983.29" switch \initial - attribute \src "libresoc.v:112100.9-112100.17" + attribute \src "libresoc.v:112983.9-112983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -174729,18 +177033,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:112126.3-112136.6" - process $proc$libresoc.v:112126$4414 + attribute \src "libresoc.v:113009.3-113019.6" + process $proc$libresoc.v:113009$4495 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112127.5-112127.29" + attribute \src "libresoc.v:113010.5-113010.29" switch \initial - attribute \src "libresoc.v:112127.9-112127.17" + attribute \src "libresoc.v:113010.9-113010.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174752,18 +177056,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:112137.3-112147.6" - process $proc$libresoc.v:112137$4415 + attribute \src "libresoc.v:113020.3-113030.6" + process $proc$libresoc.v:113020$4496 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112138.5-112138.29" + attribute \src "libresoc.v:113021.5-113021.29" switch \initial - attribute \src "libresoc.v:112138.9-112138.17" + attribute \src "libresoc.v:113021.9-113021.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174775,18 +177079,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:112148.3-112158.6" - process $proc$libresoc.v:112148$4416 + attribute \src "libresoc.v:113031.3-113041.6" + process $proc$libresoc.v:113031$4497 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112149.5-112149.29" + attribute \src "libresoc.v:113032.5-113032.29" switch \initial - attribute \src "libresoc.v:112149.9-112149.17" + attribute \src "libresoc.v:113032.9-113032.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -174798,18 +177102,18 @@ module \dec_cr_in$140 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:112159.3-112169.6" - process $proc$libresoc.v:112159$4417 + attribute \src "libresoc.v:113042.3-113052.6" + process $proc$libresoc.v:113042$4498 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:112160.5-112160.29" + attribute \src "libresoc.v:113043.5-113043.29" switch \initial - attribute \src "libresoc.v:112160.9-112160.17" + attribute \src "libresoc.v:113043.9-113043.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -174821,24 +177125,24 @@ module \dec_cr_in$140 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:112170.3-112185.6" - process $proc$libresoc.v:112170$4418 + attribute \src "libresoc.v:113053.3-113068.6" + process $proc$libresoc.v:113053$4499 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:112171.5-112171.29" + attribute \src "libresoc.v:113054.5-113054.29" switch \initial - attribute \src "libresoc.v:112171.9-112171.17" + attribute \src "libresoc.v:113054.9-113054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -174853,24 +177157,24 @@ module \dec_cr_in$140 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:112186.3-112204.6" - process $proc$libresoc.v:112186$4419 + attribute \src "libresoc.v:113069.3-113087.6" + process $proc$libresoc.v:113069$4500 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:112187.5-112187.29" + attribute \src "libresoc.v:113070.5-113070.29" switch \initial - attribute \src "libresoc.v:112187.9-112187.17" + attribute \src "libresoc.v:113070.9-113070.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -174887,89 +177191,89 @@ module \dec_cr_in$140 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:112042$4406_Y - connect \$3 $and$libresoc.v:112043$4407_Y - connect \$5 $eq$libresoc.v:112044$4408_Y - connect \$7 $and$libresoc.v:112045$4409_Y + connect \$1 $eq$libresoc.v:112925$4487_Y + connect \$3 $and$libresoc.v:112926$4488_Y + connect \$5 $eq$libresoc.v:112927$4489_Y + connect \$7 $and$libresoc.v:112928$4490_Y end -attribute \src "libresoc.v:112209.1-112506.10" +attribute \src "libresoc.v:113092.1-113389.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$147 - attribute \src "libresoc.v:112400.3-112426.6" +module \dec_cr_in$150 + attribute \src "libresoc.v:113283.3-113309.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112427.3-112437.6" + attribute \src "libresoc.v:113310.3-113320.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112378.3-112388.6" + attribute \src "libresoc.v:113261.3-113271.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112438.3-112448.6" + attribute \src "libresoc.v:113321.3-113331.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112449.3-112459.6" + attribute \src "libresoc.v:113332.3-113342.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112351.3-112377.6" + attribute \src "libresoc.v:113234.3-113260.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112487.3-112505.6" + attribute \src "libresoc.v:113370.3-113388.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112389.3-112399.6" + attribute \src "libresoc.v:113272.3-113282.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112210.7-112210.20" + attribute \src "libresoc.v:113093.7-113093.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112460.3-112470.6" + attribute \src "libresoc.v:113343.3-113353.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:112471.3-112486.6" + attribute \src "libresoc.v:113354.3-113369.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112400.3-112426.6" + attribute \src "libresoc.v:113283.3-113309.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112427.3-112437.6" + attribute \src "libresoc.v:113310.3-113320.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112378.3-112388.6" + attribute \src "libresoc.v:113261.3-113271.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112438.3-112448.6" + attribute \src "libresoc.v:113321.3-113331.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112449.3-112459.6" + attribute \src "libresoc.v:113332.3-113342.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112351.3-112377.6" + attribute \src "libresoc.v:113234.3-113260.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112487.3-112505.6" + attribute \src "libresoc.v:113370.3-113388.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112389.3-112399.6" + attribute \src "libresoc.v:113272.3-113282.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112460.3-112470.6" + attribute \src "libresoc.v:113343.3-113353.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:112471.3-112486.6" + attribute \src "libresoc.v:113354.3-113369.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112487.3-112505.6" + attribute \src "libresoc.v:113370.3-113388.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112471.3-112486.6" + attribute \src "libresoc.v:113354.3-113369.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112344.17-112344.112" - wire $and$libresoc.v:112344$4422_Y - attribute \src "libresoc.v:112346.17-112346.112" - wire $and$libresoc.v:112346$4424_Y - attribute \src "libresoc.v:112343.17-112343.124" - wire $eq$libresoc.v:112343$4421_Y - attribute \src "libresoc.v:112345.17-112345.124" - wire $eq$libresoc.v:112345$4423_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:113227.17-113227.112" + wire $and$libresoc.v:113227$4503_Y + attribute \src "libresoc.v:113229.17-113229.112" + wire $and$libresoc.v:113229$4505_Y + attribute \src "libresoc.v:113226.17-113226.124" + wire $eq$libresoc.v:113226$4502_Y + attribute \src "libresoc.v:113228.17-113228.124" + wire $eq$libresoc.v:113228$4504_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \BRANCH_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -175045,31 +177349,31 @@ module \dec_cr_in$147 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:112210.7-112210.15" + attribute \src "libresoc.v:113093.7-113093.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -175083,10 +177387,10 @@ module \dec_cr_in$147 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112344$4422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113227$4503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -175094,10 +177398,10 @@ module \dec_cr_in$147 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:112344$4422_Y + connect \Y $and$libresoc.v:113227$4503_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112346$4424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113229$4505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -175105,10 +177409,10 @@ module \dec_cr_in$147 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:112346$4424_Y + connect \Y $and$libresoc.v:113229$4505_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112343$4421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113226$4502 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -175116,10 +177420,10 @@ module \dec_cr_in$147 parameter \Y_WIDTH 1 connect \A \BRANCH_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112343$4421_Y + connect \Y $eq$libresoc.v:113226$4502_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112345$4423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113228$4504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -175127,34 +177431,34 @@ module \dec_cr_in$147 parameter \Y_WIDTH 1 connect \A \BRANCH_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112345$4423_Y + connect \Y $eq$libresoc.v:113228$4504_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:112347.15-112350.4" - cell \ppick$148 \ppick + attribute \src "libresoc.v:113230.15-113233.4" + cell \ppick$151 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:112210.7-112210.20" - process $proc$libresoc.v:112210$4435 + attribute \src "libresoc.v:113093.7-113093.20" + process $proc$libresoc.v:113093$4516 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112351.3-112377.6" - process $proc$libresoc.v:112351$4425 + attribute \src "libresoc.v:113234.3-113260.6" + process $proc$libresoc.v:113234$4506 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112352.5-112352.29" + attribute \src "libresoc.v:113235.5-113235.29" switch \initial - attribute \src "libresoc.v:112352.9-112352.17" + attribute \src "libresoc.v:113235.9-113235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -175182,18 +177486,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:112378.3-112388.6" - process $proc$libresoc.v:112378$4426 + attribute \src "libresoc.v:113261.3-113271.6" + process $proc$libresoc.v:113261$4507 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112379.5-112379.29" + attribute \src "libresoc.v:113262.5-113262.29" switch \initial - attribute \src "libresoc.v:112379.9-112379.17" + attribute \src "libresoc.v:113262.9-113262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175205,18 +177509,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:112389.3-112399.6" - process $proc$libresoc.v:112389$4427 + attribute \src "libresoc.v:113272.3-113282.6" + process $proc$libresoc.v:113272$4508 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112390.5-112390.29" + attribute \src "libresoc.v:113273.5-113273.29" switch \initial - attribute \src "libresoc.v:112390.9-112390.17" + attribute \src "libresoc.v:113273.9-113273.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -175228,18 +177532,18 @@ module \dec_cr_in$147 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:112400.3-112426.6" - process $proc$libresoc.v:112400$4428 + attribute \src "libresoc.v:113283.3-113309.6" + process $proc$libresoc.v:113283$4509 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112401.5-112401.29" + attribute \src "libresoc.v:113284.5-113284.29" switch \initial - attribute \src "libresoc.v:112401.9-112401.17" + attribute \src "libresoc.v:113284.9-113284.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -175267,18 +177571,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:112427.3-112437.6" - process $proc$libresoc.v:112427$4429 + attribute \src "libresoc.v:113310.3-113320.6" + process $proc$libresoc.v:113310$4510 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112428.5-112428.29" + attribute \src "libresoc.v:113311.5-113311.29" switch \initial - attribute \src "libresoc.v:112428.9-112428.17" + attribute \src "libresoc.v:113311.9-113311.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175290,18 +177594,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:112438.3-112448.6" - process $proc$libresoc.v:112438$4430 + attribute \src "libresoc.v:113321.3-113331.6" + process $proc$libresoc.v:113321$4511 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112439.5-112439.29" + attribute \src "libresoc.v:113322.5-113322.29" switch \initial - attribute \src "libresoc.v:112439.9-112439.17" + attribute \src "libresoc.v:113322.9-113322.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175313,18 +177617,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:112449.3-112459.6" - process $proc$libresoc.v:112449$4431 + attribute \src "libresoc.v:113332.3-113342.6" + process $proc$libresoc.v:113332$4512 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112450.5-112450.29" + attribute \src "libresoc.v:113333.5-113333.29" switch \initial - attribute \src "libresoc.v:112450.9-112450.17" + attribute \src "libresoc.v:113333.9-113333.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175336,18 +177640,18 @@ module \dec_cr_in$147 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:112460.3-112470.6" - process $proc$libresoc.v:112460$4432 + attribute \src "libresoc.v:113343.3-113353.6" + process $proc$libresoc.v:113343$4513 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:112461.5-112461.29" + attribute \src "libresoc.v:113344.5-113344.29" switch \initial - attribute \src "libresoc.v:112461.9-112461.17" + attribute \src "libresoc.v:113344.9-113344.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -175359,24 +177663,24 @@ module \dec_cr_in$147 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:112471.3-112486.6" - process $proc$libresoc.v:112471$4433 + attribute \src "libresoc.v:113354.3-113369.6" + process $proc$libresoc.v:113354$4514 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:112472.5-112472.29" + attribute \src "libresoc.v:113355.5-113355.29" switch \initial - attribute \src "libresoc.v:112472.9-112472.17" + attribute \src "libresoc.v:113355.9-113355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -175391,24 +177695,24 @@ module \dec_cr_in$147 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:112487.3-112505.6" - process $proc$libresoc.v:112487$4434 + attribute \src "libresoc.v:113370.3-113388.6" + process $proc$libresoc.v:113370$4515 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:112488.5-112488.29" + attribute \src "libresoc.v:113371.5-113371.29" switch \initial - attribute \src "libresoc.v:112488.9-112488.17" + attribute \src "libresoc.v:113371.9-113371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -175425,89 +177729,89 @@ module \dec_cr_in$147 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:112343$4421_Y - connect \$3 $and$libresoc.v:112344$4422_Y - connect \$5 $eq$libresoc.v:112345$4423_Y - connect \$7 $and$libresoc.v:112346$4424_Y + connect \$1 $eq$libresoc.v:113226$4502_Y + connect \$3 $and$libresoc.v:113227$4503_Y + connect \$5 $eq$libresoc.v:113228$4504_Y + connect \$7 $and$libresoc.v:113229$4505_Y end -attribute \src "libresoc.v:112510.1-112807.10" +attribute \src "libresoc.v:113393.1-113690.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$155 - attribute \src "libresoc.v:112701.3-112727.6" +module \dec_cr_in$158 + attribute \src "libresoc.v:113584.3-113610.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112728.3-112738.6" + attribute \src "libresoc.v:113611.3-113621.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112679.3-112689.6" + attribute \src "libresoc.v:113562.3-113572.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112739.3-112749.6" + attribute \src "libresoc.v:113622.3-113632.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112750.3-112760.6" + attribute \src "libresoc.v:113633.3-113643.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112652.3-112678.6" + attribute \src "libresoc.v:113535.3-113561.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112788.3-112806.6" + attribute \src "libresoc.v:113671.3-113689.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112690.3-112700.6" + attribute \src "libresoc.v:113573.3-113583.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112511.7-112511.20" + attribute \src "libresoc.v:113394.7-113394.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112761.3-112771.6" + attribute \src "libresoc.v:113644.3-113654.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:112772.3-112787.6" + attribute \src "libresoc.v:113655.3-113670.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112701.3-112727.6" + attribute \src "libresoc.v:113584.3-113610.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112728.3-112738.6" + attribute \src "libresoc.v:113611.3-113621.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112679.3-112689.6" + attribute \src "libresoc.v:113562.3-113572.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112739.3-112749.6" + attribute \src "libresoc.v:113622.3-113632.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112750.3-112760.6" + attribute \src "libresoc.v:113633.3-113643.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112652.3-112678.6" + attribute \src "libresoc.v:113535.3-113561.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112788.3-112806.6" + attribute \src "libresoc.v:113671.3-113689.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112690.3-112700.6" + attribute \src "libresoc.v:113573.3-113583.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112761.3-112771.6" + attribute \src "libresoc.v:113644.3-113654.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:112772.3-112787.6" + attribute \src "libresoc.v:113655.3-113670.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112788.3-112806.6" + attribute \src "libresoc.v:113671.3-113689.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112772.3-112787.6" + attribute \src "libresoc.v:113655.3-113670.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112645.17-112645.112" - wire $and$libresoc.v:112645$4437_Y - attribute \src "libresoc.v:112647.17-112647.112" - wire $and$libresoc.v:112647$4439_Y - attribute \src "libresoc.v:112644.17-112644.125" - wire $eq$libresoc.v:112644$4436_Y - attribute \src "libresoc.v:112646.17-112646.125" - wire $eq$libresoc.v:112646$4438_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:113528.17-113528.112" + wire $and$libresoc.v:113528$4518_Y + attribute \src "libresoc.v:113530.17-113530.112" + wire $and$libresoc.v:113530$4520_Y + attribute \src "libresoc.v:113527.17-113527.125" + wire $eq$libresoc.v:113527$4517_Y + attribute \src "libresoc.v:113529.17-113529.125" + wire $eq$libresoc.v:113529$4519_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \LOGICAL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -175583,31 +177887,31 @@ module \dec_cr_in$155 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:112511.7-112511.15" + attribute \src "libresoc.v:113394.7-113394.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -175621,10 +177925,10 @@ module \dec_cr_in$155 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112645$4437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113528$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -175632,10 +177936,10 @@ module \dec_cr_in$155 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:112645$4437_Y + connect \Y $and$libresoc.v:113528$4518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112647$4439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113530$4520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -175643,10 +177947,10 @@ module \dec_cr_in$155 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:112647$4439_Y + connect \Y $and$libresoc.v:113530$4520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112644$4436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113527$4517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -175654,10 +177958,10 @@ module \dec_cr_in$155 parameter \Y_WIDTH 1 connect \A \LOGICAL_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112644$4436_Y + connect \Y $eq$libresoc.v:113527$4517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112646$4438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113529$4519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -175665,34 +177969,34 @@ module \dec_cr_in$155 parameter \Y_WIDTH 1 connect \A \LOGICAL_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112646$4438_Y + connect \Y $eq$libresoc.v:113529$4519_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:112648.15-112651.4" - cell \ppick$156 \ppick + attribute \src "libresoc.v:113531.15-113534.4" + cell \ppick$159 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:112511.7-112511.20" - process $proc$libresoc.v:112511$4450 + attribute \src "libresoc.v:113394.7-113394.20" + process $proc$libresoc.v:113394$4531 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112652.3-112678.6" - process $proc$libresoc.v:112652$4440 + attribute \src "libresoc.v:113535.3-113561.6" + process $proc$libresoc.v:113535$4521 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112653.5-112653.29" + attribute \src "libresoc.v:113536.5-113536.29" switch \initial - attribute \src "libresoc.v:112653.9-112653.17" + attribute \src "libresoc.v:113536.9-113536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -175720,18 +178024,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:112679.3-112689.6" - process $proc$libresoc.v:112679$4441 + attribute \src "libresoc.v:113562.3-113572.6" + process $proc$libresoc.v:113562$4522 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112680.5-112680.29" + attribute \src "libresoc.v:113563.5-113563.29" switch \initial - attribute \src "libresoc.v:112680.9-112680.17" + attribute \src "libresoc.v:113563.9-113563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175743,18 +178047,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:112690.3-112700.6" - process $proc$libresoc.v:112690$4442 + attribute \src "libresoc.v:113573.3-113583.6" + process $proc$libresoc.v:113573$4523 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112691.5-112691.29" + attribute \src "libresoc.v:113574.5-113574.29" switch \initial - attribute \src "libresoc.v:112691.9-112691.17" + attribute \src "libresoc.v:113574.9-113574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -175766,18 +178070,18 @@ module \dec_cr_in$155 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:112701.3-112727.6" - process $proc$libresoc.v:112701$4443 + attribute \src "libresoc.v:113584.3-113610.6" + process $proc$libresoc.v:113584$4524 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112702.5-112702.29" + attribute \src "libresoc.v:113585.5-113585.29" switch \initial - attribute \src "libresoc.v:112702.9-112702.17" + attribute \src "libresoc.v:113585.9-113585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -175805,18 +178109,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:112728.3-112738.6" - process $proc$libresoc.v:112728$4444 + attribute \src "libresoc.v:113611.3-113621.6" + process $proc$libresoc.v:113611$4525 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112729.5-112729.29" + attribute \src "libresoc.v:113612.5-113612.29" switch \initial - attribute \src "libresoc.v:112729.9-112729.17" + attribute \src "libresoc.v:113612.9-113612.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175828,18 +178132,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:112739.3-112749.6" - process $proc$libresoc.v:112739$4445 + attribute \src "libresoc.v:113622.3-113632.6" + process $proc$libresoc.v:113622$4526 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112740.5-112740.29" + attribute \src "libresoc.v:113623.5-113623.29" switch \initial - attribute \src "libresoc.v:112740.9-112740.17" + attribute \src "libresoc.v:113623.9-113623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175851,18 +178155,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:112750.3-112760.6" - process $proc$libresoc.v:112750$4446 + attribute \src "libresoc.v:113633.3-113643.6" + process $proc$libresoc.v:113633$4527 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112751.5-112751.29" + attribute \src "libresoc.v:113634.5-113634.29" switch \initial - attribute \src "libresoc.v:112751.9-112751.17" + attribute \src "libresoc.v:113634.9-113634.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -175874,18 +178178,18 @@ module \dec_cr_in$155 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:112761.3-112771.6" - process $proc$libresoc.v:112761$4447 + attribute \src "libresoc.v:113644.3-113654.6" + process $proc$libresoc.v:113644$4528 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:112762.5-112762.29" + attribute \src "libresoc.v:113645.5-113645.29" switch \initial - attribute \src "libresoc.v:112762.9-112762.17" + attribute \src "libresoc.v:113645.9-113645.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -175897,24 +178201,24 @@ module \dec_cr_in$155 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:112772.3-112787.6" - process $proc$libresoc.v:112772$4448 + attribute \src "libresoc.v:113655.3-113670.6" + process $proc$libresoc.v:113655$4529 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:112773.5-112773.29" + attribute \src "libresoc.v:113656.5-113656.29" switch \initial - attribute \src "libresoc.v:112773.9-112773.17" + attribute \src "libresoc.v:113656.9-113656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -175929,24 +178233,24 @@ module \dec_cr_in$155 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:112788.3-112806.6" - process $proc$libresoc.v:112788$4449 + attribute \src "libresoc.v:113671.3-113689.6" + process $proc$libresoc.v:113671$4530 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:112789.5-112789.29" + attribute \src "libresoc.v:113672.5-113672.29" switch \initial - attribute \src "libresoc.v:112789.9-112789.17" + attribute \src "libresoc.v:113672.9-113672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -175963,89 +178267,89 @@ module \dec_cr_in$155 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:112644$4436_Y - connect \$3 $and$libresoc.v:112645$4437_Y - connect \$5 $eq$libresoc.v:112646$4438_Y - connect \$7 $and$libresoc.v:112647$4439_Y + connect \$1 $eq$libresoc.v:113527$4517_Y + connect \$3 $and$libresoc.v:113528$4518_Y + connect \$5 $eq$libresoc.v:113529$4519_Y + connect \$7 $and$libresoc.v:113530$4520_Y end -attribute \src "libresoc.v:112811.1-113108.10" +attribute \src "libresoc.v:113694.1-113991.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$164 - attribute \src "libresoc.v:113002.3-113028.6" +module \dec_cr_in$167 + attribute \src "libresoc.v:113885.3-113911.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113029.3-113039.6" + attribute \src "libresoc.v:113912.3-113922.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112980.3-112990.6" + attribute \src "libresoc.v:113863.3-113873.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113040.3-113050.6" + attribute \src "libresoc.v:113923.3-113933.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113051.3-113061.6" + attribute \src "libresoc.v:113934.3-113944.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112953.3-112979.6" + attribute \src "libresoc.v:113836.3-113862.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113089.3-113107.6" + attribute \src "libresoc.v:113972.3-113990.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112991.3-113001.6" + attribute \src "libresoc.v:113874.3-113884.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112812.7-112812.20" + attribute \src "libresoc.v:113695.7-113695.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113062.3-113072.6" + attribute \src "libresoc.v:113945.3-113955.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:113073.3-113088.6" + attribute \src "libresoc.v:113956.3-113971.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113002.3-113028.6" + attribute \src "libresoc.v:113885.3-113911.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113029.3-113039.6" + attribute \src "libresoc.v:113912.3-113922.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112980.3-112990.6" + attribute \src "libresoc.v:113863.3-113873.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113040.3-113050.6" + attribute \src "libresoc.v:113923.3-113933.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113051.3-113061.6" + attribute \src "libresoc.v:113934.3-113944.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112953.3-112979.6" + attribute \src "libresoc.v:113836.3-113862.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113089.3-113107.6" + attribute \src "libresoc.v:113972.3-113990.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112991.3-113001.6" + attribute \src "libresoc.v:113874.3-113884.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113062.3-113072.6" + attribute \src "libresoc.v:113945.3-113955.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:113073.3-113088.6" + attribute \src "libresoc.v:113956.3-113971.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113089.3-113107.6" + attribute \src "libresoc.v:113972.3-113990.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113073.3-113088.6" + attribute \src "libresoc.v:113956.3-113971.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112946.17-112946.112" - wire $and$libresoc.v:112946$4452_Y - attribute \src "libresoc.v:112948.17-112948.112" - wire $and$libresoc.v:112948$4454_Y - attribute \src "libresoc.v:112945.17-112945.121" - wire $eq$libresoc.v:112945$4451_Y - attribute \src "libresoc.v:112947.17-112947.121" - wire $eq$libresoc.v:112947$4453_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:113829.17-113829.112" + wire $and$libresoc.v:113829$4533_Y + attribute \src "libresoc.v:113831.17-113831.112" + wire $and$libresoc.v:113831$4535_Y + attribute \src "libresoc.v:113828.17-113828.121" + wire $eq$libresoc.v:113828$4532_Y + attribute \src "libresoc.v:113830.17-113830.121" + wire $eq$libresoc.v:113830$4534_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \SPR_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -176121,31 +178425,31 @@ module \dec_cr_in$164 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:112812.7-112812.15" + attribute \src "libresoc.v:113695.7-113695.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -176159,10 +178463,10 @@ module \dec_cr_in$164 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112946$4452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113829$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -176170,10 +178474,10 @@ module \dec_cr_in$164 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:112946$4452_Y + connect \Y $and$libresoc.v:113829$4533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:112948$4454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:113831$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -176181,10 +178485,10 @@ module \dec_cr_in$164 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:112948$4454_Y + connect \Y $and$libresoc.v:113831$4535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112945$4451 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113828$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -176192,10 +178496,10 @@ module \dec_cr_in$164 parameter \Y_WIDTH 1 connect \A \SPR_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112945$4451_Y + connect \Y $eq$libresoc.v:113828$4532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:112947$4453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:113830$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -176203,34 +178507,34 @@ module \dec_cr_in$164 parameter \Y_WIDTH 1 connect \A \SPR_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:112947$4453_Y + connect \Y $eq$libresoc.v:113830$4534_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:112949.15-112952.4" - cell \ppick$165 \ppick + attribute \src "libresoc.v:113832.15-113835.4" + cell \ppick$168 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:112812.7-112812.20" - process $proc$libresoc.v:112812$4465 + attribute \src "libresoc.v:113695.7-113695.20" + process $proc$libresoc.v:113695$4546 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112953.3-112979.6" - process $proc$libresoc.v:112953$4455 + attribute \src "libresoc.v:113836.3-113862.6" + process $proc$libresoc.v:113836$4536 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112954.5-112954.29" + attribute \src "libresoc.v:113837.5-113837.29" switch \initial - attribute \src "libresoc.v:112954.9-112954.17" + attribute \src "libresoc.v:113837.9-113837.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -176258,18 +178562,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:112980.3-112990.6" - process $proc$libresoc.v:112980$4456 + attribute \src "libresoc.v:113863.3-113873.6" + process $proc$libresoc.v:113863$4537 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112981.5-112981.29" + attribute \src "libresoc.v:113864.5-113864.29" switch \initial - attribute \src "libresoc.v:112981.9-112981.17" + attribute \src "libresoc.v:113864.9-113864.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176281,18 +178585,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:112991.3-113001.6" - process $proc$libresoc.v:112991$4457 + attribute \src "libresoc.v:113874.3-113884.6" + process $proc$libresoc.v:113874$4538 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112992.5-112992.29" + attribute \src "libresoc.v:113875.5-113875.29" switch \initial - attribute \src "libresoc.v:112992.9-112992.17" + attribute \src "libresoc.v:113875.9-113875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -176304,18 +178608,18 @@ module \dec_cr_in$164 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:113002.3-113028.6" - process $proc$libresoc.v:113002$4458 + attribute \src "libresoc.v:113885.3-113911.6" + process $proc$libresoc.v:113885$4539 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113003.5-113003.29" + attribute \src "libresoc.v:113886.5-113886.29" switch \initial - attribute \src "libresoc.v:113003.9-113003.17" + attribute \src "libresoc.v:113886.9-113886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -176343,18 +178647,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:113029.3-113039.6" - process $proc$libresoc.v:113029$4459 + attribute \src "libresoc.v:113912.3-113922.6" + process $proc$libresoc.v:113912$4540 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113030.5-113030.29" + attribute \src "libresoc.v:113913.5-113913.29" switch \initial - attribute \src "libresoc.v:113030.9-113030.17" + attribute \src "libresoc.v:113913.9-113913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176366,18 +178670,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:113040.3-113050.6" - process $proc$libresoc.v:113040$4460 + attribute \src "libresoc.v:113923.3-113933.6" + process $proc$libresoc.v:113923$4541 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113041.5-113041.29" + attribute \src "libresoc.v:113924.5-113924.29" switch \initial - attribute \src "libresoc.v:113041.9-113041.17" + attribute \src "libresoc.v:113924.9-113924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176389,18 +178693,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:113051.3-113061.6" - process $proc$libresoc.v:113051$4461 + attribute \src "libresoc.v:113934.3-113944.6" + process $proc$libresoc.v:113934$4542 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113052.5-113052.29" + attribute \src "libresoc.v:113935.5-113935.29" switch \initial - attribute \src "libresoc.v:113052.9-113052.17" + attribute \src "libresoc.v:113935.9-113935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176412,18 +178716,18 @@ module \dec_cr_in$164 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:113062.3-113072.6" - process $proc$libresoc.v:113062$4462 + attribute \src "libresoc.v:113945.3-113955.6" + process $proc$libresoc.v:113945$4543 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113063.5-113063.29" + attribute \src "libresoc.v:113946.5-113946.29" switch \initial - attribute \src "libresoc.v:113063.9-113063.17" + attribute \src "libresoc.v:113946.9-113946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -176435,24 +178739,24 @@ module \dec_cr_in$164 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:113073.3-113088.6" - process $proc$libresoc.v:113073$4463 + attribute \src "libresoc.v:113956.3-113971.6" + process $proc$libresoc.v:113956$4544 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113074.5-113074.29" + attribute \src "libresoc.v:113957.5-113957.29" switch \initial - attribute \src "libresoc.v:113074.9-113074.17" + attribute \src "libresoc.v:113957.9-113957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -176467,24 +178771,24 @@ module \dec_cr_in$164 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:113089.3-113107.6" - process $proc$libresoc.v:113089$4464 + attribute \src "libresoc.v:113972.3-113990.6" + process $proc$libresoc.v:113972$4545 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113090.5-113090.29" + attribute \src "libresoc.v:113973.5-113973.29" switch \initial - attribute \src "libresoc.v:113090.9-113090.17" + attribute \src "libresoc.v:113973.9-113973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -176501,89 +178805,89 @@ module \dec_cr_in$164 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:112945$4451_Y - connect \$3 $and$libresoc.v:112946$4452_Y - connect \$5 $eq$libresoc.v:112947$4453_Y - connect \$7 $and$libresoc.v:112948$4454_Y + connect \$1 $eq$libresoc.v:113828$4532_Y + connect \$3 $and$libresoc.v:113829$4533_Y + connect \$5 $eq$libresoc.v:113830$4534_Y + connect \$7 $and$libresoc.v:113831$4535_Y end -attribute \src "libresoc.v:113112.1-113409.10" +attribute \src "libresoc.v:113995.1-114292.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$171 - attribute \src "libresoc.v:113303.3-113329.6" +module \dec_cr_in$174 + attribute \src "libresoc.v:114186.3-114212.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113330.3-113340.6" + attribute \src "libresoc.v:114213.3-114223.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113281.3-113291.6" + attribute \src "libresoc.v:114164.3-114174.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113341.3-113351.6" + attribute \src "libresoc.v:114224.3-114234.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113352.3-113362.6" + attribute \src "libresoc.v:114235.3-114245.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113254.3-113280.6" + attribute \src "libresoc.v:114137.3-114163.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113390.3-113408.6" + attribute \src "libresoc.v:114273.3-114291.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113292.3-113302.6" + attribute \src "libresoc.v:114175.3-114185.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113113.7-113113.20" + attribute \src "libresoc.v:113996.7-113996.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113363.3-113373.6" + attribute \src "libresoc.v:114246.3-114256.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:113374.3-113389.6" + attribute \src "libresoc.v:114257.3-114272.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113303.3-113329.6" + attribute \src "libresoc.v:114186.3-114212.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113330.3-113340.6" + attribute \src "libresoc.v:114213.3-114223.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113281.3-113291.6" + attribute \src "libresoc.v:114164.3-114174.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113341.3-113351.6" + attribute \src "libresoc.v:114224.3-114234.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113352.3-113362.6" + attribute \src "libresoc.v:114235.3-114245.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113254.3-113280.6" + attribute \src "libresoc.v:114137.3-114163.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113390.3-113408.6" + attribute \src "libresoc.v:114273.3-114291.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113292.3-113302.6" + attribute \src "libresoc.v:114175.3-114185.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113363.3-113373.6" + attribute \src "libresoc.v:114246.3-114256.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:113374.3-113389.6" + attribute \src "libresoc.v:114257.3-114272.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113390.3-113408.6" + attribute \src "libresoc.v:114273.3-114291.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113374.3-113389.6" + attribute \src "libresoc.v:114257.3-114272.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113247.17-113247.112" - wire $and$libresoc.v:113247$4467_Y - attribute \src "libresoc.v:113249.17-113249.112" - wire $and$libresoc.v:113249$4469_Y - attribute \src "libresoc.v:113246.17-113246.121" - wire $eq$libresoc.v:113246$4466_Y - attribute \src "libresoc.v:113248.17-113248.121" - wire $eq$libresoc.v:113248$4468_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:114130.17-114130.112" + wire $and$libresoc.v:114130$4548_Y + attribute \src "libresoc.v:114132.17-114132.112" + wire $and$libresoc.v:114132$4550_Y + attribute \src "libresoc.v:114129.17-114129.121" + wire $eq$libresoc.v:114129$4547_Y + attribute \src "libresoc.v:114131.17-114131.121" + wire $eq$libresoc.v:114131$4549_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \DIV_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -176659,31 +178963,31 @@ module \dec_cr_in$171 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:113113.7-113113.15" + attribute \src "libresoc.v:113996.7-113996.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -176697,10 +179001,10 @@ module \dec_cr_in$171 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113247$4467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114130$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -176708,10 +179012,10 @@ module \dec_cr_in$171 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:113247$4467_Y + connect \Y $and$libresoc.v:114130$4548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113249$4469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114132$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -176719,10 +179023,10 @@ module \dec_cr_in$171 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:113249$4469_Y + connect \Y $and$libresoc.v:114132$4550_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113246$4466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114129$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -176730,10 +179034,10 @@ module \dec_cr_in$171 parameter \Y_WIDTH 1 connect \A \DIV_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113246$4466_Y + connect \Y $eq$libresoc.v:114129$4547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113248$4468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114131$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -176741,34 +179045,34 @@ module \dec_cr_in$171 parameter \Y_WIDTH 1 connect \A \DIV_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113248$4468_Y + connect \Y $eq$libresoc.v:114131$4549_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:113250.15-113253.4" - cell \ppick$172 \ppick + attribute \src "libresoc.v:114133.15-114136.4" + cell \ppick$175 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:113113.7-113113.20" - process $proc$libresoc.v:113113$4480 + attribute \src "libresoc.v:113996.7-113996.20" + process $proc$libresoc.v:113996$4561 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113254.3-113280.6" - process $proc$libresoc.v:113254$4470 + attribute \src "libresoc.v:114137.3-114163.6" + process $proc$libresoc.v:114137$4551 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113255.5-113255.29" + attribute \src "libresoc.v:114138.5-114138.29" switch \initial - attribute \src "libresoc.v:113255.9-113255.17" + attribute \src "libresoc.v:114138.9-114138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -176796,18 +179100,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:113281.3-113291.6" - process $proc$libresoc.v:113281$4471 + attribute \src "libresoc.v:114164.3-114174.6" + process $proc$libresoc.v:114164$4552 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113282.5-113282.29" + attribute \src "libresoc.v:114165.5-114165.29" switch \initial - attribute \src "libresoc.v:113282.9-113282.17" + attribute \src "libresoc.v:114165.9-114165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176819,18 +179123,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:113292.3-113302.6" - process $proc$libresoc.v:113292$4472 + attribute \src "libresoc.v:114175.3-114185.6" + process $proc$libresoc.v:114175$4553 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113293.5-113293.29" + attribute \src "libresoc.v:114176.5-114176.29" switch \initial - attribute \src "libresoc.v:113293.9-113293.17" + attribute \src "libresoc.v:114176.9-114176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -176842,18 +179146,18 @@ module \dec_cr_in$171 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:113303.3-113329.6" - process $proc$libresoc.v:113303$4473 + attribute \src "libresoc.v:114186.3-114212.6" + process $proc$libresoc.v:114186$4554 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113304.5-113304.29" + attribute \src "libresoc.v:114187.5-114187.29" switch \initial - attribute \src "libresoc.v:113304.9-113304.17" + attribute \src "libresoc.v:114187.9-114187.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -176881,18 +179185,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:113330.3-113340.6" - process $proc$libresoc.v:113330$4474 + attribute \src "libresoc.v:114213.3-114223.6" + process $proc$libresoc.v:114213$4555 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113331.5-113331.29" + attribute \src "libresoc.v:114214.5-114214.29" switch \initial - attribute \src "libresoc.v:113331.9-113331.17" + attribute \src "libresoc.v:114214.9-114214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176904,18 +179208,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:113341.3-113351.6" - process $proc$libresoc.v:113341$4475 + attribute \src "libresoc.v:114224.3-114234.6" + process $proc$libresoc.v:114224$4556 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113342.5-113342.29" + attribute \src "libresoc.v:114225.5-114225.29" switch \initial - attribute \src "libresoc.v:113342.9-113342.17" + attribute \src "libresoc.v:114225.9-114225.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176927,18 +179231,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:113352.3-113362.6" - process $proc$libresoc.v:113352$4476 + attribute \src "libresoc.v:114235.3-114245.6" + process $proc$libresoc.v:114235$4557 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113353.5-113353.29" + attribute \src "libresoc.v:114236.5-114236.29" switch \initial - attribute \src "libresoc.v:113353.9-113353.17" + attribute \src "libresoc.v:114236.9-114236.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -176950,18 +179254,18 @@ module \dec_cr_in$171 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:113363.3-113373.6" - process $proc$libresoc.v:113363$4477 + attribute \src "libresoc.v:114246.3-114256.6" + process $proc$libresoc.v:114246$4558 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113364.5-113364.29" + attribute \src "libresoc.v:114247.5-114247.29" switch \initial - attribute \src "libresoc.v:113364.9-113364.17" + attribute \src "libresoc.v:114247.9-114247.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -176973,24 +179277,24 @@ module \dec_cr_in$171 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:113374.3-113389.6" - process $proc$libresoc.v:113374$4478 + attribute \src "libresoc.v:114257.3-114272.6" + process $proc$libresoc.v:114257$4559 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113375.5-113375.29" + attribute \src "libresoc.v:114258.5-114258.29" switch \initial - attribute \src "libresoc.v:113375.9-113375.17" + attribute \src "libresoc.v:114258.9-114258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -177005,24 +179309,24 @@ module \dec_cr_in$171 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:113390.3-113408.6" - process $proc$libresoc.v:113390$4479 + attribute \src "libresoc.v:114273.3-114291.6" + process $proc$libresoc.v:114273$4560 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113391.5-113391.29" + attribute \src "libresoc.v:114274.5-114274.29" switch \initial - attribute \src "libresoc.v:113391.9-113391.17" + attribute \src "libresoc.v:114274.9-114274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -177039,89 +179343,89 @@ module \dec_cr_in$171 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:113246$4466_Y - connect \$3 $and$libresoc.v:113247$4467_Y - connect \$5 $eq$libresoc.v:113248$4468_Y - connect \$7 $and$libresoc.v:113249$4469_Y + connect \$1 $eq$libresoc.v:114129$4547_Y + connect \$3 $and$libresoc.v:114130$4548_Y + connect \$5 $eq$libresoc.v:114131$4549_Y + connect \$7 $and$libresoc.v:114132$4550_Y end -attribute \src "libresoc.v:113413.1-113710.10" +attribute \src "libresoc.v:114296.1-114593.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$180 - attribute \src "libresoc.v:113604.3-113630.6" +module \dec_cr_in$183 + attribute \src "libresoc.v:114487.3-114513.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113631.3-113641.6" + attribute \src "libresoc.v:114514.3-114524.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113582.3-113592.6" + attribute \src "libresoc.v:114465.3-114475.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113642.3-113652.6" + attribute \src "libresoc.v:114525.3-114535.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113653.3-113663.6" + attribute \src "libresoc.v:114536.3-114546.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113555.3-113581.6" + attribute \src "libresoc.v:114438.3-114464.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113691.3-113709.6" + attribute \src "libresoc.v:114574.3-114592.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113593.3-113603.6" + attribute \src "libresoc.v:114476.3-114486.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113414.7-113414.20" + attribute \src "libresoc.v:114297.7-114297.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113664.3-113674.6" + attribute \src "libresoc.v:114547.3-114557.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:113675.3-113690.6" + attribute \src "libresoc.v:114558.3-114573.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113604.3-113630.6" + attribute \src "libresoc.v:114487.3-114513.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113631.3-113641.6" + attribute \src "libresoc.v:114514.3-114524.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113582.3-113592.6" + attribute \src "libresoc.v:114465.3-114475.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113642.3-113652.6" + attribute \src "libresoc.v:114525.3-114535.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113653.3-113663.6" + attribute \src "libresoc.v:114536.3-114546.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113555.3-113581.6" + attribute \src "libresoc.v:114438.3-114464.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113691.3-113709.6" + attribute \src "libresoc.v:114574.3-114592.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113593.3-113603.6" + attribute \src "libresoc.v:114476.3-114486.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113664.3-113674.6" + attribute \src "libresoc.v:114547.3-114557.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:113675.3-113690.6" + attribute \src "libresoc.v:114558.3-114573.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113691.3-113709.6" + attribute \src "libresoc.v:114574.3-114592.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113675.3-113690.6" + attribute \src "libresoc.v:114558.3-114573.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113548.17-113548.112" - wire $and$libresoc.v:113548$4482_Y - attribute \src "libresoc.v:113550.17-113550.112" - wire $and$libresoc.v:113550$4484_Y - attribute \src "libresoc.v:113547.17-113547.121" - wire $eq$libresoc.v:113547$4481_Y - attribute \src "libresoc.v:113549.17-113549.121" - wire $eq$libresoc.v:113549$4483_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:114431.17-114431.112" + wire $and$libresoc.v:114431$4563_Y + attribute \src "libresoc.v:114433.17-114433.112" + wire $and$libresoc.v:114433$4565_Y + attribute \src "libresoc.v:114430.17-114430.121" + wire $eq$libresoc.v:114430$4562_Y + attribute \src "libresoc.v:114432.17-114432.121" + wire $eq$libresoc.v:114432$4564_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \MUL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -177197,31 +179501,31 @@ module \dec_cr_in$180 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:113414.7-113414.15" + attribute \src "libresoc.v:114297.7-114297.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -177235,10 +179539,10 @@ module \dec_cr_in$180 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113548$4482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114431$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -177246,10 +179550,10 @@ module \dec_cr_in$180 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:113548$4482_Y + connect \Y $and$libresoc.v:114431$4563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113550$4484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114433$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -177257,10 +179561,10 @@ module \dec_cr_in$180 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:113550$4484_Y + connect \Y $and$libresoc.v:114433$4565_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113547$4481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114430$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -177268,10 +179572,10 @@ module \dec_cr_in$180 parameter \Y_WIDTH 1 connect \A \MUL_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113547$4481_Y + connect \Y $eq$libresoc.v:114430$4562_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113549$4483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114432$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -177279,34 +179583,34 @@ module \dec_cr_in$180 parameter \Y_WIDTH 1 connect \A \MUL_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113549$4483_Y + connect \Y $eq$libresoc.v:114432$4564_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:113551.15-113554.4" - cell \ppick$181 \ppick + attribute \src "libresoc.v:114434.15-114437.4" + cell \ppick$184 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:113414.7-113414.20" - process $proc$libresoc.v:113414$4495 + attribute \src "libresoc.v:114297.7-114297.20" + process $proc$libresoc.v:114297$4576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113555.3-113581.6" - process $proc$libresoc.v:113555$4485 + attribute \src "libresoc.v:114438.3-114464.6" + process $proc$libresoc.v:114438$4566 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113556.5-113556.29" + attribute \src "libresoc.v:114439.5-114439.29" switch \initial - attribute \src "libresoc.v:113556.9-113556.17" + attribute \src "libresoc.v:114439.9-114439.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -177334,18 +179638,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:113582.3-113592.6" - process $proc$libresoc.v:113582$4486 + attribute \src "libresoc.v:114465.3-114475.6" + process $proc$libresoc.v:114465$4567 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113583.5-113583.29" + attribute \src "libresoc.v:114466.5-114466.29" switch \initial - attribute \src "libresoc.v:113583.9-113583.17" + attribute \src "libresoc.v:114466.9-114466.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177357,18 +179661,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:113593.3-113603.6" - process $proc$libresoc.v:113593$4487 + attribute \src "libresoc.v:114476.3-114486.6" + process $proc$libresoc.v:114476$4568 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113594.5-113594.29" + attribute \src "libresoc.v:114477.5-114477.29" switch \initial - attribute \src "libresoc.v:113594.9-113594.17" + attribute \src "libresoc.v:114477.9-114477.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -177380,18 +179684,18 @@ module \dec_cr_in$180 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:113604.3-113630.6" - process $proc$libresoc.v:113604$4488 + attribute \src "libresoc.v:114487.3-114513.6" + process $proc$libresoc.v:114487$4569 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113605.5-113605.29" + attribute \src "libresoc.v:114488.5-114488.29" switch \initial - attribute \src "libresoc.v:113605.9-113605.17" + attribute \src "libresoc.v:114488.9-114488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -177419,18 +179723,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:113631.3-113641.6" - process $proc$libresoc.v:113631$4489 + attribute \src "libresoc.v:114514.3-114524.6" + process $proc$libresoc.v:114514$4570 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113632.5-113632.29" + attribute \src "libresoc.v:114515.5-114515.29" switch \initial - attribute \src "libresoc.v:113632.9-113632.17" + attribute \src "libresoc.v:114515.9-114515.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177442,18 +179746,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:113642.3-113652.6" - process $proc$libresoc.v:113642$4490 + attribute \src "libresoc.v:114525.3-114535.6" + process $proc$libresoc.v:114525$4571 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113643.5-113643.29" + attribute \src "libresoc.v:114526.5-114526.29" switch \initial - attribute \src "libresoc.v:113643.9-113643.17" + attribute \src "libresoc.v:114526.9-114526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177465,18 +179769,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:113653.3-113663.6" - process $proc$libresoc.v:113653$4491 + attribute \src "libresoc.v:114536.3-114546.6" + process $proc$libresoc.v:114536$4572 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113654.5-113654.29" + attribute \src "libresoc.v:114537.5-114537.29" switch \initial - attribute \src "libresoc.v:113654.9-113654.17" + attribute \src "libresoc.v:114537.9-114537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177488,18 +179792,18 @@ module \dec_cr_in$180 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:113664.3-113674.6" - process $proc$libresoc.v:113664$4492 + attribute \src "libresoc.v:114547.3-114557.6" + process $proc$libresoc.v:114547$4573 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113665.5-113665.29" + attribute \src "libresoc.v:114548.5-114548.29" switch \initial - attribute \src "libresoc.v:113665.9-113665.17" + attribute \src "libresoc.v:114548.9-114548.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -177511,24 +179815,24 @@ module \dec_cr_in$180 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:113675.3-113690.6" - process $proc$libresoc.v:113675$4493 + attribute \src "libresoc.v:114558.3-114573.6" + process $proc$libresoc.v:114558$4574 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113676.5-113676.29" + attribute \src "libresoc.v:114559.5-114559.29" switch \initial - attribute \src "libresoc.v:113676.9-113676.17" + attribute \src "libresoc.v:114559.9-114559.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -177543,24 +179847,24 @@ module \dec_cr_in$180 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:113691.3-113709.6" - process $proc$libresoc.v:113691$4494 + attribute \src "libresoc.v:114574.3-114592.6" + process $proc$libresoc.v:114574$4575 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113692.5-113692.29" + attribute \src "libresoc.v:114575.5-114575.29" switch \initial - attribute \src "libresoc.v:113692.9-113692.17" + attribute \src "libresoc.v:114575.9-114575.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -177577,89 +179881,89 @@ module \dec_cr_in$180 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:113547$4481_Y - connect \$3 $and$libresoc.v:113548$4482_Y - connect \$5 $eq$libresoc.v:113549$4483_Y - connect \$7 $and$libresoc.v:113550$4484_Y + connect \$1 $eq$libresoc.v:114430$4562_Y + connect \$3 $and$libresoc.v:114431$4563_Y + connect \$5 $eq$libresoc.v:114432$4564_Y + connect \$7 $and$libresoc.v:114433$4565_Y end -attribute \src "libresoc.v:113714.1-114011.10" +attribute \src "libresoc.v:114597.1-114894.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$188 - attribute \src "libresoc.v:113905.3-113931.6" +module \dec_cr_in$191 + attribute \src "libresoc.v:114788.3-114814.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113932.3-113942.6" + attribute \src "libresoc.v:114815.3-114825.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113883.3-113893.6" + attribute \src "libresoc.v:114766.3-114776.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113943.3-113953.6" + attribute \src "libresoc.v:114826.3-114836.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113954.3-113964.6" + attribute \src "libresoc.v:114837.3-114847.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113856.3-113882.6" + attribute \src "libresoc.v:114739.3-114765.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113992.3-114010.6" + attribute \src "libresoc.v:114875.3-114893.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113894.3-113904.6" + attribute \src "libresoc.v:114777.3-114787.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113715.7-113715.20" + attribute \src "libresoc.v:114598.7-114598.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113965.3-113975.6" + attribute \src "libresoc.v:114848.3-114858.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:113976.3-113991.6" + attribute \src "libresoc.v:114859.3-114874.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113905.3-113931.6" + attribute \src "libresoc.v:114788.3-114814.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113932.3-113942.6" + attribute \src "libresoc.v:114815.3-114825.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113883.3-113893.6" + attribute \src "libresoc.v:114766.3-114776.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113943.3-113953.6" + attribute \src "libresoc.v:114826.3-114836.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113954.3-113964.6" + attribute \src "libresoc.v:114837.3-114847.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113856.3-113882.6" + attribute \src "libresoc.v:114739.3-114765.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113992.3-114010.6" + attribute \src "libresoc.v:114875.3-114893.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113894.3-113904.6" + attribute \src "libresoc.v:114777.3-114787.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113965.3-113975.6" + attribute \src "libresoc.v:114848.3-114858.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:113976.3-113991.6" + attribute \src "libresoc.v:114859.3-114874.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113992.3-114010.6" + attribute \src "libresoc.v:114875.3-114893.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113976.3-113991.6" + attribute \src "libresoc.v:114859.3-114874.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113849.17-113849.112" - wire $and$libresoc.v:113849$4497_Y - attribute \src "libresoc.v:113851.17-113851.112" - wire $and$libresoc.v:113851$4499_Y - attribute \src "libresoc.v:113848.17-113848.127" - wire $eq$libresoc.v:113848$4496_Y - attribute \src "libresoc.v:113850.17-113850.127" - wire $eq$libresoc.v:113850$4498_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:114732.17-114732.112" + wire $and$libresoc.v:114732$4578_Y + attribute \src "libresoc.v:114734.17-114734.112" + wire $and$libresoc.v:114734$4580_Y + attribute \src "libresoc.v:114731.17-114731.127" + wire $eq$libresoc.v:114731$4577_Y + attribute \src "libresoc.v:114733.17-114733.127" + wire $eq$libresoc.v:114733$4579_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \SHIFT_ROT_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -177735,31 +180039,31 @@ module \dec_cr_in$188 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:113715.7-113715.15" + attribute \src "libresoc.v:114598.7-114598.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -177773,10 +180077,10 @@ module \dec_cr_in$188 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113849$4497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114732$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -177784,10 +180088,10 @@ module \dec_cr_in$188 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:113849$4497_Y + connect \Y $and$libresoc.v:114732$4578_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:113851$4499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:114734$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -177795,10 +180099,10 @@ module \dec_cr_in$188 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:113851$4499_Y + connect \Y $and$libresoc.v:114734$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113848$4496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114731$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -177806,10 +180110,10 @@ module \dec_cr_in$188 parameter \Y_WIDTH 1 connect \A \SHIFT_ROT_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113848$4496_Y + connect \Y $eq$libresoc.v:114731$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:113850$4498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:114733$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -177817,34 +180121,34 @@ module \dec_cr_in$188 parameter \Y_WIDTH 1 connect \A \SHIFT_ROT_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:113850$4498_Y + connect \Y $eq$libresoc.v:114733$4579_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:113852.15-113855.4" - cell \ppick$189 \ppick + attribute \src "libresoc.v:114735.15-114738.4" + cell \ppick$192 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:113715.7-113715.20" - process $proc$libresoc.v:113715$4510 + attribute \src "libresoc.v:114598.7-114598.20" + process $proc$libresoc.v:114598$4591 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113856.3-113882.6" - process $proc$libresoc.v:113856$4500 + attribute \src "libresoc.v:114739.3-114765.6" + process $proc$libresoc.v:114739$4581 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113857.5-113857.29" + attribute \src "libresoc.v:114740.5-114740.29" switch \initial - attribute \src "libresoc.v:113857.9-113857.17" + attribute \src "libresoc.v:114740.9-114740.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -177872,18 +180176,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:113883.3-113893.6" - process $proc$libresoc.v:113883$4501 + attribute \src "libresoc.v:114766.3-114776.6" + process $proc$libresoc.v:114766$4582 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113884.5-113884.29" + attribute \src "libresoc.v:114767.5-114767.29" switch \initial - attribute \src "libresoc.v:113884.9-113884.17" + attribute \src "libresoc.v:114767.9-114767.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177895,18 +180199,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:113894.3-113904.6" - process $proc$libresoc.v:113894$4502 + attribute \src "libresoc.v:114777.3-114787.6" + process $proc$libresoc.v:114777$4583 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113895.5-113895.29" + attribute \src "libresoc.v:114778.5-114778.29" switch \initial - attribute \src "libresoc.v:113895.9-113895.17" + attribute \src "libresoc.v:114778.9-114778.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -177918,18 +180222,18 @@ module \dec_cr_in$188 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:113905.3-113931.6" - process $proc$libresoc.v:113905$4503 + attribute \src "libresoc.v:114788.3-114814.6" + process $proc$libresoc.v:114788$4584 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113906.5-113906.29" + attribute \src "libresoc.v:114789.5-114789.29" switch \initial - attribute \src "libresoc.v:113906.9-113906.17" + attribute \src "libresoc.v:114789.9-114789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -177957,18 +180261,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:113932.3-113942.6" - process $proc$libresoc.v:113932$4504 + attribute \src "libresoc.v:114815.3-114825.6" + process $proc$libresoc.v:114815$4585 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113933.5-113933.29" + attribute \src "libresoc.v:114816.5-114816.29" switch \initial - attribute \src "libresoc.v:113933.9-113933.17" + attribute \src "libresoc.v:114816.9-114816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -177980,18 +180284,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:113943.3-113953.6" - process $proc$libresoc.v:113943$4505 + attribute \src "libresoc.v:114826.3-114836.6" + process $proc$libresoc.v:114826$4586 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113944.5-113944.29" + attribute \src "libresoc.v:114827.5-114827.29" switch \initial - attribute \src "libresoc.v:113944.9-113944.17" + attribute \src "libresoc.v:114827.9-114827.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178003,18 +180307,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:113954.3-113964.6" - process $proc$libresoc.v:113954$4506 + attribute \src "libresoc.v:114837.3-114847.6" + process $proc$libresoc.v:114837$4587 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113955.5-113955.29" + attribute \src "libresoc.v:114838.5-114838.29" switch \initial - attribute \src "libresoc.v:113955.9-113955.17" + attribute \src "libresoc.v:114838.9-114838.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178026,18 +180330,18 @@ module \dec_cr_in$188 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:113965.3-113975.6" - process $proc$libresoc.v:113965$4507 + attribute \src "libresoc.v:114848.3-114858.6" + process $proc$libresoc.v:114848$4588 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113966.5-113966.29" + attribute \src "libresoc.v:114849.5-114849.29" switch \initial - attribute \src "libresoc.v:113966.9-113966.17" + attribute \src "libresoc.v:114849.9-114849.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -178049,24 +180353,24 @@ module \dec_cr_in$188 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:113976.3-113991.6" - process $proc$libresoc.v:113976$4508 + attribute \src "libresoc.v:114859.3-114874.6" + process $proc$libresoc.v:114859$4589 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113977.5-113977.29" + attribute \src "libresoc.v:114860.5-114860.29" switch \initial - attribute \src "libresoc.v:113977.9-113977.17" + attribute \src "libresoc.v:114860.9-114860.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -178081,24 +180385,24 @@ module \dec_cr_in$188 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:113992.3-114010.6" - process $proc$libresoc.v:113992$4509 + attribute \src "libresoc.v:114875.3-114893.6" + process $proc$libresoc.v:114875$4590 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113993.5-113993.29" + attribute \src "libresoc.v:114876.5-114876.29" switch \initial - attribute \src "libresoc.v:113993.9-113993.17" + attribute \src "libresoc.v:114876.9-114876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -178115,89 +180419,89 @@ module \dec_cr_in$188 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:113848$4496_Y - connect \$3 $and$libresoc.v:113849$4497_Y - connect \$5 $eq$libresoc.v:113850$4498_Y - connect \$7 $and$libresoc.v:113851$4499_Y + connect \$1 $eq$libresoc.v:114731$4577_Y + connect \$3 $and$libresoc.v:114732$4578_Y + connect \$5 $eq$libresoc.v:114733$4579_Y + connect \$7 $and$libresoc.v:114734$4580_Y end -attribute \src "libresoc.v:114015.1-114312.10" +attribute \src "libresoc.v:114898.1-115195.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$196 - attribute \src "libresoc.v:114206.3-114232.6" +module \dec_cr_in$199 + attribute \src "libresoc.v:115089.3-115115.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114233.3-114243.6" + attribute \src "libresoc.v:115116.3-115126.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114184.3-114194.6" + attribute \src "libresoc.v:115067.3-115077.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114244.3-114254.6" + attribute \src "libresoc.v:115127.3-115137.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114255.3-114265.6" + attribute \src "libresoc.v:115138.3-115148.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114157.3-114183.6" + attribute \src "libresoc.v:115040.3-115066.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114293.3-114311.6" + attribute \src "libresoc.v:115176.3-115194.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114195.3-114205.6" + attribute \src "libresoc.v:115078.3-115088.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114016.7-114016.20" + attribute \src "libresoc.v:114899.7-114899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114266.3-114276.6" + attribute \src "libresoc.v:115149.3-115159.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:114277.3-114292.6" + attribute \src "libresoc.v:115160.3-115175.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114206.3-114232.6" + attribute \src "libresoc.v:115089.3-115115.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114233.3-114243.6" + attribute \src "libresoc.v:115116.3-115126.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114184.3-114194.6" + attribute \src "libresoc.v:115067.3-115077.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114244.3-114254.6" + attribute \src "libresoc.v:115127.3-115137.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114255.3-114265.6" + attribute \src "libresoc.v:115138.3-115148.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114157.3-114183.6" + attribute \src "libresoc.v:115040.3-115066.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114293.3-114311.6" + attribute \src "libresoc.v:115176.3-115194.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114195.3-114205.6" + attribute \src "libresoc.v:115078.3-115088.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114266.3-114276.6" + attribute \src "libresoc.v:115149.3-115159.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:114277.3-114292.6" + attribute \src "libresoc.v:115160.3-115175.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114293.3-114311.6" + attribute \src "libresoc.v:115176.3-115194.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114277.3-114292.6" + attribute \src "libresoc.v:115160.3-115175.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114150.17-114150.112" - wire $and$libresoc.v:114150$4512_Y - attribute \src "libresoc.v:114152.17-114152.112" - wire $and$libresoc.v:114152$4514_Y - attribute \src "libresoc.v:114149.17-114149.122" - wire $eq$libresoc.v:114149$4511_Y - attribute \src "libresoc.v:114151.17-114151.122" - wire $eq$libresoc.v:114151$4513_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:115033.17-115033.112" + wire $and$libresoc.v:115033$4593_Y + attribute \src "libresoc.v:115035.17-115035.112" + wire $and$libresoc.v:115035$4595_Y + attribute \src "libresoc.v:115032.17-115032.122" + wire $eq$libresoc.v:115032$4592_Y + attribute \src "libresoc.v:115034.17-115034.122" + wire $eq$libresoc.v:115034$4594_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 4 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 3 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 5 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 6 \LDST_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -178273,31 +180577,31 @@ module \dec_cr_in$196 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:114016.7-114016.15" + attribute \src "libresoc.v:114899.7-114899.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -178311,10 +180615,10 @@ module \dec_cr_in$196 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:114150$4512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115033$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -178322,10 +180626,10 @@ module \dec_cr_in$196 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:114150$4512_Y + connect \Y $and$libresoc.v:115033$4593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:114152$4514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115035$4595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -178333,10 +180637,10 @@ module \dec_cr_in$196 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:114152$4514_Y + connect \Y $and$libresoc.v:115035$4595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:114149$4511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115032$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -178344,10 +180648,10 @@ module \dec_cr_in$196 parameter \Y_WIDTH 1 connect \A \LDST_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:114149$4511_Y + connect \Y $eq$libresoc.v:115032$4592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:114151$4513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115034$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -178355,34 +180659,34 @@ module \dec_cr_in$196 parameter \Y_WIDTH 1 connect \A \LDST_internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:114151$4513_Y + connect \Y $eq$libresoc.v:115034$4594_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:114153.15-114156.4" - cell \ppick$197 \ppick + attribute \src "libresoc.v:115036.15-115039.4" + cell \ppick$200 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:114016.7-114016.20" - process $proc$libresoc.v:114016$4525 + attribute \src "libresoc.v:114899.7-114899.20" + process $proc$libresoc.v:114899$4606 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114157.3-114183.6" - process $proc$libresoc.v:114157$4515 + attribute \src "libresoc.v:115040.3-115066.6" + process $proc$libresoc.v:115040$4596 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114158.5-114158.29" + attribute \src "libresoc.v:115041.5-115041.29" switch \initial - attribute \src "libresoc.v:114158.9-114158.17" + attribute \src "libresoc.v:115041.9-115041.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -178410,18 +180714,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:114184.3-114194.6" - process $proc$libresoc.v:114184$4516 + attribute \src "libresoc.v:115067.3-115077.6" + process $proc$libresoc.v:115067$4597 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114185.5-114185.29" + attribute \src "libresoc.v:115068.5-115068.29" switch \initial - attribute \src "libresoc.v:114185.9-114185.17" + attribute \src "libresoc.v:115068.9-115068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178433,18 +180737,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:114195.3-114205.6" - process $proc$libresoc.v:114195$4517 + attribute \src "libresoc.v:115078.3-115088.6" + process $proc$libresoc.v:115078$4598 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114196.5-114196.29" + attribute \src "libresoc.v:115079.5-115079.29" switch \initial - attribute \src "libresoc.v:114196.9-114196.17" + attribute \src "libresoc.v:115079.9-115079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -178456,18 +180760,18 @@ module \dec_cr_in$196 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:114206.3-114232.6" - process $proc$libresoc.v:114206$4518 + attribute \src "libresoc.v:115089.3-115115.6" + process $proc$libresoc.v:115089$4599 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114207.5-114207.29" + attribute \src "libresoc.v:115090.5-115090.29" switch \initial - attribute \src "libresoc.v:114207.9-114207.17" + attribute \src "libresoc.v:115090.9-115090.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -178495,18 +180799,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:114233.3-114243.6" - process $proc$libresoc.v:114233$4519 + attribute \src "libresoc.v:115116.3-115126.6" + process $proc$libresoc.v:115116$4600 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114234.5-114234.29" + attribute \src "libresoc.v:115117.5-115117.29" switch \initial - attribute \src "libresoc.v:114234.9-114234.17" + attribute \src "libresoc.v:115117.9-115117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178518,18 +180822,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:114244.3-114254.6" - process $proc$libresoc.v:114244$4520 + attribute \src "libresoc.v:115127.3-115137.6" + process $proc$libresoc.v:115127$4601 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114245.5-114245.29" + attribute \src "libresoc.v:115128.5-115128.29" switch \initial - attribute \src "libresoc.v:114245.9-114245.17" + attribute \src "libresoc.v:115128.9-115128.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178541,18 +180845,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:114255.3-114265.6" - process $proc$libresoc.v:114255$4521 + attribute \src "libresoc.v:115138.3-115148.6" + process $proc$libresoc.v:115138$4602 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114256.5-114256.29" + attribute \src "libresoc.v:115139.5-115139.29" switch \initial - attribute \src "libresoc.v:114256.9-114256.17" + attribute \src "libresoc.v:115139.9-115139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178564,18 +180868,18 @@ module \dec_cr_in$196 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:114266.3-114276.6" - process $proc$libresoc.v:114266$4522 + attribute \src "libresoc.v:115149.3-115159.6" + process $proc$libresoc.v:115149$4603 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114267.5-114267.29" + attribute \src "libresoc.v:115150.5-115150.29" switch \initial - attribute \src "libresoc.v:114267.9-114267.17" + attribute \src "libresoc.v:115150.9-115150.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -178587,24 +180891,24 @@ module \dec_cr_in$196 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:114277.3-114292.6" - process $proc$libresoc.v:114277$4523 + attribute \src "libresoc.v:115160.3-115175.6" + process $proc$libresoc.v:115160$4604 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114278.5-114278.29" + attribute \src "libresoc.v:115161.5-115161.29" switch \initial - attribute \src "libresoc.v:114278.9-114278.17" + attribute \src "libresoc.v:115161.9-115161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -178619,24 +180923,24 @@ module \dec_cr_in$196 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:114293.3-114311.6" - process $proc$libresoc.v:114293$4524 + attribute \src "libresoc.v:115176.3-115194.6" + process $proc$libresoc.v:115176$4605 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114294.5-114294.29" + attribute \src "libresoc.v:115177.5-115177.29" switch \initial - attribute \src "libresoc.v:114294.9-114294.17" + attribute \src "libresoc.v:115177.9-115177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -178653,111 +180957,111 @@ module \dec_cr_in$196 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:114149$4511_Y - connect \$3 $and$libresoc.v:114150$4512_Y - connect \$5 $eq$libresoc.v:114151$4513_Y - connect \$7 $and$libresoc.v:114152$4514_Y + connect \$1 $eq$libresoc.v:115032$4592_Y + connect \$3 $and$libresoc.v:115033$4593_Y + connect \$5 $eq$libresoc.v:115034$4594_Y + connect \$7 $and$libresoc.v:115035$4595_Y end -attribute \src "libresoc.v:114316.1-114621.10" +attribute \src "libresoc.v:115199.1-115504.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" -module \dec_cr_in$205 - attribute \src "libresoc.v:114515.3-114541.6" +module \dec_cr_in$208 + attribute \src "libresoc.v:115398.3-115424.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114542.3-114552.6" + attribute \src "libresoc.v:115425.3-115435.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114493.3-114503.6" + attribute \src "libresoc.v:115376.3-115386.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114553.3-114563.6" + attribute \src "libresoc.v:115436.3-115446.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114564.3-114574.6" + attribute \src "libresoc.v:115447.3-115457.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114466.3-114492.6" + attribute \src "libresoc.v:115349.3-115375.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114602.3-114620.6" + attribute \src "libresoc.v:115485.3-115503.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114504.3-114514.6" + attribute \src "libresoc.v:115387.3-115397.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114317.7-114317.20" + attribute \src "libresoc.v:115200.7-115200.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114575.3-114585.6" + attribute \src "libresoc.v:115458.3-115468.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:114586.3-114601.6" + attribute \src "libresoc.v:115469.3-115484.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114515.3-114541.6" + attribute \src "libresoc.v:115398.3-115424.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114542.3-114552.6" + attribute \src "libresoc.v:115425.3-115435.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114493.3-114503.6" + attribute \src "libresoc.v:115376.3-115386.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114553.3-114563.6" + attribute \src "libresoc.v:115436.3-115446.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114564.3-114574.6" + attribute \src "libresoc.v:115447.3-115457.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114466.3-114492.6" + attribute \src "libresoc.v:115349.3-115375.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114602.3-114620.6" + attribute \src "libresoc.v:115485.3-115503.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114504.3-114514.6" + attribute \src "libresoc.v:115387.3-115397.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114575.3-114585.6" + attribute \src "libresoc.v:115458.3-115468.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:114586.3-114601.6" + attribute \src "libresoc.v:115469.3-115484.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114602.3-114620.6" + attribute \src "libresoc.v:115485.3-115503.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114586.3-114601.6" + attribute \src "libresoc.v:115469.3-115484.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114459.17-114459.112" - wire $and$libresoc.v:114459$4527_Y - attribute \src "libresoc.v:114461.17-114461.112" - wire $and$libresoc.v:114461$4529_Y - attribute \src "libresoc.v:114458.17-114458.117" - wire $eq$libresoc.v:114458$4526_Y - attribute \src "libresoc.v:114460.17-114460.117" - wire $eq$libresoc.v:114460$4528_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "libresoc.v:115342.17-115342.112" + wire $and$libresoc.v:115342$4608_Y + attribute \src "libresoc.v:115344.17-115344.112" + wire $and$libresoc.v:115344$4610_Y + attribute \src "libresoc.v:115341.17-115341.117" + wire $eq$libresoc.v:115341$4607_Y + attribute \src "libresoc.v:115343.17-115343.117" + wire $eq$libresoc.v:115343$4609_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:114317.7-114317.15" + attribute \src "libresoc.v:115200.7-115200.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" wire width 32 input 18 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -178833,9 +181137,9 @@ module \dec_cr_in$205 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 2 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" wire width 8 \ppick_i @@ -178849,10 +181153,10 @@ module \dec_cr_in$205 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:114459$4527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115342$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -178860,10 +181164,10 @@ module \dec_cr_in$205 parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:114459$4527_Y + connect \Y $and$libresoc.v:115342$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $and $and$libresoc.v:114461$4529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $and $and$libresoc.v:115344$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -178871,10 +181175,10 @@ module \dec_cr_in$205 parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:114461$4529_Y + connect \Y $and$libresoc.v:115344$4610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:114458$4526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115341$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -178882,10 +181186,10 @@ module \dec_cr_in$205 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:114458$4526_Y + connect \Y $eq$libresoc.v:115341$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - cell $eq $eq$libresoc.v:114460$4528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:115343$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -178893,34 +181197,34 @@ module \dec_cr_in$205 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:114460$4528_Y + connect \Y $eq$libresoc.v:115343$4609_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:114462.15-114465.4" - cell \ppick$206 \ppick + attribute \src "libresoc.v:115345.15-115348.4" + cell \ppick$209 \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:114317.7-114317.20" - process $proc$libresoc.v:114317$4540 + attribute \src "libresoc.v:115200.7-115200.20" + process $proc$libresoc.v:115200$4621 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114466.3-114492.6" - process $proc$libresoc.v:114466$4530 + attribute \src "libresoc.v:115349.3-115375.6" + process $proc$libresoc.v:115349$4611 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114467.5-114467.29" + attribute \src "libresoc.v:115350.5-115350.29" switch \initial - attribute \src "libresoc.v:114467.9-114467.17" + attribute \src "libresoc.v:115350.9-115350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -178948,18 +181252,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:114493.3-114503.6" - process $proc$libresoc.v:114493$4531 + attribute \src "libresoc.v:115376.3-115386.6" + process $proc$libresoc.v:115376$4612 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114494.5-114494.29" + attribute \src "libresoc.v:115377.5-115377.29" switch \initial - attribute \src "libresoc.v:114494.9-114494.17" + attribute \src "libresoc.v:115377.9-115377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -178971,18 +181275,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:114504.3-114514.6" - process $proc$libresoc.v:114504$4532 + attribute \src "libresoc.v:115387.3-115397.6" + process $proc$libresoc.v:115387$4613 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114505.5-114505.29" + attribute \src "libresoc.v:115388.5-115388.29" switch \initial - attribute \src "libresoc.v:114505.9-114505.17" + attribute \src "libresoc.v:115388.9-115388.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -178994,18 +181298,18 @@ module \dec_cr_in$205 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:114515.3-114541.6" - process $proc$libresoc.v:114515$4533 + attribute \src "libresoc.v:115398.3-115424.6" + process $proc$libresoc.v:115398$4614 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114516.5-114516.29" + attribute \src "libresoc.v:115399.5-115399.29" switch \initial - attribute \src "libresoc.v:114516.9-114516.17" + attribute \src "libresoc.v:115399.9-115399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -179033,18 +181337,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:114542.3-114552.6" - process $proc$libresoc.v:114542$4534 + attribute \src "libresoc.v:115425.3-115435.6" + process $proc$libresoc.v:115425$4615 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114543.5-114543.29" + attribute \src "libresoc.v:115426.5-115426.29" switch \initial - attribute \src "libresoc.v:114543.9-114543.17" + attribute \src "libresoc.v:115426.9-115426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179056,18 +181360,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:114553.3-114563.6" - process $proc$libresoc.v:114553$4535 + attribute \src "libresoc.v:115436.3-115446.6" + process $proc$libresoc.v:115436$4616 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114554.5-114554.29" + attribute \src "libresoc.v:115437.5-115437.29" switch \initial - attribute \src "libresoc.v:114554.9-114554.17" + attribute \src "libresoc.v:115437.9-115437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179079,18 +181383,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:114564.3-114574.6" - process $proc$libresoc.v:114564$4536 + attribute \src "libresoc.v:115447.3-115457.6" + process $proc$libresoc.v:115447$4617 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114565.5-114565.29" + attribute \src "libresoc.v:115448.5-115448.29" switch \initial - attribute \src "libresoc.v:114565.9-114565.17" + attribute \src "libresoc.v:115448.9-115448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179102,18 +181406,18 @@ module \dec_cr_in$205 sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:114575.3-114585.6" - process $proc$libresoc.v:114575$4537 + attribute \src "libresoc.v:115458.3-115468.6" + process $proc$libresoc.v:115458$4618 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114576.5-114576.29" + attribute \src "libresoc.v:115459.5-115459.29" switch \initial - attribute \src "libresoc.v:114576.9-114576.17" + attribute \src "libresoc.v:115459.9-115459.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -179125,24 +181429,24 @@ module \dec_cr_in$205 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:114586.3-114601.6" - process $proc$libresoc.v:114586$4538 + attribute \src "libresoc.v:115469.3-115484.6" + process $proc$libresoc.v:115469$4619 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114587.5-114587.29" + attribute \src "libresoc.v:115470.5-115470.29" switch \initial - attribute \src "libresoc.v:114587.9-114587.17" + attribute \src "libresoc.v:115470.9-115470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -179157,24 +181461,24 @@ module \dec_cr_in$205 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:114602.3-114620.6" - process $proc$libresoc.v:114602$4539 + attribute \src "libresoc.v:115485.3-115503.6" + process $proc$libresoc.v:115485$4620 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114603.5-114603.29" + attribute \src "libresoc.v:115486.5-115486.29" switch \initial - attribute \src "libresoc.v:114603.9-114603.17" + attribute \src "libresoc.v:115486.9-115486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -179191,61 +181495,61 @@ module \dec_cr_in$205 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:114458$4526_Y - connect \$3 $and$libresoc.v:114459$4527_Y - connect \$5 $eq$libresoc.v:114460$4528_Y - connect \$7 $and$libresoc.v:114461$4529_Y + connect \$1 $eq$libresoc.v:115341$4607_Y + connect \$3 $and$libresoc.v:115342$4608_Y + connect \$5 $eq$libresoc.v:115343$4609_Y + connect \$7 $and$libresoc.v:115344$4610_Y end -attribute \src "libresoc.v:114625.1-114865.10" +attribute \src "libresoc.v:115508.1-115748.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:114779.3-114797.6" + attribute \src "libresoc.v:115662.3-115680.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114749.3-114767.6" + attribute \src "libresoc.v:115632.3-115650.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114830.3-114864.6" + attribute \src "libresoc.v:115713.3-115747.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114768.3-114778.6" + attribute \src "libresoc.v:115651.3-115661.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114626.7-114626.20" + attribute \src "libresoc.v:115509.7-115509.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114798.3-114808.6" + attribute \src "libresoc.v:115681.3-115691.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:114809.3-114829.6" + attribute \src "libresoc.v:115692.3-115712.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114779.3-114797.6" + attribute \src "libresoc.v:115662.3-115680.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114749.3-114767.6" + attribute \src "libresoc.v:115632.3-115650.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114830.3-114864.6" + attribute \src "libresoc.v:115713.3-115747.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114768.3-114778.6" + attribute \src "libresoc.v:115651.3-115661.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114798.3-114808.6" + attribute \src "libresoc.v:115681.3-115691.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:114809.3-114829.6" + attribute \src "libresoc.v:115692.3-115712.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114830.3-114864.6" + attribute \src "libresoc.v:115713.3-115747.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114809.3-114829.6" + attribute \src "libresoc.v:115692.3-115712.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114830.3-114864.6" + attribute \src "libresoc.v:115713.3-115747.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:114809.3-114829.6" + attribute \src "libresoc.v:115692.3-115712.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:114830.3-114864.6" + attribute \src "libresoc.v:115713.3-115747.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:114742.17-114742.121" - wire $eq$libresoc.v:114742$4541_Y - attribute \src "libresoc.v:114743.17-114743.121" - wire $eq$libresoc.v:114743$4542_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:115625.17-115625.121" + wire $eq$libresoc.v:115625$4622_Y + attribute \src "libresoc.v:115626.17-115626.121" + wire $eq$libresoc.v:115626$4623_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 5 \ALU_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -179321,25 +181625,25 @@ module \dec_cr_out attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:114626.7-114626.15" + attribute \src "libresoc.v:115509.7-115509.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -179347,7 +181651,7 @@ module \dec_cr_out wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -179355,10 +181659,10 @@ module \dec_cr_out attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:114742$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115625$4622 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -179366,10 +181670,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \ALU_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:114742$4541_Y + connect \Y $eq$libresoc.v:115625$4622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:114743$4542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115626$4623 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -179377,35 +181681,35 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \ALU_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:114743$4542_Y + connect \Y $eq$libresoc.v:115626$4623_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:114744.15-114748.4" - cell \ppick$136 \ppick + attribute \src "libresoc.v:115627.15-115631.4" + cell \ppick$139 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:114626.7-114626.20" - process $proc$libresoc.v:114626$4549 + attribute \src "libresoc.v:115509.7-115509.20" + process $proc$libresoc.v:115509$4630 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114749.3-114767.6" - process $proc$libresoc.v:114749$4543 + attribute \src "libresoc.v:115632.3-115650.6" + process $proc$libresoc.v:115632$4624 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114750.5-114750.29" + attribute \src "libresoc.v:115633.5-115633.29" switch \initial - attribute \src "libresoc.v:114750.9-114750.17" + attribute \src "libresoc.v:115633.9-115633.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -179425,18 +181729,18 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:114768.3-114778.6" - process $proc$libresoc.v:114768$4544 + attribute \src "libresoc.v:115651.3-115661.6" + process $proc$libresoc.v:115651$4625 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114769.5-114769.29" + attribute \src "libresoc.v:115652.5-115652.29" switch \initial - attribute \src "libresoc.v:114769.9-114769.17" + attribute \src "libresoc.v:115652.9-115652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179448,18 +181752,18 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:114779.3-114797.6" - process $proc$libresoc.v:114779$4545 + attribute \src "libresoc.v:115662.3-115680.6" + process $proc$libresoc.v:115662$4626 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114780.5-114780.29" + attribute \src "libresoc.v:115663.5-115663.29" switch \initial - attribute \src "libresoc.v:114780.9-114780.17" + attribute \src "libresoc.v:115663.9-115663.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -179479,18 +181783,18 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:114798.3-114808.6" - process $proc$libresoc.v:114798$4546 + attribute \src "libresoc.v:115681.3-115691.6" + process $proc$libresoc.v:115681$4627 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114799.5-114799.29" + attribute \src "libresoc.v:115682.5-115682.29" switch \initial - attribute \src "libresoc.v:114799.9-114799.17" + attribute \src "libresoc.v:115682.9-115682.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179502,30 +181806,30 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:114809.3-114829.6" - process $proc$libresoc.v:114809$4547 + attribute \src "libresoc.v:115692.3-115712.6" + process $proc$libresoc.v:115692$4628 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114810.5-114810.29" + attribute \src "libresoc.v:115693.5-115693.29" switch \initial - attribute \src "libresoc.v:114810.9-114810.17" + attribute \src "libresoc.v:115693.9-115693.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -179543,36 +181847,36 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:114830.3-114864.6" - process $proc$libresoc.v:114830$4548 + attribute \src "libresoc.v:115713.3-115747.6" + process $proc$libresoc.v:115713$4629 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114831.5-114831.29" + attribute \src "libresoc.v:115714.5-115714.29" switch \initial - attribute \src "libresoc.v:114831.9-114831.17" + attribute \src "libresoc.v:115714.9-115714.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -179599,59 +181903,59 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:114742$4541_Y - connect \$3 $eq$libresoc.v:114743$4542_Y + connect \$1 $eq$libresoc.v:115625$4622_Y + connect \$3 $eq$libresoc.v:115626$4623_Y end -attribute \src "libresoc.v:114869.1-115108.10" +attribute \src "libresoc.v:115752.1-115991.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$142 - attribute \src "libresoc.v:115022.3-115040.6" +module \dec_cr_out$145 + attribute \src "libresoc.v:115905.3-115923.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114992.3-115010.6" + attribute \src "libresoc.v:115875.3-115893.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115073.3-115107.6" + attribute \src "libresoc.v:115956.3-115990.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115011.3-115021.6" + attribute \src "libresoc.v:115894.3-115904.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114870.7-114870.20" + attribute \src "libresoc.v:115753.7-115753.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115041.3-115051.6" + attribute \src "libresoc.v:115924.3-115934.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:115052.3-115072.6" + attribute \src "libresoc.v:115935.3-115955.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115022.3-115040.6" + attribute \src "libresoc.v:115905.3-115923.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114992.3-115010.6" + attribute \src "libresoc.v:115875.3-115893.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115073.3-115107.6" + attribute \src "libresoc.v:115956.3-115990.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115011.3-115021.6" + attribute \src "libresoc.v:115894.3-115904.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115041.3-115051.6" + attribute \src "libresoc.v:115924.3-115934.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:115052.3-115072.6" + attribute \src "libresoc.v:115935.3-115955.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:115073.3-115107.6" + attribute \src "libresoc.v:115956.3-115990.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115052.3-115072.6" + attribute \src "libresoc.v:115935.3-115955.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:115073.3-115107.6" + attribute \src "libresoc.v:115956.3-115990.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115052.3-115072.6" + attribute \src "libresoc.v:115935.3-115955.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:115073.3-115107.6" + attribute \src "libresoc.v:115956.3-115990.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:114985.17-114985.120" - wire $eq$libresoc.v:114985$4550_Y - attribute \src "libresoc.v:114986.17-114986.120" - wire $eq$libresoc.v:114986$4551_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:115868.17-115868.120" + wire $eq$libresoc.v:115868$4631_Y + attribute \src "libresoc.v:115869.17-115869.120" + wire $eq$libresoc.v:115869$4632_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 4 \CR_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -179727,25 +182031,25 @@ module \dec_cr_out$142 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:114870.7-114870.15" + attribute \src "libresoc.v:115753.7-115753.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -179753,7 +182057,7 @@ module \dec_cr_out$142 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -179761,10 +182065,10 @@ module \dec_cr_out$142 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:114985$4550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115868$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -179772,10 +182076,10 @@ module \dec_cr_out$142 parameter \Y_WIDTH 1 connect \A \CR_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:114985$4550_Y + connect \Y $eq$libresoc.v:115868$4631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:114986$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:115869$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -179783,35 +182087,35 @@ module \dec_cr_out$142 parameter \Y_WIDTH 1 connect \A \CR_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:114986$4551_Y + connect \Y $eq$libresoc.v:115869$4632_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:114987.15-114991.4" - cell \ppick$143 \ppick + attribute \src "libresoc.v:115870.15-115874.4" + cell \ppick$146 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:114870.7-114870.20" - process $proc$libresoc.v:114870$4558 + attribute \src "libresoc.v:115753.7-115753.20" + process $proc$libresoc.v:115753$4639 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114992.3-115010.6" - process $proc$libresoc.v:114992$4552 + attribute \src "libresoc.v:115875.3-115893.6" + process $proc$libresoc.v:115875$4633 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114993.5-114993.29" + attribute \src "libresoc.v:115876.5-115876.29" switch \initial - attribute \src "libresoc.v:114993.9-114993.17" + attribute \src "libresoc.v:115876.9-115876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -179831,18 +182135,18 @@ module \dec_cr_out$142 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:115011.3-115021.6" - process $proc$libresoc.v:115011$4553 + attribute \src "libresoc.v:115894.3-115904.6" + process $proc$libresoc.v:115894$4634 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115012.5-115012.29" + attribute \src "libresoc.v:115895.5-115895.29" switch \initial - attribute \src "libresoc.v:115012.9-115012.17" + attribute \src "libresoc.v:115895.9-115895.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179854,18 +182158,18 @@ module \dec_cr_out$142 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:115022.3-115040.6" - process $proc$libresoc.v:115022$4554 + attribute \src "libresoc.v:115905.3-115923.6" + process $proc$libresoc.v:115905$4635 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115023.5-115023.29" + attribute \src "libresoc.v:115906.5-115906.29" switch \initial - attribute \src "libresoc.v:115023.9-115023.17" + attribute \src "libresoc.v:115906.9-115906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -179885,18 +182189,18 @@ module \dec_cr_out$142 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:115041.3-115051.6" - process $proc$libresoc.v:115041$4555 + attribute \src "libresoc.v:115924.3-115934.6" + process $proc$libresoc.v:115924$4636 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115042.5-115042.29" + attribute \src "libresoc.v:115925.5-115925.29" switch \initial - attribute \src "libresoc.v:115042.9-115042.17" + attribute \src "libresoc.v:115925.9-115925.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -179908,30 +182212,30 @@ module \dec_cr_out$142 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:115052.3-115072.6" - process $proc$libresoc.v:115052$4556 + attribute \src "libresoc.v:115935.3-115955.6" + process $proc$libresoc.v:115935$4637 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115053.5-115053.29" + attribute \src "libresoc.v:115936.5-115936.29" switch \initial - attribute \src "libresoc.v:115053.9-115053.17" + attribute \src "libresoc.v:115936.9-115936.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -179949,36 +182253,36 @@ module \dec_cr_out$142 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:115073.3-115107.6" - process $proc$libresoc.v:115073$4557 + attribute \src "libresoc.v:115956.3-115990.6" + process $proc$libresoc.v:115956$4638 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115074.5-115074.29" + attribute \src "libresoc.v:115957.5-115957.29" switch \initial - attribute \src "libresoc.v:115074.9-115074.17" + attribute \src "libresoc.v:115957.9-115957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -180005,59 +182309,59 @@ module \dec_cr_out$142 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:114985$4550_Y - connect \$3 $eq$libresoc.v:114986$4551_Y + connect \$1 $eq$libresoc.v:115868$4631_Y + connect \$3 $eq$libresoc.v:115869$4632_Y end -attribute \src "libresoc.v:115112.1-115351.10" +attribute \src "libresoc.v:115995.1-116234.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$149 - attribute \src "libresoc.v:115265.3-115283.6" +module \dec_cr_out$152 + attribute \src "libresoc.v:116148.3-116166.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115235.3-115253.6" + attribute \src "libresoc.v:116118.3-116136.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115316.3-115350.6" + attribute \src "libresoc.v:116199.3-116233.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115254.3-115264.6" + attribute \src "libresoc.v:116137.3-116147.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115113.7-115113.20" + attribute \src "libresoc.v:115996.7-115996.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115284.3-115294.6" + attribute \src "libresoc.v:116167.3-116177.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:115295.3-115315.6" + attribute \src "libresoc.v:116178.3-116198.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115265.3-115283.6" + attribute \src "libresoc.v:116148.3-116166.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115235.3-115253.6" + attribute \src "libresoc.v:116118.3-116136.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115316.3-115350.6" + attribute \src "libresoc.v:116199.3-116233.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115254.3-115264.6" + attribute \src "libresoc.v:116137.3-116147.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115284.3-115294.6" + attribute \src "libresoc.v:116167.3-116177.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:115295.3-115315.6" + attribute \src "libresoc.v:116178.3-116198.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:115316.3-115350.6" + attribute \src "libresoc.v:116199.3-116233.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115295.3-115315.6" + attribute \src "libresoc.v:116178.3-116198.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:115316.3-115350.6" + attribute \src "libresoc.v:116199.3-116233.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115295.3-115315.6" + attribute \src "libresoc.v:116178.3-116198.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:115316.3-115350.6" + attribute \src "libresoc.v:116199.3-116233.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115228.17-115228.124" - wire $eq$libresoc.v:115228$4559_Y - attribute \src "libresoc.v:115229.17-115229.124" - wire $eq$libresoc.v:115229$4560_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:116111.17-116111.124" + wire $eq$libresoc.v:116111$4640_Y + attribute \src "libresoc.v:116112.17-116112.124" + wire $eq$libresoc.v:116112$4641_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 4 \BRANCH_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -180133,25 +182437,25 @@ module \dec_cr_out$149 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:115113.7-115113.15" + attribute \src "libresoc.v:115996.7-115996.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -180159,7 +182463,7 @@ module \dec_cr_out$149 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -180167,10 +182471,10 @@ module \dec_cr_out$149 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115228$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116111$4640 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -180178,10 +182482,10 @@ module \dec_cr_out$149 parameter \Y_WIDTH 1 connect \A \BRANCH_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115228$4559_Y + connect \Y $eq$libresoc.v:116111$4640_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115229$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116112$4641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -180189,35 +182493,35 @@ module \dec_cr_out$149 parameter \Y_WIDTH 1 connect \A \BRANCH_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115229$4560_Y + connect \Y $eq$libresoc.v:116112$4641_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:115230.15-115234.4" - cell \ppick$150 \ppick + attribute \src "libresoc.v:116113.15-116117.4" + cell \ppick$153 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:115113.7-115113.20" - process $proc$libresoc.v:115113$4567 + attribute \src "libresoc.v:115996.7-115996.20" + process $proc$libresoc.v:115996$4648 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115235.3-115253.6" - process $proc$libresoc.v:115235$4561 + attribute \src "libresoc.v:116118.3-116136.6" + process $proc$libresoc.v:116118$4642 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115236.5-115236.29" + attribute \src "libresoc.v:116119.5-116119.29" switch \initial - attribute \src "libresoc.v:115236.9-115236.17" + attribute \src "libresoc.v:116119.9-116119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -180237,18 +182541,18 @@ module \dec_cr_out$149 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:115254.3-115264.6" - process $proc$libresoc.v:115254$4562 + attribute \src "libresoc.v:116137.3-116147.6" + process $proc$libresoc.v:116137$4643 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115255.5-115255.29" + attribute \src "libresoc.v:116138.5-116138.29" switch \initial - attribute \src "libresoc.v:115255.9-115255.17" + attribute \src "libresoc.v:116138.9-116138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -180260,18 +182564,18 @@ module \dec_cr_out$149 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:115265.3-115283.6" - process $proc$libresoc.v:115265$4563 + attribute \src "libresoc.v:116148.3-116166.6" + process $proc$libresoc.v:116148$4644 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115266.5-115266.29" + attribute \src "libresoc.v:116149.5-116149.29" switch \initial - attribute \src "libresoc.v:115266.9-115266.17" + attribute \src "libresoc.v:116149.9-116149.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -180291,18 +182595,18 @@ module \dec_cr_out$149 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:115284.3-115294.6" - process $proc$libresoc.v:115284$4564 + attribute \src "libresoc.v:116167.3-116177.6" + process $proc$libresoc.v:116167$4645 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115285.5-115285.29" + attribute \src "libresoc.v:116168.5-116168.29" switch \initial - attribute \src "libresoc.v:115285.9-115285.17" + attribute \src "libresoc.v:116168.9-116168.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -180314,30 +182618,30 @@ module \dec_cr_out$149 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:115295.3-115315.6" - process $proc$libresoc.v:115295$4565 + attribute \src "libresoc.v:116178.3-116198.6" + process $proc$libresoc.v:116178$4646 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115296.5-115296.29" + attribute \src "libresoc.v:116179.5-116179.29" switch \initial - attribute \src "libresoc.v:115296.9-115296.17" + attribute \src "libresoc.v:116179.9-116179.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -180355,36 +182659,36 @@ module \dec_cr_out$149 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:115316.3-115350.6" - process $proc$libresoc.v:115316$4566 + attribute \src "libresoc.v:116199.3-116233.6" + process $proc$libresoc.v:116199$4647 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115317.5-115317.29" + attribute \src "libresoc.v:116200.5-116200.29" switch \initial - attribute \src "libresoc.v:115317.9-115317.17" + attribute \src "libresoc.v:116200.9-116200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -180411,59 +182715,59 @@ module \dec_cr_out$149 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:115228$4559_Y - connect \$3 $eq$libresoc.v:115229$4560_Y + connect \$1 $eq$libresoc.v:116111$4640_Y + connect \$3 $eq$libresoc.v:116112$4641_Y end -attribute \src "libresoc.v:115355.1-115595.10" +attribute \src "libresoc.v:116238.1-116478.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$157 - attribute \src "libresoc.v:115509.3-115527.6" +module \dec_cr_out$160 + attribute \src "libresoc.v:116392.3-116410.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115479.3-115497.6" + attribute \src "libresoc.v:116362.3-116380.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115560.3-115594.6" + attribute \src "libresoc.v:116443.3-116477.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115498.3-115508.6" + attribute \src "libresoc.v:116381.3-116391.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115356.7-115356.20" + attribute \src "libresoc.v:116239.7-116239.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115528.3-115538.6" + attribute \src "libresoc.v:116411.3-116421.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:115539.3-115559.6" + attribute \src "libresoc.v:116422.3-116442.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115509.3-115527.6" + attribute \src "libresoc.v:116392.3-116410.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115479.3-115497.6" + attribute \src "libresoc.v:116362.3-116380.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115560.3-115594.6" + attribute \src "libresoc.v:116443.3-116477.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115498.3-115508.6" + attribute \src "libresoc.v:116381.3-116391.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115528.3-115538.6" + attribute \src "libresoc.v:116411.3-116421.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:115539.3-115559.6" + attribute \src "libresoc.v:116422.3-116442.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:115560.3-115594.6" + attribute \src "libresoc.v:116443.3-116477.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115539.3-115559.6" + attribute \src "libresoc.v:116422.3-116442.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:115560.3-115594.6" + attribute \src "libresoc.v:116443.3-116477.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115539.3-115559.6" + attribute \src "libresoc.v:116422.3-116442.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:115560.3-115594.6" + attribute \src "libresoc.v:116443.3-116477.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115472.17-115472.125" - wire $eq$libresoc.v:115472$4568_Y - attribute \src "libresoc.v:115473.17-115473.125" - wire $eq$libresoc.v:115473$4569_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:116355.17-116355.125" + wire $eq$libresoc.v:116355$4649_Y + attribute \src "libresoc.v:116356.17-116356.125" + wire $eq$libresoc.v:116356$4650_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 5 \LOGICAL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -180539,25 +182843,25 @@ module \dec_cr_out$157 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:115356.7-115356.15" + attribute \src "libresoc.v:116239.7-116239.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -180565,7 +182869,7 @@ module \dec_cr_out$157 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -180573,10 +182877,10 @@ module \dec_cr_out$157 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115472$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116355$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -180584,10 +182888,10 @@ module \dec_cr_out$157 parameter \Y_WIDTH 1 connect \A \LOGICAL_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115472$4568_Y + connect \Y $eq$libresoc.v:116355$4649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115473$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116356$4650 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -180595,35 +182899,35 @@ module \dec_cr_out$157 parameter \Y_WIDTH 1 connect \A \LOGICAL_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115473$4569_Y + connect \Y $eq$libresoc.v:116356$4650_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:115474.15-115478.4" - cell \ppick$158 \ppick + attribute \src "libresoc.v:116357.15-116361.4" + cell \ppick$161 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:115356.7-115356.20" - process $proc$libresoc.v:115356$4576 + attribute \src "libresoc.v:116239.7-116239.20" + process $proc$libresoc.v:116239$4657 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115479.3-115497.6" - process $proc$libresoc.v:115479$4570 + attribute \src "libresoc.v:116362.3-116380.6" + process $proc$libresoc.v:116362$4651 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115480.5-115480.29" + attribute \src "libresoc.v:116363.5-116363.29" switch \initial - attribute \src "libresoc.v:115480.9-115480.17" + attribute \src "libresoc.v:116363.9-116363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -180643,18 +182947,18 @@ module \dec_cr_out$157 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:115498.3-115508.6" - process $proc$libresoc.v:115498$4571 + attribute \src "libresoc.v:116381.3-116391.6" + process $proc$libresoc.v:116381$4652 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115499.5-115499.29" + attribute \src "libresoc.v:116382.5-116382.29" switch \initial - attribute \src "libresoc.v:115499.9-115499.17" + attribute \src "libresoc.v:116382.9-116382.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -180666,18 +182970,18 @@ module \dec_cr_out$157 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:115509.3-115527.6" - process $proc$libresoc.v:115509$4572 + attribute \src "libresoc.v:116392.3-116410.6" + process $proc$libresoc.v:116392$4653 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115510.5-115510.29" + attribute \src "libresoc.v:116393.5-116393.29" switch \initial - attribute \src "libresoc.v:115510.9-115510.17" + attribute \src "libresoc.v:116393.9-116393.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -180697,18 +183001,18 @@ module \dec_cr_out$157 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:115528.3-115538.6" - process $proc$libresoc.v:115528$4573 + attribute \src "libresoc.v:116411.3-116421.6" + process $proc$libresoc.v:116411$4654 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115529.5-115529.29" + attribute \src "libresoc.v:116412.5-116412.29" switch \initial - attribute \src "libresoc.v:115529.9-115529.17" + attribute \src "libresoc.v:116412.9-116412.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -180720,30 +183024,30 @@ module \dec_cr_out$157 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:115539.3-115559.6" - process $proc$libresoc.v:115539$4574 + attribute \src "libresoc.v:116422.3-116442.6" + process $proc$libresoc.v:116422$4655 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115540.5-115540.29" + attribute \src "libresoc.v:116423.5-116423.29" switch \initial - attribute \src "libresoc.v:115540.9-115540.17" + attribute \src "libresoc.v:116423.9-116423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -180761,36 +183065,36 @@ module \dec_cr_out$157 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:115560.3-115594.6" - process $proc$libresoc.v:115560$4575 + attribute \src "libresoc.v:116443.3-116477.6" + process $proc$libresoc.v:116443$4656 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115561.5-115561.29" + attribute \src "libresoc.v:116444.5-116444.29" switch \initial - attribute \src "libresoc.v:115561.9-115561.17" + attribute \src "libresoc.v:116444.9-116444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -180817,59 +183121,59 @@ module \dec_cr_out$157 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:115472$4568_Y - connect \$3 $eq$libresoc.v:115473$4569_Y + connect \$1 $eq$libresoc.v:116355$4649_Y + connect \$3 $eq$libresoc.v:116356$4650_Y end -attribute \src "libresoc.v:115599.1-115838.10" +attribute \src "libresoc.v:116482.1-116721.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$166 - attribute \src "libresoc.v:115752.3-115770.6" +module \dec_cr_out$169 + attribute \src "libresoc.v:116635.3-116653.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115722.3-115740.6" + attribute \src "libresoc.v:116605.3-116623.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115803.3-115837.6" + attribute \src "libresoc.v:116686.3-116720.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115741.3-115751.6" + attribute \src "libresoc.v:116624.3-116634.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115600.7-115600.20" + attribute \src "libresoc.v:116483.7-116483.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115771.3-115781.6" + attribute \src "libresoc.v:116654.3-116664.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:115782.3-115802.6" + attribute \src "libresoc.v:116665.3-116685.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115752.3-115770.6" + attribute \src "libresoc.v:116635.3-116653.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115722.3-115740.6" + attribute \src "libresoc.v:116605.3-116623.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115803.3-115837.6" + attribute \src "libresoc.v:116686.3-116720.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115741.3-115751.6" + attribute \src "libresoc.v:116624.3-116634.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115771.3-115781.6" + attribute \src "libresoc.v:116654.3-116664.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:115782.3-115802.6" + attribute \src "libresoc.v:116665.3-116685.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:115803.3-115837.6" + attribute \src "libresoc.v:116686.3-116720.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115782.3-115802.6" + attribute \src "libresoc.v:116665.3-116685.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:115803.3-115837.6" + attribute \src "libresoc.v:116686.3-116720.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115782.3-115802.6" + attribute \src "libresoc.v:116665.3-116685.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:115803.3-115837.6" + attribute \src "libresoc.v:116686.3-116720.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115715.17-115715.121" - wire $eq$libresoc.v:115715$4577_Y - attribute \src "libresoc.v:115716.17-115716.121" - wire $eq$libresoc.v:115716$4578_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:116598.17-116598.121" + wire $eq$libresoc.v:116598$4658_Y + attribute \src "libresoc.v:116599.17-116599.121" + wire $eq$libresoc.v:116599$4659_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 4 \SPR_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -180945,25 +183249,25 @@ module \dec_cr_out$166 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:115600.7-115600.15" + attribute \src "libresoc.v:116483.7-116483.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -180971,7 +183275,7 @@ module \dec_cr_out$166 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -180979,10 +183283,10 @@ module \dec_cr_out$166 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115715$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116598$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -180990,10 +183294,10 @@ module \dec_cr_out$166 parameter \Y_WIDTH 1 connect \A \SPR_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115715$4577_Y + connect \Y $eq$libresoc.v:116598$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115716$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116599$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -181001,35 +183305,35 @@ module \dec_cr_out$166 parameter \Y_WIDTH 1 connect \A \SPR_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115716$4578_Y + connect \Y $eq$libresoc.v:116599$4659_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:115717.15-115721.4" - cell \ppick$167 \ppick + attribute \src "libresoc.v:116600.15-116604.4" + cell \ppick$170 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:115600.7-115600.20" - process $proc$libresoc.v:115600$4585 + attribute \src "libresoc.v:116483.7-116483.20" + process $proc$libresoc.v:116483$4666 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115722.3-115740.6" - process $proc$libresoc.v:115722$4579 + attribute \src "libresoc.v:116605.3-116623.6" + process $proc$libresoc.v:116605$4660 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115723.5-115723.29" + attribute \src "libresoc.v:116606.5-116606.29" switch \initial - attribute \src "libresoc.v:115723.9-115723.17" + attribute \src "libresoc.v:116606.9-116606.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181049,18 +183353,18 @@ module \dec_cr_out$166 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:115741.3-115751.6" - process $proc$libresoc.v:115741$4580 + attribute \src "libresoc.v:116624.3-116634.6" + process $proc$libresoc.v:116624$4661 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115742.5-115742.29" + attribute \src "libresoc.v:116625.5-116625.29" switch \initial - attribute \src "libresoc.v:115742.9-115742.17" + attribute \src "libresoc.v:116625.9-116625.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181072,18 +183376,18 @@ module \dec_cr_out$166 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:115752.3-115770.6" - process $proc$libresoc.v:115752$4581 + attribute \src "libresoc.v:116635.3-116653.6" + process $proc$libresoc.v:116635$4662 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115753.5-115753.29" + attribute \src "libresoc.v:116636.5-116636.29" switch \initial - attribute \src "libresoc.v:115753.9-115753.17" + attribute \src "libresoc.v:116636.9-116636.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181103,18 +183407,18 @@ module \dec_cr_out$166 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:115771.3-115781.6" - process $proc$libresoc.v:115771$4582 + attribute \src "libresoc.v:116654.3-116664.6" + process $proc$libresoc.v:116654$4663 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115772.5-115772.29" + attribute \src "libresoc.v:116655.5-116655.29" switch \initial - attribute \src "libresoc.v:115772.9-115772.17" + attribute \src "libresoc.v:116655.9-116655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181126,30 +183430,30 @@ module \dec_cr_out$166 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:115782.3-115802.6" - process $proc$libresoc.v:115782$4583 + attribute \src "libresoc.v:116665.3-116685.6" + process $proc$libresoc.v:116665$4664 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:115783.5-115783.29" + attribute \src "libresoc.v:116666.5-116666.29" switch \initial - attribute \src "libresoc.v:115783.9-115783.17" + attribute \src "libresoc.v:116666.9-116666.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -181167,36 +183471,36 @@ module \dec_cr_out$166 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:115803.3-115837.6" - process $proc$libresoc.v:115803$4584 + attribute \src "libresoc.v:116686.3-116720.6" + process $proc$libresoc.v:116686$4665 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115804.5-115804.29" + attribute \src "libresoc.v:116687.5-116687.29" switch \initial - attribute \src "libresoc.v:115804.9-115804.17" + attribute \src "libresoc.v:116687.9-116687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -181223,59 +183527,59 @@ module \dec_cr_out$166 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:115715$4577_Y - connect \$3 $eq$libresoc.v:115716$4578_Y + connect \$1 $eq$libresoc.v:116598$4658_Y + connect \$3 $eq$libresoc.v:116599$4659_Y end -attribute \src "libresoc.v:115842.1-116082.10" +attribute \src "libresoc.v:116725.1-116965.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$173 - attribute \src "libresoc.v:115996.3-116014.6" +module \dec_cr_out$176 + attribute \src "libresoc.v:116879.3-116897.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115966.3-115984.6" + attribute \src "libresoc.v:116849.3-116867.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116047.3-116081.6" + attribute \src "libresoc.v:116930.3-116964.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115985.3-115995.6" + attribute \src "libresoc.v:116868.3-116878.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115843.7-115843.20" + attribute \src "libresoc.v:116726.7-116726.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116015.3-116025.6" + attribute \src "libresoc.v:116898.3-116908.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:116026.3-116046.6" + attribute \src "libresoc.v:116909.3-116929.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115996.3-116014.6" + attribute \src "libresoc.v:116879.3-116897.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115966.3-115984.6" + attribute \src "libresoc.v:116849.3-116867.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116047.3-116081.6" + attribute \src "libresoc.v:116930.3-116964.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115985.3-115995.6" + attribute \src "libresoc.v:116868.3-116878.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116015.3-116025.6" + attribute \src "libresoc.v:116898.3-116908.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:116026.3-116046.6" + attribute \src "libresoc.v:116909.3-116929.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116047.3-116081.6" + attribute \src "libresoc.v:116930.3-116964.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116026.3-116046.6" + attribute \src "libresoc.v:116909.3-116929.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116047.3-116081.6" + attribute \src "libresoc.v:116930.3-116964.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116026.3-116046.6" + attribute \src "libresoc.v:116909.3-116929.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116047.3-116081.6" + attribute \src "libresoc.v:116930.3-116964.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115959.17-115959.121" - wire $eq$libresoc.v:115959$4586_Y - attribute \src "libresoc.v:115960.17-115960.121" - wire $eq$libresoc.v:115960$4587_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:116842.17-116842.121" + wire $eq$libresoc.v:116842$4667_Y + attribute \src "libresoc.v:116843.17-116843.121" + wire $eq$libresoc.v:116843$4668_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 5 \DIV_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -181351,25 +183655,25 @@ module \dec_cr_out$173 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:115843.7-115843.15" + attribute \src "libresoc.v:116726.7-116726.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -181377,7 +183681,7 @@ module \dec_cr_out$173 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -181385,10 +183689,10 @@ module \dec_cr_out$173 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115959$4586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116842$4667 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -181396,10 +183700,10 @@ module \dec_cr_out$173 parameter \Y_WIDTH 1 connect \A \DIV_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115959$4586_Y + connect \Y $eq$libresoc.v:116842$4667_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:115960$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:116843$4668 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -181407,35 +183711,35 @@ module \dec_cr_out$173 parameter \Y_WIDTH 1 connect \A \DIV_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:115960$4587_Y + connect \Y $eq$libresoc.v:116843$4668_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:115961.15-115965.4" - cell \ppick$174 \ppick + attribute \src "libresoc.v:116844.15-116848.4" + cell \ppick$177 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:115843.7-115843.20" - process $proc$libresoc.v:115843$4594 + attribute \src "libresoc.v:116726.7-116726.20" + process $proc$libresoc.v:116726$4675 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115966.3-115984.6" - process $proc$libresoc.v:115966$4588 + attribute \src "libresoc.v:116849.3-116867.6" + process $proc$libresoc.v:116849$4669 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115967.5-115967.29" + attribute \src "libresoc.v:116850.5-116850.29" switch \initial - attribute \src "libresoc.v:115967.9-115967.17" + attribute \src "libresoc.v:116850.9-116850.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181455,18 +183759,18 @@ module \dec_cr_out$173 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:115985.3-115995.6" - process $proc$libresoc.v:115985$4589 + attribute \src "libresoc.v:116868.3-116878.6" + process $proc$libresoc.v:116868$4670 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115986.5-115986.29" + attribute \src "libresoc.v:116869.5-116869.29" switch \initial - attribute \src "libresoc.v:115986.9-115986.17" + attribute \src "libresoc.v:116869.9-116869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181478,18 +183782,18 @@ module \dec_cr_out$173 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:115996.3-116014.6" - process $proc$libresoc.v:115996$4590 + attribute \src "libresoc.v:116879.3-116897.6" + process $proc$libresoc.v:116879$4671 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115997.5-115997.29" + attribute \src "libresoc.v:116880.5-116880.29" switch \initial - attribute \src "libresoc.v:115997.9-115997.17" + attribute \src "libresoc.v:116880.9-116880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181509,18 +183813,18 @@ module \dec_cr_out$173 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:116015.3-116025.6" - process $proc$libresoc.v:116015$4591 + attribute \src "libresoc.v:116898.3-116908.6" + process $proc$libresoc.v:116898$4672 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116016.5-116016.29" + attribute \src "libresoc.v:116899.5-116899.29" switch \initial - attribute \src "libresoc.v:116016.9-116016.17" + attribute \src "libresoc.v:116899.9-116899.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181532,30 +183836,30 @@ module \dec_cr_out$173 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:116026.3-116046.6" - process $proc$libresoc.v:116026$4592 + attribute \src "libresoc.v:116909.3-116929.6" + process $proc$libresoc.v:116909$4673 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116027.5-116027.29" + attribute \src "libresoc.v:116910.5-116910.29" switch \initial - attribute \src "libresoc.v:116027.9-116027.17" + attribute \src "libresoc.v:116910.9-116910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -181573,36 +183877,36 @@ module \dec_cr_out$173 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:116047.3-116081.6" - process $proc$libresoc.v:116047$4593 + attribute \src "libresoc.v:116930.3-116964.6" + process $proc$libresoc.v:116930$4674 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116048.5-116048.29" + attribute \src "libresoc.v:116931.5-116931.29" switch \initial - attribute \src "libresoc.v:116048.9-116048.17" + attribute \src "libresoc.v:116931.9-116931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -181629,59 +183933,59 @@ module \dec_cr_out$173 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:115959$4586_Y - connect \$3 $eq$libresoc.v:115960$4587_Y + connect \$1 $eq$libresoc.v:116842$4667_Y + connect \$3 $eq$libresoc.v:116843$4668_Y end -attribute \src "libresoc.v:116086.1-116326.10" +attribute \src "libresoc.v:116969.1-117209.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$182 - attribute \src "libresoc.v:116240.3-116258.6" +module \dec_cr_out$185 + attribute \src "libresoc.v:117123.3-117141.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116210.3-116228.6" + attribute \src "libresoc.v:117093.3-117111.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116291.3-116325.6" + attribute \src "libresoc.v:117174.3-117208.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116229.3-116239.6" + attribute \src "libresoc.v:117112.3-117122.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116087.7-116087.20" + attribute \src "libresoc.v:116970.7-116970.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116259.3-116269.6" + attribute \src "libresoc.v:117142.3-117152.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:116270.3-116290.6" + attribute \src "libresoc.v:117153.3-117173.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116240.3-116258.6" + attribute \src "libresoc.v:117123.3-117141.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116210.3-116228.6" + attribute \src "libresoc.v:117093.3-117111.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116291.3-116325.6" + attribute \src "libresoc.v:117174.3-117208.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116229.3-116239.6" + attribute \src "libresoc.v:117112.3-117122.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116259.3-116269.6" + attribute \src "libresoc.v:117142.3-117152.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:116270.3-116290.6" + attribute \src "libresoc.v:117153.3-117173.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116291.3-116325.6" + attribute \src "libresoc.v:117174.3-117208.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116270.3-116290.6" + attribute \src "libresoc.v:117153.3-117173.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116291.3-116325.6" + attribute \src "libresoc.v:117174.3-117208.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116270.3-116290.6" + attribute \src "libresoc.v:117153.3-117173.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116291.3-116325.6" + attribute \src "libresoc.v:117174.3-117208.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116203.17-116203.121" - wire $eq$libresoc.v:116203$4595_Y - attribute \src "libresoc.v:116204.17-116204.121" - wire $eq$libresoc.v:116204$4596_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:117086.17-117086.121" + wire $eq$libresoc.v:117086$4676_Y + attribute \src "libresoc.v:117087.17-117087.121" + wire $eq$libresoc.v:117087$4677_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 5 \MUL_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -181757,25 +184061,25 @@ module \dec_cr_out$182 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:116087.7-116087.15" + attribute \src "libresoc.v:116970.7-116970.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -181783,7 +184087,7 @@ module \dec_cr_out$182 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -181791,10 +184095,10 @@ module \dec_cr_out$182 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116203$4595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117086$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -181802,10 +184106,10 @@ module \dec_cr_out$182 parameter \Y_WIDTH 1 connect \A \MUL_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116203$4595_Y + connect \Y $eq$libresoc.v:117086$4676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116204$4596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117087$4677 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -181813,35 +184117,35 @@ module \dec_cr_out$182 parameter \Y_WIDTH 1 connect \A \MUL_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116204$4596_Y + connect \Y $eq$libresoc.v:117087$4677_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:116205.15-116209.4" - cell \ppick$183 \ppick + attribute \src "libresoc.v:117088.15-117092.4" + cell \ppick$186 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:116087.7-116087.20" - process $proc$libresoc.v:116087$4603 + attribute \src "libresoc.v:116970.7-116970.20" + process $proc$libresoc.v:116970$4684 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116210.3-116228.6" - process $proc$libresoc.v:116210$4597 + attribute \src "libresoc.v:117093.3-117111.6" + process $proc$libresoc.v:117093$4678 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116211.5-116211.29" + attribute \src "libresoc.v:117094.5-117094.29" switch \initial - attribute \src "libresoc.v:116211.9-116211.17" + attribute \src "libresoc.v:117094.9-117094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181861,18 +184165,18 @@ module \dec_cr_out$182 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:116229.3-116239.6" - process $proc$libresoc.v:116229$4598 + attribute \src "libresoc.v:117112.3-117122.6" + process $proc$libresoc.v:117112$4679 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116230.5-116230.29" + attribute \src "libresoc.v:117113.5-117113.29" switch \initial - attribute \src "libresoc.v:116230.9-116230.17" + attribute \src "libresoc.v:117113.9-117113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181884,18 +184188,18 @@ module \dec_cr_out$182 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:116240.3-116258.6" - process $proc$libresoc.v:116240$4599 + attribute \src "libresoc.v:117123.3-117141.6" + process $proc$libresoc.v:117123$4680 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116241.5-116241.29" + attribute \src "libresoc.v:117124.5-117124.29" switch \initial - attribute \src "libresoc.v:116241.9-116241.17" + attribute \src "libresoc.v:117124.9-117124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -181915,18 +184219,18 @@ module \dec_cr_out$182 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:116259.3-116269.6" - process $proc$libresoc.v:116259$4600 + attribute \src "libresoc.v:117142.3-117152.6" + process $proc$libresoc.v:117142$4681 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116260.5-116260.29" + attribute \src "libresoc.v:117143.5-117143.29" switch \initial - attribute \src "libresoc.v:116260.9-116260.17" + attribute \src "libresoc.v:117143.9-117143.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -181938,30 +184242,30 @@ module \dec_cr_out$182 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:116270.3-116290.6" - process $proc$libresoc.v:116270$4601 + attribute \src "libresoc.v:117153.3-117173.6" + process $proc$libresoc.v:117153$4682 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116271.5-116271.29" + attribute \src "libresoc.v:117154.5-117154.29" switch \initial - attribute \src "libresoc.v:116271.9-116271.17" + attribute \src "libresoc.v:117154.9-117154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -181979,36 +184283,36 @@ module \dec_cr_out$182 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:116291.3-116325.6" - process $proc$libresoc.v:116291$4602 + attribute \src "libresoc.v:117174.3-117208.6" + process $proc$libresoc.v:117174$4683 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116292.5-116292.29" + attribute \src "libresoc.v:117175.5-117175.29" switch \initial - attribute \src "libresoc.v:116292.9-116292.17" + attribute \src "libresoc.v:117175.9-117175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -182035,59 +184339,59 @@ module \dec_cr_out$182 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:116203$4595_Y - connect \$3 $eq$libresoc.v:116204$4596_Y + connect \$1 $eq$libresoc.v:117086$4676_Y + connect \$3 $eq$libresoc.v:117087$4677_Y end -attribute \src "libresoc.v:116330.1-116570.10" +attribute \src "libresoc.v:117213.1-117453.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$190 - attribute \src "libresoc.v:116484.3-116502.6" +module \dec_cr_out$193 + attribute \src "libresoc.v:117367.3-117385.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116454.3-116472.6" + attribute \src "libresoc.v:117337.3-117355.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116535.3-116569.6" + attribute \src "libresoc.v:117418.3-117452.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116473.3-116483.6" + attribute \src "libresoc.v:117356.3-117366.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116331.7-116331.20" + attribute \src "libresoc.v:117214.7-117214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116503.3-116513.6" + attribute \src "libresoc.v:117386.3-117396.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:116514.3-116534.6" + attribute \src "libresoc.v:117397.3-117417.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116484.3-116502.6" + attribute \src "libresoc.v:117367.3-117385.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116454.3-116472.6" + attribute \src "libresoc.v:117337.3-117355.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116535.3-116569.6" + attribute \src "libresoc.v:117418.3-117452.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116473.3-116483.6" + attribute \src "libresoc.v:117356.3-117366.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116503.3-116513.6" + attribute \src "libresoc.v:117386.3-117396.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:116514.3-116534.6" + attribute \src "libresoc.v:117397.3-117417.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116535.3-116569.6" + attribute \src "libresoc.v:117418.3-117452.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116514.3-116534.6" + attribute \src "libresoc.v:117397.3-117417.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116535.3-116569.6" + attribute \src "libresoc.v:117418.3-117452.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116514.3-116534.6" + attribute \src "libresoc.v:117397.3-117417.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116535.3-116569.6" + attribute \src "libresoc.v:117418.3-117452.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116447.17-116447.127" - wire $eq$libresoc.v:116447$4604_Y - attribute \src "libresoc.v:116448.17-116448.127" - wire $eq$libresoc.v:116448$4605_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:117330.17-117330.127" + wire $eq$libresoc.v:117330$4685_Y + attribute \src "libresoc.v:117331.17-117331.127" + wire $eq$libresoc.v:117331$4686_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 5 \SHIFT_ROT_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -182163,25 +184467,25 @@ module \dec_cr_out$190 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:116331.7-116331.15" + attribute \src "libresoc.v:117214.7-117214.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -182189,7 +184493,7 @@ module \dec_cr_out$190 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -182197,10 +184501,10 @@ module \dec_cr_out$190 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116447$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117330$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -182208,10 +184512,10 @@ module \dec_cr_out$190 parameter \Y_WIDTH 1 connect \A \SHIFT_ROT_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116447$4604_Y + connect \Y $eq$libresoc.v:117330$4685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116448$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117331$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -182219,35 +184523,35 @@ module \dec_cr_out$190 parameter \Y_WIDTH 1 connect \A \SHIFT_ROT_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116448$4605_Y + connect \Y $eq$libresoc.v:117331$4686_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:116449.15-116453.4" - cell \ppick$191 \ppick + attribute \src "libresoc.v:117332.15-117336.4" + cell \ppick$194 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:116331.7-116331.20" - process $proc$libresoc.v:116331$4612 + attribute \src "libresoc.v:117214.7-117214.20" + process $proc$libresoc.v:117214$4693 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116454.3-116472.6" - process $proc$libresoc.v:116454$4606 + attribute \src "libresoc.v:117337.3-117355.6" + process $proc$libresoc.v:117337$4687 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116455.5-116455.29" + attribute \src "libresoc.v:117338.5-117338.29" switch \initial - attribute \src "libresoc.v:116455.9-116455.17" + attribute \src "libresoc.v:117338.9-117338.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -182267,18 +184571,18 @@ module \dec_cr_out$190 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:116473.3-116483.6" - process $proc$libresoc.v:116473$4607 + attribute \src "libresoc.v:117356.3-117366.6" + process $proc$libresoc.v:117356$4688 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116474.5-116474.29" + attribute \src "libresoc.v:117357.5-117357.29" switch \initial - attribute \src "libresoc.v:116474.9-116474.17" + attribute \src "libresoc.v:117357.9-117357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -182290,18 +184594,18 @@ module \dec_cr_out$190 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:116484.3-116502.6" - process $proc$libresoc.v:116484$4608 + attribute \src "libresoc.v:117367.3-117385.6" + process $proc$libresoc.v:117367$4689 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116485.5-116485.29" + attribute \src "libresoc.v:117368.5-117368.29" switch \initial - attribute \src "libresoc.v:116485.9-116485.17" + attribute \src "libresoc.v:117368.9-117368.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -182321,18 +184625,18 @@ module \dec_cr_out$190 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:116503.3-116513.6" - process $proc$libresoc.v:116503$4609 + attribute \src "libresoc.v:117386.3-117396.6" + process $proc$libresoc.v:117386$4690 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116504.5-116504.29" + attribute \src "libresoc.v:117387.5-117387.29" switch \initial - attribute \src "libresoc.v:116504.9-116504.17" + attribute \src "libresoc.v:117387.9-117387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -182344,30 +184648,30 @@ module \dec_cr_out$190 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:116514.3-116534.6" - process $proc$libresoc.v:116514$4610 + attribute \src "libresoc.v:117397.3-117417.6" + process $proc$libresoc.v:117397$4691 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116515.5-116515.29" + attribute \src "libresoc.v:117398.5-117398.29" switch \initial - attribute \src "libresoc.v:116515.9-116515.17" + attribute \src "libresoc.v:117398.9-117398.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -182385,36 +184689,36 @@ module \dec_cr_out$190 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:116535.3-116569.6" - process $proc$libresoc.v:116535$4611 + attribute \src "libresoc.v:117418.3-117452.6" + process $proc$libresoc.v:117418$4692 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116536.5-116536.29" + attribute \src "libresoc.v:117419.5-117419.29" switch \initial - attribute \src "libresoc.v:116536.9-116536.17" + attribute \src "libresoc.v:117419.9-117419.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -182441,59 +184745,59 @@ module \dec_cr_out$190 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:116447$4604_Y - connect \$3 $eq$libresoc.v:116448$4605_Y + connect \$1 $eq$libresoc.v:117330$4685_Y + connect \$3 $eq$libresoc.v:117331$4686_Y end -attribute \src "libresoc.v:116574.1-116813.10" +attribute \src "libresoc.v:117457.1-117696.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$198 - attribute \src "libresoc.v:116727.3-116745.6" +module \dec_cr_out$201 + attribute \src "libresoc.v:117610.3-117628.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116697.3-116715.6" + attribute \src "libresoc.v:117580.3-117598.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116778.3-116812.6" + attribute \src "libresoc.v:117661.3-117695.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116716.3-116726.6" + attribute \src "libresoc.v:117599.3-117609.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116575.7-116575.20" + attribute \src "libresoc.v:117458.7-117458.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116746.3-116756.6" + attribute \src "libresoc.v:117629.3-117639.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:116757.3-116777.6" + attribute \src "libresoc.v:117640.3-117660.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116727.3-116745.6" + attribute \src "libresoc.v:117610.3-117628.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116697.3-116715.6" + attribute \src "libresoc.v:117580.3-117598.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116778.3-116812.6" + attribute \src "libresoc.v:117661.3-117695.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116716.3-116726.6" + attribute \src "libresoc.v:117599.3-117609.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116746.3-116756.6" + attribute \src "libresoc.v:117629.3-117639.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:116757.3-116777.6" + attribute \src "libresoc.v:117640.3-117660.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116778.3-116812.6" + attribute \src "libresoc.v:117661.3-117695.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116757.3-116777.6" + attribute \src "libresoc.v:117640.3-117660.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116778.3-116812.6" + attribute \src "libresoc.v:117661.3-117695.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116757.3-116777.6" + attribute \src "libresoc.v:117640.3-117660.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116778.3-116812.6" + attribute \src "libresoc.v:117661.3-117695.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116690.17-116690.122" - wire $eq$libresoc.v:116690$4613_Y - attribute \src "libresoc.v:116691.17-116691.122" - wire $eq$libresoc.v:116691$4614_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:117573.17-117573.122" + wire $eq$libresoc.v:117573$4694_Y + attribute \src "libresoc.v:117574.17-117574.122" + wire $eq$libresoc.v:117574$4695_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 4 \LDST_FXM attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -182569,25 +184873,25 @@ module \dec_cr_out$198 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_fxm_ok - attribute \src "libresoc.v:116575.7-116575.15" + attribute \src "libresoc.v:117458.7-117458.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -182595,7 +184899,7 @@ module \dec_cr_out$198 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -182603,10 +184907,10 @@ module \dec_cr_out$198 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116690$4613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117573$4694 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -182614,10 +184918,10 @@ module \dec_cr_out$198 parameter \Y_WIDTH 1 connect \A \LDST_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116690$4613_Y + connect \Y $eq$libresoc.v:117573$4694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116691$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117574$4695 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -182625,35 +184929,35 @@ module \dec_cr_out$198 parameter \Y_WIDTH 1 connect \A \LDST_internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116691$4614_Y + connect \Y $eq$libresoc.v:117574$4695_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:116692.15-116696.4" - cell \ppick$199 \ppick + attribute \src "libresoc.v:117575.15-117579.4" + cell \ppick$202 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:116575.7-116575.20" - process $proc$libresoc.v:116575$4621 + attribute \src "libresoc.v:117458.7-117458.20" + process $proc$libresoc.v:117458$4702 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116697.3-116715.6" - process $proc$libresoc.v:116697$4615 + attribute \src "libresoc.v:117580.3-117598.6" + process $proc$libresoc.v:117580$4696 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116698.5-116698.29" + attribute \src "libresoc.v:117581.5-117581.29" switch \initial - attribute \src "libresoc.v:116698.9-116698.17" + attribute \src "libresoc.v:117581.9-117581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -182673,18 +184977,18 @@ module \dec_cr_out$198 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:116716.3-116726.6" - process $proc$libresoc.v:116716$4616 + attribute \src "libresoc.v:117599.3-117609.6" + process $proc$libresoc.v:117599$4697 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116717.5-116717.29" + attribute \src "libresoc.v:117600.5-117600.29" switch \initial - attribute \src "libresoc.v:116717.9-116717.17" + attribute \src "libresoc.v:117600.9-117600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -182696,18 +185000,18 @@ module \dec_cr_out$198 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:116727.3-116745.6" - process $proc$libresoc.v:116727$4617 + attribute \src "libresoc.v:117610.3-117628.6" + process $proc$libresoc.v:117610$4698 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116728.5-116728.29" + attribute \src "libresoc.v:117611.5-117611.29" switch \initial - attribute \src "libresoc.v:116728.9-116728.17" + attribute \src "libresoc.v:117611.9-117611.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -182727,18 +185031,18 @@ module \dec_cr_out$198 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:116746.3-116756.6" - process $proc$libresoc.v:116746$4618 + attribute \src "libresoc.v:117629.3-117639.6" + process $proc$libresoc.v:117629$4699 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116747.5-116747.29" + attribute \src "libresoc.v:117630.5-117630.29" switch \initial - attribute \src "libresoc.v:116747.9-116747.17" + attribute \src "libresoc.v:117630.9-117630.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -182750,30 +185054,30 @@ module \dec_cr_out$198 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:116757.3-116777.6" - process $proc$libresoc.v:116757$4619 + attribute \src "libresoc.v:117640.3-117660.6" + process $proc$libresoc.v:117640$4700 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116758.5-116758.29" + attribute \src "libresoc.v:117641.5-117641.29" switch \initial - attribute \src "libresoc.v:116758.9-116758.17" + attribute \src "libresoc.v:117641.9-117641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -182791,36 +185095,36 @@ module \dec_cr_out$198 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:116778.3-116812.6" - process $proc$libresoc.v:116778$4620 + attribute \src "libresoc.v:117661.3-117695.6" + process $proc$libresoc.v:117661$4701 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116779.5-116779.29" + attribute \src "libresoc.v:117662.5-117662.29" switch \initial - attribute \src "libresoc.v:116779.9-116779.17" + attribute \src "libresoc.v:117662.9-117662.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -182847,75 +185151,75 @@ module \dec_cr_out$198 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:116690$4613_Y - connect \$3 $eq$libresoc.v:116691$4614_Y + connect \$1 $eq$libresoc.v:117573$4694_Y + connect \$3 $eq$libresoc.v:117574$4695_Y end -attribute \src "libresoc.v:116817.1-117060.10" +attribute \src "libresoc.v:117700.1-117943.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_out$207 - attribute \src "libresoc.v:116974.3-116992.6" +module \dec_cr_out$210 + attribute \src "libresoc.v:117857.3-117875.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116944.3-116962.6" + attribute \src "libresoc.v:117827.3-117845.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117025.3-117059.6" + attribute \src "libresoc.v:117908.3-117942.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116963.3-116973.6" + attribute \src "libresoc.v:117846.3-117856.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116818.7-116818.20" + attribute \src "libresoc.v:117701.7-117701.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116993.3-117003.6" + attribute \src "libresoc.v:117876.3-117886.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:117004.3-117024.6" + attribute \src "libresoc.v:117887.3-117907.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116974.3-116992.6" + attribute \src "libresoc.v:117857.3-117875.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116944.3-116962.6" + attribute \src "libresoc.v:117827.3-117845.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117025.3-117059.6" + attribute \src "libresoc.v:117908.3-117942.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116963.3-116973.6" + attribute \src "libresoc.v:117846.3-117856.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116993.3-117003.6" + attribute \src "libresoc.v:117876.3-117886.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:117004.3-117024.6" + attribute \src "libresoc.v:117887.3-117907.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117025.3-117059.6" + attribute \src "libresoc.v:117908.3-117942.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117004.3-117024.6" + attribute \src "libresoc.v:117887.3-117907.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117025.3-117059.6" + attribute \src "libresoc.v:117908.3-117942.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117004.3-117024.6" + attribute \src "libresoc.v:117887.3-117907.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117025.3-117059.6" + attribute \src "libresoc.v:117908.3-117942.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116937.17-116937.117" - wire $eq$libresoc.v:116937$4622_Y - attribute \src "libresoc.v:116938.17-116938.117" - wire $eq$libresoc.v:116938$4623_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "libresoc.v:117820.17-117820.117" + wire $eq$libresoc.v:117820$4703_Y + attribute \src "libresoc.v:117821.17-117821.117" + wire $eq$libresoc.v:117821$4704_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:116818.7-116818.15" + attribute \src "libresoc.v:117701.7-117701.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" wire width 32 input 11 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -182991,9 +185295,9 @@ module \dec_cr_out$207 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:578" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" wire \ppick_en_o @@ -183001,7 +185305,7 @@ module \dec_cr_out$207 wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" wire input 2 \rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -183009,10 +185313,10 @@ module \dec_cr_out$207 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116937$4622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117820$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -183020,10 +185324,10 @@ module \dec_cr_out$207 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116937$4622_Y + connect \Y $eq$libresoc.v:117820$4703_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - cell $eq $eq$libresoc.v:116938$4623 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:117821$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -183031,35 +185335,35 @@ module \dec_cr_out$207 parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:116938$4623_Y + connect \Y $eq$libresoc.v:117821$4704_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:116939.15-116943.4" - cell \ppick$208 \ppick + attribute \src "libresoc.v:117822.15-117826.4" + cell \ppick$211 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:116818.7-116818.20" - process $proc$libresoc.v:116818$4630 + attribute \src "libresoc.v:117701.7-117701.20" + process $proc$libresoc.v:117701$4711 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:116944.3-116962.6" - process $proc$libresoc.v:116944$4624 + attribute \src "libresoc.v:117827.3-117845.6" + process $proc$libresoc.v:117827$4705 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116945.5-116945.29" + attribute \src "libresoc.v:117828.5-117828.29" switch \initial - attribute \src "libresoc.v:116945.9-116945.17" + attribute \src "libresoc.v:117828.9-117828.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -183079,18 +185383,18 @@ module \dec_cr_out$207 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:116963.3-116973.6" - process $proc$libresoc.v:116963$4625 + attribute \src "libresoc.v:117846.3-117856.6" + process $proc$libresoc.v:117846$4706 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116964.5-116964.29" + attribute \src "libresoc.v:117847.5-117847.29" switch \initial - attribute \src "libresoc.v:116964.9-116964.17" + attribute \src "libresoc.v:117847.9-117847.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -183102,18 +185406,18 @@ module \dec_cr_out$207 sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:116974.3-116992.6" - process $proc$libresoc.v:116974$4626 + attribute \src "libresoc.v:117857.3-117875.6" + process $proc$libresoc.v:117857$4707 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116975.5-116975.29" + attribute \src "libresoc.v:117858.5-117858.29" switch \initial - attribute \src "libresoc.v:116975.9-116975.17" + attribute \src "libresoc.v:117858.9-117858.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -183133,18 +185437,18 @@ module \dec_cr_out$207 sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:116993.3-117003.6" - process $proc$libresoc.v:116993$4627 + attribute \src "libresoc.v:117876.3-117886.6" + process $proc$libresoc.v:117876$4708 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116994.5-116994.29" + attribute \src "libresoc.v:117877.5-117877.29" switch \initial - attribute \src "libresoc.v:116994.9-116994.17" + attribute \src "libresoc.v:117877.9-117877.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -183156,30 +185460,30 @@ module \dec_cr_out$207 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:117004.3-117024.6" - process $proc$libresoc.v:117004$4628 + attribute \src "libresoc.v:117887.3-117907.6" + process $proc$libresoc.v:117887$4709 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117005.5-117005.29" + attribute \src "libresoc.v:117888.5-117888.29" switch \initial - attribute \src "libresoc.v:117005.9-117005.17" + attribute \src "libresoc.v:117888.9-117888.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183197,36 +185501,36 @@ module \dec_cr_out$207 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:117025.3-117059.6" - process $proc$libresoc.v:117025$4629 + attribute \src "libresoc.v:117908.3-117942.6" + process $proc$libresoc.v:117908$4710 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117026.5-117026.29" + attribute \src "libresoc.v:117909.5-117909.29" switch \initial - attribute \src "libresoc.v:117026.9-117026.17" + attribute \src "libresoc.v:117909.9-117909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" switch \move_one attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" switch \ppick_en_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183253,95 +185557,95 @@ module \dec_cr_out$207 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:116937$4622_Y - connect \$3 $eq$libresoc.v:116938$4623_Y + connect \$1 $eq$libresoc.v:117820$4703_Y + connect \$3 $eq$libresoc.v:117821$4704_Y end -attribute \src "libresoc.v:117064.1-117541.10" +attribute \src "libresoc.v:117947.1-118424.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:117065.7-117065.20" + attribute \src "libresoc.v:117948.7-117948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117428.3-117442.6" + attribute \src "libresoc.v:118311.3-118325.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:117443.3-117457.6" + attribute \src "libresoc.v:118326.3-118340.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:117458.3-117468.6" + attribute \src "libresoc.v:118341.3-118351.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:117469.3-117484.6" + attribute \src "libresoc.v:118352.3-118367.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:117428.3-117442.6" + attribute \src "libresoc.v:118311.3-118325.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:117443.3-117457.6" + attribute \src "libresoc.v:118326.3-118340.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:117458.3-117468.6" + attribute \src "libresoc.v:118341.3-118351.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:117469.3-117484.6" + attribute \src "libresoc.v:118352.3-118367.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:117485.3-117501.6" + attribute \src "libresoc.v:118368.3-118384.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:117469.3-117484.6" + attribute \src "libresoc.v:118352.3-118367.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:117502.3-117540.6" + attribute \src "libresoc.v:118385.3-118423.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:117417.17-117417.117" - wire $eq$libresoc.v:117417$4631_Y - attribute \src "libresoc.v:117418.17-117418.117" - wire $eq$libresoc.v:117418$4632_Y - attribute \src "libresoc.v:117419.17-117419.117" - wire $eq$libresoc.v:117419$4633_Y - attribute \src "libresoc.v:117420.17-117420.104" - wire $not$libresoc.v:117420$4634_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "libresoc.v:118300.17-118300.117" + wire $eq$libresoc.v:118300$4712_Y + attribute \src "libresoc.v:118301.17-118301.117" + wire $eq$libresoc.v:118301$4713_Y + attribute \src "libresoc.v:118302.17-118302.117" + wire $eq$libresoc.v:118302$4714_Y + attribute \src "libresoc.v:118303.17-118303.104" + wire $not$libresoc.v:118303$4715_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 8 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 6 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 7 \fast_o_ok - attribute \src "libresoc.v:117065.7-117065.15" + attribute \src "libresoc.v:117948.7-117948.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -183417,20 +185721,20 @@ module \dec_o attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 12 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \reg_o_ok attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" wire width 2 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -183543,15 +185847,15 @@ module \dec_o attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 4 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -183664,12 +185968,12 @@ module \dec_o attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:117417$4631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118300$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -183677,10 +185981,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:117417$4631_Y + connect \Y $eq$libresoc.v:118300$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:117418$4632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118301$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -183688,10 +185992,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:117418$4632_Y + connect \Y $eq$libresoc.v:118301$4713_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $eq$libresoc.v:117419$4633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:118302$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -183699,45 +186003,45 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:117419$4633_Y + connect \Y $eq$libresoc.v:118302$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $not$libresoc.v:117420$4634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + cell $not $not$libresoc.v:118303$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:117420$4634_Y + connect \Y $not$libresoc.v:118303$4715_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:117421.16-117427.4" - cell \sprmap$209 \sprmap + attribute \src "libresoc.v:118304.16-118310.4" + cell \sprmap$212 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok connect \spr_i \sprmap_spr_i connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:117065.7-117065.20" - process $proc$libresoc.v:117065$4641 + attribute \src "libresoc.v:117948.7-117948.20" + process $proc$libresoc.v:117948$4722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117428.3-117442.6" - process $proc$libresoc.v:117428$4635 + attribute \src "libresoc.v:118311.3-118325.6" + process $proc$libresoc.v:118311$4716 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:117429.5-117429.29" + attribute \src "libresoc.v:118312.5-118312.29" switch \initial - attribute \src "libresoc.v:117429.9-117429.17" + attribute \src "libresoc.v:118312.9-118312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -183753,18 +186057,18 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:117443.3-117457.6" - process $proc$libresoc.v:117443$4636 + attribute \src "libresoc.v:118326.3-118340.6" + process $proc$libresoc.v:118326$4717 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:117444.5-117444.29" + attribute \src "libresoc.v:118327.5-118327.29" switch \initial - attribute \src "libresoc.v:117444.9-117444.17" + attribute \src "libresoc.v:118327.9-118327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -183780,18 +186084,18 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:117458.3-117468.6" - process $proc$libresoc.v:117458$4637 + attribute \src "libresoc.v:118341.3-118351.6" + process $proc$libresoc.v:118341$4718 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:117459.5-117459.29" + attribute \src "libresoc.v:118342.5-118342.29" switch \initial - attribute \src "libresoc.v:117459.9-117459.17" + attribute \src "libresoc.v:118342.9-118342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'11 @@ -183803,24 +186107,24 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:117469.3-117484.6" - process $proc$libresoc.v:117469$4638 + attribute \src "libresoc.v:118352.3-118367.6" + process $proc$libresoc.v:118352$4719 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:117470.5-117470.29" + attribute \src "libresoc.v:118353.5-118353.29" switch \initial - attribute \src "libresoc.v:117470.9-117470.17" + attribute \src "libresoc.v:118353.9-118353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183835,21 +186139,21 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:117485.3-117501.6" - process $proc$libresoc.v:117485$4639 + attribute \src "libresoc.v:118368.3-118384.6" + process $proc$libresoc.v:118368$4720 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:117486.5-117486.29" + attribute \src "libresoc.v:118369.5-118369.29" switch \initial - attribute \src "libresoc.v:117486.9-117486.17" + attribute \src "libresoc.v:118369.9-118369.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'11 @@ -183857,7 +186161,7 @@ module \dec_o assign { } { } assign $1\spr_o[9:0] $2\spr_o[9:0] assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183876,8 +186180,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:117502.3-117540.6" - process $proc$libresoc.v:117502$4640 + attribute \src "libresoc.v:118385.3-118423.6" + process $proc$libresoc.v:118385$4721 assign { } { } assign { } { } assign { } { } @@ -183886,13 +186190,13 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:117503.5-117503.29" + attribute \src "libresoc.v:118386.5-118386.29" switch \initial - attribute \src "libresoc.v:117503.9-117503.17" + attribute \src "libresoc.v:118386.9-118386.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'11 @@ -183900,7 +186204,7 @@ module \dec_o assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183915,7 +186219,7 @@ module \dec_o assign $1\fast_o[2:0] 3'000 assign $1\fast_o_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0001000 @@ -183923,7 +186227,7 @@ module \dec_o assign { } { } assign $3\fast_o[2:0] $4\fast_o[2:0] assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -183949,55 +186253,55 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:117417$4631_Y - connect \$3 $eq$libresoc.v:117418$4632_Y - connect \$5 $eq$libresoc.v:117419$4633_Y - connect \$7 $not$libresoc.v:117420$4634_Y + connect \$1 $eq$libresoc.v:118300$4712_Y + connect \$3 $eq$libresoc.v:118301$4713_Y + connect \$5 $eq$libresoc.v:118302$4714_Y + connect \$7 $not$libresoc.v:118303$4715_Y end -attribute \src "libresoc.v:117545.1-117706.10" +attribute \src "libresoc.v:118428.1-118589.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:117666.3-117685.6" + attribute \src "libresoc.v:118549.3-118568.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:117686.3-117705.6" + attribute \src "libresoc.v:118569.3-118588.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:117546.7-117546.20" + attribute \src "libresoc.v:118429.7-118429.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117652.3-117665.6" + attribute \src "libresoc.v:118535.3-118548.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:117652.3-117665.6" + attribute \src "libresoc.v:118535.3-118548.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:117666.3-117685.6" + attribute \src "libresoc.v:118549.3-118568.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:117686.3-117705.6" + attribute \src "libresoc.v:118569.3-118588.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:117652.3-117665.6" + attribute \src "libresoc.v:118535.3-118548.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:117652.3-117665.6" + attribute \src "libresoc.v:118535.3-118548.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:117666.3-117685.6" + attribute \src "libresoc.v:118549.3-118568.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:117686.3-117705.6" + attribute \src "libresoc.v:118569.3-118588.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:117650.17-117650.108" - wire $eq$libresoc.v:117650$4642_Y - attribute \src "libresoc.v:117651.17-117651.100" - wire width 6 $extend$libresoc.v:117651$4643_Y - attribute \src "libresoc.v:117651.17-117651.100" - wire width 6 $pos$libresoc.v:117651$4644_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + attribute \src "libresoc.v:118533.17-118533.108" + wire $eq$libresoc.v:118533$4723_Y + attribute \src "libresoc.v:118534.17-118534.100" + wire width 6 $extend$libresoc.v:118534$4724_Y + attribute \src "libresoc.v:118534.17-118534.100" + wire width 6 $pos$libresoc.v:118534$4725_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_o_ok - attribute \src "libresoc.v:117546.7-117546.15" + attribute \src "libresoc.v:118429.7-118429.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184073,23 +186377,23 @@ module \dec_o2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \reg_o_ok attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" - cell $eq $eq$libresoc.v:117650$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + cell $eq $eq$libresoc.v:118533$4723 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -184097,47 +186401,47 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:117650$4642_Y + connect \Y $eq$libresoc.v:118533$4723_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $extend$libresoc.v:117651$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:118534$4724 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 6 connect \A \RA - connect \Y $extend$libresoc.v:117651$4643_Y + connect \Y $extend$libresoc.v:118534$4724_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" - cell $pos $pos$libresoc.v:117651$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:118534$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 - connect \A $extend$libresoc.v:117651$4643_Y - connect \Y $pos$libresoc.v:117651$4644_Y + connect \A $extend$libresoc.v:118534$4724_Y + connect \Y $pos$libresoc.v:118534$4725_Y end - attribute \src "libresoc.v:117546.7-117546.20" - process $proc$libresoc.v:117546$4648 + attribute \src "libresoc.v:118429.7-118429.20" + process $proc$libresoc.v:118429$4729 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117652.3-117665.6" - process $proc$libresoc.v:117652$4645 + attribute \src "libresoc.v:118535.3-118548.6" + process $proc$libresoc.v:118535$4726 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:117653.5-117653.29" + attribute \src "libresoc.v:118536.5-118536.29" switch \initial - attribute \src "libresoc.v:117653.9-117653.17" + attribute \src "libresoc.v:118536.9-118536.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -184153,24 +186457,24 @@ module \dec_o2 update \reg_o $0\reg_o[4:0] update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:117666.3-117685.6" - process $proc$libresoc.v:117666$4646 + attribute \src "libresoc.v:118549.3-118568.6" + process $proc$libresoc.v:118549$4727 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:117667.5-117667.29" + attribute \src "libresoc.v:118550.5-118550.29" switch \initial - attribute \src "libresoc.v:117667.9-117667.17" + attribute \src "libresoc.v:118550.9-118550.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -184189,24 +186493,24 @@ module \dec_o2 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:117686.3-117705.6" - process $proc$libresoc.v:117686$4647 + attribute \src "libresoc.v:118569.3-118588.6" + process $proc$libresoc.v:118569$4728 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:117687.5-117687.29" + attribute \src "libresoc.v:118570.5-118570.29" switch \initial - attribute \src "libresoc.v:117687.9-117687.17" + attribute \src "libresoc.v:118570.9-118570.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:381" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:385" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -184225,29 +186529,29 @@ module \dec_o2 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:117650$4642_Y - connect \$3 $pos$libresoc.v:117651$4644_Y + connect \$1 $eq$libresoc.v:118533$4723_Y + connect \$3 $pos$libresoc.v:118534$4725_Y end -attribute \src "libresoc.v:117710.1-117844.10" +attribute \src "libresoc.v:118593.1-118727.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:117711.7-117711.20" + attribute \src "libresoc.v:118594.7-118594.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117802.3-117822.6" + attribute \src "libresoc.v:118685.3-118705.6" wire $0\oe[0:0] - attribute \src "libresoc.v:117823.3-117843.6" + attribute \src "libresoc.v:118706.3-118726.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:117802.3-117822.6" + attribute \src "libresoc.v:118685.3-118705.6" wire $1\oe[0:0] - attribute \src "libresoc.v:117823.3-117843.6" + attribute \src "libresoc.v:118706.3-118726.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:117802.3-117822.6" + attribute \src "libresoc.v:118685.3-118705.6" wire $2\oe[0:0] - attribute \src "libresoc.v:117823.3-117843.6" + attribute \src "libresoc.v:118706.3-118726.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184323,40 +186627,40 @@ module \dec_oe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:117711.7-117711.15" + attribute \src "libresoc.v:118594.7-118594.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:117711.7-117711.20" - process $proc$libresoc.v:117711$4651 + attribute \src "libresoc.v:118594.7-118594.20" + process $proc$libresoc.v:118594$4732 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117802.3-117822.6" - process $proc$libresoc.v:117802$4649 + attribute \src "libresoc.v:118685.3-118705.6" + process $proc$libresoc.v:118685$4730 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:117803.5-117803.29" + attribute \src "libresoc.v:118686.5-118686.29" switch \initial - attribute \src "libresoc.v:117803.9-117803.17" + attribute \src "libresoc.v:118686.9-118686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184365,7 +186669,7 @@ module \dec_oe case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184378,18 +186682,18 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:117823.3-117843.6" - process $proc$libresoc.v:117823$4650 + attribute \src "libresoc.v:118706.3-118726.6" + process $proc$libresoc.v:118706$4731 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:117824.5-117824.29" + attribute \src "libresoc.v:118707.5-118707.29" switch \initial - attribute \src "libresoc.v:117824.9-117824.17" + attribute \src "libresoc.v:118707.9-118707.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184398,7 +186702,7 @@ module \dec_oe case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184412,26 +186716,26 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:117848.1-117980.10" +attribute \src "libresoc.v:118731.1-118863.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" -module \dec_oe$139 - attribute \src "libresoc.v:117849.7-117849.20" +module \dec_oe$142 + attribute \src "libresoc.v:118732.7-118732.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117938.3-117958.6" + attribute \src "libresoc.v:118821.3-118841.6" wire $0\oe[0:0] - attribute \src "libresoc.v:117959.3-117979.6" + attribute \src "libresoc.v:118842.3-118862.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:117938.3-117958.6" + attribute \src "libresoc.v:118821.3-118841.6" wire $1\oe[0:0] - attribute \src "libresoc.v:117959.3-117979.6" + attribute \src "libresoc.v:118842.3-118862.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:117938.3-117958.6" + attribute \src "libresoc.v:118821.3-118841.6" wire $2\oe[0:0] - attribute \src "libresoc.v:117959.3-117979.6" + attribute \src "libresoc.v:118842.3-118862.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184507,40 +186811,40 @@ module \dec_oe$139 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:117849.7-117849.15" + attribute \src "libresoc.v:118732.7-118732.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:117849.7-117849.20" - process $proc$libresoc.v:117849$4654 + attribute \src "libresoc.v:118732.7-118732.20" + process $proc$libresoc.v:118732$4735 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117938.3-117958.6" - process $proc$libresoc.v:117938$4652 + attribute \src "libresoc.v:118821.3-118841.6" + process $proc$libresoc.v:118821$4733 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:117939.5-117939.29" + attribute \src "libresoc.v:118822.5-118822.29" switch \initial - attribute \src "libresoc.v:117939.9-117939.17" + attribute \src "libresoc.v:118822.9-118822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184549,7 +186853,7 @@ module \dec_oe$139 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184562,18 +186866,18 @@ module \dec_oe$139 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:117959.3-117979.6" - process $proc$libresoc.v:117959$4653 + attribute \src "libresoc.v:118842.3-118862.6" + process $proc$libresoc.v:118842$4734 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:117960.5-117960.29" + attribute \src "libresoc.v:118843.5-118843.29" switch \initial - attribute \src "libresoc.v:117960.9-117960.17" + attribute \src "libresoc.v:118843.9-118843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184582,7 +186886,7 @@ module \dec_oe$139 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184596,26 +186900,26 @@ module \dec_oe$139 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:117984.1-118116.10" +attribute \src "libresoc.v:118867.1-118999.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" -module \dec_oe$146 - attribute \src "libresoc.v:117985.7-117985.20" +module \dec_oe$149 + attribute \src "libresoc.v:118868.7-118868.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118074.3-118094.6" + attribute \src "libresoc.v:118957.3-118977.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118095.3-118115.6" + attribute \src "libresoc.v:118978.3-118998.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118074.3-118094.6" + attribute \src "libresoc.v:118957.3-118977.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118095.3-118115.6" + attribute \src "libresoc.v:118978.3-118998.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118074.3-118094.6" + attribute \src "libresoc.v:118957.3-118977.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118095.3-118115.6" + attribute \src "libresoc.v:118978.3-118998.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184691,40 +186995,40 @@ module \dec_oe$146 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:117985.7-117985.15" + attribute \src "libresoc.v:118868.7-118868.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:117985.7-117985.20" - process $proc$libresoc.v:117985$4657 + attribute \src "libresoc.v:118868.7-118868.20" + process $proc$libresoc.v:118868$4738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118074.3-118094.6" - process $proc$libresoc.v:118074$4655 + attribute \src "libresoc.v:118957.3-118977.6" + process $proc$libresoc.v:118957$4736 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118075.5-118075.29" + attribute \src "libresoc.v:118958.5-118958.29" switch \initial - attribute \src "libresoc.v:118075.9-118075.17" + attribute \src "libresoc.v:118958.9-118958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184733,7 +187037,7 @@ module \dec_oe$146 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184746,18 +187050,18 @@ module \dec_oe$146 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118095.3-118115.6" - process $proc$libresoc.v:118095$4656 + attribute \src "libresoc.v:118978.3-118998.6" + process $proc$libresoc.v:118978$4737 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118096.5-118096.29" + attribute \src "libresoc.v:118979.5-118979.29" switch \initial - attribute \src "libresoc.v:118096.9-118096.17" + attribute \src "libresoc.v:118979.9-118979.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184766,7 +187070,7 @@ module \dec_oe$146 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184780,26 +187084,26 @@ module \dec_oe$146 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118120.1-118254.10" +attribute \src "libresoc.v:119003.1-119137.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" -module \dec_oe$154 - attribute \src "libresoc.v:118121.7-118121.20" +module \dec_oe$157 + attribute \src "libresoc.v:119004.7-119004.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118212.3-118232.6" + attribute \src "libresoc.v:119095.3-119115.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118233.3-118253.6" + attribute \src "libresoc.v:119116.3-119136.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118212.3-118232.6" + attribute \src "libresoc.v:119095.3-119115.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118233.3-118253.6" + attribute \src "libresoc.v:119116.3-119136.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118212.3-118232.6" + attribute \src "libresoc.v:119095.3-119115.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118233.3-118253.6" + attribute \src "libresoc.v:119116.3-119136.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -184875,40 +187179,40 @@ module \dec_oe$154 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:118121.7-118121.15" + attribute \src "libresoc.v:119004.7-119004.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118121.7-118121.20" - process $proc$libresoc.v:118121$4660 + attribute \src "libresoc.v:119004.7-119004.20" + process $proc$libresoc.v:119004$4741 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118212.3-118232.6" - process $proc$libresoc.v:118212$4658 + attribute \src "libresoc.v:119095.3-119115.6" + process $proc$libresoc.v:119095$4739 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118213.5-118213.29" + attribute \src "libresoc.v:119096.5-119096.29" switch \initial - attribute \src "libresoc.v:118213.9-118213.17" + attribute \src "libresoc.v:119096.9-119096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184917,7 +187221,7 @@ module \dec_oe$154 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184930,18 +187234,18 @@ module \dec_oe$154 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118233.3-118253.6" - process $proc$libresoc.v:118233$4659 + attribute \src "libresoc.v:119116.3-119136.6" + process $proc$libresoc.v:119116$4740 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118234.5-118234.29" + attribute \src "libresoc.v:119117.5-119117.29" switch \initial - attribute \src "libresoc.v:118234.9-118234.17" + attribute \src "libresoc.v:119117.9-119117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -184950,7 +187254,7 @@ module \dec_oe$154 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -184964,26 +187268,26 @@ module \dec_oe$154 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118258.1-118390.10" +attribute \src "libresoc.v:119141.1-119273.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" -module \dec_oe$163 - attribute \src "libresoc.v:118259.7-118259.20" +module \dec_oe$166 + attribute \src "libresoc.v:119142.7-119142.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118348.3-118368.6" + attribute \src "libresoc.v:119231.3-119251.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118369.3-118389.6" + attribute \src "libresoc.v:119252.3-119272.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118348.3-118368.6" + attribute \src "libresoc.v:119231.3-119251.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118369.3-118389.6" + attribute \src "libresoc.v:119252.3-119272.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118348.3-118368.6" + attribute \src "libresoc.v:119231.3-119251.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118369.3-118389.6" + attribute \src "libresoc.v:119252.3-119272.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185059,40 +187363,40 @@ module \dec_oe$163 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:118259.7-118259.15" + attribute \src "libresoc.v:119142.7-119142.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118259.7-118259.20" - process $proc$libresoc.v:118259$4663 + attribute \src "libresoc.v:119142.7-119142.20" + process $proc$libresoc.v:119142$4744 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118348.3-118368.6" - process $proc$libresoc.v:118348$4661 + attribute \src "libresoc.v:119231.3-119251.6" + process $proc$libresoc.v:119231$4742 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118349.5-118349.29" + attribute \src "libresoc.v:119232.5-119232.29" switch \initial - attribute \src "libresoc.v:118349.9-118349.17" + attribute \src "libresoc.v:119232.9-119232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185101,7 +187405,7 @@ module \dec_oe$163 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185114,18 +187418,18 @@ module \dec_oe$163 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118369.3-118389.6" - process $proc$libresoc.v:118369$4662 + attribute \src "libresoc.v:119252.3-119272.6" + process $proc$libresoc.v:119252$4743 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118370.5-118370.29" + attribute \src "libresoc.v:119253.5-119253.29" switch \initial - attribute \src "libresoc.v:118370.9-118370.17" + attribute \src "libresoc.v:119253.9-119253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185134,7 +187438,7 @@ module \dec_oe$163 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185148,26 +187452,26 @@ module \dec_oe$163 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118394.1-118528.10" +attribute \src "libresoc.v:119277.1-119411.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" -module \dec_oe$170 - attribute \src "libresoc.v:118395.7-118395.20" +module \dec_oe$173 + attribute \src "libresoc.v:119278.7-119278.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118486.3-118506.6" + attribute \src "libresoc.v:119369.3-119389.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118507.3-118527.6" + attribute \src "libresoc.v:119390.3-119410.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118486.3-118506.6" + attribute \src "libresoc.v:119369.3-119389.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118507.3-118527.6" + attribute \src "libresoc.v:119390.3-119410.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118486.3-118506.6" + attribute \src "libresoc.v:119369.3-119389.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118507.3-118527.6" + attribute \src "libresoc.v:119390.3-119410.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185243,40 +187547,40 @@ module \dec_oe$170 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:118395.7-118395.15" + attribute \src "libresoc.v:119278.7-119278.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118395.7-118395.20" - process $proc$libresoc.v:118395$4666 + attribute \src "libresoc.v:119278.7-119278.20" + process $proc$libresoc.v:119278$4747 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118486.3-118506.6" - process $proc$libresoc.v:118486$4664 + attribute \src "libresoc.v:119369.3-119389.6" + process $proc$libresoc.v:119369$4745 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118487.5-118487.29" + attribute \src "libresoc.v:119370.5-119370.29" switch \initial - attribute \src "libresoc.v:118487.9-118487.17" + attribute \src "libresoc.v:119370.9-119370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185285,7 +187589,7 @@ module \dec_oe$170 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185298,18 +187602,18 @@ module \dec_oe$170 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118507.3-118527.6" - process $proc$libresoc.v:118507$4665 + attribute \src "libresoc.v:119390.3-119410.6" + process $proc$libresoc.v:119390$4746 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118508.5-118508.29" + attribute \src "libresoc.v:119391.5-119391.29" switch \initial - attribute \src "libresoc.v:118508.9-118508.17" + attribute \src "libresoc.v:119391.9-119391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185318,7 +187622,7 @@ module \dec_oe$170 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185332,26 +187636,26 @@ module \dec_oe$170 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118532.1-118666.10" +attribute \src "libresoc.v:119415.1-119549.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" -module \dec_oe$179 - attribute \src "libresoc.v:118533.7-118533.20" +module \dec_oe$182 + attribute \src "libresoc.v:119416.7-119416.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118624.3-118644.6" + attribute \src "libresoc.v:119507.3-119527.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118645.3-118665.6" + attribute \src "libresoc.v:119528.3-119548.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118624.3-118644.6" + attribute \src "libresoc.v:119507.3-119527.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118645.3-118665.6" + attribute \src "libresoc.v:119528.3-119548.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118624.3-118644.6" + attribute \src "libresoc.v:119507.3-119527.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118645.3-118665.6" + attribute \src "libresoc.v:119528.3-119548.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185427,40 +187731,40 @@ module \dec_oe$179 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:118533.7-118533.15" + attribute \src "libresoc.v:119416.7-119416.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118533.7-118533.20" - process $proc$libresoc.v:118533$4669 + attribute \src "libresoc.v:119416.7-119416.20" + process $proc$libresoc.v:119416$4750 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118624.3-118644.6" - process $proc$libresoc.v:118624$4667 + attribute \src "libresoc.v:119507.3-119527.6" + process $proc$libresoc.v:119507$4748 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118625.5-118625.29" + attribute \src "libresoc.v:119508.5-119508.29" switch \initial - attribute \src "libresoc.v:118625.9-118625.17" + attribute \src "libresoc.v:119508.9-119508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185469,7 +187773,7 @@ module \dec_oe$179 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185482,18 +187786,18 @@ module \dec_oe$179 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118645.3-118665.6" - process $proc$libresoc.v:118645$4668 + attribute \src "libresoc.v:119528.3-119548.6" + process $proc$libresoc.v:119528$4749 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118646.5-118646.29" + attribute \src "libresoc.v:119529.5-119529.29" switch \initial - attribute \src "libresoc.v:118646.9-118646.17" + attribute \src "libresoc.v:119529.9-119529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185502,7 +187806,7 @@ module \dec_oe$179 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185516,26 +187820,26 @@ module \dec_oe$179 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118670.1-118804.10" +attribute \src "libresoc.v:119553.1-119687.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" -module \dec_oe$187 - attribute \src "libresoc.v:118671.7-118671.20" +module \dec_oe$190 + attribute \src "libresoc.v:119554.7-119554.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118762.3-118782.6" + attribute \src "libresoc.v:119645.3-119665.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118783.3-118803.6" + attribute \src "libresoc.v:119666.3-119686.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118762.3-118782.6" + attribute \src "libresoc.v:119645.3-119665.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118783.3-118803.6" + attribute \src "libresoc.v:119666.3-119686.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118762.3-118782.6" + attribute \src "libresoc.v:119645.3-119665.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118783.3-118803.6" + attribute \src "libresoc.v:119666.3-119686.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185611,40 +187915,40 @@ module \dec_oe$187 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:118671.7-118671.15" + attribute \src "libresoc.v:119554.7-119554.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118671.7-118671.20" - process $proc$libresoc.v:118671$4672 + attribute \src "libresoc.v:119554.7-119554.20" + process $proc$libresoc.v:119554$4753 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118762.3-118782.6" - process $proc$libresoc.v:118762$4670 + attribute \src "libresoc.v:119645.3-119665.6" + process $proc$libresoc.v:119645$4751 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118763.5-118763.29" + attribute \src "libresoc.v:119646.5-119646.29" switch \initial - attribute \src "libresoc.v:118763.9-118763.17" + attribute \src "libresoc.v:119646.9-119646.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185653,7 +187957,7 @@ module \dec_oe$187 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185666,18 +187970,18 @@ module \dec_oe$187 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118783.3-118803.6" - process $proc$libresoc.v:118783$4671 + attribute \src "libresoc.v:119666.3-119686.6" + process $proc$libresoc.v:119666$4752 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118784.5-118784.29" + attribute \src "libresoc.v:119667.5-119667.29" switch \initial - attribute \src "libresoc.v:118784.9-118784.17" + attribute \src "libresoc.v:119667.9-119667.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185686,7 +187990,7 @@ module \dec_oe$187 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185700,26 +188004,26 @@ module \dec_oe$187 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118808.1-118942.10" +attribute \src "libresoc.v:119691.1-119825.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" -module \dec_oe$195 - attribute \src "libresoc.v:118809.7-118809.20" +module \dec_oe$198 + attribute \src "libresoc.v:119692.7-119692.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118900.3-118920.6" + attribute \src "libresoc.v:119783.3-119803.6" wire $0\oe[0:0] - attribute \src "libresoc.v:118921.3-118941.6" + attribute \src "libresoc.v:119804.3-119824.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118900.3-118920.6" + attribute \src "libresoc.v:119783.3-119803.6" wire $1\oe[0:0] - attribute \src "libresoc.v:118921.3-118941.6" + attribute \src "libresoc.v:119804.3-119824.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118900.3-118920.6" + attribute \src "libresoc.v:119783.3-119803.6" wire $2\oe[0:0] - attribute \src "libresoc.v:118921.3-118941.6" + attribute \src "libresoc.v:119804.3-119824.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185795,40 +188099,40 @@ module \dec_oe$195 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:118809.7-118809.15" + attribute \src "libresoc.v:119692.7-119692.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118809.7-118809.20" - process $proc$libresoc.v:118809$4675 + attribute \src "libresoc.v:119692.7-119692.20" + process $proc$libresoc.v:119692$4756 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118900.3-118920.6" - process $proc$libresoc.v:118900$4673 + attribute \src "libresoc.v:119783.3-119803.6" + process $proc$libresoc.v:119783$4754 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118901.5-118901.29" + attribute \src "libresoc.v:119784.5-119784.29" switch \initial - attribute \src "libresoc.v:118901.9-118901.17" + attribute \src "libresoc.v:119784.9-119784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185837,7 +188141,7 @@ module \dec_oe$195 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185850,18 +188154,18 @@ module \dec_oe$195 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:118921.3-118941.6" - process $proc$libresoc.v:118921$4674 + attribute \src "libresoc.v:119804.3-119824.6" + process $proc$libresoc.v:119804$4755 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118922.5-118922.29" + attribute \src "libresoc.v:119805.5-119805.29" switch \initial - attribute \src "libresoc.v:118922.9-118922.17" + attribute \src "libresoc.v:119805.9-119805.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -185870,7 +188174,7 @@ module \dec_oe$195 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -185884,28 +188188,28 @@ module \dec_oe$195 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:118946.1-119080.10" +attribute \src "libresoc.v:119829.1-119963.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" -module \dec_oe$204 - attribute \src "libresoc.v:118947.7-118947.20" +module \dec_oe$207 + attribute \src "libresoc.v:119830.7-119830.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119038.3-119058.6" + attribute \src "libresoc.v:119921.3-119941.6" wire $0\oe[0:0] - attribute \src "libresoc.v:119059.3-119079.6" + attribute \src "libresoc.v:119942.3-119962.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119038.3-119058.6" + attribute \src "libresoc.v:119921.3-119941.6" wire $1\oe[0:0] - attribute \src "libresoc.v:119059.3-119079.6" + attribute \src "libresoc.v:119942.3-119962.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119038.3-119058.6" + attribute \src "libresoc.v:119921.3-119941.6" wire $2\oe[0:0] - attribute \src "libresoc.v:119059.3-119079.6" + attribute \src "libresoc.v:119942.3-119962.6" wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 4 \OE - attribute \src "libresoc.v:118947.7-118947.15" + attribute \src "libresoc.v:119830.7-119830.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -185981,38 +188285,38 @@ module \dec_oe$204 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 3 \oe_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118947.7-118947.20" - process $proc$libresoc.v:118947$4678 + attribute \src "libresoc.v:119830.7-119830.20" + process $proc$libresoc.v:119830$4759 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119038.3-119058.6" - process $proc$libresoc.v:119038$4676 + attribute \src "libresoc.v:119921.3-119941.6" + process $proc$libresoc.v:119921$4757 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119039.5-119039.29" + attribute \src "libresoc.v:119922.5-119922.29" switch \initial - attribute \src "libresoc.v:119039.9-119039.17" + attribute \src "libresoc.v:119922.9-119922.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186021,7 +188325,7 @@ module \dec_oe$204 case assign { } { } assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186034,18 +188338,18 @@ module \dec_oe$204 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:119059.3-119079.6" - process $proc$libresoc.v:119059$4677 + attribute \src "libresoc.v:119942.3-119962.6" + process $proc$libresoc.v:119942$4758 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119060.5-119060.29" + attribute \src "libresoc.v:119943.5-119943.29" switch \initial - attribute \src "libresoc.v:119060.9-119060.17" + attribute \src "libresoc.v:119943.9-119943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 @@ -186054,7 +188358,7 @@ module \dec_oe$204 case assign { } { } assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186068,55 +188372,55 @@ module \dec_oe$204 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:119084.1-119138.10" +attribute \src "libresoc.v:119967.1-120021.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:119085.7-119085.20" + attribute \src "libresoc.v:119968.7-119968.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119100.3-119118.6" + attribute \src "libresoc.v:119983.3-120001.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119119.3-119137.6" + attribute \src "libresoc.v:120002.3-120020.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119100.3-119118.6" + attribute \src "libresoc.v:119983.3-120001.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119119.3-119137.6" + attribute \src "libresoc.v:120002.3-120020.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \ALU_Rc - attribute \src "libresoc.v:119085.7-119085.15" + attribute \src "libresoc.v:119968.7-119968.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119085.7-119085.20" - process $proc$libresoc.v:119085$4681 + attribute \src "libresoc.v:119968.7-119968.20" + process $proc$libresoc.v:119968$4762 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119100.3-119118.6" - process $proc$libresoc.v:119100$4679 + attribute \src "libresoc.v:119983.3-120001.6" + process $proc$libresoc.v:119983$4760 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119101.5-119101.29" + attribute \src "libresoc.v:119984.5-119984.29" switch \initial - attribute \src "libresoc.v:119101.9-119101.17" + attribute \src "libresoc.v:119984.9-119984.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186136,18 +188440,18 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119119.3-119137.6" - process $proc$libresoc.v:119119$4680 + attribute \src "libresoc.v:120002.3-120020.6" + process $proc$libresoc.v:120002$4761 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119120.5-119120.29" + attribute \src "libresoc.v:120003.5-120003.29" switch \initial - attribute \src "libresoc.v:119120.9-119120.17" + attribute \src "libresoc.v:120003.9-120003.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186168,55 +188472,55 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119142.1-119195.10" +attribute \src "libresoc.v:120025.1-120078.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" -module \dec_rc$138 - attribute \src "libresoc.v:119143.7-119143.20" +module \dec_rc$141 + attribute \src "libresoc.v:120026.7-120026.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119157.3-119175.6" + attribute \src "libresoc.v:120040.3-120058.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119176.3-119194.6" + attribute \src "libresoc.v:120059.3-120077.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119157.3-119175.6" + attribute \src "libresoc.v:120040.3-120058.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119176.3-119194.6" + attribute \src "libresoc.v:120059.3-120077.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \CR_Rc - attribute \src "libresoc.v:119143.7-119143.15" + attribute \src "libresoc.v:120026.7-120026.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119143.7-119143.20" - process $proc$libresoc.v:119143$4684 + attribute \src "libresoc.v:120026.7-120026.20" + process $proc$libresoc.v:120026$4765 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119157.3-119175.6" - process $proc$libresoc.v:119157$4682 + attribute \src "libresoc.v:120040.3-120058.6" + process $proc$libresoc.v:120040$4763 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119158.5-119158.29" + attribute \src "libresoc.v:120041.5-120041.29" switch \initial - attribute \src "libresoc.v:119158.9-119158.17" + attribute \src "libresoc.v:120041.9-120041.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186236,18 +188540,18 @@ module \dec_rc$138 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119176.3-119194.6" - process $proc$libresoc.v:119176$4683 + attribute \src "libresoc.v:120059.3-120077.6" + process $proc$libresoc.v:120059$4764 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119177.5-119177.29" + attribute \src "libresoc.v:120060.5-120060.29" switch \initial - attribute \src "libresoc.v:119177.9-119177.17" + attribute \src "libresoc.v:120060.9-120060.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186268,55 +188572,55 @@ module \dec_rc$138 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119199.1-119252.10" +attribute \src "libresoc.v:120082.1-120135.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" -module \dec_rc$145 - attribute \src "libresoc.v:119200.7-119200.20" +module \dec_rc$148 + attribute \src "libresoc.v:120083.7-120083.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119214.3-119232.6" + attribute \src "libresoc.v:120097.3-120115.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119233.3-119251.6" + attribute \src "libresoc.v:120116.3-120134.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119214.3-119232.6" + attribute \src "libresoc.v:120097.3-120115.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119233.3-119251.6" + attribute \src "libresoc.v:120116.3-120134.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \BRANCH_Rc - attribute \src "libresoc.v:119200.7-119200.15" + attribute \src "libresoc.v:120083.7-120083.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119200.7-119200.20" - process $proc$libresoc.v:119200$4687 + attribute \src "libresoc.v:120083.7-120083.20" + process $proc$libresoc.v:120083$4768 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119214.3-119232.6" - process $proc$libresoc.v:119214$4685 + attribute \src "libresoc.v:120097.3-120115.6" + process $proc$libresoc.v:120097$4766 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119215.5-119215.29" + attribute \src "libresoc.v:120098.5-120098.29" switch \initial - attribute \src "libresoc.v:119215.9-119215.17" + attribute \src "libresoc.v:120098.9-120098.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186336,18 +188640,18 @@ module \dec_rc$145 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119233.3-119251.6" - process $proc$libresoc.v:119233$4686 + attribute \src "libresoc.v:120116.3-120134.6" + process $proc$libresoc.v:120116$4767 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119234.5-119234.29" + attribute \src "libresoc.v:120117.5-120117.29" switch \initial - attribute \src "libresoc.v:119234.9-119234.17" + attribute \src "libresoc.v:120117.9-120117.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186368,55 +188672,55 @@ module \dec_rc$145 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119256.1-119310.10" +attribute \src "libresoc.v:120139.1-120193.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" -module \dec_rc$153 - attribute \src "libresoc.v:119257.7-119257.20" +module \dec_rc$156 + attribute \src "libresoc.v:120140.7-120140.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119272.3-119290.6" + attribute \src "libresoc.v:120155.3-120173.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119291.3-119309.6" + attribute \src "libresoc.v:120174.3-120192.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119272.3-119290.6" + attribute \src "libresoc.v:120155.3-120173.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119291.3-119309.6" + attribute \src "libresoc.v:120174.3-120192.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:119257.7-119257.15" + attribute \src "libresoc.v:120140.7-120140.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119257.7-119257.20" - process $proc$libresoc.v:119257$4690 + attribute \src "libresoc.v:120140.7-120140.20" + process $proc$libresoc.v:120140$4771 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119272.3-119290.6" - process $proc$libresoc.v:119272$4688 + attribute \src "libresoc.v:120155.3-120173.6" + process $proc$libresoc.v:120155$4769 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119273.5-119273.29" + attribute \src "libresoc.v:120156.5-120156.29" switch \initial - attribute \src "libresoc.v:119273.9-119273.17" + attribute \src "libresoc.v:120156.9-120156.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186436,18 +188740,18 @@ module \dec_rc$153 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119291.3-119309.6" - process $proc$libresoc.v:119291$4689 + attribute \src "libresoc.v:120174.3-120192.6" + process $proc$libresoc.v:120174$4770 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119292.5-119292.29" + attribute \src "libresoc.v:120175.5-120175.29" switch \initial - attribute \src "libresoc.v:119292.9-119292.17" + attribute \src "libresoc.v:120175.9-120175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186468,55 +188772,55 @@ module \dec_rc$153 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119314.1-119367.10" +attribute \src "libresoc.v:120197.1-120250.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" -module \dec_rc$162 - attribute \src "libresoc.v:119315.7-119315.20" +module \dec_rc$165 + attribute \src "libresoc.v:120198.7-120198.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119329.3-119347.6" + attribute \src "libresoc.v:120212.3-120230.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119348.3-119366.6" + attribute \src "libresoc.v:120231.3-120249.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119329.3-119347.6" + attribute \src "libresoc.v:120212.3-120230.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119348.3-119366.6" + attribute \src "libresoc.v:120231.3-120249.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 2 \SPR_Rc - attribute \src "libresoc.v:119315.7-119315.15" + attribute \src "libresoc.v:120198.7-120198.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119315.7-119315.20" - process $proc$libresoc.v:119315$4693 + attribute \src "libresoc.v:120198.7-120198.20" + process $proc$libresoc.v:120198$4774 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119329.3-119347.6" - process $proc$libresoc.v:119329$4691 + attribute \src "libresoc.v:120212.3-120230.6" + process $proc$libresoc.v:120212$4772 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119330.5-119330.29" + attribute \src "libresoc.v:120213.5-120213.29" switch \initial - attribute \src "libresoc.v:119330.9-119330.17" + attribute \src "libresoc.v:120213.9-120213.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186536,18 +188840,18 @@ module \dec_rc$162 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119348.3-119366.6" - process $proc$libresoc.v:119348$4692 + attribute \src "libresoc.v:120231.3-120249.6" + process $proc$libresoc.v:120231$4773 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119349.5-119349.29" + attribute \src "libresoc.v:120232.5-120232.29" switch \initial - attribute \src "libresoc.v:119349.9-119349.17" + attribute \src "libresoc.v:120232.9-120232.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186568,55 +188872,55 @@ module \dec_rc$162 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119371.1-119425.10" +attribute \src "libresoc.v:120254.1-120308.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" -module \dec_rc$169 - attribute \src "libresoc.v:119372.7-119372.20" +module \dec_rc$172 + attribute \src "libresoc.v:120255.7-120255.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119387.3-119405.6" + attribute \src "libresoc.v:120270.3-120288.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119406.3-119424.6" + attribute \src "libresoc.v:120289.3-120307.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119387.3-119405.6" + attribute \src "libresoc.v:120270.3-120288.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119406.3-119424.6" + attribute \src "libresoc.v:120289.3-120307.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \DIV_Rc - attribute \src "libresoc.v:119372.7-119372.15" + attribute \src "libresoc.v:120255.7-120255.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119372.7-119372.20" - process $proc$libresoc.v:119372$4696 + attribute \src "libresoc.v:120255.7-120255.20" + process $proc$libresoc.v:120255$4777 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119387.3-119405.6" - process $proc$libresoc.v:119387$4694 + attribute \src "libresoc.v:120270.3-120288.6" + process $proc$libresoc.v:120270$4775 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119388.5-119388.29" + attribute \src "libresoc.v:120271.5-120271.29" switch \initial - attribute \src "libresoc.v:119388.9-119388.17" + attribute \src "libresoc.v:120271.9-120271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186636,18 +188940,18 @@ module \dec_rc$169 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119406.3-119424.6" - process $proc$libresoc.v:119406$4695 + attribute \src "libresoc.v:120289.3-120307.6" + process $proc$libresoc.v:120289$4776 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119407.5-119407.29" + attribute \src "libresoc.v:120290.5-120290.29" switch \initial - attribute \src "libresoc.v:119407.9-119407.17" + attribute \src "libresoc.v:120290.9-120290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186668,55 +188972,55 @@ module \dec_rc$169 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119429.1-119483.10" +attribute \src "libresoc.v:120312.1-120366.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" -module \dec_rc$178 - attribute \src "libresoc.v:119430.7-119430.20" +module \dec_rc$181 + attribute \src "libresoc.v:120313.7-120313.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119445.3-119463.6" + attribute \src "libresoc.v:120328.3-120346.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119464.3-119482.6" + attribute \src "libresoc.v:120347.3-120365.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119445.3-119463.6" + attribute \src "libresoc.v:120328.3-120346.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119464.3-119482.6" + attribute \src "libresoc.v:120347.3-120365.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \MUL_Rc - attribute \src "libresoc.v:119430.7-119430.15" + attribute \src "libresoc.v:120313.7-120313.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119430.7-119430.20" - process $proc$libresoc.v:119430$4699 + attribute \src "libresoc.v:120313.7-120313.20" + process $proc$libresoc.v:120313$4780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119445.3-119463.6" - process $proc$libresoc.v:119445$4697 + attribute \src "libresoc.v:120328.3-120346.6" + process $proc$libresoc.v:120328$4778 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119446.5-119446.29" + attribute \src "libresoc.v:120329.5-120329.29" switch \initial - attribute \src "libresoc.v:119446.9-119446.17" + attribute \src "libresoc.v:120329.9-120329.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186736,18 +189040,18 @@ module \dec_rc$178 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119464.3-119482.6" - process $proc$libresoc.v:119464$4698 + attribute \src "libresoc.v:120347.3-120365.6" + process $proc$libresoc.v:120347$4779 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119465.5-119465.29" + attribute \src "libresoc.v:120348.5-120348.29" switch \initial - attribute \src "libresoc.v:119465.9-119465.17" + attribute \src "libresoc.v:120348.9-120348.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186768,55 +189072,55 @@ module \dec_rc$178 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119487.1-119541.10" +attribute \src "libresoc.v:120370.1-120424.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" -module \dec_rc$186 - attribute \src "libresoc.v:119488.7-119488.20" +module \dec_rc$189 + attribute \src "libresoc.v:120371.7-120371.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119503.3-119521.6" + attribute \src "libresoc.v:120386.3-120404.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119522.3-119540.6" + attribute \src "libresoc.v:120405.3-120423.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119503.3-119521.6" + attribute \src "libresoc.v:120386.3-120404.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119522.3-119540.6" + attribute \src "libresoc.v:120405.3-120423.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:119488.7-119488.15" + attribute \src "libresoc.v:120371.7-120371.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119488.7-119488.20" - process $proc$libresoc.v:119488$4702 + attribute \src "libresoc.v:120371.7-120371.20" + process $proc$libresoc.v:120371$4783 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119503.3-119521.6" - process $proc$libresoc.v:119503$4700 + attribute \src "libresoc.v:120386.3-120404.6" + process $proc$libresoc.v:120386$4781 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119504.5-119504.29" + attribute \src "libresoc.v:120387.5-120387.29" switch \initial - attribute \src "libresoc.v:119504.9-119504.17" + attribute \src "libresoc.v:120387.9-120387.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186836,18 +189140,18 @@ module \dec_rc$186 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119522.3-119540.6" - process $proc$libresoc.v:119522$4701 + attribute \src "libresoc.v:120405.3-120423.6" + process $proc$libresoc.v:120405$4782 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119523.5-119523.29" + attribute \src "libresoc.v:120406.5-120406.29" switch \initial - attribute \src "libresoc.v:119523.9-119523.17" + attribute \src "libresoc.v:120406.9-120406.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186868,55 +189172,55 @@ module \dec_rc$186 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119545.1-119599.10" +attribute \src "libresoc.v:120428.1-120482.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" -module \dec_rc$194 - attribute \src "libresoc.v:119546.7-119546.20" +module \dec_rc$197 + attribute \src "libresoc.v:120429.7-120429.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119561.3-119579.6" + attribute \src "libresoc.v:120444.3-120462.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119580.3-119598.6" + attribute \src "libresoc.v:120463.3-120481.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119561.3-119579.6" + attribute \src "libresoc.v:120444.3-120462.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119580.3-119598.6" + attribute \src "libresoc.v:120463.3-120481.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \LDST_Rc - attribute \src "libresoc.v:119546.7-119546.15" + attribute \src "libresoc.v:120429.7-120429.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119546.7-119546.20" - process $proc$libresoc.v:119546$4705 + attribute \src "libresoc.v:120429.7-120429.20" + process $proc$libresoc.v:120429$4786 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119561.3-119579.6" - process $proc$libresoc.v:119561$4703 + attribute \src "libresoc.v:120444.3-120462.6" + process $proc$libresoc.v:120444$4784 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119562.5-119562.29" + attribute \src "libresoc.v:120445.5-120445.29" switch \initial - attribute \src "libresoc.v:119562.9-119562.17" + attribute \src "libresoc.v:120445.9-120445.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186936,18 +189240,18 @@ module \dec_rc$194 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119580.3-119598.6" - process $proc$libresoc.v:119580$4704 + attribute \src "libresoc.v:120463.3-120481.6" + process $proc$libresoc.v:120463$4785 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119581.5-119581.29" + attribute \src "libresoc.v:120464.5-120464.29" switch \initial - attribute \src "libresoc.v:119581.9-119581.17" + attribute \src "libresoc.v:120464.9-120464.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -186968,55 +189272,55 @@ module \dec_rc$194 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119603.1-119657.10" +attribute \src "libresoc.v:120486.1-120540.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" -module \dec_rc$203 - attribute \src "libresoc.v:119604.7-119604.20" +module \dec_rc$206 + attribute \src "libresoc.v:120487.7-120487.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119619.3-119637.6" + attribute \src "libresoc.v:120502.3-120520.6" wire $0\rc[0:0] - attribute \src "libresoc.v:119638.3-119656.6" + attribute \src "libresoc.v:120521.3-120539.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119619.3-119637.6" + attribute \src "libresoc.v:120502.3-120520.6" wire $1\rc[0:0] - attribute \src "libresoc.v:119638.3-119656.6" + attribute \src "libresoc.v:120521.3-120539.6" wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" wire input 3 \Rc - attribute \src "libresoc.v:119604.7-119604.15" + attribute \src "libresoc.v:120487.7-120487.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \rc_ok attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119604.7-119604.20" - process $proc$libresoc.v:119604$4708 + attribute \src "libresoc.v:120487.7-120487.20" + process $proc$libresoc.v:120487$4789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119619.3-119637.6" - process $proc$libresoc.v:119619$4706 + attribute \src "libresoc.v:120502.3-120520.6" + process $proc$libresoc.v:120502$4787 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119620.5-119620.29" + attribute \src "libresoc.v:120503.5-120503.29" switch \initial - attribute \src "libresoc.v:119620.9-119620.17" + attribute \src "libresoc.v:120503.9-120503.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187036,18 +189340,18 @@ module \dec_rc$203 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:119638.3-119656.6" - process $proc$libresoc.v:119638$4707 + attribute \src "libresoc.v:120521.3-120539.6" + process $proc$libresoc.v:120521$4788 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:119639.5-119639.29" + attribute \src "libresoc.v:120522.5-120522.29" switch \initial - attribute \src "libresoc.v:119639.9-119639.17" + attribute \src "libresoc.v:120522.9-120522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -187068,539 +189372,539 @@ module \dec_rc$203 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:119661.1-120899.10" +attribute \src "libresoc.v:120544.1-121782.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:120456.3-120457.25" + attribute \src "libresoc.v:121339.3-121340.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4848 - attribute \src "libresoc.v:120428.3-120429.75" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4929 + attribute \src "libresoc.v:121311.3-121312.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 - attribute \src "libresoc.v:120398.3-120399.73" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 + attribute \src "libresoc.v:121281.3-121282.73" wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 - attribute \src "libresoc.v:120400.3-120401.87" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 + attribute \src "libresoc.v:121283.3-121284.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 - attribute \src "libresoc.v:120402.3-120403.83" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 + attribute \src "libresoc.v:121285.3-121286.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4852 - attribute \src "libresoc.v:120416.3-120417.81" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4933 + attribute \src "libresoc.v:121299.3-121300.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4853 - attribute \src "libresoc.v:120430.3-120431.67" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4934 + attribute \src "libresoc.v:121313.3-121314.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4854 - attribute \src "libresoc.v:120396.3-120397.77" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4935 + attribute \src "libresoc.v:121279.3-121280.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$4855 - attribute \src "libresoc.v:120412.3-120413.77" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$4936 + attribute \src "libresoc.v:121295.3-121296.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$4856 - attribute \src "libresoc.v:120418.3-120419.79" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$4937 + attribute \src "libresoc.v:121301.3-121302.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 - attribute \src "libresoc.v:120424.3-120425.75" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 + attribute \src "libresoc.v:121307.3-121308.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$4858 - attribute \src "libresoc.v:120426.3-120427.77" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$4939 + attribute \src "libresoc.v:121309.3-121310.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 - attribute \src "libresoc.v:120408.3-120409.71" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 + attribute \src "libresoc.v:121291.3-121292.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 - attribute \src "libresoc.v:120410.3-120411.71" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 + attribute \src "libresoc.v:121293.3-121294.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$4861 - attribute \src "libresoc.v:120422.3-120423.83" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$4942 + attribute \src "libresoc.v:121305.3-121306.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 - attribute \src "libresoc.v:120406.3-120407.71" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 + attribute \src "libresoc.v:121289.3-121290.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 - attribute \src "libresoc.v:120404.3-120405.71" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 + attribute \src "libresoc.v:121287.3-121288.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 - attribute \src "libresoc.v:120420.3-120421.77" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 + attribute \src "libresoc.v:121303.3-121304.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$4865 - attribute \src "libresoc.v:120414.3-120415.71" + attribute \src "libresoc.v:121526.3-121564.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$4946 + attribute \src "libresoc.v:121297.3-121298.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:120454.3-120455.40" + attribute \src "libresoc.v:121337.3-121338.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:120809.3-120817.6" - wire $0\alu_l_r_alu$next[0:0]$4935 - attribute \src "libresoc.v:120370.3-120371.39" + attribute \src "libresoc.v:121692.3-121700.6" + wire $0\alu_l_r_alu$next[0:0]$5016 + attribute \src "libresoc.v:121253.3-121254.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:120800.3-120808.6" - wire $0\alui_l_r_alui$next[0:0]$4932 - attribute \src "libresoc.v:120372.3-120373.43" + attribute \src "libresoc.v:121683.3-121691.6" + wire $0\alui_l_r_alui$next[0:0]$5013 + attribute \src "libresoc.v:121255.3-121256.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:120682.3-120703.6" - wire width 64 $0\data_r0__o$next[63:0]$4891 - attribute \src "libresoc.v:120392.3-120393.37" + attribute \src "libresoc.v:121565.3-121586.6" + wire width 64 $0\data_r0__o$next[63:0]$4972 + attribute \src "libresoc.v:121275.3-121276.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:120682.3-120703.6" - wire $0\data_r0__o_ok$next[0:0]$4892 - attribute \src "libresoc.v:120394.3-120395.43" + attribute \src "libresoc.v:121565.3-121586.6" + wire $0\data_r0__o_ok$next[0:0]$4973 + attribute \src "libresoc.v:121277.3-121278.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:120704.3-120725.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$4899 - attribute \src "libresoc.v:120388.3-120389.43" + attribute \src "libresoc.v:121587.3-121608.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$4980 + attribute \src "libresoc.v:121271.3-121272.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:120704.3-120725.6" - wire $0\data_r1__cr_a_ok$next[0:0]$4900 - attribute \src "libresoc.v:120390.3-120391.49" + attribute \src "libresoc.v:121587.3-121608.6" + wire $0\data_r1__cr_a_ok$next[0:0]$4981 + attribute \src "libresoc.v:121273.3-121274.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:120726.3-120747.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$4907 - attribute \src "libresoc.v:120384.3-120385.47" + attribute \src "libresoc.v:121609.3-121630.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$4988 + attribute \src "libresoc.v:121267.3-121268.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:120726.3-120747.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$4908 - attribute \src "libresoc.v:120386.3-120387.53" + attribute \src "libresoc.v:121609.3-121630.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$4989 + attribute \src "libresoc.v:121269.3-121270.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:120748.3-120769.6" - wire $0\data_r3__xer_so$next[0:0]$4915 - attribute \src "libresoc.v:120380.3-120381.47" + attribute \src "libresoc.v:121631.3-121652.6" + wire $0\data_r3__xer_so$next[0:0]$4996 + attribute \src "libresoc.v:121263.3-121264.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:120748.3-120769.6" - wire $0\data_r3__xer_so_ok$next[0:0]$4916 - attribute \src "libresoc.v:120382.3-120383.53" + attribute \src "libresoc.v:121631.3-121652.6" + wire $0\data_r3__xer_so_ok$next[0:0]$4997 + attribute \src "libresoc.v:121265.3-121266.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:120818.3-120827.6" + attribute \src "libresoc.v:121701.3-121710.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:120828.3-120837.6" + attribute \src "libresoc.v:121711.3-121720.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:120838.3-120847.6" + attribute \src "libresoc.v:121721.3-121730.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:120848.3-120857.6" + attribute \src "libresoc.v:121731.3-121740.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:119662.7-119662.20" + attribute \src "libresoc.v:120545.7-120545.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120598.3-120606.6" - wire $0\opc_l_r_opc$next[0:0]$4833 - attribute \src "libresoc.v:120440.3-120441.39" + attribute \src "libresoc.v:121481.3-121489.6" + wire $0\opc_l_r_opc$next[0:0]$4914 + attribute \src "libresoc.v:121323.3-121324.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:120589.3-120597.6" - wire $0\opc_l_s_opc$next[0:0]$4830 - attribute \src "libresoc.v:120442.3-120443.39" + attribute \src "libresoc.v:121472.3-121480.6" + wire $0\opc_l_s_opc$next[0:0]$4911 + attribute \src "libresoc.v:121325.3-121326.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:120858.3-120866.6" - wire width 4 $0\prev_wr_go$next[3:0]$4942 - attribute \src "libresoc.v:120452.3-120453.37" + attribute \src "libresoc.v:121741.3-121749.6" + wire width 4 $0\prev_wr_go$next[3:0]$5023 + attribute \src "libresoc.v:121335.3-121336.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:120543.3-120552.6" + attribute \src "libresoc.v:121426.3-121435.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:120634.3-120642.6" - wire width 4 $0\req_l_r_req$next[3:0]$4845 - attribute \src "libresoc.v:120432.3-120433.39" + attribute \src "libresoc.v:121517.3-121525.6" + wire width 4 $0\req_l_r_req$next[3:0]$4926 + attribute \src "libresoc.v:121315.3-121316.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:120625.3-120633.6" - wire width 4 $0\req_l_s_req$next[3:0]$4842 - attribute \src "libresoc.v:120434.3-120435.39" + attribute \src "libresoc.v:121508.3-121516.6" + wire width 4 $0\req_l_s_req$next[3:0]$4923 + attribute \src "libresoc.v:121317.3-121318.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:120562.3-120570.6" - wire $0\rok_l_r_rdok$next[0:0]$4821 - attribute \src "libresoc.v:120448.3-120449.41" + attribute \src "libresoc.v:121445.3-121453.6" + wire $0\rok_l_r_rdok$next[0:0]$4902 + attribute \src "libresoc.v:121331.3-121332.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:120553.3-120561.6" - wire $0\rok_l_s_rdok$next[0:0]$4818 - attribute \src "libresoc.v:120450.3-120451.41" + attribute \src "libresoc.v:121436.3-121444.6" + wire $0\rok_l_s_rdok$next[0:0]$4899 + attribute \src "libresoc.v:121333.3-121334.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:120580.3-120588.6" - wire $0\rst_l_r_rst$next[0:0]$4827 - attribute \src "libresoc.v:120444.3-120445.39" + attribute \src "libresoc.v:121463.3-121471.6" + wire $0\rst_l_r_rst$next[0:0]$4908 + attribute \src "libresoc.v:121327.3-121328.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:120571.3-120579.6" - wire $0\rst_l_s_rst$next[0:0]$4824 - attribute \src "libresoc.v:120446.3-120447.39" + attribute \src "libresoc.v:121454.3-121462.6" + wire $0\rst_l_s_rst$next[0:0]$4905 + attribute \src "libresoc.v:121329.3-121330.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:120616.3-120624.6" - wire width 3 $0\src_l_r_src$next[2:0]$4839 - attribute \src "libresoc.v:120436.3-120437.39" + attribute \src "libresoc.v:121499.3-121507.6" + wire width 3 $0\src_l_r_src$next[2:0]$4920 + attribute \src "libresoc.v:121319.3-121320.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:120607.3-120615.6" - wire width 3 $0\src_l_s_src$next[2:0]$4836 - attribute \src "libresoc.v:120438.3-120439.39" + attribute \src "libresoc.v:121490.3-121498.6" + wire width 3 $0\src_l_s_src$next[2:0]$4917 + attribute \src "libresoc.v:121321.3-121322.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:120770.3-120779.6" - wire width 64 $0\src_r0$next[63:0]$4923 - attribute \src "libresoc.v:120378.3-120379.29" + attribute \src "libresoc.v:121653.3-121662.6" + wire width 64 $0\src_r0$next[63:0]$5004 + attribute \src "libresoc.v:121261.3-121262.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:120780.3-120789.6" - wire width 64 $0\src_r1$next[63:0]$4926 - attribute \src "libresoc.v:120376.3-120377.29" + attribute \src "libresoc.v:121663.3-121672.6" + wire width 64 $0\src_r1$next[63:0]$5007 + attribute \src "libresoc.v:121259.3-121260.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:120790.3-120799.6" - wire $0\src_r2$next[0:0]$4929 - attribute \src "libresoc.v:120374.3-120375.29" + attribute \src "libresoc.v:121673.3-121682.6" + wire $0\src_r2$next[0:0]$5010 + attribute \src "libresoc.v:121257.3-121258.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:119792.7-119792.24" + attribute \src "libresoc.v:120675.7-120675.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4866 - attribute \src "libresoc.v:119802.13-119802.49" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4947 + attribute \src "libresoc.v:120685.13-120685.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 - attribute \src "libresoc.v:119819.14-119819.52" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 + attribute \src "libresoc.v:120702.14-120702.52" wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 - attribute \src "libresoc.v:119823.14-119823.72" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 + attribute \src "libresoc.v:120706.14-120706.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 - attribute \src "libresoc.v:119827.7-119827.47" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 + attribute \src "libresoc.v:120710.7-120710.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 - attribute \src "libresoc.v:119835.13-119835.52" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 + attribute \src "libresoc.v:120718.13-120718.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4871 - attribute \src "libresoc.v:119839.14-119839.47" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4952 + attribute \src "libresoc.v:120722.14-120722.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 - attribute \src "libresoc.v:119917.13-119917.51" + attribute \src "libresoc.v:121526.3-121564.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 + attribute \src "libresoc.v:120800.13-120800.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$4873 - attribute \src "libresoc.v:119921.7-119921.44" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$4954 + attribute \src "libresoc.v:120804.7-120804.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$4874 - attribute \src "libresoc.v:119925.7-119925.45" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$4955 + attribute \src "libresoc.v:120808.7-120808.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 - attribute \src "libresoc.v:119929.7-119929.43" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 + attribute \src "libresoc.v:120812.7-120812.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$4876 - attribute \src "libresoc.v:119933.7-119933.44" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$4957 + attribute \src "libresoc.v:120816.7-120816.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 - attribute \src "libresoc.v:119937.7-119937.41" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 + attribute \src "libresoc.v:120820.7-120820.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 - attribute \src "libresoc.v:119941.7-119941.41" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 + attribute \src "libresoc.v:120824.7-120824.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$4879 - attribute \src "libresoc.v:119945.7-119945.47" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$4960 + attribute \src "libresoc.v:120828.7-120828.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 - attribute \src "libresoc.v:119949.7-119949.41" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 + attribute \src "libresoc.v:120832.7-120832.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 - attribute \src "libresoc.v:119953.7-119953.41" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 + attribute \src "libresoc.v:120836.7-120836.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 - attribute \src "libresoc.v:119957.7-119957.44" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 + attribute \src "libresoc.v:120840.7-120840.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$4883 - attribute \src "libresoc.v:119961.7-119961.41" + attribute \src "libresoc.v:121526.3-121564.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$4964 + attribute \src "libresoc.v:120844.7-120844.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:119987.7-119987.26" + attribute \src "libresoc.v:120870.7-120870.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:120809.3-120817.6" - wire $1\alu_l_r_alu$next[0:0]$4936 - attribute \src "libresoc.v:119995.7-119995.25" + attribute \src "libresoc.v:121692.3-121700.6" + wire $1\alu_l_r_alu$next[0:0]$5017 + attribute \src "libresoc.v:120878.7-120878.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:120800.3-120808.6" - wire $1\alui_l_r_alui$next[0:0]$4933 - attribute \src "libresoc.v:120007.7-120007.27" + attribute \src "libresoc.v:121683.3-121691.6" + wire $1\alui_l_r_alui$next[0:0]$5014 + attribute \src "libresoc.v:120890.7-120890.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:120682.3-120703.6" - wire width 64 $1\data_r0__o$next[63:0]$4893 - attribute \src "libresoc.v:120041.14-120041.47" + attribute \src "libresoc.v:121565.3-121586.6" + wire width 64 $1\data_r0__o$next[63:0]$4974 + attribute \src "libresoc.v:120924.14-120924.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:120682.3-120703.6" - wire $1\data_r0__o_ok$next[0:0]$4894 - attribute \src "libresoc.v:120045.7-120045.27" + attribute \src "libresoc.v:121565.3-121586.6" + wire $1\data_r0__o_ok$next[0:0]$4975 + attribute \src "libresoc.v:120928.7-120928.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:120704.3-120725.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$4901 - attribute \src "libresoc.v:120049.13-120049.33" + attribute \src "libresoc.v:121587.3-121608.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$4982 + attribute \src "libresoc.v:120932.13-120932.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:120704.3-120725.6" - wire $1\data_r1__cr_a_ok$next[0:0]$4902 - attribute \src "libresoc.v:120053.7-120053.30" + attribute \src "libresoc.v:121587.3-121608.6" + wire $1\data_r1__cr_a_ok$next[0:0]$4983 + attribute \src "libresoc.v:120936.7-120936.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:120726.3-120747.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$4909 - attribute \src "libresoc.v:120057.13-120057.35" + attribute \src "libresoc.v:121609.3-121630.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$4990 + attribute \src "libresoc.v:120940.13-120940.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:120726.3-120747.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$4910 - attribute \src "libresoc.v:120061.7-120061.32" + attribute \src "libresoc.v:121609.3-121630.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$4991 + attribute \src "libresoc.v:120944.7-120944.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:120748.3-120769.6" - wire $1\data_r3__xer_so$next[0:0]$4917 - attribute \src "libresoc.v:120065.7-120065.29" + attribute \src "libresoc.v:121631.3-121652.6" + wire $1\data_r3__xer_so$next[0:0]$4998 + attribute \src "libresoc.v:120948.7-120948.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:120748.3-120769.6" - wire $1\data_r3__xer_so_ok$next[0:0]$4918 - attribute \src "libresoc.v:120069.7-120069.32" + attribute \src "libresoc.v:121631.3-121652.6" + wire $1\data_r3__xer_so_ok$next[0:0]$4999 + attribute \src "libresoc.v:120952.7-120952.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:120818.3-120827.6" + attribute \src "libresoc.v:121701.3-121710.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:120828.3-120837.6" + attribute \src "libresoc.v:121711.3-121720.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:120838.3-120847.6" + attribute \src "libresoc.v:121721.3-121730.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:120848.3-120857.6" + attribute \src "libresoc.v:121731.3-121740.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:120598.3-120606.6" - wire $1\opc_l_r_opc$next[0:0]$4834 - attribute \src "libresoc.v:120089.7-120089.25" + attribute \src "libresoc.v:121481.3-121489.6" + wire $1\opc_l_r_opc$next[0:0]$4915 + attribute \src "libresoc.v:120972.7-120972.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:120589.3-120597.6" - wire $1\opc_l_s_opc$next[0:0]$4831 - attribute \src "libresoc.v:120093.7-120093.25" + attribute \src "libresoc.v:121472.3-121480.6" + wire $1\opc_l_s_opc$next[0:0]$4912 + attribute \src "libresoc.v:120976.7-120976.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:120858.3-120866.6" - wire width 4 $1\prev_wr_go$next[3:0]$4943 - attribute \src "libresoc.v:120224.13-120224.30" + attribute \src "libresoc.v:121741.3-121749.6" + wire width 4 $1\prev_wr_go$next[3:0]$5024 + attribute \src "libresoc.v:121107.13-121107.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:120543.3-120552.6" + attribute \src "libresoc.v:121426.3-121435.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:120634.3-120642.6" - wire width 4 $1\req_l_r_req$next[3:0]$4846 - attribute \src "libresoc.v:120232.13-120232.31" + attribute \src "libresoc.v:121517.3-121525.6" + wire width 4 $1\req_l_r_req$next[3:0]$4927 + attribute \src "libresoc.v:121115.13-121115.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:120625.3-120633.6" - wire width 4 $1\req_l_s_req$next[3:0]$4843 - attribute \src "libresoc.v:120236.13-120236.31" + attribute \src "libresoc.v:121508.3-121516.6" + wire width 4 $1\req_l_s_req$next[3:0]$4924 + attribute \src "libresoc.v:121119.13-121119.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:120562.3-120570.6" - wire $1\rok_l_r_rdok$next[0:0]$4822 - attribute \src "libresoc.v:120248.7-120248.26" + attribute \src "libresoc.v:121445.3-121453.6" + wire $1\rok_l_r_rdok$next[0:0]$4903 + attribute \src "libresoc.v:121131.7-121131.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:120553.3-120561.6" - wire $1\rok_l_s_rdok$next[0:0]$4819 - attribute \src "libresoc.v:120252.7-120252.26" + attribute \src "libresoc.v:121436.3-121444.6" + wire $1\rok_l_s_rdok$next[0:0]$4900 + attribute \src "libresoc.v:121135.7-121135.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:120580.3-120588.6" - wire $1\rst_l_r_rst$next[0:0]$4828 - attribute \src "libresoc.v:120256.7-120256.25" + attribute \src "libresoc.v:121463.3-121471.6" + wire $1\rst_l_r_rst$next[0:0]$4909 + attribute \src "libresoc.v:121139.7-121139.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:120571.3-120579.6" - wire $1\rst_l_s_rst$next[0:0]$4825 - attribute \src "libresoc.v:120260.7-120260.25" + attribute \src "libresoc.v:121454.3-121462.6" + wire $1\rst_l_s_rst$next[0:0]$4906 + attribute \src "libresoc.v:121143.7-121143.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:120616.3-120624.6" - wire width 3 $1\src_l_r_src$next[2:0]$4840 - attribute \src "libresoc.v:120274.13-120274.31" + attribute \src "libresoc.v:121499.3-121507.6" + wire width 3 $1\src_l_r_src$next[2:0]$4921 + attribute \src "libresoc.v:121157.13-121157.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:120607.3-120615.6" - wire width 3 $1\src_l_s_src$next[2:0]$4837 - attribute \src "libresoc.v:120278.13-120278.31" + attribute \src "libresoc.v:121490.3-121498.6" + wire width 3 $1\src_l_s_src$next[2:0]$4918 + attribute \src "libresoc.v:121161.13-121161.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:120770.3-120779.6" - wire width 64 $1\src_r0$next[63:0]$4924 - attribute \src "libresoc.v:120286.14-120286.43" + attribute \src "libresoc.v:121653.3-121662.6" + wire width 64 $1\src_r0$next[63:0]$5005 + attribute \src "libresoc.v:121169.14-121169.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:120780.3-120789.6" - wire width 64 $1\src_r1$next[63:0]$4927 - attribute \src "libresoc.v:120290.14-120290.43" + attribute \src "libresoc.v:121663.3-121672.6" + wire width 64 $1\src_r1$next[63:0]$5008 + attribute \src "libresoc.v:121173.14-121173.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:120790.3-120799.6" - wire $1\src_r2$next[0:0]$4930 - attribute \src "libresoc.v:120294.7-120294.20" + attribute \src "libresoc.v:121673.3-121682.6" + wire $1\src_r2$next[0:0]$5011 + attribute \src "libresoc.v:121177.7-121177.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:120643.3-120681.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 - attribute \src "libresoc.v:120643.3-120681.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 - attribute \src "libresoc.v:120643.3-120681.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 - attribute \src "libresoc.v:120643.3-120681.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 - attribute \src "libresoc.v:120643.3-120681.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 - attribute \src "libresoc.v:120643.3-120681.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 - attribute \src "libresoc.v:120682.3-120703.6" - wire width 64 $2\data_r0__o$next[63:0]$4895 - attribute \src "libresoc.v:120682.3-120703.6" - wire $2\data_r0__o_ok$next[0:0]$4896 - attribute \src "libresoc.v:120704.3-120725.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$4903 - attribute \src "libresoc.v:120704.3-120725.6" - wire $2\data_r1__cr_a_ok$next[0:0]$4904 - attribute \src "libresoc.v:120726.3-120747.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$4911 - attribute \src "libresoc.v:120726.3-120747.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$4912 - attribute \src "libresoc.v:120748.3-120769.6" - wire $2\data_r3__xer_so$next[0:0]$4919 - attribute \src "libresoc.v:120748.3-120769.6" - wire $2\data_r3__xer_so_ok$next[0:0]$4920 - attribute \src "libresoc.v:120682.3-120703.6" - wire $3\data_r0__o_ok$next[0:0]$4897 - attribute \src "libresoc.v:120704.3-120725.6" - wire $3\data_r1__cr_a_ok$next[0:0]$4905 - attribute \src "libresoc.v:120726.3-120747.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$4913 - attribute \src "libresoc.v:120748.3-120769.6" - wire $3\data_r3__xer_so_ok$next[0:0]$4921 - attribute \src "libresoc.v:120309.19-120309.133" - wire width 3 $and$libresoc.v:120309$4711_Y - attribute \src "libresoc.v:120311.19-120311.115" - wire width 3 $and$libresoc.v:120311$4713_Y - attribute \src "libresoc.v:120312.18-120312.110" - wire $and$libresoc.v:120312$4714_Y - attribute \src "libresoc.v:120313.19-120313.125" - wire $and$libresoc.v:120313$4715_Y - attribute \src "libresoc.v:120314.19-120314.125" - wire $and$libresoc.v:120314$4716_Y - attribute \src "libresoc.v:120315.19-120315.125" - wire $and$libresoc.v:120315$4717_Y - attribute \src "libresoc.v:120316.19-120316.125" - wire $and$libresoc.v:120316$4718_Y - attribute \src "libresoc.v:120317.19-120317.149" - wire width 4 $and$libresoc.v:120317$4719_Y - attribute \src "libresoc.v:120318.19-120318.121" - wire width 4 $and$libresoc.v:120318$4720_Y - attribute \src "libresoc.v:120319.19-120319.127" - wire $and$libresoc.v:120319$4721_Y - attribute \src "libresoc.v:120320.19-120320.127" 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$and$libresoc.v:120341$4743_Y - attribute \src "libresoc.v:120343.18-120343.126" - wire $and$libresoc.v:120343$4745_Y - attribute \src "libresoc.v:120344.18-120344.126" - wire $and$libresoc.v:120344$4746_Y - attribute \src "libresoc.v:120345.18-120345.117" - wire $and$libresoc.v:120345$4747_Y - attribute \src "libresoc.v:120351.18-120351.130" - wire $and$libresoc.v:120351$4753_Y - attribute \src "libresoc.v:120352.18-120352.124" - wire width 4 $and$libresoc.v:120352$4754_Y - attribute \src "libresoc.v:120354.18-120354.116" - wire $and$libresoc.v:120354$4756_Y - attribute \src "libresoc.v:120355.18-120355.119" - wire $and$libresoc.v:120355$4757_Y - attribute \src "libresoc.v:120356.18-120356.121" - wire $and$libresoc.v:120356$4758_Y - attribute \src "libresoc.v:120357.18-120357.121" - wire $and$libresoc.v:120357$4759_Y - attribute \src "libresoc.v:120367.18-120367.134" - wire $and$libresoc.v:120367$4769_Y - attribute \src "libresoc.v:120368.18-120368.132" - wire $and$libresoc.v:120368$4770_Y - attribute \src "libresoc.v:120369.18-120369.149" - wire width 3 $and$libresoc.v:120369$4771_Y - attribute \src "libresoc.v:120340.18-120340.113" - wire $eq$libresoc.v:120340$4742_Y - attribute \src "libresoc.v:120342.18-120342.119" - wire $eq$libresoc.v:120342$4744_Y - attribute \src "libresoc.v:120307.19-120307.130" - wire $not$libresoc.v:120307$4709_Y - attribute \src "libresoc.v:120308.19-120308.136" - wire $not$libresoc.v:120308$4710_Y - attribute \src "libresoc.v:120310.19-120310.115" - wire width 3 $not$libresoc.v:120310$4712_Y - attribute \src "libresoc.v:120323.18-120323.97" - wire $not$libresoc.v:120323$4725_Y - attribute \src "libresoc.v:120325.18-120325.99" - wire $not$libresoc.v:120325$4727_Y - attribute \src "libresoc.v:120328.18-120328.113" - wire width 4 $not$libresoc.v:120328$4730_Y - attribute \src "libresoc.v:120331.18-120331.106" - wire $not$libresoc.v:120331$4733_Y - attribute \src "libresoc.v:120337.18-120337.120" - wire $not$libresoc.v:120337$4739_Y - attribute \src "libresoc.v:120348.17-120348.113" - wire width 3 $not$libresoc.v:120348$4750_Y - attribute \src "libresoc.v:120336.18-120336.112" - wire $or$libresoc.v:120336$4738_Y - attribute \src "libresoc.v:120346.18-120346.122" - wire $or$libresoc.v:120346$4748_Y - attribute \src "libresoc.v:120347.18-120347.124" - wire $or$libresoc.v:120347$4749_Y - attribute \src "libresoc.v:120349.18-120349.168" - wire width 4 $or$libresoc.v:120349$4751_Y - attribute \src "libresoc.v:120350.18-120350.155" - wire width 3 $or$libresoc.v:120350$4752_Y - attribute \src "libresoc.v:120353.18-120353.120" - wire width 4 $or$libresoc.v:120353$4755_Y - attribute \src "libresoc.v:120359.17-120359.117" - wire width 3 $or$libresoc.v:120359$4761_Y - attribute \src "libresoc.v:120364.17-120364.104" - wire $reduce_and$libresoc.v:120364$4766_Y - attribute \src "libresoc.v:120330.18-120330.106" - wire $reduce_or$libresoc.v:120330$4732_Y - attribute \src "libresoc.v:120334.18-120334.113" - wire $reduce_or$libresoc.v:120334$4736_Y - attribute \src "libresoc.v:120335.18-120335.112" - wire $reduce_or$libresoc.v:120335$4737_Y - attribute \src "libresoc.v:120358.18-120358.158" - wire $ternary$libresoc.v:120358$4760_Y - attribute \src "libresoc.v:120360.18-120360.159" - wire width 64 $ternary$libresoc.v:120360$4762_Y - attribute \src "libresoc.v:120361.18-120361.164" - wire $ternary$libresoc.v:120361$4763_Y - attribute \src "libresoc.v:120362.18-120362.180" - wire width 64 $ternary$libresoc.v:120362$4764_Y - attribute \src "libresoc.v:120363.18-120363.115" - wire width 64 $ternary$libresoc.v:120363$4765_Y - attribute \src "libresoc.v:120365.18-120365.125" - wire width 64 $ternary$libresoc.v:120365$4767_Y - attribute \src "libresoc.v:120366.18-120366.118" - wire $ternary$libresoc.v:120366$4768_Y + attribute \src "libresoc.v:121526.3-121564.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 + attribute \src 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\src "libresoc.v:121197.19-121197.125" + wire $and$libresoc.v:121197$4797_Y + attribute \src "libresoc.v:121198.19-121198.125" + wire $and$libresoc.v:121198$4798_Y + attribute \src "libresoc.v:121199.19-121199.125" + wire $and$libresoc.v:121199$4799_Y + attribute \src "libresoc.v:121200.19-121200.149" + wire width 4 $and$libresoc.v:121200$4800_Y + attribute \src "libresoc.v:121201.19-121201.121" + wire width 4 $and$libresoc.v:121201$4801_Y + attribute \src "libresoc.v:121202.19-121202.127" + wire $and$libresoc.v:121202$4802_Y + attribute \src "libresoc.v:121203.19-121203.127" + wire $and$libresoc.v:121203$4803_Y + attribute \src "libresoc.v:121204.19-121204.127" + wire $and$libresoc.v:121204$4804_Y + attribute \src "libresoc.v:121205.19-121205.127" + wire $and$libresoc.v:121205$4805_Y + attribute \src "libresoc.v:121207.18-121207.98" + wire $and$libresoc.v:121207$4807_Y + attribute \src "libresoc.v:121209.18-121209.100" + wire $and$libresoc.v:121209$4809_Y + attribute \src "libresoc.v:121210.18-121210.160" + wire width 4 $and$libresoc.v:121210$4810_Y + attribute \src "libresoc.v:121212.18-121212.119" + wire width 4 $and$libresoc.v:121212$4812_Y + attribute \src "libresoc.v:121215.17-121215.123" + wire $and$libresoc.v:121215$4815_Y + attribute \src "libresoc.v:121216.18-121216.116" + wire $and$libresoc.v:121216$4816_Y + attribute \src "libresoc.v:121221.18-121221.113" + wire $and$libresoc.v:121221$4821_Y + attribute \src "libresoc.v:121222.18-121222.125" + wire width 4 $and$libresoc.v:121222$4822_Y + attribute \src "libresoc.v:121224.18-121224.112" + wire $and$libresoc.v:121224$4824_Y + attribute \src "libresoc.v:121226.18-121226.126" + wire $and$libresoc.v:121226$4826_Y + attribute \src "libresoc.v:121227.18-121227.126" + wire $and$libresoc.v:121227$4827_Y + attribute \src "libresoc.v:121228.18-121228.117" + wire $and$libresoc.v:121228$4828_Y + attribute \src "libresoc.v:121234.18-121234.130" + wire $and$libresoc.v:121234$4834_Y + attribute \src "libresoc.v:121235.18-121235.124" + wire width 4 $and$libresoc.v:121235$4835_Y + attribute \src "libresoc.v:121237.18-121237.116" + wire $and$libresoc.v:121237$4837_Y + attribute \src "libresoc.v:121238.18-121238.119" + wire $and$libresoc.v:121238$4838_Y + attribute \src "libresoc.v:121239.18-121239.121" + wire $and$libresoc.v:121239$4839_Y + attribute \src "libresoc.v:121240.18-121240.121" + wire $and$libresoc.v:121240$4840_Y + attribute \src "libresoc.v:121250.18-121250.134" + wire $and$libresoc.v:121250$4850_Y + attribute \src "libresoc.v:121251.18-121251.132" + wire $and$libresoc.v:121251$4851_Y + attribute \src "libresoc.v:121252.18-121252.149" + wire width 3 $and$libresoc.v:121252$4852_Y + attribute \src "libresoc.v:121223.18-121223.113" + wire $eq$libresoc.v:121223$4823_Y + attribute \src "libresoc.v:121225.18-121225.119" + wire $eq$libresoc.v:121225$4825_Y + attribute \src "libresoc.v:121190.19-121190.130" + wire $not$libresoc.v:121190$4790_Y + attribute \src "libresoc.v:121191.19-121191.136" + wire $not$libresoc.v:121191$4791_Y + attribute \src "libresoc.v:121193.19-121193.115" + wire width 3 $not$libresoc.v:121193$4793_Y + attribute \src "libresoc.v:121206.18-121206.97" + wire $not$libresoc.v:121206$4806_Y + attribute \src "libresoc.v:121208.18-121208.99" + wire $not$libresoc.v:121208$4808_Y + attribute \src "libresoc.v:121211.18-121211.113" + wire width 4 $not$libresoc.v:121211$4811_Y + attribute \src "libresoc.v:121214.18-121214.106" + wire $not$libresoc.v:121214$4814_Y + attribute \src "libresoc.v:121220.18-121220.120" + wire $not$libresoc.v:121220$4820_Y + attribute \src "libresoc.v:121231.17-121231.113" + wire width 3 $not$libresoc.v:121231$4831_Y + attribute \src "libresoc.v:121219.18-121219.112" + wire $or$libresoc.v:121219$4819_Y + attribute \src "libresoc.v:121229.18-121229.122" + wire $or$libresoc.v:121229$4829_Y + attribute \src "libresoc.v:121230.18-121230.124" + wire $or$libresoc.v:121230$4830_Y + attribute \src "libresoc.v:121232.18-121232.168" + wire width 4 $or$libresoc.v:121232$4832_Y + attribute \src "libresoc.v:121233.18-121233.155" + wire width 3 $or$libresoc.v:121233$4833_Y + attribute \src "libresoc.v:121236.18-121236.120" + wire width 4 $or$libresoc.v:121236$4836_Y + attribute \src "libresoc.v:121242.17-121242.117" + wire width 3 $or$libresoc.v:121242$4842_Y + attribute \src "libresoc.v:121247.17-121247.104" + wire $reduce_and$libresoc.v:121247$4847_Y + attribute \src "libresoc.v:121213.18-121213.106" + wire $reduce_or$libresoc.v:121213$4813_Y + attribute \src "libresoc.v:121217.18-121217.113" + wire $reduce_or$libresoc.v:121217$4817_Y + attribute \src "libresoc.v:121218.18-121218.112" + wire $reduce_or$libresoc.v:121218$4818_Y + attribute \src "libresoc.v:121241.18-121241.158" + wire $ternary$libresoc.v:121241$4841_Y + attribute \src "libresoc.v:121243.18-121243.159" + wire width 64 $ternary$libresoc.v:121243$4843_Y + attribute \src "libresoc.v:121244.18-121244.164" + wire $ternary$libresoc.v:121244$4844_Y + attribute \src "libresoc.v:121245.18-121245.180" + wire width 64 $ternary$libresoc.v:121245$4845_Y + attribute \src "libresoc.v:121246.18-121246.115" + wire width 64 $ternary$libresoc.v:121246$4846_Y + attribute \src "libresoc.v:121248.18-121248.125" + wire width 64 $ternary$libresoc.v:121248$4848_Y + attribute \src "libresoc.v:121249.18-121249.118" + wire $ternary$libresoc.v:121249$4849_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -187737,7 +190041,7 @@ module \div0 wire \all_rd_pulse attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_div0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_div0_logical_op__data_len @@ -187906,7 +190210,7 @@ module \div0 wire \alu_div0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_div0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_div0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_div0_p_ready_o @@ -187916,9 +190220,9 @@ module \div0 wire width 64 \alu_div0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_div0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \alu_div0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_div0_xer_so$1 @@ -187950,32 +190254,32 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 37 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o + wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i + wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 23 \cu_rd__go_i + wire width 3 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 22 \cu_rd__rel_o + wire width 3 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 21 \cu_rdmaskn_i + wire width 3 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 29 \cu_wr__go_i + wire width 4 input 30 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 28 \cu_wr__rel_o + wire width 4 output 29 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 4 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -188011,17 +190315,17 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o + wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o + wire width 4 output 33 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o + wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 36 \dest4_o - attribute \src "libresoc.v:119662.7-119662.15" + wire output 37 \dest4_o + attribute \src "libresoc.v:120545.7-120545.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -188033,7 +190337,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_div0__data_len + wire width 4 input 18 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -188048,19 +190352,19 @@ module \div0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_div0__fn_unit + wire width 12 input 3 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_div0__imm_data__data + wire width 64 input 4 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_div0__imm_data__ok + wire input 5 \oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_div0__input_carry + wire width 2 input 12 \oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_div0__insn + wire width 32 input 19 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -188136,29 +190440,29 @@ module \div0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_div0__insn_type + wire width 7 input 2 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_div0__invert_in + wire input 10 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_div0__invert_out + wire input 13 \oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_div0__is_32bit + wire input 16 \oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_div0__is_signed + wire input 17 \oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_div0__oe__oe + wire input 8 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_div0__oe__ok + wire input 9 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_div0__output_carry + wire input 15 \oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_div0__rc__ok + wire input 7 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_div0__rc__rc + wire input 6 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_div0__write_cr0 + wire input 14 \oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_div0__zero_a + wire input 11 \oper_i_alu_div0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -188202,11 +190506,11 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i + wire width 64 input 25 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i + wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 26 \src3_i + wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -188239,12 +190543,12 @@ module \div0 wire \src_sel$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 35 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:120309$4711 + cell $and $and$libresoc.v:121192$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -188252,10 +190556,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:120309$4711_Y + connect \Y $and$libresoc.v:121192$4792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:120311$4713 + cell $and $and$libresoc.v:121194$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -188263,10 +190567,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:120311$4713_Y + connect \Y $and$libresoc.v:121194$4794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:120312$4714 + cell $and $and$libresoc.v:121195$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188274,10 +190578,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:120312$4714_Y + connect \Y $and$libresoc.v:121195$4795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:120313$4715 + cell $and $and$libresoc.v:121196$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188285,10 +190589,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:120313$4715_Y + connect \Y $and$libresoc.v:121196$4796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:120314$4716 + cell $and $and$libresoc.v:121197$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188296,10 +190600,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:120314$4716_Y + connect \Y $and$libresoc.v:121197$4797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:120315$4717 + cell $and $and$libresoc.v:121198$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188307,10 +190611,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:120315$4717_Y + connect \Y $and$libresoc.v:121198$4798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:120316$4718 + cell $and $and$libresoc.v:121199$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188318,10 +190622,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:120316$4718_Y + connect \Y $and$libresoc.v:121199$4799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:120317$4719 + cell $and $and$libresoc.v:121200$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188329,10 +190633,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:120317$4719_Y + connect \Y $and$libresoc.v:121200$4800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:120318$4720 + cell $and $and$libresoc.v:121201$4801 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188340,10 +190644,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:120318$4720_Y + connect \Y $and$libresoc.v:121201$4801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:120319$4721 + cell $and $and$libresoc.v:121202$4802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188351,10 +190655,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:120319$4721_Y + connect \Y $and$libresoc.v:121202$4802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:120320$4722 + cell $and $and$libresoc.v:121203$4803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188362,10 +190666,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:120320$4722_Y + connect \Y $and$libresoc.v:121203$4803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:120321$4723 + cell $and $and$libresoc.v:121204$4804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188373,10 +190677,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:120321$4723_Y + connect \Y $and$libresoc.v:121204$4804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:120322$4724 + cell $and $and$libresoc.v:121205$4805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188384,10 +190688,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:120322$4724_Y + connect \Y $and$libresoc.v:121205$4805_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:120324$4726 + cell $and $and$libresoc.v:121207$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188395,10 +190699,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:120324$4726_Y + connect \Y $and$libresoc.v:121207$4807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:120326$4728 + cell $and $and$libresoc.v:121209$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188406,10 +190710,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:120326$4728_Y + connect \Y $and$libresoc.v:121209$4809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:120327$4729 + cell $and $and$libresoc.v:121210$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188417,10 +190721,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:120327$4729_Y + connect \Y $and$libresoc.v:121210$4810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:120329$4731 + cell $and $and$libresoc.v:121212$4812 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188428,10 +190732,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:120329$4731_Y + connect \Y $and$libresoc.v:121212$4812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:120332$4734 + cell $and $and$libresoc.v:121215$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188439,10 +190743,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:120332$4734_Y + connect \Y $and$libresoc.v:121215$4815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:120333$4735 + cell $and $and$libresoc.v:121216$4816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188450,10 +190754,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:120333$4735_Y + connect \Y $and$libresoc.v:121216$4816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:120338$4740 + cell $and $and$libresoc.v:121221$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188461,10 +190765,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:120338$4740_Y + connect \Y $and$libresoc.v:121221$4821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:120339$4741 + cell $and $and$libresoc.v:121222$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188472,10 +190776,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:120339$4741_Y + connect \Y $and$libresoc.v:121222$4822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:120341$4743 + cell $and $and$libresoc.v:121224$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188483,10 +190787,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:120341$4743_Y + connect \Y $and$libresoc.v:121224$4824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:120343$4745 + cell $and $and$libresoc.v:121226$4826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188494,10 +190798,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:120343$4745_Y + connect \Y $and$libresoc.v:121226$4826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:120344$4746 + cell $and $and$libresoc.v:121227$4827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188505,10 +190809,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:120344$4746_Y + connect \Y $and$libresoc.v:121227$4827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:120345$4747 + cell $and $and$libresoc.v:121228$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188516,10 +190820,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:120345$4747_Y + connect \Y $and$libresoc.v:121228$4828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:120351$4753 + cell $and $and$libresoc.v:121234$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188527,10 +190831,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:120351$4753_Y + connect \Y $and$libresoc.v:121234$4834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:120352$4754 + cell $and $and$libresoc.v:121235$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188538,10 +190842,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:120352$4754_Y + connect \Y $and$libresoc.v:121235$4835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:120354$4756 + cell $and $and$libresoc.v:121237$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188549,10 +190853,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:120354$4756_Y + connect \Y $and$libresoc.v:121237$4837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:120355$4757 + cell $and $and$libresoc.v:121238$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188560,10 +190864,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:120355$4757_Y + connect \Y $and$libresoc.v:121238$4838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:120356$4758 + cell $and $and$libresoc.v:121239$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188571,10 +190875,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:120356$4758_Y + connect \Y $and$libresoc.v:121239$4839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:120357$4759 + cell $and $and$libresoc.v:121240$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188582,10 +190886,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:120357$4759_Y + connect \Y $and$libresoc.v:121240$4840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:120367$4769 + cell $and $and$libresoc.v:121250$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188593,10 +190897,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:120367$4769_Y + connect \Y $and$libresoc.v:121250$4850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:120368$4770 + cell $and $and$libresoc.v:121251$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188604,10 +190908,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:120368$4770_Y + connect \Y $and$libresoc.v:121251$4851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:120369$4771 + cell $and $and$libresoc.v:121252$4852 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -188615,10 +190919,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:120369$4771_Y + connect \Y $and$libresoc.v:121252$4852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:120340$4742 + cell $eq $eq$libresoc.v:121223$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188626,10 +190930,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:120340$4742_Y + connect \Y $eq$libresoc.v:121223$4823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:120342$4744 + cell $eq $eq$libresoc.v:121225$4825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188637,82 +190941,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:120342$4744_Y + connect \Y $eq$libresoc.v:121225$4825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:120307$4709 + cell $not $not$libresoc.v:121190$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:120307$4709_Y + connect \Y $not$libresoc.v:121190$4790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:120308$4710 + cell $not $not$libresoc.v:121191$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:120308$4710_Y + connect \Y $not$libresoc.v:121191$4791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:120310$4712 + cell $not $not$libresoc.v:121193$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:120310$4712_Y + connect \Y $not$libresoc.v:121193$4793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:120323$4725 + cell $not $not$libresoc.v:121206$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:120323$4725_Y + connect \Y $not$libresoc.v:121206$4806_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:120325$4727 + cell $not $not$libresoc.v:121208$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:120325$4727_Y + connect \Y $not$libresoc.v:121208$4808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:120328$4730 + cell $not $not$libresoc.v:121211$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:120328$4730_Y + connect \Y $not$libresoc.v:121211$4811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:120331$4733 + cell $not $not$libresoc.v:121214$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:120331$4733_Y + connect \Y $not$libresoc.v:121214$4814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:120337$4739 + cell $not $not$libresoc.v:121220$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:120337$4739_Y + connect \Y $not$libresoc.v:121220$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:120348$4750 + cell $not $not$libresoc.v:121231$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:120348$4750_Y + connect \Y $not$libresoc.v:121231$4831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:120336$4738 + cell $or $or$libresoc.v:121219$4819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188720,10 +191024,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:120336$4738_Y + connect \Y $or$libresoc.v:121219$4819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:120346$4748 + cell $or $or$libresoc.v:121229$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188731,10 +191035,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:120346$4748_Y + connect \Y $or$libresoc.v:121229$4829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:120347$4749 + cell $or $or$libresoc.v:121230$4830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188742,10 +191046,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:120347$4749_Y + connect \Y $or$libresoc.v:121230$4830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:120349$4751 + cell $or $or$libresoc.v:121232$4832 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188753,10 +191057,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:120349$4751_Y + connect \Y $or$libresoc.v:121232$4832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:120350$4752 + cell $or $or$libresoc.v:121233$4833 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -188764,10 +191068,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:120350$4752_Y + connect \Y $or$libresoc.v:121233$4833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:120353$4755 + cell $or $or$libresoc.v:121236$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -188775,10 +191079,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:120353$4755_Y + connect \Y $or$libresoc.v:121236$4836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:120359$4761 + cell $or $or$libresoc.v:121242$4842 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -188786,98 +191090,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:120359$4761_Y + connect \Y $or$libresoc.v:121242$4842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:120364$4766 + cell $reduce_and $reduce_and$libresoc.v:121247$4847 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:120364$4766_Y + connect \Y $reduce_and$libresoc.v:121247$4847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:120330$4732 + cell $reduce_or $reduce_or$libresoc.v:121213$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:120330$4732_Y + connect \Y $reduce_or$libresoc.v:121213$4813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:120334$4736 + cell $reduce_or $reduce_or$libresoc.v:121217$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:120334$4736_Y + connect \Y $reduce_or$libresoc.v:121217$4817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:120335$4737 + cell $reduce_or $reduce_or$libresoc.v:121218$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:120335$4737_Y + connect \Y $reduce_or$libresoc.v:121218$4818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:120358$4760 + cell $mux $ternary$libresoc.v:121241$4841 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:120358$4760_Y + connect \Y $ternary$libresoc.v:121241$4841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:120360$4762 + cell $mux $ternary$libresoc.v:121243$4843 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:120360$4762_Y + connect \Y $ternary$libresoc.v:121243$4843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:120361$4763 + cell $mux $ternary$libresoc.v:121244$4844 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:120361$4763_Y + connect \Y $ternary$libresoc.v:121244$4844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:120362$4764 + cell $mux $ternary$libresoc.v:121245$4845 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:120362$4764_Y + connect \Y $ternary$libresoc.v:121245$4845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:120363$4765 + cell $mux $ternary$libresoc.v:121246$4846 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:120363$4765_Y + connect \Y $ternary$libresoc.v:121246$4846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:120365$4767 + cell $mux $ternary$libresoc.v:121248$4848 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:120365$4767_Y + connect \Y $ternary$libresoc.v:121248$4848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:120366$4768 + cell $mux $ternary$libresoc.v:121249$4849 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:120366$4768_Y + connect \Y $ternary$libresoc.v:121249$4849_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120458.12-120494.4" + attribute \src "libresoc.v:121341.12-121377.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -188916,8 +191220,8 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:120495.14-120501.4" - cell \alu_l$87 \alu_l + attribute \src "libresoc.v:121378.14-121384.4" + cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -188925,8 +191229,8 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:120502.15-120508.4" - cell \alui_l$86 \alui_l + attribute \src "libresoc.v:121385.15-121391.4" + cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -188934,8 +191238,8 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:120509.14-120515.4" - cell \opc_l$82 \opc_l + attribute \src "libresoc.v:121392.14-121398.4" + cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -188943,8 +191247,8 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:120516.14-120522.4" - cell \req_l$83 \req_l + attribute \src "libresoc.v:121399.14-121405.4" + cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -188952,8 +191256,8 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:120523.14-120529.4" - cell \rok_l$85 \rok_l + attribute \src "libresoc.v:121406.14-121412.4" + cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -188961,698 +191265,698 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:120530.14-120535.4" - cell \rst_l$84 \rst_l + attribute \src "libresoc.v:121413.14-121418.4" + cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:120536.14-120542.4" - cell \src_l$81 \src_l + attribute \src "libresoc.v:121419.14-121425.4" + cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:119662.7-119662.20" - process $proc$libresoc.v:119662$4944 + attribute \src "libresoc.v:120545.7-120545.20" + process $proc$libresoc.v:120545$5025 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119792.7-119792.24" - process $proc$libresoc.v:119792$4945 + attribute \src "libresoc.v:120675.7-120675.24" + process $proc$libresoc.v:120675$5026 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:119802.13-119802.49" - process $proc$libresoc.v:119802$4946 + attribute \src "libresoc.v:120685.13-120685.49" + process $proc$libresoc.v:120685$5027 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:119819.14-119819.52" - process $proc$libresoc.v:119819$4947 + attribute \src "libresoc.v:120702.14-120702.52" + process $proc$libresoc.v:120702$5028 assign { } { } assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:119823.14-119823.72" - process $proc$libresoc.v:119823$4948 + attribute \src "libresoc.v:120706.14-120706.72" + process $proc$libresoc.v:120706$5029 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:119827.7-119827.47" - process $proc$libresoc.v:119827$4949 + attribute \src "libresoc.v:120710.7-120710.47" + process $proc$libresoc.v:120710$5030 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:119835.13-119835.52" - process $proc$libresoc.v:119835$4950 + attribute \src "libresoc.v:120718.13-120718.52" + process $proc$libresoc.v:120718$5031 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:119839.14-119839.47" - process $proc$libresoc.v:119839$4951 + attribute \src "libresoc.v:120722.14-120722.47" + process $proc$libresoc.v:120722$5032 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:119917.13-119917.51" - process $proc$libresoc.v:119917$4952 + attribute \src "libresoc.v:120800.13-120800.51" + process $proc$libresoc.v:120800$5033 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:119921.7-119921.44" - process $proc$libresoc.v:119921$4953 + attribute \src "libresoc.v:120804.7-120804.44" + process $proc$libresoc.v:120804$5034 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:119925.7-119925.45" - process $proc$libresoc.v:119925$4954 + attribute \src "libresoc.v:120808.7-120808.45" + process $proc$libresoc.v:120808$5035 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:119929.7-119929.43" - process $proc$libresoc.v:119929$4955 + attribute \src "libresoc.v:120812.7-120812.43" + process $proc$libresoc.v:120812$5036 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:119933.7-119933.44" - process $proc$libresoc.v:119933$4956 + attribute \src "libresoc.v:120816.7-120816.44" + process $proc$libresoc.v:120816$5037 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:119937.7-119937.41" - process $proc$libresoc.v:119937$4957 + attribute \src "libresoc.v:120820.7-120820.41" + process $proc$libresoc.v:120820$5038 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:119941.7-119941.41" - process $proc$libresoc.v:119941$4958 + attribute \src "libresoc.v:120824.7-120824.41" + process $proc$libresoc.v:120824$5039 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:119945.7-119945.47" - process $proc$libresoc.v:119945$4959 + attribute \src "libresoc.v:120828.7-120828.47" + process $proc$libresoc.v:120828$5040 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:119949.7-119949.41" - process $proc$libresoc.v:119949$4960 + attribute \src "libresoc.v:120832.7-120832.41" + process $proc$libresoc.v:120832$5041 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:119953.7-119953.41" - process $proc$libresoc.v:119953$4961 + attribute \src "libresoc.v:120836.7-120836.41" + process $proc$libresoc.v:120836$5042 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:119957.7-119957.44" - process $proc$libresoc.v:119957$4962 + attribute \src "libresoc.v:120840.7-120840.44" + process $proc$libresoc.v:120840$5043 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:119961.7-119961.41" - process $proc$libresoc.v:119961$4963 + attribute \src "libresoc.v:120844.7-120844.41" + process $proc$libresoc.v:120844$5044 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:119987.7-119987.26" - process $proc$libresoc.v:119987$4964 + attribute \src "libresoc.v:120870.7-120870.26" + process $proc$libresoc.v:120870$5045 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:119995.7-119995.25" - process $proc$libresoc.v:119995$4965 + attribute \src "libresoc.v:120878.7-120878.25" + process $proc$libresoc.v:120878$5046 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:120007.7-120007.27" - process $proc$libresoc.v:120007$4966 + attribute \src "libresoc.v:120890.7-120890.27" + process $proc$libresoc.v:120890$5047 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:120041.14-120041.47" - process $proc$libresoc.v:120041$4967 + attribute \src "libresoc.v:120924.14-120924.47" + process $proc$libresoc.v:120924$5048 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:120045.7-120045.27" - process $proc$libresoc.v:120045$4968 + attribute \src "libresoc.v:120928.7-120928.27" + process $proc$libresoc.v:120928$5049 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:120049.13-120049.33" - process $proc$libresoc.v:120049$4969 + attribute \src "libresoc.v:120932.13-120932.33" + process $proc$libresoc.v:120932$5050 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:120053.7-120053.30" - process $proc$libresoc.v:120053$4970 + attribute \src "libresoc.v:120936.7-120936.30" + process $proc$libresoc.v:120936$5051 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:120057.13-120057.35" - process $proc$libresoc.v:120057$4971 + attribute \src "libresoc.v:120940.13-120940.35" + process $proc$libresoc.v:120940$5052 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:120061.7-120061.32" - process $proc$libresoc.v:120061$4972 + attribute \src "libresoc.v:120944.7-120944.32" + process $proc$libresoc.v:120944$5053 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:120065.7-120065.29" - process $proc$libresoc.v:120065$4973 + attribute \src "libresoc.v:120948.7-120948.29" + process $proc$libresoc.v:120948$5054 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:120069.7-120069.32" - process $proc$libresoc.v:120069$4974 + attribute \src "libresoc.v:120952.7-120952.32" + process $proc$libresoc.v:120952$5055 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:120089.7-120089.25" - process $proc$libresoc.v:120089$4975 + attribute \src "libresoc.v:120972.7-120972.25" + process $proc$libresoc.v:120972$5056 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:120093.7-120093.25" - process $proc$libresoc.v:120093$4976 + attribute \src "libresoc.v:120976.7-120976.25" + process $proc$libresoc.v:120976$5057 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:120224.13-120224.30" - process $proc$libresoc.v:120224$4977 + attribute \src "libresoc.v:121107.13-121107.30" + process $proc$libresoc.v:121107$5058 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:120232.13-120232.31" - process $proc$libresoc.v:120232$4978 + attribute \src "libresoc.v:121115.13-121115.31" + process $proc$libresoc.v:121115$5059 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:120236.13-120236.31" - process $proc$libresoc.v:120236$4979 + attribute \src "libresoc.v:121119.13-121119.31" + process $proc$libresoc.v:121119$5060 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:120248.7-120248.26" - process $proc$libresoc.v:120248$4980 + attribute \src "libresoc.v:121131.7-121131.26" + process $proc$libresoc.v:121131$5061 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:120252.7-120252.26" - process $proc$libresoc.v:120252$4981 + attribute \src "libresoc.v:121135.7-121135.26" + process $proc$libresoc.v:121135$5062 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:120256.7-120256.25" - process $proc$libresoc.v:120256$4982 + attribute \src "libresoc.v:121139.7-121139.25" + process $proc$libresoc.v:121139$5063 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:120260.7-120260.25" - process $proc$libresoc.v:120260$4983 + attribute \src "libresoc.v:121143.7-121143.25" + process $proc$libresoc.v:121143$5064 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:120274.13-120274.31" - process $proc$libresoc.v:120274$4984 + attribute \src "libresoc.v:121157.13-121157.31" + process $proc$libresoc.v:121157$5065 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:120278.13-120278.31" - process $proc$libresoc.v:120278$4985 + attribute \src "libresoc.v:121161.13-121161.31" + process $proc$libresoc.v:121161$5066 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:120286.14-120286.43" - process $proc$libresoc.v:120286$4986 + attribute \src "libresoc.v:121169.14-121169.43" + process $proc$libresoc.v:121169$5067 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:120290.14-120290.43" - process $proc$libresoc.v:120290$4987 + attribute \src "libresoc.v:121173.14-121173.43" + process $proc$libresoc.v:121173$5068 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:120294.7-120294.20" - process $proc$libresoc.v:120294$4988 + attribute \src "libresoc.v:121177.7-121177.20" + process $proc$libresoc.v:121177$5069 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:120370.3-120371.39" - process $proc$libresoc.v:120370$4772 + attribute \src "libresoc.v:121253.3-121254.39" + process $proc$libresoc.v:121253$4853 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:120372.3-120373.43" - process $proc$libresoc.v:120372$4773 + attribute \src "libresoc.v:121255.3-121256.43" + process $proc$libresoc.v:121255$4854 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:120374.3-120375.29" - process $proc$libresoc.v:120374$4774 + attribute \src "libresoc.v:121257.3-121258.29" + process $proc$libresoc.v:121257$4855 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:120376.3-120377.29" - process $proc$libresoc.v:120376$4775 + attribute \src "libresoc.v:121259.3-121260.29" + process $proc$libresoc.v:121259$4856 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:120378.3-120379.29" - process $proc$libresoc.v:120378$4776 + attribute \src "libresoc.v:121261.3-121262.29" + process $proc$libresoc.v:121261$4857 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:120380.3-120381.47" - process $proc$libresoc.v:120380$4777 + attribute \src "libresoc.v:121263.3-121264.47" + process $proc$libresoc.v:121263$4858 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:120382.3-120383.53" - process $proc$libresoc.v:120382$4778 + attribute \src "libresoc.v:121265.3-121266.53" + process $proc$libresoc.v:121265$4859 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:120384.3-120385.47" - process $proc$libresoc.v:120384$4779 + attribute \src "libresoc.v:121267.3-121268.47" + process $proc$libresoc.v:121267$4860 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:120386.3-120387.53" - process $proc$libresoc.v:120386$4780 + attribute \src "libresoc.v:121269.3-121270.53" + process $proc$libresoc.v:121269$4861 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:120388.3-120389.43" - process $proc$libresoc.v:120388$4781 + attribute \src "libresoc.v:121271.3-121272.43" + process $proc$libresoc.v:121271$4862 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:120390.3-120391.49" - process $proc$libresoc.v:120390$4782 + attribute \src "libresoc.v:121273.3-121274.49" + process $proc$libresoc.v:121273$4863 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:120392.3-120393.37" - process $proc$libresoc.v:120392$4783 + attribute \src "libresoc.v:121275.3-121276.37" + process $proc$libresoc.v:121275$4864 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:120394.3-120395.43" - process $proc$libresoc.v:120394$4784 + attribute \src "libresoc.v:121277.3-121278.43" + process $proc$libresoc.v:121277$4865 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:120396.3-120397.77" - process $proc$libresoc.v:120396$4785 + attribute \src "libresoc.v:121279.3-121280.77" + process $proc$libresoc.v:121279$4866 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:120398.3-120399.73" - process $proc$libresoc.v:120398$4786 + attribute \src "libresoc.v:121281.3-121282.73" + process $proc$libresoc.v:121281$4867 assign { } { } assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:120400.3-120401.87" - process $proc$libresoc.v:120400$4787 + attribute \src "libresoc.v:121283.3-121284.87" + process $proc$libresoc.v:121283$4868 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:120402.3-120403.83" - process $proc$libresoc.v:120402$4788 + attribute \src "libresoc.v:121285.3-121286.83" + process $proc$libresoc.v:121285$4869 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:120404.3-120405.71" - process $proc$libresoc.v:120404$4789 + attribute \src "libresoc.v:121287.3-121288.71" + process $proc$libresoc.v:121287$4870 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:120406.3-120407.71" - process $proc$libresoc.v:120406$4790 + attribute \src "libresoc.v:121289.3-121290.71" + process $proc$libresoc.v:121289$4871 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:120408.3-120409.71" - process $proc$libresoc.v:120408$4791 + attribute \src "libresoc.v:121291.3-121292.71" + process $proc$libresoc.v:121291$4872 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:120410.3-120411.71" - process $proc$libresoc.v:120410$4792 + attribute \src "libresoc.v:121293.3-121294.71" + process $proc$libresoc.v:121293$4873 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:120412.3-120413.77" - process $proc$libresoc.v:120412$4793 + attribute \src "libresoc.v:121295.3-121296.77" + process $proc$libresoc.v:121295$4874 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:120414.3-120415.71" - process $proc$libresoc.v:120414$4794 + attribute \src "libresoc.v:121297.3-121298.71" + process $proc$libresoc.v:121297$4875 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:120416.3-120417.81" - process $proc$libresoc.v:120416$4795 + attribute \src "libresoc.v:121299.3-121300.81" + process $proc$libresoc.v:121299$4876 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:120418.3-120419.79" - process $proc$libresoc.v:120418$4796 + attribute \src "libresoc.v:121301.3-121302.79" + process $proc$libresoc.v:121301$4877 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:120420.3-120421.77" - process $proc$libresoc.v:120420$4797 + attribute \src "libresoc.v:121303.3-121304.77" + process $proc$libresoc.v:121303$4878 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:120422.3-120423.83" - process $proc$libresoc.v:120422$4798 + attribute \src "libresoc.v:121305.3-121306.83" + process $proc$libresoc.v:121305$4879 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:120424.3-120425.75" - process $proc$libresoc.v:120424$4799 + attribute \src "libresoc.v:121307.3-121308.75" + process $proc$libresoc.v:121307$4880 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:120426.3-120427.77" - process $proc$libresoc.v:120426$4800 + attribute \src "libresoc.v:121309.3-121310.77" + process $proc$libresoc.v:121309$4881 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:120428.3-120429.75" - process $proc$libresoc.v:120428$4801 + attribute \src "libresoc.v:121311.3-121312.75" + process $proc$libresoc.v:121311$4882 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:120430.3-120431.67" - process $proc$libresoc.v:120430$4802 + attribute \src "libresoc.v:121313.3-121314.67" + process $proc$libresoc.v:121313$4883 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:120432.3-120433.39" - process $proc$libresoc.v:120432$4803 + attribute \src "libresoc.v:121315.3-121316.39" + process $proc$libresoc.v:121315$4884 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:120434.3-120435.39" - process $proc$libresoc.v:120434$4804 + attribute \src "libresoc.v:121317.3-121318.39" + process $proc$libresoc.v:121317$4885 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:120436.3-120437.39" - process $proc$libresoc.v:120436$4805 + attribute \src "libresoc.v:121319.3-121320.39" + process $proc$libresoc.v:121319$4886 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:120438.3-120439.39" - process $proc$libresoc.v:120438$4806 + attribute \src "libresoc.v:121321.3-121322.39" + process $proc$libresoc.v:121321$4887 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:120440.3-120441.39" - process $proc$libresoc.v:120440$4807 + attribute \src "libresoc.v:121323.3-121324.39" + process $proc$libresoc.v:121323$4888 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:120442.3-120443.39" - process $proc$libresoc.v:120442$4808 + attribute \src "libresoc.v:121325.3-121326.39" + process $proc$libresoc.v:121325$4889 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:120444.3-120445.39" - process $proc$libresoc.v:120444$4809 + attribute \src "libresoc.v:121327.3-121328.39" + process $proc$libresoc.v:121327$4890 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:120446.3-120447.39" - process $proc$libresoc.v:120446$4810 + attribute \src "libresoc.v:121329.3-121330.39" + process $proc$libresoc.v:121329$4891 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:120448.3-120449.41" - process $proc$libresoc.v:120448$4811 + attribute \src "libresoc.v:121331.3-121332.41" + process $proc$libresoc.v:121331$4892 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:120450.3-120451.41" - process $proc$libresoc.v:120450$4812 + attribute \src "libresoc.v:121333.3-121334.41" + process $proc$libresoc.v:121333$4893 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:120452.3-120453.37" - process $proc$libresoc.v:120452$4813 + attribute \src "libresoc.v:121335.3-121336.37" + process $proc$libresoc.v:121335$4894 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:120454.3-120455.40" - process $proc$libresoc.v:120454$4814 + attribute \src "libresoc.v:121337.3-121338.40" + process $proc$libresoc.v:121337$4895 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:120456.3-120457.25" - process $proc$libresoc.v:120456$4815 + attribute \src "libresoc.v:121339.3-121340.25" + process $proc$libresoc.v:121339$4896 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:120543.3-120552.6" - process $proc$libresoc.v:120543$4816 + attribute \src "libresoc.v:121426.3-121435.6" + process $proc$libresoc.v:121426$4897 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:120544.5-120544.29" + attribute \src "libresoc.v:121427.5-121427.29" switch \initial - attribute \src "libresoc.v:120544.9-120544.17" + attribute \src "libresoc.v:121427.9-121427.17" case 1'1 case end @@ -189668,14 +191972,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:120553.3-120561.6" - process $proc$libresoc.v:120553$4817 + attribute \src "libresoc.v:121436.3-121444.6" + process $proc$libresoc.v:121436$4898 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$4818 $1\rok_l_s_rdok$next[0:0]$4819 - attribute \src "libresoc.v:120554.5-120554.29" + assign $0\rok_l_s_rdok$next[0:0]$4899 $1\rok_l_s_rdok$next[0:0]$4900 + attribute \src "libresoc.v:121437.5-121437.29" switch \initial - attribute \src "libresoc.v:120554.9-120554.17" + attribute \src "libresoc.v:121437.9-121437.17" case 1'1 case end @@ -189684,21 +191988,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$4819 1'0 + assign $1\rok_l_s_rdok$next[0:0]$4900 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$4819 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$4900 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4818 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4899 end - attribute \src "libresoc.v:120562.3-120570.6" - process $proc$libresoc.v:120562$4820 + attribute \src "libresoc.v:121445.3-121453.6" + process $proc$libresoc.v:121445$4901 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$4821 $1\rok_l_r_rdok$next[0:0]$4822 - attribute \src "libresoc.v:120563.5-120563.29" + assign $0\rok_l_r_rdok$next[0:0]$4902 $1\rok_l_r_rdok$next[0:0]$4903 + attribute \src "libresoc.v:121446.5-121446.29" switch \initial - attribute \src "libresoc.v:120563.9-120563.17" + attribute \src "libresoc.v:121446.9-121446.17" case 1'1 case end @@ -189707,21 +192011,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$4822 1'1 + assign $1\rok_l_r_rdok$next[0:0]$4903 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$4822 \$64 + assign $1\rok_l_r_rdok$next[0:0]$4903 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4821 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4902 end - attribute \src "libresoc.v:120571.3-120579.6" - process $proc$libresoc.v:120571$4823 + attribute \src "libresoc.v:121454.3-121462.6" + process $proc$libresoc.v:121454$4904 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$4824 $1\rst_l_s_rst$next[0:0]$4825 - attribute \src "libresoc.v:120572.5-120572.29" + assign $0\rst_l_s_rst$next[0:0]$4905 $1\rst_l_s_rst$next[0:0]$4906 + attribute \src "libresoc.v:121455.5-121455.29" switch \initial - attribute \src "libresoc.v:120572.9-120572.17" + attribute \src "libresoc.v:121455.9-121455.17" case 1'1 case end @@ -189730,21 +192034,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$4825 1'0 + assign $1\rst_l_s_rst$next[0:0]$4906 1'0 case - assign $1\rst_l_s_rst$next[0:0]$4825 \all_rd + assign $1\rst_l_s_rst$next[0:0]$4906 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4824 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4905 end - attribute \src "libresoc.v:120580.3-120588.6" - process $proc$libresoc.v:120580$4826 + attribute \src "libresoc.v:121463.3-121471.6" + process $proc$libresoc.v:121463$4907 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$4827 $1\rst_l_r_rst$next[0:0]$4828 - attribute \src "libresoc.v:120581.5-120581.29" + assign $0\rst_l_r_rst$next[0:0]$4908 $1\rst_l_r_rst$next[0:0]$4909 + attribute \src "libresoc.v:121464.5-121464.29" switch \initial - attribute \src "libresoc.v:120581.9-120581.17" + attribute \src "libresoc.v:121464.9-121464.17" case 1'1 case end @@ -189753,21 +192057,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$4828 1'1 + assign $1\rst_l_r_rst$next[0:0]$4909 1'1 case - assign $1\rst_l_r_rst$next[0:0]$4828 \rst_r + assign $1\rst_l_r_rst$next[0:0]$4909 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4827 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4908 end - attribute \src "libresoc.v:120589.3-120597.6" - process $proc$libresoc.v:120589$4829 + attribute \src "libresoc.v:121472.3-121480.6" + process $proc$libresoc.v:121472$4910 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$4830 $1\opc_l_s_opc$next[0:0]$4831 - attribute \src "libresoc.v:120590.5-120590.29" + assign $0\opc_l_s_opc$next[0:0]$4911 $1\opc_l_s_opc$next[0:0]$4912 + attribute \src "libresoc.v:121473.5-121473.29" switch \initial - attribute \src "libresoc.v:120590.9-120590.17" + attribute \src "libresoc.v:121473.9-121473.17" case 1'1 case end @@ -189776,21 +192080,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$4831 1'0 + assign $1\opc_l_s_opc$next[0:0]$4912 1'0 case - assign $1\opc_l_s_opc$next[0:0]$4831 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$4912 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4830 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4911 end - attribute \src "libresoc.v:120598.3-120606.6" - process $proc$libresoc.v:120598$4832 + attribute \src "libresoc.v:121481.3-121489.6" + process $proc$libresoc.v:121481$4913 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$4833 $1\opc_l_r_opc$next[0:0]$4834 - attribute \src "libresoc.v:120599.5-120599.29" + assign $0\opc_l_r_opc$next[0:0]$4914 $1\opc_l_r_opc$next[0:0]$4915 + attribute \src "libresoc.v:121482.5-121482.29" switch \initial - attribute \src "libresoc.v:120599.9-120599.17" + attribute \src "libresoc.v:121482.9-121482.17" case 1'1 case end @@ -189799,21 +192103,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$4834 1'1 + assign $1\opc_l_r_opc$next[0:0]$4915 1'1 case - assign $1\opc_l_r_opc$next[0:0]$4834 \req_done + assign $1\opc_l_r_opc$next[0:0]$4915 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4833 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4914 end - attribute \src "libresoc.v:120607.3-120615.6" - process $proc$libresoc.v:120607$4835 + attribute \src "libresoc.v:121490.3-121498.6" + process $proc$libresoc.v:121490$4916 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$4836 $1\src_l_s_src$next[2:0]$4837 - attribute \src "libresoc.v:120608.5-120608.29" + assign $0\src_l_s_src$next[2:0]$4917 $1\src_l_s_src$next[2:0]$4918 + attribute \src "libresoc.v:121491.5-121491.29" switch \initial - attribute \src "libresoc.v:120608.9-120608.17" + attribute \src "libresoc.v:121491.9-121491.17" case 1'1 case end @@ -189822,21 +192126,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$4837 3'000 + assign $1\src_l_s_src$next[2:0]$4918 3'000 case - assign $1\src_l_s_src$next[2:0]$4837 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$4918 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4836 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4917 end - attribute \src "libresoc.v:120616.3-120624.6" - process $proc$libresoc.v:120616$4838 + attribute \src "libresoc.v:121499.3-121507.6" + process $proc$libresoc.v:121499$4919 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$4839 $1\src_l_r_src$next[2:0]$4840 - attribute \src "libresoc.v:120617.5-120617.29" + assign $0\src_l_r_src$next[2:0]$4920 $1\src_l_r_src$next[2:0]$4921 + attribute \src "libresoc.v:121500.5-121500.29" switch \initial - attribute \src "libresoc.v:120617.9-120617.17" + attribute \src "libresoc.v:121500.9-121500.17" case 1'1 case end @@ -189845,21 +192149,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$4840 3'111 + assign $1\src_l_r_src$next[2:0]$4921 3'111 case - assign $1\src_l_r_src$next[2:0]$4840 \reset_r + assign $1\src_l_r_src$next[2:0]$4921 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4839 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4920 end - attribute \src "libresoc.v:120625.3-120633.6" - process $proc$libresoc.v:120625$4841 + attribute \src "libresoc.v:121508.3-121516.6" + process $proc$libresoc.v:121508$4922 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$4842 $1\req_l_s_req$next[3:0]$4843 - attribute \src "libresoc.v:120626.5-120626.29" + assign $0\req_l_s_req$next[3:0]$4923 $1\req_l_s_req$next[3:0]$4924 + attribute \src "libresoc.v:121509.5-121509.29" switch \initial - attribute \src "libresoc.v:120626.9-120626.17" + attribute \src "libresoc.v:121509.9-121509.17" case 1'1 case end @@ -189868,21 +192172,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$4843 4'0000 + assign $1\req_l_s_req$next[3:0]$4924 4'0000 case - assign $1\req_l_s_req$next[3:0]$4843 \$66 + assign $1\req_l_s_req$next[3:0]$4924 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4842 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4923 end - attribute \src "libresoc.v:120634.3-120642.6" - process $proc$libresoc.v:120634$4844 + attribute \src "libresoc.v:121517.3-121525.6" + process $proc$libresoc.v:121517$4925 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$4845 $1\req_l_r_req$next[3:0]$4846 - attribute \src "libresoc.v:120635.5-120635.29" + assign $0\req_l_r_req$next[3:0]$4926 $1\req_l_r_req$next[3:0]$4927 + attribute \src "libresoc.v:121518.5-121518.29" switch \initial - attribute \src "libresoc.v:120635.9-120635.17" + attribute \src "libresoc.v:121518.9-121518.17" case 1'1 case end @@ -189891,15 +192195,15 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$4846 4'1111 + assign $1\req_l_r_req$next[3:0]$4927 4'1111 case - assign $1\req_l_r_req$next[3:0]$4846 \$68 + assign $1\req_l_r_req$next[3:0]$4927 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4845 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4926 end - attribute \src "libresoc.v:120643.3-120681.6" - process $proc$libresoc.v:120643$4847 + attribute \src "libresoc.v:121526.3-121564.6" + process $proc$libresoc.v:121526$4928 assign { } { } assign { } { } assign { } { } @@ -189936,33 +192240,33 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$4848 $1\alu_div0_logical_op__data_len$next[3:0]$4866 - assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 + assign $0\alu_div0_logical_op__data_len$next[3:0]$4929 $1\alu_div0_logical_op__data_len$next[3:0]$4947 + assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$4852 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 - assign $0\alu_div0_logical_op__insn$next[31:0]$4853 $1\alu_div0_logical_op__insn$next[31:0]$4871 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$4854 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$4855 $1\alu_div0_logical_op__invert_in$next[0:0]$4873 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$4856 $1\alu_div0_logical_op__invert_out$next[0:0]$4874 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$4858 $1\alu_div0_logical_op__is_signed$next[0:0]$4876 + assign $0\alu_div0_logical_op__input_carry$next[1:0]$4933 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 + assign $0\alu_div0_logical_op__insn$next[31:0]$4934 $1\alu_div0_logical_op__insn$next[31:0]$4952 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$4935 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$4936 $1\alu_div0_logical_op__invert_in$next[0:0]$4954 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$4937 $1\alu_div0_logical_op__invert_out$next[0:0]$4955 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$4939 $1\alu_div0_logical_op__is_signed$next[0:0]$4957 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$4861 $1\alu_div0_logical_op__output_carry$next[0:0]$4879 + assign $0\alu_div0_logical_op__output_carry$next[0:0]$4942 $1\alu_div0_logical_op__output_carry$next[0:0]$4960 assign { } { } assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$4865 $1\alu_div0_logical_op__zero_a$next[0:0]$4883 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 - attribute \src "libresoc.v:120644.5-120644.29" + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$4946 $1\alu_div0_logical_op__zero_a$next[0:0]$4964 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 + attribute \src "libresoc.v:121527.5-121527.29" switch \initial - attribute \src "libresoc.v:120644.9-120644.17" + attribute \src "libresoc.v:121527.9-121527.17" case 1'1 case end @@ -189988,26 +192292,26 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$4871 $1\alu_div0_logical_op__data_len$next[3:0]$4866 $1\alu_div0_logical_op__is_signed$next[0:0]$4876 $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 $1\alu_div0_logical_op__output_carry$next[0:0]$4879 $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 $1\alu_div0_logical_op__invert_out$next[0:0]$4874 $1\alu_div0_logical_op__input_carry$next[1:0]$4870 $1\alu_div0_logical_op__zero_a$next[0:0]$4883 $1\alu_div0_logical_op__invert_in$next[0:0]$4873 $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 $1\alu_div0_logical_op__insn_type$next[6:0]$4872 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + assign { $1\alu_div0_logical_op__insn$next[31:0]$4952 $1\alu_div0_logical_op__data_len$next[3:0]$4947 $1\alu_div0_logical_op__is_signed$next[0:0]$4957 $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 $1\alu_div0_logical_op__output_carry$next[0:0]$4960 $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 $1\alu_div0_logical_op__invert_out$next[0:0]$4955 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 $1\alu_div0_logical_op__zero_a$next[0:0]$4964 $1\alu_div0_logical_op__invert_in$next[0:0]$4954 $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } case - assign $1\alu_div0_logical_op__data_len$next[3:0]$4866 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4867 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$4870 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$4871 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$4872 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$4873 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$4874 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4875 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$4876 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$4879 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4882 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$4883 \alu_div0_logical_op__zero_a + assign $1\alu_div0_logical_op__data_len$next[3:0]$4947 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$4951 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$4952 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$4953 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$4954 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$4955 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$4957 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$4960 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$4964 \alu_div0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -190019,54 +192323,54 @@ module \div0 assign { } { } assign { } { } assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 1'0 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 1'0 case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4884 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4868 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4885 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4869 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4886 $1\alu_div0_logical_op__oe__oe$next[0:0]$4877 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4887 $1\alu_div0_logical_op__oe__ok$next[0:0]$4878 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4888 $1\alu_div0_logical_op__rc__ok$next[0:0]$4880 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4889 $1\alu_div0_logical_op__rc__rc$next[0:0]$4881 + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 end sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4848 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4849 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4850 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4851 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4852 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4853 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4854 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4855 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4856 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4857 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4858 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4859 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4860 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4861 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4862 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4863 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4864 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4865 + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4929 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4933 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4934 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4935 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4936 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4937 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4939 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4942 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4946 end - attribute \src "libresoc.v:120682.3-120703.6" - process $proc$libresoc.v:120682$4890 + attribute \src "libresoc.v:121565.3-121586.6" + process $proc$libresoc.v:121565$4971 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$4891 $2\data_r0__o$next[63:0]$4895 + assign $0\data_r0__o$next[63:0]$4972 $2\data_r0__o$next[63:0]$4976 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$4892 $3\data_r0__o_ok$next[0:0]$4897 - attribute \src "libresoc.v:120683.5-120683.29" + assign $0\data_r0__o_ok$next[0:0]$4973 $3\data_r0__o_ok$next[0:0]$4978 + attribute \src "libresoc.v:121566.5-121566.29" switch \initial - attribute \src "libresoc.v:120683.9-120683.17" + attribute \src "libresoc.v:121566.9-121566.17" case 1'1 case end @@ -190076,10 +192380,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$4894 $1\data_r0__o$next[63:0]$4893 } { \o_ok \alu_div0_o } + assign { $1\data_r0__o_ok$next[0:0]$4975 $1\data_r0__o$next[63:0]$4974 } { \o_ok \alu_div0_o } case - assign $1\data_r0__o$next[63:0]$4893 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$4894 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$4974 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$4975 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -190087,38 +192391,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$4896 $2\data_r0__o$next[63:0]$4895 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$4977 $2\data_r0__o$next[63:0]$4976 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$4895 $1\data_r0__o$next[63:0]$4893 - assign $2\data_r0__o_ok$next[0:0]$4896 $1\data_r0__o_ok$next[0:0]$4894 + assign $2\data_r0__o$next[63:0]$4976 $1\data_r0__o$next[63:0]$4974 + assign $2\data_r0__o_ok$next[0:0]$4977 $1\data_r0__o_ok$next[0:0]$4975 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$4897 1'0 + assign $3\data_r0__o_ok$next[0:0]$4978 1'0 case - assign $3\data_r0__o_ok$next[0:0]$4897 $2\data_r0__o_ok$next[0:0]$4896 + assign $3\data_r0__o_ok$next[0:0]$4978 $2\data_r0__o_ok$next[0:0]$4977 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$4891 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4892 + update \data_r0__o$next $0\data_r0__o$next[63:0]$4972 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4973 end - attribute \src "libresoc.v:120704.3-120725.6" - process $proc$libresoc.v:120704$4898 + attribute \src "libresoc.v:121587.3-121608.6" + process $proc$libresoc.v:121587$4979 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$4899 $2\data_r1__cr_a$next[3:0]$4903 + assign $0\data_r1__cr_a$next[3:0]$4980 $2\data_r1__cr_a$next[3:0]$4984 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$4900 $3\data_r1__cr_a_ok$next[0:0]$4905 - attribute \src "libresoc.v:120705.5-120705.29" + assign $0\data_r1__cr_a_ok$next[0:0]$4981 $3\data_r1__cr_a_ok$next[0:0]$4986 + attribute \src "libresoc.v:121588.5-121588.29" switch \initial - attribute \src "libresoc.v:120705.9-120705.17" + attribute \src "libresoc.v:121588.9-121588.17" case 1'1 case end @@ -190128,10 +192432,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$4902 $1\data_r1__cr_a$next[3:0]$4901 } { \cr_a_ok \alu_div0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$4983 $1\data_r1__cr_a$next[3:0]$4982 } { \cr_a_ok \alu_div0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$4901 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$4902 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$4982 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$4983 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -190139,38 +192443,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$4904 $2\data_r1__cr_a$next[3:0]$4903 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$4985 $2\data_r1__cr_a$next[3:0]$4984 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$4903 $1\data_r1__cr_a$next[3:0]$4901 - assign $2\data_r1__cr_a_ok$next[0:0]$4904 $1\data_r1__cr_a_ok$next[0:0]$4902 + assign $2\data_r1__cr_a$next[3:0]$4984 $1\data_r1__cr_a$next[3:0]$4982 + assign $2\data_r1__cr_a_ok$next[0:0]$4985 $1\data_r1__cr_a_ok$next[0:0]$4983 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$4905 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$4986 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$4905 $2\data_r1__cr_a_ok$next[0:0]$4904 + assign $3\data_r1__cr_a_ok$next[0:0]$4986 $2\data_r1__cr_a_ok$next[0:0]$4985 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4899 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4900 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4980 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4981 end - attribute \src "libresoc.v:120726.3-120747.6" - process $proc$libresoc.v:120726$4906 + attribute \src "libresoc.v:121609.3-121630.6" + process $proc$libresoc.v:121609$4987 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$4907 $2\data_r2__xer_ov$next[1:0]$4911 + assign $0\data_r2__xer_ov$next[1:0]$4988 $2\data_r2__xer_ov$next[1:0]$4992 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$4908 $3\data_r2__xer_ov_ok$next[0:0]$4913 - attribute \src "libresoc.v:120727.5-120727.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$4989 $3\data_r2__xer_ov_ok$next[0:0]$4994 + attribute \src "libresoc.v:121610.5-121610.29" switch \initial - attribute \src "libresoc.v:120727.9-120727.17" + attribute \src "libresoc.v:121610.9-121610.17" case 1'1 case end @@ -190180,10 +192484,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$4910 $1\data_r2__xer_ov$next[1:0]$4909 } { \xer_ov_ok \alu_div0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$4991 $1\data_r2__xer_ov$next[1:0]$4990 } { \xer_ov_ok \alu_div0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$4909 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$4910 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$4990 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$4991 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -190191,38 +192495,38 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$4912 $2\data_r2__xer_ov$next[1:0]$4911 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$4993 $2\data_r2__xer_ov$next[1:0]$4992 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$4911 $1\data_r2__xer_ov$next[1:0]$4909 - assign $2\data_r2__xer_ov_ok$next[0:0]$4912 $1\data_r2__xer_ov_ok$next[0:0]$4910 + assign $2\data_r2__xer_ov$next[1:0]$4992 $1\data_r2__xer_ov$next[1:0]$4990 + assign $2\data_r2__xer_ov_ok$next[0:0]$4993 $1\data_r2__xer_ov_ok$next[0:0]$4991 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$4913 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$4994 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$4913 $2\data_r2__xer_ov_ok$next[0:0]$4912 + assign $3\data_r2__xer_ov_ok$next[0:0]$4994 $2\data_r2__xer_ov_ok$next[0:0]$4993 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4907 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4908 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4988 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4989 end - attribute \src "libresoc.v:120748.3-120769.6" - process $proc$libresoc.v:120748$4914 + attribute \src "libresoc.v:121631.3-121652.6" + process $proc$libresoc.v:121631$4995 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$4915 $2\data_r3__xer_so$next[0:0]$4919 + assign $0\data_r3__xer_so$next[0:0]$4996 $2\data_r3__xer_so$next[0:0]$5000 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$4916 $3\data_r3__xer_so_ok$next[0:0]$4921 - attribute \src "libresoc.v:120749.5-120749.29" + assign $0\data_r3__xer_so_ok$next[0:0]$4997 $3\data_r3__xer_so_ok$next[0:0]$5002 + attribute \src "libresoc.v:121632.5-121632.29" switch \initial - attribute \src "libresoc.v:120749.9-120749.17" + attribute \src "libresoc.v:121632.9-121632.17" case 1'1 case end @@ -190232,10 +192536,10 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$4918 $1\data_r3__xer_so$next[0:0]$4917 } { \xer_so_ok \alu_div0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$4999 $1\data_r3__xer_so$next[0:0]$4998 } { \xer_so_ok \alu_div0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$4917 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$4918 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$4998 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$4999 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -190243,32 +192547,32 @@ module \div0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$4920 $2\data_r3__xer_so$next[0:0]$4919 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$5001 $2\data_r3__xer_so$next[0:0]$5000 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$4919 $1\data_r3__xer_so$next[0:0]$4917 - assign $2\data_r3__xer_so_ok$next[0:0]$4920 $1\data_r3__xer_so_ok$next[0:0]$4918 + assign $2\data_r3__xer_so$next[0:0]$5000 $1\data_r3__xer_so$next[0:0]$4998 + assign $2\data_r3__xer_so_ok$next[0:0]$5001 $1\data_r3__xer_so_ok$next[0:0]$4999 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$4921 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$5002 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$4921 $2\data_r3__xer_so_ok$next[0:0]$4920 + assign $3\data_r3__xer_so_ok$next[0:0]$5002 $2\data_r3__xer_so_ok$next[0:0]$5001 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4915 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4916 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4996 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4997 end - attribute \src "libresoc.v:120770.3-120779.6" - process $proc$libresoc.v:120770$4922 + attribute \src "libresoc.v:121653.3-121662.6" + process $proc$libresoc.v:121653$5003 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$4923 $1\src_r0$next[63:0]$4924 - attribute \src "libresoc.v:120771.5-120771.29" + assign $0\src_r0$next[63:0]$5004 $1\src_r0$next[63:0]$5005 + attribute \src "libresoc.v:121654.5-121654.29" switch \initial - attribute \src "libresoc.v:120771.9-120771.17" + attribute \src "libresoc.v:121654.9-121654.17" case 1'1 case end @@ -190277,21 +192581,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$4924 \src_or_imm + assign $1\src_r0$next[63:0]$5005 \src_or_imm case - assign $1\src_r0$next[63:0]$4924 \src_r0 + assign $1\src_r0$next[63:0]$5005 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$4923 + update \src_r0$next $0\src_r0$next[63:0]$5004 end - attribute \src "libresoc.v:120780.3-120789.6" - process $proc$libresoc.v:120780$4925 + attribute \src "libresoc.v:121663.3-121672.6" + process $proc$libresoc.v:121663$5006 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$4926 $1\src_r1$next[63:0]$4927 - attribute \src "libresoc.v:120781.5-120781.29" + assign $0\src_r1$next[63:0]$5007 $1\src_r1$next[63:0]$5008 + attribute \src "libresoc.v:121664.5-121664.29" switch \initial - attribute \src "libresoc.v:120781.9-120781.17" + attribute \src "libresoc.v:121664.9-121664.17" case 1'1 case end @@ -190300,21 +192604,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$4927 \src_or_imm$85 + assign $1\src_r1$next[63:0]$5008 \src_or_imm$85 case - assign $1\src_r1$next[63:0]$4927 \src_r1 + assign $1\src_r1$next[63:0]$5008 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$4926 + update \src_r1$next $0\src_r1$next[63:0]$5007 end - attribute \src "libresoc.v:120790.3-120799.6" - process $proc$libresoc.v:120790$4928 + attribute \src "libresoc.v:121673.3-121682.6" + process $proc$libresoc.v:121673$5009 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$4929 $1\src_r2$next[0:0]$4930 - attribute \src "libresoc.v:120791.5-120791.29" + assign $0\src_r2$next[0:0]$5010 $1\src_r2$next[0:0]$5011 + attribute \src "libresoc.v:121674.5-121674.29" switch \initial - attribute \src "libresoc.v:120791.9-120791.17" + attribute \src "libresoc.v:121674.9-121674.17" case 1'1 case end @@ -190323,21 +192627,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$4930 \src3_i + assign $1\src_r2$next[0:0]$5011 \src3_i case - assign $1\src_r2$next[0:0]$4930 \src_r2 + assign $1\src_r2$next[0:0]$5011 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$4929 + update \src_r2$next $0\src_r2$next[0:0]$5010 end - attribute \src "libresoc.v:120800.3-120808.6" - process $proc$libresoc.v:120800$4931 + attribute \src "libresoc.v:121683.3-121691.6" + process $proc$libresoc.v:121683$5012 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$4932 $1\alui_l_r_alui$next[0:0]$4933 - attribute \src "libresoc.v:120801.5-120801.29" + assign $0\alui_l_r_alui$next[0:0]$5013 $1\alui_l_r_alui$next[0:0]$5014 + attribute \src "libresoc.v:121684.5-121684.29" switch \initial - attribute \src "libresoc.v:120801.9-120801.17" + attribute \src "libresoc.v:121684.9-121684.17" case 1'1 case end @@ -190346,21 +192650,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$4933 1'1 + assign $1\alui_l_r_alui$next[0:0]$5014 1'1 case - assign $1\alui_l_r_alui$next[0:0]$4933 \$94 + assign $1\alui_l_r_alui$next[0:0]$5014 \$94 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4932 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5013 end - attribute \src "libresoc.v:120809.3-120817.6" - process $proc$libresoc.v:120809$4934 + attribute \src "libresoc.v:121692.3-121700.6" + process $proc$libresoc.v:121692$5015 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$4935 $1\alu_l_r_alu$next[0:0]$4936 - attribute \src "libresoc.v:120810.5-120810.29" + assign $0\alu_l_r_alu$next[0:0]$5016 $1\alu_l_r_alu$next[0:0]$5017 + attribute \src "libresoc.v:121693.5-121693.29" switch \initial - attribute \src "libresoc.v:120810.9-120810.17" + attribute \src "libresoc.v:121693.9-121693.17" case 1'1 case end @@ -190369,21 +192673,21 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$4936 1'1 + assign $1\alu_l_r_alu$next[0:0]$5017 1'1 case - assign $1\alu_l_r_alu$next[0:0]$4936 \$96 + assign $1\alu_l_r_alu$next[0:0]$5017 \$96 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4935 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5016 end - attribute \src "libresoc.v:120818.3-120827.6" - process $proc$libresoc.v:120818$4937 + attribute \src "libresoc.v:121701.3-121710.6" + process $proc$libresoc.v:121701$5018 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:120819.5-120819.29" + attribute \src "libresoc.v:121702.5-121702.29" switch \initial - attribute \src "libresoc.v:120819.9-120819.17" + attribute \src "libresoc.v:121702.9-121702.17" case 1'1 case end @@ -190399,14 +192703,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:120828.3-120837.6" - process $proc$libresoc.v:120828$4938 + attribute \src "libresoc.v:121711.3-121720.6" + process $proc$libresoc.v:121711$5019 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:120829.5-120829.29" + attribute \src "libresoc.v:121712.5-121712.29" switch \initial - attribute \src "libresoc.v:120829.9-120829.17" + attribute \src "libresoc.v:121712.9-121712.17" case 1'1 case end @@ -190422,14 +192726,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:120838.3-120847.6" - process $proc$libresoc.v:120838$4939 + attribute \src "libresoc.v:121721.3-121730.6" + process $proc$libresoc.v:121721$5020 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:120839.5-120839.29" + attribute \src "libresoc.v:121722.5-121722.29" switch \initial - attribute \src "libresoc.v:120839.9-120839.17" + attribute \src "libresoc.v:121722.9-121722.17" case 1'1 case end @@ -190445,14 +192749,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:120848.3-120857.6" - process $proc$libresoc.v:120848$4940 + attribute \src "libresoc.v:121731.3-121740.6" + process $proc$libresoc.v:121731$5021 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:120849.5-120849.29" + attribute \src "libresoc.v:121732.5-121732.29" switch \initial - attribute \src "libresoc.v:120849.9-120849.17" + attribute \src "libresoc.v:121732.9-121732.17" case 1'1 case end @@ -190468,14 +192772,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:120858.3-120866.6" - process $proc$libresoc.v:120858$4941 + attribute \src "libresoc.v:121741.3-121749.6" + process $proc$libresoc.v:121741$5022 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$4942 $1\prev_wr_go$next[3:0]$4943 - attribute \src "libresoc.v:120859.5-120859.29" + assign $0\prev_wr_go$next[3:0]$5023 $1\prev_wr_go$next[3:0]$5024 + attribute \src "libresoc.v:121742.5-121742.29" switch \initial - attribute \src "libresoc.v:120859.9-120859.17" + attribute \src "libresoc.v:121742.9-121742.17" case 1'1 case end @@ -190484,76 +192788,76 @@ module \div0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$4943 4'0000 - case - assign $1\prev_wr_go$next[3:0]$4943 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$4942 - end - connect \$100 $not$libresoc.v:120307$4709_Y - connect \$102 $not$libresoc.v:120308$4710_Y - connect \$104 $and$libresoc.v:120309$4711_Y - connect \$106 $not$libresoc.v:120310$4712_Y - connect \$108 $and$libresoc.v:120311$4713_Y - connect \$10 $and$libresoc.v:120312$4714_Y - connect \$110 $and$libresoc.v:120313$4715_Y - connect \$112 $and$libresoc.v:120314$4716_Y - connect \$114 $and$libresoc.v:120315$4717_Y - connect \$116 $and$libresoc.v:120316$4718_Y - connect \$118 $and$libresoc.v:120317$4719_Y - connect \$120 $and$libresoc.v:120318$4720_Y - connect \$122 $and$libresoc.v:120319$4721_Y - connect \$124 $and$libresoc.v:120320$4722_Y - connect \$126 $and$libresoc.v:120321$4723_Y - connect \$128 $and$libresoc.v:120322$4724_Y - connect \$12 $not$libresoc.v:120323$4725_Y - connect \$14 $and$libresoc.v:120324$4726_Y - connect \$16 $not$libresoc.v:120325$4727_Y - connect \$18 $and$libresoc.v:120326$4728_Y - connect \$20 $and$libresoc.v:120327$4729_Y - connect \$24 $not$libresoc.v:120328$4730_Y - connect \$26 $and$libresoc.v:120329$4731_Y - connect \$23 $reduce_or$libresoc.v:120330$4732_Y - connect \$22 $not$libresoc.v:120331$4733_Y - connect \$2 $and$libresoc.v:120332$4734_Y - connect \$30 $and$libresoc.v:120333$4735_Y - connect \$32 $reduce_or$libresoc.v:120334$4736_Y - connect \$34 $reduce_or$libresoc.v:120335$4737_Y - connect \$36 $or$libresoc.v:120336$4738_Y - connect \$38 $not$libresoc.v:120337$4739_Y - connect \$40 $and$libresoc.v:120338$4740_Y - connect \$42 $and$libresoc.v:120339$4741_Y - connect \$44 $eq$libresoc.v:120340$4742_Y - connect \$46 $and$libresoc.v:120341$4743_Y - connect \$48 $eq$libresoc.v:120342$4744_Y - connect \$50 $and$libresoc.v:120343$4745_Y - connect \$52 $and$libresoc.v:120344$4746_Y - connect \$54 $and$libresoc.v:120345$4747_Y - connect \$56 $or$libresoc.v:120346$4748_Y - connect \$58 $or$libresoc.v:120347$4749_Y - connect \$5 $not$libresoc.v:120348$4750_Y - connect \$60 $or$libresoc.v:120349$4751_Y - connect \$62 $or$libresoc.v:120350$4752_Y - connect \$64 $and$libresoc.v:120351$4753_Y - connect \$66 $and$libresoc.v:120352$4754_Y - connect \$68 $or$libresoc.v:120353$4755_Y - connect \$70 $and$libresoc.v:120354$4756_Y - connect \$72 $and$libresoc.v:120355$4757_Y - connect \$74 $and$libresoc.v:120356$4758_Y - connect \$76 $and$libresoc.v:120357$4759_Y - connect \$78 $ternary$libresoc.v:120358$4760_Y - connect \$7 $or$libresoc.v:120359$4761_Y - connect \$80 $ternary$libresoc.v:120360$4762_Y - connect \$83 $ternary$libresoc.v:120361$4763_Y - connect \$86 $ternary$libresoc.v:120362$4764_Y - connect \$88 $ternary$libresoc.v:120363$4765_Y - connect \$4 $reduce_and$libresoc.v:120364$4766_Y - connect \$90 $ternary$libresoc.v:120365$4767_Y - connect \$92 $ternary$libresoc.v:120366$4768_Y - connect \$94 $and$libresoc.v:120367$4769_Y - connect \$96 $and$libresoc.v:120368$4770_Y - connect \$98 $and$libresoc.v:120369$4771_Y + assign $1\prev_wr_go$next[3:0]$5024 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5024 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5023 + end + connect \$100 $not$libresoc.v:121190$4790_Y + connect \$102 $not$libresoc.v:121191$4791_Y + connect \$104 $and$libresoc.v:121192$4792_Y + connect \$106 $not$libresoc.v:121193$4793_Y + connect \$108 $and$libresoc.v:121194$4794_Y + connect \$10 $and$libresoc.v:121195$4795_Y + connect \$110 $and$libresoc.v:121196$4796_Y + connect \$112 $and$libresoc.v:121197$4797_Y + connect \$114 $and$libresoc.v:121198$4798_Y + connect \$116 $and$libresoc.v:121199$4799_Y + connect \$118 $and$libresoc.v:121200$4800_Y + connect \$120 $and$libresoc.v:121201$4801_Y + connect \$122 $and$libresoc.v:121202$4802_Y + connect \$124 $and$libresoc.v:121203$4803_Y + connect \$126 $and$libresoc.v:121204$4804_Y + connect \$128 $and$libresoc.v:121205$4805_Y + connect \$12 $not$libresoc.v:121206$4806_Y + connect \$14 $and$libresoc.v:121207$4807_Y + connect \$16 $not$libresoc.v:121208$4808_Y + connect \$18 $and$libresoc.v:121209$4809_Y + connect \$20 $and$libresoc.v:121210$4810_Y + connect \$24 $not$libresoc.v:121211$4811_Y + connect \$26 $and$libresoc.v:121212$4812_Y + connect \$23 $reduce_or$libresoc.v:121213$4813_Y + connect \$22 $not$libresoc.v:121214$4814_Y + connect \$2 $and$libresoc.v:121215$4815_Y + connect \$30 $and$libresoc.v:121216$4816_Y + connect \$32 $reduce_or$libresoc.v:121217$4817_Y + connect \$34 $reduce_or$libresoc.v:121218$4818_Y + connect \$36 $or$libresoc.v:121219$4819_Y + connect \$38 $not$libresoc.v:121220$4820_Y + connect \$40 $and$libresoc.v:121221$4821_Y + connect \$42 $and$libresoc.v:121222$4822_Y + connect \$44 $eq$libresoc.v:121223$4823_Y + connect \$46 $and$libresoc.v:121224$4824_Y + connect \$48 $eq$libresoc.v:121225$4825_Y + connect \$50 $and$libresoc.v:121226$4826_Y + connect \$52 $and$libresoc.v:121227$4827_Y + connect \$54 $and$libresoc.v:121228$4828_Y + connect \$56 $or$libresoc.v:121229$4829_Y + connect \$58 $or$libresoc.v:121230$4830_Y + connect \$5 $not$libresoc.v:121231$4831_Y + connect \$60 $or$libresoc.v:121232$4832_Y + connect \$62 $or$libresoc.v:121233$4833_Y + connect \$64 $and$libresoc.v:121234$4834_Y + connect \$66 $and$libresoc.v:121235$4835_Y + connect \$68 $or$libresoc.v:121236$4836_Y + connect \$70 $and$libresoc.v:121237$4837_Y + connect \$72 $and$libresoc.v:121238$4838_Y + connect \$74 $and$libresoc.v:121239$4839_Y + connect \$76 $and$libresoc.v:121240$4840_Y + connect \$78 $ternary$libresoc.v:121241$4841_Y + connect \$7 $or$libresoc.v:121242$4842_Y + connect \$80 $ternary$libresoc.v:121243$4843_Y + connect \$83 $ternary$libresoc.v:121244$4844_Y + connect \$86 $ternary$libresoc.v:121245$4845_Y + connect \$88 $ternary$libresoc.v:121246$4846_Y + connect \$4 $reduce_and$libresoc.v:121247$4847_Y + connect \$90 $ternary$libresoc.v:121248$4848_Y + connect \$92 $ternary$libresoc.v:121249$4849_Y + connect \$94 $and$libresoc.v:121250$4850_Y + connect \$96 $and$libresoc.v:121251$4851_Y + connect \$98 $and$libresoc.v:121252$4852_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -190587,9 +192891,9 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:120903.1-120912.10" +attribute \src "libresoc.v:121786.1-121795.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" module \div_state_init attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" @@ -190601,44 +192905,44 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:120916.1-120998.10" +attribute \src "libresoc.v:121799.1-121881.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:120917.7-120917.20" + attribute \src "libresoc.v:121800.7-121800.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120982.3-120993.6" + attribute \src "libresoc.v:121865.3-121876.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:120970.3-120981.6" + attribute \src "libresoc.v:121853.3-121864.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:120958.3-120969.6" + attribute \src "libresoc.v:121841.3-121852.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:120982.3-120993.6" + attribute \src "libresoc.v:121865.3-121876.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:120970.3-120981.6" + attribute \src "libresoc.v:121853.3-121864.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:120958.3-120969.6" + attribute \src "libresoc.v:121841.3-121852.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:120952.18-120952.106" - wire width 8 $add$libresoc.v:120952$4989_Y - attribute \src "libresoc.v:120953.18-120953.109" - wire $eq$libresoc.v:120953$4990_Y - attribute \src "libresoc.v:120957.17-120957.108" - wire $eq$libresoc.v:120957$4994_Y - attribute \src "libresoc.v:120956.17-120956.101" - wire $not$libresoc.v:120956$4993_Y - attribute \src "libresoc.v:120954.17-120954.101" - wire width 127 $sshl$libresoc.v:120954$4991_Y - attribute \src "libresoc.v:120955.17-120955.109" - wire width 129 $sub$libresoc.v:120955$4992_Y + attribute \src "libresoc.v:121835.18-121835.106" + wire width 8 $add$libresoc.v:121835$5070_Y + attribute \src "libresoc.v:121836.18-121836.109" + wire $ge$libresoc.v:121836$5071_Y + attribute \src "libresoc.v:121840.17-121840.108" + wire $ge$libresoc.v:121840$5075_Y + attribute \src "libresoc.v:121839.17-121839.101" + wire $not$libresoc.v:121839$5074_Y + attribute \src "libresoc.v:121837.17-121837.101" + wire width 127 $sshl$libresoc.v:121837$5072_Y + attribute \src "libresoc.v:121838.17-121838.109" + wire width 129 $sub$libresoc.v:121838$5073_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" wire width 8 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" wire width 8 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 127 \$2 @@ -190646,7 +192950,7 @@ module \div_state_next wire width 129 \$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" wire width 128 \difference @@ -190656,7 +192960,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:120917.7-120917.15" + attribute \src "libresoc.v:121800.7-121800.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -190667,7 +192971,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:120952$4989 + cell $add $add$libresoc.v:121835$5070 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190675,10 +192979,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:120952$4989_Y + connect \Y $add$libresoc.v:121835$5070_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$libresoc.v:120953$4990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:121836$5071 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190686,10 +192990,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $eq$libresoc.v:120953$4990_Y + connect \Y $ge$libresoc.v:121836$5071_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$libresoc.v:120957$4994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:121840$5075 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190697,18 +193001,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $eq$libresoc.v:120957$4994_Y + connect \Y $ge$libresoc.v:121840$5075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:120956$4993 + cell $not $not$libresoc.v:121839$5074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:120956$4993_Y + connect \Y $not$libresoc.v:121839$5074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:120954$4991 + cell $sshl $sshl$libresoc.v:121837$5072 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -190716,10 +193020,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:120954$4991_Y + connect \Y $sshl$libresoc.v:121837$5072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:120955$4992 + cell $sub $sub$libresoc.v:121838$5073 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -190727,23 +193031,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:120955$4992_Y + connect \Y $sub$libresoc.v:121838$5073_Y end - attribute \src "libresoc.v:120917.7-120917.20" - process $proc$libresoc.v:120917$4998 + attribute \src "libresoc.v:121800.7-121800.20" + process $proc$libresoc.v:121800$5079 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120958.3-120969.6" - process $proc$libresoc.v:120958$4995 + attribute \src "libresoc.v:121841.3-121852.6" + process $proc$libresoc.v:121841$5076 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:120959.5-120959.29" + attribute \src "libresoc.v:121842.5-121842.29" switch \initial - attribute \src "libresoc.v:120959.9-120959.17" + attribute \src "libresoc.v:121842.9-121842.17" case 1'1 case end @@ -190761,13 +193065,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:120970.3-120981.6" - process $proc$libresoc.v:120970$4996 + attribute \src "libresoc.v:121853.3-121864.6" + process $proc$libresoc.v:121853$5077 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:120971.5-120971.29" + attribute \src "libresoc.v:121854.5-121854.29" switch \initial - attribute \src "libresoc.v:120971.9-120971.17" + attribute \src "libresoc.v:121854.9-121854.17" case 1'1 case end @@ -190785,13 +193089,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:120982.3-120993.6" - process $proc$libresoc.v:120982$4997 + attribute \src "libresoc.v:121865.3-121876.6" + process $proc$libresoc.v:121865$5078 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:120983.5-120983.29" + attribute \src "libresoc.v:121866.5-121866.29" switch \initial - attribute \src "libresoc.v:120983.9-120983.17" + attribute \src "libresoc.v:121866.9-121866.17" case 1'1 case end @@ -190809,126 +193113,368 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:120952$4989_Y - connect \$13 $eq$libresoc.v:120953$4990_Y - connect \$2 $sshl$libresoc.v:120954$4991_Y - connect \$4 $sub$libresoc.v:120955$4992_Y - connect \$6 $not$libresoc.v:120956$4993_Y - connect \$8 $eq$libresoc.v:120957$4994_Y + connect \$11 $add$libresoc.v:121835$5070_Y + connect \$13 $ge$libresoc.v:121836$5071_Y + connect \$2 $sshl$libresoc.v:121837$5072_Y + connect \$4 $sub$libresoc.v:121838$5073_Y + connect \$6 $not$libresoc.v:121839$5074_Y + connect \$8 $ge$libresoc.v:121840$5075_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:121002.1-121173.10" +attribute \src "libresoc.v:121885.1-122122.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" +attribute \generator "nMigen" +module \dummy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 12 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 26 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 27 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 14 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 25 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 16 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \trap_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 15 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + connect \fast2$14 \fast2 + connect \fast1$13 \fast1 + connect \rb$12 \rb + connect \ra$11 \ra + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:122126.1-122297.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fast" +attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:121097.3-121103.6" - wire width 3 $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 - attribute \src "libresoc.v:121097.3-121103.6" - wire width 64 $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 - attribute \src "libresoc.v:121097.3-121103.6" - wire width 64 $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 - attribute \src "libresoc.v:121097.3-121103.6" - wire width 3 $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 - attribute \src "libresoc.v:121097.3-121103.6" - wire width 64 $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 - attribute \src "libresoc.v:121097.3-121103.6" - wire width 64 $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 - attribute \src "libresoc.v:121097.3-121103.6" + attribute \src "libresoc.v:122221.3-122227.6" + wire width 3 $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 + attribute \src "libresoc.v:122221.3-122227.6" + wire width 64 $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 + attribute \src "libresoc.v:122221.3-122227.6" + wire width 64 $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 + attribute \src "libresoc.v:122221.3-122227.6" + wire width 3 $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 + attribute \src "libresoc.v:122221.3-122227.6" + wire width 64 $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 + attribute \src "libresoc.v:122221.3-122227.6" + wire width 64 $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 + attribute \src "libresoc.v:122221.3-122227.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:121097.3-121103.6" + attribute \src "libresoc.v:122221.3-122227.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:121097.3-121103.6" + attribute \src "libresoc.v:122221.3-122227.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:121003.7-121003.20" + attribute \src "libresoc.v:122127.7-122127.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121154.3-121163.6" + attribute \src "libresoc.v:122278.3-122287.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:121126.3-121134.6" - wire $0\ren_delay$10$next[0:0]$5029 - attribute \src "libresoc.v:121079.3-121080.43" - wire $0\ren_delay$10[0:0]$5012 - attribute \src "libresoc.v:121054.7-121054.28" - wire $0\ren_delay$10[0:0]$5049 - attribute \src "libresoc.v:121145.3-121153.6" - wire $0\ren_delay$11$next[0:0]$5033 - attribute \src "libresoc.v:121077.3-121078.43" - wire $0\ren_delay$11[0:0]$5010 - attribute \src "libresoc.v:121058.7-121058.28" - wire $0\ren_delay$11[0:0]$5051 - attribute \src "libresoc.v:121107.3-121115.6" - wire $0\ren_delay$next[0:0]$5025 - attribute \src "libresoc.v:121081.3-121082.35" + attribute \src "libresoc.v:122250.3-122258.6" + wire $0\ren_delay$10$next[0:0]$5110 + attribute \src "libresoc.v:122203.3-122204.43" + wire $0\ren_delay$10[0:0]$5093 + attribute \src "libresoc.v:122178.7-122178.28" + wire $0\ren_delay$10[0:0]$5130 + attribute \src "libresoc.v:122269.3-122277.6" + wire $0\ren_delay$11$next[0:0]$5114 + attribute \src "libresoc.v:122201.3-122202.43" + wire $0\ren_delay$11[0:0]$5091 + attribute \src "libresoc.v:122182.7-122182.28" + wire $0\ren_delay$11[0:0]$5132 + attribute \src "libresoc.v:122231.3-122239.6" + wire $0\ren_delay$next[0:0]$5106 + attribute \src "libresoc.v:122205.3-122206.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:121116.3-121125.6" + attribute \src "libresoc.v:122240.3-122249.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:121135.3-121144.6" + attribute \src "libresoc.v:122259.3-122268.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:121154.3-121163.6" + attribute \src "libresoc.v:122278.3-122287.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:121126.3-121134.6" - wire $1\ren_delay$10$next[0:0]$5030 - attribute \src "libresoc.v:121145.3-121153.6" - wire $1\ren_delay$11$next[0:0]$5034 - attribute \src "libresoc.v:121107.3-121115.6" - wire $1\ren_delay$next[0:0]$5026 - attribute \src "libresoc.v:121052.7-121052.23" + attribute \src "libresoc.v:122250.3-122258.6" + wire $1\ren_delay$10$next[0:0]$5111 + attribute \src "libresoc.v:122269.3-122277.6" + wire $1\ren_delay$11$next[0:0]$5115 + attribute \src "libresoc.v:122231.3-122239.6" + wire $1\ren_delay$next[0:0]$5107 + attribute \src "libresoc.v:122176.7-122176.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:121116.3-121125.6" + attribute \src "libresoc.v:122240.3-122249.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:121135.3-121144.6" + attribute \src "libresoc.v:122259.3-122268.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:121104.26-121104.32" - wire width 64 $memrd$\memory$libresoc.v:121104$5021_DATA - attribute \src "libresoc.v:121105.30-121105.36" - wire width 64 $memrd$\memory$libresoc.v:121105$5022_DATA - attribute \src "libresoc.v:121106.30-121106.36" - wire width 64 $memrd$\memory$libresoc.v:121106$5023_DATA + attribute \src "libresoc.v:122228.26-122228.32" + wire width 64 $memrd$\memory$libresoc.v:122228$5102_DATA + attribute \src "libresoc.v:122229.30-122229.36" + wire width 64 $memrd$\memory$libresoc.v:122229$5103_DATA + attribute \src "libresoc.v:122230.30-122230.36" + wire width 64 $memrd$\memory$libresoc.v:122230$5104_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:121101$5007_ADDR + wire width 3 $memwr$\memory$libresoc.v:122225$5088_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:121101$5007_DATA + wire width 64 $memwr$\memory$libresoc.v:122225$5088_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:121101$5007_EN + wire width 64 $memwr$\memory$libresoc.v:122225$5088_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:121102$5008_ADDR + wire width 3 $memwr$\memory$libresoc.v:122226$5089_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:121102$5008_DATA + wire width 64 $memwr$\memory$libresoc.v:122226$5089_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:121102$5008_EN - attribute \src "libresoc.v:121094.13-121094.16" + wire width 64 $memwr$\memory$libresoc.v:122226$5089_EN + attribute \src "libresoc.v:122218.13-122218.16" wire width 3 \_0_ - attribute \src "libresoc.v:121095.13-121095.16" + attribute \src "libresoc.v:122219.13-122219.16" wire width 3 \_1_ - attribute \src "libresoc.v:121096.13-121096.16" + attribute \src "libresoc.v:122220.13-122220.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \dest1__addr + wire width 3 input 15 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i + wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \dest1__wen - attribute \src "libresoc.v:121003.7-121003.15" + wire input 16 \dest1__wen + attribute \src "libresoc.v:122127.7-122127.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \issue__addr + wire width 3 input 2 \issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \issue__addr$1 + wire width 3 input 5 \issue__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 6 \issue__data_i + wire width 64 input 7 \issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \issue__data_o + wire width 64 output 4 \issue__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \issue__ren + wire input 3 \issue__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 5 \issue__wen + wire input 6 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 3 \memory_r_addr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" @@ -190966,101 +193512,101 @@ module \fast attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src1__addr + wire width 3 input 9 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src1__data_o + wire width 64 output 8 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 9 \src1__ren + wire input 10 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 11 \src2__addr + wire width 3 input 12 \src2__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src2__data_o + wire width 64 output 11 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \src2__ren - attribute \src "libresoc.v:121083.14-121083.20" + wire input 13 \src2__ren + attribute \src "libresoc.v:122207.14-122207.20" memory width 64 size 8 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5036 + cell $meminit $meminit$\memory$libresoc.v:0$5117 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5036 + parameter \PRIORITY 5117 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5037 + cell $meminit $meminit$\memory$libresoc.v:0$5118 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5037 + parameter \PRIORITY 5118 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5038 + cell $meminit $meminit$\memory$libresoc.v:0$5119 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5038 + parameter \PRIORITY 5119 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5039 + cell $meminit $meminit$\memory$libresoc.v:0$5120 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5039 + parameter \PRIORITY 5120 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5040 + cell $meminit $meminit$\memory$libresoc.v:0$5121 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5040 + parameter \PRIORITY 5121 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5041 + cell $meminit $meminit$\memory$libresoc.v:0$5122 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5041 + parameter \PRIORITY 5122 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5042 + cell $meminit $meminit$\memory$libresoc.v:0$5123 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5042 + parameter \PRIORITY 5123 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5043 + cell $meminit $meminit$\memory$libresoc.v:0$5124 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5043 + parameter \PRIORITY 5124 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:121104.26-121104.32" - cell $memrd $memrd$\memory$libresoc.v:121104$5021 + attribute \src "libresoc.v:122228.26-122228.32" + cell $memrd $memrd$\memory$libresoc.v:122228$5102 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -191069,11 +193615,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:121104$5021_DATA + connect \DATA $memrd$\memory$libresoc.v:122228$5102_DATA connect \EN 1'x end - attribute \src "libresoc.v:121105.30-121105.36" - cell $memrd $memrd$\memory$libresoc.v:121105$5022 + attribute \src "libresoc.v:122229.30-122229.36" + cell $memrd $memrd$\memory$libresoc.v:122229$5103 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -191082,11 +193628,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:121105$5022_DATA + connect \DATA $memrd$\memory$libresoc.v:122229$5103_DATA connect \EN 1'x end - attribute \src "libresoc.v:121106.30-121106.36" - cell $memrd $memrd$\memory$libresoc.v:121106$5023 + attribute \src "libresoc.v:122230.30-122230.36" + cell $memrd $memrd$\memory$libresoc.v:122230$5104 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -191095,95 +193641,95 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:121106$5023_DATA + connect \DATA $memrd$\memory$libresoc.v:122230$5104_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5044 + cell $memwr $memwr$\memory$libresoc.v:0$5125 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5044 + parameter \PRIORITY 5125 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:121101$5007_ADDR + connect \ADDR $memwr$\memory$libresoc.v:122225$5088_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:121101$5007_DATA - connect \EN $memwr$\memory$libresoc.v:121101$5007_EN + connect \DATA $memwr$\memory$libresoc.v:122225$5088_DATA + connect \EN $memwr$\memory$libresoc.v:122225$5088_EN end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5045 + cell $memwr $memwr$\memory$libresoc.v:0$5126 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5045 + parameter \PRIORITY 5126 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:121102$5008_ADDR + connect \ADDR $memwr$\memory$libresoc.v:122226$5089_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:121102$5008_DATA - connect \EN $memwr$\memory$libresoc.v:121102$5008_EN + connect \DATA $memwr$\memory$libresoc.v:122226$5089_DATA + connect \EN $memwr$\memory$libresoc.v:122226$5089_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5052 + process $proc$libresoc.v:0$5133 sync always sync init end - attribute \src "libresoc.v:121003.7-121003.20" - process $proc$libresoc.v:121003$5046 + attribute \src "libresoc.v:122127.7-122127.20" + process $proc$libresoc.v:122127$5127 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121052.7-121052.23" - process $proc$libresoc.v:121052$5047 + attribute \src "libresoc.v:122176.7-122176.23" + process $proc$libresoc.v:122176$5128 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:121054.7-121054.28" - process $proc$libresoc.v:121054$5048 + attribute \src "libresoc.v:122178.7-122178.28" + process $proc$libresoc.v:122178$5129 assign { } { } - assign $0\ren_delay$10[0:0]$5049 1'0 + assign $0\ren_delay$10[0:0]$5130 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5049 + update \ren_delay$10 $0\ren_delay$10[0:0]$5130 end - attribute \src "libresoc.v:121058.7-121058.28" - process $proc$libresoc.v:121058$5050 + attribute \src "libresoc.v:122182.7-122182.28" + process $proc$libresoc.v:122182$5131 assign { } { } - assign $0\ren_delay$11[0:0]$5051 1'0 + assign $0\ren_delay$11[0:0]$5132 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5051 + update \ren_delay$11 $0\ren_delay$11[0:0]$5132 end - attribute \src "libresoc.v:121077.3-121078.43" - process $proc$libresoc.v:121077$5009 + attribute \src "libresoc.v:122201.3-122202.43" + process $proc$libresoc.v:122201$5090 assign { } { } - assign $0\ren_delay$11[0:0]$5010 \ren_delay$11$next + assign $0\ren_delay$11[0:0]$5091 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5010 + update \ren_delay$11 $0\ren_delay$11[0:0]$5091 end - attribute \src "libresoc.v:121079.3-121080.43" - process $proc$libresoc.v:121079$5011 + attribute \src "libresoc.v:122203.3-122204.43" + process $proc$libresoc.v:122203$5092 assign { } { } - assign $0\ren_delay$10[0:0]$5012 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5093 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5012 + update \ren_delay$10 $0\ren_delay$10[0:0]$5093 end - attribute \src "libresoc.v:121081.3-121082.35" - process $proc$libresoc.v:121081$5013 + attribute \src "libresoc.v:122205.3-122206.35" + process $proc$libresoc.v:122205$5094 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:121097.3-121103.6" - process $proc$libresoc.v:121097$5014 + attribute \src "libresoc.v:122221.3-122227.6" + process $proc$libresoc.v:122221$5095 assign { } { } assign { } { } assign { } { } @@ -191193,52 +193739,52 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 3'xxx - assign $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 3'xxx - assign $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 3'xxx + assign $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 3'xxx + assign $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[2:0] \src1__addr assign $0\_1_[2:0] \src2__addr assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:121101.5-121101.62" + attribute \src "libresoc.v:122225.5-122225.62" switch \issue__wen - attribute \src "libresoc.v:121101.9-121101.19" + attribute \src "libresoc.v:122225.9-122225.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 \issue__data_i - assign $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 \issue__data_i + assign $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 64'1111111111111111111111111111111111111111111111111111111111111111 case end - attribute \src "libresoc.v:121102.5-121102.58" + attribute \src "libresoc.v:122226.5-122226.58" switch \dest1__wen - attribute \src "libresoc.v:121102.9-121102.19" + attribute \src "libresoc.v:122226.9-122226.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 \dest1__addr - assign $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 \dest1__addr + assign $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:121101$5007_ADDR $0$memwr$\memory$libresoc.v:121101$5007_ADDR[2:0]$5015 - update $memwr$\memory$libresoc.v:121101$5007_DATA $0$memwr$\memory$libresoc.v:121101$5007_DATA[63:0]$5016 - update $memwr$\memory$libresoc.v:121101$5007_EN $0$memwr$\memory$libresoc.v:121101$5007_EN[63:0]$5017 - update $memwr$\memory$libresoc.v:121102$5008_ADDR $0$memwr$\memory$libresoc.v:121102$5008_ADDR[2:0]$5018 - update $memwr$\memory$libresoc.v:121102$5008_DATA $0$memwr$\memory$libresoc.v:121102$5008_DATA[63:0]$5019 - update $memwr$\memory$libresoc.v:121102$5008_EN $0$memwr$\memory$libresoc.v:121102$5008_EN[63:0]$5020 + update $memwr$\memory$libresoc.v:122225$5088_ADDR $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 + update $memwr$\memory$libresoc.v:122225$5088_DATA $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 + update $memwr$\memory$libresoc.v:122225$5088_EN $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 + update $memwr$\memory$libresoc.v:122226$5089_ADDR $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 + update $memwr$\memory$libresoc.v:122226$5089_DATA $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 + update $memwr$\memory$libresoc.v:122226$5089_EN $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 end - attribute \src "libresoc.v:121107.3-121115.6" - process $proc$libresoc.v:121107$5024 + attribute \src "libresoc.v:122231.3-122239.6" + process $proc$libresoc.v:122231$5105 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5025 $1\ren_delay$next[0:0]$5026 - attribute \src "libresoc.v:121108.5-121108.29" + assign $0\ren_delay$next[0:0]$5106 $1\ren_delay$next[0:0]$5107 + attribute \src "libresoc.v:122232.5-122232.29" switch \initial - attribute \src "libresoc.v:121108.9-121108.17" + attribute \src "libresoc.v:122232.9-122232.17" case 1'1 case end @@ -191247,21 +193793,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5026 1'0 + assign $1\ren_delay$next[0:0]$5107 1'0 case - assign $1\ren_delay$next[0:0]$5026 \src1__ren + assign $1\ren_delay$next[0:0]$5107 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5025 + update \ren_delay$next $0\ren_delay$next[0:0]$5106 end - attribute \src "libresoc.v:121116.3-121125.6" - process $proc$libresoc.v:121116$5027 + attribute \src "libresoc.v:122240.3-122249.6" + process $proc$libresoc.v:122240$5108 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:121117.5-121117.29" + attribute \src "libresoc.v:122241.5-122241.29" switch \initial - attribute \src "libresoc.v:121117.9-121117.17" + attribute \src "libresoc.v:122241.9-122241.17" case 1'1 case end @@ -191277,14 +193823,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:121126.3-121134.6" - process $proc$libresoc.v:121126$5028 + attribute \src "libresoc.v:122250.3-122258.6" + process $proc$libresoc.v:122250$5109 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5029 $1\ren_delay$10$next[0:0]$5030 - attribute \src "libresoc.v:121127.5-121127.29" + assign $0\ren_delay$10$next[0:0]$5110 $1\ren_delay$10$next[0:0]$5111 + attribute \src "libresoc.v:122251.5-122251.29" switch \initial - attribute \src "libresoc.v:121127.9-121127.17" + attribute \src "libresoc.v:122251.9-122251.17" case 1'1 case end @@ -191293,21 +193839,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5030 1'0 + assign $1\ren_delay$10$next[0:0]$5111 1'0 case - assign $1\ren_delay$10$next[0:0]$5030 \src2__ren + assign $1\ren_delay$10$next[0:0]$5111 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5029 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5110 end - attribute \src "libresoc.v:121135.3-121144.6" - process $proc$libresoc.v:121135$5031 + attribute \src "libresoc.v:122259.3-122268.6" + process $proc$libresoc.v:122259$5112 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:121136.5-121136.29" + attribute \src "libresoc.v:122260.5-122260.29" switch \initial - attribute \src "libresoc.v:121136.9-121136.17" + attribute \src "libresoc.v:122260.9-122260.17" case 1'1 case end @@ -191323,14 +193869,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:121145.3-121153.6" - process $proc$libresoc.v:121145$5032 + attribute \src "libresoc.v:122269.3-122277.6" + process $proc$libresoc.v:122269$5113 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5033 $1\ren_delay$11$next[0:0]$5034 - attribute \src "libresoc.v:121146.5-121146.29" + assign $0\ren_delay$11$next[0:0]$5114 $1\ren_delay$11$next[0:0]$5115 + attribute \src "libresoc.v:122270.5-122270.29" switch \initial - attribute \src "libresoc.v:121146.9-121146.17" + attribute \src "libresoc.v:122270.9-122270.17" case 1'1 case end @@ -191339,21 +193885,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5034 1'0 + assign $1\ren_delay$11$next[0:0]$5115 1'0 case - assign $1\ren_delay$11$next[0:0]$5034 \issue__ren + assign $1\ren_delay$11$next[0:0]$5115 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5033 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5114 end - attribute \src "libresoc.v:121154.3-121163.6" - process $proc$libresoc.v:121154$5035 + attribute \src "libresoc.v:122278.3-122287.6" + process $proc$libresoc.v:122278$5116 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:121155.5-121155.29" + attribute \src "libresoc.v:122279.5-122279.29" switch \initial - attribute \src "libresoc.v:121155.9-121155.17" + attribute \src "libresoc.v:122279.9-122279.17" case 1'1 case end @@ -191369,9 +193915,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:121104$5021_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:121105$5022_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:121106$5023_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:122228$5102_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:122229$5103_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:122230$5104_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -191382,309 +193928,323 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:121177.1-123070.10" +attribute \src "libresoc.v:122301.1-124221.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 321 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 308 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 254 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 255 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 256 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 257 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 258 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 259 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 330 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 257 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 258 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 259 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 260 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 261 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 262 \cr_a_ok$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 2 \cu_ad__go_i + wire input 3 \cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 3 \cu_ad__rel_o + wire output 4 \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 24 \cu_busy_o + wire output 25 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 73 \cu_busy_o$11 + wire output 75 \cu_busy_o$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 80 \cu_busy_o$14 + wire output 82 \cu_busy_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 101 \cu_busy_o$17 + wire output 103 \cu_busy_o$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 30 \cu_busy_o$2 + wire output 31 \cu_busy_o$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 116 \cu_busy_o$20 + wire output 118 \cu_busy_o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 135 \cu_busy_o$23 + wire output 138 \cu_busy_o$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 154 \cu_busy_o$26 + wire output 157 \cu_busy_o$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 41 \cu_busy_o$5 + wire output 42 \cu_busy_o$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 52 \cu_busy_o$8 + wire output 54 \cu_busy_o$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 23 \cu_issue_i + wire input 24 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 29 \cu_issue_i$1 + wire input 30 \cu_issue_i$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 72 \cu_issue_i$10 + wire input 74 \cu_issue_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 79 \cu_issue_i$13 + wire input 81 \cu_issue_i$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 100 \cu_issue_i$16 + wire input 102 \cu_issue_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 115 \cu_issue_i$19 + wire input 117 \cu_issue_i$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 134 \cu_issue_i$22 + wire input 137 \cu_issue_i$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 153 \cu_issue_i$25 + wire input 156 \cu_issue_i$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 40 \cu_issue_i$4 + wire input 41 \cu_issue_i$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 51 \cu_issue_i$7 + wire input 53 \cu_issue_i$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 157 \cu_rd__go_i + wire width 4 input 160 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 160 \cu_rd__go_i$29 + wire width 6 input 163 \cu_rd__go_i$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 163 \cu_rd__go_i$32 + wire width 4 input 166 \cu_rd__go_i$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 166 \cu_rd__go_i$35 + wire width 3 input 169 \cu_rd__go_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 169 \cu_rd__go_i$38 + wire width 6 input 172 \cu_rd__go_i$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 172 \cu_rd__go_i$41 + wire width 3 input 175 \cu_rd__go_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 175 \cu_rd__go_i$44 + wire width 3 input 178 \cu_rd__go_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 178 \cu_rd__go_i$47 + wire width 5 input 181 \cu_rd__go_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 181 \cu_rd__go_i$50 + wire width 3 input 184 \cu_rd__go_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 206 \cu_rd__go_i$70 + wire width 3 input 209 \cu_rd__go_i$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 156 \cu_rd__rel_o + wire width 4 output 159 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 159 \cu_rd__rel_o$28 + wire width 6 output 162 \cu_rd__rel_o$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 162 \cu_rd__rel_o$31 + wire width 4 output 165 \cu_rd__rel_o$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 165 \cu_rd__rel_o$34 + wire width 3 output 168 \cu_rd__rel_o$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 168 \cu_rd__rel_o$37 + wire width 6 output 171 \cu_rd__rel_o$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 171 \cu_rd__rel_o$40 + wire width 3 output 174 \cu_rd__rel_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 174 \cu_rd__rel_o$43 + wire width 3 output 177 \cu_rd__rel_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 177 \cu_rd__rel_o$46 + wire width 5 output 180 \cu_rd__rel_o$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 180 \cu_rd__rel_o$49 + wire width 3 output 183 \cu_rd__rel_o$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 205 \cu_rd__rel_o$69 + wire width 3 output 208 \cu_rd__rel_o$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 25 \cu_rdmaskn_i + wire width 4 input 26 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 74 \cu_rdmaskn_i$12 + wire width 3 input 76 \cu_rdmaskn_i$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 81 \cu_rdmaskn_i$15 + wire width 6 input 83 \cu_rdmaskn_i$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 102 \cu_rdmaskn_i$18 + wire width 3 input 104 \cu_rdmaskn_i$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 117 \cu_rdmaskn_i$21 + wire width 3 input 119 \cu_rdmaskn_i$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 136 \cu_rdmaskn_i$24 + wire width 5 input 139 \cu_rdmaskn_i$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 155 \cu_rdmaskn_i$27 + wire width 3 input 158 \cu_rdmaskn_i$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 31 \cu_rdmaskn_i$3 + wire width 6 input 32 \cu_rdmaskn_i$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 42 \cu_rdmaskn_i$6 + wire width 3 input 43 \cu_rdmaskn_i$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 53 \cu_rdmaskn_i$9 + wire width 4 input 55 \cu_rdmaskn_i$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 4 \cu_st__go_i + wire input 5 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 1 \cu_st__rel_o + wire output 2 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 218 \cu_wr__go_i + wire width 5 input 221 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 239 \cu_wr__go_i$100 + wire width 3 input 242 \cu_wr__go_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 241 \cu_wr__go_i$102 + wire width 2 input 244 \cu_wr__go_i$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 290 \cu_wr__go_i$137 + wire width 3 input 293 \cu_wr__go_i$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 221 \cu_wr__go_i$82 + wire width 3 input 224 \cu_wr__go_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 224 \cu_wr__go_i$85 + wire width 5 input 227 \cu_wr__go_i$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 227 \cu_wr__go_i$88 + wire width 2 input 230 \cu_wr__go_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 230 \cu_wr__go_i$91 + wire width 6 input 233 \cu_wr__go_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 233 \cu_wr__go_i$94 + wire width 4 input 236 \cu_wr__go_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 236 \cu_wr__go_i$97 + wire width 4 input 239 \cu_wr__go_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 217 \cu_wr__rel_o + wire width 5 output 220 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 240 \cu_wr__rel_o$101 + wire width 2 output 243 \cu_wr__rel_o$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 289 \cu_wr__rel_o$136 + wire width 3 output 292 \cu_wr__rel_o$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 220 \cu_wr__rel_o$81 + wire width 3 output 223 \cu_wr__rel_o$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 223 \cu_wr__rel_o$84 + wire width 5 output 226 \cu_wr__rel_o$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 226 \cu_wr__rel_o$87 + wire width 2 output 229 \cu_wr__rel_o$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 229 \cu_wr__rel_o$90 + wire width 6 output 232 \cu_wr__rel_o$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 232 \cu_wr__rel_o$93 + wire width 4 output 235 \cu_wr__rel_o$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 235 \cu_wr__rel_o$96 + wire width 4 output 238 \cu_wr__rel_o$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 238 \cu_wr__rel_o$99 + wire width 3 output 241 \cu_wr__rel_o$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 242 \dest1_o + wire width 64 output 245 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 243 \dest1_o$103 + wire width 64 output 246 \dest1_o$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 244 \dest1_o$104 + wire width 64 output 247 \dest1_o$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 245 \dest1_o$105 + wire width 64 output 248 \dest1_o$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 246 \dest1_o$106 + wire width 64 output 249 \dest1_o$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 247 \dest1_o$107 + wire width 64 output 250 \dest1_o$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 248 \dest1_o$108 + wire width 64 output 251 \dest1_o$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 249 \dest1_o$109 + wire width 64 output 252 \dest1_o$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 295 \dest1_o$141 + wire width 64 output 298 \dest1_o$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 253 \dest2_o + wire width 32 output 256 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 260 \dest2_o$115 + wire width 4 output 263 \dest2_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 262 \dest2_o$116 + wire width 4 output 265 \dest2_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 263 \dest2_o$117 + wire width 4 output 266 \dest2_o$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 264 \dest2_o$118 + wire width 4 output 267 \dest2_o$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 265 \dest2_o$119 + wire width 4 output 268 \dest2_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 296 \dest2_o$142 + wire width 64 output 299 \dest2_o$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 298 \dest2_o$144 + wire width 64 output 301 \dest2_o$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 307 \dest2_o$150 + wire width 64 output 310 \dest2_o$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 261 \dest3_o + wire width 4 output 264 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 269 \dest3_o$122 + wire width 2 output 272 \dest3_o$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 271 \dest3_o$123 + wire width 2 output 274 \dest3_o$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 278 \dest3_o$127 + wire width 2 output 281 \dest3_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 279 \dest3_o$128 + wire width 2 output 282 \dest3_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 297 \dest3_o$143 + wire width 64 output 300 \dest3_o$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 299 \dest3_o$145 + wire width 64 output 302 \dest3_o$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 302 \dest3_o$147 + wire width 64 output 305 \dest3_o$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 276 \dest4_o + wire width 2 output 279 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 285 \dest4_o$133 + wire output 288 \dest4_o$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 286 \dest4_o$134 + wire output 289 \dest4_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 287 \dest4_o$135 + wire output 290 \dest4_o$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 303 \dest4_o$148 + wire width 64 output 306 \dest4_o$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 277 \dest5_o + wire width 2 output 280 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 284 \dest5_o$132 + wire output 287 \dest5_o$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 305 \dest5_o$149 + wire width 64 output 308 \dest5_o$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 270 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 251 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 288 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 291 \fast1_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 292 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 293 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 294 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 252 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 315 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 313 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 314 \ldst_port0_addr_i_ok + wire width 2 output 273 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 254 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 291 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 294 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 295 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 296 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 297 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 255 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 315 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 316 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 316 \ldst_port0_addr_ok_o + wire input 325 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 309 \ldst_port0_busy_o + wire input 311 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 312 \ldst_port0_data_len + wire width 4 output 314 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 317 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 318 \ldst_port0_exc_$signal$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 319 \ldst_port0_exc_$signal$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 320 \ldst_port0_exc_$signal$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 321 \ldst_port0_exc_$signal$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 322 \ldst_port0_exc_$signal$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 323 \ldst_port0_exc_$signal$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 324 \ldst_port0_exc_$signal$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 310 \ldst_port0_is_ld_i + wire output 312 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 311 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 317 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 318 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 319 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 320 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 304 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 300 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 301 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 250 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 216 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 219 \o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 222 \o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 225 \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 228 \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 231 \o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 234 \o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 237 \o_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \oper_i_alu_alu0__data_len + wire output 313 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 326 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 327 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 328 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 329 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 307 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 303 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 304 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 253 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 219 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 222 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 225 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 228 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 231 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 234 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 237 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 240 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \oper_i_alu_alu0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -191699,19 +194259,19 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \oper_i_alu_alu0__fn_unit + wire width 12 input 7 \oper_i_alu_alu0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_alu_alu0__imm_data__data + wire width 64 input 8 \oper_i_alu_alu0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_alu0__imm_data__ok + wire input 9 \oper_i_alu_alu0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \oper_i_alu_alu0__input_carry + wire width 2 input 18 \oper_i_alu_alu0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \oper_i_alu_alu0__insn + wire width 32 input 23 \oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -191787,31 +194347,31 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \oper_i_alu_alu0__insn_type + wire width 7 input 6 \oper_i_alu_alu0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_alu0__invert_in + wire input 14 \oper_i_alu_alu0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_alu0__invert_out + wire input 16 \oper_i_alu_alu0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \oper_i_alu_alu0__is_32bit + wire input 20 \oper_i_alu_alu0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \oper_i_alu_alu0__is_signed + wire input 21 \oper_i_alu_alu0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_alu0__oe__oe + wire input 12 \oper_i_alu_alu0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_alu0__oe__ok + wire input 13 \oper_i_alu_alu0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \oper_i_alu_alu0__output_carry + wire input 19 \oper_i_alu_alu0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_alu0__rc__ok + wire input 11 \oper_i_alu_alu0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_alu0__rc__rc + wire input 10 \oper_i_alu_alu0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_alu0__write_cr0 + wire input 17 \oper_i_alu_alu0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_alu0__zero_a + wire input 15 \oper_i_alu_alu0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 32 \oper_i_alu_branch0__cia + wire width 64 input 33 \oper_i_alu_branch0__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -191826,13 +194386,13 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 34 \oper_i_alu_branch0__fn_unit + wire width 12 input 35 \oper_i_alu_branch0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 36 \oper_i_alu_branch0__imm_data__data + wire width 64 input 37 \oper_i_alu_branch0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \oper_i_alu_branch0__imm_data__ok + wire input 38 \oper_i_alu_branch0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 35 \oper_i_alu_branch0__insn + wire width 32 input 36 \oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -191908,11 +194468,11 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 33 \oper_i_alu_branch0__insn_type + wire width 7 input 34 \oper_i_alu_branch0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \oper_i_alu_branch0__is_32bit + wire input 40 \oper_i_alu_branch0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \oper_i_alu_branch0__lk + wire input 39 \oper_i_alu_branch0__lk attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -191927,9 +194487,9 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 27 \oper_i_alu_cr0__fn_unit + wire width 12 input 28 \oper_i_alu_cr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 28 \oper_i_alu_cr0__insn + wire width 32 input 29 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192005,9 +194565,9 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 26 \oper_i_alu_cr0__insn_type + wire width 7 input 27 \oper_i_alu_cr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 98 \oper_i_alu_div0__data_len + wire width 4 input 100 \oper_i_alu_div0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192022,19 +194582,19 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 83 \oper_i_alu_div0__fn_unit + wire width 12 input 85 \oper_i_alu_div0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 84 \oper_i_alu_div0__imm_data__data + wire width 64 input 86 \oper_i_alu_div0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 85 \oper_i_alu_div0__imm_data__ok + wire input 87 \oper_i_alu_div0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 92 \oper_i_alu_div0__input_carry + wire width 2 input 94 \oper_i_alu_div0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 99 \oper_i_alu_div0__insn + wire width 32 input 101 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192110,31 +194670,31 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 82 \oper_i_alu_div0__insn_type + wire width 7 input 84 \oper_i_alu_div0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 90 \oper_i_alu_div0__invert_in + wire input 92 \oper_i_alu_div0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 93 \oper_i_alu_div0__invert_out + wire input 95 \oper_i_alu_div0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 96 \oper_i_alu_div0__is_32bit + wire input 98 \oper_i_alu_div0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 97 \oper_i_alu_div0__is_signed + wire input 99 \oper_i_alu_div0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 88 \oper_i_alu_div0__oe__oe + wire input 90 \oper_i_alu_div0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 89 \oper_i_alu_div0__oe__ok + wire input 91 \oper_i_alu_div0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 95 \oper_i_alu_div0__output_carry + wire input 97 \oper_i_alu_div0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 87 \oper_i_alu_div0__rc__ok + wire input 89 \oper_i_alu_div0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 86 \oper_i_alu_div0__rc__rc + wire input 88 \oper_i_alu_div0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 94 \oper_i_alu_div0__write_cr0 + wire input 96 \oper_i_alu_div0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 91 \oper_i_alu_div0__zero_a + wire input 93 \oper_i_alu_div0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 70 \oper_i_alu_logical0__data_len + wire width 4 input 72 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192149,19 +194709,19 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 55 \oper_i_alu_logical0__fn_unit + wire width 12 input 57 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 56 \oper_i_alu_logical0__imm_data__data + wire width 64 input 58 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 57 \oper_i_alu_logical0__imm_data__ok + wire input 59 \oper_i_alu_logical0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 64 \oper_i_alu_logical0__input_carry + wire width 2 input 66 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 71 \oper_i_alu_logical0__insn + wire width 32 input 73 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192237,29 +194797,29 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 54 \oper_i_alu_logical0__insn_type + wire width 7 input 56 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 62 \oper_i_alu_logical0__invert_in + wire input 64 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 65 \oper_i_alu_logical0__invert_out + wire input 67 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 68 \oper_i_alu_logical0__is_32bit + wire input 70 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 69 \oper_i_alu_logical0__is_signed + wire input 71 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 60 \oper_i_alu_logical0__oe__oe + wire input 62 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 61 \oper_i_alu_logical0__oe__ok + wire input 63 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 67 \oper_i_alu_logical0__output_carry + wire input 69 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 59 \oper_i_alu_logical0__rc__ok + wire input 61 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 58 \oper_i_alu_logical0__rc__rc + wire input 60 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 66 \oper_i_alu_logical0__write_cr0 + wire input 68 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 63 \oper_i_alu_logical0__zero_a + wire input 65 \oper_i_alu_logical0__zero_a attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192274,13 +194834,13 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 104 \oper_i_alu_mul0__fn_unit + wire width 12 input 106 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 105 \oper_i_alu_mul0__imm_data__data + wire width 64 input 107 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 106 \oper_i_alu_mul0__imm_data__ok + wire input 108 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 114 \oper_i_alu_mul0__insn + wire width 32 input 116 \oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192356,21 +194916,21 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 103 \oper_i_alu_mul0__insn_type + wire width 7 input 105 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 112 \oper_i_alu_mul0__is_32bit + wire input 114 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 113 \oper_i_alu_mul0__is_signed + wire input 115 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 109 \oper_i_alu_mul0__oe__oe + wire input 111 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 110 \oper_i_alu_mul0__oe__ok + wire input 112 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 108 \oper_i_alu_mul0__rc__ok + wire input 110 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 107 \oper_i_alu_mul0__rc__rc + wire input 109 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 111 \oper_i_alu_mul0__write_cr0 + wire input 113 \oper_i_alu_mul0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192385,21 +194945,21 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 119 \oper_i_alu_shift_rot0__fn_unit + wire width 12 input 121 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 120 \oper_i_alu_shift_rot0__imm_data__data + wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 121 \oper_i_alu_shift_rot0__imm_data__ok + wire input 123 \oper_i_alu_shift_rot0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 127 \oper_i_alu_shift_rot0__input_carry + wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 129 \oper_i_alu_shift_rot0__input_cr + wire input 132 \oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 133 \oper_i_alu_shift_rot0__insn + wire width 32 input 136 \oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192475,25 +195035,27 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 118 \oper_i_alu_shift_rot0__insn_type + wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 131 \oper_i_alu_shift_rot0__is_32bit + wire input 134 \oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 132 \oper_i_alu_shift_rot0__is_signed + wire input 135 \oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 124 \oper_i_alu_shift_rot0__oe__oe + wire input 126 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 125 \oper_i_alu_shift_rot0__oe__ok + wire input 127 \oper_i_alu_shift_rot0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 128 \oper_i_alu_shift_rot0__output_carry + wire input 131 \oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 130 \oper_i_alu_shift_rot0__output_cr + wire input 133 \oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 123 \oper_i_alu_shift_rot0__rc__ok + wire input 125 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 122 \oper_i_alu_shift_rot0__rc__rc + wire input 124 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 126 \oper_i_alu_shift_rot0__write_cr0 + wire input 128 \oper_i_alu_shift_rot0__write_cr0 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192508,9 +195070,9 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 76 \oper_i_alu_spr0__fn_unit + wire width 12 input 78 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 77 \oper_i_alu_spr0__insn + wire width 32 input 79 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192586,11 +195148,11 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 75 \oper_i_alu_spr0__insn_type + wire width 7 input 77 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 78 \oper_i_alu_spr0__is_32bit + wire input 80 \oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 47 \oper_i_alu_trap0__cia + wire width 64 input 48 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192605,9 +195167,9 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 44 \oper_i_alu_trap0__fn_unit + wire width 12 input 45 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 45 \oper_i_alu_trap0__insn + wire width 32 input 46 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192683,19 +195245,21 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 43 \oper_i_alu_trap0__insn_type + wire width 7 input 44 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \oper_i_alu_trap0__is_32bit + wire input 49 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 46 \oper_i_alu_trap0__msr + wire width 8 input 52 \oper_i_alu_trap0__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 50 \oper_i_alu_trap0__trapaddr + wire width 64 input 47 \oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 49 \oper_i_alu_trap0__traptype + wire width 13 input 51 \oper_i_alu_trap0__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 149 \oper_i_ldst_ldst0__byte_reverse + wire width 8 input 50 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 148 \oper_i_ldst_ldst0__data_len + wire input 152 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 151 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -192710,13 +195274,13 @@ module \fus attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 138 \oper_i_ldst_ldst0__fn_unit + wire width 12 input 141 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 139 \oper_i_ldst_ldst0__imm_data__data + wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 140 \oper_i_ldst_ldst0__imm_data__ok + wire input 143 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 152 \oper_i_ldst_ldst0__insn + wire width 32 input 155 \oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -192792,136 +195356,136 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 137 \oper_i_ldst_ldst0__insn_type + wire width 7 input 140 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 146 \oper_i_ldst_ldst0__is_32bit + wire input 149 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 147 \oper_i_ldst_ldst0__is_signed + wire input 150 \oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 151 \oper_i_ldst_ldst0__ldst_mode + wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 144 \oper_i_ldst_ldst0__oe__oe + wire input 147 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 145 \oper_i_ldst_ldst0__oe__ok + wire input 148 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 143 \oper_i_ldst_ldst0__rc__ok + wire input 146 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 142 \oper_i_ldst_ldst0__rc__rc + wire input 145 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 150 \oper_i_ldst_ldst0__sign_extend + wire input 153 \oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 141 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 306 \spr1_ok + wire input 144 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 309 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 158 \src1_i + wire width 64 input 161 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 161 \src1_i$30 + wire width 64 input 164 \src1_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 164 \src1_i$33 + wire width 64 input 167 \src1_i$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 167 \src1_i$36 + wire width 64 input 170 \src1_i$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 170 \src1_i$39 + wire width 64 input 173 \src1_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 173 \src1_i$42 + wire width 64 input 176 \src1_i$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 176 \src1_i$45 + wire width 64 input 179 \src1_i$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 179 \src1_i$48 + wire width 64 input 182 \src1_i$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 182 \src1_i$51 + wire width 64 input 185 \src1_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 210 \src1_i$74 + wire width 64 input 213 \src1_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 183 \src2_i + wire width 64 input 186 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 184 \src2_i$52 + wire width 64 input 187 \src2_i$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 185 \src2_i$53 + wire width 64 input 188 \src2_i$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 186 \src2_i$54 + wire width 64 input 189 \src2_i$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 187 \src2_i$55 + wire width 64 input 190 \src2_i$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 188 \src2_i$56 + wire width 64 input 191 \src2_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 189 \src2_i$57 + wire width 64 input 192 \src2_i$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 190 \src2_i$58 + wire width 64 input 193 \src2_i$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 213 \src2_i$77 + wire width 64 input 216 \src2_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 215 \src2_i$79 + wire width 64 input 218 \src2_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 191 \src3_i + wire width 64 input 194 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 192 \src3_i$59 + wire width 64 input 195 \src3_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 193 \src3_i$60 + wire input 196 \src3_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 194 \src3_i$61 + wire input 197 \src3_i$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 196 \src3_i$62 + wire input 199 \src3_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 197 \src3_i$63 + wire input 200 \src3_i$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 203 \src3_i$67 + wire width 32 input 206 \src3_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 207 \src3_i$71 + wire width 4 input 210 \src3_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 211 \src3_i$75 + wire width 64 input 214 \src3_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 212 \src3_i$76 + wire width 64 input 215 \src3_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 195 \src4_i + wire input 198 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 198 \src4_i$64 + wire input 201 \src4_i$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 199 \src4_i$65 + wire width 2 input 202 \src4_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 204 \src4_i$68 + wire width 4 input 207 \src4_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 214 \src4_i$78 + wire width 64 input 217 \src4_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 201 \src5_i + wire width 2 input 204 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 202 \src5_i$66 + wire width 2 input 205 \src5_i$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 208 \src5_i$72 + wire width 4 input 211 \src5_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 200 \src6_i + wire width 2 input 203 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 209 \src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 266 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 267 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 268 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 272 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 273 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 274 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 275 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 280 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 281 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 282 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 283 \xer_so_ok$131 + wire width 4 input 212 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 269 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 270 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 271 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 275 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 276 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 277 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 278 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 283 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 284 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 285 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:122711.8-122753.4" + attribute \src "libresoc.v:123853.8-123895.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -192966,7 +195530,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:122754.11-122781.4" + attribute \src "libresoc.v:123896.11-123923.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -192996,7 +195560,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122782.7-122807.4" + attribute \src "libresoc.v:123924.7-123949.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193024,7 +195588,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122808.8-122847.4" + attribute \src "libresoc.v:123950.8-123989.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193066,7 +195630,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122848.9-122895.4" + attribute \src "libresoc.v:123990.9-124044.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193082,12 +195646,19 @@ module \fus connect \cu_wr__go_i \cu_wr__go_i$102 connect \cu_wr__rel_o \cu_wr__rel_o$101 connect \ea \ea - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o connect \ldst_port0_addr_i \ldst_port0_addr_i connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o connect \ldst_port0_busy_o \ldst_port0_busy_o connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o @@ -193116,7 +195687,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122896.12-122931.4" + attribute \src "libresoc.v:124045.12-124080.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193154,7 +195725,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122932.8-122965.4" + attribute \src "libresoc.v:124081.8-124114.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193190,7 +195761,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:122966.13-123003.4" + attribute \src "libresoc.v:124115.13-124153.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193213,6 +195784,7 @@ module \fus connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe @@ -193230,7 +195802,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123004.8-123036.4" + attribute \src "libresoc.v:124154.8-124186.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193265,7 +195837,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:123037.9-123069.4" + attribute \src "libresoc.v:124187.9-124220.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -193291,6 +195863,7 @@ module \fus connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype @@ -193300,37 +195873,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:123074.1-123132.10" +attribute \src "libresoc.v:124225.1-124283.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:123075.7-123075.20" + attribute \src "libresoc.v:124226.7-124226.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123120.3-123128.6" - wire $0\q_int$next[0:0]$5063 - attribute \src "libresoc.v:123118.3-123119.27" + attribute \src "libresoc.v:124271.3-124279.6" + wire $0\q_int$next[0:0]$5144 + attribute \src "libresoc.v:124269.3-124270.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:123120.3-123128.6" - wire $1\q_int$next[0:0]$5064 - attribute \src "libresoc.v:123099.7-123099.19" + attribute \src "libresoc.v:124271.3-124279.6" + wire $1\q_int$next[0:0]$5145 + attribute \src "libresoc.v:124250.7-124250.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:123110.17-123110.96" - wire $and$libresoc.v:123110$5053_Y - attribute \src "libresoc.v:123115.17-123115.96" - wire $and$libresoc.v:123115$5058_Y - attribute \src "libresoc.v:123112.18-123112.95" - wire $not$libresoc.v:123112$5055_Y - attribute \src "libresoc.v:123114.17-123114.94" - wire $not$libresoc.v:123114$5057_Y - attribute \src "libresoc.v:123117.17-123117.94" - wire $not$libresoc.v:123117$5060_Y - attribute \src "libresoc.v:123111.18-123111.100" - wire $or$libresoc.v:123111$5054_Y - attribute \src "libresoc.v:123113.18-123113.101" - wire $or$libresoc.v:123113$5056_Y - attribute \src "libresoc.v:123116.17-123116.99" - wire $or$libresoc.v:123116$5059_Y + attribute \src "libresoc.v:124261.17-124261.96" + wire $and$libresoc.v:124261$5134_Y + attribute \src "libresoc.v:124266.17-124266.96" + wire $and$libresoc.v:124266$5139_Y + attribute \src "libresoc.v:124263.18-124263.95" + wire $not$libresoc.v:124263$5136_Y + attribute \src "libresoc.v:124265.17-124265.94" + wire $not$libresoc.v:124265$5138_Y + attribute \src "libresoc.v:124268.17-124268.94" + wire $not$libresoc.v:124268$5141_Y + attribute \src "libresoc.v:124262.18-124262.100" + wire $or$libresoc.v:124262$5135_Y + attribute \src "libresoc.v:124264.18-124264.101" + wire $or$libresoc.v:124264$5137_Y + attribute \src "libresoc.v:124267.17-124267.99" + wire $or$libresoc.v:124267$5140_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -193347,11 +195920,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:123075.7-123075.15" + attribute \src "libresoc.v:124226.7-124226.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire output 2 \q_idx_l @@ -193368,7 +195941,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:123110$5053 + cell $and $and$libresoc.v:124261$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193376,10 +195949,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:123110$5053_Y + connect \Y $and$libresoc.v:124261$5134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:123115$5058 + cell $and $and$libresoc.v:124266$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193387,34 +195960,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:123115$5058_Y + connect \Y $and$libresoc.v:124266$5139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:123112$5055 + cell $not $not$libresoc.v:124263$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:123112$5055_Y + connect \Y $not$libresoc.v:124263$5136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:123114$5057 + cell $not $not$libresoc.v:124265$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:123114$5057_Y + connect \Y $not$libresoc.v:124265$5138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:123117$5060 + cell $not $not$libresoc.v:124268$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:123117$5060_Y + connect \Y $not$libresoc.v:124268$5141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:123111$5054 + cell $or $or$libresoc.v:124262$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193422,10 +195995,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:123111$5054_Y + connect \Y $or$libresoc.v:124262$5135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:123113$5056 + cell $or $or$libresoc.v:124264$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193433,10 +196006,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:123113$5056_Y + connect \Y $or$libresoc.v:124264$5137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:123116$5059 + cell $or $or$libresoc.v:124267$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193444,39 +196017,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:123116$5059_Y + connect \Y $or$libresoc.v:124267$5140_Y end - attribute \src "libresoc.v:123075.7-123075.20" - process $proc$libresoc.v:123075$5065 + attribute \src "libresoc.v:124226.7-124226.20" + process $proc$libresoc.v:124226$5146 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123099.7-123099.19" - process $proc$libresoc.v:123099$5066 + attribute \src "libresoc.v:124250.7-124250.19" + process $proc$libresoc.v:124250$5147 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:123118.3-123119.27" - process $proc$libresoc.v:123118$5061 + attribute \src "libresoc.v:124269.3-124270.27" + process $proc$libresoc.v:124269$5142 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:123120.3-123128.6" - process $proc$libresoc.v:123120$5062 + attribute \src "libresoc.v:124271.3-124279.6" + process $proc$libresoc.v:124271$5143 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5063 $1\q_int$next[0:0]$5064 - attribute \src "libresoc.v:123121.5-123121.29" + assign $0\q_int$next[0:0]$5144 $1\q_int$next[0:0]$5145 + attribute \src "libresoc.v:124272.5-124272.29" switch \initial - attribute \src "libresoc.v:123121.9-123121.17" + attribute \src "libresoc.v:124272.9-124272.17" case 1'1 case end @@ -193485,280 +196058,304 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5064 1'0 + assign $1\q_int$next[0:0]$5145 1'0 case - assign $1\q_int$next[0:0]$5064 \$5 + assign $1\q_int$next[0:0]$5145 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5063 + update \q_int$next $0\q_int$next[0:0]$5144 end - connect \$9 $and$libresoc.v:123110$5053_Y - connect \$11 $or$libresoc.v:123111$5054_Y - connect \$13 $not$libresoc.v:123112$5055_Y - connect \$15 $or$libresoc.v:123113$5056_Y - connect \$1 $not$libresoc.v:123114$5057_Y - connect \$3 $and$libresoc.v:123115$5058_Y - connect \$5 $or$libresoc.v:123116$5059_Y - connect \$7 $not$libresoc.v:123117$5060_Y + connect \$9 $and$libresoc.v:124261$5134_Y + connect \$11 $or$libresoc.v:124262$5135_Y + connect \$13 $not$libresoc.v:124263$5136_Y + connect \$15 $or$libresoc.v:124264$5137_Y + connect \$1 $not$libresoc.v:124265$5138_Y + connect \$3 $and$libresoc.v:124266$5139_Y + connect \$5 $or$libresoc.v:124267$5140_Y + connect \$7 $not$libresoc.v:124268$5141_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:123136.1-123458.10" +attribute \src "libresoc.v:124287.1-124666.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.imem" +attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:123415.3-123429.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5129 - attribute \src "libresoc.v:123276.3-123277.39" + attribute \src "libresoc.v:124618.3-124627.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:124598.3-124617.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5216 + attribute \src "libresoc.v:124429.3-124430.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:123430.3-123441.6" + attribute \src "libresoc.v:124628.3-124645.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:123397.3-123414.6" - wire $0\f_fetch_err_o$next[0:0]$5125 - attribute \src "libresoc.v:123278.3-123279.43" + attribute \src "libresoc.v:124575.3-124597.6" + wire $0\f_fetch_err_o$next[0:0]$5211 + attribute \src "libresoc.v:124431.3-124432.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:123442.3-123454.6" + attribute \src "libresoc.v:124646.3-124663.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:123379.3-123396.6" - wire width 45 $0\ibus__adr$next[44:0]$5121 - attribute \src "libresoc.v:123280.3-123281.35" + attribute \src "libresoc.v:124552.3-124574.6" + wire width 45 $0\ibus__adr$next[44:0]$5206 + attribute \src "libresoc.v:124433.3-124434.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:123290.3-123312.6" - wire $0\ibus__cyc$next[0:0]$5101 - attribute \src "libresoc.v:123288.3-123289.35" + attribute \src "libresoc.v:124443.3-124470.6" + wire $0\ibus__cyc$next[0:0]$5182 + attribute \src "libresoc.v:124441.3-124442.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:123336.3-123358.6" - wire width 8 $0\ibus__sel$next[7:0]$5111 - attribute \src "libresoc.v:123284.3-123285.35" + attribute \src "libresoc.v:124499.3-124526.6" + wire width 8 $0\ibus__sel$next[7:0]$5194 + attribute \src "libresoc.v:124437.3-124438.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:123313.3-123335.6" - wire $0\ibus__stb$next[0:0]$5106 - attribute \src "libresoc.v:123286.3-123287.35" + attribute \src "libresoc.v:124471.3-124498.6" + wire $0\ibus__stb$next[0:0]$5188 + attribute \src "libresoc.v:124439.3-124440.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:123359.3-123378.6" - wire width 64 $0\ibus_rdata$next[63:0]$5116 - attribute \src "libresoc.v:123282.3-123283.37" + attribute \src "libresoc.v:124527.3-124551.6" + wire width 64 $0\ibus_rdata$next[63:0]$5200 + attribute \src "libresoc.v:124435.3-124436.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:123137.7-123137.20" + attribute \src "libresoc.v:124288.7-124288.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123415.3-123429.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5130 - attribute \src "libresoc.v:123201.14-123201.44" + attribute \src "libresoc.v:124618.3-124627.6" + wire $1\a_busy_o[0:0] + attribute \src "libresoc.v:124598.3-124617.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5217 + attribute \src "libresoc.v:124352.14-124352.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:123430.3-123441.6" + attribute \src "libresoc.v:124628.3-124645.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:123397.3-123414.6" - wire $1\f_fetch_err_o$next[0:0]$5126 - attribute \src "libresoc.v:123208.7-123208.27" + attribute \src "libresoc.v:124575.3-124597.6" + wire $1\f_fetch_err_o$next[0:0]$5212 + attribute \src "libresoc.v:124359.7-124359.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:123442.3-123454.6" + attribute \src "libresoc.v:124646.3-124663.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:123379.3-123396.6" - wire width 45 $1\ibus__adr$next[44:0]$5122 - attribute \src "libresoc.v:123222.14-123222.42" + attribute \src "libresoc.v:124552.3-124574.6" + wire width 45 $1\ibus__adr$next[44:0]$5207 + attribute \src "libresoc.v:124373.14-124373.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:123290.3-123312.6" - wire $1\ibus__cyc$next[0:0]$5102 - attribute \src "libresoc.v:123227.7-123227.23" + attribute \src "libresoc.v:124443.3-124470.6" + wire $1\ibus__cyc$next[0:0]$5183 + attribute \src "libresoc.v:124378.7-124378.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:123336.3-123358.6" - wire width 8 $1\ibus__sel$next[7:0]$5112 - attribute \src "libresoc.v:123236.13-123236.30" + attribute \src "libresoc.v:124499.3-124526.6" + wire width 8 $1\ibus__sel$next[7:0]$5195 + attribute \src "libresoc.v:124387.13-124387.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:123313.3-123335.6" - wire $1\ibus__stb$next[0:0]$5107 - attribute \src "libresoc.v:123241.7-123241.23" + attribute \src "libresoc.v:124471.3-124498.6" + wire $1\ibus__stb$next[0:0]$5189 + attribute \src "libresoc.v:124392.7-124392.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:123359.3-123378.6" - wire width 64 $1\ibus_rdata$next[63:0]$5117 - attribute \src "libresoc.v:123245.14-123245.47" + attribute \src "libresoc.v:124527.3-124551.6" + wire width 64 $1\ibus_rdata$next[63:0]$5201 + attribute \src "libresoc.v:124396.14-124396.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:123415.3-123429.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5131 - attribute \src "libresoc.v:123397.3-123414.6" - wire $2\f_fetch_err_o$next[0:0]$5127 - attribute \src "libresoc.v:123379.3-123396.6" - wire width 45 $2\ibus__adr$next[44:0]$5123 - attribute \src "libresoc.v:123290.3-123312.6" - wire $2\ibus__cyc$next[0:0]$5103 - attribute \src "libresoc.v:123336.3-123358.6" - wire width 8 $2\ibus__sel$next[7:0]$5113 - attribute \src "libresoc.v:123313.3-123335.6" - wire $2\ibus__stb$next[0:0]$5108 - attribute \src "libresoc.v:123359.3-123378.6" - wire width 64 $2\ibus_rdata$next[63:0]$5118 - attribute \src "libresoc.v:123290.3-123312.6" - wire $3\ibus__cyc$next[0:0]$5104 - attribute \src "libresoc.v:123336.3-123358.6" - wire width 8 $3\ibus__sel$next[7:0]$5114 - attribute \src "libresoc.v:123313.3-123335.6" - wire $3\ibus__stb$next[0:0]$5109 - attribute \src "libresoc.v:123359.3-123378.6" - wire width 64 $3\ibus_rdata$next[63:0]$5119 - attribute \src "libresoc.v:123252.18-123252.110" - wire $and$libresoc.v:123252$5069_Y - attribute \src "libresoc.v:123258.18-123258.110" - wire $and$libresoc.v:123258$5075_Y - attribute \src "libresoc.v:123263.18-123263.110" - wire $and$libresoc.v:123263$5080_Y - attribute \src "libresoc.v:123266.17-123266.108" - wire $and$libresoc.v:123266$5083_Y - attribute \src "libresoc.v:123269.18-123269.110" - wire $and$libresoc.v:123269$5086_Y - attribute \src "libresoc.v:123270.18-123270.115" - wire $and$libresoc.v:123270$5087_Y - attribute \src "libresoc.v:123272.18-123272.115" - wire $and$libresoc.v:123272$5089_Y - attribute \src "libresoc.v:123251.18-123251.105" - wire $not$libresoc.v:123251$5068_Y - attribute \src "libresoc.v:123254.18-123254.105" - wire $not$libresoc.v:123254$5071_Y - attribute \src "libresoc.v:123255.17-123255.104" - wire $not$libresoc.v:123255$5072_Y - attribute \src "libresoc.v:123257.18-123257.105" - wire $not$libresoc.v:123257$5074_Y - attribute \src "libresoc.v:123260.18-123260.105" - wire $not$libresoc.v:123260$5077_Y - attribute \src "libresoc.v:123262.18-123262.105" - wire $not$libresoc.v:123262$5079_Y - attribute \src "libresoc.v:123265.18-123265.105" - wire $not$libresoc.v:123265$5082_Y - attribute \src "libresoc.v:123268.18-123268.105" - wire $not$libresoc.v:123268$5085_Y - attribute \src "libresoc.v:123271.18-123271.105" - wire $not$libresoc.v:123271$5088_Y - attribute \src "libresoc.v:123273.18-123273.105" - wire $not$libresoc.v:123273$5090_Y - attribute \src "libresoc.v:123275.17-123275.104" - wire $not$libresoc.v:123275$5092_Y - attribute \src "libresoc.v:123250.17-123250.103" - wire $or$libresoc.v:123250$5067_Y - attribute \src "libresoc.v:123253.18-123253.115" - wire $or$libresoc.v:123253$5070_Y - attribute \src "libresoc.v:123256.18-123256.106" - wire $or$libresoc.v:123256$5073_Y - attribute \src "libresoc.v:123259.18-123259.115" - wire $or$libresoc.v:123259$5076_Y - attribute \src "libresoc.v:123261.18-123261.106" - wire $or$libresoc.v:123261$5078_Y - attribute \src "libresoc.v:123264.18-123264.115" - wire $or$libresoc.v:123264$5081_Y - attribute \src "libresoc.v:123267.18-123267.106" - wire $or$libresoc.v:123267$5084_Y - attribute \src "libresoc.v:123274.17-123274.114" - wire $or$libresoc.v:123274$5091_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "libresoc.v:124598.3-124617.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5218 + attribute \src "libresoc.v:124628.3-124645.6" + wire $2\f_busy_o[0:0] + attribute \src "libresoc.v:124575.3-124597.6" + wire $2\f_fetch_err_o$next[0:0]$5213 + attribute \src "libresoc.v:124646.3-124663.6" + wire width 64 $2\f_instr_o[63:0] + attribute \src "libresoc.v:124552.3-124574.6" + wire width 45 $2\ibus__adr$next[44:0]$5208 + attribute \src "libresoc.v:124443.3-124470.6" + wire $2\ibus__cyc$next[0:0]$5184 + attribute \src "libresoc.v:124499.3-124526.6" + wire width 8 $2\ibus__sel$next[7:0]$5196 + attribute \src "libresoc.v:124471.3-124498.6" + wire $2\ibus__stb$next[0:0]$5190 + attribute \src "libresoc.v:124527.3-124551.6" + wire width 64 $2\ibus_rdata$next[63:0]$5202 + attribute \src "libresoc.v:124598.3-124617.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5219 + attribute \src "libresoc.v:124575.3-124597.6" + wire $3\f_fetch_err_o$next[0:0]$5214 + attribute \src "libresoc.v:124552.3-124574.6" + wire width 45 $3\ibus__adr$next[44:0]$5209 + attribute \src "libresoc.v:124443.3-124470.6" + wire $3\ibus__cyc$next[0:0]$5185 + attribute \src "libresoc.v:124499.3-124526.6" + wire width 8 $3\ibus__sel$next[7:0]$5197 + attribute \src "libresoc.v:124471.3-124498.6" + wire $3\ibus__stb$next[0:0]$5191 + attribute \src "libresoc.v:124527.3-124551.6" + wire width 64 $3\ibus_rdata$next[63:0]$5203 + attribute \src "libresoc.v:124443.3-124470.6" + wire $4\ibus__cyc$next[0:0]$5186 + attribute \src "libresoc.v:124499.3-124526.6" + wire width 8 $4\ibus__sel$next[7:0]$5198 + attribute \src "libresoc.v:124471.3-124498.6" + wire $4\ibus__stb$next[0:0]$5192 + attribute \src "libresoc.v:124527.3-124551.6" + wire width 64 $4\ibus_rdata$next[63:0]$5204 + attribute \src "libresoc.v:124405.18-124405.110" + wire $and$libresoc.v:124405$5150_Y + attribute \src "libresoc.v:124411.18-124411.110" + wire $and$libresoc.v:124411$5156_Y + attribute \src "libresoc.v:124416.18-124416.110" + wire $and$libresoc.v:124416$5161_Y + attribute \src "libresoc.v:124419.17-124419.108" + wire $and$libresoc.v:124419$5164_Y + attribute \src "libresoc.v:124422.18-124422.110" + wire $and$libresoc.v:124422$5167_Y + attribute \src "libresoc.v:124423.18-124423.115" + wire $and$libresoc.v:124423$5168_Y + attribute \src "libresoc.v:124425.18-124425.115" + wire $and$libresoc.v:124425$5170_Y + attribute \src "libresoc.v:124404.18-124404.105" + wire $not$libresoc.v:124404$5149_Y + attribute \src "libresoc.v:124407.18-124407.105" + wire $not$libresoc.v:124407$5152_Y + attribute \src "libresoc.v:124408.17-124408.104" + wire $not$libresoc.v:124408$5153_Y + attribute \src "libresoc.v:124410.18-124410.105" + wire $not$libresoc.v:124410$5155_Y + attribute \src "libresoc.v:124413.18-124413.105" + wire $not$libresoc.v:124413$5158_Y + attribute \src "libresoc.v:124415.18-124415.105" + wire $not$libresoc.v:124415$5160_Y + attribute \src "libresoc.v:124418.18-124418.105" + wire $not$libresoc.v:124418$5163_Y + attribute \src "libresoc.v:124421.18-124421.105" + wire $not$libresoc.v:124421$5166_Y + attribute \src "libresoc.v:124424.18-124424.105" + wire $not$libresoc.v:124424$5169_Y + attribute \src "libresoc.v:124426.18-124426.105" + wire $not$libresoc.v:124426$5171_Y + attribute \src "libresoc.v:124428.17-124428.104" + wire $not$libresoc.v:124428$5173_Y + attribute \src "libresoc.v:124403.17-124403.103" + wire $or$libresoc.v:124403$5148_Y + attribute \src "libresoc.v:124406.18-124406.115" + wire $or$libresoc.v:124406$5151_Y + attribute \src "libresoc.v:124409.18-124409.106" + wire $or$libresoc.v:124409$5154_Y + attribute \src "libresoc.v:124412.18-124412.115" + wire $or$libresoc.v:124412$5157_Y + attribute \src "libresoc.v:124414.18-124414.106" + wire $or$libresoc.v:124414$5159_Y + attribute \src "libresoc.v:124417.18-124417.115" + wire $or$libresoc.v:124417$5162_Y + attribute \src "libresoc.v:124420.18-124420.106" + wire $or$libresoc.v:124420$5165_Y + attribute \src "libresoc.v:124427.17-124427.114" + wire $or$libresoc.v:124427$5172_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" wire \a_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 1 \a_pc_i + wire width 48 input 2 \a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire input 2 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 14 \clk + wire input 3 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 4 \f_busy_o + wire output 5 \f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" wire \f_fetch_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" wire \f_fetch_err_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 5 \f_instr_o + wire width 64 output 6 \f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" wire \f_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 3 \f_valid_i + wire input 4 \f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 8 \ibus__ack + wire input 9 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 13 \ibus__adr + wire width 45 output 14 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 45 \ibus__adr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 7 \ibus__cyc + wire output 8 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire \ibus__cyc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 12 \ibus__dat_r + wire width 64 input 13 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__err + wire input 10 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 11 \ibus__sel + wire width 8 output 12 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire width 8 \ibus__sel$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 10 \ibus__stb + wire output 11 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:123137.7-123137.15" + attribute \src "libresoc.v:124288.7-124288.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 6 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:123252$5069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire input 7 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:124405$5150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193766,10 +196363,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:123252$5069_Y + connect \Y $and$libresoc.v:124405$5150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:123258$5075 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:124411$5156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193777,10 +196374,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:123258$5075_Y + connect \Y $and$libresoc.v:124411$5156_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:123263$5080 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:124416$5161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193788,10 +196385,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:123263$5080_Y + connect \Y $and$libresoc.v:124416$5161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:123266$5083 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:124419$5164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193799,10 +196396,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:123266$5083_Y + connect \Y $and$libresoc.v:124419$5164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $and$libresoc.v:123269$5086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:124422$5167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193810,10 +196407,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:123269$5086_Y + connect \Y $and$libresoc.v:124422$5167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$libresoc.v:123270$5087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:124423$5168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193821,10 +196418,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:123270$5087_Y + connect \Y $and$libresoc.v:124423$5168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $and$libresoc.v:123272$5089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:124425$5170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193832,98 +196429,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:123272$5089_Y + connect \Y $and$libresoc.v:124425$5170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:123251$5068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:124404$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:123251$5068_Y + connect \Y $not$libresoc.v:124404$5149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:123254$5071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:124407$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:123254$5071_Y + connect \Y $not$libresoc.v:124407$5152_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:123255$5072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:124408$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:123255$5072_Y + connect \Y $not$libresoc.v:124408$5153_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:123257$5074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:124410$5155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:123257$5074_Y + connect \Y $not$libresoc.v:124410$5155_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:123260$5077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:124413$5158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:123260$5077_Y + connect \Y $not$libresoc.v:124413$5158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:123262$5079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:124415$5160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:123262$5079_Y + connect \Y $not$libresoc.v:124415$5160_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:123265$5082 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:124418$5163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:123265$5082_Y + connect \Y $not$libresoc.v:124418$5163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $not$libresoc.v:123268$5085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:124421$5166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:123268$5085_Y + connect \Y $not$libresoc.v:124421$5166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$libresoc.v:123271$5088 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:124424$5169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:123271$5088_Y + connect \Y $not$libresoc.v:124424$5169_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $not$libresoc.v:123273$5090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:124426$5171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:123273$5090_Y + connect \Y $not$libresoc.v:124426$5171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $not$libresoc.v:123275$5092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:124428$5173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:123275$5092_Y + connect \Y $not$libresoc.v:124428$5173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123250$5067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124403$5148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193931,10 +196528,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:123250$5067_Y + connect \Y $or$libresoc.v:124403$5148_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123253$5070 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124406$5151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193942,10 +196539,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:123253$5070_Y + connect \Y $or$libresoc.v:124406$5151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123256$5073 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124409$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193953,10 +196550,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:123256$5073_Y + connect \Y $or$libresoc.v:124409$5154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123259$5076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124412$5157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193964,10 +196561,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:123259$5076_Y + connect \Y $or$libresoc.v:124412$5157_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123261$5078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124414$5159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193975,10 +196572,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:123261$5078_Y + connect \Y $or$libresoc.v:124414$5159_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123264$5081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124417$5162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193986,10 +196583,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:123264$5081_Y + connect \Y $or$libresoc.v:124417$5162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123267$5084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124420$5165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193997,10 +196594,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:123267$5084_Y + connect \Y $or$libresoc.v:124420$5165_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $or$libresoc.v:123274$5091 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:124427$5172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194008,502 +196605,606 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:123274$5091_Y + connect \Y $or$libresoc.v:124427$5172_Y end - attribute \src "libresoc.v:123137.7-123137.20" - process $proc$libresoc.v:123137$5134 + attribute \src "libresoc.v:124288.7-124288.20" + process $proc$libresoc.v:124288$5223 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123201.14-123201.44" - process $proc$libresoc.v:123201$5135 + attribute \src "libresoc.v:124352.14-124352.44" + process $proc$libresoc.v:124352$5224 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:123208.7-123208.27" - process $proc$libresoc.v:123208$5136 + attribute \src "libresoc.v:124359.7-124359.27" + process $proc$libresoc.v:124359$5225 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:123222.14-123222.42" - process $proc$libresoc.v:123222$5137 + attribute \src "libresoc.v:124373.14-124373.42" + process $proc$libresoc.v:124373$5226 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:123227.7-123227.23" - process $proc$libresoc.v:123227$5138 + attribute \src "libresoc.v:124378.7-124378.23" + process $proc$libresoc.v:124378$5227 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:123236.13-123236.30" - process $proc$libresoc.v:123236$5139 + attribute \src "libresoc.v:124387.13-124387.30" + process $proc$libresoc.v:124387$5228 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:123241.7-123241.23" - process $proc$libresoc.v:123241$5140 + attribute \src "libresoc.v:124392.7-124392.23" + process $proc$libresoc.v:124392$5229 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:123245.14-123245.47" - process $proc$libresoc.v:123245$5141 + attribute \src "libresoc.v:124396.14-124396.47" + process $proc$libresoc.v:124396$5230 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:123276.3-123277.39" - process $proc$libresoc.v:123276$5093 + attribute \src "libresoc.v:124429.3-124430.39" + process $proc$libresoc.v:124429$5174 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:123278.3-123279.43" - process $proc$libresoc.v:123278$5094 + attribute \src "libresoc.v:124431.3-124432.43" + process $proc$libresoc.v:124431$5175 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:123280.3-123281.35" - process $proc$libresoc.v:123280$5095 + attribute \src "libresoc.v:124433.3-124434.35" + process $proc$libresoc.v:124433$5176 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:123282.3-123283.37" - process $proc$libresoc.v:123282$5096 + attribute \src "libresoc.v:124435.3-124436.37" + process $proc$libresoc.v:124435$5177 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:123284.3-123285.35" - process $proc$libresoc.v:123284$5097 + attribute \src "libresoc.v:124437.3-124438.35" + process $proc$libresoc.v:124437$5178 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:123286.3-123287.35" - process $proc$libresoc.v:123286$5098 + attribute \src "libresoc.v:124439.3-124440.35" + process $proc$libresoc.v:124439$5179 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:123288.3-123289.35" - process $proc$libresoc.v:123288$5099 + attribute \src "libresoc.v:124441.3-124442.35" + process $proc$libresoc.v:124441$5180 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:123290.3-123312.6" - process $proc$libresoc.v:123290$5100 + attribute \src "libresoc.v:124443.3-124470.6" + process $proc$libresoc.v:124443$5181 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5101 $3\ibus__cyc$next[0:0]$5104 - attribute \src "libresoc.v:123291.5-123291.29" + assign $0\ibus__cyc$next[0:0]$5182 $4\ibus__cyc$next[0:0]$5186 + attribute \src "libresoc.v:124444.5-124444.29" switch \initial - attribute \src "libresoc.v:123291.9-123291.17" + attribute \src "libresoc.v:124444.9-124444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$3 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5102 $2\ibus__cyc$next[0:0]$5103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$9 + assign $1\ibus__cyc$next[0:0]$5183 $2\ibus__cyc$next[0:0]$5184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5103 1'0 + assign $2\ibus__cyc$next[0:0]$5184 $3\ibus__cyc$next[0:0]$5185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5185 1'0 + case + assign $3\ibus__cyc$next[0:0]$5185 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$5184 1'1 case - assign $2\ibus__cyc$next[0:0]$5103 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5184 \ibus__cyc end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__cyc$next[0:0]$5102 1'1 case - assign $1\ibus__cyc$next[0:0]$5102 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5183 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5104 1'0 + assign $4\ibus__cyc$next[0:0]$5186 1'0 case - assign $3\ibus__cyc$next[0:0]$5104 $1\ibus__cyc$next[0:0]$5102 + assign $4\ibus__cyc$next[0:0]$5186 $1\ibus__cyc$next[0:0]$5183 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5101 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5182 end - attribute \src "libresoc.v:123313.3-123335.6" - process $proc$libresoc.v:123313$5105 + attribute \src "libresoc.v:124471.3-124498.6" + process $proc$libresoc.v:124471$5187 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5106 $3\ibus__stb$next[0:0]$5109 - attribute \src "libresoc.v:123314.5-123314.29" + assign $0\ibus__stb$next[0:0]$5188 $4\ibus__stb$next[0:0]$5192 + attribute \src "libresoc.v:124472.5-124472.29" switch \initial - attribute \src "libresoc.v:123314.9-123314.17" + attribute \src "libresoc.v:124472.9-124472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$13 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5107 $2\ibus__stb$next[0:0]$5108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$19 + assign $1\ibus__stb$next[0:0]$5189 $2\ibus__stb$next[0:0]$5190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5190 $3\ibus__stb$next[0:0]$5191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5191 1'0 + case + assign $3\ibus__stb$next[0:0]$5191 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5108 1'0 + assign $2\ibus__stb$next[0:0]$5190 1'1 case - assign $2\ibus__stb$next[0:0]$5108 \ibus__stb + assign $2\ibus__stb$next[0:0]$5190 \ibus__stb end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__stb$next[0:0]$5107 1'1 case - assign $1\ibus__stb$next[0:0]$5107 \ibus__stb + assign $1\ibus__stb$next[0:0]$5189 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5109 1'0 + assign $4\ibus__stb$next[0:0]$5192 1'0 case - assign $3\ibus__stb$next[0:0]$5109 $1\ibus__stb$next[0:0]$5107 + assign $4\ibus__stb$next[0:0]$5192 $1\ibus__stb$next[0:0]$5189 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5106 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5188 end - attribute \src "libresoc.v:123336.3-123358.6" - process $proc$libresoc.v:123336$5110 + attribute \src "libresoc.v:124499.3-124526.6" + process $proc$libresoc.v:124499$5193 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5111 $3\ibus__sel$next[7:0]$5114 - attribute \src "libresoc.v:123337.5-123337.29" + assign $0\ibus__sel$next[7:0]$5194 $4\ibus__sel$next[7:0]$5198 + attribute \src "libresoc.v:124500.5-124500.29" switch \initial - attribute \src "libresoc.v:123337.9-123337.17" + attribute \src "libresoc.v:124500.9-124500.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$23 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5112 $2\ibus__sel$next[7:0]$5113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$29 + assign $1\ibus__sel$next[7:0]$5195 $2\ibus__sel$next[7:0]$5196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5113 8'00000000 + assign $2\ibus__sel$next[7:0]$5196 $3\ibus__sel$next[7:0]$5197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5197 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5197 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$5196 8'11111111 case - assign $2\ibus__sel$next[7:0]$5113 \ibus__sel + assign $2\ibus__sel$next[7:0]$5196 \ibus__sel end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ibus__sel$next[7:0]$5112 8'11111111 case - assign $1\ibus__sel$next[7:0]$5112 \ibus__sel + assign $1\ibus__sel$next[7:0]$5195 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5114 8'00000000 + assign $4\ibus__sel$next[7:0]$5198 8'00000000 case - assign $3\ibus__sel$next[7:0]$5114 $1\ibus__sel$next[7:0]$5112 + assign $4\ibus__sel$next[7:0]$5198 $1\ibus__sel$next[7:0]$5195 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5111 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5194 end - attribute \src "libresoc.v:123359.3-123378.6" - process $proc$libresoc.v:123359$5115 + attribute \src "libresoc.v:124527.3-124551.6" + process $proc$libresoc.v:124527$5199 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5116 $3\ibus_rdata$next[63:0]$5119 - attribute \src "libresoc.v:123360.5-123360.29" + assign $0\ibus_rdata$next[63:0]$5200 $4\ibus_rdata$next[63:0]$5204 + attribute \src "libresoc.v:124528.5-124528.29" switch \initial - attribute \src "libresoc.v:123360.9-123360.17" + attribute \src "libresoc.v:124528.9-124528.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$33 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5117 $2\ibus_rdata$next[63:0]$5118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch \$39 + assign $1\ibus_rdata$next[63:0]$5201 $2\ibus_rdata$next[63:0]$5202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5118 \ibus__dat_r + assign $2\ibus_rdata$next[63:0]$5202 $3\ibus_rdata$next[63:0]$5203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5203 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$5203 \ibus_rdata + end case - assign $2\ibus_rdata$next[63:0]$5118 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5202 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5117 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5201 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5119 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5204 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\ibus_rdata$next[63:0]$5119 $1\ibus_rdata$next[63:0]$5117 + assign $4\ibus_rdata$next[63:0]$5204 $1\ibus_rdata$next[63:0]$5201 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5116 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5200 end - attribute \src "libresoc.v:123379.3-123396.6" - process $proc$libresoc.v:123379$5120 + attribute \src "libresoc.v:124552.3-124574.6" + process $proc$libresoc.v:124552$5205 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5121 $2\ibus__adr$next[44:0]$5123 - attribute \src "libresoc.v:123380.5-123380.29" + assign $0\ibus__adr$next[44:0]$5206 $3\ibus__adr$next[44:0]$5209 + attribute \src "libresoc.v:124553.5-124553.29" switch \initial - attribute \src "libresoc.v:123380.9-123380.17" + attribute \src "libresoc.v:124553.9-124553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { \$43 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $1\ibus__adr$next[44:0]$5122 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5122 \a_pc_i [47:3] + assign $1\ibus__adr$next[44:0]$5207 $2\ibus__adr$next[44:0]$5208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$5208 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$5208 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$5208 \ibus__adr + end case - assign $1\ibus__adr$next[44:0]$5122 \ibus__adr + assign $1\ibus__adr$next[44:0]$5207 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ibus__adr$next[44:0]$5123 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5209 45'000000000000000000000000000000000000000000000 case - assign $2\ibus__adr$next[44:0]$5123 $1\ibus__adr$next[44:0]$5122 + assign $3\ibus__adr$next[44:0]$5209 $1\ibus__adr$next[44:0]$5207 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5121 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5206 end - attribute \src "libresoc.v:123397.3-123414.6" - process $proc$libresoc.v:123397$5124 + attribute \src "libresoc.v:124575.3-124597.6" + process $proc$libresoc.v:124575$5210 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5125 $2\f_fetch_err_o$next[0:0]$5127 - attribute \src "libresoc.v:123398.5-123398.29" + assign $0\f_fetch_err_o$next[0:0]$5211 $3\f_fetch_err_o$next[0:0]$5214 + attribute \src "libresoc.v:124576.5-124576.29" switch \initial - attribute \src "libresoc.v:123398.9-123398.17" + attribute \src "libresoc.v:124576.9-124576.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$47 \$45 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5126 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5126 1'0 + assign $1\f_fetch_err_o$next[0:0]$5212 $2\f_fetch_err_o$next[0:0]$5213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5213 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5213 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5213 \f_fetch_err_o + end case - assign $1\f_fetch_err_o$next[0:0]$5126 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5212 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5127 1'0 + assign $3\f_fetch_err_o$next[0:0]$5214 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5127 $1\f_fetch_err_o$next[0:0]$5126 + assign $3\f_fetch_err_o$next[0:0]$5214 $1\f_fetch_err_o$next[0:0]$5212 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5125 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5211 end - attribute \src "libresoc.v:123415.3-123429.6" - process $proc$libresoc.v:123415$5128 + attribute \src "libresoc.v:124598.3-124617.6" + process $proc$libresoc.v:124598$5215 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5129 $2\f_badaddr_o$next[44:0]$5131 - attribute \src "libresoc.v:123416.5-123416.29" + assign $0\f_badaddr_o$next[44:0]$5216 $3\f_badaddr_o$next[44:0]$5219 + attribute \src "libresoc.v:124599.5-124599.29" switch \initial - attribute \src "libresoc.v:123416.9-123416.17" + attribute \src "libresoc.v:124599.9-124599.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { \$51 \$49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5130 \ibus__adr + assign $1\f_badaddr_o$next[44:0]$5217 $2\f_badaddr_o$next[44:0]$5218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5218 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$5218 \f_badaddr_o + end case - assign $1\f_badaddr_o$next[44:0]$5130 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5217 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5131 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5219 45'000000000000000000000000000000000000000000000 case - assign $2\f_badaddr_o$next[44:0]$5131 $1\f_badaddr_o$next[44:0]$5130 + assign $3\f_badaddr_o$next[44:0]$5219 $1\f_badaddr_o$next[44:0]$5217 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5129 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5216 end - attribute \src "libresoc.v:123430.3-123441.6" - process $proc$libresoc.v:123430$5132 + attribute \src "libresoc.v:124618.3-124627.6" + process $proc$libresoc.v:124618$5220 assign { } { } - assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:123431.5-123431.29" + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:124619.5-124619.29" switch \initial - attribute \src "libresoc.v:123431.9-123431.17" + attribute \src "libresoc.v:124619.9-124619.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $1\a_busy_o[0:0] \ibus__cyc case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:124628.3-124645.6" + process $proc$libresoc.v:124628$5221 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:124629.5-124629.29" + switch \initial + attribute \src "libresoc.v:124629.9-124629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\f_busy_o[0:0] \ibus__cyc + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 end sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:123442.3-123454.6" - process $proc$libresoc.v:123442$5133 + attribute \src "libresoc.v:124646.3-124663.6" + process $proc$libresoc.v:124646$5222 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:123443.5-123443.29" + attribute \src "libresoc.v:124647.5-124647.29" switch \initial - attribute \src "libresoc.v:123443.9-123443.17" + attribute \src "libresoc.v:124647.9-124647.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } - assign $1\f_instr_o[63:0] \ibus_rdata + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:123250$5067_Y - connect \$11 $not$libresoc.v:123251$5068_Y - connect \$13 $and$libresoc.v:123252$5069_Y - connect \$15 $or$libresoc.v:123253$5070_Y - connect \$17 $not$libresoc.v:123254$5071_Y - connect \$1 $not$libresoc.v:123255$5072_Y - connect \$19 $or$libresoc.v:123256$5073_Y - connect \$21 $not$libresoc.v:123257$5074_Y - connect \$23 $and$libresoc.v:123258$5075_Y - connect \$25 $or$libresoc.v:123259$5076_Y - connect \$27 $not$libresoc.v:123260$5077_Y - connect \$29 $or$libresoc.v:123261$5078_Y - connect \$31 $not$libresoc.v:123262$5079_Y - connect \$33 $and$libresoc.v:123263$5080_Y - connect \$35 $or$libresoc.v:123264$5081_Y - connect \$37 $not$libresoc.v:123265$5082_Y - connect \$3 $and$libresoc.v:123266$5083_Y - connect \$39 $or$libresoc.v:123267$5084_Y - connect \$41 $not$libresoc.v:123268$5085_Y - connect \$43 $and$libresoc.v:123269$5086_Y - connect \$45 $and$libresoc.v:123270$5087_Y - connect \$47 $not$libresoc.v:123271$5088_Y - connect \$49 $and$libresoc.v:123272$5089_Y - connect \$51 $not$libresoc.v:123273$5090_Y - connect \$5 $or$libresoc.v:123274$5091_Y - connect \$7 $not$libresoc.v:123275$5092_Y + connect \$9 $or$libresoc.v:124403$5148_Y + connect \$11 $not$libresoc.v:124404$5149_Y + connect \$13 $and$libresoc.v:124405$5150_Y + connect \$15 $or$libresoc.v:124406$5151_Y + connect \$17 $not$libresoc.v:124407$5152_Y + connect \$1 $not$libresoc.v:124408$5153_Y + connect \$19 $or$libresoc.v:124409$5154_Y + connect \$21 $not$libresoc.v:124410$5155_Y + connect \$23 $and$libresoc.v:124411$5156_Y + connect \$25 $or$libresoc.v:124412$5157_Y + connect \$27 $not$libresoc.v:124413$5158_Y + connect \$29 $or$libresoc.v:124414$5159_Y + connect \$31 $not$libresoc.v:124415$5160_Y + connect \$33 $and$libresoc.v:124416$5161_Y + connect \$35 $or$libresoc.v:124417$5162_Y + connect \$37 $not$libresoc.v:124418$5163_Y + connect \$3 $and$libresoc.v:124419$5164_Y + connect \$39 $or$libresoc.v:124420$5165_Y + connect \$41 $not$libresoc.v:124421$5166_Y + connect \$43 $and$libresoc.v:124422$5167_Y + connect \$45 $and$libresoc.v:124423$5168_Y + connect \$47 $not$libresoc.v:124424$5169_Y + connect \$49 $and$libresoc.v:124425$5170_Y + connect \$51 $not$libresoc.v:124426$5171_Y + connect \$5 $or$libresoc.v:124427$5172_Y + connect \$7 $not$libresoc.v:124428$5173_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 - connect \a_busy_o \ibus__cyc end -attribute \src "libresoc.v:123462.1-123783.10" +attribute \src "libresoc.v:124670.1-124991.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:123746.3-123757.6" + attribute \src "libresoc.v:124954.3-124965.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:123463.7-123463.20" + attribute \src "libresoc.v:124671.7-124671.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123758.3-123776.6" - wire width 2 $0\xer_ca$23[1:0]$5145 - attribute \src "libresoc.v:123746.3-123757.6" + attribute \src "libresoc.v:124966.3-124984.6" + wire width 2 $0\xer_ca$23[1:0]$5234 + attribute \src "libresoc.v:124954.3-124965.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:123758.3-123776.6" - wire width 2 $1\xer_ca$23[1:0]$5146 - attribute \src "libresoc.v:123745.18-123745.100" - wire width 64 $not$libresoc.v:123745$5142_Y + attribute \src "libresoc.v:124966.3-124984.6" + wire width 2 $1\xer_ca$23[1:0]$5235 + attribute \src "libresoc.v:124953.18-124953.100" + wire width 64 $not$libresoc.v:124953$5231_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -194764,7 +197465,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:123463.7-123463.15" + attribute \src "libresoc.v:124671.7-124671.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 46 \muxid @@ -194787,28 +197488,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:123745$5142 + cell $not $not$libresoc.v:124953$5231 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:123745$5142_Y + connect \Y $not$libresoc.v:124953$5231_Y end - attribute \src "libresoc.v:123463.7-123463.20" - process $proc$libresoc.v:123463$5147 + attribute \src "libresoc.v:124671.7-124671.20" + process $proc$libresoc.v:124671$5236 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123746.3-123757.6" - process $proc$libresoc.v:123746$5143 + attribute \src "libresoc.v:124954.3-124965.6" + process $proc$libresoc.v:124954$5232 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:123747.5-123747.29" + attribute \src "libresoc.v:124955.5-124955.29" switch \initial - attribute \src "libresoc.v:123747.9-123747.17" + attribute \src "libresoc.v:124955.9-124955.17" case 1'1 case end @@ -194826,14 +197527,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:123758.3-123776.6" - process $proc$libresoc.v:123758$5144 + attribute \src "libresoc.v:124966.3-124984.6" + process $proc$libresoc.v:124966$5233 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5145 $1\xer_ca$23[1:0]$5146 - attribute \src "libresoc.v:123759.5-123759.29" + assign $0\xer_ca$23[1:0]$5234 $1\xer_ca$23[1:0]$5235 + attribute \src "libresoc.v:124967.5-124967.29" switch \initial - attribute \src "libresoc.v:123759.9-123759.17" + attribute \src "libresoc.v:124967.9-124967.17" case 1'1 case end @@ -194842,22 +197543,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5146 2'00 + assign $1\xer_ca$23[1:0]$5235 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5146 2'11 + assign $1\xer_ca$23[1:0]$5235 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5146 \xer_ca + assign $1\xer_ca$23[1:0]$5235 \xer_ca case - assign $1\xer_ca$23[1:0]$5146 2'00 + assign $1\xer_ca$23[1:0]$5235 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5145 + update \xer_ca$23 $0\xer_ca$23[1:0]$5234 end - connect \$24 $not$libresoc.v:123745$5142_Y + connect \$24 $not$libresoc.v:124953$5231_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -194865,39 +197566,47 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:123787.1-124091.10" +attribute \src "libresoc.v:124995.1-125317.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" -module \input$110 - attribute \src "libresoc.v:123788.7-123788.20" +module \input$113 + attribute \src "libresoc.v:125279.3-125290.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:124996.7-124996.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124064.3-124082.6" - wire width 2 $0\xer_ca$22[1:0]$5149 - attribute \src "libresoc.v:124064.3-124082.6" - wire width 2 $1\xer_ca$22[1:0]$5150 + attribute \src "libresoc.v:125291.3-125309.6" + wire width 2 $0\xer_ca$23[1:0]$5240 + attribute \src "libresoc.v:125279.3-125290.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:125291.3-125309.6" + wire width 2 $1\xer_ca$23[1:0]$5241 + attribute \src "libresoc.v:125278.18-125278.100" + wire width 64 $not$libresoc.v:125278$5237_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:123788.7-123788.15" + attribute \src "libresoc.v:124996.7-124996.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid + wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 + wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra + wire width 64 input 18 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 39 \ra$18 + wire width 64 output 41 \ra$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb + wire width 64 input 19 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \rb$19 + wire width 64 output 42 \rb$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rc + wire width 64 input 20 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \rc$20 + wire width 64 output 43 \rc$21 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -194927,35 +197636,35 @@ module \input$110 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \sr_op__fn_unit$3 + wire width 12 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \sr_op__imm_data__data$4 + wire width 64 output 26 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \sr_op__imm_data__ok$5 + wire output 27 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry + wire width 2 input 11 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \sr_op__input_carry$11 + wire width 2 output 34 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__input_cr + wire input 13 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \sr_op__input_cr$13 + wire output 36 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn + wire width 32 input 17 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 38 \sr_op__insn$17 + wire width 32 output 40 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -195107,67 +197816,103 @@ module \input$110 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \sr_op__insn_type$2 + wire width 7 output 24 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__is_32bit + wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__is_32bit$15 + wire output 33 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_signed + wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__is_signed$16 + wire output 38 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__oe__oe$8 + wire output 30 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__ok$9 + wire output 31 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__output_carry + wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__output_carry$12 + wire output 35 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__output_cr + wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_cr$14 + wire output 37 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__ok$7 + wire output 29 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__rc__rc$6 + wire output 28 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__write_cr0$10 + wire output 32 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 21 \xer_ca + wire width 2 input 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 43 \xer_ca$22 + wire width 2 output 45 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 20 \xer_so + wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 42 \xer_so$21 - attribute \src "libresoc.v:123788.7-123788.20" - process $proc$libresoc.v:123788$5151 + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:125278$5237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:125278$5237_Y + end + attribute \src "libresoc.v:124996.7-124996.20" + process $proc$libresoc.v:124996$5242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124064.3-124082.6" - process $proc$libresoc.v:124064$5148 + attribute \src "libresoc.v:125279.3-125290.6" + process $proc$libresoc.v:125279$5238 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:125280.5-125280.29" + switch \initial + attribute \src "libresoc.v:125280.9-125280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \sr_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:125291.3-125309.6" + process $proc$libresoc.v:125291$5239 assign { } { } assign { } { } - assign $0\xer_ca$22[1:0]$5149 $1\xer_ca$22[1:0]$5150 - attribute \src "libresoc.v:124065.5-124065.29" + assign $0\xer_ca$23[1:0]$5240 $1\xer_ca$23[1:0]$5241 + attribute \src "libresoc.v:125292.5-125292.29" switch \initial - attribute \src "libresoc.v:124065.9-124065.17" + attribute \src "libresoc.v:125292.9-125292.17" case 1'1 case end @@ -195176,50 +197921,50 @@ module \input$110 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$22[1:0]$5150 2'00 + assign $1\xer_ca$23[1:0]$5241 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$22[1:0]$5150 2'11 + assign $1\xer_ca$23[1:0]$5241 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$22[1:0]$5150 \xer_ca + assign $1\xer_ca$23[1:0]$5241 \xer_ca case - assign $1\xer_ca$22[1:0]$5150 2'00 + assign $1\xer_ca$23[1:0]$5241 2'00 end sync always - update \xer_ca$22 $0\xer_ca$22[1:0]$5149 + update \xer_ca$23 $0\xer_ca$23[1:0]$5240 end - connect \rc$20 \rc - connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \$24 $not$libresoc.v:125278$5237_Y + connect \rc$21 \rc + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid - connect \xer_so$21 \xer_so - connect \rb$19 \b + connect \xer_so$22 \xer_so + connect \rb$20 \b connect \b \rb - connect \ra$18 \a - connect \a \ra + connect \ra$19 \a end -attribute \src "libresoc.v:124095.1-124392.10" +attribute \src "libresoc.v:125321.1-125618.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" -module \input$47 - attribute \src "libresoc.v:124374.3-124385.6" +module \input$50 + attribute \src "libresoc.v:125600.3-125611.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:124096.7-124096.20" + attribute \src "libresoc.v:125322.7-125322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124374.3-124385.6" + attribute \src "libresoc.v:125600.3-125611.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:124373.18-124373.100" - wire width 64 $not$libresoc.v:124373$5152_Y + attribute \src "libresoc.v:125599.18-125599.100" + wire width 64 $not$libresoc.v:125599$5243_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:124096.7-124096.15" + attribute \src "libresoc.v:125322.7-125322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -195492,28 +198237,28 @@ module \input$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:124373$5152 + cell $not $not$libresoc.v:125599$5243 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:124373$5152_Y + connect \Y $not$libresoc.v:125599$5243_Y end - attribute \src "libresoc.v:124096.7-124096.20" - process $proc$libresoc.v:124096$5154 + attribute \src "libresoc.v:125322.7-125322.20" + process $proc$libresoc.v:125322$5245 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124374.3-124385.6" - process $proc$libresoc.v:124374$5153 + attribute \src "libresoc.v:125600.3-125611.6" + process $proc$libresoc.v:125600$5244 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:124375.5-124375.29" + attribute \src "libresoc.v:125601.5-125601.29" switch \initial - attribute \src "libresoc.v:124375.9-124375.17" + attribute \src "libresoc.v:125601.9-125601.17" case 1'1 case end @@ -195531,7 +198276,7 @@ module \input$47 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:124373$5152_Y + connect \$23 $not$libresoc.v:125599$5243_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -195539,26 +198284,26 @@ module \input$47 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:124396.1-124693.10" +attribute \src "libresoc.v:125622.1-125919.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" -module \input$75 - attribute \src "libresoc.v:124675.3-124686.6" +module \input$78 + attribute \src "libresoc.v:125901.3-125912.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:124397.7-124397.20" + attribute \src "libresoc.v:125623.7-125623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124675.3-124686.6" + attribute \src "libresoc.v:125901.3-125912.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:124674.18-124674.100" - wire width 64 $not$libresoc.v:124674$5155_Y + attribute \src "libresoc.v:125900.18-125900.100" + wire width 64 $not$libresoc.v:125900$5246_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:124397.7-124397.15" + attribute \src "libresoc.v:125623.7-125623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -195831,28 +198576,28 @@ module \input$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:124674$5155 + cell $not $not$libresoc.v:125900$5246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:124674$5155_Y + connect \Y $not$libresoc.v:125900$5246_Y end - attribute \src "libresoc.v:124397.7-124397.20" - process $proc$libresoc.v:124397$5157 + attribute \src "libresoc.v:125623.7-125623.20" + process $proc$libresoc.v:125623$5248 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124675.3-124686.6" - process $proc$libresoc.v:124675$5156 + attribute \src "libresoc.v:125901.3-125912.6" + process $proc$libresoc.v:125901$5247 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:124676.5-124676.29" + attribute \src "libresoc.v:125902.5-125902.29" switch \initial - attribute \src "libresoc.v:124676.9-124676.17" + attribute \src "libresoc.v:125902.9-125902.17" case 1'1 case end @@ -195870,7 +198615,7 @@ module \input$75 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:124674$5155_Y + connect \$23 $not$libresoc.v:125900$5246_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -195878,11 +198623,11 @@ module \input$75 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:124697.1-124947.10" +attribute \src "libresoc.v:125923.1-126173.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" -module \input$92 +module \input$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" @@ -196133,114 +198878,114 @@ module \input$92 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:124951.1-125170.10" +attribute \src "libresoc.v:126177.1-126396.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.int" +attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:125076.3-125082.6" - wire width 5 $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 - attribute \src "libresoc.v:125076.3-125082.6" - wire width 64 $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 - attribute \src "libresoc.v:125076.3-125082.6" - wire width 64 $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 - attribute \src "libresoc.v:125076.3-125082.6" + attribute \src "libresoc.v:126302.3-126308.6" + wire width 5 $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 + attribute \src "libresoc.v:126302.3-126308.6" + wire width 64 $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 + attribute \src "libresoc.v:126302.3-126308.6" + wire width 64 $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 + attribute \src "libresoc.v:126302.3-126308.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:125076.3-125082.6" + attribute \src "libresoc.v:126302.3-126308.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:125076.3-125082.6" + attribute \src "libresoc.v:126302.3-126308.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:125076.3-125082.6" + attribute \src "libresoc.v:126302.3-126308.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:125105.3-125114.6" + attribute \src "libresoc.v:126331.3-126340.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:124952.7-124952.20" + attribute \src "libresoc.v:126178.7-126178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125096.3-125104.6" - wire $0\ren_delay$10$next[0:0]$5210 - attribute \src "libresoc.v:125029.3-125030.43" - wire $0\ren_delay$10[0:0]$5192 - attribute \src "libresoc.v:124995.7-124995.28" - wire $0\ren_delay$10[0:0]$5258 - attribute \src "libresoc.v:125125.3-125133.6" - wire $0\ren_delay$8$next[0:0]$5215 - attribute \src "libresoc.v:125033.3-125034.41" - wire $0\ren_delay$8[0:0]$5196 - attribute \src "libresoc.v:124999.7-124999.27" - wire $0\ren_delay$8[0:0]$5260 - attribute \src "libresoc.v:125144.3-125152.6" - wire $0\ren_delay$9$next[0:0]$5219 - attribute \src "libresoc.v:125031.3-125032.41" - wire $0\ren_delay$9[0:0]$5194 - attribute \src "libresoc.v:125003.7-125003.27" - wire $0\ren_delay$9[0:0]$5262 - attribute \src "libresoc.v:125087.3-125095.6" - wire $0\ren_delay$next[0:0]$5207 - attribute \src "libresoc.v:125035.3-125036.35" + attribute \src "libresoc.v:126322.3-126330.6" + wire $0\ren_delay$10$next[0:0]$5301 + attribute \src "libresoc.v:126255.3-126256.43" + wire $0\ren_delay$10[0:0]$5283 + attribute \src "libresoc.v:126221.7-126221.28" + wire $0\ren_delay$10[0:0]$5349 + attribute \src "libresoc.v:126351.3-126359.6" + wire $0\ren_delay$8$next[0:0]$5306 + attribute \src "libresoc.v:126259.3-126260.41" + wire $0\ren_delay$8[0:0]$5287 + attribute \src "libresoc.v:126225.7-126225.27" + wire $0\ren_delay$8[0:0]$5351 + attribute \src "libresoc.v:126370.3-126378.6" + wire $0\ren_delay$9$next[0:0]$5310 + attribute \src "libresoc.v:126257.3-126258.41" + wire $0\ren_delay$9[0:0]$5285 + attribute \src "libresoc.v:126229.7-126229.27" + wire $0\ren_delay$9[0:0]$5353 + attribute \src "libresoc.v:126313.3-126321.6" + wire $0\ren_delay$next[0:0]$5298 + attribute \src "libresoc.v:126261.3-126262.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:125115.3-125124.6" + attribute \src "libresoc.v:126341.3-126350.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:125134.3-125143.6" + attribute \src "libresoc.v:126360.3-126369.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:125153.3-125162.6" + attribute \src "libresoc.v:126379.3-126388.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:125105.3-125114.6" + attribute \src "libresoc.v:126331.3-126340.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:125096.3-125104.6" - wire $1\ren_delay$10$next[0:0]$5211 - attribute \src "libresoc.v:125125.3-125133.6" - wire $1\ren_delay$8$next[0:0]$5216 - attribute \src "libresoc.v:125144.3-125152.6" - wire $1\ren_delay$9$next[0:0]$5220 - attribute \src "libresoc.v:125087.3-125095.6" - wire $1\ren_delay$next[0:0]$5208 - attribute \src "libresoc.v:124993.7-124993.23" + attribute \src "libresoc.v:126322.3-126330.6" + wire $1\ren_delay$10$next[0:0]$5302 + attribute \src "libresoc.v:126351.3-126359.6" + wire $1\ren_delay$8$next[0:0]$5307 + attribute \src "libresoc.v:126370.3-126378.6" + wire $1\ren_delay$9$next[0:0]$5311 + attribute \src "libresoc.v:126313.3-126321.6" + wire $1\ren_delay$next[0:0]$5299 + attribute \src "libresoc.v:126219.7-126219.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:125115.3-125124.6" + attribute \src "libresoc.v:126341.3-126350.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:125134.3-125143.6" + attribute \src "libresoc.v:126360.3-126369.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:125153.3-125162.6" + attribute \src "libresoc.v:126379.3-126388.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:125083.26-125083.32" - wire width 64 $memrd$\memory$libresoc.v:125083$5202_DATA - attribute \src "libresoc.v:125084.30-125084.36" - wire width 64 $memrd$\memory$libresoc.v:125084$5203_DATA - attribute \src "libresoc.v:125085.30-125085.36" - wire width 64 $memrd$\memory$libresoc.v:125085$5204_DATA - attribute \src "libresoc.v:125086.30-125086.36" - wire width 64 $memrd$\memory$libresoc.v:125086$5205_DATA + attribute \src "libresoc.v:126309.26-126309.32" + wire width 64 $memrd$\memory$libresoc.v:126309$5293_DATA + attribute \src "libresoc.v:126310.30-126310.36" + wire width 64 $memrd$\memory$libresoc.v:126310$5294_DATA + attribute \src "libresoc.v:126311.30-126311.36" + wire width 64 $memrd$\memory$libresoc.v:126311$5295_DATA + attribute \src "libresoc.v:126312.30-126312.36" + wire width 64 $memrd$\memory$libresoc.v:126312$5296_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:125081$5190_ADDR + wire width 5 $memwr$\memory$libresoc.v:126307$5281_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:125081$5190_DATA + wire width 64 $memwr$\memory$libresoc.v:126307$5281_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:125081$5190_EN - attribute \src "libresoc.v:125072.13-125072.16" + wire width 64 $memwr$\memory$libresoc.v:126307$5281_EN + attribute \src "libresoc.v:126298.13-126298.16" wire width 5 \_0_ - attribute \src "libresoc.v:125073.13-125073.16" + attribute \src "libresoc.v:126299.13-126299.16" wire width 5 \_1_ - attribute \src "libresoc.v:125074.13-125074.16" + attribute \src "libresoc.v:126300.13-126300.16" wire width 5 \_2_ - attribute \src "libresoc.v:125075.13-125075.16" + attribute \src "libresoc.v:126301.13-126301.16" wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 14 \dest1__addr + wire width 5 input 15 \dest1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i + wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \dest1__wen + wire input 16 \dest1__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 1 \dmi__addr + wire width 5 input 2 \dmi__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \dmi__data_o + wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \dmi__ren - attribute \src "libresoc.v:124952.7-124952.15" + wire input 3 \dmi__ren + attribute \src "libresoc.v:126178.7-126178.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -196281,347 +199026,347 @@ module \int attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 5 \src1__addr + wire width 5 input 6 \src1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \src1__data_o + wire width 64 output 5 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src1__ren + wire input 7 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 8 \src2__addr + wire width 5 input 9 \src2__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src2__data_o + wire width 64 output 8 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 9 \src2__ren + wire input 10 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 11 \src3__addr + wire width 5 input 12 \src3__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src3__data_o + wire width 64 output 11 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \src3__ren - attribute \src "libresoc.v:125037.14-125037.20" + wire input 13 \src3__ren + attribute \src "libresoc.v:126263.14-126263.20" memory width 64 size 32 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5222 + cell $meminit $meminit$\memory$libresoc.v:0$5313 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5222 + parameter \PRIORITY 5313 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5223 + cell $meminit $meminit$\memory$libresoc.v:0$5314 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5223 + parameter \PRIORITY 5314 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5224 + cell $meminit $meminit$\memory$libresoc.v:0$5315 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5224 + parameter \PRIORITY 5315 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5225 + cell $meminit $meminit$\memory$libresoc.v:0$5316 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5225 + parameter \PRIORITY 5316 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5226 + cell $meminit $meminit$\memory$libresoc.v:0$5317 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5226 + parameter \PRIORITY 5317 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5227 + cell $meminit $meminit$\memory$libresoc.v:0$5318 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5227 + parameter \PRIORITY 5318 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5228 + cell $meminit $meminit$\memory$libresoc.v:0$5319 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5228 + parameter \PRIORITY 5319 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5229 + cell $meminit $meminit$\memory$libresoc.v:0$5320 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5229 + parameter \PRIORITY 5320 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5230 + cell $meminit $meminit$\memory$libresoc.v:0$5321 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5230 + parameter \PRIORITY 5321 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5231 + cell $meminit $meminit$\memory$libresoc.v:0$5322 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5231 + parameter \PRIORITY 5322 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5232 + cell $meminit $meminit$\memory$libresoc.v:0$5323 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5232 + parameter \PRIORITY 5323 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5233 + cell $meminit $meminit$\memory$libresoc.v:0$5324 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5233 + parameter \PRIORITY 5324 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5234 + cell $meminit $meminit$\memory$libresoc.v:0$5325 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5234 + parameter \PRIORITY 5325 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5235 + cell $meminit $meminit$\memory$libresoc.v:0$5326 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5235 + parameter \PRIORITY 5326 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5236 + cell $meminit $meminit$\memory$libresoc.v:0$5327 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5236 + parameter \PRIORITY 5327 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5237 + cell $meminit $meminit$\memory$libresoc.v:0$5328 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5237 + parameter \PRIORITY 5328 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5238 + cell $meminit $meminit$\memory$libresoc.v:0$5329 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5238 + parameter \PRIORITY 5329 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5239 + cell $meminit $meminit$\memory$libresoc.v:0$5330 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5239 + parameter \PRIORITY 5330 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5240 + cell $meminit $meminit$\memory$libresoc.v:0$5331 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5240 + parameter \PRIORITY 5331 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5241 + cell $meminit $meminit$\memory$libresoc.v:0$5332 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5241 + parameter \PRIORITY 5332 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5242 + cell $meminit $meminit$\memory$libresoc.v:0$5333 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5242 + parameter \PRIORITY 5333 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5243 + cell $meminit $meminit$\memory$libresoc.v:0$5334 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5243 + parameter \PRIORITY 5334 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5244 + cell $meminit $meminit$\memory$libresoc.v:0$5335 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5244 + parameter \PRIORITY 5335 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5245 + cell $meminit $meminit$\memory$libresoc.v:0$5336 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5245 + parameter \PRIORITY 5336 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5246 + cell $meminit $meminit$\memory$libresoc.v:0$5337 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5246 + parameter \PRIORITY 5337 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5247 + cell $meminit $meminit$\memory$libresoc.v:0$5338 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5247 + parameter \PRIORITY 5338 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5248 + cell $meminit $meminit$\memory$libresoc.v:0$5339 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5248 + parameter \PRIORITY 5339 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5249 + cell $meminit $meminit$\memory$libresoc.v:0$5340 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5249 + parameter \PRIORITY 5340 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5250 + cell $meminit $meminit$\memory$libresoc.v:0$5341 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5250 + parameter \PRIORITY 5341 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5251 + cell $meminit $meminit$\memory$libresoc.v:0$5342 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5251 + parameter \PRIORITY 5342 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5252 + cell $meminit $meminit$\memory$libresoc.v:0$5343 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5252 + parameter \PRIORITY 5343 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5253 + cell $meminit $meminit$\memory$libresoc.v:0$5344 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5253 + parameter \PRIORITY 5344 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:125083.26-125083.32" - cell $memrd $memrd$\memory$libresoc.v:125083$5202 + attribute \src "libresoc.v:126309.26-126309.32" + cell $memrd $memrd$\memory$libresoc.v:126309$5293 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -196630,11 +199375,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:125083$5202_DATA + connect \DATA $memrd$\memory$libresoc.v:126309$5293_DATA connect \EN 1'x end - attribute \src "libresoc.v:125084.30-125084.36" - cell $memrd $memrd$\memory$libresoc.v:125084$5203 + attribute \src "libresoc.v:126310.30-126310.36" + cell $memrd $memrd$\memory$libresoc.v:126310$5294 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -196643,11 +199388,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:125084$5203_DATA + connect \DATA $memrd$\memory$libresoc.v:126310$5294_DATA connect \EN 1'x end - attribute \src "libresoc.v:125085.30-125085.36" - cell $memrd $memrd$\memory$libresoc.v:125085$5204 + attribute \src "libresoc.v:126311.30-126311.36" + cell $memrd $memrd$\memory$libresoc.v:126311$5295 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -196656,11 +199401,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:125085$5204_DATA + connect \DATA $memrd$\memory$libresoc.v:126311$5295_DATA connect \EN 1'x end - attribute \src "libresoc.v:125086.30-125086.36" - cell $memrd $memrd$\memory$libresoc.v:125086$5205 + attribute \src "libresoc.v:126312.30-126312.36" + cell $memrd $memrd$\memory$libresoc.v:126312$5296 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -196669,97 +199414,97 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:125086$5205_DATA + connect \DATA $memrd$\memory$libresoc.v:126312$5296_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5254 + cell $memwr $memwr$\memory$libresoc.v:0$5345 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 5254 + parameter \PRIORITY 5345 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:125081$5190_ADDR + connect \ADDR $memwr$\memory$libresoc.v:126307$5281_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:125081$5190_DATA - connect \EN $memwr$\memory$libresoc.v:125081$5190_EN + connect \DATA $memwr$\memory$libresoc.v:126307$5281_DATA + connect \EN $memwr$\memory$libresoc.v:126307$5281_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5263 + process $proc$libresoc.v:0$5354 sync always sync init end - attribute \src "libresoc.v:124952.7-124952.20" - process $proc$libresoc.v:124952$5255 + attribute \src "libresoc.v:126178.7-126178.20" + process $proc$libresoc.v:126178$5346 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124993.7-124993.23" - process $proc$libresoc.v:124993$5256 + attribute \src "libresoc.v:126219.7-126219.23" + process $proc$libresoc.v:126219$5347 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:124995.7-124995.28" - process $proc$libresoc.v:124995$5257 + attribute \src "libresoc.v:126221.7-126221.28" + process $proc$libresoc.v:126221$5348 assign { } { } - assign $0\ren_delay$10[0:0]$5258 1'0 + assign $0\ren_delay$10[0:0]$5349 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5258 + update \ren_delay$10 $0\ren_delay$10[0:0]$5349 end - attribute \src "libresoc.v:124999.7-124999.27" - process $proc$libresoc.v:124999$5259 + attribute \src "libresoc.v:126225.7-126225.27" + process $proc$libresoc.v:126225$5350 assign { } { } - assign $0\ren_delay$8[0:0]$5260 1'0 + assign $0\ren_delay$8[0:0]$5351 1'0 sync always sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5260 + update \ren_delay$8 $0\ren_delay$8[0:0]$5351 end - attribute \src "libresoc.v:125003.7-125003.27" - process $proc$libresoc.v:125003$5261 + attribute \src "libresoc.v:126229.7-126229.27" + process $proc$libresoc.v:126229$5352 assign { } { } - assign $0\ren_delay$9[0:0]$5262 1'0 + assign $0\ren_delay$9[0:0]$5353 1'0 sync always sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5262 + update \ren_delay$9 $0\ren_delay$9[0:0]$5353 end - attribute \src "libresoc.v:125029.3-125030.43" - process $proc$libresoc.v:125029$5191 + attribute \src "libresoc.v:126255.3-126256.43" + process $proc$libresoc.v:126255$5282 assign { } { } - assign $0\ren_delay$10[0:0]$5192 \ren_delay$10$next + assign $0\ren_delay$10[0:0]$5283 \ren_delay$10$next sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5192 + update \ren_delay$10 $0\ren_delay$10[0:0]$5283 end - attribute \src "libresoc.v:125031.3-125032.41" - process $proc$libresoc.v:125031$5193 + attribute \src "libresoc.v:126257.3-126258.41" + process $proc$libresoc.v:126257$5284 assign { } { } - assign $0\ren_delay$9[0:0]$5194 \ren_delay$9$next + assign $0\ren_delay$9[0:0]$5285 \ren_delay$9$next sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5194 + update \ren_delay$9 $0\ren_delay$9[0:0]$5285 end - attribute \src "libresoc.v:125033.3-125034.41" - process $proc$libresoc.v:125033$5195 + attribute \src "libresoc.v:126259.3-126260.41" + process $proc$libresoc.v:126259$5286 assign { } { } - assign $0\ren_delay$8[0:0]$5196 \ren_delay$8$next + assign $0\ren_delay$8[0:0]$5287 \ren_delay$8$next sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5196 + update \ren_delay$8 $0\ren_delay$8[0:0]$5287 end - attribute \src "libresoc.v:125035.3-125036.35" - process $proc$libresoc.v:125035$5197 + attribute \src "libresoc.v:126261.3-126262.35" + process $proc$libresoc.v:126261$5288 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:125076.3-125082.6" - process $proc$libresoc.v:125076$5198 + attribute \src "libresoc.v:126302.3-126308.6" + process $proc$libresoc.v:126302$5289 assign { } { } assign { } { } assign { } { } @@ -196767,20 +199512,20 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 5'xxxxx - assign $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 5'xxxxx + assign $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[4:0] \src1__addr assign $0\_1_[4:0] \src2__addr assign $0\_2_[4:0] \src3__addr assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:125081.5-125081.58" + attribute \src "libresoc.v:126307.5-126307.58" switch \dest1__wen - attribute \src "libresoc.v:125081.9-125081.19" + attribute \src "libresoc.v:126307.9-126307.19" case 1'1 - assign $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 \dest1__addr - assign $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 \dest1__addr + assign $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk @@ -196788,18 +199533,18 @@ module \int update \_1_ $0\_1_[4:0] update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:125081$5190_ADDR $0$memwr$\memory$libresoc.v:125081$5190_ADDR[4:0]$5199 - update $memwr$\memory$libresoc.v:125081$5190_DATA $0$memwr$\memory$libresoc.v:125081$5190_DATA[63:0]$5200 - update $memwr$\memory$libresoc.v:125081$5190_EN $0$memwr$\memory$libresoc.v:125081$5190_EN[63:0]$5201 + update $memwr$\memory$libresoc.v:126307$5281_ADDR $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 + update $memwr$\memory$libresoc.v:126307$5281_DATA $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 + update $memwr$\memory$libresoc.v:126307$5281_EN $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 end - attribute \src "libresoc.v:125087.3-125095.6" - process $proc$libresoc.v:125087$5206 + attribute \src "libresoc.v:126313.3-126321.6" + process $proc$libresoc.v:126313$5297 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5207 $1\ren_delay$next[0:0]$5208 - attribute \src "libresoc.v:125088.5-125088.29" + assign $0\ren_delay$next[0:0]$5298 $1\ren_delay$next[0:0]$5299 + attribute \src "libresoc.v:126314.5-126314.29" switch \initial - attribute \src "libresoc.v:125088.9-125088.17" + attribute \src "libresoc.v:126314.9-126314.17" case 1'1 case end @@ -196808,21 +199553,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5208 1'0 + assign $1\ren_delay$next[0:0]$5299 1'0 case - assign $1\ren_delay$next[0:0]$5208 \src1__ren + assign $1\ren_delay$next[0:0]$5299 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5207 + update \ren_delay$next $0\ren_delay$next[0:0]$5298 end - attribute \src "libresoc.v:125096.3-125104.6" - process $proc$libresoc.v:125096$5209 + attribute \src "libresoc.v:126322.3-126330.6" + process $proc$libresoc.v:126322$5300 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5210 $1\ren_delay$10$next[0:0]$5211 - attribute \src "libresoc.v:125097.5-125097.29" + assign $0\ren_delay$10$next[0:0]$5301 $1\ren_delay$10$next[0:0]$5302 + attribute \src "libresoc.v:126323.5-126323.29" switch \initial - attribute \src "libresoc.v:125097.9-125097.17" + attribute \src "libresoc.v:126323.9-126323.17" case 1'1 case end @@ -196831,21 +199576,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5211 1'0 + assign $1\ren_delay$10$next[0:0]$5302 1'0 case - assign $1\ren_delay$10$next[0:0]$5211 \dmi__ren + assign $1\ren_delay$10$next[0:0]$5302 \dmi__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5210 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5301 end - attribute \src "libresoc.v:125105.3-125114.6" - process $proc$libresoc.v:125105$5212 + attribute \src "libresoc.v:126331.3-126340.6" + process $proc$libresoc.v:126331$5303 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:125106.5-125106.29" + attribute \src "libresoc.v:126332.5-126332.29" switch \initial - attribute \src "libresoc.v:125106.9-125106.17" + attribute \src "libresoc.v:126332.9-126332.17" case 1'1 case end @@ -196861,14 +199606,14 @@ module \int sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:125115.3-125124.6" - process $proc$libresoc.v:125115$5213 + attribute \src "libresoc.v:126341.3-126350.6" + process $proc$libresoc.v:126341$5304 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:125116.5-125116.29" + attribute \src "libresoc.v:126342.5-126342.29" switch \initial - attribute \src "libresoc.v:125116.9-125116.17" + attribute \src "libresoc.v:126342.9-126342.17" case 1'1 case end @@ -196884,14 +199629,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:125125.3-125133.6" - process $proc$libresoc.v:125125$5214 + attribute \src "libresoc.v:126351.3-126359.6" + process $proc$libresoc.v:126351$5305 assign { } { } assign { } { } - assign $0\ren_delay$8$next[0:0]$5215 $1\ren_delay$8$next[0:0]$5216 - attribute \src "libresoc.v:125126.5-125126.29" + assign $0\ren_delay$8$next[0:0]$5306 $1\ren_delay$8$next[0:0]$5307 + attribute \src "libresoc.v:126352.5-126352.29" switch \initial - attribute \src "libresoc.v:125126.9-125126.17" + attribute \src "libresoc.v:126352.9-126352.17" case 1'1 case end @@ -196900,21 +199645,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$8$next[0:0]$5216 1'0 + assign $1\ren_delay$8$next[0:0]$5307 1'0 case - assign $1\ren_delay$8$next[0:0]$5216 \src2__ren + assign $1\ren_delay$8$next[0:0]$5307 \src2__ren end sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5215 + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5306 end - attribute \src "libresoc.v:125134.3-125143.6" - process $proc$libresoc.v:125134$5217 + attribute \src "libresoc.v:126360.3-126369.6" + process $proc$libresoc.v:126360$5308 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:125135.5-125135.29" + attribute \src "libresoc.v:126361.5-126361.29" switch \initial - attribute \src "libresoc.v:125135.9-125135.17" + attribute \src "libresoc.v:126361.9-126361.17" case 1'1 case end @@ -196930,14 +199675,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:125144.3-125152.6" - process $proc$libresoc.v:125144$5218 + attribute \src "libresoc.v:126370.3-126378.6" + process $proc$libresoc.v:126370$5309 assign { } { } assign { } { } - assign $0\ren_delay$9$next[0:0]$5219 $1\ren_delay$9$next[0:0]$5220 - attribute \src "libresoc.v:125145.5-125145.29" + assign $0\ren_delay$9$next[0:0]$5310 $1\ren_delay$9$next[0:0]$5311 + attribute \src "libresoc.v:126371.5-126371.29" switch \initial - attribute \src "libresoc.v:125145.9-125145.17" + attribute \src "libresoc.v:126371.9-126371.17" case 1'1 case end @@ -196946,21 +199691,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$9$next[0:0]$5220 1'0 + assign $1\ren_delay$9$next[0:0]$5311 1'0 case - assign $1\ren_delay$9$next[0:0]$5220 \src3__ren + assign $1\ren_delay$9$next[0:0]$5311 \src3__ren end sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5219 + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5310 end - attribute \src "libresoc.v:125153.3-125162.6" - process $proc$libresoc.v:125153$5221 + attribute \src "libresoc.v:126379.3-126388.6" + process $proc$libresoc.v:126379$5312 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:125154.5-125154.29" + attribute \src "libresoc.v:126380.5-126380.29" switch \initial - attribute \src "libresoc.v:125154.9-125154.17" + attribute \src "libresoc.v:126380.9-126380.17" case 1'1 case end @@ -196976,10 +199721,10 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:125083$5202_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:125084$5203_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:125085$5204_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:125086$5205_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:126309$5293_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:126310$5294_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:126311$5295_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:126312$5296_DATA connect \memory_w_data \dest1__data_i connect \memory_w_en \dest1__wen connect \memory_w_addr \dest1__addr @@ -196988,1365 +199733,2341 @@ module \int connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:125174.1-126925.10" +attribute \src "libresoc.v:126400.1-129114.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.jtag" +attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:126201.3-126224.6" + attribute \src "libresoc.v:128546.3-128572.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:126562.3-126577.6" + attribute \src "libresoc.v:128194.3-128209.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:126359.3-126391.6" - wire width 4 $0\dmi0_addr_i$next[3:0]$5475 - attribute \src "libresoc.v:126065.3-126066.39" - wire width 4 $0\dmi0_addr_i[3:0] - attribute \src "libresoc.v:126785.3-126801.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5558 - attribute \src "libresoc.v:126085.3-126086.47" + attribute \src "libresoc.v:128707.3-128739.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$5765 + attribute \src "libresoc.v:128097.3-128098.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:128793.3-128819.6" + wire width 64 $0\dmi0__din$next[63:0]$5778 + attribute \src "libresoc.v:128093.3-128094.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:128396.3-128412.6" + wire $0\dmi0_addrsr__oe$next[0:0]$5702 + attribute \src "libresoc.v:128125.3-128126.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:126802.3-126822.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5562 - attribute \src "libresoc.v:126083.3-126084.47" + attribute \src "libresoc.v:128413.3-128433.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5706 + attribute \src "libresoc.v:128123.3-128124.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:126767.3-126775.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5552 - attribute \src "libresoc.v:126089.3-126090.63" + attribute \src "libresoc.v:128378.3-128386.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$5696 + attribute \src "libresoc.v:128129.3-128130.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:126776.3-126784.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 - attribute \src "libresoc.v:126087.3-126088.73" + attribute \src "libresoc.v:128387.3-128395.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 + attribute \src "libresoc.v:128127.3-128128.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:126472.3-126492.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$5493 - attribute \src "libresoc.v:126059.3-126060.45" + attribute \src "libresoc.v:128820.3-128840.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$5783 + attribute \src "libresoc.v:128091.3-128092.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:126163.3-126179.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5442 - attribute \src "libresoc.v:126077.3-126078.47" + attribute \src "libresoc.v:128452.3-128468.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$5717 + attribute \src "libresoc.v:128117.3-128118.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:126180.3-126200.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5446 - attribute \src "libresoc.v:126075.3-126076.47" + attribute \src "libresoc.v:128469.3-128489.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$5721 + attribute \src "libresoc.v:128115.3-128116.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:126823.3-126831.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5567 - attribute \src "libresoc.v:126081.3-126082.63" + attribute \src "libresoc.v:128434.3-128442.6" + wire $0\dmi0_datasr_update_core$next[0:0]$5711 + attribute \src "libresoc.v:128121.3-128122.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:126154.3-126162.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5439 - attribute \src "libresoc.v:126079.3-126080.73" + attribute \src "libresoc.v:128443.3-128451.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$5714 + attribute \src "libresoc.v:128119.3-128120.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:126445.3-126471.6" - wire width 64 $0\dmi0_din$next[63:0]$5488 - attribute \src "libresoc.v:126061.3-126062.33" - wire width 64 $0\dmi0_din[63:0] - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $0\fsm_state$275$next[2:0]$5481 - attribute \src "libresoc.v:126063.3-126064.45" - wire width 3 $0\fsm_state$275[2:0]$5410 - attribute \src "libresoc.v:125576.13-125576.35" - wire width 3 $0\fsm_state$275[2:0]$5583 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $0\fsm_state$next[2:0]$5458 - attribute \src "libresoc.v:126071.3-126072.35" + attribute \src "libresoc.v:128740.3-128792.6" + wire width 3 $0\fsm_state$503$next[2:0]$5771 + attribute \src "libresoc.v:128095.3-128096.45" + wire width 3 $0\fsm_state$503[2:0]$5617 + attribute \src "libresoc.v:127046.13-127046.35" + wire width 3 $0\fsm_state$503[2:0]$5817 + attribute \src "libresoc.v:128606.3-128658.6" + wire width 3 $0\fsm_state$next[2:0]$5748 + attribute \src "libresoc.v:128103.3-128104.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:125175.7-125175.20" + attribute \src "libresoc.v:126401.7-126401.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126578.3-126598.6" - wire width 50 $0\io_bd$next[49:0]$5503 - attribute \src "libresoc.v:126115.3-126116.27" - wire width 50 $0\io_bd[49:0] - attribute \src "libresoc.v:126493.3-126561.6" - wire width 50 $0\io_sr$next[49:0]$5498 - attribute \src "libresoc.v:126117.3-126118.27" - wire width 50 $0\io_sr[49:0] - attribute \src "libresoc.v:126225.3-126257.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$5452 - attribute \src "libresoc.v:126073.3-126074.41" + attribute \src "libresoc.v:128888.3-128908.6" + wire width 154 $0\io_bd$next[153:0]$5800 + attribute \src "libresoc.v:128155.3-128156.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:128870.3-128887.6" + wire width 154 $0\io_sr$next[153:0]$5796 + attribute \src "libresoc.v:128157.3-128158.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:128573.3-128605.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$5742 + attribute \src "libresoc.v:128105.3-128106.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:126311.3-126337.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$5465 - attribute \src "libresoc.v:126069.3-126070.45" + attribute \src "libresoc.v:128659.3-128685.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$5755 + attribute \src "libresoc.v:128101.3-128102.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:126673.3-126689.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5528 - attribute \src "libresoc.v:126101.3-126102.53" + attribute \src "libresoc.v:128284.3-128300.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5672 + attribute \src "libresoc.v:128141.3-128142.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:126690.3-126710.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5532 - attribute \src "libresoc.v:126099.3-126100.53" + attribute \src "libresoc.v:128301.3-128321.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5676 + attribute \src "libresoc.v:128139.3-128140.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:126655.3-126663.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5522 - attribute \src "libresoc.v:126105.3-126106.69" + attribute \src "libresoc.v:128266.3-128274.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5666 + attribute \src "libresoc.v:128145.3-128146.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:126664.3-126672.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 - attribute \src "libresoc.v:126103.3-126104.79" + attribute \src "libresoc.v:128275.3-128283.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 + attribute \src "libresoc.v:128143.3-128144.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:126338.3-126358.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5470 - attribute \src "libresoc.v:126067.3-126068.51" + attribute \src "libresoc.v:128686.3-128706.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5760 + attribute \src "libresoc.v:128099.3-128100.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:126729.3-126745.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5543 - attribute \src "libresoc.v:126093.3-126094.53" + attribute \src "libresoc.v:128340.3-128356.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5687 + attribute \src "libresoc.v:128133.3-128134.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:126746.3-126766.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5547 - attribute \src "libresoc.v:126091.3-126092.53" + attribute \src "libresoc.v:128357.3-128377.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5691 + attribute \src "libresoc.v:128131.3-128132.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:126711.3-126719.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5537 - attribute \src "libresoc.v:126097.3-126098.69" + attribute \src "libresoc.v:128322.3-128330.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5681 + attribute \src "libresoc.v:128137.3-128138.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:126720.3-126728.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 - attribute \src "libresoc.v:126095.3-126096.79" + attribute \src "libresoc.v:128331.3-128339.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 + attribute \src "libresoc.v:128135.3-128136.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:126617.3-126633.6" - wire $0\sr0__oe$next[0:0]$5513 - attribute \src "libresoc.v:126109.3-126110.31" + attribute \src "libresoc.v:128228.3-128244.6" + wire $0\sr0__oe$next[0:0]$5657 + attribute \src "libresoc.v:128149.3-128150.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:126634.3-126654.6" - wire width 3 $0\sr0_reg$next[2:0]$5517 - attribute \src "libresoc.v:126107.3-126108.31" + attribute \src "libresoc.v:128245.3-128265.6" + wire width 3 $0\sr0_reg$next[2:0]$5661 + attribute \src "libresoc.v:128147.3-128148.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:126599.3-126607.6" - wire $0\sr0_update_core$next[0:0]$5507 - attribute \src "libresoc.v:126113.3-126114.47" + attribute \src "libresoc.v:128210.3-128218.6" + wire $0\sr0_update_core$next[0:0]$5651 + attribute \src "libresoc.v:128153.3-128154.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:126608.3-126616.6" - wire $0\sr0_update_core_prev$next[0:0]$5510 - attribute \src "libresoc.v:126111.3-126112.57" + attribute \src "libresoc.v:128219.3-128227.6" + wire $0\sr0_update_core_prev$next[0:0]$5654 + attribute \src "libresoc.v:128151.3-128152.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:126201.3-126224.6" + attribute \src "libresoc.v:128860.3-128869.6" + wire width 2 $0\sr5__i[1:0] + attribute \src "libresoc.v:128508.3-128524.6" + wire $0\sr5__oe$next[0:0]$5732 + attribute \src "libresoc.v:128109.3-128110.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:128525.3-128545.6" + wire width 2 $0\sr5_reg$next[1:0]$5736 + attribute \src "libresoc.v:128107.3-128108.31" + wire width 2 $0\sr5_reg[1:0] + attribute \src "libresoc.v:128490.3-128498.6" + wire $0\sr5_update_core$next[0:0]$5726 + attribute \src "libresoc.v:128113.3-128114.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:128499.3-128507.6" + wire $0\sr5_update_core_prev$next[0:0]$5729 + attribute \src "libresoc.v:128111.3-128112.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:128841.3-128859.6" + wire $0\wb_dcache_en$next[0:0]$5788 + attribute \src "libresoc.v:128089.3-128090.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:128841.3-128859.6" + wire $0\wb_icache_en$next[0:0]$5789 + attribute \src "libresoc.v:128087.3-128088.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:128546.3-128572.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:126562.3-126577.6" + attribute \src "libresoc.v:128194.3-128209.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:126359.3-126391.6" - wire width 4 $1\dmi0_addr_i$next[3:0]$5476 - attribute \src "libresoc.v:125501.13-125501.31" - wire width 4 $1\dmi0_addr_i[3:0] - attribute \src "libresoc.v:126785.3-126801.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5559 - attribute \src "libresoc.v:125509.7-125509.29" + attribute \src "libresoc.v:128707.3-128739.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$5766 + attribute \src "libresoc.v:126959.13-126959.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:128793.3-128819.6" + wire width 64 $1\dmi0__din$next[63:0]$5779 + attribute \src "libresoc.v:126964.14-126964.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:128396.3-128412.6" + wire $1\dmi0_addrsr__oe$next[0:0]$5703 + attribute \src "libresoc.v:126978.7-126978.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:126802.3-126822.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5563 - attribute \src "libresoc.v:125517.13-125517.36" + attribute \src "libresoc.v:128413.3-128433.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5707 + attribute \src "libresoc.v:126986.13-126986.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:126767.3-126775.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5553 - attribute \src "libresoc.v:125525.7-125525.37" + attribute \src "libresoc.v:128378.3-128386.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$5697 + attribute \src "libresoc.v:126994.7-126994.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:126776.3-126784.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 - attribute \src "libresoc.v:125529.7-125529.42" + attribute \src "libresoc.v:128387.3-128395.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 + attribute \src "libresoc.v:126998.7-126998.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:126472.3-126492.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$5494 - attribute \src "libresoc.v:125533.14-125533.51" + attribute \src "libresoc.v:128820.3-128840.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$5784 + attribute \src "libresoc.v:127002.14-127002.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:126163.3-126179.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5443 - attribute \src "libresoc.v:125539.13-125539.35" + attribute \src "libresoc.v:128452.3-128468.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$5718 + attribute \src "libresoc.v:127008.13-127008.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:126180.3-126200.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$5447 - attribute \src "libresoc.v:125547.14-125547.52" + attribute \src "libresoc.v:128469.3-128489.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$5722 + attribute \src "libresoc.v:127016.14-127016.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:126823.3-126831.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5568 - attribute \src "libresoc.v:125555.7-125555.37" + attribute \src "libresoc.v:128434.3-128442.6" + wire $1\dmi0_datasr_update_core$next[0:0]$5712 + attribute \src "libresoc.v:127024.7-127024.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:126154.3-126162.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5440 - attribute \src "libresoc.v:125559.7-125559.42" + attribute \src "libresoc.v:128443.3-128451.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$5715 + attribute \src "libresoc.v:127028.7-127028.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:126445.3-126471.6" - wire width 64 $1\dmi0_din$next[63:0]$5489 - attribute \src "libresoc.v:125564.14-125564.45" - wire width 64 $1\dmi0_din[63:0] - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $1\fsm_state$275$next[2:0]$5482 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $1\fsm_state$next[2:0]$5459 - attribute \src "libresoc.v:125574.13-125574.29" + attribute \src "libresoc.v:128740.3-128792.6" + wire width 3 $1\fsm_state$503$next[2:0]$5772 + attribute \src "libresoc.v:128606.3-128658.6" + wire width 3 $1\fsm_state$next[2:0]$5749 + attribute \src "libresoc.v:127044.13-127044.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:126578.3-126598.6" - wire width 50 $1\io_bd$next[49:0]$5504 - attribute \src "libresoc.v:125774.14-125774.39" - wire width 50 $1\io_bd[49:0] - attribute \src "libresoc.v:126493.3-126561.6" - wire width 50 $1\io_sr$next[49:0]$5499 - attribute \src "libresoc.v:125786.14-125786.39" - wire width 50 $1\io_sr[49:0] - attribute \src "libresoc.v:126225.3-126257.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$5453 - attribute \src "libresoc.v:125795.14-125795.41" + attribute \src "libresoc.v:128888.3-128908.6" + wire width 154 $1\io_bd$next[153:0]$5801 + attribute \src "libresoc.v:127244.15-127244.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:128870.3-128887.6" + wire width 154 $1\io_sr$next[153:0]$5797 + attribute \src "libresoc.v:127256.15-127256.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:128573.3-128605.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$5743 + attribute \src "libresoc.v:127265.14-127265.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:126311.3-126337.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$5466 - attribute \src "libresoc.v:125804.14-125804.51" + attribute \src "libresoc.v:128659.3-128685.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$5756 + attribute \src "libresoc.v:127274.14-127274.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:126673.3-126689.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5529 - attribute \src "libresoc.v:125818.7-125818.32" + attribute \src "libresoc.v:128284.3-128300.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5673 + attribute \src "libresoc.v:127288.7-127288.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:126690.3-126710.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5533 - attribute \src "libresoc.v:125826.14-125826.47" + attribute \src "libresoc.v:128301.3-128321.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5677 + attribute \src "libresoc.v:127296.14-127296.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:126655.3-126663.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5523 - attribute \src "libresoc.v:125834.7-125834.40" + attribute \src "libresoc.v:128266.3-128274.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5667 + attribute \src "libresoc.v:127304.7-127304.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:126664.3-126672.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 - attribute \src "libresoc.v:125838.7-125838.45" + attribute \src "libresoc.v:128275.3-128283.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 + attribute \src "libresoc.v:127308.7-127308.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:126338.3-126358.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5471 - attribute \src "libresoc.v:125842.14-125842.54" + attribute \src "libresoc.v:128686.3-128706.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5761 + attribute \src "libresoc.v:127312.14-127312.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:126729.3-126745.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5544 - attribute \src "libresoc.v:125848.13-125848.38" + attribute \src "libresoc.v:128340.3-128356.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5688 + attribute \src "libresoc.v:127318.13-127318.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:126746.3-126766.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5548 - attribute \src "libresoc.v:125856.14-125856.55" + attribute \src "libresoc.v:128357.3-128377.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5692 + attribute \src "libresoc.v:127326.14-127326.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:126711.3-126719.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5538 - attribute \src "libresoc.v:125864.7-125864.40" + attribute \src "libresoc.v:128322.3-128330.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5682 + attribute \src "libresoc.v:127334.7-127334.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:126720.3-126728.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 - attribute \src "libresoc.v:125868.7-125868.45" + attribute \src "libresoc.v:128331.3-128339.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 + attribute \src "libresoc.v:127338.7-127338.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:126617.3-126633.6" - wire $1\sr0__oe$next[0:0]$5514 - attribute \src "libresoc.v:125886.7-125886.21" + attribute \src "libresoc.v:128228.3-128244.6" + wire $1\sr0__oe$next[0:0]$5658 + attribute \src "libresoc.v:127768.7-127768.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:126634.3-126654.6" - wire width 3 $1\sr0_reg$next[2:0]$5518 - attribute \src "libresoc.v:125894.13-125894.27" + attribute \src "libresoc.v:128245.3-128265.6" + wire width 3 $1\sr0_reg$next[2:0]$5662 + attribute \src "libresoc.v:127776.13-127776.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:126599.3-126607.6" - wire $1\sr0_update_core$next[0:0]$5508 - attribute \src "libresoc.v:125902.7-125902.29" + attribute \src "libresoc.v:128210.3-128218.6" + wire $1\sr0_update_core$next[0:0]$5652 + attribute \src "libresoc.v:127784.7-127784.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:126608.3-126616.6" - wire $1\sr0_update_core_prev$next[0:0]$5511 - attribute \src "libresoc.v:125906.7-125906.34" + attribute \src "libresoc.v:128219.3-128227.6" + wire $1\sr0_update_core_prev$next[0:0]$5655 + attribute \src "libresoc.v:127788.7-127788.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:126359.3-126391.6" - wire width 4 $2\dmi0_addr_i$next[3:0]$5477 - attribute \src "libresoc.v:126785.3-126801.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5560 - attribute \src "libresoc.v:126802.3-126822.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5564 - attribute \src "libresoc.v:126472.3-126492.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$5495 - attribute \src "libresoc.v:126163.3-126179.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5444 - attribute \src "libresoc.v:126180.3-126200.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$5448 - attribute \src "libresoc.v:126445.3-126471.6" - wire width 64 $2\dmi0_din$next[63:0]$5490 - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $2\fsm_state$275$next[2:0]$5483 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $2\fsm_state$next[2:0]$5460 - attribute \src "libresoc.v:126578.3-126598.6" - wire width 50 $2\io_bd$next[49:0]$5505 - attribute \src "libresoc.v:126493.3-126561.6" - wire width 50 $2\io_sr$next[49:0]$5500 - attribute \src "libresoc.v:126225.3-126257.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$5454 - attribute \src "libresoc.v:126311.3-126337.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$5467 - attribute \src "libresoc.v:126673.3-126689.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5530 - attribute \src "libresoc.v:126690.3-126710.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5534 - attribute \src "libresoc.v:126338.3-126358.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5472 - attribute \src "libresoc.v:126729.3-126745.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5545 - attribute \src "libresoc.v:126746.3-126766.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5549 - attribute \src "libresoc.v:126617.3-126633.6" - wire $2\sr0__oe$next[0:0]$5515 - attribute \src "libresoc.v:126634.3-126654.6" - wire width 3 $2\sr0_reg$next[2:0]$5519 - attribute \src "libresoc.v:126359.3-126391.6" - wire width 4 $3\dmi0_addr_i$next[3:0]$5478 - attribute \src "libresoc.v:126802.3-126822.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5565 - attribute \src "libresoc.v:126472.3-126492.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$5496 - attribute \src "libresoc.v:126180.3-126200.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$5449 - attribute \src "libresoc.v:126445.3-126471.6" - wire width 64 $3\dmi0_din$next[63:0]$5491 - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $3\fsm_state$275$next[2:0]$5484 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $3\fsm_state$next[2:0]$5461 - attribute \src "libresoc.v:126225.3-126257.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$5455 - attribute \src "libresoc.v:126311.3-126337.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$5468 - attribute \src "libresoc.v:126690.3-126710.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5535 - attribute \src "libresoc.v:126338.3-126358.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5473 - attribute \src "libresoc.v:126746.3-126766.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5550 - attribute \src "libresoc.v:126634.3-126654.6" - wire width 3 $3\sr0_reg$next[2:0]$5520 - attribute \src "libresoc.v:126359.3-126391.6" - wire width 4 $4\dmi0_addr_i$next[3:0]$5479 - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $4\fsm_state$275$next[2:0]$5485 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $4\fsm_state$next[2:0]$5462 - attribute \src "libresoc.v:126225.3-126257.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$5456 - attribute \src "libresoc.v:126392.3-126444.6" - wire width 3 $5\fsm_state$275$next[2:0]$5486 - attribute \src "libresoc.v:126258.3-126310.6" - wire width 3 $5\fsm_state$next[2:0]$5463 - attribute \src "libresoc.v:126011.19-126011.110" - wire width 30 $add$libresoc.v:126011$5358_Y - attribute \src "libresoc.v:126012.19-126012.110" - wire width 30 $add$libresoc.v:126012$5359_Y - attribute \src "libresoc.v:126019.19-126019.109" - wire width 5 $add$libresoc.v:126019$5367_Y - attribute \src "libresoc.v:126020.19-126020.109" - wire width 5 $add$libresoc.v:126020$5368_Y - attribute \src "libresoc.v:125944.19-125944.110" - wire $and$libresoc.v:125944$5291_Y - attribute \src "libresoc.v:125951.19-125951.110" - wire $and$libresoc.v:125951$5298_Y - attribute \src "libresoc.v:125954.19-125954.114" - wire $and$libresoc.v:125954$5301_Y - attribute \src "libresoc.v:125956.19-125956.112" - wire $and$libresoc.v:125956$5303_Y - attribute \src "libresoc.v:125958.19-125958.113" - wire $and$libresoc.v:125958$5305_Y - attribute \src "libresoc.v:125960.19-125960.121" - wire $and$libresoc.v:125960$5307_Y - attribute \src "libresoc.v:125964.19-125964.114" - wire $and$libresoc.v:125964$5311_Y - attribute \src "libresoc.v:125966.19-125966.112" - wire $and$libresoc.v:125966$5313_Y - attribute \src "libresoc.v:125968.19-125968.113" - wire $and$libresoc.v:125968$5315_Y - attribute \src "libresoc.v:125970.19-125970.132" - wire $and$libresoc.v:125970$5317_Y - attribute \src "libresoc.v:125973.18-125973.108" - wire $and$libresoc.v:125973$5320_Y - attribute \src "libresoc.v:125976.19-125976.114" - wire $and$libresoc.v:125976$5323_Y - attribute \src "libresoc.v:125978.19-125978.112" - wire $and$libresoc.v:125978$5325_Y - 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"libresoc.v:128413.3-128433.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5709 + attribute \src "libresoc.v:128820.3-128840.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$5786 + attribute \src "libresoc.v:128469.3-128489.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$5724 + attribute \src "libresoc.v:128740.3-128792.6" + wire width 3 $3\fsm_state$503$next[2:0]$5774 + attribute \src "libresoc.v:128606.3-128658.6" + wire width 3 $3\fsm_state$next[2:0]$5751 + attribute \src "libresoc.v:128573.3-128605.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$5745 + attribute \src "libresoc.v:128659.3-128685.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$5758 + attribute \src "libresoc.v:128301.3-128321.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5679 + attribute \src "libresoc.v:128686.3-128706.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5763 + attribute \src "libresoc.v:128357.3-128377.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5694 + attribute \src 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"libresoc.v:127842.18-127842.111" + wire $eq$libresoc.v:127842$5366_Y + attribute \src "libresoc.v:127853.18-127853.111" + wire $eq$libresoc.v:127853$5377_Y + attribute \src "libresoc.v:127886.17-127886.110" + wire $eq$libresoc.v:127886$5410_Y + attribute \src "libresoc.v:127887.18-127887.111" + wire $eq$libresoc.v:127887$5411_Y + attribute \src "libresoc.v:127898.18-127898.111" + wire $eq$libresoc.v:127898$5422_Y + attribute \src "libresoc.v:127920.18-127920.111" + wire $eq$libresoc.v:127920$5444_Y + attribute \src "libresoc.v:127964.18-127964.111" + wire $eq$libresoc.v:127964$5488_Y + attribute \src "libresoc.v:127975.18-127975.111" + wire $eq$libresoc.v:127975$5499_Y + attribute \src "libresoc.v:127976.19-127976.112" + wire $eq$libresoc.v:127976$5500_Y + attribute \src "libresoc.v:127977.19-127977.112" + wire $eq$libresoc.v:127977$5501_Y + attribute \src "libresoc.v:127979.19-127979.112" + wire $eq$libresoc.v:127979$5503_Y + attribute \src "libresoc.v:127982.19-127982.112" + wire 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$ternary$libresoc.v:127927$5451_Y + attribute \src "libresoc.v:127928.19-127928.133" + wire $ternary$libresoc.v:127928$5452_Y + attribute \src "libresoc.v:127929.19-127929.133" + wire $ternary$libresoc.v:127929$5453_Y + attribute \src "libresoc.v:127930.19-127930.133" + wire $ternary$libresoc.v:127930$5454_Y + attribute \src "libresoc.v:127932.19-127932.133" + wire $ternary$libresoc.v:127932$5456_Y + attribute \src "libresoc.v:127933.19-127933.133" + wire $ternary$libresoc.v:127933$5457_Y + attribute \src "libresoc.v:127934.19-127934.134" + wire $ternary$libresoc.v:127934$5458_Y + attribute \src "libresoc.v:127935.19-127935.134" + wire $ternary$libresoc.v:127935$5459_Y + attribute \src "libresoc.v:127936.19-127936.135" + wire $ternary$libresoc.v:127936$5460_Y + attribute \src "libresoc.v:127937.19-127937.133" + wire $ternary$libresoc.v:127937$5461_Y + attribute \src "libresoc.v:127938.19-127938.135" + wire $ternary$libresoc.v:127938$5462_Y + attribute \src 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attribute \src "libresoc.v:127951.19-127951.135" + wire $ternary$libresoc.v:127951$5475_Y + attribute \src "libresoc.v:127952.19-127952.135" + wire $ternary$libresoc.v:127952$5476_Y + attribute \src "libresoc.v:127954.19-127954.134" + wire $ternary$libresoc.v:127954$5478_Y + attribute \src "libresoc.v:127955.19-127955.135" + wire $ternary$libresoc.v:127955$5479_Y + attribute \src "libresoc.v:127956.19-127956.136" + wire $ternary$libresoc.v:127956$5480_Y + attribute \src "libresoc.v:127957.19-127957.135" + wire $ternary$libresoc.v:127957$5481_Y + attribute \src "libresoc.v:127958.19-127958.136" + wire $ternary$libresoc.v:127958$5482_Y + attribute \src "libresoc.v:127959.19-127959.136" + wire $ternary$libresoc.v:127959$5483_Y + attribute \src "libresoc.v:127960.19-127960.135" + wire $ternary$libresoc.v:127960$5484_Y + attribute \src "libresoc.v:127961.19-127961.136" + wire $ternary$libresoc.v:127961$5485_Y + attribute \src "libresoc.v:127962.19-127962.136" + wire $ternary$libresoc.v:127962$5486_Y + attribute \src "libresoc.v:127963.19-127963.135" + wire $ternary$libresoc.v:127963$5487_Y + attribute \src "libresoc.v:127965.19-127965.136" + wire $ternary$libresoc.v:127965$5489_Y + attribute \src "libresoc.v:127966.19-127966.136" + wire $ternary$libresoc.v:127966$5490_Y + attribute \src "libresoc.v:127967.19-127967.135" + wire $ternary$libresoc.v:127967$5491_Y + attribute \src "libresoc.v:127968.19-127968.136" + wire $ternary$libresoc.v:127968$5492_Y + attribute \src "libresoc.v:127969.19-127969.136" + wire $ternary$libresoc.v:127969$5493_Y + attribute \src "libresoc.v:127970.19-127970.135" + wire $ternary$libresoc.v:127970$5494_Y + attribute \src "libresoc.v:127971.19-127971.136" + wire $ternary$libresoc.v:127971$5495_Y + attribute \src "libresoc.v:127972.19-127972.136" + wire $ternary$libresoc.v:127972$5496_Y + attribute \src "libresoc.v:127973.19-127973.135" + wire $ternary$libresoc.v:127973$5497_Y + attribute \src "libresoc.v:127974.19-127974.136" + wire $ternary$libresoc.v:127974$5498_Y + attribute \src "libresoc.v:128061.18-128061.130" + wire $ternary$libresoc.v:128061$5586_Y + attribute \src "libresoc.v:128062.18-128062.130" + wire $ternary$libresoc.v:128062$5587_Y + attribute \src "libresoc.v:128063.18-128063.130" + wire $ternary$libresoc.v:128063$5588_Y + attribute \src "libresoc.v:128064.18-128064.131" + wire $ternary$libresoc.v:128064$5589_Y + attribute \src "libresoc.v:128066.18-128066.130" + wire $ternary$libresoc.v:128066$5591_Y + attribute \src "libresoc.v:128067.18-128067.131" + wire $ternary$libresoc.v:128067$5592_Y + attribute \src "libresoc.v:128068.18-128068.131" + wire $ternary$libresoc.v:128068$5593_Y + attribute \src "libresoc.v:128069.18-128069.130" + wire $ternary$libresoc.v:128069$5594_Y + attribute \src "libresoc.v:128070.18-128070.131" + wire $ternary$libresoc.v:128070$5595_Y + attribute \src "libresoc.v:128071.18-128071.132" + wire $ternary$libresoc.v:128071$5596_Y + attribute \src "libresoc.v:128072.18-128072.132" + wire $ternary$libresoc.v:128072$5597_Y + attribute \src "libresoc.v:128073.18-128073.133" + wire $ternary$libresoc.v:128073$5598_Y + attribute \src "libresoc.v:128074.18-128074.133" + wire $ternary$libresoc.v:128074$5599_Y + attribute \src "libresoc.v:128075.18-128075.132" + wire $ternary$libresoc.v:128075$5600_Y + attribute \src "libresoc.v:128077.18-128077.133" + wire $ternary$libresoc.v:128077$5602_Y + attribute \src "libresoc.v:128078.18-128078.133" + wire $ternary$libresoc.v:128078$5603_Y + attribute \src "libresoc.v:128079.18-128079.132" + wire $ternary$libresoc.v:128079$5604_Y + attribute \src "libresoc.v:128080.18-128080.133" + wire $ternary$libresoc.v:128080$5605_Y + attribute \src "libresoc.v:128081.18-128081.133" + wire $ternary$libresoc.v:128081$5606_Y + attribute \src "libresoc.v:128082.18-128082.132" + wire $ternary$libresoc.v:128082$5607_Y + attribute \src "libresoc.v:128083.18-128083.133" + wire $ternary$libresoc.v:128083$5608_Y + attribute \src "libresoc.v:128084.18-128084.133" + wire $ternary$libresoc.v:128084$5609_Y + attribute \src "libresoc.v:128085.18-128085.132" + wire $ternary$libresoc.v:128085$5610_Y + attribute \src "libresoc.v:128086.18-128086.133" + wire $ternary$libresoc.v:128086$5611_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$101 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$103 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$105 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$107 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$109 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$113 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$115 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$117 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$119 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$129 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$133 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$135 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$137 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$139 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$141 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$143 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$145 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$147 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$149 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$151 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$153 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$155 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$157 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$169 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$187 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$189 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$191 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$193 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$195 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$197 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$199 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$201 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$203 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$205 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$207 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$209 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$213 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$215 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$217 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$229 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$249 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$255 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - wire \$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$257 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - wire width 30 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - wire width 30 \$268 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$267 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$269 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - wire width 30 \$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - wire width 30 \$271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 8 \$273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - wire \$280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" - wire \$282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - wire width 5 \$284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - wire width 5 \$285 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - wire width 5 \$287 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - wire width 5 \$288 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$271 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$273 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$275 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$277 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$279 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$281 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$283 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$285 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$287 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$289 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$291 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$293 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$295 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$297 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$299 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$301 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$303 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$305 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$309 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$311 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$313 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$315 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$317 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$319 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$321 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$323 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$325 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$327 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$329 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$331 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$333 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$335 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$337 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$339 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$341 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$343 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$345 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$347 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$349 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$351 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$353 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$355 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$357 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$359 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$361 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$363 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$367 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$369 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$373 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$377 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$381 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$385 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$387 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$389 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$391 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$395 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$399 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$403 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$407 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$409 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$411 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$413 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$415 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$417 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$419 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$421 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$423 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$425 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$427 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$429 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$433 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$437 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$441 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$445 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$449 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$453 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$457 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$481 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + wire \$493 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$496 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$498 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$501 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$508 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + wire \$510 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$512 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$513 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$515 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$516 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$53 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$55 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$57 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$59 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$61 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$63 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$65 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$67 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$69 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$71 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$73 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$75 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$77 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$79 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$81 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$83 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$85 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$87 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$89 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" wire \$9 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$91 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$93 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$95 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$97 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 118 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 58 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire output 109 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 119 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 328 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 164 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 319 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 329 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire \_fsm_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \_fsm_isdr + wire \_fsm_capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" wire \_fsm_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" wire \_fsm_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:27" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire \_fsm_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:215" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" wire \_idblock_TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 \_irblock_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:129" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 6 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire input 4 \dmi0_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 output 120 \dmi0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dmi0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 330 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire width 8 \dmi0_addrsr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire \dmi0_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:130" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" wire \dmi0_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \dmi0_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \dmi0_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 8 \dmi0_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 8 \dmi0_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \dmi0_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \dmi0_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 64 \dmi0_datasr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 2 \dmi0_datasr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:132" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" wire width 2 \dmi0_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \dmi0_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire width 2 \dmi0_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \dmi0_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \dmi0_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \dmi0_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \dmi0_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \dmi0_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 output 3 \dmi0_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dmi0_din$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 input 5 \dmi0_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire output 1 \dmi0_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire output 2 \dmi0_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 10 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - wire width 3 \fsm_state$275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - wire width 3 \fsm_state$275$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 61 \gpio_gpio0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 11 \gpio_gpio0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 12 \gpio_gpio0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 10 \gpio_gpio0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 62 \gpio_gpio0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 63 \gpio_gpio0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 91 \gpio_gpio10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 41 \gpio_gpio10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 42 \gpio_gpio10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 40 \gpio_gpio10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 92 \gpio_gpio10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 93 \gpio_gpio10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 94 \gpio_gpio11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 44 \gpio_gpio11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 45 \gpio_gpio11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 43 \gpio_gpio11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 95 \gpio_gpio11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 96 \gpio_gpio11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 97 \gpio_gpio12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 47 \gpio_gpio12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 48 \gpio_gpio12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 46 \gpio_gpio12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 98 \gpio_gpio12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 99 \gpio_gpio12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 100 \gpio_gpio13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 50 \gpio_gpio13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 51 \gpio_gpio13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 49 \gpio_gpio13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 101 \gpio_gpio13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 102 \gpio_gpio13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 103 \gpio_gpio14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 53 \gpio_gpio14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 54 \gpio_gpio14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 52 \gpio_gpio14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 104 \gpio_gpio14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 105 \gpio_gpio14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 106 \gpio_gpio15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 56 \gpio_gpio15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 57 \gpio_gpio15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 55 \gpio_gpio15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 107 \gpio_gpio15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 108 \gpio_gpio15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 64 \gpio_gpio1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 14 \gpio_gpio1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 15 \gpio_gpio1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 13 \gpio_gpio1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 65 \gpio_gpio1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 66 \gpio_gpio1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 67 \gpio_gpio2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 17 \gpio_gpio2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 18 \gpio_gpio2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 16 \gpio_gpio2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 68 \gpio_gpio2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 69 \gpio_gpio2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 70 \gpio_gpio3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 20 \gpio_gpio3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 21 \gpio_gpio3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 19 \gpio_gpio3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 71 \gpio_gpio3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 72 \gpio_gpio3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 73 \gpio_gpio4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 23 \gpio_gpio4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 24 \gpio_gpio4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 22 \gpio_gpio4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 74 \gpio_gpio4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 75 \gpio_gpio4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 76 \gpio_gpio5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 26 \gpio_gpio5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 27 \gpio_gpio5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 25 \gpio_gpio5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 77 \gpio_gpio5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 78 \gpio_gpio5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 79 \gpio_gpio6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 29 \gpio_gpio6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 30 \gpio_gpio6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 28 \gpio_gpio6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 80 \gpio_gpio6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 81 \gpio_gpio6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 82 \gpio_gpio7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 32 \gpio_gpio7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 33 \gpio_gpio7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 31 \gpio_gpio7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 83 \gpio_gpio7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 84 \gpio_gpio7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 85 \gpio_gpio8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 35 \gpio_gpio8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 36 \gpio_gpio8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 34 \gpio_gpio8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 86 \gpio_gpio8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 87 \gpio_gpio8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 88 \gpio_gpio9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 38 \gpio_gpio9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 39 \gpio_gpio9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 37 \gpio_gpio9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 89 \gpio_gpio9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 90 \gpio_gpio9__pad__oe - attribute \src "libresoc.v:125175.7-125175.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s7__pad__oe + attribute \src "libresoc.v:126401.7-126401.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" - wire width 50 \io_bd - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:437" - wire width 50 \io_bd$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:376" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" wire \io_bd2io - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:373" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" wire \io_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" - wire width 50 \io_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:436" - wire width 50 \io_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 116 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 output 110 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 326 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 320 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 112 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 input 117 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 output 115 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 327 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 325 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 111 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 113 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 114 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 324 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire \jtag_wb_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire \jtag_wb_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \jtag_wb_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \jtag_wb_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 29 \jtag_wb_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 29 \jtag_wb_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \jtag_wb_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \jtag_wb_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 64 \jtag_wb_datasr__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 2 \jtag_wb_datasr__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:82" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" wire width 2 \jtag_wb_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \jtag_wb_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire width 2 \jtag_wb_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \jtag_wb_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 64 \jtag_wb_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \jtag_wb_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \jtag_wb_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \jtag_wb_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:30" - wire \negjtag_rst attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 7 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire \sr0__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire \sr0__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:534" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" wire \sr0_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:533" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" wire \sr0_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:530" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" wire width 3 \sr0_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:535" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" wire \sr0_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:536" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" wire \sr0_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr0_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:547" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" wire \sr0_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr0_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 60 \uart_rx__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 9 \uart_rx__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 8 \uart_tx__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 59 \uart_tx__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:201" - cell $add $add$libresoc.v:126011$5358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire output 8 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire output 9 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:128051$5575 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -198354,10 +202075,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:126011$5358_Y + connect \Y $add$libresoc.v:128051$5575_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:225" - cell $add $add$libresoc.v:126012$5359 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:128053$5577 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -198365,329 +202086,384 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:126012$5359_Y + connect \Y $add$libresoc.v:128053$5577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:153" - cell $add $add$libresoc.v:126019$5367 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:128059$5584 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \dmi0_addr_i + connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:126019$5367_Y + connect \Y $add$libresoc.v:128059$5584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:177" - cell $add $add$libresoc.v:126020$5368 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:128060$5585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \dmi0_addr_i + connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:126020$5368_Y + connect \Y $add$libresoc.v:128060$5585_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $and $and$libresoc.v:125944$5291 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:127875$5399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:127875$5399_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:127942$5466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$145 - connect \Y $and$libresoc.v:125944$5291_Y + connect \B \$27 + connect \Y $and$libresoc.v:127942$5466_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:127953$5477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:127953$5477_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:125951$5298 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:127981$5505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$157 - connect \Y $and$libresoc.v:125951$5298_Y + connect \B \$367 + connect \Y $and$libresoc.v:127981$5505_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:125954$5301 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127984$5508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$163 + connect \A \$373 connect \B \_fsm_capture - connect \Y $and$libresoc.v:125954$5301_Y + connect \Y $and$libresoc.v:127984$5508_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:125956$5303 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127987$5511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$167 + connect \A \$377 connect \B \_fsm_shift - connect \Y $and$libresoc.v:125956$5303_Y + connect \Y $and$libresoc.v:127987$5511_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:125958$5305 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:127989$5513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$171 + connect \A \$381 connect \B \_fsm_update - connect \Y $and$libresoc.v:125958$5305_Y + connect \Y $and$libresoc.v:127989$5513_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:125960$5307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:127991$5515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev - connect \B \$175 - connect \Y $and$libresoc.v:125960$5307_Y + connect \B \$385 + connect \Y $and$libresoc.v:127991$5515_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:125964$5311 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:127994$5518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$181 + connect \A \$391 connect \B \_fsm_capture - connect \Y $and$libresoc.v:125964$5311_Y + connect \Y $and$libresoc.v:127994$5518_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:125966$5313 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:127996$5520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$185 + connect \A \$395 connect \B \_fsm_shift - connect \Y $and$libresoc.v:125966$5313_Y + connect \Y $and$libresoc.v:127996$5520_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:125968$5315 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:128000$5524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$189 + connect \A \$399 connect \B \_fsm_update - connect \Y $and$libresoc.v:125968$5315_Y + connect \Y $and$libresoc.v:128000$5524_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:125970$5317 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:128002$5526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$193 - connect \Y $and$libresoc.v:125970$5317_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:125973$5320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$17 - connect \Y $and$libresoc.v:125973$5320_Y + connect \B \$403 + connect \Y $and$libresoc.v:128002$5526_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:125976$5323 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:128006$5530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$201 + connect \A \$411 connect \B \_fsm_capture - connect \Y $and$libresoc.v:125976$5323_Y + connect \Y $and$libresoc.v:128006$5530_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:125978$5325 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:128008$5532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$205 + connect \A \$415 connect \B \_fsm_shift - connect \Y $and$libresoc.v:125978$5325_Y + connect \Y $and$libresoc.v:128008$5532_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:125980$5327 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:128011$5535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$209 + connect \A \$419 connect \B \_fsm_update - connect \Y $and$libresoc.v:125980$5327_Y + connect \Y $and$libresoc.v:128011$5535_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:125982$5329 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:128013$5537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev - connect \B \$213 - connect \Y $and$libresoc.v:125982$5329_Y + connect \B \$423 + connect \Y $and$libresoc.v:128013$5537_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:125984$5331 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:128016$5540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:125984$5331_Y + connect \A \$429 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:128016$5540_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:125986$5333 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:128018$5542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$219 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:125986$5333_Y + connect \A \$433 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:128018$5542_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:125988$5335 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:128020$5544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$223 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:125988$5335_Y + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:128020$5544_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:125990$5337 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:128021$5545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$227 + connect \A \$437 connect \B \_fsm_update - connect \Y $and$libresoc.v:125990$5337_Y + connect \Y $and$libresoc.v:128021$5545_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:125992$5339 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:128023$5547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev - connect \B \$231 - connect \Y $and$libresoc.v:125992$5339_Y + connect \B \$441 + connect \Y $and$libresoc.v:128023$5547_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $and $and$libresoc.v:125997$5344 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:128027$5551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$239 + connect \A \$449 connect \B \_fsm_capture - connect \Y $and$libresoc.v:125997$5344_Y + connect \Y $and$libresoc.v:128027$5551_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $and $and$libresoc.v:125999$5346 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:128029$5553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$243 + connect \A \$453 connect \B \_fsm_shift - connect \Y $and$libresoc.v:125999$5346_Y + connect \Y $and$libresoc.v:128029$5553_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:128031$5555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:128031$5555_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $and $and$libresoc.v:126001$5348 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:128032$5556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$247 + connect \A \$457 connect \B \_fsm_update - connect \Y $and$libresoc.v:126001$5348_Y + connect \Y $and$libresoc.v:128032$5556_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $and $and$libresoc.v:126003$5350 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:128034$5558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev - connect \B \$251 - connect \Y $and$libresoc.v:126003$5350_Y + connect \B \$461 + connect \Y $and$libresoc.v:128034$5558_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $and $and$libresoc.v:126023$5371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:128037$5561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$31 - connect \Y $and$libresoc.v:126023$5371_Y + connect \A \$467 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:128037$5561_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:126024$5372 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:128039$5563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$33 + connect \A \$471 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:128039$5563_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:128041$5565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$475 connect \B \_fsm_update - connect \Y $and$libresoc.v:126024$5372_Y + connect \Y $and$libresoc.v:128041$5565_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:382" - cell $and $and$libresoc.v:126048$5396 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:128044$5568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:126048$5396_Y + connect \A \sr5_update_core_prev + connect \B \$479 + connect \Y $and$libresoc.v:128044$5568_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $and $and$libresoc.v:128076$5601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$5 + connect \Y $and$libresoc.v:128076$5601_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125917$5264 + cell $eq $eq$libresoc.v:127831$5355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:127831$5355_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127842$5366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198695,10 +202471,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:125917$5264_Y + connect \Y $eq$libresoc.v:127842$5366_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125928$5275 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127853$5377 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198706,10 +202482,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:125928$5275_Y + connect \Y $eq$libresoc.v:127853$5377_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:125941$5288 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:127886$5410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198717,21 +202493,43 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:125941$5288_Y + connect \Y $eq$libresoc.v:127886$5410_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $eq $eq$libresoc.v:125942$5289 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127887$5411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:125942$5289_Y + connect \B 1'0 + connect \Y $eq$libresoc.v:127887$5411_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125945$5292 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127898$5422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127898$5422_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127920$5444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:127920$5444_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127964$5488 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198739,10 +202537,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:125945$5292_Y + connect \Y $eq$libresoc.v:127964$5488_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125946$5293 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127975$5499 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198750,10 +202548,21 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:125946$5293_Y + connect \Y $eq$libresoc.v:127975$5499_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127976$5500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:127976$5500_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:125948$5295 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:127977$5501 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198761,10 +202570,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:125948$5295_Y + connect \Y $eq$libresoc.v:127977$5501_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:125950$5297 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127979$5503 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198772,10 +202581,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:125950$5297_Y + connect \Y $eq$libresoc.v:127979$5503_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125952$5299 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127982$5506 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198783,10 +202592,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:125952$5299_Y + connect \Y $eq$libresoc.v:127982$5506_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125962$5309 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:127992$5516 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198794,32 +202603,43 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:125962$5309_Y + connect \Y $eq$libresoc.v:127992$5516_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125971$5318 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:127997$5521 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 3'110 - connect \Y $eq$libresoc.v:125971$5318_Y + connect \B 4'1111 + connect \Y $eq$libresoc.v:127997$5521_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125972$5319 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:127998$5522 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:125972$5319_Y + connect \B 2'10 + connect \Y $eq$libresoc.v:127998$5522_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128003$5527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:128003$5527_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125974$5321 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128004$5528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198827,10 +202647,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:125974$5321_Y + connect \Y $eq$libresoc.v:128004$5528_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125983$5330 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128014$5538 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198838,10 +202658,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:125983$5330_Y + connect \Y $eq$libresoc.v:128014$5538_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125993$5340 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128024$5548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198849,10 +202669,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:125993$5340_Y + connect \Y $eq$libresoc.v:128024$5548_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:538" - cell $eq $eq$libresoc.v:125994$5341 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128025$5549 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -198860,43 +202680,43 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:125994$5341_Y + connect \Y $eq$libresoc.v:128025$5549_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:125995$5342 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:128035$5559 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:125995$5342_Y + connect \B 4'1011 + connect \Y $eq$libresoc.v:128035$5559_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - cell $eq $eq$libresoc.v:126004$5351 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $eq$libresoc.v:128042$5566 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state + connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:126004$5351_Y + connect \Y $eq$libresoc.v:128042$5566_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:126006$5353 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $eq $eq$libresoc.v:128045$5569 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:126006$5353_Y + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:128045$5569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $eq $eq$libresoc.v:126007$5354 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:128047$5571 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -198904,10 +202724,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:126007$5354_Y + connect \Y $eq$libresoc.v:128047$5571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $eq $eq$libresoc.v:126008$5355 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:128048$5572 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -198915,10 +202735,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:126008$5355_Y + connect \Y $eq$libresoc.v:128048$5572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:231" - cell $eq $eq$libresoc.v:126010$5357 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + cell $eq $eq$libresoc.v:128050$5574 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -198926,95 +202746,62 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:126010$5357_Y + connect \Y $eq$libresoc.v:128050$5574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $eq $eq$libresoc.v:126014$5362 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $eq$libresoc.v:128052$5576 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 1'1 - connect \Y $eq$libresoc.v:126014$5362_Y + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:128052$5576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $eq $eq$libresoc.v:126015$5363 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:128055$5580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 2'10 - connect \Y $eq$libresoc.v:126015$5363_Y + connect \A \fsm_state$503 + connect \B 1'1 + connect \Y $eq$libresoc.v:128055$5580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:183" - cell $eq $eq$libresoc.v:126018$5366 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:128056$5581 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$275 - connect \B 2'10 - connect \Y $eq$libresoc.v:126018$5366_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:379" - cell $eq $eq$libresoc.v:126021$5369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir + connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:126021$5369_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $eq $eq$libresoc.v:126025$5373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:126025$5373_Y + connect \Y $eq$libresoc.v:128056$5581_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:126026$5374 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + cell $eq $eq$libresoc.v:128058$5583 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \_irblock_ir + connect \A \fsm_state$503 connect \B 2'10 - connect \Y $eq$libresoc.v:126026$5374_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:386" - cell $eq $eq$libresoc.v:126027$5375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:126027$5375_Y + connect \Y $eq$libresoc.v:128058$5583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - cell $pos $extend$libresoc.v:126013$5360 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $extend$libresoc.v:128054$5578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 - connect \A \dmi0_addr_i - connect \Y $extend$libresoc.v:126013$5360_Y + connect \A \dmi0__addr_i + connect \Y $extend$libresoc.v:128054$5578_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:125953$5300 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127983$5507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199022,10 +202809,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125953$5300_Y + connect \Y $ne$libresoc.v:127983$5507_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:125955$5302 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127985$5509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199033,10 +202820,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125955$5302_Y + connect \Y $ne$libresoc.v:127985$5509_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:125957$5304 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127988$5512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199044,10 +202831,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125957$5304_Y + connect \Y $ne$libresoc.v:127988$5512_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:125963$5310 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:127993$5517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199055,10 +202842,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125963$5310_Y + connect \Y $ne$libresoc.v:127993$5517_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:125965$5312 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:127995$5519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199066,10 +202853,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125965$5312_Y + connect \Y $ne$libresoc.v:127995$5519_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:125967$5314 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:127999$5523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199077,10 +202864,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125967$5314_Y + connect \Y $ne$libresoc.v:127999$5523_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:125975$5322 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:128005$5529 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199088,10 +202875,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125975$5322_Y + connect \Y $ne$libresoc.v:128005$5529_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:125977$5324 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:128007$5531 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199099,10 +202886,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125977$5324_Y + connect \Y $ne$libresoc.v:128007$5531_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:125979$5326 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:128010$5534 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199110,10 +202897,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125979$5326_Y + connect \Y $ne$libresoc.v:128010$5534_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:125985$5332 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:128015$5539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199121,10 +202908,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125985$5332_Y + connect \Y $ne$libresoc.v:128015$5539_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:125987$5334 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:128017$5541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199132,10 +202919,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125987$5334_Y + connect \Y $ne$libresoc.v:128017$5541_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:125989$5336 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:128019$5543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199143,10 +202930,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125989$5336_Y + connect \Y $ne$libresoc.v:128019$5543_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:539" - cell $ne $ne$libresoc.v:125996$5343 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:128026$5550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199154,10 +202941,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125996$5343_Y + connect \Y $ne$libresoc.v:128026$5550_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:540" - cell $ne $ne$libresoc.v:125998$5345 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:128028$5552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199165,10 +202952,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:125998$5345_Y + connect \Y $ne$libresoc.v:128028$5552_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:541" - cell $ne $ne$libresoc.v:126000$5347 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:128030$5554 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -199176,157 +202963,198 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:126000$5347_Y + connect \Y $ne$libresoc.v:128030$5554_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:128036$5560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:128036$5560_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:128038$5562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:128038$5562_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:128040$5564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:128040$5564_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:125959$5306 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:127990$5514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:125959$5306_Y + connect \Y $not$libresoc.v:127990$5514_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:125969$5316 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:128001$5525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:125969$5316_Y + connect \Y $not$libresoc.v:128001$5525_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:125981$5328 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:128012$5536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:125981$5328_Y + connect \Y $not$libresoc.v:128012$5536_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:125991$5338 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:128022$5546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:125991$5338_Y + connect \Y $not$libresoc.v:128022$5546_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - cell $not $not$libresoc.v:126002$5349 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:128033$5557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:126002$5349_Y + connect \Y $not$libresoc.v:128033$5557_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:229" - cell $not $not$libresoc.v:126005$5352 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:128043$5567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$256 - connect \Y $not$libresoc.v:126005$5352_Y + connect \A \sr5_update_core + connect \Y $not$libresoc.v:128043$5567_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:125939$5286 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:128046$5570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:128046$5570_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127864$5388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \$11 - connect \Y $or$libresoc.v:125939$5286_Y + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:127864$5388_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:362" - cell $or $or$libresoc.v:125943$5290 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127909$5433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$141 - connect \B \$143 - connect \Y $or$libresoc.v:125943$5290_Y + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:127909$5433_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:125947$5294 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:127931$5455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$149 - connect \B \$151 - connect \Y $or$libresoc.v:125947$5294_Y + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:127931$5455_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:125949$5296 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127978$5502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$153 - connect \B \$155 - connect \Y $or$libresoc.v:125949$5296_Y + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:127978$5502_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:125961$5308 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:127980$5504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$13 - connect \B \$15 - connect \Y $or$libresoc.v:125961$5308_Y + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:127980$5504_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:230" - cell $or $or$libresoc.v:126009$5356 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:127986$5510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$259 - connect \B \$261 - connect \Y $or$libresoc.v:126009$5356_Y + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:127986$5510_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:126016$5364 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:128009$5533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:126016$5364_Y + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:128009$5533_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:182" - cell $or $or$libresoc.v:126017$5365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:128049$5573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$276 - connect \B \$278 - connect \Y $or$libresoc.v:126017$5365_Y + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:128049$5573_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:380" - cell $or $or$libresoc.v:126022$5370 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:128057$5582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$27 - connect \B \$29 - connect \Y $or$libresoc.v:126022$5370_Y + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:128057$5582_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $or $or$libresoc.v:126037$5385 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:128065$5590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -199334,418 +203162,1250 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:126037$5385_Y + connect \Y $or$libresoc.v:128065$5590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - cell $pos $pos$libresoc.v:126013$5361 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:128054$5579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:126013$5360_Y - connect \Y $pos$libresoc.v:126013$5361_Y + connect \A $extend$libresoc.v:128054$5578_Y + connect \Y $pos$libresoc.v:128054$5579_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125918$5265 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127832$5356 parameter \WIDTH 1 - connect \A \gpio_gpio9__pad__i - connect \B \io_bd [29] + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125918$5265_Y + connect \Y $ternary$libresoc.v:127832$5356_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125919$5266 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127833$5357 parameter \WIDTH 1 - connect \A \gpio_gpio9__core__o - connect \B \io_bd [30] + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127833$5357_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127834$5358 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127834$5358_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127835$5359 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127835$5359_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127836$5360 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127836$5360_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127837$5361 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125919$5266_Y + connect \Y $ternary$libresoc.v:127837$5361_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125920$5267 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127838$5362 parameter \WIDTH 1 - connect \A \gpio_gpio9__core__oe + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127838$5362_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127839$5363 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125920$5267_Y + connect \Y $ternary$libresoc.v:127839$5363_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125921$5268 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127840$5364 parameter \WIDTH 1 - connect \A \gpio_gpio10__pad__i + connect \A \gpio_s1__core__oe connect \B \io_bd [32] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125921$5268_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127840$5364_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125922$5269 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127841$5365 parameter \WIDTH 1 - connect \A \gpio_gpio10__core__o + connect \A \gpio_s2__pad__i connect \B \io_bd [33] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125922$5269_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127841$5365_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125923$5270 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127843$5367 parameter \WIDTH 1 - connect \A \gpio_gpio10__core__oe + connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125923$5270_Y + connect \Y $ternary$libresoc.v:127843$5367_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125924$5271 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127844$5368 parameter \WIDTH 1 - connect \A \gpio_gpio11__pad__i + connect \A \gpio_s2__core__oe connect \B \io_bd [35] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125924$5271_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127844$5368_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125925$5272 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127845$5369 parameter \WIDTH 1 - connect \A \gpio_gpio11__core__o + connect \A \gpio_s3__pad__i connect \B \io_bd [36] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125925$5272_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127845$5369_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125926$5273 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127846$5370 parameter \WIDTH 1 - connect \A \gpio_gpio11__core__oe + connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125926$5273_Y + connect \Y $ternary$libresoc.v:127846$5370_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125927$5274 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127847$5371 parameter \WIDTH 1 - connect \A \gpio_gpio12__pad__i + connect \A \gpio_s3__core__oe connect \B \io_bd [38] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125927$5274_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127847$5371_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125929$5276 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127848$5372 parameter \WIDTH 1 - connect \A \gpio_gpio12__core__o + connect \A \gpio_s4__pad__i connect \B \io_bd [39] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125929$5276_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127848$5372_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125930$5277 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127849$5373 parameter \WIDTH 1 - connect \A \gpio_gpio12__core__oe + connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125930$5277_Y + connect \Y $ternary$libresoc.v:127849$5373_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125931$5278 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127850$5374 parameter \WIDTH 1 - connect \A \gpio_gpio13__pad__i + connect \A \gpio_s4__core__oe connect \B \io_bd [41] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125931$5278_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127850$5374_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125932$5279 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127851$5375 parameter \WIDTH 1 - connect \A \gpio_gpio13__core__o + connect \A \gpio_s5__pad__i connect \B \io_bd [42] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125932$5279_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127851$5375_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125933$5280 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127852$5376 parameter \WIDTH 1 - connect \A \gpio_gpio13__core__oe + connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125933$5280_Y + connect \Y $ternary$libresoc.v:127852$5376_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125934$5281 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127854$5378 parameter \WIDTH 1 - connect \A \gpio_gpio14__pad__i + connect \A \gpio_s5__core__oe connect \B \io_bd [44] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125934$5281_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127854$5378_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125935$5282 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127855$5379 parameter \WIDTH 1 - connect \A \gpio_gpio14__core__o + connect \A \gpio_s6__pad__i connect \B \io_bd [45] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125935$5282_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127855$5379_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125936$5283 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127856$5380 parameter \WIDTH 1 - connect \A \gpio_gpio14__core__oe + connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125936$5283_Y + connect \Y $ternary$libresoc.v:127856$5380_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:125937$5284 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127857$5381 parameter \WIDTH 1 - connect \A \gpio_gpio15__pad__i + connect \A \gpio_s6__core__oe connect \B \io_bd [47] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:125937$5284_Y + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127857$5381_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:125938$5285 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127858$5382 parameter \WIDTH 1 - connect \A \gpio_gpio15__core__o + connect \A \gpio_s7__pad__i connect \B \io_bd [48] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125938$5285_Y + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127858$5382_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:125940$5287 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127859$5383 parameter \WIDTH 1 - connect \A \gpio_gpio15__core__oe + connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:125940$5287_Y + connect \Y $ternary$libresoc.v:127859$5383_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:475" - cell $mux $ternary$libresoc.v:126028$5376 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127860$5384 parameter \WIDTH 1 - connect \A \uart_tx__core__o - connect \B \io_bd [0] + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126028$5376_Y + connect \Y $ternary$libresoc.v:127860$5384_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:472" - cell $mux $ternary$libresoc.v:126029$5377 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127861$5385 parameter \WIDTH 1 - connect \A \uart_rx__pad__i - connect \B \io_bd [1] + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127861$5385_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127862$5386 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127862$5386_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127863$5387 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127863$5387_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127865$5389 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126029$5377_Y + connect \Y $ternary$libresoc.v:127865$5389_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126030$5378 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127866$5390 parameter \WIDTH 1 - connect \A \gpio_gpio0__pad__i - connect \B \io_bd [2] + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127866$5390_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127867$5391 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127867$5391_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127868$5392 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127868$5392_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:127869$5393 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126030$5378_Y + connect \Y $ternary$libresoc.v:127869$5393_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126031$5379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127870$5394 parameter \WIDTH 1 - connect \A \gpio_gpio0__core__o - connect \B \io_bd [3] + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127870$5394_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127871$5395 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126031$5379_Y + connect \Y $ternary$libresoc.v:127871$5395_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126032$5380 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127872$5396 parameter \WIDTH 1 - connect \A \gpio_gpio0__core__oe - connect \B \io_bd [4] + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126032$5380_Y + connect \Y $ternary$libresoc.v:127872$5396_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126033$5381 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127873$5397 parameter \WIDTH 1 - connect \A \gpio_gpio1__pad__i - connect \B \io_bd [5] + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127873$5397_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127874$5398 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127874$5398_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127876$5400 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127876$5400_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127877$5401 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126033$5381_Y + connect \Y $ternary$libresoc.v:127877$5401_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126034$5382 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127878$5402 parameter \WIDTH 1 - connect \A \gpio_gpio1__core__o - connect \B \io_bd [6] + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126034$5382_Y + connect \Y $ternary$libresoc.v:127878$5402_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126035$5383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127879$5403 parameter \WIDTH 1 - connect \A \gpio_gpio1__core__oe - connect \B \io_bd [7] + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126035$5383_Y + connect \Y $ternary$libresoc.v:127879$5403_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126036$5384 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127880$5404 parameter \WIDTH 1 - connect \A \gpio_gpio2__pad__i - connect \B \io_bd [8] + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127880$5404_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127881$5405 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126036$5384_Y + connect \Y $ternary$libresoc.v:127881$5405_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126038$5386 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127882$5406 parameter \WIDTH 1 - connect \A \gpio_gpio2__core__o - connect \B \io_bd [9] + connect \A \sd0_data0__core__o + connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126038$5386_Y + connect \Y $ternary$libresoc.v:127882$5406_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126039$5387 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127883$5407 parameter \WIDTH 1 - connect \A \gpio_gpio2__core__oe - connect \B \io_bd [10] + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126039$5387_Y + connect \Y $ternary$libresoc.v:127883$5407_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126040$5388 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127884$5408 parameter \WIDTH 1 - connect \A \gpio_gpio3__pad__i - connect \B \io_bd [11] + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126040$5388_Y + connect \Y $ternary$libresoc.v:127884$5408_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126041$5389 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127885$5409 parameter \WIDTH 1 - connect \A \gpio_gpio3__core__o - connect \B \io_bd [12] + connect \A \sd0_data1__core__o + connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126041$5389_Y + connect \Y $ternary$libresoc.v:127885$5409_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126042$5390 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127888$5412 parameter \WIDTH 1 - connect \A \gpio_gpio3__core__oe - connect \B \io_bd [13] + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126042$5390_Y + connect \Y $ternary$libresoc.v:127888$5412_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126043$5391 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127889$5413 parameter \WIDTH 1 - connect \A \gpio_gpio4__pad__i - connect \B \io_bd [14] + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126043$5391_Y + connect \Y $ternary$libresoc.v:127889$5413_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126044$5392 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127890$5414 parameter \WIDTH 1 - connect \A \gpio_gpio4__core__o - connect \B \io_bd [15] + connect \A \sd0_data2__core__o + connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126044$5392_Y + connect \Y $ternary$libresoc.v:127890$5414_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126045$5393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127891$5415 parameter \WIDTH 1 - connect \A \gpio_gpio4__core__oe - connect \B \io_bd [16] + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126045$5393_Y + connect \Y $ternary$libresoc.v:127891$5415_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126046$5394 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127892$5416 parameter \WIDTH 1 - connect \A \gpio_gpio5__pad__i - connect \B \io_bd [17] + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126046$5394_Y + connect \Y $ternary$libresoc.v:127892$5416_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126047$5395 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127893$5417 parameter \WIDTH 1 - connect \A \gpio_gpio5__core__o - connect \B \io_bd [18] + connect \A \sd0_data3__core__o + connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126047$5395_Y + connect \Y $ternary$libresoc.v:127893$5417_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126049$5397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127894$5418 parameter \WIDTH 1 - connect \A \gpio_gpio5__core__oe - connect \B \io_bd [19] + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126049$5397_Y + connect \Y $ternary$libresoc.v:127894$5418_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126050$5398 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127895$5419 parameter \WIDTH 1 - connect \A \gpio_gpio6__pad__i - connect \B \io_bd [20] + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127895$5419_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127896$5420 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126050$5398_Y + connect \Y $ternary$libresoc.v:127896$5420_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126051$5399 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127897$5421 parameter \WIDTH 1 - connect \A \gpio_gpio6__core__o - connect \B \io_bd [21] + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126051$5399_Y + connect \Y $ternary$libresoc.v:127897$5421_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126052$5400 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127899$5423 parameter \WIDTH 1 - connect \A \gpio_gpio6__core__oe - connect \B \io_bd [22] + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126052$5400_Y + connect \Y $ternary$libresoc.v:127899$5423_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126053$5401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127900$5424 parameter \WIDTH 1 - connect \A \gpio_gpio7__pad__i - connect \B \io_bd [23] + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126053$5401_Y + connect \Y $ternary$libresoc.v:127900$5424_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126054$5402 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127901$5425 parameter \WIDTH 1 - connect \A \gpio_gpio7__core__o - connect \B \io_bd [24] + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126054$5402_Y + connect \Y $ternary$libresoc.v:127901$5425_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126055$5403 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127902$5426 parameter \WIDTH 1 - connect \A \gpio_gpio7__core__oe - connect \B \io_bd [25] + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126055$5403_Y + connect \Y $ternary$libresoc.v:127902$5426_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - cell $mux $ternary$libresoc.v:126056$5404 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127903$5427 parameter \WIDTH 1 - connect \A \gpio_gpio8__pad__i - connect \B \io_bd [26] + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:126056$5404_Y + connect \Y $ternary$libresoc.v:127903$5427_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:486" - cell $mux $ternary$libresoc.v:126057$5405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127904$5428 parameter \WIDTH 1 - connect \A \gpio_gpio8__core__o - connect \B \io_bd [27] + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126057$5405_Y + connect \Y $ternary$libresoc.v:127904$5428_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:487" - cell $mux $ternary$libresoc.v:126058$5406 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127905$5429 parameter \WIDTH 1 - connect \A \gpio_gpio8__core__oe - connect \B \io_bd [28] + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127905$5429_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127906$5430 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127906$5430_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127907$5431 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127907$5431_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127908$5432 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127908$5432_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127910$5434 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127910$5434_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127911$5435 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127911$5435_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127912$5436 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127912$5436_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127913$5437 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127913$5437_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127914$5438 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127914$5438_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127915$5439 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127915$5439_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127916$5440 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127916$5440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127917$5441 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127917$5441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127918$5442 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127918$5442_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127919$5443 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127919$5443_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127921$5445 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127921$5445_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127922$5446 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127922$5446_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127923$5447 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127923$5447_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127924$5448 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127924$5448_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127925$5449 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127925$5449_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127926$5450 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127926$5450_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127927$5451 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127927$5451_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127928$5452 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127928$5452_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127929$5453 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127929$5453_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127930$5454 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127930$5454_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127932$5456 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127932$5456_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127933$5457 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127933$5457_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127934$5458 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127934$5458_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127935$5459 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127935$5459_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127936$5460 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127936$5460_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127937$5461 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127937$5461_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127938$5462 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127938$5462_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127939$5463 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127939$5463_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127940$5464 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127940$5464_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127941$5465 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127941$5465_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127943$5467 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127943$5467_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127944$5468 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127944$5468_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:127945$5469 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127945$5469_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127946$5470 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127946$5470_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127947$5471 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127947$5471_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127948$5472 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127948$5472_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127949$5473 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127949$5473_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127950$5474 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127950$5474_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127951$5475 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127951$5475_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127952$5476 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127952$5476_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127954$5478 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127954$5478_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127955$5479 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127955$5479_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127956$5480 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127956$5480_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127957$5481 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127957$5481_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127958$5482 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127958$5482_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127959$5483 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127959$5483_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127960$5484 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127960$5484_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127961$5485 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127961$5485_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127962$5486 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127962$5486_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127963$5487 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127963$5487_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127965$5489 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127965$5489_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127966$5490 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127966$5490_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127967$5491 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127967$5491_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127968$5492 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127968$5492_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127969$5493 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127969$5493_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127970$5494 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127970$5494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127971$5495 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127971$5495_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:127972$5496 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:127972$5496_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:127973$5497 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127973$5497_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:127974$5498 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:127974$5498_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:128061$5586 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128061$5586_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:128062$5587 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128062$5587_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:128063$5588 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128063$5588_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128064$5589 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128064$5589_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128066$5591 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128066$5591_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128067$5592 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128067$5592_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128068$5593 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128068$5593_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128069$5594 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128069$5594_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128070$5595 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128070$5595_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128071$5596 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128071$5596_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128072$5597 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128072$5597_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128073$5598 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128073$5598_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128074$5599 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128074$5599_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128075$5600 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128075$5600_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128077$5602 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128077$5602_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128078$5603 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128078$5603_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128079$5604 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128079$5604_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128080$5605 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128080$5605_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128081$5606 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128081$5606_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128082$5607 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128082$5607_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128083$5608 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128083$5608_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:128084$5609 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:128084$5609_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:128085$5610 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:128085$5610_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:128086$5611 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:126058$5406_Y + connect \Y $ternary$libresoc.v:128086$5611_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126119.8-126131.4" + attribute \src "libresoc.v:128159.8-128171.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -199760,20 +204420,20 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:126132.12-126142.4" + attribute \src "libresoc.v:128172.12-128182.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isdr \_fsm_isdr + connect \id_bypass \_idblock_id_bypass connect \posjtag_clk \posjtag_clk connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id connect \shift \_fsm_shift connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:126143.12-126153.4" + attribute \src "libresoc.v:128183.12-128193.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -199785,1234 +204445,962 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:125175.7-125175.20" - process $proc$libresoc.v:125175$5569 + attribute \src "libresoc.v:126401.7-126401.20" + process $proc$libresoc.v:126401$5803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125501.13-125501.31" - process $proc$libresoc.v:125501$5570 + attribute \src "libresoc.v:126959.13-126959.32" + process $proc$libresoc.v:126959$5804 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:126964.14-126964.46" + process $proc$libresoc.v:126964$5805 assign { } { } - assign $1\dmi0_addr_i[3:0] 4'0000 + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dmi0_addr_i $1\dmi0_addr_i[3:0] + update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:125509.7-125509.29" - process $proc$libresoc.v:125509$5571 + attribute \src "libresoc.v:126978.7-126978.29" + process $proc$libresoc.v:126978$5806 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:125517.13-125517.36" - process $proc$libresoc.v:125517$5572 + attribute \src "libresoc.v:126986.13-126986.36" + process $proc$libresoc.v:126986$5807 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:125525.7-125525.37" - process $proc$libresoc.v:125525$5573 + attribute \src "libresoc.v:126994.7-126994.37" + process $proc$libresoc.v:126994$5808 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:125529.7-125529.42" - process $proc$libresoc.v:125529$5574 + attribute \src "libresoc.v:126998.7-126998.42" + process $proc$libresoc.v:126998$5809 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:125533.14-125533.51" - process $proc$libresoc.v:125533$5575 + attribute \src "libresoc.v:127002.14-127002.51" + process $proc$libresoc.v:127002$5810 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:125539.13-125539.35" - process $proc$libresoc.v:125539$5576 + attribute \src "libresoc.v:127008.13-127008.35" + process $proc$libresoc.v:127008$5811 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:125547.14-125547.52" - process $proc$libresoc.v:125547$5577 + attribute \src "libresoc.v:127016.14-127016.52" + process $proc$libresoc.v:127016$5812 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:125555.7-125555.37" - process $proc$libresoc.v:125555$5578 + attribute \src "libresoc.v:127024.7-127024.37" + process $proc$libresoc.v:127024$5813 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:125559.7-125559.42" - process $proc$libresoc.v:125559$5579 + attribute \src "libresoc.v:127028.7-127028.42" + process $proc$libresoc.v:127028$5814 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:125564.14-125564.45" - process $proc$libresoc.v:125564$5580 - assign { } { } - assign $1\dmi0_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_din $1\dmi0_din[63:0] - end - attribute \src "libresoc.v:125574.13-125574.29" - process $proc$libresoc.v:125574$5581 + attribute \src "libresoc.v:127044.13-127044.29" + process $proc$libresoc.v:127044$5815 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:125576.13-125576.35" - process $proc$libresoc.v:125576$5582 + attribute \src "libresoc.v:127046.13-127046.35" + process $proc$libresoc.v:127046$5816 assign { } { } - assign $0\fsm_state$275[2:0]$5583 3'000 + assign $0\fsm_state$503[2:0]$5817 3'000 sync always sync init - update \fsm_state$275 $0\fsm_state$275[2:0]$5583 + update \fsm_state$503 $0\fsm_state$503[2:0]$5817 end - attribute \src "libresoc.v:125774.14-125774.39" - process $proc$libresoc.v:125774$5584 + attribute \src "libresoc.v:127244.15-127244.67" + process $proc$libresoc.v:127244$5818 assign { } { } - assign $1\io_bd[49:0] 50'00000000000000000000000000000000000000000000000000 + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_bd $1\io_bd[49:0] + update \io_bd $1\io_bd[153:0] end - attribute \src "libresoc.v:125786.14-125786.39" - process $proc$libresoc.v:125786$5585 + attribute \src "libresoc.v:127256.15-127256.67" + process $proc$libresoc.v:127256$5819 assign { } { } - assign $1\io_sr[49:0] 50'00000000000000000000000000000000000000000000000000 + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[49:0] + update \io_sr $1\io_sr[153:0] end - attribute \src "libresoc.v:125795.14-125795.41" - process $proc$libresoc.v:125795$5586 + attribute \src "libresoc.v:127265.14-127265.41" + process $proc$libresoc.v:127265$5820 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:125804.14-125804.51" - process $proc$libresoc.v:125804$5587 + attribute \src "libresoc.v:127274.14-127274.51" + process $proc$libresoc.v:127274$5821 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:125818.7-125818.32" - process $proc$libresoc.v:125818$5588 + attribute \src "libresoc.v:127288.7-127288.32" + process $proc$libresoc.v:127288$5822 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:125826.14-125826.47" - process $proc$libresoc.v:125826$5589 + attribute \src "libresoc.v:127296.14-127296.47" + process $proc$libresoc.v:127296$5823 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:125834.7-125834.40" - process $proc$libresoc.v:125834$5590 + attribute \src "libresoc.v:127304.7-127304.40" + process $proc$libresoc.v:127304$5824 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:125838.7-125838.45" - process $proc$libresoc.v:125838$5591 + attribute \src "libresoc.v:127308.7-127308.45" + process $proc$libresoc.v:127308$5825 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:125842.14-125842.54" - process $proc$libresoc.v:125842$5592 + attribute \src "libresoc.v:127312.14-127312.54" + process $proc$libresoc.v:127312$5826 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:125848.13-125848.38" - process $proc$libresoc.v:125848$5593 + attribute \src "libresoc.v:127318.13-127318.38" + process $proc$libresoc.v:127318$5827 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:125856.14-125856.55" - process $proc$libresoc.v:125856$5594 + attribute \src "libresoc.v:127326.14-127326.55" + process $proc$libresoc.v:127326$5828 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:125864.7-125864.40" - process $proc$libresoc.v:125864$5595 + attribute \src "libresoc.v:127334.7-127334.40" + process $proc$libresoc.v:127334$5829 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:125868.7-125868.45" - process $proc$libresoc.v:125868$5596 + attribute \src "libresoc.v:127338.7-127338.45" + process $proc$libresoc.v:127338$5830 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:125886.7-125886.21" - process $proc$libresoc.v:125886$5597 + attribute \src "libresoc.v:127768.7-127768.21" + process $proc$libresoc.v:127768$5831 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:125894.13-125894.27" - process $proc$libresoc.v:125894$5598 + attribute \src "libresoc.v:127776.13-127776.27" + process $proc$libresoc.v:127776$5832 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:125902.7-125902.29" - process $proc$libresoc.v:125902$5599 + attribute \src "libresoc.v:127784.7-127784.29" + process $proc$libresoc.v:127784$5833 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:125906.7-125906.34" - process $proc$libresoc.v:125906$5600 + attribute \src "libresoc.v:127788.7-127788.34" + process $proc$libresoc.v:127788$5834 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:126059.3-126060.45" - process $proc$libresoc.v:126059$5407 + attribute \src "libresoc.v:127798.7-127798.21" + process $proc$libresoc.v:127798$5835 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:127806.13-127806.27" + process $proc$libresoc.v:127806$5836 + assign { } { } + assign $1\sr5_reg[1:0] 2'00 + sync always + sync init + update \sr5_reg $1\sr5_reg[1:0] + end + attribute \src "libresoc.v:127814.7-127814.29" + process $proc$libresoc.v:127814$5837 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:127818.7-127818.34" + process $proc$libresoc.v:127818$5838 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:127823.7-127823.26" + process $proc$libresoc.v:127823$5839 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:127828.7-127828.26" + process $proc$libresoc.v:127828$5840 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] + end + attribute \src "libresoc.v:128087.3-128088.41" + process $proc$libresoc.v:128087$5612 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:128089.3-128090.41" + process $proc$libresoc.v:128089$5613 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:128091.3-128092.45" + process $proc$libresoc.v:128091$5614 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:126061.3-126062.33" - process $proc$libresoc.v:126061$5408 + attribute \src "libresoc.v:128093.3-128094.35" + process $proc$libresoc.v:128093$5615 assign { } { } - assign $0\dmi0_din[63:0] \dmi0_din$next + assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk - update \dmi0_din $0\dmi0_din[63:0] + update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:126063.3-126064.45" - process $proc$libresoc.v:126063$5409 + attribute \src "libresoc.v:128095.3-128096.45" + process $proc$libresoc.v:128095$5616 assign { } { } - assign $0\fsm_state$275[2:0]$5410 \fsm_state$275$next + assign $0\fsm_state$503[2:0]$5617 \fsm_state$503$next sync posedge \clk - update \fsm_state$275 $0\fsm_state$275[2:0]$5410 + update \fsm_state$503 $0\fsm_state$503[2:0]$5617 end - attribute \src "libresoc.v:126065.3-126066.39" - process $proc$libresoc.v:126065$5411 + attribute \src "libresoc.v:128097.3-128098.41" + process $proc$libresoc.v:128097$5618 assign { } { } - assign $0\dmi0_addr_i[3:0] \dmi0_addr_i$next + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk - update \dmi0_addr_i $0\dmi0_addr_i[3:0] + update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:126067.3-126068.51" - process $proc$libresoc.v:126067$5412 + attribute \src "libresoc.v:128099.3-128100.51" + process $proc$libresoc.v:128099$5619 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:126069.3-126070.45" - process $proc$libresoc.v:126069$5413 + attribute \src "libresoc.v:128101.3-128102.45" + process $proc$libresoc.v:128101$5620 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:126071.3-126072.35" - process $proc$libresoc.v:126071$5414 + attribute \src "libresoc.v:128103.3-128104.35" + process $proc$libresoc.v:128103$5621 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:126073.3-126074.41" - process $proc$libresoc.v:126073$5415 + attribute \src "libresoc.v:128105.3-128106.41" + process $proc$libresoc.v:128105$5622 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:126075.3-126076.47" - process $proc$libresoc.v:126075$5416 + attribute \src "libresoc.v:128107.3-128108.31" + process $proc$libresoc.v:128107$5623 + assign { } { } + assign $0\sr5_reg[1:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[1:0] + end + attribute \src "libresoc.v:128109.3-128110.31" + process $proc$libresoc.v:128109$5624 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] + end + attribute \src "libresoc.v:128111.3-128112.57" + process $proc$libresoc.v:128111$5625 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:128113.3-128114.47" + process $proc$libresoc.v:128113$5626 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] + end + attribute \src "libresoc.v:128115.3-128116.47" + process $proc$libresoc.v:128115$5627 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:126077.3-126078.47" - process $proc$libresoc.v:126077$5417 + attribute \src "libresoc.v:128117.3-128118.47" + process $proc$libresoc.v:128117$5628 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:126079.3-126080.73" - process $proc$libresoc.v:126079$5418 + attribute \src "libresoc.v:128119.3-128120.73" + process $proc$libresoc.v:128119$5629 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:126081.3-126082.63" - process $proc$libresoc.v:126081$5419 + attribute \src "libresoc.v:128121.3-128122.63" + process $proc$libresoc.v:128121$5630 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:126083.3-126084.47" - process $proc$libresoc.v:126083$5420 + attribute \src "libresoc.v:128123.3-128124.47" + process $proc$libresoc.v:128123$5631 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:126085.3-126086.47" - process $proc$libresoc.v:126085$5421 + attribute \src "libresoc.v:128125.3-128126.47" + process $proc$libresoc.v:128125$5632 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:126087.3-126088.73" - process $proc$libresoc.v:126087$5422 + attribute \src "libresoc.v:128127.3-128128.73" + process $proc$libresoc.v:128127$5633 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:126089.3-126090.63" - process $proc$libresoc.v:126089$5423 + attribute \src "libresoc.v:128129.3-128130.63" + process $proc$libresoc.v:128129$5634 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:126091.3-126092.53" - process $proc$libresoc.v:126091$5424 + attribute \src "libresoc.v:128131.3-128132.53" + process $proc$libresoc.v:128131$5635 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:126093.3-126094.53" - process $proc$libresoc.v:126093$5425 + attribute \src "libresoc.v:128133.3-128134.53" + process $proc$libresoc.v:128133$5636 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:126095.3-126096.79" - process $proc$libresoc.v:126095$5426 + attribute \src "libresoc.v:128135.3-128136.79" + process $proc$libresoc.v:128135$5637 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:126097.3-126098.69" - process $proc$libresoc.v:126097$5427 + attribute \src "libresoc.v:128137.3-128138.69" + process $proc$libresoc.v:128137$5638 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:126099.3-126100.53" - process $proc$libresoc.v:126099$5428 + attribute \src "libresoc.v:128139.3-128140.53" + process $proc$libresoc.v:128139$5639 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:126101.3-126102.53" - process $proc$libresoc.v:126101$5429 + attribute \src "libresoc.v:128141.3-128142.53" + process $proc$libresoc.v:128141$5640 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:126103.3-126104.79" - process $proc$libresoc.v:126103$5430 + attribute \src "libresoc.v:128143.3-128144.79" + process $proc$libresoc.v:128143$5641 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:126105.3-126106.69" - process $proc$libresoc.v:126105$5431 + attribute \src "libresoc.v:128145.3-128146.69" + process $proc$libresoc.v:128145$5642 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:126107.3-126108.31" - process $proc$libresoc.v:126107$5432 + attribute \src "libresoc.v:128147.3-128148.31" + process $proc$libresoc.v:128147$5643 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:126109.3-126110.31" - process $proc$libresoc.v:126109$5433 + attribute \src "libresoc.v:128149.3-128150.31" + process $proc$libresoc.v:128149$5644 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:126111.3-126112.57" - process $proc$libresoc.v:126111$5434 + attribute \src "libresoc.v:128151.3-128152.57" + process $proc$libresoc.v:128151$5645 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:126113.3-126114.47" - process $proc$libresoc.v:126113$5435 + attribute \src "libresoc.v:128153.3-128154.47" + process $proc$libresoc.v:128153$5646 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:126115.3-126116.27" - process $proc$libresoc.v:126115$5436 + attribute \src "libresoc.v:128155.3-128156.27" + process $proc$libresoc.v:128155$5647 assign { } { } - assign $0\io_bd[49:0] \io_bd$next + assign $0\io_bd[153:0] \io_bd$next sync negedge \negjtag_clk - update \io_bd $0\io_bd[49:0] + update \io_bd $0\io_bd[153:0] end - attribute \src "libresoc.v:126117.3-126118.27" - process $proc$libresoc.v:126117$5437 + attribute \src "libresoc.v:128157.3-128158.27" + process $proc$libresoc.v:128157$5648 assign { } { } - assign $0\io_sr[49:0] \io_sr$next + assign $0\io_sr[153:0] \io_sr$next sync posedge \posjtag_clk - update \io_sr $0\io_sr[49:0] - end - attribute \src "libresoc.v:126154.3-126162.6" - process $proc$libresoc.v:126154$5438 - assign { } { } - assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5439 $1\dmi0_datasr_update_core_prev$next[0:0]$5440 - attribute \src "libresoc.v:126155.5-126155.29" - switch \initial - attribute \src "libresoc.v:126155.9-126155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5440 1'0 - case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5440 \dmi0_datasr_update_core - end - sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5439 + update \io_sr $0\io_sr[153:0] end - attribute \src "libresoc.v:126163.3-126179.6" - process $proc$libresoc.v:126163$5441 + attribute \src "libresoc.v:128194.3-128209.6" + process $proc$libresoc.v:128194$5649 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5442 $2\dmi0_datasr__oe$next[1:0]$5444 - attribute \src "libresoc.v:126164.5-126164.29" + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:128195.5-128195.29" switch \initial - attribute \src "libresoc.v:126164.9-126164.17" + attribute \src "libresoc.v:128195.9-128195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$253 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'--1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5443 \dmi0_datasr_isir + assign $1\TAP_tdo[0:0] \_irblock_tdo attribute \src "libresoc.v:0.0-0.0" - case + case 3'-1- assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5443 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'1-- assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5444 2'00 + assign $1\TAP_tdo[0:0] \io_sr [153] case - assign $2\dmi0_datasr__oe$next[1:0]$5444 $1\dmi0_datasr__oe$next[1:0]$5443 + assign $1\TAP_tdo[0:0] 1'0 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5442 + update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:126180.3-126200.6" - process $proc$libresoc.v:126180$5445 - assign { } { } - assign { } { } + attribute \src "libresoc.v:128210.3-128218.6" + process $proc$libresoc.v:128210$5650 assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5446 $3\dmi0_datasr_reg$next[63:0]$5449 - attribute \src "libresoc.v:126181.5-126181.29" + assign $0\sr0_update_core$next[0:0]$5651 $1\sr0_update_core$next[0:0]$5652 + attribute \src "libresoc.v:128211.5-128211.29" switch \initial - attribute \src "libresoc.v:126181.9-126181.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \dmi0_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$5447 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } - case - assign $1\dmi0_datasr_reg$next[63:0]$5447 \dmi0_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \dmi0_datasr_capture - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:128211.9-128211.17" case 1'1 - assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$5448 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$5448 $1\dmi0_datasr_reg$next[63:0]$5447 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$5449 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sr0_update_core$next[0:0]$5652 1'0 case - assign $3\dmi0_datasr_reg$next[63:0]$5449 $2\dmi0_datasr_reg$next[63:0]$5448 + assign $1\sr0_update_core$next[0:0]$5652 \sr0_update end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5446 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5651 end - attribute \src "libresoc.v:126201.3-126224.6" - process $proc$libresoc.v:126201$5450 + attribute \src "libresoc.v:128219.3-128227.6" + process $proc$libresoc.v:128219$5653 assign { } { } - assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:126202.5-126202.29" + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5654 $1\sr0_update_core_prev$next[0:0]$5655 + attribute \src "libresoc.v:128220.5-128220.29" switch \initial - attribute \src "libresoc.v:126202.9-126202.17" + attribute \src "libresoc.v:128220.9-128220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:571" - switch { \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } - attribute \src "libresoc.v:0.0-0.0" - case 5'----1 - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'---1- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'--1-- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 5'-1--- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 5'1---- + case 1'1 assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" + assign $1\sr0_update_core_prev$next[0:0]$5655 1'0 case - assign { } { } - assign $1\TAP_bus__tdo[0:0] \TAP_tdo + assign $1\sr0_update_core_prev$next[0:0]$5655 \sr0_update_core end sync always - update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5654 end - attribute \src "libresoc.v:126225.3-126257.6" - process $proc$libresoc.v:126225$5451 - assign { } { } + attribute \src "libresoc.v:128228.3-128244.6" + process $proc$libresoc.v:128228$5656 assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$5452 $4\jtag_wb__adr$next[28:0]$5456 - attribute \src "libresoc.v:126226.5-126226.29" + assign $0\sr0__oe$next[0:0]$5657 $2\sr0__oe$next[0:0]$5659 + attribute \src "libresoc.v:128229.5-128229.29" switch \initial - attribute \src "libresoc.v:126226.9-126226.17" + attribute \src "libresoc.v:128229.9-128229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 1'1 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5453 $2\jtag_wb__adr$next[28:0]$5454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5454 \jtag_wb_addrsr__o - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5454 \$267 [28:0] - case - assign $2\jtag_wb__adr$next[28:0]$5454 \jtag_wb__adr - end + assign $1\sr0__oe$next[0:0]$5658 \sr0_isir attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5453 $3\jtag_wb__adr$next[28:0]$5455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__adr$next[28:0]$5455 \$270 [28:0] - case - assign $3\jtag_wb__adr$next[28:0]$5455 \jtag_wb__adr - end case - assign $1\jtag_wb__adr$next[28:0]$5453 \jtag_wb__adr + assign { } { } + assign $1\sr0__oe$next[0:0]$5658 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$5456 29'00000000000000000000000000000 + assign $2\sr0__oe$next[0:0]$5659 1'0 case - assign $4\jtag_wb__adr$next[28:0]$5456 $1\jtag_wb__adr$next[28:0]$5453 + assign $2\sr0__oe$next[0:0]$5659 $1\sr0__oe$next[0:0]$5658 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5452 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5657 end - attribute \src "libresoc.v:126258.3-126310.6" - process $proc$libresoc.v:126258$5457 + attribute \src "libresoc.v:128245.3-128265.6" + process $proc$libresoc.v:128245$5660 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$5458 $5\fsm_state$next[2:0]$5463 - attribute \src "libresoc.v:126259.5-126259.29" + assign $0\sr0_reg$next[2:0]$5661 $3\sr0_reg$next[2:0]$5664 + attribute \src "libresoc.v:128246.5-128246.29" switch \initial - attribute \src "libresoc.v:126259.9-126259.17" + attribute \src "libresoc.v:128246.9-128246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$next[2:0]$5459 $2\fsm_state$next[2:0]$5460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$next[2:0]$5460 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$next[2:0]$5460 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$next[2:0]$5460 3'010 - case - assign $2\fsm_state$next[2:0]$5460 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$next[2:0]$5459 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$next[2:0]$5459 $3\fsm_state$next[2:0]$5461 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[2:0]$5461 3'000 - case - assign $3\fsm_state$next[2:0]$5461 \fsm_state - end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 1'1 assign { } { } - assign $1\fsm_state$next[2:0]$5459 3'100 + assign $1\sr0_reg$next[2:0]$5662 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5662 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\fsm_state$next[2:0]$5459 $4\fsm_state$next[2:0]$5462 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:224" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[2:0]$5462 3'001 - case - assign $4\fsm_state$next[2:0]$5462 \fsm_state - end + assign $2\sr0_reg$next[2:0]$5663 \sr0__i case - assign $1\fsm_state$next[2:0]$5459 \fsm_state + assign $2\sr0_reg$next[2:0]$5663 $1\sr0_reg$next[2:0]$5662 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$5463 3'000 + assign $3\sr0_reg$next[2:0]$5664 3'000 case - assign $5\fsm_state$next[2:0]$5463 $1\fsm_state$next[2:0]$5459 + assign $3\sr0_reg$next[2:0]$5664 $2\sr0_reg$next[2:0]$5663 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$5458 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5661 end - attribute \src "libresoc.v:126311.3-126337.6" - process $proc$libresoc.v:126311$5464 + attribute \src "libresoc.v:128266.3-128274.6" + process $proc$libresoc.v:128266$5665 assign { } { } assign { } { } - assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$5465 $3\jtag_wb__dat_w$next[63:0]$5468 - attribute \src "libresoc.v:126312.5-126312.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5666 $1\jtag_wb_addrsr_update_core$next[0:0]$5667 + attribute \src "libresoc.v:128267.5-128267.29" switch \initial - attribute \src "libresoc.v:126312.9-126312.17" + attribute \src "libresoc.v:128267.9-128267.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$5466 $2\jtag_wb__dat_w$next[63:0]$5467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:196" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb_datasr__o - case - assign $2\jtag_wb__dat_w$next[63:0]$5467 \jtag_wb__dat_w - end - case - assign $1\jtag_wb__dat_w$next[63:0]$5466 \jtag_wb__dat_w - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$5468 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5667 1'0 case - assign $3\jtag_wb__dat_w$next[63:0]$5468 $1\jtag_wb__dat_w$next[63:0]$5466 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5667 \jtag_wb_addrsr_update end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5465 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5666 end - attribute \src "libresoc.v:126338.3-126358.6" - process $proc$libresoc.v:126338$5469 - assign { } { } + attribute \src "libresoc.v:128275.3-128283.6" + process $proc$libresoc.v:128275$5668 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$5470 $3\jtag_wb_datasr__i$next[63:0]$5473 - attribute \src "libresoc.v:126339.5-126339.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 + attribute \src "libresoc.v:128276.5-128276.29" switch \initial - attribute \src "libresoc.v:126339.9-126339.17" + attribute \src "libresoc.v:128276.9-128276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:194" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$5471 $2\jtag_wb_datasr__i$next[63:0]$5472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:213" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$5472 \jtag_wb__dat_r - case - assign $2\jtag_wb_datasr__i$next[63:0]$5472 \jtag_wb_datasr__i - end - case - assign $1\jtag_wb_datasr__i$next[63:0]$5471 \jtag_wb_datasr__i - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$5473 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 1'0 case - assign $3\jtag_wb_datasr__i$next[63:0]$5473 $1\jtag_wb_datasr__i$next[63:0]$5471 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5470 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 end - attribute \src "libresoc.v:126359.3-126391.6" - process $proc$libresoc.v:126359$5474 + attribute \src "libresoc.v:128284.3-128300.6" + process $proc$libresoc.v:128284$5671 assign { } { } assign { } { } - assign { } { } - assign $0\dmi0_addr_i$next[3:0]$5475 $4\dmi0_addr_i$next[3:0]$5479 - attribute \src "libresoc.v:126360.5-126360.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5672 $2\jtag_wb_addrsr__oe$next[0:0]$5674 + attribute \src "libresoc.v:128285.5-128285.29" switch \initial - attribute \src "libresoc.v:126360.9-126360.17" + attribute \src "libresoc.v:128285.9-128285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 1'1 assign { } { } - assign $1\dmi0_addr_i$next[3:0]$5476 $2\dmi0_addr_i$next[3:0]$5477 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\dmi0_addr_i$next[3:0]$5477 \dmi0_addrsr__o [3:0] - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\dmi0_addr_i$next[3:0]$5477 \$284 [3:0] - case - assign $2\dmi0_addr_i$next[3:0]$5477 \dmi0_addr_i - end + assign $1\jtag_wb_addrsr__oe$next[0:0]$5673 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\dmi0_addr_i$next[3:0]$5476 $3\dmi0_addr_i$next[3:0]$5478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addr_i$next[3:0]$5478 \$287 [3:0] - case - assign $3\dmi0_addr_i$next[3:0]$5478 \dmi0_addr_i - end case - assign $1\dmi0_addr_i$next[3:0]$5476 \dmi0_addr_i + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5673 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0_addr_i$next[3:0]$5479 4'0000 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5674 1'0 case - assign $4\dmi0_addr_i$next[3:0]$5479 $1\dmi0_addr_i$next[3:0]$5476 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5674 $1\jtag_wb_addrsr__oe$next[0:0]$5673 end sync always - update \dmi0_addr_i$next $0\dmi0_addr_i$next[3:0]$5475 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5672 end - attribute \src "libresoc.v:126392.3-126444.6" - process $proc$libresoc.v:126392$5480 + attribute \src "libresoc.v:128301.3-128321.6" + process $proc$libresoc.v:128301$5675 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$275$next[2:0]$5481 $5\fsm_state$275$next[2:0]$5486 - attribute \src "libresoc.v:126393.5-126393.29" + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$5676 $3\jtag_wb_addrsr_reg$next[28:0]$5679 + attribute \src "libresoc.v:128302.5-128302.29" switch \initial - attribute \src "libresoc.v:126393.9-126393.17" + attribute \src "libresoc.v:128302.9-128302.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$275$next[2:0]$5482 $2\fsm_state$275$next[2:0]$5483 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$275$next[2:0]$5483 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$275$next[2:0]$5483 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$275$next[2:0]$5483 3'010 - case - assign $2\fsm_state$275$next[2:0]$5483 \fsm_state$275 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$275$next[2:0]$5482 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$275$next[2:0]$5482 $3\fsm_state$275$next[2:0]$5484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$275$next[2:0]$5484 3'000 - case - assign $3\fsm_state$275$next[2:0]$5484 \fsm_state$275 - end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 1'1 assign { } { } - assign $1\fsm_state$275$next[2:0]$5482 3'100 + assign $1\jtag_wb_addrsr_reg$next[28:0]$5677 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$5677 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\fsm_state$275$next[2:0]$5482 $4\fsm_state$275$next[2:0]$5485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:176" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$275$next[2:0]$5485 3'001 - case - assign $4\fsm_state$275$next[2:0]$5485 \fsm_state$275 - end + assign $2\jtag_wb_addrsr_reg$next[28:0]$5678 \jtag_wb_addrsr__i case - assign $1\fsm_state$275$next[2:0]$5482 \fsm_state$275 + assign $2\jtag_wb_addrsr_reg$next[28:0]$5678 $1\jtag_wb_addrsr_reg$next[28:0]$5677 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$275$next[2:0]$5486 3'000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5679 29'00000000000000000000000000000 case - assign $5\fsm_state$275$next[2:0]$5486 $1\fsm_state$275$next[2:0]$5482 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5679 $2\jtag_wb_addrsr_reg$next[28:0]$5678 end sync always - update \fsm_state$275$next $0\fsm_state$275$next[2:0]$5481 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5676 end - attribute \src "libresoc.v:126445.3-126471.6" - process $proc$libresoc.v:126445$5487 + attribute \src "libresoc.v:128322.3-128330.6" + process $proc$libresoc.v:128322$5680 assign { } { } assign { } { } - assign { } { } - assign $0\dmi0_din$next[63:0]$5488 $3\dmi0_din$next[63:0]$5491 - attribute \src "libresoc.v:126446.5-126446.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$5681 $1\jtag_wb_datasr_update_core$next[0:0]$5682 + attribute \src "libresoc.v:128323.5-128323.29" switch \initial - attribute \src "libresoc.v:126446.9-126446.17" + attribute \src "libresoc.v:128323.9-128323.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0_din$next[63:0]$5489 $2\dmi0_din$next[63:0]$5490 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:148" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\dmi0_din$next[63:0]$5490 \dmi0_din - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\dmi0_din$next[63:0]$5490 \dmi0_din - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\dmi0_din$next[63:0]$5490 \dmi0_datasr__o - case - assign $2\dmi0_din$next[63:0]$5490 \dmi0_din - end - case - assign $1\dmi0_din$next[63:0]$5489 \dmi0_din - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_din$next[63:0]$5491 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5682 1'0 case - assign $3\dmi0_din$next[63:0]$5491 $1\dmi0_din$next[63:0]$5489 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5682 \jtag_wb_datasr_update end sync always - update \dmi0_din$next $0\dmi0_din$next[63:0]$5488 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5681 end - attribute \src "libresoc.v:126472.3-126492.6" - process $proc$libresoc.v:126472$5492 + attribute \src "libresoc.v:128331.3-128339.6" + process $proc$libresoc.v:128331$5683 assign { } { } assign { } { } - assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$5493 $3\dmi0_datasr__i$next[63:0]$5496 - attribute \src "libresoc.v:126473.5-126473.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 + attribute \src "libresoc.v:128332.5-128332.29" switch \initial - attribute \src "libresoc.v:126473.9-126473.17" + attribute \src "libresoc.v:128332.9-128332.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:144" - switch \fsm_state$275 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$5494 $2\dmi0_datasr__i$next[63:0]$5495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:165" - switch \dmi0_ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$5495 \dmi0_dout - case - assign $2\dmi0_datasr__i$next[63:0]$5495 \dmi0_datasr__i - end - case - assign $1\dmi0_datasr__i$next[63:0]$5494 \dmi0_datasr__i - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$5496 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 1'0 case - assign $3\dmi0_datasr__i$next[63:0]$5496 $1\dmi0_datasr__i$next[63:0]$5494 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 \jtag_wb_datasr_update_core end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5493 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 end - attribute \src "libresoc.v:126493.3-126561.6" - process $proc$libresoc.v:126493$5497 - assign { } { } + attribute \src "libresoc.v:128340.3-128356.6" + process $proc$libresoc.v:128340$5686 assign { } { } assign { } { } - assign $0\io_sr$next[49:0]$5498 $2\io_sr$next[49:0]$5500 - attribute \src "libresoc.v:126494.5-126494.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$5687 $2\jtag_wb_datasr__oe$next[1:0]$5689 + attribute \src "libresoc.v:128341.5-128341.29" switch \initial - attribute \src "libresoc.v:126494.9-126494.17" + attribute \src "libresoc.v:128341.9-128341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" - switch { \io_update \io_shift \io_capture } + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 attribute \src "libresoc.v:0.0-0.0" - case 3'--1 + case 1'1 assign { } { } - assign $1\io_sr$next[49:0]$5499 [0] \uart_tx__core__o - assign $1\io_sr$next[49:0]$5499 [1] \uart_rx__pad__i - assign $1\io_sr$next[49:0]$5499 [2] \gpio_gpio0__pad__i - assign $1\io_sr$next[49:0]$5499 [3] \gpio_gpio0__core__o - assign $1\io_sr$next[49:0]$5499 [4] \gpio_gpio0__core__oe - assign $1\io_sr$next[49:0]$5499 [5] \gpio_gpio1__pad__i - assign $1\io_sr$next[49:0]$5499 [6] \gpio_gpio1__core__o - assign $1\io_sr$next[49:0]$5499 [7] \gpio_gpio1__core__oe - assign $1\io_sr$next[49:0]$5499 [8] \gpio_gpio2__pad__i - assign $1\io_sr$next[49:0]$5499 [9] \gpio_gpio2__core__o - assign $1\io_sr$next[49:0]$5499 [10] \gpio_gpio2__core__oe - assign $1\io_sr$next[49:0]$5499 [11] \gpio_gpio3__pad__i - assign $1\io_sr$next[49:0]$5499 [12] \gpio_gpio3__core__o - assign $1\io_sr$next[49:0]$5499 [13] \gpio_gpio3__core__oe - assign $1\io_sr$next[49:0]$5499 [14] \gpio_gpio4__pad__i - assign $1\io_sr$next[49:0]$5499 [15] \gpio_gpio4__core__o - assign $1\io_sr$next[49:0]$5499 [16] \gpio_gpio4__core__oe - assign $1\io_sr$next[49:0]$5499 [17] \gpio_gpio5__pad__i - assign $1\io_sr$next[49:0]$5499 [18] \gpio_gpio5__core__o - assign $1\io_sr$next[49:0]$5499 [19] \gpio_gpio5__core__oe - assign $1\io_sr$next[49:0]$5499 [20] \gpio_gpio6__pad__i - assign $1\io_sr$next[49:0]$5499 [21] \gpio_gpio6__core__o - assign $1\io_sr$next[49:0]$5499 [22] \gpio_gpio6__core__oe - assign $1\io_sr$next[49:0]$5499 [23] \gpio_gpio7__pad__i - assign $1\io_sr$next[49:0]$5499 [24] \gpio_gpio7__core__o - assign $1\io_sr$next[49:0]$5499 [25] \gpio_gpio7__core__oe - assign $1\io_sr$next[49:0]$5499 [26] \gpio_gpio8__pad__i - assign $1\io_sr$next[49:0]$5499 [27] \gpio_gpio8__core__o - assign $1\io_sr$next[49:0]$5499 [28] \gpio_gpio8__core__oe - assign $1\io_sr$next[49:0]$5499 [29] \gpio_gpio9__pad__i - assign $1\io_sr$next[49:0]$5499 [30] \gpio_gpio9__core__o - assign $1\io_sr$next[49:0]$5499 [31] \gpio_gpio9__core__oe - assign $1\io_sr$next[49:0]$5499 [32] \gpio_gpio10__pad__i - assign $1\io_sr$next[49:0]$5499 [33] \gpio_gpio10__core__o - assign $1\io_sr$next[49:0]$5499 [34] \gpio_gpio10__core__oe - assign $1\io_sr$next[49:0]$5499 [35] \gpio_gpio11__pad__i - assign $1\io_sr$next[49:0]$5499 [36] \gpio_gpio11__core__o - assign $1\io_sr$next[49:0]$5499 [37] \gpio_gpio11__core__oe - assign $1\io_sr$next[49:0]$5499 [38] \gpio_gpio12__pad__i - assign $1\io_sr$next[49:0]$5499 [39] \gpio_gpio12__core__o - assign $1\io_sr$next[49:0]$5499 [40] \gpio_gpio12__core__oe - assign $1\io_sr$next[49:0]$5499 [41] \gpio_gpio13__pad__i - assign $1\io_sr$next[49:0]$5499 [42] \gpio_gpio13__core__o - assign $1\io_sr$next[49:0]$5499 [43] \gpio_gpio13__core__oe - assign $1\io_sr$next[49:0]$5499 [44] \gpio_gpio14__pad__i - assign $1\io_sr$next[49:0]$5499 [45] \gpio_gpio14__core__o - assign $1\io_sr$next[49:0]$5499 [46] \gpio_gpio14__core__oe - assign $1\io_sr$next[49:0]$5499 [47] \gpio_gpio15__pad__i - assign $1\io_sr$next[49:0]$5499 [48] \gpio_gpio15__core__o - assign $1\io_sr$next[49:0]$5499 [49] \gpio_gpio15__core__oe + assign $1\jtag_wb_datasr__oe$next[1:0]$5688 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\io_sr$next[49:0]$5499 { \io_sr [48:0] \TAP_bus__tdi } case - assign $1\io_sr$next[49:0]$5499 \io_sr + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5688 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[49:0]$5500 50'00000000000000000000000000000000000000000000000000 + assign $2\jtag_wb_datasr__oe$next[1:0]$5689 2'00 case - assign $2\io_sr$next[49:0]$5500 $1\io_sr$next[49:0]$5499 + assign $2\jtag_wb_datasr__oe$next[1:0]$5689 $1\jtag_wb_datasr__oe$next[1:0]$5688 end sync always - update \io_sr$next $0\io_sr$next[49:0]$5498 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5687 end - attribute \src "libresoc.v:126562.3-126577.6" - process $proc$libresoc.v:126562$5501 + attribute \src "libresoc.v:128357.3-128377.6" + process $proc$libresoc.v:128357$5690 assign { } { } assign { } { } - assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:126563.5-126563.29" + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$5691 $3\jtag_wb_datasr_reg$next[63:0]$5694 + attribute \src "libresoc.v:128358.5-128358.29" switch \initial - attribute \src "libresoc.v:126563.9-126563.17" + attribute \src "libresoc.v:128358.9-128358.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" - switch { \$159 \$147 \_fsm_isir } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\TAP_tdo[0:0] \_irblock_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [49] - case - assign $1\TAP_tdo[0:0] 1'0 - end - sync always - update \TAP_tdo $0\TAP_tdo[0:0] - end - attribute \src "libresoc.v:126578.3-126598.6" - process $proc$libresoc.v:126578$5502 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_bd$next[49:0]$5503 $2\io_bd$next[49:0]$5505 - attribute \src "libresoc.v:126579.5-126579.29" - switch \initial - attribute \src "libresoc.v:126579.9-126579.17" case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$5692 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case + assign $1\jtag_wb_datasr_reg$next[63:0]$5692 \jtag_wb_datasr_reg end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:439" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\io_bd$next[49:0]$5504 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\io_bd$next[49:0]$5504 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" - case 3'1-- + case 1'1 assign { } { } - assign $1\io_bd$next[49:0]$5504 \io_sr + assign $2\jtag_wb_datasr_reg$next[63:0]$5693 \jtag_wb_datasr__i case - assign $1\io_bd$next[49:0]$5504 \io_bd + assign $2\jtag_wb_datasr_reg$next[63:0]$5693 $1\jtag_wb_datasr_reg$next[63:0]$5692 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \negjtag_rst + switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[49:0]$5505 50'00000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$5694 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_bd$next[49:0]$5505 $1\io_bd$next[49:0]$5504 + assign $3\jtag_wb_datasr_reg$next[63:0]$5694 $2\jtag_wb_datasr_reg$next[63:0]$5693 end sync always - update \io_bd$next $0\io_bd$next[49:0]$5503 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5691 end - attribute \src "libresoc.v:126599.3-126607.6" - process $proc$libresoc.v:126599$5506 + attribute \src "libresoc.v:128378.3-128386.6" + process $proc$libresoc.v:128378$5695 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5507 $1\sr0_update_core$next[0:0]$5508 - attribute \src "libresoc.v:126600.5-126600.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$5696 $1\dmi0_addrsr_update_core$next[0:0]$5697 + attribute \src "libresoc.v:128379.5-128379.29" switch \initial - attribute \src "libresoc.v:126600.9-126600.17" + attribute \src "libresoc.v:128379.9-128379.17" case 1'1 case end @@ -201021,21 +205409,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5508 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$5697 1'0 case - assign $1\sr0_update_core$next[0:0]$5508 \sr0_update + assign $1\dmi0_addrsr_update_core$next[0:0]$5697 \dmi0_addrsr_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5507 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5696 end - attribute \src "libresoc.v:126608.3-126616.6" - process $proc$libresoc.v:126608$5509 + attribute \src "libresoc.v:128387.3-128395.6" + process $proc$libresoc.v:128387$5698 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5510 $1\sr0_update_core_prev$next[0:0]$5511 - attribute \src "libresoc.v:126609.5-126609.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 + attribute \src "libresoc.v:128388.5-128388.29" switch \initial - attribute \src "libresoc.v:126609.9-126609.17" + attribute \src "libresoc.v:128388.9-128388.17" case 1'1 case end @@ -201044,98 +205432,98 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5511 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5511 \sr0_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 \dmi0_addrsr_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5510 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 end - attribute \src "libresoc.v:126617.3-126633.6" - process $proc$libresoc.v:126617$5512 + attribute \src "libresoc.v:128396.3-128412.6" + process $proc$libresoc.v:128396$5701 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5513 $2\sr0__oe$next[0:0]$5515 - attribute \src "libresoc.v:126618.5-126618.29" + assign $0\dmi0_addrsr__oe$next[0:0]$5702 $2\dmi0_addrsr__oe$next[0:0]$5704 + attribute \src "libresoc.v:128397.5-128397.29" switch \initial - attribute \src "libresoc.v:126618.9-126618.17" + attribute \src "libresoc.v:128397.9-128397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$177 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5514 \sr0_isir + assign $1\dmi0_addrsr__oe$next[0:0]$5703 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5514 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$5703 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5515 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$5704 1'0 case - assign $2\sr0__oe$next[0:0]$5515 $1\sr0__oe$next[0:0]$5514 + assign $2\dmi0_addrsr__oe$next[0:0]$5704 $1\dmi0_addrsr__oe$next[0:0]$5703 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5513 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5702 end - attribute \src "libresoc.v:126634.3-126654.6" - process $proc$libresoc.v:126634$5516 + attribute \src "libresoc.v:128413.3-128433.6" + process $proc$libresoc.v:128413$5705 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5517 $3\sr0_reg$next[2:0]$5520 - attribute \src "libresoc.v:126635.5-126635.29" + assign $0\dmi0_addrsr_reg$next[7:0]$5706 $3\dmi0_addrsr_reg$next[7:0]$5709 + attribute \src "libresoc.v:128414.5-128414.29" switch \initial - attribute \src "libresoc.v:126635.9-126635.17" + attribute \src "libresoc.v:128414.9-128414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5518 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$5707 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\sr0_reg$next[2:0]$5518 \sr0_reg + assign $1\dmi0_addrsr_reg$next[7:0]$5707 \dmi0_addrsr_reg end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5519 \sr0__i + assign $2\dmi0_addrsr_reg$next[7:0]$5708 \dmi0_addrsr__i case - assign $2\sr0_reg$next[2:0]$5519 $1\sr0_reg$next[2:0]$5518 + assign $2\dmi0_addrsr_reg$next[7:0]$5708 $1\dmi0_addrsr_reg$next[7:0]$5707 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5520 3'000 + assign $3\dmi0_addrsr_reg$next[7:0]$5709 8'00000000 case - assign $3\sr0_reg$next[2:0]$5520 $2\sr0_reg$next[2:0]$5519 + assign $3\dmi0_addrsr_reg$next[7:0]$5709 $2\dmi0_addrsr_reg$next[7:0]$5708 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5517 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5706 end - attribute \src "libresoc.v:126655.3-126663.6" - process $proc$libresoc.v:126655$5521 + attribute \src "libresoc.v:128434.3-128442.6" + process $proc$libresoc.v:128434$5710 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5522 $1\jtag_wb_addrsr_update_core$next[0:0]$5523 - attribute \src "libresoc.v:126656.5-126656.29" + assign $0\dmi0_datasr_update_core$next[0:0]$5711 $1\dmi0_datasr_update_core$next[0:0]$5712 + attribute \src "libresoc.v:128435.5-128435.29" switch \initial - attribute \src "libresoc.v:126656.9-126656.17" + attribute \src "libresoc.v:128435.9-128435.17" case 1'1 case end @@ -201144,21 +205532,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5523 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$5712 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5523 \jtag_wb_addrsr_update + assign $1\dmi0_datasr_update_core$next[0:0]$5712 \dmi0_datasr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5522 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5711 end - attribute \src "libresoc.v:126664.3-126672.6" - process $proc$libresoc.v:126664$5524 + attribute \src "libresoc.v:128443.3-128451.6" + process $proc$libresoc.v:128443$5713 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 - attribute \src "libresoc.v:126665.5-126665.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$5714 $1\dmi0_datasr_update_core_prev$next[0:0]$5715 + attribute \src "libresoc.v:128444.5-128444.29" switch \initial - attribute \src "libresoc.v:126665.9-126665.17" + attribute \src "libresoc.v:128444.9-128444.17" case 1'1 case end @@ -201167,98 +205555,98 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5715 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5526 \jtag_wb_addrsr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$5715 \dmi0_datasr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5525 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5714 end - attribute \src "libresoc.v:126673.3-126689.6" - process $proc$libresoc.v:126673$5527 + attribute \src "libresoc.v:128452.3-128468.6" + process $proc$libresoc.v:128452$5716 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5528 $2\jtag_wb_addrsr__oe$next[0:0]$5530 - attribute \src "libresoc.v:126674.5-126674.29" + assign $0\dmi0_datasr__oe$next[1:0]$5717 $2\dmi0_datasr__oe$next[1:0]$5719 + attribute \src "libresoc.v:128453.5-128453.29" switch \initial - attribute \src "libresoc.v:126674.9-126674.17" + attribute \src "libresoc.v:128453.9-128453.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$195 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5529 \jtag_wb_addrsr_isir + assign $1\dmi0_datasr__oe$next[1:0]$5718 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5529 1'0 + assign $1\dmi0_datasr__oe$next[1:0]$5718 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5530 1'0 + assign $2\dmi0_datasr__oe$next[1:0]$5719 2'00 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5530 $1\jtag_wb_addrsr__oe$next[0:0]$5529 + assign $2\dmi0_datasr__oe$next[1:0]$5719 $1\dmi0_datasr__oe$next[1:0]$5718 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5528 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5717 end - attribute \src "libresoc.v:126690.3-126710.6" - process $proc$libresoc.v:126690$5531 + attribute \src "libresoc.v:128469.3-128489.6" + process $proc$libresoc.v:128469$5720 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5532 $3\jtag_wb_addrsr_reg$next[28:0]$5535 - attribute \src "libresoc.v:126691.5-126691.29" + assign $0\dmi0_datasr_reg$next[63:0]$5721 $3\dmi0_datasr_reg$next[63:0]$5724 + attribute \src "libresoc.v:128470.5-128470.29" switch \initial - attribute \src "libresoc.v:126691.9-126691.17" + attribute \src "libresoc.v:128470.9-128470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5533 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\dmi0_datasr_reg$next[63:0]$5722 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5533 \jtag_wb_addrsr_reg + assign $1\dmi0_datasr_reg$next[63:0]$5722 \dmi0_datasr_reg end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5534 \jtag_wb_addrsr__i + assign $2\dmi0_datasr_reg$next[63:0]$5723 \dmi0_datasr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5534 $1\jtag_wb_addrsr_reg$next[28:0]$5533 + assign $2\dmi0_datasr_reg$next[63:0]$5723 $1\dmi0_datasr_reg$next[63:0]$5722 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5535 29'00000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$5724 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5535 $2\jtag_wb_addrsr_reg$next[28:0]$5534 + assign $3\dmi0_datasr_reg$next[63:0]$5724 $2\dmi0_datasr_reg$next[63:0]$5723 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5532 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5721 end - attribute \src "libresoc.v:126711.3-126719.6" - process $proc$libresoc.v:126711$5536 + attribute \src "libresoc.v:128490.3-128498.6" + process $proc$libresoc.v:128490$5725 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5537 $1\jtag_wb_datasr_update_core$next[0:0]$5538 - attribute \src "libresoc.v:126712.5-126712.29" + assign $0\sr5_update_core$next[0:0]$5726 $1\sr5_update_core$next[0:0]$5727 + attribute \src "libresoc.v:128491.5-128491.29" switch \initial - attribute \src "libresoc.v:126712.9-126712.17" + attribute \src "libresoc.v:128491.9-128491.17" case 1'1 case end @@ -201267,21 +205655,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5538 1'0 + assign $1\sr5_update_core$next[0:0]$5727 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5538 \jtag_wb_datasr_update + assign $1\sr5_update_core$next[0:0]$5727 \sr5_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5537 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5726 end - attribute \src "libresoc.v:126720.3-126728.6" - process $proc$libresoc.v:126720$5539 + attribute \src "libresoc.v:128499.3-128507.6" + process $proc$libresoc.v:128499$5728 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 - attribute \src "libresoc.v:126721.5-126721.29" + assign $0\sr5_update_core_prev$next[0:0]$5729 $1\sr5_update_core_prev$next[0:0]$5730 + attribute \src "libresoc.v:128500.5-128500.29" switch \initial - attribute \src "libresoc.v:126721.9-126721.17" + attribute \src "libresoc.v:128500.9-128500.17" case 1'1 case end @@ -201290,528 +205678,1272 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 1'0 + assign $1\sr5_update_core_prev$next[0:0]$5730 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5541 \jtag_wb_datasr_update_core + assign $1\sr5_update_core_prev$next[0:0]$5730 \sr5_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5540 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5729 end - attribute \src "libresoc.v:126729.3-126745.6" - process $proc$libresoc.v:126729$5542 + attribute \src "libresoc.v:128508.3-128524.6" + process $proc$libresoc.v:128508$5731 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5543 $2\jtag_wb_datasr__oe$next[1:0]$5545 - attribute \src "libresoc.v:126730.5-126730.29" + assign $0\sr5__oe$next[0:0]$5732 $2\sr5__oe$next[0:0]$5734 + attribute \src "libresoc.v:128509.5-128509.29" switch \initial - attribute \src "libresoc.v:126730.9-126730.17" + attribute \src "libresoc.v:128509.9-128509.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$215 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5544 \jtag_wb_datasr_isir + assign $1\sr5__oe$next[0:0]$5733 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5544 2'00 + assign $1\sr5__oe$next[0:0]$5733 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5545 2'00 + assign $2\sr5__oe$next[0:0]$5734 1'0 case - assign $2\jtag_wb_datasr__oe$next[1:0]$5545 $1\jtag_wb_datasr__oe$next[1:0]$5544 + assign $2\sr5__oe$next[0:0]$5734 $1\sr5__oe$next[0:0]$5733 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5543 + update \sr5__oe$next $0\sr5__oe$next[0:0]$5732 end - attribute \src "libresoc.v:126746.3-126766.6" - process $proc$libresoc.v:126746$5546 + attribute \src "libresoc.v:128525.3-128545.6" + process $proc$libresoc.v:128525$5735 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5547 $3\jtag_wb_datasr_reg$next[63:0]$5550 - attribute \src "libresoc.v:126747.5-126747.29" + assign $0\sr5_reg$next[1:0]$5736 $3\sr5_reg$next[1:0]$5739 + attribute \src "libresoc.v:128526.5-128526.29" switch \initial - attribute \src "libresoc.v:126747.9-126747.17" + attribute \src "libresoc.v:128526.9-128526.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5548 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\sr5_reg$next[1:0]$5737 { \TAP_bus__tdi \sr5_reg [1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$5548 \jtag_wb_datasr_reg + assign $1\sr5_reg$next[1:0]$5737 \sr5_reg end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5549 \jtag_wb_datasr__i + assign $2\sr5_reg$next[1:0]$5738 \sr5__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$5549 $1\jtag_wb_datasr_reg$next[63:0]$5548 + assign $2\sr5_reg$next[1:0]$5738 $1\sr5_reg$next[1:0]$5737 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5550 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\sr5_reg$next[1:0]$5739 2'00 case - assign $3\jtag_wb_datasr_reg$next[63:0]$5550 $2\jtag_wb_datasr_reg$next[63:0]$5549 + assign $3\sr5_reg$next[1:0]$5739 $2\sr5_reg$next[1:0]$5738 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5547 + update \sr5_reg$next $0\sr5_reg$next[1:0]$5736 end - attribute \src "libresoc.v:126767.3-126775.6" - process $proc$libresoc.v:126767$5551 + attribute \src "libresoc.v:128546.3-128572.6" + process $proc$libresoc.v:128546$5740 assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5552 $1\dmi0_addrsr_update_core$next[0:0]$5553 - attribute \src "libresoc.v:126768.5-126768.29" + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:128547.5-128547.29" switch \initial - attribute \src "libresoc.v:126768.9-126768.17" + attribute \src "libresoc.v:128547.9-128547.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:128573.3-128605.6" + process $proc$libresoc.v:128573$5741 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$5742 $4\jtag_wb__adr$next[28:0]$5746 + attribute \src "libresoc.v:128574.5-128574.29" + switch \initial + attribute \src "libresoc.v:128574.9-128574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5743 $2\jtag_wb__adr$next[28:0]$5744 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5744 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$5744 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$5744 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$5743 $3\jtag_wb__adr$next[28:0]$5745 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$5745 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$5745 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$5743 \jtag_wb__adr + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5553 1'0 + assign $4\jtag_wb__adr$next[28:0]$5746 29'00000000000000000000000000000 case - assign $1\dmi0_addrsr_update_core$next[0:0]$5553 \dmi0_addrsr_update + assign $4\jtag_wb__adr$next[28:0]$5746 $1\jtag_wb__adr$next[28:0]$5743 end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5552 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5742 end - attribute \src "libresoc.v:126776.3-126784.6" - process $proc$libresoc.v:126776$5554 + attribute \src "libresoc.v:128606.3-128658.6" + process $proc$libresoc.v:128606$5747 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 - attribute \src "libresoc.v:126777.5-126777.29" + assign { } { } + assign $0\fsm_state$next[2:0]$5748 $5\fsm_state$next[2:0]$5753 + attribute \src "libresoc.v:128607.5-128607.29" switch \initial - attribute \src "libresoc.v:126777.9-126777.17" + attribute \src "libresoc.v:128607.9-128607.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$5749 $2\fsm_state$next[2:0]$5750 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$5750 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$5750 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$5750 3'010 + case + assign $2\fsm_state$next[2:0]$5750 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$5749 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$5749 $3\fsm_state$next[2:0]$5751 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$5751 3'000 + case + assign $3\fsm_state$next[2:0]$5751 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$5749 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$5749 $4\fsm_state$next[2:0]$5752 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$5752 3'001 + case + assign $4\fsm_state$next[2:0]$5752 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$5749 \fsm_state + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 1'0 + assign $5\fsm_state$next[2:0]$5753 3'000 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5556 \dmi0_addrsr_update_core + assign $5\fsm_state$next[2:0]$5753 $1\fsm_state$next[2:0]$5749 end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5555 + update \fsm_state$next $0\fsm_state$next[2:0]$5748 end - attribute \src "libresoc.v:126785.3-126801.6" - process $proc$libresoc.v:126785$5557 + attribute \src "libresoc.v:128659.3-128685.6" + process $proc$libresoc.v:128659$5754 + assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5558 $2\dmi0_addrsr__oe$next[0:0]$5560 - attribute \src "libresoc.v:126786.5-126786.29" + assign $0\jtag_wb__dat_w$next[63:0]$5755 $3\jtag_wb__dat_w$next[63:0]$5758 + attribute \src "libresoc.v:128660.5-128660.29" switch \initial - attribute \src "libresoc.v:126786.9-126786.17" + attribute \src "libresoc.v:128660.9-128660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:553" - switch \$233 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$5756 $2\jtag_wb__dat_w$next[63:0]$5757 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$5756 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$5758 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$5758 $1\jtag_wb__dat_w$next[63:0]$5756 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5755 + end + attribute \src "libresoc.v:128686.3-128706.6" + process $proc$libresoc.v:128686$5759 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$5760 $3\jtag_wb_datasr__i$next[63:0]$5763 + attribute \src "libresoc.v:128687.5-128687.29" + switch \initial + attribute \src "libresoc.v:128687.9-128687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$5761 $2\jtag_wb_datasr__i$next[63:0]$5762 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$5762 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$5762 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$5761 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$5763 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$5763 $1\jtag_wb_datasr__i$next[63:0]$5761 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5760 + end + attribute \src "libresoc.v:128707.3-128739.6" + process $proc$libresoc.v:128707$5764 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$5765 $4\dmi0__addr_i$next[3:0]$5769 + attribute \src "libresoc.v:128708.5-128708.29" + switch \initial + attribute \src "libresoc.v:128708.9-128708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$5766 $2\dmi0__addr_i$next[3:0]$5767 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$5767 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$5767 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$5767 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$5766 $3\dmi0__addr_i$next[3:0]$5768 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$5768 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$5768 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$5766 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$5769 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$5769 $1\dmi0__addr_i$next[3:0]$5766 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5765 + end + attribute \src "libresoc.v:128740.3-128792.6" + process $proc$libresoc.v:128740$5770 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$5771 $5\fsm_state$503$next[2:0]$5776 + attribute \src "libresoc.v:128741.5-128741.29" + switch \initial + attribute \src "libresoc.v:128741.9-128741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5772 $2\fsm_state$503$next[2:0]$5773 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$5773 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$5773 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$5773 3'010 + case + assign $2\fsm_state$503$next[2:0]$5773 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5772 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5772 $3\fsm_state$503$next[2:0]$5774 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$5774 3'000 + case + assign $3\fsm_state$503$next[2:0]$5774 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5772 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$5772 $4\fsm_state$503$next[2:0]$5775 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$5775 3'001 + case + assign $4\fsm_state$503$next[2:0]$5775 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$5772 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5559 \dmi0_addrsr_isir + assign $5\fsm_state$503$next[2:0]$5776 3'000 + case + assign $5\fsm_state$503$next[2:0]$5776 $1\fsm_state$503$next[2:0]$5772 + end + sync always + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$5771 + end + attribute \src "libresoc.v:128793.3-128819.6" + process $proc$libresoc.v:128793$5777 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$5778 $3\dmi0__din$next[63:0]$5781 + attribute \src "libresoc.v:128794.5-128794.29" + switch \initial + attribute \src "libresoc.v:128794.9-128794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$5779 $2\dmi0__din$next[63:0]$5780 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$5780 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$5780 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$5780 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$5780 \dmi0__din + end case + assign $1\dmi0__din$next[63:0]$5779 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5559 1'0 + assign $3\dmi0__din$next[63:0]$5781 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$5781 $1\dmi0__din$next[63:0]$5779 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$5778 + end + attribute \src "libresoc.v:128820.3-128840.6" + process $proc$libresoc.v:128820$5782 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$5783 $3\dmi0_datasr__i$next[63:0]$5786 + attribute \src "libresoc.v:128821.5-128821.29" + switch \initial + attribute \src "libresoc.v:128821.9-128821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$5784 $2\dmi0_datasr__i$next[63:0]$5785 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$5785 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$5785 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$5784 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5560 1'0 + assign $3\dmi0_datasr__i$next[63:0]$5786 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dmi0_addrsr__oe$next[0:0]$5560 $1\dmi0_addrsr__oe$next[0:0]$5559 + assign $3\dmi0_datasr__i$next[63:0]$5786 $1\dmi0_datasr__i$next[63:0]$5784 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5558 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5783 end - attribute \src "libresoc.v:126802.3-126822.6" - process $proc$libresoc.v:126802$5561 + attribute \src "libresoc.v:128841.3-128859.6" + process $proc$libresoc.v:128841$5787 + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5562 $3\dmi0_addrsr_reg$next[7:0]$5565 - attribute \src "libresoc.v:126803.5-126803.29" + assign { } { } + assign $0\wb_dcache_en$next[0:0]$5788 $2\wb_dcache_en$next[0:0]$5792 + assign $0\wb_icache_en$next[0:0]$5789 $2\wb_icache_en$next[0:0]$5793 + attribute \src "libresoc.v:128842.5-128842.29" switch \initial - attribute \src "libresoc.v:126803.9-126803.17" + attribute \src "libresoc.v:128842.9-128842.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:559" - switch \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + switch \sr5__oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5563 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign { } { } + assign { $1\wb_dcache_en$next[0:0]$5790 $1\wb_icache_en$next[0:0]$5791 } \sr5__o case - assign $1\dmi0_addrsr_reg$next[7:0]$5563 \dmi0_addrsr_reg + assign $1\wb_dcache_en$next[0:0]$5790 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$5791 \wb_icache_en end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:561" - switch \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5564 \dmi0_addrsr__i + assign { } { } + assign $2\wb_icache_en$next[0:0]$5793 1'1 + assign $2\wb_dcache_en$next[0:0]$5792 1'1 + case + assign $2\wb_dcache_en$next[0:0]$5792 $1\wb_dcache_en$next[0:0]$5790 + assign $2\wb_icache_en$next[0:0]$5793 $1\wb_icache_en$next[0:0]$5791 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$5788 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$5789 + end + attribute \src "libresoc.v:128860.3-128869.6" + process $proc$libresoc.v:128860$5794 + assign { } { } + assign { } { } + assign $0\sr5__i[1:0] $1\sr5__i[1:0] + attribute \src "libresoc.v:128861.5-128861.29" + switch \initial + attribute \src "libresoc.v:128861.9-128861.17" + case 1'1 case - assign $2\dmi0_addrsr_reg$next[7:0]$5564 $1\dmi0_addrsr_reg$next[7:0]$5563 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[1:0] 2'00 + end + sync always + update \sr5__i $0\sr5__i[1:0] + end + attribute \src "libresoc.v:128870.3-128887.6" + process $proc$libresoc.v:128870$5795 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[153:0]$5796 $2\io_sr$next[153:0]$5798 + attribute \src "libresoc.v:128871.5-128871.29" + switch \initial + attribute \src "libresoc.v:128871.9-128871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[153:0]$5797 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[153:0]$5797 { \io_sr [152:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[153:0]$5797 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5565 8'00000000 + assign $2\io_sr$next[153:0]$5798 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$5565 $2\dmi0_addrsr_reg$next[7:0]$5564 + assign $2\io_sr$next[153:0]$5798 $1\io_sr$next[153:0]$5797 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5562 + update \io_sr$next $0\io_sr$next[153:0]$5796 end - attribute \src "libresoc.v:126823.3-126831.6" - process $proc$libresoc.v:126823$5566 + attribute \src "libresoc.v:128888.3-128908.6" + process $proc$libresoc.v:128888$5799 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5567 $1\dmi0_datasr_update_core$next[0:0]$5568 - attribute \src "libresoc.v:126824.5-126824.29" + assign { } { } + assign $0\io_bd$next[153:0]$5800 $2\io_bd$next[153:0]$5802 + attribute \src "libresoc.v:128889.5-128889.29" switch \initial - attribute \src "libresoc.v:126824.9-126824.17" + attribute \src "libresoc.v:128889.9-128889.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[153:0]$5801 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[153:0]$5801 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[153:0]$5801 \io_sr + case + assign $1\io_bd$next[153:0]$5801 \io_bd + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5568 1'0 - case - assign $1\dmi0_datasr_update_core$next[0:0]$5568 \dmi0_datasr_update - end - sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5567 - end - connect \$9 $eq$libresoc.v:125917$5264_Y - connect \$99 $ternary$libresoc.v:125918$5265_Y - connect \$101 $ternary$libresoc.v:125919$5266_Y - connect \$103 $ternary$libresoc.v:125920$5267_Y - connect \$105 $ternary$libresoc.v:125921$5268_Y - connect \$107 $ternary$libresoc.v:125922$5269_Y - connect \$109 $ternary$libresoc.v:125923$5270_Y - connect \$111 $ternary$libresoc.v:125924$5271_Y - connect \$113 $ternary$libresoc.v:125925$5272_Y - connect \$115 $ternary$libresoc.v:125926$5273_Y - connect \$117 $ternary$libresoc.v:125927$5274_Y - connect \$11 $eq$libresoc.v:125928$5275_Y - connect \$119 $ternary$libresoc.v:125929$5276_Y - connect \$121 $ternary$libresoc.v:125930$5277_Y - connect \$123 $ternary$libresoc.v:125931$5278_Y - connect \$125 $ternary$libresoc.v:125932$5279_Y - connect \$127 $ternary$libresoc.v:125933$5280_Y - connect \$129 $ternary$libresoc.v:125934$5281_Y - connect \$131 $ternary$libresoc.v:125935$5282_Y - connect \$133 $ternary$libresoc.v:125936$5283_Y - connect \$135 $ternary$libresoc.v:125937$5284_Y - connect \$137 $ternary$libresoc.v:125938$5285_Y - connect \$13 $or$libresoc.v:125939$5286_Y - connect \$139 $ternary$libresoc.v:125940$5287_Y - connect \$141 $eq$libresoc.v:125941$5288_Y - connect \$143 $eq$libresoc.v:125942$5289_Y - connect \$145 $or$libresoc.v:125943$5290_Y - connect \$147 $and$libresoc.v:125944$5291_Y - connect \$149 $eq$libresoc.v:125945$5292_Y - connect \$151 $eq$libresoc.v:125946$5293_Y - connect \$153 $or$libresoc.v:125947$5294_Y - connect \$155 $eq$libresoc.v:125948$5295_Y - connect \$157 $or$libresoc.v:125949$5296_Y - connect \$15 $eq$libresoc.v:125950$5297_Y - connect \$159 $and$libresoc.v:125951$5298_Y - connect \$161 $eq$libresoc.v:125952$5299_Y - connect \$163 $ne$libresoc.v:125953$5300_Y - connect \$165 $and$libresoc.v:125954$5301_Y - connect \$167 $ne$libresoc.v:125955$5302_Y - connect \$169 $and$libresoc.v:125956$5303_Y - connect \$171 $ne$libresoc.v:125957$5304_Y - connect \$173 $and$libresoc.v:125958$5305_Y - connect \$175 $not$libresoc.v:125959$5306_Y - connect \$177 $and$libresoc.v:125960$5307_Y - connect \$17 $or$libresoc.v:125961$5308_Y - connect \$179 $eq$libresoc.v:125962$5309_Y - connect \$181 $ne$libresoc.v:125963$5310_Y - connect \$183 $and$libresoc.v:125964$5311_Y - connect \$185 $ne$libresoc.v:125965$5312_Y - connect \$187 $and$libresoc.v:125966$5313_Y - connect \$189 $ne$libresoc.v:125967$5314_Y - connect \$191 $and$libresoc.v:125968$5315_Y - connect \$193 $not$libresoc.v:125969$5316_Y - connect \$195 $and$libresoc.v:125970$5317_Y - connect \$197 $eq$libresoc.v:125971$5318_Y - connect \$1 $eq$libresoc.v:125972$5319_Y - connect \$19 $and$libresoc.v:125973$5320_Y - connect \$199 $eq$libresoc.v:125974$5321_Y - connect \$201 $ne$libresoc.v:125975$5322_Y - connect \$203 $and$libresoc.v:125976$5323_Y - connect \$205 $ne$libresoc.v:125977$5324_Y - connect \$207 $and$libresoc.v:125978$5325_Y - connect \$209 $ne$libresoc.v:125979$5326_Y - connect \$211 $and$libresoc.v:125980$5327_Y - connect \$213 $not$libresoc.v:125981$5328_Y - connect \$215 $and$libresoc.v:125982$5329_Y - connect \$217 $eq$libresoc.v:125983$5330_Y - connect \$21 $and$libresoc.v:125984$5331_Y - connect \$219 $ne$libresoc.v:125985$5332_Y - connect \$221 $and$libresoc.v:125986$5333_Y - connect \$223 $ne$libresoc.v:125987$5334_Y - connect \$225 $and$libresoc.v:125988$5335_Y - connect \$227 $ne$libresoc.v:125989$5336_Y - connect \$229 $and$libresoc.v:125990$5337_Y - connect \$231 $not$libresoc.v:125991$5338_Y - connect \$233 $and$libresoc.v:125992$5339_Y - connect \$235 $eq$libresoc.v:125993$5340_Y - connect \$237 $eq$libresoc.v:125994$5341_Y - connect \$23 $eq$libresoc.v:125995$5342_Y - connect \$239 $ne$libresoc.v:125996$5343_Y - connect \$241 $and$libresoc.v:125997$5344_Y - connect \$243 $ne$libresoc.v:125998$5345_Y - connect \$245 $and$libresoc.v:125999$5346_Y - connect \$247 $ne$libresoc.v:126000$5347_Y - connect \$249 $and$libresoc.v:126001$5348_Y - connect \$251 $not$libresoc.v:126002$5349_Y - connect \$253 $and$libresoc.v:126003$5350_Y - connect \$256 $eq$libresoc.v:126004$5351_Y - connect \$255 $not$libresoc.v:126005$5352_Y - connect \$25 $eq$libresoc.v:126006$5353_Y - connect \$259 $eq$libresoc.v:126007$5354_Y - connect \$261 $eq$libresoc.v:126008$5355_Y - connect \$263 $or$libresoc.v:126009$5356_Y - connect \$265 $eq$libresoc.v:126010$5357_Y - connect \$268 $add$libresoc.v:126011$5358_Y - connect \$271 $add$libresoc.v:126012$5359_Y - connect \$273 $pos$libresoc.v:126013$5361_Y - connect \$276 $eq$libresoc.v:126014$5362_Y - connect \$278 $eq$libresoc.v:126015$5363_Y - connect \$27 $or$libresoc.v:126016$5364_Y - connect \$280 $or$libresoc.v:126017$5365_Y - connect \$282 $eq$libresoc.v:126018$5366_Y - connect \$285 $add$libresoc.v:126019$5367_Y - connect \$288 $add$libresoc.v:126020$5368_Y - connect \$29 $eq$libresoc.v:126021$5369_Y - connect \$31 $or$libresoc.v:126022$5370_Y - connect \$33 $and$libresoc.v:126023$5371_Y - connect \$35 $and$libresoc.v:126024$5372_Y - connect \$37 $eq$libresoc.v:126025$5373_Y - connect \$3 $eq$libresoc.v:126026$5374_Y - connect \$39 $eq$libresoc.v:126027$5375_Y - connect \$41 $ternary$libresoc.v:126028$5376_Y - connect \$43 $ternary$libresoc.v:126029$5377_Y - connect \$45 $ternary$libresoc.v:126030$5378_Y - connect \$47 $ternary$libresoc.v:126031$5379_Y - connect \$49 $ternary$libresoc.v:126032$5380_Y - connect \$51 $ternary$libresoc.v:126033$5381_Y - connect \$53 $ternary$libresoc.v:126034$5382_Y - connect \$55 $ternary$libresoc.v:126035$5383_Y - connect \$57 $ternary$libresoc.v:126036$5384_Y - connect \$5 $or$libresoc.v:126037$5385_Y - connect \$59 $ternary$libresoc.v:126038$5386_Y - connect \$61 $ternary$libresoc.v:126039$5387_Y - connect \$63 $ternary$libresoc.v:126040$5388_Y - connect \$65 $ternary$libresoc.v:126041$5389_Y - connect \$67 $ternary$libresoc.v:126042$5390_Y - connect \$69 $ternary$libresoc.v:126043$5391_Y - connect \$71 $ternary$libresoc.v:126044$5392_Y - connect \$73 $ternary$libresoc.v:126045$5393_Y - connect \$75 $ternary$libresoc.v:126046$5394_Y - connect \$77 $ternary$libresoc.v:126047$5395_Y - connect \$7 $and$libresoc.v:126048$5396_Y - connect \$79 $ternary$libresoc.v:126049$5397_Y - connect \$81 $ternary$libresoc.v:126050$5398_Y - connect \$83 $ternary$libresoc.v:126051$5399_Y - connect \$85 $ternary$libresoc.v:126052$5400_Y - connect \$87 $ternary$libresoc.v:126053$5401_Y - connect \$89 $ternary$libresoc.v:126054$5402_Y - connect \$91 $ternary$libresoc.v:126055$5403_Y - connect \$93 $ternary$libresoc.v:126056$5404_Y - connect \$95 $ternary$libresoc.v:126057$5405_Y - connect \$97 $ternary$libresoc.v:126058$5406_Y - connect \$267 \$268 - connect \$270 \$271 - connect \$284 \$285 - connect \$287 \$288 + assign $2\io_bd$next[153:0]$5802 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$5802 $1\io_bd$next[153:0]$5801 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$5800 + end + connect \$9 $eq$libresoc.v:127831$5355_Y + connect \$99 $ternary$libresoc.v:127832$5356_Y + connect \$101 $ternary$libresoc.v:127833$5357_Y + connect \$103 $ternary$libresoc.v:127834$5358_Y + connect \$105 $ternary$libresoc.v:127835$5359_Y + connect \$107 $ternary$libresoc.v:127836$5360_Y + connect \$109 $ternary$libresoc.v:127837$5361_Y + connect \$111 $ternary$libresoc.v:127838$5362_Y + connect \$113 $ternary$libresoc.v:127839$5363_Y + connect \$115 $ternary$libresoc.v:127840$5364_Y + connect \$117 $ternary$libresoc.v:127841$5365_Y + connect \$11 $eq$libresoc.v:127842$5366_Y + connect \$119 $ternary$libresoc.v:127843$5367_Y + connect \$121 $ternary$libresoc.v:127844$5368_Y + connect \$123 $ternary$libresoc.v:127845$5369_Y + connect \$125 $ternary$libresoc.v:127846$5370_Y + connect \$127 $ternary$libresoc.v:127847$5371_Y + connect \$129 $ternary$libresoc.v:127848$5372_Y + connect \$131 $ternary$libresoc.v:127849$5373_Y + connect \$133 $ternary$libresoc.v:127850$5374_Y + connect \$135 $ternary$libresoc.v:127851$5375_Y + connect \$137 $ternary$libresoc.v:127852$5376_Y + connect \$13 $eq$libresoc.v:127853$5377_Y + connect \$139 $ternary$libresoc.v:127854$5378_Y + connect \$141 $ternary$libresoc.v:127855$5379_Y + connect \$143 $ternary$libresoc.v:127856$5380_Y + connect \$145 $ternary$libresoc.v:127857$5381_Y + connect \$147 $ternary$libresoc.v:127858$5382_Y + connect \$149 $ternary$libresoc.v:127859$5383_Y + connect \$151 $ternary$libresoc.v:127860$5384_Y + connect \$153 $ternary$libresoc.v:127861$5385_Y + connect \$155 $ternary$libresoc.v:127862$5386_Y + connect \$157 $ternary$libresoc.v:127863$5387_Y + connect \$15 $or$libresoc.v:127864$5388_Y + connect \$159 $ternary$libresoc.v:127865$5389_Y + connect \$161 $ternary$libresoc.v:127866$5390_Y + connect \$163 $ternary$libresoc.v:127867$5391_Y + connect \$165 $ternary$libresoc.v:127868$5392_Y + connect \$167 $ternary$libresoc.v:127869$5393_Y + connect \$169 $ternary$libresoc.v:127870$5394_Y + connect \$171 $ternary$libresoc.v:127871$5395_Y + connect \$173 $ternary$libresoc.v:127872$5396_Y + connect \$175 $ternary$libresoc.v:127873$5397_Y + connect \$177 $ternary$libresoc.v:127874$5398_Y + connect \$17 $and$libresoc.v:127875$5399_Y + connect \$179 $ternary$libresoc.v:127876$5400_Y + connect \$181 $ternary$libresoc.v:127877$5401_Y + connect \$183 $ternary$libresoc.v:127878$5402_Y + connect \$185 $ternary$libresoc.v:127879$5403_Y + connect \$187 $ternary$libresoc.v:127880$5404_Y + connect \$189 $ternary$libresoc.v:127881$5405_Y + connect \$191 $ternary$libresoc.v:127882$5406_Y + connect \$193 $ternary$libresoc.v:127883$5407_Y + connect \$195 $ternary$libresoc.v:127884$5408_Y + connect \$197 $ternary$libresoc.v:127885$5409_Y + connect \$1 $eq$libresoc.v:127886$5410_Y + connect \$19 $eq$libresoc.v:127887$5411_Y + connect \$199 $ternary$libresoc.v:127888$5412_Y + connect \$201 $ternary$libresoc.v:127889$5413_Y + connect \$203 $ternary$libresoc.v:127890$5414_Y + connect \$205 $ternary$libresoc.v:127891$5415_Y + connect \$207 $ternary$libresoc.v:127892$5416_Y + connect \$209 $ternary$libresoc.v:127893$5417_Y + connect \$211 $ternary$libresoc.v:127894$5418_Y + connect \$213 $ternary$libresoc.v:127895$5419_Y + connect \$215 $ternary$libresoc.v:127896$5420_Y + connect \$217 $ternary$libresoc.v:127897$5421_Y + connect \$21 $eq$libresoc.v:127898$5422_Y + connect \$219 $ternary$libresoc.v:127899$5423_Y + connect \$221 $ternary$libresoc.v:127900$5424_Y + connect \$223 $ternary$libresoc.v:127901$5425_Y + connect \$225 $ternary$libresoc.v:127902$5426_Y + connect \$227 $ternary$libresoc.v:127903$5427_Y + connect \$229 $ternary$libresoc.v:127904$5428_Y + connect \$231 $ternary$libresoc.v:127905$5429_Y + connect \$233 $ternary$libresoc.v:127906$5430_Y + connect \$235 $ternary$libresoc.v:127907$5431_Y + connect \$237 $ternary$libresoc.v:127908$5432_Y + connect \$23 $or$libresoc.v:127909$5433_Y + connect \$239 $ternary$libresoc.v:127910$5434_Y + connect \$241 $ternary$libresoc.v:127911$5435_Y + connect \$243 $ternary$libresoc.v:127912$5436_Y + connect \$245 $ternary$libresoc.v:127913$5437_Y + connect \$247 $ternary$libresoc.v:127914$5438_Y + connect \$249 $ternary$libresoc.v:127915$5439_Y + connect \$251 $ternary$libresoc.v:127916$5440_Y + connect \$253 $ternary$libresoc.v:127917$5441_Y + connect \$255 $ternary$libresoc.v:127918$5442_Y + connect \$257 $ternary$libresoc.v:127919$5443_Y + connect \$25 $eq$libresoc.v:127920$5444_Y + connect \$259 $ternary$libresoc.v:127921$5445_Y + connect \$261 $ternary$libresoc.v:127922$5446_Y + connect \$263 $ternary$libresoc.v:127923$5447_Y + connect \$265 $ternary$libresoc.v:127924$5448_Y + connect \$267 $ternary$libresoc.v:127925$5449_Y + connect \$269 $ternary$libresoc.v:127926$5450_Y + connect \$271 $ternary$libresoc.v:127927$5451_Y + connect \$273 $ternary$libresoc.v:127928$5452_Y + connect \$275 $ternary$libresoc.v:127929$5453_Y + connect \$277 $ternary$libresoc.v:127930$5454_Y + connect \$27 $or$libresoc.v:127931$5455_Y + connect \$279 $ternary$libresoc.v:127932$5456_Y + connect \$281 $ternary$libresoc.v:127933$5457_Y + connect \$283 $ternary$libresoc.v:127934$5458_Y + connect \$285 $ternary$libresoc.v:127935$5459_Y + connect \$287 $ternary$libresoc.v:127936$5460_Y + connect \$289 $ternary$libresoc.v:127937$5461_Y + connect \$291 $ternary$libresoc.v:127938$5462_Y + connect \$293 $ternary$libresoc.v:127939$5463_Y + connect \$295 $ternary$libresoc.v:127940$5464_Y + connect \$297 $ternary$libresoc.v:127941$5465_Y + connect \$29 $and$libresoc.v:127942$5466_Y + connect \$299 $ternary$libresoc.v:127943$5467_Y + connect \$301 $ternary$libresoc.v:127944$5468_Y + connect \$303 $ternary$libresoc.v:127945$5469_Y + connect \$305 $ternary$libresoc.v:127946$5470_Y + connect \$307 $ternary$libresoc.v:127947$5471_Y + connect \$309 $ternary$libresoc.v:127948$5472_Y + connect \$311 $ternary$libresoc.v:127949$5473_Y + connect \$313 $ternary$libresoc.v:127950$5474_Y + connect \$315 $ternary$libresoc.v:127951$5475_Y + connect \$317 $ternary$libresoc.v:127952$5476_Y + connect \$31 $and$libresoc.v:127953$5477_Y + connect \$319 $ternary$libresoc.v:127954$5478_Y + connect \$321 $ternary$libresoc.v:127955$5479_Y + connect \$323 $ternary$libresoc.v:127956$5480_Y + connect \$325 $ternary$libresoc.v:127957$5481_Y + connect \$327 $ternary$libresoc.v:127958$5482_Y + connect \$329 $ternary$libresoc.v:127959$5483_Y + connect \$331 $ternary$libresoc.v:127960$5484_Y + connect \$333 $ternary$libresoc.v:127961$5485_Y + connect \$335 $ternary$libresoc.v:127962$5486_Y + connect \$337 $ternary$libresoc.v:127963$5487_Y + connect \$33 $eq$libresoc.v:127964$5488_Y + connect \$339 $ternary$libresoc.v:127965$5489_Y + connect \$341 $ternary$libresoc.v:127966$5490_Y + connect \$343 $ternary$libresoc.v:127967$5491_Y + connect \$345 $ternary$libresoc.v:127968$5492_Y + connect \$347 $ternary$libresoc.v:127969$5493_Y + connect \$349 $ternary$libresoc.v:127970$5494_Y + connect \$351 $ternary$libresoc.v:127971$5495_Y + connect \$353 $ternary$libresoc.v:127972$5496_Y + connect \$355 $ternary$libresoc.v:127973$5497_Y + connect \$357 $ternary$libresoc.v:127974$5498_Y + connect \$35 $eq$libresoc.v:127975$5499_Y + connect \$359 $eq$libresoc.v:127976$5500_Y + connect \$361 $eq$libresoc.v:127977$5501_Y + connect \$363 $or$libresoc.v:127978$5502_Y + connect \$365 $eq$libresoc.v:127979$5503_Y + connect \$367 $or$libresoc.v:127980$5504_Y + connect \$369 $and$libresoc.v:127981$5505_Y + connect \$371 $eq$libresoc.v:127982$5506_Y + connect \$373 $ne$libresoc.v:127983$5507_Y + connect \$375 $and$libresoc.v:127984$5508_Y + connect \$377 $ne$libresoc.v:127985$5509_Y + connect \$37 $or$libresoc.v:127986$5510_Y + connect \$379 $and$libresoc.v:127987$5511_Y + connect \$381 $ne$libresoc.v:127988$5512_Y + connect \$383 $and$libresoc.v:127989$5513_Y + connect \$385 $not$libresoc.v:127990$5514_Y + connect \$387 $and$libresoc.v:127991$5515_Y + connect \$389 $eq$libresoc.v:127992$5516_Y + connect \$391 $ne$libresoc.v:127993$5517_Y + connect \$393 $and$libresoc.v:127994$5518_Y + connect \$395 $ne$libresoc.v:127995$5519_Y + connect \$397 $and$libresoc.v:127996$5520_Y + connect \$3 $eq$libresoc.v:127997$5521_Y + connect \$39 $eq$libresoc.v:127998$5522_Y + connect \$399 $ne$libresoc.v:127999$5523_Y + connect \$401 $and$libresoc.v:128000$5524_Y + connect \$403 $not$libresoc.v:128001$5525_Y + connect \$405 $and$libresoc.v:128002$5526_Y + connect \$407 $eq$libresoc.v:128003$5527_Y + connect \$409 $eq$libresoc.v:128004$5528_Y + connect \$411 $ne$libresoc.v:128005$5529_Y + connect \$413 $and$libresoc.v:128006$5530_Y + connect \$415 $ne$libresoc.v:128007$5531_Y + connect \$417 $and$libresoc.v:128008$5532_Y + connect \$41 $or$libresoc.v:128009$5533_Y + connect \$419 $ne$libresoc.v:128010$5534_Y + connect \$421 $and$libresoc.v:128011$5535_Y + connect \$423 $not$libresoc.v:128012$5536_Y + connect \$425 $and$libresoc.v:128013$5537_Y + connect \$427 $eq$libresoc.v:128014$5538_Y + connect \$429 $ne$libresoc.v:128015$5539_Y + connect \$431 $and$libresoc.v:128016$5540_Y + connect \$433 $ne$libresoc.v:128017$5541_Y + connect \$435 $and$libresoc.v:128018$5542_Y + connect \$437 $ne$libresoc.v:128019$5543_Y + connect \$43 $and$libresoc.v:128020$5544_Y + connect \$439 $and$libresoc.v:128021$5545_Y + connect \$441 $not$libresoc.v:128022$5546_Y + connect \$443 $and$libresoc.v:128023$5547_Y + connect \$445 $eq$libresoc.v:128024$5548_Y + connect \$447 $eq$libresoc.v:128025$5549_Y + connect \$449 $ne$libresoc.v:128026$5550_Y + connect \$451 $and$libresoc.v:128027$5551_Y + connect \$453 $ne$libresoc.v:128028$5552_Y + connect \$455 $and$libresoc.v:128029$5553_Y + connect \$457 $ne$libresoc.v:128030$5554_Y + connect \$45 $and$libresoc.v:128031$5555_Y + connect \$459 $and$libresoc.v:128032$5556_Y + connect \$461 $not$libresoc.v:128033$5557_Y + connect \$463 $and$libresoc.v:128034$5558_Y + connect \$465 $eq$libresoc.v:128035$5559_Y + connect \$467 $ne$libresoc.v:128036$5560_Y + connect \$469 $and$libresoc.v:128037$5561_Y + connect \$471 $ne$libresoc.v:128038$5562_Y + connect \$473 $and$libresoc.v:128039$5563_Y + connect \$475 $ne$libresoc.v:128040$5564_Y + connect \$477 $and$libresoc.v:128041$5565_Y + connect \$47 $eq$libresoc.v:128042$5566_Y + connect \$479 $not$libresoc.v:128043$5567_Y + connect \$481 $and$libresoc.v:128044$5568_Y + connect \$484 $eq$libresoc.v:128045$5569_Y + connect \$483 $not$libresoc.v:128046$5570_Y + connect \$487 $eq$libresoc.v:128047$5571_Y + connect \$489 $eq$libresoc.v:128048$5572_Y + connect \$491 $or$libresoc.v:128049$5573_Y + connect \$493 $eq$libresoc.v:128050$5574_Y + connect \$496 $add$libresoc.v:128051$5575_Y + connect \$49 $eq$libresoc.v:128052$5576_Y + connect \$499 $add$libresoc.v:128053$5577_Y + connect \$501 $pos$libresoc.v:128054$5579_Y + connect \$504 $eq$libresoc.v:128055$5580_Y + connect \$506 $eq$libresoc.v:128056$5581_Y + connect \$508 $or$libresoc.v:128057$5582_Y + connect \$510 $eq$libresoc.v:128058$5583_Y + connect \$513 $add$libresoc.v:128059$5584_Y + connect \$516 $add$libresoc.v:128060$5585_Y + connect \$51 $ternary$libresoc.v:128061$5586_Y + connect \$53 $ternary$libresoc.v:128062$5587_Y + connect \$55 $ternary$libresoc.v:128063$5588_Y + connect \$57 $ternary$libresoc.v:128064$5589_Y + connect \$5 $or$libresoc.v:128065$5590_Y + connect \$59 $ternary$libresoc.v:128066$5591_Y + connect \$61 $ternary$libresoc.v:128067$5592_Y + connect \$63 $ternary$libresoc.v:128068$5593_Y + connect \$65 $ternary$libresoc.v:128069$5594_Y + connect \$67 $ternary$libresoc.v:128070$5595_Y + connect \$69 $ternary$libresoc.v:128071$5596_Y + connect \$71 $ternary$libresoc.v:128072$5597_Y + connect \$73 $ternary$libresoc.v:128073$5598_Y + connect \$75 $ternary$libresoc.v:128074$5599_Y + connect \$77 $ternary$libresoc.v:128075$5600_Y + connect \$7 $and$libresoc.v:128076$5601_Y + connect \$79 $ternary$libresoc.v:128077$5602_Y + connect \$81 $ternary$libresoc.v:128078$5603_Y + connect \$83 $ternary$libresoc.v:128079$5604_Y + connect \$85 $ternary$libresoc.v:128080$5605_Y + connect \$87 $ternary$libresoc.v:128081$5606_Y + connect \$89 $ternary$libresoc.v:128082$5607_Y + connect \$91 $ternary$libresoc.v:128083$5608_Y + connect \$93 $ternary$libresoc.v:128084$5609_Y + connect \$95 $ternary$libresoc.v:128085$5610_Y + connect \$97 $ternary$libresoc.v:128086$5611_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 connect \sr0__i \sr0__o - connect \dmi0_we_i \$282 - connect \dmi0_req_i \$280 - connect \dmi0_addrsr__i \$273 - connect \jtag_wb__we \$265 - connect \jtag_wb__stb \$263 - connect \jtag_wb__cyc \$255 + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \dmi0_datasr_update \$249 - connect \dmi0_datasr_shift \$245 - connect \dmi0_datasr_capture \$241 - connect \dmi0_datasr_isir { \$237 \$235 } + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$229 - connect \dmi0_addrsr_shift \$225 - connect \dmi0_addrsr_capture \$221 - connect \dmi0_addrsr_isir \$217 + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$211 - connect \jtag_wb_datasr_shift \$207 - connect \jtag_wb_datasr_capture \$203 - connect \jtag_wb_datasr_isir { \$199 \$197 } + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$191 - connect \jtag_wb_addrsr_shift \$187 - connect \jtag_wb_addrsr_capture \$183 - connect \jtag_wb_addrsr_isir \$179 + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$173 - connect \sr0_shift \$169 - connect \sr0_capture \$165 - connect \sr0_isir \$161 + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 connect \sr0__o \sr0_reg - connect \gpio_gpio15__pad__oe \$139 - connect \gpio_gpio15__pad__o \$137 - connect \gpio_gpio15__core__i \$135 - connect \gpio_gpio14__pad__oe \$133 - connect \gpio_gpio14__pad__o \$131 - connect \gpio_gpio14__core__i \$129 - connect \gpio_gpio13__pad__oe \$127 - connect \gpio_gpio13__pad__o \$125 - connect \gpio_gpio13__core__i \$123 - connect \gpio_gpio12__pad__oe \$121 - connect \gpio_gpio12__pad__o \$119 - connect \gpio_gpio12__core__i \$117 - connect \gpio_gpio11__pad__oe \$115 - connect \gpio_gpio11__pad__o \$113 - connect \gpio_gpio11__core__i \$111 - connect \gpio_gpio10__pad__oe \$109 - connect \gpio_gpio10__pad__o \$107 - connect \gpio_gpio10__core__i \$105 - connect \gpio_gpio9__pad__oe \$103 - connect \gpio_gpio9__pad__o \$101 - connect \gpio_gpio9__core__i \$99 - connect \gpio_gpio8__pad__oe \$97 - connect \gpio_gpio8__pad__o \$95 - connect \gpio_gpio8__core__i \$93 - connect \gpio_gpio7__pad__oe \$91 - connect \gpio_gpio7__pad__o \$89 - connect \gpio_gpio7__core__i \$87 - connect \gpio_gpio6__pad__oe \$85 - connect \gpio_gpio6__pad__o \$83 - connect \gpio_gpio6__core__i \$81 - connect \gpio_gpio5__pad__oe \$79 - connect \gpio_gpio5__pad__o \$77 - connect \gpio_gpio5__core__i \$75 - connect \gpio_gpio4__pad__oe \$73 - connect \gpio_gpio4__pad__o \$71 - connect \gpio_gpio4__core__i \$69 - connect \gpio_gpio3__pad__oe \$67 - connect \gpio_gpio3__pad__o \$65 - connect \gpio_gpio3__core__i \$63 - connect \gpio_gpio2__pad__oe \$61 - connect \gpio_gpio2__pad__o \$59 - connect \gpio_gpio2__core__i \$57 - connect \gpio_gpio1__pad__oe \$55 - connect \gpio_gpio1__pad__o \$53 - connect \gpio_gpio1__core__i \$51 - connect \gpio_gpio0__pad__oe \$49 - connect \gpio_gpio0__pad__o \$47 - connect \gpio_gpio0__core__i \$45 - connect \uart_rx__core__i \$43 - connect \uart_tx__pad__o \$41 - connect \io_bd2core \$39 - connect \io_bd2io \$37 - connect \io_update \$35 - connect \io_shift \$21 - connect \io_capture \$7 + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:126929.1-127094.10" +attribute \src "libresoc.v:129118.1-129307.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 15 \dbus__ack + wire input 23 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 20 \dbus__adr + wire width 45 output 28 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 14 \dbus__cyc + wire output 22 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 19 \dbus__dat_r + wire width 64 input 27 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 22 \dbus__dat_w + wire width 64 output 30 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 16 \dbus__err + wire input 24 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 18 \dbus__sel + wire width 8 output 26 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 17 \dbus__stb + wire output 25 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 21 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 9 \ldst_port0_addr_ok_o + wire output 16 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire output 2 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 3 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire \pimem_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pimem_ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire \pimem_ldst_port0_addr_ok_o @@ -201819,68 +206951,79 @@ module \l0 wire \pimem_ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \pimem_ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire \pimem_ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire \pimem_x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:127018.12-127045.4" - cell \l0$127 \l0 + attribute \src "libresoc.v:129223.12-129257.4" + cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o + connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len + connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 + connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i + connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:127046.9-127067.4" + attribute \src "libresoc.v:129258.9-129280.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -201895,6 +207038,7 @@ module \l0 connect \dbus__we \dbus__we connect \m_ld_data_o \pimem_m_ld_data_o connect \m_valid_i \pimem_m_valid_i + connect \wb_dcache_en \wb_dcache_en connect \x_addr_i \pimem_x_addr_i connect \x_busy_o \pimem_x_busy_o connect \x_ld_i \pimem_x_ld_i @@ -201904,16 +207048,16 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:127068.9-127092.4" + attribute \src "libresoc.v:129281.9-129305.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o @@ -201930,189 +207074,269 @@ module \l0 connect \x_st_i \pimem_x_st_i connect \x_valid_i \pimem_x_valid_i end - connect \pimem_ldst_port0_addr_exc_o 1'0 + connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:127098.1-127412.10" +attribute \src "libresoc.v:129311.1-129719.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" -module \l0$127 - attribute \src "libresoc.v:127307.3-127321.6" - wire $0\idx_l$16$next[0:0]$5624 - attribute \src "libresoc.v:127214.3-127215.35" - wire $0\idx_l$16[0:0]$5607 - attribute \src "libresoc.v:127119.7-127119.24" - wire $0\idx_l$16[0:0]$5643 - attribute \src "libresoc.v:127322.3-127331.6" +module \l0$130 + attribute \src "libresoc.v:129574.3-129588.6" + wire $0\idx_l$23$next[0:0]$5880 + attribute \src "libresoc.v:129474.3-129475.35" + wire $0\idx_l$23[0:0]$5847 + attribute \src "libresoc.v:129332.7-129332.24" + wire $0\idx_l$23[0:0]$5902 + attribute \src "libresoc.v:129629.3-129638.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:127332.3-127341.6" + attribute \src "libresoc.v:129619.3-129628.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:127099.7-127099.20" + attribute \src "libresoc.v:129312.7-129312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127297.3-127306.6" - wire $0\ldst_port0_addr_exc_o[0:0] - attribute \src "libresoc.v:127235.3-127244.6" - wire width 48 $0\ldst_port0_addr_i$5[47:0]$5609 - attribute \src "libresoc.v:127245.3-127254.6" - wire $0\ldst_port0_addr_i_ok$6[0:0]$5612 - attribute \src "libresoc.v:127287.3-127296.6" + attribute \src "libresoc.v:129495.3-129504.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$5849 + attribute \src "libresoc.v:129505.3-129514.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$5852 + attribute \src "libresoc.v:129547.3-129556.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:127277.3-127286.6" + attribute \src "libresoc.v:129537.3-129546.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:127387.3-127396.6" - wire width 4 $0\ldst_port0_data_len$4[3:0]$5638 - attribute \src "libresoc.v:127397.3-127406.6" + attribute \src "libresoc.v:129609.3-129618.6" + wire $0\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:129684.3-129693.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$5897 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$5864 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$5865 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$5866 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$5867 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$5868 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$5869 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$5870 + attribute \src "libresoc.v:129557.3-129573.6" + wire $0\ldst_port0_exc_$signal[0:0]$5863 + attribute \src "libresoc.v:129694.3-129703.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:127367.3-127376.6" - wire $0\ldst_port0_is_ld_i$1[0:0]$5632 - attribute \src "libresoc.v:127377.3-127386.6" - wire $0\ldst_port0_is_st_i$2[0:0]$5635 - attribute \src "libresoc.v:127266.3-127276.6" + attribute \src "libresoc.v:129664.3-129673.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$5891 + attribute \src "libresoc.v:129674.3-129683.6" + wire $0\ldst_port0_is_st_i$9[0:0]$5894 + attribute \src "libresoc.v:129526.3-129536.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:127266.3-127276.6" + attribute \src "libresoc.v:129526.3-129536.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:127255.3-127265.6" - wire width 64 $0\ldst_port0_st_data_i$11[63:0]$5615 - attribute \src "libresoc.v:127255.3-127265.6" - wire $0\ldst_port0_st_data_i_ok$10[0:0]$5616 - attribute \src "libresoc.v:127212.3-127213.36" + attribute \src "libresoc.v:129599.3-129608.6" + wire $0\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:129589.3-129598.6" + wire $0\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:129515.3-129525.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$5855 + attribute \src "libresoc.v:129515.3-129525.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$5856 + attribute \src "libresoc.v:129472.3-129473.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:127357.3-127366.6" + attribute \src "libresoc.v:129654.3-129663.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:127342.3-127356.6" + attribute \src "libresoc.v:129639.3-129653.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:127307.3-127321.6" - wire $1\idx_l$16$next[0:0]$5625 - attribute \src "libresoc.v:127322.3-127331.6" + attribute \src "libresoc.v:129574.3-129588.6" + wire $1\idx_l$23$next[0:0]$5881 + attribute \src "libresoc.v:129629.3-129638.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:127332.3-127341.6" + attribute \src "libresoc.v:129619.3-129628.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:127297.3-127306.6" - wire $1\ldst_port0_addr_exc_o[0:0] - attribute \src "libresoc.v:127235.3-127244.6" - wire width 48 $1\ldst_port0_addr_i$5[47:0]$5610 - attribute \src "libresoc.v:127245.3-127254.6" - wire $1\ldst_port0_addr_i_ok$6[0:0]$5613 - attribute \src "libresoc.v:127287.3-127296.6" + attribute \src "libresoc.v:129495.3-129504.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$5850 + attribute \src "libresoc.v:129505.3-129514.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$5853 + attribute \src "libresoc.v:129547.3-129556.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:127277.3-127286.6" + attribute \src "libresoc.v:129537.3-129546.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:127387.3-127396.6" - wire width 4 $1\ldst_port0_data_len$4[3:0]$5639 - attribute \src "libresoc.v:127397.3-127406.6" + attribute \src "libresoc.v:129609.3-129618.6" + wire $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:129684.3-129693.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$5898 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$5872 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$5873 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$5874 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$5875 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$5876 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$5877 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$5878 + attribute \src "libresoc.v:129557.3-129573.6" + wire $1\ldst_port0_exc_$signal[0:0]$5871 + attribute \src "libresoc.v:129694.3-129703.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:127367.3-127376.6" - wire $1\ldst_port0_is_ld_i$1[0:0]$5633 - attribute \src "libresoc.v:127377.3-127386.6" - wire $1\ldst_port0_is_st_i$2[0:0]$5636 - attribute \src "libresoc.v:127266.3-127276.6" + attribute \src "libresoc.v:129664.3-129673.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$5892 + attribute \src "libresoc.v:129674.3-129683.6" + wire $1\ldst_port0_is_st_i$9[0:0]$5895 + attribute \src "libresoc.v:129526.3-129536.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:127266.3-127276.6" + attribute \src "libresoc.v:129526.3-129536.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:127255.3-127265.6" - wire width 64 $1\ldst_port0_st_data_i$11[63:0]$5617 - attribute \src "libresoc.v:127255.3-127265.6" - wire $1\ldst_port0_st_data_i_ok$10[0:0]$5618 - attribute \src "libresoc.v:127199.7-127199.25" + attribute \src "libresoc.v:129599.3-129608.6" + wire $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:129589.3-129598.6" + wire $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:129515.3-129525.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$5857 + attribute \src "libresoc.v:129515.3-129525.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$5858 + attribute \src "libresoc.v:129459.7-129459.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:127357.3-127366.6" + attribute \src "libresoc.v:129654.3-129663.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:127342.3-127356.6" + attribute \src "libresoc.v:129639.3-129653.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:127307.3-127321.6" - wire $2\idx_l$16$next[0:0]$5626 - attribute \src "libresoc.v:127342.3-127356.6" + attribute \src "libresoc.v:129574.3-129588.6" + wire $2\idx_l$23$next[0:0]$5882 + attribute \src "libresoc.v:129639.3-129653.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:127210.18-127210.103" - wire $not$libresoc.v:127210$5603_Y - attribute \src "libresoc.v:127211.18-127211.117" - wire $not$libresoc.v:127211$5604_Y - attribute \src "libresoc.v:127208.18-127208.134" - wire $or$libresoc.v:127208$5601_Y - attribute \src "libresoc.v:127209.18-127209.120" - wire $ternary$libresoc.v:127209$5602_Y + attribute \src "libresoc.v:129470.18-129470.103" + wire $not$libresoc.v:129470$5843_Y + attribute \src "libresoc.v:129471.18-129471.118" + wire $not$libresoc.v:129471$5844_Y + attribute \src "libresoc.v:129468.18-129468.134" + wire $or$libresoc.v:129468$5841_Y + attribute \src "libresoc.v:129469.18-129469.120" + wire $ternary$libresoc.v:129469$5842_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - wire \$13 + wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$15 + wire \$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$17 + wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - wire \$19 + wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire width 96 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire width 96 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$16 + wire \idx_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$16$next + wire \idx_l$23$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \idx_l_q_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \idx_l_s_idx_l - attribute \src "libresoc.v:127099.7-127099.15" + attribute \src "libresoc.v:129312.7-129312.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 25 \ldst_port0_addr_exc_o$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 output 18 \ldst_port0_addr_i$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 output 25 \ldst_port0_addr_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 19 \ldst_port0_addr_i_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \ldst_port0_addr_i_ok$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 9 \ldst_port0_addr_ok_o + wire output 16 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 20 \ldst_port0_addr_ok_o$7 + wire input 27 \ldst_port0_addr_ok_o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire output 2 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 16 \ldst_port0_busy_o$3 + wire input 23 \ldst_port0_busy_o$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 17 \ldst_port0_data_len$4 + wire width 4 output 24 \ldst_port0_data_len$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 32 \ldst_port0_exc_$signal$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" wire \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i$23 + wire \ldst_port0_go_die_i$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 3 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 14 \ldst_port0_is_ld_i$1 + wire output 21 \ldst_port0_is_ld_i$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 4 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 15 \ldst_port0_is_st_i$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 21 \ldst_port0_ld_data_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 22 \ldst_port0_ld_data_o_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \ldst_port0_st_data_i$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \ldst_port0_st_data_i_ok$10 + wire output 22 \ldst_port0_is_st_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 28 \ldst_port0_ld_data_o$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \ldst_port0_ld_data_o_ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \ldst_port0_st_data_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \ldst_port0_st_data_i_ok$17 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire \pick_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" @@ -202130,23 +207354,23 @@ module \l0$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:127210$5603 + cell $not $not$libresoc.v:129470$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:127210$5603_Y + connect \Y $not$libresoc.v:129470$5843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:127211$5604 + cell $not $not$libresoc.v:129471$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o$3 - connect \Y $not$libresoc.v:127211$5604_Y + connect \A \ldst_port0_busy_o$10 + connect \Y $not$libresoc.v:129471$5844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:127208$5601 + cell $or $or$libresoc.v:129468$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202154,18 +207378,18 @@ module \l0$127 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:127208$5601_Y + connect \Y $or$libresoc.v:129468$5841_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:127209$5602 + cell $mux $ternary$libresoc.v:129469$5842 parameter \WIDTH 1 - connect \A \idx_l$16 + connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:127209$5602_Y + connect \Y $ternary$libresoc.v:129469$5842_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127216.9-127222.4" + attribute \src "libresoc.v:129476.9-129482.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -202174,67 +207398,67 @@ module \l0$127 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:127223.8-127227.4" + attribute \src "libresoc.v:129483.8-129487.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:127228.17-127234.4" - cell \reset_l$128 \reset_l + attribute \src "libresoc.v:129488.17-129494.4" + cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_reset \reset_l_q_reset connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:127099.7-127099.20" - process $proc$libresoc.v:127099$5641 + attribute \src "libresoc.v:129312.7-129312.20" + process $proc$libresoc.v:129312$5900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127119.7-127119.24" - process $proc$libresoc.v:127119$5642 + attribute \src "libresoc.v:129332.7-129332.24" + process $proc$libresoc.v:129332$5901 assign { } { } - assign $0\idx_l$16[0:0]$5643 1'0 + assign $0\idx_l$23[0:0]$5902 1'0 sync always sync init - update \idx_l$16 $0\idx_l$16[0:0]$5643 + update \idx_l$23 $0\idx_l$23[0:0]$5902 end - attribute \src "libresoc.v:127199.7-127199.25" - process $proc$libresoc.v:127199$5644 + attribute \src "libresoc.v:129459.7-129459.25" + process $proc$libresoc.v:129459$5903 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:127212.3-127213.36" - process $proc$libresoc.v:127212$5605 + attribute \src "libresoc.v:129472.3-129473.36" + process $proc$libresoc.v:129472$5845 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:127214.3-127215.35" - process $proc$libresoc.v:127214$5606 + attribute \src "libresoc.v:129474.3-129475.35" + process $proc$libresoc.v:129474$5846 assign { } { } - assign $0\idx_l$16[0:0]$5607 \idx_l$16$next + assign $0\idx_l$23[0:0]$5847 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$16 $0\idx_l$16[0:0]$5607 + update \idx_l$23 $0\idx_l$23[0:0]$5847 end - attribute \src "libresoc.v:127235.3-127244.6" - process $proc$libresoc.v:127235$5608 + attribute \src "libresoc.v:129495.3-129504.6" + process $proc$libresoc.v:129495$5848 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$5[47:0]$5609 $1\ldst_port0_addr_i$5[47:0]$5610 - attribute \src "libresoc.v:127236.5-127236.29" + assign $0\ldst_port0_addr_i$12[47:0]$5849 $1\ldst_port0_addr_i$12[47:0]$5850 + attribute \src "libresoc.v:129496.5-129496.29" switch \initial - attribute \src "libresoc.v:127236.9-127236.17" + attribute \src "libresoc.v:129496.9-129496.17" case 1'1 case end @@ -202243,21 +207467,21 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$5[47:0]$5610 \$25 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$5850 \$32 [47:0] case - assign $1\ldst_port0_addr_i$5[47:0]$5610 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$5850 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$5 $0\ldst_port0_addr_i$5[47:0]$5609 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$5849 end - attribute \src "libresoc.v:127245.3-127254.6" - process $proc$libresoc.v:127245$5611 + attribute \src "libresoc.v:129505.3-129514.6" + process $proc$libresoc.v:129505$5851 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$6[0:0]$5612 $1\ldst_port0_addr_i_ok$6[0:0]$5613 - attribute \src "libresoc.v:127246.5-127246.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$5852 $1\ldst_port0_addr_i_ok$13[0:0]$5853 + attribute \src "libresoc.v:129506.5-129506.29" switch \initial - attribute \src "libresoc.v:127246.9-127246.17" + attribute \src "libresoc.v:129506.9-129506.17" case 1'1 case end @@ -202266,24 +207490,24 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$6[0:0]$5613 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$5853 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$6[0:0]$5613 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$5853 1'0 end sync always - update \ldst_port0_addr_i_ok$6 $0\ldst_port0_addr_i_ok$6[0:0]$5612 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$5852 end - attribute \src "libresoc.v:127255.3-127265.6" - process $proc$libresoc.v:127255$5614 + attribute \src "libresoc.v:129515.3-129525.6" + process $proc$libresoc.v:129515$5854 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$11[63:0]$5615 $1\ldst_port0_st_data_i$11[63:0]$5617 - assign $0\ldst_port0_st_data_i_ok$10[0:0]$5616 $1\ldst_port0_st_data_i_ok$10[0:0]$5618 - attribute \src "libresoc.v:127256.5-127256.29" + assign $0\ldst_port0_st_data_i$18[63:0]$5855 $1\ldst_port0_st_data_i$18[63:0]$5857 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$5856 $1\ldst_port0_st_data_i_ok$17[0:0]$5858 + attribute \src "libresoc.v:129516.5-129516.29" switch \initial - attribute \src "libresoc.v:127256.9-127256.17" + attribute \src "libresoc.v:129516.9-129516.17" case 1'1 case end @@ -202293,26 +207517,26 @@ module \l0$127 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$10[0:0]$5618 $1\ldst_port0_st_data_i$11[63:0]$5617 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$5858 $1\ldst_port0_st_data_i$18[63:0]$5857 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$11[63:0]$5617 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$10[0:0]$5618 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$5857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$5858 1'0 end sync always - update \ldst_port0_st_data_i$11 $0\ldst_port0_st_data_i$11[63:0]$5615 - update \ldst_port0_st_data_i_ok$10 $0\ldst_port0_st_data_i_ok$10[0:0]$5616 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$5855 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$5856 end - attribute \src "libresoc.v:127266.3-127276.6" - process $proc$libresoc.v:127266$5619 + attribute \src "libresoc.v:129526.3-129536.6" + process $proc$libresoc.v:129526$5859 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:127267.5-127267.29" + attribute \src "libresoc.v:129527.5-129527.29" switch \initial - attribute \src "libresoc.v:127267.9-127267.17" + attribute \src "libresoc.v:129527.9-129527.17" case 1'1 case end @@ -202322,7 +207546,7 @@ module \l0$127 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } case assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 @@ -202331,14 +207555,14 @@ module \l0$127 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:127277.3-127286.6" - process $proc$libresoc.v:127277$5620 + attribute \src "libresoc.v:129537.3-129546.6" + process $proc$libresoc.v:129537$5860 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:127278.5-127278.29" + attribute \src "libresoc.v:129538.5-129538.29" switch \initial - attribute \src "libresoc.v:127278.9-127278.17" + attribute \src "libresoc.v:129538.9-129538.17" case 1'1 case end @@ -202347,21 +207571,21 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$3 + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 case assign $1\ldst_port0_busy_o[0:0] 1'0 end sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:127287.3-127296.6" - process $proc$libresoc.v:127287$5621 + attribute \src "libresoc.v:129547.3-129556.6" + process $proc$libresoc.v:129547$5861 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:127288.5-127288.29" + attribute \src "libresoc.v:129548.5-129548.29" switch \initial - attribute \src "libresoc.v:127288.9-127288.17" + attribute \src "libresoc.v:129548.9-129548.17" case 1'1 case end @@ -202370,21 +207594,42 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$7 + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 case assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:127297.3-127306.6" - process $proc$libresoc.v:127297$5622 + attribute \src "libresoc.v:129557.3-129573.6" + process $proc$libresoc.v:129557$5862 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_addr_exc_o[0:0] $1\ldst_port0_addr_exc_o[0:0] - attribute \src "libresoc.v:127298.5-127298.29" + assign { } { } + assign { } { } + assign $0\ldst_port0_exc_$signal[0:0]$5863 $1\ldst_port0_exc_$signal[0:0]$5871 + assign $0\ldst_port0_exc_$signal$1[0:0]$5864 $1\ldst_port0_exc_$signal$1[0:0]$5872 + assign $0\ldst_port0_exc_$signal$2[0:0]$5865 $1\ldst_port0_exc_$signal$2[0:0]$5873 + assign $0\ldst_port0_exc_$signal$3[0:0]$5866 $1\ldst_port0_exc_$signal$3[0:0]$5874 + assign $0\ldst_port0_exc_$signal$4[0:0]$5867 $1\ldst_port0_exc_$signal$4[0:0]$5875 + assign $0\ldst_port0_exc_$signal$5[0:0]$5868 $1\ldst_port0_exc_$signal$5[0:0]$5876 + assign $0\ldst_port0_exc_$signal$6[0:0]$5869 $1\ldst_port0_exc_$signal$6[0:0]$5877 + assign $0\ldst_port0_exc_$signal$7[0:0]$5870 $1\ldst_port0_exc_$signal$7[0:0]$5878 + attribute \src "libresoc.v:129558.5-129558.29" switch \initial - attribute \src "libresoc.v:127298.9-127298.17" + attribute \src "libresoc.v:129558.9-129558.17" case 1'1 case end @@ -202393,22 +207638,43 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_exc_o[0:0] \ldst_port0_addr_exc_o$12 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\ldst_port0_exc_$signal$7[0:0]$5878 $1\ldst_port0_exc_$signal$6[0:0]$5877 $1\ldst_port0_exc_$signal$5[0:0]$5876 $1\ldst_port0_exc_$signal$4[0:0]$5875 $1\ldst_port0_exc_$signal$3[0:0]$5874 $1\ldst_port0_exc_$signal$2[0:0]$5873 $1\ldst_port0_exc_$signal$1[0:0]$5872 $1\ldst_port0_exc_$signal[0:0]$5871 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_addr_exc_o[0:0] 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$5871 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$5872 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$5873 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$5874 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$5875 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$5876 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$5877 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$5878 1'0 end sync always - update \ldst_port0_addr_exc_o $0\ldst_port0_addr_exc_o[0:0] + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$5863 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$5864 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$5865 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$5866 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$5867 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$5868 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$5869 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$5870 end - attribute \src "libresoc.v:127307.3-127321.6" - process $proc$libresoc.v:127307$5623 + attribute \src "libresoc.v:129574.3-129588.6" + process $proc$libresoc.v:129574$5879 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$16$next[0:0]$5624 $2\idx_l$16$next[0:0]$5626 - attribute \src "libresoc.v:127308.5-127308.29" + assign $0\idx_l$23$next[0:0]$5880 $2\idx_l$23$next[0:0]$5882 + attribute \src "libresoc.v:129575.5-129575.29" switch \initial - attribute \src "libresoc.v:127308.9-127308.17" + attribute \src "libresoc.v:129575.9-129575.17" case 1'1 case end @@ -202417,58 +207683,104 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$16$next[0:0]$5625 \pick_o + assign $1\idx_l$23$next[0:0]$5881 \pick_o case - assign $1\idx_l$16$next[0:0]$5625 \idx_l$16 + assign $1\idx_l$23$next[0:0]$5881 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$16$next[0:0]$5626 1'0 + assign $2\idx_l$23$next[0:0]$5882 1'0 case - assign $2\idx_l$16$next[0:0]$5626 $1\idx_l$16$next[0:0]$5625 + assign $2\idx_l$23$next[0:0]$5882 $1\idx_l$23$next[0:0]$5881 end sync always - update \idx_l$16$next $0\idx_l$16$next[0:0]$5624 + update \idx_l$23$next $0\idx_l$23$next[0:0]$5880 end - attribute \src "libresoc.v:127322.3-127331.6" - process $proc$libresoc.v:127322$5627 + attribute \src "libresoc.v:129589.3-129598.6" + process $proc$libresoc.v:129589$5883 assign { } { } assign { } { } - assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:127323.5-127323.29" + assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:129590.5-129590.29" switch \initial - attribute \src "libresoc.v:127323.9-127323.17" + attribute \src "libresoc.v:129590.9-129590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l_r_idx_l[0:0] 1'1 + assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 case - assign $1\idx_l_r_idx_l[0:0] 1'1 + assign $1\ldst_port0_mmu_done[0:0] 1'0 end sync always - update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] + end + attribute \src "libresoc.v:129599.3-129608.6" + process $proc$libresoc.v:129599$5884 + assign { } { } + assign { } { } + assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:129600.5-129600.29" + switch \initial + attribute \src "libresoc.v:129600.9-129600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 + case + assign $1\ldst_port0_ldst_error[0:0] 1'0 + end + sync always + update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:127332.3-127341.6" - process $proc$libresoc.v:127332$5628 + attribute \src "libresoc.v:129609.3-129618.6" + process $proc$libresoc.v:129609$5885 + assign { } { } + assign { } { } + assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:129610.5-129610.29" + switch \initial + attribute \src "libresoc.v:129610.9-129610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 + case + assign $1\ldst_port0_cache_paradox[0:0] 1'0 + end + sync always + update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] + end + attribute \src "libresoc.v:129619.3-129628.6" + process $proc$libresoc.v:129619$5886 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:127333.5-127333.29" + attribute \src "libresoc.v:129620.5-129620.29" switch \initial - attribute \src "libresoc.v:127333.9-127333.17" + attribute \src "libresoc.v:129620.9-129620.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - switch \$19 + switch \$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -202479,14 +207791,37 @@ module \l0$127 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:127342.3-127356.6" - process $proc$libresoc.v:127342$5629 + attribute \src "libresoc.v:129629.3-129638.6" + process $proc$libresoc.v:129629$5887 + assign { } { } + assign { } { } + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:129630.5-129630.29" + switch \initial + attribute \src "libresoc.v:129630.9-129630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_r_idx_l[0:0] 1'1 + case + assign $1\idx_l_r_idx_l[0:0] 1'1 + end + sync always + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + end + attribute \src "libresoc.v:129639.3-129653.6" + process $proc$libresoc.v:129639$5888 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:127343.5-127343.29" + attribute \src "libresoc.v:129640.5-129640.29" switch \initial - attribute \src "libresoc.v:127343.9-127343.17" + attribute \src "libresoc.v:129640.9-129640.17" case 1'1 case end @@ -202497,7 +207832,7 @@ module \l0$127 assign { } { } assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - switch \$21 + switch \$28 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -202511,14 +207846,14 @@ module \l0$127 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:127357.3-127366.6" - process $proc$libresoc.v:127357$5630 + attribute \src "libresoc.v:129654.3-129663.6" + process $proc$libresoc.v:129654$5889 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:127358.5-127358.29" + attribute \src "libresoc.v:129655.5-129655.29" switch \initial - attribute \src "libresoc.v:127358.9-127358.17" + attribute \src "libresoc.v:129655.9-129655.17" case 1'1 case end @@ -202534,14 +207869,14 @@ module \l0$127 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:127367.3-127376.6" - process $proc$libresoc.v:127367$5631 + attribute \src "libresoc.v:129664.3-129673.6" + process $proc$libresoc.v:129664$5890 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$1[0:0]$5632 $1\ldst_port0_is_ld_i$1[0:0]$5633 - attribute \src "libresoc.v:127368.5-127368.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$5891 $1\ldst_port0_is_ld_i$8[0:0]$5892 + attribute \src "libresoc.v:129665.5-129665.29" switch \initial - attribute \src "libresoc.v:127368.9-127368.17" + attribute \src "libresoc.v:129665.9-129665.17" case 1'1 case end @@ -202550,21 +207885,21 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$1[0:0]$5633 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$5892 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$1[0:0]$5633 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$5892 1'0 end sync always - update \ldst_port0_is_ld_i$1 $0\ldst_port0_is_ld_i$1[0:0]$5632 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$5891 end - attribute \src "libresoc.v:127377.3-127386.6" - process $proc$libresoc.v:127377$5634 + attribute \src "libresoc.v:129674.3-129683.6" + process $proc$libresoc.v:129674$5893 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$2[0:0]$5635 $1\ldst_port0_is_st_i$2[0:0]$5636 - attribute \src "libresoc.v:127378.5-127378.29" + assign $0\ldst_port0_is_st_i$9[0:0]$5894 $1\ldst_port0_is_st_i$9[0:0]$5895 + attribute \src "libresoc.v:129675.5-129675.29" switch \initial - attribute \src "libresoc.v:127378.9-127378.17" + attribute \src "libresoc.v:129675.9-129675.17" case 1'1 case end @@ -202573,21 +207908,21 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$2[0:0]$5636 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$5895 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$2[0:0]$5636 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$5895 1'0 end sync always - update \ldst_port0_is_st_i$2 $0\ldst_port0_is_st_i$2[0:0]$5635 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$5894 end - attribute \src "libresoc.v:127387.3-127396.6" - process $proc$libresoc.v:127387$5637 + attribute \src "libresoc.v:129684.3-129693.6" + process $proc$libresoc.v:129684$5896 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$4[3:0]$5638 $1\ldst_port0_data_len$4[3:0]$5639 - attribute \src "libresoc.v:127388.5-127388.29" + assign $0\ldst_port0_data_len$11[3:0]$5897 $1\ldst_port0_data_len$11[3:0]$5898 + attribute \src "libresoc.v:129685.5-129685.29" switch \initial - attribute \src "libresoc.v:127388.9-127388.17" + attribute \src "libresoc.v:129685.9-129685.17" case 1'1 case end @@ -202596,21 +207931,21 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$4[3:0]$5639 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$5898 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$4[3:0]$5639 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$5898 4'0000 end sync always - update \ldst_port0_data_len$4 $0\ldst_port0_data_len$4[3:0]$5638 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$5897 end - attribute \src "libresoc.v:127397.3-127406.6" - process $proc$libresoc.v:127397$5640 + attribute \src "libresoc.v:129694.3-129703.6" + process $proc$libresoc.v:129694$5899 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:127398.5-127398.29" + attribute \src "libresoc.v:129695.5-129695.29" switch \initial - attribute \src "libresoc.v:127398.9-127398.17" + attribute \src "libresoc.v:129695.9-129695.17" case 1'1 case end @@ -202619,54 +207954,64 @@ module \l0$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$23 + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 case assign $1\ldst_port0_go_die_i[0:0] 1'0 end sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$13 $or$libresoc.v:127208$5601_Y - connect \$17 $ternary$libresoc.v:127209$5602_Y - connect \$19 $not$libresoc.v:127210$5603_Y - connect \$21 $not$libresoc.v:127211$5604_Y - connect \$15 \$17 - connect \$25 \ldst_port0_addr_i - connect \ldst_port0_go_die_i$23 1'0 + connect \$20 $or$libresoc.v:129468$5841_Y + connect \$24 $ternary$libresoc.v:129469$5842_Y + connect \$26 $not$libresoc.v:129470$5843_Y + connect \$28 $not$libresoc.v:129471$5844_Y + connect \$22 \$24 + connect \$32 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$30 1'0 + connect \ldst_port0_exc_$signal$33 1'0 + connect \ldst_port0_exc_$signal$34 1'0 + connect \ldst_port0_exc_$signal$35 1'0 + connect \ldst_port0_exc_$signal$36 1'0 + connect \ldst_port0_exc_$signal$37 1'0 + connect \ldst_port0_exc_$signal$38 1'0 + connect \ldst_port0_exc_$signal$39 1'0 + connect \ldst_port0_mmu_done$40 1'0 + connect \ldst_port0_ldst_error$41 1'0 + connect \ldst_port0_cache_paradox$42 1'0 connect \reset_delay$next \reset_l_q_reset - connect \pick_i \$13 + connect \pick_i \$20 end -attribute \src "libresoc.v:127416.1-127474.10" +attribute \src "libresoc.v:129723.1-129781.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:127417.7-127417.20" + attribute \src "libresoc.v:129724.7-129724.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127462.3-127470.6" - wire $0\q_int$next[0:0]$5655 - attribute \src "libresoc.v:127460.3-127461.27" + attribute \src "libresoc.v:129769.3-129777.6" + wire $0\q_int$next[0:0]$5914 + attribute \src "libresoc.v:129767.3-129768.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:127462.3-127470.6" - wire $1\q_int$next[0:0]$5656 - attribute \src "libresoc.v:127439.7-127439.19" + attribute \src "libresoc.v:129769.3-129777.6" + wire $1\q_int$next[0:0]$5915 + attribute \src "libresoc.v:129746.7-129746.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:127452.17-127452.96" - wire $and$libresoc.v:127452$5645_Y - attribute \src "libresoc.v:127457.17-127457.96" - wire $and$libresoc.v:127457$5650_Y - attribute \src "libresoc.v:127454.18-127454.99" - wire $not$libresoc.v:127454$5647_Y - attribute \src "libresoc.v:127456.17-127456.98" - wire $not$libresoc.v:127456$5649_Y - attribute \src "libresoc.v:127459.17-127459.98" - wire $not$libresoc.v:127459$5652_Y - attribute \src "libresoc.v:127453.18-127453.104" - wire $or$libresoc.v:127453$5646_Y - attribute \src "libresoc.v:127455.18-127455.105" - wire $or$libresoc.v:127455$5648_Y - attribute \src "libresoc.v:127458.17-127458.103" - wire $or$libresoc.v:127458$5651_Y + attribute \src "libresoc.v:129759.17-129759.96" + wire $and$libresoc.v:129759$5904_Y + attribute \src "libresoc.v:129764.17-129764.96" + wire $and$libresoc.v:129764$5909_Y + attribute \src "libresoc.v:129761.18-129761.99" + wire $not$libresoc.v:129761$5906_Y + attribute \src "libresoc.v:129763.17-129763.98" + wire $not$libresoc.v:129763$5908_Y + attribute \src "libresoc.v:129766.17-129766.98" + wire $not$libresoc.v:129766$5911_Y + attribute \src "libresoc.v:129760.18-129760.104" + wire $or$libresoc.v:129760$5905_Y + attribute \src "libresoc.v:129762.18-129762.105" + wire $or$libresoc.v:129762$5907_Y + attribute \src "libresoc.v:129765.17-129765.103" + wire $or$libresoc.v:129765$5910_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -202683,11 +208028,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:127417.7-127417.15" + attribute \src "libresoc.v:129724.7-129724.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -202704,7 +208049,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:127452$5645 + cell $and $and$libresoc.v:129759$5904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202712,10 +208057,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:127452$5645_Y + connect \Y $and$libresoc.v:129759$5904_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:127457$5650 + cell $and $and$libresoc.v:129764$5909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202723,34 +208068,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:127457$5650_Y + connect \Y $and$libresoc.v:129764$5909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:127454$5647 + cell $not $not$libresoc.v:129761$5906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:127454$5647_Y + connect \Y $not$libresoc.v:129761$5906_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:127456$5649 + cell $not $not$libresoc.v:129763$5908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:127456$5649_Y + connect \Y $not$libresoc.v:129763$5908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:127459$5652 + cell $not $not$libresoc.v:129766$5911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:127459$5652_Y + connect \Y $not$libresoc.v:129766$5911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:127453$5646 + cell $or $or$libresoc.v:129760$5905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202758,10 +208103,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:127453$5646_Y + connect \Y $or$libresoc.v:129760$5905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:127455$5648 + cell $or $or$libresoc.v:129762$5907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202769,10 +208114,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:127455$5648_Y + connect \Y $or$libresoc.v:129762$5907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:127458$5651 + cell $or $or$libresoc.v:129765$5910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202780,39 +208125,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:127458$5651_Y + connect \Y $or$libresoc.v:129765$5910_Y end - attribute \src "libresoc.v:127417.7-127417.20" - process $proc$libresoc.v:127417$5657 + attribute \src "libresoc.v:129724.7-129724.20" + process $proc$libresoc.v:129724$5916 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127439.7-127439.19" - process $proc$libresoc.v:127439$5658 + attribute \src "libresoc.v:129746.7-129746.19" + process $proc$libresoc.v:129746$5917 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:127460.3-127461.27" - process $proc$libresoc.v:127460$5653 + attribute \src "libresoc.v:129767.3-129768.27" + process $proc$libresoc.v:129767$5912 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:127462.3-127470.6" - process $proc$libresoc.v:127462$5654 + attribute \src "libresoc.v:129769.3-129777.6" + process $proc$libresoc.v:129769$5913 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5655 $1\q_int$next[0:0]$5656 - attribute \src "libresoc.v:127463.5-127463.29" + assign $0\q_int$next[0:0]$5914 $1\q_int$next[0:0]$5915 + attribute \src "libresoc.v:129770.5-129770.29" switch \initial - attribute \src "libresoc.v:127463.9-127463.17" + attribute \src "libresoc.v:129770.9-129770.17" case 1'1 case end @@ -202821,765 +208166,763 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5656 1'0 + assign $1\q_int$next[0:0]$5915 1'0 case - assign $1\q_int$next[0:0]$5656 \$5 + assign $1\q_int$next[0:0]$5915 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5655 + update \q_int$next $0\q_int$next[0:0]$5914 end - connect \$9 $and$libresoc.v:127452$5645_Y - connect \$11 $or$libresoc.v:127453$5646_Y - connect \$13 $not$libresoc.v:127454$5647_Y - connect \$15 $or$libresoc.v:127455$5648_Y - connect \$1 $not$libresoc.v:127456$5649_Y - connect \$3 $and$libresoc.v:127457$5650_Y - connect \$5 $or$libresoc.v:127458$5651_Y - connect \$7 $not$libresoc.v:127459$5652_Y + connect \$9 $and$libresoc.v:129759$5904_Y + connect \$11 $or$libresoc.v:129760$5905_Y + connect \$13 $not$libresoc.v:129761$5906_Y + connect \$15 $or$libresoc.v:129762$5907_Y + connect \$1 $not$libresoc.v:129763$5908_Y + connect \$3 $and$libresoc.v:129764$5909_Y + connect \$5 $or$libresoc.v:129765$5910_Y + connect \$7 $not$libresoc.v:129766$5911_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:127478.1-128807.10" +attribute \src "libresoc.v:129785.1-131142.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:128462.3-128470.6" - wire $0\adr_l_r_adr$next[0:0]$5801 - attribute \src "libresoc.v:128344.3-128345.39" + attribute \src "libresoc.v:130797.3-130805.6" + wire $0\adr_l_r_adr$next[0:0]$6060 + attribute \src "libresoc.v:130679.3-130680.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:128290.3-128291.21" + attribute \src "libresoc.v:130625.3-130626.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:128627.3-128636.6" + attribute \src "libresoc.v:130962.3-130971.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:128637.3-128646.6" + attribute \src "libresoc.v:130972.3-130981.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:128617.3-128626.6" - wire width 64 $0\ea_r$next[63:0]$5889 - attribute \src "libresoc.v:128292.3-128293.25" + attribute \src "libresoc.v:130952.3-130961.6" + wire width 64 $0\ea_r$next[63:0]$6148 + attribute \src "libresoc.v:130627.3-130628.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:127479.7-127479.20" + attribute \src "libresoc.v:129786.7-129786.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128692.3-128711.6" + attribute \src "libresoc.v:131027.3-131046.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:128656.3-128679.6" + attribute \src "libresoc.v:130991.3-131014.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:128559.3-128568.6" - wire width 64 $0\ldo_r$next[63:0]$5874 - attribute \src "libresoc.v:128300.3-128301.27" + attribute \src "libresoc.v:130894.3-130903.6" + wire width 64 $0\ldo_r$next[63:0]$6133 + attribute \src "libresoc.v:130635.3-130636.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:128288.3-128289.33" + attribute \src "libresoc.v:130623.3-130624.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:128647.3-128655.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$5894 - attribute \src "libresoc.v:128286.3-128287.57" + attribute \src "libresoc.v:130982.3-130990.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6153 + attribute \src "libresoc.v:130621.3-130622.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:128736.3-128747.6" + attribute \src "libresoc.v:131071.3-131082.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:128507.3-128515.6" - wire $0\lsd_l_r_lsd$next[0:0]$5816 - attribute \src "libresoc.v:128334.3-128335.39" + attribute \src "libresoc.v:130842.3-130850.6" + wire $0\lsd_l_r_lsd$next[0:0]$6075 + attribute \src "libresoc.v:130669.3-130670.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:128435.3-128443.6" - wire $0\opc_l_r_opc$next[0:0]$5792 - attribute \src "libresoc.v:128350.3-128351.39" + attribute \src "libresoc.v:130770.3-130778.6" + wire $0\opc_l_r_opc$next[0:0]$6051 + attribute \src "libresoc.v:130685.3-130686.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:128426.3-128434.6" - wire $0\opc_l_s_opc$next[0:0]$5789 - attribute \src "libresoc.v:128352.3-128353.39" + attribute \src "libresoc.v:130761.3-130769.6" + wire $0\opc_l_s_opc$next[0:0]$6048 + attribute \src "libresoc.v:130687.3-130688.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__byte_reverse$next[0:0]$5819 - attribute \src "libresoc.v:128326.3-128327.57" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__byte_reverse$next[0:0]$6078 + attribute \src "libresoc.v:130661.3-130662.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 4 $0\oper_r__data_len$next[3:0]$5820 - attribute \src "libresoc.v:128324.3-128325.49" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6079 + attribute \src "libresoc.v:130659.3-130660.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 12 $0\oper_r__fn_unit$next[11:0]$5821 - attribute \src "libresoc.v:128304.3-128305.47" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 12 $0\oper_r__fn_unit$next[11:0]$6080 + attribute \src "libresoc.v:130639.3-130640.47" wire width 12 $0\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$5822 - attribute \src "libresoc.v:128306.3-128307.61" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6081 + attribute \src "libresoc.v:130641.3-130642.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__imm_data__ok$next[0:0]$5823 - attribute \src "libresoc.v:128308.3-128309.57" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6082 + attribute \src "libresoc.v:130643.3-130644.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 32 $0\oper_r__insn$next[31:0]$5824 - attribute \src "libresoc.v:128332.3-128333.41" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 32 $0\oper_r__insn$next[31:0]$6083 + attribute \src "libresoc.v:130667.3-130668.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$5825 - attribute \src "libresoc.v:128302.3-128303.51" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6084 + attribute \src "libresoc.v:130637.3-130638.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__is_32bit$next[0:0]$5826 - attribute \src "libresoc.v:128320.3-128321.49" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__is_32bit$next[0:0]$6085 + attribute \src "libresoc.v:130655.3-130656.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__is_signed$next[0:0]$5827 - attribute \src "libresoc.v:128322.3-128323.51" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__is_signed$next[0:0]$6086 + attribute \src "libresoc.v:130657.3-130658.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$5828 - attribute \src "libresoc.v:128330.3-128331.51" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6087 + attribute \src "libresoc.v:130665.3-130666.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__oe__oe$next[0:0]$5829 - attribute \src "libresoc.v:128316.3-128317.45" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__oe__oe$next[0:0]$6088 + attribute \src "libresoc.v:130651.3-130652.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__oe__ok$next[0:0]$5830 - attribute \src "libresoc.v:128318.3-128319.45" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__oe__ok$next[0:0]$6089 + attribute \src "libresoc.v:130653.3-130654.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__rc__ok$next[0:0]$5831 - attribute \src "libresoc.v:128314.3-128315.45" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__rc__ok$next[0:0]$6090 + attribute \src "libresoc.v:130649.3-130650.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__rc__rc$next[0:0]$5832 - attribute \src "libresoc.v:128312.3-128313.45" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__rc__rc$next[0:0]$6091 + attribute \src "libresoc.v:130647.3-130648.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__sign_extend$next[0:0]$5833 - attribute \src "libresoc.v:128328.3-128329.55" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__sign_extend$next[0:0]$6092 + attribute \src "libresoc.v:130663.3-130664.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $0\oper_r__zero_a$next[0:0]$5834 - attribute \src "libresoc.v:128310.3-128311.45" + attribute \src "libresoc.v:130851.3-130893.6" + wire $0\oper_r__zero_a$next[0:0]$6093 + attribute \src "libresoc.v:130645.3-130646.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:128354.3-128355.28" + attribute \src "libresoc.v:130689.3-130690.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:128680.3-128691.6" + attribute \src "libresoc.v:131015.3-131026.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:128453.3-128461.6" - wire width 3 $0\src_l_r_src$next[2:0]$5798 - attribute \src "libresoc.v:128346.3-128347.39" + attribute \src "libresoc.v:130788.3-130796.6" + wire width 3 $0\src_l_r_src$next[2:0]$6057 + attribute \src "libresoc.v:130681.3-130682.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:128444.3-128452.6" - wire width 3 $0\src_l_s_src$next[2:0]$5795 - attribute \src "libresoc.v:128348.3-128349.39" + attribute \src "libresoc.v:130779.3-130787.6" + wire width 3 $0\src_l_s_src$next[2:0]$6054 + attribute \src "libresoc.v:130683.3-130684.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:128569.3-128584.6" - wire width 64 $0\src_r0$next[63:0]$5877 - attribute \src "libresoc.v:128298.3-128299.29" + attribute \src "libresoc.v:130904.3-130919.6" + wire width 64 $0\src_r0$next[63:0]$6136 + attribute \src "libresoc.v:130633.3-130634.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:128585.3-128600.6" - wire width 64 $0\src_r1$next[63:0]$5881 - attribute \src "libresoc.v:128296.3-128297.29" + attribute \src "libresoc.v:130920.3-130935.6" + wire width 64 $0\src_r1$next[63:0]$6140 + attribute \src "libresoc.v:130631.3-130632.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:128601.3-128616.6" - wire width 64 $0\src_r2$next[63:0]$5885 - attribute \src "libresoc.v:128294.3-128295.29" + attribute \src "libresoc.v:130936.3-130951.6" + wire width 64 $0\src_r2$next[63:0]$6144 + attribute \src "libresoc.v:130629.3-130630.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:128712.3-128735.6" + attribute \src "libresoc.v:131047.3-131070.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:128498.3-128506.6" - wire $0\sto_l_r_sto$next[0:0]$5813 - attribute \src "libresoc.v:128336.3-128337.39" + attribute \src "libresoc.v:130833.3-130841.6" + wire $0\sto_l_r_sto$next[0:0]$6072 + attribute \src "libresoc.v:130671.3-130672.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:128489.3-128497.6" - wire $0\upd_l_r_upd$next[0:0]$5810 - attribute \src "libresoc.v:128338.3-128339.39" + attribute \src "libresoc.v:130824.3-130832.6" + wire $0\upd_l_r_upd$next[0:0]$6069 + attribute \src "libresoc.v:130673.3-130674.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:128480.3-128488.6" - wire $0\upd_l_s_upd$next[0:0]$5807 - attribute \src "libresoc.v:128340.3-128341.39" + attribute \src "libresoc.v:130815.3-130823.6" + wire $0\upd_l_s_upd$next[0:0]$6066 + attribute \src "libresoc.v:130675.3-130676.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:128471.3-128479.6" - wire $0\wri_l_r_wri$next[0:0]$5804 - attribute \src "libresoc.v:128342.3-128343.39" + attribute \src "libresoc.v:130806.3-130814.6" + wire $0\wri_l_r_wri$next[0:0]$6063 + attribute \src "libresoc.v:130677.3-130678.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:128462.3-128470.6" - wire $1\adr_l_r_adr$next[0:0]$5802 - attribute \src "libresoc.v:127677.7-127677.25" + attribute \src "libresoc.v:130797.3-130805.6" + wire $1\adr_l_r_adr$next[0:0]$6061 + attribute \src "libresoc.v:129982.7-129982.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:127691.7-127691.20" + attribute \src "libresoc.v:129996.7-129996.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:128627.3-128636.6" + attribute \src "libresoc.v:130962.3-130971.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:128637.3-128646.6" + attribute \src "libresoc.v:130972.3-130981.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:128617.3-128626.6" - wire width 64 $1\ea_r$next[63:0]$5890 - attribute \src "libresoc.v:127737.14-127737.41" + attribute \src "libresoc.v:130952.3-130961.6" + wire width 64 $1\ea_r$next[63:0]$6149 + attribute \src "libresoc.v:130042.14-130042.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:128692.3-128711.6" + attribute \src "libresoc.v:131027.3-131046.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:128656.3-128679.6" + attribute \src "libresoc.v:130991.3-131014.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:128559.3-128568.6" - wire width 64 $1\ldo_r$next[63:0]$5875 - attribute \src "libresoc.v:127751.14-127751.42" + attribute \src "libresoc.v:130894.3-130903.6" + wire width 64 $1\ldo_r$next[63:0]$6134 + attribute \src "libresoc.v:130072.14-130072.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:127758.14-127758.62" + attribute \src "libresoc.v:130077.14-130077.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:128647.3-128655.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$5895 - attribute \src "libresoc.v:127763.7-127763.34" + attribute \src "libresoc.v:130982.3-130990.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6154 + attribute \src "libresoc.v:130082.7-130082.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:128736.3-128747.6" + attribute \src "libresoc.v:131071.3-131082.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:128507.3-128515.6" - wire $1\lsd_l_r_lsd$next[0:0]$5817 - attribute \src "libresoc.v:127796.7-127796.25" + attribute \src "libresoc.v:130842.3-130850.6" + wire $1\lsd_l_r_lsd$next[0:0]$6076 + attribute \src "libresoc.v:130131.7-130131.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:128435.3-128443.6" - wire $1\opc_l_r_opc$next[0:0]$5793 - attribute \src "libresoc.v:127810.7-127810.25" + attribute \src "libresoc.v:130770.3-130778.6" + wire $1\opc_l_r_opc$next[0:0]$6052 + attribute \src "libresoc.v:130145.7-130145.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:128426.3-128434.6" - wire $1\opc_l_s_opc$next[0:0]$5790 - attribute \src "libresoc.v:127814.7-127814.25" + attribute \src "libresoc.v:130761.3-130769.6" + wire $1\opc_l_s_opc$next[0:0]$6049 + attribute \src "libresoc.v:130149.7-130149.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__byte_reverse$next[0:0]$5835 - attribute \src "libresoc.v:127942.7-127942.34" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__byte_reverse$next[0:0]$6094 + attribute \src "libresoc.v:130277.7-130277.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 4 $1\oper_r__data_len$next[3:0]$5836 - attribute \src "libresoc.v:127946.13-127946.36" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6095 + attribute \src "libresoc.v:130281.13-130281.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 12 $1\oper_r__fn_unit$next[11:0]$5837 - attribute \src "libresoc.v:127963.14-127963.39" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 12 $1\oper_r__fn_unit$next[11:0]$6096 + attribute \src "libresoc.v:130298.14-130298.39" wire width 12 $1\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$5838 - attribute \src "libresoc.v:127967.14-127967.59" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6097 + attribute \src "libresoc.v:130302.14-130302.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__imm_data__ok$next[0:0]$5839 - attribute \src "libresoc.v:127971.7-127971.34" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6098 + attribute \src "libresoc.v:130306.7-130306.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 32 $1\oper_r__insn$next[31:0]$5840 - attribute \src "libresoc.v:127975.14-127975.34" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 32 $1\oper_r__insn$next[31:0]$6099 + attribute \src "libresoc.v:130310.14-130310.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$5841 - attribute \src "libresoc.v:128053.13-128053.38" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6100 + attribute \src "libresoc.v:130388.13-130388.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__is_32bit$next[0:0]$5842 - attribute \src "libresoc.v:128057.7-128057.30" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__is_32bit$next[0:0]$6101 + attribute \src "libresoc.v:130392.7-130392.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__is_signed$next[0:0]$5843 - attribute \src "libresoc.v:128061.7-128061.31" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__is_signed$next[0:0]$6102 + attribute \src "libresoc.v:130396.7-130396.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$5844 - attribute \src "libresoc.v:128070.13-128070.37" + attribute \src "libresoc.v:130851.3-130893.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6103 + attribute \src "libresoc.v:130405.13-130405.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__oe__oe$next[0:0]$5845 - attribute \src "libresoc.v:128074.7-128074.28" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__oe__oe$next[0:0]$6104 + attribute \src "libresoc.v:130409.7-130409.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__oe__ok$next[0:0]$5846 - attribute \src "libresoc.v:128078.7-128078.28" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__oe__ok$next[0:0]$6105 + attribute \src "libresoc.v:130413.7-130413.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__rc__ok$next[0:0]$5847 - attribute \src "libresoc.v:128082.7-128082.28" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__rc__ok$next[0:0]$6106 + attribute \src "libresoc.v:130417.7-130417.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__rc__rc$next[0:0]$5848 - attribute \src "libresoc.v:128086.7-128086.28" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__rc__rc$next[0:0]$6107 + attribute \src "libresoc.v:130421.7-130421.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__sign_extend$next[0:0]$5849 - attribute \src "libresoc.v:128090.7-128090.33" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__sign_extend$next[0:0]$6108 + attribute \src "libresoc.v:130425.7-130425.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $1\oper_r__zero_a$next[0:0]$5850 - attribute \src "libresoc.v:128094.7-128094.28" + attribute \src "libresoc.v:130851.3-130893.6" + wire $1\oper_r__zero_a$next[0:0]$6109 + attribute \src "libresoc.v:130429.7-130429.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:128098.7-128098.21" + attribute \src "libresoc.v:130433.7-130433.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:128680.3-128691.6" + attribute \src "libresoc.v:131015.3-131026.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:128453.3-128461.6" - wire width 3 $1\src_l_r_src$next[2:0]$5799 - attribute \src "libresoc.v:128140.13-128140.31" + attribute \src "libresoc.v:130788.3-130796.6" + wire width 3 $1\src_l_r_src$next[2:0]$6058 + attribute \src "libresoc.v:130475.13-130475.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:128444.3-128452.6" - wire width 3 $1\src_l_s_src$next[2:0]$5796 - attribute \src "libresoc.v:128144.13-128144.31" + attribute \src "libresoc.v:130779.3-130787.6" + wire width 3 $1\src_l_s_src$next[2:0]$6055 + attribute \src "libresoc.v:130479.13-130479.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:128569.3-128584.6" - wire width 64 $1\src_r0$next[63:0]$5878 - attribute \src "libresoc.v:128148.14-128148.43" + attribute \src "libresoc.v:130904.3-130919.6" + wire width 64 $1\src_r0$next[63:0]$6137 + attribute \src "libresoc.v:130483.14-130483.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:128585.3-128600.6" - wire width 64 $1\src_r1$next[63:0]$5882 - attribute \src "libresoc.v:128152.14-128152.43" + attribute \src "libresoc.v:130920.3-130935.6" + wire width 64 $1\src_r1$next[63:0]$6141 + attribute \src "libresoc.v:130487.14-130487.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:128601.3-128616.6" - wire width 64 $1\src_r2$next[63:0]$5886 - attribute \src "libresoc.v:128156.14-128156.43" + attribute \src "libresoc.v:130936.3-130951.6" + wire width 64 $1\src_r2$next[63:0]$6145 + attribute \src "libresoc.v:130491.14-130491.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:128712.3-128735.6" + attribute \src "libresoc.v:131047.3-131070.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:128498.3-128506.6" - wire $1\sto_l_r_sto$next[0:0]$5814 - attribute \src "libresoc.v:128166.7-128166.25" + attribute \src "libresoc.v:130833.3-130841.6" + wire $1\sto_l_r_sto$next[0:0]$6073 + attribute \src "libresoc.v:130501.7-130501.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:128489.3-128497.6" - wire $1\upd_l_r_upd$next[0:0]$5811 - attribute \src "libresoc.v:128176.7-128176.25" + attribute \src "libresoc.v:130824.3-130832.6" + wire $1\upd_l_r_upd$next[0:0]$6070 + attribute \src "libresoc.v:130511.7-130511.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:128480.3-128488.6" - wire $1\upd_l_s_upd$next[0:0]$5808 - attribute \src "libresoc.v:128180.7-128180.25" + attribute \src "libresoc.v:130815.3-130823.6" + wire $1\upd_l_s_upd$next[0:0]$6067 + attribute \src "libresoc.v:130515.7-130515.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:128471.3-128479.6" - wire $1\wri_l_r_wri$next[0:0]$5805 - attribute \src "libresoc.v:128190.7-128190.25" + attribute \src "libresoc.v:130806.3-130814.6" + wire $1\wri_l_r_wri$next[0:0]$6064 + attribute \src "libresoc.v:130525.7-130525.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:128692.3-128711.6" + attribute \src "libresoc.v:131027.3-131046.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:128656.3-128679.6" + attribute \src "libresoc.v:130991.3-131014.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__byte_reverse$next[0:0]$5851 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 4 $2\oper_r__data_len$next[3:0]$5852 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 12 $2\oper_r__fn_unit$next[11:0]$5853 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$5854 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__imm_data__ok$next[0:0]$5855 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 32 $2\oper_r__insn$next[31:0]$5856 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$5857 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__is_32bit$next[0:0]$5858 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__is_signed$next[0:0]$5859 - attribute \src "libresoc.v:128516.3-128558.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$5860 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__oe__oe$next[0:0]$5861 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__oe__ok$next[0:0]$5862 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__rc__ok$next[0:0]$5863 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__rc__rc$next[0:0]$5864 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__sign_extend$next[0:0]$5865 - attribute \src "libresoc.v:128516.3-128558.6" - wire $2\oper_r__zero_a$next[0:0]$5866 - attribute \src "libresoc.v:128569.3-128584.6" - wire width 64 $2\src_r0$next[63:0]$5879 - attribute \src "libresoc.v:128585.3-128600.6" - wire width 64 $2\src_r1$next[63:0]$5883 - attribute \src "libresoc.v:128601.3-128616.6" - wire width 64 $2\src_r2$next[63:0]$5887 - attribute \src "libresoc.v:128712.3-128735.6" + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__byte_reverse$next[0:0]$6110 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6111 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 12 $2\oper_r__fn_unit$next[11:0]$6112 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6113 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6114 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 32 $2\oper_r__insn$next[31:0]$6115 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6116 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__is_32bit$next[0:0]$6117 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__is_signed$next[0:0]$6118 + attribute \src "libresoc.v:130851.3-130893.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6119 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__oe__oe$next[0:0]$6120 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__oe__ok$next[0:0]$6121 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__rc__ok$next[0:0]$6122 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__rc__rc$next[0:0]$6123 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__sign_extend$next[0:0]$6124 + attribute \src "libresoc.v:130851.3-130893.6" + wire $2\oper_r__zero_a$next[0:0]$6125 + attribute \src "libresoc.v:130904.3-130919.6" + wire width 64 $2\src_r0$next[63:0]$6138 + attribute \src "libresoc.v:130920.3-130935.6" + wire width 64 $2\src_r1$next[63:0]$6142 + attribute \src "libresoc.v:130936.3-130951.6" + wire width 64 $2\src_r2$next[63:0]$6146 + attribute \src "libresoc.v:131047.3-131070.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:128516.3-128558.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$5867 - attribute \src "libresoc.v:128516.3-128558.6" - wire $3\oper_r__imm_data__ok$next[0:0]$5868 - attribute \src "libresoc.v:128516.3-128558.6" - wire $3\oper_r__oe__oe$next[0:0]$5869 - attribute \src "libresoc.v:128516.3-128558.6" - wire $3\oper_r__oe__ok$next[0:0]$5870 - attribute \src "libresoc.v:128516.3-128558.6" - wire $3\oper_r__rc__ok$next[0:0]$5871 - attribute \src "libresoc.v:128516.3-128558.6" - wire $3\oper_r__rc__rc$next[0:0]$5872 - attribute \src "libresoc.v:128269.18-128269.124" - wire width 65 $add$libresoc.v:128269$5736_Y - attribute \src "libresoc.v:128196.18-128196.124" - wire $and$libresoc.v:128196$5660_Y - attribute \src "libresoc.v:128197.19-128197.117" - wire $and$libresoc.v:128197$5661_Y - attribute \src "libresoc.v:128198.19-128198.119" - wire $and$libresoc.v:128198$5662_Y - attribute \src "libresoc.v:128199.19-128199.123" - wire $and$libresoc.v:128199$5663_Y - attribute \src "libresoc.v:128200.19-128200.123" - wire $and$libresoc.v:128200$5664_Y - attribute \src "libresoc.v:128201.19-128201.120" - wire $and$libresoc.v:128201$5665_Y - attribute \src "libresoc.v:128202.19-128202.123" - wire $and$libresoc.v:128202$5666_Y - attribute \src "libresoc.v:128203.19-128203.119" - wire $and$libresoc.v:128203$5667_Y - attribute \src "libresoc.v:128204.19-128204.123" - wire $and$libresoc.v:128204$5668_Y - attribute \src "libresoc.v:128205.19-128205.125" - wire $and$libresoc.v:128205$5669_Y - attribute \src "libresoc.v:128208.19-128208.116" - wire $and$libresoc.v:128208$5672_Y - attribute \src "libresoc.v:128209.19-128209.120" - wire $and$libresoc.v:128209$5673_Y - attribute \src "libresoc.v:128210.19-128210.123" - wire $and$libresoc.v:128210$5674_Y - attribute \src "libresoc.v:128214.19-128214.125" - wire $and$libresoc.v:128214$5678_Y - attribute \src "libresoc.v:128215.19-128215.123" - wire $and$libresoc.v:128215$5679_Y - attribute \src "libresoc.v:128220.19-128220.116" - wire $and$libresoc.v:128220$5684_Y - attribute \src "libresoc.v:128222.19-128222.116" - wire $and$libresoc.v:128222$5686_Y - attribute \src "libresoc.v:128225.19-128225.118" - wire $and$libresoc.v:128225$5689_Y - attribute \src "libresoc.v:128227.19-128227.125" - wire $and$libresoc.v:128227$5691_Y - attribute \src "libresoc.v:128230.19-128230.160" - wire width 3 $and$libresoc.v:128230$5694_Y - attribute \src "libresoc.v:128231.19-128231.122" - wire $and$libresoc.v:128231$5695_Y - attribute \src "libresoc.v:128232.19-128232.122" - wire $and$libresoc.v:128232$5696_Y - attribute \src "libresoc.v:128234.19-128234.122" - wire $and$libresoc.v:128234$5699_Y - attribute \src "libresoc.v:128244.18-128244.123" - wire $and$libresoc.v:128244$5711_Y - attribute \src "libresoc.v:128245.18-128245.123" - wire $and$libresoc.v:128245$5712_Y - attribute \src "libresoc.v:128247.18-128247.114" - wire $and$libresoc.v:128247$5714_Y - attribute \src "libresoc.v:128249.18-128249.113" - wire $and$libresoc.v:128249$5716_Y - attribute \src "libresoc.v:128252.18-128252.113" - wire $and$libresoc.v:128252$5719_Y - attribute \src "libresoc.v:128257.18-128257.113" - wire $and$libresoc.v:128257$5724_Y - attribute \src "libresoc.v:128260.18-128260.119" - wire $and$libresoc.v:128260$5727_Y - attribute \src "libresoc.v:128270.18-128270.150" - wire width 3 $and$libresoc.v:128270$5737_Y - attribute \src "libresoc.v:128272.18-128272.113" - wire width 3 $and$libresoc.v:128272$5739_Y - attribute \src "libresoc.v:128274.18-128274.113" - wire width 3 $and$libresoc.v:128274$5741_Y - attribute \src "libresoc.v:128276.18-128276.127" - wire $and$libresoc.v:128276$5743_Y - attribute \src "libresoc.v:128277.18-128277.117" - wire $and$libresoc.v:128277$5744_Y - attribute \src "libresoc.v:128281.18-128281.117" - wire $and$libresoc.v:128281$5748_Y - attribute \src "libresoc.v:128283.18-128283.117" - wire $and$libresoc.v:128283$5750_Y - attribute \src "libresoc.v:128284.18-128284.124" - wire $and$libresoc.v:128284$5751_Y - attribute \src "libresoc.v:128285.18-128285.118" - wire $and$libresoc.v:128285$5752_Y - attribute \src "libresoc.v:128207.19-128207.127" - wire $eq$libresoc.v:128207$5671_Y - attribute \src "libresoc.v:128226.19-128226.127" - wire $eq$libresoc.v:128226$5690_Y - attribute \src "libresoc.v:128228.18-128228.127" - wire $eq$libresoc.v:128228$5692_Y - attribute \src "libresoc.v:128229.19-128229.127" - wire $eq$libresoc.v:128229$5693_Y - attribute \src "libresoc.v:128238.19-128238.126" - wire $eq$libresoc.v:128238$5704_Y - attribute \src "libresoc.v:128239.18-128239.127" - wire $eq$libresoc.v:128239$5705_Y - attribute \src "libresoc.v:128251.18-128251.126" - wire $eq$libresoc.v:128251$5718_Y - attribute \src "libresoc.v:128256.18-128256.126" - wire $eq$libresoc.v:128256$5723_Y - attribute \src "libresoc.v:128233.19-128233.110" - wire width 96 $extend$libresoc.v:128233$5697_Y - attribute \src "libresoc.v:128235.19-128235.116" - wire width 64 $extend$libresoc.v:128235$5700_Y - attribute \src "libresoc.v:128240.19-128240.102" - wire width 64 $extend$libresoc.v:128240$5706_Y - attribute \src "libresoc.v:128219.19-128219.109" - wire $not$libresoc.v:128219$5683_Y - attribute \src "libresoc.v:128223.19-128223.121" - wire $not$libresoc.v:128223$5687_Y - attribute \src "libresoc.v:128246.18-128246.112" - wire $not$libresoc.v:128246$5713_Y - attribute \src "libresoc.v:128248.18-128248.110" - wire $not$libresoc.v:128248$5715_Y - attribute \src "libresoc.v:128250.18-128250.120" - wire $not$libresoc.v:128250$5717_Y - attribute \src "libresoc.v:128255.18-128255.120" - wire $not$libresoc.v:128255$5722_Y - attribute \src "libresoc.v:128271.18-128271.143" - wire width 2 $not$libresoc.v:128271$5738_Y - attribute \src "libresoc.v:128273.18-128273.115" - wire width 3 $not$libresoc.v:128273$5740_Y - attribute \src "libresoc.v:128280.18-128280.107" - wire $not$libresoc.v:128280$5747_Y - attribute \src "libresoc.v:128282.18-128282.118" - wire $not$libresoc.v:128282$5749_Y - attribute \src "libresoc.v:128195.17-128195.125" - wire $or$libresoc.v:128195$5659_Y - attribute \src "libresoc.v:128206.18-128206.156" - wire width 3 $or$libresoc.v:128206$5670_Y - attribute \src "libresoc.v:128211.19-128211.123" - wire $or$libresoc.v:128211$5675_Y - attribute \src "libresoc.v:128212.19-128212.125" - wire $or$libresoc.v:128212$5676_Y - attribute \src "libresoc.v:128213.19-128213.125" - wire $or$libresoc.v:128213$5677_Y - attribute \src "libresoc.v:128216.19-128216.132" - wire $or$libresoc.v:128216$5680_Y - attribute \src "libresoc.v:128217.18-128217.126" - wire $or$libresoc.v:128217$5681_Y - attribute \src "libresoc.v:128218.19-128218.126" - wire $or$libresoc.v:128218$5682_Y - attribute \src "libresoc.v:128221.19-128221.125" - wire $or$libresoc.v:128221$5685_Y - attribute \src "libresoc.v:128224.19-128224.119" - wire $or$libresoc.v:128224$5688_Y - attribute \src "libresoc.v:128243.17-128243.124" - wire $or$libresoc.v:128243$5710_Y - attribute \src "libresoc.v:128253.18-128253.116" - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - wire \$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - wire width 3 \$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + wire \$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" + wire \$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" + wire \$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + wire \$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + wire \$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - wire width 3 \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + wire \$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" wire \$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" + wire width 3 \$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" + wire width 3 \$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - wire width 96 \$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" - wire \$170 + wire \$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + wire width 96 \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + wire width 3 \$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$172 + wire width 64 \$186 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$174 + wire width 64 \$188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - wire \$178 + wire width 64 \$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + wire \$192 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$180 + wire width 64 \$194 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$182 + wire width 64 \$196 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 \$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" - wire \$19 + wire width 64 \$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - wire width 2 \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - wire width 2 \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" - wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" + wire width 2 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" + wire width 2 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - wire \$56 + wire \$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + wire \$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$58 + wire width 64 \$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - wire width 64 \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 64 \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - wire width 65 \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - wire width 65 \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 2 \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire width 64 \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + wire width 64 \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + wire width 64 \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" + wire width 65 \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" + wire width 65 \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + wire width 3 \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + wire width 2 \$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + wire width 3 \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + wire width 3 \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + wire width 3 \$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" + wire \$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + wire \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + wire \$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:107" - wire \addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + wire \$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" + wire \$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" wire \addr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" wire width 64 \addr_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \adr_l_q_adr @@ -203595,67 +208938,83 @@ module \ldst0 wire \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" wire width 64 \alu_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" wire \alu_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" wire \alu_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 46 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 33 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 2 \cu_ad__go_i + wire input 3 \cu_ad__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 3 \cu_ad__rel_o + wire output 4 \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 22 \cu_busy_o + wire output 23 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 21 \cu_issue_i + wire input 22 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 25 \cu_rd__go_i + wire width 3 input 26 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 24 \cu_rd__rel_o + wire width 3 output 25 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 23 \cu_rdmaskn_i + wire width 3 input 24 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 4 \cu_st__go_i + wire input 5 \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 1 \cu_st__rel_o + wire output 2 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 30 \cu_wr__go_i + wire width 2 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 29 \cu_wr__rel_o + wire width 2 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 2 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 64 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 33 \ea attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \ea_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \ea_r$next - attribute \src "libresoc.v:127479.7-127479.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$185 + attribute \src "libresoc.v:129786.7-129786.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" wire \ld_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" wire width 64 \ldd_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" wire width 64 \lddata_r @@ -203663,35 +209022,49 @@ module \ldst0 wire width 64 \ldo_r attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 40 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \ldst_port0_addr_i_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 41 \ldst_port0_addr_ok_o + wire input 48 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" wire input 34 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 output 37 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 40 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 41 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 42 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 43 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 44 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 45 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 46 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 47 \ldst_port0_exc_$signal$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire output 35 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 42 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 43 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 45 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 49 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 50 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 51 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" wire \load_mem_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" wire \lod_l_qn_lod @@ -203707,11 +209080,11 @@ module \ldst0 wire \lsd_l_r_lsd$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" - wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" wire \op_is_st attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc @@ -203724,9 +209097,9 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_ldst_ldst0__byte_reverse + wire input 18 \oper_i_ldst_ldst0__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 16 \oper_i_ldst_ldst0__data_len + wire width 4 input 17 \oper_i_ldst_ldst0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -203741,13 +209114,13 @@ module \ldst0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \oper_i_ldst_ldst0__fn_unit + wire width 12 input 7 \oper_i_ldst_ldst0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data + wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_ldst_ldst0__imm_data__ok + wire input 9 \oper_i_ldst_ldst0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 20 \oper_i_ldst_ldst0__insn + wire width 32 input 21 \oper_i_ldst_ldst0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -203823,30 +209196,30 @@ module \ldst0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \oper_i_ldst_ldst0__insn_type + wire width 7 input 6 \oper_i_ldst_ldst0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_ldst_ldst0__is_32bit + wire input 15 \oper_i_ldst_ldst0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_ldst_ldst0__is_signed + wire input 16 \oper_i_ldst_ldst0__is_signed attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode + wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_ldst_ldst0__oe__oe + wire input 13 \oper_i_ldst_ldst0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_ldst_ldst0__oe__ok + wire input 14 \oper_i_ldst_ldst0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_ldst_ldst0__rc__ok + wire input 12 \oper_i_ldst_ldst0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_ldst_ldst0__rc__rc + wire input 11 \oper_i_ldst_ldst0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \oper_i_ldst_ldst0__sign_extend + wire input 19 \oper_i_ldst_ldst0__sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_ldst_ldst0__zero_a + wire input 10 \oper_i_ldst_ldst0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -204003,29 +209376,29 @@ module \ldst0 wire \oper_r__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \oper_r__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" wire \p_st_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" wire \p_st_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" wire \rd_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" wire \rda_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" - wire \reset_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" + wire \reset_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" wire \reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" wire \reset_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" - wire width 3 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" wire \reset_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" wire \reset_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" wire \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" wire width 64 \revnorev attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \rst_l_q_rst @@ -204034,15 +209407,15 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:404" + wire width 64 input 27 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" wire width 64 \src1_or_z attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 27 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:409" + wire width 64 input 28 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" wire width 64 \src2_or_imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 28 \src3_i + wire width 64 input 29 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -204053,19 +209426,19 @@ module \ldst0 wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" wire \st_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" wire width 64 \stdata_r @@ -204077,7 +209450,7 @@ module \ldst0 wire \sto_l_r_sto$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \sto_l_s_sto - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" wire \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \upd_l_q_upd @@ -204089,9 +209462,9 @@ module \ldst0 wire \upd_l_s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \upd_l_s_upd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" wire \wr_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \wri_l_q_wri @@ -204101,8 +209474,8 @@ module \ldst0 wire \wri_l_r_wri$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \wri_l_s_wri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - cell $add $add$libresoc.v:128269$5736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" + cell $add $add$libresoc.v:130607$5998 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -204110,10 +209483,43 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:128269$5736_Y + connect \Y $add$libresoc.v:130607$5998_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$libresoc.v:128196$5660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" + cell $and $and$libresoc.v:130530$5918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \$98 + connect \Y $and$libresoc.v:130530$5918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" + cell $and $and$libresoc.v:130531$5919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \adr_l_q_adr + connect \Y $and$libresoc.v:130531$5919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" + cell $and $and$libresoc.v:130532$5920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$102 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130532$5920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130533$5921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204121,43 +209527,43 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:128196$5660_Y + connect \Y $and$libresoc.v:130533$5921_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$libresoc.v:128197$5661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130534$5922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$99 + connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:128197$5661_Y + connect \Y $and$libresoc.v:130534$5922_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $and$libresoc.v:128198$5662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:130536$5924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$101 + connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:128198$5662_Y + connect \Y $and$libresoc.v:130536$5924_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:128199$5663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" + cell $and $and$libresoc.v:130537$5925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$103 + connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128199$5663_Y + connect \Y $and$libresoc.v:130537$5925_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$libresoc.v:128200$5664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130538$5926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204165,54 +209571,54 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:128200$5664_Y + connect \Y $and$libresoc.v:130538$5926_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$libresoc.v:128201$5665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130539$5927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$107 + connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:128201$5665_Y + connect \Y $and$libresoc.v:130539$5927_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$libresoc.v:128202$5666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130540$5928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$109 + connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:128202$5666_Y + connect \Y $and$libresoc.v:130540$5928_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$libresoc.v:128203$5667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130541$5929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$111 + connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:128203$5667_Y + connect \Y $and$libresoc.v:130541$5929_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $and$libresoc.v:128204$5668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" + cell $and $and$libresoc.v:130542$5930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$113 + connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128204$5668_Y + connect \Y $and$libresoc.v:130542$5930_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $and$libresoc.v:128205$5669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:130543$5931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204220,43 +209626,43 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:128205$5669_Y + connect \Y $and$libresoc.v:130543$5931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $and$libresoc.v:128208$5672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:130545$5933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$117 - connect \B \$119 - connect \Y $and$libresoc.v:128208$5672_Y + connect \A \$124 + connect \B \$126 + connect \Y $and$libresoc.v:130545$5933_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $and$libresoc.v:128209$5673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:130547$5935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$121 + connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:128209$5673_Y + connect \Y $and$libresoc.v:130547$5935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $and$libresoc.v:128210$5674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:130548$5936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$123 + connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128210$5674_Y + connect \Y $and$libresoc.v:130548$5936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $and$libresoc.v:128214$5678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130552$5940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204264,76 +209670,76 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:128214$5678_Y + connect \Y $and$libresoc.v:130552$5940_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $and$libresoc.v:128215$5679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130553$5941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$133 + connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:128215$5679_Y + connect \Y $and$libresoc.v:130553$5941_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $and$libresoc.v:128220$5684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:130558$5946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$135 - connect \B \$137 - connect \Y $and$libresoc.v:128220$5684_Y + connect \A \$142 + connect \B \$144 + connect \Y $and$libresoc.v:130558$5946_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:128222$5686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" + cell $and $and$libresoc.v:130560$5948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$143 - connect \B \$145 - connect \Y $and$libresoc.v:128222$5686_Y + connect \A \$150 + connect \B \$152 + connect \Y $and$libresoc.v:130560$5948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $and $and$libresoc.v:128225$5689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $and $and$libresoc.v:130563$5951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_reset - connect \B \$151 - connect \Y $and$libresoc.v:128225$5689_Y + connect \B \$158 + connect \Y $and$libresoc.v:130563$5951_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - cell $and $and$libresoc.v:128227$5691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + cell $and $and$libresoc.v:130565$5953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$155 + connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:128227$5691_Y + connect \Y $and$libresoc.v:130565$5953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - cell $and $and$libresoc.v:128230$5694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" + cell $and $and$libresoc.v:130568$5956 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \B { 1'0 \$160 \op_is_ld } - connect \Y $and$libresoc.v:128230$5694_Y + connect \B { 1'0 \$167 \op_is_ld } + connect \Y $and$libresoc.v:130568$5956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" - cell $and $and$libresoc.v:128231$5695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + cell $and $and$libresoc.v:130569$5957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204341,10 +209747,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:128231$5695_Y + connect \Y $and$libresoc.v:130569$5957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:128232$5696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" + cell $and $and$libresoc.v:130570$5958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204352,10 +209758,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:128232$5696_Y + connect \Y $and$libresoc.v:130570$5958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" - cell $and $and$libresoc.v:128234$5699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" + cell $and $and$libresoc.v:130572$5961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204363,10 +209769,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:128234$5699_Y + connect \Y $and$libresoc.v:130572$5961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" - cell $and $and$libresoc.v:128244$5711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" + cell $and $and$libresoc.v:130584$5975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204374,10 +209780,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:128244$5711_Y + connect \Y $and$libresoc.v:130584$5975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:128245$5712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" + cell $and $and$libresoc.v:130585$5976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204385,54 +209791,54 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:128245$5712_Y + connect \Y $and$libresoc.v:130585$5976_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $and $and$libresoc.v:128247$5714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $and $and$libresoc.v:130587$5978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_ok - connect \B \$23 - connect \Y $and$libresoc.v:128247$5714_Y + connect \B \$30 + connect \Y $and$libresoc.v:130587$5978_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $and $and$libresoc.v:128249$5716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $and $and$libresoc.v:130589$5980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \$27 - connect \Y $and$libresoc.v:128249$5716_Y + connect \A \$32 + connect \B \$34 + connect \Y $and$libresoc.v:130589$5980_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $and $and$libresoc.v:128252$5719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $and $and$libresoc.v:130592$5983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $and$libresoc.v:128252$5719_Y + connect \A \$39 + connect \B \$41 + connect \Y $and$libresoc.v:130592$5983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $and $and$libresoc.v:128257$5724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $and $and$libresoc.v:130596$5987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$40 - connect \B \$42 - connect \Y $and$libresoc.v:128257$5724_Y + connect \A \$47 + connect \B \$49 + connect \Y $and$libresoc.v:130596$5987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" - cell $and $and$libresoc.v:128260$5727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + cell $and $and$libresoc.v:130599$5990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204440,10 +209846,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:128260$5727_Y + connect \Y $and$libresoc.v:130599$5990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $and$libresoc.v:128270$5737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130608$5999 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -204451,32 +209857,32 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:128270$5737_Y + connect \Y $and$libresoc.v:130608$5999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $and$libresoc.v:128272$5739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130610$6001 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 3 - connect \A \$69 - connect \B \$71 - connect \Y $and$libresoc.v:128272$5739_Y + connect \A \$76 + connect \B \$78 + connect \Y $and$libresoc.v:130610$6001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $and$libresoc.v:128274$5741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $and $and$libresoc.v:130612$6003 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A \$73 - connect \B \$75 - connect \Y $and$libresoc.v:128274$5741_Y + connect \A \$80 + connect \B \$82 + connect \Y $and$libresoc.v:130612$6003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $and$libresoc.v:128276$5743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" + cell $and $and$libresoc.v:130613$6004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204484,65 +209890,32 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:128276$5743_Y + connect \Y $and$libresoc.v:130613$6004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $and$libresoc.v:128277$5744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" + cell $and $and$libresoc.v:130614$6005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$79 + connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:128277$5744_Y + connect \Y $and$libresoc.v:130614$6005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $and$libresoc.v:128281$5748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $and $and$libresoc.v:130619$6010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o - connect \B \$85 - connect \Y $and$libresoc.v:128281$5748_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $and$libresoc.v:128283$5750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \$91 - connect \Y $and$libresoc.v:128283$5750_Y + connect \B \$92 + connect \Y $and$libresoc.v:130619$6010_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $and$libresoc.v:128284$5751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:128284$5751_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $and$libresoc.v:128285$5752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$95 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:128285$5752_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:128207$5671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130544$5932 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204550,10 +209923,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:128207$5671_Y + connect \Y $eq$libresoc.v:130544$5932_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:128226$5690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130564$5952 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204561,21 +209934,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:128226$5690_Y + connect \Y $eq$libresoc.v:130564$5952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" - cell $eq $eq$libresoc.v:128228$5692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100110 - connect \Y $eq$libresoc.v:128228$5692_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:128229$5693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130566$5954 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204583,10 +209945,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:128229$5693_Y + connect \Y $eq$libresoc.v:130566$5954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - cell $eq $eq$libresoc.v:128238$5704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + cell $eq $eq$libresoc.v:130577$5967 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -204594,21 +209956,32 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:128238$5704_Y + connect \Y $eq$libresoc.v:130577$5967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:128239$5705 + cell $eq $eq$libresoc.v:130582$5973 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type - connect \B 7'0100101 - connect \Y $eq$libresoc.v:128239$5705_Y + connect \B 7'0100110 + connect \Y $eq$libresoc.v:130582$5973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:128251$5718 + cell $eq $eq$libresoc.v:130583$5974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100101 + connect \Y $eq$libresoc.v:130583$5974_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130591$5982 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204616,10 +209989,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:128251$5718_Y + connect \Y $eq$libresoc.v:130591$5982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:128256$5723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" + cell $eq $eq$libresoc.v:130595$5986 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -204627,136 +210000,136 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:128256$5723_Y + connect \Y $eq$libresoc.v:130595$5986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - cell $pos $extend$libresoc.v:128233$5697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $extend$libresoc.v:130571$5959 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:128233$5697_Y + connect \Y $extend$libresoc.v:130571$5959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$libresoc.v:128235$5700 + cell $pos $extend$libresoc.v:130573$5962 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:128235$5700_Y + connect \Y $extend$libresoc.v:130573$5962_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $extend$libresoc.v:128240$5706 + cell $pos $extend$libresoc.v:130578$5968 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:128240$5706_Y + connect \Y $extend$libresoc.v:130578$5968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $not $not$libresoc.v:128219$5683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $not $not$libresoc.v:130556$5944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$140 - connect \Y $not$libresoc.v:128219$5683_Y + connect \A \$147 + connect \Y $not$libresoc.v:130556$5944_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $not $not$libresoc.v:128223$5687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $not $not$libresoc.v:130561$5949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:128223$5687_Y + connect \Y $not$libresoc.v:130561$5949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $not$libresoc.v:128246$5713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $not $not$libresoc.v:130586$5977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:128246$5713_Y + connect \Y $not$libresoc.v:130586$5977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $not$libresoc.v:128248$5715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" + cell $not $not$libresoc.v:130588$5979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:128248$5715_Y + connect \Y $not$libresoc.v:130588$5979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $not$libresoc.v:128250$5717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $not $not$libresoc.v:130590$5981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:128250$5717_Y + connect \Y $not$libresoc.v:130590$5981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $not$libresoc.v:128255$5722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $not $not$libresoc.v:130594$5985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:128255$5722_Y + connect \Y $not$libresoc.v:130594$5985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $not$libresoc.v:128271$5738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $not $not$libresoc.v:130609$6000 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:128271$5738_Y + connect \Y $not$libresoc.v:130609$6000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $not$libresoc.v:128273$5740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" + cell $not $not$libresoc.v:130611$6002 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:128273$5740_Y + connect \Y $not$libresoc.v:130611$6002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $not $not$libresoc.v:128280$5747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $not $not$libresoc.v:130618$6009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$86 - connect \Y $not$libresoc.v:128280$5747_Y + connect \A \$93 + connect \Y $not$libresoc.v:130618$6009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $not $not$libresoc.v:128282$5749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" + cell $not $not$libresoc.v:130620$6011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:128282$5749_Y + connect \Y $not$libresoc.v:130620$6011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:128195$5659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + cell $or $or$libresoc.v:130535$5923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__go_i + connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128195$5659_Y + connect \Y $or$libresoc.v:130535$5923_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:128206$5670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + cell $or $or$libresoc.v:130546$5934 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:128206$5670_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130546$5934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$libresoc.v:128211$5675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130549$5937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204764,32 +210137,32 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:128211$5675_Y + connect \Y $or$libresoc.v:130549$5937_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$libresoc.v:128212$5676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130550$5938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$127 + connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:128212$5676_Y + connect \Y $or$libresoc.v:130550$5938_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $or$libresoc.v:128213$5677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" + cell $or $or$libresoc.v:130551$5939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$129 + connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:128213$5677_Y + connect \Y $or$libresoc.v:130551$5939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $or$libresoc.v:128216$5680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$libresoc.v:130554$5942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204797,32 +210170,32 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:128216$5680_Y + connect \Y $or$libresoc.v:130554$5942_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:128217$5681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$libresoc.v:130555$5943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_ad__go_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128217$5681_Y + connect \A \$145 + connect \B \cu_wr__rel_o [1] + connect \Y $or$libresoc.v:130555$5943_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $or$libresoc.v:128218$5682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + cell $or $or$libresoc.v:130557$5945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$138 - connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:128218$5682_Y + connect \A \cu_wr__go_i [1] + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130557$5945_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:128221$5685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" + cell $or $or$libresoc.v:130559$5947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204830,76 +210203,87 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:128221$5685_Y + connect \Y $or$libresoc.v:130559$5947_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $or $or$libresoc.v:128224$5688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $or $or$libresoc.v:130562$5950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$149 + connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:128224$5688_Y + connect \Y $or$libresoc.v:130562$5950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - cell $or $or$libresoc.v:128243$5710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + cell $or $or$libresoc.v:130567$5955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i + connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128243$5710_Y + connect \Y $or$libresoc.v:130567$5955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + cell $or $or$libresoc.v:130575$5965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130575$5965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $or$libresoc.v:128253$5720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" + cell $or $or$libresoc.v:130581$5972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$36 - connect \Y $or$libresoc.v:128253$5720_Y + connect \A \cu_ad__go_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130581$5972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:128254$5721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:130593$5984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_done_o - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128254$5721_Y + connect \A \wr_reset + connect \B \$43 + connect \Y $or$libresoc.v:130593$5984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $or$libresoc.v:128258$5725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:130597$5988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_reset - connect \B \$44 - connect \Y $or$libresoc.v:128258$5725_Y + connect \B \$51 + connect \Y $or$libresoc.v:130597$5988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - cell $or $or$libresoc.v:128259$5726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" + cell $or $or$libresoc.v:130598$5989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reset_w - connect \B { \$38 \$46 } - connect \Y $or$libresoc.v:128259$5726_Y + connect \B { \$45 \$53 } + connect \Y $or$libresoc.v:130598$5989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $or $or$libresoc.v:128261$5728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" + cell $or $or$libresoc.v:130600$5991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204907,10 +210291,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:128261$5728_Y + connect \Y $or$libresoc.v:130600$5991_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $or$libresoc.v:128262$5729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:130601$5992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204918,43 +210302,32 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:128262$5729_Y + connect \Y $or$libresoc.v:130601$5992_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $or$libresoc.v:128263$5730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:130602$5993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$54 + connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:128263$5730_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:128265$5732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128265$5732_Y + connect \Y $or$libresoc.v:130602$5993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:128275$5742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$libresoc.v:130615$6006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] + connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:128275$5742_Y + connect \Y $or$libresoc.v:130615$6006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" - cell $or $or$libresoc.v:128278$5745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + cell $or $or$libresoc.v:130616$6007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204962,10 +210335,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:128278$5745_Y + connect \Y $or$libresoc.v:130616$6007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $or $or$libresoc.v:128279$5746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $or $or$libresoc.v:130617$6008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -204973,98 +210346,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:128279$5746_Y + connect \Y $or$libresoc.v:130617$6008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - cell $pos $pos$libresoc.v:128233$5698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $pos$libresoc.v:130571$5960 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:128233$5697_Y - connect \Y $pos$libresoc.v:128233$5698_Y + connect \A $extend$libresoc.v:130571$5959_Y + connect \Y $pos$libresoc.v:130571$5960_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128235$5701 + cell $pos $pos$libresoc.v:130573$5963 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128235$5700_Y - connect \Y $pos$libresoc.v:128235$5701_Y + connect \A $extend$libresoc.v:130573$5962_Y + connect \Y $pos$libresoc.v:130573$5963_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128236$5702 + cell $pos $pos$libresoc.v:130574$5964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:128236$5702_Y + connect \Y $pos$libresoc.v:130574$5964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128237$5703 + cell $pos $pos$libresoc.v:130576$5966 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:128237$5703_Y + connect \Y $pos$libresoc.v:130576$5966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128240$5707 + cell $pos $pos$libresoc.v:130578$5969 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128240$5706_Y - connect \Y $pos$libresoc.v:128240$5707_Y + connect \A $extend$libresoc.v:130578$5968_Y + connect \Y $pos$libresoc.v:130578$5969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128241$5708 + cell $pos $pos$libresoc.v:130579$5970 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:128241$5708_Y + connect \Y $pos$libresoc.v:130579$5970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:128242$5709 + cell $pos $pos$libresoc.v:130580$5971 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:128242$5709_Y + connect \Y $pos$libresoc.v:130580$5971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:128264$5731 + cell $mux $ternary$libresoc.v:130603$5994 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:128264$5731_Y + connect \Y $ternary$libresoc.v:130603$5994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:128266$5733 + cell $mux $ternary$libresoc.v:130604$5995 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:128266$5733_Y + connect \Y $ternary$libresoc.v:130604$5995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - cell $mux $ternary$libresoc.v:128267$5734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + cell $mux $ternary$libresoc.v:130605$5996 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:128267$5734_Y + connect \Y $ternary$libresoc.v:130605$5996_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $mux $ternary$libresoc.v:128268$5735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + cell $mux $ternary$libresoc.v:130606$5997 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:128268$5735_Y + connect \Y $ternary$libresoc.v:130606$5997_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:128356.9-128362.4" + attribute \src "libresoc.v:130691.9-130697.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205073,8 +210446,8 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:128363.15-128369.4" - cell \alu_l$125 \alu_l + attribute \src "libresoc.v:130698.15-130704.4" + cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -205082,7 +210455,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:128370.9-128376.4" + attribute \src "libresoc.v:130705.9-130711.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205091,7 +210464,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:128377.9-128383.4" + attribute \src "libresoc.v:130712.9-130718.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205100,8 +210473,8 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:128384.15-128390.4" - cell \opc_l$123 \opc_l + attribute \src "libresoc.v:130719.15-130725.4" + cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -205109,8 +210482,8 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:128391.15-128397.4" - cell \rst_l$126 \rst_l + attribute \src "libresoc.v:130726.15-130732.4" + cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rst \rst_l_q_rst @@ -205118,8 +210491,8 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:128398.15-128404.4" - cell \src_l$124 \src_l + attribute \src "libresoc.v:130733.15-130739.4" + cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src @@ -205127,7 +210500,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:128405.9-128411.4" + attribute \src "libresoc.v:130740.9-130746.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205136,7 +210509,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:128412.9-128418.4" + attribute \src "libresoc.v:130747.9-130753.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205145,7 +210518,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:128419.9-128425.4" + attribute \src "libresoc.v:130754.9-130760.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -205153,547 +210526,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:127479.7-127479.20" - process $proc$libresoc.v:127479$5901 + attribute \src "libresoc.v:129786.7-129786.20" + process $proc$libresoc.v:129786$6160 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127677.7-127677.25" - process $proc$libresoc.v:127677$5902 + attribute \src "libresoc.v:129982.7-129982.25" + process $proc$libresoc.v:129982$6161 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:127691.7-127691.20" - process $proc$libresoc.v:127691$5903 + attribute \src "libresoc.v:129996.7-129996.20" + process $proc$libresoc.v:129996$6162 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:127737.14-127737.41" - process $proc$libresoc.v:127737$5904 + attribute \src "libresoc.v:130042.14-130042.41" + process $proc$libresoc.v:130042$6163 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:127751.14-127751.42" - process $proc$libresoc.v:127751$5905 + attribute \src "libresoc.v:130072.14-130072.42" + process $proc$libresoc.v:130072$6164 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:127758.14-127758.62" - process $proc$libresoc.v:127758$5906 + attribute \src "libresoc.v:130077.14-130077.62" + process $proc$libresoc.v:130077$6165 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:127763.7-127763.34" - process $proc$libresoc.v:127763$5907 + attribute \src "libresoc.v:130082.7-130082.34" + process $proc$libresoc.v:130082$6166 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:127796.7-127796.25" - process $proc$libresoc.v:127796$5908 + attribute \src "libresoc.v:130131.7-130131.25" + process $proc$libresoc.v:130131$6167 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:127810.7-127810.25" - process $proc$libresoc.v:127810$5909 + attribute \src "libresoc.v:130145.7-130145.25" + process $proc$libresoc.v:130145$6168 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:127814.7-127814.25" - process $proc$libresoc.v:127814$5910 + attribute \src "libresoc.v:130149.7-130149.25" + process $proc$libresoc.v:130149$6169 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:127942.7-127942.34" - process $proc$libresoc.v:127942$5911 + attribute \src "libresoc.v:130277.7-130277.34" + process $proc$libresoc.v:130277$6170 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:127946.13-127946.36" - process $proc$libresoc.v:127946$5912 + attribute \src "libresoc.v:130281.13-130281.36" + process $proc$libresoc.v:130281$6171 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:127963.14-127963.39" - process $proc$libresoc.v:127963$5913 + attribute \src "libresoc.v:130298.14-130298.39" + process $proc$libresoc.v:130298$6172 assign { } { } assign $1\oper_r__fn_unit[11:0] 12'000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] end - attribute \src "libresoc.v:127967.14-127967.59" - process $proc$libresoc.v:127967$5914 + attribute \src "libresoc.v:130302.14-130302.59" + process $proc$libresoc.v:130302$6173 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:127971.7-127971.34" - process $proc$libresoc.v:127971$5915 + attribute \src "libresoc.v:130306.7-130306.34" + process $proc$libresoc.v:130306$6174 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:127975.14-127975.34" - process $proc$libresoc.v:127975$5916 + attribute \src "libresoc.v:130310.14-130310.34" + process $proc$libresoc.v:130310$6175 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:128053.13-128053.38" - process $proc$libresoc.v:128053$5917 + attribute \src "libresoc.v:130388.13-130388.38" + process $proc$libresoc.v:130388$6176 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:128057.7-128057.30" - process $proc$libresoc.v:128057$5918 + attribute \src "libresoc.v:130392.7-130392.30" + process $proc$libresoc.v:130392$6177 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:128061.7-128061.31" - process $proc$libresoc.v:128061$5919 + attribute \src "libresoc.v:130396.7-130396.31" + process $proc$libresoc.v:130396$6178 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:128070.13-128070.37" - process $proc$libresoc.v:128070$5920 + attribute \src "libresoc.v:130405.13-130405.37" + process $proc$libresoc.v:130405$6179 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:128074.7-128074.28" - process $proc$libresoc.v:128074$5921 + attribute \src "libresoc.v:130409.7-130409.28" + process $proc$libresoc.v:130409$6180 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:128078.7-128078.28" - process $proc$libresoc.v:128078$5922 + attribute \src "libresoc.v:130413.7-130413.28" + process $proc$libresoc.v:130413$6181 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:128082.7-128082.28" - process $proc$libresoc.v:128082$5923 + attribute \src "libresoc.v:130417.7-130417.28" + process $proc$libresoc.v:130417$6182 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:128086.7-128086.28" - process $proc$libresoc.v:128086$5924 + attribute \src "libresoc.v:130421.7-130421.28" + process $proc$libresoc.v:130421$6183 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:128090.7-128090.33" - process $proc$libresoc.v:128090$5925 + attribute \src "libresoc.v:130425.7-130425.33" + process $proc$libresoc.v:130425$6184 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:128094.7-128094.28" - process $proc$libresoc.v:128094$5926 + attribute \src "libresoc.v:130429.7-130429.28" + process $proc$libresoc.v:130429$6185 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:128098.7-128098.21" - process $proc$libresoc.v:128098$5927 + attribute \src "libresoc.v:130433.7-130433.21" + process $proc$libresoc.v:130433$6186 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:128140.13-128140.31" - process $proc$libresoc.v:128140$5928 + attribute \src "libresoc.v:130475.13-130475.31" + process $proc$libresoc.v:130475$6187 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:128144.13-128144.31" - process $proc$libresoc.v:128144$5929 + attribute \src "libresoc.v:130479.13-130479.31" + process $proc$libresoc.v:130479$6188 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:128148.14-128148.43" - process $proc$libresoc.v:128148$5930 + attribute \src "libresoc.v:130483.14-130483.43" + process $proc$libresoc.v:130483$6189 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:128152.14-128152.43" - process $proc$libresoc.v:128152$5931 + attribute \src "libresoc.v:130487.14-130487.43" + process $proc$libresoc.v:130487$6190 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:128156.14-128156.43" - process $proc$libresoc.v:128156$5932 + attribute \src "libresoc.v:130491.14-130491.43" + process $proc$libresoc.v:130491$6191 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:128166.7-128166.25" - process $proc$libresoc.v:128166$5933 + attribute \src "libresoc.v:130501.7-130501.25" + process $proc$libresoc.v:130501$6192 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:128176.7-128176.25" - process $proc$libresoc.v:128176$5934 + attribute \src "libresoc.v:130511.7-130511.25" + process $proc$libresoc.v:130511$6193 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:128180.7-128180.25" - process $proc$libresoc.v:128180$5935 + attribute \src "libresoc.v:130515.7-130515.25" + process $proc$libresoc.v:130515$6194 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:128190.7-128190.25" - process $proc$libresoc.v:128190$5936 + attribute \src "libresoc.v:130525.7-130525.25" + process $proc$libresoc.v:130525$6195 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:128286.3-128287.57" - process $proc$libresoc.v:128286$5753 + attribute \src "libresoc.v:130621.3-130622.57" + process $proc$libresoc.v:130621$6012 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:128288.3-128289.33" - process $proc$libresoc.v:128288$5754 + attribute \src "libresoc.v:130623.3-130624.33" + process $proc$libresoc.v:130623$6013 assign { } { } - assign $0\ldst_port0_addr_i[95:0] \$168 + assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:128290.3-128291.21" - process $proc$libresoc.v:128290$5755 + attribute \src "libresoc.v:130625.3-130626.21" + process $proc$libresoc.v:130625$6014 assign { } { } - assign $0\alu_ok[0:0] \$89 + assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:128292.3-128293.25" - process $proc$libresoc.v:128292$5756 + attribute \src "libresoc.v:130627.3-130628.25" + process $proc$libresoc.v:130627$6015 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:128294.3-128295.29" - process $proc$libresoc.v:128294$5757 + attribute \src "libresoc.v:130629.3-130630.29" + process $proc$libresoc.v:130629$6016 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:128296.3-128297.29" - process $proc$libresoc.v:128296$5758 + attribute \src "libresoc.v:130631.3-130632.29" + process $proc$libresoc.v:130631$6017 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:128298.3-128299.29" - process $proc$libresoc.v:128298$5759 + attribute \src "libresoc.v:130633.3-130634.29" + process $proc$libresoc.v:130633$6018 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:128300.3-128301.27" - process $proc$libresoc.v:128300$5760 + attribute \src "libresoc.v:130635.3-130636.27" + process $proc$libresoc.v:130635$6019 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:128302.3-128303.51" - process $proc$libresoc.v:128302$5761 + attribute \src "libresoc.v:130637.3-130638.51" + process $proc$libresoc.v:130637$6020 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:128304.3-128305.47" - process $proc$libresoc.v:128304$5762 + attribute \src "libresoc.v:130639.3-130640.47" + process $proc$libresoc.v:130639$6021 assign { } { } assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] end - attribute \src "libresoc.v:128306.3-128307.61" - process $proc$libresoc.v:128306$5763 + attribute \src "libresoc.v:130641.3-130642.61" + process $proc$libresoc.v:130641$6022 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:128308.3-128309.57" - process $proc$libresoc.v:128308$5764 + attribute \src "libresoc.v:130643.3-130644.57" + process $proc$libresoc.v:130643$6023 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:128310.3-128311.45" - process $proc$libresoc.v:128310$5765 + attribute \src "libresoc.v:130645.3-130646.45" + process $proc$libresoc.v:130645$6024 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:128312.3-128313.45" - process $proc$libresoc.v:128312$5766 + attribute \src "libresoc.v:130647.3-130648.45" + process $proc$libresoc.v:130647$6025 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:128314.3-128315.45" - process $proc$libresoc.v:128314$5767 + attribute \src "libresoc.v:130649.3-130650.45" + process $proc$libresoc.v:130649$6026 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:128316.3-128317.45" - process $proc$libresoc.v:128316$5768 + attribute \src "libresoc.v:130651.3-130652.45" + process $proc$libresoc.v:130651$6027 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:128318.3-128319.45" - process $proc$libresoc.v:128318$5769 + attribute \src "libresoc.v:130653.3-130654.45" + process $proc$libresoc.v:130653$6028 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:128320.3-128321.49" - process $proc$libresoc.v:128320$5770 + attribute \src "libresoc.v:130655.3-130656.49" + process $proc$libresoc.v:130655$6029 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:128322.3-128323.51" - process $proc$libresoc.v:128322$5771 + attribute \src "libresoc.v:130657.3-130658.51" + process $proc$libresoc.v:130657$6030 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:128324.3-128325.49" - process $proc$libresoc.v:128324$5772 + attribute \src "libresoc.v:130659.3-130660.49" + process $proc$libresoc.v:130659$6031 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:128326.3-128327.57" - process $proc$libresoc.v:128326$5773 + attribute \src "libresoc.v:130661.3-130662.57" + process $proc$libresoc.v:130661$6032 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:128328.3-128329.55" - process $proc$libresoc.v:128328$5774 + attribute \src "libresoc.v:130663.3-130664.55" + process $proc$libresoc.v:130663$6033 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:128330.3-128331.51" - process $proc$libresoc.v:128330$5775 + attribute \src "libresoc.v:130665.3-130666.51" + process $proc$libresoc.v:130665$6034 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:128332.3-128333.41" - process $proc$libresoc.v:128332$5776 + attribute \src "libresoc.v:130667.3-130668.41" + process $proc$libresoc.v:130667$6035 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:128334.3-128335.39" - process $proc$libresoc.v:128334$5777 + attribute \src "libresoc.v:130669.3-130670.39" + process $proc$libresoc.v:130669$6036 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:128336.3-128337.39" - process $proc$libresoc.v:128336$5778 + attribute \src "libresoc.v:130671.3-130672.39" + process $proc$libresoc.v:130671$6037 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:128338.3-128339.39" - process $proc$libresoc.v:128338$5779 + attribute \src "libresoc.v:130673.3-130674.39" + process $proc$libresoc.v:130673$6038 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:128340.3-128341.39" - process $proc$libresoc.v:128340$5780 + attribute \src "libresoc.v:130675.3-130676.39" + process $proc$libresoc.v:130675$6039 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:128342.3-128343.39" - process $proc$libresoc.v:128342$5781 + attribute \src "libresoc.v:130677.3-130678.39" + process $proc$libresoc.v:130677$6040 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:128344.3-128345.39" - process $proc$libresoc.v:128344$5782 + attribute \src "libresoc.v:130679.3-130680.39" + process $proc$libresoc.v:130679$6041 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:128346.3-128347.39" - process $proc$libresoc.v:128346$5783 + attribute \src "libresoc.v:130681.3-130682.39" + process $proc$libresoc.v:130681$6042 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:128348.3-128349.39" - process $proc$libresoc.v:128348$5784 + attribute \src "libresoc.v:130683.3-130684.39" + process $proc$libresoc.v:130683$6043 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:128350.3-128351.39" - process $proc$libresoc.v:128350$5785 + attribute \src "libresoc.v:130685.3-130686.39" + process $proc$libresoc.v:130685$6044 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:128352.3-128353.39" - process $proc$libresoc.v:128352$5786 + attribute \src "libresoc.v:130687.3-130688.39" + process $proc$libresoc.v:130687$6045 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:128354.3-128355.28" - process $proc$libresoc.v:128354$5787 + attribute \src "libresoc.v:130689.3-130690.28" + process $proc$libresoc.v:130689$6046 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:128426.3-128434.6" - process $proc$libresoc.v:128426$5788 + attribute \src "libresoc.v:130761.3-130769.6" + process $proc$libresoc.v:130761$6047 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5789 $1\opc_l_s_opc$next[0:0]$5790 - attribute \src "libresoc.v:128427.5-128427.29" + assign $0\opc_l_s_opc$next[0:0]$6048 $1\opc_l_s_opc$next[0:0]$6049 + attribute \src "libresoc.v:130762.5-130762.29" switch \initial - attribute \src "libresoc.v:128427.9-128427.17" + attribute \src "libresoc.v:130762.9-130762.17" case 1'1 case end @@ -205702,21 +211075,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5790 1'0 + assign $1\opc_l_s_opc$next[0:0]$6049 1'0 case - assign $1\opc_l_s_opc$next[0:0]$5790 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6049 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5789 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6048 end - attribute \src "libresoc.v:128435.3-128443.6" - process $proc$libresoc.v:128435$5791 + attribute \src "libresoc.v:130770.3-130778.6" + process $proc$libresoc.v:130770$6050 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5792 $1\opc_l_r_opc$next[0:0]$5793 - attribute \src "libresoc.v:128436.5-128436.29" + assign $0\opc_l_r_opc$next[0:0]$6051 $1\opc_l_r_opc$next[0:0]$6052 + attribute \src "libresoc.v:130771.5-130771.29" switch \initial - attribute \src "libresoc.v:128436.9-128436.17" + attribute \src "libresoc.v:130771.9-130771.17" case 1'1 case end @@ -205725,21 +211098,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5793 1'1 + assign $1\opc_l_r_opc$next[0:0]$6052 1'1 case - assign $1\opc_l_r_opc$next[0:0]$5793 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6052 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5792 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6051 end - attribute \src "libresoc.v:128444.3-128452.6" - process $proc$libresoc.v:128444$5794 + attribute \src "libresoc.v:130779.3-130787.6" + process $proc$libresoc.v:130779$6053 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$5795 $1\src_l_s_src$next[2:0]$5796 - attribute \src "libresoc.v:128445.5-128445.29" + assign $0\src_l_s_src$next[2:0]$6054 $1\src_l_s_src$next[2:0]$6055 + attribute \src "libresoc.v:130780.5-130780.29" switch \initial - attribute \src "libresoc.v:128445.9-128445.17" + attribute \src "libresoc.v:130780.9-130780.17" case 1'1 case end @@ -205748,21 +211121,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$5796 3'000 + assign $1\src_l_s_src$next[2:0]$6055 3'000 case - assign $1\src_l_s_src$next[2:0]$5796 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6055 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5795 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6054 end - attribute \src "libresoc.v:128453.3-128461.6" - process $proc$libresoc.v:128453$5797 + attribute \src "libresoc.v:130788.3-130796.6" + process $proc$libresoc.v:130788$6056 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$5798 $1\src_l_r_src$next[2:0]$5799 - attribute \src "libresoc.v:128454.5-128454.29" + assign $0\src_l_r_src$next[2:0]$6057 $1\src_l_r_src$next[2:0]$6058 + attribute \src "libresoc.v:130789.5-130789.29" switch \initial - attribute \src "libresoc.v:128454.9-128454.17" + attribute \src "libresoc.v:130789.9-130789.17" case 1'1 case end @@ -205771,21 +211144,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$5799 3'111 + assign $1\src_l_r_src$next[2:0]$6058 3'111 case - assign $1\src_l_r_src$next[2:0]$5799 \reset_r + assign $1\src_l_r_src$next[2:0]$6058 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5798 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6057 end - attribute \src "libresoc.v:128462.3-128470.6" - process $proc$libresoc.v:128462$5800 + attribute \src "libresoc.v:130797.3-130805.6" + process $proc$libresoc.v:130797$6059 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$5801 $1\adr_l_r_adr$next[0:0]$5802 - attribute \src "libresoc.v:128463.5-128463.29" + assign $0\adr_l_r_adr$next[0:0]$6060 $1\adr_l_r_adr$next[0:0]$6061 + attribute \src "libresoc.v:130798.5-130798.29" switch \initial - attribute \src "libresoc.v:128463.9-128463.17" + attribute \src "libresoc.v:130798.9-130798.17" case 1'1 case end @@ -205794,21 +211167,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$5802 1'1 + assign $1\adr_l_r_adr$next[0:0]$6061 1'1 case - assign $1\adr_l_r_adr$next[0:0]$5802 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6061 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$5801 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6060 end - attribute \src "libresoc.v:128471.3-128479.6" - process $proc$libresoc.v:128471$5803 + attribute \src "libresoc.v:130806.3-130814.6" + process $proc$libresoc.v:130806$6062 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$5804 $1\wri_l_r_wri$next[0:0]$5805 - attribute \src "libresoc.v:128472.5-128472.29" + assign $0\wri_l_r_wri$next[0:0]$6063 $1\wri_l_r_wri$next[0:0]$6064 + attribute \src "libresoc.v:130807.5-130807.29" switch \initial - attribute \src "libresoc.v:128472.9-128472.17" + attribute \src "libresoc.v:130807.9-130807.17" case 1'1 case end @@ -205817,21 +211190,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$5805 1'1 + assign $1\wri_l_r_wri$next[0:0]$6064 1'1 case - assign $1\wri_l_r_wri$next[0:0]$5805 \$31 [0] + assign $1\wri_l_r_wri$next[0:0]$6064 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$5804 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6063 end - attribute \src "libresoc.v:128480.3-128488.6" - process $proc$libresoc.v:128480$5806 + attribute \src "libresoc.v:130815.3-130823.6" + process $proc$libresoc.v:130815$6065 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$5807 $1\upd_l_s_upd$next[0:0]$5808 - attribute \src "libresoc.v:128481.5-128481.29" + assign $0\upd_l_s_upd$next[0:0]$6066 $1\upd_l_s_upd$next[0:0]$6067 + attribute \src "libresoc.v:130816.5-130816.29" switch \initial - attribute \src "libresoc.v:128481.9-128481.17" + attribute \src "libresoc.v:130816.9-130816.17" case 1'1 case end @@ -205840,21 +211213,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$5808 1'0 + assign $1\upd_l_s_upd$next[0:0]$6067 1'0 case - assign $1\upd_l_s_upd$next[0:0]$5808 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6067 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$5807 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6066 end - attribute \src "libresoc.v:128489.3-128497.6" - process $proc$libresoc.v:128489$5809 + attribute \src "libresoc.v:130824.3-130832.6" + process $proc$libresoc.v:130824$6068 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$5810 $1\upd_l_r_upd$next[0:0]$5811 - attribute \src "libresoc.v:128490.5-128490.29" + assign $0\upd_l_r_upd$next[0:0]$6069 $1\upd_l_r_upd$next[0:0]$6070 + attribute \src "libresoc.v:130825.5-130825.29" switch \initial - attribute \src "libresoc.v:128490.9-128490.17" + attribute \src "libresoc.v:130825.9-130825.17" case 1'1 case end @@ -205863,21 +211236,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$5811 1'1 + assign $1\upd_l_r_upd$next[0:0]$6070 1'1 case - assign $1\upd_l_r_upd$next[0:0]$5811 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6070 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$5810 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6069 end - attribute \src "libresoc.v:128498.3-128506.6" - process $proc$libresoc.v:128498$5812 + attribute \src "libresoc.v:130833.3-130841.6" + process $proc$libresoc.v:130833$6071 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$5813 $1\sto_l_r_sto$next[0:0]$5814 - attribute \src "libresoc.v:128499.5-128499.29" + assign $0\sto_l_r_sto$next[0:0]$6072 $1\sto_l_r_sto$next[0:0]$6073 + attribute \src "libresoc.v:130834.5-130834.29" switch \initial - attribute \src "libresoc.v:128499.9-128499.17" + attribute \src "libresoc.v:130834.9-130834.17" case 1'1 case end @@ -205886,21 +211259,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$5814 1'1 + assign $1\sto_l_r_sto$next[0:0]$6073 1'1 case - assign $1\sto_l_r_sto$next[0:0]$5814 \$52 + assign $1\sto_l_r_sto$next[0:0]$6073 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$5813 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6072 end - attribute \src "libresoc.v:128507.3-128515.6" - process $proc$libresoc.v:128507$5815 + attribute \src "libresoc.v:130842.3-130850.6" + process $proc$libresoc.v:130842$6074 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$5816 $1\lsd_l_r_lsd$next[0:0]$5817 - attribute \src "libresoc.v:128508.5-128508.29" + assign $0\lsd_l_r_lsd$next[0:0]$6075 $1\lsd_l_r_lsd$next[0:0]$6076 + attribute \src "libresoc.v:130843.5-130843.29" switch \initial - attribute \src "libresoc.v:128508.9-128508.17" + attribute \src "libresoc.v:130843.9-130843.17" case 1'1 case end @@ -205909,15 +211282,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$5817 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6076 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$5817 \$56 + assign $1\lsd_l_r_lsd$next[0:0]$6076 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$5816 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6075 end - attribute \src "libresoc.v:128516.3-128558.6" - process $proc$libresoc.v:128516$5818 + attribute \src "libresoc.v:130851.3-130893.6" + process $proc$libresoc.v:130851$6077 assign { } { } assign { } { } assign { } { } @@ -205966,35 +211339,35 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$5819 $2\oper_r__byte_reverse$next[0:0]$5851 - assign $0\oper_r__data_len$next[3:0]$5820 $2\oper_r__data_len$next[3:0]$5852 - assign $0\oper_r__fn_unit$next[11:0]$5821 $2\oper_r__fn_unit$next[11:0]$5853 + assign $0\oper_r__byte_reverse$next[0:0]$6078 $2\oper_r__byte_reverse$next[0:0]$6110 + assign $0\oper_r__data_len$next[3:0]$6079 $2\oper_r__data_len$next[3:0]$6111 + assign $0\oper_r__fn_unit$next[11:0]$6080 $2\oper_r__fn_unit$next[11:0]$6112 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$5824 $2\oper_r__insn$next[31:0]$5856 - assign $0\oper_r__insn_type$next[6:0]$5825 $2\oper_r__insn_type$next[6:0]$5857 - assign $0\oper_r__is_32bit$next[0:0]$5826 $2\oper_r__is_32bit$next[0:0]$5858 - assign $0\oper_r__is_signed$next[0:0]$5827 $2\oper_r__is_signed$next[0:0]$5859 - assign $0\oper_r__ldst_mode$next[1:0]$5828 $2\oper_r__ldst_mode$next[1:0]$5860 + assign $0\oper_r__insn$next[31:0]$6083 $2\oper_r__insn$next[31:0]$6115 + assign $0\oper_r__insn_type$next[6:0]$6084 $2\oper_r__insn_type$next[6:0]$6116 + assign $0\oper_r__is_32bit$next[0:0]$6085 $2\oper_r__is_32bit$next[0:0]$6117 + assign $0\oper_r__is_signed$next[0:0]$6086 $2\oper_r__is_signed$next[0:0]$6118 + assign $0\oper_r__ldst_mode$next[1:0]$6087 $2\oper_r__ldst_mode$next[1:0]$6119 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$5833 $2\oper_r__sign_extend$next[0:0]$5865 - assign $0\oper_r__zero_a$next[0:0]$5834 $2\oper_r__zero_a$next[0:0]$5866 - assign $0\oper_r__imm_data__data$next[63:0]$5822 $3\oper_r__imm_data__data$next[63:0]$5867 - assign $0\oper_r__imm_data__ok$next[0:0]$5823 $3\oper_r__imm_data__ok$next[0:0]$5868 - assign $0\oper_r__oe__oe$next[0:0]$5829 $3\oper_r__oe__oe$next[0:0]$5869 - assign $0\oper_r__oe__ok$next[0:0]$5830 $3\oper_r__oe__ok$next[0:0]$5870 - assign $0\oper_r__rc__ok$next[0:0]$5831 $3\oper_r__rc__ok$next[0:0]$5871 - assign $0\oper_r__rc__rc$next[0:0]$5832 $3\oper_r__rc__rc$next[0:0]$5872 - attribute \src "libresoc.v:128517.5-128517.29" + assign $0\oper_r__sign_extend$next[0:0]$6092 $2\oper_r__sign_extend$next[0:0]$6124 + assign $0\oper_r__zero_a$next[0:0]$6093 $2\oper_r__zero_a$next[0:0]$6125 + assign $0\oper_r__imm_data__data$next[63:0]$6081 $3\oper_r__imm_data__data$next[63:0]$6126 + assign $0\oper_r__imm_data__ok$next[0:0]$6082 $3\oper_r__imm_data__ok$next[0:0]$6127 + assign $0\oper_r__oe__oe$next[0:0]$6088 $3\oper_r__oe__oe$next[0:0]$6128 + assign $0\oper_r__oe__ok$next[0:0]$6089 $3\oper_r__oe__ok$next[0:0]$6129 + assign $0\oper_r__rc__ok$next[0:0]$6090 $3\oper_r__rc__ok$next[0:0]$6130 + assign $0\oper_r__rc__rc$next[0:0]$6091 $3\oper_r__rc__rc$next[0:0]$6131 + attribute \src "libresoc.v:130852.5-130852.29" switch \initial - attribute \src "libresoc.v:128517.9-128517.17" + attribute \src "libresoc.v:130852.9-130852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206014,26 +211387,26 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$5840 $1\oper_r__ldst_mode$next[1:0]$5844 $1\oper_r__sign_extend$next[0:0]$5849 $1\oper_r__byte_reverse$next[0:0]$5835 $1\oper_r__data_len$next[3:0]$5836 $1\oper_r__is_signed$next[0:0]$5843 $1\oper_r__is_32bit$next[0:0]$5842 $1\oper_r__oe__ok$next[0:0]$5846 $1\oper_r__oe__oe$next[0:0]$5845 $1\oper_r__rc__ok$next[0:0]$5847 $1\oper_r__rc__rc$next[0:0]$5848 $1\oper_r__zero_a$next[0:0]$5850 $1\oper_r__imm_data__ok$next[0:0]$5839 $1\oper_r__imm_data__data$next[63:0]$5838 $1\oper_r__fn_unit$next[11:0]$5837 $1\oper_r__insn_type$next[6:0]$5841 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6099 $1\oper_r__ldst_mode$next[1:0]$6103 $1\oper_r__sign_extend$next[0:0]$6108 $1\oper_r__byte_reverse$next[0:0]$6094 $1\oper_r__data_len$next[3:0]$6095 $1\oper_r__is_signed$next[0:0]$6102 $1\oper_r__is_32bit$next[0:0]$6101 $1\oper_r__oe__ok$next[0:0]$6105 $1\oper_r__oe__oe$next[0:0]$6104 $1\oper_r__rc__ok$next[0:0]$6106 $1\oper_r__rc__rc$next[0:0]$6107 $1\oper_r__zero_a$next[0:0]$6109 $1\oper_r__imm_data__ok$next[0:0]$6098 $1\oper_r__imm_data__data$next[63:0]$6097 $1\oper_r__fn_unit$next[11:0]$6096 $1\oper_r__insn_type$next[6:0]$6100 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$5835 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$5836 \oper_r__data_len - assign $1\oper_r__fn_unit$next[11:0]$5837 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$5838 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$5839 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$5840 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$5841 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$5842 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$5843 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$5844 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$5845 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$5846 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$5847 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$5848 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$5849 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$5850 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6094 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6095 \oper_r__data_len + assign $1\oper_r__fn_unit$next[11:0]$6096 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6097 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6098 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6099 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6100 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6101 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6102 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6103 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6104 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6105 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6106 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6107 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6108 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6109 \oper_r__zero_a end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206053,24 +211426,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$5856 $2\oper_r__ldst_mode$next[1:0]$5860 $2\oper_r__sign_extend$next[0:0]$5865 $2\oper_r__byte_reverse$next[0:0]$5851 $2\oper_r__data_len$next[3:0]$5852 $2\oper_r__is_signed$next[0:0]$5859 $2\oper_r__is_32bit$next[0:0]$5858 $2\oper_r__oe__ok$next[0:0]$5862 $2\oper_r__oe__oe$next[0:0]$5861 $2\oper_r__rc__ok$next[0:0]$5863 $2\oper_r__rc__rc$next[0:0]$5864 $2\oper_r__zero_a$next[0:0]$5866 $2\oper_r__imm_data__ok$next[0:0]$5855 $2\oper_r__imm_data__data$next[63:0]$5854 $2\oper_r__fn_unit$next[11:0]$5853 $2\oper_r__insn_type$next[6:0]$5857 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6115 $2\oper_r__ldst_mode$next[1:0]$6119 $2\oper_r__sign_extend$next[0:0]$6124 $2\oper_r__byte_reverse$next[0:0]$6110 $2\oper_r__data_len$next[3:0]$6111 $2\oper_r__is_signed$next[0:0]$6118 $2\oper_r__is_32bit$next[0:0]$6117 $2\oper_r__oe__ok$next[0:0]$6121 $2\oper_r__oe__oe$next[0:0]$6120 $2\oper_r__rc__ok$next[0:0]$6122 $2\oper_r__rc__rc$next[0:0]$6123 $2\oper_r__zero_a$next[0:0]$6125 $2\oper_r__imm_data__ok$next[0:0]$6114 $2\oper_r__imm_data__data$next[63:0]$6113 $2\oper_r__fn_unit$next[11:0]$6112 $2\oper_r__insn_type$next[6:0]$6116 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$5851 $1\oper_r__byte_reverse$next[0:0]$5835 - assign $2\oper_r__data_len$next[3:0]$5852 $1\oper_r__data_len$next[3:0]$5836 - assign $2\oper_r__fn_unit$next[11:0]$5853 $1\oper_r__fn_unit$next[11:0]$5837 - assign $2\oper_r__imm_data__data$next[63:0]$5854 $1\oper_r__imm_data__data$next[63:0]$5838 - assign $2\oper_r__imm_data__ok$next[0:0]$5855 $1\oper_r__imm_data__ok$next[0:0]$5839 - assign $2\oper_r__insn$next[31:0]$5856 $1\oper_r__insn$next[31:0]$5840 - assign $2\oper_r__insn_type$next[6:0]$5857 $1\oper_r__insn_type$next[6:0]$5841 - assign $2\oper_r__is_32bit$next[0:0]$5858 $1\oper_r__is_32bit$next[0:0]$5842 - assign $2\oper_r__is_signed$next[0:0]$5859 $1\oper_r__is_signed$next[0:0]$5843 - assign $2\oper_r__ldst_mode$next[1:0]$5860 $1\oper_r__ldst_mode$next[1:0]$5844 - assign $2\oper_r__oe__oe$next[0:0]$5861 $1\oper_r__oe__oe$next[0:0]$5845 - assign $2\oper_r__oe__ok$next[0:0]$5862 $1\oper_r__oe__ok$next[0:0]$5846 - assign $2\oper_r__rc__ok$next[0:0]$5863 $1\oper_r__rc__ok$next[0:0]$5847 - assign $2\oper_r__rc__rc$next[0:0]$5864 $1\oper_r__rc__rc$next[0:0]$5848 - assign $2\oper_r__sign_extend$next[0:0]$5865 $1\oper_r__sign_extend$next[0:0]$5849 - assign $2\oper_r__zero_a$next[0:0]$5866 $1\oper_r__zero_a$next[0:0]$5850 + assign $2\oper_r__byte_reverse$next[0:0]$6110 $1\oper_r__byte_reverse$next[0:0]$6094 + assign $2\oper_r__data_len$next[3:0]$6111 $1\oper_r__data_len$next[3:0]$6095 + assign $2\oper_r__fn_unit$next[11:0]$6112 $1\oper_r__fn_unit$next[11:0]$6096 + assign $2\oper_r__imm_data__data$next[63:0]$6113 $1\oper_r__imm_data__data$next[63:0]$6097 + assign $2\oper_r__imm_data__ok$next[0:0]$6114 $1\oper_r__imm_data__ok$next[0:0]$6098 + assign $2\oper_r__insn$next[31:0]$6115 $1\oper_r__insn$next[31:0]$6099 + assign $2\oper_r__insn_type$next[6:0]$6116 $1\oper_r__insn_type$next[6:0]$6100 + assign $2\oper_r__is_32bit$next[0:0]$6117 $1\oper_r__is_32bit$next[0:0]$6101 + assign $2\oper_r__is_signed$next[0:0]$6118 $1\oper_r__is_signed$next[0:0]$6102 + assign $2\oper_r__ldst_mode$next[1:0]$6119 $1\oper_r__ldst_mode$next[1:0]$6103 + assign $2\oper_r__oe__oe$next[0:0]$6120 $1\oper_r__oe__oe$next[0:0]$6104 + assign $2\oper_r__oe__ok$next[0:0]$6121 $1\oper_r__oe__ok$next[0:0]$6105 + assign $2\oper_r__rc__ok$next[0:0]$6122 $1\oper_r__rc__ok$next[0:0]$6106 + assign $2\oper_r__rc__rc$next[0:0]$6123 $1\oper_r__rc__rc$next[0:0]$6107 + assign $2\oper_r__sign_extend$next[0:0]$6124 $1\oper_r__sign_extend$next[0:0]$6108 + assign $2\oper_r__zero_a$next[0:0]$6125 $1\oper_r__zero_a$next[0:0]$6109 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -206082,46 +211455,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$5867 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$5868 1'0 - assign $3\oper_r__rc__rc$next[0:0]$5872 1'0 - assign $3\oper_r__rc__ok$next[0:0]$5871 1'0 - assign $3\oper_r__oe__oe$next[0:0]$5869 1'0 - assign $3\oper_r__oe__ok$next[0:0]$5870 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6127 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6131 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6130 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6128 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6129 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$5867 $2\oper_r__imm_data__data$next[63:0]$5854 - assign $3\oper_r__imm_data__ok$next[0:0]$5868 $2\oper_r__imm_data__ok$next[0:0]$5855 - assign $3\oper_r__oe__oe$next[0:0]$5869 $2\oper_r__oe__oe$next[0:0]$5861 - assign $3\oper_r__oe__ok$next[0:0]$5870 $2\oper_r__oe__ok$next[0:0]$5862 - assign $3\oper_r__rc__ok$next[0:0]$5871 $2\oper_r__rc__ok$next[0:0]$5863 - assign $3\oper_r__rc__rc$next[0:0]$5872 $2\oper_r__rc__rc$next[0:0]$5864 + assign $3\oper_r__imm_data__data$next[63:0]$6126 $2\oper_r__imm_data__data$next[63:0]$6113 + assign $3\oper_r__imm_data__ok$next[0:0]$6127 $2\oper_r__imm_data__ok$next[0:0]$6114 + assign $3\oper_r__oe__oe$next[0:0]$6128 $2\oper_r__oe__oe$next[0:0]$6120 + assign $3\oper_r__oe__ok$next[0:0]$6129 $2\oper_r__oe__ok$next[0:0]$6121 + assign $3\oper_r__rc__ok$next[0:0]$6130 $2\oper_r__rc__ok$next[0:0]$6122 + assign $3\oper_r__rc__rc$next[0:0]$6131 $2\oper_r__rc__rc$next[0:0]$6123 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$5819 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$5820 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$5821 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$5822 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$5823 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$5824 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$5825 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$5826 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$5827 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$5828 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$5829 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$5830 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$5831 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$5832 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$5833 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$5834 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6078 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6079 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$6080 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6081 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6082 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6083 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6084 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6085 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6086 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6087 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6088 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6089 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6090 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6091 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6092 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6093 end - attribute \src "libresoc.v:128559.3-128568.6" - process $proc$libresoc.v:128559$5873 + attribute \src "libresoc.v:130894.3-130903.6" + process $proc$libresoc.v:130894$6132 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$5874 $1\ldo_r$next[63:0]$5875 - attribute \src "libresoc.v:128560.5-128560.29" + assign $0\ldo_r$next[63:0]$6133 $1\ldo_r$next[63:0]$6134 + attribute \src "libresoc.v:130895.5-130895.29" switch \initial - attribute \src "libresoc.v:128560.9-128560.17" + attribute \src "libresoc.v:130895.9-130895.17" case 1'1 case end @@ -206130,120 +211503,120 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$5875 \ldd_o + assign $1\ldo_r$next[63:0]$6134 \ldd_o case - assign $1\ldo_r$next[63:0]$5875 \ldo_r + assign $1\ldo_r$next[63:0]$6134 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$5874 + update \ldo_r$next $0\ldo_r$next[63:0]$6133 end - attribute \src "libresoc.v:128569.3-128584.6" - process $proc$libresoc.v:128569$5876 + attribute \src "libresoc.v:130904.3-130919.6" + process $proc$libresoc.v:130904$6135 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$5877 $2\src_r0$next[63:0]$5879 - attribute \src "libresoc.v:128570.5-128570.29" + assign $0\src_r0$next[63:0]$6136 $2\src_r0$next[63:0]$6138 + attribute \src "libresoc.v:130905.5-130905.29" switch \initial - attribute \src "libresoc.v:128570.9-128570.17" + attribute \src "libresoc.v:130905.9-130905.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$5878 \src1_i + assign $1\src_r0$next[63:0]$6137 \src1_i case - assign $1\src_r0$next[63:0]$5878 \src_r0 + assign $1\src_r0$next[63:0]$6137 \src_r0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$5879 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6138 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$5879 $1\src_r0$next[63:0]$5878 + assign $2\src_r0$next[63:0]$6138 $1\src_r0$next[63:0]$6137 end sync always - update \src_r0$next $0\src_r0$next[63:0]$5877 + update \src_r0$next $0\src_r0$next[63:0]$6136 end - attribute \src "libresoc.v:128585.3-128600.6" - process $proc$libresoc.v:128585$5880 + attribute \src "libresoc.v:130920.3-130935.6" + process $proc$libresoc.v:130920$6139 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$5881 $2\src_r1$next[63:0]$5883 - attribute \src "libresoc.v:128586.5-128586.29" + assign $0\src_r1$next[63:0]$6140 $2\src_r1$next[63:0]$6142 + attribute \src "libresoc.v:130921.5-130921.29" switch \initial - attribute \src "libresoc.v:128586.9-128586.17" + attribute \src "libresoc.v:130921.9-130921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$5882 \src2_i + assign $1\src_r1$next[63:0]$6141 \src2_i case - assign $1\src_r1$next[63:0]$5882 \src_r1 + assign $1\src_r1$next[63:0]$6141 \src_r1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$5883 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6142 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$5883 $1\src_r1$next[63:0]$5882 + assign $2\src_r1$next[63:0]$6142 $1\src_r1$next[63:0]$6141 end sync always - update \src_r1$next $0\src_r1$next[63:0]$5881 + update \src_r1$next $0\src_r1$next[63:0]$6140 end - attribute \src "libresoc.v:128601.3-128616.6" - process $proc$libresoc.v:128601$5884 + attribute \src "libresoc.v:130936.3-130951.6" + process $proc$libresoc.v:130936$6143 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$5885 $2\src_r2$next[63:0]$5887 - attribute \src "libresoc.v:128602.5-128602.29" + assign $0\src_r2$next[63:0]$6144 $2\src_r2$next[63:0]$6146 + attribute \src "libresoc.v:130937.5-130937.29" switch \initial - attribute \src "libresoc.v:128602.9-128602.17" + attribute \src "libresoc.v:130937.9-130937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" switch \cu_rd__go_i [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$5886 \src3_i + assign $1\src_r2$next[63:0]$6145 \src3_i case - assign $1\src_r2$next[63:0]$5886 \src_r2 + assign $1\src_r2$next[63:0]$6145 \src_r2 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$5887 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6146 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$5887 $1\src_r2$next[63:0]$5886 + assign $2\src_r2$next[63:0]$6146 $1\src_r2$next[63:0]$6145 end sync always - update \src_r2$next $0\src_r2$next[63:0]$5885 + update \src_r2$next $0\src_r2$next[63:0]$6144 end - attribute \src "libresoc.v:128617.3-128626.6" - process $proc$libresoc.v:128617$5888 + attribute \src "libresoc.v:130952.3-130961.6" + process $proc$libresoc.v:130952$6147 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$5889 $1\ea_r$next[63:0]$5890 - attribute \src "libresoc.v:128618.5-128618.29" + assign $0\ea_r$next[63:0]$6148 $1\ea_r$next[63:0]$6149 + attribute \src "libresoc.v:130953.5-130953.29" switch \initial - attribute \src "libresoc.v:128618.9-128618.17" + attribute \src "libresoc.v:130953.9-130953.17" case 1'1 case end @@ -206252,25 +211625,25 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$5890 \alu_o + assign $1\ea_r$next[63:0]$6149 \alu_o case - assign $1\ea_r$next[63:0]$5890 \ea_r + assign $1\ea_r$next[63:0]$6149 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$5889 + update \ea_r$next $0\ea_r$next[63:0]$6148 end - attribute \src "libresoc.v:128627.3-128636.6" - process $proc$libresoc.v:128627$5891 + attribute \src "libresoc.v:130962.3-130971.6" + process $proc$libresoc.v:130962$6150 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:128628.5-128628.29" + attribute \src "libresoc.v:130963.5-130963.29" switch \initial - attribute \src "libresoc.v:128628.9-128628.17" + attribute \src "libresoc.v:130963.9-130963.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" switch \cu_wr__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206282,19 +211655,19 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:128637.3-128646.6" - process $proc$libresoc.v:128637$5892 + attribute \src "libresoc.v:130972.3-130981.6" + process $proc$libresoc.v:130972$6151 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:128638.5-128638.29" + attribute \src "libresoc.v:130973.5-130973.29" switch \initial - attribute \src "libresoc.v:128638.9-128638.17" + attribute \src "libresoc.v:130973.9-130973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - switch \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + switch \$164 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -206305,14 +211678,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:128647.3-128655.6" - process $proc$libresoc.v:128647$5893 + attribute \src "libresoc.v:130982.3-130990.6" + process $proc$libresoc.v:130982$6152 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$5894 $1\ldst_port0_addr_i_ok$next[0:0]$5895 - attribute \src "libresoc.v:128648.5-128648.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6153 $1\ldst_port0_addr_i_ok$next[0:0]$6154 + attribute \src "libresoc.v:130983.5-130983.29" switch \initial - attribute \src "libresoc.v:128648.9-128648.17" + attribute \src "libresoc.v:130983.9-130983.17" case 1'1 case end @@ -206321,25 +211694,25 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$5895 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6154 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$5895 \$170 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6154 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$5894 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6153 end - attribute \src "libresoc.v:128656.3-128679.6" - process $proc$libresoc.v:128656$5896 + attribute \src "libresoc.v:130991.3-131014.6" + process $proc$libresoc.v:130991$6155 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:128657.5-128657.29" + attribute \src "libresoc.v:130992.5-130992.29" switch \initial - attribute \src "libresoc.v:128657.9-128657.17" + attribute \src "libresoc.v:130992.9-130992.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206350,15 +211723,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $2\lddata_r[63:0] \$172 + assign $2\lddata_r[63:0] \$186 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $2\lddata_r[63:0] \$174 + assign $2\lddata_r[63:0] \$188 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $2\lddata_r[63:0] \$176 + assign $2\lddata_r[63:0] \$190 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } @@ -206372,17 +211745,17 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:128680.3-128691.6" - process $proc$libresoc.v:128680$5897 + attribute \src "libresoc.v:131015.3-131026.6" + process $proc$libresoc.v:131015$6156 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:128681.5-128681.29" + attribute \src "libresoc.v:131016.5-131016.29" switch \initial - attribute \src "libresoc.v:128681.9-128681.17" + attribute \src "libresoc.v:131016.9-131016.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206396,24 +211769,24 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:128692.3-128711.6" - process $proc$libresoc.v:128692$5898 + attribute \src "libresoc.v:131027.3-131046.6" + process $proc$libresoc.v:131027$6157 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:128693.5-128693.29" + attribute \src "libresoc.v:131028.5-131028.29" switch \initial - attribute \src "libresoc.v:128693.9-128693.17" + attribute \src "libresoc.v:131028.9-131028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" switch \oper_r__sign_extend attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldd_o[63:0] $2\ldd_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - switch \$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -206431,18 +211804,18 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:128712.3-128735.6" - process $proc$libresoc.v:128712$5899 + attribute \src "libresoc.v:131047.3-131070.6" + process $proc$libresoc.v:131047$6158 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:128713.5-128713.29" + attribute \src "libresoc.v:131048.5-131048.29" switch \initial - attribute \src "libresoc.v:128713.9-128713.17" + attribute \src "libresoc.v:131048.9-131048.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206453,15 +211826,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 4'0001 assign { } { } - assign $2\stdata_r[63:0] \$180 + assign $2\stdata_r[63:0] \$194 attribute \src "libresoc.v:0.0-0.0" case 4'0010 assign { } { } - assign $2\stdata_r[63:0] \$182 + assign $2\stdata_r[63:0] \$196 attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } - assign $2\stdata_r[63:0] \$184 + assign $2\stdata_r[63:0] \$198 attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } @@ -206475,17 +211848,17 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:128736.3-128747.6" - process $proc$libresoc.v:128736$5900 + attribute \src "libresoc.v:131071.3-131082.6" + process $proc$libresoc.v:131071$6159 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:128737.5-128737.29" + attribute \src "libresoc.v:131072.5-131072.29" switch \initial - attribute \src "libresoc.v:128737.9-128737.17" + attribute \src "libresoc.v:131072.9-131072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -206499,422 +211872,422 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$9 $or$libresoc.v:128195$5659_Y - connect \$99 $and$libresoc.v:128196$5660_Y - connect \$101 $and$libresoc.v:128197$5661_Y - connect \$103 $and$libresoc.v:128198$5662_Y - connect \$105 $and$libresoc.v:128199$5663_Y - connect \$107 $and$libresoc.v:128200$5664_Y - connect \$109 $and$libresoc.v:128201$5665_Y - connect \$111 $and$libresoc.v:128202$5666_Y - connect \$113 $and$libresoc.v:128203$5667_Y - connect \$115 $and$libresoc.v:128204$5668_Y - connect \$117 $and$libresoc.v:128205$5669_Y - connect \$11 $or$libresoc.v:128206$5670_Y - connect \$119 $eq$libresoc.v:128207$5671_Y - connect \$121 $and$libresoc.v:128208$5672_Y - connect \$123 $and$libresoc.v:128209$5673_Y - connect \$125 $and$libresoc.v:128210$5674_Y - connect \$127 $or$libresoc.v:128211$5675_Y - connect \$129 $or$libresoc.v:128212$5676_Y - connect \$131 $or$libresoc.v:128213$5677_Y - connect \$133 $and$libresoc.v:128214$5678_Y - connect \$135 $and$libresoc.v:128215$5679_Y - connect \$138 $or$libresoc.v:128216$5680_Y - connect \$13 $or$libresoc.v:128217$5681_Y - connect \$140 $or$libresoc.v:128218$5682_Y - connect \$137 $not$libresoc.v:128219$5683_Y - connect \$143 $and$libresoc.v:128220$5684_Y - connect \$145 $or$libresoc.v:128221$5685_Y - connect \$147 $and$libresoc.v:128222$5686_Y - connect \$149 $not$libresoc.v:128223$5687_Y - connect \$151 $or$libresoc.v:128224$5688_Y - connect \$153 $and$libresoc.v:128225$5689_Y - connect \$155 $eq$libresoc.v:128226$5690_Y - connect \$157 $and$libresoc.v:128227$5691_Y - connect \$15 $eq$libresoc.v:128228$5692_Y - connect \$160 $eq$libresoc.v:128229$5693_Y - connect \$162 $and$libresoc.v:128230$5694_Y - connect \$164 $and$libresoc.v:128231$5695_Y - connect \$166 $and$libresoc.v:128232$5696_Y - connect \$168 $pos$libresoc.v:128233$5698_Y - connect \$170 $and$libresoc.v:128234$5699_Y - connect \$172 $pos$libresoc.v:128235$5701_Y - connect \$174 $pos$libresoc.v:128236$5702_Y - connect \$176 $pos$libresoc.v:128237$5703_Y - connect \$178 $eq$libresoc.v:128238$5704_Y - connect \$17 $eq$libresoc.v:128239$5705_Y - connect \$180 $pos$libresoc.v:128240$5707_Y - connect \$182 $pos$libresoc.v:128241$5708_Y - connect \$184 $pos$libresoc.v:128242$5709_Y - connect \$1 $or$libresoc.v:128243$5710_Y - connect \$19 $and$libresoc.v:128244$5711_Y - connect \$21 $and$libresoc.v:128245$5712_Y - connect \$23 $not$libresoc.v:128246$5713_Y - connect \$25 $and$libresoc.v:128247$5714_Y - connect \$27 $not$libresoc.v:128248$5715_Y - connect \$29 $and$libresoc.v:128249$5716_Y - connect \$32 $not$libresoc.v:128250$5717_Y - connect \$34 $eq$libresoc.v:128251$5718_Y - connect \$36 $and$libresoc.v:128252$5719_Y - connect \$38 $or$libresoc.v:128253$5720_Y - connect \$3 $or$libresoc.v:128254$5721_Y - connect \$40 $not$libresoc.v:128255$5722_Y - connect \$42 $eq$libresoc.v:128256$5723_Y - connect \$44 $and$libresoc.v:128257$5724_Y - connect \$46 $or$libresoc.v:128258$5725_Y - connect \$48 $or$libresoc.v:128259$5726_Y - connect \$50 $and$libresoc.v:128260$5727_Y - connect \$52 $or$libresoc.v:128261$5728_Y - connect \$54 $or$libresoc.v:128262$5729_Y - connect \$56 $or$libresoc.v:128263$5730_Y - connect \$58 $ternary$libresoc.v:128264$5731_Y - connect \$5 $or$libresoc.v:128265$5732_Y - connect \$60 $ternary$libresoc.v:128266$5733_Y - connect \$62 $ternary$libresoc.v:128267$5734_Y - connect \$64 $ternary$libresoc.v:128268$5735_Y - connect \$67 $add$libresoc.v:128269$5736_Y - connect \$69 $and$libresoc.v:128270$5737_Y - connect \$71 $not$libresoc.v:128271$5738_Y - connect \$73 $and$libresoc.v:128272$5739_Y - connect \$75 $not$libresoc.v:128273$5740_Y - connect \$77 $and$libresoc.v:128274$5741_Y - connect \$7 $or$libresoc.v:128275$5742_Y - connect \$79 $and$libresoc.v:128276$5743_Y - connect \$81 $and$libresoc.v:128277$5744_Y - connect \$83 $or$libresoc.v:128278$5745_Y - connect \$86 $or$libresoc.v:128279$5746_Y - connect \$85 $not$libresoc.v:128280$5747_Y - connect \$89 $and$libresoc.v:128281$5748_Y - connect \$91 $not$libresoc.v:128282$5749_Y - connect \$93 $and$libresoc.v:128283$5750_Y - connect \$95 $and$libresoc.v:128284$5751_Y - connect \$97 $and$libresoc.v:128285$5752_Y - connect \$31 \$48 - connect \$66 \$67 - connect \$159 \$162 + connect \$100 $and$libresoc.v:130530$5918_Y + connect \$102 $and$libresoc.v:130531$5919_Y + connect \$104 $and$libresoc.v:130532$5920_Y + connect \$106 $and$libresoc.v:130533$5921_Y + connect \$108 $and$libresoc.v:130534$5922_Y + connect \$10 $or$libresoc.v:130535$5923_Y + connect \$110 $and$libresoc.v:130536$5924_Y + connect \$112 $and$libresoc.v:130537$5925_Y + connect \$114 $and$libresoc.v:130538$5926_Y + connect \$116 $and$libresoc.v:130539$5927_Y + connect \$118 $and$libresoc.v:130540$5928_Y + connect \$120 $and$libresoc.v:130541$5929_Y + connect \$122 $and$libresoc.v:130542$5930_Y + connect \$124 $and$libresoc.v:130543$5931_Y + connect \$126 $eq$libresoc.v:130544$5932_Y + connect \$128 $and$libresoc.v:130545$5933_Y + connect \$12 $or$libresoc.v:130546$5934_Y + connect \$130 $and$libresoc.v:130547$5935_Y + connect \$132 $and$libresoc.v:130548$5936_Y + connect \$134 $or$libresoc.v:130549$5937_Y + connect \$136 $or$libresoc.v:130550$5938_Y + connect \$138 $or$libresoc.v:130551$5939_Y + connect \$140 $and$libresoc.v:130552$5940_Y + connect \$142 $and$libresoc.v:130553$5941_Y + connect \$145 $or$libresoc.v:130554$5942_Y + connect \$147 $or$libresoc.v:130555$5943_Y + connect \$144 $not$libresoc.v:130556$5944_Y + connect \$14 $or$libresoc.v:130557$5945_Y + connect \$150 $and$libresoc.v:130558$5946_Y + connect \$152 $or$libresoc.v:130559$5947_Y + connect \$154 $and$libresoc.v:130560$5948_Y + connect \$156 $not$libresoc.v:130561$5949_Y + connect \$158 $or$libresoc.v:130562$5950_Y + connect \$160 $and$libresoc.v:130563$5951_Y + connect \$162 $eq$libresoc.v:130564$5952_Y + connect \$164 $and$libresoc.v:130565$5953_Y + connect \$167 $eq$libresoc.v:130566$5954_Y + connect \$16 $or$libresoc.v:130567$5955_Y + connect \$169 $and$libresoc.v:130568$5956_Y + connect \$171 $and$libresoc.v:130569$5957_Y + connect \$173 $and$libresoc.v:130570$5958_Y + connect \$175 $pos$libresoc.v:130571$5960_Y + connect \$177 $and$libresoc.v:130572$5961_Y + connect \$186 $pos$libresoc.v:130573$5963_Y + connect \$188 $pos$libresoc.v:130574$5964_Y + connect \$18 $or$libresoc.v:130575$5965_Y + connect \$190 $pos$libresoc.v:130576$5966_Y + connect \$192 $eq$libresoc.v:130577$5967_Y + connect \$194 $pos$libresoc.v:130578$5969_Y + connect \$196 $pos$libresoc.v:130579$5970_Y + connect \$198 $pos$libresoc.v:130580$5971_Y + connect \$20 $or$libresoc.v:130581$5972_Y + connect \$22 $eq$libresoc.v:130582$5973_Y + connect \$24 $eq$libresoc.v:130583$5974_Y + connect \$26 $and$libresoc.v:130584$5975_Y + connect \$28 $and$libresoc.v:130585$5976_Y + connect \$30 $not$libresoc.v:130586$5977_Y + connect \$32 $and$libresoc.v:130587$5978_Y + connect \$34 $not$libresoc.v:130588$5979_Y + connect \$36 $and$libresoc.v:130589$5980_Y + connect \$39 $not$libresoc.v:130590$5981_Y + connect \$41 $eq$libresoc.v:130591$5982_Y + connect \$43 $and$libresoc.v:130592$5983_Y + connect \$45 $or$libresoc.v:130593$5984_Y + connect \$47 $not$libresoc.v:130594$5985_Y + connect \$49 $eq$libresoc.v:130595$5986_Y + connect \$51 $and$libresoc.v:130596$5987_Y + connect \$53 $or$libresoc.v:130597$5988_Y + connect \$55 $or$libresoc.v:130598$5989_Y + connect \$57 $and$libresoc.v:130599$5990_Y + connect \$59 $or$libresoc.v:130600$5991_Y + connect \$61 $or$libresoc.v:130601$5992_Y + connect \$63 $or$libresoc.v:130602$5993_Y + connect \$65 $ternary$libresoc.v:130603$5994_Y + connect \$67 $ternary$libresoc.v:130604$5995_Y + connect \$69 $ternary$libresoc.v:130605$5996_Y + connect \$71 $ternary$libresoc.v:130606$5997_Y + connect \$74 $add$libresoc.v:130607$5998_Y + connect \$76 $and$libresoc.v:130608$5999_Y + connect \$78 $not$libresoc.v:130609$6000_Y + connect \$80 $and$libresoc.v:130610$6001_Y + connect \$82 $not$libresoc.v:130611$6002_Y + connect \$84 $and$libresoc.v:130612$6003_Y + connect \$86 $and$libresoc.v:130613$6004_Y + connect \$88 $and$libresoc.v:130614$6005_Y + connect \$8 $or$libresoc.v:130615$6006_Y + connect \$90 $or$libresoc.v:130616$6007_Y + connect \$93 $or$libresoc.v:130617$6008_Y + connect \$92 $not$libresoc.v:130618$6009_Y + connect \$96 $and$libresoc.v:130619$6010_Y + connect \$98 $not$libresoc.v:130620$6011_Y + connect \$38 \$55 + connect \$73 \$74 + connect \$166 \$169 connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \ldst_port0_st_data_i_ok \cu_st__go_i connect \ld_ok \ldst_port0_ld_data_o_ok connect \addr_ok \ldst_port0_addr_ok_o - connect \addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_i$next \$168 + connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } + connect \ldst_port0_addr_i$next \$175 connect \ldst_port0_data_len \oper_r__data_len - connect \ldst_port0_is_st_i \$166 - connect \ldst_port0_is_ld_i \$164 - connect \cu_wrmask_o \$162 [1:0] + connect \ldst_port0_is_st_i \$173 + connect \ldst_port0_is_ld_i \$171 + connect \cu_wrmask_o \$169 [1:0] connect \ea \dest2_o connect \o \dest1_o - connect \cu_done_o \$153 - connect \wr_reset \$147 - connect \wr_any \$131 - connect \cu_wr__rel_o [1] \$125 - connect \cu_wr__rel_o [0] \$115 - connect \cu_st__rel_o \$105 - connect \cu_ad__rel_o \$97 - connect \rd_done \$93 - connect \alu_valid \$89 - connect \rda_any \$83 - connect \cu_rd__rel_o [2] \$81 - connect \cu_rd__rel_o [1:0] \$77 [1:0] + connect \cu_done_o \$160 + connect \wr_reset \$154 + connect \wr_any \$138 + connect \cu_wr__rel_o [1] \$132 + connect \cu_wr__rel_o [0] \$122 + connect \cu_st__rel_o \$112 + connect \cu_ad__rel_o \$104 + connect \rd_done \$100 + connect \alu_valid \$96 + connect \rda_any \$90 + connect \cu_rd__rel_o [2] \$88 + connect \cu_rd__rel_o [1:0] \$84 [1:0] connect \cu_busy_o \opc_l_q_opc connect \alu_ok$next \alu_valid - connect \alu_o \$67 [63:0] - connect \src2_or_imm \$64 - connect \src1_or_z \$62 - connect \addr_r \$60 - connect \ldd_r \$58 + connect \alu_o \$74 [63:0] + connect \src2_or_imm \$71 + connect \src1_or_z \$69 + connect \addr_r \$67 + connect \ldd_r \$65 connect \rst_l_r_rst \cu_issue_i connect \rst_l_s_rst \addr_ok connect \lsd_l_s_lsd \cu_issue_i - connect \sto_l_s_sto \$50 + connect \sto_l_s_sto \$57 connect \wri_l_s_wri \cu_issue_i connect \lod_l_r_lod \ld_ok connect \lod_l_s_lod \reset_i connect \adr_l_s_adr \reset_i - connect \alu_l_r_alu \$29 + connect \alu_l_r_alu \$36 connect \alu_l_s_alu \reset_i connect \st_o \op_is_st connect \ld_o \op_is_ld - connect \stwd_mem_o \$21 - connect \load_mem_o \$19 - connect \op_is_ld \$17 - connect \op_is_st \$15 + connect \stwd_mem_o \$28 + connect \load_mem_o \$26 + connect \op_is_ld \$24 + connect \op_is_st \$22 connect \p_st_go$next \cu_st__go_i - connect \reset_a \$13 - connect \reset_r \$11 - connect \reset_s \$9 - connect \reset_u \$7 - connect \reset_w \$5 - connect \reset_o \$3 - connect \reset_i \$1 + connect \reset_a \$20 + connect \reset_r \$18 + connect \reset_s \$16 + connect \reset_u \$14 + connect \reset_w \$12 + connect \reset_o \$10 + connect \reset_i \$8 end -attribute \src "libresoc.v:128811.1-129398.10" +attribute \src "libresoc.v:131146.1-131733.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:128812.7-128812.20" + attribute \src "libresoc.v:131147.7-131147.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $10\mask[9:9] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $11\mask[10:10] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $12\mask[11:11] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $13\mask[12:12] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $14\mask[13:13] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $15\mask[14:14] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $16\mask[15:15] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $17\mask[16:16] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $18\mask[17:17] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $19\mask[18:18] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $1\mask[0:0] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $20\mask[19:19] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $21\mask[20:20] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $22\mask[21:21] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $23\mask[22:22] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $24\mask[23:23] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $25\mask[24:24] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $26\mask[25:25] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $27\mask[26:26] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $28\mask[27:27] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $29\mask[28:28] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $2\mask[1:1] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $30\mask[29:29] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $31\mask[30:30] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $32\mask[31:31] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $33\mask[32:32] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $34\mask[33:33] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $35\mask[34:34] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $36\mask[35:35] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $37\mask[36:36] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $38\mask[37:37] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $39\mask[38:38] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $3\mask[2:2] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $40\mask[39:39] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $41\mask[40:40] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $42\mask[41:41] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $43\mask[42:42] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $44\mask[43:43] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $45\mask[44:44] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $46\mask[45:45] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $47\mask[46:46] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $48\mask[47:47] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $49\mask[48:48] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $4\mask[3:3] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $50\mask[49:49] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $51\mask[50:50] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $52\mask[51:51] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $53\mask[52:52] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $54\mask[53:53] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $55\mask[54:54] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $56\mask[55:55] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $57\mask[56:56] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $58\mask[57:57] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $59\mask[58:58] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $5\mask[4:4] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $60\mask[59:59] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $61\mask[60:60] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $62\mask[61:61] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $63\mask[62:62] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $64\mask[63:63] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $6\mask[5:5] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $7\mask[6:6] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $8\mask[7:7] - attribute \src "libresoc.v:129010.3-129397.6" + attribute \src "libresoc.v:131345.3-131732.6" wire $9\mask[8:8] - attribute \src "libresoc.v:128946.17-128946.96" - wire $gt$libresoc.v:128946$5937_Y - attribute \src "libresoc.v:128947.18-128947.98" - wire $gt$libresoc.v:128947$5938_Y - attribute \src "libresoc.v:128948.19-128948.99" - wire $gt$libresoc.v:128948$5939_Y - attribute \src "libresoc.v:128949.19-128949.99" - wire $gt$libresoc.v:128949$5940_Y - attribute \src "libresoc.v:128950.19-128950.99" - wire $gt$libresoc.v:128950$5941_Y - attribute \src "libresoc.v:128951.19-128951.99" - wire $gt$libresoc.v:128951$5942_Y - attribute \src "libresoc.v:128952.19-128952.99" - wire $gt$libresoc.v:128952$5943_Y - attribute \src "libresoc.v:128953.19-128953.99" - wire $gt$libresoc.v:128953$5944_Y - attribute \src "libresoc.v:128954.19-128954.99" - wire $gt$libresoc.v:128954$5945_Y - attribute \src "libresoc.v:128955.19-128955.99" - wire $gt$libresoc.v:128955$5946_Y - attribute \src "libresoc.v:128956.19-128956.99" - wire $gt$libresoc.v:128956$5947_Y - attribute \src "libresoc.v:128957.18-128957.97" - wire $gt$libresoc.v:128957$5948_Y - attribute \src "libresoc.v:128958.19-128958.99" - wire $gt$libresoc.v:128958$5949_Y - attribute \src "libresoc.v:128959.19-128959.99" - wire $gt$libresoc.v:128959$5950_Y - attribute \src "libresoc.v:128960.19-128960.99" - wire $gt$libresoc.v:128960$5951_Y - attribute \src "libresoc.v:128961.19-128961.99" - wire $gt$libresoc.v:128961$5952_Y - attribute \src "libresoc.v:128962.19-128962.99" - wire $gt$libresoc.v:128962$5953_Y - attribute \src "libresoc.v:128963.18-128963.97" - wire $gt$libresoc.v:128963$5954_Y - attribute \src "libresoc.v:128964.18-128964.97" - wire $gt$libresoc.v:128964$5955_Y - attribute \src "libresoc.v:128965.18-128965.97" - wire $gt$libresoc.v:128965$5956_Y - attribute \src "libresoc.v:128966.17-128966.96" - wire $gt$libresoc.v:128966$5957_Y - attribute \src "libresoc.v:128967.18-128967.97" - wire $gt$libresoc.v:128967$5958_Y - attribute \src "libresoc.v:128968.18-128968.97" - wire $gt$libresoc.v:128968$5959_Y - attribute \src "libresoc.v:128969.18-128969.97" - wire $gt$libresoc.v:128969$5960_Y - attribute \src "libresoc.v:128970.18-128970.97" - wire $gt$libresoc.v:128970$5961_Y - attribute \src "libresoc.v:128971.18-128971.97" - wire $gt$libresoc.v:128971$5962_Y - attribute \src "libresoc.v:128972.18-128972.97" - wire $gt$libresoc.v:128972$5963_Y - attribute \src "libresoc.v:128973.18-128973.97" - wire $gt$libresoc.v:128973$5964_Y - attribute \src "libresoc.v:128974.18-128974.98" - wire $gt$libresoc.v:128974$5965_Y - attribute \src "libresoc.v:128975.18-128975.98" - wire $gt$libresoc.v:128975$5966_Y - attribute \src "libresoc.v:128976.18-128976.98" - wire $gt$libresoc.v:128976$5967_Y - attribute \src "libresoc.v:128977.17-128977.96" - wire $gt$libresoc.v:128977$5968_Y - attribute \src "libresoc.v:128978.18-128978.98" - wire $gt$libresoc.v:128978$5969_Y - attribute \src "libresoc.v:128979.18-128979.98" - wire $gt$libresoc.v:128979$5970_Y - attribute \src "libresoc.v:128980.18-128980.98" - wire $gt$libresoc.v:128980$5971_Y - attribute \src "libresoc.v:128981.18-128981.98" - wire $gt$libresoc.v:128981$5972_Y - attribute \src "libresoc.v:128982.18-128982.98" - wire $gt$libresoc.v:128982$5973_Y - attribute \src "libresoc.v:128983.18-128983.98" - wire $gt$libresoc.v:128983$5974_Y - attribute \src "libresoc.v:128984.18-128984.98" - wire $gt$libresoc.v:128984$5975_Y - attribute \src "libresoc.v:128985.18-128985.98" - wire $gt$libresoc.v:128985$5976_Y - attribute \src "libresoc.v:128986.18-128986.98" - wire $gt$libresoc.v:128986$5977_Y - attribute \src "libresoc.v:128987.18-128987.98" - wire $gt$libresoc.v:128987$5978_Y - attribute \src "libresoc.v:128988.17-128988.96" - wire $gt$libresoc.v:128988$5979_Y - attribute \src "libresoc.v:128989.18-128989.98" - wire $gt$libresoc.v:128989$5980_Y - attribute \src "libresoc.v:128990.18-128990.98" - wire $gt$libresoc.v:128990$5981_Y - attribute \src "libresoc.v:128991.18-128991.98" - wire $gt$libresoc.v:128991$5982_Y - attribute \src "libresoc.v:128992.18-128992.98" - wire $gt$libresoc.v:128992$5983_Y - attribute \src "libresoc.v:128993.18-128993.98" - wire $gt$libresoc.v:128993$5984_Y - attribute \src "libresoc.v:128994.18-128994.98" - wire $gt$libresoc.v:128994$5985_Y - attribute \src "libresoc.v:128995.18-128995.98" - wire $gt$libresoc.v:128995$5986_Y - attribute \src "libresoc.v:128996.18-128996.98" - wire $gt$libresoc.v:128996$5987_Y - attribute \src "libresoc.v:128997.18-128997.98" - wire $gt$libresoc.v:128997$5988_Y - attribute \src "libresoc.v:128998.18-128998.98" - wire $gt$libresoc.v:128998$5989_Y - attribute \src "libresoc.v:128999.17-128999.96" - wire $gt$libresoc.v:128999$5990_Y - attribute \src "libresoc.v:129000.18-129000.98" - wire $gt$libresoc.v:129000$5991_Y - attribute \src "libresoc.v:129001.18-129001.98" - wire $gt$libresoc.v:129001$5992_Y - attribute \src "libresoc.v:129002.18-129002.98" - wire $gt$libresoc.v:129002$5993_Y - attribute \src "libresoc.v:129003.18-129003.98" - wire $gt$libresoc.v:129003$5994_Y - attribute \src "libresoc.v:129004.18-129004.98" - wire $gt$libresoc.v:129004$5995_Y - attribute \src "libresoc.v:129005.18-129005.98" - wire $gt$libresoc.v:129005$5996_Y - attribute \src "libresoc.v:129006.18-129006.98" - wire $gt$libresoc.v:129006$5997_Y - attribute \src "libresoc.v:129007.18-129007.98" - wire $gt$libresoc.v:129007$5998_Y - attribute \src "libresoc.v:129008.18-129008.98" - wire $gt$libresoc.v:129008$5999_Y - attribute \src "libresoc.v:129009.18-129009.98" - wire $gt$libresoc.v:129009$6000_Y + attribute \src "libresoc.v:131281.17-131281.96" + wire $gt$libresoc.v:131281$6196_Y + attribute \src "libresoc.v:131282.18-131282.98" + wire $gt$libresoc.v:131282$6197_Y + attribute \src "libresoc.v:131283.19-131283.99" + wire $gt$libresoc.v:131283$6198_Y + attribute \src "libresoc.v:131284.19-131284.99" + wire $gt$libresoc.v:131284$6199_Y + attribute \src "libresoc.v:131285.19-131285.99" + wire $gt$libresoc.v:131285$6200_Y + attribute \src "libresoc.v:131286.19-131286.99" + wire $gt$libresoc.v:131286$6201_Y + attribute \src "libresoc.v:131287.19-131287.99" + wire $gt$libresoc.v:131287$6202_Y + attribute \src "libresoc.v:131288.19-131288.99" + wire $gt$libresoc.v:131288$6203_Y + attribute \src "libresoc.v:131289.19-131289.99" + wire $gt$libresoc.v:131289$6204_Y + attribute \src "libresoc.v:131290.19-131290.99" + wire $gt$libresoc.v:131290$6205_Y + attribute \src "libresoc.v:131291.19-131291.99" + wire $gt$libresoc.v:131291$6206_Y + attribute \src "libresoc.v:131292.18-131292.97" + wire $gt$libresoc.v:131292$6207_Y + attribute \src "libresoc.v:131293.19-131293.99" + wire $gt$libresoc.v:131293$6208_Y + attribute \src "libresoc.v:131294.19-131294.99" + wire $gt$libresoc.v:131294$6209_Y + attribute \src "libresoc.v:131295.19-131295.99" + wire $gt$libresoc.v:131295$6210_Y + attribute \src "libresoc.v:131296.19-131296.99" + wire $gt$libresoc.v:131296$6211_Y + attribute \src "libresoc.v:131297.19-131297.99" + wire $gt$libresoc.v:131297$6212_Y + attribute \src "libresoc.v:131298.18-131298.97" + wire $gt$libresoc.v:131298$6213_Y + attribute \src "libresoc.v:131299.18-131299.97" + wire $gt$libresoc.v:131299$6214_Y + attribute \src "libresoc.v:131300.18-131300.97" + wire $gt$libresoc.v:131300$6215_Y + attribute \src "libresoc.v:131301.17-131301.96" + wire $gt$libresoc.v:131301$6216_Y + attribute \src "libresoc.v:131302.18-131302.97" + wire $gt$libresoc.v:131302$6217_Y + attribute \src "libresoc.v:131303.18-131303.97" + wire $gt$libresoc.v:131303$6218_Y + attribute \src "libresoc.v:131304.18-131304.97" + wire $gt$libresoc.v:131304$6219_Y + attribute \src "libresoc.v:131305.18-131305.97" + wire $gt$libresoc.v:131305$6220_Y + attribute \src "libresoc.v:131306.18-131306.97" + wire $gt$libresoc.v:131306$6221_Y + attribute \src "libresoc.v:131307.18-131307.97" + wire $gt$libresoc.v:131307$6222_Y + attribute \src "libresoc.v:131308.18-131308.97" + wire $gt$libresoc.v:131308$6223_Y + attribute \src "libresoc.v:131309.18-131309.98" + wire $gt$libresoc.v:131309$6224_Y + attribute \src "libresoc.v:131310.18-131310.98" + wire $gt$libresoc.v:131310$6225_Y + attribute \src "libresoc.v:131311.18-131311.98" + wire $gt$libresoc.v:131311$6226_Y + attribute \src "libresoc.v:131312.17-131312.96" + wire $gt$libresoc.v:131312$6227_Y + attribute \src "libresoc.v:131313.18-131313.98" + wire $gt$libresoc.v:131313$6228_Y + attribute \src "libresoc.v:131314.18-131314.98" + wire $gt$libresoc.v:131314$6229_Y + attribute \src "libresoc.v:131315.18-131315.98" + wire $gt$libresoc.v:131315$6230_Y + attribute \src "libresoc.v:131316.18-131316.98" + wire $gt$libresoc.v:131316$6231_Y + attribute \src "libresoc.v:131317.18-131317.98" + wire $gt$libresoc.v:131317$6232_Y + attribute \src "libresoc.v:131318.18-131318.98" + wire $gt$libresoc.v:131318$6233_Y + attribute \src "libresoc.v:131319.18-131319.98" + wire $gt$libresoc.v:131319$6234_Y + attribute \src "libresoc.v:131320.18-131320.98" + wire $gt$libresoc.v:131320$6235_Y + attribute \src "libresoc.v:131321.18-131321.98" + wire $gt$libresoc.v:131321$6236_Y + attribute \src "libresoc.v:131322.18-131322.98" + wire $gt$libresoc.v:131322$6237_Y + attribute \src "libresoc.v:131323.17-131323.96" + wire $gt$libresoc.v:131323$6238_Y + attribute \src "libresoc.v:131324.18-131324.98" + wire $gt$libresoc.v:131324$6239_Y + attribute \src "libresoc.v:131325.18-131325.98" + wire $gt$libresoc.v:131325$6240_Y + attribute \src "libresoc.v:131326.18-131326.98" + wire $gt$libresoc.v:131326$6241_Y + attribute \src "libresoc.v:131327.18-131327.98" + wire $gt$libresoc.v:131327$6242_Y + attribute \src "libresoc.v:131328.18-131328.98" + wire $gt$libresoc.v:131328$6243_Y + attribute \src "libresoc.v:131329.18-131329.98" + wire $gt$libresoc.v:131329$6244_Y + attribute \src "libresoc.v:131330.18-131330.98" + wire $gt$libresoc.v:131330$6245_Y + attribute \src "libresoc.v:131331.18-131331.98" + wire $gt$libresoc.v:131331$6246_Y + attribute \src "libresoc.v:131332.18-131332.98" + wire $gt$libresoc.v:131332$6247_Y + attribute \src "libresoc.v:131333.18-131333.98" + wire $gt$libresoc.v:131333$6248_Y + attribute \src "libresoc.v:131334.17-131334.96" + wire $gt$libresoc.v:131334$6249_Y + attribute \src "libresoc.v:131335.18-131335.98" + wire $gt$libresoc.v:131335$6250_Y + attribute \src "libresoc.v:131336.18-131336.98" + wire $gt$libresoc.v:131336$6251_Y + attribute \src "libresoc.v:131337.18-131337.98" + wire $gt$libresoc.v:131337$6252_Y + attribute \src "libresoc.v:131338.18-131338.98" + wire $gt$libresoc.v:131338$6253_Y + attribute \src "libresoc.v:131339.18-131339.98" + wire $gt$libresoc.v:131339$6254_Y + attribute \src "libresoc.v:131340.18-131340.98" + wire $gt$libresoc.v:131340$6255_Y + attribute \src "libresoc.v:131341.18-131341.98" + wire $gt$libresoc.v:131341$6256_Y + attribute \src "libresoc.v:131342.18-131342.98" + wire $gt$libresoc.v:131342$6257_Y + attribute \src "libresoc.v:131343.18-131343.98" + wire $gt$libresoc.v:131343$6258_Y + attribute \src "libresoc.v:131344.18-131344.98" + wire $gt$libresoc.v:131344$6259_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" @@ -207043,14 +212416,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$99 - attribute \src "libresoc.v:128812.7-128812.15" + attribute \src "libresoc.v:131147.7-131147.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128946$5937 + cell $gt $gt$libresoc.v:131281$6196 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207058,10 +212431,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:128946$5937_Y + connect \Y $gt$libresoc.v:131281$6196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128947$5938 + cell $gt $gt$libresoc.v:131282$6197 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207069,10 +212442,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:128947$5938_Y + connect \Y $gt$libresoc.v:131282$6197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128948$5939 + cell $gt $gt$libresoc.v:131283$6198 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207080,10 +212453,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:128948$5939_Y + connect \Y $gt$libresoc.v:131283$6198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128949$5940 + cell $gt $gt$libresoc.v:131284$6199 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207091,10 +212464,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:128949$5940_Y + connect \Y $gt$libresoc.v:131284$6199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128950$5941 + cell $gt $gt$libresoc.v:131285$6200 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207102,10 +212475,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:128950$5941_Y + connect \Y $gt$libresoc.v:131285$6200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128951$5942 + cell $gt $gt$libresoc.v:131286$6201 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207113,10 +212486,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:128951$5942_Y + connect \Y $gt$libresoc.v:131286$6201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128952$5943 + cell $gt $gt$libresoc.v:131287$6202 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207124,10 +212497,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:128952$5943_Y + connect \Y $gt$libresoc.v:131287$6202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128953$5944 + cell $gt $gt$libresoc.v:131288$6203 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207135,10 +212508,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:128953$5944_Y + connect \Y $gt$libresoc.v:131288$6203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128954$5945 + cell $gt $gt$libresoc.v:131289$6204 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207146,10 +212519,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:128954$5945_Y + connect \Y $gt$libresoc.v:131289$6204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128955$5946 + cell $gt $gt$libresoc.v:131290$6205 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207157,10 +212530,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:128955$5946_Y + connect \Y $gt$libresoc.v:131290$6205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128956$5947 + cell $gt $gt$libresoc.v:131291$6206 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207168,10 +212541,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:128956$5947_Y + connect \Y $gt$libresoc.v:131291$6206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128957$5948 + cell $gt $gt$libresoc.v:131292$6207 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207179,10 +212552,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:128957$5948_Y + connect \Y $gt$libresoc.v:131292$6207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128958$5949 + cell $gt $gt$libresoc.v:131293$6208 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207190,10 +212563,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:128958$5949_Y + connect \Y $gt$libresoc.v:131293$6208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128959$5950 + cell $gt $gt$libresoc.v:131294$6209 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207201,10 +212574,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:128959$5950_Y + connect \Y $gt$libresoc.v:131294$6209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128960$5951 + cell $gt $gt$libresoc.v:131295$6210 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207212,10 +212585,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:128960$5951_Y + connect \Y $gt$libresoc.v:131295$6210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128961$5952 + cell $gt $gt$libresoc.v:131296$6211 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207223,10 +212596,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:128961$5952_Y + connect \Y $gt$libresoc.v:131296$6211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128962$5953 + cell $gt $gt$libresoc.v:131297$6212 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207234,10 +212607,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:128962$5953_Y + connect \Y $gt$libresoc.v:131297$6212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128963$5954 + cell $gt $gt$libresoc.v:131298$6213 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207245,10 +212618,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:128963$5954_Y + connect \Y $gt$libresoc.v:131298$6213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128964$5955 + cell $gt $gt$libresoc.v:131299$6214 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207256,10 +212629,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:128964$5955_Y + connect \Y $gt$libresoc.v:131299$6214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128965$5956 + cell $gt $gt$libresoc.v:131300$6215 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207267,10 +212640,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:128965$5956_Y + connect \Y $gt$libresoc.v:131300$6215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128966$5957 + cell $gt $gt$libresoc.v:131301$6216 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207278,10 +212651,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:128966$5957_Y + connect \Y $gt$libresoc.v:131301$6216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128967$5958 + cell $gt $gt$libresoc.v:131302$6217 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207289,10 +212662,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:128967$5958_Y + connect \Y $gt$libresoc.v:131302$6217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128968$5959 + cell $gt $gt$libresoc.v:131303$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207300,10 +212673,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:128968$5959_Y + connect \Y $gt$libresoc.v:131303$6218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128969$5960 + cell $gt $gt$libresoc.v:131304$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207311,10 +212684,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:128969$5960_Y + connect \Y $gt$libresoc.v:131304$6219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128970$5961 + cell $gt $gt$libresoc.v:131305$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207322,10 +212695,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:128970$5961_Y + connect \Y $gt$libresoc.v:131305$6220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128971$5962 + cell $gt $gt$libresoc.v:131306$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207333,10 +212706,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:128971$5962_Y + connect \Y $gt$libresoc.v:131306$6221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128972$5963 + cell $gt $gt$libresoc.v:131307$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207344,10 +212717,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:128972$5963_Y + connect \Y $gt$libresoc.v:131307$6222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128973$5964 + cell $gt $gt$libresoc.v:131308$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207355,10 +212728,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:128973$5964_Y + connect \Y $gt$libresoc.v:131308$6223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128974$5965 + cell $gt $gt$libresoc.v:131309$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207366,10 +212739,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:128974$5965_Y + connect \Y $gt$libresoc.v:131309$6224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128975$5966 + cell $gt $gt$libresoc.v:131310$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207377,10 +212750,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:128975$5966_Y + connect \Y $gt$libresoc.v:131310$6225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128976$5967 + cell $gt $gt$libresoc.v:131311$6226 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207388,10 +212761,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:128976$5967_Y + connect \Y $gt$libresoc.v:131311$6226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128977$5968 + cell $gt $gt$libresoc.v:131312$6227 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207399,10 +212772,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:128977$5968_Y + connect \Y $gt$libresoc.v:131312$6227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128978$5969 + cell $gt $gt$libresoc.v:131313$6228 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207410,10 +212783,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:128978$5969_Y + connect \Y $gt$libresoc.v:131313$6228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128979$5970 + cell $gt $gt$libresoc.v:131314$6229 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207421,10 +212794,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:128979$5970_Y + connect \Y $gt$libresoc.v:131314$6229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128980$5971 + cell $gt $gt$libresoc.v:131315$6230 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207432,10 +212805,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:128980$5971_Y + connect \Y $gt$libresoc.v:131315$6230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128981$5972 + cell $gt $gt$libresoc.v:131316$6231 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207443,10 +212816,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:128981$5972_Y + connect \Y $gt$libresoc.v:131316$6231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128982$5973 + cell $gt $gt$libresoc.v:131317$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207454,10 +212827,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:128982$5973_Y + connect \Y $gt$libresoc.v:131317$6232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128983$5974 + cell $gt $gt$libresoc.v:131318$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207465,10 +212838,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:128983$5974_Y + connect \Y $gt$libresoc.v:131318$6233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128984$5975 + cell $gt $gt$libresoc.v:131319$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207476,10 +212849,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:128984$5975_Y + connect \Y $gt$libresoc.v:131319$6234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128985$5976 + cell $gt $gt$libresoc.v:131320$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207487,10 +212860,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:128985$5976_Y + connect \Y $gt$libresoc.v:131320$6235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128986$5977 + cell $gt $gt$libresoc.v:131321$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207498,10 +212871,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:128986$5977_Y + connect \Y $gt$libresoc.v:131321$6236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128987$5978 + cell $gt $gt$libresoc.v:131322$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207509,10 +212882,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:128987$5978_Y + connect \Y $gt$libresoc.v:131322$6237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128988$5979 + cell $gt $gt$libresoc.v:131323$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207520,10 +212893,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:128988$5979_Y + connect \Y $gt$libresoc.v:131323$6238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128989$5980 + cell $gt $gt$libresoc.v:131324$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207531,10 +212904,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:128989$5980_Y + connect \Y $gt$libresoc.v:131324$6239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128990$5981 + cell $gt $gt$libresoc.v:131325$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207542,10 +212915,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:128990$5981_Y + connect \Y $gt$libresoc.v:131325$6240_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128991$5982 + cell $gt $gt$libresoc.v:131326$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207553,10 +212926,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:128991$5982_Y + connect \Y $gt$libresoc.v:131326$6241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128992$5983 + cell $gt $gt$libresoc.v:131327$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207564,10 +212937,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:128992$5983_Y + connect \Y $gt$libresoc.v:131327$6242_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128993$5984 + cell $gt $gt$libresoc.v:131328$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207575,10 +212948,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:128993$5984_Y + connect \Y $gt$libresoc.v:131328$6243_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128994$5985 + cell $gt $gt$libresoc.v:131329$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207586,10 +212959,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:128994$5985_Y + connect \Y $gt$libresoc.v:131329$6244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128995$5986 + cell $gt $gt$libresoc.v:131330$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207597,10 +212970,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:128995$5986_Y + connect \Y $gt$libresoc.v:131330$6245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128996$5987 + cell $gt $gt$libresoc.v:131331$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207608,10 +212981,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:128996$5987_Y + connect \Y $gt$libresoc.v:131331$6246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128997$5988 + cell $gt $gt$libresoc.v:131332$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207619,10 +212992,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:128997$5988_Y + connect \Y $gt$libresoc.v:131332$6247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128998$5989 + cell $gt $gt$libresoc.v:131333$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207630,10 +213003,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:128998$5989_Y + connect \Y $gt$libresoc.v:131333$6248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:128999$5990 + cell $gt $gt$libresoc.v:131334$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207641,10 +213014,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:128999$5990_Y + connect \Y $gt$libresoc.v:131334$6249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129000$5991 + cell $gt $gt$libresoc.v:131335$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207652,10 +213025,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:129000$5991_Y + connect \Y $gt$libresoc.v:131335$6250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129001$5992 + cell $gt $gt$libresoc.v:131336$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207663,10 +213036,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:129001$5992_Y + connect \Y $gt$libresoc.v:131336$6251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129002$5993 + cell $gt $gt$libresoc.v:131337$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207674,10 +213047,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:129002$5993_Y + connect \Y $gt$libresoc.v:131337$6252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129003$5994 + cell $gt $gt$libresoc.v:131338$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207685,10 +213058,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:129003$5994_Y + connect \Y $gt$libresoc.v:131338$6253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129004$5995 + cell $gt $gt$libresoc.v:131339$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207696,10 +213069,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:129004$5995_Y + connect \Y $gt$libresoc.v:131339$6254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129005$5996 + cell $gt $gt$libresoc.v:131340$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207707,10 +213080,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:129005$5996_Y + connect \Y $gt$libresoc.v:131340$6255_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129006$5997 + cell $gt $gt$libresoc.v:131341$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207718,10 +213091,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:129006$5997_Y + connect \Y $gt$libresoc.v:131341$6256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129007$5998 + cell $gt $gt$libresoc.v:131342$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207729,10 +213102,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:129007$5998_Y + connect \Y $gt$libresoc.v:131342$6257_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129008$5999 + cell $gt $gt$libresoc.v:131343$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207740,10 +213113,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:129008$5999_Y + connect \Y $gt$libresoc.v:131343$6258_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:129009$6000 + cell $gt $gt$libresoc.v:131344$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -207751,18 +213124,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:129009$6000_Y + connect \Y $gt$libresoc.v:131344$6259_Y end - attribute \src "libresoc.v:128812.7-128812.20" - process $proc$libresoc.v:128812$6002 + attribute \src "libresoc.v:131147.7-131147.20" + process $proc$libresoc.v:131147$6261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129010.3-129397.6" - process $proc$libresoc.v:129010$6001 + attribute \src "libresoc.v:131345.3-131732.6" + process $proc$libresoc.v:131345$6260 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -207829,9 +213202,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:129011.5-129011.29" + attribute \src "libresoc.v:131346.5-131346.29" switch \initial - attribute \src "libresoc.v:129011.9-129011.17" + attribute \src "libresoc.v:131346.9-131346.17" case 1'1 case end @@ -208414,86 +213787,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:128946$5937_Y - connect \$99 $gt$libresoc.v:128947$5938_Y - connect \$101 $gt$libresoc.v:128948$5939_Y - connect \$103 $gt$libresoc.v:128949$5940_Y - connect \$105 $gt$libresoc.v:128950$5941_Y - connect \$107 $gt$libresoc.v:128951$5942_Y - connect \$109 $gt$libresoc.v:128952$5943_Y - connect \$111 $gt$libresoc.v:128953$5944_Y - connect \$113 $gt$libresoc.v:128954$5945_Y - connect \$115 $gt$libresoc.v:128955$5946_Y - connect \$117 $gt$libresoc.v:128956$5947_Y - connect \$11 $gt$libresoc.v:128957$5948_Y - connect \$119 $gt$libresoc.v:128958$5949_Y - connect \$121 $gt$libresoc.v:128959$5950_Y - connect \$123 $gt$libresoc.v:128960$5951_Y - connect \$125 $gt$libresoc.v:128961$5952_Y - connect \$127 $gt$libresoc.v:128962$5953_Y - connect \$13 $gt$libresoc.v:128963$5954_Y - connect \$15 $gt$libresoc.v:128964$5955_Y - connect \$17 $gt$libresoc.v:128965$5956_Y - connect \$1 $gt$libresoc.v:128966$5957_Y - connect \$19 $gt$libresoc.v:128967$5958_Y - connect \$21 $gt$libresoc.v:128968$5959_Y - connect \$23 $gt$libresoc.v:128969$5960_Y - connect \$25 $gt$libresoc.v:128970$5961_Y - connect \$27 $gt$libresoc.v:128971$5962_Y - connect \$29 $gt$libresoc.v:128972$5963_Y - connect \$31 $gt$libresoc.v:128973$5964_Y - connect \$33 $gt$libresoc.v:128974$5965_Y - connect \$35 $gt$libresoc.v:128975$5966_Y - connect \$37 $gt$libresoc.v:128976$5967_Y - connect \$3 $gt$libresoc.v:128977$5968_Y - connect \$39 $gt$libresoc.v:128978$5969_Y - connect \$41 $gt$libresoc.v:128979$5970_Y - connect \$43 $gt$libresoc.v:128980$5971_Y - connect \$45 $gt$libresoc.v:128981$5972_Y - connect \$47 $gt$libresoc.v:128982$5973_Y - connect \$49 $gt$libresoc.v:128983$5974_Y - connect \$51 $gt$libresoc.v:128984$5975_Y - connect \$53 $gt$libresoc.v:128985$5976_Y - connect \$55 $gt$libresoc.v:128986$5977_Y - connect \$57 $gt$libresoc.v:128987$5978_Y - connect \$5 $gt$libresoc.v:128988$5979_Y - connect \$59 $gt$libresoc.v:128989$5980_Y - connect \$61 $gt$libresoc.v:128990$5981_Y - connect \$63 $gt$libresoc.v:128991$5982_Y - connect \$65 $gt$libresoc.v:128992$5983_Y - connect \$67 $gt$libresoc.v:128993$5984_Y - connect \$69 $gt$libresoc.v:128994$5985_Y - connect \$71 $gt$libresoc.v:128995$5986_Y - connect \$73 $gt$libresoc.v:128996$5987_Y - connect \$75 $gt$libresoc.v:128997$5988_Y - connect \$77 $gt$libresoc.v:128998$5989_Y - connect \$7 $gt$libresoc.v:128999$5990_Y - connect \$79 $gt$libresoc.v:129000$5991_Y - connect \$81 $gt$libresoc.v:129001$5992_Y - connect \$83 $gt$libresoc.v:129002$5993_Y - connect \$85 $gt$libresoc.v:129003$5994_Y - connect \$87 $gt$libresoc.v:129004$5995_Y - connect \$89 $gt$libresoc.v:129005$5996_Y - connect \$91 $gt$libresoc.v:129006$5997_Y - connect \$93 $gt$libresoc.v:129007$5998_Y - connect \$95 $gt$libresoc.v:129008$5999_Y - connect \$97 $gt$libresoc.v:129009$6000_Y + connect \$9 $gt$libresoc.v:131281$6196_Y + connect \$99 $gt$libresoc.v:131282$6197_Y + connect \$101 $gt$libresoc.v:131283$6198_Y + connect \$103 $gt$libresoc.v:131284$6199_Y + connect \$105 $gt$libresoc.v:131285$6200_Y + connect \$107 $gt$libresoc.v:131286$6201_Y + connect \$109 $gt$libresoc.v:131287$6202_Y + connect \$111 $gt$libresoc.v:131288$6203_Y + connect \$113 $gt$libresoc.v:131289$6204_Y + connect \$115 $gt$libresoc.v:131290$6205_Y + connect \$117 $gt$libresoc.v:131291$6206_Y + connect \$11 $gt$libresoc.v:131292$6207_Y + connect \$119 $gt$libresoc.v:131293$6208_Y + connect \$121 $gt$libresoc.v:131294$6209_Y + connect \$123 $gt$libresoc.v:131295$6210_Y + connect \$125 $gt$libresoc.v:131296$6211_Y + connect \$127 $gt$libresoc.v:131297$6212_Y + connect \$13 $gt$libresoc.v:131298$6213_Y + connect \$15 $gt$libresoc.v:131299$6214_Y + connect \$17 $gt$libresoc.v:131300$6215_Y + connect \$1 $gt$libresoc.v:131301$6216_Y + connect \$19 $gt$libresoc.v:131302$6217_Y + connect \$21 $gt$libresoc.v:131303$6218_Y + connect \$23 $gt$libresoc.v:131304$6219_Y + connect \$25 $gt$libresoc.v:131305$6220_Y + connect \$27 $gt$libresoc.v:131306$6221_Y + connect \$29 $gt$libresoc.v:131307$6222_Y + connect \$31 $gt$libresoc.v:131308$6223_Y + connect \$33 $gt$libresoc.v:131309$6224_Y + connect \$35 $gt$libresoc.v:131310$6225_Y + connect \$37 $gt$libresoc.v:131311$6226_Y + connect \$3 $gt$libresoc.v:131312$6227_Y + connect \$39 $gt$libresoc.v:131313$6228_Y + connect \$41 $gt$libresoc.v:131314$6229_Y + connect \$43 $gt$libresoc.v:131315$6230_Y + connect \$45 $gt$libresoc.v:131316$6231_Y + connect \$47 $gt$libresoc.v:131317$6232_Y + connect \$49 $gt$libresoc.v:131318$6233_Y + connect \$51 $gt$libresoc.v:131319$6234_Y + connect \$53 $gt$libresoc.v:131320$6235_Y + connect \$55 $gt$libresoc.v:131321$6236_Y + connect \$57 $gt$libresoc.v:131322$6237_Y + connect \$5 $gt$libresoc.v:131323$6238_Y + connect \$59 $gt$libresoc.v:131324$6239_Y + connect \$61 $gt$libresoc.v:131325$6240_Y + connect \$63 $gt$libresoc.v:131326$6241_Y + connect \$65 $gt$libresoc.v:131327$6242_Y + connect \$67 $gt$libresoc.v:131328$6243_Y + connect \$69 $gt$libresoc.v:131329$6244_Y + connect \$71 $gt$libresoc.v:131330$6245_Y + connect \$73 $gt$libresoc.v:131331$6246_Y + connect \$75 $gt$libresoc.v:131332$6247_Y + connect \$77 $gt$libresoc.v:131333$6248_Y + connect \$7 $gt$libresoc.v:131334$6249_Y + connect \$79 $gt$libresoc.v:131335$6250_Y + connect \$81 $gt$libresoc.v:131336$6251_Y + connect \$83 $gt$libresoc.v:131337$6252_Y + connect \$85 $gt$libresoc.v:131338$6253_Y + connect \$87 $gt$libresoc.v:131339$6254_Y + connect \$89 $gt$libresoc.v:131340$6255_Y + connect \$91 $gt$libresoc.v:131341$6256_Y + connect \$93 $gt$libresoc.v:131342$6257_Y + connect \$95 $gt$libresoc.v:131343$6258_Y + connect \$97 $gt$libresoc.v:131344$6259_Y end -attribute \src "libresoc.v:129402.1-129431.10" +attribute \src "libresoc.v:131737.1-131766.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:129426.17-129426.101" - wire width 64 $extend$libresoc.v:129426$6006_Y - attribute \src "libresoc.v:129426.17-129426.101" - wire width 64 $pos$libresoc.v:129426$6007_Y - attribute \src "libresoc.v:129423.17-129423.111" - wire width 20 $sshl$libresoc.v:129423$6003_Y - attribute \src "libresoc.v:129425.17-129425.113" - wire width 32 $sshl$libresoc.v:129425$6005_Y - attribute \src "libresoc.v:129424.17-129424.107" - wire width 21 $sub$libresoc.v:129424$6004_Y + attribute \src "libresoc.v:131761.17-131761.101" + wire width 64 $extend$libresoc.v:131761$6265_Y + attribute \src "libresoc.v:131761.17-131761.101" + wire width 64 $pos$libresoc.v:131761$6266_Y + attribute \src "libresoc.v:131758.17-131758.111" + wire width 20 $sshl$libresoc.v:131758$6262_Y + attribute \src "libresoc.v:131760.17-131760.113" + wire width 32 $sshl$libresoc.v:131760$6264_Y + attribute \src "libresoc.v:131759.17-131759.107" + wire width 21 $sub$libresoc.v:131759$6263_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -208515,23 +213888,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:129426$6006 + cell $pos $extend$libresoc.v:131761$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:129426$6006_Y + connect \Y $extend$libresoc.v:131761$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:129426$6007 + cell $pos $pos$libresoc.v:131761$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:129426$6006_Y - connect \Y $pos$libresoc.v:129426$6007_Y + connect \A $extend$libresoc.v:131761$6265_Y + connect \Y $pos$libresoc.v:131761$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:129423$6003 + cell $sshl $sshl$libresoc.v:131758$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -208539,10 +213912,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:129423$6003_Y + connect \Y $sshl$libresoc.v:131758$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:129425$6005 + cell $sshl $sshl$libresoc.v:131760$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -208550,10 +213923,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:129425$6005_Y + connect \Y $sshl$libresoc.v:131760$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:129424$6004 + cell $sub $sub$libresoc.v:131759$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -208561,48 +213934,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:129424$6004_Y + connect \Y $sub$libresoc.v:131759$6263_Y end - connect \$2 $sshl$libresoc.v:129423$6003_Y - connect \$4 $sub$libresoc.v:129424$6004_Y - connect \$7 $sshl$libresoc.v:129425$6005_Y - connect \$6 $pos$libresoc.v:129426$6007_Y + connect \$2 $sshl$libresoc.v:131758$6262_Y + connect \$4 $sub$libresoc.v:131759$6263_Y + connect \$7 $sshl$libresoc.v:131760$6264_Y + connect \$6 $pos$libresoc.v:131761$6266_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:129435.1-129493.10" +attribute \src "libresoc.v:131770.1-131828.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:129436.7-129436.20" + attribute \src "libresoc.v:131771.7-131771.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129481.3-129489.6" - wire $0\q_int$next[0:0]$6018 - attribute \src "libresoc.v:129479.3-129480.27" + attribute \src "libresoc.v:131816.3-131824.6" + wire $0\q_int$next[0:0]$6277 + attribute \src "libresoc.v:131814.3-131815.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:129481.3-129489.6" - wire $1\q_int$next[0:0]$6019 - attribute \src "libresoc.v:129458.7-129458.19" + attribute \src "libresoc.v:131816.3-131824.6" + wire $1\q_int$next[0:0]$6278 + attribute \src "libresoc.v:131793.7-131793.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:129471.17-129471.96" - wire $and$libresoc.v:129471$6008_Y - attribute \src "libresoc.v:129476.17-129476.96" - wire $and$libresoc.v:129476$6013_Y - attribute \src "libresoc.v:129473.18-129473.93" - wire $not$libresoc.v:129473$6010_Y - attribute \src "libresoc.v:129475.17-129475.92" - wire $not$libresoc.v:129475$6012_Y - attribute \src "libresoc.v:129478.17-129478.92" - wire $not$libresoc.v:129478$6015_Y - attribute \src "libresoc.v:129472.18-129472.98" - wire $or$libresoc.v:129472$6009_Y - attribute \src "libresoc.v:129474.18-129474.99" - wire $or$libresoc.v:129474$6011_Y - attribute \src "libresoc.v:129477.17-129477.97" - wire $or$libresoc.v:129477$6014_Y + attribute \src "libresoc.v:131806.17-131806.96" + wire $and$libresoc.v:131806$6267_Y + attribute \src "libresoc.v:131811.17-131811.96" + wire $and$libresoc.v:131811$6272_Y + attribute \src "libresoc.v:131808.18-131808.93" + wire $not$libresoc.v:131808$6269_Y + attribute \src "libresoc.v:131810.17-131810.92" + wire $not$libresoc.v:131810$6271_Y + attribute \src "libresoc.v:131813.17-131813.92" + wire $not$libresoc.v:131813$6274_Y + attribute \src "libresoc.v:131807.18-131807.98" + wire $or$libresoc.v:131807$6268_Y + attribute \src "libresoc.v:131809.18-131809.99" + wire $or$libresoc.v:131809$6270_Y + attribute \src "libresoc.v:131812.17-131812.97" + wire $or$libresoc.v:131812$6273_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -208619,11 +213992,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:129436.7-129436.15" + attribute \src "libresoc.v:131771.7-131771.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -208640,7 +214013,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:129471$6008 + cell $and $and$libresoc.v:131806$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208648,10 +214021,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:129471$6008_Y + connect \Y $and$libresoc.v:131806$6267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:129476$6013 + cell $and $and$libresoc.v:131811$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208659,34 +214032,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:129476$6013_Y + connect \Y $and$libresoc.v:131811$6272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:129473$6010 + cell $not $not$libresoc.v:131808$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:129473$6010_Y + connect \Y $not$libresoc.v:131808$6269_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:129475$6012 + cell $not $not$libresoc.v:131810$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:129475$6012_Y + connect \Y $not$libresoc.v:131810$6271_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:129478$6015 + cell $not $not$libresoc.v:131813$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:129478$6015_Y + connect \Y $not$libresoc.v:131813$6274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:129472$6009 + cell $or $or$libresoc.v:131807$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208694,10 +214067,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:129472$6009_Y + connect \Y $or$libresoc.v:131807$6268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:129474$6011 + cell $or $or$libresoc.v:131809$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208705,10 +214078,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:129474$6011_Y + connect \Y $or$libresoc.v:131809$6270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:129477$6014 + cell $or $or$libresoc.v:131812$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208716,39 +214089,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:129477$6014_Y + connect \Y $or$libresoc.v:131812$6273_Y end - attribute \src "libresoc.v:129436.7-129436.20" - process $proc$libresoc.v:129436$6020 + attribute \src "libresoc.v:131771.7-131771.20" + process $proc$libresoc.v:131771$6279 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129458.7-129458.19" - process $proc$libresoc.v:129458$6021 + attribute \src "libresoc.v:131793.7-131793.19" + process $proc$libresoc.v:131793$6280 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:129479.3-129480.27" - process $proc$libresoc.v:129479$6016 + attribute \src "libresoc.v:131814.3-131815.27" + process $proc$libresoc.v:131814$6275 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:129481.3-129489.6" - process $proc$libresoc.v:129481$6017 + attribute \src "libresoc.v:131816.3-131824.6" + process $proc$libresoc.v:131816$6276 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6018 $1\q_int$next[0:0]$6019 - attribute \src "libresoc.v:129482.5-129482.29" + assign $0\q_int$next[0:0]$6277 $1\q_int$next[0:0]$6278 + attribute \src "libresoc.v:131817.5-131817.29" switch \initial - attribute \src "libresoc.v:129482.9-129482.17" + attribute \src "libresoc.v:131817.9-131817.17" case 1'1 case end @@ -208757,494 +214130,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6019 1'0 + assign $1\q_int$next[0:0]$6278 1'0 case - assign $1\q_int$next[0:0]$6019 \$5 + assign $1\q_int$next[0:0]$6278 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6018 + update \q_int$next $0\q_int$next[0:0]$6277 end - connect \$9 $and$libresoc.v:129471$6008_Y - connect \$11 $or$libresoc.v:129472$6009_Y - connect \$13 $not$libresoc.v:129473$6010_Y - connect \$15 $or$libresoc.v:129474$6011_Y - connect \$1 $not$libresoc.v:129475$6012_Y - connect \$3 $and$libresoc.v:129476$6013_Y - connect \$5 $or$libresoc.v:129477$6014_Y - connect \$7 $not$libresoc.v:129478$6015_Y + connect \$9 $and$libresoc.v:131806$6267_Y + connect \$11 $or$libresoc.v:131807$6268_Y + connect \$13 $not$libresoc.v:131808$6269_Y + connect \$15 $or$libresoc.v:131809$6270_Y + connect \$1 $not$libresoc.v:131810$6271_Y + connect \$3 $and$libresoc.v:131811$6272_Y + connect \$5 $or$libresoc.v:131812$6273_Y + connect \$7 $not$libresoc.v:131813$6274_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:129497.1-130611.10" +attribute \src "libresoc.v:131832.1-132946.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:130236.3-130237.24" + attribute \src "libresoc.v:132571.3-132572.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:130234.3-130235.44" + attribute \src "libresoc.v:132569.3-132570.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:130541.3-130549.6" - wire $0\alu_l_r_alu$next[0:0]$6222 - attribute \src "libresoc.v:130158.3-130159.39" + attribute \src "libresoc.v:132876.3-132884.6" + wire $0\alu_l_r_alu$next[0:0]$6481 + attribute \src "libresoc.v:132493.3-132494.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6151 - attribute \src "libresoc.v:130208.3-130209.83" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6410 + attribute \src "libresoc.v:132543.3-132544.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 - attribute \src "libresoc.v:130178.3-130179.81" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 + attribute \src "libresoc.v:132513.3-132514.81" wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 - attribute \src "libresoc.v:130180.3-130181.95" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 + attribute \src "libresoc.v:132515.3-132516.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 - attribute \src "libresoc.v:130182.3-130183.91" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 + attribute \src "libresoc.v:132517.3-132518.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 - attribute \src "libresoc.v:130196.3-130197.89" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 + attribute \src "libresoc.v:132531.3-132532.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6156 - attribute \src "libresoc.v:130210.3-130211.75" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6415 + attribute \src "libresoc.v:132545.3-132546.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 - attribute \src "libresoc.v:130176.3-130177.85" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 + attribute \src "libresoc.v:132511.3-132512.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 - attribute \src "libresoc.v:130192.3-130193.85" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 + attribute \src "libresoc.v:132527.3-132528.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 - attribute \src "libresoc.v:130198.3-130199.87" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 + attribute \src "libresoc.v:132533.3-132534.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 - attribute \src "libresoc.v:130204.3-130205.83" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 + attribute \src "libresoc.v:132539.3-132540.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 - attribute \src "libresoc.v:130206.3-130207.85" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 + attribute \src "libresoc.v:132541.3-132542.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 - attribute \src "libresoc.v:130188.3-130189.79" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 + attribute \src "libresoc.v:132523.3-132524.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 - attribute \src "libresoc.v:130190.3-130191.79" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 + attribute \src "libresoc.v:132525.3-132526.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 - attribute \src "libresoc.v:130202.3-130203.91" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 + attribute \src "libresoc.v:132537.3-132538.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 - attribute \src "libresoc.v:130186.3-130187.79" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 + attribute \src "libresoc.v:132521.3-132522.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 - attribute \src "libresoc.v:130184.3-130185.79" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 + attribute \src "libresoc.v:132519.3-132520.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 - attribute \src "libresoc.v:130200.3-130201.85" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 + attribute \src "libresoc.v:132535.3-132536.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 - attribute \src "libresoc.v:130194.3-130195.79" + attribute \src "libresoc.v:132754.3-132792.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 + attribute \src "libresoc.v:132529.3-132530.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130532.3-130540.6" - wire $0\alui_l_r_alui$next[0:0]$6219 - attribute \src "libresoc.v:130160.3-130161.43" + attribute \src "libresoc.v:132867.3-132875.6" + wire $0\alui_l_r_alui$next[0:0]$6478 + attribute \src "libresoc.v:132495.3-132496.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:130458.3-130479.6" - wire width 64 $0\data_r0__o$next[63:0]$6194 - attribute \src "libresoc.v:130172.3-130173.37" + attribute \src "libresoc.v:132793.3-132814.6" + wire width 64 $0\data_r0__o$next[63:0]$6453 + attribute \src "libresoc.v:132507.3-132508.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:130458.3-130479.6" - wire $0\data_r0__o_ok$next[0:0]$6195 - attribute \src "libresoc.v:130174.3-130175.43" + attribute \src "libresoc.v:132793.3-132814.6" + wire $0\data_r0__o_ok$next[0:0]$6454 + attribute \src "libresoc.v:132509.3-132510.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:130480.3-130501.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6202 - attribute \src "libresoc.v:130168.3-130169.43" + attribute \src "libresoc.v:132815.3-132836.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6461 + attribute \src "libresoc.v:132503.3-132504.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:130480.3-130501.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6203 - attribute \src "libresoc.v:130170.3-130171.49" + attribute \src "libresoc.v:132815.3-132836.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6462 + attribute \src "libresoc.v:132505.3-132506.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:130550.3-130559.6" + attribute \src "libresoc.v:132885.3-132894.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:130560.3-130569.6" + attribute \src "libresoc.v:132895.3-132904.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:129498.7-129498.20" + attribute \src "libresoc.v:131833.7-131833.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130374.3-130382.6" - wire $0\opc_l_r_opc$next[0:0]$6136 - attribute \src "libresoc.v:130220.3-130221.39" + attribute \src "libresoc.v:132709.3-132717.6" + wire $0\opc_l_r_opc$next[0:0]$6395 + attribute \src "libresoc.v:132555.3-132556.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130365.3-130373.6" - wire $0\opc_l_s_opc$next[0:0]$6133 - attribute \src "libresoc.v:130222.3-130223.39" + attribute \src "libresoc.v:132700.3-132708.6" + wire $0\opc_l_s_opc$next[0:0]$6392 + attribute \src "libresoc.v:132557.3-132558.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130570.3-130578.6" - wire width 2 $0\prev_wr_go$next[1:0]$6227 - attribute \src "libresoc.v:130232.3-130233.37" + attribute \src "libresoc.v:132905.3-132913.6" + wire width 2 $0\prev_wr_go$next[1:0]$6486 + attribute \src "libresoc.v:132567.3-132568.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:130319.3-130328.6" + attribute \src "libresoc.v:132654.3-132663.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:130410.3-130418.6" - wire width 2 $0\req_l_r_req$next[1:0]$6148 - attribute \src "libresoc.v:130212.3-130213.39" + attribute \src "libresoc.v:132745.3-132753.6" + wire width 2 $0\req_l_r_req$next[1:0]$6407 + attribute \src "libresoc.v:132547.3-132548.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:130401.3-130409.6" - wire width 2 $0\req_l_s_req$next[1:0]$6145 - attribute \src "libresoc.v:130214.3-130215.39" + attribute \src "libresoc.v:132736.3-132744.6" + wire width 2 $0\req_l_s_req$next[1:0]$6404 + attribute \src "libresoc.v:132549.3-132550.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:130338.3-130346.6" - wire $0\rok_l_r_rdok$next[0:0]$6124 - attribute \src "libresoc.v:130228.3-130229.41" + attribute \src "libresoc.v:132673.3-132681.6" + wire $0\rok_l_r_rdok$next[0:0]$6383 + attribute \src "libresoc.v:132563.3-132564.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130329.3-130337.6" - wire $0\rok_l_s_rdok$next[0:0]$6121 - attribute \src "libresoc.v:130230.3-130231.41" + attribute \src "libresoc.v:132664.3-132672.6" + wire $0\rok_l_s_rdok$next[0:0]$6380 + attribute \src "libresoc.v:132565.3-132566.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130356.3-130364.6" - wire $0\rst_l_r_rst$next[0:0]$6130 - attribute \src "libresoc.v:130224.3-130225.39" + attribute \src "libresoc.v:132691.3-132699.6" + wire $0\rst_l_r_rst$next[0:0]$6389 + attribute \src "libresoc.v:132559.3-132560.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130347.3-130355.6" - wire $0\rst_l_s_rst$next[0:0]$6127 - attribute \src "libresoc.v:130226.3-130227.39" + attribute \src "libresoc.v:132682.3-132690.6" + wire $0\rst_l_s_rst$next[0:0]$6386 + attribute \src "libresoc.v:132561.3-132562.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130392.3-130400.6" - wire width 3 $0\src_l_r_src$next[2:0]$6142 - attribute \src "libresoc.v:130216.3-130217.39" + attribute \src "libresoc.v:132727.3-132735.6" + wire width 3 $0\src_l_r_src$next[2:0]$6401 + attribute \src "libresoc.v:132551.3-132552.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:130383.3-130391.6" - wire width 3 $0\src_l_s_src$next[2:0]$6139 - attribute \src "libresoc.v:130218.3-130219.39" + attribute \src "libresoc.v:132718.3-132726.6" + wire width 3 $0\src_l_s_src$next[2:0]$6398 + attribute \src "libresoc.v:132553.3-132554.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:130502.3-130511.6" - wire width 64 $0\src_r0$next[63:0]$6210 - attribute \src "libresoc.v:130166.3-130167.29" + attribute \src "libresoc.v:132837.3-132846.6" + wire width 64 $0\src_r0$next[63:0]$6469 + attribute \src "libresoc.v:132501.3-132502.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:130512.3-130521.6" - wire width 64 $0\src_r1$next[63:0]$6213 - attribute \src "libresoc.v:130164.3-130165.29" + attribute \src "libresoc.v:132847.3-132856.6" + wire width 64 $0\src_r1$next[63:0]$6472 + attribute \src "libresoc.v:132499.3-132500.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:130522.3-130531.6" - wire $0\src_r2$next[0:0]$6216 - attribute \src "libresoc.v:130162.3-130163.29" + attribute \src "libresoc.v:132857.3-132866.6" + wire $0\src_r2$next[0:0]$6475 + attribute \src "libresoc.v:132497.3-132498.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:129616.7-129616.24" + attribute \src "libresoc.v:131951.7-131951.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:129626.7-129626.26" + attribute \src "libresoc.v:131961.7-131961.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:130541.3-130549.6" - wire $1\alu_l_r_alu$next[0:0]$6223 - attribute \src "libresoc.v:129634.7-129634.25" + attribute \src "libresoc.v:132876.3-132884.6" + wire $1\alu_l_r_alu$next[0:0]$6482 + attribute \src "libresoc.v:131969.7-131969.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 - attribute \src "libresoc.v:129642.13-129642.53" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 + attribute \src "libresoc.v:131977.13-131977.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 - attribute \src "libresoc.v:129659.14-129659.56" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 + attribute \src "libresoc.v:131994.14-131994.56" wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 - attribute \src "libresoc.v:129663.14-129663.76" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 + attribute \src "libresoc.v:131998.14-131998.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 - attribute \src "libresoc.v:129667.7-129667.51" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 + attribute \src "libresoc.v:132002.7-132002.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 - attribute \src "libresoc.v:129675.13-129675.56" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 + attribute \src "libresoc.v:132010.13-132010.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6174 - attribute \src "libresoc.v:129679.14-129679.51" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6433 + attribute \src "libresoc.v:132014.14-132014.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 - attribute \src "libresoc.v:129757.13-129757.55" + attribute \src "libresoc.v:132754.3-132792.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 + attribute \src "libresoc.v:132092.13-132092.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 - attribute \src "libresoc.v:129761.7-129761.48" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 + attribute \src "libresoc.v:132096.7-132096.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 - attribute \src "libresoc.v:129765.7-129765.49" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 + attribute \src "libresoc.v:132100.7-132100.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 - attribute \src "libresoc.v:129769.7-129769.47" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 + attribute \src "libresoc.v:132104.7-132104.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 - attribute \src "libresoc.v:129773.7-129773.48" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 + attribute \src "libresoc.v:132108.7-132108.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 - attribute \src "libresoc.v:129777.7-129777.45" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 + attribute \src "libresoc.v:132112.7-132112.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 - attribute \src "libresoc.v:129781.7-129781.45" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 + attribute \src "libresoc.v:132116.7-132116.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 - attribute \src "libresoc.v:129785.7-129785.51" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 + attribute \src "libresoc.v:132120.7-132120.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 - attribute \src "libresoc.v:129789.7-129789.45" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 + attribute \src "libresoc.v:132124.7-132124.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 - attribute \src "libresoc.v:129793.7-129793.45" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 + attribute \src "libresoc.v:132128.7-132128.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 - attribute \src "libresoc.v:129797.7-129797.48" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 + attribute \src "libresoc.v:132132.7-132132.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 - attribute \src "libresoc.v:129801.7-129801.45" + attribute \src "libresoc.v:132754.3-132792.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 + attribute \src "libresoc.v:132136.7-132136.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:130532.3-130540.6" - wire $1\alui_l_r_alui$next[0:0]$6220 - attribute \src "libresoc.v:129827.7-129827.27" + attribute \src "libresoc.v:132867.3-132875.6" + wire $1\alui_l_r_alui$next[0:0]$6479 + attribute \src "libresoc.v:132162.7-132162.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:130458.3-130479.6" - wire width 64 $1\data_r0__o$next[63:0]$6196 - attribute \src "libresoc.v:129861.14-129861.47" + attribute \src "libresoc.v:132793.3-132814.6" + wire width 64 $1\data_r0__o$next[63:0]$6455 + attribute \src "libresoc.v:132196.14-132196.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:130458.3-130479.6" - wire $1\data_r0__o_ok$next[0:0]$6197 - attribute \src "libresoc.v:129865.7-129865.27" + attribute \src "libresoc.v:132793.3-132814.6" + wire $1\data_r0__o_ok$next[0:0]$6456 + attribute \src "libresoc.v:132200.7-132200.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:130480.3-130501.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6204 - attribute \src "libresoc.v:129869.13-129869.33" + attribute \src "libresoc.v:132815.3-132836.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6463 + attribute \src "libresoc.v:132204.13-132204.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:130480.3-130501.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6205 - attribute \src "libresoc.v:129873.7-129873.30" + attribute \src "libresoc.v:132815.3-132836.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6464 + attribute \src "libresoc.v:132208.7-132208.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:130550.3-130559.6" + attribute \src "libresoc.v:132885.3-132894.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:130560.3-130569.6" + attribute \src "libresoc.v:132895.3-132904.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:130374.3-130382.6" - wire $1\opc_l_r_opc$next[0:0]$6137 - attribute \src "libresoc.v:129887.7-129887.25" + attribute \src "libresoc.v:132709.3-132717.6" + wire $1\opc_l_r_opc$next[0:0]$6396 + attribute \src "libresoc.v:132222.7-132222.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130365.3-130373.6" - wire $1\opc_l_s_opc$next[0:0]$6134 - attribute \src "libresoc.v:129891.7-129891.25" + attribute \src "libresoc.v:132700.3-132708.6" + wire $1\opc_l_s_opc$next[0:0]$6393 + attribute \src "libresoc.v:132226.7-132226.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130570.3-130578.6" - wire width 2 $1\prev_wr_go$next[1:0]$6228 - attribute \src "libresoc.v:130022.13-130022.30" + attribute \src "libresoc.v:132905.3-132913.6" + wire width 2 $1\prev_wr_go$next[1:0]$6487 + attribute \src "libresoc.v:132357.13-132357.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:130319.3-130328.6" + attribute \src "libresoc.v:132654.3-132663.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:130410.3-130418.6" - wire width 2 $1\req_l_r_req$next[1:0]$6149 - attribute \src "libresoc.v:130030.13-130030.31" + attribute \src "libresoc.v:132745.3-132753.6" + wire width 2 $1\req_l_r_req$next[1:0]$6408 + attribute \src "libresoc.v:132365.13-132365.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:130401.3-130409.6" - wire width 2 $1\req_l_s_req$next[1:0]$6146 - attribute \src "libresoc.v:130034.13-130034.31" + attribute \src "libresoc.v:132736.3-132744.6" + wire width 2 $1\req_l_s_req$next[1:0]$6405 + attribute \src "libresoc.v:132369.13-132369.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:130338.3-130346.6" - wire $1\rok_l_r_rdok$next[0:0]$6125 - attribute \src "libresoc.v:130046.7-130046.26" + attribute \src "libresoc.v:132673.3-132681.6" + wire $1\rok_l_r_rdok$next[0:0]$6384 + attribute \src "libresoc.v:132381.7-132381.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:130329.3-130337.6" - wire $1\rok_l_s_rdok$next[0:0]$6122 - attribute \src "libresoc.v:130050.7-130050.26" + attribute \src "libresoc.v:132664.3-132672.6" + wire $1\rok_l_s_rdok$next[0:0]$6381 + attribute \src "libresoc.v:132385.7-132385.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:130356.3-130364.6" - wire $1\rst_l_r_rst$next[0:0]$6131 - attribute \src "libresoc.v:130054.7-130054.25" + attribute \src "libresoc.v:132691.3-132699.6" + wire $1\rst_l_r_rst$next[0:0]$6390 + attribute \src "libresoc.v:132389.7-132389.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:130347.3-130355.6" - wire $1\rst_l_s_rst$next[0:0]$6128 - attribute \src "libresoc.v:130058.7-130058.25" + attribute \src "libresoc.v:132682.3-132690.6" + wire $1\rst_l_s_rst$next[0:0]$6387 + attribute \src "libresoc.v:132393.7-132393.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:130392.3-130400.6" - wire width 3 $1\src_l_r_src$next[2:0]$6143 - attribute \src "libresoc.v:130072.13-130072.31" + attribute \src "libresoc.v:132727.3-132735.6" + wire width 3 $1\src_l_r_src$next[2:0]$6402 + attribute \src "libresoc.v:132407.13-132407.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:130383.3-130391.6" - wire width 3 $1\src_l_s_src$next[2:0]$6140 - attribute \src "libresoc.v:130076.13-130076.31" + attribute \src "libresoc.v:132718.3-132726.6" + wire width 3 $1\src_l_s_src$next[2:0]$6399 + attribute \src "libresoc.v:132411.13-132411.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:130502.3-130511.6" - wire width 64 $1\src_r0$next[63:0]$6211 - attribute \src "libresoc.v:130084.14-130084.43" + attribute \src "libresoc.v:132837.3-132846.6" + wire width 64 $1\src_r0$next[63:0]$6470 + attribute \src "libresoc.v:132419.14-132419.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:130512.3-130521.6" - wire width 64 $1\src_r1$next[63:0]$6214 - attribute \src "libresoc.v:130088.14-130088.43" + attribute \src "libresoc.v:132847.3-132856.6" + wire width 64 $1\src_r1$next[63:0]$6473 + attribute \src "libresoc.v:132423.14-132423.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:130522.3-130531.6" - wire $1\src_r2$next[0:0]$6217 - attribute \src "libresoc.v:130092.7-130092.20" + attribute \src "libresoc.v:132857.3-132866.6" + wire $1\src_r2$next[0:0]$6476 + attribute \src "libresoc.v:132427.7-132427.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:130419.3-130457.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 - attribute \src "libresoc.v:130419.3-130457.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 - attribute \src "libresoc.v:130419.3-130457.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 - attribute \src "libresoc.v:130419.3-130457.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 - attribute \src "libresoc.v:130419.3-130457.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 - attribute \src "libresoc.v:130419.3-130457.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 - attribute \src "libresoc.v:130458.3-130479.6" - wire width 64 $2\data_r0__o$next[63:0]$6198 - attribute \src "libresoc.v:130458.3-130479.6" - wire $2\data_r0__o_ok$next[0:0]$6199 - attribute \src "libresoc.v:130480.3-130501.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6206 - attribute \src "libresoc.v:130480.3-130501.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6207 - attribute \src "libresoc.v:130458.3-130479.6" - wire $3\data_r0__o_ok$next[0:0]$6200 - attribute \src "libresoc.v:130480.3-130501.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6208 - attribute \src "libresoc.v:130101.17-130101.109" - wire $and$libresoc.v:130101$6022_Y - attribute \src "libresoc.v:130102.18-130102.130" - wire width 3 $and$libresoc.v:130102$6023_Y - attribute \src "libresoc.v:130104.19-130104.114" - wire width 3 $and$libresoc.v:130104$6025_Y - attribute \src "libresoc.v:130105.19-130105.125" - wire $and$libresoc.v:130105$6026_Y - attribute \src "libresoc.v:130106.19-130106.125" - wire $and$libresoc.v:130106$6027_Y - attribute \src "libresoc.v:130107.19-130107.133" - wire width 2 $and$libresoc.v:130107$6028_Y - attribute \src "libresoc.v:130108.19-130108.121" - wire width 2 $and$libresoc.v:130108$6029_Y - attribute \src "libresoc.v:130109.19-130109.127" - wire $and$libresoc.v:130109$6030_Y - attribute \src "libresoc.v:130110.19-130110.127" - wire $and$libresoc.v:130110$6031_Y - attribute \src "libresoc.v:130112.18-130112.98" - wire $and$libresoc.v:130112$6033_Y - attribute \src "libresoc.v:130114.18-130114.100" - wire $and$libresoc.v:130114$6035_Y - attribute \src "libresoc.v:130115.17-130115.123" - wire $and$libresoc.v:130115$6036_Y - attribute \src "libresoc.v:130116.18-130116.138" - wire width 2 $and$libresoc.v:130116$6037_Y - attribute \src "libresoc.v:130118.18-130118.119" - wire width 2 $and$libresoc.v:130118$6039_Y - attribute \src "libresoc.v:130121.18-130121.116" - wire $and$libresoc.v:130121$6042_Y - attribute \src "libresoc.v:130126.18-130126.113" - wire $and$libresoc.v:130126$6047_Y - attribute \src "libresoc.v:130127.18-130127.125" - wire width 2 $and$libresoc.v:130127$6048_Y - attribute \src "libresoc.v:130129.18-130129.112" - wire $and$libresoc.v:130129$6050_Y - attribute \src "libresoc.v:130132.18-130132.130" - wire $and$libresoc.v:130132$6053_Y - attribute \src "libresoc.v:130133.18-130133.130" - wire $and$libresoc.v:130133$6054_Y - attribute \src "libresoc.v:130134.18-130134.117" - wire $and$libresoc.v:130134$6055_Y - attribute \src "libresoc.v:130139.18-130139.134" - wire $and$libresoc.v:130139$6060_Y - attribute \src "libresoc.v:130140.18-130140.124" - wire width 2 $and$libresoc.v:130140$6061_Y - attribute \src "libresoc.v:130143.18-130143.116" - wire $and$libresoc.v:130143$6064_Y - attribute \src "libresoc.v:130144.18-130144.119" - wire $and$libresoc.v:130144$6065_Y - attribute \src "libresoc.v:130153.18-130153.138" - wire $and$libresoc.v:130153$6074_Y - attribute \src "libresoc.v:130154.18-130154.136" - wire $and$libresoc.v:130154$6075_Y - attribute \src "libresoc.v:130155.18-130155.149" - wire width 3 $and$libresoc.v:130155$6076_Y - attribute \src "libresoc.v:130128.18-130128.113" - wire $eq$libresoc.v:130128$6049_Y - attribute \src "libresoc.v:130130.18-130130.119" - wire $eq$libresoc.v:130130$6051_Y - attribute \src "libresoc.v:130103.19-130103.115" - wire width 3 $not$libresoc.v:130103$6024_Y - attribute \src "libresoc.v:130111.18-130111.97" - wire $not$libresoc.v:130111$6032_Y - attribute \src "libresoc.v:130113.18-130113.99" - wire $not$libresoc.v:130113$6034_Y - attribute \src "libresoc.v:130117.18-130117.113" - wire width 2 $not$libresoc.v:130117$6038_Y - attribute \src "libresoc.v:130120.18-130120.106" - wire $not$libresoc.v:130120$6041_Y - attribute \src "libresoc.v:130125.18-130125.124" - wire $not$libresoc.v:130125$6046_Y - attribute \src "libresoc.v:130131.17-130131.113" - wire width 3 $not$libresoc.v:130131$6052_Y - attribute \src "libresoc.v:130156.18-130156.133" - wire $not$libresoc.v:130156$6077_Y - attribute \src "libresoc.v:130157.18-130157.139" - wire $not$libresoc.v:130157$6078_Y - attribute \src "libresoc.v:130124.18-130124.112" - wire $or$libresoc.v:130124$6045_Y - attribute \src "libresoc.v:130135.18-130135.122" - wire $or$libresoc.v:130135$6056_Y - attribute \src "libresoc.v:130136.18-130136.124" - wire $or$libresoc.v:130136$6057_Y - attribute \src "libresoc.v:130137.18-130137.142" - wire width 2 $or$libresoc.v:130137$6058_Y - attribute \src "libresoc.v:130138.18-130138.155" - wire width 3 $or$libresoc.v:130138$6059_Y - attribute \src "libresoc.v:130141.18-130141.120" - wire width 2 $or$libresoc.v:130141$6062_Y - attribute \src "libresoc.v:130142.17-130142.117" - wire width 3 $or$libresoc.v:130142$6063_Y - attribute \src "libresoc.v:130148.17-130148.104" - wire $reduce_and$libresoc.v:130148$6069_Y - attribute \src "libresoc.v:130119.18-130119.106" - wire $reduce_or$libresoc.v:130119$6040_Y - attribute \src "libresoc.v:130122.18-130122.113" - wire $reduce_or$libresoc.v:130122$6043_Y - attribute \src "libresoc.v:130123.18-130123.112" - wire $reduce_or$libresoc.v:130123$6044_Y - attribute \src "libresoc.v:130145.18-130145.162" - wire $ternary$libresoc.v:130145$6066_Y - attribute \src "libresoc.v:130146.18-130146.163" - wire width 64 $ternary$libresoc.v:130146$6067_Y - attribute \src "libresoc.v:130147.18-130147.168" - wire $ternary$libresoc.v:130147$6068_Y - attribute \src "libresoc.v:130149.18-130149.188" - wire width 64 $ternary$libresoc.v:130149$6070_Y - attribute \src "libresoc.v:130150.18-130150.115" - wire width 64 $ternary$libresoc.v:130150$6071_Y - attribute \src "libresoc.v:130151.18-130151.125" - wire width 64 $ternary$libresoc.v:130151$6072_Y - attribute \src "libresoc.v:130152.18-130152.118" - wire $ternary$libresoc.v:130152$6073_Y + attribute \src "libresoc.v:132754.3-132792.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 + attribute \src "libresoc.v:132754.3-132792.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 + attribute \src "libresoc.v:132754.3-132792.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 + attribute \src "libresoc.v:132754.3-132792.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 + attribute \src "libresoc.v:132754.3-132792.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 + attribute \src "libresoc.v:132754.3-132792.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 + attribute \src "libresoc.v:132793.3-132814.6" + wire width 64 $2\data_r0__o$next[63:0]$6457 + attribute \src "libresoc.v:132793.3-132814.6" + wire $2\data_r0__o_ok$next[0:0]$6458 + attribute \src "libresoc.v:132815.3-132836.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6465 + attribute \src "libresoc.v:132815.3-132836.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6466 + attribute \src "libresoc.v:132793.3-132814.6" + wire $3\data_r0__o_ok$next[0:0]$6459 + attribute \src "libresoc.v:132815.3-132836.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6467 + attribute \src "libresoc.v:132436.17-132436.109" + wire $and$libresoc.v:132436$6281_Y + attribute \src "libresoc.v:132437.18-132437.130" + wire width 3 $and$libresoc.v:132437$6282_Y + attribute \src "libresoc.v:132439.19-132439.114" + wire width 3 $and$libresoc.v:132439$6284_Y + attribute \src "libresoc.v:132440.19-132440.125" + wire $and$libresoc.v:132440$6285_Y + attribute \src "libresoc.v:132441.19-132441.125" + wire $and$libresoc.v:132441$6286_Y + attribute \src "libresoc.v:132442.19-132442.133" + wire width 2 $and$libresoc.v:132442$6287_Y + attribute \src "libresoc.v:132443.19-132443.121" + wire width 2 $and$libresoc.v:132443$6288_Y + attribute \src "libresoc.v:132444.19-132444.127" + wire $and$libresoc.v:132444$6289_Y + attribute \src "libresoc.v:132445.19-132445.127" + wire $and$libresoc.v:132445$6290_Y + attribute \src "libresoc.v:132447.18-132447.98" + wire $and$libresoc.v:132447$6292_Y + attribute \src "libresoc.v:132449.18-132449.100" + wire $and$libresoc.v:132449$6294_Y + attribute \src "libresoc.v:132450.17-132450.123" + wire $and$libresoc.v:132450$6295_Y + attribute \src "libresoc.v:132451.18-132451.138" + wire width 2 $and$libresoc.v:132451$6296_Y + attribute \src "libresoc.v:132453.18-132453.119" + wire width 2 $and$libresoc.v:132453$6298_Y + attribute \src "libresoc.v:132456.18-132456.116" + wire $and$libresoc.v:132456$6301_Y + attribute \src "libresoc.v:132461.18-132461.113" + wire $and$libresoc.v:132461$6306_Y + attribute \src "libresoc.v:132462.18-132462.125" + wire width 2 $and$libresoc.v:132462$6307_Y + attribute \src "libresoc.v:132464.18-132464.112" + wire $and$libresoc.v:132464$6309_Y + attribute \src "libresoc.v:132467.18-132467.130" + wire $and$libresoc.v:132467$6312_Y + attribute \src "libresoc.v:132468.18-132468.130" + wire $and$libresoc.v:132468$6313_Y + attribute \src "libresoc.v:132469.18-132469.117" + wire $and$libresoc.v:132469$6314_Y + attribute \src "libresoc.v:132474.18-132474.134" + wire $and$libresoc.v:132474$6319_Y + attribute \src "libresoc.v:132475.18-132475.124" + wire width 2 $and$libresoc.v:132475$6320_Y + attribute \src "libresoc.v:132478.18-132478.116" + wire $and$libresoc.v:132478$6323_Y + attribute \src "libresoc.v:132479.18-132479.119" + wire $and$libresoc.v:132479$6324_Y + attribute \src "libresoc.v:132488.18-132488.138" + wire $and$libresoc.v:132488$6333_Y + attribute \src "libresoc.v:132489.18-132489.136" + wire $and$libresoc.v:132489$6334_Y + attribute \src "libresoc.v:132490.18-132490.149" + wire width 3 $and$libresoc.v:132490$6335_Y + attribute \src "libresoc.v:132463.18-132463.113" + wire $eq$libresoc.v:132463$6308_Y + attribute \src "libresoc.v:132465.18-132465.119" + wire $eq$libresoc.v:132465$6310_Y + attribute \src "libresoc.v:132438.19-132438.115" + wire width 3 $not$libresoc.v:132438$6283_Y + attribute \src "libresoc.v:132446.18-132446.97" + wire $not$libresoc.v:132446$6291_Y + attribute \src "libresoc.v:132448.18-132448.99" + wire $not$libresoc.v:132448$6293_Y + attribute \src "libresoc.v:132452.18-132452.113" + wire width 2 $not$libresoc.v:132452$6297_Y + attribute \src "libresoc.v:132455.18-132455.106" + wire $not$libresoc.v:132455$6300_Y + attribute \src "libresoc.v:132460.18-132460.124" + wire $not$libresoc.v:132460$6305_Y + attribute \src "libresoc.v:132466.17-132466.113" + wire width 3 $not$libresoc.v:132466$6311_Y + attribute \src "libresoc.v:132491.18-132491.133" + wire $not$libresoc.v:132491$6336_Y + attribute \src "libresoc.v:132492.18-132492.139" + wire $not$libresoc.v:132492$6337_Y + attribute \src "libresoc.v:132459.18-132459.112" + wire $or$libresoc.v:132459$6304_Y + attribute \src "libresoc.v:132470.18-132470.122" + wire $or$libresoc.v:132470$6315_Y + attribute \src "libresoc.v:132471.18-132471.124" + wire $or$libresoc.v:132471$6316_Y + attribute \src "libresoc.v:132472.18-132472.142" + wire width 2 $or$libresoc.v:132472$6317_Y + attribute \src "libresoc.v:132473.18-132473.155" + wire width 3 $or$libresoc.v:132473$6318_Y + attribute \src "libresoc.v:132476.18-132476.120" + wire width 2 $or$libresoc.v:132476$6321_Y + attribute \src "libresoc.v:132477.17-132477.117" + wire width 3 $or$libresoc.v:132477$6322_Y + attribute \src "libresoc.v:132483.17-132483.104" + wire $reduce_and$libresoc.v:132483$6328_Y + attribute \src "libresoc.v:132454.18-132454.106" + wire $reduce_or$libresoc.v:132454$6299_Y + attribute \src "libresoc.v:132457.18-132457.113" + wire $reduce_or$libresoc.v:132457$6302_Y + attribute \src "libresoc.v:132458.18-132458.112" + wire $reduce_or$libresoc.v:132458$6303_Y + attribute \src "libresoc.v:132480.18-132480.162" + wire $ternary$libresoc.v:132480$6325_Y + attribute \src "libresoc.v:132481.18-132481.163" + wire width 64 $ternary$libresoc.v:132481$6326_Y + attribute \src "libresoc.v:132482.18-132482.168" + wire $ternary$libresoc.v:132482$6327_Y + attribute \src "libresoc.v:132484.18-132484.188" + wire width 64 $ternary$libresoc.v:132484$6329_Y + attribute \src "libresoc.v:132485.18-132485.115" + wire width 64 $ternary$libresoc.v:132485$6330_Y + attribute \src "libresoc.v:132486.18-132486.125" + wire width 64 $ternary$libresoc.v:132486$6331_Y + attribute \src "libresoc.v:132487.18-132487.118" + wire $ternary$libresoc.v:132487$6332_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -209385,7 +214758,7 @@ module \logical0 wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_logical0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \alu_logical0_logical_op__data_len @@ -209554,7 +214927,7 @@ module \logical0 wire \alu_logical0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_logical0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_logical0_p_ready_o @@ -209578,32 +214951,32 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 33 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o + wire output 21 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i + wire input 20 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 23 \cu_rd__go_i + wire width 3 input 24 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 22 \cu_rd__rel_o + wire width 3 output 23 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 21 \cu_rdmaskn_i + wire width 3 input 22 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 29 \cu_wr__go_i + wire width 2 input 30 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 28 \cu_wr__rel_o + wire width 2 output 29 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 2 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -209623,13 +214996,13 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r1__cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o + wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "libresoc.v:129498.7-129498.15" + wire width 4 output 33 \dest2_o + attribute \src "libresoc.v:131833.7-131833.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -209641,7 +215014,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_logical0__data_len + wire width 4 input 18 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -209656,19 +215029,19 @@ module \logical0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_logical0__fn_unit + wire width 12 input 3 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_logical0__imm_data__data + wire width 64 input 4 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_logical0__imm_data__ok + wire input 5 \oper_i_alu_logical0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_logical0__input_carry + wire width 2 input 12 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_logical0__insn + wire width 32 input 19 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -209744,29 +215117,29 @@ module \logical0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_logical0__insn_type + wire width 7 input 2 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_logical0__invert_in + wire input 10 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_logical0__invert_out + wire input 13 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_logical0__is_32bit + wire input 16 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_logical0__is_signed + wire input 17 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_logical0__oe__oe + wire input 8 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_logical0__oe__ok + wire input 9 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_logical0__output_carry + wire input 15 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_logical0__rc__ok + wire input 7 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_logical0__rc__rc + wire input 6 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_logical0__write_cr0 + wire input 14 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_logical0__zero_a + wire input 11 \oper_i_alu_logical0__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 2 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -209810,11 +215183,11 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i + wire width 64 input 25 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i + wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 26 \src3_i + wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -209848,7 +215221,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:130101$6022 + cell $and $and$libresoc.v:132436$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209856,10 +215229,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:130101$6022_Y + connect \Y $and$libresoc.v:132436$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130102$6023 + cell $and $and$libresoc.v:132437$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209867,10 +215240,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:130102$6023_Y + connect \Y $and$libresoc.v:132437$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130104$6025 + cell $and $and$libresoc.v:132439$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -209878,10 +215251,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:130104$6025_Y + connect \Y $and$libresoc.v:132439$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130105$6026 + cell $and $and$libresoc.v:132440$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209889,10 +215262,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130105$6026_Y + connect \Y $and$libresoc.v:132440$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:130106$6027 + cell $and $and$libresoc.v:132441$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209900,10 +215273,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:130106$6027_Y + connect \Y $and$libresoc.v:132441$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130107$6028 + cell $and $and$libresoc.v:132442$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209911,10 +215284,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:130107$6028_Y + connect \Y $and$libresoc.v:132442$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:130108$6029 + cell $and $and$libresoc.v:132443$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209922,10 +215295,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130108$6029_Y + connect \Y $and$libresoc.v:132443$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130109$6030 + cell $and $and$libresoc.v:132444$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209933,10 +215306,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130109$6030_Y + connect \Y $and$libresoc.v:132444$6289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:130110$6031 + cell $and $and$libresoc.v:132445$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209944,10 +215317,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:130110$6031_Y + connect \Y $and$libresoc.v:132445$6290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:130112$6033 + cell $and $and$libresoc.v:132447$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209955,10 +215328,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:130112$6033_Y + connect \Y $and$libresoc.v:132447$6292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:130114$6035 + cell $and $and$libresoc.v:132449$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209966,10 +215339,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:130114$6035_Y + connect \Y $and$libresoc.v:132449$6294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:130115$6036 + cell $and $and$libresoc.v:132450$6295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -209977,10 +215350,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:130115$6036_Y + connect \Y $and$libresoc.v:132450$6295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:130116$6037 + cell $and $and$libresoc.v:132451$6296 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209988,10 +215361,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130116$6037_Y + connect \Y $and$libresoc.v:132451$6296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130118$6039 + cell $and $and$libresoc.v:132453$6298 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -209999,10 +215372,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:130118$6039_Y + connect \Y $and$libresoc.v:132453$6298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:130121$6042 + cell $and $and$libresoc.v:132456$6301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210010,10 +215383,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:130121$6042_Y + connect \Y $and$libresoc.v:132456$6301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:130126$6047 + cell $and $and$libresoc.v:132461$6306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210021,10 +215394,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:130126$6047_Y + connect \Y $and$libresoc.v:132461$6306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130127$6048 + cell $and $and$libresoc.v:132462$6307 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210032,10 +215405,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130127$6048_Y + connect \Y $and$libresoc.v:132462$6307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:130129$6050 + cell $and $and$libresoc.v:132464$6309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210043,10 +215416,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:130129$6050_Y + connect \Y $and$libresoc.v:132464$6309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130132$6053 + cell $and $and$libresoc.v:132467$6312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210054,10 +215427,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:130132$6053_Y + connect \Y $and$libresoc.v:132467$6312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130133$6054 + cell $and $and$libresoc.v:132468$6313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210065,10 +215438,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:130133$6054_Y + connect \Y $and$libresoc.v:132468$6313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:130134$6055 + cell $and $and$libresoc.v:132469$6314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210076,10 +215449,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:130134$6055_Y + connect \Y $and$libresoc.v:132469$6314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:130139$6060 + cell $and $and$libresoc.v:132474$6319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210087,10 +215460,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:130139$6060_Y + connect \Y $and$libresoc.v:132474$6319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:130140$6061 + cell $and $and$libresoc.v:132475$6320 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210098,10 +215471,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:130140$6061_Y + connect \Y $and$libresoc.v:132475$6320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130143$6064 + cell $and $and$libresoc.v:132478$6323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210109,10 +215482,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130143$6064_Y + connect \Y $and$libresoc.v:132478$6323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:130144$6065 + cell $and $and$libresoc.v:132479$6324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210120,10 +215493,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:130144$6065_Y + connect \Y $and$libresoc.v:132479$6324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:130153$6074 + cell $and $and$libresoc.v:132488$6333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210131,10 +215504,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:130153$6074_Y + connect \Y $and$libresoc.v:132488$6333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:130154$6075 + cell $and $and$libresoc.v:132489$6334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210142,10 +215515,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:130154$6075_Y + connect \Y $and$libresoc.v:132489$6334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:130155$6076 + cell $and $and$libresoc.v:132490$6335 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -210153,10 +215526,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:130155$6076_Y + connect \Y $and$libresoc.v:132490$6335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:130128$6049 + cell $eq $eq$libresoc.v:132463$6308 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210164,10 +215537,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:130128$6049_Y + connect \Y $eq$libresoc.v:132463$6308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:130130$6051 + cell $eq $eq$libresoc.v:132465$6310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210175,82 +215548,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:130130$6051_Y + connect \Y $eq$libresoc.v:132465$6310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:130103$6024 + cell $not $not$libresoc.v:132438$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:130103$6024_Y + connect \Y $not$libresoc.v:132438$6283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:130111$6032 + cell $not $not$libresoc.v:132446$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:130111$6032_Y + connect \Y $not$libresoc.v:132446$6291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:130113$6034 + cell $not $not$libresoc.v:132448$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:130113$6034_Y + connect \Y $not$libresoc.v:132448$6293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130117$6038 + cell $not $not$libresoc.v:132452$6297 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:130117$6038_Y + connect \Y $not$libresoc.v:132452$6297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:130120$6041 + cell $not $not$libresoc.v:132455$6300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:130120$6041_Y + connect \Y $not$libresoc.v:132455$6300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:130125$6046 + cell $not $not$libresoc.v:132460$6305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:130125$6046_Y + connect \Y $not$libresoc.v:132460$6305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:130131$6052 + cell $not $not$libresoc.v:132466$6311 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:130131$6052_Y + connect \Y $not$libresoc.v:132466$6311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130156$6077 + cell $not $not$libresoc.v:132491$6336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:130156$6077_Y + connect \Y $not$libresoc.v:132491$6336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:130157$6078 + cell $not $not$libresoc.v:132492$6337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:130157$6078_Y + connect \Y $not$libresoc.v:132492$6337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:130124$6045 + cell $or $or$libresoc.v:132459$6304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210258,10 +215631,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:130124$6045_Y + connect \Y $or$libresoc.v:132459$6304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:130135$6056 + cell $or $or$libresoc.v:132470$6315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210269,10 +215642,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130135$6056_Y + connect \Y $or$libresoc.v:132470$6315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:130136$6057 + cell $or $or$libresoc.v:132471$6316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -210280,10 +215653,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:130136$6057_Y + connect \Y $or$libresoc.v:132471$6316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:130137$6058 + cell $or $or$libresoc.v:132472$6317 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210291,10 +215664,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130137$6058_Y + connect \Y $or$libresoc.v:132472$6317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:130138$6059 + cell $or $or$libresoc.v:132473$6318 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -210302,10 +215675,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:130138$6059_Y + connect \Y $or$libresoc.v:132473$6318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:130141$6062 + cell $or $or$libresoc.v:132476$6321 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -210313,10 +215686,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:130141$6062_Y + connect \Y $or$libresoc.v:132476$6321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:130142$6063 + cell $or $or$libresoc.v:132477$6322 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -210324,99 +215697,99 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:130142$6063_Y + connect \Y $or$libresoc.v:132477$6322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:130148$6069 + cell $reduce_and $reduce_and$libresoc.v:132483$6328 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:130148$6069_Y + connect \Y $reduce_and$libresoc.v:132483$6328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:130119$6040 + cell $reduce_or $reduce_or$libresoc.v:132454$6299 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:130119$6040_Y + connect \Y $reduce_or$libresoc.v:132454$6299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130122$6043 + cell $reduce_or $reduce_or$libresoc.v:132457$6302 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:130122$6043_Y + connect \Y $reduce_or$libresoc.v:132457$6302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:130123$6044 + cell $reduce_or $reduce_or$libresoc.v:132458$6303 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:130123$6044_Y + connect \Y $reduce_or$libresoc.v:132458$6303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130145$6066 + cell $mux $ternary$libresoc.v:132480$6325 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130145$6066_Y + connect \Y $ternary$libresoc.v:132480$6325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130146$6067 + cell $mux $ternary$libresoc.v:132481$6326 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:130146$6067_Y + connect \Y $ternary$libresoc.v:132481$6326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:130147$6068 + cell $mux $ternary$libresoc.v:132482$6327 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130147$6068_Y + connect \Y $ternary$libresoc.v:132482$6327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:130149$6070 + cell $mux $ternary$libresoc.v:132484$6329 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:130149$6070_Y + connect \Y $ternary$libresoc.v:132484$6329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130150$6071 + cell $mux $ternary$libresoc.v:132485$6330 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:130150$6071_Y + connect \Y $ternary$libresoc.v:132485$6330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130151$6072 + cell $mux $ternary$libresoc.v:132486$6331 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:130151$6072_Y + connect \Y $ternary$libresoc.v:132486$6331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130152$6073 + cell $mux $ternary$libresoc.v:132487$6332 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:130152$6073_Y + connect \Y $ternary$libresoc.v:132487$6332_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:130238.14-130244.4" - cell \alu_l$58 \alu_l + attribute \src "libresoc.v:132573.14-132579.4" + cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -210424,7 +215797,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:130245.16-130277.4" + attribute \src "libresoc.v:132580.16-132612.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -210459,8 +215832,8 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:130278.15-130284.4" - cell \alui_l$57 \alui_l + attribute \src "libresoc.v:132613.15-132619.4" + cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -210468,8 +215841,8 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:130285.14-130291.4" - cell \opc_l$53 \opc_l + attribute \src "libresoc.v:132620.14-132626.4" + cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -210477,8 +215850,8 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:130292.14-130298.4" - cell \req_l$54 \req_l + attribute \src "libresoc.v:132627.14-132633.4" + cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -210486,8 +215859,8 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:130299.14-130305.4" - cell \rok_l$56 \rok_l + attribute \src "libresoc.v:132634.14-132640.4" + cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -210495,638 +215868,638 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:130306.14-130311.4" - cell \rst_l$55 \rst_l + attribute \src "libresoc.v:132641.14-132646.4" + cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:130312.14-130318.4" - cell \src_l$52 \src_l + attribute \src "libresoc.v:132647.14-132653.4" + cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:129498.7-129498.20" - process $proc$libresoc.v:129498$6229 + attribute \src "libresoc.v:131833.7-131833.20" + process $proc$libresoc.v:131833$6488 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129616.7-129616.24" - process $proc$libresoc.v:129616$6230 + attribute \src "libresoc.v:131951.7-131951.24" + process $proc$libresoc.v:131951$6489 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:129626.7-129626.26" - process $proc$libresoc.v:129626$6231 + attribute \src "libresoc.v:131961.7-131961.26" + process $proc$libresoc.v:131961$6490 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:129634.7-129634.25" - process $proc$libresoc.v:129634$6232 + attribute \src "libresoc.v:131969.7-131969.25" + process $proc$libresoc.v:131969$6491 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:129642.13-129642.53" - process $proc$libresoc.v:129642$6233 + attribute \src "libresoc.v:131977.13-131977.53" + process $proc$libresoc.v:131977$6492 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:129659.14-129659.56" - process $proc$libresoc.v:129659$6234 + attribute \src "libresoc.v:131994.14-131994.56" + process $proc$libresoc.v:131994$6493 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:129663.14-129663.76" - process $proc$libresoc.v:129663$6235 + attribute \src "libresoc.v:131998.14-131998.76" + process $proc$libresoc.v:131998$6494 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:129667.7-129667.51" - process $proc$libresoc.v:129667$6236 + attribute \src "libresoc.v:132002.7-132002.51" + process $proc$libresoc.v:132002$6495 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:129675.13-129675.56" - process $proc$libresoc.v:129675$6237 + attribute \src "libresoc.v:132010.13-132010.56" + process $proc$libresoc.v:132010$6496 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:129679.14-129679.51" - process $proc$libresoc.v:129679$6238 + attribute \src "libresoc.v:132014.14-132014.51" + process $proc$libresoc.v:132014$6497 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:129757.13-129757.55" - process $proc$libresoc.v:129757$6239 + attribute \src "libresoc.v:132092.13-132092.55" + process $proc$libresoc.v:132092$6498 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:129761.7-129761.48" - process $proc$libresoc.v:129761$6240 + attribute \src "libresoc.v:132096.7-132096.48" + process $proc$libresoc.v:132096$6499 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:129765.7-129765.49" - process $proc$libresoc.v:129765$6241 + attribute \src "libresoc.v:132100.7-132100.49" + process $proc$libresoc.v:132100$6500 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:129769.7-129769.47" - process $proc$libresoc.v:129769$6242 + attribute \src "libresoc.v:132104.7-132104.47" + process $proc$libresoc.v:132104$6501 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:129773.7-129773.48" - process $proc$libresoc.v:129773$6243 + attribute \src "libresoc.v:132108.7-132108.48" + process $proc$libresoc.v:132108$6502 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:129777.7-129777.45" - process $proc$libresoc.v:129777$6244 + attribute \src "libresoc.v:132112.7-132112.45" + process $proc$libresoc.v:132112$6503 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:129781.7-129781.45" - process $proc$libresoc.v:129781$6245 + attribute \src "libresoc.v:132116.7-132116.45" + process $proc$libresoc.v:132116$6504 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:129785.7-129785.51" - process $proc$libresoc.v:129785$6246 + attribute \src "libresoc.v:132120.7-132120.51" + process $proc$libresoc.v:132120$6505 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:129789.7-129789.45" - process $proc$libresoc.v:129789$6247 + attribute \src "libresoc.v:132124.7-132124.45" + process $proc$libresoc.v:132124$6506 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:129793.7-129793.45" - process $proc$libresoc.v:129793$6248 + attribute \src "libresoc.v:132128.7-132128.45" + process $proc$libresoc.v:132128$6507 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:129797.7-129797.48" - process $proc$libresoc.v:129797$6249 + attribute \src "libresoc.v:132132.7-132132.48" + process $proc$libresoc.v:132132$6508 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:129801.7-129801.45" - process $proc$libresoc.v:129801$6250 + attribute \src "libresoc.v:132136.7-132136.45" + process $proc$libresoc.v:132136$6509 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:129827.7-129827.27" - process $proc$libresoc.v:129827$6251 + attribute \src "libresoc.v:132162.7-132162.27" + process $proc$libresoc.v:132162$6510 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:129861.14-129861.47" - process $proc$libresoc.v:129861$6252 + attribute \src "libresoc.v:132196.14-132196.47" + process $proc$libresoc.v:132196$6511 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:129865.7-129865.27" - process $proc$libresoc.v:129865$6253 + attribute \src "libresoc.v:132200.7-132200.27" + process $proc$libresoc.v:132200$6512 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:129869.13-129869.33" - process $proc$libresoc.v:129869$6254 + attribute \src "libresoc.v:132204.13-132204.33" + process $proc$libresoc.v:132204$6513 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:129873.7-129873.30" - process $proc$libresoc.v:129873$6255 + attribute \src "libresoc.v:132208.7-132208.30" + process $proc$libresoc.v:132208$6514 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:129887.7-129887.25" - process $proc$libresoc.v:129887$6256 + attribute \src "libresoc.v:132222.7-132222.25" + process $proc$libresoc.v:132222$6515 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:129891.7-129891.25" - process $proc$libresoc.v:129891$6257 + attribute \src "libresoc.v:132226.7-132226.25" + process $proc$libresoc.v:132226$6516 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130022.13-130022.30" - process $proc$libresoc.v:130022$6258 + attribute \src "libresoc.v:132357.13-132357.30" + process $proc$libresoc.v:132357$6517 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:130030.13-130030.31" - process $proc$libresoc.v:130030$6259 + attribute \src "libresoc.v:132365.13-132365.31" + process $proc$libresoc.v:132365$6518 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:130034.13-130034.31" - process $proc$libresoc.v:130034$6260 + attribute \src "libresoc.v:132369.13-132369.31" + process $proc$libresoc.v:132369$6519 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:130046.7-130046.26" - process $proc$libresoc.v:130046$6261 + attribute \src "libresoc.v:132381.7-132381.26" + process $proc$libresoc.v:132381$6520 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130050.7-130050.26" - process $proc$libresoc.v:130050$6262 + attribute \src "libresoc.v:132385.7-132385.26" + process $proc$libresoc.v:132385$6521 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130054.7-130054.25" - process $proc$libresoc.v:130054$6263 + attribute \src "libresoc.v:132389.7-132389.25" + process $proc$libresoc.v:132389$6522 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130058.7-130058.25" - process $proc$libresoc.v:130058$6264 + attribute \src "libresoc.v:132393.7-132393.25" + process $proc$libresoc.v:132393$6523 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130072.13-130072.31" - process $proc$libresoc.v:130072$6265 + attribute \src "libresoc.v:132407.13-132407.31" + process $proc$libresoc.v:132407$6524 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:130076.13-130076.31" - process $proc$libresoc.v:130076$6266 + attribute \src "libresoc.v:132411.13-132411.31" + process $proc$libresoc.v:132411$6525 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:130084.14-130084.43" - process $proc$libresoc.v:130084$6267 + attribute \src "libresoc.v:132419.14-132419.43" + process $proc$libresoc.v:132419$6526 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:130088.14-130088.43" - process $proc$libresoc.v:130088$6268 + attribute \src "libresoc.v:132423.14-132423.43" + process $proc$libresoc.v:132423$6527 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:130092.7-130092.20" - process $proc$libresoc.v:130092$6269 + attribute \src "libresoc.v:132427.7-132427.20" + process $proc$libresoc.v:132427$6528 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:130158.3-130159.39" - process $proc$libresoc.v:130158$6079 + attribute \src "libresoc.v:132493.3-132494.39" + process $proc$libresoc.v:132493$6338 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:130160.3-130161.43" - process $proc$libresoc.v:130160$6080 + attribute \src "libresoc.v:132495.3-132496.43" + process $proc$libresoc.v:132495$6339 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:130162.3-130163.29" - process $proc$libresoc.v:130162$6081 + attribute \src "libresoc.v:132497.3-132498.29" + process $proc$libresoc.v:132497$6340 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:130164.3-130165.29" - process $proc$libresoc.v:130164$6082 + attribute \src "libresoc.v:132499.3-132500.29" + process $proc$libresoc.v:132499$6341 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:130166.3-130167.29" - process $proc$libresoc.v:130166$6083 + attribute \src "libresoc.v:132501.3-132502.29" + process $proc$libresoc.v:132501$6342 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:130168.3-130169.43" - process $proc$libresoc.v:130168$6084 + attribute \src "libresoc.v:132503.3-132504.43" + process $proc$libresoc.v:132503$6343 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:130170.3-130171.49" - process $proc$libresoc.v:130170$6085 + attribute \src "libresoc.v:132505.3-132506.49" + process $proc$libresoc.v:132505$6344 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:130172.3-130173.37" - process $proc$libresoc.v:130172$6086 + attribute \src "libresoc.v:132507.3-132508.37" + process $proc$libresoc.v:132507$6345 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:130174.3-130175.43" - process $proc$libresoc.v:130174$6087 + attribute \src "libresoc.v:132509.3-132510.43" + process $proc$libresoc.v:132509$6346 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:130176.3-130177.85" - process $proc$libresoc.v:130176$6088 + attribute \src "libresoc.v:132511.3-132512.85" + process $proc$libresoc.v:132511$6347 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:130178.3-130179.81" - process $proc$libresoc.v:130178$6089 + attribute \src "libresoc.v:132513.3-132514.81" + process $proc$libresoc.v:132513$6348 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:130180.3-130181.95" - process $proc$libresoc.v:130180$6090 + attribute \src "libresoc.v:132515.3-132516.95" + process $proc$libresoc.v:132515$6349 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130182.3-130183.91" - process $proc$libresoc.v:130182$6091 + attribute \src "libresoc.v:132517.3-132518.91" + process $proc$libresoc.v:132517$6350 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130184.3-130185.79" - process $proc$libresoc.v:130184$6092 + attribute \src "libresoc.v:132519.3-132520.79" + process $proc$libresoc.v:132519$6351 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:130186.3-130187.79" - process $proc$libresoc.v:130186$6093 + attribute \src "libresoc.v:132521.3-132522.79" + process $proc$libresoc.v:132521$6352 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:130188.3-130189.79" - process $proc$libresoc.v:130188$6094 + attribute \src "libresoc.v:132523.3-132524.79" + process $proc$libresoc.v:132523$6353 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:130190.3-130191.79" - process $proc$libresoc.v:130190$6095 + attribute \src "libresoc.v:132525.3-132526.79" + process $proc$libresoc.v:132525$6354 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:130192.3-130193.85" - process $proc$libresoc.v:130192$6096 + attribute \src "libresoc.v:132527.3-132528.85" + process $proc$libresoc.v:132527$6355 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:130194.3-130195.79" - process $proc$libresoc.v:130194$6097 + attribute \src "libresoc.v:132529.3-132530.79" + process $proc$libresoc.v:132529$6356 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:130196.3-130197.89" - process $proc$libresoc.v:130196$6098 + attribute \src "libresoc.v:132531.3-132532.89" + process $proc$libresoc.v:132531$6357 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:130198.3-130199.87" - process $proc$libresoc.v:130198$6099 + attribute \src "libresoc.v:132533.3-132534.87" + process $proc$libresoc.v:132533$6358 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:130200.3-130201.85" - process $proc$libresoc.v:130200$6100 + attribute \src "libresoc.v:132535.3-132536.85" + process $proc$libresoc.v:132535$6359 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:130202.3-130203.91" - process $proc$libresoc.v:130202$6101 + attribute \src "libresoc.v:132537.3-132538.91" + process $proc$libresoc.v:132537$6360 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:130204.3-130205.83" - process $proc$libresoc.v:130204$6102 + attribute \src "libresoc.v:132539.3-132540.83" + process $proc$libresoc.v:132539$6361 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:130206.3-130207.85" - process $proc$libresoc.v:130206$6103 + attribute \src "libresoc.v:132541.3-132542.85" + process $proc$libresoc.v:132541$6362 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:130208.3-130209.83" - process $proc$libresoc.v:130208$6104 + attribute \src "libresoc.v:132543.3-132544.83" + process $proc$libresoc.v:132543$6363 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:130210.3-130211.75" - process $proc$libresoc.v:130210$6105 + attribute \src "libresoc.v:132545.3-132546.75" + process $proc$libresoc.v:132545$6364 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:130212.3-130213.39" - process $proc$libresoc.v:130212$6106 + attribute \src "libresoc.v:132547.3-132548.39" + process $proc$libresoc.v:132547$6365 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:130214.3-130215.39" - process $proc$libresoc.v:130214$6107 + attribute \src "libresoc.v:132549.3-132550.39" + process $proc$libresoc.v:132549$6366 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:130216.3-130217.39" - process $proc$libresoc.v:130216$6108 + attribute \src "libresoc.v:132551.3-132552.39" + process $proc$libresoc.v:132551$6367 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:130218.3-130219.39" - process $proc$libresoc.v:130218$6109 + attribute \src "libresoc.v:132553.3-132554.39" + process $proc$libresoc.v:132553$6368 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:130220.3-130221.39" - process $proc$libresoc.v:130220$6110 + attribute \src "libresoc.v:132555.3-132556.39" + process $proc$libresoc.v:132555$6369 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:130222.3-130223.39" - process $proc$libresoc.v:130222$6111 + attribute \src "libresoc.v:132557.3-132558.39" + process $proc$libresoc.v:132557$6370 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:130224.3-130225.39" - process $proc$libresoc.v:130224$6112 + attribute \src "libresoc.v:132559.3-132560.39" + process $proc$libresoc.v:132559$6371 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:130226.3-130227.39" - process $proc$libresoc.v:130226$6113 + attribute \src "libresoc.v:132561.3-132562.39" + process $proc$libresoc.v:132561$6372 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:130228.3-130229.41" - process $proc$libresoc.v:130228$6114 + attribute \src "libresoc.v:132563.3-132564.41" + process $proc$libresoc.v:132563$6373 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:130230.3-130231.41" - process $proc$libresoc.v:130230$6115 + attribute \src "libresoc.v:132565.3-132566.41" + process $proc$libresoc.v:132565$6374 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:130232.3-130233.37" - process $proc$libresoc.v:130232$6116 + attribute \src "libresoc.v:132567.3-132568.37" + process $proc$libresoc.v:132567$6375 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:130234.3-130235.44" - process $proc$libresoc.v:130234$6117 + attribute \src "libresoc.v:132569.3-132570.44" + process $proc$libresoc.v:132569$6376 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:130236.3-130237.24" - process $proc$libresoc.v:130236$6118 + attribute \src "libresoc.v:132571.3-132572.24" + process $proc$libresoc.v:132571$6377 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:130319.3-130328.6" - process $proc$libresoc.v:130319$6119 + attribute \src "libresoc.v:132654.3-132663.6" + process $proc$libresoc.v:132654$6378 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:130320.5-130320.29" + attribute \src "libresoc.v:132655.5-132655.29" switch \initial - attribute \src "libresoc.v:130320.9-130320.17" + attribute \src "libresoc.v:132655.9-132655.17" case 1'1 case end @@ -211142,14 +216515,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:130329.3-130337.6" - process $proc$libresoc.v:130329$6120 + attribute \src "libresoc.v:132664.3-132672.6" + process $proc$libresoc.v:132664$6379 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6121 $1\rok_l_s_rdok$next[0:0]$6122 - attribute \src "libresoc.v:130330.5-130330.29" + assign $0\rok_l_s_rdok$next[0:0]$6380 $1\rok_l_s_rdok$next[0:0]$6381 + attribute \src "libresoc.v:132665.5-132665.29" switch \initial - attribute \src "libresoc.v:130330.9-130330.17" + attribute \src "libresoc.v:132665.9-132665.17" case 1'1 case end @@ -211158,21 +216531,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6122 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6381 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6122 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6381 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6121 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6380 end - attribute \src "libresoc.v:130338.3-130346.6" - process $proc$libresoc.v:130338$6123 + attribute \src "libresoc.v:132673.3-132681.6" + process $proc$libresoc.v:132673$6382 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6124 $1\rok_l_r_rdok$next[0:0]$6125 - attribute \src "libresoc.v:130339.5-130339.29" + assign $0\rok_l_r_rdok$next[0:0]$6383 $1\rok_l_r_rdok$next[0:0]$6384 + attribute \src "libresoc.v:132674.5-132674.29" switch \initial - attribute \src "libresoc.v:130339.9-130339.17" + attribute \src "libresoc.v:132674.9-132674.17" case 1'1 case end @@ -211181,21 +216554,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6125 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6384 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6125 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6384 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6124 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6383 end - attribute \src "libresoc.v:130347.3-130355.6" - process $proc$libresoc.v:130347$6126 + attribute \src "libresoc.v:132682.3-132690.6" + process $proc$libresoc.v:132682$6385 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6127 $1\rst_l_s_rst$next[0:0]$6128 - attribute \src "libresoc.v:130348.5-130348.29" + assign $0\rst_l_s_rst$next[0:0]$6386 $1\rst_l_s_rst$next[0:0]$6387 + attribute \src "libresoc.v:132683.5-132683.29" switch \initial - attribute \src "libresoc.v:130348.9-130348.17" + attribute \src "libresoc.v:132683.9-132683.17" case 1'1 case end @@ -211204,21 +216577,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6128 1'0 + assign $1\rst_l_s_rst$next[0:0]$6387 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6128 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6387 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6127 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6386 end - attribute \src "libresoc.v:130356.3-130364.6" - process $proc$libresoc.v:130356$6129 + attribute \src "libresoc.v:132691.3-132699.6" + process $proc$libresoc.v:132691$6388 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6130 $1\rst_l_r_rst$next[0:0]$6131 - attribute \src "libresoc.v:130357.5-130357.29" + assign $0\rst_l_r_rst$next[0:0]$6389 $1\rst_l_r_rst$next[0:0]$6390 + attribute \src "libresoc.v:132692.5-132692.29" switch \initial - attribute \src "libresoc.v:130357.9-130357.17" + attribute \src "libresoc.v:132692.9-132692.17" case 1'1 case end @@ -211227,21 +216600,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6131 1'1 + assign $1\rst_l_r_rst$next[0:0]$6390 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6131 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6390 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6130 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6389 end - attribute \src "libresoc.v:130365.3-130373.6" - process $proc$libresoc.v:130365$6132 + attribute \src "libresoc.v:132700.3-132708.6" + process $proc$libresoc.v:132700$6391 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6133 $1\opc_l_s_opc$next[0:0]$6134 - attribute \src "libresoc.v:130366.5-130366.29" + assign $0\opc_l_s_opc$next[0:0]$6392 $1\opc_l_s_opc$next[0:0]$6393 + attribute \src "libresoc.v:132701.5-132701.29" switch \initial - attribute \src "libresoc.v:130366.9-130366.17" + attribute \src "libresoc.v:132701.9-132701.17" case 1'1 case end @@ -211250,21 +216623,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6134 1'0 + assign $1\opc_l_s_opc$next[0:0]$6393 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6134 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6393 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6133 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6392 end - attribute \src "libresoc.v:130374.3-130382.6" - process $proc$libresoc.v:130374$6135 + attribute \src "libresoc.v:132709.3-132717.6" + process $proc$libresoc.v:132709$6394 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6136 $1\opc_l_r_opc$next[0:0]$6137 - attribute \src "libresoc.v:130375.5-130375.29" + assign $0\opc_l_r_opc$next[0:0]$6395 $1\opc_l_r_opc$next[0:0]$6396 + attribute \src "libresoc.v:132710.5-132710.29" switch \initial - attribute \src "libresoc.v:130375.9-130375.17" + attribute \src "libresoc.v:132710.9-132710.17" case 1'1 case end @@ -211273,21 +216646,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6137 1'1 + assign $1\opc_l_r_opc$next[0:0]$6396 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6137 \req_done + assign $1\opc_l_r_opc$next[0:0]$6396 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6136 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6395 end - attribute \src "libresoc.v:130383.3-130391.6" - process $proc$libresoc.v:130383$6138 + attribute \src "libresoc.v:132718.3-132726.6" + process $proc$libresoc.v:132718$6397 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6139 $1\src_l_s_src$next[2:0]$6140 - attribute \src "libresoc.v:130384.5-130384.29" + assign $0\src_l_s_src$next[2:0]$6398 $1\src_l_s_src$next[2:0]$6399 + attribute \src "libresoc.v:132719.5-132719.29" switch \initial - attribute \src "libresoc.v:130384.9-130384.17" + attribute \src "libresoc.v:132719.9-132719.17" case 1'1 case end @@ -211296,21 +216669,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6140 3'000 + assign $1\src_l_s_src$next[2:0]$6399 3'000 case - assign $1\src_l_s_src$next[2:0]$6140 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6399 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6139 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6398 end - attribute \src "libresoc.v:130392.3-130400.6" - process $proc$libresoc.v:130392$6141 + attribute \src "libresoc.v:132727.3-132735.6" + process $proc$libresoc.v:132727$6400 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6142 $1\src_l_r_src$next[2:0]$6143 - attribute \src "libresoc.v:130393.5-130393.29" + assign $0\src_l_r_src$next[2:0]$6401 $1\src_l_r_src$next[2:0]$6402 + attribute \src "libresoc.v:132728.5-132728.29" switch \initial - attribute \src "libresoc.v:130393.9-130393.17" + attribute \src "libresoc.v:132728.9-132728.17" case 1'1 case end @@ -211319,21 +216692,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6143 3'111 + assign $1\src_l_r_src$next[2:0]$6402 3'111 case - assign $1\src_l_r_src$next[2:0]$6143 \reset_r + assign $1\src_l_r_src$next[2:0]$6402 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6142 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6401 end - attribute \src "libresoc.v:130401.3-130409.6" - process $proc$libresoc.v:130401$6144 + attribute \src "libresoc.v:132736.3-132744.6" + process $proc$libresoc.v:132736$6403 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6145 $1\req_l_s_req$next[1:0]$6146 - attribute \src "libresoc.v:130402.5-130402.29" + assign $0\req_l_s_req$next[1:0]$6404 $1\req_l_s_req$next[1:0]$6405 + attribute \src "libresoc.v:132737.5-132737.29" switch \initial - attribute \src "libresoc.v:130402.9-130402.17" + attribute \src "libresoc.v:132737.9-132737.17" case 1'1 case end @@ -211342,21 +216715,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6146 2'00 + assign $1\req_l_s_req$next[1:0]$6405 2'00 case - assign $1\req_l_s_req$next[1:0]$6146 \$65 + assign $1\req_l_s_req$next[1:0]$6405 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6145 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6404 end - attribute \src "libresoc.v:130410.3-130418.6" - process $proc$libresoc.v:130410$6147 + attribute \src "libresoc.v:132745.3-132753.6" + process $proc$libresoc.v:132745$6406 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6148 $1\req_l_r_req$next[1:0]$6149 - attribute \src "libresoc.v:130411.5-130411.29" + assign $0\req_l_r_req$next[1:0]$6407 $1\req_l_r_req$next[1:0]$6408 + attribute \src "libresoc.v:132746.5-132746.29" switch \initial - attribute \src "libresoc.v:130411.9-130411.17" + attribute \src "libresoc.v:132746.9-132746.17" case 1'1 case end @@ -211365,15 +216738,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6149 2'11 + assign $1\req_l_r_req$next[1:0]$6408 2'11 case - assign $1\req_l_r_req$next[1:0]$6149 \$67 + assign $1\req_l_r_req$next[1:0]$6408 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6148 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6407 end - attribute \src "libresoc.v:130419.3-130457.6" - process $proc$libresoc.v:130419$6150 + attribute \src "libresoc.v:132754.3-132792.6" + process $proc$libresoc.v:132754$6409 assign { } { } assign { } { } assign { } { } @@ -211410,33 +216783,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6151 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 - assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6410 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 + assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6156 $1\alu_logical0_logical_op__insn$next[31:0]$6174 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6415 $1\alu_logical0_logical_op__insn$next[31:0]$6433 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 - attribute \src "libresoc.v:130420.5-130420.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 + attribute \src "libresoc.v:132755.5-132755.29" switch \initial - attribute \src "libresoc.v:130420.9-130420.17" + attribute \src "libresoc.v:132755.9-132755.17" case 1'1 case end @@ -211462,26 +216835,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6174 $1\alu_logical0_logical_op__data_len$next[3:0]$6169 $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6433 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6169 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6170 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6173 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6174 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6175 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6176 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6177 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6178 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6179 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6182 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6185 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6186 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6428 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6433 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -211493,54 +216866,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6187 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6171 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6188 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6172 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6189 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6180 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6190 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6181 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6191 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6183 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6192 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6184 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6151 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6152 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6153 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6154 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6155 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6156 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6157 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6158 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6159 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6160 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6161 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6162 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6163 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6164 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6165 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6166 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6167 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6168 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6410 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6415 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 end - attribute \src "libresoc.v:130458.3-130479.6" - process $proc$libresoc.v:130458$6193 + attribute \src "libresoc.v:132793.3-132814.6" + process $proc$libresoc.v:132793$6452 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6194 $2\data_r0__o$next[63:0]$6198 + assign $0\data_r0__o$next[63:0]$6453 $2\data_r0__o$next[63:0]$6457 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6195 $3\data_r0__o_ok$next[0:0]$6200 - attribute \src "libresoc.v:130459.5-130459.29" + assign $0\data_r0__o_ok$next[0:0]$6454 $3\data_r0__o_ok$next[0:0]$6459 + attribute \src "libresoc.v:132794.5-132794.29" switch \initial - attribute \src "libresoc.v:130459.9-130459.17" + attribute \src "libresoc.v:132794.9-132794.17" case 1'1 case end @@ -211550,10 +216923,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6197 $1\data_r0__o$next[63:0]$6196 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6456 $1\data_r0__o$next[63:0]$6455 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6196 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6197 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6455 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6456 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -211561,38 +216934,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6199 $2\data_r0__o$next[63:0]$6198 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6458 $2\data_r0__o$next[63:0]$6457 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6198 $1\data_r0__o$next[63:0]$6196 - assign $2\data_r0__o_ok$next[0:0]$6199 $1\data_r0__o_ok$next[0:0]$6197 + assign $2\data_r0__o$next[63:0]$6457 $1\data_r0__o$next[63:0]$6455 + assign $2\data_r0__o_ok$next[0:0]$6458 $1\data_r0__o_ok$next[0:0]$6456 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6200 1'0 + assign $3\data_r0__o_ok$next[0:0]$6459 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6200 $2\data_r0__o_ok$next[0:0]$6199 + assign $3\data_r0__o_ok$next[0:0]$6459 $2\data_r0__o_ok$next[0:0]$6458 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6194 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6195 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6453 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6454 end - attribute \src "libresoc.v:130480.3-130501.6" - process $proc$libresoc.v:130480$6201 + attribute \src "libresoc.v:132815.3-132836.6" + process $proc$libresoc.v:132815$6460 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6202 $2\data_r1__cr_a$next[3:0]$6206 + assign $0\data_r1__cr_a$next[3:0]$6461 $2\data_r1__cr_a$next[3:0]$6465 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6203 $3\data_r1__cr_a_ok$next[0:0]$6208 - attribute \src "libresoc.v:130481.5-130481.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6462 $3\data_r1__cr_a_ok$next[0:0]$6467 + attribute \src "libresoc.v:132816.5-132816.29" switch \initial - attribute \src "libresoc.v:130481.9-130481.17" + attribute \src "libresoc.v:132816.9-132816.17" case 1'1 case end @@ -211602,10 +216975,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6205 $1\data_r1__cr_a$next[3:0]$6204 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6464 $1\data_r1__cr_a$next[3:0]$6463 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6204 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6205 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6463 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6464 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -211613,32 +216986,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6207 $2\data_r1__cr_a$next[3:0]$6206 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6466 $2\data_r1__cr_a$next[3:0]$6465 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6206 $1\data_r1__cr_a$next[3:0]$6204 - assign $2\data_r1__cr_a_ok$next[0:0]$6207 $1\data_r1__cr_a_ok$next[0:0]$6205 + assign $2\data_r1__cr_a$next[3:0]$6465 $1\data_r1__cr_a$next[3:0]$6463 + assign $2\data_r1__cr_a_ok$next[0:0]$6466 $1\data_r1__cr_a_ok$next[0:0]$6464 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6208 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6467 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6208 $2\data_r1__cr_a_ok$next[0:0]$6207 + assign $3\data_r1__cr_a_ok$next[0:0]$6467 $2\data_r1__cr_a_ok$next[0:0]$6466 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6202 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6203 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6461 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6462 end - attribute \src "libresoc.v:130502.3-130511.6" - process $proc$libresoc.v:130502$6209 + attribute \src "libresoc.v:132837.3-132846.6" + process $proc$libresoc.v:132837$6468 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6210 $1\src_r0$next[63:0]$6211 - attribute \src "libresoc.v:130503.5-130503.29" + assign $0\src_r0$next[63:0]$6469 $1\src_r0$next[63:0]$6470 + attribute \src "libresoc.v:132838.5-132838.29" switch \initial - attribute \src "libresoc.v:130503.9-130503.17" + attribute \src "libresoc.v:132838.9-132838.17" case 1'1 case end @@ -211647,21 +217020,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6211 \src_or_imm + assign $1\src_r0$next[63:0]$6470 \src_or_imm case - assign $1\src_r0$next[63:0]$6211 \src_r0 + assign $1\src_r0$next[63:0]$6470 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6210 + update \src_r0$next $0\src_r0$next[63:0]$6469 end - attribute \src "libresoc.v:130512.3-130521.6" - process $proc$libresoc.v:130512$6212 + attribute \src "libresoc.v:132847.3-132856.6" + process $proc$libresoc.v:132847$6471 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6213 $1\src_r1$next[63:0]$6214 - attribute \src "libresoc.v:130513.5-130513.29" + assign $0\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6473 + attribute \src "libresoc.v:132848.5-132848.29" switch \initial - attribute \src "libresoc.v:130513.9-130513.17" + attribute \src "libresoc.v:132848.9-132848.17" case 1'1 case end @@ -211670,21 +217043,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6214 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6473 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6214 \src_r1 + assign $1\src_r1$next[63:0]$6473 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6213 + update \src_r1$next $0\src_r1$next[63:0]$6472 end - attribute \src "libresoc.v:130522.3-130531.6" - process $proc$libresoc.v:130522$6215 + attribute \src "libresoc.v:132857.3-132866.6" + process $proc$libresoc.v:132857$6474 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6216 $1\src_r2$next[0:0]$6217 - attribute \src "libresoc.v:130523.5-130523.29" + assign $0\src_r2$next[0:0]$6475 $1\src_r2$next[0:0]$6476 + attribute \src "libresoc.v:132858.5-132858.29" switch \initial - attribute \src "libresoc.v:130523.9-130523.17" + attribute \src "libresoc.v:132858.9-132858.17" case 1'1 case end @@ -211693,21 +217066,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6217 \src3_i + assign $1\src_r2$next[0:0]$6476 \src3_i case - assign $1\src_r2$next[0:0]$6217 \src_r2 + assign $1\src_r2$next[0:0]$6476 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6216 + update \src_r2$next $0\src_r2$next[0:0]$6475 end - attribute \src "libresoc.v:130532.3-130540.6" - process $proc$libresoc.v:130532$6218 + attribute \src "libresoc.v:132867.3-132875.6" + process $proc$libresoc.v:132867$6477 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6219 $1\alui_l_r_alui$next[0:0]$6220 - attribute \src "libresoc.v:130533.5-130533.29" + assign $0\alui_l_r_alui$next[0:0]$6478 $1\alui_l_r_alui$next[0:0]$6479 + attribute \src "libresoc.v:132868.5-132868.29" switch \initial - attribute \src "libresoc.v:130533.9-130533.17" + attribute \src "libresoc.v:132868.9-132868.17" case 1'1 case end @@ -211716,21 +217089,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6220 1'1 + assign $1\alui_l_r_alui$next[0:0]$6479 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6220 \$89 + assign $1\alui_l_r_alui$next[0:0]$6479 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6219 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6478 end - attribute \src "libresoc.v:130541.3-130549.6" - process $proc$libresoc.v:130541$6221 + attribute \src "libresoc.v:132876.3-132884.6" + process $proc$libresoc.v:132876$6480 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6222 $1\alu_l_r_alu$next[0:0]$6223 - attribute \src "libresoc.v:130542.5-130542.29" + assign $0\alu_l_r_alu$next[0:0]$6481 $1\alu_l_r_alu$next[0:0]$6482 + attribute \src "libresoc.v:132877.5-132877.29" switch \initial - attribute \src "libresoc.v:130542.9-130542.17" + attribute \src "libresoc.v:132877.9-132877.17" case 1'1 case end @@ -211739,21 +217112,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6223 1'1 + assign $1\alu_l_r_alu$next[0:0]$6482 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6223 \$91 + assign $1\alu_l_r_alu$next[0:0]$6482 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6222 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6481 end - attribute \src "libresoc.v:130550.3-130559.6" - process $proc$libresoc.v:130550$6224 + attribute \src "libresoc.v:132885.3-132894.6" + process $proc$libresoc.v:132885$6483 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:130551.5-130551.29" + attribute \src "libresoc.v:132886.5-132886.29" switch \initial - attribute \src "libresoc.v:130551.9-130551.17" + attribute \src "libresoc.v:132886.9-132886.17" case 1'1 case end @@ -211769,14 +217142,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:130560.3-130569.6" - process $proc$libresoc.v:130560$6225 + attribute \src "libresoc.v:132895.3-132904.6" + process $proc$libresoc.v:132895$6484 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:130561.5-130561.29" + attribute \src "libresoc.v:132896.5-132896.29" switch \initial - attribute \src "libresoc.v:130561.9-130561.17" + attribute \src "libresoc.v:132896.9-132896.17" case 1'1 case end @@ -211792,14 +217165,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:130570.3-130578.6" - process $proc$libresoc.v:130570$6226 + attribute \src "libresoc.v:132905.3-132913.6" + process $proc$libresoc.v:132905$6485 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6227 $1\prev_wr_go$next[1:0]$6228 - attribute \src "libresoc.v:130571.5-130571.29" + assign $0\prev_wr_go$next[1:0]$6486 $1\prev_wr_go$next[1:0]$6487 + attribute \src "libresoc.v:132906.5-132906.29" switch \initial - attribute \src "libresoc.v:130571.9-130571.17" + attribute \src "libresoc.v:132906.9-132906.17" case 1'1 case end @@ -211808,70 +217181,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6228 2'00 - case - assign $1\prev_wr_go$next[1:0]$6228 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6227 - end - connect \$9 $and$libresoc.v:130101$6022_Y - connect \$99 $and$libresoc.v:130102$6023_Y - connect \$101 $not$libresoc.v:130103$6024_Y - connect \$103 $and$libresoc.v:130104$6025_Y - connect \$105 $and$libresoc.v:130105$6026_Y - connect \$107 $and$libresoc.v:130106$6027_Y - connect \$109 $and$libresoc.v:130107$6028_Y - connect \$111 $and$libresoc.v:130108$6029_Y - connect \$113 $and$libresoc.v:130109$6030_Y - connect \$115 $and$libresoc.v:130110$6031_Y - connect \$11 $not$libresoc.v:130111$6032_Y - connect \$13 $and$libresoc.v:130112$6033_Y - connect \$15 $not$libresoc.v:130113$6034_Y - connect \$17 $and$libresoc.v:130114$6035_Y - connect \$1 $and$libresoc.v:130115$6036_Y - connect \$19 $and$libresoc.v:130116$6037_Y - connect \$23 $not$libresoc.v:130117$6038_Y - connect \$25 $and$libresoc.v:130118$6039_Y - connect \$22 $reduce_or$libresoc.v:130119$6040_Y - connect \$21 $not$libresoc.v:130120$6041_Y - connect \$29 $and$libresoc.v:130121$6042_Y - connect \$31 $reduce_or$libresoc.v:130122$6043_Y - connect \$33 $reduce_or$libresoc.v:130123$6044_Y - connect \$35 $or$libresoc.v:130124$6045_Y - connect \$37 $not$libresoc.v:130125$6046_Y - connect \$39 $and$libresoc.v:130126$6047_Y - connect \$41 $and$libresoc.v:130127$6048_Y - connect \$43 $eq$libresoc.v:130128$6049_Y - connect \$45 $and$libresoc.v:130129$6050_Y - connect \$47 $eq$libresoc.v:130130$6051_Y - connect \$4 $not$libresoc.v:130131$6052_Y - connect \$49 $and$libresoc.v:130132$6053_Y - connect \$51 $and$libresoc.v:130133$6054_Y - connect \$53 $and$libresoc.v:130134$6055_Y - connect \$55 $or$libresoc.v:130135$6056_Y - connect \$57 $or$libresoc.v:130136$6057_Y - connect \$59 $or$libresoc.v:130137$6058_Y - connect \$61 $or$libresoc.v:130138$6059_Y - connect \$63 $and$libresoc.v:130139$6060_Y - connect \$65 $and$libresoc.v:130140$6061_Y - connect \$67 $or$libresoc.v:130141$6062_Y - connect \$6 $or$libresoc.v:130142$6063_Y - connect \$69 $and$libresoc.v:130143$6064_Y - connect \$71 $and$libresoc.v:130144$6065_Y - connect \$73 $ternary$libresoc.v:130145$6066_Y - connect \$75 $ternary$libresoc.v:130146$6067_Y - connect \$78 $ternary$libresoc.v:130147$6068_Y - connect \$3 $reduce_and$libresoc.v:130148$6069_Y - connect \$81 $ternary$libresoc.v:130149$6070_Y - connect \$83 $ternary$libresoc.v:130150$6071_Y - connect \$85 $ternary$libresoc.v:130151$6072_Y - connect \$87 $ternary$libresoc.v:130152$6073_Y - connect \$89 $and$libresoc.v:130153$6074_Y - connect \$91 $and$libresoc.v:130154$6075_Y - connect \$93 $and$libresoc.v:130155$6076_Y - connect \$95 $not$libresoc.v:130156$6077_Y - connect \$97 $not$libresoc.v:130157$6078_Y + assign $1\prev_wr_go$next[1:0]$6487 2'00 + case + assign $1\prev_wr_go$next[1:0]$6487 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6486 + end + connect \$9 $and$libresoc.v:132436$6281_Y + connect \$99 $and$libresoc.v:132437$6282_Y + connect \$101 $not$libresoc.v:132438$6283_Y + connect \$103 $and$libresoc.v:132439$6284_Y + connect \$105 $and$libresoc.v:132440$6285_Y + connect \$107 $and$libresoc.v:132441$6286_Y + connect \$109 $and$libresoc.v:132442$6287_Y + connect \$111 $and$libresoc.v:132443$6288_Y + connect \$113 $and$libresoc.v:132444$6289_Y + connect \$115 $and$libresoc.v:132445$6290_Y + connect \$11 $not$libresoc.v:132446$6291_Y + connect \$13 $and$libresoc.v:132447$6292_Y + connect \$15 $not$libresoc.v:132448$6293_Y + connect \$17 $and$libresoc.v:132449$6294_Y + connect \$1 $and$libresoc.v:132450$6295_Y + connect \$19 $and$libresoc.v:132451$6296_Y + connect \$23 $not$libresoc.v:132452$6297_Y + connect \$25 $and$libresoc.v:132453$6298_Y + connect \$22 $reduce_or$libresoc.v:132454$6299_Y + connect \$21 $not$libresoc.v:132455$6300_Y + connect \$29 $and$libresoc.v:132456$6301_Y + connect \$31 $reduce_or$libresoc.v:132457$6302_Y + connect \$33 $reduce_or$libresoc.v:132458$6303_Y + connect \$35 $or$libresoc.v:132459$6304_Y + connect \$37 $not$libresoc.v:132460$6305_Y + connect \$39 $and$libresoc.v:132461$6306_Y + connect \$41 $and$libresoc.v:132462$6307_Y + connect \$43 $eq$libresoc.v:132463$6308_Y + connect \$45 $and$libresoc.v:132464$6309_Y + connect \$47 $eq$libresoc.v:132465$6310_Y + connect \$4 $not$libresoc.v:132466$6311_Y + connect \$49 $and$libresoc.v:132467$6312_Y + connect \$51 $and$libresoc.v:132468$6313_Y + connect \$53 $and$libresoc.v:132469$6314_Y + connect \$55 $or$libresoc.v:132470$6315_Y + connect \$57 $or$libresoc.v:132471$6316_Y + connect \$59 $or$libresoc.v:132472$6317_Y + connect \$61 $or$libresoc.v:132473$6318_Y + connect \$63 $and$libresoc.v:132474$6319_Y + connect \$65 $and$libresoc.v:132475$6320_Y + connect \$67 $or$libresoc.v:132476$6321_Y + connect \$6 $or$libresoc.v:132477$6322_Y + connect \$69 $and$libresoc.v:132478$6323_Y + connect \$71 $and$libresoc.v:132479$6324_Y + connect \$73 $ternary$libresoc.v:132480$6325_Y + connect \$75 $ternary$libresoc.v:132481$6326_Y + connect \$78 $ternary$libresoc.v:132482$6327_Y + connect \$3 $reduce_and$libresoc.v:132483$6328_Y + connect \$81 $ternary$libresoc.v:132484$6329_Y + connect \$83 $ternary$libresoc.v:132485$6330_Y + connect \$85 $ternary$libresoc.v:132486$6331_Y + connect \$87 $ternary$libresoc.v:132487$6332_Y + connect \$89 $and$libresoc.v:132488$6333_Y + connect \$91 $and$libresoc.v:132489$6334_Y + connect \$93 $and$libresoc.v:132490$6335_Y + connect \$95 $not$libresoc.v:132491$6336_Y + connect \$97 $not$libresoc.v:132492$6337_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -211905,266 +217278,266 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:130615.1-131985.10" +attribute \src "libresoc.v:132950.1-134320.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:131924.3-131942.6" - wire width 4 $0\cr_a$next[3:0]$6354 - attribute \src "libresoc.v:131684.3-131685.25" + attribute \src "libresoc.v:134259.3-134277.6" + wire width 4 $0\cr_a$next[3:0]$6613 + attribute \src "libresoc.v:134019.3-134020.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:131924.3-131942.6" - wire $0\cr_a_ok$next[0:0]$6355 - attribute \src "libresoc.v:131686.3-131687.31" + attribute \src "libresoc.v:134259.3-134277.6" + wire $0\cr_a_ok$next[0:0]$6614 + attribute \src "libresoc.v:134021.3-134022.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:130616.7-130616.20" + attribute \src "libresoc.v:132951.7-132951.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6305 - attribute \src "libresoc.v:131724.3-131725.57" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6564 + attribute \src "libresoc.v:134059.3-134060.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$6306 - attribute \src "libresoc.v:131694.3-131695.55" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$6565 + attribute \src "libresoc.v:134029.3-134030.55" wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6307 - attribute \src "libresoc.v:131696.3-131697.69" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6566 + attribute \src "libresoc.v:134031.3-134032.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6308 - attribute \src "libresoc.v:131698.3-131699.65" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6567 + attribute \src "libresoc.v:134033.3-134034.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6309 - attribute \src "libresoc.v:131712.3-131713.63" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6568 + attribute \src "libresoc.v:134047.3-134048.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 32 $0\logical_op__insn$next[31:0]$6310 - attribute \src "libresoc.v:131726.3-131727.49" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 32 $0\logical_op__insn$next[31:0]$6569 + attribute \src "libresoc.v:134061.3-134062.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6311 - attribute \src "libresoc.v:131692.3-131693.59" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6570 + attribute \src "libresoc.v:134027.3-134028.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__invert_in$next[0:0]$6312 - attribute \src "libresoc.v:131708.3-131709.59" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__invert_in$next[0:0]$6571 + attribute \src "libresoc.v:134043.3-134044.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__invert_out$next[0:0]$6313 - attribute \src "libresoc.v:131714.3-131715.61" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__invert_out$next[0:0]$6572 + attribute \src "libresoc.v:134049.3-134050.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__is_32bit$next[0:0]$6314 - attribute \src "libresoc.v:131720.3-131721.57" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__is_32bit$next[0:0]$6573 + attribute \src "libresoc.v:134055.3-134056.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__is_signed$next[0:0]$6315 - attribute \src "libresoc.v:131722.3-131723.59" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__is_signed$next[0:0]$6574 + attribute \src "libresoc.v:134057.3-134058.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__oe__oe$next[0:0]$6316 - attribute \src "libresoc.v:131704.3-131705.53" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__oe__oe$next[0:0]$6575 + attribute \src "libresoc.v:134039.3-134040.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__oe__ok$next[0:0]$6317 - attribute \src "libresoc.v:131706.3-131707.53" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__oe__ok$next[0:0]$6576 + attribute \src "libresoc.v:134041.3-134042.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__output_carry$next[0:0]$6318 - attribute \src "libresoc.v:131718.3-131719.65" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__output_carry$next[0:0]$6577 + attribute \src "libresoc.v:134053.3-134054.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__rc__ok$next[0:0]$6319 - attribute \src "libresoc.v:131702.3-131703.53" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__rc__ok$next[0:0]$6578 + attribute \src "libresoc.v:134037.3-134038.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__rc__rc$next[0:0]$6320 - attribute \src "libresoc.v:131700.3-131701.53" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__rc__rc$next[0:0]$6579 + attribute \src "libresoc.v:134035.3-134036.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__write_cr0$next[0:0]$6321 - attribute \src "libresoc.v:131716.3-131717.59" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__write_cr0$next[0:0]$6580 + attribute \src "libresoc.v:134051.3-134052.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $0\logical_op__zero_a$next[0:0]$6322 - attribute \src "libresoc.v:131710.3-131711.53" + attribute \src "libresoc.v:134198.3-134239.6" + wire $0\logical_op__zero_a$next[0:0]$6581 + attribute \src "libresoc.v:134045.3-134046.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:131850.3-131862.6" - wire width 2 $0\muxid$next[1:0]$6302 - attribute \src "libresoc.v:131728.3-131729.27" + attribute \src "libresoc.v:134185.3-134197.6" + wire width 2 $0\muxid$next[1:0]$6561 + attribute \src "libresoc.v:134063.3-134064.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:131905.3-131923.6" - wire width 64 $0\o$next[63:0]$6348 - attribute \src "libresoc.v:131688.3-131689.19" + attribute \src "libresoc.v:134240.3-134258.6" + wire width 64 $0\o$next[63:0]$6607 + attribute \src "libresoc.v:134023.3-134024.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:131905.3-131923.6" - wire $0\o_ok$next[0:0]$6349 - attribute \src "libresoc.v:131690.3-131691.25" + attribute \src "libresoc.v:134240.3-134258.6" + wire $0\o_ok$next[0:0]$6608 + attribute \src "libresoc.v:134025.3-134026.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:131832.3-131849.6" - wire $0\r_busy$next[0:0]$6298 - attribute \src "libresoc.v:131730.3-131731.29" + attribute \src "libresoc.v:134167.3-134184.6" + wire $0\r_busy$next[0:0]$6557 + attribute \src "libresoc.v:134065.3-134066.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:131943.3-131961.6" - wire $0\xer_so$next[0:0]$6360 - attribute \src "libresoc.v:131680.3-131681.29" + attribute \src "libresoc.v:134278.3-134296.6" + wire $0\xer_so$next[0:0]$6619 + attribute \src "libresoc.v:134015.3-134016.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:131943.3-131961.6" - wire $0\xer_so_ok$next[0:0]$6361 - attribute \src "libresoc.v:131682.3-131683.35" + attribute \src "libresoc.v:134278.3-134296.6" + wire $0\xer_so_ok$next[0:0]$6620 + attribute \src "libresoc.v:134017.3-134018.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:131924.3-131942.6" - wire width 4 $1\cr_a$next[3:0]$6356 - attribute \src "libresoc.v:130625.13-130625.24" + attribute \src "libresoc.v:134259.3-134277.6" + wire width 4 $1\cr_a$next[3:0]$6615 + attribute \src "libresoc.v:132960.13-132960.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:131924.3-131942.6" - wire $1\cr_a_ok$next[0:0]$6357 - attribute \src "libresoc.v:130634.7-130634.21" + attribute \src "libresoc.v:134259.3-134277.6" + wire $1\cr_a_ok$next[0:0]$6616 + attribute \src "libresoc.v:132969.7-132969.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6323 - attribute \src "libresoc.v:130913.13-130913.40" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6582 + attribute \src "libresoc.v:133248.13-133248.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$6324 - attribute \src "libresoc.v:130935.14-130935.43" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$6583 + attribute \src "libresoc.v:133270.14-133270.43" wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6325 - attribute \src "libresoc.v:130970.14-130970.63" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6584 + attribute \src "libresoc.v:133305.14-133305.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6326 - attribute \src "libresoc.v:130979.7-130979.38" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6585 + attribute \src "libresoc.v:133314.7-133314.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6327 - attribute \src "libresoc.v:130992.13-130992.43" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6586 + attribute \src "libresoc.v:133327.13-133327.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 32 $1\logical_op__insn$next[31:0]$6328 - attribute \src "libresoc.v:131009.14-131009.38" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 32 $1\logical_op__insn$next[31:0]$6587 + attribute \src "libresoc.v:133344.14-133344.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6329 - attribute \src "libresoc.v:131092.13-131092.42" + attribute \src "libresoc.v:134198.3-134239.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6588 + attribute \src "libresoc.v:133427.13-133427.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__invert_in$next[0:0]$6330 - attribute \src "libresoc.v:131249.7-131249.35" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__invert_in$next[0:0]$6589 + attribute \src "libresoc.v:133584.7-133584.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__invert_out$next[0:0]$6331 - attribute \src "libresoc.v:131258.7-131258.36" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__invert_out$next[0:0]$6590 + attribute \src "libresoc.v:133593.7-133593.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__is_32bit$next[0:0]$6332 - attribute \src "libresoc.v:131267.7-131267.34" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__is_32bit$next[0:0]$6591 + attribute \src "libresoc.v:133602.7-133602.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__is_signed$next[0:0]$6333 - attribute \src "libresoc.v:131276.7-131276.35" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__is_signed$next[0:0]$6592 + attribute \src "libresoc.v:133611.7-133611.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__oe__oe$next[0:0]$6334 - attribute \src "libresoc.v:131285.7-131285.32" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__oe__oe$next[0:0]$6593 + attribute \src "libresoc.v:133620.7-133620.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__oe__ok$next[0:0]$6335 - attribute \src "libresoc.v:131294.7-131294.32" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__oe__ok$next[0:0]$6594 + attribute \src "libresoc.v:133629.7-133629.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__output_carry$next[0:0]$6336 - attribute \src "libresoc.v:131303.7-131303.38" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__output_carry$next[0:0]$6595 + attribute \src "libresoc.v:133638.7-133638.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__rc__ok$next[0:0]$6337 - attribute \src "libresoc.v:131312.7-131312.32" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__rc__ok$next[0:0]$6596 + attribute \src "libresoc.v:133647.7-133647.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__rc__rc$next[0:0]$6338 - attribute \src "libresoc.v:131321.7-131321.32" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__rc__rc$next[0:0]$6597 + attribute \src "libresoc.v:133656.7-133656.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__write_cr0$next[0:0]$6339 - attribute \src "libresoc.v:131330.7-131330.35" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__write_cr0$next[0:0]$6598 + attribute \src "libresoc.v:133665.7-133665.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:131863.3-131904.6" - wire $1\logical_op__zero_a$next[0:0]$6340 - attribute \src "libresoc.v:131339.7-131339.32" + attribute \src "libresoc.v:134198.3-134239.6" + wire $1\logical_op__zero_a$next[0:0]$6599 + attribute \src "libresoc.v:133674.7-133674.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:131850.3-131862.6" - wire width 2 $1\muxid$next[1:0]$6303 - attribute \src "libresoc.v:131618.13-131618.25" + attribute \src "libresoc.v:134185.3-134197.6" + wire width 2 $1\muxid$next[1:0]$6562 + attribute \src "libresoc.v:133953.13-133953.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:131905.3-131923.6" - wire width 64 $1\o$next[63:0]$6350 - attribute \src "libresoc.v:131633.14-131633.38" + attribute \src "libresoc.v:134240.3-134258.6" + wire width 64 $1\o$next[63:0]$6609 + attribute \src "libresoc.v:133968.14-133968.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:131905.3-131923.6" - wire $1\o_ok$next[0:0]$6351 - attribute \src "libresoc.v:131640.7-131640.18" + attribute \src "libresoc.v:134240.3-134258.6" + wire $1\o_ok$next[0:0]$6610 + attribute \src "libresoc.v:133975.7-133975.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:131832.3-131849.6" - wire $1\r_busy$next[0:0]$6299 - attribute \src "libresoc.v:131654.7-131654.20" + attribute \src "libresoc.v:134167.3-134184.6" + wire $1\r_busy$next[0:0]$6558 + attribute \src "libresoc.v:133989.7-133989.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:131943.3-131961.6" - wire $1\xer_so$next[0:0]$6362 - attribute \src "libresoc.v:131663.7-131663.20" + attribute \src "libresoc.v:134278.3-134296.6" + wire $1\xer_so$next[0:0]$6621 + attribute \src "libresoc.v:133998.7-133998.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:131943.3-131961.6" - wire $1\xer_so_ok$next[0:0]$6363 - attribute \src "libresoc.v:131672.7-131672.23" + attribute \src "libresoc.v:134278.3-134296.6" + wire $1\xer_so_ok$next[0:0]$6622 + attribute \src "libresoc.v:134007.7-134007.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:131924.3-131942.6" - wire $2\cr_a_ok$next[0:0]$6358 - attribute \src "libresoc.v:131863.3-131904.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6341 - attribute \src "libresoc.v:131863.3-131904.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6342 - attribute \src "libresoc.v:131863.3-131904.6" - wire $2\logical_op__oe__oe$next[0:0]$6343 - attribute \src "libresoc.v:131863.3-131904.6" - wire $2\logical_op__oe__ok$next[0:0]$6344 - attribute \src "libresoc.v:131863.3-131904.6" - wire $2\logical_op__rc__ok$next[0:0]$6345 - attribute \src "libresoc.v:131863.3-131904.6" - wire $2\logical_op__rc__rc$next[0:0]$6346 - attribute \src "libresoc.v:131905.3-131923.6" - wire $2\o_ok$next[0:0]$6352 - attribute \src "libresoc.v:131832.3-131849.6" - wire $2\r_busy$next[0:0]$6300 - attribute \src "libresoc.v:131943.3-131961.6" - wire $2\xer_so_ok$next[0:0]$6364 - attribute \src "libresoc.v:131679.18-131679.118" - wire $and$libresoc.v:131679$6270_Y + attribute \src "libresoc.v:134259.3-134277.6" + wire $2\cr_a_ok$next[0:0]$6617 + attribute \src "libresoc.v:134198.3-134239.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6600 + attribute \src "libresoc.v:134198.3-134239.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6601 + attribute \src "libresoc.v:134198.3-134239.6" + wire $2\logical_op__oe__oe$next[0:0]$6602 + attribute \src "libresoc.v:134198.3-134239.6" + wire $2\logical_op__oe__ok$next[0:0]$6603 + attribute \src "libresoc.v:134198.3-134239.6" + wire $2\logical_op__rc__ok$next[0:0]$6604 + attribute \src "libresoc.v:134198.3-134239.6" + wire $2\logical_op__rc__rc$next[0:0]$6605 + attribute \src "libresoc.v:134240.3-134258.6" + wire $2\o_ok$next[0:0]$6611 + attribute \src "libresoc.v:134167.3-134184.6" + wire $2\r_busy$next[0:0]$6559 + attribute \src "libresoc.v:134278.3-134296.6" + wire $2\xer_so_ok$next[0:0]$6623 + attribute \src "libresoc.v:134014.18-134014.118" + wire $and$libresoc.v:134014$6529_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:130616.7-130616.15" + attribute \src "libresoc.v:132951.7-132951.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -213111,9 +218484,9 @@ module \logical_pipe1 wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -213121,7 +218494,7 @@ module \logical_pipe1 wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 4 \muxid @@ -213137,17 +218510,17 @@ module \logical_pipe1 wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 30 \p_ready_o @@ -213165,24 +218538,24 @@ module \logical_pipe1 wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 52 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:131679$6270 + cell $and $and$libresoc.v:134014$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213190,11 +218563,11 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:131679$6270_Y + connect \Y $and$libresoc.v:134014$6529_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:131732.14-131777.4" - cell \input$47 \input + attribute \src "libresoc.v:134067.14-134112.4" + cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 connect \logical_op__fn_unit \input_logical_op__fn_unit @@ -213241,8 +218614,8 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131778.13-131823.4" - cell \main$48 \main + attribute \src "libresoc.v:134113.13-134158.4" + cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 connect \logical_op__fn_unit \main_logical_op__fn_unit @@ -213289,424 +218662,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:131824.10-131827.4" - cell \n$46 \n + attribute \src "libresoc.v:134159.10-134162.4" + cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:131828.10-131831.4" - cell \p$45 \p + attribute \src "libresoc.v:134163.10-134166.4" + cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:130616.7-130616.20" - process $proc$libresoc.v:130616$6365 + attribute \src "libresoc.v:132951.7-132951.20" + process $proc$libresoc.v:132951$6624 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130625.13-130625.24" - process $proc$libresoc.v:130625$6366 + attribute \src "libresoc.v:132960.13-132960.24" + process $proc$libresoc.v:132960$6625 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:130634.7-130634.21" - process $proc$libresoc.v:130634$6367 + attribute \src "libresoc.v:132969.7-132969.21" + process $proc$libresoc.v:132969$6626 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:130913.13-130913.40" - process $proc$libresoc.v:130913$6368 + attribute \src "libresoc.v:133248.13-133248.40" + process $proc$libresoc.v:133248$6627 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:130935.14-130935.43" - process $proc$libresoc.v:130935$6369 + attribute \src "libresoc.v:133270.14-133270.43" + process $proc$libresoc.v:133270$6628 assign { } { } assign $1\logical_op__fn_unit[11:0] 12'000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:130970.14-130970.63" - process $proc$libresoc.v:130970$6370 + attribute \src "libresoc.v:133305.14-133305.63" + process $proc$libresoc.v:133305$6629 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:130979.7-130979.38" - process $proc$libresoc.v:130979$6371 + attribute \src "libresoc.v:133314.7-133314.38" + process $proc$libresoc.v:133314$6630 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:130992.13-130992.43" - process $proc$libresoc.v:130992$6372 + attribute \src "libresoc.v:133327.13-133327.43" + process $proc$libresoc.v:133327$6631 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:131009.14-131009.38" - process $proc$libresoc.v:131009$6373 + attribute \src "libresoc.v:133344.14-133344.38" + process $proc$libresoc.v:133344$6632 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:131092.13-131092.42" - process $proc$libresoc.v:131092$6374 + attribute \src "libresoc.v:133427.13-133427.42" + process $proc$libresoc.v:133427$6633 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:131249.7-131249.35" - process $proc$libresoc.v:131249$6375 + attribute \src "libresoc.v:133584.7-133584.35" + process $proc$libresoc.v:133584$6634 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:131258.7-131258.36" - process $proc$libresoc.v:131258$6376 + attribute \src "libresoc.v:133593.7-133593.36" + process $proc$libresoc.v:133593$6635 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:131267.7-131267.34" - process $proc$libresoc.v:131267$6377 + attribute \src "libresoc.v:133602.7-133602.34" + process $proc$libresoc.v:133602$6636 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:131276.7-131276.35" - process $proc$libresoc.v:131276$6378 + attribute \src "libresoc.v:133611.7-133611.35" + process $proc$libresoc.v:133611$6637 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:131285.7-131285.32" - process $proc$libresoc.v:131285$6379 + attribute \src "libresoc.v:133620.7-133620.32" + process $proc$libresoc.v:133620$6638 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:131294.7-131294.32" - process $proc$libresoc.v:131294$6380 + attribute \src "libresoc.v:133629.7-133629.32" + process $proc$libresoc.v:133629$6639 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:131303.7-131303.38" - process $proc$libresoc.v:131303$6381 + attribute \src "libresoc.v:133638.7-133638.38" + process $proc$libresoc.v:133638$6640 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:131312.7-131312.32" - process $proc$libresoc.v:131312$6382 + attribute \src "libresoc.v:133647.7-133647.32" + process $proc$libresoc.v:133647$6641 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:131321.7-131321.32" - process $proc$libresoc.v:131321$6383 + attribute \src "libresoc.v:133656.7-133656.32" + process $proc$libresoc.v:133656$6642 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:131330.7-131330.35" - process $proc$libresoc.v:131330$6384 + attribute \src "libresoc.v:133665.7-133665.35" + process $proc$libresoc.v:133665$6643 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:131339.7-131339.32" - process $proc$libresoc.v:131339$6385 + attribute \src "libresoc.v:133674.7-133674.32" + process $proc$libresoc.v:133674$6644 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:131618.13-131618.25" - process $proc$libresoc.v:131618$6386 + attribute \src "libresoc.v:133953.13-133953.25" + process $proc$libresoc.v:133953$6645 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:131633.14-131633.38" - process $proc$libresoc.v:131633$6387 + attribute \src "libresoc.v:133968.14-133968.38" + process $proc$libresoc.v:133968$6646 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:131640.7-131640.18" - process $proc$libresoc.v:131640$6388 + attribute \src "libresoc.v:133975.7-133975.18" + process $proc$libresoc.v:133975$6647 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:131654.7-131654.20" - process $proc$libresoc.v:131654$6389 + attribute \src "libresoc.v:133989.7-133989.20" + process $proc$libresoc.v:133989$6648 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:131663.7-131663.20" - process $proc$libresoc.v:131663$6390 + attribute \src "libresoc.v:133998.7-133998.20" + process $proc$libresoc.v:133998$6649 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:131672.7-131672.23" - process $proc$libresoc.v:131672$6391 + attribute \src "libresoc.v:134007.7-134007.23" + process $proc$libresoc.v:134007$6650 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:131680.3-131681.29" - process $proc$libresoc.v:131680$6271 + attribute \src "libresoc.v:134015.3-134016.29" + process $proc$libresoc.v:134015$6530 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:131682.3-131683.35" - process $proc$libresoc.v:131682$6272 + attribute \src "libresoc.v:134017.3-134018.35" + process $proc$libresoc.v:134017$6531 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:131684.3-131685.25" - process $proc$libresoc.v:131684$6273 + attribute \src "libresoc.v:134019.3-134020.25" + process $proc$libresoc.v:134019$6532 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:131686.3-131687.31" - process $proc$libresoc.v:131686$6274 + attribute \src "libresoc.v:134021.3-134022.31" + process $proc$libresoc.v:134021$6533 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:131688.3-131689.19" - process $proc$libresoc.v:131688$6275 + attribute \src "libresoc.v:134023.3-134024.19" + process $proc$libresoc.v:134023$6534 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:131690.3-131691.25" - process $proc$libresoc.v:131690$6276 + attribute \src "libresoc.v:134025.3-134026.25" + process $proc$libresoc.v:134025$6535 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:131692.3-131693.59" - process $proc$libresoc.v:131692$6277 + attribute \src "libresoc.v:134027.3-134028.59" + process $proc$libresoc.v:134027$6536 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:131694.3-131695.55" - process $proc$libresoc.v:131694$6278 + attribute \src "libresoc.v:134029.3-134030.55" + process $proc$libresoc.v:134029$6537 assign { } { } assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:131696.3-131697.69" - process $proc$libresoc.v:131696$6279 + attribute \src "libresoc.v:134031.3-134032.69" + process $proc$libresoc.v:134031$6538 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:131698.3-131699.65" - process $proc$libresoc.v:131698$6280 + attribute \src "libresoc.v:134033.3-134034.65" + process $proc$libresoc.v:134033$6539 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:131700.3-131701.53" - process $proc$libresoc.v:131700$6281 + attribute \src "libresoc.v:134035.3-134036.53" + process $proc$libresoc.v:134035$6540 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:131702.3-131703.53" - process $proc$libresoc.v:131702$6282 + attribute \src "libresoc.v:134037.3-134038.53" + process $proc$libresoc.v:134037$6541 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:131704.3-131705.53" - process $proc$libresoc.v:131704$6283 + attribute \src "libresoc.v:134039.3-134040.53" + process $proc$libresoc.v:134039$6542 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:131706.3-131707.53" - process $proc$libresoc.v:131706$6284 + attribute \src "libresoc.v:134041.3-134042.53" + process $proc$libresoc.v:134041$6543 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:131708.3-131709.59" - process $proc$libresoc.v:131708$6285 + attribute \src "libresoc.v:134043.3-134044.59" + process $proc$libresoc.v:134043$6544 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:131710.3-131711.53" - process $proc$libresoc.v:131710$6286 + attribute \src "libresoc.v:134045.3-134046.53" + process $proc$libresoc.v:134045$6545 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:131712.3-131713.63" - process $proc$libresoc.v:131712$6287 + attribute \src "libresoc.v:134047.3-134048.63" + process $proc$libresoc.v:134047$6546 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:131714.3-131715.61" - process $proc$libresoc.v:131714$6288 + attribute \src "libresoc.v:134049.3-134050.61" + process $proc$libresoc.v:134049$6547 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:131716.3-131717.59" - process $proc$libresoc.v:131716$6289 + attribute \src "libresoc.v:134051.3-134052.59" + process $proc$libresoc.v:134051$6548 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:131718.3-131719.65" - process $proc$libresoc.v:131718$6290 + attribute \src "libresoc.v:134053.3-134054.65" + process $proc$libresoc.v:134053$6549 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:131720.3-131721.57" - process $proc$libresoc.v:131720$6291 + attribute \src "libresoc.v:134055.3-134056.57" + process $proc$libresoc.v:134055$6550 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:131722.3-131723.59" - process $proc$libresoc.v:131722$6292 + attribute \src "libresoc.v:134057.3-134058.59" + process $proc$libresoc.v:134057$6551 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:131724.3-131725.57" - process $proc$libresoc.v:131724$6293 + attribute \src "libresoc.v:134059.3-134060.57" + process $proc$libresoc.v:134059$6552 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:131726.3-131727.49" - process $proc$libresoc.v:131726$6294 + attribute \src "libresoc.v:134061.3-134062.49" + process $proc$libresoc.v:134061$6553 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:131728.3-131729.27" - process $proc$libresoc.v:131728$6295 + attribute \src "libresoc.v:134063.3-134064.27" + process $proc$libresoc.v:134063$6554 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:131730.3-131731.29" - process $proc$libresoc.v:131730$6296 + attribute \src "libresoc.v:134065.3-134066.29" + process $proc$libresoc.v:134065$6555 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:131832.3-131849.6" - process $proc$libresoc.v:131832$6297 + attribute \src "libresoc.v:134167.3-134184.6" + process $proc$libresoc.v:134167$6556 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6298 $2\r_busy$next[0:0]$6300 - attribute \src "libresoc.v:131833.5-131833.29" + assign $0\r_busy$next[0:0]$6557 $2\r_busy$next[0:0]$6559 + attribute \src "libresoc.v:134168.5-134168.29" switch \initial - attribute \src "libresoc.v:131833.9-131833.17" + attribute \src "libresoc.v:134168.9-134168.17" case 1'1 case end @@ -213715,34 +219088,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6299 1'1 + assign $1\r_busy$next[0:0]$6558 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6299 1'0 + assign $1\r_busy$next[0:0]$6558 1'0 case - assign $1\r_busy$next[0:0]$6299 \r_busy + assign $1\r_busy$next[0:0]$6558 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6300 1'0 + assign $2\r_busy$next[0:0]$6559 1'0 case - assign $2\r_busy$next[0:0]$6300 $1\r_busy$next[0:0]$6299 + assign $2\r_busy$next[0:0]$6559 $1\r_busy$next[0:0]$6558 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6298 + update \r_busy$next $0\r_busy$next[0:0]$6557 end - attribute \src "libresoc.v:131850.3-131862.6" - process $proc$libresoc.v:131850$6301 + attribute \src "libresoc.v:134185.3-134197.6" + process $proc$libresoc.v:134185$6560 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6302 $1\muxid$next[1:0]$6303 - attribute \src "libresoc.v:131851.5-131851.29" + assign $0\muxid$next[1:0]$6561 $1\muxid$next[1:0]$6562 + attribute \src "libresoc.v:134186.5-134186.29" switch \initial - attribute \src "libresoc.v:131851.9-131851.17" + attribute \src "libresoc.v:134186.9-134186.17" case 1'1 case end @@ -213751,19 +219124,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6303 \muxid$66 + assign $1\muxid$next[1:0]$6562 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6303 \muxid$66 + assign $1\muxid$next[1:0]$6562 \muxid$66 case - assign $1\muxid$next[1:0]$6303 \muxid + assign $1\muxid$next[1:0]$6562 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6302 + update \muxid$next $0\muxid$next[1:0]$6561 end - attribute \src "libresoc.v:131863.3-131904.6" - process $proc$libresoc.v:131863$6304 + attribute \src "libresoc.v:134198.3-134239.6" + process $proc$libresoc.v:134198$6563 assign { } { } assign { } { } assign { } { } @@ -213800,33 +219173,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6305 $1\logical_op__data_len$next[3:0]$6323 - assign $0\logical_op__fn_unit$next[11:0]$6306 $1\logical_op__fn_unit$next[11:0]$6324 + assign $0\logical_op__data_len$next[3:0]$6564 $1\logical_op__data_len$next[3:0]$6582 + assign $0\logical_op__fn_unit$next[11:0]$6565 $1\logical_op__fn_unit$next[11:0]$6583 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6309 $1\logical_op__input_carry$next[1:0]$6327 - assign $0\logical_op__insn$next[31:0]$6310 $1\logical_op__insn$next[31:0]$6328 - assign $0\logical_op__insn_type$next[6:0]$6311 $1\logical_op__insn_type$next[6:0]$6329 - assign $0\logical_op__invert_in$next[0:0]$6312 $1\logical_op__invert_in$next[0:0]$6330 - assign $0\logical_op__invert_out$next[0:0]$6313 $1\logical_op__invert_out$next[0:0]$6331 - assign $0\logical_op__is_32bit$next[0:0]$6314 $1\logical_op__is_32bit$next[0:0]$6332 - assign $0\logical_op__is_signed$next[0:0]$6315 $1\logical_op__is_signed$next[0:0]$6333 + assign $0\logical_op__input_carry$next[1:0]$6568 $1\logical_op__input_carry$next[1:0]$6586 + assign $0\logical_op__insn$next[31:0]$6569 $1\logical_op__insn$next[31:0]$6587 + assign $0\logical_op__insn_type$next[6:0]$6570 $1\logical_op__insn_type$next[6:0]$6588 + assign $0\logical_op__invert_in$next[0:0]$6571 $1\logical_op__invert_in$next[0:0]$6589 + assign $0\logical_op__invert_out$next[0:0]$6572 $1\logical_op__invert_out$next[0:0]$6590 + assign $0\logical_op__is_32bit$next[0:0]$6573 $1\logical_op__is_32bit$next[0:0]$6591 + assign $0\logical_op__is_signed$next[0:0]$6574 $1\logical_op__is_signed$next[0:0]$6592 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6318 $1\logical_op__output_carry$next[0:0]$6336 + assign $0\logical_op__output_carry$next[0:0]$6577 $1\logical_op__output_carry$next[0:0]$6595 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6321 $1\logical_op__write_cr0$next[0:0]$6339 - assign $0\logical_op__zero_a$next[0:0]$6322 $1\logical_op__zero_a$next[0:0]$6340 - assign $0\logical_op__imm_data__data$next[63:0]$6307 $2\logical_op__imm_data__data$next[63:0]$6341 - assign $0\logical_op__imm_data__ok$next[0:0]$6308 $2\logical_op__imm_data__ok$next[0:0]$6342 - assign $0\logical_op__oe__oe$next[0:0]$6316 $2\logical_op__oe__oe$next[0:0]$6343 - assign $0\logical_op__oe__ok$next[0:0]$6317 $2\logical_op__oe__ok$next[0:0]$6344 - assign $0\logical_op__rc__ok$next[0:0]$6319 $2\logical_op__rc__ok$next[0:0]$6345 - assign $0\logical_op__rc__rc$next[0:0]$6320 $2\logical_op__rc__rc$next[0:0]$6346 - attribute \src "libresoc.v:131864.5-131864.29" + assign $0\logical_op__write_cr0$next[0:0]$6580 $1\logical_op__write_cr0$next[0:0]$6598 + assign $0\logical_op__zero_a$next[0:0]$6581 $1\logical_op__zero_a$next[0:0]$6599 + assign $0\logical_op__imm_data__data$next[63:0]$6566 $2\logical_op__imm_data__data$next[63:0]$6600 + assign $0\logical_op__imm_data__ok$next[0:0]$6567 $2\logical_op__imm_data__ok$next[0:0]$6601 + assign $0\logical_op__oe__oe$next[0:0]$6575 $2\logical_op__oe__oe$next[0:0]$6602 + assign $0\logical_op__oe__ok$next[0:0]$6576 $2\logical_op__oe__ok$next[0:0]$6603 + assign $0\logical_op__rc__ok$next[0:0]$6578 $2\logical_op__rc__ok$next[0:0]$6604 + assign $0\logical_op__rc__rc$next[0:0]$6579 $2\logical_op__rc__rc$next[0:0]$6605 + attribute \src "libresoc.v:134199.5-134199.29" switch \initial - attribute \src "libresoc.v:131864.9-131864.17" + attribute \src "libresoc.v:134199.9-134199.17" case 1'1 case end @@ -213852,7 +219225,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6328 $1\logical_op__data_len$next[3:0]$6323 $1\logical_op__is_signed$next[0:0]$6333 $1\logical_op__is_32bit$next[0:0]$6332 $1\logical_op__output_carry$next[0:0]$6336 $1\logical_op__write_cr0$next[0:0]$6339 $1\logical_op__invert_out$next[0:0]$6331 $1\logical_op__input_carry$next[1:0]$6327 $1\logical_op__zero_a$next[0:0]$6340 $1\logical_op__invert_in$next[0:0]$6330 $1\logical_op__oe__ok$next[0:0]$6335 $1\logical_op__oe__oe$next[0:0]$6334 $1\logical_op__rc__ok$next[0:0]$6337 $1\logical_op__rc__rc$next[0:0]$6338 $1\logical_op__imm_data__ok$next[0:0]$6326 $1\logical_op__imm_data__data$next[63:0]$6325 $1\logical_op__fn_unit$next[11:0]$6324 $1\logical_op__insn_type$next[6:0]$6329 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6587 $1\logical_op__data_len$next[3:0]$6582 $1\logical_op__is_signed$next[0:0]$6592 $1\logical_op__is_32bit$next[0:0]$6591 $1\logical_op__output_carry$next[0:0]$6595 $1\logical_op__write_cr0$next[0:0]$6598 $1\logical_op__invert_out$next[0:0]$6590 $1\logical_op__input_carry$next[1:0]$6586 $1\logical_op__zero_a$next[0:0]$6599 $1\logical_op__invert_in$next[0:0]$6589 $1\logical_op__oe__ok$next[0:0]$6594 $1\logical_op__oe__oe$next[0:0]$6593 $1\logical_op__rc__ok$next[0:0]$6596 $1\logical_op__rc__rc$next[0:0]$6597 $1\logical_op__imm_data__ok$next[0:0]$6585 $1\logical_op__imm_data__data$next[63:0]$6584 $1\logical_op__fn_unit$next[11:0]$6583 $1\logical_op__insn_type$next[6:0]$6588 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -213873,26 +219246,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6328 $1\logical_op__data_len$next[3:0]$6323 $1\logical_op__is_signed$next[0:0]$6333 $1\logical_op__is_32bit$next[0:0]$6332 $1\logical_op__output_carry$next[0:0]$6336 $1\logical_op__write_cr0$next[0:0]$6339 $1\logical_op__invert_out$next[0:0]$6331 $1\logical_op__input_carry$next[1:0]$6327 $1\logical_op__zero_a$next[0:0]$6340 $1\logical_op__invert_in$next[0:0]$6330 $1\logical_op__oe__ok$next[0:0]$6335 $1\logical_op__oe__oe$next[0:0]$6334 $1\logical_op__rc__ok$next[0:0]$6337 $1\logical_op__rc__rc$next[0:0]$6338 $1\logical_op__imm_data__ok$next[0:0]$6326 $1\logical_op__imm_data__data$next[63:0]$6325 $1\logical_op__fn_unit$next[11:0]$6324 $1\logical_op__insn_type$next[6:0]$6329 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6587 $1\logical_op__data_len$next[3:0]$6582 $1\logical_op__is_signed$next[0:0]$6592 $1\logical_op__is_32bit$next[0:0]$6591 $1\logical_op__output_carry$next[0:0]$6595 $1\logical_op__write_cr0$next[0:0]$6598 $1\logical_op__invert_out$next[0:0]$6590 $1\logical_op__input_carry$next[1:0]$6586 $1\logical_op__zero_a$next[0:0]$6599 $1\logical_op__invert_in$next[0:0]$6589 $1\logical_op__oe__ok$next[0:0]$6594 $1\logical_op__oe__oe$next[0:0]$6593 $1\logical_op__rc__ok$next[0:0]$6596 $1\logical_op__rc__rc$next[0:0]$6597 $1\logical_op__imm_data__ok$next[0:0]$6585 $1\logical_op__imm_data__data$next[63:0]$6584 $1\logical_op__fn_unit$next[11:0]$6583 $1\logical_op__insn_type$next[6:0]$6588 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6323 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$6324 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6325 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6326 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6327 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6328 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6329 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6330 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6331 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6332 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6333 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6334 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6335 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6336 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6337 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6338 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6339 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6340 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6582 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$6583 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6584 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6585 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6586 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6587 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6588 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6589 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6590 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6591 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6592 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6593 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6594 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6595 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6596 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6597 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6598 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6599 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -213904,52 +219277,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6341 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6342 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6346 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6345 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6343 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6344 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6600 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6601 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6605 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6604 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6602 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6603 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6341 $1\logical_op__imm_data__data$next[63:0]$6325 - assign $2\logical_op__imm_data__ok$next[0:0]$6342 $1\logical_op__imm_data__ok$next[0:0]$6326 - assign $2\logical_op__oe__oe$next[0:0]$6343 $1\logical_op__oe__oe$next[0:0]$6334 - assign $2\logical_op__oe__ok$next[0:0]$6344 $1\logical_op__oe__ok$next[0:0]$6335 - assign $2\logical_op__rc__ok$next[0:0]$6345 $1\logical_op__rc__ok$next[0:0]$6337 - assign $2\logical_op__rc__rc$next[0:0]$6346 $1\logical_op__rc__rc$next[0:0]$6338 + assign $2\logical_op__imm_data__data$next[63:0]$6600 $1\logical_op__imm_data__data$next[63:0]$6584 + assign $2\logical_op__imm_data__ok$next[0:0]$6601 $1\logical_op__imm_data__ok$next[0:0]$6585 + assign $2\logical_op__oe__oe$next[0:0]$6602 $1\logical_op__oe__oe$next[0:0]$6593 + assign $2\logical_op__oe__ok$next[0:0]$6603 $1\logical_op__oe__ok$next[0:0]$6594 + assign $2\logical_op__rc__ok$next[0:0]$6604 $1\logical_op__rc__ok$next[0:0]$6596 + assign $2\logical_op__rc__rc$next[0:0]$6605 $1\logical_op__rc__rc$next[0:0]$6597 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6305 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6306 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6307 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6308 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6309 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6310 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6311 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6312 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6313 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6314 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6315 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6316 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6317 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6318 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6319 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6320 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6321 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6322 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6564 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6565 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6566 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6567 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6568 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6569 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6570 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6571 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6572 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6573 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6574 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6575 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6576 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6577 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6578 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6579 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6580 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6581 end - attribute \src "libresoc.v:131905.3-131923.6" - process $proc$libresoc.v:131905$6347 + attribute \src "libresoc.v:134240.3-134258.6" + process $proc$libresoc.v:134240$6606 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6348 $1\o$next[63:0]$6350 + assign $0\o$next[63:0]$6607 $1\o$next[63:0]$6609 assign { } { } - assign $0\o_ok$next[0:0]$6349 $2\o_ok$next[0:0]$6352 - attribute \src "libresoc.v:131906.5-131906.29" + assign $0\o_ok$next[0:0]$6608 $2\o_ok$next[0:0]$6611 + attribute \src "libresoc.v:134241.5-134241.29" switch \initial - attribute \src "libresoc.v:131906.9-131906.17" + attribute \src "libresoc.v:134241.9-134241.17" case 1'1 case end @@ -213959,41 +219332,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6351 $1\o$next[63:0]$6350 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6610 $1\o$next[63:0]$6609 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6351 $1\o$next[63:0]$6350 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6610 $1\o$next[63:0]$6609 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6350 \o - assign $1\o_ok$next[0:0]$6351 \o_ok + assign $1\o$next[63:0]$6609 \o + assign $1\o_ok$next[0:0]$6610 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6352 1'0 + assign $2\o_ok$next[0:0]$6611 1'0 case - assign $2\o_ok$next[0:0]$6352 $1\o_ok$next[0:0]$6351 + assign $2\o_ok$next[0:0]$6611 $1\o_ok$next[0:0]$6610 end sync always - update \o$next $0\o$next[63:0]$6348 - update \o_ok$next $0\o_ok$next[0:0]$6349 + update \o$next $0\o$next[63:0]$6607 + update \o_ok$next $0\o_ok$next[0:0]$6608 end - attribute \src "libresoc.v:131924.3-131942.6" - process $proc$libresoc.v:131924$6353 + attribute \src "libresoc.v:134259.3-134277.6" + process $proc$libresoc.v:134259$6612 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6354 $1\cr_a$next[3:0]$6356 + assign $0\cr_a$next[3:0]$6613 $1\cr_a$next[3:0]$6615 assign { } { } - assign $0\cr_a_ok$next[0:0]$6355 $2\cr_a_ok$next[0:0]$6358 - attribute \src "libresoc.v:131925.5-131925.29" + assign $0\cr_a_ok$next[0:0]$6614 $2\cr_a_ok$next[0:0]$6617 + attribute \src "libresoc.v:134260.5-134260.29" switch \initial - attribute \src "libresoc.v:131925.9-131925.17" + attribute \src "libresoc.v:134260.9-134260.17" case 1'1 case end @@ -214003,41 +219376,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6357 $1\cr_a$next[3:0]$6356 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6616 $1\cr_a$next[3:0]$6615 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6357 $1\cr_a$next[3:0]$6356 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6616 $1\cr_a$next[3:0]$6615 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6356 \cr_a - assign $1\cr_a_ok$next[0:0]$6357 \cr_a_ok + assign $1\cr_a$next[3:0]$6615 \cr_a + assign $1\cr_a_ok$next[0:0]$6616 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6358 1'0 + assign $2\cr_a_ok$next[0:0]$6617 1'0 case - assign $2\cr_a_ok$next[0:0]$6358 $1\cr_a_ok$next[0:0]$6357 + assign $2\cr_a_ok$next[0:0]$6617 $1\cr_a_ok$next[0:0]$6616 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6354 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6355 + update \cr_a$next $0\cr_a$next[3:0]$6613 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6614 end - attribute \src "libresoc.v:131943.3-131961.6" - process $proc$libresoc.v:131943$6359 + attribute \src "libresoc.v:134278.3-134296.6" + process $proc$libresoc.v:134278$6618 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6360 $1\xer_so$next[0:0]$6362 + assign $0\xer_so$next[0:0]$6619 $1\xer_so$next[0:0]$6621 assign { } { } - assign $0\xer_so_ok$next[0:0]$6361 $2\xer_so_ok$next[0:0]$6364 - attribute \src "libresoc.v:131944.5-131944.29" + assign $0\xer_so_ok$next[0:0]$6620 $2\xer_so_ok$next[0:0]$6623 + attribute \src "libresoc.v:134279.5-134279.29" switch \initial - attribute \src "libresoc.v:131944.9-131944.17" + attribute \src "libresoc.v:134279.9-134279.17" case 1'1 case end @@ -214047,30 +219420,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6363 $1\xer_so$next[0:0]$6362 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6622 $1\xer_so$next[0:0]$6621 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6363 $1\xer_so$next[0:0]$6362 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6622 $1\xer_so$next[0:0]$6621 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6362 \xer_so - assign $1\xer_so_ok$next[0:0]$6363 \xer_so_ok + assign $1\xer_so$next[0:0]$6621 \xer_so + assign $1\xer_so_ok$next[0:0]$6622 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6364 1'0 + assign $2\xer_so_ok$next[0:0]$6623 1'0 case - assign $2\xer_so_ok$next[0:0]$6364 $1\xer_so_ok$next[0:0]$6363 + assign $2\xer_so_ok$next[0:0]$6623 $1\xer_so_ok$next[0:0]$6622 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6360 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6361 + update \xer_so$next $0\xer_so$next[0:0]$6619 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6620 end - connect \$64 $and$libresoc.v:131679$6270_Y + connect \$64 $and$libresoc.v:134014$6529_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -214095,250 +219468,250 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:131989.1-133007.10" +attribute \src "libresoc.v:134324.1-135342.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:132974.3-132992.6" - wire width 4 $0\cr_a$22$next[3:0]$6497 - attribute \src "libresoc.v:132778.3-132779.33" - wire width 4 $0\cr_a$22[3:0]$6394 - attribute \src "libresoc.v:132001.13-132001.29" - wire width 4 $0\cr_a$22[3:0]$6504 - attribute \src "libresoc.v:132974.3-132992.6" - wire $0\cr_a_ok$23$next[0:0]$6498 - attribute \src "libresoc.v:132780.3-132781.39" - wire $0\cr_a_ok$23[0:0]$6396 - attribute \src "libresoc.v:132010.7-132010.26" - wire $0\cr_a_ok$23[0:0]$6506 - attribute \src "libresoc.v:131990.7-131990.20" + attribute \src "libresoc.v:135309.3-135327.6" + wire width 4 $0\cr_a$22$next[3:0]$6756 + attribute \src "libresoc.v:135113.3-135114.33" + wire width 4 $0\cr_a$22[3:0]$6653 + attribute \src "libresoc.v:134336.13-134336.29" + wire width 4 $0\cr_a$22[3:0]$6763 + attribute \src "libresoc.v:135309.3-135327.6" + wire $0\cr_a_ok$23$next[0:0]$6757 + attribute \src "libresoc.v:135115.3-135116.39" + wire $0\cr_a_ok$23[0:0]$6655 + attribute \src "libresoc.v:134345.7-134345.26" + wire $0\cr_a_ok$23[0:0]$6765 + attribute \src "libresoc.v:134325.7-134325.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132913.3-132954.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6448 - attribute \src "libresoc.v:132818.3-132819.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6434 - attribute \src "libresoc.v:132021.13-132021.45" - wire width 4 $0\logical_op__data_len$18[3:0]$6508 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6449 - attribute \src "libresoc.v:132788.3-132789.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6404 - attribute \src "libresoc.v:132056.14-132056.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6510 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6450 - attribute \src "libresoc.v:132790.3-132791.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6406 - attribute \src "libresoc.v:132078.14-132078.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6512 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6451 - attribute \src "libresoc.v:132792.3-132793.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6408 - attribute \src "libresoc.v:132087.7-132087.42" - wire $0\logical_op__imm_data__ok$5[0:0]$6514 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6452 - attribute \src "libresoc.v:132806.3-132807.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6422 - attribute \src "libresoc.v:132104.13-132104.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$6516 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6453 - attribute \src "libresoc.v:132820.3-132821.57" - wire width 32 $0\logical_op__insn$19[31:0]$6436 - attribute \src "libresoc.v:132117.14-132117.43" - wire width 32 $0\logical_op__insn$19[31:0]$6518 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6454 - attribute \src "libresoc.v:132786.3-132787.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6402 - attribute \src "libresoc.v:132274.13-132274.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$6520 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__invert_in$10$next[0:0]$6455 - attribute \src "libresoc.v:132802.3-132803.67" - wire $0\logical_op__invert_in$10[0:0]$6418 - attribute \src "libresoc.v:132357.7-132357.40" - wire $0\logical_op__invert_in$10[0:0]$6522 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__invert_out$13$next[0:0]$6456 - attribute \src "libresoc.v:132808.3-132809.69" - wire $0\logical_op__invert_out$13[0:0]$6424 - attribute \src "libresoc.v:132366.7-132366.41" - wire $0\logical_op__invert_out$13[0:0]$6524 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6457 - attribute \src "libresoc.v:132814.3-132815.65" - wire $0\logical_op__is_32bit$16[0:0]$6430 - attribute \src "libresoc.v:132375.7-132375.39" - wire $0\logical_op__is_32bit$16[0:0]$6526 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__is_signed$17$next[0:0]$6458 - attribute \src "libresoc.v:132816.3-132817.67" - wire $0\logical_op__is_signed$17[0:0]$6432 - attribute \src "libresoc.v:132384.7-132384.40" - wire $0\logical_op__is_signed$17[0:0]$6528 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__oe__oe$8$next[0:0]$6459 - attribute \src "libresoc.v:132798.3-132799.59" - wire $0\logical_op__oe__oe$8[0:0]$6414 - attribute \src "libresoc.v:132395.7-132395.36" - wire $0\logical_op__oe__oe$8[0:0]$6530 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__oe__ok$9$next[0:0]$6460 - attribute \src "libresoc.v:132800.3-132801.59" - wire $0\logical_op__oe__ok$9[0:0]$6416 - attribute \src "libresoc.v:132404.7-132404.36" - wire $0\logical_op__oe__ok$9[0:0]$6532 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__output_carry$15$next[0:0]$6461 - attribute \src "libresoc.v:132812.3-132813.73" - wire $0\logical_op__output_carry$15[0:0]$6428 - attribute \src "libresoc.v:132411.7-132411.43" - wire $0\logical_op__output_carry$15[0:0]$6534 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__rc__ok$7$next[0:0]$6462 - attribute \src "libresoc.v:132796.3-132797.59" - wire $0\logical_op__rc__ok$7[0:0]$6412 - attribute \src "libresoc.v:132422.7-132422.36" - wire $0\logical_op__rc__ok$7[0:0]$6536 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__rc__rc$6$next[0:0]$6463 - attribute \src "libresoc.v:132794.3-132795.59" - wire $0\logical_op__rc__rc$6[0:0]$6410 - attribute \src "libresoc.v:132431.7-132431.36" - wire $0\logical_op__rc__rc$6[0:0]$6538 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__write_cr0$14$next[0:0]$6464 - attribute \src "libresoc.v:132810.3-132811.67" - wire $0\logical_op__write_cr0$14[0:0]$6426 - attribute \src "libresoc.v:132438.7-132438.40" - wire $0\logical_op__write_cr0$14[0:0]$6540 - attribute \src "libresoc.v:132913.3-132954.6" - wire $0\logical_op__zero_a$11$next[0:0]$6465 - attribute \src "libresoc.v:132804.3-132805.61" - wire $0\logical_op__zero_a$11[0:0]$6420 - attribute \src "libresoc.v:132447.7-132447.37" - wire $0\logical_op__zero_a$11[0:0]$6542 - attribute \src "libresoc.v:132900.3-132912.6" - wire width 2 $0\muxid$1$next[1:0]$6445 - attribute \src "libresoc.v:132822.3-132823.33" - wire width 2 $0\muxid$1[1:0]$6438 - attribute \src "libresoc.v:132456.13-132456.29" - wire width 2 $0\muxid$1[1:0]$6544 - attribute \src "libresoc.v:132955.3-132973.6" - wire width 64 $0\o$20$next[63:0]$6491 - attribute \src "libresoc.v:132782.3-132783.27" - wire width 64 $0\o$20[63:0]$6398 - attribute \src "libresoc.v:132471.14-132471.43" - wire width 64 $0\o$20[63:0]$6546 - attribute \src "libresoc.v:132955.3-132973.6" - wire $0\o_ok$21$next[0:0]$6492 - attribute \src "libresoc.v:132784.3-132785.33" - wire $0\o_ok$21[0:0]$6400 - attribute \src "libresoc.v:132480.7-132480.23" - wire $0\o_ok$21[0:0]$6548 - attribute \src "libresoc.v:132882.3-132899.6" - wire $0\r_busy$next[0:0]$6441 - attribute \src "libresoc.v:132824.3-132825.29" + attribute \src "libresoc.v:135248.3-135289.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6707 + attribute \src "libresoc.v:135153.3-135154.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6693 + attribute \src "libresoc.v:134356.13-134356.45" + wire width 4 $0\logical_op__data_len$18[3:0]$6767 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6708 + attribute \src "libresoc.v:135123.3-135124.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6663 + attribute \src "libresoc.v:134391.14-134391.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6769 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6709 + attribute \src "libresoc.v:135125.3-135126.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6665 + attribute \src "libresoc.v:134413.14-134413.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6771 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6710 + attribute \src "libresoc.v:135127.3-135128.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6667 + attribute \src "libresoc.v:134422.7-134422.42" + wire $0\logical_op__imm_data__ok$5[0:0]$6773 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6711 + attribute \src "libresoc.v:135141.3-135142.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6681 + attribute \src "libresoc.v:134439.13-134439.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$6775 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6712 + attribute \src "libresoc.v:135155.3-135156.57" + wire width 32 $0\logical_op__insn$19[31:0]$6695 + attribute \src "libresoc.v:134452.14-134452.43" + wire width 32 $0\logical_op__insn$19[31:0]$6777 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6713 + attribute \src "libresoc.v:135121.3-135122.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6661 + attribute \src "libresoc.v:134609.13-134609.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$6779 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__invert_in$10$next[0:0]$6714 + attribute \src "libresoc.v:135137.3-135138.67" + wire $0\logical_op__invert_in$10[0:0]$6677 + attribute \src "libresoc.v:134692.7-134692.40" + wire $0\logical_op__invert_in$10[0:0]$6781 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__invert_out$13$next[0:0]$6715 + attribute \src "libresoc.v:135143.3-135144.69" + wire $0\logical_op__invert_out$13[0:0]$6683 + attribute \src "libresoc.v:134701.7-134701.41" + wire $0\logical_op__invert_out$13[0:0]$6783 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6716 + attribute \src "libresoc.v:135149.3-135150.65" + wire $0\logical_op__is_32bit$16[0:0]$6689 + attribute \src "libresoc.v:134710.7-134710.39" + wire $0\logical_op__is_32bit$16[0:0]$6785 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__is_signed$17$next[0:0]$6717 + attribute \src "libresoc.v:135151.3-135152.67" + wire $0\logical_op__is_signed$17[0:0]$6691 + attribute \src "libresoc.v:134719.7-134719.40" + wire $0\logical_op__is_signed$17[0:0]$6787 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__oe__oe$8$next[0:0]$6718 + attribute \src "libresoc.v:135133.3-135134.59" + wire $0\logical_op__oe__oe$8[0:0]$6673 + attribute \src "libresoc.v:134730.7-134730.36" + wire $0\logical_op__oe__oe$8[0:0]$6789 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__oe__ok$9$next[0:0]$6719 + attribute \src "libresoc.v:135135.3-135136.59" + wire $0\logical_op__oe__ok$9[0:0]$6675 + attribute \src "libresoc.v:134739.7-134739.36" + wire $0\logical_op__oe__ok$9[0:0]$6791 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__output_carry$15$next[0:0]$6720 + attribute \src "libresoc.v:135147.3-135148.73" + wire $0\logical_op__output_carry$15[0:0]$6687 + attribute \src "libresoc.v:134746.7-134746.43" + wire $0\logical_op__output_carry$15[0:0]$6793 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__rc__ok$7$next[0:0]$6721 + attribute \src "libresoc.v:135131.3-135132.59" + wire $0\logical_op__rc__ok$7[0:0]$6671 + attribute \src "libresoc.v:134757.7-134757.36" + wire $0\logical_op__rc__ok$7[0:0]$6795 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__rc__rc$6$next[0:0]$6722 + attribute \src "libresoc.v:135129.3-135130.59" + wire $0\logical_op__rc__rc$6[0:0]$6669 + attribute \src "libresoc.v:134766.7-134766.36" + wire $0\logical_op__rc__rc$6[0:0]$6797 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__write_cr0$14$next[0:0]$6723 + attribute \src "libresoc.v:135145.3-135146.67" + wire $0\logical_op__write_cr0$14[0:0]$6685 + attribute \src "libresoc.v:134773.7-134773.40" + wire $0\logical_op__write_cr0$14[0:0]$6799 + attribute \src "libresoc.v:135248.3-135289.6" + wire $0\logical_op__zero_a$11$next[0:0]$6724 + attribute \src "libresoc.v:135139.3-135140.61" + wire $0\logical_op__zero_a$11[0:0]$6679 + attribute \src "libresoc.v:134782.7-134782.37" + wire $0\logical_op__zero_a$11[0:0]$6801 + attribute \src "libresoc.v:135235.3-135247.6" + wire width 2 $0\muxid$1$next[1:0]$6704 + attribute \src "libresoc.v:135157.3-135158.33" + wire width 2 $0\muxid$1[1:0]$6697 + attribute \src "libresoc.v:134791.13-134791.29" + wire width 2 $0\muxid$1[1:0]$6803 + attribute \src "libresoc.v:135290.3-135308.6" + wire width 64 $0\o$20$next[63:0]$6750 + attribute \src "libresoc.v:135117.3-135118.27" + wire width 64 $0\o$20[63:0]$6657 + attribute \src "libresoc.v:134806.14-134806.43" + wire width 64 $0\o$20[63:0]$6805 + attribute \src "libresoc.v:135290.3-135308.6" + wire $0\o_ok$21$next[0:0]$6751 + attribute \src "libresoc.v:135119.3-135120.33" + wire $0\o_ok$21[0:0]$6659 + attribute \src "libresoc.v:134815.7-134815.23" + wire $0\o_ok$21[0:0]$6807 + attribute \src "libresoc.v:135217.3-135234.6" + wire $0\r_busy$next[0:0]$6700 + attribute \src "libresoc.v:135159.3-135160.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:132974.3-132992.6" - wire width 4 $1\cr_a$22$next[3:0]$6499 - attribute \src "libresoc.v:132974.3-132992.6" - wire $1\cr_a_ok$23$next[0:0]$6500 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$6466 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6467 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6468 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$6469 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$6470 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$6471 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$6472 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__invert_in$10$next[0:0]$6473 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__invert_out$13$next[0:0]$6474 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__is_32bit$16$next[0:0]$6475 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__is_signed$17$next[0:0]$6476 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__oe__oe$8$next[0:0]$6477 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__oe__ok$9$next[0:0]$6478 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__output_carry$15$next[0:0]$6479 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__rc__ok$7$next[0:0]$6480 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__rc__rc$6$next[0:0]$6481 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__write_cr0$14$next[0:0]$6482 - attribute \src "libresoc.v:132913.3-132954.6" - wire $1\logical_op__zero_a$11$next[0:0]$6483 - attribute \src "libresoc.v:132900.3-132912.6" - wire width 2 $1\muxid$1$next[1:0]$6446 - attribute \src "libresoc.v:132955.3-132973.6" - wire width 64 $1\o$20$next[63:0]$6493 - attribute \src "libresoc.v:132955.3-132973.6" - wire $1\o_ok$21$next[0:0]$6494 - attribute \src "libresoc.v:132882.3-132899.6" - wire $1\r_busy$next[0:0]$6442 - attribute \src "libresoc.v:132768.7-132768.20" + attribute \src "libresoc.v:135309.3-135327.6" + wire width 4 $1\cr_a$22$next[3:0]$6758 + attribute \src "libresoc.v:135309.3-135327.6" + wire $1\cr_a_ok$23$next[0:0]$6759 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$6725 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6726 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6727 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$6728 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$6729 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$6730 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$6731 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__invert_in$10$next[0:0]$6732 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__invert_out$13$next[0:0]$6733 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__is_32bit$16$next[0:0]$6734 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__is_signed$17$next[0:0]$6735 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__oe__oe$8$next[0:0]$6736 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__oe__ok$9$next[0:0]$6737 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__output_carry$15$next[0:0]$6738 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__rc__ok$7$next[0:0]$6739 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__rc__rc$6$next[0:0]$6740 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__write_cr0$14$next[0:0]$6741 + attribute \src "libresoc.v:135248.3-135289.6" + wire $1\logical_op__zero_a$11$next[0:0]$6742 + attribute \src "libresoc.v:135235.3-135247.6" + wire width 2 $1\muxid$1$next[1:0]$6705 + attribute \src "libresoc.v:135290.3-135308.6" + wire width 64 $1\o$20$next[63:0]$6752 + attribute \src "libresoc.v:135290.3-135308.6" + wire $1\o_ok$21$next[0:0]$6753 + attribute \src "libresoc.v:135217.3-135234.6" + wire $1\r_busy$next[0:0]$6701 + attribute \src "libresoc.v:135103.7-135103.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:132974.3-132992.6" - wire $2\cr_a_ok$23$next[0:0]$6501 - attribute \src "libresoc.v:132913.3-132954.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6484 - attribute \src "libresoc.v:132913.3-132954.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$6485 - attribute \src "libresoc.v:132913.3-132954.6" - wire $2\logical_op__oe__oe$8$next[0:0]$6486 - attribute \src "libresoc.v:132913.3-132954.6" - wire $2\logical_op__oe__ok$9$next[0:0]$6487 - attribute \src "libresoc.v:132913.3-132954.6" - wire $2\logical_op__rc__ok$7$next[0:0]$6488 - attribute \src "libresoc.v:132913.3-132954.6" - wire $2\logical_op__rc__rc$6$next[0:0]$6489 - attribute \src "libresoc.v:132955.3-132973.6" - wire $2\o_ok$21$next[0:0]$6495 - attribute \src "libresoc.v:132882.3-132899.6" - wire $2\r_busy$next[0:0]$6443 - attribute \src "libresoc.v:132777.18-132777.118" - wire $and$libresoc.v:132777$6392_Y + attribute \src "libresoc.v:135309.3-135327.6" + wire $2\cr_a_ok$23$next[0:0]$6760 + attribute \src "libresoc.v:135248.3-135289.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6743 + attribute \src "libresoc.v:135248.3-135289.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$6744 + attribute \src "libresoc.v:135248.3-135289.6" + wire $2\logical_op__oe__oe$8$next[0:0]$6745 + attribute \src "libresoc.v:135248.3-135289.6" + wire $2\logical_op__oe__ok$9$next[0:0]$6746 + attribute \src "libresoc.v:135248.3-135289.6" + wire $2\logical_op__rc__ok$7$next[0:0]$6747 + attribute \src "libresoc.v:135248.3-135289.6" + wire $2\logical_op__rc__rc$6$next[0:0]$6748 + attribute \src "libresoc.v:135290.3-135308.6" + wire $2\o_ok$21$next[0:0]$6754 + attribute \src "libresoc.v:135217.3-135234.6" + wire $2\r_busy$next[0:0]$6702 + attribute \src "libresoc.v:135112.18-135112.118" + wire $and$libresoc.v:135112$6651_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 52 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:131990.7-131990.15" + attribute \src "libresoc.v:134325.7-134325.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -214771,27 +220144,27 @@ module \logical_pipe2 wire input 30 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 50 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 51 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len @@ -215051,15 +220424,15 @@ module \logical_pipe2 wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o @@ -215073,14 +220446,14 @@ module \logical_pipe2 wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:132777$6392 + cell $and $and$libresoc.v:135112$6651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -215088,17 +220461,17 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:132777$6392_Y + connect \Y $and$libresoc.v:135112$6651_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:132826.10-132829.4" - cell \n$50 \n + attribute \src "libresoc.v:135161.10-135164.4" + cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:132830.15-132877.4" - cell \output$51 \output + attribute \src "libresoc.v:135165.15-135212.4" + cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok @@ -215147,388 +220520,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:132878.10-132881.4" - cell \p$49 \p + attribute \src "libresoc.v:135213.10-135216.4" + cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:131990.7-131990.20" - process $proc$libresoc.v:131990$6502 + attribute \src "libresoc.v:134325.7-134325.20" + process $proc$libresoc.v:134325$6761 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132001.13-132001.29" - process $proc$libresoc.v:132001$6503 + attribute \src "libresoc.v:134336.13-134336.29" + process $proc$libresoc.v:134336$6762 assign { } { } - assign $0\cr_a$22[3:0]$6504 4'0000 + assign $0\cr_a$22[3:0]$6763 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$6504 + update \cr_a$22 $0\cr_a$22[3:0]$6763 end - attribute \src "libresoc.v:132010.7-132010.26" - process $proc$libresoc.v:132010$6505 + attribute \src "libresoc.v:134345.7-134345.26" + process $proc$libresoc.v:134345$6764 assign { } { } - assign $0\cr_a_ok$23[0:0]$6506 1'0 + assign $0\cr_a_ok$23[0:0]$6765 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6506 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6765 end - attribute \src "libresoc.v:132021.13-132021.45" - process $proc$libresoc.v:132021$6507 + attribute \src "libresoc.v:134356.13-134356.45" + process $proc$libresoc.v:134356$6766 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6508 4'0000 + assign $0\logical_op__data_len$18[3:0]$6767 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6508 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6767 end - attribute \src "libresoc.v:132056.14-132056.47" - process $proc$libresoc.v:132056$6509 + attribute \src "libresoc.v:134391.14-134391.47" + process $proc$libresoc.v:134391$6768 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6510 12'000000000000 + assign $0\logical_op__fn_unit$3[11:0]$6769 12'000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6510 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6769 end - attribute \src "libresoc.v:132078.14-132078.67" - process $proc$libresoc.v:132078$6511 + attribute \src "libresoc.v:134413.14-134413.67" + process $proc$libresoc.v:134413$6770 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6512 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$6771 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6512 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6771 end - attribute \src "libresoc.v:132087.7-132087.42" - process $proc$libresoc.v:132087$6513 + attribute \src "libresoc.v:134422.7-134422.42" + process $proc$libresoc.v:134422$6772 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6514 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$6773 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6514 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6773 end - attribute \src "libresoc.v:132104.13-132104.48" - process $proc$libresoc.v:132104$6515 + attribute \src "libresoc.v:134439.13-134439.48" + process $proc$libresoc.v:134439$6774 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6516 2'00 + assign $0\logical_op__input_carry$12[1:0]$6775 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6516 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6775 end - attribute \src "libresoc.v:132117.14-132117.43" - process $proc$libresoc.v:132117$6517 + attribute \src "libresoc.v:134452.14-134452.43" + process $proc$libresoc.v:134452$6776 assign { } { } - assign $0\logical_op__insn$19[31:0]$6518 0 + assign $0\logical_op__insn$19[31:0]$6777 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6518 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6777 end - attribute \src "libresoc.v:132274.13-132274.46" - process $proc$libresoc.v:132274$6519 + attribute \src "libresoc.v:134609.13-134609.46" + process $proc$libresoc.v:134609$6778 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6520 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$6779 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6520 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6779 end - attribute \src "libresoc.v:132357.7-132357.40" - process $proc$libresoc.v:132357$6521 + attribute \src "libresoc.v:134692.7-134692.40" + process $proc$libresoc.v:134692$6780 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6522 1'0 + assign $0\logical_op__invert_in$10[0:0]$6781 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6522 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6781 end - attribute \src "libresoc.v:132366.7-132366.41" - process $proc$libresoc.v:132366$6523 + attribute \src "libresoc.v:134701.7-134701.41" + process $proc$libresoc.v:134701$6782 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6524 1'0 + assign $0\logical_op__invert_out$13[0:0]$6783 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6524 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6783 end - attribute \src "libresoc.v:132375.7-132375.39" - process $proc$libresoc.v:132375$6525 + attribute \src "libresoc.v:134710.7-134710.39" + process $proc$libresoc.v:134710$6784 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6526 1'0 + assign $0\logical_op__is_32bit$16[0:0]$6785 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6526 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6785 end - attribute \src "libresoc.v:132384.7-132384.40" - process $proc$libresoc.v:132384$6527 + attribute \src "libresoc.v:134719.7-134719.40" + process $proc$libresoc.v:134719$6786 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6528 1'0 + assign $0\logical_op__is_signed$17[0:0]$6787 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6528 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6787 end - attribute \src "libresoc.v:132395.7-132395.36" - process $proc$libresoc.v:132395$6529 + attribute \src "libresoc.v:134730.7-134730.36" + process $proc$libresoc.v:134730$6788 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6530 1'0 + assign $0\logical_op__oe__oe$8[0:0]$6789 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6530 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6789 end - attribute \src "libresoc.v:132404.7-132404.36" - process $proc$libresoc.v:132404$6531 + attribute \src "libresoc.v:134739.7-134739.36" + process $proc$libresoc.v:134739$6790 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6532 1'0 + assign $0\logical_op__oe__ok$9[0:0]$6791 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6532 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6791 end - attribute \src "libresoc.v:132411.7-132411.43" - process $proc$libresoc.v:132411$6533 + attribute \src "libresoc.v:134746.7-134746.43" + process $proc$libresoc.v:134746$6792 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6534 1'0 + assign $0\logical_op__output_carry$15[0:0]$6793 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6534 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6793 end - attribute \src "libresoc.v:132422.7-132422.36" - process $proc$libresoc.v:132422$6535 + attribute \src "libresoc.v:134757.7-134757.36" + process $proc$libresoc.v:134757$6794 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6536 1'0 + assign $0\logical_op__rc__ok$7[0:0]$6795 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6536 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6795 end - attribute \src "libresoc.v:132431.7-132431.36" - process $proc$libresoc.v:132431$6537 + attribute \src "libresoc.v:134766.7-134766.36" + process $proc$libresoc.v:134766$6796 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6538 1'0 + assign $0\logical_op__rc__rc$6[0:0]$6797 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6538 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6797 end - attribute \src "libresoc.v:132438.7-132438.40" - process $proc$libresoc.v:132438$6539 + attribute \src "libresoc.v:134773.7-134773.40" + process $proc$libresoc.v:134773$6798 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6540 1'0 + assign $0\logical_op__write_cr0$14[0:0]$6799 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6540 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6799 end - attribute \src "libresoc.v:132447.7-132447.37" - process $proc$libresoc.v:132447$6541 + attribute \src "libresoc.v:134782.7-134782.37" + process $proc$libresoc.v:134782$6800 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6542 1'0 + assign $0\logical_op__zero_a$11[0:0]$6801 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6542 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6801 end - attribute \src "libresoc.v:132456.13-132456.29" - process $proc$libresoc.v:132456$6543 + attribute \src "libresoc.v:134791.13-134791.29" + process $proc$libresoc.v:134791$6802 assign { } { } - assign $0\muxid$1[1:0]$6544 2'00 + assign $0\muxid$1[1:0]$6803 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$6544 + update \muxid$1 $0\muxid$1[1:0]$6803 end - attribute \src "libresoc.v:132471.14-132471.43" - process $proc$libresoc.v:132471$6545 + attribute \src "libresoc.v:134806.14-134806.43" + process $proc$libresoc.v:134806$6804 assign { } { } - assign $0\o$20[63:0]$6546 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$6805 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$6546 + update \o$20 $0\o$20[63:0]$6805 end - attribute \src "libresoc.v:132480.7-132480.23" - process $proc$libresoc.v:132480$6547 + attribute \src "libresoc.v:134815.7-134815.23" + process $proc$libresoc.v:134815$6806 assign { } { } - assign $0\o_ok$21[0:0]$6548 1'0 + assign $0\o_ok$21[0:0]$6807 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$6548 + update \o_ok$21 $0\o_ok$21[0:0]$6807 end - attribute \src "libresoc.v:132768.7-132768.20" - process $proc$libresoc.v:132768$6549 + attribute \src "libresoc.v:135103.7-135103.20" + process $proc$libresoc.v:135103$6808 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:132778.3-132779.33" - process $proc$libresoc.v:132778$6393 + attribute \src "libresoc.v:135113.3-135114.33" + process $proc$libresoc.v:135113$6652 assign { } { } - assign $0\cr_a$22[3:0]$6394 \cr_a$22$next + assign $0\cr_a$22[3:0]$6653 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6394 + update \cr_a$22 $0\cr_a$22[3:0]$6653 end - attribute \src "libresoc.v:132780.3-132781.39" - process $proc$libresoc.v:132780$6395 + attribute \src "libresoc.v:135115.3-135116.39" + process $proc$libresoc.v:135115$6654 assign { } { } - assign $0\cr_a_ok$23[0:0]$6396 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6655 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6396 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6655 end - attribute \src "libresoc.v:132782.3-132783.27" - process $proc$libresoc.v:132782$6397 + attribute \src "libresoc.v:135117.3-135118.27" + process $proc$libresoc.v:135117$6656 assign { } { } - assign $0\o$20[63:0]$6398 \o$20$next + assign $0\o$20[63:0]$6657 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6398 + update \o$20 $0\o$20[63:0]$6657 end - attribute \src "libresoc.v:132784.3-132785.33" - process $proc$libresoc.v:132784$6399 + attribute \src "libresoc.v:135119.3-135120.33" + process $proc$libresoc.v:135119$6658 assign { } { } - assign $0\o_ok$21[0:0]$6400 \o_ok$21$next + assign $0\o_ok$21[0:0]$6659 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6400 + update \o_ok$21 $0\o_ok$21[0:0]$6659 end - attribute \src "libresoc.v:132786.3-132787.65" - process $proc$libresoc.v:132786$6401 + attribute \src "libresoc.v:135121.3-135122.65" + process $proc$libresoc.v:135121$6660 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6402 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6661 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6402 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6661 end - attribute \src "libresoc.v:132788.3-132789.61" - process $proc$libresoc.v:132788$6403 + attribute \src "libresoc.v:135123.3-135124.61" + process $proc$libresoc.v:135123$6662 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6404 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[11:0]$6663 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6404 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6663 end - attribute \src "libresoc.v:132790.3-132791.75" - process $proc$libresoc.v:132790$6405 + attribute \src "libresoc.v:135125.3-135126.75" + process $proc$libresoc.v:135125$6664 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6406 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6665 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6406 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6665 end - attribute \src "libresoc.v:132792.3-132793.71" - process $proc$libresoc.v:132792$6407 + attribute \src "libresoc.v:135127.3-135128.71" + process $proc$libresoc.v:135127$6666 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6408 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6667 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6408 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6667 end - attribute \src "libresoc.v:132794.3-132795.59" - process $proc$libresoc.v:132794$6409 + attribute \src "libresoc.v:135129.3-135130.59" + process $proc$libresoc.v:135129$6668 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6410 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6669 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6410 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6669 end - attribute \src "libresoc.v:132796.3-132797.59" - process $proc$libresoc.v:132796$6411 + attribute \src "libresoc.v:135131.3-135132.59" + process $proc$libresoc.v:135131$6670 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6412 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$6671 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6412 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6671 end - attribute \src "libresoc.v:132798.3-132799.59" - process $proc$libresoc.v:132798$6413 + attribute \src "libresoc.v:135133.3-135134.59" + process $proc$libresoc.v:135133$6672 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6414 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$6673 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6414 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6673 end - attribute \src "libresoc.v:132800.3-132801.59" - process $proc$libresoc.v:132800$6415 + attribute \src "libresoc.v:135135.3-135136.59" + process $proc$libresoc.v:135135$6674 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6416 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$6675 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6416 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6675 end - attribute \src "libresoc.v:132802.3-132803.67" - process $proc$libresoc.v:132802$6417 + attribute \src "libresoc.v:135137.3-135138.67" + process $proc$libresoc.v:135137$6676 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6418 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$6677 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6418 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6677 end - attribute \src "libresoc.v:132804.3-132805.61" - process $proc$libresoc.v:132804$6419 + attribute \src "libresoc.v:135139.3-135140.61" + process $proc$libresoc.v:135139$6678 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6420 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$6679 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6420 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6679 end - attribute \src "libresoc.v:132806.3-132807.71" - process $proc$libresoc.v:132806$6421 + attribute \src "libresoc.v:135141.3-135142.71" + process $proc$libresoc.v:135141$6680 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6422 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$6681 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6422 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6681 end - attribute \src "libresoc.v:132808.3-132809.69" - process $proc$libresoc.v:132808$6423 + attribute \src "libresoc.v:135143.3-135144.69" + process $proc$libresoc.v:135143$6682 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6424 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$6683 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6424 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6683 end - attribute \src "libresoc.v:132810.3-132811.67" - process $proc$libresoc.v:132810$6425 + attribute \src "libresoc.v:135145.3-135146.67" + process $proc$libresoc.v:135145$6684 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6426 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$6685 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6426 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6685 end - attribute \src "libresoc.v:132812.3-132813.73" - process $proc$libresoc.v:132812$6427 + attribute \src "libresoc.v:135147.3-135148.73" + process $proc$libresoc.v:135147$6686 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6428 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$6687 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6428 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6687 end - attribute \src "libresoc.v:132814.3-132815.65" - process $proc$libresoc.v:132814$6429 + attribute \src "libresoc.v:135149.3-135150.65" + process $proc$libresoc.v:135149$6688 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6430 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$6689 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6430 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6689 end - attribute \src "libresoc.v:132816.3-132817.67" - process $proc$libresoc.v:132816$6431 + attribute \src "libresoc.v:135151.3-135152.67" + process $proc$libresoc.v:135151$6690 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6432 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$6691 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6432 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6691 end - attribute \src "libresoc.v:132818.3-132819.65" - process $proc$libresoc.v:132818$6433 + attribute \src "libresoc.v:135153.3-135154.65" + process $proc$libresoc.v:135153$6692 assign { } { } - assign $0\logical_op__data_len$18[3:0]$6434 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$6693 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6434 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6693 end - attribute \src "libresoc.v:132820.3-132821.57" - process $proc$libresoc.v:132820$6435 + attribute \src "libresoc.v:135155.3-135156.57" + process $proc$libresoc.v:135155$6694 assign { } { } - assign $0\logical_op__insn$19[31:0]$6436 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$6695 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6436 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6695 end - attribute \src "libresoc.v:132822.3-132823.33" - process $proc$libresoc.v:132822$6437 + attribute \src "libresoc.v:135157.3-135158.33" + process $proc$libresoc.v:135157$6696 assign { } { } - assign $0\muxid$1[1:0]$6438 \muxid$1$next + assign $0\muxid$1[1:0]$6697 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6438 + update \muxid$1 $0\muxid$1[1:0]$6697 end - attribute \src "libresoc.v:132824.3-132825.29" - process $proc$libresoc.v:132824$6439 + attribute \src "libresoc.v:135159.3-135160.29" + process $proc$libresoc.v:135159$6698 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:132882.3-132899.6" - process $proc$libresoc.v:132882$6440 + attribute \src "libresoc.v:135217.3-135234.6" + process $proc$libresoc.v:135217$6699 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6441 $2\r_busy$next[0:0]$6443 - attribute \src "libresoc.v:132883.5-132883.29" + assign $0\r_busy$next[0:0]$6700 $2\r_busy$next[0:0]$6702 + attribute \src "libresoc.v:135218.5-135218.29" switch \initial - attribute \src "libresoc.v:132883.9-132883.17" + attribute \src "libresoc.v:135218.9-135218.17" case 1'1 case end @@ -215537,34 +220910,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6442 1'1 + assign $1\r_busy$next[0:0]$6701 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6442 1'0 + assign $1\r_busy$next[0:0]$6701 1'0 case - assign $1\r_busy$next[0:0]$6442 \r_busy + assign $1\r_busy$next[0:0]$6701 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6443 1'0 + assign $2\r_busy$next[0:0]$6702 1'0 case - assign $2\r_busy$next[0:0]$6443 $1\r_busy$next[0:0]$6442 + assign $2\r_busy$next[0:0]$6702 $1\r_busy$next[0:0]$6701 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6441 + update \r_busy$next $0\r_busy$next[0:0]$6700 end - attribute \src "libresoc.v:132900.3-132912.6" - process $proc$libresoc.v:132900$6444 + attribute \src "libresoc.v:135235.3-135247.6" + process $proc$libresoc.v:135235$6703 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$6445 $1\muxid$1$next[1:0]$6446 - attribute \src "libresoc.v:132901.5-132901.29" + assign $0\muxid$1$next[1:0]$6704 $1\muxid$1$next[1:0]$6705 + attribute \src "libresoc.v:135236.5-135236.29" switch \initial - attribute \src "libresoc.v:132901.9-132901.17" + attribute \src "libresoc.v:135236.9-135236.17" case 1'1 case end @@ -215573,19 +220946,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$6446 \muxid$51 + assign $1\muxid$1$next[1:0]$6705 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$6446 \muxid$51 + assign $1\muxid$1$next[1:0]$6705 \muxid$51 case - assign $1\muxid$1$next[1:0]$6446 \muxid$1 + assign $1\muxid$1$next[1:0]$6705 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6445 + update \muxid$1$next $0\muxid$1$next[1:0]$6704 end - attribute \src "libresoc.v:132913.3-132954.6" - process $proc$libresoc.v:132913$6447 + attribute \src "libresoc.v:135248.3-135289.6" + process $proc$libresoc.v:135248$6706 assign { } { } assign { } { } assign { } { } @@ -215622,33 +220995,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6448 $1\logical_op__data_len$18$next[3:0]$6466 - assign $0\logical_op__fn_unit$3$next[11:0]$6449 $1\logical_op__fn_unit$3$next[11:0]$6467 + assign $0\logical_op__data_len$18$next[3:0]$6707 $1\logical_op__data_len$18$next[3:0]$6725 + assign $0\logical_op__fn_unit$3$next[11:0]$6708 $1\logical_op__fn_unit$3$next[11:0]$6726 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6452 $1\logical_op__input_carry$12$next[1:0]$6470 - assign $0\logical_op__insn$19$next[31:0]$6453 $1\logical_op__insn$19$next[31:0]$6471 - assign $0\logical_op__insn_type$2$next[6:0]$6454 $1\logical_op__insn_type$2$next[6:0]$6472 - assign $0\logical_op__invert_in$10$next[0:0]$6455 $1\logical_op__invert_in$10$next[0:0]$6473 - assign $0\logical_op__invert_out$13$next[0:0]$6456 $1\logical_op__invert_out$13$next[0:0]$6474 - assign $0\logical_op__is_32bit$16$next[0:0]$6457 $1\logical_op__is_32bit$16$next[0:0]$6475 - assign $0\logical_op__is_signed$17$next[0:0]$6458 $1\logical_op__is_signed$17$next[0:0]$6476 + assign $0\logical_op__input_carry$12$next[1:0]$6711 $1\logical_op__input_carry$12$next[1:0]$6729 + assign $0\logical_op__insn$19$next[31:0]$6712 $1\logical_op__insn$19$next[31:0]$6730 + assign $0\logical_op__insn_type$2$next[6:0]$6713 $1\logical_op__insn_type$2$next[6:0]$6731 + assign $0\logical_op__invert_in$10$next[0:0]$6714 $1\logical_op__invert_in$10$next[0:0]$6732 + assign $0\logical_op__invert_out$13$next[0:0]$6715 $1\logical_op__invert_out$13$next[0:0]$6733 + assign $0\logical_op__is_32bit$16$next[0:0]$6716 $1\logical_op__is_32bit$16$next[0:0]$6734 + assign $0\logical_op__is_signed$17$next[0:0]$6717 $1\logical_op__is_signed$17$next[0:0]$6735 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$6461 $1\logical_op__output_carry$15$next[0:0]$6479 + assign $0\logical_op__output_carry$15$next[0:0]$6720 $1\logical_op__output_carry$15$next[0:0]$6738 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$6464 $1\logical_op__write_cr0$14$next[0:0]$6482 - assign $0\logical_op__zero_a$11$next[0:0]$6465 $1\logical_op__zero_a$11$next[0:0]$6483 - assign $0\logical_op__imm_data__data$4$next[63:0]$6450 $2\logical_op__imm_data__data$4$next[63:0]$6484 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6451 $2\logical_op__imm_data__ok$5$next[0:0]$6485 - assign $0\logical_op__oe__oe$8$next[0:0]$6459 $2\logical_op__oe__oe$8$next[0:0]$6486 - assign $0\logical_op__oe__ok$9$next[0:0]$6460 $2\logical_op__oe__ok$9$next[0:0]$6487 - assign $0\logical_op__rc__ok$7$next[0:0]$6462 $2\logical_op__rc__ok$7$next[0:0]$6488 - assign $0\logical_op__rc__rc$6$next[0:0]$6463 $2\logical_op__rc__rc$6$next[0:0]$6489 - attribute \src "libresoc.v:132914.5-132914.29" + assign $0\logical_op__write_cr0$14$next[0:0]$6723 $1\logical_op__write_cr0$14$next[0:0]$6741 + assign $0\logical_op__zero_a$11$next[0:0]$6724 $1\logical_op__zero_a$11$next[0:0]$6742 + assign $0\logical_op__imm_data__data$4$next[63:0]$6709 $2\logical_op__imm_data__data$4$next[63:0]$6743 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6710 $2\logical_op__imm_data__ok$5$next[0:0]$6744 + assign $0\logical_op__oe__oe$8$next[0:0]$6718 $2\logical_op__oe__oe$8$next[0:0]$6745 + assign $0\logical_op__oe__ok$9$next[0:0]$6719 $2\logical_op__oe__ok$9$next[0:0]$6746 + assign $0\logical_op__rc__ok$7$next[0:0]$6721 $2\logical_op__rc__ok$7$next[0:0]$6747 + assign $0\logical_op__rc__rc$6$next[0:0]$6722 $2\logical_op__rc__rc$6$next[0:0]$6748 + attribute \src "libresoc.v:135249.5-135249.29" switch \initial - attribute \src "libresoc.v:132914.9-132914.17" + attribute \src "libresoc.v:135249.9-135249.17" case 1'1 case end @@ -215674,7 +221047,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6471 $1\logical_op__data_len$18$next[3:0]$6466 $1\logical_op__is_signed$17$next[0:0]$6476 $1\logical_op__is_32bit$16$next[0:0]$6475 $1\logical_op__output_carry$15$next[0:0]$6479 $1\logical_op__write_cr0$14$next[0:0]$6482 $1\logical_op__invert_out$13$next[0:0]$6474 $1\logical_op__input_carry$12$next[1:0]$6470 $1\logical_op__zero_a$11$next[0:0]$6483 $1\logical_op__invert_in$10$next[0:0]$6473 $1\logical_op__oe__ok$9$next[0:0]$6478 $1\logical_op__oe__oe$8$next[0:0]$6477 $1\logical_op__rc__ok$7$next[0:0]$6480 $1\logical_op__rc__rc$6$next[0:0]$6481 $1\logical_op__imm_data__ok$5$next[0:0]$6469 $1\logical_op__imm_data__data$4$next[63:0]$6468 $1\logical_op__fn_unit$3$next[11:0]$6467 $1\logical_op__insn_type$2$next[6:0]$6472 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$6730 $1\logical_op__data_len$18$next[3:0]$6725 $1\logical_op__is_signed$17$next[0:0]$6735 $1\logical_op__is_32bit$16$next[0:0]$6734 $1\logical_op__output_carry$15$next[0:0]$6738 $1\logical_op__write_cr0$14$next[0:0]$6741 $1\logical_op__invert_out$13$next[0:0]$6733 $1\logical_op__input_carry$12$next[1:0]$6729 $1\logical_op__zero_a$11$next[0:0]$6742 $1\logical_op__invert_in$10$next[0:0]$6732 $1\logical_op__oe__ok$9$next[0:0]$6737 $1\logical_op__oe__oe$8$next[0:0]$6736 $1\logical_op__rc__ok$7$next[0:0]$6739 $1\logical_op__rc__rc$6$next[0:0]$6740 $1\logical_op__imm_data__ok$5$next[0:0]$6728 $1\logical_op__imm_data__data$4$next[63:0]$6727 $1\logical_op__fn_unit$3$next[11:0]$6726 $1\logical_op__insn_type$2$next[6:0]$6731 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -215695,26 +221068,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6471 $1\logical_op__data_len$18$next[3:0]$6466 $1\logical_op__is_signed$17$next[0:0]$6476 $1\logical_op__is_32bit$16$next[0:0]$6475 $1\logical_op__output_carry$15$next[0:0]$6479 $1\logical_op__write_cr0$14$next[0:0]$6482 $1\logical_op__invert_out$13$next[0:0]$6474 $1\logical_op__input_carry$12$next[1:0]$6470 $1\logical_op__zero_a$11$next[0:0]$6483 $1\logical_op__invert_in$10$next[0:0]$6473 $1\logical_op__oe__ok$9$next[0:0]$6478 $1\logical_op__oe__oe$8$next[0:0]$6477 $1\logical_op__rc__ok$7$next[0:0]$6480 $1\logical_op__rc__rc$6$next[0:0]$6481 $1\logical_op__imm_data__ok$5$next[0:0]$6469 $1\logical_op__imm_data__data$4$next[63:0]$6468 $1\logical_op__fn_unit$3$next[11:0]$6467 $1\logical_op__insn_type$2$next[6:0]$6472 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$6730 $1\logical_op__data_len$18$next[3:0]$6725 $1\logical_op__is_signed$17$next[0:0]$6735 $1\logical_op__is_32bit$16$next[0:0]$6734 $1\logical_op__output_carry$15$next[0:0]$6738 $1\logical_op__write_cr0$14$next[0:0]$6741 $1\logical_op__invert_out$13$next[0:0]$6733 $1\logical_op__input_carry$12$next[1:0]$6729 $1\logical_op__zero_a$11$next[0:0]$6742 $1\logical_op__invert_in$10$next[0:0]$6732 $1\logical_op__oe__ok$9$next[0:0]$6737 $1\logical_op__oe__oe$8$next[0:0]$6736 $1\logical_op__rc__ok$7$next[0:0]$6739 $1\logical_op__rc__rc$6$next[0:0]$6740 $1\logical_op__imm_data__ok$5$next[0:0]$6728 $1\logical_op__imm_data__data$4$next[63:0]$6727 $1\logical_op__fn_unit$3$next[11:0]$6726 $1\logical_op__insn_type$2$next[6:0]$6731 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$6466 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$6467 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$6468 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$6469 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$6470 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$6471 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$6472 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$6473 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$6474 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$6475 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$6476 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$6477 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$6478 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$6479 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$6480 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$6481 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$6482 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$6483 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$6725 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$6726 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$6727 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$6728 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$6729 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$6730 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$6731 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$6732 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$6733 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$6734 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$6735 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$6736 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$6737 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$6738 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$6739 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$6740 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$6741 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$6742 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -215726,52 +221099,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$6484 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6485 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$6489 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$6488 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$6486 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$6487 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$6743 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6744 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$6748 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$6747 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$6745 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$6746 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$6484 $1\logical_op__imm_data__data$4$next[63:0]$6468 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6485 $1\logical_op__imm_data__ok$5$next[0:0]$6469 - assign $2\logical_op__oe__oe$8$next[0:0]$6486 $1\logical_op__oe__oe$8$next[0:0]$6477 - assign $2\logical_op__oe__ok$9$next[0:0]$6487 $1\logical_op__oe__ok$9$next[0:0]$6478 - assign $2\logical_op__rc__ok$7$next[0:0]$6488 $1\logical_op__rc__ok$7$next[0:0]$6480 - assign $2\logical_op__rc__rc$6$next[0:0]$6489 $1\logical_op__rc__rc$6$next[0:0]$6481 + assign $2\logical_op__imm_data__data$4$next[63:0]$6743 $1\logical_op__imm_data__data$4$next[63:0]$6727 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6744 $1\logical_op__imm_data__ok$5$next[0:0]$6728 + assign $2\logical_op__oe__oe$8$next[0:0]$6745 $1\logical_op__oe__oe$8$next[0:0]$6736 + assign $2\logical_op__oe__ok$9$next[0:0]$6746 $1\logical_op__oe__ok$9$next[0:0]$6737 + assign $2\logical_op__rc__ok$7$next[0:0]$6747 $1\logical_op__rc__ok$7$next[0:0]$6739 + assign $2\logical_op__rc__rc$6$next[0:0]$6748 $1\logical_op__rc__rc$6$next[0:0]$6740 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6448 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6449 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6450 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6451 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6452 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6453 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6454 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6455 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6456 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6457 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6458 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6459 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6460 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6461 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6462 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6463 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6464 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6465 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6707 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6708 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6709 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6710 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6711 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6712 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6713 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6714 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6715 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6716 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6717 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6718 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6719 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6720 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6721 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6722 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6723 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6724 end - attribute \src "libresoc.v:132955.3-132973.6" - process $proc$libresoc.v:132955$6490 + attribute \src "libresoc.v:135290.3-135308.6" + process $proc$libresoc.v:135290$6749 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$6491 $1\o$20$next[63:0]$6493 + assign $0\o$20$next[63:0]$6750 $1\o$20$next[63:0]$6752 assign { } { } - assign $0\o_ok$21$next[0:0]$6492 $2\o_ok$21$next[0:0]$6495 - attribute \src "libresoc.v:132956.5-132956.29" + assign $0\o_ok$21$next[0:0]$6751 $2\o_ok$21$next[0:0]$6754 + attribute \src "libresoc.v:135291.5-135291.29" switch \initial - attribute \src "libresoc.v:132956.9-132956.17" + attribute \src "libresoc.v:135291.9-135291.17" case 1'1 case end @@ -215781,41 +221154,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6494 $1\o$20$next[63:0]$6493 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$6753 $1\o$20$next[63:0]$6752 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$6494 $1\o$20$next[63:0]$6493 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$6753 $1\o$20$next[63:0]$6752 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$6493 \o$20 - assign $1\o_ok$21$next[0:0]$6494 \o_ok$21 + assign $1\o$20$next[63:0]$6752 \o$20 + assign $1\o_ok$21$next[0:0]$6753 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$6495 1'0 + assign $2\o_ok$21$next[0:0]$6754 1'0 case - assign $2\o_ok$21$next[0:0]$6495 $1\o_ok$21$next[0:0]$6494 + assign $2\o_ok$21$next[0:0]$6754 $1\o_ok$21$next[0:0]$6753 end sync always - update \o$20$next $0\o$20$next[63:0]$6491 - update \o_ok$21$next $0\o_ok$21$next[0:0]$6492 + update \o$20$next $0\o$20$next[63:0]$6750 + update \o_ok$21$next $0\o_ok$21$next[0:0]$6751 end - attribute \src "libresoc.v:132974.3-132992.6" - process $proc$libresoc.v:132974$6496 + attribute \src "libresoc.v:135309.3-135327.6" + process $proc$libresoc.v:135309$6755 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$6497 $1\cr_a$22$next[3:0]$6499 + assign $0\cr_a$22$next[3:0]$6756 $1\cr_a$22$next[3:0]$6758 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$6498 $2\cr_a_ok$23$next[0:0]$6501 - attribute \src "libresoc.v:132975.5-132975.29" + assign $0\cr_a_ok$23$next[0:0]$6757 $2\cr_a_ok$23$next[0:0]$6760 + attribute \src "libresoc.v:135310.5-135310.29" switch \initial - attribute \src "libresoc.v:132975.9-132975.17" + attribute \src "libresoc.v:135310.9-135310.17" case 1'1 case end @@ -215825,30 +221198,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6500 $1\cr_a$22$next[3:0]$6499 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$6759 $1\cr_a$22$next[3:0]$6758 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6500 $1\cr_a$22$next[3:0]$6499 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$6759 $1\cr_a$22$next[3:0]$6758 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$6499 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$6500 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$6758 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$6759 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$6501 1'0 + assign $2\cr_a_ok$23$next[0:0]$6760 1'0 case - assign $2\cr_a_ok$23$next[0:0]$6501 $1\cr_a_ok$23$next[0:0]$6500 + assign $2\cr_a_ok$23$next[0:0]$6760 $1\cr_a_ok$23$next[0:0]$6759 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$6497 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6498 + update \cr_a$22$next $0\cr_a$22$next[3:0]$6756 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6757 end - connect \$49 $and$libresoc.v:132777$6392_Y + connect \$49 $and$libresoc.v:135112$6651_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -215864,14303 +221237,14447 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-10282.10" +attribute \src "ls180.v:4.1-10571.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:9977.1-9987.4" - wire width 7 $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 - attribute \src "ls180.v:9977.1-9987.4" - wire width 7 $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 - attribute \src "ls180.v:9977.1-9987.4" - wire width 7 $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 - attribute \src "ls180.v:9977.1-9987.4" - wire width 7 $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 - attribute \src "ls180.v:9977.1-9987.4" - wire width 32 $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 - attribute \src "ls180.v:9997.1-10001.4" - wire width 3 $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 - attribute \src "ls180.v:9997.1-10001.4" - wire width 25 $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 - attribute \src "ls180.v:9997.1-10001.4" - wire width 25 $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 - attribute \src "ls180.v:10011.1-10015.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 - attribute \src "ls180.v:10011.1-10015.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 - attribute \src "ls180.v:10011.1-10015.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 - attribute \src "ls180.v:10025.1-10029.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 - attribute \src "ls180.v:10025.1-10029.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 - attribute \src "ls180.v:10025.1-10029.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 - attribute \src "ls180.v:10039.1-10043.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 - attribute \src "ls180.v:10039.1-10043.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 - attribute \src "ls180.v:10039.1-10043.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 - attribute \src "ls180.v:10054.1-10058.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 - attribute \src "ls180.v:10054.1-10058.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 - attribute \src "ls180.v:10054.1-10058.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 - attribute \src "ls180.v:10071.1-10075.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 - attribute \src "ls180.v:10071.1-10075.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 - attribute \src "ls180.v:10071.1-10075.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 - attribute \src "ls180.v:10087.1-10091.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 - attribute \src "ls180.v:10087.1-10091.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 - attribute \src "ls180.v:10087.1-10091.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 - attribute \src "ls180.v:10101.1-10105.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 - attribute \src "ls180.v:10101.1-10105.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 - attribute \src "ls180.v:10101.1-10105.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:10056.1-10066.4" + wire width 7 $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 + attribute \src "ls180.v:10056.1-10066.4" + wire width 7 $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 + attribute \src "ls180.v:10056.1-10066.4" + wire width 7 $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 + attribute \src "ls180.v:10056.1-10066.4" + wire width 7 $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 + attribute \src "ls180.v:10056.1-10066.4" + wire width 32 $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 + attribute \src "ls180.v:10076.1-10080.4" + wire width 3 $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 + attribute \src "ls180.v:10076.1-10080.4" + wire width 25 $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 + attribute \src "ls180.v:10076.1-10080.4" + wire width 25 $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 + attribute \src "ls180.v:10090.1-10094.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 + attribute \src "ls180.v:10090.1-10094.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 + attribute \src "ls180.v:10090.1-10094.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 + attribute \src "ls180.v:10104.1-10108.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 + attribute \src "ls180.v:10104.1-10108.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 + attribute \src "ls180.v:10104.1-10108.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 + attribute \src "ls180.v:10118.1-10122.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 + attribute \src "ls180.v:10118.1-10122.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 + attribute \src "ls180.v:10118.1-10122.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 + attribute \src "ls180.v:10133.1-10137.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 + attribute \src "ls180.v:10133.1-10137.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 + attribute \src "ls180.v:10133.1-10137.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 + attribute \src "ls180.v:10150.1-10154.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 + attribute \src "ls180.v:10150.1-10154.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 + attribute \src "ls180.v:10150.1-10154.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 + attribute \src "ls180.v:10166.1-10170.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 + attribute \src "ls180.v:10166.1-10170.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 + attribute \src "ls180.v:10166.1-10170.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 + attribute \src "ls180.v:10180.1-10184.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 + attribute \src "ls180.v:10180.1-10184.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 + attribute \src "ls180.v:10180.1-10184.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 + attribute \src "ls180.v:3223.1-3316.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6448.1-6464.4" + attribute \src "ls180.v:6517.1-6533.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6669.1-6685.4" + attribute \src "ls180.v:6738.1-6754.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6686.1-6702.4" + attribute \src "ls180.v:6755.1-6771.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6754.1-6761.4" + attribute \src "ls180.v:6823.1-6830.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6762.1-6769.4" + attribute \src "ls180.v:6831.1-6838.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6770.1-6777.4" + attribute \src "ls180.v:6839.1-6846.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6778.1-6785.4" + attribute \src "ls180.v:6847.1-6854.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6786.1-6793.4" + attribute \src "ls180.v:6855.1-6862.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6794.1-6801.4" + attribute \src "ls180.v:6863.1-6870.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6802.1-6809.4" + attribute \src "ls180.v:6871.1-6878.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6810.1-6817.4" + attribute \src "ls180.v:6879.1-6886.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6465.1-6481.4" + attribute \src "ls180.v:6534.1-6550.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6818.1-6825.4" + attribute \src "ls180.v:6887.1-6894.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6826.1-6833.4" + attribute \src "ls180.v:6895.1-6902.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6834.1-6841.4" + attribute \src "ls180.v:6903.1-6910.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6842.1-6849.4" + attribute \src "ls180.v:6911.1-6918.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6850.1-6869.4" + attribute \src "ls180.v:6919.1-6938.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6870.1-6889.4" + attribute \src "ls180.v:6939.1-6958.4" wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6890.1-6909.4" + attribute \src "ls180.v:6959.1-6978.4" wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6910.1-6929.4" + attribute \src "ls180.v:6979.1-6998.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6930.1-6949.4" + attribute \src "ls180.v:6999.1-7018.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:6950.1-6969.4" + attribute \src "ls180.v:7019.1-7038.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6482.1-6498.4" + attribute \src "ls180.v:6551.1-6567.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:6970.1-6989.4" + attribute \src "ls180.v:7039.1-7058.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:6990.1-7009.4" + attribute \src "ls180.v:7059.1-7078.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6499.1-6515.4" + attribute \src "ls180.v:6568.1-6584.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6516.1-6532.4" + attribute \src "ls180.v:6585.1-6601.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6533.1-6549.4" + attribute \src "ls180.v:6602.1-6618.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6601.1-6617.4" + attribute \src "ls180.v:6670.1-6686.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6618.1-6634.4" + attribute \src "ls180.v:6687.1-6703.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6635.1-6651.4" + attribute \src "ls180.v:6704.1-6720.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6652.1-6668.4" + attribute \src "ls180.v:6721.1-6737.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6550.1-6566.4" + attribute \src "ls180.v:6619.1-6635.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6567.1-6583.4" + attribute \src "ls180.v:6636.1-6652.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6584.1-6600.4" + attribute \src "ls180.v:6653.1-6669.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6703.1-6719.4" + attribute \src "ls180.v:6772.1-6788.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6720.1-6736.4" + attribute \src "ls180.v:6789.1-6805.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6737.1-6753.4" + attribute \src "ls180.v:6806.1-6822.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5705.1-5716.4" + attribute \src "ls180.v:5757.1-5768.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1841.5-1841.44" + attribute \src "ls180.v:1879.5-1879.44" wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1730.5-1730.27" + attribute \src "ls180.v:1768.5-1768.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1731.5-1731.27" + attribute \src "ls180.v:1769.5-1769.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1732.5-1732.27" + attribute \src "ls180.v:1770.5-1770.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1733.5-1733.27" + attribute \src "ls180.v:1771.5-1771.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5594.1-5630.4" + attribute \src "ls180.v:5646.1-5682.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3081.1-3111.4" + attribute \src "ls180.v:3129.1-3159.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5705.1-5716.4" + attribute \src "ls180.v:5757.1-5768.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5705.1-5716.4" + attribute \src "ls180.v:5757.1-5768.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5655.1-5662.4" + attribute \src "ls180.v:5707.1-5714.4" wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:4182.1-4230.4" + attribute \src "ls180.v:4230.1-4278.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:5545.1-5593.4" + attribute \src "ls180.v:4289.1-4337.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7129.1-7157.4" + attribute \src "ls180.v:7198.1-7226.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7158.1-7186.4" + attribute \src "ls180.v:7227.1-7255.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7010.1-7026.4" + attribute \src "ls180.v:7079.1-7095.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7027.1-7043.4" + attribute \src "ls180.v:7096.1-7112.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7044.1-7060.4" + attribute \src "ls180.v:7113.1-7129.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7061.1-7077.4" + attribute \src "ls180.v:7130.1-7146.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7078.1-7094.4" + attribute \src "ls180.v:7147.1-7163.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7095.1-7111.4" + attribute \src "ls180.v:7164.1-7180.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7112.1-7128.4" + attribute \src "ls180.v:7181.1-7197.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 16 $0\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_control_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 16 $0\libresocsim_control_storage[15:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 3 $0\libresocsim_count[2:0] - attribute \src "ls180.v:5545.1-5593.4" - wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_cs_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_done0[0:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_irq[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\libresocsim_miso[7:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\libresocsim_miso_data[7:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:5545.1-5593.4" - wire $0\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 3 $0\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\libresocsim_re[0:0] - attribute \src "ls180.v:6262.1-6267.4" - wire $0\libresocsim_start1[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 16 $0\libresocsim_storage[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:154.11-154.24" + wire width 3 $0\eint_1[2:0] + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 42 $0\main_dummy[41:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" + wire width 36 $0\main_dummy[35:0] + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7244.1-7262.4" + attribute \src "ls180.v:7313.1-7331.4" wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7283.1-7285.4" + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7352.1-7354.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1480.11-1480.41" + attribute \src "ls180.v:1556.11-1556.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1479.11-1479.41" + attribute \src "ls180.v:1555.11-1555.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1571.11-1571.41" + attribute \src "ls180.v:1647.11-1647.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1570.11-1570.41" + attribute \src "ls180.v:1646.11-1646.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1563.12-1563.45" + attribute \src "ls180.v:1639.12-1639.45" wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:139.11-139.69" + attribute \src "ls180.v:169.11-169.69" wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:138.11-138.69" + attribute \src "ls180.v:168.11-168.69" wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2727.1-2737.4" + attribute \src "ls180.v:2775.1-2785.4" wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:154.11-154.69" + attribute \src "ls180.v:184.11-184.69" wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:153.11-153.69" + attribute \src "ls180.v:183.11-183.69" wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2787.1-2797.4" + attribute \src "ls180.v:2835.1-2845.4" wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:169.11-169.69" + attribute \src "ls180.v:199.11-199.69" wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:168.11-168.69" + attribute \src "ls180.v:198.11-198.69" wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2847.1-2857.4" + attribute \src "ls180.v:2895.1-2905.4" wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - attribute \src "ls180.v:2799.1-2845.4" + attribute \src "ls180.v:127.12-127.74" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + attribute \src "ls180.v:135.5-135.69" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + attribute \src "ls180.v:131.5-131.72" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + attribute \src "ls180.v:143.12-143.78" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + attribute \src "ls180.v:141.5-141.74" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] + attribute \src "ls180.v:159.5-159.74" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] + attribute \src "ls180.v:2847.1-2893.4" wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:70.5-70.46" + attribute \src "ls180.v:75.5-75.46" wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2739.1-2785.4" + attribute \src "ls180.v:2787.1-2833.4" wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:81.5-81.46" + attribute \src "ls180.v:86.5-86.46" wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2720.1-2725.4" + attribute \src "ls180.v:2768.1-2773.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2859.1-2905.4" + attribute \src "ls180.v:2907.1-2953.4" wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:112.5-112.49" + attribute \src "ls180.v:117.5-117.49" wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:185.5-185.40" + attribute \src "ls180.v:215.5-215.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2908.1-2914.4" + attribute \src "ls180.v:2956.1-2962.4" wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:2920.1-2925.4" + attribute \src "ls180.v:2968.1-2973.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:3980.1-3990.4" + attribute \src "ls180.v:4028.1-4038.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 32 $0\main_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 32 $0\main_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 4 $0\main_rx_bitcount[3:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_rx_busy[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_rx_r[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_rx_reg[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1504.5-1504.41" + attribute \src "ls180.v:1580.5-1580.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5312.1-5319.4" + attribute \src "ls180.v:5423.1-5430.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5345.1-5384.4" + attribute \src "ls180.v:5456.1-5495.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1313.5-1313.34" + attribute \src "ls180.v:1389.5-1389.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5000.1-5007.4" + attribute \src "ls180.v:5111.1-5118.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5056.1-5063.4" + attribute \src "ls180.v:5167.1-5174.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5010.1-5017.4" + attribute \src "ls180.v:5121.1-5128.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5066.1-5073.4" + attribute \src "ls180.v:5177.1-5184.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5020.1-5027.4" + attribute \src "ls180.v:5131.1-5138.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5076.1-5083.4" + attribute \src "ls180.v:5187.1-5194.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5030.1-5037.4" + attribute \src "ls180.v:5141.1-5148.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5086.1-5093.4" + attribute \src "ls180.v:5197.1-5204.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5045.1-5052.4" + attribute \src "ls180.v:5156.1-5163.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1419.5-1419.50" + attribute \src "ls180.v:1495.5-1495.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5039.1-5044.4" + attribute \src "ls180.v:5150.1-5155.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:4992.1-4997.4" + attribute \src "ls180.v:5103.1-5108.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4874.1-4881.4" + attribute \src "ls180.v:4985.1-4992.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4884.1-4891.4" + attribute \src "ls180.v:4995.1-5002.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:4894.1-4901.4" + attribute \src "ls180.v:5005.1-5012.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:4904.1-4911.4" + attribute \src "ls180.v:5015.1-5022.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1376.5-1376.51" + attribute \src "ls180.v:1452.5-1452.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:4912.1-4991.4" + attribute \src "ls180.v:5023.1-5102.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4852.1-4859.4" + attribute \src "ls180.v:4963.1-4970.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5490.1-5506.4" + attribute \src "ls180.v:5601.1-5617.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5442.1-5478.4" + attribute \src "ls180.v:5553.1-5589.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1584.5-1584.45" + attribute \src "ls180.v:1660.5-1660.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5404.1-5441.4" + attribute \src "ls180.v:5515.1-5552.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1640.5-1640.41" + attribute \src "ls180.v:1716.5-1716.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5520.1-5527.4" + attribute \src "ls180.v:5631.1-5638.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4258.1-4286.4" + attribute \src "ls180.v:4369.1-4397.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1105.5-1105.53" + attribute \src "ls180.v:1181.5-1181.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1106.5-1106.52" + attribute \src "ls180.v:1182.5-1182.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1086.5-1086.46" + attribute \src "ls180.v:1162.5-1162.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1059.5-1059.49" + attribute \src "ls180.v:1135.5-1135.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1060.5-1060.48" + attribute \src "ls180.v:1136.5-1136.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1061.5-1061.55" + attribute \src "ls180.v:1137.5-1137.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1063.5-1063.57" + attribute \src "ls180.v:1139.5-1139.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1064.5-1064.58" + attribute \src "ls180.v:1140.5-1140.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1066.11-1066.64" + attribute \src "ls180.v:1142.11-1142.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1067.5-1067.59" + attribute \src "ls180.v:1143.5-1143.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1072.11-1072.57" + attribute \src "ls180.v:1148.11-1148.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1073.5-1073.52" + attribute \src "ls180.v:1149.5-1149.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4432.1-4525.4" + attribute \src "ls180.v:4543.1-4636.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1049.11-1049.57" + attribute \src "ls180.v:1125.11-1125.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1050.5-1050.52" + attribute \src "ls180.v:1126.5-1126.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4322.1-4398.4" + attribute \src "ls180.v:4433.1-4509.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1261.5-1261.55" + attribute \src "ls180.v:1337.5-1337.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1262.5-1262.54" + attribute \src "ls180.v:1338.5-1338.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1242.5-1242.48" + attribute \src "ls180.v:1318.5-1318.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1213.5-1213.50" + attribute \src "ls180.v:1289.5-1289.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1214.5-1214.49" + attribute \src "ls180.v:1290.5-1290.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1215.5-1215.56" + attribute \src "ls180.v:1291.5-1291.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1217.5-1217.58" + attribute \src "ls180.v:1293.5-1293.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1218.5-1218.59" + attribute \src "ls180.v:1294.5-1294.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1220.11-1220.65" + attribute \src "ls180.v:1296.11-1296.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1221.5-1221.60" + attribute \src "ls180.v:1297.5-1297.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1224.5-1224.51" + attribute \src "ls180.v:1300.5-1300.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1225.5-1225.52" + attribute \src "ls180.v:1301.5-1301.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1226.11-1226.58" + attribute \src "ls180.v:1302.11-1302.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1227.5-1227.53" + attribute \src "ls180.v:1303.5-1303.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1234.5-1234.41" + attribute \src "ls180.v:1310.5-1310.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4693.1-4794.4" + attribute \src "ls180.v:4804.1-4905.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1183.5-1183.54" + attribute \src "ls180.v:1259.5-1259.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1184.5-1184.53" + attribute \src "ls180.v:1260.5-1260.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1164.5-1164.47" + attribute \src "ls180.v:1240.5-1240.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1151.5-1151.50" + attribute \src "ls180.v:1227.5-1227.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1152.5-1152.49" + attribute \src "ls180.v:1228.5-1228.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1153.5-1153.56" + attribute \src "ls180.v:1229.5-1229.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1154.5-1154.58" + attribute \src "ls180.v:1230.5-1230.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1155.5-1155.58" + attribute \src "ls180.v:1231.5-1231.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1156.5-1156.59" + attribute \src "ls180.v:1232.5-1232.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1157.11-1157.65" + attribute \src "ls180.v:1233.11-1233.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1158.11-1158.65" + attribute \src "ls180.v:1234.11-1234.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1159.5-1159.60" + attribute \src "ls180.v:1235.5-1235.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1149.5-1149.50" + attribute \src "ls180.v:1225.5-1225.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1138.5-1138.51" + attribute \src "ls180.v:1214.5-1214.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1139.5-1139.52" + attribute \src "ls180.v:1215.5-1215.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5094.1-5284.4" + attribute \src "ls180.v:5205.1-5395.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4587.1-4659.4" + attribute \src "ls180.v:4698.1-4770.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4559.1-4586.4" + attribute \src "ls180.v:4670.1-4697.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1031.5-1031.40" + attribute \src "ls180.v:1107.5-1107.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4288.1-4321.4" + attribute \src "ls180.v:4399.1-4432.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3137.1-3144.4" + attribute \src "ls180.v:3185.1-3192.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:417.5-417.64" + attribute \src "ls180.v:447.5-447.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:400.5-400.67" + attribute \src "ls180.v:430.5-430.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:401.5-401.66" + attribute \src "ls180.v:431.5-431.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3159.1-3166.4" + attribute \src "ls180.v:3207.1-3214.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3126.1-3133.4" + attribute \src "ls180.v:3174.1-3181.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3824.1-3832.4" + attribute \src "ls180.v:3872.1-3880.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3175.1-3268.4" + attribute \src "ls180.v:3223.1-3316.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:459.32-459.76" + attribute \src "ls180.v:489.32-489.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:457.32-457.75" + attribute \src "ls180.v:487.32-487.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3294.1-3301.4" + attribute \src "ls180.v:3342.1-3349.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:499.5-499.64" + attribute \src "ls180.v:529.5-529.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:482.5-482.67" + attribute \src "ls180.v:512.5-512.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:483.5-483.66" + attribute \src "ls180.v:513.5-513.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3316.1-3323.4" + attribute \src "ls180.v:3364.1-3371.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3283.1-3290.4" + attribute \src "ls180.v:3331.1-3338.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3833.1-3841.4" + attribute \src "ls180.v:3881.1-3889.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3332.1-3425.4" + attribute \src "ls180.v:3380.1-3473.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:541.32-541.76" + attribute \src "ls180.v:571.32-571.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:539.32-539.75" + attribute \src "ls180.v:569.32-569.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3451.1-3458.4" + attribute \src "ls180.v:3499.1-3506.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:581.5-581.64" + attribute \src "ls180.v:611.5-611.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:564.5-564.67" + attribute \src "ls180.v:594.5-594.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:565.5-565.66" + attribute \src "ls180.v:595.5-595.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3473.1-3480.4" + attribute \src "ls180.v:3521.1-3528.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3440.1-3447.4" + attribute \src "ls180.v:3488.1-3495.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3842.1-3850.4" + attribute \src "ls180.v:3890.1-3898.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3489.1-3582.4" + attribute \src "ls180.v:3537.1-3630.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:623.32-623.76" + attribute \src "ls180.v:653.32-653.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:621.32-621.75" + attribute \src "ls180.v:651.32-651.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3608.1-3615.4" + attribute \src "ls180.v:3656.1-3663.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:663.5-663.64" + attribute \src "ls180.v:693.5-693.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:646.5-646.67" + attribute \src "ls180.v:676.5-676.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:647.5-647.66" + attribute \src "ls180.v:677.5-677.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3630.1-3637.4" + attribute \src "ls180.v:3678.1-3685.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3597.1-3604.4" + attribute \src "ls180.v:3645.1-3652.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3851.1-3859.4" + attribute \src "ls180.v:3899.1-3907.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3646.1-3739.4" + attribute \src "ls180.v:3694.1-3787.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:705.32-705.76" + attribute \src "ls180.v:735.32-735.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:703.32-703.75" + attribute \src "ls180.v:733.32-733.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3773.1-3778.4" + attribute \src "ls180.v:3821.1-3826.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3779.1-3784.4" + attribute \src "ls180.v:3827.1-3832.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3785.1-3790.4" + attribute \src "ls180.v:3833.1-3838.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:713.5-713.43" + attribute \src "ls180.v:743.5-743.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3759.1-3765.4" + attribute \src "ls180.v:3807.1-3813.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:711.5-711.48" + attribute \src "ls180.v:741.5-741.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:710.5-710.43" + attribute \src "ls180.v:740.5-740.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:708.5-708.44" + attribute \src "ls180.v:738.5-738.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:709.5-709.45" + attribute \src "ls180.v:739.5-739.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3806.1-3811.4" + attribute \src "ls180.v:3854.1-3859.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3812.1-3817.4" + attribute \src "ls180.v:3860.1-3865.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3818.1-3823.4" + attribute \src "ls180.v:3866.1-3871.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3792.1-3798.4" + attribute \src "ls180.v:3840.1-3846.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3081.1-3111.4" + attribute \src "ls180.v:3129.1-3159.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:361.5-361.42" + attribute \src "ls180.v:391.5-391.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:362.5-362.43" + attribute \src "ls180.v:392.5-392.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3081.1-3111.4" + attribute \src "ls180.v:3129.1-3159.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:297.5-297.38" + attribute \src "ls180.v:327.5-327.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:346.5-346.35" + attribute \src "ls180.v:376.5-376.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:3960.1-3973.4" + attribute \src "ls180.v:4008.1-4021.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:3960.1-3973.4" + attribute \src "ls180.v:4008.1-4021.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:247.5-247.36" + attribute \src "ls180.v:277.5-277.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3022.1-3038.4" + attribute \src "ls180.v:3070.1-3086.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3022.1-3038.4" + attribute \src "ls180.v:3070.1-3086.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3022.1-3038.4" + attribute \src "ls180.v:3070.1-3086.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3022.1-3038.4" + attribute \src "ls180.v:3070.1-3086.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:744.12-744.36" + attribute \src "ls180.v:774.12-774.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:745.11-745.35" + attribute \src "ls180.v:775.11-775.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3081.1-3111.4" + attribute \src "ls180.v:3129.1-3159.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:2964.1-3018.4" + attribute \src "ls180.v:3012.1-3066.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:747.5-747.31" + attribute \src "ls180.v:777.5-777.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:748.5-748.31" + attribute \src "ls180.v:778.5-778.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3864.1-3936.4" + attribute \src "ls180.v:3912.1-3984.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:752.32-752.63" + attribute \src "ls180.v:782.32-782.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:750.32-750.63" + attribute \src "ls180.v:780.32-780.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_sink_ready[0:0] - attribute \src "ls180.v:823.5-823.29" - wire $0\main_source_first[0:0] - attribute \src "ls180.v:824.5-824.28" - wire $0\main_source_last[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_source_payload_data[7:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_source_valid[0:0] - attribute \src "ls180.v:968.12-968.48" - wire width 16 $0\main_spi_master_clk_divider0[15:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 16 $0\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_control_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 16 $0\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 3 $0\main_spi_master_count[2:0] - attribute \src "ls180.v:4182.1-4230.4" - wire width 3 $0\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_done0[0:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_irq[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_spi_master_miso[7:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:4182.1-4230.4" - wire $0\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 3 $0\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:6216.1-6221.4" - wire $0\main_spi_master_start1[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 32 $0\main_storage[31:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 4 $0\main_tx_bitcount[3:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_tx_busy[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire width 8 $0\main_tx_reg[7:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_uart_clk_rxen[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\main_uart_clk_txen[0:0] - attribute \src "ls180.v:4100.1-4104.4" + attribute \src "ls180.v:7428.1-10052.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4230.1-4278.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4230.1-4278.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:998.12-998.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6282.1-6287.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4289.1-4337.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4289.1-4337.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6328.1-6333.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:4148.1-4152.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4089.1-4093.4" + attribute \src "ls180.v:4137.1-4141.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:950.5-950.27" + attribute \src "ls180.v:7428.1-10052.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:853.5-853.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:854.5-854.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:980.5-980.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4094.1-4099.4" + attribute \src "ls180.v:4142.1-4147.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:932.5-932.37" + attribute \src "ls180.v:962.5-962.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4152.1-4159.4" + attribute \src "ls180.v:4200.1-4207.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4083.1-4088.4" + attribute \src "ls180.v:4131.1-4136.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:895.5-895.37" + attribute \src "ls180.v:925.5-925.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:878.5-878.40" + attribute \src "ls180.v:908.5-908.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:879.5-879.39" + attribute \src "ls180.v:909.5-909.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4122.1-4129.4" + attribute \src "ls180.v:4170.1-4177.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:3992.1-4038.4" + attribute \src "ls180.v:4040.1-4086.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:791.5-791.29" + attribute \src "ls180.v:821.5-821.29" wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:9977.1-9987.4" + attribute \src "ls180.v:10056.1-10066.4" wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:9997.1-10001.4" + attribute \src "ls180.v:10076.1-10080.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10011.1-10015.4" + attribute \src "ls180.v:10090.1-10094.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10025.1-10029.4" + attribute \src "ls180.v:10104.1-10108.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10039.1-10043.4" + attribute \src "ls180.v:10118.1-10122.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10054.1-10058.4" + attribute \src "ls180.v:10133.1-10137.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10060.1-10063.4" + attribute \src "ls180.v:10139.1-10142.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10071.1-10075.4" + attribute \src "ls180.v:10150.1-10154.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10077.1-10080.4" + attribute \src "ls180.v:10156.1-10159.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10087.1-10091.4" + attribute \src "ls180.v:10166.1-10170.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10101.1-10105.4" + attribute \src "ls180.v:10180.1-10184.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\pwm0[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\pwm1[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7428.1-10052.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7287.1-7357.4" + attribute \src "ls180.v:7356.1-7426.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\spi_master_clk[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\spi_master_cs_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" - wire $0\spi_master_mosi[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7428.1-10052.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7428.1-10052.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7359.1-9973.4" + attribute \src "ls180.v:7428.1-10052.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:1709.11-1709.49" + attribute \src "ls180.v:7428.1-10052.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1747.11-1747.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1708.11-1708.44" + attribute \src "ls180.v:1746.11-1746.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1711.11-1711.49" + attribute \src "ls180.v:1749.11-1749.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1710.11-1710.44" + attribute \src "ls180.v:1748.11-1748.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1713.11-1713.49" + attribute \src "ls180.v:1751.11-1751.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1712.11-1712.44" + attribute \src "ls180.v:1750.11-1750.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1715.11-1715.49" + attribute \src "ls180.v:1753.11-1753.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1714.11-1714.44" + attribute \src "ls180.v:1752.11-1752.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2547.5-2547.41" + attribute \src "ls180.v:2598.5-2598.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2560.5-2560.42" + attribute \src "ls180.v:2611.5-2611.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2561.5-2561.42" + attribute \src "ls180.v:2612.5-2612.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2565.12-2565.50" + attribute \src "ls180.v:2616.12-2616.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2566.5-2566.42" + attribute \src "ls180.v:2617.5-2617.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2567.5-2567.42" + attribute \src "ls180.v:2618.5-2618.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2568.12-2568.50" + attribute \src "ls180.v:2619.12-2619.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2569.5-2569.42" + attribute \src "ls180.v:2620.5-2620.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2570.5-2570.42" + attribute \src "ls180.v:2621.5-2621.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2571.12-2571.50" + attribute \src "ls180.v:2622.12-2622.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2572.5-2572.42" + attribute \src "ls180.v:2623.5-2623.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2548.12-2548.49" + attribute \src "ls180.v:2599.12-2599.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2573.5-2573.42" + attribute \src "ls180.v:2624.5-2624.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2574.12-2574.50" + attribute \src "ls180.v:2625.12-2625.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2575.5-2575.42" + attribute \src "ls180.v:2626.5-2626.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2576.5-2576.42" + attribute \src "ls180.v:2627.5-2627.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2577.12-2577.50" + attribute \src "ls180.v:2628.12-2628.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2578.12-2578.50" + attribute \src "ls180.v:2629.12-2629.50" wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2579.11-2579.48" + attribute \src "ls180.v:2630.11-2630.48" wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2580.5-2580.42" + attribute \src "ls180.v:2631.5-2631.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2581.5-2581.42" + attribute \src "ls180.v:2632.5-2632.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2582.5-2582.42" + attribute \src "ls180.v:2633.5-2633.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2549.11-2549.47" + attribute \src "ls180.v:2600.11-2600.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2583.11-2583.48" + attribute \src "ls180.v:2634.11-2634.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2584.11-2584.48" + attribute \src "ls180.v:2635.11-2635.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2550.5-2550.41" + attribute \src "ls180.v:2601.5-2601.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2551.5-2551.41" + attribute \src "ls180.v:2602.5-2602.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2552.5-2552.41" + attribute \src "ls180.v:2603.5-2603.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2556.5-2556.41" + attribute \src "ls180.v:2607.5-2607.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2557.12-2557.49" + attribute \src "ls180.v:2608.12-2608.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2558.11-2558.47" + attribute \src "ls180.v:2609.11-2609.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2559.5-2559.41" + attribute \src "ls180.v:2610.5-2610.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2553.5-2553.39" + attribute \src "ls180.v:2604.5-2604.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2554.5-2554.39" + attribute \src "ls180.v:2605.5-2605.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2555.5-2555.39" + attribute \src "ls180.v:2606.5-2606.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2562.5-2562.39" + attribute \src "ls180.v:2613.5-2613.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2563.5-2563.39" + attribute \src "ls180.v:2614.5-2614.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2564.5-2564.39" + attribute \src "ls180.v:2615.5-2615.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1695.5-1695.41" + attribute \src "ls180.v:1733.5-1733.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1694.5-1694.36" + attribute \src "ls180.v:1732.5-1732.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1699.5-1699.41" + attribute \src "ls180.v:1737.5-1737.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1698.5-1698.36" + attribute \src "ls180.v:1736.5-1736.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1703.5-1703.41" + attribute \src "ls180.v:1741.5-1741.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1702.5-1702.36" + attribute \src "ls180.v:1740.5-1740.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1740.5-1740.40" + attribute \src "ls180.v:1778.5-1778.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1739.5-1739.35" + attribute \src "ls180.v:1777.5-1777.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1860.12-1860.39" + attribute \src "ls180.v:1898.12-1898.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1857.5-1857.25" + attribute \src "ls180.v:1895.5-1895.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:1854.11-1854.31" + attribute \src "ls180.v:1892.11-1892.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1864.11-1864.51" + attribute \src "ls180.v:1902.11-1902.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2386.11-2386.52" + attribute \src "ls180.v:2404.11-2404.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2427.11-2427.52" + attribute \src "ls180.v:2437.11-2437.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2492.11-2492.52" + attribute \src "ls180.v:2478.11-2478.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2517.11-2517.52" + attribute \src "ls180.v:2543.11-2543.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1905.11-1905.51" + attribute \src "ls180.v:2568.11-2568.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1943.11-1943.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1934.11-1934.51" + attribute \src "ls180.v:1972.11-1972.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1975.11-1975.51" + attribute \src "ls180.v:1985.11-1985.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2016.11-2016.51" + attribute \src "ls180.v:2026.11-2026.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2081.11-2081.51" + attribute \src "ls180.v:2067.11-2067.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2214.11-2214.51" + attribute \src "ls180.v:2132.11-2132.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2295.11-2295.51" + attribute \src "ls180.v:2265.11-2265.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2312.11-2312.51" + attribute \src "ls180.v:2346.11-2346.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2353.11-2353.51" + attribute \src "ls180.v:2363.11-2363.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1827.12-1827.43" + attribute \src "ls180.v:1865.12-1865.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2543.12-2543.55" + attribute \src "ls180.v:2594.12-2594.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2544.5-2544.50" + attribute \src "ls180.v:2595.5-2595.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1829.11-1829.43" + attribute \src "ls180.v:1867.11-1867.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2541.11-2541.55" + attribute \src "ls180.v:2592.11-2592.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2542.5-2542.52" + attribute \src "ls180.v:2593.5-2593.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1828.5-1828.34" + attribute \src "ls180.v:1866.5-1866.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2545.5-2545.46" + attribute \src "ls180.v:2596.5-2596.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2546.5-2546.49" + attribute \src "ls180.v:2597.5-2597.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1837.5-1837.44" + attribute \src "ls180.v:1875.5-1875.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1833.12-1833.54" + attribute \src "ls180.v:1871.12-1871.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1717.11-1717.48" + attribute \src "ls180.v:1755.11-1755.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1716.11-1716.43" + attribute \src "ls180.v:1754.11-1754.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2650.32-2650.66" + attribute \src "ls180.v:2701.32-2701.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2651.32-2651.66" + attribute \src "ls180.v:2702.32-2702.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2670.32-2670.67" + attribute \src "ls180.v:2721.32-2721.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2671.32-2671.67" + attribute \src "ls180.v:2722.32-2722.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2672.32-2672.67" + attribute \src "ls180.v:2723.32-2723.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2673.32-2673.67" + attribute \src "ls180.v:2724.32-2724.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2674.32-2674.67" + attribute \src "ls180.v:2725.32-2725.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2675.32-2675.67" + attribute \src "ls180.v:2726.32-2726.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2676.32-2676.67" + attribute \src "ls180.v:2727.32-2727.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2677.32-2677.67" + attribute \src "ls180.v:2728.32-2728.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2678.32-2678.67" + attribute \src "ls180.v:2729.32-2729.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2679.32-2679.67" + attribute \src "ls180.v:2730.32-2730.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2680.32-2680.67" + attribute \src "ls180.v:2731.32-2731.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2681.32-2681.67" + attribute \src "ls180.v:2732.32-2732.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2682.32-2682.67" + attribute \src "ls180.v:2733.32-2733.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2683.32-2683.67" + attribute \src "ls180.v:2734.32-2734.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2652.32-2652.66" + attribute \src "ls180.v:2703.32-2703.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2653.32-2653.66" + attribute \src "ls180.v:2704.32-2704.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2654.32-2654.66" + attribute \src "ls180.v:2705.32-2705.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2655.32-2655.66" + attribute \src "ls180.v:2706.32-2706.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2656.32-2656.66" + attribute \src "ls180.v:2707.32-2707.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2657.32-2657.66" + attribute \src "ls180.v:2708.32-2708.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2658.32-2658.66" + attribute \src "ls180.v:2709.32-2709.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2659.32-2659.66" + attribute \src "ls180.v:2710.32-2710.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2660.32-2660.66" + attribute \src "ls180.v:2711.32-2711.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2661.32-2661.66" + attribute \src "ls180.v:2712.32-2712.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2662.32-2662.66" + attribute \src "ls180.v:2713.32-2713.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2663.32-2663.66" + attribute \src "ls180.v:2714.32-2714.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2664.32-2664.66" + attribute \src "ls180.v:2715.32-2715.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2665.32-2665.66" + attribute \src "ls180.v:2716.32-2716.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2666.32-2666.66" + attribute \src "ls180.v:2717.32-2717.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2667.32-2667.66" + attribute \src "ls180.v:2718.32-2718.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2668.32-2668.66" + attribute \src "ls180.v:2719.32-2719.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2669.32-2669.66" + attribute \src "ls180.v:2720.32-2720.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1735.5-1735.43" + attribute \src "ls180.v:1773.5-1773.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1736.5-1736.43" + attribute \src "ls180.v:1774.5-1774.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1737.5-1737.43" + attribute \src "ls180.v:1775.5-1775.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1738.5-1738.43" + attribute \src "ls180.v:1776.5-1776.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1734.5-1734.42" + attribute \src "ls180.v:1772.5-1772.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2540.11-2540.36" + attribute \src "ls180.v:2591.11-2591.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1707.11-1707.46" + attribute \src "ls180.v:1745.11-1745.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1706.11-1706.41" + attribute \src "ls180.v:1744.11-1744.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1812.11-1812.51" + attribute \src "ls180.v:1854.11-1854.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1811.11-1811.46" + attribute \src "ls180.v:1853.11-1853.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1780.5-1780.57" + attribute \src "ls180.v:1822.5-1822.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1779.5-1779.52" + attribute \src "ls180.v:1821.5-1821.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1792.11-1792.47" + attribute \src "ls180.v:1834.11-1834.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1791.11-1791.42" + attribute \src "ls180.v:1833.11-1833.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1816.5-1816.49" + attribute \src "ls180.v:1858.5-1858.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1815.5-1815.44" + attribute \src "ls180.v:1857.5-1857.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1820.11-1820.65" + attribute \src "ls180.v:1862.11-1862.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1819.11-1819.60" + attribute \src "ls180.v:1861.11-1861.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1768.11-1768.46" + attribute \src "ls180.v:1810.11-1810.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1767.11-1767.41" + attribute \src "ls180.v:1809.11-1809.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1756.11-1756.52" + attribute \src "ls180.v:1798.11-1798.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1755.11-1755.47" + attribute \src "ls180.v:1797.11-1797.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1752.11-1752.52" + attribute \src "ls180.v:1794.11-1794.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1751.11-1751.47" + attribute \src "ls180.v:1793.11-1793.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1764.5-1764.46" + attribute \src "ls180.v:1806.5-1806.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1763.5-1763.41" + attribute \src "ls180.v:1805.5-1805.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1772.11-1772.53" + attribute \src "ls180.v:1814.11-1814.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1771.11-1771.48" + attribute \src "ls180.v:1813.11-1813.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1748.5-1748.46" + attribute \src "ls180.v:1790.5-1790.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1747.5-1747.41" + attribute \src "ls180.v:1789.5-1789.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1848.5-1848.30" + attribute \src "ls180.v:1886.5-1886.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1844.12-1844.40" + attribute \src "ls180.v:1882.12-1882.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1855.11-1855.35" + attribute \src "ls180.v:1893.11-1893.35" wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1856.11-1856.37" + attribute \src "ls180.v:1894.11-1894.37" wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1744.11-1744.47" + attribute \src "ls180.v:1782.11-1782.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1743.11-1743.42" + attribute \src "ls180.v:1781.11-1781.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1824.11-1824.47" + attribute \src "ls180.v:1786.11-1786.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1823.11-1823.42" + attribute \src "ls180.v:1785.11-1785.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2539.11-2539.31" + attribute \src "ls180.v:2590.11-2590.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2592.5-2592.39" + attribute \src "ls180.v:2643.5-2643.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2593.5-2593.39" + attribute \src "ls180.v:2644.5-2644.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2585.11-2585.47" + attribute \src "ls180.v:2636.11-2636.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2586.12-2586.49" + attribute \src "ls180.v:2637.12-2637.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2587.5-2587.41" + attribute \src "ls180.v:2638.5-2638.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2588.5-2588.41" + attribute \src "ls180.v:2639.5-2639.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2589.5-2589.41" + attribute \src "ls180.v:2640.5-2640.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2590.5-2590.41" + attribute \src "ls180.v:2641.5-2641.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2591.5-2591.41" + attribute \src "ls180.v:2642.5-2642.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:1686.12-1686.44" - wire width 16 $1\libresocsim_clk_divider1[15:0] - attribute \src "ls180.v:1681.5-1681.34" - wire $1\libresocsim_clk_enable[0:0] - attribute \src "ls180.v:1668.5-1668.34" - wire $1\libresocsim_control_re[0:0] - attribute \src "ls180.v:1667.12-1667.47" - wire width 16 $1\libresocsim_control_storage[15:0] - attribute \src "ls180.v:1683.11-1683.35" - wire width 3 $1\libresocsim_count[2:0] - attribute \src "ls180.v:1825.11-1825.57" - wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1826.5-1826.54" - wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1682.5-1682.33" - wire $1\libresocsim_cs_enable[0:0] - attribute \src "ls180.v:1678.5-1678.29" - wire $1\libresocsim_cs_re[0:0] - attribute \src "ls180.v:1677.5-1677.34" - wire $1\libresocsim_cs_storage[0:0] - attribute \src "ls180.v:1658.5-1658.29" - wire $1\libresocsim_done0[0:0] - attribute \src "ls180.v:1659.5-1659.27" - wire $1\libresocsim_irq[0:0] - attribute \src "ls180.v:1680.5-1680.35" - wire $1\libresocsim_loopback_re[0:0] - attribute \src "ls180.v:1679.5-1679.40" - wire $1\libresocsim_loopback_storage[0:0] - attribute \src "ls180.v:1661.11-1661.34" - wire width 8 $1\libresocsim_miso[7:0] - attribute \src "ls180.v:1691.11-1691.39" - wire width 8 $1\libresocsim_miso_data[7:0] - attribute \src "ls180.v:1685.5-1685.34" - wire $1\libresocsim_miso_latch[0:0] - attribute \src "ls180.v:1689.11-1689.39" - wire width 8 $1\libresocsim_mosi_data[7:0] - attribute \src "ls180.v:1684.5-1684.34" - wire $1\libresocsim_mosi_latch[0:0] - attribute \src "ls180.v:1673.5-1673.31" - wire $1\libresocsim_mosi_re[0:0] - attribute \src "ls180.v:1690.11-1690.38" - wire width 3 $1\libresocsim_mosi_sel[2:0] - attribute \src "ls180.v:1672.11-1672.42" - wire width 8 $1\libresocsim_mosi_storage[7:0] - attribute \src "ls180.v:1693.5-1693.26" - wire $1\libresocsim_re[0:0] - attribute \src "ls180.v:1665.5-1665.30" - wire $1\libresocsim_start1[0:0] - attribute \src "ls180.v:1692.12-1692.41" - wire width 16 $1\libresocsim_storage[15:0] - attribute \src "ls180.v:804.5-804.29" + attribute \src "ls180.v:834.5-834.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:801.5-801.34" + attribute \src "ls180.v:831.5-831.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1741.5-1741.55" + attribute \src "ls180.v:1779.5-1779.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1742.5-1742.58" + attribute \src "ls180.v:1780.5-1780.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:803.12-803.40" + attribute \src "ls180.v:833.12-833.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:800.5-800.31" + attribute \src "ls180.v:830.5-830.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:235.12-235.38" + attribute \src "ls180.v:265.12-265.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:236.5-236.36" + attribute \src "ls180.v:266.5-266.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:997.12-997.30" - wire width 42 $1\main_dummy[41:0] - attribute \src "ls180.v:952.5-952.27" + attribute \src "ls180.v:1065.12-1065.30" + wire width 36 $1\main_dummy[35:0] + attribute \src "ls180.v:982.5-982.27" wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:951.12-951.40" + attribute \src "ls180.v:981.12-981.40" wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:956.5-956.28" + attribute \src "ls180.v:986.5-986.28" wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:955.12-955.41" + attribute \src "ls180.v:985.12-985.41" wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:953.12-953.36" + attribute \src "ls180.v:983.12-983.36" wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:220.5-220.24" + attribute \src "ls180.v:1090.5-1090.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1089.11-1089.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:250.5-250.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:1562.12-1562.43" + attribute \src "ls180.v:1638.12-1638.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1566.5-1566.35" + attribute \src "ls180.v:1642.5-1642.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1565.11-1565.41" + attribute \src "ls180.v:1641.11-1641.41" wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1567.5-1567.35" + attribute \src "ls180.v:1643.5-1643.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1569.5-1569.34" + attribute \src "ls180.v:1645.5-1645.34" wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:57.12-57.47" + attribute \src "ls180.v:62.12-62.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:142.5-142.47" + attribute \src "ls180.v:172.5-172.47" wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1696.5-1696.69" + attribute \src "ls180.v:1734.5-1734.69" wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1697.5-1697.72" + attribute \src "ls180.v:1735.5-1735.72" wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:144.12-144.53" + attribute \src "ls180.v:174.12-174.53" wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:141.5-141.44" + attribute \src "ls180.v:171.5-171.44" wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:157.5-157.47" + attribute \src "ls180.v:187.5-187.47" wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1700.5-1700.69" + attribute \src "ls180.v:1738.5-1738.69" wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1701.5-1701.72" + attribute \src "ls180.v:1739.5-1739.72" wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:159.12-159.53" + attribute \src "ls180.v:189.12-189.53" wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:156.5-156.44" + attribute \src "ls180.v:186.5-186.44" wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:172.5-172.47" + attribute \src "ls180.v:202.5-202.47" wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1704.5-1704.69" + attribute \src "ls180.v:1742.5-1742.69" wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1705.5-1705.72" + attribute \src "ls180.v:1743.5-1743.72" wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:174.12-174.53" + attribute \src "ls180.v:204.12-204.53" wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:171.5-171.44" + attribute \src "ls180.v:201.5-201.44" wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:195.5-195.34" + attribute \src "ls180.v:225.5-225.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:194.5-194.39" + attribute \src "ls180.v:224.5-224.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:215.5-215.44" + attribute \src "ls180.v:245.5-245.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:214.5-214.49" + attribute \src "ls180.v:244.5-244.49" wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:130.12-130.71" + attribute \src "ls180.v:160.12-160.71" wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:134.5-134.63" + attribute \src "ls180.v:164.5-164.63" wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:131.12-131.73" + attribute \src "ls180.v:161.12-161.73" wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:133.11-133.69" + attribute \src "ls180.v:163.11-163.69" wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:135.5-135.63" + attribute \src "ls180.v:165.5-165.63" wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:137.5-137.62" + attribute \src "ls180.v:167.5-167.62" wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:145.12-145.71" + attribute \src "ls180.v:175.12-175.71" wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:149.5-149.63" + attribute \src "ls180.v:179.5-179.63" wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:146.12-146.73" + attribute \src "ls180.v:176.12-176.73" wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:148.11-148.69" + attribute \src "ls180.v:178.11-178.69" wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:150.5-150.63" + attribute \src "ls180.v:180.5-180.63" wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:152.5-152.62" + attribute \src "ls180.v:182.5-182.62" wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:160.12-160.71" + attribute \src "ls180.v:190.12-190.71" wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:164.5-164.63" + attribute \src "ls180.v:194.5-194.63" wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:161.12-161.73" + attribute \src "ls180.v:191.12-191.73" wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:163.11-163.69" + attribute \src "ls180.v:193.11-193.69" wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:165.5-165.63" + attribute \src "ls180.v:195.5-195.63" wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:167.5-167.62" + attribute \src "ls180.v:197.5-197.62" wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:120.5-120.65" - wire $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] - attribute \src "ls180.v:66.5-66.46" + attribute \src "ls180.v:71.5-71.46" wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:77.5-77.46" + attribute \src "ls180.v:82.5-82.46" wire $1\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:59.12-59.55" + attribute \src "ls180.v:64.12-64.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:110.5-110.49" + attribute \src "ls180.v:115.5-115.49" wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:191.5-191.36" + attribute \src "ls180.v:221.5-221.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:190.12-190.49" + attribute \src "ls180.v:220.12-220.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:181.5-181.40" + attribute \src "ls180.v:211.5-211.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:193.5-193.38" + attribute \src "ls180.v:223.5-223.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:192.12-192.51" + attribute \src "ls180.v:222.12-222.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:50.5-50.37" + attribute \src "ls180.v:55.5-55.37" wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:49.5-49.42" + attribute \src "ls180.v:54.5-54.42" wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:52.5-52.39" + attribute \src "ls180.v:57.5-57.39" wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:51.12-51.60" + attribute \src "ls180.v:56.12-56.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:197.5-197.44" + attribute \src "ls180.v:227.5-227.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:196.5-196.49" + attribute \src "ls180.v:226.5-226.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:216.12-216.42" + attribute \src "ls180.v:246.12-246.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:198.12-198.49" + attribute \src "ls180.v:228.12-228.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:188.11-188.37" + attribute \src "ls180.v:218.11-218.37" wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:204.5-204.39" + attribute \src "ls180.v:234.5-234.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:205.5-205.45" + attribute \src "ls180.v:235.5-235.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:202.5-202.41" + attribute \src "ls180.v:232.5-232.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:792.12-792.40" + attribute \src "ls180.v:822.12-822.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:796.5-796.32" + attribute \src "ls180.v:826.5-826.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:793.12-793.42" + attribute \src "ls180.v:823.12-823.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:795.11-795.38" + attribute \src "ls180.v:825.11-825.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:797.5-797.32" + attribute \src "ls180.v:827.5-827.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:799.5-799.31" + attribute \src "ls180.v:829.5-829.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:827.12-827.45" - wire width 32 $1\main_phase_accumulator_rx[31:0] - attribute \src "ls180.v:817.12-817.45" - wire width 32 $1\main_phase_accumulator_tx[31:0] - attribute \src "ls180.v:1001.12-1001.37" + attribute \src "ls180.v:1069.12-1069.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1003.5-1003.31" + attribute \src "ls180.v:1071.5-1071.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1002.5-1002.36" + attribute \src "ls180.v:1070.5-1070.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1007.5-1007.31" + attribute \src "ls180.v:1075.5-1075.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1006.12-1006.44" + attribute \src "ls180.v:1074.12-1074.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1005.5-1005.30" + attribute \src "ls180.v:1073.5-1073.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1004.12-1004.43" + attribute \src "ls180.v:1072.12-1072.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1011.12-1011.37" + attribute \src "ls180.v:1079.12-1079.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1013.5-1013.31" + attribute \src "ls180.v:1081.5-1081.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1012.5-1012.36" + attribute \src "ls180.v:1080.5-1080.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1017.5-1017.31" + attribute \src "ls180.v:1085.5-1085.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1016.12-1016.44" + attribute \src "ls180.v:1084.12-1084.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1015.5-1015.30" + attribute \src "ls180.v:1083.5-1083.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1014.12-1014.43" + attribute \src "ls180.v:1082.12-1082.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:237.11-237.32" + attribute \src "ls180.v:267.11-267.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:810.5-810.19" - wire $1\main_re[0:0] - attribute \src "ls180.v:831.11-831.34" - wire width 4 $1\main_rx_bitcount[3:0] - attribute \src "ls180.v:832.5-832.24" - wire $1\main_rx_busy[0:0] - attribute \src "ls180.v:829.5-829.21" - wire $1\main_rx_r[0:0] - attribute \src "ls180.v:830.11-830.29" - wire width 8 $1\main_rx_reg[7:0] - attribute \src "ls180.v:1531.11-1531.50" + attribute \src "ls180.v:1607.11-1607.50" wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1527.5-1527.51" + attribute \src "ls180.v:1603.5-1603.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1528.5-1528.50" + attribute \src "ls180.v:1604.5-1604.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1529.12-1529.66" + attribute \src "ls180.v:1605.12-1605.66" wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1530.11-1530.77" + attribute \src "ls180.v:1606.11-1606.77" wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1533.5-1533.49" + attribute \src "ls180.v:1609.5-1609.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1506.11-1506.47" + attribute \src "ls180.v:1582.11-1582.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1503.11-1503.45" + attribute \src "ls180.v:1579.11-1579.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1505.11-1505.47" + attribute \src "ls180.v:1581.11-1581.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1507.11-1507.50" + attribute \src "ls180.v:1583.11-1583.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1541.12-1541.62" + attribute \src "ls180.v:1617.12-1617.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1542.12-1542.60" + attribute \src "ls180.v:1618.12-1618.60" wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1539.5-1539.45" + attribute \src "ls180.v:1615.5-1615.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1549.5-1549.54" + attribute \src "ls180.v:1625.5-1625.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1548.12-1548.67" + attribute \src "ls180.v:1624.12-1624.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1553.5-1553.56" + attribute \src "ls180.v:1629.5-1629.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1552.5-1552.61" + attribute \src "ls180.v:1628.5-1628.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1551.5-1551.56" + attribute \src "ls180.v:1627.5-1627.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1550.12-1550.69" + attribute \src "ls180.v:1626.12-1626.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1557.5-1557.54" + attribute \src "ls180.v:1633.5-1633.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1556.5-1556.59" + attribute \src "ls180.v:1632.5-1632.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1559.12-1559.61" + attribute \src "ls180.v:1635.12-1635.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1813.12-1813.87" + attribute \src "ls180.v:1855.12-1855.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1814.5-1814.82" + attribute \src "ls180.v:1856.5-1856.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1544.5-1544.57" + attribute \src "ls180.v:1620.5-1620.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1554.5-1554.53" + attribute \src "ls180.v:1630.5-1630.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1323.5-1323.38" + attribute \src "ls180.v:1399.5-1399.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1322.12-1322.51" + attribute \src "ls180.v:1398.12-1398.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1321.5-1321.39" + attribute \src "ls180.v:1397.5-1397.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1320.11-1320.51" + attribute \src "ls180.v:1396.11-1396.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1307.5-1307.39" + attribute \src "ls180.v:1383.5-1383.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1306.12-1306.52" + attribute \src "ls180.v:1382.12-1382.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1309.5-1309.38" + attribute \src "ls180.v:1385.5-1385.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1308.12-1308.51" + attribute \src "ls180.v:1384.12-1384.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1462.11-1462.39" + attribute \src "ls180.v:1538.11-1538.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1797.11-1797.62" + attribute \src "ls180.v:1839.11-1839.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1798.5-1798.59" + attribute \src "ls180.v:1840.5-1840.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1463.5-1463.32" + attribute \src "ls180.v:1539.5-1539.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1793.5-1793.55" + attribute \src "ls180.v:1835.5-1835.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1794.5-1794.58" + attribute \src "ls180.v:1836.5-1836.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1464.5-1464.33" + attribute \src "ls180.v:1540.5-1540.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1801.5-1801.56" + attribute \src "ls180.v:1843.5-1843.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1802.5-1802.59" + attribute \src "ls180.v:1844.5-1844.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1314.13-1314.53" + attribute \src "ls180.v:1390.13-1390.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1809.13-1809.76" + attribute \src "ls180.v:1851.13-1851.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1810.5-1810.69" + attribute \src "ls180.v:1852.5-1852.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1465.5-1465.35" + attribute \src "ls180.v:1541.5-1541.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1803.5-1803.58" + attribute \src "ls180.v:1845.5-1845.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1804.5-1804.61" + attribute \src "ls180.v:1846.5-1846.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1423.11-1423.47" + attribute \src "ls180.v:1499.11-1499.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1429.5-1429.46" + attribute \src "ls180.v:1505.5-1505.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1428.12-1428.54" + attribute \src "ls180.v:1504.12-1504.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1424.12-1424.58" + attribute \src "ls180.v:1500.12-1500.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1436.5-1436.46" + attribute \src "ls180.v:1512.5-1512.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1435.12-1435.54" + attribute \src "ls180.v:1511.12-1511.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1431.12-1431.58" + attribute \src "ls180.v:1507.12-1507.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1443.5-1443.46" + attribute \src "ls180.v:1519.5-1519.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1442.12-1442.54" + attribute \src "ls180.v:1518.12-1518.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1438.12-1438.58" + attribute \src "ls180.v:1514.12-1514.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1450.5-1450.46" + attribute \src "ls180.v:1526.5-1526.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1449.12-1449.54" + attribute \src "ls180.v:1525.12-1525.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1445.12-1445.58" + attribute \src "ls180.v:1521.12-1521.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1452.12-1452.53" + attribute \src "ls180.v:1528.12-1528.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1453.12-1453.53" + attribute \src "ls180.v:1529.12-1529.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1454.12-1454.53" + attribute \src "ls180.v:1530.12-1530.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1455.12-1455.53" + attribute \src "ls180.v:1531.12-1531.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1457.12-1457.51" + attribute \src "ls180.v:1533.12-1533.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1458.12-1458.51" + attribute \src "ls180.v:1534.12-1534.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1459.12-1459.51" + attribute \src "ls180.v:1535.12-1535.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1460.12-1460.51" + attribute \src "ls180.v:1536.12-1536.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1414.5-1414.48" + attribute \src "ls180.v:1490.5-1490.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1415.5-1415.47" + attribute \src "ls180.v:1491.5-1491.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1416.11-1416.61" + attribute \src "ls180.v:1492.11-1492.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1413.5-1413.48" + attribute \src "ls180.v:1489.5-1489.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1412.5-1412.48" + attribute \src "ls180.v:1488.5-1488.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1417.5-1417.50" + attribute \src "ls180.v:1493.5-1493.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1422.11-1422.47" + attribute \src "ls180.v:1498.11-1498.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1456.5-1456.43" + attribute \src "ls180.v:1532.5-1532.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1379.11-1379.48" + attribute \src "ls180.v:1455.11-1455.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1789.11-1789.87" + attribute \src "ls180.v:1831.11-1831.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1790.5-1790.84" + attribute \src "ls180.v:1832.5-1832.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1384.12-1384.55" + attribute \src "ls180.v:1460.12-1460.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1380.12-1380.59" + attribute \src "ls180.v:1456.12-1456.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1391.12-1391.55" + attribute \src "ls180.v:1467.12-1467.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1387.12-1387.59" + attribute \src "ls180.v:1463.12-1463.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1398.12-1398.55" + attribute \src "ls180.v:1474.12-1474.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1394.12-1394.59" + attribute \src "ls180.v:1470.12-1470.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1405.12-1405.55" + attribute \src "ls180.v:1481.12-1481.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1401.12-1401.59" + attribute \src "ls180.v:1477.12-1477.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1408.12-1408.54" + attribute \src "ls180.v:1484.12-1484.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1781.12-1781.93" + attribute \src "ls180.v:1823.12-1823.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1782.5-1782.88" + attribute \src "ls180.v:1824.5-1824.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1409.12-1409.54" + attribute \src "ls180.v:1485.12-1485.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1783.12-1783.93" + attribute \src "ls180.v:1825.12-1825.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1784.5-1784.88" + attribute \src "ls180.v:1826.5-1826.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1410.12-1410.54" + attribute \src "ls180.v:1486.12-1486.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1785.12-1785.93" + attribute \src "ls180.v:1827.12-1827.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1786.5-1786.88" + attribute \src "ls180.v:1828.5-1828.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1411.12-1411.54" + attribute \src "ls180.v:1487.12-1487.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1787.12-1787.93" + attribute \src "ls180.v:1829.12-1829.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1788.5-1788.88" + attribute \src "ls180.v:1830.5-1830.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1370.5-1370.49" + attribute \src "ls180.v:1446.5-1446.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1377.5-1377.50" + attribute \src "ls180.v:1453.5-1453.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1378.11-1378.64" + attribute \src "ls180.v:1454.11-1454.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1375.5-1375.51" + attribute \src "ls180.v:1451.5-1451.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1374.5-1374.51" + attribute \src "ls180.v:1450.5-1450.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1366.11-1366.47" + attribute \src "ls180.v:1442.11-1442.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1324.11-1324.51" + attribute \src "ls180.v:1400.11-1400.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1467.12-1467.42" + attribute \src "ls180.v:1543.12-1543.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1799.12-1799.65" + attribute \src "ls180.v:1841.12-1841.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1800.5-1800.60" + attribute \src "ls180.v:1842.5-1842.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1468.5-1468.33" + attribute \src "ls180.v:1544.5-1544.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1795.5-1795.56" + attribute \src "ls180.v:1837.5-1837.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1796.5-1796.59" + attribute \src "ls180.v:1838.5-1838.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1469.5-1469.34" + attribute \src "ls180.v:1545.5-1545.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1805.5-1805.57" + attribute \src "ls180.v:1847.5-1847.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1806.5-1806.60" + attribute \src "ls180.v:1848.5-1848.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1470.5-1470.36" + attribute \src "ls180.v:1546.5-1546.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1807.5-1807.59" + attribute \src "ls180.v:1849.5-1849.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1808.5-1808.62" + attribute \src "ls180.v:1850.5-1850.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1615.11-1615.48" + attribute \src "ls180.v:1691.11-1691.48" wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1613.11-1613.64" + attribute \src "ls180.v:1689.11-1689.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1589.5-1589.40" + attribute \src "ls180.v:1665.5-1665.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1588.12-1588.53" + attribute \src "ls180.v:1664.12-1664.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1587.12-1587.45" + attribute \src "ls180.v:1663.12-1663.45" wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1817.12-1817.75" + attribute \src "ls180.v:1859.12-1859.75" wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1818.5-1818.70" + attribute \src "ls180.v:1860.5-1860.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1594.5-1594.44" + attribute \src "ls180.v:1670.5-1670.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1593.5-1593.42" + attribute \src "ls180.v:1669.5-1669.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1592.5-1592.47" + attribute \src "ls180.v:1668.5-1668.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1591.5-1591.42" + attribute \src "ls180.v:1667.5-1667.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1590.12-1590.55" + attribute \src "ls180.v:1666.12-1666.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1597.5-1597.40" + attribute \src "ls180.v:1673.5-1673.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1596.5-1596.45" + attribute \src "ls180.v:1672.5-1672.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1601.12-1601.47" + attribute \src "ls180.v:1677.12-1677.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1821.12-1821.87" + attribute \src "ls180.v:1863.12-1863.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1822.5-1822.82" + attribute \src "ls180.v:1864.5-1864.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1580.5-1580.42" + attribute \src "ls180.v:1656.5-1656.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1581.12-1581.61" + attribute \src "ls180.v:1657.12-1657.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1579.5-1579.43" + attribute \src "ls180.v:1655.5-1655.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1578.5-1578.43" + attribute \src "ls180.v:1654.5-1654.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1585.5-1585.44" + attribute \src "ls180.v:1661.5-1661.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1586.12-1586.60" + attribute \src "ls180.v:1662.12-1662.60" wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1582.5-1582.45" + attribute \src "ls180.v:1658.5-1658.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1642.11-1642.47" + attribute \src "ls180.v:1718.11-1718.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1639.11-1639.45" + attribute \src "ls180.v:1715.11-1715.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1641.11-1641.47" + attribute \src "ls180.v:1717.11-1717.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1643.11-1643.50" + attribute \src "ls180.v:1719.11-1719.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1023.5-1023.35" + attribute \src "ls180.v:1099.5-1099.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1026.5-1026.35" + attribute \src "ls180.v:1102.5-1102.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1027.5-1027.36" + attribute \src "ls180.v:1103.5-1103.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1025.11-1025.41" + attribute \src "ls180.v:1101.11-1101.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1021.5-1021.33" + attribute \src "ls180.v:1097.5-1097.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1020.11-1020.46" + attribute \src "ls180.v:1096.11-1096.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1129.5-1129.49" + attribute \src "ls180.v:1205.5-1205.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1130.5-1130.48" + attribute \src "ls180.v:1206.5-1206.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1131.11-1131.62" + attribute \src "ls180.v:1207.11-1207.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1127.5-1127.49" + attribute \src "ls180.v:1203.5-1203.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1114.11-1114.54" + attribute \src "ls180.v:1190.11-1190.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1110.5-1110.55" + attribute \src "ls180.v:1186.5-1186.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1111.5-1111.54" + attribute \src "ls180.v:1187.5-1187.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1112.11-1112.68" + attribute \src "ls180.v:1188.11-1188.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1113.11-1113.81" + attribute \src "ls180.v:1189.11-1189.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1116.5-1116.53" + attribute \src "ls180.v:1192.5-1192.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1132.5-1132.38" + attribute \src "ls180.v:1208.5-1208.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1761.5-1761.66" + attribute \src "ls180.v:1803.5-1803.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1762.5-1762.69" + attribute \src "ls180.v:1804.5-1804.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1102.5-1102.36" + attribute \src "ls180.v:1178.5-1178.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1097.5-1097.53" + attribute \src "ls180.v:1173.5-1173.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1084.11-1084.39" + attribute \src "ls180.v:1160.11-1160.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1757.11-1757.67" + attribute \src "ls180.v:1799.11-1799.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1758.5-1758.64" + attribute \src "ls180.v:1800.5-1800.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1069.5-1069.48" + attribute \src "ls180.v:1145.5-1145.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1070.5-1070.50" + attribute \src "ls180.v:1146.5-1146.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1071.5-1071.51" + attribute \src "ls180.v:1147.5-1147.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1076.5-1076.37" + attribute \src "ls180.v:1152.5-1152.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1077.11-1077.53" + attribute \src "ls180.v:1153.11-1153.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1075.5-1075.38" + attribute \src "ls180.v:1151.5-1151.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1074.5-1074.38" + attribute \src "ls180.v:1150.5-1150.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1080.5-1080.39" + attribute \src "ls180.v:1156.5-1156.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1081.11-1081.53" + attribute \src "ls180.v:1157.11-1157.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1082.11-1082.55" + attribute \src "ls180.v:1158.11-1158.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1079.5-1079.40" + attribute \src "ls180.v:1155.5-1155.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1078.5-1078.40" + attribute \src "ls180.v:1154.5-1154.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1083.12-1083.48" + attribute \src "ls180.v:1159.12-1159.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1759.12-1759.71" + attribute \src "ls180.v:1801.12-1801.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1760.5-1760.66" + attribute \src "ls180.v:1802.5-1802.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1056.11-1056.39" + attribute \src "ls180.v:1132.11-1132.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1753.11-1753.66" + attribute \src "ls180.v:1795.11-1795.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1754.5-1754.63" + attribute \src "ls180.v:1796.5-1796.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1055.5-1055.32" + attribute \src "ls180.v:1131.5-1131.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1046.5-1046.48" + attribute \src "ls180.v:1122.5-1122.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1047.5-1047.50" + attribute \src "ls180.v:1123.5-1123.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1048.5-1048.51" + attribute \src "ls180.v:1124.5-1124.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1053.5-1053.37" + attribute \src "ls180.v:1129.5-1129.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1054.11-1054.51" + attribute \src "ls180.v:1130.11-1130.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1052.5-1052.38" + attribute \src "ls180.v:1128.5-1128.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1051.5-1051.38" + attribute \src "ls180.v:1127.5-1127.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1240.11-1240.41" + attribute \src "ls180.v:1316.11-1316.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1773.11-1773.70" + attribute \src "ls180.v:1815.11-1815.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1774.5-1774.66" + attribute \src "ls180.v:1816.5-1816.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1285.5-1285.51" + attribute \src "ls180.v:1361.5-1361.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1286.5-1286.50" + attribute \src "ls180.v:1362.5-1362.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1287.11-1287.64" + attribute \src "ls180.v:1363.11-1363.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1283.5-1283.51" + attribute \src "ls180.v:1359.5-1359.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1270.5-1270.50" + attribute \src "ls180.v:1346.5-1346.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1266.5-1266.57" + attribute \src "ls180.v:1342.5-1342.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1267.5-1267.56" + attribute \src "ls180.v:1343.5-1343.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1268.11-1268.70" + attribute \src "ls180.v:1344.11-1344.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1269.11-1269.83" + attribute \src "ls180.v:1345.11-1345.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1272.5-1272.55" + attribute \src "ls180.v:1348.5-1348.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1288.5-1288.40" + attribute \src "ls180.v:1364.5-1364.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1777.5-1777.69" + attribute \src "ls180.v:1819.5-1819.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1778.5-1778.72" + attribute \src "ls180.v:1820.5-1820.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1258.5-1258.38" + attribute \src "ls180.v:1334.5-1334.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1253.5-1253.55" + attribute \src "ls180.v:1329.5-1329.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1223.5-1223.49" + attribute \src "ls180.v:1299.5-1299.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1230.5-1230.38" + attribute \src "ls180.v:1306.5-1306.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1231.11-1231.61" + attribute \src "ls180.v:1307.11-1307.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1229.5-1229.39" + attribute \src "ls180.v:1305.5-1305.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1228.5-1228.39" + attribute \src "ls180.v:1304.5-1304.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1235.5-1235.40" + attribute \src "ls180.v:1311.5-1311.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1236.11-1236.54" + attribute \src "ls180.v:1312.11-1312.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1237.11-1237.56" + attribute \src "ls180.v:1313.11-1313.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1233.5-1233.41" + attribute \src "ls180.v:1309.5-1309.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1232.5-1232.41" + attribute \src "ls180.v:1308.5-1308.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1238.5-1238.33" + attribute \src "ls180.v:1314.5-1314.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1239.12-1239.49" + attribute \src "ls180.v:1315.12-1315.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1775.12-1775.73" + attribute \src "ls180.v:1817.12-1817.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1776.5-1776.68" + attribute \src "ls180.v:1818.5-1818.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1148.11-1148.40" + attribute \src "ls180.v:1224.11-1224.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1769.11-1769.61" + attribute \src "ls180.v:1811.11-1811.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1770.5-1770.58" + attribute \src "ls180.v:1812.5-1812.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1207.5-1207.50" + attribute \src "ls180.v:1283.5-1283.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1208.5-1208.49" + attribute \src "ls180.v:1284.5-1284.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1209.11-1209.63" + attribute \src "ls180.v:1285.11-1285.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1205.5-1205.50" + attribute \src "ls180.v:1281.5-1281.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1192.11-1192.55" + attribute \src "ls180.v:1268.11-1268.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1188.5-1188.56" + attribute \src "ls180.v:1264.5-1264.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1189.5-1189.55" + attribute \src "ls180.v:1265.5-1265.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1190.11-1190.69" + attribute \src "ls180.v:1266.11-1266.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1191.11-1191.82" + attribute \src "ls180.v:1267.11-1267.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1194.5-1194.54" + attribute \src "ls180.v:1270.5-1270.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1210.5-1210.39" + attribute \src "ls180.v:1286.5-1286.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1765.5-1765.66" + attribute \src "ls180.v:1807.5-1807.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1766.5-1766.69" + attribute \src "ls180.v:1808.5-1808.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1180.5-1180.37" + attribute \src "ls180.v:1256.5-1256.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1175.5-1175.54" + attribute \src "ls180.v:1251.5-1251.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1162.5-1162.34" + attribute \src "ls180.v:1238.5-1238.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1137.5-1137.49" + attribute \src "ls180.v:1213.5-1213.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1140.11-1140.58" + attribute \src "ls180.v:1216.11-1216.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1141.5-1141.53" + attribute \src "ls180.v:1217.5-1217.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1144.5-1144.39" + attribute \src "ls180.v:1220.5-1220.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1145.5-1145.38" + attribute \src "ls180.v:1221.5-1221.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1146.11-1146.52" + attribute \src "ls180.v:1222.11-1222.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1143.5-1143.39" + attribute \src "ls180.v:1219.5-1219.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1142.5-1142.39" + attribute \src "ls180.v:1218.5-1218.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1160.5-1160.34" + attribute \src "ls180.v:1236.5-1236.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1147.5-1147.33" + attribute \src "ls180.v:1223.5-1223.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1161.5-1161.34" + attribute \src "ls180.v:1237.5-1237.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1041.11-1041.39" + attribute \src "ls180.v:1117.11-1117.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1749.11-1749.66" + attribute \src "ls180.v:1791.11-1791.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1750.5-1750.63" + attribute \src "ls180.v:1792.5-1792.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1036.5-1036.48" + attribute \src "ls180.v:1112.5-1112.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1037.5-1037.50" + attribute \src "ls180.v:1113.5-1113.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1038.5-1038.51" + attribute \src "ls180.v:1114.5-1114.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1039.11-1039.57" + attribute \src "ls180.v:1115.11-1115.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1040.5-1040.52" + attribute \src "ls180.v:1116.5-1116.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1290.5-1290.35" + attribute \src "ls180.v:1366.5-1366.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1293.11-1293.42" + attribute \src "ls180.v:1369.11-1369.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:299.5-299.33" + attribute \src "ls180.v:329.5-329.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:298.12-298.46" + attribute \src "ls180.v:328.12-328.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:301.5-301.34" + attribute \src "ls180.v:331.5-331.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:300.11-300.45" + attribute \src "ls180.v:330.11-330.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:397.5-397.50" + attribute \src "ls180.v:427.5-427.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:419.11-419.70" + attribute \src "ls180.v:449.11-449.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:416.11-416.68" + attribute \src "ls180.v:446.11-446.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:418.11-418.70" + attribute \src "ls180.v:448.11-448.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:420.11-420.73" + attribute \src "ls180.v:450.11-450.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:443.5-443.59" + attribute \src "ls180.v:473.5-473.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:444.5-444.58" + attribute \src "ls180.v:474.5-474.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:446.12-446.74" + attribute \src "ls180.v:476.12-476.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:445.5-445.64" + attribute \src "ls180.v:475.5-475.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:441.5-441.59" + attribute \src "ls180.v:471.5-471.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:389.12-389.57" + attribute \src "ls180.v:419.12-419.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:391.5-391.51" + attribute \src "ls180.v:421.5-421.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:394.5-394.54" + attribute \src "ls180.v:424.5-424.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:395.5-395.55" + attribute \src "ls180.v:425.5-425.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:396.5-396.56" + attribute \src "ls180.v:426.5-426.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:392.5-392.51" + attribute \src "ls180.v:422.5-422.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:393.5-393.50" + attribute \src "ls180.v:423.5-423.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:388.5-388.45" + attribute \src "ls180.v:418.5-418.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:387.5-387.45" + attribute \src "ls180.v:417.5-417.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:386.5-386.47" + attribute \src "ls180.v:416.5-416.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:384.5-384.51" + attribute \src "ls180.v:414.5-414.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:383.5-383.51" + attribute \src "ls180.v:413.5-413.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:447.12-447.47" + attribute \src "ls180.v:477.12-477.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:451.5-451.45" + attribute \src "ls180.v:481.5-481.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:452.5-452.54" + attribute \src "ls180.v:482.5-482.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:450.5-450.44" + attribute \src "ls180.v:480.5-480.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:448.5-448.46" + attribute \src "ls180.v:478.5-478.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:455.11-455.55" + attribute \src "ls180.v:485.11-485.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:454.32-454.76" + attribute \src "ls180.v:484.32-484.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:479.5-479.50" + attribute \src "ls180.v:509.5-509.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:501.11-501.70" + attribute \src "ls180.v:531.11-531.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:498.11-498.68" + attribute \src "ls180.v:528.11-528.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:500.11-500.70" + attribute \src "ls180.v:530.11-530.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:502.11-502.73" + attribute \src "ls180.v:532.11-532.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:525.5-525.59" + attribute \src "ls180.v:555.5-555.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:526.5-526.58" + attribute \src "ls180.v:556.5-556.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:528.12-528.74" + attribute \src "ls180.v:558.12-558.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:527.5-527.64" + attribute \src "ls180.v:557.5-557.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:523.5-523.59" + attribute \src "ls180.v:553.5-553.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:471.12-471.57" + attribute \src "ls180.v:501.12-501.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:473.5-473.51" + attribute \src "ls180.v:503.5-503.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:476.5-476.54" + attribute \src "ls180.v:506.5-506.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:477.5-477.55" + attribute \src "ls180.v:507.5-507.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:478.5-478.56" + attribute \src "ls180.v:508.5-508.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:474.5-474.51" + attribute \src "ls180.v:504.5-504.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:475.5-475.50" + attribute \src "ls180.v:505.5-505.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:470.5-470.45" + attribute \src "ls180.v:500.5-500.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:469.5-469.45" + attribute \src "ls180.v:499.5-499.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:468.5-468.47" + attribute \src "ls180.v:498.5-498.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:466.5-466.51" + attribute \src "ls180.v:496.5-496.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:465.5-465.51" + attribute \src "ls180.v:495.5-495.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:529.12-529.47" + attribute \src "ls180.v:559.12-559.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:533.5-533.45" + attribute \src "ls180.v:563.5-563.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:534.5-534.54" + attribute \src "ls180.v:564.5-564.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:532.5-532.44" + attribute \src "ls180.v:562.5-562.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:530.5-530.46" + attribute \src "ls180.v:560.5-560.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:537.11-537.55" + attribute \src "ls180.v:567.11-567.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:536.32-536.76" + attribute \src "ls180.v:566.32-566.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:561.5-561.50" + attribute \src "ls180.v:591.5-591.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:583.11-583.70" + attribute \src "ls180.v:613.11-613.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:580.11-580.68" + attribute \src "ls180.v:610.11-610.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:582.11-582.70" + attribute \src "ls180.v:612.11-612.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:584.11-584.73" + attribute \src "ls180.v:614.11-614.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:607.5-607.59" + attribute \src "ls180.v:637.5-637.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:608.5-608.58" + attribute \src "ls180.v:638.5-638.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:610.12-610.74" + attribute \src "ls180.v:640.12-640.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:609.5-609.64" + attribute \src "ls180.v:639.5-639.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:605.5-605.59" + attribute \src "ls180.v:635.5-635.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:553.12-553.57" + attribute \src "ls180.v:583.12-583.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:555.5-555.51" + attribute \src "ls180.v:585.5-585.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:558.5-558.54" + attribute \src "ls180.v:588.5-588.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:559.5-559.55" + attribute \src "ls180.v:589.5-589.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:560.5-560.56" + attribute \src "ls180.v:590.5-590.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:556.5-556.51" + attribute \src "ls180.v:586.5-586.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:557.5-557.50" + attribute \src "ls180.v:587.5-587.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:552.5-552.45" + attribute \src "ls180.v:582.5-582.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:551.5-551.45" + attribute \src "ls180.v:581.5-581.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:550.5-550.47" + attribute \src "ls180.v:580.5-580.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:548.5-548.51" + attribute \src "ls180.v:578.5-578.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:547.5-547.51" + attribute \src "ls180.v:577.5-577.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:611.12-611.47" + attribute \src "ls180.v:641.12-641.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:615.5-615.45" + attribute \src "ls180.v:645.5-645.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:616.5-616.54" + attribute \src "ls180.v:646.5-646.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:614.5-614.44" + attribute \src "ls180.v:644.5-644.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:612.5-612.46" + attribute \src "ls180.v:642.5-642.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:619.11-619.55" + attribute \src "ls180.v:649.11-649.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:618.32-618.76" + attribute \src "ls180.v:648.32-648.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:643.5-643.50" + attribute \src "ls180.v:673.5-673.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:665.11-665.70" + attribute \src "ls180.v:695.11-695.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:662.11-662.68" + attribute \src "ls180.v:692.11-692.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:664.11-664.70" + attribute \src "ls180.v:694.11-694.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:666.11-666.73" + attribute \src "ls180.v:696.11-696.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:689.5-689.59" + attribute \src "ls180.v:719.5-719.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:690.5-690.58" + attribute \src "ls180.v:720.5-720.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:692.12-692.74" + attribute \src "ls180.v:722.12-722.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:691.5-691.64" + attribute \src "ls180.v:721.5-721.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:687.5-687.59" + attribute \src "ls180.v:717.5-717.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:635.12-635.57" + attribute \src "ls180.v:665.12-665.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:637.5-637.51" + attribute \src "ls180.v:667.5-667.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:640.5-640.54" + attribute \src "ls180.v:670.5-670.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:641.5-641.55" + attribute \src "ls180.v:671.5-671.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:642.5-642.56" + attribute \src "ls180.v:672.5-672.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:638.5-638.51" + attribute \src "ls180.v:668.5-668.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:639.5-639.50" + attribute \src "ls180.v:669.5-669.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:634.5-634.45" + attribute \src "ls180.v:664.5-664.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:633.5-633.45" + attribute \src "ls180.v:663.5-663.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:632.5-632.47" + attribute \src "ls180.v:662.5-662.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:630.5-630.51" + attribute \src "ls180.v:660.5-660.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:629.5-629.51" + attribute \src "ls180.v:659.5-659.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:693.12-693.47" + attribute \src "ls180.v:723.12-723.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:697.5-697.45" + attribute \src "ls180.v:727.5-727.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:698.5-698.54" + attribute \src "ls180.v:728.5-728.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:696.5-696.44" + attribute \src "ls180.v:726.5-726.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:694.5-694.46" + attribute \src "ls180.v:724.5-724.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:701.11-701.55" + attribute \src "ls180.v:731.11-731.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:700.32-700.76" + attribute \src "ls180.v:730.32-730.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:716.5-716.49" + attribute \src "ls180.v:746.5-746.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:717.5-717.49" + attribute \src "ls180.v:747.5-747.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:718.5-718.48" + attribute \src "ls180.v:748.5-748.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:724.11-724.45" + attribute \src "ls180.v:754.11-754.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:722.11-722.46" + attribute \src "ls180.v:752.11-752.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:734.5-734.49" + attribute \src "ls180.v:764.5-764.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:735.5-735.49" + attribute \src "ls180.v:765.5-765.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:736.5-736.48" + attribute \src "ls180.v:766.5-766.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:731.5-731.43" + attribute \src "ls180.v:761.5-761.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:742.11-742.45" + attribute \src "ls180.v:772.11-772.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:740.11-740.46" + attribute \src "ls180.v:770.11-770.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:729.5-729.48" + attribute \src "ls180.v:759.5-759.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:726.5-726.44" + attribute \src "ls180.v:756.5-756.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:727.5-727.45" + attribute \src "ls180.v:757.5-757.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:355.5-355.31" + attribute \src "ls180.v:385.5-385.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:356.12-356.44" + attribute \src "ls180.v:386.12-386.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:357.11-357.43" + attribute \src "ls180.v:387.11-387.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:358.5-358.38" + attribute \src "ls180.v:388.5-388.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:359.5-359.38" + attribute \src "ls180.v:389.5-389.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:360.5-360.37" + attribute \src "ls180.v:390.5-390.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:354.5-354.32" + attribute \src "ls180.v:384.5-384.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:353.5-353.32" + attribute \src "ls180.v:383.5-383.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:293.5-293.33" + attribute \src "ls180.v:323.5-323.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:292.11-292.44" + attribute \src "ls180.v:322.11-322.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:337.12-337.45" + attribute \src "ls180.v:367.12-367.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:338.11-338.40" + attribute \src "ls180.v:368.11-368.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:339.5-339.35" + attribute \src "ls180.v:369.5-369.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:340.5-340.34" + attribute \src "ls180.v:370.5-370.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:341.5-341.35" + attribute \src "ls180.v:371.5-371.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:350.5-350.39" + attribute \src "ls180.v:380.5-380.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:342.5-342.34" + attribute \src "ls180.v:372.5-372.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:348.5-348.39" + attribute \src "ls180.v:378.5-378.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:761.5-761.26" + attribute \src "ls180.v:791.5-791.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:764.5-764.26" + attribute \src "ls180.v:794.5-794.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:334.12-334.46" + attribute \src "ls180.v:364.12-364.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:335.11-335.47" + attribute \src "ls180.v:365.11-365.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:240.5-240.36" + attribute \src "ls180.v:270.5-270.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:241.5-241.35" + attribute \src "ls180.v:271.5-271.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:242.5-242.36" + attribute \src "ls180.v:272.5-272.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:252.12-252.45" + attribute \src "ls180.v:282.12-282.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:253.5-253.43" + attribute \src "ls180.v:283.5-283.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:243.5-243.35" + attribute \src "ls180.v:273.5-273.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:279.5-279.38" + attribute \src "ls180.v:309.5-309.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:270.12-270.48" + attribute \src "ls180.v:300.12-300.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:271.11-271.43" + attribute \src "ls180.v:301.11-301.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:272.5-272.38" + attribute \src "ls180.v:302.5-302.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:276.5-276.36" + attribute \src "ls180.v:306.5-306.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:273.5-273.37" + attribute \src "ls180.v:303.5-303.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:277.5-277.36" + attribute \src "ls180.v:307.5-307.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:274.5-274.38" + attribute \src "ls180.v:304.5-304.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:283.5-283.42" + attribute \src "ls180.v:313.5-313.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:278.5-278.40" + attribute \src "ls180.v:308.5-308.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:275.5-275.37" + attribute \src "ls180.v:305.5-305.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:280.12-280.47" + attribute \src "ls180.v:310.12-310.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:281.5-281.42" + attribute \src "ls180.v:311.5-311.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:282.11-282.50" + attribute \src "ls180.v:312.11-312.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:371.5-371.38" + attribute \src "ls180.v:401.5-401.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:370.5-370.38" + attribute \src "ls180.v:400.5-400.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:291.5-291.25" + attribute \src "ls180.v:321.5-321.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:377.5-377.38" + attribute \src "ls180.v:407.5-407.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:376.11-376.46" + attribute \src "ls180.v:406.11-406.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:375.5-375.38" + attribute \src "ls180.v:405.5-405.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:372.5-372.39" + attribute \src "ls180.v:402.5-402.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:268.12-268.46" + attribute \src "ls180.v:298.12-298.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:269.5-269.44" + attribute \src "ls180.v:299.5-299.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:304.12-304.37" + attribute \src "ls180.v:334.12-334.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:746.11-746.40" + attribute \src "ls180.v:776.11-776.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:290.11-290.36" + attribute \src "ls180.v:320.11-320.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:755.5-755.36" + attribute \src "ls180.v:785.5-785.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:754.32-754.63" + attribute \src "ls180.v:784.32-784.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:763.11-763.34" + attribute \src "ls180.v:793.11-793.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:766.11-766.34" + attribute \src "ls180.v:796.11-796.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:368.11-368.44" + attribute \src "ls180.v:398.11-398.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:758.11-758.42" + attribute \src "ls180.v:788.11-788.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:757.32-757.63" + attribute \src "ls180.v:787.32-787.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:303.5-303.32" + attribute \src "ls180.v:333.5-333.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:302.12-302.45" + attribute \src "ls180.v:332.12-332.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:812.5-812.27" - wire $1\main_sink_ready[0:0] - attribute \src "ls180.v:825.11-825.42" - wire width 8 $1\main_source_payload_data[7:0] - attribute \src "ls180.v:821.5-821.29" - wire $1\main_source_valid[0:0] - attribute \src "ls180.v:990.12-990.48" - wire width 16 $1\main_spi_master_clk_divider1[15:0] - attribute \src "ls180.v:985.5-985.38" - wire $1\main_spi_master_clk_enable[0:0] - attribute \src "ls180.v:972.5-972.38" - wire $1\main_spi_master_control_re[0:0] - attribute \src "ls180.v:971.12-971.51" - wire width 16 $1\main_spi_master_control_storage[15:0] - attribute \src "ls180.v:987.11-987.39" - wire width 3 $1\main_spi_master_count[2:0] - attribute \src "ls180.v:1745.11-1745.61" - wire width 3 $1\main_spi_master_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1746.5-1746.58" - wire $1\main_spi_master_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:986.5-986.37" - wire $1\main_spi_master_cs_enable[0:0] - attribute \src "ls180.v:982.5-982.33" - wire $1\main_spi_master_cs_re[0:0] - attribute \src "ls180.v:981.5-981.38" - wire $1\main_spi_master_cs_storage[0:0] - attribute \src "ls180.v:962.5-962.33" - wire $1\main_spi_master_done0[0:0] - attribute \src "ls180.v:963.5-963.31" - wire $1\main_spi_master_irq[0:0] - attribute \src "ls180.v:984.5-984.39" - wire $1\main_spi_master_loopback_re[0:0] - attribute \src "ls180.v:983.5-983.44" - wire $1\main_spi_master_loopback_storage[0:0] - attribute \src "ls180.v:965.11-965.38" - wire width 8 $1\main_spi_master_miso[7:0] - attribute \src "ls180.v:995.11-995.43" - wire width 8 $1\main_spi_master_miso_data[7:0] - attribute \src "ls180.v:989.5-989.38" - wire $1\main_spi_master_miso_latch[0:0] - attribute \src "ls180.v:993.11-993.43" - wire width 8 $1\main_spi_master_mosi_data[7:0] - attribute \src "ls180.v:988.5-988.38" - wire $1\main_spi_master_mosi_latch[0:0] - attribute \src "ls180.v:977.5-977.35" - wire $1\main_spi_master_mosi_re[0:0] - attribute \src "ls180.v:994.11-994.42" - wire width 3 $1\main_spi_master_mosi_sel[2:0] - attribute \src "ls180.v:976.11-976.46" - wire width 8 $1\main_spi_master_mosi_storage[7:0] - attribute \src "ls180.v:969.5-969.34" - wire $1\main_spi_master_start1[0:0] - attribute \src "ls180.v:809.12-809.38" - wire width 32 $1\main_storage[31:0] - attribute \src "ls180.v:819.11-819.34" - wire width 4 $1\main_tx_bitcount[3:0] - attribute \src "ls180.v:820.5-820.24" - wire $1\main_tx_busy[0:0] - attribute \src "ls180.v:818.11-818.29" - wire width 8 $1\main_tx_reg[7:0] - attribute \src "ls180.v:826.5-826.30" - wire $1\main_uart_clk_rxen[0:0] - attribute \src "ls180.v:816.5-816.30" - wire $1\main_uart_clk_txen[0:0] - attribute \src "ls180.v:859.11-859.50" + attribute \src "ls180.v:1001.12-1001.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1002.5-1002.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1006.11-1006.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1007.5-1007.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1063.5-1063.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1062.12-1062.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1011.5-1011.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1012.5-1012.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1013.5-1013.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1014.5-1014.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1015.5-1015.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1016.5-1016.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1017.11-1017.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1783.11-1783.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1784.5-1784.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1018.5-1018.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1019.5-1019.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:992.5-992.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1020.12-1020.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1023.11-1023.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1024.11-1024.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1025.11-1025.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:993.5-993.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:995.11-995.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:999.5-999.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1056.12-1056.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1051.5-1051.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1038.5-1038.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1037.12-1037.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1053.11-1053.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1787.11-1787.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1788.5-1788.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1052.5-1052.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1048.5-1048.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1047.5-1047.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1028.5-1028.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1029.5-1029.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1050.5-1050.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1049.5-1049.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1031.11-1031.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1061.11-1061.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1055.5-1055.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1059.11-1059.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1054.5-1054.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1043.5-1043.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1060.11-1060.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1042.11-1042.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1035.5-1035.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:889.11-889.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:861.5-861.37" + attribute \src "ls180.v:891.5-891.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:855.11-855.49" + attribute \src "ls180.v:885.11-885.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:860.11-860.48" + attribute \src "ls180.v:890.11-890.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:850.5-850.30" + attribute \src "ls180.v:857.12-857.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:847.12-847.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:840.5-840.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:861.11-861.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:862.5-862.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:859.5-859.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:860.11-860.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:842.5-842.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:855.11-855.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:851.5-851.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:839.12-839.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:849.11-849.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:850.5-850.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:848.11-848.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:856.5-856.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:846.5-846.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:880.5-880.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:934.11-934.43" + attribute \src "ls180.v:964.11-964.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:931.11-931.42" + attribute \src "ls180.v:961.11-961.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:933.11-933.43" + attribute \src "ls180.v:963.11-963.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:924.5-924.38" + attribute \src "ls180.v:954.5-954.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:935.11-935.46" + attribute \src "ls180.v:965.11-965.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:851.5-851.36" + attribute \src "ls180.v:881.5-881.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:848.5-848.32" + attribute \src "ls180.v:878.5-878.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:845.5-845.30" + attribute \src "ls180.v:875.5-875.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:897.11-897.43" + attribute \src "ls180.v:927.11-927.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:894.11-894.42" + attribute \src "ls180.v:924.11-924.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:896.11-896.43" + attribute \src "ls180.v:926.11-926.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:887.5-887.38" + attribute \src "ls180.v:917.5-917.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:898.11-898.46" + attribute \src "ls180.v:928.11-928.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:846.5-846.36" + attribute \src "ls180.v:876.5-876.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:843.5-843.32" + attribute \src "ls180.v:873.5-873.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:787.5-787.29" + attribute \src "ls180.v:817.5-817.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:805.5-805.31" + attribute \src "ls180.v:835.5-835.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2768.68-2768.110" - wire $add$ls180.v:2768$22_Y - attribute \src "ls180.v:2828.68-2828.110" - wire $add$ls180.v:2828$33_Y - attribute \src "ls180.v:2888.68-2888.110" - wire $add$ls180.v:2888$44_Y - attribute \src "ls180.v:4021.54-4021.83" - wire $add$ls180.v:4021$537_Y - attribute \src "ls180.v:4121.36-4121.89" - wire width 5 $add$ls180.v:4121$583_Y - attribute \src "ls180.v:4151.36-4151.89" - wire width 5 $add$ls180.v:4151$594_Y - attribute \src "ls180.v:4206.53-4206.81" - wire width 3 $add$ls180.v:4206$607_Y - attribute \src "ls180.v:4306.58-4306.86" - wire width 8 $add$ls180.v:4306$635_Y - attribute \src "ls180.v:4363.58-4363.86" - wire width 8 $add$ls180.v:4363$638_Y - attribute \src "ls180.v:4380.58-4380.86" - wire width 8 $add$ls180.v:4380$640_Y - attribute \src "ls180.v:4473.59-4473.87" - wire width 8 $add$ls180.v:4473$657_Y - attribute \src "ls180.v:4498.59-4498.87" - wire width 8 $add$ls180.v:4498$660_Y - attribute \src "ls180.v:4620.53-4620.82" - wire width 8 $add$ls180.v:4620$677_Y - attribute \src "ls180.v:4731.65-4731.114" - wire width 10 $add$ls180.v:4731$691_Y - attribute \src "ls180.v:4736.62-4736.91" - wire width 10 $add$ls180.v:4736$694_Y - attribute \src "ls180.v:4762.61-4762.90" - wire width 10 $add$ls180.v:4762$697_Y - attribute \src "ls180.v:4966.80-4966.117" - wire width 3 $add$ls180.v:4966$882_Y - attribute \src "ls180.v:5160.54-5160.82" - wire width 3 $add$ls180.v:5160$957_Y - attribute \src "ls180.v:5212.55-5212.84" - wire width 32 $add$ls180.v:5212$967_Y - attribute \src "ls180.v:5238.57-5238.86" - wire width 32 $add$ls180.v:5238$975_Y - attribute \src "ls180.v:5359.51-5359.134" - wire width 32 $add$ls180.v:5359$991_Y - attribute \src "ls180.v:5362.77-5362.125" - wire width 32 $add$ls180.v:5362$993_Y - attribute \src "ls180.v:5455.50-5455.105" - wire width 32 $add$ls180.v:5455$1002_Y - attribute \src "ls180.v:5457.77-5457.111" - wire width 32 $add$ls180.v:5457$1003_Y - attribute \src "ls180.v:5569.49-5569.73" - wire width 3 $add$ls180.v:5569$1022_Y - attribute \src "ls180.v:7437.36-7437.70" - wire width 32 $add$ls180.v:7437$2405_Y - attribute \src "ls180.v:7522.37-7522.72" - wire width 4 $add$ls180.v:7522$2426_Y - attribute \src "ls180.v:7539.60-7539.119" - wire width 3 $add$ls180.v:7539$2430_Y - attribute \src "ls180.v:7542.60-7542.119" - wire width 3 $add$ls180.v:7542$2431_Y - attribute \src "ls180.v:7546.59-7546.116" - wire width 4 $add$ls180.v:7546$2436_Y - attribute \src "ls180.v:7585.60-7585.119" - wire width 3 $add$ls180.v:7585$2446_Y - attribute \src "ls180.v:7588.60-7588.119" - wire width 3 $add$ls180.v:7588$2447_Y - attribute \src "ls180.v:7592.59-7592.116" - wire width 4 $add$ls180.v:7592$2452_Y - attribute \src "ls180.v:7631.60-7631.119" - wire width 3 $add$ls180.v:7631$2462_Y - attribute \src "ls180.v:7634.60-7634.119" - wire width 3 $add$ls180.v:7634$2463_Y - attribute \src "ls180.v:7638.59-7638.116" - wire width 4 $add$ls180.v:7638$2468_Y - attribute \src "ls180.v:7677.60-7677.119" - wire width 3 $add$ls180.v:7677$2478_Y - attribute \src "ls180.v:7680.60-7680.119" - wire width 3 $add$ls180.v:7680$2479_Y - attribute \src "ls180.v:7684.59-7684.116" - wire width 4 $add$ls180.v:7684$2484_Y - attribute \src "ls180.v:7914.25-7914.48" - wire width 4 $add$ls180.v:7914$2538_Y - attribute \src "ls180.v:7930.55-7930.95" - wire width 33 $add$ls180.v:7930$2541_Y - attribute \src "ls180.v:7943.25-7943.48" - wire width 4 $add$ls180.v:7943$2545_Y - attribute \src "ls180.v:7962.55-7962.95" - wire width 33 $add$ls180.v:7962$2548_Y - attribute \src "ls180.v:7988.33-7988.65" - wire width 4 $add$ls180.v:7988$2556_Y - attribute \src "ls180.v:7991.33-7991.65" - wire width 4 $add$ls180.v:7991$2557_Y - attribute \src "ls180.v:7995.33-7995.64" - wire width 5 $add$ls180.v:7995$2562_Y - attribute \src "ls180.v:8010.33-8010.65" - wire width 4 $add$ls180.v:8010$2567_Y - attribute \src "ls180.v:8013.33-8013.65" - wire width 4 $add$ls180.v:8013$2568_Y - attribute \src "ls180.v:8017.33-8017.64" - wire width 5 $add$ls180.v:8017$2573_Y - attribute \src "ls180.v:8038.35-8038.70" - wire width 16 $add$ls180.v:8038$2575_Y - attribute \src "ls180.v:8074.25-8074.49" - wire width 32 $add$ls180.v:8074$2580_Y - attribute \src "ls180.v:8088.25-8088.49" - wire width 32 $add$ls180.v:8088$2584_Y - attribute \src "ls180.v:8102.31-8102.61" - wire width 9 $add$ls180.v:8102$2589_Y - attribute \src "ls180.v:8125.45-8125.88" - wire width 3 $add$ls180.v:8125$2593_Y - attribute \src "ls180.v:8171.71-8171.114" - wire width 4 $add$ls180.v:8171$2599_Y - attribute \src "ls180.v:8206.46-8206.90" - wire width 3 $add$ls180.v:8206$2605_Y - attribute \src "ls180.v:8252.72-8252.116" - wire width 4 $add$ls180.v:8252$2611_Y - attribute \src "ls180.v:8285.47-8285.92" - wire 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"ls180.v:6421.100-6421.145" + wire $eq$ls180.v:6421$2149_Y + attribute \src "ls180.v:6422.103-6422.148" + wire $eq$ls180.v:6422$2153_Y + attribute \src "ls180.v:6424.101-6424.146" + wire $eq$ls180.v:6424$2156_Y + attribute \src "ls180.v:6425.104-6425.149" + wire $eq$ls180.v:6425$2160_Y + attribute \src "ls180.v:6427.105-6427.150" + wire $eq$ls180.v:6427$2163_Y + attribute \src "ls180.v:6428.108-6428.153" + wire $eq$ls180.v:6428$2167_Y + attribute \src "ls180.v:6430.106-6430.151" + wire $eq$ls180.v:6430$2170_Y + attribute \src "ls180.v:6431.109-6431.154" + wire $eq$ls180.v:6431$2174_Y + attribute \src "ls180.v:6433.104-6433.149" + wire $eq$ls180.v:6433$2177_Y + attribute \src "ls180.v:6434.107-6434.152" + wire $eq$ls180.v:6434$2181_Y + attribute \src "ls180.v:6436.101-6436.146" + wire $eq$ls180.v:6436$2184_Y + attribute \src "ls180.v:6437.104-6437.149" + wire $eq$ls180.v:6437$2188_Y + attribute \src "ls180.v:6439.100-6439.145" + wire $eq$ls180.v:6439$2191_Y + attribute \src "ls180.v:6440.103-6440.148" + wire $eq$ls180.v:6440$2195_Y + attribute \src "ls180.v:6450.33-6450.79" + wire $eq$ls180.v:6450$2197_Y + attribute \src "ls180.v:6452.106-6452.151" + wire $eq$ls180.v:6452$2199_Y + attribute \src "ls180.v:6453.109-6453.154" + wire $eq$ls180.v:6453$2203_Y + attribute \src "ls180.v:6455.106-6455.151" + wire $eq$ls180.v:6455$2206_Y + attribute \src "ls180.v:6456.109-6456.154" + wire $eq$ls180.v:6456$2210_Y + attribute \src "ls180.v:6458.106-6458.151" + wire $eq$ls180.v:6458$2213_Y + attribute \src "ls180.v:6459.109-6459.154" + wire $eq$ls180.v:6459$2217_Y + attribute \src "ls180.v:6461.106-6461.151" + wire $eq$ls180.v:6461$2220_Y + attribute \src "ls180.v:6462.109-6462.154" + wire $eq$ls180.v:6462$2224_Y + attribute \src "ls180.v:6843.41-6843.81" + wire $eq$ls180.v:6843$2261_Y + attribute \src "ls180.v:6843.144-6843.177" + wire $eq$ls180.v:6843$2262_Y + attribute \src "ls180.v:6843.219-6843.252" + wire $eq$ls180.v:6843$2265_Y + attribute \src "ls180.v:6843.294-6843.327" + wire $eq$ls180.v:6843$2268_Y + attribute \src "ls180.v:6867.41-6867.81" + wire $eq$ls180.v:6867$2277_Y + attribute \src "ls180.v:6867.144-6867.177" + wire $eq$ls180.v:6867$2278_Y + attribute \src "ls180.v:6867.219-6867.252" + wire $eq$ls180.v:6867$2281_Y + attribute \src "ls180.v:6867.294-6867.327" + wire $eq$ls180.v:6867$2284_Y + attribute \src "ls180.v:6891.41-6891.81" + wire $eq$ls180.v:6891$2293_Y + attribute \src "ls180.v:6891.144-6891.177" + wire $eq$ls180.v:6891$2294_Y + attribute \src "ls180.v:6891.219-6891.252" + wire $eq$ls180.v:6891$2297_Y + attribute \src "ls180.v:6891.294-6891.327" + wire $eq$ls180.v:6891$2300_Y + attribute \src "ls180.v:6915.41-6915.81" + wire $eq$ls180.v:6915$2309_Y + attribute \src "ls180.v:6915.144-6915.177" + wire $eq$ls180.v:6915$2310_Y + attribute \src "ls180.v:6915.219-6915.252" + wire $eq$ls180.v:6915$2313_Y + attribute \src "ls180.v:6915.294-6915.327" + wire $eq$ls180.v:6915$2316_Y + attribute \src "ls180.v:7508.8-7508.38" + wire $eq$ls180.v:7508$2419_Y + attribute \src "ls180.v:7539.8-7539.42" + wire $eq$ls180.v:7539$2427_Y + attribute \src "ls180.v:7559.38-7559.74" + wire $eq$ls180.v:7559$2430_Y + attribute \src "ls180.v:7566.7-7566.43" + wire $eq$ls180.v:7566$2432_Y + attribute \src "ls180.v:7573.7-7573.43" + wire $eq$ls180.v:7573$2433_Y + attribute \src "ls180.v:7581.7-7581.43" + wire $eq$ls180.v:7581$2434_Y + attribute \src "ls180.v:7633.9-7633.54" + wire $eq$ls180.v:7633$2452_Y + attribute \src "ls180.v:7679.9-7679.54" + wire $eq$ls180.v:7679$2468_Y + attribute \src "ls180.v:7725.9-7725.54" + wire $eq$ls180.v:7725$2484_Y + attribute \src "ls180.v:7771.9-7771.54" + wire $eq$ls180.v:7771$2500_Y + attribute \src "ls180.v:7921.9-7921.41" + wire $eq$ls180.v:7921$2512_Y + attribute \src "ls180.v:7936.9-7936.41" + wire $eq$ls180.v:7936$2515_Y + attribute \src "ls180.v:7942.49-7942.82" + wire $eq$ls180.v:7942$2516_Y + attribute \src "ls180.v:7942.131-7942.164" + wire $eq$ls180.v:7942$2519_Y + attribute \src "ls180.v:7942.213-7942.246" + wire $eq$ls180.v:7942$2522_Y + attribute \src "ls180.v:7942.295-7942.328" + wire $eq$ls180.v:7942$2525_Y + attribute \src "ls180.v:7943.50-7943.83" + wire $eq$ls180.v:7943$2528_Y + attribute \src "ls180.v:7943.132-7943.165" + wire $eq$ls180.v:7943$2531_Y + attribute \src "ls180.v:7943.214-7943.247" + wire $eq$ls180.v:7943$2534_Y + attribute \src "ls180.v:7943.296-7943.329" + wire $eq$ls180.v:7943$2537_Y + attribute \src "ls180.v:7978.9-7978.42" + wire $eq$ls180.v:7978$2549_Y + attribute \src "ls180.v:7981.10-7981.43" + wire $eq$ls180.v:7981$2550_Y + attribute \src "ls180.v:8007.9-8007.42" + wire $eq$ls180.v:8007$2556_Y + attribute \src "ls180.v:8012.10-8012.43" + wire $eq$ls180.v:8012$2557_Y + attribute \src "ls180.v:8219.9-8219.53" + wire $eq$ls180.v:8219$2606_Y + attribute \src "ls180.v:8300.9-8300.54" + wire $eq$ls180.v:8300$2618_Y + attribute \src "ls180.v:8379.9-8379.55" + wire $eq$ls180.v:8379$2630_Y + attribute \src "ls180.v:8602.9-8602.49" + wire $eq$ls180.v:8602$2663_Y + attribute \src "ls180.v:8178.8-8178.54" + wire $ge$ls180.v:8178$2598_Y + attribute \src "ls180.v:8192.8-8192.54" + wire $ge$ls180.v:8192$2602_Y + attribute \src "ls180.v:5152.47-5152.83" + wire $gt$ls180.v:5152$914_Y + attribute \src "ls180.v:5158.7-5158.43" + wire $lt$ls180.v:5158$917_Y + attribute \src "ls180.v:8173.8-8173.43" + wire $lt$ls180.v:8173$2596_Y + attribute \src "ls180.v:8187.8-8187.43" + wire $lt$ls180.v:8187$2600_Y + attribute \src "ls180.v:10068.33-10068.36" + wire width 32 $memrd$\mem$ls180.v:10068$2705_DATA + attribute \src "ls180.v:10079.12-10079.19" + wire width 25 $memrd$\storage$ls180.v:10079$2710_DATA + attribute \src "ls180.v:10086.68-10086.75" + wire width 25 $memrd$\storage$ls180.v:10086$2712_DATA + attribute \src "ls180.v:10093.14-10093.23" + wire width 25 $memrd$\storage_1$ls180.v:10093$2717_DATA + attribute \src "ls180.v:10100.68-10100.77" + wire width 25 $memrd$\storage_1$ls180.v:10100$2719_DATA + attribute \src "ls180.v:10107.14-10107.23" + wire width 25 $memrd$\storage_2$ls180.v:10107$2724_DATA + attribute \src "ls180.v:10114.68-10114.77" + wire width 25 $memrd$\storage_2$ls180.v:10114$2726_DATA + attribute \src "ls180.v:10121.14-10121.23" + wire width 25 $memrd$\storage_3$ls180.v:10121$2731_DATA + attribute \src "ls180.v:10128.68-10128.77" + wire width 25 $memrd$\storage_3$ls180.v:10128$2733_DATA + attribute \src "ls180.v:10136.14-10136.23" + wire width 10 $memrd$\storage_4$ls180.v:10136$2738_DATA + attribute \src "ls180.v:10141.15-10141.24" + wire width 10 $memrd$\storage_4$ls180.v:10141$2740_DATA + attribute \src "ls180.v:10153.14-10153.23" + wire width 10 $memrd$\storage_5$ls180.v:10153$2745_DATA + attribute \src "ls180.v:10158.15-10158.24" + wire width 10 $memrd$\storage_5$ls180.v:10158$2747_DATA + attribute \src "ls180.v:10169.14-10169.23" + wire width 10 $memrd$\storage_6$ls180.v:10169$2752_DATA + attribute \src "ls180.v:10176.45-10176.54" + wire width 10 $memrd$\storage_6$ls180.v:10176$2754_DATA + attribute \src "ls180.v:10183.14-10183.23" + wire width 10 $memrd$\storage_7$ls180.v:10183$2759_DATA + attribute \src "ls180.v:10190.45-10190.54" + wire width 10 $memrd$\storage_7$ls180.v:10190$2761_DATA attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:9979$1_ADDR + wire width 7 $memwr$\mem$ls180.v:10058$1_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9979$1_DATA + wire width 32 $memwr$\mem$ls180.v:10058$1_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9979$1_EN + wire width 32 $memwr$\mem$ls180.v:10058$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:9981$2_ADDR + wire width 7 $memwr$\mem$ls180.v:10060$2_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9981$2_DATA + wire width 32 $memwr$\mem$ls180.v:10060$2_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9981$2_EN + wire width 32 $memwr$\mem$ls180.v:10060$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:9983$3_ADDR + wire width 7 $memwr$\mem$ls180.v:10062$3_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9983$3_DATA + wire width 32 $memwr$\mem$ls180.v:10062$3_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9983$3_EN + wire width 32 $memwr$\mem$ls180.v:10062$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 7 $memwr$\mem$ls180.v:9985$4_ADDR + wire width 7 $memwr$\mem$ls180.v:10064$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9985$4_DATA + wire width 32 $memwr$\mem$ls180.v:10064$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 32 $memwr$\mem$ls180.v:9985$4_EN + wire width 32 $memwr$\mem$ls180.v:10064$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:9999$5_ADDR + wire width 3 $memwr$\storage$ls180.v:10078$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:9999$5_DATA + wire width 25 $memwr$\storage$ls180.v:10078$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:9999$5_EN + wire width 25 $memwr$\storage$ls180.v:10078$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10013$6_ADDR + wire width 3 $memwr$\storage_1$ls180.v:10092$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10013$6_DATA + wire width 25 $memwr$\storage_1$ls180.v:10092$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10013$6_EN + wire width 25 $memwr$\storage_1$ls180.v:10092$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10027$7_ADDR + wire width 3 $memwr$\storage_2$ls180.v:10106$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10027$7_DATA + wire width 25 $memwr$\storage_2$ls180.v:10106$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_2$ls180.v:10027$7_EN + wire width 25 $memwr$\storage_2$ls180.v:10106$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_3$ls180.v:10041$8_ADDR + wire width 3 $memwr$\storage_3$ls180.v:10120$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10041$8_DATA + wire width 25 $memwr$\storage_3$ls180.v:10120$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_3$ls180.v:10041$8_EN + wire width 25 $memwr$\storage_3$ls180.v:10120$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_4$ls180.v:10056$9_ADDR + wire width 4 $memwr$\storage_4$ls180.v:10135$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10056$9_DATA + wire width 10 $memwr$\storage_4$ls180.v:10135$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_4$ls180.v:10056$9_EN + wire width 10 $memwr$\storage_4$ls180.v:10135$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\storage_5$ls180.v:10073$10_ADDR + wire width 4 $memwr$\storage_5$ls180.v:10152$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10073$10_DATA + wire width 10 $memwr$\storage_5$ls180.v:10152$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_5$ls180.v:10073$10_EN + wire width 10 $memwr$\storage_5$ls180.v:10152$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_6$ls180.v:10089$11_ADDR + wire width 5 $memwr$\storage_6$ls180.v:10168$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10089$11_DATA + wire width 10 $memwr$\storage_6$ls180.v:10168$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_6$ls180.v:10089$11_EN + wire width 10 $memwr$\storage_6$ls180.v:10168$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 5 $memwr$\storage_7$ls180.v:10103$12_ADDR + wire width 5 $memwr$\storage_7$ls180.v:10182$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10103$12_DATA + wire width 10 $memwr$\storage_7$ls180.v:10182$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 10 $memwr$\storage_7$ls180.v:10103$12_EN - attribute \src "ls180.v:2918.41-2918.71" - wire $ne$ls180.v:2918$60_Y - attribute \src "ls180.v:3079.70-3079.104" - wire $ne$ls180.v:3079$74_Y - attribute \src "ls180.v:3140.8-3140.142" - wire $ne$ls180.v:3140$93_Y - attribute \src "ls180.v:3172.75-3172.133" - wire $ne$ls180.v:3172$100_Y - attribute \src "ls180.v:3173.75-3173.133" - wire $ne$ls180.v:3173$101_Y - attribute \src "ls180.v:3297.8-3297.142" - wire $ne$ls180.v:3297$123_Y - attribute \src "ls180.v:3329.75-3329.133" - wire $ne$ls180.v:3329$130_Y - attribute \src "ls180.v:3330.75-3330.133" - wire $ne$ls180.v:3330$131_Y - attribute \src "ls180.v:3454.8-3454.142" - wire $ne$ls180.v:3454$153_Y - attribute \src "ls180.v:3486.75-3486.133" - wire $ne$ls180.v:3486$160_Y - attribute \src "ls180.v:3487.75-3487.133" - wire $ne$ls180.v:3487$161_Y - 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"ls180.v:4845.360-4845.432" - wire $xor$ls180.v:4845$801_Y - attribute \src "ls180.v:4845.205-4845.277" - wire $xor$ls180.v:4845$802_Y - attribute \src "ls180.v:4845.164-4845.278" - wire $xor$ls180.v:4845$803_Y - attribute \src "ls180.v:4846.360-4846.432" - wire $xor$ls180.v:4846$804_Y - attribute \src "ls180.v:4846.205-4846.277" - wire $xor$ls180.v:4846$805_Y - attribute \src "ls180.v:4846.164-4846.278" - wire $xor$ls180.v:4846$806_Y - attribute \src "ls180.v:4847.360-4847.432" - wire $xor$ls180.v:4847$807_Y - attribute \src "ls180.v:4847.205-4847.277" - wire $xor$ls180.v:4847$808_Y - attribute \src "ls180.v:4847.164-4847.278" - wire $xor$ls180.v:4847$809_Y - attribute \src "ls180.v:4848.360-4848.432" - wire $xor$ls180.v:4848$810_Y - attribute \src "ls180.v:4848.205-4848.277" - wire $xor$ls180.v:4848$811_Y - attribute \src "ls180.v:4848.164-4848.278" - wire $xor$ls180.v:4848$812_Y - attribute \src "ls180.v:4849.360-4849.432" - wire $xor$ls180.v:4849$813_Y - attribute \src "ls180.v:4849.205-4849.277" - wire $xor$ls180.v:4849$814_Y - attribute \src "ls180.v:4849.164-4849.278" - wire $xor$ls180.v:4849$815_Y - attribute \src "ls180.v:4850.360-4850.432" - wire $xor$ls180.v:4850$816_Y - attribute \src "ls180.v:4850.205-4850.277" - wire $xor$ls180.v:4850$817_Y - attribute \src "ls180.v:4850.164-4850.278" - wire $xor$ls180.v:4850$818_Y - attribute \src "ls180.v:4851.360-4851.432" - wire $xor$ls180.v:4851$819_Y - attribute \src "ls180.v:4851.205-4851.277" - wire $xor$ls180.v:4851$820_Y - attribute \src "ls180.v:4851.164-4851.278" - wire $xor$ls180.v:4851$821_Y - attribute \src "ls180.v:4872.899-4872.983" - wire $xor$ls180.v:4872$835_Y - attribute \src "ls180.v:4872.634-4872.718" - wire $xor$ls180.v:4872$836_Y - attribute \src "ls180.v:4872.588-4872.719" - wire $xor$ls180.v:4872$837_Y - attribute \src "ls180.v:4872.234-4872.318" - wire $xor$ls180.v:4872$838_Y - attribute \src "ls180.v:4872.187-4872.319" - wire $xor$ls180.v:4872$839_Y - attribute \src "ls180.v:4873.899-4873.983" - wire $xor$ls180.v:4873$840_Y - attribute \src "ls180.v:4873.634-4873.718" - wire $xor$ls180.v:4873$841_Y - attribute \src "ls180.v:4873.588-4873.719" - wire $xor$ls180.v:4873$842_Y - attribute \src "ls180.v:4873.234-4873.318" - wire $xor$ls180.v:4873$843_Y - attribute \src "ls180.v:4873.187-4873.319" - wire $xor$ls180.v:4873$844_Y - attribute \src "ls180.v:4882.899-4882.983" - wire $xor$ls180.v:4882$846_Y - attribute \src "ls180.v:4882.634-4882.718" - wire $xor$ls180.v:4882$847_Y - attribute \src "ls180.v:4882.588-4882.719" - wire $xor$ls180.v:4882$848_Y - attribute \src "ls180.v:4882.234-4882.318" - wire $xor$ls180.v:4882$849_Y - attribute \src "ls180.v:4882.187-4882.319" - wire $xor$ls180.v:4882$850_Y - attribute \src "ls180.v:4883.899-4883.983" - wire $xor$ls180.v:4883$851_Y - attribute \src "ls180.v:4883.634-4883.718" - wire $xor$ls180.v:4883$852_Y - attribute \src "ls180.v:4883.588-4883.719" - wire $xor$ls180.v:4883$853_Y - attribute \src "ls180.v:4883.234-4883.318" - wire $xor$ls180.v:4883$854_Y - attribute \src "ls180.v:4883.187-4883.319" - wire $xor$ls180.v:4883$855_Y - attribute \src "ls180.v:4892.899-4892.983" - wire $xor$ls180.v:4892$857_Y - attribute \src "ls180.v:4892.634-4892.718" - wire $xor$ls180.v:4892$858_Y - attribute \src "ls180.v:4892.588-4892.719" - wire $xor$ls180.v:4892$859_Y - attribute \src "ls180.v:4892.234-4892.318" - wire $xor$ls180.v:4892$860_Y - attribute \src "ls180.v:4892.187-4892.319" - wire $xor$ls180.v:4892$861_Y - attribute \src "ls180.v:4893.899-4893.983" - wire $xor$ls180.v:4893$862_Y - attribute \src "ls180.v:4893.634-4893.718" - wire $xor$ls180.v:4893$863_Y - attribute \src "ls180.v:4893.588-4893.719" - wire $xor$ls180.v:4893$864_Y - attribute \src "ls180.v:4893.234-4893.318" - wire $xor$ls180.v:4893$865_Y - attribute \src "ls180.v:4893.187-4893.319" - wire $xor$ls180.v:4893$866_Y - attribute \src "ls180.v:4902.899-4902.983" - wire $xor$ls180.v:4902$868_Y - attribute \src "ls180.v:4902.634-4902.718" - wire $xor$ls180.v:4902$869_Y - attribute \src "ls180.v:4902.588-4902.719" - wire $xor$ls180.v:4902$870_Y - attribute \src "ls180.v:4902.234-4902.318" - wire $xor$ls180.v:4902$871_Y - attribute \src "ls180.v:4902.187-4902.319" - wire $xor$ls180.v:4902$872_Y - attribute \src "ls180.v:4903.899-4903.983" - wire $xor$ls180.v:4903$873_Y - attribute \src "ls180.v:4903.634-4903.718" - wire $xor$ls180.v:4903$874_Y - attribute \src "ls180.v:4903.588-4903.719" - wire $xor$ls180.v:4903$875_Y - attribute \src "ls180.v:4903.234-4903.318" - wire $xor$ls180.v:4903$876_Y - attribute \src "ls180.v:4903.187-4903.319" - wire $xor$ls180.v:4903$877_Y - attribute \src "ls180.v:5054.879-5054.961" - wire $xor$ls180.v:5054$910_Y - attribute \src "ls180.v:5054.620-5054.702" - wire $xor$ls180.v:5054$911_Y - attribute \src "ls180.v:5054.575-5054.703" - wire $xor$ls180.v:5054$912_Y - attribute \src "ls180.v:5054.229-5054.311" - wire $xor$ls180.v:5054$913_Y - attribute \src "ls180.v:5054.183-5054.312" - wire $xor$ls180.v:5054$914_Y - attribute \src "ls180.v:5055.879-5055.961" - wire $xor$ls180.v:5055$915_Y - attribute \src "ls180.v:5055.620-5055.702" - wire $xor$ls180.v:5055$916_Y - attribute \src "ls180.v:5055.575-5055.703" - wire $xor$ls180.v:5055$917_Y - attribute \src "ls180.v:5055.229-5055.311" - wire $xor$ls180.v:5055$918_Y - attribute \src "ls180.v:5055.183-5055.312" - wire $xor$ls180.v:5055$919_Y - attribute \src "ls180.v:5064.879-5064.961" - wire $xor$ls180.v:5064$921_Y - attribute \src "ls180.v:5064.620-5064.702" - wire $xor$ls180.v:5064$922_Y - attribute \src "ls180.v:5064.575-5064.703" - wire $xor$ls180.v:5064$923_Y - attribute \src "ls180.v:5064.229-5064.311" - wire $xor$ls180.v:5064$924_Y - attribute \src "ls180.v:5064.183-5064.312" - wire $xor$ls180.v:5064$925_Y - attribute \src "ls180.v:5065.879-5065.961" - wire $xor$ls180.v:5065$926_Y - attribute \src "ls180.v:5065.620-5065.702" - wire $xor$ls180.v:5065$927_Y - attribute \src "ls180.v:5065.575-5065.703" - wire $xor$ls180.v:5065$928_Y - attribute \src "ls180.v:5065.229-5065.311" - wire $xor$ls180.v:5065$929_Y - attribute \src "ls180.v:5065.183-5065.312" - wire $xor$ls180.v:5065$930_Y - attribute \src "ls180.v:5074.879-5074.961" - wire $xor$ls180.v:5074$932_Y - attribute \src "ls180.v:5074.620-5074.702" - wire $xor$ls180.v:5074$933_Y - attribute \src "ls180.v:5074.575-5074.703" - wire $xor$ls180.v:5074$934_Y - attribute \src "ls180.v:5074.229-5074.311" - wire $xor$ls180.v:5074$935_Y - attribute \src "ls180.v:5074.183-5074.312" - wire $xor$ls180.v:5074$936_Y - attribute \src "ls180.v:5075.879-5075.961" - wire $xor$ls180.v:5075$937_Y - attribute \src "ls180.v:5075.620-5075.702" - wire $xor$ls180.v:5075$938_Y - attribute \src "ls180.v:5075.575-5075.703" - wire $xor$ls180.v:5075$939_Y - attribute \src "ls180.v:5075.229-5075.311" - wire $xor$ls180.v:5075$940_Y - attribute \src "ls180.v:5075.183-5075.312" - wire $xor$ls180.v:5075$941_Y - attribute \src "ls180.v:5084.879-5084.961" - wire $xor$ls180.v:5084$943_Y - attribute \src "ls180.v:5084.620-5084.702" - wire $xor$ls180.v:5084$944_Y - attribute \src "ls180.v:5084.575-5084.703" - wire $xor$ls180.v:5084$945_Y - attribute \src "ls180.v:5084.229-5084.311" - wire $xor$ls180.v:5084$946_Y - attribute \src "ls180.v:5084.183-5084.312" - wire $xor$ls180.v:5084$947_Y - attribute \src "ls180.v:5085.879-5085.961" - wire $xor$ls180.v:5085$948_Y - attribute \src "ls180.v:5085.620-5085.702" - wire $xor$ls180.v:5085$949_Y - attribute \src "ls180.v:5085.575-5085.703" - wire $xor$ls180.v:5085$950_Y - attribute \src "ls180.v:5085.229-5085.311" - wire $xor$ls180.v:5085$951_Y - attribute \src "ls180.v:5085.183-5085.312" - wire $xor$ls180.v:5085$952_Y - attribute \src "ls180.v:1709.11-1709.42" + wire $not$ls180.v:6062$1617_Y + attribute \src "ls180.v:6065.67-6065.98" + wire $not$ls180.v:6065$1624_Y + attribute \src "ls180.v:6068.70-6068.101" + wire $not$ls180.v:6068$1631_Y + attribute \src "ls180.v:6071.70-6071.101" + wire $not$ls180.v:6071$1638_Y + attribute \src "ls180.v:6074.69-6074.100" + wire $not$ls180.v:6074$1645_Y + attribute \src "ls180.v:6077.69-6077.100" + wire $not$ls180.v:6077$1652_Y + attribute \src "ls180.v:6080.69-6080.100" + wire $not$ls180.v:6080$1659_Y + attribute \src "ls180.v:6083.69-6083.100" + wire $not$ls180.v:6083$1666_Y + attribute \src "ls180.v:6122.66-6122.97" + wire $not$ls180.v:6122$1674_Y + attribute \src "ls180.v:6125.66-6125.97" + wire $not$ls180.v:6125$1681_Y + attribute \src "ls180.v:6128.66-6128.97" + wire $not$ls180.v:6128$1688_Y + attribute \src "ls180.v:6131.66-6131.97" + wire $not$ls180.v:6131$1695_Y + attribute \src "ls180.v:6134.66-6134.97" + wire $not$ls180.v:6134$1702_Y + attribute \src "ls180.v:6137.66-6137.97" + wire $not$ls180.v:6137$1709_Y + attribute \src "ls180.v:6140.66-6140.97" + wire $not$ls180.v:6140$1716_Y + attribute \src "ls180.v:6143.66-6143.97" + wire $not$ls180.v:6143$1723_Y + attribute \src "ls180.v:6146.68-6146.99" + wire $not$ls180.v:6146$1730_Y + attribute \src "ls180.v:6149.68-6149.99" + wire $not$ls180.v:6149$1737_Y + attribute \src "ls180.v:6152.68-6152.99" + wire $not$ls180.v:6152$1744_Y + attribute \src "ls180.v:6155.68-6155.99" + wire $not$ls180.v:6155$1751_Y + attribute \src "ls180.v:6158.68-6158.99" + wire $not$ls180.v:6158$1758_Y + attribute \src "ls180.v:6161.65-6161.96" + wire $not$ls180.v:6161$1765_Y + attribute \src "ls180.v:6164.66-6164.97" + wire $not$ls180.v:6164$1772_Y + attribute \src "ls180.v:6167.68-6167.99" + wire $not$ls180.v:6167$1779_Y + attribute \src "ls180.v:6170.68-6170.99" + wire $not$ls180.v:6170$1786_Y + attribute \src "ls180.v:6173.68-6173.99" + wire $not$ls180.v:6173$1793_Y + attribute \src "ls180.v:6176.68-6176.99" + wire $not$ls180.v:6176$1800_Y + attribute \src "ls180.v:6201.68-6201.99" + wire $not$ls180.v:6201$1808_Y + attribute \src "ls180.v:6204.73-6204.104" + wire $not$ls180.v:6204$1815_Y + attribute \src "ls180.v:6207.73-6207.104" + wire $not$ls180.v:6207$1822_Y + attribute \src "ls180.v:6210.66-6210.97" + wire $not$ls180.v:6210$1829_Y + attribute \src "ls180.v:6218.70-6218.101" + wire $not$ls180.v:6218$1837_Y + attribute \src "ls180.v:6221.74-6221.105" + wire $not$ls180.v:6221$1844_Y + attribute \src "ls180.v:6224.64-6224.95" + wire $not$ls180.v:6224$1851_Y + attribute \src "ls180.v:6227.74-6227.105" + wire $not$ls180.v:6227$1858_Y + attribute \src "ls180.v:6230.74-6230.105" + wire $not$ls180.v:6230$1865_Y + attribute \src "ls180.v:6233.75-6233.106" + wire $not$ls180.v:6233$1872_Y + attribute \src "ls180.v:6236.73-6236.104" + wire $not$ls180.v:6236$1879_Y + attribute \src "ls180.v:6239.73-6239.104" + wire $not$ls180.v:6239$1886_Y + attribute \src "ls180.v:6242.73-6242.104" + wire $not$ls180.v:6242$1893_Y + attribute \src "ls180.v:6245.73-6245.104" + wire $not$ls180.v:6245$1900_Y + attribute \src "ls180.v:6263.67-6263.99" + wire $not$ls180.v:6263$1908_Y + attribute \src "ls180.v:6266.67-6266.99" + wire $not$ls180.v:6266$1915_Y + attribute \src "ls180.v:6269.65-6269.97" + wire $not$ls180.v:6269$1922_Y + attribute \src "ls180.v:6272.64-6272.96" + wire $not$ls180.v:6272$1929_Y + attribute \src "ls180.v:6275.63-6275.95" + wire $not$ls180.v:6275$1936_Y + attribute \src "ls180.v:6278.62-6278.94" + wire $not$ls180.v:6278$1943_Y + attribute \src "ls180.v:6281.68-6281.100" + wire $not$ls180.v:6281$1950_Y + attribute \src "ls180.v:6303.67-6303.99" + wire $not$ls180.v:6303$1959_Y + attribute \src "ls180.v:6306.67-6306.99" + wire $not$ls180.v:6306$1966_Y + attribute \src "ls180.v:6309.65-6309.97" + wire $not$ls180.v:6309$1973_Y + attribute \src "ls180.v:6312.64-6312.96" + wire $not$ls180.v:6312$1980_Y + attribute \src "ls180.v:6315.63-6315.95" + wire $not$ls180.v:6315$1987_Y + attribute \src "ls180.v:6318.62-6318.94" + wire $not$ls180.v:6318$1994_Y + attribute \src "ls180.v:6321.68-6321.100" + wire $not$ls180.v:6321$2001_Y + attribute \src "ls180.v:6324.71-6324.103" + wire $not$ls180.v:6324$2008_Y + attribute \src "ls180.v:6327.71-6327.103" + wire $not$ls180.v:6327$2015_Y + attribute \src "ls180.v:6351.64-6351.96" + wire $not$ls180.v:6351$2024_Y + attribute \src "ls180.v:6354.64-6354.96" + wire $not$ls180.v:6354$2031_Y + attribute \src "ls180.v:6357.64-6357.96" + wire $not$ls180.v:6357$2038_Y + attribute \src "ls180.v:6360.64-6360.96" + wire $not$ls180.v:6360$2045_Y + attribute \src "ls180.v:6363.66-6363.98" + wire $not$ls180.v:6363$2052_Y + attribute \src "ls180.v:6366.66-6366.98" + wire $not$ls180.v:6366$2059_Y + attribute \src "ls180.v:6369.66-6369.98" + wire $not$ls180.v:6369$2066_Y + attribute \src "ls180.v:6372.66-6372.98" + wire $not$ls180.v:6372$2073_Y + attribute \src "ls180.v:6375.62-6375.94" + wire $not$ls180.v:6375$2080_Y + attribute \src "ls180.v:6378.72-6378.104" + wire $not$ls180.v:6378$2087_Y + attribute \src "ls180.v:6381.65-6381.97" + wire $not$ls180.v:6381$2094_Y + attribute \src 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$sub$ls180.v:8794$2691_Y + attribute \src "ls180.v:4923.353-4923.425" + wire $xor$ls180.v:4923$710_Y + attribute \src "ls180.v:4923.200-4923.272" + wire $xor$ls180.v:4923$711_Y + attribute \src "ls180.v:4923.160-4923.273" + wire $xor$ls180.v:4923$712_Y + attribute \src "ls180.v:4924.353-4924.425" + wire $xor$ls180.v:4924$713_Y + attribute \src "ls180.v:4924.200-4924.272" + wire $xor$ls180.v:4924$714_Y + attribute \src "ls180.v:4924.160-4924.273" + wire $xor$ls180.v:4924$715_Y + attribute \src "ls180.v:4925.353-4925.425" + wire $xor$ls180.v:4925$716_Y + attribute \src "ls180.v:4925.200-4925.272" + wire $xor$ls180.v:4925$717_Y + attribute \src "ls180.v:4925.160-4925.273" + wire $xor$ls180.v:4925$718_Y + attribute \src "ls180.v:4926.353-4926.425" + wire $xor$ls180.v:4926$719_Y + attribute \src "ls180.v:4926.200-4926.272" + wire $xor$ls180.v:4926$720_Y + attribute \src "ls180.v:4926.160-4926.273" + wire $xor$ls180.v:4926$721_Y + attribute \src "ls180.v:4927.353-4927.425" + wire $xor$ls180.v:4927$722_Y + attribute \src "ls180.v:4927.200-4927.272" + wire $xor$ls180.v:4927$723_Y + attribute \src "ls180.v:4927.160-4927.273" + wire $xor$ls180.v:4927$724_Y + attribute \src "ls180.v:4928.353-4928.425" + wire $xor$ls180.v:4928$725_Y + attribute \src "ls180.v:4928.200-4928.272" + wire $xor$ls180.v:4928$726_Y + attribute \src "ls180.v:4928.160-4928.273" + wire $xor$ls180.v:4928$727_Y + attribute \src "ls180.v:4929.353-4929.425" + wire $xor$ls180.v:4929$728_Y + attribute \src "ls180.v:4929.200-4929.272" + wire $xor$ls180.v:4929$729_Y + attribute \src "ls180.v:4929.160-4929.273" + wire $xor$ls180.v:4929$730_Y + attribute \src "ls180.v:4930.353-4930.425" + wire $xor$ls180.v:4930$731_Y + attribute \src "ls180.v:4930.200-4930.272" + wire $xor$ls180.v:4930$732_Y + attribute \src "ls180.v:4930.160-4930.273" + wire $xor$ls180.v:4930$733_Y + attribute \src "ls180.v:4931.353-4931.425" + wire $xor$ls180.v:4931$734_Y + attribute \src "ls180.v:4931.200-4931.272" + wire $xor$ls180.v:4931$735_Y + attribute \src "ls180.v:4931.160-4931.273" + wire $xor$ls180.v:4931$736_Y + attribute \src "ls180.v:4932.354-4932.426" + wire $xor$ls180.v:4932$737_Y + attribute \src "ls180.v:4932.201-4932.273" + wire $xor$ls180.v:4932$738_Y + attribute \src "ls180.v:4932.161-4932.274" + wire $xor$ls180.v:4932$739_Y + attribute \src "ls180.v:4933.361-4933.434" + wire $xor$ls180.v:4933$740_Y + attribute \src "ls180.v:4933.205-4933.278" + wire $xor$ls180.v:4933$741_Y + attribute \src "ls180.v:4933.164-4933.279" + wire $xor$ls180.v:4933$742_Y + attribute \src "ls180.v:4934.361-4934.434" + wire $xor$ls180.v:4934$743_Y + attribute \src "ls180.v:4934.205-4934.278" + wire $xor$ls180.v:4934$744_Y + attribute \src "ls180.v:4934.164-4934.279" + wire $xor$ls180.v:4934$745_Y + attribute \src "ls180.v:4935.361-4935.434" + wire $xor$ls180.v:4935$746_Y + attribute \src "ls180.v:4935.205-4935.278" + wire $xor$ls180.v:4935$747_Y + attribute \src "ls180.v:4935.164-4935.279" + wire $xor$ls180.v:4935$748_Y + attribute \src "ls180.v:4936.361-4936.434" + wire $xor$ls180.v:4936$749_Y + attribute \src "ls180.v:4936.205-4936.278" + wire $xor$ls180.v:4936$750_Y + attribute \src "ls180.v:4936.164-4936.279" + wire $xor$ls180.v:4936$751_Y + attribute \src "ls180.v:4937.361-4937.434" + wire $xor$ls180.v:4937$752_Y + attribute \src "ls180.v:4937.205-4937.278" + wire $xor$ls180.v:4937$753_Y + attribute \src "ls180.v:4937.164-4937.279" + wire $xor$ls180.v:4937$754_Y + attribute \src "ls180.v:4938.361-4938.434" + wire $xor$ls180.v:4938$755_Y + attribute \src "ls180.v:4938.205-4938.278" + wire $xor$ls180.v:4938$756_Y + attribute \src "ls180.v:4938.164-4938.279" + wire $xor$ls180.v:4938$757_Y + attribute \src "ls180.v:4939.361-4939.434" + wire $xor$ls180.v:4939$758_Y + attribute \src "ls180.v:4939.205-4939.278" + wire $xor$ls180.v:4939$759_Y + attribute \src "ls180.v:4939.164-4939.279" + wire $xor$ls180.v:4939$760_Y + attribute \src "ls180.v:4940.361-4940.434" + wire $xor$ls180.v:4940$761_Y + attribute \src "ls180.v:4940.205-4940.278" + wire $xor$ls180.v:4940$762_Y + attribute \src "ls180.v:4940.164-4940.279" + wire $xor$ls180.v:4940$763_Y + attribute \src "ls180.v:4941.361-4941.434" + wire $xor$ls180.v:4941$764_Y + attribute \src "ls180.v:4941.205-4941.278" + wire $xor$ls180.v:4941$765_Y + attribute \src "ls180.v:4941.164-4941.279" + wire $xor$ls180.v:4941$766_Y + attribute \src "ls180.v:4942.361-4942.434" + wire $xor$ls180.v:4942$767_Y + attribute \src "ls180.v:4942.205-4942.278" + wire $xor$ls180.v:4942$768_Y + attribute \src "ls180.v:4942.164-4942.279" + wire $xor$ls180.v:4942$769_Y + attribute \src "ls180.v:4943.361-4943.434" + wire $xor$ls180.v:4943$770_Y + attribute \src "ls180.v:4943.205-4943.278" + wire $xor$ls180.v:4943$771_Y + attribute \src "ls180.v:4943.164-4943.279" + wire $xor$ls180.v:4943$772_Y + attribute \src "ls180.v:4944.361-4944.434" + wire $xor$ls180.v:4944$773_Y + attribute \src "ls180.v:4944.205-4944.278" + wire $xor$ls180.v:4944$774_Y + attribute \src "ls180.v:4944.164-4944.279" + wire $xor$ls180.v:4944$775_Y + attribute \src "ls180.v:4945.361-4945.434" + wire $xor$ls180.v:4945$776_Y + attribute \src "ls180.v:4945.205-4945.278" + wire $xor$ls180.v:4945$777_Y + attribute \src "ls180.v:4945.164-4945.279" + wire $xor$ls180.v:4945$778_Y + attribute \src "ls180.v:4946.361-4946.434" + wire $xor$ls180.v:4946$779_Y + attribute \src "ls180.v:4946.205-4946.278" + wire $xor$ls180.v:4946$780_Y + attribute \src "ls180.v:4946.164-4946.279" + wire $xor$ls180.v:4946$781_Y + attribute \src "ls180.v:4947.361-4947.434" + wire $xor$ls180.v:4947$782_Y + attribute \src "ls180.v:4947.205-4947.278" + wire $xor$ls180.v:4947$783_Y + attribute \src "ls180.v:4947.164-4947.279" + wire $xor$ls180.v:4947$784_Y + attribute \src "ls180.v:4948.361-4948.434" + wire $xor$ls180.v:4948$785_Y + attribute \src "ls180.v:4948.205-4948.278" + wire $xor$ls180.v:4948$786_Y + attribute \src "ls180.v:4948.164-4948.279" + wire $xor$ls180.v:4948$787_Y + attribute \src "ls180.v:4949.361-4949.434" + wire $xor$ls180.v:4949$788_Y + attribute \src "ls180.v:4949.205-4949.278" + wire $xor$ls180.v:4949$789_Y + attribute \src "ls180.v:4949.164-4949.279" + wire $xor$ls180.v:4949$790_Y + attribute \src "ls180.v:4950.361-4950.434" + wire $xor$ls180.v:4950$791_Y + attribute \src "ls180.v:4950.205-4950.278" + wire $xor$ls180.v:4950$792_Y + attribute \src "ls180.v:4950.164-4950.279" + wire $xor$ls180.v:4950$793_Y + attribute \src "ls180.v:4951.361-4951.434" + wire $xor$ls180.v:4951$794_Y + attribute \src "ls180.v:4951.205-4951.278" + wire $xor$ls180.v:4951$795_Y + attribute \src "ls180.v:4951.164-4951.279" + wire $xor$ls180.v:4951$796_Y + attribute \src "ls180.v:4952.361-4952.434" + wire $xor$ls180.v:4952$797_Y + attribute \src "ls180.v:4952.205-4952.278" + wire $xor$ls180.v:4952$798_Y + attribute \src "ls180.v:4952.164-4952.279" + wire $xor$ls180.v:4952$799_Y + attribute \src "ls180.v:4953.360-4953.432" + wire $xor$ls180.v:4953$800_Y + attribute \src "ls180.v:4953.205-4953.277" + wire $xor$ls180.v:4953$801_Y + attribute \src "ls180.v:4953.164-4953.278" + wire $xor$ls180.v:4953$802_Y + attribute \src "ls180.v:4954.360-4954.432" + wire $xor$ls180.v:4954$803_Y + attribute \src "ls180.v:4954.205-4954.277" + wire $xor$ls180.v:4954$804_Y + attribute \src "ls180.v:4954.164-4954.278" + wire $xor$ls180.v:4954$805_Y + attribute \src "ls180.v:4955.360-4955.432" + wire $xor$ls180.v:4955$806_Y + attribute \src "ls180.v:4955.205-4955.277" + wire $xor$ls180.v:4955$807_Y + attribute \src "ls180.v:4955.164-4955.278" + wire $xor$ls180.v:4955$808_Y + attribute \src "ls180.v:4956.360-4956.432" + wire $xor$ls180.v:4956$809_Y + attribute \src "ls180.v:4956.205-4956.277" + wire $xor$ls180.v:4956$810_Y + attribute \src "ls180.v:4956.164-4956.278" + wire $xor$ls180.v:4956$811_Y + attribute \src "ls180.v:4957.360-4957.432" + wire $xor$ls180.v:4957$812_Y + attribute \src "ls180.v:4957.205-4957.277" + wire $xor$ls180.v:4957$813_Y + attribute \src "ls180.v:4957.164-4957.278" + wire $xor$ls180.v:4957$814_Y + attribute \src "ls180.v:4958.360-4958.432" + wire $xor$ls180.v:4958$815_Y + attribute \src "ls180.v:4958.205-4958.277" + wire $xor$ls180.v:4958$816_Y + attribute \src "ls180.v:4958.164-4958.278" + wire $xor$ls180.v:4958$817_Y + attribute \src "ls180.v:4959.360-4959.432" + wire $xor$ls180.v:4959$818_Y + attribute \src "ls180.v:4959.205-4959.277" + wire $xor$ls180.v:4959$819_Y + attribute \src "ls180.v:4959.164-4959.278" + wire $xor$ls180.v:4959$820_Y + attribute \src "ls180.v:4960.360-4960.432" + wire $xor$ls180.v:4960$821_Y + attribute \src "ls180.v:4960.205-4960.277" + wire $xor$ls180.v:4960$822_Y + attribute \src "ls180.v:4960.164-4960.278" + wire $xor$ls180.v:4960$823_Y + attribute \src "ls180.v:4961.360-4961.432" + wire $xor$ls180.v:4961$824_Y + attribute \src "ls180.v:4961.205-4961.277" + wire $xor$ls180.v:4961$825_Y + attribute \src "ls180.v:4961.164-4961.278" + wire $xor$ls180.v:4961$826_Y + attribute \src "ls180.v:4962.360-4962.432" + wire $xor$ls180.v:4962$827_Y + attribute \src "ls180.v:4962.205-4962.277" + wire $xor$ls180.v:4962$828_Y + attribute \src "ls180.v:4962.164-4962.278" + wire $xor$ls180.v:4962$829_Y + attribute \src "ls180.v:4983.899-4983.983" + wire $xor$ls180.v:4983$843_Y + attribute \src "ls180.v:4983.634-4983.718" + wire $xor$ls180.v:4983$844_Y + attribute \src "ls180.v:4983.588-4983.719" + wire $xor$ls180.v:4983$845_Y + attribute \src "ls180.v:4983.234-4983.318" + wire $xor$ls180.v:4983$846_Y + attribute \src "ls180.v:4983.187-4983.319" + wire $xor$ls180.v:4983$847_Y + attribute \src "ls180.v:4984.899-4984.983" + wire $xor$ls180.v:4984$848_Y + attribute \src "ls180.v:4984.634-4984.718" + wire $xor$ls180.v:4984$849_Y + attribute \src "ls180.v:4984.588-4984.719" + wire $xor$ls180.v:4984$850_Y + attribute \src "ls180.v:4984.234-4984.318" + wire $xor$ls180.v:4984$851_Y + attribute \src "ls180.v:4984.187-4984.319" + wire $xor$ls180.v:4984$852_Y + attribute \src "ls180.v:4993.899-4993.983" + wire $xor$ls180.v:4993$854_Y + attribute \src "ls180.v:4993.634-4993.718" + wire $xor$ls180.v:4993$855_Y + attribute \src "ls180.v:4993.588-4993.719" + wire $xor$ls180.v:4993$856_Y + attribute \src "ls180.v:4993.234-4993.318" + wire $xor$ls180.v:4993$857_Y + attribute \src "ls180.v:4993.187-4993.319" + wire $xor$ls180.v:4993$858_Y + attribute \src "ls180.v:4994.899-4994.983" + wire $xor$ls180.v:4994$859_Y + attribute \src "ls180.v:4994.634-4994.718" + wire $xor$ls180.v:4994$860_Y + attribute \src "ls180.v:4994.588-4994.719" + wire $xor$ls180.v:4994$861_Y + attribute \src "ls180.v:4994.234-4994.318" + wire $xor$ls180.v:4994$862_Y + attribute \src "ls180.v:4994.187-4994.319" + wire $xor$ls180.v:4994$863_Y + attribute \src "ls180.v:5003.899-5003.983" + wire $xor$ls180.v:5003$865_Y + attribute \src "ls180.v:5003.634-5003.718" + wire $xor$ls180.v:5003$866_Y + attribute \src "ls180.v:5003.588-5003.719" + wire $xor$ls180.v:5003$867_Y + attribute \src "ls180.v:5003.234-5003.318" + wire $xor$ls180.v:5003$868_Y + attribute \src "ls180.v:5003.187-5003.319" + wire $xor$ls180.v:5003$869_Y + attribute \src "ls180.v:5004.899-5004.983" + wire $xor$ls180.v:5004$870_Y + attribute \src "ls180.v:5004.634-5004.718" + wire $xor$ls180.v:5004$871_Y + attribute \src "ls180.v:5004.588-5004.719" + wire $xor$ls180.v:5004$872_Y + attribute \src "ls180.v:5004.234-5004.318" + wire $xor$ls180.v:5004$873_Y + attribute \src "ls180.v:5004.187-5004.319" + wire $xor$ls180.v:5004$874_Y + attribute \src "ls180.v:5013.899-5013.983" + wire $xor$ls180.v:5013$876_Y + attribute \src "ls180.v:5013.634-5013.718" + wire $xor$ls180.v:5013$877_Y + attribute \src "ls180.v:5013.588-5013.719" + wire $xor$ls180.v:5013$878_Y + attribute \src "ls180.v:5013.234-5013.318" + wire $xor$ls180.v:5013$879_Y + attribute \src "ls180.v:5013.187-5013.319" + wire $xor$ls180.v:5013$880_Y + attribute \src "ls180.v:5014.899-5014.983" + wire $xor$ls180.v:5014$881_Y + attribute \src "ls180.v:5014.634-5014.718" + wire $xor$ls180.v:5014$882_Y + attribute \src "ls180.v:5014.588-5014.719" + wire $xor$ls180.v:5014$883_Y + attribute \src "ls180.v:5014.234-5014.318" + wire $xor$ls180.v:5014$884_Y + attribute \src "ls180.v:5014.187-5014.319" + wire $xor$ls180.v:5014$885_Y + attribute \src "ls180.v:5165.879-5165.961" + wire $xor$ls180.v:5165$918_Y + attribute \src "ls180.v:5165.620-5165.702" + wire $xor$ls180.v:5165$919_Y + attribute \src "ls180.v:5165.575-5165.703" + wire $xor$ls180.v:5165$920_Y + attribute \src "ls180.v:5165.229-5165.311" + wire $xor$ls180.v:5165$921_Y + attribute \src "ls180.v:5165.183-5165.312" + wire $xor$ls180.v:5165$922_Y + attribute \src "ls180.v:5166.879-5166.961" + wire $xor$ls180.v:5166$923_Y + attribute \src "ls180.v:5166.620-5166.702" + wire $xor$ls180.v:5166$924_Y + attribute \src "ls180.v:5166.575-5166.703" + wire $xor$ls180.v:5166$925_Y + attribute \src "ls180.v:5166.229-5166.311" + wire $xor$ls180.v:5166$926_Y + attribute \src "ls180.v:5166.183-5166.312" + wire $xor$ls180.v:5166$927_Y + attribute \src "ls180.v:5175.879-5175.961" + wire $xor$ls180.v:5175$929_Y + attribute \src "ls180.v:5175.620-5175.702" + wire $xor$ls180.v:5175$930_Y + attribute \src "ls180.v:5175.575-5175.703" + wire $xor$ls180.v:5175$931_Y + attribute \src "ls180.v:5175.229-5175.311" + wire $xor$ls180.v:5175$932_Y + attribute \src "ls180.v:5175.183-5175.312" + wire $xor$ls180.v:5175$933_Y + attribute \src "ls180.v:5176.879-5176.961" + wire $xor$ls180.v:5176$934_Y + attribute \src "ls180.v:5176.620-5176.702" + wire $xor$ls180.v:5176$935_Y + attribute \src "ls180.v:5176.575-5176.703" + wire $xor$ls180.v:5176$936_Y + attribute \src "ls180.v:5176.229-5176.311" + wire $xor$ls180.v:5176$937_Y + attribute \src "ls180.v:5176.183-5176.312" + wire $xor$ls180.v:5176$938_Y + attribute \src "ls180.v:5185.879-5185.961" + wire $xor$ls180.v:5185$940_Y + attribute \src "ls180.v:5185.620-5185.702" + wire $xor$ls180.v:5185$941_Y + attribute \src "ls180.v:5185.575-5185.703" + wire $xor$ls180.v:5185$942_Y + attribute \src "ls180.v:5185.229-5185.311" + wire $xor$ls180.v:5185$943_Y + attribute \src "ls180.v:5185.183-5185.312" + wire $xor$ls180.v:5185$944_Y + attribute \src "ls180.v:5186.879-5186.961" + wire $xor$ls180.v:5186$945_Y + attribute \src "ls180.v:5186.620-5186.702" + wire $xor$ls180.v:5186$946_Y + attribute \src "ls180.v:5186.575-5186.703" + wire $xor$ls180.v:5186$947_Y + attribute \src "ls180.v:5186.229-5186.311" + wire $xor$ls180.v:5186$948_Y + attribute \src "ls180.v:5186.183-5186.312" + wire $xor$ls180.v:5186$949_Y + attribute \src "ls180.v:5195.879-5195.961" + wire $xor$ls180.v:5195$951_Y + attribute \src "ls180.v:5195.620-5195.702" + wire $xor$ls180.v:5195$952_Y + attribute \src "ls180.v:5195.575-5195.703" + wire $xor$ls180.v:5195$953_Y + attribute \src "ls180.v:5195.229-5195.311" + wire $xor$ls180.v:5195$954_Y + attribute \src "ls180.v:5195.183-5195.312" + wire $xor$ls180.v:5195$955_Y + attribute \src "ls180.v:5196.879-5196.961" + wire $xor$ls180.v:5196$956_Y + attribute \src "ls180.v:5196.620-5196.702" + wire $xor$ls180.v:5196$957_Y + attribute \src "ls180.v:5196.575-5196.703" + wire $xor$ls180.v:5196$958_Y + attribute \src "ls180.v:5196.229-5196.311" + wire $xor$ls180.v:5196$959_Y + attribute \src "ls180.v:5196.183-5196.312" + wire $xor$ls180.v:5196$960_Y + attribute \src "ls180.v:1747.11-1747.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1708.11-1708.37" + attribute \src "ls180.v:1746.11-1746.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1711.11-1711.42" + attribute \src "ls180.v:1749.11-1749.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1710.11-1710.37" + attribute \src "ls180.v:1748.11-1748.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1713.11-1713.42" + attribute \src "ls180.v:1751.11-1751.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1712.11-1712.37" + attribute \src "ls180.v:1750.11-1750.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1715.11-1715.42" + attribute \src "ls180.v:1753.11-1753.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1714.11-1714.37" + attribute \src "ls180.v:1752.11-1752.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2547.5-2547.34" + attribute \src "ls180.v:2598.5-2598.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2548.12-2548.41" + attribute \src "ls180.v:2599.12-2599.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2560.5-2560.35" + attribute \src "ls180.v:2611.5-2611.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2561.5-2561.35" + attribute \src "ls180.v:2612.5-2612.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2565.12-2565.42" + attribute \src "ls180.v:2616.12-2616.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2566.5-2566.35" + attribute \src "ls180.v:2617.5-2617.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2567.5-2567.35" + attribute \src "ls180.v:2618.5-2618.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2568.12-2568.42" + attribute \src "ls180.v:2619.12-2619.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2569.5-2569.35" + attribute \src "ls180.v:2620.5-2620.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2570.5-2570.35" + attribute \src "ls180.v:2621.5-2621.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2571.12-2571.42" + attribute \src "ls180.v:2622.12-2622.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2572.5-2572.35" + attribute \src "ls180.v:2623.5-2623.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2549.11-2549.40" + attribute \src "ls180.v:2600.11-2600.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2573.5-2573.35" + attribute \src "ls180.v:2624.5-2624.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2574.12-2574.42" + attribute \src "ls180.v:2625.12-2625.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2575.5-2575.35" + attribute \src "ls180.v:2626.5-2626.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2576.5-2576.35" + attribute \src "ls180.v:2627.5-2627.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2577.12-2577.42" + attribute \src "ls180.v:2628.12-2628.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2578.12-2578.42" + attribute \src "ls180.v:2629.12-2629.42" wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2579.11-2579.41" + attribute \src "ls180.v:2630.11-2630.41" wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2580.5-2580.35" + attribute \src "ls180.v:2631.5-2631.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2581.5-2581.35" + attribute \src "ls180.v:2632.5-2632.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2582.5-2582.35" + attribute \src "ls180.v:2633.5-2633.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2550.5-2550.34" + attribute \src "ls180.v:2601.5-2601.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2583.11-2583.41" + attribute \src "ls180.v:2634.11-2634.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2584.11-2584.41" + attribute \src "ls180.v:2635.11-2635.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2551.5-2551.34" + attribute \src "ls180.v:2602.5-2602.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2552.5-2552.34" + attribute \src "ls180.v:2603.5-2603.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2556.5-2556.34" + attribute \src "ls180.v:2607.5-2607.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2557.12-2557.41" + attribute \src "ls180.v:2608.12-2608.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2558.11-2558.40" + attribute \src "ls180.v:2609.11-2609.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2559.5-2559.34" + attribute \src "ls180.v:2610.5-2610.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2553.5-2553.32" + attribute \src "ls180.v:2604.5-2604.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2554.5-2554.32" + attribute \src "ls180.v:2605.5-2605.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2555.5-2555.32" + attribute \src "ls180.v:2606.5-2606.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2562.5-2562.32" + attribute \src "ls180.v:2613.5-2613.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2563.5-2563.32" + attribute \src "ls180.v:2614.5-2614.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2564.5-2564.32" + attribute \src "ls180.v:2615.5-2615.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1695.5-1695.34" + attribute \src "ls180.v:1733.5-1733.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1694.5-1694.29" + attribute \src "ls180.v:1732.5-1732.29" wire \builder_converter0_state - attribute \src "ls180.v:1699.5-1699.34" + attribute \src "ls180.v:1737.5-1737.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1698.5-1698.29" + attribute \src "ls180.v:1736.5-1736.29" wire \builder_converter1_state - attribute \src "ls180.v:1703.5-1703.34" + attribute \src "ls180.v:1741.5-1741.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1702.5-1702.29" + attribute \src "ls180.v:1740.5-1740.29" wire \builder_converter2_state - attribute \src "ls180.v:1740.5-1740.33" + attribute \src "ls180.v:1778.5-1778.33" wire \builder_converter_next_state - attribute \src "ls180.v:1739.5-1739.28" + attribute \src "ls180.v:1777.5-1777.28" wire \builder_converter_state - attribute \src "ls180.v:1860.12-1860.25" + attribute \src "ls180.v:1898.12-1898.25" wire width 20 \builder_count - attribute \src "ls180.v:2535.13-2535.41" + attribute \src "ls180.v:2586.13-2586.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2538.12-2538.42" + attribute \src "ls180.v:2589.12-2589.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2537.12-2537.42" + attribute \src "ls180.v:2588.12-2588.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2536.6-2536.33" + attribute \src "ls180.v:2587.6-2587.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:1898.12-1898.42" + attribute \src "ls180.v:1936.12-1936.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1897.6-1897.37" + attribute \src "ls180.v:1935.6-1935.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1900.12-1900.42" + attribute \src "ls180.v:1938.12-1938.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1899.6-1899.37" + attribute \src "ls180.v:1937.6-1937.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1894.12-1894.42" + attribute \src "ls180.v:1932.12-1932.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1893.6-1893.37" + attribute \src "ls180.v:1931.6-1931.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1896.12-1896.42" + attribute \src "ls180.v:1934.12-1934.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1895.6-1895.37" + attribute \src "ls180.v:1933.6-1933.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1890.12-1890.42" + attribute \src "ls180.v:1928.12-1928.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1889.6-1889.37" + attribute \src "ls180.v:1927.6-1927.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1892.12-1892.42" + attribute \src "ls180.v:1930.12-1930.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1891.6-1891.37" + attribute \src "ls180.v:1929.6-1929.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1886.12-1886.42" + attribute \src "ls180.v:1924.12-1924.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1885.6-1885.37" + attribute \src "ls180.v:1923.6-1923.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1888.12-1888.42" + attribute \src "ls180.v:1926.12-1926.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1887.6-1887.37" + attribute \src "ls180.v:1925.6-1925.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1866.6-1866.31" + attribute \src "ls180.v:1904.6-1904.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1865.6-1865.32" + attribute \src "ls180.v:1903.6-1903.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1868.6-1868.31" + attribute \src "ls180.v:1906.6-1906.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1867.6-1867.32" + attribute \src "ls180.v:1905.6-1905.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1882.12-1882.39" + attribute \src "ls180.v:1920.12-1920.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1881.6-1881.34" + attribute \src "ls180.v:1919.6-1919.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1884.12-1884.39" + attribute \src "ls180.v:1922.12-1922.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1883.6-1883.34" + attribute \src "ls180.v:1921.6-1921.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1878.12-1878.39" + attribute \src "ls180.v:1916.12-1916.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1877.6-1877.34" + attribute \src "ls180.v:1915.6-1915.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1880.12-1880.39" + attribute \src "ls180.v:1918.12-1918.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1879.6-1879.34" + attribute \src "ls180.v:1917.6-1917.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1874.12-1874.39" + attribute \src "ls180.v:1912.12-1912.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1873.6-1873.34" + attribute \src "ls180.v:1911.6-1911.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1876.12-1876.39" + attribute \src "ls180.v:1914.12-1914.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1875.6-1875.34" + attribute \src "ls180.v:1913.6-1913.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1870.12-1870.39" + attribute \src "ls180.v:1908.12-1908.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1869.6-1869.34" + attribute \src "ls180.v:1907.6-1907.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1872.12-1872.39" + attribute \src "ls180.v:1910.12-1910.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1871.6-1871.34" + attribute \src "ls180.v:1909.6-1909.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1901.6-1901.26" + attribute \src "ls180.v:1939.6-1939.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2420.12-2420.44" - wire width 8 \builder_csrbank10_clk_divider0_r - attribute \src "ls180.v:2419.6-2419.39" - wire \builder_csrbank10_clk_divider0_re - attribute \src "ls180.v:2422.12-2422.44" - wire width 8 \builder_csrbank10_clk_divider0_w - attribute \src "ls180.v:2421.6-2421.39" - wire \builder_csrbank10_clk_divider0_we - attribute \src "ls180.v:2416.12-2416.44" - wire width 8 \builder_csrbank10_clk_divider1_r - attribute \src "ls180.v:2415.6-2415.39" - wire \builder_csrbank10_clk_divider1_re - attribute \src "ls180.v:2418.12-2418.44" - wire width 8 \builder_csrbank10_clk_divider1_w - attribute \src "ls180.v:2417.6-2417.39" - wire \builder_csrbank10_clk_divider1_we - attribute \src "ls180.v:2392.12-2392.40" + attribute \src "ls180.v:2410.12-2410.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2391.6-2391.35" + attribute \src "ls180.v:2409.6-2409.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2394.12-2394.40" + attribute \src "ls180.v:2412.12-2412.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2393.6-2393.35" + attribute \src "ls180.v:2411.6-2411.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2388.12-2388.40" + attribute \src "ls180.v:2406.12-2406.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2387.6-2387.35" + attribute \src "ls180.v:2405.6-2405.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2390.12-2390.40" + attribute \src "ls180.v:2408.12-2408.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2389.6-2389.35" + attribute \src "ls180.v:2407.6-2407.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2408.6-2408.29" + attribute \src "ls180.v:2426.6-2426.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2407.6-2407.30" + attribute \src "ls180.v:2425.6-2425.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2410.6-2410.29" + attribute \src "ls180.v:2428.6-2428.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2409.6-2409.30" + attribute \src "ls180.v:2427.6-2427.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2412.6-2412.35" + attribute \src "ls180.v:2430.6-2430.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2411.6-2411.36" + attribute \src "ls180.v:2429.6-2429.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2414.6-2414.35" + attribute \src "ls180.v:2432.6-2432.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2413.6-2413.36" + attribute \src "ls180.v:2431.6-2431.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2404.12-2404.36" + attribute \src "ls180.v:2422.12-2422.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2403.6-2403.31" + attribute \src "ls180.v:2421.6-2421.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2406.12-2406.36" + attribute \src "ls180.v:2424.12-2424.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2405.6-2405.31" + attribute \src "ls180.v:2423.6-2423.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2400.12-2400.37" + attribute \src "ls180.v:2418.12-2418.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2399.6-2399.32" + attribute \src "ls180.v:2417.6-2417.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2402.12-2402.37" + attribute \src "ls180.v:2420.12-2420.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2401.6-2401.32" + attribute \src "ls180.v:2419.6-2419.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2423.6-2423.27" + attribute \src "ls180.v:2433.6-2433.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2396.6-2396.32" + attribute \src "ls180.v:2414.6-2414.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2395.6-2395.33" + attribute \src "ls180.v:2413.6-2413.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2398.6-2398.32" + attribute \src "ls180.v:2416.6-2416.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2397.6-2397.33" + attribute \src "ls180.v:2415.6-2415.33" wire \builder_csrbank10_status_we + attribute \src "ls180.v:2471.12-2471.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2470.6-2470.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2473.12-2473.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2472.6-2472.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2467.12-2467.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2466.6-2466.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2469.12-2469.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2468.6-2468.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2443.12-2443.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2442.6-2442.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2445.12-2445.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2444.6-2444.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2439.12-2439.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2438.6-2438.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2441.12-2441.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2440.6-2440.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2459.6-2459.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2458.6-2458.30" + wire \builder_csrbank11_cs0_re attribute \src "ls180.v:2461.6-2461.29" - wire \builder_csrbank11_en0_r + wire \builder_csrbank11_cs0_w attribute \src "ls180.v:2460.6-2460.30" - wire \builder_csrbank11_en0_re - attribute \src "ls180.v:2463.6-2463.29" - wire \builder_csrbank11_en0_w - attribute \src "ls180.v:2462.6-2462.30" - wire \builder_csrbank11_en0_we - attribute \src "ls180.v:2485.6-2485.36" - wire \builder_csrbank11_ev_enable0_r - attribute \src "ls180.v:2484.6-2484.37" - wire \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:2487.6-2487.36" - wire \builder_csrbank11_ev_enable0_w - attribute \src "ls180.v:2486.6-2486.37" - wire \builder_csrbank11_ev_enable0_we - attribute \src "ls180.v:2441.12-2441.37" - wire width 8 \builder_csrbank11_load0_r - attribute \src "ls180.v:2440.6-2440.32" - wire \builder_csrbank11_load0_re - attribute \src "ls180.v:2443.12-2443.37" - wire width 8 \builder_csrbank11_load0_w - attribute \src "ls180.v:2442.6-2442.32" - wire \builder_csrbank11_load0_we - attribute \src "ls180.v:2437.12-2437.37" - wire width 8 \builder_csrbank11_load1_r - attribute \src "ls180.v:2436.6-2436.32" - wire \builder_csrbank11_load1_re - attribute \src "ls180.v:2439.12-2439.37" - wire width 8 \builder_csrbank11_load1_w - attribute \src "ls180.v:2438.6-2438.32" - wire \builder_csrbank11_load1_we - attribute \src "ls180.v:2433.12-2433.37" - wire width 8 \builder_csrbank11_load2_r - attribute \src "ls180.v:2432.6-2432.32" - wire \builder_csrbank11_load2_re - attribute \src "ls180.v:2435.12-2435.37" - wire width 8 \builder_csrbank11_load2_w - attribute \src "ls180.v:2434.6-2434.32" - wire \builder_csrbank11_load2_we - attribute \src "ls180.v:2429.12-2429.37" - wire width 8 \builder_csrbank11_load3_r - attribute \src "ls180.v:2428.6-2428.32" - wire \builder_csrbank11_load3_re - attribute \src "ls180.v:2431.12-2431.37" - wire width 8 \builder_csrbank11_load3_w - attribute \src "ls180.v:2430.6-2430.32" - wire \builder_csrbank11_load3_we - attribute \src "ls180.v:2457.12-2457.39" - wire width 8 \builder_csrbank11_reload0_r - attribute \src "ls180.v:2456.6-2456.34" - wire \builder_csrbank11_reload0_re - attribute \src "ls180.v:2459.12-2459.39" - wire width 8 \builder_csrbank11_reload0_w - attribute \src "ls180.v:2458.6-2458.34" - wire \builder_csrbank11_reload0_we - attribute \src "ls180.v:2453.12-2453.39" - wire width 8 \builder_csrbank11_reload1_r - attribute \src "ls180.v:2452.6-2452.34" - wire \builder_csrbank11_reload1_re - attribute \src "ls180.v:2455.12-2455.39" - wire width 8 \builder_csrbank11_reload1_w - attribute \src "ls180.v:2454.6-2454.34" - wire \builder_csrbank11_reload1_we - attribute \src "ls180.v:2449.12-2449.39" - wire width 8 \builder_csrbank11_reload2_r - attribute \src "ls180.v:2448.6-2448.34" - wire \builder_csrbank11_reload2_re - attribute \src "ls180.v:2451.12-2451.39" - wire width 8 \builder_csrbank11_reload2_w - attribute \src "ls180.v:2450.6-2450.34" - wire \builder_csrbank11_reload2_we - attribute \src "ls180.v:2445.12-2445.39" - wire width 8 \builder_csrbank11_reload3_r - attribute \src "ls180.v:2444.6-2444.34" - wire \builder_csrbank11_reload3_re - attribute \src "ls180.v:2447.12-2447.39" - wire width 8 \builder_csrbank11_reload3_w - attribute \src "ls180.v:2446.6-2446.34" - wire \builder_csrbank11_reload3_we - attribute \src "ls180.v:2488.6-2488.27" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2463.6-2463.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2462.6-2462.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2465.6-2465.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2464.6-2464.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2455.12-2455.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2454.6-2454.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2457.12-2457.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2456.6-2456.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2451.12-2451.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2450.6-2450.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2453.12-2453.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2452.6-2452.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2474.6-2474.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2465.6-2465.39" - wire \builder_csrbank11_update_value0_r - attribute \src "ls180.v:2464.6-2464.40" - wire \builder_csrbank11_update_value0_re - attribute \src "ls180.v:2467.6-2467.39" - wire \builder_csrbank11_update_value0_w - attribute \src "ls180.v:2466.6-2466.40" - wire \builder_csrbank11_update_value0_we - attribute \src "ls180.v:2481.12-2481.38" - wire width 8 \builder_csrbank11_value0_r - attribute \src "ls180.v:2480.6-2480.33" - wire \builder_csrbank11_value0_re - attribute \src "ls180.v:2483.12-2483.38" - wire width 8 \builder_csrbank11_value0_w - attribute \src "ls180.v:2482.6-2482.33" - wire \builder_csrbank11_value0_we - attribute \src "ls180.v:2477.12-2477.38" - wire width 8 \builder_csrbank11_value1_r - attribute \src "ls180.v:2476.6-2476.33" - wire \builder_csrbank11_value1_re - attribute \src "ls180.v:2479.12-2479.38" - wire width 8 \builder_csrbank11_value1_w - attribute \src "ls180.v:2478.6-2478.33" - wire \builder_csrbank11_value1_we - attribute \src "ls180.v:2473.12-2473.38" - wire width 8 \builder_csrbank11_value2_r - attribute \src "ls180.v:2472.6-2472.33" - wire \builder_csrbank11_value2_re - attribute \src "ls180.v:2475.12-2475.38" - wire width 8 \builder_csrbank11_value2_w - attribute \src "ls180.v:2474.6-2474.33" - wire \builder_csrbank11_value2_we - attribute \src "ls180.v:2469.12-2469.38" - wire width 8 \builder_csrbank11_value3_r - attribute \src "ls180.v:2468.6-2468.33" - wire \builder_csrbank11_value3_re - attribute \src "ls180.v:2471.12-2471.38" - wire width 8 \builder_csrbank11_value3_w - attribute \src "ls180.v:2470.6-2470.33" - wire \builder_csrbank11_value3_we - attribute \src "ls180.v:2502.12-2502.42" - wire width 2 \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2501.6-2501.37" + attribute \src "ls180.v:2447.6-2447.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2446.6-2446.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2449.6-2449.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2448.6-2448.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2512.6-2512.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2511.6-2511.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2514.6-2514.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2513.6-2513.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2536.6-2536.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2535.6-2535.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2504.12-2504.42" - wire width 2 \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2503.6-2503.37" + attribute \src "ls180.v:2538.6-2538.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2537.6-2537.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2498.6-2498.33" - wire \builder_csrbank12_rxempty_r - attribute \src "ls180.v:2497.6-2497.34" - wire \builder_csrbank12_rxempty_re - attribute \src "ls180.v:2500.6-2500.33" - wire \builder_csrbank12_rxempty_w + attribute \src "ls180.v:2492.12-2492.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2491.6-2491.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2494.12-2494.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2493.6-2493.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2488.12-2488.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2487.6-2487.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2490.12-2490.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2489.6-2489.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2484.12-2484.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2483.6-2483.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2486.12-2486.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2485.6-2485.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2480.12-2480.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2479.6-2479.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2482.12-2482.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2481.6-2481.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2508.12-2508.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2507.6-2507.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2510.12-2510.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2509.6-2509.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2504.12-2504.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2503.6-2503.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2506.12-2506.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2505.6-2505.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2500.12-2500.39" + wire width 8 \builder_csrbank12_reload2_r attribute \src "ls180.v:2499.6-2499.34" - wire \builder_csrbank12_rxempty_we - attribute \src "ls180.v:2510.6-2510.32" - wire \builder_csrbank12_rxfull_r - attribute \src "ls180.v:2509.6-2509.33" - wire \builder_csrbank12_rxfull_re - attribute \src "ls180.v:2512.6-2512.32" - wire \builder_csrbank12_rxfull_w - attribute \src "ls180.v:2511.6-2511.33" - wire \builder_csrbank12_rxfull_we - attribute \src "ls180.v:2513.6-2513.27" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2502.12-2502.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2501.6-2501.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2496.12-2496.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2495.6-2495.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2498.12-2498.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2497.6-2497.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2539.6-2539.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2506.6-2506.33" - wire \builder_csrbank12_txempty_r - attribute \src "ls180.v:2505.6-2505.34" - wire \builder_csrbank12_txempty_re - attribute \src "ls180.v:2508.6-2508.33" - wire \builder_csrbank12_txempty_w - attribute \src "ls180.v:2507.6-2507.34" - wire \builder_csrbank12_txempty_we - attribute \src "ls180.v:2494.6-2494.32" - wire \builder_csrbank12_txfull_r - attribute \src "ls180.v:2493.6-2493.33" - wire \builder_csrbank12_txfull_re - attribute \src "ls180.v:2496.6-2496.32" - wire \builder_csrbank12_txfull_w - attribute \src "ls180.v:2495.6-2495.33" - wire \builder_csrbank12_txfull_we - attribute \src "ls180.v:2534.6-2534.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2531.12-2531.44" - wire width 8 \builder_csrbank13_tuning_word0_r - attribute \src "ls180.v:2530.6-2530.39" - wire \builder_csrbank13_tuning_word0_re - attribute \src "ls180.v:2533.12-2533.44" - wire width 8 \builder_csrbank13_tuning_word0_w - attribute \src "ls180.v:2532.6-2532.39" - wire \builder_csrbank13_tuning_word0_we - attribute \src "ls180.v:2527.12-2527.44" - wire width 8 \builder_csrbank13_tuning_word1_r - attribute \src "ls180.v:2526.6-2526.39" - wire \builder_csrbank13_tuning_word1_re - attribute \src "ls180.v:2529.12-2529.44" - wire width 8 \builder_csrbank13_tuning_word1_w - attribute \src "ls180.v:2528.6-2528.39" - wire \builder_csrbank13_tuning_word1_we - attribute \src "ls180.v:2523.12-2523.44" - wire width 8 \builder_csrbank13_tuning_word2_r - attribute \src "ls180.v:2522.6-2522.39" - wire \builder_csrbank13_tuning_word2_re - attribute \src "ls180.v:2525.12-2525.44" - wire width 8 \builder_csrbank13_tuning_word2_w - attribute \src "ls180.v:2524.6-2524.39" - wire \builder_csrbank13_tuning_word2_we - attribute \src "ls180.v:2519.12-2519.44" - wire width 8 \builder_csrbank13_tuning_word3_r + attribute \src "ls180.v:2516.6-2516.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2515.6-2515.40" + wire \builder_csrbank12_update_value0_re attribute \src "ls180.v:2518.6-2518.39" - wire \builder_csrbank13_tuning_word3_re - attribute \src "ls180.v:2521.12-2521.44" - wire width 8 \builder_csrbank13_tuning_word3_w - attribute \src "ls180.v:2520.6-2520.39" - wire \builder_csrbank13_tuning_word3_we - attribute \src "ls180.v:1919.12-1919.34" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2517.6-2517.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2532.12-2532.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2531.6-2531.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2534.12-2534.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2533.6-2533.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2528.12-2528.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2527.6-2527.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2530.12-2530.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2529.6-2529.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2524.12-2524.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2523.6-2523.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2526.12-2526.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2525.6-2525.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2520.12-2520.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2519.6-2519.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2522.12-2522.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2521.6-2521.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2553.12-2553.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2552.6-2552.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2555.12-2555.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2554.6-2554.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2549.6-2549.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2548.6-2548.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2551.6-2551.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2550.6-2550.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2561.6-2561.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2560.6-2560.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2563.6-2563.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2562.6-2562.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2564.6-2564.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2557.6-2557.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2556.6-2556.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2559.6-2559.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2558.6-2558.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2545.6-2545.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2544.6-2544.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2547.6-2547.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2546.6-2546.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2585.6-2585.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2582.12-2582.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2581.6-2581.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2584.12-2584.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2583.6-2583.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2578.12-2578.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2577.6-2577.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2580.12-2580.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2579.6-2579.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2574.12-2574.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2573.6-2573.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2576.12-2576.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2575.6-2575.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2570.12-2570.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2569.6-2569.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2572.12-2572.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2571.6-2571.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:1957.12-1957.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1918.6-1918.29" + attribute \src "ls180.v:1956.6-1956.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1921.12-1921.34" + attribute \src "ls180.v:1959.12-1959.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1920.6-1920.29" + attribute \src "ls180.v:1958.6-1958.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1915.12-1915.34" + attribute \src "ls180.v:1953.12-1953.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1914.6-1914.29" + attribute \src "ls180.v:1952.6-1952.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1917.12-1917.34" + attribute \src "ls180.v:1955.12-1955.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1916.6-1916.29" + attribute \src "ls180.v:1954.6-1954.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1911.12-1911.34" + attribute \src "ls180.v:1949.12-1949.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1910.6-1910.29" + attribute \src "ls180.v:1948.6-1948.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1913.12-1913.34" + attribute \src "ls180.v:1951.12-1951.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1912.6-1912.29" + attribute \src "ls180.v:1950.6-1950.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1907.12-1907.34" + attribute \src "ls180.v:1945.12-1945.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1906.6-1906.29" + attribute \src "ls180.v:1944.6-1944.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1909.12-1909.34" + attribute \src "ls180.v:1947.12-1947.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1908.6-1908.29" + attribute \src "ls180.v:1946.6-1946.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1927.12-1927.35" + attribute \src "ls180.v:1965.12-1965.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1926.6-1926.30" + attribute \src "ls180.v:1964.6-1964.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1929.12-1929.35" + attribute \src "ls180.v:1967.12-1967.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1928.6-1928.30" + attribute \src "ls180.v:1966.6-1966.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1923.12-1923.35" + attribute \src "ls180.v:1961.12-1961.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1922.6-1922.30" + attribute \src "ls180.v:1960.6-1960.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1925.12-1925.35" + attribute \src "ls180.v:1963.12-1963.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1924.6-1924.30" + attribute \src "ls180.v:1962.6-1962.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1930.6-1930.26" + attribute \src "ls180.v:1968.6-1968.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:1936.6-1936.32" - wire \builder_csrbank2_enable0_r - attribute \src "ls180.v:1935.6-1935.33" - wire \builder_csrbank2_enable0_re - attribute \src "ls180.v:1938.6-1938.32" - wire \builder_csrbank2_enable0_w - attribute \src "ls180.v:1937.6-1937.33" - wire \builder_csrbank2_enable0_we - attribute \src "ls180.v:1968.12-1968.38" - wire width 8 \builder_csrbank2_period0_r - attribute \src "ls180.v:1967.6-1967.33" - wire \builder_csrbank2_period0_re - attribute \src "ls180.v:1970.12-1970.38" - wire width 8 \builder_csrbank2_period0_w - attribute \src "ls180.v:1969.6-1969.33" - wire \builder_csrbank2_period0_we - attribute \src "ls180.v:1964.12-1964.38" - wire width 8 \builder_csrbank2_period1_r - attribute \src "ls180.v:1963.6-1963.33" - wire \builder_csrbank2_period1_re - attribute \src "ls180.v:1966.12-1966.38" - wire width 8 \builder_csrbank2_period1_w - attribute \src "ls180.v:1965.6-1965.33" - wire \builder_csrbank2_period1_we - attribute \src "ls180.v:1960.12-1960.38" - wire width 8 \builder_csrbank2_period2_r - attribute \src "ls180.v:1959.6-1959.33" - wire \builder_csrbank2_period2_re - attribute \src "ls180.v:1962.12-1962.38" - wire width 8 \builder_csrbank2_period2_w - attribute \src "ls180.v:1961.6-1961.33" - wire \builder_csrbank2_period2_we - attribute \src "ls180.v:1956.12-1956.38" - wire width 8 \builder_csrbank2_period3_r - attribute \src "ls180.v:1955.6-1955.33" - wire \builder_csrbank2_period3_re - attribute \src "ls180.v:1958.12-1958.38" - wire width 8 \builder_csrbank2_period3_w - attribute \src "ls180.v:1957.6-1957.33" - wire \builder_csrbank2_period3_we - attribute \src "ls180.v:1971.6-1971.26" + attribute \src "ls180.v:1978.6-1978.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:1977.6-1977.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:1980.6-1980.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:1979.6-1979.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:1981.6-1981.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:1952.12-1952.37" - wire width 8 \builder_csrbank2_width0_r - attribute \src "ls180.v:1951.6-1951.32" - wire \builder_csrbank2_width0_re - attribute \src "ls180.v:1954.12-1954.37" - wire width 8 \builder_csrbank2_width0_w - attribute \src "ls180.v:1953.6-1953.32" - wire \builder_csrbank2_width0_we - attribute \src "ls180.v:1948.12-1948.37" - wire width 8 \builder_csrbank2_width1_r - attribute \src "ls180.v:1947.6-1947.32" - wire \builder_csrbank2_width1_re - attribute \src "ls180.v:1950.12-1950.37" - wire width 8 \builder_csrbank2_width1_w - attribute \src "ls180.v:1949.6-1949.32" - wire \builder_csrbank2_width1_we - attribute \src "ls180.v:1944.12-1944.37" - wire width 8 \builder_csrbank2_width2_r - attribute \src "ls180.v:1943.6-1943.32" - wire \builder_csrbank2_width2_re - attribute \src "ls180.v:1946.12-1946.37" - wire width 8 \builder_csrbank2_width2_w - attribute \src "ls180.v:1945.6-1945.32" - wire \builder_csrbank2_width2_we - attribute \src "ls180.v:1940.12-1940.37" - wire width 8 \builder_csrbank2_width3_r - attribute \src "ls180.v:1939.6-1939.32" - wire \builder_csrbank2_width3_re - attribute \src "ls180.v:1942.12-1942.37" - wire width 8 \builder_csrbank2_width3_w - attribute \src "ls180.v:1941.6-1941.32" - wire \builder_csrbank2_width3_we - attribute \src "ls180.v:1977.6-1977.32" + attribute \src "ls180.v:1974.12-1974.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:1973.6-1973.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:1976.12-1976.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:1975.6-1975.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:1987.6-1987.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:1976.6-1976.33" + attribute \src "ls180.v:1986.6-1986.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:1979.6-1979.32" + attribute \src "ls180.v:1989.6-1989.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:1978.6-1978.33" + attribute \src "ls180.v:1988.6-1988.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2009.12-2009.38" + attribute \src "ls180.v:2019.12-2019.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2008.6-2008.33" + attribute \src "ls180.v:2018.6-2018.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2011.12-2011.38" + attribute \src "ls180.v:2021.12-2021.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2010.6-2010.33" + attribute \src "ls180.v:2020.6-2020.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2005.12-2005.38" + attribute \src "ls180.v:2015.12-2015.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2004.6-2004.33" + attribute \src "ls180.v:2014.6-2014.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2007.12-2007.38" + attribute \src "ls180.v:2017.12-2017.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2006.6-2006.33" + attribute \src "ls180.v:2016.6-2016.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2001.12-2001.38" + attribute \src "ls180.v:2011.12-2011.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2000.6-2000.33" + attribute \src "ls180.v:2010.6-2010.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2003.12-2003.38" + attribute \src "ls180.v:2013.12-2013.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2002.6-2002.33" + attribute \src "ls180.v:2012.6-2012.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:1997.12-1997.38" + attribute \src "ls180.v:2007.12-2007.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:1996.6-1996.33" + attribute \src "ls180.v:2006.6-2006.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:1999.12-1999.38" + attribute \src "ls180.v:2009.12-2009.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:1998.6-1998.33" + attribute \src "ls180.v:2008.6-2008.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2012.6-2012.26" + attribute \src "ls180.v:2022.6-2022.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:1993.12-1993.37" + attribute \src "ls180.v:2003.12-2003.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:1992.6-1992.32" + attribute \src "ls180.v:2002.6-2002.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:1995.12-1995.37" + attribute \src "ls180.v:2005.12-2005.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:1994.6-1994.32" + attribute \src "ls180.v:2004.6-2004.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:1989.12-1989.37" + attribute \src "ls180.v:1999.12-1999.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:1988.6-1988.32" + attribute \src "ls180.v:1998.6-1998.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:1991.12-1991.37" + attribute \src "ls180.v:2001.12-2001.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:1990.6-1990.32" + attribute \src "ls180.v:2000.6-2000.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:1985.12-1985.37" + attribute \src "ls180.v:1995.12-1995.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:1984.6-1984.32" + attribute \src "ls180.v:1994.6-1994.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:1987.12-1987.37" + attribute \src "ls180.v:1997.12-1997.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:1986.6-1986.32" + attribute \src "ls180.v:1996.6-1996.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:1981.12-1981.37" + attribute \src "ls180.v:1991.12-1991.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:1980.6-1980.32" + attribute \src "ls180.v:1990.6-1990.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:1983.12-1983.37" + attribute \src "ls180.v:1993.12-1993.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:1982.6-1982.32" + attribute \src "ls180.v:1992.6-1992.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2046.12-2046.40" - wire width 8 \builder_csrbank4_dma_base0_r - attribute \src "ls180.v:2045.6-2045.35" - wire \builder_csrbank4_dma_base0_re - attribute \src "ls180.v:2048.12-2048.40" - wire width 8 \builder_csrbank4_dma_base0_w - attribute \src "ls180.v:2047.6-2047.35" - wire \builder_csrbank4_dma_base0_we - attribute \src "ls180.v:2042.12-2042.40" - wire width 8 \builder_csrbank4_dma_base1_r - attribute \src "ls180.v:2041.6-2041.35" - wire \builder_csrbank4_dma_base1_re - attribute \src "ls180.v:2044.12-2044.40" - wire width 8 \builder_csrbank4_dma_base1_w - attribute \src "ls180.v:2043.6-2043.35" - wire \builder_csrbank4_dma_base1_we - attribute \src "ls180.v:2038.12-2038.40" - wire width 8 \builder_csrbank4_dma_base2_r - attribute \src "ls180.v:2037.6-2037.35" - wire \builder_csrbank4_dma_base2_re - attribute \src "ls180.v:2040.12-2040.40" - wire width 8 \builder_csrbank4_dma_base2_w - attribute \src "ls180.v:2039.6-2039.35" - wire \builder_csrbank4_dma_base2_we - attribute \src "ls180.v:2034.12-2034.40" - wire width 8 \builder_csrbank4_dma_base3_r - attribute \src "ls180.v:2033.6-2033.35" - wire \builder_csrbank4_dma_base3_re - attribute \src "ls180.v:2036.12-2036.40" - wire width 8 \builder_csrbank4_dma_base3_w - attribute \src "ls180.v:2035.6-2035.35" - wire \builder_csrbank4_dma_base3_we - attribute \src "ls180.v:2030.12-2030.40" - wire width 8 \builder_csrbank4_dma_base4_r - attribute \src "ls180.v:2029.6-2029.35" - wire \builder_csrbank4_dma_base4_re - attribute \src "ls180.v:2032.12-2032.40" - wire width 8 \builder_csrbank4_dma_base4_w - attribute \src "ls180.v:2031.6-2031.35" - wire \builder_csrbank4_dma_base4_we - attribute \src "ls180.v:2026.12-2026.40" - wire width 8 \builder_csrbank4_dma_base5_r - attribute \src "ls180.v:2025.6-2025.35" - wire \builder_csrbank4_dma_base5_re - attribute \src "ls180.v:2028.12-2028.40" - wire width 8 \builder_csrbank4_dma_base5_w - attribute \src "ls180.v:2027.6-2027.35" - wire \builder_csrbank4_dma_base5_we - attribute \src "ls180.v:2022.12-2022.40" - wire width 8 \builder_csrbank4_dma_base6_r - attribute \src "ls180.v:2021.6-2021.35" - wire \builder_csrbank4_dma_base6_re - attribute \src "ls180.v:2024.12-2024.40" - wire width 8 \builder_csrbank4_dma_base6_w - attribute \src "ls180.v:2023.6-2023.35" - wire \builder_csrbank4_dma_base6_we - attribute \src "ls180.v:2018.12-2018.40" - wire width 8 \builder_csrbank4_dma_base7_r - attribute \src "ls180.v:2017.6-2017.35" - wire \builder_csrbank4_dma_base7_re - attribute \src "ls180.v:2020.12-2020.40" - wire width 8 \builder_csrbank4_dma_base7_w - attribute \src "ls180.v:2019.6-2019.35" - wire \builder_csrbank4_dma_base7_we - attribute \src "ls180.v:2070.6-2070.33" - wire \builder_csrbank4_dma_done_r - attribute \src "ls180.v:2069.6-2069.34" - wire \builder_csrbank4_dma_done_re - attribute \src "ls180.v:2072.6-2072.33" - wire \builder_csrbank4_dma_done_w - attribute \src "ls180.v:2071.6-2071.34" - wire \builder_csrbank4_dma_done_we - attribute \src "ls180.v:2066.6-2066.36" - wire \builder_csrbank4_dma_enable0_r - attribute \src "ls180.v:2065.6-2065.37" - wire \builder_csrbank4_dma_enable0_re - attribute \src "ls180.v:2068.6-2068.36" - wire \builder_csrbank4_dma_enable0_w - attribute \src "ls180.v:2067.6-2067.37" - wire \builder_csrbank4_dma_enable0_we - attribute \src "ls180.v:2062.12-2062.42" - wire width 8 \builder_csrbank4_dma_length0_r - attribute \src "ls180.v:2061.6-2061.37" - wire \builder_csrbank4_dma_length0_re - attribute \src "ls180.v:2064.12-2064.42" - wire width 8 \builder_csrbank4_dma_length0_w - attribute \src "ls180.v:2063.6-2063.37" - wire \builder_csrbank4_dma_length0_we - attribute \src "ls180.v:2058.12-2058.42" - wire width 8 \builder_csrbank4_dma_length1_r - attribute \src "ls180.v:2057.6-2057.37" - wire \builder_csrbank4_dma_length1_re - attribute \src "ls180.v:2060.12-2060.42" - wire width 8 \builder_csrbank4_dma_length1_w - attribute \src "ls180.v:2059.6-2059.37" - wire \builder_csrbank4_dma_length1_we - attribute \src "ls180.v:2054.12-2054.42" - wire width 8 \builder_csrbank4_dma_length2_r - attribute \src "ls180.v:2053.6-2053.37" - wire \builder_csrbank4_dma_length2_re - attribute \src "ls180.v:2056.12-2056.42" - wire width 8 \builder_csrbank4_dma_length2_w - attribute \src "ls180.v:2055.6-2055.37" - wire \builder_csrbank4_dma_length2_we - attribute \src "ls180.v:2050.12-2050.42" - wire width 8 \builder_csrbank4_dma_length3_r - attribute \src "ls180.v:2049.6-2049.37" - wire \builder_csrbank4_dma_length3_re - attribute \src "ls180.v:2052.12-2052.42" - wire width 8 \builder_csrbank4_dma_length3_w - attribute \src "ls180.v:2051.6-2051.37" - wire \builder_csrbank4_dma_length3_we - attribute \src "ls180.v:2074.6-2074.34" - wire \builder_csrbank4_dma_loop0_r - attribute \src "ls180.v:2073.6-2073.35" - wire \builder_csrbank4_dma_loop0_re - attribute \src "ls180.v:2076.6-2076.34" - wire \builder_csrbank4_dma_loop0_w - attribute \src "ls180.v:2075.6-2075.35" - wire \builder_csrbank4_dma_loop0_we - attribute \src "ls180.v:2077.6-2077.26" + attribute \src "ls180.v:2028.6-2028.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2027.6-2027.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2030.6-2030.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2029.6-2029.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2060.12-2060.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2059.6-2059.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2062.12-2062.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2061.6-2061.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2056.12-2056.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2055.6-2055.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2058.12-2058.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2057.6-2057.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2052.12-2052.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2051.6-2051.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2054.12-2054.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2053.6-2053.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2048.12-2048.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2047.6-2047.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2050.12-2050.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2049.6-2049.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2063.6-2063.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2207.12-2207.43" - wire width 8 \builder_csrbank5_block_count0_r - attribute \src "ls180.v:2206.6-2206.38" - wire \builder_csrbank5_block_count0_re - attribute \src "ls180.v:2209.12-2209.43" - wire width 8 \builder_csrbank5_block_count0_w - attribute \src "ls180.v:2208.6-2208.38" - wire \builder_csrbank5_block_count0_we - attribute \src "ls180.v:2203.12-2203.43" - wire width 8 \builder_csrbank5_block_count1_r - attribute \src "ls180.v:2202.6-2202.38" - wire \builder_csrbank5_block_count1_re - attribute \src "ls180.v:2205.12-2205.43" - wire width 8 \builder_csrbank5_block_count1_w - attribute \src "ls180.v:2204.6-2204.38" - wire \builder_csrbank5_block_count1_we - attribute \src "ls180.v:2199.12-2199.43" - wire width 8 \builder_csrbank5_block_count2_r - attribute \src "ls180.v:2198.6-2198.38" - wire \builder_csrbank5_block_count2_re - attribute \src "ls180.v:2201.12-2201.43" - wire width 8 \builder_csrbank5_block_count2_w - attribute \src "ls180.v:2200.6-2200.38" - wire \builder_csrbank5_block_count2_we - attribute \src "ls180.v:2195.12-2195.43" - wire width 8 \builder_csrbank5_block_count3_r - attribute \src "ls180.v:2194.6-2194.38" - wire \builder_csrbank5_block_count3_re - attribute \src "ls180.v:2197.12-2197.43" - wire width 8 \builder_csrbank5_block_count3_w - attribute \src "ls180.v:2196.6-2196.38" - wire \builder_csrbank5_block_count3_we - attribute \src "ls180.v:2191.12-2191.44" - wire width 8 \builder_csrbank5_block_length0_r - attribute \src "ls180.v:2190.6-2190.39" - wire \builder_csrbank5_block_length0_re - attribute \src "ls180.v:2193.12-2193.44" - wire width 8 \builder_csrbank5_block_length0_w - attribute \src "ls180.v:2192.6-2192.39" - wire \builder_csrbank5_block_length0_we - attribute \src "ls180.v:2187.12-2187.44" - wire width 2 \builder_csrbank5_block_length1_r - attribute \src "ls180.v:2186.6-2186.39" - wire \builder_csrbank5_block_length1_re - attribute \src "ls180.v:2189.12-2189.44" - wire width 2 \builder_csrbank5_block_length1_w - attribute \src "ls180.v:2188.6-2188.39" - wire \builder_csrbank5_block_length1_we - attribute \src "ls180.v:2095.12-2095.44" - wire width 8 \builder_csrbank5_cmd_argument0_r - attribute \src "ls180.v:2094.6-2094.39" - wire \builder_csrbank5_cmd_argument0_re - attribute \src "ls180.v:2097.12-2097.44" - wire width 8 \builder_csrbank5_cmd_argument0_w - attribute \src "ls180.v:2096.6-2096.39" - wire \builder_csrbank5_cmd_argument0_we - attribute \src "ls180.v:2091.12-2091.44" - wire width 8 \builder_csrbank5_cmd_argument1_r - attribute \src "ls180.v:2090.6-2090.39" - wire \builder_csrbank5_cmd_argument1_re - attribute \src "ls180.v:2093.12-2093.44" - wire width 8 \builder_csrbank5_cmd_argument1_w - attribute \src "ls180.v:2092.6-2092.39" - wire \builder_csrbank5_cmd_argument1_we - attribute \src "ls180.v:2087.12-2087.44" - wire width 8 \builder_csrbank5_cmd_argument2_r - attribute \src "ls180.v:2086.6-2086.39" - wire \builder_csrbank5_cmd_argument2_re - attribute \src "ls180.v:2089.12-2089.44" - wire width 8 \builder_csrbank5_cmd_argument2_w - attribute \src "ls180.v:2088.6-2088.39" - wire \builder_csrbank5_cmd_argument2_we - attribute \src "ls180.v:2083.12-2083.44" - wire width 8 \builder_csrbank5_cmd_argument3_r - attribute \src "ls180.v:2082.6-2082.39" - wire \builder_csrbank5_cmd_argument3_re - attribute \src "ls180.v:2085.12-2085.44" - wire width 8 \builder_csrbank5_cmd_argument3_w - attribute \src "ls180.v:2084.6-2084.39" - wire \builder_csrbank5_cmd_argument3_we - attribute \src "ls180.v:2111.12-2111.43" - wire width 8 \builder_csrbank5_cmd_command0_r - attribute \src "ls180.v:2110.6-2110.38" - wire \builder_csrbank5_cmd_command0_re - attribute \src "ls180.v:2113.12-2113.43" - wire width 8 \builder_csrbank5_cmd_command0_w - attribute \src "ls180.v:2112.6-2112.38" - wire \builder_csrbank5_cmd_command0_we - attribute \src "ls180.v:2107.12-2107.43" - wire width 8 \builder_csrbank5_cmd_command1_r - attribute \src "ls180.v:2106.6-2106.38" - wire \builder_csrbank5_cmd_command1_re - attribute \src "ls180.v:2109.12-2109.43" - wire width 8 \builder_csrbank5_cmd_command1_w - attribute \src "ls180.v:2108.6-2108.38" - wire \builder_csrbank5_cmd_command1_we - attribute \src "ls180.v:2103.12-2103.43" - wire width 8 \builder_csrbank5_cmd_command2_r - attribute \src "ls180.v:2102.6-2102.38" - wire \builder_csrbank5_cmd_command2_re - attribute \src "ls180.v:2105.12-2105.43" - wire width 8 \builder_csrbank5_cmd_command2_w - attribute \src "ls180.v:2104.6-2104.38" - wire \builder_csrbank5_cmd_command2_we - attribute \src "ls180.v:2099.12-2099.43" - wire width 8 \builder_csrbank5_cmd_command3_r - attribute \src "ls180.v:2098.6-2098.38" - wire \builder_csrbank5_cmd_command3_re - attribute \src "ls180.v:2101.12-2101.43" - wire width 8 \builder_csrbank5_cmd_command3_w - attribute \src "ls180.v:2100.6-2100.38" - wire \builder_csrbank5_cmd_command3_we - attribute \src "ls180.v:2179.12-2179.40" - wire width 4 \builder_csrbank5_cmd_event_r - attribute \src "ls180.v:2178.6-2178.35" - wire \builder_csrbank5_cmd_event_re - attribute \src "ls180.v:2181.12-2181.40" - wire width 4 \builder_csrbank5_cmd_event_w - attribute \src "ls180.v:2180.6-2180.35" - wire \builder_csrbank5_cmd_event_we - attribute \src "ls180.v:2175.12-2175.44" - wire width 8 \builder_csrbank5_cmd_response0_r - attribute \src "ls180.v:2174.6-2174.39" - wire \builder_csrbank5_cmd_response0_re - attribute \src "ls180.v:2177.12-2177.44" - wire width 8 \builder_csrbank5_cmd_response0_w - attribute \src "ls180.v:2176.6-2176.39" - wire \builder_csrbank5_cmd_response0_we - attribute \src "ls180.v:2135.12-2135.45" - wire width 8 \builder_csrbank5_cmd_response10_r - attribute \src "ls180.v:2134.6-2134.40" - wire \builder_csrbank5_cmd_response10_re - attribute \src "ls180.v:2137.12-2137.45" - wire width 8 \builder_csrbank5_cmd_response10_w - attribute \src "ls180.v:2136.6-2136.40" - wire \builder_csrbank5_cmd_response10_we - attribute \src "ls180.v:2131.12-2131.45" - wire width 8 \builder_csrbank5_cmd_response11_r - attribute \src "ls180.v:2130.6-2130.40" - wire \builder_csrbank5_cmd_response11_re - attribute \src "ls180.v:2133.12-2133.45" - wire width 8 \builder_csrbank5_cmd_response11_w - attribute \src "ls180.v:2132.6-2132.40" - wire \builder_csrbank5_cmd_response11_we - attribute \src "ls180.v:2127.12-2127.45" - wire width 8 \builder_csrbank5_cmd_response12_r - attribute \src "ls180.v:2126.6-2126.40" - wire \builder_csrbank5_cmd_response12_re - attribute \src "ls180.v:2129.12-2129.45" - wire width 8 \builder_csrbank5_cmd_response12_w - attribute \src "ls180.v:2128.6-2128.40" - wire \builder_csrbank5_cmd_response12_we - attribute \src "ls180.v:2123.12-2123.45" - wire width 8 \builder_csrbank5_cmd_response13_r - attribute \src "ls180.v:2122.6-2122.40" - wire \builder_csrbank5_cmd_response13_re - attribute \src "ls180.v:2125.12-2125.45" - wire width 8 \builder_csrbank5_cmd_response13_w - attribute \src "ls180.v:2124.6-2124.40" - wire \builder_csrbank5_cmd_response13_we - attribute \src "ls180.v:2119.12-2119.45" - wire width 8 \builder_csrbank5_cmd_response14_r - attribute \src "ls180.v:2118.6-2118.40" - wire \builder_csrbank5_cmd_response14_re - attribute \src "ls180.v:2121.12-2121.45" - wire width 8 \builder_csrbank5_cmd_response14_w - attribute \src "ls180.v:2120.6-2120.40" - wire \builder_csrbank5_cmd_response14_we - attribute \src "ls180.v:2115.12-2115.45" - wire width 8 \builder_csrbank5_cmd_response15_r - attribute \src "ls180.v:2114.6-2114.40" - wire \builder_csrbank5_cmd_response15_re - attribute \src "ls180.v:2117.12-2117.45" - wire width 8 \builder_csrbank5_cmd_response15_w - attribute \src "ls180.v:2116.6-2116.40" - wire \builder_csrbank5_cmd_response15_we - attribute \src "ls180.v:2171.12-2171.44" - wire width 8 \builder_csrbank5_cmd_response1_r - attribute \src "ls180.v:2170.6-2170.39" - wire \builder_csrbank5_cmd_response1_re - attribute \src "ls180.v:2173.12-2173.44" - wire width 8 \builder_csrbank5_cmd_response1_w - attribute \src "ls180.v:2172.6-2172.39" - wire \builder_csrbank5_cmd_response1_we - attribute \src "ls180.v:2167.12-2167.44" - wire width 8 \builder_csrbank5_cmd_response2_r - attribute \src "ls180.v:2166.6-2166.39" - wire \builder_csrbank5_cmd_response2_re - attribute \src "ls180.v:2169.12-2169.44" - wire width 8 \builder_csrbank5_cmd_response2_w - attribute \src "ls180.v:2168.6-2168.39" - wire \builder_csrbank5_cmd_response2_we - attribute \src "ls180.v:2163.12-2163.44" - wire width 8 \builder_csrbank5_cmd_response3_r - attribute \src "ls180.v:2162.6-2162.39" - wire \builder_csrbank5_cmd_response3_re - attribute \src "ls180.v:2165.12-2165.44" - wire width 8 \builder_csrbank5_cmd_response3_w - attribute \src "ls180.v:2164.6-2164.39" - wire \builder_csrbank5_cmd_response3_we - attribute \src "ls180.v:2159.12-2159.44" - wire width 8 \builder_csrbank5_cmd_response4_r - attribute \src "ls180.v:2158.6-2158.39" - wire \builder_csrbank5_cmd_response4_re - attribute \src "ls180.v:2161.12-2161.44" - wire width 8 \builder_csrbank5_cmd_response4_w - attribute \src "ls180.v:2160.6-2160.39" - wire \builder_csrbank5_cmd_response4_we - attribute \src "ls180.v:2155.12-2155.44" - wire width 8 \builder_csrbank5_cmd_response5_r - attribute \src "ls180.v:2154.6-2154.39" - wire \builder_csrbank5_cmd_response5_re - attribute \src "ls180.v:2157.12-2157.44" - wire width 8 \builder_csrbank5_cmd_response5_w - attribute \src "ls180.v:2156.6-2156.39" - wire \builder_csrbank5_cmd_response5_we - attribute \src "ls180.v:2151.12-2151.44" - wire width 8 \builder_csrbank5_cmd_response6_r - attribute \src "ls180.v:2150.6-2150.39" - wire \builder_csrbank5_cmd_response6_re - attribute \src "ls180.v:2153.12-2153.44" - wire width 8 \builder_csrbank5_cmd_response6_w - attribute \src "ls180.v:2152.6-2152.39" - wire \builder_csrbank5_cmd_response6_we - attribute \src "ls180.v:2147.12-2147.44" - wire width 8 \builder_csrbank5_cmd_response7_r - attribute \src "ls180.v:2146.6-2146.39" - wire \builder_csrbank5_cmd_response7_re - attribute \src "ls180.v:2149.12-2149.44" - wire width 8 \builder_csrbank5_cmd_response7_w - attribute \src "ls180.v:2148.6-2148.39" - wire \builder_csrbank5_cmd_response7_we - attribute \src "ls180.v:2143.12-2143.44" - wire width 8 \builder_csrbank5_cmd_response8_r - attribute \src "ls180.v:2142.6-2142.39" - wire \builder_csrbank5_cmd_response8_re - attribute \src "ls180.v:2145.12-2145.44" - wire width 8 \builder_csrbank5_cmd_response8_w - attribute \src "ls180.v:2144.6-2144.39" - wire \builder_csrbank5_cmd_response8_we - attribute \src "ls180.v:2139.12-2139.44" - wire width 8 \builder_csrbank5_cmd_response9_r - attribute \src "ls180.v:2138.6-2138.39" - wire \builder_csrbank5_cmd_response9_re - attribute \src "ls180.v:2141.12-2141.44" - wire width 8 \builder_csrbank5_cmd_response9_w - attribute \src "ls180.v:2140.6-2140.39" - wire \builder_csrbank5_cmd_response9_we - attribute \src "ls180.v:2183.12-2183.41" - wire width 4 \builder_csrbank5_data_event_r - attribute \src "ls180.v:2182.6-2182.36" - wire \builder_csrbank5_data_event_re - attribute \src "ls180.v:2185.12-2185.41" - wire width 4 \builder_csrbank5_data_event_w - attribute \src "ls180.v:2184.6-2184.36" - wire \builder_csrbank5_data_event_we - attribute \src "ls180.v:2210.6-2210.26" + attribute \src "ls180.v:2044.12-2044.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2043.6-2043.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2046.12-2046.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2045.6-2045.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2040.12-2040.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2039.6-2039.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2042.12-2042.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2041.6-2041.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2036.12-2036.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2035.6-2035.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2038.12-2038.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2037.6-2037.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2032.12-2032.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2031.6-2031.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2034.12-2034.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2033.6-2033.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2097.12-2097.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2096.6-2096.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2099.12-2099.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2098.6-2098.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2093.12-2093.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2092.6-2092.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2095.12-2095.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2094.6-2094.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2089.12-2089.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2088.6-2088.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2091.12-2091.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2090.6-2090.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2085.12-2085.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2084.6-2084.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2087.12-2087.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2086.6-2086.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2081.12-2081.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2080.6-2080.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2083.12-2083.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2082.6-2082.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2077.12-2077.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2076.6-2076.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2079.12-2079.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2078.6-2078.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2073.12-2073.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2072.6-2072.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2075.12-2075.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2074.6-2074.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2069.12-2069.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2068.6-2068.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2071.12-2071.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2070.6-2070.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2121.6-2121.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2120.6-2120.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2123.6-2123.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2122.6-2122.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2117.6-2117.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2116.6-2116.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2119.6-2119.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2118.6-2118.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2113.12-2113.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2112.6-2112.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2115.12-2115.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2114.6-2114.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2109.12-2109.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2108.6-2108.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2111.12-2111.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2110.6-2110.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2105.12-2105.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2104.6-2104.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2107.12-2107.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2106.6-2106.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2101.12-2101.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2100.6-2100.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2103.12-2103.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2102.6-2102.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2125.6-2125.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2124.6-2124.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2127.6-2127.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2126.6-2126.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2128.6-2128.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2244.12-2244.40" - wire width 8 \builder_csrbank6_dma_base0_r - attribute \src "ls180.v:2243.6-2243.35" - wire \builder_csrbank6_dma_base0_re - attribute \src "ls180.v:2246.12-2246.40" - wire width 8 \builder_csrbank6_dma_base0_w - attribute \src "ls180.v:2245.6-2245.35" - wire \builder_csrbank6_dma_base0_we - attribute \src "ls180.v:2240.12-2240.40" - wire width 8 \builder_csrbank6_dma_base1_r - attribute \src "ls180.v:2239.6-2239.35" - wire \builder_csrbank6_dma_base1_re - attribute \src "ls180.v:2242.12-2242.40" - wire width 8 \builder_csrbank6_dma_base1_w - attribute \src "ls180.v:2241.6-2241.35" - wire \builder_csrbank6_dma_base1_we - attribute \src "ls180.v:2236.12-2236.40" - wire width 8 \builder_csrbank6_dma_base2_r - attribute \src "ls180.v:2235.6-2235.35" - wire \builder_csrbank6_dma_base2_re - attribute \src "ls180.v:2238.12-2238.40" - wire width 8 \builder_csrbank6_dma_base2_w - attribute \src "ls180.v:2237.6-2237.35" - wire \builder_csrbank6_dma_base2_we - attribute \src "ls180.v:2232.12-2232.40" - wire width 8 \builder_csrbank6_dma_base3_r - attribute \src "ls180.v:2231.6-2231.35" - wire \builder_csrbank6_dma_base3_re - attribute \src "ls180.v:2234.12-2234.40" - wire width 8 \builder_csrbank6_dma_base3_w - attribute \src "ls180.v:2233.6-2233.35" - wire \builder_csrbank6_dma_base3_we - attribute \src "ls180.v:2228.12-2228.40" - wire width 8 \builder_csrbank6_dma_base4_r - attribute \src "ls180.v:2227.6-2227.35" - wire \builder_csrbank6_dma_base4_re + attribute \src "ls180.v:2258.12-2258.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2257.6-2257.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2260.12-2260.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2259.6-2259.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2254.12-2254.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2253.6-2253.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2256.12-2256.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2255.6-2255.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2250.12-2250.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2249.6-2249.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2252.12-2252.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2251.6-2251.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2246.12-2246.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2245.6-2245.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2248.12-2248.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2247.6-2247.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2242.12-2242.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2241.6-2241.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2244.12-2244.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2243.6-2243.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2238.12-2238.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2237.6-2237.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2240.12-2240.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2239.6-2239.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2146.12-2146.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2145.6-2145.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2148.12-2148.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2147.6-2147.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2142.12-2142.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2141.6-2141.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2144.12-2144.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2143.6-2143.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2138.12-2138.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2137.6-2137.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2140.12-2140.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2139.6-2139.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2134.12-2134.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2133.6-2133.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2136.12-2136.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2135.6-2135.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2162.12-2162.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2161.6-2161.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2164.12-2164.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2163.6-2163.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2158.12-2158.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2157.6-2157.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2160.12-2160.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2159.6-2159.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2154.12-2154.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2153.6-2153.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2156.12-2156.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2155.6-2155.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2150.12-2150.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2149.6-2149.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2152.12-2152.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2151.6-2151.38" + wire \builder_csrbank6_cmd_command3_we attribute \src "ls180.v:2230.12-2230.40" - wire width 8 \builder_csrbank6_dma_base4_w + wire width 4 \builder_csrbank6_cmd_event_r attribute \src "ls180.v:2229.6-2229.35" - wire \builder_csrbank6_dma_base4_we - attribute \src "ls180.v:2224.12-2224.40" - wire width 8 \builder_csrbank6_dma_base5_r - attribute \src "ls180.v:2223.6-2223.35" - wire \builder_csrbank6_dma_base5_re - attribute \src "ls180.v:2226.12-2226.40" - wire width 8 \builder_csrbank6_dma_base5_w - attribute \src "ls180.v:2225.6-2225.35" - wire \builder_csrbank6_dma_base5_we - attribute \src "ls180.v:2220.12-2220.40" - wire width 8 \builder_csrbank6_dma_base6_r - attribute \src "ls180.v:2219.6-2219.35" - wire \builder_csrbank6_dma_base6_re - attribute \src "ls180.v:2222.12-2222.40" - wire width 8 \builder_csrbank6_dma_base6_w - attribute \src "ls180.v:2221.6-2221.35" - wire \builder_csrbank6_dma_base6_we - attribute \src "ls180.v:2216.12-2216.40" - wire width 8 \builder_csrbank6_dma_base7_r - attribute \src "ls180.v:2215.6-2215.35" - wire \builder_csrbank6_dma_base7_re - attribute \src "ls180.v:2218.12-2218.40" - wire width 8 \builder_csrbank6_dma_base7_w - attribute \src "ls180.v:2217.6-2217.35" - wire \builder_csrbank6_dma_base7_we - attribute \src "ls180.v:2268.6-2268.33" - wire \builder_csrbank6_dma_done_r - attribute \src "ls180.v:2267.6-2267.34" - wire \builder_csrbank6_dma_done_re - attribute \src "ls180.v:2270.6-2270.33" - wire \builder_csrbank6_dma_done_w - attribute \src "ls180.v:2269.6-2269.34" - wire \builder_csrbank6_dma_done_we - attribute \src "ls180.v:2264.6-2264.36" - wire \builder_csrbank6_dma_enable0_r - attribute \src "ls180.v:2263.6-2263.37" - wire \builder_csrbank6_dma_enable0_re - attribute \src "ls180.v:2266.6-2266.36" - wire \builder_csrbank6_dma_enable0_w - attribute \src "ls180.v:2265.6-2265.37" - wire \builder_csrbank6_dma_enable0_we - attribute \src "ls180.v:2260.12-2260.42" - wire width 8 \builder_csrbank6_dma_length0_r - attribute \src "ls180.v:2259.6-2259.37" - wire \builder_csrbank6_dma_length0_re - attribute \src "ls180.v:2262.12-2262.42" - wire width 8 \builder_csrbank6_dma_length0_w - attribute \src "ls180.v:2261.6-2261.37" - wire \builder_csrbank6_dma_length0_we - attribute \src "ls180.v:2256.12-2256.42" - wire width 8 \builder_csrbank6_dma_length1_r - attribute \src "ls180.v:2255.6-2255.37" - wire \builder_csrbank6_dma_length1_re - attribute \src "ls180.v:2258.12-2258.42" - wire width 8 \builder_csrbank6_dma_length1_w - attribute \src "ls180.v:2257.6-2257.37" - wire \builder_csrbank6_dma_length1_we - attribute \src "ls180.v:2252.12-2252.42" - wire width 8 \builder_csrbank6_dma_length2_r - attribute \src "ls180.v:2251.6-2251.37" - wire \builder_csrbank6_dma_length2_re - attribute \src "ls180.v:2254.12-2254.42" - wire width 8 \builder_csrbank6_dma_length2_w - attribute \src "ls180.v:2253.6-2253.37" - wire \builder_csrbank6_dma_length2_we - attribute \src "ls180.v:2248.12-2248.42" - wire width 8 \builder_csrbank6_dma_length3_r - attribute \src "ls180.v:2247.6-2247.37" - wire \builder_csrbank6_dma_length3_re - attribute \src "ls180.v:2250.12-2250.42" - wire width 8 \builder_csrbank6_dma_length3_w - attribute \src "ls180.v:2249.6-2249.37" - wire \builder_csrbank6_dma_length3_we - attribute \src "ls180.v:2272.6-2272.34" - wire \builder_csrbank6_dma_loop0_r - attribute \src "ls180.v:2271.6-2271.35" - wire \builder_csrbank6_dma_loop0_re - attribute \src "ls180.v:2274.6-2274.34" - wire \builder_csrbank6_dma_loop0_w - attribute \src "ls180.v:2273.6-2273.35" - wire \builder_csrbank6_dma_loop0_we - attribute \src "ls180.v:2288.12-2288.42" - wire width 8 \builder_csrbank6_dma_offset0_r - attribute \src "ls180.v:2287.6-2287.37" - wire \builder_csrbank6_dma_offset0_re - attribute \src "ls180.v:2290.12-2290.42" - wire width 8 \builder_csrbank6_dma_offset0_w - attribute \src "ls180.v:2289.6-2289.37" - wire \builder_csrbank6_dma_offset0_we - attribute \src "ls180.v:2284.12-2284.42" - wire width 8 \builder_csrbank6_dma_offset1_r - attribute \src "ls180.v:2283.6-2283.37" - wire \builder_csrbank6_dma_offset1_re - attribute \src "ls180.v:2286.12-2286.42" - wire width 8 \builder_csrbank6_dma_offset1_w - attribute \src "ls180.v:2285.6-2285.37" - wire \builder_csrbank6_dma_offset1_we - attribute \src "ls180.v:2280.12-2280.42" - wire width 8 \builder_csrbank6_dma_offset2_r - attribute \src "ls180.v:2279.6-2279.37" - wire \builder_csrbank6_dma_offset2_re - attribute \src "ls180.v:2282.12-2282.42" - wire width 8 \builder_csrbank6_dma_offset2_w - attribute \src "ls180.v:2281.6-2281.37" - wire \builder_csrbank6_dma_offset2_we - attribute \src "ls180.v:2276.12-2276.42" - wire width 8 \builder_csrbank6_dma_offset3_r - attribute \src "ls180.v:2275.6-2275.37" - wire \builder_csrbank6_dma_offset3_re - attribute \src "ls180.v:2278.12-2278.42" - wire width 8 \builder_csrbank6_dma_offset3_w - attribute \src "ls180.v:2277.6-2277.37" - wire \builder_csrbank6_dma_offset3_we - attribute \src "ls180.v:2291.6-2291.26" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2232.12-2232.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2231.6-2231.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2226.12-2226.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2225.6-2225.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2228.12-2228.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2227.6-2227.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2186.12-2186.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2185.6-2185.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2188.12-2188.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2187.6-2187.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2182.12-2182.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2181.6-2181.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2184.12-2184.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2183.6-2183.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2178.12-2178.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2177.6-2177.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2180.12-2180.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2179.6-2179.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2174.12-2174.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2173.6-2173.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2176.12-2176.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2175.6-2175.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2170.12-2170.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2169.6-2169.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2172.12-2172.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2171.6-2171.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2166.12-2166.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2165.6-2165.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2168.12-2168.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2167.6-2167.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2222.12-2222.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2221.6-2221.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2224.12-2224.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2223.6-2223.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2218.12-2218.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2217.6-2217.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2220.12-2220.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2219.6-2219.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2214.12-2214.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2213.6-2213.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2216.12-2216.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2215.6-2215.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2210.12-2210.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2209.6-2209.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2212.12-2212.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2211.6-2211.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2206.12-2206.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2205.6-2205.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2208.12-2208.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2207.6-2207.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2202.12-2202.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2201.6-2201.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2204.12-2204.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2203.6-2203.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2198.12-2198.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2197.6-2197.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2200.12-2200.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2199.6-2199.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2194.12-2194.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2193.6-2193.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2196.12-2196.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2195.6-2195.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2190.12-2190.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2189.6-2189.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2192.12-2192.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2191.6-2191.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2234.12-2234.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2233.6-2233.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2236.12-2236.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2235.6-2235.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2261.6-2261.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2297.6-2297.36" - wire \builder_csrbank7_card_detect_r - attribute \src "ls180.v:2296.6-2296.37" - wire \builder_csrbank7_card_detect_re - attribute \src "ls180.v:2299.6-2299.36" - wire \builder_csrbank7_card_detect_w + attribute \src "ls180.v:2295.12-2295.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2294.6-2294.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2297.12-2297.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2296.6-2296.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2291.12-2291.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2290.6-2290.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2293.12-2293.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2292.6-2292.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2287.12-2287.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2286.6-2286.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2289.12-2289.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2288.6-2288.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2283.12-2283.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2282.6-2282.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2285.12-2285.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2284.6-2284.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2279.12-2279.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2278.6-2278.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2281.12-2281.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2280.6-2280.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2275.12-2275.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2274.6-2274.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2277.12-2277.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2276.6-2276.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2271.12-2271.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2270.6-2270.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2273.12-2273.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2272.6-2272.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2267.12-2267.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2266.6-2266.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2269.12-2269.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2268.6-2268.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2319.6-2319.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2318.6-2318.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2321.6-2321.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2320.6-2320.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2315.6-2315.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2314.6-2314.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2317.6-2317.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2316.6-2316.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2311.12-2311.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2310.6-2310.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2313.12-2313.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2312.6-2312.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2307.12-2307.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2306.6-2306.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2309.12-2309.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2308.6-2308.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2303.12-2303.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2302.6-2302.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2305.12-2305.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2304.6-2304.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2299.12-2299.42" + wire width 8 \builder_csrbank7_dma_length3_r attribute \src "ls180.v:2298.6-2298.37" - wire \builder_csrbank7_card_detect_we - attribute \src "ls180.v:2305.12-2305.47" - wire width 8 \builder_csrbank7_clocker_divider0_r - attribute \src "ls180.v:2304.6-2304.42" - wire \builder_csrbank7_clocker_divider0_re - attribute \src "ls180.v:2307.12-2307.47" - wire width 8 \builder_csrbank7_clocker_divider0_w - attribute \src "ls180.v:2306.6-2306.42" - wire \builder_csrbank7_clocker_divider0_we - attribute \src "ls180.v:2301.6-2301.41" - wire \builder_csrbank7_clocker_divider1_r - attribute \src "ls180.v:2300.6-2300.42" - wire \builder_csrbank7_clocker_divider1_re - attribute \src "ls180.v:2303.6-2303.41" - wire \builder_csrbank7_clocker_divider1_w - attribute \src "ls180.v:2302.6-2302.42" - wire \builder_csrbank7_clocker_divider1_we - attribute \src "ls180.v:2308.6-2308.26" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2301.12-2301.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2300.6-2300.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2323.6-2323.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2322.6-2322.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2325.6-2325.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2324.6-2324.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2339.12-2339.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2338.6-2338.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2341.12-2341.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2340.6-2340.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2335.12-2335.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2334.6-2334.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2337.12-2337.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2336.6-2336.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2331.12-2331.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2330.6-2330.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2333.12-2333.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2332.6-2332.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2327.12-2327.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2326.6-2326.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2329.12-2329.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2328.6-2328.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2342.6-2342.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2314.12-2314.44" - wire width 4 \builder_csrbank8_dfii_control0_r - attribute \src "ls180.v:2313.6-2313.39" - wire \builder_csrbank8_dfii_control0_re - attribute \src "ls180.v:2316.12-2316.44" - wire width 4 \builder_csrbank8_dfii_control0_w - attribute \src "ls180.v:2315.6-2315.39" - wire \builder_csrbank8_dfii_control0_we - attribute \src "ls180.v:2326.12-2326.48" - wire width 8 \builder_csrbank8_dfii_pi0_address0_r - attribute \src "ls180.v:2325.6-2325.43" - wire \builder_csrbank8_dfii_pi0_address0_re - attribute \src "ls180.v:2328.12-2328.48" - wire width 8 \builder_csrbank8_dfii_pi0_address0_w - attribute \src "ls180.v:2327.6-2327.43" - wire \builder_csrbank8_dfii_pi0_address0_we - attribute \src "ls180.v:2322.12-2322.48" - wire width 5 \builder_csrbank8_dfii_pi0_address1_r - attribute \src "ls180.v:2321.6-2321.43" - wire \builder_csrbank8_dfii_pi0_address1_re - attribute \src "ls180.v:2324.12-2324.48" - wire width 5 \builder_csrbank8_dfii_pi0_address1_w - attribute \src "ls180.v:2323.6-2323.43" - wire \builder_csrbank8_dfii_pi0_address1_we - attribute \src "ls180.v:2330.12-2330.49" - wire width 2 \builder_csrbank8_dfii_pi0_baddress0_r - attribute \src "ls180.v:2329.6-2329.44" - wire \builder_csrbank8_dfii_pi0_baddress0_re - attribute \src "ls180.v:2332.12-2332.49" - wire width 2 \builder_csrbank8_dfii_pi0_baddress0_w - attribute \src "ls180.v:2331.6-2331.44" - wire \builder_csrbank8_dfii_pi0_baddress0_we - attribute \src "ls180.v:2318.12-2318.48" - wire width 6 \builder_csrbank8_dfii_pi0_command0_r - attribute \src "ls180.v:2317.6-2317.43" - wire \builder_csrbank8_dfii_pi0_command0_re - attribute \src "ls180.v:2320.12-2320.48" - wire width 6 \builder_csrbank8_dfii_pi0_command0_w - attribute \src "ls180.v:2319.6-2319.43" - wire \builder_csrbank8_dfii_pi0_command0_we - attribute \src "ls180.v:2346.12-2346.47" - wire width 8 \builder_csrbank8_dfii_pi0_rddata0_r - attribute \src "ls180.v:2345.6-2345.42" - wire \builder_csrbank8_dfii_pi0_rddata0_re - attribute \src "ls180.v:2348.12-2348.47" - wire width 8 \builder_csrbank8_dfii_pi0_rddata0_w - attribute \src "ls180.v:2347.6-2347.42" - wire \builder_csrbank8_dfii_pi0_rddata0_we - attribute \src "ls180.v:2342.12-2342.47" - wire width 8 \builder_csrbank8_dfii_pi0_rddata1_r - attribute \src "ls180.v:2341.6-2341.42" - wire \builder_csrbank8_dfii_pi0_rddata1_re - attribute \src "ls180.v:2344.12-2344.47" - wire width 8 \builder_csrbank8_dfii_pi0_rddata1_w - attribute \src "ls180.v:2343.6-2343.42" - wire \builder_csrbank8_dfii_pi0_rddata1_we - attribute \src "ls180.v:2338.12-2338.47" - wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2337.6-2337.42" - wire \builder_csrbank8_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2340.12-2340.47" - wire width 8 \builder_csrbank8_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2339.6-2339.42" - wire \builder_csrbank8_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2334.12-2334.47" - wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2333.6-2333.42" - wire \builder_csrbank8_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2336.12-2336.47" - wire width 8 \builder_csrbank8_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2335.6-2335.42" - wire \builder_csrbank8_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2349.6-2349.26" + attribute \src "ls180.v:2348.6-2348.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2347.6-2347.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2350.6-2350.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2349.6-2349.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2356.12-2356.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2355.6-2355.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2358.12-2358.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2357.6-2357.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2352.6-2352.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2351.6-2351.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2354.6-2354.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2353.6-2353.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2359.6-2359.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2359.12-2359.39" - wire width 8 \builder_csrbank9_control0_r - attribute \src "ls180.v:2358.6-2358.34" - wire \builder_csrbank9_control0_re - attribute \src "ls180.v:2361.12-2361.39" - wire width 8 \builder_csrbank9_control0_w - attribute \src "ls180.v:2360.6-2360.34" - wire \builder_csrbank9_control0_we - attribute \src "ls180.v:2355.12-2355.39" - wire width 8 \builder_csrbank9_control1_r - attribute \src "ls180.v:2354.6-2354.34" - wire \builder_csrbank9_control1_re - attribute \src "ls180.v:2357.12-2357.39" - wire width 8 \builder_csrbank9_control1_w - attribute \src "ls180.v:2356.6-2356.34" - wire \builder_csrbank9_control1_we - attribute \src "ls180.v:2375.6-2375.28" - wire \builder_csrbank9_cs0_r - attribute \src "ls180.v:2374.6-2374.29" - wire \builder_csrbank9_cs0_re - attribute \src "ls180.v:2377.6-2377.28" - wire \builder_csrbank9_cs0_w - attribute \src "ls180.v:2376.6-2376.29" - wire \builder_csrbank9_cs0_we - attribute \src "ls180.v:2379.6-2379.34" - wire \builder_csrbank9_loopback0_r - attribute \src "ls180.v:2378.6-2378.35" - wire \builder_csrbank9_loopback0_re - attribute \src "ls180.v:2381.6-2381.34" - wire \builder_csrbank9_loopback0_w - attribute \src "ls180.v:2380.6-2380.35" - wire \builder_csrbank9_loopback0_we - attribute \src "ls180.v:2371.12-2371.35" - wire width 8 \builder_csrbank9_miso_r - attribute \src "ls180.v:2370.6-2370.30" - wire \builder_csrbank9_miso_re - attribute \src "ls180.v:2373.12-2373.35" - wire width 8 \builder_csrbank9_miso_w - attribute \src "ls180.v:2372.6-2372.30" - wire \builder_csrbank9_miso_we - attribute \src "ls180.v:2367.12-2367.36" - wire width 8 \builder_csrbank9_mosi0_r - attribute \src "ls180.v:2366.6-2366.31" - wire \builder_csrbank9_mosi0_re - attribute \src "ls180.v:2369.12-2369.36" - wire width 8 \builder_csrbank9_mosi0_w - attribute \src "ls180.v:2368.6-2368.31" - wire \builder_csrbank9_mosi0_we - attribute \src "ls180.v:2382.6-2382.26" + attribute \src "ls180.v:2365.12-2365.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2364.6-2364.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2367.12-2367.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2366.6-2366.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2377.12-2377.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2376.6-2376.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2379.12-2379.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2378.6-2378.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2373.12-2373.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2372.6-2372.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2375.12-2375.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2374.6-2374.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2381.12-2381.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2380.6-2380.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2383.12-2383.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2382.6-2382.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2369.12-2369.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2368.6-2368.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2371.12-2371.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2370.6-2370.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2397.12-2397.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2396.6-2396.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2399.12-2399.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2398.6-2398.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2393.12-2393.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2392.6-2392.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2395.12-2395.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2394.6-2394.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2389.12-2389.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2388.6-2388.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2391.12-2391.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2390.6-2390.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2385.12-2385.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2384.6-2384.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2387.12-2387.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2386.6-2386.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2400.6-2400.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:2363.6-2363.31" - wire \builder_csrbank9_status_r - attribute \src "ls180.v:2362.6-2362.32" - wire \builder_csrbank9_status_re - attribute \src "ls180.v:2365.6-2365.31" - wire \builder_csrbank9_status_w - attribute \src "ls180.v:2364.6-2364.32" - wire \builder_csrbank9_status_we - attribute \src "ls180.v:1859.6-1859.18" + attribute \src "ls180.v:1897.6-1897.18" wire \builder_done - attribute \src "ls180.v:1857.5-1857.18" + attribute \src "ls180.v:1895.5-1895.18" wire \builder_error - attribute \src "ls180.v:1854.11-1854.24" + attribute \src "ls180.v:1892.11-1892.24" wire width 3 \builder_grant - attribute \src "ls180.v:1861.13-1861.44" + attribute \src "ls180.v:1899.13-1899.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1864.11-1864.44" + attribute \src "ls180.v:1902.11-1902.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1863.12-1863.45" + attribute \src "ls180.v:1901.12-1901.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1862.6-1862.36" + attribute \src "ls180.v:1900.6-1900.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2383.13-2383.45" + attribute \src "ls180.v:2401.13-2401.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2386.11-2386.45" + attribute \src "ls180.v:2404.11-2404.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2385.12-2385.46" + attribute \src "ls180.v:2403.12-2403.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2384.6-2384.37" + attribute \src "ls180.v:2402.6-2402.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2424.13-2424.45" + attribute \src "ls180.v:2434.13-2434.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2427.11-2427.45" + attribute \src "ls180.v:2437.11-2437.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2426.12-2426.46" + attribute \src "ls180.v:2436.12-2436.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2425.6-2425.37" + attribute \src "ls180.v:2435.6-2435.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2489.13-2489.45" + attribute \src "ls180.v:2475.13-2475.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2492.11-2492.45" + attribute \src "ls180.v:2478.11-2478.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2491.12-2491.46" + attribute \src "ls180.v:2477.12-2477.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2490.6-2490.37" + attribute \src "ls180.v:2476.6-2476.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2514.13-2514.45" + attribute \src "ls180.v:2540.13-2540.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2517.11-2517.45" + attribute \src "ls180.v:2543.11-2543.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2516.12-2516.46" + attribute \src "ls180.v:2542.12-2542.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2515.6-2515.37" + attribute \src "ls180.v:2541.6-2541.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:1902.13-1902.44" + attribute \src "ls180.v:2565.13-2565.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2568.11-2568.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2567.12-2567.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2566.6-2566.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:1940.13-1940.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1905.11-1905.44" + attribute \src "ls180.v:1943.11-1943.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1904.12-1904.45" + attribute \src "ls180.v:1942.12-1942.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1903.6-1903.36" + attribute \src "ls180.v:1941.6-1941.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1931.13-1931.44" + attribute \src "ls180.v:1969.13-1969.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1934.11-1934.44" + attribute \src "ls180.v:1972.11-1972.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1933.12-1933.45" + attribute \src "ls180.v:1971.12-1971.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1932.6-1932.36" + attribute \src "ls180.v:1970.6-1970.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1972.13-1972.44" + attribute \src "ls180.v:1982.13-1982.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1975.11-1975.44" + attribute \src "ls180.v:1985.11-1985.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1974.12-1974.45" + attribute \src "ls180.v:1984.12-1984.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1973.6-1973.36" + attribute \src "ls180.v:1983.6-1983.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2013.13-2013.44" + attribute \src "ls180.v:2023.13-2023.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2016.11-2016.44" + attribute \src "ls180.v:2026.11-2026.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2015.12-2015.45" + attribute \src "ls180.v:2025.12-2025.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2014.6-2014.36" + attribute \src "ls180.v:2024.6-2024.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2078.13-2078.44" + attribute \src "ls180.v:2064.13-2064.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2081.11-2081.44" + attribute \src "ls180.v:2067.11-2067.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2080.12-2080.45" + attribute \src "ls180.v:2066.12-2066.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2079.6-2079.36" + attribute \src "ls180.v:2065.6-2065.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2211.13-2211.44" + attribute \src "ls180.v:2129.13-2129.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2214.11-2214.44" + attribute \src "ls180.v:2132.11-2132.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2213.12-2213.45" + attribute \src "ls180.v:2131.12-2131.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2212.6-2212.36" + attribute \src "ls180.v:2130.6-2130.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2292.13-2292.44" + attribute \src "ls180.v:2262.13-2262.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2295.11-2295.44" + attribute \src "ls180.v:2265.11-2265.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2294.12-2294.45" + attribute \src "ls180.v:2264.12-2264.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2293.6-2293.36" + attribute \src "ls180.v:2263.6-2263.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2309.13-2309.44" + attribute \src "ls180.v:2343.13-2343.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2312.11-2312.44" + attribute \src "ls180.v:2346.11-2346.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2311.12-2311.45" + attribute \src "ls180.v:2345.12-2345.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2310.6-2310.36" + attribute \src "ls180.v:2344.6-2344.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2350.13-2350.44" + attribute \src "ls180.v:2360.13-2360.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2353.11-2353.44" + attribute \src "ls180.v:2363.11-2363.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2352.12-2352.45" + attribute \src "ls180.v:2362.12-2362.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2351.6-2351.36" + attribute \src "ls180.v:2361.6-2361.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1827.12-1827.35" + attribute \src "ls180.v:1865.12-1865.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2543.12-2543.47" + attribute \src "ls180.v:2594.12-2594.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2544.5-2544.43" + attribute \src "ls180.v:2595.5-2595.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1830.12-1830.37" + attribute \src "ls180.v:1868.12-1868.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1829.11-1829.36" + attribute \src "ls180.v:1867.11-1867.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2541.11-2541.48" + attribute \src "ls180.v:2592.11-2592.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2542.5-2542.45" + attribute \src "ls180.v:2593.5-2593.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1828.5-1828.27" + attribute \src "ls180.v:1866.5-1866.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2545.5-2545.39" + attribute \src "ls180.v:2596.5-2596.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2546.5-2546.42" + attribute \src "ls180.v:2597.5-2597.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1837.5-1837.37" + attribute \src "ls180.v:1875.5-1875.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1831.13-1831.45" + attribute \src "ls180.v:1869.13-1869.45" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1840.12-1840.44" + attribute \src "ls180.v:1878.12-1878.44" wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1839.12-1839.44" + attribute \src "ls180.v:1877.12-1877.44" wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1835.6-1835.38" + attribute \src "ls180.v:1873.6-1873.38" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1833.12-1833.46" + attribute \src "ls180.v:1871.12-1871.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1832.13-1832.47" + attribute \src "ls180.v:1870.13-1870.47" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1841.5-1841.37" + attribute \src "ls180.v:1879.5-1879.37" wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1834.12-1834.44" + attribute \src "ls180.v:1872.12-1872.44" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1836.6-1836.38" + attribute \src "ls180.v:1874.6-1874.38" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1838.6-1838.37" + attribute \src "ls180.v:1876.6-1876.37" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1730.5-1730.20" + attribute \src "ls180.v:1768.5-1768.20" wire \builder_locked0 - attribute \src "ls180.v:1731.5-1731.20" + attribute \src "ls180.v:1769.5-1769.20" wire \builder_locked1 - attribute \src "ls180.v:1732.5-1732.20" + attribute \src "ls180.v:1770.5-1770.20" wire \builder_locked2 - attribute \src "ls180.v:1733.5-1733.20" + attribute \src "ls180.v:1771.5-1771.20" wire \builder_locked3 - attribute \src "ls180.v:1717.11-1717.41" + attribute \src "ls180.v:1755.11-1755.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1716.11-1716.36" + attribute \src "ls180.v:1754.11-1754.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2650.32-2650.59" + attribute \src "ls180.v:2701.32-2701.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2651.32-2651.59" + attribute \src "ls180.v:2702.32-2702.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2670.32-2670.60" + attribute \src "ls180.v:2721.32-2721.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2671.32-2671.60" + attribute \src "ls180.v:2722.32-2722.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2672.32-2672.60" + attribute \src "ls180.v:2723.32-2723.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2673.32-2673.60" + attribute \src "ls180.v:2724.32-2724.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2674.32-2674.60" + attribute \src "ls180.v:2725.32-2725.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2675.32-2675.60" + attribute \src "ls180.v:2726.32-2726.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2676.32-2676.60" + attribute \src "ls180.v:2727.32-2727.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2677.32-2677.60" + attribute \src "ls180.v:2728.32-2728.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2678.32-2678.60" + attribute \src "ls180.v:2729.32-2729.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2679.32-2679.60" + attribute \src "ls180.v:2730.32-2730.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2680.32-2680.60" + attribute \src "ls180.v:2731.32-2731.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2681.32-2681.60" + attribute \src "ls180.v:2732.32-2732.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2682.32-2682.60" + attribute \src "ls180.v:2733.32-2733.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2683.32-2683.60" + attribute \src "ls180.v:2734.32-2734.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2652.32-2652.59" + attribute \src "ls180.v:2703.32-2703.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2653.32-2653.59" + attribute \src "ls180.v:2704.32-2704.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2654.32-2654.59" + attribute \src "ls180.v:2705.32-2705.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2655.32-2655.59" + attribute \src "ls180.v:2706.32-2706.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2656.32-2656.59" + attribute \src "ls180.v:2707.32-2707.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2657.32-2657.59" + attribute \src "ls180.v:2708.32-2708.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2658.32-2658.59" + attribute \src "ls180.v:2709.32-2709.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2659.32-2659.59" + attribute \src "ls180.v:2710.32-2710.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2660.32-2660.59" + attribute \src "ls180.v:2711.32-2711.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2661.32-2661.59" + attribute \src "ls180.v:2712.32-2712.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2662.32-2662.59" + attribute \src "ls180.v:2713.32-2713.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2663.32-2663.59" + attribute \src "ls180.v:2714.32-2714.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2664.32-2664.59" + attribute \src "ls180.v:2715.32-2715.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2665.32-2665.59" + attribute \src "ls180.v:2716.32-2716.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2666.32-2666.59" + attribute \src "ls180.v:2717.32-2717.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2667.32-2667.59" + attribute \src "ls180.v:2718.32-2718.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2668.32-2668.59" + attribute \src "ls180.v:2719.32-2719.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2669.32-2669.59" + attribute \src "ls180.v:2720.32-2720.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1735.5-1735.36" + attribute \src "ls180.v:1773.5-1773.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1736.5-1736.36" + attribute \src "ls180.v:1774.5-1774.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1737.5-1737.36" + attribute \src "ls180.v:1775.5-1775.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1738.5-1738.36" + attribute \src "ls180.v:1776.5-1776.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1734.5-1734.35" + attribute \src "ls180.v:1772.5-1772.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2540.11-2540.29" + attribute \src "ls180.v:2591.11-2591.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1707.11-1707.39" + attribute \src "ls180.v:1745.11-1745.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1706.11-1706.34" + attribute \src "ls180.v:1744.11-1744.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:1853.12-1853.27" + attribute \src "ls180.v:1891.12-1891.27" wire width 5 \builder_request - attribute \src "ls180.v:1720.6-1720.28" + attribute \src "ls180.v:1758.6-1758.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1719.6-1719.31" + attribute \src "ls180.v:1757.6-1757.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1718.6-1718.33" + attribute \src "ls180.v:1756.6-1756.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1723.6-1723.28" + attribute \src "ls180.v:1761.6-1761.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1722.6-1722.31" + attribute \src "ls180.v:1760.6-1760.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1721.6-1721.33" + attribute \src "ls180.v:1759.6-1759.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1726.6-1726.28" + attribute \src "ls180.v:1764.6-1764.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1725.6-1725.31" + attribute \src "ls180.v:1763.6-1763.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1724.6-1724.33" + attribute \src "ls180.v:1762.6-1762.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1729.6-1729.28" + attribute \src "ls180.v:1767.6-1767.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1728.6-1728.31" + attribute \src "ls180.v:1766.6-1766.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1727.6-1727.33" + attribute \src "ls180.v:1765.6-1765.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1812.11-1812.44" + attribute \src "ls180.v:1854.11-1854.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1811.11-1811.39" + attribute \src "ls180.v:1853.11-1853.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1780.5-1780.50" + attribute \src "ls180.v:1822.5-1822.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1779.5-1779.45" + attribute \src "ls180.v:1821.5-1821.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1792.11-1792.40" + attribute \src "ls180.v:1834.11-1834.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1791.11-1791.35" + attribute \src "ls180.v:1833.11-1833.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1816.5-1816.42" + attribute \src "ls180.v:1858.5-1858.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1815.5-1815.37" + attribute \src "ls180.v:1857.5-1857.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1820.11-1820.58" + attribute \src "ls180.v:1862.11-1862.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1819.11-1819.53" + attribute \src "ls180.v:1861.11-1861.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1768.11-1768.39" + attribute \src "ls180.v:1810.11-1810.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1767.11-1767.34" + attribute \src "ls180.v:1809.11-1809.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1756.11-1756.45" + attribute \src "ls180.v:1798.11-1798.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1755.11-1755.40" + attribute \src "ls180.v:1797.11-1797.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1752.11-1752.45" + attribute \src "ls180.v:1794.11-1794.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1751.11-1751.40" + attribute \src "ls180.v:1793.11-1793.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1764.5-1764.39" + attribute \src "ls180.v:1806.5-1806.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1763.5-1763.34" + attribute \src "ls180.v:1805.5-1805.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1772.11-1772.46" + attribute \src "ls180.v:1814.11-1814.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1771.11-1771.41" + attribute \src "ls180.v:1813.11-1813.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1748.5-1748.39" + attribute \src "ls180.v:1790.5-1790.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1747.5-1747.34" + attribute \src "ls180.v:1789.5-1789.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1848.5-1848.23" + attribute \src "ls180.v:1886.5-1886.23" wire \builder_shared_ack - attribute \src "ls180.v:1842.13-1842.31" + attribute \src "ls180.v:1880.13-1880.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:1851.12-1851.30" + attribute \src "ls180.v:1889.12-1889.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:1850.12-1850.30" + attribute \src "ls180.v:1888.12-1888.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:1846.6-1846.24" + attribute \src "ls180.v:1884.6-1884.24" wire \builder_shared_cyc - attribute \src "ls180.v:1844.12-1844.32" + attribute \src "ls180.v:1882.12-1882.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1843.13-1843.33" + attribute \src "ls180.v:1881.13-1881.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1852.6-1852.24" + attribute \src "ls180.v:1890.6-1890.24" wire \builder_shared_err - attribute \src "ls180.v:1845.12-1845.30" + attribute \src "ls180.v:1883.12-1883.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:1847.6-1847.24" + attribute \src "ls180.v:1885.6-1885.24" wire \builder_shared_stb - attribute \src "ls180.v:1849.6-1849.23" + attribute \src "ls180.v:1887.6-1887.23" wire \builder_shared_we - attribute \src "ls180.v:1855.11-1855.28" + attribute \src "ls180.v:1893.11-1893.28" wire width 5 \builder_slave_sel - attribute \src "ls180.v:1856.11-1856.30" + attribute \src "ls180.v:1894.11-1894.30" wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1744.11-1744.40" + attribute \src "ls180.v:1782.11-1782.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1743.11-1743.35" + attribute \src "ls180.v:1781.11-1781.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1824.11-1824.40" + attribute \src "ls180.v:1786.11-1786.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1823.11-1823.35" + attribute \src "ls180.v:1785.11-1785.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2539.11-2539.24" + attribute \src "ls180.v:2590.11-2590.24" wire width 2 \builder_state - attribute \src "ls180.v:2592.5-2592.32" + attribute \src "ls180.v:2643.5-2643.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2593.5-2593.32" + attribute \src "ls180.v:2644.5-2644.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2585.11-2585.40" + attribute \src "ls180.v:2636.11-2636.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2586.12-2586.41" + attribute \src "ls180.v:2637.12-2637.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2587.5-2587.34" + attribute \src "ls180.v:2638.5-2638.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2588.5-2588.34" + attribute \src "ls180.v:2639.5-2639.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2589.5-2589.34" + attribute \src "ls180.v:2640.5-2640.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2590.5-2590.34" + attribute \src "ls180.v:2641.5-2641.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2591.5-2591.34" + attribute \src "ls180.v:2642.5-2642.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1858.6-1858.18" + attribute \src "ls180.v:1896.6-1896.18" wire \builder_wait - attribute \src "ls180.v:28.19-28.23" - wire width 3 input 24 \eint - attribute \src "ls180.v:21.20-21.26" - wire width 16 input 17 \gpio_i - attribute \src "ls180.v:22.21-22.27" - wire width 16 output 18 \gpio_o - attribute \src "ls180.v:23.21-23.28" - wire width 16 output 19 \gpio_oe - attribute \src "ls180.v:30.13-30.21" - wire input 26 \jtag_tck - attribute \src "ls180.v:31.13-31.21" - wire input 27 \jtag_tdi - attribute \src "ls180.v:32.14-32.22" - wire output 28 \jtag_tdo - attribute \src "ls180.v:29.13-29.21" - wire input 25 \jtag_tms - attribute \src "ls180.v:1664.13-1664.37" - wire width 16 \libresocsim_clk_divider0 - attribute \src "ls180.v:1686.12-1686.36" - wire width 16 \libresocsim_clk_divider1 - attribute \src "ls180.v:1681.5-1681.27" - wire \libresocsim_clk_enable - attribute \src "ls180.v:1688.6-1688.26" - wire \libresocsim_clk_fall - attribute \src "ls180.v:1687.6-1687.26" - wire \libresocsim_clk_rise - attribute \src "ls180.v:1668.5-1668.27" - wire \libresocsim_control_re - attribute \src "ls180.v:1667.12-1667.39" - wire width 16 \libresocsim_control_storage - attribute \src "ls180.v:1683.11-1683.28" - wire width 3 \libresocsim_count - attribute \src "ls180.v:1825.11-1825.50" - wire width 3 \libresocsim_count_spimaster1_next_value - attribute \src "ls180.v:1826.5-1826.47" - wire \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:1662.6-1662.20" - wire \libresocsim_cs - attribute \src "ls180.v:1682.5-1682.26" - wire \libresocsim_cs_enable - attribute \src "ls180.v:1678.5-1678.22" - wire \libresocsim_cs_re - attribute \src "ls180.v:1677.5-1677.27" - wire \libresocsim_cs_storage - attribute \src "ls180.v:1658.5-1658.22" - wire \libresocsim_done0 - attribute \src "ls180.v:1669.6-1669.23" - wire \libresocsim_done1 - attribute \src "ls180.v:1659.5-1659.20" - wire \libresocsim_irq - attribute \src "ls180.v:1657.12-1657.31" - wire width 8 \libresocsim_length0 - attribute \src "ls180.v:1666.12-1666.31" - wire width 8 \libresocsim_length1 - attribute \src "ls180.v:1663.6-1663.26" - wire \libresocsim_loopback - attribute \src "ls180.v:1680.5-1680.28" - wire \libresocsim_loopback_re - attribute \src "ls180.v:1679.5-1679.33" - wire \libresocsim_loopback_storage - attribute \src "ls180.v:1661.11-1661.27" - wire width 8 \libresocsim_miso - attribute \src "ls180.v:1691.11-1691.32" - wire width 8 \libresocsim_miso_data - attribute \src "ls180.v:1685.5-1685.27" - wire \libresocsim_miso_latch - attribute \src "ls180.v:1674.12-1674.35" - wire width 8 \libresocsim_miso_status - attribute \src "ls180.v:1675.6-1675.25" - wire \libresocsim_miso_we - attribute \src "ls180.v:1660.12-1660.28" - wire width 8 \libresocsim_mosi - attribute \src "ls180.v:1689.11-1689.32" - wire width 8 \libresocsim_mosi_data - attribute \src "ls180.v:1684.5-1684.27" - wire \libresocsim_mosi_latch - attribute \src "ls180.v:1673.5-1673.24" - wire \libresocsim_mosi_re - attribute \src "ls180.v:1690.11-1690.31" - wire width 3 \libresocsim_mosi_sel - attribute \src "ls180.v:1672.11-1672.35" - wire width 8 \libresocsim_mosi_storage - attribute \src "ls180.v:1693.5-1693.19" - wire \libresocsim_re - attribute \src "ls180.v:1676.6-1676.21" - wire \libresocsim_sel - attribute \src "ls180.v:1656.6-1656.24" - wire \libresocsim_start0 - attribute \src "ls180.v:1665.5-1665.23" - wire \libresocsim_start1 - attribute \src "ls180.v:1670.6-1670.31" - wire \libresocsim_status_status - attribute \src "ls180.v:1671.6-1671.27" - wire \libresocsim_status_we - attribute \src "ls180.v:1692.12-1692.31" - wire width 16 \libresocsim_storage - attribute \src "ls180.v:806.6-806.18" + attribute \src "ls180.v:37.20-37.24" + wire width 3 output 33 \eint + attribute \src "ls180.v:154.11-154.17" + wire width 3 \eint_1 + attribute \src "ls180.v:5.21-5.27" + wire width 16 output 1 \gpio_i + attribute \src "ls180.v:6.21-6.27" + wire width 16 output 2 \gpio_o + attribute \src "ls180.v:7.21-7.28" + wire width 16 output 3 \gpio_oe + attribute \src "ls180.v:17.14-17.21" + wire output 13 \i2c_scl + attribute \src "ls180.v:18.14-18.23" + wire output 14 \i2c_sda_i + attribute \src "ls180.v:19.14-19.23" + wire output 15 \i2c_sda_o + attribute \src "ls180.v:20.14-20.24" + wire output 16 \i2c_sda_oe + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tck + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tdi + attribute \src "ls180.v:50.14-50.22" + wire output 46 \jtag_tdo + attribute \src "ls180.v:47.13-47.21" + wire input 43 \jtag_tms + attribute \src "ls180.v:836.6-836.18" wire \main_ack_cmd - attribute \src "ls180.v:808.6-808.20" + attribute \src "ls180.v:838.6-838.20" wire \main_ack_rdata - attribute \src "ls180.v:807.6-807.20" + attribute \src "ls180.v:837.6-837.20" wire \main_ack_wdata - attribute \src "ls180.v:804.5-804.22" + attribute \src "ls180.v:834.5-834.22" wire \main_cmd_consumed - attribute \src "ls180.v:801.5-801.27" + attribute \src "ls180.v:831.5-831.27" wire \main_converter_counter - attribute \src "ls180.v:1741.5-1741.48" + attribute \src "ls180.v:1779.5-1779.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1742.5-1742.51" + attribute \src "ls180.v:1780.5-1780.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:803.12-803.32" + attribute \src "ls180.v:833.12-833.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:802.6-802.26" + attribute \src "ls180.v:832.6-832.26" wire \main_converter_reset - attribute \src "ls180.v:800.5-800.24" + attribute \src "ls180.v:830.5-830.24" wire \main_converter_skip - attribute \src "ls180.v:230.6-230.23" + attribute \src "ls180.v:260.6-260.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:221.13-221.32" + attribute \src "ls180.v:251.13-251.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:222.12-222.28" + attribute \src "ls180.v:252.12-252.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:223.6-223.23" + attribute \src "ls180.v:253.6-253.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:227.6-227.21" + attribute \src "ls180.v:257.6-257.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:224.6-224.22" + attribute \src "ls180.v:254.6-254.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:228.6-228.21" + attribute \src "ls180.v:258.6-258.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:225.6-225.23" + attribute \src "ls180.v:255.6-255.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:235.12-235.30" + attribute \src "ls180.v:265.12-265.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:234.6-234.27" + attribute \src "ls180.v:264.6-264.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:236.5-236.29" + attribute \src "ls180.v:266.5-266.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:229.6-229.25" + attribute \src "ls180.v:259.6-259.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:226.6-226.22" + attribute \src "ls180.v:256.6-256.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:231.13-231.31" + attribute \src "ls180.v:261.13-261.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:232.6-232.27" + attribute \src "ls180.v:262.6-262.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:233.12-233.35" + attribute \src "ls180.v:263.12-263.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:997.12-997.22" - wire width 42 \main_dummy - attribute \src "ls180.v:952.5-952.20" + attribute \src "ls180.v:1065.12-1065.22" + wire width 36 \main_dummy + attribute \src "ls180.v:982.5-982.20" wire \main_gpio_oe_re - attribute \src "ls180.v:951.12-951.32" + attribute \src "ls180.v:981.12-981.32" wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:956.5-956.21" + attribute \src "ls180.v:986.5-986.21" wire \main_gpio_out_re - attribute \src "ls180.v:955.12-955.33" + attribute \src "ls180.v:985.12-985.33" wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:957.13-957.29" + attribute \src "ls180.v:987.13-987.29" wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:958.13-958.29" + attribute \src "ls180.v:988.13-988.29" wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:959.13-959.30" + attribute \src "ls180.v:989.13-989.30" wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:953.12-953.28" + attribute \src "ls180.v:983.12-983.28" wire width 16 \main_gpio_status - attribute \src "ls180.v:954.6-954.18" + attribute \src "ls180.v:984.6-984.18" wire \main_gpio_we - attribute \src "ls180.v:220.5-220.17" + attribute \src "ls180.v:1087.6-1087.17" + wire \main_i2c_oe + attribute \src "ls180.v:1090.5-1090.16" + wire \main_i2c_re + attribute \src "ls180.v:1086.6-1086.18" + wire \main_i2c_scl + attribute \src "ls180.v:1088.6-1088.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1091.6-1091.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1092.6-1092.21" + wire \main_i2c_status + attribute \src "ls180.v:1089.11-1089.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1093.6-1093.17" + wire \main_i2c_we + attribute \src "ls180.v:250.5-250.17" wire \main_int_rst - attribute \src "ls180.v:1477.6-1477.29" + attribute \src "ls180.v:1553.6-1553.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1471.13-1471.36" + attribute \src "ls180.v:1547.13-1547.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1480.11-1480.34" + attribute \src "ls180.v:1556.11-1556.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1479.11-1479.34" + attribute \src "ls180.v:1555.11-1555.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1475.6-1475.29" + attribute \src "ls180.v:1551.6-1551.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1473.13-1473.38" + attribute \src "ls180.v:1549.13-1549.38" wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1472.13-1472.38" + attribute \src "ls180.v:1548.13-1548.38" wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1481.6-1481.29" + attribute \src "ls180.v:1557.6-1557.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1474.12-1474.35" + attribute \src "ls180.v:1550.12-1550.35" wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1476.6-1476.29" + attribute \src "ls180.v:1552.6-1552.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1478.6-1478.28" + attribute \src "ls180.v:1554.6-1554.28" wire \main_interface0_bus_we - attribute \src "ls180.v:1568.6-1568.29" + attribute \src "ls180.v:1644.6-1644.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1562.12-1562.35" + attribute \src "ls180.v:1638.12-1638.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1571.11-1571.34" + attribute \src "ls180.v:1647.11-1647.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1570.11-1570.34" + attribute \src "ls180.v:1646.11-1646.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1566.5-1566.28" + attribute \src "ls180.v:1642.5-1642.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1564.13-1564.38" + attribute \src "ls180.v:1640.13-1640.38" wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1563.12-1563.37" + attribute \src "ls180.v:1639.12-1639.37" wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1572.6-1572.29" + attribute \src "ls180.v:1648.6-1648.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1565.11-1565.34" + attribute \src "ls180.v:1641.11-1641.34" wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1567.5-1567.28" + attribute \src "ls180.v:1643.5-1643.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1569.5-1569.27" + attribute \src "ls180.v:1645.5-1645.27" wire \main_interface1_bus_we - attribute \src "ls180.v:186.12-186.32" + attribute \src "ls180.v:216.12-216.32" wire width 7 \main_libresocsim_adr - attribute \src "ls180.v:56.6-56.32" + attribute \src "ls180.v:61.6-61.32" wire \main_libresocsim_bus_error - attribute \src "ls180.v:57.12-57.39" + attribute \src "ls180.v:62.12-62.39" wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:53.13-53.47" + attribute \src "ls180.v:58.13-58.47" wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:54.6-54.36" + attribute \src "ls180.v:59.6-59.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:142.5-142.40" + attribute \src "ls180.v:172.5-172.40" wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1696.5-1696.62" + attribute \src "ls180.v:1734.5-1734.62" wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1697.5-1697.65" + attribute \src "ls180.v:1735.5-1735.65" wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:144.12-144.45" + attribute \src "ls180.v:174.12-174.45" wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:143.6-143.39" + attribute \src "ls180.v:173.6-173.39" wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:141.5-141.37" + attribute \src "ls180.v:171.5-171.37" wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:157.5-157.40" + attribute \src "ls180.v:187.5-187.40" wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1700.5-1700.62" + attribute \src "ls180.v:1738.5-1738.62" wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1701.5-1701.65" + attribute \src "ls180.v:1739.5-1739.65" wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:159.12-159.45" + attribute \src "ls180.v:189.12-189.45" wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:158.6-158.39" + attribute \src "ls180.v:188.6-188.39" wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:156.5-156.37" + attribute \src "ls180.v:186.5-186.37" wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:172.5-172.40" + attribute \src "ls180.v:202.5-202.40" wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1704.5-1704.62" + attribute \src "ls180.v:1742.5-1742.62" wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1705.5-1705.65" + attribute \src "ls180.v:1743.5-1743.65" wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:174.12-174.45" + attribute \src "ls180.v:204.12-204.45" wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:173.6-173.39" + attribute \src "ls180.v:203.6-203.39" wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:171.5-171.37" + attribute \src "ls180.v:201.5-201.37" wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:187.13-187.35" + attribute \src "ls180.v:217.13-217.35" wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:189.13-189.35" + attribute \src "ls180.v:219.13-219.35" wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:195.5-195.27" + attribute \src "ls180.v:225.5-225.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:194.5-194.32" + attribute \src "ls180.v:224.5-224.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:211.6-211.45" + attribute \src "ls180.v:241.6-241.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:210.6-210.46" + attribute \src "ls180.v:240.6-240.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:213.6-213.45" + attribute \src "ls180.v:243.6-243.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:212.6-212.46" + attribute \src "ls180.v:242.6-242.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:215.5-215.37" + attribute \src "ls180.v:245.5-245.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:207.6-207.44" + attribute \src "ls180.v:237.6-237.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:206.6-206.45" + attribute \src "ls180.v:236.6-236.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:209.6-209.44" + attribute \src "ls180.v:239.6-239.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:208.6-208.45" + attribute \src "ls180.v:238.6-238.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:214.5-214.42" + attribute \src "ls180.v:244.5-244.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:136.6-136.57" + attribute \src "ls180.v:166.6-166.57" wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:130.12-130.63" + attribute \src "ls180.v:160.12-160.63" wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:139.11-139.62" + attribute \src "ls180.v:169.11-169.62" wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:138.11-138.62" + attribute \src "ls180.v:168.11-168.62" wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:134.5-134.56" + attribute \src "ls180.v:164.5-164.56" wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:132.13-132.66" + attribute \src "ls180.v:162.13-162.66" wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:131.12-131.65" + attribute \src "ls180.v:161.12-161.65" wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:140.6-140.57" + attribute \src "ls180.v:170.6-170.57" wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:133.11-133.62" + attribute \src "ls180.v:163.11-163.62" wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:135.5-135.56" + attribute \src "ls180.v:165.5-165.56" wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:137.5-137.55" + attribute \src "ls180.v:167.5-167.55" wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:151.6-151.57" + attribute \src "ls180.v:181.6-181.57" wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:145.12-145.63" + attribute \src "ls180.v:175.12-175.63" wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:154.11-154.62" + attribute \src "ls180.v:184.11-184.62" wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:153.11-153.62" + attribute \src "ls180.v:183.11-183.62" wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:149.5-149.56" + attribute \src "ls180.v:179.5-179.56" wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:147.13-147.66" + attribute \src "ls180.v:177.13-177.66" wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:146.12-146.65" + attribute \src "ls180.v:176.12-176.65" wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:155.6-155.57" + attribute \src "ls180.v:185.6-185.57" wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:148.11-148.62" + attribute \src "ls180.v:178.11-178.62" wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:150.5-150.56" + attribute \src "ls180.v:180.5-180.56" wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:152.5-152.55" + attribute \src "ls180.v:182.5-182.55" wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:166.6-166.57" + attribute \src "ls180.v:196.6-196.57" wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:160.12-160.63" + attribute \src "ls180.v:190.12-190.63" wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:169.11-169.62" + attribute \src "ls180.v:199.11-199.62" wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:168.11-168.62" + attribute \src "ls180.v:198.11-198.62" wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:164.5-164.56" + attribute \src "ls180.v:194.5-194.56" wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:162.13-162.66" + attribute \src "ls180.v:192.13-192.66" wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:161.12-161.65" + attribute \src "ls180.v:191.12-191.65" wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:170.6-170.57" + attribute \src "ls180.v:200.6-200.57" wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:163.11-163.62" + attribute \src "ls180.v:193.11-193.62" wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:165.5-165.56" + attribute \src "ls180.v:195.5-195.56" wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:167.5-167.55" + attribute \src "ls180.v:197.5-197.55" wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:200.6-200.26" + attribute \src "ls180.v:230.6-230.26" wire \main_libresocsim_irq - attribute \src "ls180.v:117.6-117.32" + attribute \src "ls180.v:122.6-122.32" wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:118.6-118.32" + attribute \src "ls180.v:123.6-123.32" wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:119.13-119.39" + attribute \src "ls180.v:124.13-124.39" wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:122.13-122.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_i - attribute \src "ls180.v:123.13-123.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_o - attribute \src "ls180.v:124.13-124.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager0_gpio0_oe - attribute \src "ls180.v:121.6-121.59" - wire \main_libresocsim_libresoc_constraintmanager0_uart0_rx - attribute \src "ls180.v:120.5-120.58" - wire \main_libresocsim_libresoc_constraintmanager0_uart0_tx - attribute \src "ls180.v:127.13-127.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_i - attribute \src "ls180.v:128.13-128.65" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_o - attribute \src "ls180.v:129.13-129.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager1_gpio0_oe - attribute \src "ls180.v:126.6-126.59" - wire \main_libresocsim_libresoc_constraintmanager1_uart0_rx - attribute \src "ls180.v:125.6-125.59" - wire \main_libresocsim_libresoc_constraintmanager1_uart0_tx - attribute \src "ls180.v:66.5-66.39" + attribute \src "ls180.v:126.12-126.45" + wire width 3 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:127.12-127.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:128.13-128.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:129.13-129.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:134.6-134.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:135.5-135.62" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:136.6-136.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:137.6-137.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:130.6-130.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:131.5-131.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:132.6-132.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:133.6-133.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:142.13-142.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:151.12-151.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:148.6-148.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:150.6-150.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:149.6-149.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:152.12-152.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:143.12-143.70" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:144.13-144.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:145.6-145.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:147.6-147.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:146.6-146.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:138.6-138.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:140.6-140.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:141.5-141.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:139.6-139.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:156.6-156.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:158.6-158.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:159.5-159.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:157.6-157.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:71.5-71.39" wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:60.13-60.47" + attribute \src "ls180.v:65.13-65.47" wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:69.12-69.46" + attribute \src "ls180.v:74.12-74.46" wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:68.12-68.46" + attribute \src "ls180.v:73.12-73.46" wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:64.6-64.40" + attribute \src "ls180.v:69.6-69.40" wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:62.13-62.49" + attribute \src "ls180.v:67.13-67.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:61.13-61.49" + attribute \src "ls180.v:66.13-66.49" wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:70.5-70.39" + attribute \src "ls180.v:75.5-75.39" wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:63.12-63.46" + attribute \src "ls180.v:68.12-68.46" wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:65.6-65.40" + attribute \src "ls180.v:70.6-70.40" wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:67.6-67.39" + attribute \src "ls180.v:72.6-72.39" wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:77.5-77.39" + attribute \src "ls180.v:82.5-82.39" wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:71.13-71.47" + attribute \src "ls180.v:76.13-76.47" wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:80.12-80.46" + attribute \src "ls180.v:85.12-85.46" wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:79.12-79.46" + attribute \src "ls180.v:84.12-84.46" wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:75.6-75.40" + attribute \src "ls180.v:80.6-80.40" wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:73.13-73.49" + attribute \src "ls180.v:78.13-78.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:72.13-72.49" + attribute \src "ls180.v:77.13-77.49" wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:81.5-81.39" + attribute \src "ls180.v:86.5-86.39" wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:74.12-74.46" + attribute \src "ls180.v:79.12-79.46" wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:76.6-76.40" + attribute \src "ls180.v:81.6-81.40" wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:78.6-78.39" + attribute \src "ls180.v:83.6-83.39" wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:59.12-59.47" + attribute \src "ls180.v:64.12-64.47" wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:113.6-113.40" + attribute \src "ls180.v:118.6-118.40" wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:115.6-115.40" + attribute \src "ls180.v:120.6-120.40" wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:116.6-116.40" + attribute \src "ls180.v:121.6-121.40" wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:114.6-114.40" + attribute \src "ls180.v:119.6-119.40" wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:110.5-110.42" + attribute \src "ls180.v:115.5-115.42" wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:104.13-104.50" + attribute \src "ls180.v:109.13-109.50" wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:108.6-108.43" + attribute \src "ls180.v:113.6-113.43" wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:106.13-106.52" + attribute \src "ls180.v:111.13-111.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:105.13-105.52" + attribute \src "ls180.v:110.13-110.52" wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:112.5-112.42" + attribute \src "ls180.v:117.5-117.42" wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:107.12-107.49" + attribute \src "ls180.v:112.12-112.49" wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:109.6-109.43" + attribute \src "ls180.v:114.6-114.43" wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:111.6-111.42" + attribute \src "ls180.v:116.6-116.42" wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:58.6-58.37" + attribute \src "ls180.v:125.6-125.40" + wire \main_libresocsim_libresoc_pll_48_o + attribute \src "ls180.v:63.6-63.37" wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:88.6-88.44" + attribute \src "ls180.v:93.6-93.44" wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:82.13-82.51" + attribute \src "ls180.v:87.13-87.51" wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:91.12-91.50" + attribute \src "ls180.v:96.12-96.50" wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:90.12-90.50" + attribute \src "ls180.v:95.12-95.50" wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:86.6-86.44" + attribute \src "ls180.v:91.6-91.44" wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:84.13-84.53" + attribute \src "ls180.v:89.13-89.53" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:83.13-83.53" + attribute \src "ls180.v:88.13-88.53" wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:92.6-92.44" + attribute \src "ls180.v:97.6-97.44" wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:85.12-85.50" + attribute \src "ls180.v:90.12-90.50" wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:87.6-87.44" + attribute \src "ls180.v:92.6-92.44" wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:89.6-89.43" + attribute \src "ls180.v:94.6-94.43" wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:99.6-99.44" + attribute \src "ls180.v:104.6-104.44" wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:93.13-93.51" + attribute \src "ls180.v:98.13-98.51" wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:102.12-102.50" + attribute \src "ls180.v:107.12-107.50" wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:101.12-101.50" + attribute \src "ls180.v:106.12-106.50" wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:97.6-97.44" + attribute \src "ls180.v:102.6-102.44" wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:95.13-95.53" + attribute \src "ls180.v:100.13-100.53" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:94.13-94.53" + attribute \src "ls180.v:99.13-99.53" wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:103.6-103.44" + attribute \src "ls180.v:108.6-108.44" wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:96.12-96.50" + attribute \src "ls180.v:101.12-101.50" wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:98.6-98.44" + attribute \src "ls180.v:103.6-103.44" wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:100.6-100.43" + attribute \src "ls180.v:105.6-105.43" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:191.5-191.29" + attribute \src "ls180.v:221.5-221.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:190.12-190.41" + attribute \src "ls180.v:220.12-220.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:181.5-181.33" + attribute \src "ls180.v:211.5-211.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:175.13-175.41" + attribute \src "ls180.v:205.13-205.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:184.12-184.40" + attribute \src "ls180.v:214.12-214.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:183.12-183.40" + attribute \src "ls180.v:213.12-213.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:179.6-179.34" + attribute \src "ls180.v:209.6-209.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:177.13-177.43" + attribute \src "ls180.v:207.13-207.43" wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:176.13-176.43" + attribute \src "ls180.v:206.13-206.43" wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:185.5-185.33" + attribute \src "ls180.v:215.5-215.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:178.12-178.40" + attribute \src "ls180.v:208.12-208.40" wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:180.6-180.34" + attribute \src "ls180.v:210.6-210.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:182.6-182.33" + attribute \src "ls180.v:212.6-212.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:193.5-193.31" + attribute \src "ls180.v:223.5-223.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:192.12-192.43" + attribute \src "ls180.v:222.12-222.43" wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:55.6-55.28" + attribute \src "ls180.v:60.6-60.28" wire \main_libresocsim_reset - attribute \src "ls180.v:50.5-50.30" + attribute \src "ls180.v:55.5-55.30" wire \main_libresocsim_reset_re - attribute \src "ls180.v:49.5-49.35" + attribute \src "ls180.v:54.5-54.35" wire \main_libresocsim_reset_storage - attribute \src "ls180.v:52.5-52.32" + attribute \src "ls180.v:57.5-57.32" wire \main_libresocsim_scratch_re - attribute \src "ls180.v:51.12-51.44" + attribute \src "ls180.v:56.12-56.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:197.5-197.37" + attribute \src "ls180.v:227.5-227.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:196.5-196.42" + attribute \src "ls180.v:226.5-226.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:216.12-216.34" + attribute \src "ls180.v:246.12-246.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:198.12-198.41" + attribute \src "ls180.v:228.12-228.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:199.6-199.31" + attribute \src "ls180.v:229.6-229.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:188.11-188.30" + attribute \src "ls180.v:218.11-218.30" wire width 4 \main_libresocsim_we - attribute \src "ls180.v:204.5-204.32" + attribute \src "ls180.v:234.5-234.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:205.5-205.38" + attribute \src "ls180.v:235.5-235.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:202.5-202.34" + attribute \src "ls180.v:232.5-232.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:201.6-201.34" + attribute \src "ls180.v:231.6-231.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:203.6-203.35" + attribute \src "ls180.v:233.6-233.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:798.6-798.26" + attribute \src "ls180.v:828.6-828.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:792.12-792.32" + attribute \src "ls180.v:822.12-822.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:796.5-796.25" + attribute \src "ls180.v:826.5-826.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:794.13-794.35" + attribute \src "ls180.v:824.13-824.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:793.12-793.34" + attribute \src "ls180.v:823.12-823.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:795.11-795.31" + attribute \src "ls180.v:825.11-825.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:797.5-797.25" + attribute \src "ls180.v:827.5-827.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:799.5-799.24" + attribute \src "ls180.v:829.5-829.24" wire \main_litedram_wb_we - attribute \src "ls180.v:996.13-996.20" - wire width 42 \main_nc - attribute \src "ls180.v:827.12-827.37" - wire width 32 \main_phase_accumulator_rx - attribute \src "ls180.v:817.12-817.37" - wire width 32 \main_phase_accumulator_tx - attribute \src "ls180.v:771.6-771.24" + attribute \src "ls180.v:1064.13-1064.20" + wire width 36 \main_nc + attribute \src "ls180.v:801.6-801.24" wire \main_port_cmd_last - attribute \src "ls180.v:773.13-773.39" + attribute \src "ls180.v:803.13-803.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:772.6-772.30" + attribute \src "ls180.v:802.6-802.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:770.6-770.25" + attribute \src "ls180.v:800.6-800.25" wire \main_port_cmd_ready - attribute \src "ls180.v:769.6-769.25" + attribute \src "ls180.v:799.6-799.25" wire \main_port_cmd_valid - attribute \src "ls180.v:768.6-768.21" + attribute \src "ls180.v:798.6-798.21" wire \main_port_flush - attribute \src "ls180.v:780.13-780.41" + attribute \src "ls180.v:810.13-810.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:779.6-779.27" + attribute \src "ls180.v:809.6-809.27" wire \main_port_rdata_ready - attribute \src "ls180.v:778.6-778.27" + attribute \src "ls180.v:808.6-808.27" wire \main_port_rdata_valid - attribute \src "ls180.v:776.13-776.41" + attribute \src "ls180.v:806.13-806.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:777.12-777.38" + attribute \src "ls180.v:807.12-807.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:775.6-775.27" + attribute \src "ls180.v:805.6-805.27" wire \main_port_wdata_ready - attribute \src "ls180.v:774.6-774.27" + attribute \src "ls180.v:804.6-804.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1001.12-1001.29" + attribute \src "ls180.v:1069.12-1069.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:998.6-998.22" + attribute \src "ls180.v:1066.6-1066.22" wire \main_pwm0_enable - attribute \src "ls180.v:1003.5-1003.24" + attribute \src "ls180.v:1071.5-1071.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1002.5-1002.29" + attribute \src "ls180.v:1070.5-1070.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1000.13-1000.29" + attribute \src "ls180.v:1068.13-1068.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1007.5-1007.24" + attribute \src "ls180.v:1075.5-1075.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1006.12-1006.36" + attribute \src "ls180.v:1074.12-1074.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:999.13-999.28" + attribute \src "ls180.v:1067.13-1067.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1005.5-1005.23" + attribute \src "ls180.v:1073.5-1073.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1004.12-1004.35" + attribute \src "ls180.v:1072.12-1072.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1011.12-1011.29" + attribute \src "ls180.v:1079.12-1079.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1008.6-1008.22" + attribute \src "ls180.v:1076.6-1076.22" wire \main_pwm1_enable - attribute \src "ls180.v:1013.5-1013.24" + attribute \src "ls180.v:1081.5-1081.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1012.5-1012.29" + attribute \src "ls180.v:1080.5-1080.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1010.13-1010.29" + attribute \src "ls180.v:1078.13-1078.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1017.5-1017.24" + attribute \src "ls180.v:1085.5-1085.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1016.12-1016.36" + attribute \src "ls180.v:1084.12-1084.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1009.13-1009.28" + attribute \src "ls180.v:1077.13-1077.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1015.5-1015.23" + attribute \src "ls180.v:1083.5-1083.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1014.12-1014.35" + attribute \src "ls180.v:1082.12-1082.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:237.11-237.25" + attribute \src "ls180.v:267.11-267.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:810.5-810.12" - wire \main_re - attribute \src "ls180.v:828.6-828.13" - wire \main_rx - attribute \src "ls180.v:831.11-831.27" - wire width 4 \main_rx_bitcount - attribute \src "ls180.v:832.5-832.17" - wire \main_rx_busy - attribute \src "ls180.v:829.5-829.14" - wire \main_rx_r - attribute \src "ls180.v:830.11-830.22" - wire width 8 \main_rx_reg - attribute \src "ls180.v:1531.11-1531.43" + attribute \src "ls180.v:1607.11-1607.43" wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1532.6-1532.42" + attribute \src "ls180.v:1608.6-1608.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1522.6-1522.43" + attribute \src "ls180.v:1598.6-1598.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1523.6-1523.42" + attribute \src "ls180.v:1599.6-1599.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1524.12-1524.56" + attribute \src "ls180.v:1600.12-1600.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1521.6-1521.43" + attribute \src "ls180.v:1597.6-1597.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1520.6-1520.43" + attribute \src "ls180.v:1596.6-1596.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1527.5-1527.44" + attribute \src "ls180.v:1603.5-1603.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1528.5-1528.43" + attribute \src "ls180.v:1604.5-1604.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1529.12-1529.58" + attribute \src "ls180.v:1605.12-1605.58" wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1530.11-1530.70" + attribute \src "ls180.v:1606.11-1606.70" wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1526.6-1526.45" + attribute \src "ls180.v:1602.6-1602.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1525.6-1525.45" + attribute \src "ls180.v:1601.6-1601.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1533.5-1533.42" + attribute \src "ls180.v:1609.5-1609.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1506.11-1506.40" + attribute \src "ls180.v:1582.11-1582.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1511.6-1511.35" + attribute \src "ls180.v:1587.6-1587.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1515.6-1515.41" + attribute \src "ls180.v:1591.6-1591.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1516.6-1516.40" + attribute \src "ls180.v:1592.6-1592.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1514.12-1514.54" + attribute \src "ls180.v:1590.12-1590.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1518.6-1518.42" + attribute \src "ls180.v:1594.6-1594.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1519.6-1519.41" + attribute \src "ls180.v:1595.6-1595.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1517.12-1517.55" + attribute \src "ls180.v:1593.12-1593.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1503.11-1503.38" + attribute \src "ls180.v:1579.11-1579.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1505.11-1505.40" + attribute \src "ls180.v:1581.11-1581.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1512.12-1512.44" + attribute \src "ls180.v:1588.12-1588.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1513.12-1513.46" + attribute \src "ls180.v:1589.12-1589.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1504.5-1504.34" + attribute \src "ls180.v:1580.5-1580.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1489.6-1489.38" + attribute \src "ls180.v:1565.6-1565.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1490.6-1490.37" + attribute \src "ls180.v:1566.6-1566.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1491.12-1491.51" + attribute \src "ls180.v:1567.12-1567.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1488.6-1488.38" + attribute \src "ls180.v:1564.6-1564.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1487.6-1487.38" + attribute \src "ls180.v:1563.6-1563.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1494.6-1494.40" + attribute \src "ls180.v:1570.6-1570.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1495.6-1495.39" + attribute \src "ls180.v:1571.6-1571.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1496.12-1496.53" + attribute \src "ls180.v:1572.12-1572.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1493.6-1493.40" + attribute \src "ls180.v:1569.6-1569.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1492.6-1492.40" + attribute \src "ls180.v:1568.6-1568.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1501.12-1501.46" + attribute \src "ls180.v:1577.12-1577.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1502.12-1502.47" + attribute \src "ls180.v:1578.12-1578.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1499.6-1499.39" + attribute \src "ls180.v:1575.6-1575.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1500.6-1500.45" + attribute \src "ls180.v:1576.6-1576.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1497.6-1497.39" + attribute \src "ls180.v:1573.6-1573.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1498.6-1498.45" + attribute \src "ls180.v:1574.6-1574.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1507.11-1507.43" + attribute \src "ls180.v:1583.11-1583.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1508.12-1508.46" + attribute \src "ls180.v:1584.12-1584.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1510.12-1510.46" + attribute \src "ls180.v:1586.12-1586.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1509.6-1509.37" + attribute \src "ls180.v:1585.6-1585.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1484.6-1484.38" + attribute \src "ls180.v:1560.6-1560.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1485.6-1485.37" + attribute \src "ls180.v:1561.6-1561.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1541.12-1541.54" + attribute \src "ls180.v:1617.12-1617.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1486.12-1486.52" + attribute \src "ls180.v:1562.12-1562.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1542.12-1542.52" + attribute \src "ls180.v:1618.12-1618.52" wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1483.6-1483.39" + attribute \src "ls180.v:1559.6-1559.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1540.6-1540.39" + attribute \src "ls180.v:1616.6-1616.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1482.6-1482.39" + attribute \src "ls180.v:1558.6-1558.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1539.5-1539.38" + attribute \src "ls180.v:1615.5-1615.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1536.6-1536.42" + attribute \src "ls180.v:1612.6-1612.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1537.6-1537.41" + attribute \src "ls180.v:1613.6-1613.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1538.13-1538.56" + attribute \src "ls180.v:1614.13-1614.56" wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1535.6-1535.42" + attribute \src "ls180.v:1611.6-1611.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1534.6-1534.42" + attribute \src "ls180.v:1610.6-1610.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1558.13-1558.52" + attribute \src "ls180.v:1634.13-1634.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1549.5-1549.47" + attribute \src "ls180.v:1625.5-1625.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1548.12-1548.59" + attribute \src "ls180.v:1624.12-1624.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1553.5-1553.49" + attribute \src "ls180.v:1629.5-1629.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1552.5-1552.54" + attribute \src "ls180.v:1628.5-1628.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1560.13-1560.54" + attribute \src "ls180.v:1636.13-1636.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1551.5-1551.49" + attribute \src "ls180.v:1627.5-1627.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1550.12-1550.61" + attribute \src "ls180.v:1626.12-1626.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1557.5-1557.47" + attribute \src "ls180.v:1633.5-1633.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1556.5-1556.52" + attribute \src "ls180.v:1632.5-1632.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1559.12-1559.53" + attribute \src "ls180.v:1635.12-1635.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1813.12-1813.79" + attribute \src "ls180.v:1855.12-1855.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1814.5-1814.75" + attribute \src "ls180.v:1856.5-1856.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1561.6-1561.46" + attribute \src "ls180.v:1637.6-1637.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1545.6-1545.51" + attribute \src "ls180.v:1621.6-1621.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1546.6-1546.50" + attribute \src "ls180.v:1622.6-1622.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1547.13-1547.65" + attribute \src "ls180.v:1623.13-1623.65" wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1544.5-1544.50" + attribute \src "ls180.v:1620.5-1620.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1543.6-1543.51" + attribute \src "ls180.v:1619.6-1619.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1554.5-1554.46" + attribute \src "ls180.v:1630.5-1630.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1555.6-1555.43" + attribute \src "ls180.v:1631.6-1631.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1323.5-1323.31" + attribute \src "ls180.v:1399.5-1399.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1322.12-1322.43" + attribute \src "ls180.v:1398.12-1398.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1321.5-1321.32" + attribute \src "ls180.v:1397.5-1397.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1320.11-1320.43" + attribute \src "ls180.v:1396.11-1396.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1307.5-1307.32" + attribute \src "ls180.v:1383.5-1383.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1306.12-1306.44" + attribute \src "ls180.v:1382.12-1382.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1309.5-1309.31" + attribute \src "ls180.v:1385.5-1385.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1308.12-1308.43" + attribute \src "ls180.v:1384.12-1384.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1462.11-1462.32" + attribute \src "ls180.v:1538.11-1538.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1797.11-1797.55" + attribute \src "ls180.v:1839.11-1839.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1798.5-1798.52" + attribute \src "ls180.v:1840.5-1840.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1463.5-1463.25" + attribute \src "ls180.v:1539.5-1539.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1793.5-1793.48" + attribute \src "ls180.v:1835.5-1835.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1794.5-1794.51" + attribute \src "ls180.v:1836.5-1836.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1464.5-1464.26" + attribute \src "ls180.v:1540.5-1540.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1801.5-1801.49" + attribute \src "ls180.v:1843.5-1843.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1802.5-1802.52" + attribute \src "ls180.v:1844.5-1844.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1316.12-1316.40" + attribute \src "ls180.v:1392.12-1392.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1317.6-1317.30" + attribute \src "ls180.v:1393.6-1393.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1314.13-1314.44" + attribute \src "ls180.v:1390.13-1390.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1809.13-1809.67" + attribute \src "ls180.v:1851.13-1851.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1810.5-1810.62" + attribute \src "ls180.v:1852.5-1852.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1315.6-1315.33" + attribute \src "ls180.v:1391.6-1391.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1311.6-1311.28" + attribute \src "ls180.v:1387.6-1387.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1310.6-1310.29" + attribute \src "ls180.v:1386.6-1386.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1313.5-1313.27" + attribute \src "ls180.v:1389.5-1389.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1312.6-1312.29" + attribute \src "ls180.v:1388.6-1388.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1465.5-1465.28" + attribute \src "ls180.v:1541.5-1541.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1803.5-1803.51" + attribute \src "ls180.v:1845.5-1845.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1804.5-1804.54" + attribute \src "ls180.v:1846.5-1846.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1461.12-1461.32" + attribute \src "ls180.v:1537.12-1537.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1423.11-1423.40" + attribute \src "ls180.v:1499.11-1499.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1429.5-1429.39" + attribute \src "ls180.v:1505.5-1505.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1428.12-1428.46" + attribute \src "ls180.v:1504.12-1504.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1424.12-1424.50" + attribute \src "ls180.v:1500.12-1500.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1425.13-1425.51" + attribute \src "ls180.v:1501.13-1501.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1426.13-1426.51" + attribute \src "ls180.v:1502.13-1502.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1430.6-1430.43" + attribute \src "ls180.v:1506.6-1506.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1427.12-1427.46" + attribute \src "ls180.v:1503.12-1503.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1436.5-1436.39" + attribute \src "ls180.v:1512.5-1512.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1435.12-1435.46" + attribute \src "ls180.v:1511.12-1511.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1431.12-1431.50" + attribute \src "ls180.v:1507.12-1507.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1432.13-1432.51" + attribute \src "ls180.v:1508.13-1508.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1433.13-1433.51" + attribute \src "ls180.v:1509.13-1509.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1437.6-1437.43" + attribute \src "ls180.v:1513.6-1513.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1434.12-1434.46" + attribute \src "ls180.v:1510.12-1510.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1443.5-1443.39" + attribute \src "ls180.v:1519.5-1519.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1442.12-1442.46" + attribute \src "ls180.v:1518.12-1518.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1438.12-1438.50" + attribute \src "ls180.v:1514.12-1514.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1439.13-1439.51" + attribute \src "ls180.v:1515.13-1515.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1440.13-1440.51" + attribute \src "ls180.v:1516.13-1516.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1444.6-1444.43" + attribute \src "ls180.v:1520.6-1520.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1441.12-1441.46" + attribute \src "ls180.v:1517.12-1517.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1450.5-1450.39" + attribute \src "ls180.v:1526.5-1526.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1449.12-1449.46" + attribute \src "ls180.v:1525.12-1525.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1445.12-1445.50" + attribute \src "ls180.v:1521.12-1521.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1446.13-1446.51" + attribute \src "ls180.v:1522.13-1522.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1447.13-1447.51" + attribute \src "ls180.v:1523.13-1523.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1451.6-1451.43" + attribute \src "ls180.v:1527.6-1527.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1448.12-1448.46" + attribute \src "ls180.v:1524.12-1524.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1452.12-1452.45" + attribute \src "ls180.v:1528.12-1528.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1453.12-1453.45" + attribute \src "ls180.v:1529.12-1529.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1454.12-1454.45" + attribute \src "ls180.v:1530.12-1530.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1455.12-1455.45" + attribute \src "ls180.v:1531.12-1531.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1457.12-1457.43" + attribute \src "ls180.v:1533.12-1533.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1458.12-1458.43" + attribute \src "ls180.v:1534.12-1534.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1459.12-1459.43" + attribute \src "ls180.v:1535.12-1535.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1460.12-1460.43" + attribute \src "ls180.v:1536.12-1536.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1414.5-1414.41" + attribute \src "ls180.v:1490.5-1490.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1415.5-1415.40" + attribute \src "ls180.v:1491.5-1491.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1416.11-1416.54" + attribute \src "ls180.v:1492.11-1492.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1413.5-1413.41" + attribute \src "ls180.v:1489.5-1489.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1412.5-1412.41" + attribute \src "ls180.v:1488.5-1488.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1419.5-1419.43" + attribute \src "ls180.v:1495.5-1495.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1420.6-1420.43" + attribute \src "ls180.v:1496.6-1496.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1421.12-1421.57" + attribute \src "ls180.v:1497.12-1497.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1418.6-1418.44" + attribute \src "ls180.v:1494.6-1494.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1417.5-1417.43" + attribute \src "ls180.v:1493.5-1493.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1422.11-1422.40" + attribute \src "ls180.v:1498.11-1498.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1456.5-1456.36" + attribute \src "ls180.v:1532.5-1532.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1379.11-1379.41" + attribute \src "ls180.v:1455.11-1455.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1789.11-1789.80" + attribute \src "ls180.v:1831.11-1831.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1790.5-1790.77" + attribute \src "ls180.v:1832.5-1832.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1385.6-1385.41" + attribute \src "ls180.v:1461.6-1461.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1384.12-1384.47" + attribute \src "ls180.v:1460.12-1460.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1380.12-1380.51" + attribute \src "ls180.v:1456.12-1456.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1381.13-1381.52" + attribute \src "ls180.v:1457.13-1457.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1382.13-1382.52" + attribute \src "ls180.v:1458.13-1458.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1386.6-1386.44" + attribute \src "ls180.v:1462.6-1462.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1383.12-1383.47" + attribute \src "ls180.v:1459.12-1459.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1392.6-1392.41" + attribute \src "ls180.v:1468.6-1468.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1391.12-1391.47" + attribute \src "ls180.v:1467.12-1467.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1387.12-1387.51" + attribute \src "ls180.v:1463.12-1463.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1388.13-1388.52" + attribute \src "ls180.v:1464.13-1464.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1389.13-1389.52" + attribute \src "ls180.v:1465.13-1465.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1393.6-1393.44" + attribute \src "ls180.v:1469.6-1469.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1390.12-1390.47" + attribute \src "ls180.v:1466.12-1466.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1399.6-1399.41" + attribute \src "ls180.v:1475.6-1475.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1398.12-1398.47" + attribute \src "ls180.v:1474.12-1474.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1394.12-1394.51" + attribute \src "ls180.v:1470.12-1470.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1395.13-1395.52" + attribute \src "ls180.v:1471.13-1471.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1396.13-1396.52" + attribute \src "ls180.v:1472.13-1472.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1400.6-1400.44" + attribute \src "ls180.v:1476.6-1476.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1397.12-1397.47" + attribute \src "ls180.v:1473.12-1473.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1406.6-1406.41" + attribute \src "ls180.v:1482.6-1482.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1405.12-1405.47" + attribute \src "ls180.v:1481.12-1481.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1401.12-1401.51" + attribute \src "ls180.v:1477.12-1477.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1402.13-1402.52" + attribute \src "ls180.v:1478.13-1478.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1403.13-1403.52" + attribute \src "ls180.v:1479.13-1479.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1407.6-1407.44" + attribute \src "ls180.v:1483.6-1483.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1404.12-1404.47" + attribute \src "ls180.v:1480.12-1480.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1408.12-1408.46" + attribute \src "ls180.v:1484.12-1484.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1781.12-1781.85" + attribute \src "ls180.v:1823.12-1823.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1782.5-1782.81" + attribute \src "ls180.v:1824.5-1824.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1409.12-1409.46" + attribute \src "ls180.v:1485.12-1485.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1783.12-1783.85" + attribute \src "ls180.v:1825.12-1825.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1784.5-1784.81" + attribute \src "ls180.v:1826.5-1826.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1410.12-1410.46" + attribute \src "ls180.v:1486.12-1486.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1785.12-1785.85" + attribute \src "ls180.v:1827.12-1827.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1786.5-1786.81" + attribute \src "ls180.v:1828.5-1828.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1411.12-1411.46" + attribute \src "ls180.v:1487.12-1487.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1787.12-1787.85" + attribute \src "ls180.v:1829.12-1829.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1788.5-1788.81" + attribute \src "ls180.v:1830.5-1830.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1371.6-1371.43" + attribute \src "ls180.v:1447.6-1447.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1372.6-1372.42" + attribute \src "ls180.v:1448.6-1448.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1373.12-1373.56" + attribute \src "ls180.v:1449.12-1449.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1370.5-1370.42" + attribute \src "ls180.v:1446.5-1446.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1369.6-1369.43" + attribute \src "ls180.v:1445.6-1445.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1376.5-1376.44" + attribute \src "ls180.v:1452.5-1452.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1377.5-1377.43" + attribute \src "ls180.v:1453.5-1453.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1378.11-1378.57" + attribute \src "ls180.v:1454.11-1454.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1375.5-1375.44" + attribute \src "ls180.v:1451.5-1451.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1374.5-1374.44" + attribute \src "ls180.v:1450.5-1450.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1367.6-1367.35" + attribute \src "ls180.v:1443.6-1443.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1366.11-1366.40" + attribute \src "ls180.v:1442.11-1442.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1324.11-1324.44" + attribute \src "ls180.v:1400.11-1400.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1325.12-1325.45" + attribute \src "ls180.v:1401.12-1401.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1334.12-1334.46" + attribute \src "ls180.v:1410.12-1410.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1335.12-1335.46" + attribute \src "ls180.v:1411.12-1411.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1336.12-1336.46" + attribute \src "ls180.v:1412.12-1412.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1337.12-1337.46" + attribute \src "ls180.v:1413.12-1413.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1338.12-1338.46" + attribute \src "ls180.v:1414.12-1414.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1339.12-1339.46" + attribute \src "ls180.v:1415.12-1415.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1340.12-1340.46" + attribute \src "ls180.v:1416.12-1416.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1341.12-1341.46" + attribute \src "ls180.v:1417.12-1417.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1342.12-1342.46" + attribute \src "ls180.v:1418.12-1418.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1343.12-1343.46" + attribute \src "ls180.v:1419.12-1419.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1326.12-1326.45" + attribute \src "ls180.v:1402.12-1402.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1344.12-1344.46" + attribute \src "ls180.v:1420.12-1420.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1345.12-1345.46" + attribute \src "ls180.v:1421.12-1421.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1346.12-1346.46" + attribute \src "ls180.v:1422.12-1422.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1347.12-1347.46" + attribute \src "ls180.v:1423.12-1423.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1348.12-1348.46" + attribute \src "ls180.v:1424.12-1424.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1349.12-1349.46" + attribute \src "ls180.v:1425.12-1425.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1350.12-1350.46" + attribute \src "ls180.v:1426.12-1426.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1351.12-1351.46" + attribute \src "ls180.v:1427.12-1427.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1352.12-1352.46" + attribute \src "ls180.v:1428.12-1428.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1353.12-1353.46" + attribute \src "ls180.v:1429.12-1429.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1327.12-1327.45" + attribute \src "ls180.v:1403.12-1403.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1354.12-1354.46" + attribute \src "ls180.v:1430.12-1430.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1355.12-1355.46" + attribute \src "ls180.v:1431.12-1431.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1356.12-1356.46" + attribute \src "ls180.v:1432.12-1432.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1357.12-1357.46" + attribute \src "ls180.v:1433.12-1433.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1358.12-1358.46" + attribute \src "ls180.v:1434.12-1434.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1359.12-1359.46" + attribute \src "ls180.v:1435.12-1435.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1360.12-1360.46" + attribute \src "ls180.v:1436.12-1436.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1361.12-1361.46" + attribute \src "ls180.v:1437.12-1437.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1362.12-1362.46" + attribute \src "ls180.v:1438.12-1438.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1363.12-1363.46" + attribute \src "ls180.v:1439.12-1439.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1328.12-1328.45" + attribute \src "ls180.v:1404.12-1404.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1364.12-1364.46" + attribute \src "ls180.v:1440.12-1440.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1329.12-1329.45" + attribute \src "ls180.v:1405.12-1405.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1330.12-1330.45" + attribute \src "ls180.v:1406.12-1406.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1331.12-1331.45" + attribute \src "ls180.v:1407.12-1407.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1332.12-1332.45" + attribute \src "ls180.v:1408.12-1408.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1333.12-1333.45" + attribute \src "ls180.v:1409.12-1409.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1368.6-1368.38" + attribute \src "ls180.v:1444.6-1444.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1365.13-1365.42" + attribute \src "ls180.v:1441.13-1441.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1467.12-1467.34" + attribute \src "ls180.v:1543.12-1543.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1799.12-1799.57" + attribute \src "ls180.v:1841.12-1841.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1800.5-1800.53" + attribute \src "ls180.v:1842.5-1842.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1468.5-1468.26" + attribute \src "ls180.v:1544.5-1544.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1795.5-1795.49" + attribute \src "ls180.v:1837.5-1837.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1796.5-1796.52" + attribute \src "ls180.v:1838.5-1838.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1469.5-1469.27" + attribute \src "ls180.v:1545.5-1545.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1805.5-1805.50" + attribute \src "ls180.v:1847.5-1847.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1806.5-1806.53" + attribute \src "ls180.v:1848.5-1848.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1318.12-1318.41" + attribute \src "ls180.v:1394.12-1394.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1319.6-1319.31" + attribute \src "ls180.v:1395.6-1395.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1470.5-1470.29" + attribute \src "ls180.v:1546.5-1546.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1807.5-1807.52" + attribute \src "ls180.v:1849.5-1849.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1808.5-1808.55" + attribute \src "ls180.v:1850.5-1850.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1466.12-1466.33" + attribute \src "ls180.v:1542.12-1542.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1298.6-1298.33" + attribute \src "ls180.v:1374.6-1374.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1299.6-1299.32" + attribute \src "ls180.v:1375.6-1375.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1300.12-1300.46" + attribute \src "ls180.v:1376.12-1376.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1297.6-1297.33" + attribute \src "ls180.v:1373.6-1373.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1296.6-1296.33" + attribute \src "ls180.v:1372.6-1372.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1303.6-1303.37" + attribute \src "ls180.v:1379.6-1379.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1304.6-1304.36" + attribute \src "ls180.v:1380.6-1380.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1305.12-1305.50" + attribute \src "ls180.v:1381.12-1381.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1302.6-1302.37" + attribute \src "ls180.v:1378.6-1378.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1301.6-1301.37" + attribute \src "ls180.v:1377.6-1377.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1616.6-1616.38" + attribute \src "ls180.v:1692.6-1692.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1617.6-1617.37" + attribute \src "ls180.v:1693.6-1693.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1615.11-1615.41" + attribute \src "ls180.v:1691.11-1691.41" wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1606.6-1606.43" + attribute \src "ls180.v:1682.6-1682.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1607.6-1607.42" + attribute \src "ls180.v:1683.6-1683.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1608.13-1608.57" + attribute \src "ls180.v:1684.13-1684.57" wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1605.6-1605.43" + attribute \src "ls180.v:1681.6-1681.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1604.6-1604.43" + attribute \src "ls180.v:1680.6-1680.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1611.6-1611.45" + attribute \src "ls180.v:1687.6-1687.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1612.6-1612.44" + attribute \src "ls180.v:1688.6-1688.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1613.11-1613.57" + attribute \src "ls180.v:1689.11-1689.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1614.6-1614.65" + attribute \src "ls180.v:1690.6-1690.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1610.6-1610.45" + attribute \src "ls180.v:1686.6-1686.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1609.6-1609.45" + attribute \src "ls180.v:1685.6-1685.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1600.13-1600.38" + attribute \src "ls180.v:1676.13-1676.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1589.5-1589.33" + attribute \src "ls180.v:1665.5-1665.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1588.12-1588.45" + attribute \src "ls180.v:1664.12-1664.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1587.12-1587.37" + attribute \src "ls180.v:1663.12-1663.37" wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1817.12-1817.67" + attribute \src "ls180.v:1859.12-1859.67" wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1818.5-1818.63" + attribute \src "ls180.v:1860.5-1860.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1594.5-1594.37" + attribute \src "ls180.v:1670.5-1670.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1595.6-1595.34" + attribute \src "ls180.v:1671.6-1671.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1593.5-1593.35" + attribute \src "ls180.v:1669.5-1669.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1592.5-1592.40" + attribute \src "ls180.v:1668.5-1668.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1602.13-1602.40" + attribute \src "ls180.v:1678.13-1678.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1591.5-1591.35" + attribute \src "ls180.v:1667.5-1667.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1590.12-1590.47" + attribute \src "ls180.v:1666.12-1666.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1597.5-1597.33" + attribute \src "ls180.v:1673.5-1673.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1596.5-1596.38" + attribute \src "ls180.v:1672.5-1672.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1601.12-1601.39" + attribute \src "ls180.v:1677.12-1677.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1821.12-1821.79" + attribute \src "ls180.v:1863.12-1863.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1822.5-1822.75" + attribute \src "ls180.v:1864.5-1864.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1598.13-1598.47" + attribute \src "ls180.v:1674.13-1674.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1599.6-1599.36" + attribute \src "ls180.v:1675.6-1675.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1603.6-1603.32" + attribute \src "ls180.v:1679.6-1679.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1580.5-1580.35" + attribute \src "ls180.v:1656.5-1656.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1581.12-1581.53" + attribute \src "ls180.v:1657.12-1657.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1579.5-1579.36" + attribute \src "ls180.v:1655.5-1655.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1578.5-1578.36" + attribute \src "ls180.v:1654.5-1654.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1584.5-1584.38" + attribute \src "ls180.v:1660.5-1660.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1585.5-1585.37" + attribute \src "ls180.v:1661.5-1661.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1586.12-1586.52" + attribute \src "ls180.v:1662.12-1662.52" wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1583.6-1583.39" + attribute \src "ls180.v:1659.6-1659.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1582.5-1582.38" + attribute \src "ls180.v:1658.5-1658.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1642.11-1642.40" + attribute \src "ls180.v:1718.11-1718.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1647.6-1647.35" + attribute \src "ls180.v:1723.6-1723.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1651.6-1651.41" + attribute \src "ls180.v:1727.6-1727.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1652.6-1652.40" + attribute \src "ls180.v:1728.6-1728.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1650.12-1650.54" + attribute \src "ls180.v:1726.12-1726.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1654.6-1654.42" + attribute \src "ls180.v:1730.6-1730.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1655.6-1655.41" + attribute \src "ls180.v:1731.6-1731.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1653.12-1653.55" + attribute \src "ls180.v:1729.12-1729.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1639.11-1639.38" + attribute \src "ls180.v:1715.11-1715.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1641.11-1641.40" + attribute \src "ls180.v:1717.11-1717.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1648.12-1648.44" + attribute \src "ls180.v:1724.12-1724.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1649.12-1649.46" + attribute \src "ls180.v:1725.12-1725.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1640.5-1640.34" + attribute \src "ls180.v:1716.5-1716.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1625.6-1625.38" + attribute \src "ls180.v:1701.6-1701.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1626.6-1626.37" + attribute \src "ls180.v:1702.6-1702.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1627.12-1627.51" + attribute \src "ls180.v:1703.12-1703.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1624.6-1624.38" + attribute \src "ls180.v:1700.6-1700.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1623.6-1623.38" + attribute \src "ls180.v:1699.6-1699.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1630.6-1630.40" + attribute \src "ls180.v:1706.6-1706.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1631.6-1631.39" + attribute \src "ls180.v:1707.6-1707.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1632.12-1632.53" + attribute \src "ls180.v:1708.12-1708.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1629.6-1629.40" + attribute \src "ls180.v:1705.6-1705.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1628.6-1628.40" + attribute \src "ls180.v:1704.6-1704.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1637.12-1637.46" + attribute \src "ls180.v:1713.12-1713.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1638.12-1638.47" + attribute \src "ls180.v:1714.12-1714.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1635.6-1635.39" + attribute \src "ls180.v:1711.6-1711.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1636.6-1636.45" + attribute \src "ls180.v:1712.6-1712.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1633.6-1633.39" + attribute \src "ls180.v:1709.6-1709.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1634.6-1634.45" + attribute \src "ls180.v:1710.6-1710.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1643.11-1643.43" + attribute \src "ls180.v:1719.11-1719.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1644.12-1644.46" + attribute \src "ls180.v:1720.12-1720.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1646.12-1646.46" + attribute \src "ls180.v:1722.12-1722.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1645.6-1645.37" + attribute \src "ls180.v:1721.6-1721.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1575.6-1575.43" + attribute \src "ls180.v:1651.6-1651.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1620.6-1620.43" + attribute \src "ls180.v:1696.6-1696.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1576.6-1576.42" + attribute \src "ls180.v:1652.6-1652.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1621.6-1621.42" + attribute \src "ls180.v:1697.6-1697.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1577.12-1577.56" + attribute \src "ls180.v:1653.12-1653.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1622.12-1622.56" + attribute \src "ls180.v:1698.12-1698.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1574.6-1574.43" + attribute \src "ls180.v:1650.6-1650.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1619.6-1619.43" + attribute \src "ls180.v:1695.6-1695.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1573.6-1573.43" + attribute \src "ls180.v:1649.6-1649.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1618.6-1618.43" + attribute \src "ls180.v:1694.6-1694.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1024.6-1024.27" + attribute \src "ls180.v:1100.6-1100.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1023.5-1023.28" + attribute \src "ls180.v:1099.5-1099.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1026.5-1026.28" + attribute \src "ls180.v:1102.5-1102.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1027.5-1027.29" + attribute \src "ls180.v:1103.5-1103.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1025.11-1025.34" + attribute \src "ls180.v:1101.11-1101.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1021.5-1021.26" + attribute \src "ls180.v:1097.5-1097.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1022.6-1022.29" + attribute \src "ls180.v:1098.6-1098.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1020.11-1020.37" + attribute \src "ls180.v:1096.11-1096.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1124.6-1124.41" + attribute \src "ls180.v:1200.6-1200.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1125.6-1125.40" + attribute \src "ls180.v:1201.6-1201.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1126.12-1126.54" + attribute \src "ls180.v:1202.12-1202.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1123.6-1123.41" + attribute \src "ls180.v:1199.6-1199.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1122.6-1122.41" + attribute \src "ls180.v:1198.6-1198.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1129.5-1129.42" + attribute \src "ls180.v:1205.5-1205.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1130.5-1130.41" + attribute \src "ls180.v:1206.5-1206.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1131.11-1131.55" + attribute \src "ls180.v:1207.11-1207.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1128.6-1128.43" + attribute \src "ls180.v:1204.6-1204.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1127.5-1127.42" + attribute \src "ls180.v:1203.5-1203.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1114.11-1114.47" + attribute \src "ls180.v:1190.11-1190.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1115.6-1115.46" + attribute \src "ls180.v:1191.6-1191.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1105.5-1105.46" + attribute \src "ls180.v:1181.5-1181.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1106.5-1106.45" + attribute \src "ls180.v:1182.5-1182.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1107.6-1107.54" + attribute \src "ls180.v:1183.6-1183.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1104.6-1104.47" + attribute \src "ls180.v:1180.6-1180.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1103.6-1103.47" + attribute \src "ls180.v:1179.6-1179.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1110.5-1110.48" + attribute \src "ls180.v:1186.5-1186.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1111.5-1111.47" + attribute \src "ls180.v:1187.5-1187.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1112.11-1112.61" + attribute \src "ls180.v:1188.11-1188.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1113.11-1113.74" + attribute \src "ls180.v:1189.11-1189.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1109.6-1109.49" + attribute \src "ls180.v:1185.6-1185.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1108.6-1108.49" + attribute \src "ls180.v:1184.6-1184.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1116.5-1116.46" + attribute \src "ls180.v:1192.5-1192.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1087.6-1087.40" + attribute \src "ls180.v:1163.6-1163.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1088.6-1088.39" + attribute \src "ls180.v:1164.6-1164.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1089.6-1089.46" + attribute \src "ls180.v:1165.6-1165.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1090.6-1090.48" + attribute \src "ls180.v:1166.6-1166.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1091.6-1091.48" + attribute \src "ls180.v:1167.6-1167.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1092.6-1092.49" + attribute \src "ls180.v:1168.6-1168.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1093.12-1093.55" + attribute \src "ls180.v:1169.12-1169.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1094.12-1094.55" + attribute \src "ls180.v:1170.12-1170.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1095.6-1095.50" + attribute \src "ls180.v:1171.6-1171.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1086.5-1086.39" + attribute \src "ls180.v:1162.5-1162.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1085.6-1085.40" + attribute \src "ls180.v:1161.6-1161.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1132.5-1132.31" + attribute \src "ls180.v:1208.5-1208.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1761.5-1761.59" + attribute \src "ls180.v:1803.5-1803.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1762.5-1762.62" + attribute \src "ls180.v:1804.5-1804.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1102.5-1102.29" + attribute \src "ls180.v:1178.5-1178.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1098.6-1098.47" + attribute \src "ls180.v:1174.6-1174.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1119.6-1119.47" + attribute \src "ls180.v:1195.6-1195.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1099.6-1099.46" + attribute \src "ls180.v:1175.6-1175.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1120.6-1120.46" + attribute \src "ls180.v:1196.6-1196.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1100.12-1100.60" + attribute \src "ls180.v:1176.12-1176.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1121.12-1121.60" + attribute \src "ls180.v:1197.12-1197.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1097.5-1097.46" + attribute \src "ls180.v:1173.5-1173.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1118.6-1118.47" + attribute \src "ls180.v:1194.6-1194.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1096.6-1096.47" + attribute \src "ls180.v:1172.6-1172.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1117.6-1117.47" + attribute \src "ls180.v:1193.6-1193.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1101.6-1101.32" + attribute \src "ls180.v:1177.6-1177.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1084.11-1084.32" + attribute \src "ls180.v:1160.11-1160.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1757.11-1757.60" + attribute \src "ls180.v:1799.11-1799.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1758.5-1758.57" + attribute \src "ls180.v:1800.5-1800.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1059.5-1059.42" + attribute \src "ls180.v:1135.5-1135.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1060.5-1060.41" + attribute \src "ls180.v:1136.5-1136.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1061.5-1061.48" + attribute \src "ls180.v:1137.5-1137.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1062.6-1062.51" + attribute \src "ls180.v:1138.6-1138.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1063.5-1063.50" + attribute \src "ls180.v:1139.5-1139.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1064.5-1064.51" + attribute \src "ls180.v:1140.5-1140.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1065.12-1065.58" + attribute \src "ls180.v:1141.12-1141.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1066.11-1066.57" + attribute \src "ls180.v:1142.11-1142.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1067.5-1067.52" + attribute \src "ls180.v:1143.5-1143.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1058.6-1058.43" + attribute \src "ls180.v:1134.6-1134.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1057.6-1057.43" + attribute \src "ls180.v:1133.6-1133.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1069.5-1069.41" + attribute \src "ls180.v:1145.5-1145.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1070.5-1070.43" + attribute \src "ls180.v:1146.5-1146.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1071.5-1071.44" + attribute \src "ls180.v:1147.5-1147.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1072.11-1072.50" + attribute \src "ls180.v:1148.11-1148.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1073.5-1073.45" + attribute \src "ls180.v:1149.5-1149.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1068.6-1068.36" + attribute \src "ls180.v:1144.6-1144.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1076.5-1076.30" + attribute \src "ls180.v:1152.5-1152.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1077.11-1077.46" + attribute \src "ls180.v:1153.11-1153.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1075.5-1075.31" + attribute \src "ls180.v:1151.5-1151.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1074.5-1074.31" + attribute \src "ls180.v:1150.5-1150.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1080.5-1080.32" + attribute \src "ls180.v:1156.5-1156.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1081.11-1081.46" + attribute \src "ls180.v:1157.11-1157.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1082.11-1082.48" + attribute \src "ls180.v:1158.11-1158.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1079.5-1079.33" + attribute \src "ls180.v:1155.5-1155.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1078.5-1078.33" + attribute \src "ls180.v:1154.5-1154.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1083.12-1083.35" + attribute \src "ls180.v:1159.12-1159.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1759.12-1759.63" + attribute \src "ls180.v:1801.12-1801.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1760.5-1760.59" + attribute \src "ls180.v:1802.5-1802.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1056.11-1056.32" + attribute \src "ls180.v:1132.11-1132.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1753.11-1753.59" + attribute \src "ls180.v:1795.11-1795.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1754.5-1754.56" + attribute \src "ls180.v:1796.5-1796.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1055.5-1055.25" + attribute \src "ls180.v:1131.5-1131.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1043.6-1043.43" + attribute \src "ls180.v:1119.6-1119.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1044.12-1044.50" + attribute \src "ls180.v:1120.12-1120.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1042.6-1042.35" + attribute \src "ls180.v:1118.6-1118.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1046.5-1046.41" + attribute \src "ls180.v:1122.5-1122.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1047.5-1047.43" + attribute \src "ls180.v:1123.5-1123.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1048.5-1048.44" + attribute \src "ls180.v:1124.5-1124.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1049.11-1049.50" + attribute \src "ls180.v:1125.11-1125.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1050.5-1050.45" + attribute \src "ls180.v:1126.5-1126.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1045.6-1045.36" + attribute \src "ls180.v:1121.6-1121.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1053.5-1053.30" + attribute \src "ls180.v:1129.5-1129.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1054.11-1054.44" + attribute \src "ls180.v:1130.11-1130.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1052.5-1052.31" + attribute \src "ls180.v:1128.5-1128.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1051.5-1051.31" + attribute \src "ls180.v:1127.5-1127.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1240.11-1240.33" + attribute \src "ls180.v:1316.11-1316.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1773.11-1773.62" + attribute \src "ls180.v:1815.11-1815.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1774.5-1774.59" + attribute \src "ls180.v:1816.5-1816.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1280.6-1280.43" + attribute \src "ls180.v:1356.6-1356.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1281.6-1281.42" + attribute \src "ls180.v:1357.6-1357.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1282.12-1282.56" + attribute \src "ls180.v:1358.12-1358.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1279.6-1279.43" + attribute \src "ls180.v:1355.6-1355.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1278.6-1278.43" + attribute \src "ls180.v:1354.6-1354.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1285.5-1285.44" + attribute \src "ls180.v:1361.5-1361.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1286.5-1286.43" + attribute \src "ls180.v:1362.5-1362.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1287.11-1287.57" + attribute \src "ls180.v:1363.11-1363.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1284.6-1284.45" + attribute \src "ls180.v:1360.6-1360.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1283.5-1283.44" + attribute \src "ls180.v:1359.5-1359.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1270.5-1270.43" + attribute \src "ls180.v:1346.5-1346.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1271.6-1271.48" + attribute \src "ls180.v:1347.6-1347.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1261.5-1261.48" + attribute \src "ls180.v:1337.5-1337.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1262.5-1262.47" + attribute \src "ls180.v:1338.5-1338.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1263.12-1263.62" + attribute \src "ls180.v:1339.12-1339.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1260.6-1260.49" + attribute \src "ls180.v:1336.6-1336.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1259.6-1259.49" + attribute \src "ls180.v:1335.6-1335.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1266.5-1266.50" + attribute \src "ls180.v:1342.5-1342.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1267.5-1267.49" + attribute \src "ls180.v:1343.5-1343.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1268.11-1268.63" + attribute \src "ls180.v:1344.11-1344.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1269.11-1269.76" + attribute \src "ls180.v:1345.11-1345.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1265.6-1265.51" + attribute \src "ls180.v:1341.6-1341.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1264.6-1264.51" + attribute \src "ls180.v:1340.6-1340.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1272.5-1272.48" + attribute \src "ls180.v:1348.5-1348.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1243.6-1243.42" + attribute \src "ls180.v:1319.6-1319.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1244.6-1244.41" + attribute \src "ls180.v:1320.6-1320.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1245.6-1245.48" + attribute \src "ls180.v:1321.6-1321.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1246.6-1246.50" + attribute \src "ls180.v:1322.6-1322.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1247.6-1247.50" + attribute \src "ls180.v:1323.6-1323.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1248.6-1248.51" + attribute \src "ls180.v:1324.6-1324.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1249.12-1249.57" + attribute \src "ls180.v:1325.12-1325.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1250.12-1250.57" + attribute \src "ls180.v:1326.12-1326.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1251.6-1251.52" + attribute \src "ls180.v:1327.6-1327.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1242.5-1242.41" + attribute \src "ls180.v:1318.5-1318.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1241.6-1241.42" + attribute \src "ls180.v:1317.6-1317.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1288.5-1288.33" + attribute \src "ls180.v:1364.5-1364.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1777.5-1777.62" + attribute \src "ls180.v:1819.5-1819.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1778.5-1778.65" + attribute \src "ls180.v:1820.5-1820.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1258.5-1258.31" + attribute \src "ls180.v:1334.5-1334.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1254.6-1254.49" + attribute \src "ls180.v:1330.6-1330.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1275.6-1275.49" + attribute \src "ls180.v:1351.6-1351.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1255.6-1255.48" + attribute \src "ls180.v:1331.6-1331.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1276.6-1276.48" + attribute \src "ls180.v:1352.6-1352.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1256.12-1256.62" + attribute \src "ls180.v:1332.12-1332.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1277.12-1277.62" + attribute \src "ls180.v:1353.12-1353.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1253.5-1253.48" + attribute \src "ls180.v:1329.5-1329.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1274.6-1274.49" + attribute \src "ls180.v:1350.6-1350.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1252.6-1252.49" + attribute \src "ls180.v:1328.6-1328.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1273.6-1273.49" + attribute \src "ls180.v:1349.6-1349.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1257.6-1257.34" + attribute \src "ls180.v:1333.6-1333.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1213.5-1213.43" + attribute \src "ls180.v:1289.5-1289.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1214.5-1214.42" + attribute \src "ls180.v:1290.5-1290.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1215.5-1215.49" + attribute \src "ls180.v:1291.5-1291.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1216.6-1216.52" + attribute \src "ls180.v:1292.6-1292.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1217.5-1217.51" + attribute \src "ls180.v:1293.5-1293.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1218.5-1218.52" + attribute \src "ls180.v:1294.5-1294.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1219.12-1219.59" + attribute \src "ls180.v:1295.12-1295.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1220.11-1220.58" + attribute \src "ls180.v:1296.11-1296.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1221.5-1221.53" + attribute \src "ls180.v:1297.5-1297.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1212.6-1212.44" + attribute \src "ls180.v:1288.6-1288.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1211.6-1211.44" + attribute \src "ls180.v:1287.6-1287.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1223.5-1223.42" + attribute \src "ls180.v:1299.5-1299.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1224.5-1224.44" + attribute \src "ls180.v:1300.5-1300.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1225.5-1225.45" + attribute \src "ls180.v:1301.5-1301.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1226.11-1226.51" + attribute \src "ls180.v:1302.11-1302.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1227.5-1227.46" + attribute \src "ls180.v:1303.5-1303.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1222.6-1222.37" + attribute \src "ls180.v:1298.6-1298.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1230.5-1230.31" + attribute \src "ls180.v:1306.5-1306.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1231.11-1231.53" + attribute \src "ls180.v:1307.11-1307.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1229.5-1229.32" + attribute \src "ls180.v:1305.5-1305.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1228.5-1228.32" + attribute \src "ls180.v:1304.5-1304.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1234.5-1234.34" + attribute \src "ls180.v:1310.5-1310.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1235.5-1235.33" + attribute \src "ls180.v:1311.5-1311.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1236.11-1236.47" + attribute \src "ls180.v:1312.11-1312.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1237.11-1237.49" + attribute \src "ls180.v:1313.11-1313.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1233.5-1233.34" + attribute \src "ls180.v:1309.5-1309.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1232.5-1232.34" + attribute \src "ls180.v:1308.5-1308.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1238.5-1238.26" + attribute \src "ls180.v:1314.5-1314.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1239.12-1239.36" + attribute \src "ls180.v:1315.12-1315.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1775.12-1775.65" + attribute \src "ls180.v:1817.12-1817.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1776.5-1776.61" + attribute \src "ls180.v:1818.5-1818.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1148.11-1148.33" + attribute \src "ls180.v:1224.11-1224.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1769.11-1769.54" + attribute \src "ls180.v:1811.11-1811.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1770.5-1770.51" + attribute \src "ls180.v:1812.5-1812.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1202.6-1202.42" + attribute \src "ls180.v:1278.6-1278.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1203.6-1203.41" + attribute \src "ls180.v:1279.6-1279.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1204.12-1204.55" + attribute \src "ls180.v:1280.12-1280.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1201.6-1201.42" + attribute \src "ls180.v:1277.6-1277.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1200.6-1200.42" + attribute \src "ls180.v:1276.6-1276.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1207.5-1207.43" + attribute \src "ls180.v:1283.5-1283.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1208.5-1208.42" + attribute \src "ls180.v:1284.5-1284.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1209.11-1209.56" + attribute \src "ls180.v:1285.11-1285.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1206.6-1206.44" + attribute \src "ls180.v:1282.6-1282.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1205.5-1205.43" + attribute \src "ls180.v:1281.5-1281.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1192.11-1192.48" + attribute \src "ls180.v:1268.11-1268.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1193.6-1193.47" + attribute \src "ls180.v:1269.6-1269.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1183.5-1183.47" + attribute \src "ls180.v:1259.5-1259.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1184.5-1184.46" + attribute \src "ls180.v:1260.5-1260.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1185.6-1185.55" + attribute \src "ls180.v:1261.6-1261.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1182.6-1182.48" + attribute \src "ls180.v:1258.6-1258.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1181.6-1181.48" + attribute \src "ls180.v:1257.6-1257.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1188.5-1188.49" + attribute \src "ls180.v:1264.5-1264.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1189.5-1189.48" + attribute \src "ls180.v:1265.5-1265.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1190.11-1190.62" + attribute \src "ls180.v:1266.11-1266.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1191.11-1191.75" + attribute \src "ls180.v:1267.11-1267.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1187.6-1187.50" + attribute \src "ls180.v:1263.6-1263.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1186.6-1186.50" + attribute \src "ls180.v:1262.6-1262.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1194.5-1194.47" + attribute \src "ls180.v:1270.5-1270.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1165.6-1165.41" + attribute \src "ls180.v:1241.6-1241.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1166.6-1166.40" + attribute \src "ls180.v:1242.6-1242.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1167.6-1167.47" + attribute \src "ls180.v:1243.6-1243.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1168.6-1168.49" + attribute \src "ls180.v:1244.6-1244.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1169.6-1169.49" + attribute \src "ls180.v:1245.6-1245.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1170.6-1170.50" + attribute \src "ls180.v:1246.6-1246.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1171.12-1171.56" + attribute \src "ls180.v:1247.12-1247.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1172.12-1172.56" + attribute \src "ls180.v:1248.12-1248.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1173.6-1173.51" + attribute \src "ls180.v:1249.6-1249.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1164.5-1164.40" + attribute \src "ls180.v:1240.5-1240.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1163.6-1163.41" + attribute \src "ls180.v:1239.6-1239.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1210.5-1210.32" + attribute \src "ls180.v:1286.5-1286.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1765.5-1765.59" + attribute \src "ls180.v:1807.5-1807.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1766.5-1766.62" + attribute \src "ls180.v:1808.5-1808.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1180.5-1180.30" + attribute \src "ls180.v:1256.5-1256.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1176.6-1176.48" + attribute \src "ls180.v:1252.6-1252.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1197.6-1197.48" + attribute \src "ls180.v:1273.6-1273.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1177.6-1177.47" + attribute \src "ls180.v:1253.6-1253.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1198.6-1198.47" + attribute \src "ls180.v:1274.6-1274.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1178.12-1178.61" + attribute \src "ls180.v:1254.12-1254.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1199.12-1199.61" + attribute \src "ls180.v:1275.12-1275.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1175.5-1175.47" + attribute \src "ls180.v:1251.5-1251.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1196.6-1196.48" + attribute \src "ls180.v:1272.6-1272.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1174.6-1174.48" + attribute \src "ls180.v:1250.6-1250.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1195.6-1195.48" + attribute \src "ls180.v:1271.6-1271.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1179.6-1179.33" + attribute \src "ls180.v:1255.6-1255.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1162.5-1162.27" + attribute \src "ls180.v:1238.5-1238.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1151.5-1151.43" + attribute \src "ls180.v:1227.5-1227.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1152.5-1152.42" + attribute \src "ls180.v:1228.5-1228.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1153.5-1153.49" + attribute \src "ls180.v:1229.5-1229.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1154.5-1154.51" + attribute \src "ls180.v:1230.5-1230.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1155.5-1155.51" + attribute \src "ls180.v:1231.5-1231.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1156.5-1156.52" + attribute \src "ls180.v:1232.5-1232.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1157.11-1157.58" + attribute \src "ls180.v:1233.11-1233.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1158.11-1158.58" + attribute \src "ls180.v:1234.11-1234.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1159.5-1159.53" + attribute \src "ls180.v:1235.5-1235.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1150.6-1150.44" + attribute \src "ls180.v:1226.6-1226.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1149.5-1149.43" + attribute \src "ls180.v:1225.5-1225.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1134.6-1134.44" + attribute \src "ls180.v:1210.6-1210.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1135.12-1135.51" + attribute \src "ls180.v:1211.12-1211.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1133.6-1133.36" + attribute \src "ls180.v:1209.6-1209.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1137.5-1137.42" + attribute \src "ls180.v:1213.5-1213.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1138.5-1138.44" + attribute \src "ls180.v:1214.5-1214.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1139.5-1139.45" + attribute \src "ls180.v:1215.5-1215.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1140.11-1140.51" + attribute \src "ls180.v:1216.11-1216.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1141.5-1141.46" + attribute \src "ls180.v:1217.5-1217.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1136.6-1136.37" + attribute \src "ls180.v:1212.6-1212.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1144.5-1144.32" + attribute \src "ls180.v:1220.5-1220.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1145.5-1145.31" + attribute \src "ls180.v:1221.5-1221.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1146.11-1146.45" + attribute \src "ls180.v:1222.11-1222.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1143.5-1143.32" + attribute \src "ls180.v:1219.5-1219.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1142.5-1142.32" + attribute \src "ls180.v:1218.5-1218.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1160.5-1160.27" + attribute \src "ls180.v:1236.5-1236.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1147.5-1147.26" + attribute \src "ls180.v:1223.5-1223.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1161.5-1161.27" + attribute \src "ls180.v:1237.5-1237.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1041.11-1041.32" + attribute \src "ls180.v:1117.11-1117.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1749.11-1749.59" + attribute \src "ls180.v:1791.11-1791.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1750.5-1750.56" + attribute \src "ls180.v:1792.5-1792.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1029.6-1029.34" + attribute \src "ls180.v:1105.6-1105.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1028.6-1028.35" + attribute \src "ls180.v:1104.6-1104.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1031.5-1031.33" + attribute \src "ls180.v:1107.5-1107.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1030.6-1030.35" + attribute \src "ls180.v:1106.6-1106.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1033.6-1033.43" + attribute \src "ls180.v:1109.6-1109.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1034.12-1034.50" + attribute \src "ls180.v:1110.12-1110.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1032.6-1032.35" + attribute \src "ls180.v:1108.6-1108.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1036.5-1036.41" + attribute \src "ls180.v:1112.5-1112.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1037.5-1037.43" + attribute \src "ls180.v:1113.5-1113.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1038.5-1038.44" + attribute \src "ls180.v:1114.5-1114.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1039.11-1039.50" + attribute \src "ls180.v:1115.11-1115.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1040.5-1040.45" + attribute \src "ls180.v:1116.5-1116.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1035.6-1035.36" + attribute \src "ls180.v:1111.6-1111.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1289.6-1289.27" + attribute \src "ls180.v:1365.6-1365.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1290.5-1290.28" + attribute \src "ls180.v:1366.5-1366.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1291.6-1291.29" + attribute \src "ls180.v:1367.6-1367.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1292.6-1292.30" + attribute \src "ls180.v:1368.6-1368.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1293.11-1293.35" + attribute \src "ls180.v:1369.11-1369.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1294.12-1294.36" + attribute \src "ls180.v:1370.12-1370.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1295.6-1295.31" + attribute \src "ls180.v:1371.6-1371.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1018.6-1018.23" + attribute \src "ls180.v:1094.6-1094.23" wire \main_sdphy_status - attribute \src "ls180.v:1019.6-1019.19" + attribute \src "ls180.v:1095.6-1095.19" wire \main_sdphy_we - attribute \src "ls180.v:299.5-299.26" + attribute \src "ls180.v:329.5-329.26" wire \main_sdram_address_re - attribute \src "ls180.v:298.12-298.38" + attribute \src "ls180.v:328.12-328.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:301.5-301.27" + attribute \src "ls180.v:331.5-331.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:300.11-300.38" + attribute \src "ls180.v:330.11-330.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:397.5-397.43" + attribute \src "ls180.v:427.5-427.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:419.11-419.63" + attribute \src "ls180.v:449.11-449.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:424.6-424.58" + attribute \src "ls180.v:454.6-454.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:429.6-429.64" + attribute \src "ls180.v:459.6-459.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:430.6-430.63" + attribute \src "ls180.v:460.6-460.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:428.13-428.78" + attribute \src "ls180.v:458.13-458.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:427.6-427.69" + attribute \src "ls180.v:457.6-457.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:433.6-433.65" + attribute \src "ls180.v:463.6-463.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:434.6-434.64" + attribute \src "ls180.v:464.6-464.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:432.13-432.79" + attribute \src "ls180.v:462.13-462.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:431.6-431.70" + attribute \src "ls180.v:461.6-461.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:416.11-416.61" + attribute \src "ls180.v:446.11-446.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:418.11-418.63" + attribute \src "ls180.v:448.11-448.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:425.12-425.67" + attribute \src "ls180.v:455.12-455.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:426.13-426.70" + attribute \src "ls180.v:456.13-456.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:417.5-417.57" + attribute \src "ls180.v:447.5-447.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:400.5-400.60" + attribute \src "ls180.v:430.5-430.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:401.5-401.59" + attribute \src "ls180.v:431.5-431.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:403.13-403.75" + attribute \src "ls180.v:433.13-433.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:402.6-402.66" + attribute \src "ls180.v:432.6-432.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:399.6-399.61" + attribute \src "ls180.v:429.6-429.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:398.6-398.61" + attribute \src "ls180.v:428.6-428.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:406.6-406.63" + attribute \src "ls180.v:436.6-436.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:407.6-407.62" + attribute \src "ls180.v:437.6-437.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:409.13-409.77" + attribute \src "ls180.v:439.13-439.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:408.6-408.68" + attribute \src "ls180.v:438.6-438.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:405.6-405.63" + attribute \src "ls180.v:435.6-435.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:404.6-404.63" + attribute \src "ls180.v:434.6-434.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:414.13-414.71" + attribute \src "ls180.v:444.13-444.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:415.13-415.72" + attribute \src "ls180.v:445.13-445.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:412.6-412.63" + attribute \src "ls180.v:442.6-442.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:413.6-413.69" + attribute \src "ls180.v:443.6-443.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:410.6-410.63" + attribute \src "ls180.v:440.6-440.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:411.6-411.69" + attribute \src "ls180.v:441.6-441.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:420.11-420.66" + attribute \src "ls180.v:450.11-450.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:421.13-421.70" + attribute \src "ls180.v:451.13-451.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:423.13-423.70" + attribute \src "ls180.v:453.13-453.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:422.6-422.60" + attribute \src "ls180.v:452.6-452.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:437.6-437.51" + attribute \src "ls180.v:467.6-467.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:438.6-438.50" + attribute \src "ls180.v:468.6-468.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:440.13-440.65" + attribute \src "ls180.v:470.13-470.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:439.6-439.56" + attribute \src "ls180.v:469.6-469.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:436.6-436.51" + attribute \src "ls180.v:466.6-466.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:435.6-435.51" + attribute \src "ls180.v:465.6-465.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:443.5-443.52" + attribute \src "ls180.v:473.5-473.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:444.5-444.51" + attribute \src "ls180.v:474.5-474.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:446.12-446.66" + attribute \src "ls180.v:476.12-476.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:445.5-445.57" + attribute \src "ls180.v:475.5-475.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:442.6-442.53" + attribute \src "ls180.v:472.6-472.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:441.5-441.52" + attribute \src "ls180.v:471.5-471.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:389.12-389.49" + attribute \src "ls180.v:419.12-419.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:390.12-390.50" + attribute \src "ls180.v:420.12-420.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:391.5-391.44" + attribute \src "ls180.v:421.5-421.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:394.5-394.47" + attribute \src "ls180.v:424.5-424.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:395.5-395.48" + attribute \src "ls180.v:425.5-425.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:396.5-396.49" + attribute \src "ls180.v:426.5-426.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:392.5-392.44" + attribute \src "ls180.v:422.5-422.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:393.5-393.43" + attribute \src "ls180.v:423.5-423.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:388.5-388.38" + attribute \src "ls180.v:418.5-418.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:387.5-387.38" + attribute \src "ls180.v:417.5-417.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:386.5-386.40" + attribute \src "ls180.v:416.5-416.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:385.6-385.41" + attribute \src "ls180.v:415.6-415.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:381.13-381.45" + attribute \src "ls180.v:411.13-411.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:382.6-382.38" + attribute \src "ls180.v:412.6-412.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:384.5-384.44" + attribute \src "ls180.v:414.5-414.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:379.6-379.39" + attribute \src "ls180.v:409.6-409.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:378.6-378.39" + attribute \src "ls180.v:408.6-408.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:383.5-383.44" + attribute \src "ls180.v:413.5-413.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:380.6-380.36" + attribute \src "ls180.v:410.6-410.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:447.12-447.39" + attribute \src "ls180.v:477.12-477.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:451.5-451.38" + attribute \src "ls180.v:481.5-481.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:452.5-452.47" + attribute \src "ls180.v:482.5-482.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:449.6-449.37" + attribute \src "ls180.v:479.6-479.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:450.5-450.37" + attribute \src "ls180.v:480.5-480.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:448.5-448.39" + attribute \src "ls180.v:478.5-478.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:459.32-459.69" + attribute \src "ls180.v:489.32-489.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:458.6-458.43" + attribute \src "ls180.v:488.6-488.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:457.32-457.68" + attribute \src "ls180.v:487.32-487.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:456.6-456.42" + attribute \src "ls180.v:486.6-486.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:455.11-455.48" + attribute \src "ls180.v:485.11-485.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:454.32-454.69" + attribute \src "ls180.v:484.32-484.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:453.6-453.43" + attribute \src "ls180.v:483.6-483.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:479.5-479.43" + attribute \src "ls180.v:509.5-509.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:501.11-501.63" + attribute \src "ls180.v:531.11-531.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:506.6-506.58" + attribute \src "ls180.v:536.6-536.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:511.6-511.64" + attribute \src "ls180.v:541.6-541.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:512.6-512.63" + attribute \src "ls180.v:542.6-542.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:510.13-510.78" + attribute \src "ls180.v:540.13-540.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:509.6-509.69" + attribute \src "ls180.v:539.6-539.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:515.6-515.65" + attribute \src "ls180.v:545.6-545.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:516.6-516.64" + attribute \src "ls180.v:546.6-546.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:514.13-514.79" + attribute \src "ls180.v:544.13-544.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:513.6-513.70" + attribute \src "ls180.v:543.6-543.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:498.11-498.61" + attribute \src "ls180.v:528.11-528.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:500.11-500.63" + attribute \src "ls180.v:530.11-530.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:507.12-507.67" + attribute \src "ls180.v:537.12-537.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:508.13-508.70" + attribute \src "ls180.v:538.13-538.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:499.5-499.57" + attribute \src "ls180.v:529.5-529.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:482.5-482.60" + attribute \src "ls180.v:512.5-512.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:483.5-483.59" + attribute \src "ls180.v:513.5-513.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:485.13-485.75" + attribute \src "ls180.v:515.13-515.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:484.6-484.66" + attribute \src "ls180.v:514.6-514.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:481.6-481.61" + attribute \src "ls180.v:511.6-511.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:480.6-480.61" + attribute \src "ls180.v:510.6-510.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:488.6-488.63" + attribute \src "ls180.v:518.6-518.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:489.6-489.62" + attribute \src "ls180.v:519.6-519.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:491.13-491.77" + attribute \src "ls180.v:521.13-521.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:490.6-490.68" + attribute \src "ls180.v:520.6-520.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:487.6-487.63" + attribute \src "ls180.v:517.6-517.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:486.6-486.63" + attribute \src "ls180.v:516.6-516.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:496.13-496.71" + attribute \src "ls180.v:526.13-526.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:497.13-497.72" + attribute \src "ls180.v:527.13-527.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:494.6-494.63" + attribute \src "ls180.v:524.6-524.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:495.6-495.69" + attribute \src "ls180.v:525.6-525.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:492.6-492.63" + attribute \src "ls180.v:522.6-522.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:493.6-493.69" + attribute \src "ls180.v:523.6-523.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:502.11-502.66" + attribute \src "ls180.v:532.11-532.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:503.13-503.70" + attribute \src "ls180.v:533.13-533.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:505.13-505.70" + attribute \src "ls180.v:535.13-535.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:504.6-504.60" + attribute \src "ls180.v:534.6-534.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:519.6-519.51" + attribute \src "ls180.v:549.6-549.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:520.6-520.50" + attribute \src "ls180.v:550.6-550.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:522.13-522.65" + attribute \src "ls180.v:552.13-552.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:521.6-521.56" + attribute \src "ls180.v:551.6-551.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:518.6-518.51" + attribute \src "ls180.v:548.6-548.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:517.6-517.51" + attribute \src "ls180.v:547.6-547.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:525.5-525.52" + attribute \src "ls180.v:555.5-555.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:526.5-526.51" + attribute \src "ls180.v:556.5-556.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:528.12-528.66" + attribute \src "ls180.v:558.12-558.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:527.5-527.57" + attribute \src "ls180.v:557.5-557.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:524.6-524.53" + attribute \src "ls180.v:554.6-554.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:523.5-523.52" + attribute \src "ls180.v:553.5-553.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:471.12-471.49" + attribute \src "ls180.v:501.12-501.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:472.12-472.50" + attribute \src "ls180.v:502.12-502.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:473.5-473.44" + attribute \src "ls180.v:503.5-503.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:476.5-476.47" + attribute \src "ls180.v:506.5-506.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:477.5-477.48" + attribute \src "ls180.v:507.5-507.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:478.5-478.49" + attribute \src "ls180.v:508.5-508.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:474.5-474.44" + attribute \src "ls180.v:504.5-504.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:475.5-475.43" + attribute \src "ls180.v:505.5-505.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:470.5-470.38" + attribute \src "ls180.v:500.5-500.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:469.5-469.38" + attribute \src "ls180.v:499.5-499.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:468.5-468.40" + attribute \src "ls180.v:498.5-498.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:467.6-467.41" + attribute \src "ls180.v:497.6-497.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:463.13-463.45" + attribute \src "ls180.v:493.13-493.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:464.6-464.38" + attribute \src "ls180.v:494.6-494.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:466.5-466.44" + attribute \src "ls180.v:496.5-496.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:461.6-461.39" + attribute \src "ls180.v:491.6-491.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:460.6-460.39" + attribute \src "ls180.v:490.6-490.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:465.5-465.44" + attribute \src "ls180.v:495.5-495.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:462.6-462.36" + attribute \src "ls180.v:492.6-492.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:529.12-529.39" + attribute \src "ls180.v:559.12-559.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:533.5-533.38" + attribute \src "ls180.v:563.5-563.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:534.5-534.47" + attribute \src "ls180.v:564.5-564.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:531.6-531.37" + attribute \src "ls180.v:561.6-561.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:532.5-532.37" + attribute \src "ls180.v:562.5-562.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:530.5-530.39" + attribute \src "ls180.v:560.5-560.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:541.32-541.69" + attribute \src "ls180.v:571.32-571.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:540.6-540.43" + attribute \src "ls180.v:570.6-570.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:539.32-539.68" + attribute \src "ls180.v:569.32-569.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:538.6-538.42" + attribute \src "ls180.v:568.6-568.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:537.11-537.48" + attribute \src "ls180.v:567.11-567.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:536.32-536.69" + attribute \src "ls180.v:566.32-566.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:535.6-535.43" + attribute \src "ls180.v:565.6-565.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:561.5-561.43" + attribute \src "ls180.v:591.5-591.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:583.11-583.63" + attribute \src "ls180.v:613.11-613.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:588.6-588.58" + attribute \src "ls180.v:618.6-618.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:593.6-593.64" + attribute \src "ls180.v:623.6-623.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:594.6-594.63" + attribute \src "ls180.v:624.6-624.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:592.13-592.78" + attribute \src "ls180.v:622.13-622.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:591.6-591.69" + attribute \src "ls180.v:621.6-621.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:597.6-597.65" + attribute \src "ls180.v:627.6-627.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:598.6-598.64" + attribute \src "ls180.v:628.6-628.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:596.13-596.79" + attribute \src "ls180.v:626.13-626.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:595.6-595.70" + attribute \src "ls180.v:625.6-625.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:580.11-580.61" + attribute \src "ls180.v:610.11-610.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:582.11-582.63" + attribute \src "ls180.v:612.11-612.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:589.12-589.67" + attribute \src "ls180.v:619.12-619.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:590.13-590.70" + attribute \src "ls180.v:620.13-620.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:581.5-581.57" + attribute \src "ls180.v:611.5-611.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:564.5-564.60" + attribute \src "ls180.v:594.5-594.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:565.5-565.59" + attribute \src "ls180.v:595.5-595.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:567.13-567.75" + attribute \src "ls180.v:597.13-597.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:566.6-566.66" + attribute \src "ls180.v:596.6-596.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:563.6-563.61" + attribute \src "ls180.v:593.6-593.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:562.6-562.61" + attribute \src "ls180.v:592.6-592.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:570.6-570.63" + attribute \src "ls180.v:600.6-600.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:571.6-571.62" + attribute \src "ls180.v:601.6-601.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:573.13-573.77" + attribute \src "ls180.v:603.13-603.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:572.6-572.68" + attribute \src "ls180.v:602.6-602.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:569.6-569.63" + attribute \src "ls180.v:599.6-599.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:568.6-568.63" + attribute \src "ls180.v:598.6-598.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:578.13-578.71" + attribute \src "ls180.v:608.13-608.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:579.13-579.72" + attribute \src "ls180.v:609.13-609.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:576.6-576.63" + attribute \src "ls180.v:606.6-606.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:577.6-577.69" + attribute \src "ls180.v:607.6-607.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:574.6-574.63" + attribute \src "ls180.v:604.6-604.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:575.6-575.69" + attribute \src "ls180.v:605.6-605.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:584.11-584.66" + attribute \src "ls180.v:614.11-614.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:585.13-585.70" + attribute \src "ls180.v:615.13-615.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:587.13-587.70" + attribute \src "ls180.v:617.13-617.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:586.6-586.60" + attribute \src "ls180.v:616.6-616.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:601.6-601.51" + attribute \src "ls180.v:631.6-631.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:602.6-602.50" + attribute \src "ls180.v:632.6-632.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:604.13-604.65" + attribute \src "ls180.v:634.13-634.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:603.6-603.56" + attribute \src "ls180.v:633.6-633.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:600.6-600.51" + attribute \src "ls180.v:630.6-630.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:599.6-599.51" + attribute \src "ls180.v:629.6-629.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:607.5-607.52" + attribute \src "ls180.v:637.5-637.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:608.5-608.51" + attribute \src "ls180.v:638.5-638.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:610.12-610.66" + attribute \src "ls180.v:640.12-640.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:609.5-609.57" + attribute \src "ls180.v:639.5-639.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:606.6-606.53" + attribute \src "ls180.v:636.6-636.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:605.5-605.52" + attribute \src "ls180.v:635.5-635.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:553.12-553.49" + attribute \src "ls180.v:583.12-583.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:554.12-554.50" + attribute \src "ls180.v:584.12-584.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:555.5-555.44" + attribute \src "ls180.v:585.5-585.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:558.5-558.47" + attribute \src "ls180.v:588.5-588.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:559.5-559.48" + attribute \src "ls180.v:589.5-589.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:560.5-560.49" + attribute \src "ls180.v:590.5-590.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:556.5-556.44" + attribute \src "ls180.v:586.5-586.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:557.5-557.43" + attribute \src "ls180.v:587.5-587.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:552.5-552.38" + attribute \src "ls180.v:582.5-582.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:551.5-551.38" + attribute \src "ls180.v:581.5-581.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:550.5-550.40" + attribute \src "ls180.v:580.5-580.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:549.6-549.41" + attribute \src "ls180.v:579.6-579.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:545.13-545.45" + attribute \src "ls180.v:575.13-575.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:546.6-546.38" + attribute \src "ls180.v:576.6-576.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:548.5-548.44" + attribute \src "ls180.v:578.5-578.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:543.6-543.39" + attribute \src "ls180.v:573.6-573.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:542.6-542.39" + attribute \src "ls180.v:572.6-572.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:547.5-547.44" + attribute \src "ls180.v:577.5-577.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:544.6-544.36" + attribute \src "ls180.v:574.6-574.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:611.12-611.39" + attribute \src "ls180.v:641.12-641.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:615.5-615.38" + attribute \src "ls180.v:645.5-645.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:616.5-616.47" + attribute \src "ls180.v:646.5-646.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:613.6-613.37" + attribute \src "ls180.v:643.6-643.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:614.5-614.37" + attribute \src "ls180.v:644.5-644.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:612.5-612.39" + attribute \src "ls180.v:642.5-642.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:623.32-623.69" + attribute \src "ls180.v:653.32-653.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:622.6-622.43" + attribute \src "ls180.v:652.6-652.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:621.32-621.68" + attribute \src "ls180.v:651.32-651.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:620.6-620.42" + attribute \src "ls180.v:650.6-650.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:619.11-619.48" + attribute \src "ls180.v:649.11-649.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:618.32-618.69" + attribute \src "ls180.v:648.32-648.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:617.6-617.43" + attribute \src "ls180.v:647.6-647.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:643.5-643.43" + attribute \src "ls180.v:673.5-673.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:665.11-665.63" + attribute \src "ls180.v:695.11-695.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:670.6-670.58" + attribute \src "ls180.v:700.6-700.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:675.6-675.64" + attribute \src "ls180.v:705.6-705.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:676.6-676.63" + attribute \src "ls180.v:706.6-706.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:674.13-674.78" + attribute \src "ls180.v:704.13-704.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:673.6-673.69" + attribute \src "ls180.v:703.6-703.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:679.6-679.65" + attribute \src "ls180.v:709.6-709.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:680.6-680.64" + attribute \src "ls180.v:710.6-710.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:678.13-678.79" + attribute \src "ls180.v:708.13-708.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:677.6-677.70" + attribute \src "ls180.v:707.6-707.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:662.11-662.61" + attribute \src "ls180.v:692.11-692.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:664.11-664.63" + attribute \src "ls180.v:694.11-694.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:671.12-671.67" + attribute \src "ls180.v:701.12-701.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:672.13-672.70" + attribute \src "ls180.v:702.13-702.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:663.5-663.57" + attribute \src "ls180.v:693.5-693.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:646.5-646.60" + attribute \src "ls180.v:676.5-676.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:647.5-647.59" + attribute \src "ls180.v:677.5-677.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:649.13-649.75" + attribute \src "ls180.v:679.13-679.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:648.6-648.66" + attribute \src "ls180.v:678.6-678.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:645.6-645.61" + attribute \src "ls180.v:675.6-675.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:644.6-644.61" + attribute \src "ls180.v:674.6-674.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:652.6-652.63" + attribute \src "ls180.v:682.6-682.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:653.6-653.62" + attribute \src "ls180.v:683.6-683.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:655.13-655.77" + attribute \src "ls180.v:685.13-685.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:654.6-654.68" + attribute \src "ls180.v:684.6-684.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:651.6-651.63" + attribute \src "ls180.v:681.6-681.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:650.6-650.63" + attribute \src "ls180.v:680.6-680.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:660.13-660.71" + attribute \src "ls180.v:690.13-690.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:661.13-661.72" + attribute \src "ls180.v:691.13-691.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:658.6-658.63" + attribute \src "ls180.v:688.6-688.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:659.6-659.69" + attribute \src "ls180.v:689.6-689.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:656.6-656.63" + attribute \src "ls180.v:686.6-686.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:657.6-657.69" + attribute \src "ls180.v:687.6-687.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:666.11-666.66" + attribute \src "ls180.v:696.11-696.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:667.13-667.70" + attribute \src "ls180.v:697.13-697.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:669.13-669.70" + attribute \src "ls180.v:699.13-699.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:668.6-668.60" + attribute \src "ls180.v:698.6-698.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:683.6-683.51" + attribute \src "ls180.v:713.6-713.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:684.6-684.50" + attribute \src "ls180.v:714.6-714.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:686.13-686.65" + attribute \src "ls180.v:716.13-716.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:685.6-685.56" + attribute \src "ls180.v:715.6-715.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:682.6-682.51" + attribute \src "ls180.v:712.6-712.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:681.6-681.51" + attribute \src "ls180.v:711.6-711.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:689.5-689.52" + attribute \src "ls180.v:719.5-719.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:690.5-690.51" + attribute \src "ls180.v:720.5-720.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:692.12-692.66" + attribute \src "ls180.v:722.12-722.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:691.5-691.57" + attribute \src "ls180.v:721.5-721.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:688.6-688.53" + attribute \src "ls180.v:718.6-718.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:687.5-687.52" + attribute \src "ls180.v:717.5-717.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:635.12-635.49" + attribute \src "ls180.v:665.12-665.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:636.12-636.50" + attribute \src "ls180.v:666.12-666.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:637.5-637.44" + attribute \src "ls180.v:667.5-667.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:640.5-640.47" + attribute \src "ls180.v:670.5-670.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:641.5-641.48" + attribute \src "ls180.v:671.5-671.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:642.5-642.49" + attribute \src "ls180.v:672.5-672.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:638.5-638.44" + attribute \src "ls180.v:668.5-668.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:639.5-639.43" + attribute \src "ls180.v:669.5-669.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:634.5-634.38" + attribute \src "ls180.v:664.5-664.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:633.5-633.38" + attribute \src "ls180.v:663.5-663.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:632.5-632.40" + attribute \src "ls180.v:662.5-662.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:631.6-631.41" + attribute \src "ls180.v:661.6-661.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:627.13-627.45" + attribute \src "ls180.v:657.13-657.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:628.6-628.38" + attribute \src "ls180.v:658.6-658.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:630.5-630.44" + attribute \src "ls180.v:660.5-660.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:625.6-625.39" + attribute \src "ls180.v:655.6-655.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:624.6-624.39" + attribute \src "ls180.v:654.6-654.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:629.5-629.44" + attribute \src "ls180.v:659.5-659.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:626.6-626.36" + attribute \src "ls180.v:656.6-656.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:693.12-693.39" + attribute \src "ls180.v:723.12-723.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:697.5-697.38" + attribute \src "ls180.v:727.5-727.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:698.5-698.47" + attribute \src "ls180.v:728.5-728.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:695.6-695.37" + attribute \src "ls180.v:725.6-725.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:696.5-696.37" + attribute \src "ls180.v:726.5-726.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:694.5-694.39" + attribute \src "ls180.v:724.5-724.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:705.32-705.69" + attribute \src "ls180.v:735.32-735.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:704.6-704.43" + attribute \src "ls180.v:734.6-734.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:703.32-703.68" + attribute \src "ls180.v:733.32-733.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:702.6-702.42" + attribute \src "ls180.v:732.6-732.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:701.11-701.48" + attribute \src "ls180.v:731.11-731.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:700.32-700.69" + attribute \src "ls180.v:730.32-730.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:699.6-699.43" + attribute \src "ls180.v:729.6-729.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:707.6-707.28" + attribute \src "ls180.v:737.6-737.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:725.6-725.30" + attribute \src "ls180.v:755.6-755.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:714.13-714.48" + attribute \src "ls180.v:744.13-744.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:715.12-715.48" + attribute \src "ls180.v:745.12-745.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:716.5-716.42" + attribute \src "ls180.v:746.5-746.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:719.6-719.46" + attribute \src "ls180.v:749.6-749.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:720.6-720.47" + attribute \src "ls180.v:750.6-750.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:721.6-721.48" + attribute \src "ls180.v:751.6-751.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:717.5-717.42" + attribute \src "ls180.v:747.5-747.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:718.5-718.41" + attribute \src "ls180.v:748.5-748.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:713.5-713.36" + attribute \src "ls180.v:743.5-743.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:712.6-712.37" + attribute \src "ls180.v:742.6-742.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:724.11-724.38" + attribute \src "ls180.v:754.11-754.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:723.12-723.41" + attribute \src "ls180.v:753.12-753.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:722.11-722.39" + attribute \src "ls180.v:752.11-752.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:711.5-711.41" + attribute \src "ls180.v:741.5-741.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:710.5-710.36" + attribute \src "ls180.v:740.5-740.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:708.5-708.37" + attribute \src "ls180.v:738.5-738.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:709.5-709.38" + attribute \src "ls180.v:739.5-739.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:743.6-743.30" + attribute \src "ls180.v:773.6-773.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:732.13-732.48" + attribute \src "ls180.v:762.13-762.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:733.12-733.48" + attribute \src "ls180.v:763.12-763.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:734.5-734.42" + attribute \src "ls180.v:764.5-764.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:737.6-737.46" + attribute \src "ls180.v:767.6-767.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:738.6-738.47" + attribute \src "ls180.v:768.6-768.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:739.6-739.48" + attribute \src "ls180.v:769.6-769.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:735.5-735.42" + attribute \src "ls180.v:765.5-765.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:736.5-736.41" + attribute \src "ls180.v:766.5-766.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:731.5-731.36" + attribute \src "ls180.v:761.5-761.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:730.6-730.37" + attribute \src "ls180.v:760.6-760.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:742.11-742.38" + attribute \src "ls180.v:772.11-772.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:741.12-741.41" + attribute \src "ls180.v:771.12-771.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:740.11-740.39" + attribute \src "ls180.v:770.11-770.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:729.5-729.41" + attribute \src "ls180.v:759.5-759.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:728.6-728.37" + attribute \src "ls180.v:758.6-758.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:726.5-726.37" + attribute \src "ls180.v:756.5-756.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:727.5-727.38" + attribute \src "ls180.v:757.5-757.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:287.6-287.20" + attribute \src "ls180.v:317.6-317.20" wire \main_sdram_cke - attribute \src "ls180.v:355.5-355.24" + attribute \src "ls180.v:385.5-385.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:356.12-356.36" + attribute \src "ls180.v:386.12-386.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:357.11-357.36" + attribute \src "ls180.v:387.11-387.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:358.5-358.31" + attribute \src "ls180.v:388.5-388.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:361.5-361.35" + attribute \src "ls180.v:391.5-391.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:362.5-362.36" + attribute \src "ls180.v:392.5-392.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:359.5-359.31" + attribute \src "ls180.v:389.5-389.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:360.5-360.30" + attribute \src "ls180.v:390.5-390.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:354.5-354.25" + attribute \src "ls180.v:384.5-384.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:353.5-353.25" + attribute \src "ls180.v:383.5-383.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:295.6-295.32" + attribute \src "ls180.v:325.6-325.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:294.6-294.33" + attribute \src "ls180.v:324.6-324.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:297.5-297.31" + attribute \src "ls180.v:327.5-327.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:296.6-296.33" + attribute \src "ls180.v:326.6-326.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:293.5-293.26" + attribute \src "ls180.v:323.5-323.26" wire \main_sdram_command_re - attribute \src "ls180.v:292.11-292.37" + attribute \src "ls180.v:322.11-322.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:346.5-346.28" + attribute \src "ls180.v:376.5-376.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:337.12-337.37" + attribute \src "ls180.v:367.12-367.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:338.11-338.33" + attribute \src "ls180.v:368.11-368.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:339.5-339.28" + attribute \src "ls180.v:369.5-369.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:343.6-343.27" + attribute \src "ls180.v:373.6-373.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:340.5-340.27" + attribute \src "ls180.v:370.5-370.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:344.6-344.27" + attribute \src "ls180.v:374.6-374.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:341.5-341.28" + attribute \src "ls180.v:371.5-371.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:351.13-351.37" + attribute \src "ls180.v:381.13-381.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:350.5-350.32" + attribute \src "ls180.v:380.5-380.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:352.6-352.36" + attribute \src "ls180.v:382.6-382.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:345.6-345.31" + attribute \src "ls180.v:375.6-375.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:342.5-342.27" + attribute \src "ls180.v:372.5-372.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:347.13-347.37" + attribute \src "ls180.v:377.13-377.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:348.5-348.32" + attribute \src "ls180.v:378.5-378.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:349.12-349.41" + attribute \src "ls180.v:379.12-379.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:761.5-761.19" + attribute \src "ls180.v:791.5-791.19" wire \main_sdram_en0 - attribute \src "ls180.v:764.5-764.19" + attribute \src "ls180.v:794.5-794.19" wire \main_sdram_en1 - attribute \src "ls180.v:767.6-767.30" + attribute \src "ls180.v:797.6-797.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:309.13-309.44" + attribute \src "ls180.v:339.13-339.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:310.6-310.37" + attribute \src "ls180.v:340.6-340.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:312.6-312.44" + attribute \src "ls180.v:342.6-342.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:307.6-307.38" + attribute \src "ls180.v:337.6-337.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:306.6-306.38" + attribute \src "ls180.v:336.6-336.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:311.6-311.44" + attribute \src "ls180.v:341.6-341.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:308.6-308.35" + attribute \src "ls180.v:338.6-338.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:316.13-316.44" + attribute \src "ls180.v:346.13-346.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:317.6-317.37" + attribute \src "ls180.v:347.6-347.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:319.6-319.44" + attribute \src "ls180.v:349.6-349.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:314.6-314.38" + attribute \src "ls180.v:344.6-344.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:313.6-313.38" + attribute \src "ls180.v:343.6-343.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:318.6-318.44" + attribute \src "ls180.v:348.6-348.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:315.6-315.35" + attribute \src "ls180.v:345.6-345.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:323.13-323.44" + attribute \src "ls180.v:353.13-353.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:324.6-324.37" + attribute \src "ls180.v:354.6-354.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:326.6-326.44" + attribute \src "ls180.v:356.6-356.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:321.6-321.38" + attribute \src "ls180.v:351.6-351.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:320.6-320.38" + attribute \src "ls180.v:350.6-350.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:325.6-325.44" + attribute \src "ls180.v:355.6-355.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:322.6-322.35" + attribute \src "ls180.v:352.6-352.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:330.13-330.44" + attribute \src "ls180.v:360.13-360.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:331.6-331.37" + attribute \src "ls180.v:361.6-361.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:333.6-333.44" + attribute \src "ls180.v:363.6-363.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:328.6-328.38" + attribute \src "ls180.v:358.6-358.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:327.6-327.38" + attribute \src "ls180.v:357.6-357.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:332.6-332.44" + attribute \src "ls180.v:362.6-362.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:329.6-329.35" + attribute \src "ls180.v:359.6-359.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:336.13-336.39" + attribute \src "ls180.v:366.13-366.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:334.12-334.38" + attribute \src "ls180.v:364.12-364.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:335.11-335.40" + attribute \src "ls180.v:365.11-365.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:247.5-247.29" + attribute \src "ls180.v:277.5-277.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:238.13-238.39" + attribute \src "ls180.v:268.13-268.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:239.12-239.35" + attribute \src "ls180.v:269.12-269.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:240.5-240.29" + attribute \src "ls180.v:270.5-270.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:244.6-244.28" + attribute \src "ls180.v:274.6-274.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:241.5-241.28" + attribute \src "ls180.v:271.5-271.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:245.6-245.28" + attribute \src "ls180.v:275.6-275.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:242.5-242.29" + attribute \src "ls180.v:272.5-272.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:252.12-252.37" + attribute \src "ls180.v:282.12-282.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:251.6-251.34" + attribute \src "ls180.v:281.6-281.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:253.5-253.36" + attribute \src "ls180.v:283.5-283.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:246.6-246.32" + attribute \src "ls180.v:276.6-276.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:243.5-243.28" + attribute \src "ls180.v:273.5-273.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:248.13-248.38" + attribute \src "ls180.v:278.13-278.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:249.6-249.34" + attribute \src "ls180.v:279.6-279.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:250.12-250.42" + attribute \src "ls180.v:280.12-280.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:279.5-279.31" + attribute \src "ls180.v:309.5-309.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:270.12-270.40" + attribute \src "ls180.v:300.12-300.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:271.11-271.36" + attribute \src "ls180.v:301.11-301.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:272.5-272.31" + attribute \src "ls180.v:302.5-302.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:276.5-276.29" + attribute \src "ls180.v:306.5-306.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:273.5-273.30" + attribute \src "ls180.v:303.5-303.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:277.5-277.29" + attribute \src "ls180.v:307.5-307.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:274.5-274.31" + attribute \src "ls180.v:304.5-304.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:284.13-284.40" + attribute \src "ls180.v:314.13-314.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:283.5-283.35" + attribute \src "ls180.v:313.5-313.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:285.6-285.39" + attribute \src "ls180.v:315.6-315.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:278.5-278.33" + attribute \src "ls180.v:308.5-308.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:275.5-275.30" + attribute \src "ls180.v:305.5-305.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:280.12-280.39" + attribute \src "ls180.v:310.12-310.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:281.5-281.35" + attribute \src "ls180.v:311.5-311.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:282.11-282.43" + attribute \src "ls180.v:312.11-312.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:762.6-762.26" + attribute \src "ls180.v:792.6-792.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:765.6-765.26" + attribute \src "ls180.v:795.6-795.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:744.12-744.28" + attribute \src "ls180.v:774.12-774.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:745.11-745.28" + attribute \src "ls180.v:775.11-775.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:288.6-288.20" + attribute \src "ls180.v:318.6-318.20" wire \main_sdram_odt - attribute \src "ls180.v:371.5-371.31" + attribute \src "ls180.v:401.5-401.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:369.6-369.32" + attribute \src "ls180.v:399.6-399.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:370.5-370.31" + attribute \src "ls180.v:400.5-400.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:706.6-706.28" + attribute \src "ls180.v:736.6-736.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:291.5-291.18" + attribute \src "ls180.v:321.5-321.18" wire \main_sdram_re - attribute \src "ls180.v:759.6-759.31" + attribute \src "ls180.v:789.6-789.31" wire \main_sdram_read_available - attribute \src "ls180.v:289.6-289.24" + attribute \src "ls180.v:319.6-319.24" wire \main_sdram_reset_n - attribute \src "ls180.v:286.6-286.20" + attribute \src "ls180.v:316.6-316.20" wire \main_sdram_sel - attribute \src "ls180.v:377.5-377.31" + attribute \src "ls180.v:407.5-407.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:376.11-376.39" + attribute \src "ls180.v:406.11-406.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:373.6-373.32" + attribute \src "ls180.v:403.6-403.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:375.5-375.31" + attribute \src "ls180.v:405.5-405.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:372.5-372.32" + attribute \src "ls180.v:402.5-402.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:374.6-374.33" + attribute \src "ls180.v:404.6-404.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:263.6-263.31" + attribute \src "ls180.v:293.6-293.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:254.13-254.40" + attribute \src "ls180.v:284.13-284.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:255.12-255.36" + attribute \src "ls180.v:285.12-285.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:256.6-256.31" + attribute \src "ls180.v:286.6-286.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:260.6-260.29" + attribute \src "ls180.v:290.6-290.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:257.6-257.30" + attribute \src "ls180.v:287.6-287.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:261.6-261.29" + attribute \src "ls180.v:291.6-291.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:258.6-258.31" + attribute \src "ls180.v:288.6-288.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:268.12-268.38" + attribute \src "ls180.v:298.12-298.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:267.6-267.35" + attribute \src "ls180.v:297.6-297.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:269.5-269.37" + attribute \src "ls180.v:299.5-299.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:262.6-262.33" + attribute \src "ls180.v:292.6-292.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:259.6-259.30" + attribute \src "ls180.v:289.6-289.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:264.13-264.39" + attribute \src "ls180.v:294.13-294.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:265.6-265.35" + attribute \src "ls180.v:295.6-295.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:266.12-266.43" + attribute \src "ls180.v:296.12-296.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:304.12-304.29" + attribute \src "ls180.v:334.12-334.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:747.5-747.24" + attribute \src "ls180.v:777.5-777.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:748.5-748.24" + attribute \src "ls180.v:778.5-778.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:746.11-746.33" + attribute \src "ls180.v:776.11-776.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:290.11-290.29" + attribute \src "ls180.v:320.11-320.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:755.5-755.29" + attribute \src "ls180.v:785.5-785.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:754.32-754.56" + attribute \src "ls180.v:784.32-784.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:753.6-753.30" + attribute \src "ls180.v:783.6-783.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:752.32-752.56" + attribute \src "ls180.v:782.32-782.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:751.6-751.30" + attribute \src "ls180.v:781.6-781.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:763.11-763.27" + attribute \src "ls180.v:793.11-793.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:766.11-766.27" + attribute \src "ls180.v:796.11-796.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:366.12-366.35" + attribute \src "ls180.v:396.12-396.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:368.11-368.34" + attribute \src "ls180.v:398.11-398.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:365.6-365.28" + attribute \src "ls180.v:395.6-395.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:367.6-367.28" + attribute \src "ls180.v:397.6-397.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:364.6-364.27" + attribute \src "ls180.v:394.6-394.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:750.32-750.56" + attribute \src "ls180.v:780.32-780.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:749.6-749.30" + attribute \src "ls180.v:779.6-779.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:758.11-758.35" + attribute \src "ls180.v:788.11-788.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:757.32-757.56" + attribute \src "ls180.v:787.32-787.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:756.6-756.30" + attribute \src "ls180.v:786.6-786.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:363.6-363.30" + attribute \src "ls180.v:393.6-393.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:305.6-305.19" + attribute \src "ls180.v:335.6-335.19" wire \main_sdram_we - attribute \src "ls180.v:303.5-303.25" + attribute \src "ls180.v:333.5-333.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:302.12-302.37" + attribute \src "ls180.v:332.12-332.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:760.6-760.32" + attribute \src "ls180.v:790.6-790.32" wire \main_sdram_write_available - attribute \src "ls180.v:813.6-813.21" - wire \main_sink_first - attribute \src "ls180.v:814.6-814.20" - wire \main_sink_last - attribute \src "ls180.v:815.12-815.34" - wire width 8 \main_sink_payload_data - attribute \src "ls180.v:812.5-812.20" - wire \main_sink_ready - attribute \src "ls180.v:811.6-811.21" - wire \main_sink_valid - attribute \src "ls180.v:823.5-823.22" - wire \main_source_first - attribute \src "ls180.v:824.5-824.21" - wire \main_source_last - attribute \src "ls180.v:825.11-825.35" - wire width 8 \main_source_payload_data - attribute \src "ls180.v:822.6-822.23" - wire \main_source_ready - attribute \src "ls180.v:821.5-821.22" - wire \main_source_valid - attribute \src "ls180.v:968.12-968.40" - wire width 16 \main_spi_master_clk_divider0 - attribute \src "ls180.v:990.12-990.40" - wire width 16 \main_spi_master_clk_divider1 - attribute \src "ls180.v:985.5-985.31" - wire \main_spi_master_clk_enable - attribute \src "ls180.v:992.6-992.30" - wire \main_spi_master_clk_fall - attribute \src "ls180.v:991.6-991.30" - wire \main_spi_master_clk_rise - attribute \src "ls180.v:972.5-972.31" - wire \main_spi_master_control_re - attribute \src "ls180.v:971.12-971.43" - wire width 16 \main_spi_master_control_storage - attribute \src "ls180.v:987.11-987.32" - wire width 3 \main_spi_master_count - attribute \src "ls180.v:1745.11-1745.54" - wire width 3 \main_spi_master_count_spimaster0_next_value - attribute \src "ls180.v:1746.5-1746.51" - wire \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:966.6-966.24" - wire \main_spi_master_cs - attribute \src "ls180.v:986.5-986.30" - wire \main_spi_master_cs_enable - attribute \src "ls180.v:982.5-982.26" - wire \main_spi_master_cs_re - attribute \src "ls180.v:981.5-981.31" - wire \main_spi_master_cs_storage - attribute \src "ls180.v:962.5-962.26" - wire \main_spi_master_done0 - attribute \src "ls180.v:973.6-973.27" - wire \main_spi_master_done1 - attribute \src "ls180.v:963.5-963.24" - wire \main_spi_master_irq - attribute \src "ls180.v:961.12-961.35" - wire width 8 \main_spi_master_length0 - attribute \src "ls180.v:970.12-970.35" - wire width 8 \main_spi_master_length1 - attribute \src "ls180.v:967.6-967.30" - wire \main_spi_master_loopback - attribute \src "ls180.v:984.5-984.32" - wire \main_spi_master_loopback_re - attribute \src "ls180.v:983.5-983.37" - wire \main_spi_master_loopback_storage - attribute \src "ls180.v:965.11-965.31" - wire width 8 \main_spi_master_miso - attribute \src "ls180.v:995.11-995.36" - wire width 8 \main_spi_master_miso_data - attribute \src "ls180.v:989.5-989.31" - wire \main_spi_master_miso_latch - attribute \src "ls180.v:978.12-978.39" - wire width 8 \main_spi_master_miso_status - attribute \src "ls180.v:979.6-979.29" - wire \main_spi_master_miso_we - attribute \src "ls180.v:964.12-964.32" - wire width 8 \main_spi_master_mosi - attribute \src "ls180.v:993.11-993.36" - wire width 8 \main_spi_master_mosi_data - attribute \src "ls180.v:988.5-988.31" - wire \main_spi_master_mosi_latch - attribute \src "ls180.v:977.5-977.28" - wire \main_spi_master_mosi_re - attribute \src "ls180.v:994.11-994.35" - wire width 3 \main_spi_master_mosi_sel - attribute \src "ls180.v:976.11-976.39" - wire width 8 \main_spi_master_mosi_storage - attribute \src "ls180.v:980.6-980.25" - wire \main_spi_master_sel - attribute \src "ls180.v:960.6-960.28" - wire \main_spi_master_start0 - attribute \src "ls180.v:969.5-969.27" - wire \main_spi_master_start1 - attribute \src "ls180.v:974.6-974.35" - wire \main_spi_master_status_status - attribute \src "ls180.v:975.6-975.31" - wire \main_spi_master_status_we - attribute \src "ls180.v:809.12-809.24" - wire width 32 \main_storage - attribute \src "ls180.v:819.11-819.27" - wire width 4 \main_tx_bitcount - attribute \src "ls180.v:820.5-820.17" - wire \main_tx_busy - attribute \src "ls180.v:818.11-818.22" - wire width 8 \main_tx_reg - attribute \src "ls180.v:826.5-826.23" - wire \main_uart_clk_rxen - attribute \src "ls180.v:816.5-816.23" - wire \main_uart_clk_txen - attribute \src "ls180.v:857.12-857.44" + attribute \src "ls180.v:990.6-990.27" + wire \main_spimaster0_start + attribute \src "ls180.v:1000.12-1000.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:1001.12-1001.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1002.5-1002.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1003.6-1003.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1004.6-1004.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1005.6-1005.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1006.11-1006.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1007.5-1007.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1008.12-1008.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1009.6-1009.25" + wire \main_spimaster19_we + attribute \src "ls180.v:991.12-991.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1063.5-1063.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1062.12-1062.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1010.6-1010.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1011.5-1011.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1012.5-1012.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1013.5-1013.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1014.5-1014.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1015.5-1015.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1016.5-1016.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1017.11-1017.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1783.11-1783.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1784.5-1784.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1018.5-1018.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1019.5-1019.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:992.5-992.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1020.12-1020.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1021.6-1021.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1022.6-1022.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1023.11-1023.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1024.11-1024.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1025.11-1025.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:993.5-993.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:994.12-994.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:995.11-995.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:996.6-996.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:997.6-997.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:998.12-998.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:999.5-999.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1034.13-1034.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1056.12-1056.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1051.5-1051.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1058.6-1058.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1057.6-1057.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1038.5-1038.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1037.12-1037.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1053.11-1053.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1787.11-1787.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1788.5-1788.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1032.6-1032.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1052.5-1052.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1048.5-1048.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1047.5-1047.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1028.5-1028.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1039.6-1039.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1029.5-1029.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1027.12-1027.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1036.12-1036.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1033.6-1033.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1050.5-1050.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1049.5-1049.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1031.11-1031.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1061.11-1061.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1055.5-1055.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1044.12-1044.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1045.6-1045.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1030.12-1030.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1059.11-1059.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1054.5-1054.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1043.5-1043.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1060.11-1060.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1042.11-1042.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1046.6-1046.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1026.6-1026.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1035.5-1035.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1040.6-1040.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1041.6-1041.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:887.12-887.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:856.6-856.39" + attribute \src "ls180.v:886.6-886.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:859.11-859.43" + attribute \src "ls180.v:889.11-889.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:858.6-858.39" + attribute \src "ls180.v:888.6-888.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:861.5-861.30" + attribute \src "ls180.v:891.5-891.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:853.12-853.43" + attribute \src "ls180.v:883.12-883.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:852.6-852.38" + attribute \src "ls180.v:882.6-882.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:855.11-855.42" + attribute \src "ls180.v:885.11-885.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:854.6-854.38" + attribute \src "ls180.v:884.6-884.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:860.11-860.41" + attribute \src "ls180.v:890.11-890.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:841.6-841.19" + attribute \src "ls180.v:871.6-871.19" wire \main_uart_irq - attribute \src "ls180.v:950.5-950.20" + attribute \src "ls180.v:857.12-857.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:847.12-847.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:840.5-840.21" + wire \main_uart_phy_re + attribute \src "ls180.v:858.6-858.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:861.11-861.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:862.5-862.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:859.5-859.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:860.11-860.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:843.6-843.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:844.6-844.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:845.12-845.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:842.5-842.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:841.6-841.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:853.5-853.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:854.5-854.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:855.11-855.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:852.6-852.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:851.5-851.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:839.12-839.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:849.11-849.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:850.5-850.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:848.11-848.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:856.5-856.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:846.5-846.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:980.5-980.20" wire \main_uart_reset - attribute \src "ls180.v:850.5-850.23" + attribute \src "ls180.v:880.5-880.23" wire \main_uart_rx_clear - attribute \src "ls180.v:934.11-934.36" + attribute \src "ls180.v:964.11-964.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:939.6-939.31" + attribute \src "ls180.v:969.6-969.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:945.6-945.37" + attribute \src "ls180.v:975.6-975.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:946.6-946.36" + attribute \src "ls180.v:976.6-976.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:944.12-944.50" + attribute \src "ls180.v:974.12-974.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:948.6-948.38" + attribute \src "ls180.v:978.6-978.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:949.6-949.37" + attribute \src "ls180.v:979.6-979.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:947.12-947.51" + attribute \src "ls180.v:977.12-977.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:931.11-931.35" + attribute \src "ls180.v:961.11-961.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:943.12-943.36" + attribute \src "ls180.v:973.12-973.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:933.11-933.36" + attribute \src "ls180.v:963.11-963.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:940.12-940.40" + attribute \src "ls180.v:970.12-970.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:941.12-941.42" + attribute \src "ls180.v:971.12-971.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:942.6-942.33" + attribute \src "ls180.v:972.6-972.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:923.6-923.26" + attribute \src "ls180.v:953.6-953.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:924.5-924.31" + attribute \src "ls180.v:954.5-954.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:932.5-932.30" + attribute \src "ls180.v:962.5-962.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:915.6-915.34" + attribute \src "ls180.v:945.6-945.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:916.6-916.33" + attribute \src "ls180.v:946.6-946.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:917.12-917.47" + attribute \src "ls180.v:947.12-947.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:914.6-914.34" + attribute \src "ls180.v:944.6-944.34" wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:913.6-913.34" + attribute \src "ls180.v:943.6-943.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:920.6-920.36" + attribute \src "ls180.v:950.6-950.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:921.6-921.35" + attribute \src "ls180.v:951.6-951.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:922.12-922.49" + attribute \src "ls180.v:952.12-952.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:919.6-919.36" + attribute \src "ls180.v:949.6-949.36" wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:918.6-918.36" + attribute \src "ls180.v:948.6-948.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:929.12-929.42" + attribute \src "ls180.v:959.12-959.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:930.12-930.43" + attribute \src "ls180.v:960.12-960.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:927.6-927.35" + attribute \src "ls180.v:957.6-957.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:928.6-928.41" + attribute \src "ls180.v:958.6-958.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:925.6-925.35" + attribute \src "ls180.v:955.6-955.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:926.6-926.41" + attribute \src "ls180.v:956.6-956.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:935.11-935.39" + attribute \src "ls180.v:965.11-965.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:936.12-936.42" + attribute \src "ls180.v:966.12-966.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:938.12-938.42" + attribute \src "ls180.v:968.12-968.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:937.6-937.33" + attribute \src "ls180.v:967.6-967.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:851.5-851.29" + attribute \src "ls180.v:881.5-881.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:848.5-848.25" + attribute \src "ls180.v:878.5-878.25" wire \main_uart_rx_pending - attribute \src "ls180.v:847.6-847.25" + attribute \src "ls180.v:877.6-877.25" wire \main_uart_rx_status - attribute \src "ls180.v:849.6-849.26" + attribute \src "ls180.v:879.6-879.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:839.6-839.30" + attribute \src "ls180.v:869.6-869.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:840.6-840.26" + attribute \src "ls180.v:870.6-870.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:864.6-864.29" + attribute \src "ls180.v:894.6-894.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:865.6-865.25" + attribute \src "ls180.v:895.6-895.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:834.12-834.28" + attribute \src "ls180.v:864.12-864.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:833.6-833.23" + attribute \src "ls180.v:863.6-863.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:836.12-836.28" + attribute \src "ls180.v:866.12-866.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:835.6-835.23" + attribute \src "ls180.v:865.6-865.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:845.5-845.23" + attribute \src "ls180.v:875.5-875.23" wire \main_uart_tx_clear - attribute \src "ls180.v:897.11-897.36" + attribute \src "ls180.v:927.11-927.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:902.6-902.31" + attribute \src "ls180.v:932.6-932.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:908.6-908.37" + attribute \src "ls180.v:938.6-938.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:909.6-909.36" + attribute \src "ls180.v:939.6-939.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:907.12-907.50" + attribute \src "ls180.v:937.12-937.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:911.6-911.38" + attribute \src "ls180.v:941.6-941.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:912.6-912.37" + attribute \src "ls180.v:942.6-942.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:910.12-910.51" + attribute \src "ls180.v:940.12-940.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:894.11-894.35" + attribute \src "ls180.v:924.11-924.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:906.12-906.36" + attribute \src "ls180.v:936.12-936.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:896.11-896.36" + attribute \src "ls180.v:926.11-926.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:903.12-903.40" + attribute \src "ls180.v:933.12-933.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:904.12-904.42" + attribute \src "ls180.v:934.12-934.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:905.6-905.33" + attribute \src "ls180.v:935.6-935.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:886.6-886.26" + attribute \src "ls180.v:916.6-916.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:887.5-887.31" + attribute \src "ls180.v:917.5-917.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:895.5-895.30" + attribute \src "ls180.v:925.5-925.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:878.5-878.33" + attribute \src "ls180.v:908.5-908.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:879.5-879.32" + attribute \src "ls180.v:909.5-909.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:880.12-880.47" + attribute \src "ls180.v:910.12-910.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:877.6-877.34" + attribute \src "ls180.v:907.6-907.34" wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:876.6-876.34" + attribute \src "ls180.v:906.6-906.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:883.6-883.36" + attribute \src "ls180.v:913.6-913.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:884.6-884.35" + attribute \src "ls180.v:914.6-914.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:885.12-885.49" + attribute \src "ls180.v:915.12-915.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:882.6-882.36" + attribute \src "ls180.v:912.6-912.36" wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:881.6-881.36" + attribute \src "ls180.v:911.6-911.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:892.12-892.42" + attribute \src "ls180.v:922.12-922.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:893.12-893.43" + attribute \src "ls180.v:923.12-923.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:890.6-890.35" + attribute \src "ls180.v:920.6-920.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:891.6-891.41" + attribute \src "ls180.v:921.6-921.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:888.6-888.35" + attribute \src "ls180.v:918.6-918.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:889.6-889.41" + attribute \src "ls180.v:919.6-919.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:898.11-898.39" + attribute \src "ls180.v:928.11-928.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:899.12-899.42" + attribute \src "ls180.v:929.12-929.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:901.12-901.42" + attribute \src "ls180.v:931.12-931.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:900.6-900.33" + attribute \src "ls180.v:930.6-930.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:846.5-846.29" + attribute \src "ls180.v:876.5-876.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:843.5-843.25" + attribute \src "ls180.v:873.5-873.25" wire \main_uart_tx_pending - attribute \src "ls180.v:842.6-842.25" + attribute \src "ls180.v:872.6-872.25" wire \main_uart_tx_status - attribute \src "ls180.v:844.6-844.26" + attribute \src "ls180.v:874.6-874.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:862.6-862.30" + attribute \src "ls180.v:892.6-892.30" wire \main_uart_txempty_status - attribute \src "ls180.v:863.6-863.26" + attribute \src "ls180.v:893.6-893.26" wire \main_uart_txempty_we - attribute \src "ls180.v:837.6-837.29" + attribute \src "ls180.v:867.6-867.29" wire \main_uart_txfull_status - attribute \src "ls180.v:838.6-838.25" + attribute \src "ls180.v:868.6-868.25" wire \main_uart_txfull_we - attribute \src "ls180.v:868.6-868.31" + attribute \src "ls180.v:898.6-898.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:869.6-869.30" + attribute \src "ls180.v:899.6-899.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:870.12-870.44" + attribute \src "ls180.v:900.12-900.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:867.6-867.31" + attribute \src "ls180.v:897.6-897.31" wire \main_uart_uart_sink_ready - attribute \src "ls180.v:866.6-866.31" + attribute \src "ls180.v:896.6-896.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:873.6-873.33" + attribute \src "ls180.v:903.6-903.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:874.6-874.32" + attribute \src "ls180.v:904.6-904.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:875.12-875.46" + attribute \src "ls180.v:905.12-905.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:872.6-872.33" + attribute \src "ls180.v:902.6-902.33" wire \main_uart_uart_source_ready - attribute \src "ls180.v:871.6-871.33" + attribute \src "ls180.v:901.6-901.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:787.5-787.22" + attribute \src "ls180.v:817.5-817.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:781.13-781.30" + attribute \src "ls180.v:811.13-811.30" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:790.12-790.29" + attribute \src "ls180.v:820.12-820.29" wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:789.12-789.29" + attribute \src "ls180.v:819.12-819.29" wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:785.6-785.23" + attribute \src "ls180.v:815.6-815.23" wire \main_wb_sdram_cyc - attribute \src "ls180.v:783.13-783.32" + attribute \src "ls180.v:813.13-813.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:782.13-782.32" + attribute \src "ls180.v:812.13-812.32" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:791.5-791.22" + attribute \src "ls180.v:821.5-821.22" wire \main_wb_sdram_err - attribute \src "ls180.v:784.12-784.29" + attribute \src "ls180.v:814.12-814.29" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:786.6-786.23" + attribute \src "ls180.v:816.6-816.23" wire \main_wb_sdram_stb - attribute \src "ls180.v:788.6-788.22" + attribute \src "ls180.v:818.6-818.22" wire \main_wb_sdram_we - attribute \src "ls180.v:805.5-805.24" + attribute \src "ls180.v:835.5-835.24" wire \main_wdata_consumed - attribute \src "ls180.v:9976.11-9976.17" + attribute \src "ls180.v:10055.11-10055.17" wire width 7 \memadr - attribute \src "ls180.v:9996.12-9996.18" + attribute \src "ls180.v:10075.12-10075.18" wire width 25 \memdat - attribute \src "ls180.v:10010.12-10010.20" + attribute \src "ls180.v:10089.12-10089.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10024.12-10024.20" + attribute \src "ls180.v:10103.12-10103.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10038.12-10038.20" + attribute \src "ls180.v:10117.12-10117.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10052.11-10052.19" + attribute \src "ls180.v:10131.11-10131.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10053.11-10053.19" + attribute \src "ls180.v:10132.11-10132.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10069.11-10069.19" + attribute \src "ls180.v:10148.11-10148.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10070.11-10070.19" + attribute \src "ls180.v:10149.11-10149.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10086.11-10086.19" + attribute \src "ls180.v:10165.11-10165.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10100.11-10100.19" + attribute \src "ls180.v:10179.11-10179.19" wire width 10 \memdat_9 - attribute \src "ls180.v:33.20-33.22" - wire width 42 input 29 \nc - attribute \src "ls180.v:219.6-219.13" + attribute \src "ls180.v:51.20-51.22" + wire width 36 input 47 \nc + attribute \src "ls180.v:249.6-249.13" wire \por_clk - attribute \src "ls180.v:34.13-34.17" - wire output 30 \pwm0 - attribute \src "ls180.v:35.13-35.17" - wire output 31 \pwm1 - attribute \src "ls180.v:36.13-36.23" - wire output 32 \sdcard_clk - attribute \src "ls180.v:37.13-37.25" - wire input 33 \sdcard_cmd_i - attribute \src "ls180.v:38.13-38.25" - wire output 34 \sdcard_cmd_o - attribute \src "ls180.v:39.13-39.26" - wire output 35 \sdcard_cmd_oe - attribute \src "ls180.v:40.19-40.32" - wire width 4 input 36 \sdcard_data_i - attribute \src "ls180.v:41.19-41.32" - wire width 4 output 37 \sdcard_data_o - attribute \src "ls180.v:42.13-42.27" - wire output 38 \sdcard_data_oe - attribute \src "ls180.v:7.20-7.27" - wire width 13 output 3 \sdram_a - attribute \src "ls180.v:16.19-16.27" - wire width 2 output 12 \sdram_ba - attribute \src "ls180.v:13.13-13.24" - wire output 9 \sdram_cas_n - attribute \src "ls180.v:15.13-15.22" - wire output 11 \sdram_cke - attribute \src "ls180.v:18.13-18.24" - wire output 14 \sdram_clock - attribute \src "ls180.v:14.13-14.23" - wire output 10 \sdram_cs_n - attribute \src "ls180.v:17.19-17.27" - wire width 2 output 13 \sdram_dm - attribute \src "ls180.v:8.20-8.30" - wire width 16 input 4 \sdram_dq_i - attribute \src "ls180.v:9.20-9.30" - wire width 16 output 5 \sdram_dq_o - attribute \src "ls180.v:10.13-10.24" - wire output 6 \sdram_dq_oe - attribute \src "ls180.v:12.13-12.24" - wire output 8 \sdram_ras_n - attribute \src "ls180.v:11.13-11.23" - wire output 7 \sdram_we_n - attribute \src "ls180.v:2594.6-2594.15" + attribute \src "ls180.v:38.19-38.22" + wire width 2 output 34 \pwm + attribute \src "ls180.v:155.12-155.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:10.13-10.23" + wire output 6 \sdcard_clk + attribute \src "ls180.v:11.14-11.26" + wire output 7 \sdcard_cmd_i + attribute \src "ls180.v:12.13-12.25" + wire output 8 \sdcard_cmd_o + attribute \src "ls180.v:13.13-13.26" + wire output 9 \sdcard_cmd_oe + attribute \src "ls180.v:14.19-14.32" + wire width 4 input 10 \sdcard_data_i + attribute \src "ls180.v:15.19-15.32" + wire width 4 output 11 \sdcard_data_o + attribute \src "ls180.v:16.13-16.27" + wire output 12 \sdcard_data_oe + attribute \src "ls180.v:25.20-25.27" + wire width 13 output 21 \sdram_a + attribute \src "ls180.v:34.19-34.27" + wire width 2 output 30 \sdram_ba + attribute \src "ls180.v:31.13-31.24" + wire output 27 \sdram_cas_n + attribute \src "ls180.v:33.13-33.22" + wire output 29 \sdram_cke + attribute \src "ls180.v:36.13-36.24" + wire output 32 \sdram_clock + attribute \src "ls180.v:153.6-153.19" + wire \sdram_clock_1 + attribute \src "ls180.v:32.13-32.23" + wire output 28 \sdram_cs_n + attribute \src "ls180.v:35.19-35.27" + wire width 2 output 31 \sdram_dm + attribute \src "ls180.v:26.21-26.31" + wire width 16 output 22 \sdram_dq_i + attribute \src "ls180.v:27.20-27.30" + wire width 16 output 23 \sdram_dq_o + attribute \src "ls180.v:28.13-28.24" + wire output 24 \sdram_dq_oe + attribute \src "ls180.v:30.13-30.24" + wire output 26 \sdram_ras_n + attribute \src "ls180.v:29.13-29.23" + wire output 25 \sdram_we_n + attribute \src "ls180.v:2645.6-2645.15" wire \sdrio_clk - attribute \src "ls180.v:2595.6-2595.17" + attribute \src "ls180.v:2646.6-2646.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2604.6-2604.18" + attribute \src "ls180.v:2655.6-2655.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2605.6-2605.18" + attribute \src "ls180.v:2656.6-2656.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2606.6-2606.18" + attribute \src "ls180.v:2657.6-2657.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2607.6-2607.18" + attribute \src "ls180.v:2658.6-2658.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2608.6-2608.18" + attribute \src "ls180.v:2659.6-2659.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2609.6-2609.18" + attribute \src "ls180.v:2660.6-2660.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2610.6-2610.18" + attribute \src "ls180.v:2661.6-2661.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2611.6-2611.18" + attribute \src "ls180.v:2662.6-2662.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2612.6-2612.18" + attribute \src "ls180.v:2663.6-2663.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2613.6-2613.18" + attribute \src "ls180.v:2664.6-2664.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2596.6-2596.17" + attribute \src "ls180.v:2647.6-2647.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2614.6-2614.18" + attribute \src "ls180.v:2665.6-2665.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2615.6-2615.18" + attribute \src "ls180.v:2666.6-2666.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2616.6-2616.18" + attribute \src "ls180.v:2667.6-2667.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2617.6-2617.18" + attribute \src "ls180.v:2668.6-2668.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2618.6-2618.18" + attribute \src "ls180.v:2669.6-2669.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2619.6-2619.18" + attribute \src "ls180.v:2670.6-2670.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2620.6-2620.18" + attribute \src "ls180.v:2671.6-2671.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2621.6-2621.18" + attribute \src "ls180.v:2672.6-2672.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2622.6-2622.18" + attribute \src "ls180.v:2673.6-2673.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2623.6-2623.18" + attribute \src "ls180.v:2674.6-2674.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2597.6-2597.17" + attribute \src "ls180.v:2648.6-2648.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2624.6-2624.18" + attribute \src "ls180.v:2675.6-2675.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2625.6-2625.18" + attribute \src "ls180.v:2676.6-2676.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2626.6-2626.18" + attribute \src "ls180.v:2677.6-2677.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2627.6-2627.18" + attribute \src "ls180.v:2678.6-2678.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2628.6-2628.18" + attribute \src "ls180.v:2679.6-2679.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2629.6-2629.18" + attribute \src "ls180.v:2680.6-2680.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2630.6-2630.18" + attribute \src "ls180.v:2681.6-2681.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2631.6-2631.18" + attribute \src "ls180.v:2682.6-2682.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2632.6-2632.18" + attribute \src "ls180.v:2683.6-2683.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2633.6-2633.18" + attribute \src "ls180.v:2684.6-2684.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2598.6-2598.17" + attribute \src "ls180.v:2649.6-2649.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2634.6-2634.18" + attribute \src "ls180.v:2685.6-2685.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2635.6-2635.18" + attribute \src "ls180.v:2686.6-2686.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2636.6-2636.18" + attribute \src "ls180.v:2687.6-2687.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2637.6-2637.18" + attribute \src "ls180.v:2688.6-2688.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2638.6-2638.18" + attribute \src "ls180.v:2689.6-2689.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2639.6-2639.18" + attribute \src "ls180.v:2690.6-2690.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2640.6-2640.18" + attribute \src "ls180.v:2691.6-2691.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2641.6-2641.18" + attribute \src "ls180.v:2692.6-2692.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2642.6-2642.18" + attribute \src "ls180.v:2693.6-2693.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2643.6-2643.18" + attribute \src "ls180.v:2694.6-2694.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2599.6-2599.17" + attribute \src "ls180.v:2650.6-2650.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2644.6-2644.18" + attribute \src "ls180.v:2695.6-2695.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2645.6-2645.18" + attribute \src "ls180.v:2696.6-2696.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2646.6-2646.18" + attribute \src "ls180.v:2697.6-2697.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2647.6-2647.18" + attribute \src "ls180.v:2698.6-2698.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2648.6-2648.18" + attribute \src "ls180.v:2699.6-2699.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2649.6-2649.18" + attribute \src "ls180.v:2700.6-2700.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2684.6-2684.18" + attribute \src "ls180.v:2735.6-2735.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2685.6-2685.18" + attribute \src "ls180.v:2736.6-2736.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2686.6-2686.18" + attribute \src "ls180.v:2737.6-2737.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2687.6-2687.18" + attribute \src "ls180.v:2738.6-2738.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2600.6-2600.17" + attribute \src "ls180.v:2651.6-2651.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2688.6-2688.18" + attribute \src "ls180.v:2739.6-2739.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2689.6-2689.18" + attribute \src "ls180.v:2740.6-2740.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2690.6-2690.18" + attribute \src "ls180.v:2741.6-2741.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2691.6-2691.18" + attribute \src "ls180.v:2742.6-2742.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2692.6-2692.18" + attribute \src "ls180.v:2743.6-2743.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2693.6-2693.18" + attribute \src "ls180.v:2744.6-2744.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2694.6-2694.18" + attribute \src "ls180.v:2745.6-2745.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2695.6-2695.18" + attribute \src "ls180.v:2746.6-2746.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2696.6-2696.18" + attribute \src "ls180.v:2747.6-2747.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2601.6-2601.17" + attribute \src "ls180.v:2652.6-2652.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2602.6-2602.17" + attribute \src "ls180.v:2653.6-2653.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2603.6-2603.17" + attribute \src "ls180.v:2654.6-2654.17" wire \sdrio_clk_9 - attribute \src "ls180.v:24.13-24.27" - wire output 20 \spi_master_clk - attribute \src "ls180.v:26.13-26.28" - wire output 22 \spi_master_cs_n - attribute \src "ls180.v:27.13-27.28" - wire input 23 \spi_master_miso - attribute \src "ls180.v:25.13-25.28" - wire output 21 \spi_master_mosi - attribute \src "ls180.v:43.13-43.26" - wire output 39 \spisdcard_clk - attribute \src "ls180.v:45.13-45.27" - wire output 41 \spisdcard_cs_n - attribute \src "ls180.v:46.13-46.27" - wire input 42 \spisdcard_miso - attribute \src "ls180.v:44.13-44.27" - wire output 40 \spisdcard_mosi - attribute \src "ls180.v:5.13-5.20" - wire input 1 \sys_clk - attribute \src "ls180.v:217.6-217.15" + attribute \src "ls180.v:21.13-21.26" + wire output 17 \spimaster_clk + attribute \src "ls180.v:23.13-23.27" + wire output 19 \spimaster_cs_n + attribute \src "ls180.v:24.14-24.28" + wire output 20 \spimaster_miso + attribute \src "ls180.v:22.13-22.27" + wire output 18 \spimaster_mosi + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spisdcard_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spisdcard_cs_n + attribute \src "ls180.v:42.14-42.28" + wire output 38 \spisdcard_miso + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:247.6-247.15" wire \sys_clk_1 - attribute \src "ls180.v:6.13-6.20" - wire input 2 \sys_rst - attribute \src "ls180.v:218.6-218.15" + attribute \src "ls180.v:45.19-45.31" + wire width 3 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_48_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:248.6-248.15" wire \sys_rst_1 - attribute \src "ls180.v:20.13-20.20" - wire input 16 \uart_rx - attribute \src "ls180.v:19.14-19.21" - wire output 15 \uart_tx - attribute \src "ls180.v:9975.12-9975.15" + attribute \src "ls180.v:9.13-9.20" + wire input 5 \uart_rx + attribute \src "ls180.v:8.13-8.20" + wire output 4 \uart_tx + attribute \src "ls180.v:10054.12-10054.15" memory width 32 size 128 \mem - attribute \src "ls180.v:9995.12-9995.19" + attribute \src "ls180.v:10074.12-10074.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10009.12-10009.21" + attribute \src "ls180.v:10088.12-10088.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10023.12-10023.21" + attribute \src "ls180.v:10102.12-10102.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10037.12-10037.21" + attribute \src "ls180.v:10116.12-10116.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10051.11-10051.20" + attribute \src "ls180.v:10130.11-10130.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10068.11-10068.20" + attribute \src "ls180.v:10147.11-10147.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10085.11-10085.20" + attribute \src "ls180.v:10164.11-10164.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10099.11-10099.20" + attribute \src "ls180.v:10178.11-10178.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2768.68-2768.110" - cell $add $add$ls180.v:2768$22 + attribute \src "ls180.v:2816.68-2816.110" + cell $add $add$ls180.v:2816$22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230168,10 +235685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2768$22_Y + connect \Y $add$ls180.v:2816$22_Y end - attribute \src "ls180.v:2828.68-2828.110" - cell $add $add$ls180.v:2828$33 + attribute \src "ls180.v:2876.68-2876.110" + cell $add $add$ls180.v:2876$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230179,10 +235696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2828$33_Y + connect \Y $add$ls180.v:2876$33_Y end - attribute \src "ls180.v:2888.68-2888.110" - cell $add $add$ls180.v:2888$44 + attribute \src "ls180.v:2936.68-2936.110" + cell $add $add$ls180.v:2936$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230190,10 +235707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_counter connect \B 1'1 - connect \Y $add$ls180.v:2888$44_Y + connect \Y $add$ls180.v:2936$44_Y end - attribute \src "ls180.v:4021.54-4021.83" - cell $add $add$ls180.v:4021$537 + attribute \src "ls180.v:4069.54-4069.83" + cell $add $add$ls180.v:4069$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230201,10 +235718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4021$537_Y + connect \Y $add$ls180.v:4069$537_Y end - attribute \src "ls180.v:4121.36-4121.89" - cell $add $add$ls180.v:4121$583 + attribute \src "ls180.v:4169.36-4169.89" + cell $add $add$ls180.v:4169$583 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230212,10 +235729,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4121$583_Y + connect \Y $add$ls180.v:4169$583_Y end - attribute \src "ls180.v:4151.36-4151.89" - cell $add $add$ls180.v:4151$594 + attribute \src "ls180.v:4199.36-4199.89" + cell $add $add$ls180.v:4199$594 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230223,21 +235740,32 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4151$594_Y + connect \Y $add$ls180.v:4199$594_Y end - attribute \src "ls180.v:4206.53-4206.81" - cell $add $add$ls180.v:4206$607 + attribute \src "ls180.v:4254.54-4254.83" + cell $add $add$ls180.v:4254$607 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_spi_master_count + connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4206$607_Y + connect \Y $add$ls180.v:4254$607_Y end - attribute \src "ls180.v:4306.58-4306.86" - cell $add $add$ls180.v:4306$635 + attribute \src "ls180.v:4313.52-4313.79" + cell $add $add$ls180.v:4313$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4313$615_Y + end + attribute \src "ls180.v:4417.58-4417.86" + cell $add $add$ls180.v:4417$643 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230245,10 +235773,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4306$635_Y + connect \Y $add$ls180.v:4417$643_Y end - attribute \src "ls180.v:4363.58-4363.86" - cell $add $add$ls180.v:4363$638 + attribute \src "ls180.v:4474.58-4474.86" + cell $add $add$ls180.v:4474$646 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230256,10 +235784,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4363$638_Y + connect \Y $add$ls180.v:4474$646_Y end - attribute \src "ls180.v:4380.58-4380.86" - cell $add $add$ls180.v:4380$640 + attribute \src "ls180.v:4491.58-4491.86" + cell $add $add$ls180.v:4491$648 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230267,10 +235795,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4380$640_Y + connect \Y $add$ls180.v:4491$648_Y end - attribute \src "ls180.v:4473.59-4473.87" - cell $add $add$ls180.v:4473$657 + attribute \src "ls180.v:4584.59-4584.87" + cell $add $add$ls180.v:4584$665 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230278,10 +235806,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4473$657_Y + connect \Y $add$ls180.v:4584$665_Y end - attribute \src "ls180.v:4498.59-4498.87" - cell $add $add$ls180.v:4498$660 + attribute \src "ls180.v:4609.59-4609.87" + cell $add $add$ls180.v:4609$668 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230289,10 +235817,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4498$660_Y + connect \Y $add$ls180.v:4609$668_Y end - attribute \src "ls180.v:4620.53-4620.82" - cell $add $add$ls180.v:4620$677 + attribute \src "ls180.v:4731.53-4731.82" + cell $add $add$ls180.v:4731$685 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -230300,10 +235828,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4620$677_Y + connect \Y $add$ls180.v:4731$685_Y end - attribute \src "ls180.v:4731.65-4731.114" - cell $add $add$ls180.v:4731$691 + attribute \src "ls180.v:4842.65-4842.114" + cell $add $add$ls180.v:4842$699 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -230311,10 +235839,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:4731$691_Y + connect \Y $add$ls180.v:4842$699_Y end - attribute \src "ls180.v:4736.62-4736.91" - cell $add $add$ls180.v:4736$694 + attribute \src "ls180.v:4847.62-4847.91" + cell $add $add$ls180.v:4847$702 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -230322,10 +235850,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4736$694_Y + connect \Y $add$ls180.v:4847$702_Y end - attribute \src "ls180.v:4762.61-4762.90" - cell $add $add$ls180.v:4762$697 + attribute \src "ls180.v:4873.61-4873.90" + cell $add $add$ls180.v:4873$705 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -230333,10 +235861,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:4762$697_Y + connect \Y $add$ls180.v:4873$705_Y end - attribute \src "ls180.v:4966.80-4966.117" - cell $add $add$ls180.v:4966$882 + attribute \src "ls180.v:5077.80-5077.117" + cell $add $add$ls180.v:5077$890 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230344,10 +235872,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:4966$882_Y + connect \Y $add$ls180.v:5077$890_Y end - attribute \src "ls180.v:5160.54-5160.82" - cell $add $add$ls180.v:5160$957 + attribute \src "ls180.v:5271.54-5271.82" + cell $add $add$ls180.v:5271$965 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230355,10 +235883,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5160$957_Y + connect \Y $add$ls180.v:5271$965_Y end - attribute \src "ls180.v:5212.55-5212.84" - cell $add $add$ls180.v:5212$967 + attribute \src "ls180.v:5323.55-5323.84" + cell $add $add$ls180.v:5323$975 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230366,10 +235894,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5212$967_Y + connect \Y $add$ls180.v:5323$975_Y end - attribute \src "ls180.v:5238.57-5238.86" - cell $add $add$ls180.v:5238$975 + attribute \src "ls180.v:5349.57-5349.86" + cell $add $add$ls180.v:5349$983 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230377,10 +235905,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5238$975_Y + connect \Y $add$ls180.v:5349$983_Y end - attribute \src "ls180.v:5359.51-5359.134" - cell $add $add$ls180.v:5359$991 + attribute \src "ls180.v:5470.51-5470.134" + cell $add $add$ls180.v:5470$999 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230388,10 +235916,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5359$991_Y + connect \Y $add$ls180.v:5470$999_Y end - attribute \src "ls180.v:5362.77-5362.125" - cell $add $add$ls180.v:5362$993 + attribute \src "ls180.v:5473.77-5473.125" + cell $add $add$ls180.v:5473$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230399,10 +235927,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5362$993_Y + connect \Y $add$ls180.v:5473$1001_Y end - attribute \src "ls180.v:5455.50-5455.105" - cell $add $add$ls180.v:5455$1002 + attribute \src "ls180.v:5566.50-5566.105" + cell $add $add$ls180.v:5566$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230410,10 +235938,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5455$1002_Y + connect \Y $add$ls180.v:5566$1010_Y end - attribute \src "ls180.v:5457.77-5457.111" - cell $add $add$ls180.v:5457$1003 + attribute \src "ls180.v:5568.77-5568.111" + cell $add $add$ls180.v:5568$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230421,21 +235949,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5457$1003_Y - end - attribute \src "ls180.v:5569.49-5569.73" - cell $add $add$ls180.v:5569$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_count - connect \B 1'1 - connect \Y $add$ls180.v:5569$1022_Y + connect \Y $add$ls180.v:5568$1011_Y end - attribute \src "ls180.v:7437.36-7437.70" - cell $add $add$ls180.v:7437$2405 + attribute \src "ls180.v:7500.36-7500.70" + cell $add $add$ls180.v:7500$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230443,10 +235960,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7437$2405_Y + connect \Y $add$ls180.v:7500$2415_Y end - attribute \src "ls180.v:7522.37-7522.72" - cell $add $add$ls180.v:7522$2426 + attribute \src "ls180.v:7585.37-7585.72" + cell $add $add$ls180.v:7585$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230454,10 +235971,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7522$2426_Y + connect \Y $add$ls180.v:7585$2436_Y end - attribute \src "ls180.v:7539.60-7539.119" - cell $add $add$ls180.v:7539$2430 + attribute \src "ls180.v:7602.60-7602.119" + cell $add $add$ls180.v:7602$2440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230465,10 +235982,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7539$2430_Y + connect \Y $add$ls180.v:7602$2440_Y end - attribute \src "ls180.v:7542.60-7542.119" - cell $add $add$ls180.v:7542$2431 + attribute \src "ls180.v:7605.60-7605.119" + cell $add $add$ls180.v:7605$2441 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230476,10 +235993,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7542$2431_Y + connect \Y $add$ls180.v:7605$2441_Y end - attribute \src "ls180.v:7546.59-7546.116" - cell $add $add$ls180.v:7546$2436 + attribute \src "ls180.v:7609.59-7609.116" + cell $add $add$ls180.v:7609$2446 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230487,10 +236004,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7546$2436_Y + connect \Y $add$ls180.v:7609$2446_Y end - attribute \src "ls180.v:7585.60-7585.119" - cell $add $add$ls180.v:7585$2446 + attribute \src "ls180.v:7648.60-7648.119" + cell $add $add$ls180.v:7648$2456 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230498,10 +236015,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7585$2446_Y + connect \Y $add$ls180.v:7648$2456_Y end - attribute \src "ls180.v:7588.60-7588.119" - cell $add $add$ls180.v:7588$2447 + attribute \src "ls180.v:7651.60-7651.119" + cell $add $add$ls180.v:7651$2457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230509,10 +236026,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7588$2447_Y + connect \Y $add$ls180.v:7651$2457_Y end - attribute \src "ls180.v:7592.59-7592.116" - cell $add $add$ls180.v:7592$2452 + attribute \src "ls180.v:7655.59-7655.116" + cell $add $add$ls180.v:7655$2462 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230520,10 +236037,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7592$2452_Y + connect \Y $add$ls180.v:7655$2462_Y end - attribute \src "ls180.v:7631.60-7631.119" - cell $add $add$ls180.v:7631$2462 + attribute \src "ls180.v:7694.60-7694.119" + cell $add $add$ls180.v:7694$2472 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230531,10 +236048,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7631$2462_Y + connect \Y $add$ls180.v:7694$2472_Y end - attribute \src "ls180.v:7634.60-7634.119" - cell $add $add$ls180.v:7634$2463 + attribute \src "ls180.v:7697.60-7697.119" + cell $add $add$ls180.v:7697$2473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230542,10 +236059,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7634$2463_Y + connect \Y $add$ls180.v:7697$2473_Y end - attribute \src "ls180.v:7638.59-7638.116" - cell $add $add$ls180.v:7638$2468 + attribute \src "ls180.v:7701.59-7701.116" + cell $add $add$ls180.v:7701$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230553,10 +236070,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7638$2468_Y + connect \Y $add$ls180.v:7701$2478_Y end - attribute \src "ls180.v:7677.60-7677.119" - cell $add $add$ls180.v:7677$2478 + attribute \src "ls180.v:7740.60-7740.119" + cell $add $add$ls180.v:7740$2488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230564,10 +236081,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7677$2478_Y + connect \Y $add$ls180.v:7740$2488_Y end - attribute \src "ls180.v:7680.60-7680.119" - cell $add $add$ls180.v:7680$2479 + attribute \src "ls180.v:7743.60-7743.119" + cell $add $add$ls180.v:7743$2489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230575,10 +236092,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7680$2479_Y + connect \Y $add$ls180.v:7743$2489_Y end - attribute \src "ls180.v:7684.59-7684.116" - cell $add $add$ls180.v:7684$2484 + attribute \src "ls180.v:7747.59-7747.116" + cell $add $add$ls180.v:7747$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230586,54 +236103,54 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7684$2484_Y + connect \Y $add$ls180.v:7747$2494_Y end - attribute \src "ls180.v:7914.25-7914.48" - cell $add $add$ls180.v:7914$2538 + attribute \src "ls180.v:7977.34-7977.66" + cell $add $add$ls180.v:7977$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_tx_bitcount + connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7914$2538_Y + connect \Y $add$ls180.v:7977$2548_Y end - attribute \src "ls180.v:7930.55-7930.95" - cell $add $add$ls180.v:7930$2541 + attribute \src "ls180.v:7993.73-7993.131" + cell $add $add$ls180.v:7993$2551 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_phase_accumulator_tx - connect \B \main_storage - connect \Y $add$ls180.v:7930$2541_Y + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:7993$2551_Y end - attribute \src "ls180.v:7943.25-7943.48" - cell $add $add$ls180.v:7943$2545 + attribute \src "ls180.v:8006.34-8006.66" + cell $add $add$ls180.v:8006$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_rx_bitcount + connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:7943$2545_Y + connect \Y $add$ls180.v:8006$2555_Y end - attribute \src "ls180.v:7962.55-7962.95" - cell $add $add$ls180.v:7962$2548 + attribute \src "ls180.v:8025.73-8025.131" + cell $add $add$ls180.v:8025$2558 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_phase_accumulator_rx - connect \B \main_storage - connect \Y $add$ls180.v:7962$2548_Y + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8025$2558_Y end - attribute \src "ls180.v:7988.33-7988.65" - cell $add $add$ls180.v:7988$2556 + attribute \src "ls180.v:8051.33-8051.65" + cell $add $add$ls180.v:8051$2566 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230641,10 +236158,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:7988$2556_Y + connect \Y $add$ls180.v:8051$2566_Y end - attribute \src "ls180.v:7991.33-7991.65" - cell $add $add$ls180.v:7991$2557 + attribute \src "ls180.v:8054.33-8054.65" + cell $add $add$ls180.v:8054$2567 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230652,10 +236169,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:7991$2557_Y + connect \Y $add$ls180.v:8054$2567_Y end - attribute \src "ls180.v:7995.33-7995.64" - cell $add $add$ls180.v:7995$2562 + attribute \src "ls180.v:8058.33-8058.64" + cell $add $add$ls180.v:8058$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230663,10 +236180,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:7995$2562_Y + connect \Y $add$ls180.v:8058$2572_Y end - attribute \src "ls180.v:8010.33-8010.65" - cell $add $add$ls180.v:8010$2567 + attribute \src "ls180.v:8073.33-8073.65" + cell $add $add$ls180.v:8073$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230674,10 +236191,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8010$2567_Y + connect \Y $add$ls180.v:8073$2577_Y end - attribute \src "ls180.v:8013.33-8013.65" - cell $add $add$ls180.v:8013$2568 + attribute \src "ls180.v:8076.33-8076.65" + cell $add $add$ls180.v:8076$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230685,10 +236202,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8013$2568_Y + connect \Y $add$ls180.v:8076$2578_Y end - attribute \src "ls180.v:8017.33-8017.64" - cell $add $add$ls180.v:8017$2573 + attribute \src "ls180.v:8080.33-8080.64" + cell $add $add$ls180.v:8080$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230696,21 +236213,32 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8017$2573_Y + connect \Y $add$ls180.v:8080$2583_Y end - attribute \src "ls180.v:8038.35-8038.70" - cell $add $add$ls180.v:8038$2575 + attribute \src "ls180.v:8101.35-8101.70" + cell $add $add$ls180.v:8101$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider1 + connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8038$2575_Y + connect \Y $add$ls180.v:8101$2585_Y end - attribute \src "ls180.v:8074.25-8074.49" - cell $add $add$ls180.v:8074$2580 + attribute \src "ls180.v:8136.34-8136.68" + cell $add $add$ls180.v:8136$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8136$2590_Y + end + attribute \src "ls180.v:8172.25-8172.49" + cell $add $add$ls180.v:8172$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230718,10 +236246,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8074$2580_Y + connect \Y $add$ls180.v:8172$2595_Y end - attribute \src "ls180.v:8088.25-8088.49" - cell $add $add$ls180.v:8088$2584 + attribute \src "ls180.v:8186.25-8186.49" + cell $add $add$ls180.v:8186$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -230729,10 +236257,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8088$2584_Y + connect \Y $add$ls180.v:8186$2599_Y end - attribute \src "ls180.v:8102.31-8102.61" - cell $add $add$ls180.v:8102$2589 + attribute \src "ls180.v:8200.31-8200.61" + cell $add $add$ls180.v:8200$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -230740,10 +236268,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8102$2589_Y + connect \Y $add$ls180.v:8200$2604_Y end - attribute \src "ls180.v:8125.45-8125.88" - cell $add $add$ls180.v:8125$2593 + attribute \src "ls180.v:8223.45-8223.88" + cell $add $add$ls180.v:8223$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230751,10 +236279,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8125$2593_Y + connect \Y $add$ls180.v:8223$2608_Y end - attribute \src "ls180.v:8171.71-8171.114" - cell $add $add$ls180.v:8171$2599 + attribute \src "ls180.v:8269.71-8269.114" + cell $add $add$ls180.v:8269$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230762,10 +236290,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8171$2599_Y + connect \Y $add$ls180.v:8269$2614_Y end - attribute \src "ls180.v:8206.46-8206.90" - cell $add $add$ls180.v:8206$2605 + attribute \src "ls180.v:8304.46-8304.90" + cell $add $add$ls180.v:8304$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230773,10 +236301,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8206$2605_Y + connect \Y $add$ls180.v:8304$2620_Y end - attribute \src "ls180.v:8252.72-8252.116" - cell $add $add$ls180.v:8252$2611 + attribute \src "ls180.v:8350.72-8350.116" + cell $add $add$ls180.v:8350$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230784,10 +236312,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8252$2611_Y + connect \Y $add$ls180.v:8350$2626_Y end - attribute \src "ls180.v:8285.47-8285.92" - cell $add $add$ls180.v:8285$2617 + attribute \src "ls180.v:8383.47-8383.92" + cell $add $add$ls180.v:8383$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230795,10 +236323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8285$2617_Y + connect \Y $add$ls180.v:8383$2632_Y end - attribute \src "ls180.v:8313.73-8313.118" - cell $add $add$ls180.v:8313$2623 + attribute \src "ls180.v:8411.73-8411.118" + cell $add $add$ls180.v:8411$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230806,10 +236334,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8313$2623_Y + connect \Y $add$ls180.v:8411$2638_Y end - attribute \src "ls180.v:8425.39-8425.75" - cell $add $add$ls180.v:8425$2636 + attribute \src "ls180.v:8523.39-8523.75" + cell $add $add$ls180.v:8523$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -230817,10 +236345,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8425$2636_Y + connect \Y $add$ls180.v:8523$2651_Y end - attribute \src "ls180.v:8486.37-8486.73" - cell $add $add$ls180.v:8486$2640 + attribute \src "ls180.v:8584.37-8584.73" + cell $add $add$ls180.v:8584$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230828,10 +236356,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8486$2640_Y + connect \Y $add$ls180.v:8584$2655_Y end - attribute \src "ls180.v:8489.37-8489.73" - cell $add $add$ls180.v:8489$2641 + attribute \src "ls180.v:8587.37-8587.73" + cell $add $add$ls180.v:8587$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230839,10 +236367,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8489$2641_Y + connect \Y $add$ls180.v:8587$2656_Y end - attribute \src "ls180.v:8493.36-8493.70" - cell $add $add$ls180.v:8493$2646 + attribute \src "ls180.v:8591.36-8591.70" + cell $add $add$ls180.v:8591$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -230850,10 +236378,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8493$2646_Y + connect \Y $add$ls180.v:8591$2661_Y end - attribute \src "ls180.v:8508.41-8508.80" - cell $add $add$ls180.v:8508$2650 + attribute \src "ls180.v:8606.41-8606.80" + cell $add $add$ls180.v:8606$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230861,10 +236389,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8508$2650_Y + connect \Y $add$ls180.v:8606$2665_Y end - attribute \src "ls180.v:8542.67-8542.106" - cell $add $add$ls180.v:8542$2656 + attribute \src "ls180.v:8640.67-8640.106" + cell $add $add$ls180.v:8640$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230872,10 +236400,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8542$2656_Y + connect \Y $add$ls180.v:8640$2671_Y end - attribute \src "ls180.v:8568.39-8568.76" - cell $add $add$ls180.v:8568$2658 + attribute \src "ls180.v:8666.39-8666.76" + cell $add $add$ls180.v:8666$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -230883,10 +236411,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8568$2658_Y + connect \Y $add$ls180.v:8666$2673_Y end - attribute \src "ls180.v:8572.37-8572.73" - cell $add $add$ls180.v:8572$2662 + attribute \src "ls180.v:8670.37-8670.73" + cell $add $add$ls180.v:8670$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230894,10 +236422,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8572$2662_Y + connect \Y $add$ls180.v:8670$2677_Y end - attribute \src "ls180.v:8575.37-8575.73" - cell $add $add$ls180.v:8575$2663 + attribute \src "ls180.v:8673.37-8673.73" + cell $add $add$ls180.v:8673$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -230905,10 +236433,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8575$2663_Y + connect \Y $add$ls180.v:8673$2678_Y end - attribute \src "ls180.v:8579.36-8579.70" - cell $add $add$ls180.v:8579$2668 + attribute \src "ls180.v:8677.36-8677.70" + cell $add $add$ls180.v:8677$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -230916,21 +236444,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8579$2668_Y - end - attribute \src "ls180.v:8586.31-8586.62" - cell $add $add$ls180.v:8586$2670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8586$2670_Y + connect \Y $add$ls180.v:8677$2683_Y end - attribute \src "ls180.v:2762.9-2762.80" - cell $and $and$ls180.v:2762$17 + attribute \src "ls180.v:2810.9-2810.80" + cell $and $and$ls180.v:2810$17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230938,10 +236455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_stb connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2762$17_Y + connect \Y $and$ls180.v:2810$17_Y end - attribute \src "ls180.v:2780.9-2780.80" - cell $and $and$ls180.v:2780$24 + attribute \src "ls180.v:2828.9-2828.80" + cell $and $and$ls180.v:2828$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230949,10 +236466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_stb connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2780$24_Y + connect \Y $and$ls180.v:2828$24_Y end - attribute \src "ls180.v:2822.9-2822.80" - cell $and $and$ls180.v:2822$28 + attribute \src "ls180.v:2870.9-2870.80" + cell $and $and$ls180.v:2870$28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230960,10 +236477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_stb connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2822$28_Y + connect \Y $and$ls180.v:2870$28_Y end - attribute \src "ls180.v:2840.9-2840.80" - cell $and $and$ls180.v:2840$35 + attribute \src "ls180.v:2888.9-2888.80" + cell $and $and$ls180.v:2888$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230971,10 +236488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_stb connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2840$35_Y + connect \Y $and$ls180.v:2888$35_Y end - attribute \src "ls180.v:2882.9-2882.86" - cell $and $and$ls180.v:2882$39 + attribute \src "ls180.v:2930.9-2930.86" + cell $and $and$ls180.v:2930$39 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230982,10 +236499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_stb connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2882$39_Y + connect \Y $and$ls180.v:2930$39_Y end - attribute \src "ls180.v:2900.9-2900.86" - cell $and $and$ls180.v:2900$46 + attribute \src "ls180.v:2948.9-2948.86" + cell $and $and$ls180.v:2948$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -230993,10 +236510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_stb connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2900$46_Y + connect \Y $and$ls180.v:2948$46_Y end - attribute \src "ls180.v:2910.31-2910.90" - cell $and $and$ls180.v:2910$48 + attribute \src "ls180.v:2958.31-2958.90" + cell $and $and$ls180.v:2958$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231004,32 +236521,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2910$48_Y + connect \Y $and$ls180.v:2958$48_Y end - attribute \src "ls180.v:2910.30-2910.121" - cell $and $and$ls180.v:2910$49 + attribute \src "ls180.v:2958.30-2958.121" + cell $and $and$ls180.v:2958$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2910$48_Y + connect \A $and$ls180.v:2958$48_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2910$49_Y + connect \Y $and$ls180.v:2958$49_Y end - attribute \src "ls180.v:2910.29-2910.156" - cell $and $and$ls180.v:2910$50 + attribute \src "ls180.v:2958.29-2958.156" + cell $and $and$ls180.v:2958$50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2910$49_Y + connect \A $and$ls180.v:2958$49_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2910$50_Y + connect \Y $and$ls180.v:2958$50_Y end - attribute \src "ls180.v:2911.31-2911.90" - cell $and $and$ls180.v:2911$51 + attribute \src "ls180.v:2959.31-2959.90" + cell $and $and$ls180.v:2959$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231037,32 +236554,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2911$51_Y + connect \Y $and$ls180.v:2959$51_Y end - attribute \src "ls180.v:2911.30-2911.121" - cell $and $and$ls180.v:2911$52 + attribute \src "ls180.v:2959.30-2959.121" + cell $and $and$ls180.v:2959$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2911$51_Y + connect \A $and$ls180.v:2959$51_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2911$52_Y + connect \Y $and$ls180.v:2959$52_Y end - attribute \src "ls180.v:2911.29-2911.156" - cell $and $and$ls180.v:2911$53 + attribute \src "ls180.v:2959.29-2959.156" + cell $and $and$ls180.v:2959$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2911$52_Y + connect \A $and$ls180.v:2959$52_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2911$53_Y + connect \Y $and$ls180.v:2959$53_Y end - attribute \src "ls180.v:2912.31-2912.90" - cell $and $and$ls180.v:2912$54 + attribute \src "ls180.v:2960.31-2960.90" + cell $and $and$ls180.v:2960$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231070,32 +236587,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2912$54_Y + connect \Y $and$ls180.v:2960$54_Y end - attribute \src "ls180.v:2912.30-2912.121" - cell $and $and$ls180.v:2912$55 + attribute \src "ls180.v:2960.30-2960.121" + cell $and $and$ls180.v:2960$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2912$54_Y + connect \A $and$ls180.v:2960$54_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2912$55_Y + connect \Y $and$ls180.v:2960$55_Y end - attribute \src "ls180.v:2912.29-2912.156" - cell $and $and$ls180.v:2912$56 + attribute \src "ls180.v:2960.29-2960.156" + cell $and $and$ls180.v:2960$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2912$55_Y + connect \A $and$ls180.v:2960$55_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2912$56_Y + connect \Y $and$ls180.v:2960$56_Y end - attribute \src "ls180.v:2913.31-2913.90" - cell $and $and$ls180.v:2913$57 + attribute \src "ls180.v:2961.31-2961.90" + cell $and $and$ls180.v:2961$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231103,32 +236620,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2913$57_Y + connect \Y $and$ls180.v:2961$57_Y end - attribute \src "ls180.v:2913.30-2913.121" - cell $and $and$ls180.v:2913$58 + attribute \src "ls180.v:2961.30-2961.121" + cell $and $and$ls180.v:2961$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2913$57_Y + connect \A $and$ls180.v:2961$57_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2913$58_Y + connect \Y $and$ls180.v:2961$58_Y end - attribute \src "ls180.v:2913.29-2913.156" - cell $and $and$ls180.v:2913$59 + attribute \src "ls180.v:2961.29-2961.156" + cell $and $and$ls180.v:2961$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2913$58_Y + connect \A $and$ls180.v:2961$58_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2913$59_Y + connect \Y $and$ls180.v:2961$59_Y end - attribute \src "ls180.v:2922.7-2922.89" - cell $and $and$ls180.v:2922$62 + attribute \src "ls180.v:2970.7-2970.89" + cell $and $and$ls180.v:2970$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231136,10 +236653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:2922$62_Y + connect \Y $and$ls180.v:2970$62_Y end - attribute \src "ls180.v:2927.32-2927.111" - cell $and $and$ls180.v:2927$63 + attribute \src "ls180.v:2975.32-2975.111" + cell $and $and$ls180.v:2975$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231147,10 +236664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:2927$63_Y + connect \Y $and$ls180.v:2975$63_Y end - attribute \src "ls180.v:3041.40-3041.99" - cell $and $and$ls180.v:3041$70 + attribute \src "ls180.v:3089.40-3089.99" + cell $and $and$ls180.v:3089$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231158,10 +236675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3041$70_Y + connect \Y $and$ls180.v:3089$70_Y end - attribute \src "ls180.v:3042.40-3042.99" - cell $and $and$ls180.v:3042$71 + attribute \src "ls180.v:3090.40-3090.99" + cell $and $and$ls180.v:3090$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231169,21 +236686,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3042$71_Y + connect \Y $and$ls180.v:3090$71_Y end - attribute \src "ls180.v:3080.38-3080.103" - cell $and $and$ls180.v:3080$77 + attribute \src "ls180.v:3128.38-3128.103" + cell $and $and$ls180.v:3128$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3080$76_Y - connect \Y $and$ls180.v:3080$77_Y + connect \B $eq$ls180.v:3128$76_Y + connect \Y $and$ls180.v:3128$77_Y end - attribute \src "ls180.v:3134.50-3134.119" - cell $and $and$ls180.v:3134$85 + attribute \src "ls180.v:3182.50-3182.119" + cell $and $and$ls180.v:3182$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231191,21 +236708,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3134$85_Y + connect \Y $and$ls180.v:3182$85_Y end - attribute \src "ls180.v:3134.49-3134.167" - cell $and $and$ls180.v:3134$86 + attribute \src "ls180.v:3182.49-3182.167" + cell $and $and$ls180.v:3182$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$85_Y + connect \A $and$ls180.v:3182$85_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3134$86_Y + connect \Y $and$ls180.v:3182$86_Y end - attribute \src "ls180.v:3135.49-3135.118" - cell $and $and$ls180.v:3135$87 + attribute \src "ls180.v:3183.49-3183.118" + cell $and $and$ls180.v:3183$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231213,21 +236730,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3135$87_Y + connect \Y $and$ls180.v:3183$87_Y end - attribute \src "ls180.v:3135.48-3135.154" - cell $and $and$ls180.v:3135$88 + attribute \src "ls180.v:3183.48-3183.154" + cell $and $and$ls180.v:3183$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3135$87_Y + connect \A $and$ls180.v:3183$87_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3135$88_Y + connect \Y $and$ls180.v:3183$88_Y end - attribute \src "ls180.v:3136.50-3136.119" - cell $and $and$ls180.v:3136$89 + attribute \src "ls180.v:3184.50-3184.119" + cell $and $and$ls180.v:3184$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231235,21 +236752,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3136$89_Y + connect \Y $and$ls180.v:3184$89_Y end - attribute \src "ls180.v:3136.49-3136.155" - cell $and $and$ls180.v:3136$90 + attribute \src "ls180.v:3184.49-3184.155" + cell $and $and$ls180.v:3184$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3136$89_Y + connect \A $and$ls180.v:3184$89_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3136$90_Y + connect \Y $and$ls180.v:3184$90_Y end - attribute \src "ls180.v:3139.7-3139.114" - cell $and $and$ls180.v:3139$92 + attribute \src "ls180.v:3187.7-3187.114" + cell $and $and$ls180.v:3187$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231257,21 +236774,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3139$92_Y + connect \Y $and$ls180.v:3187$92_Y end - attribute \src "ls180.v:3168.66-3168.246" - cell $and $and$ls180.v:3168$98 + attribute \src "ls180.v:3216.66-3216.246" + cell $and $and$ls180.v:3216$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3168$97_Y - connect \Y $and$ls180.v:3168$98_Y + connect \B $or$ls180.v:3216$97_Y + connect \Y $and$ls180.v:3216$98_Y end - attribute \src "ls180.v:3169.64-3169.187" - cell $and $and$ls180.v:3169$99 + attribute \src "ls180.v:3217.64-3217.187" + cell $and $and$ls180.v:3217$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231279,10 +236796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3169$99_Y + connect \Y $and$ls180.v:3217$99_Y end - attribute \src "ls180.v:3193.9-3193.86" - cell $and $and$ls180.v:3193$105 + attribute \src "ls180.v:3241.9-3241.86" + cell $and $and$ls180.v:3241$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231290,10 +236807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3193$105_Y + connect \Y $and$ls180.v:3241$105_Y end - attribute \src "ls180.v:3205.9-3205.86" - cell $and $and$ls180.v:3205$106 + attribute \src "ls180.v:3253.9-3253.86" + cell $and $and$ls180.v:3253$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231301,10 +236818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3205$106_Y + connect \Y $and$ls180.v:3253$106_Y end - attribute \src "ls180.v:3255.13-3255.87" - cell $and $and$ls180.v:3255$108 + attribute \src "ls180.v:3303.13-3303.87" + cell $and $and$ls180.v:3303$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231312,10 +236829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3255$108_Y + connect \Y $and$ls180.v:3303$108_Y end - attribute \src "ls180.v:3291.50-3291.119" - cell $and $and$ls180.v:3291$115 + attribute \src "ls180.v:3339.50-3339.119" + cell $and $and$ls180.v:3339$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231323,21 +236840,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3291$115_Y + connect \Y $and$ls180.v:3339$115_Y end - attribute \src "ls180.v:3291.49-3291.167" - cell $and $and$ls180.v:3291$116 + attribute \src "ls180.v:3339.49-3339.167" + cell $and $and$ls180.v:3339$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3291$115_Y + connect \A $and$ls180.v:3339$115_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3291$116_Y + connect \Y $and$ls180.v:3339$116_Y end - attribute \src "ls180.v:3292.49-3292.118" - cell $and $and$ls180.v:3292$117 + attribute \src "ls180.v:3340.49-3340.118" + cell $and $and$ls180.v:3340$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231345,21 +236862,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3292$117_Y + connect \Y $and$ls180.v:3340$117_Y end - attribute \src "ls180.v:3292.48-3292.154" - cell $and $and$ls180.v:3292$118 + attribute \src "ls180.v:3340.48-3340.154" + cell $and $and$ls180.v:3340$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3292$117_Y + connect \A $and$ls180.v:3340$117_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3292$118_Y + connect \Y $and$ls180.v:3340$118_Y end - attribute \src "ls180.v:3293.50-3293.119" - cell $and $and$ls180.v:3293$119 + attribute \src "ls180.v:3341.50-3341.119" + cell $and $and$ls180.v:3341$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231367,21 +236884,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3293$119_Y + connect \Y $and$ls180.v:3341$119_Y end - attribute \src "ls180.v:3293.49-3293.155" - cell $and $and$ls180.v:3293$120 + attribute \src "ls180.v:3341.49-3341.155" + cell $and $and$ls180.v:3341$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3293$119_Y + connect \A $and$ls180.v:3341$119_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3293$120_Y + connect \Y $and$ls180.v:3341$120_Y end - attribute \src "ls180.v:3296.7-3296.114" - cell $and $and$ls180.v:3296$122 + attribute \src "ls180.v:3344.7-3344.114" + cell $and $and$ls180.v:3344$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231389,21 +236906,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3296$122_Y + connect \Y $and$ls180.v:3344$122_Y end - attribute \src "ls180.v:3325.66-3325.246" - cell $and $and$ls180.v:3325$128 + attribute \src "ls180.v:3373.66-3373.246" + cell $and $and$ls180.v:3373$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3325$127_Y - connect \Y $and$ls180.v:3325$128_Y + connect \B $or$ls180.v:3373$127_Y + connect \Y $and$ls180.v:3373$128_Y end - attribute \src "ls180.v:3326.64-3326.187" - cell $and $and$ls180.v:3326$129 + attribute \src "ls180.v:3374.64-3374.187" + cell $and $and$ls180.v:3374$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231411,10 +236928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3326$129_Y + connect \Y $and$ls180.v:3374$129_Y end - attribute \src "ls180.v:3350.9-3350.86" - cell $and $and$ls180.v:3350$135 + attribute \src "ls180.v:3398.9-3398.86" + cell $and $and$ls180.v:3398$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231422,10 +236939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3350$135_Y + connect \Y $and$ls180.v:3398$135_Y end - attribute \src "ls180.v:3362.9-3362.86" - cell $and $and$ls180.v:3362$136 + attribute \src "ls180.v:3410.9-3410.86" + cell $and $and$ls180.v:3410$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231433,10 +236950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3362$136_Y + connect \Y $and$ls180.v:3410$136_Y end - attribute \src "ls180.v:3412.13-3412.87" - cell $and $and$ls180.v:3412$138 + attribute \src "ls180.v:3460.13-3460.87" + cell $and $and$ls180.v:3460$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231444,10 +236961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3412$138_Y + connect \Y $and$ls180.v:3460$138_Y end - attribute \src "ls180.v:3448.50-3448.119" - cell $and $and$ls180.v:3448$145 + attribute \src "ls180.v:3496.50-3496.119" + cell $and $and$ls180.v:3496$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231455,21 +236972,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3448$145_Y + connect \Y $and$ls180.v:3496$145_Y end - attribute \src "ls180.v:3448.49-3448.167" - cell $and $and$ls180.v:3448$146 + attribute \src "ls180.v:3496.49-3496.167" + cell $and $and$ls180.v:3496$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3448$145_Y + connect \A $and$ls180.v:3496$145_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3448$146_Y + connect \Y $and$ls180.v:3496$146_Y end - attribute \src "ls180.v:3449.49-3449.118" - cell $and $and$ls180.v:3449$147 + attribute \src "ls180.v:3497.49-3497.118" + cell $and $and$ls180.v:3497$147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231477,21 +236994,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3449$147_Y + connect \Y $and$ls180.v:3497$147_Y end - attribute \src "ls180.v:3449.48-3449.154" - cell $and $and$ls180.v:3449$148 + attribute \src "ls180.v:3497.48-3497.154" + cell $and $and$ls180.v:3497$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3449$147_Y + connect \A $and$ls180.v:3497$147_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3449$148_Y + connect \Y $and$ls180.v:3497$148_Y end - attribute \src "ls180.v:3450.50-3450.119" - cell $and $and$ls180.v:3450$149 + attribute \src "ls180.v:3498.50-3498.119" + cell $and $and$ls180.v:3498$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231499,21 +237016,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3450$149_Y + connect \Y $and$ls180.v:3498$149_Y end - attribute \src "ls180.v:3450.49-3450.155" - cell $and $and$ls180.v:3450$150 + attribute \src "ls180.v:3498.49-3498.155" + cell $and $and$ls180.v:3498$150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3450$149_Y + connect \A $and$ls180.v:3498$149_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3450$150_Y + connect \Y $and$ls180.v:3498$150_Y end - attribute \src "ls180.v:3453.7-3453.114" - cell $and $and$ls180.v:3453$152 + attribute \src "ls180.v:3501.7-3501.114" + cell $and $and$ls180.v:3501$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231521,21 +237038,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3453$152_Y + connect \Y $and$ls180.v:3501$152_Y end - attribute \src "ls180.v:3482.66-3482.246" - cell $and $and$ls180.v:3482$158 + attribute \src "ls180.v:3530.66-3530.246" + cell $and $and$ls180.v:3530$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3482$157_Y - connect \Y $and$ls180.v:3482$158_Y + connect \B $or$ls180.v:3530$157_Y + connect \Y $and$ls180.v:3530$158_Y end - attribute \src "ls180.v:3483.64-3483.187" - cell $and $and$ls180.v:3483$159 + attribute \src "ls180.v:3531.64-3531.187" + cell $and $and$ls180.v:3531$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231543,10 +237060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3483$159_Y + connect \Y $and$ls180.v:3531$159_Y end - attribute \src "ls180.v:3507.9-3507.86" - cell $and $and$ls180.v:3507$165 + attribute \src "ls180.v:3555.9-3555.86" + cell $and $and$ls180.v:3555$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231554,10 +237071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3507$165_Y + connect \Y $and$ls180.v:3555$165_Y end - attribute \src "ls180.v:3519.9-3519.86" - cell $and $and$ls180.v:3519$166 + attribute \src "ls180.v:3567.9-3567.86" + cell $and $and$ls180.v:3567$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231565,10 +237082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3519$166_Y + connect \Y $and$ls180.v:3567$166_Y end - attribute \src "ls180.v:3569.13-3569.87" - cell $and $and$ls180.v:3569$168 + attribute \src "ls180.v:3617.13-3617.87" + cell $and $and$ls180.v:3617$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231576,10 +237093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3569$168_Y + connect \Y $and$ls180.v:3617$168_Y end - attribute \src "ls180.v:3605.50-3605.119" - cell $and $and$ls180.v:3605$175 + attribute \src "ls180.v:3653.50-3653.119" + cell $and $and$ls180.v:3653$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231587,21 +237104,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3605$175_Y + connect \Y $and$ls180.v:3653$175_Y end - attribute \src "ls180.v:3605.49-3605.167" - cell $and $and$ls180.v:3605$176 + attribute \src "ls180.v:3653.49-3653.167" + cell $and $and$ls180.v:3653$176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3605$175_Y + connect \A $and$ls180.v:3653$175_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3605$176_Y + connect \Y $and$ls180.v:3653$176_Y end - attribute \src "ls180.v:3606.49-3606.118" - cell $and $and$ls180.v:3606$177 + attribute \src "ls180.v:3654.49-3654.118" + cell $and $and$ls180.v:3654$177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231609,21 +237126,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3606$177_Y + connect \Y $and$ls180.v:3654$177_Y end - attribute \src "ls180.v:3606.48-3606.154" - cell $and $and$ls180.v:3606$178 + attribute \src "ls180.v:3654.48-3654.154" + cell $and $and$ls180.v:3654$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3606$177_Y + connect \A $and$ls180.v:3654$177_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3606$178_Y + connect \Y $and$ls180.v:3654$178_Y end - attribute \src "ls180.v:3607.50-3607.119" - cell $and $and$ls180.v:3607$179 + attribute \src "ls180.v:3655.50-3655.119" + cell $and $and$ls180.v:3655$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231631,21 +237148,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3607$179_Y + connect \Y $and$ls180.v:3655$179_Y end - attribute \src "ls180.v:3607.49-3607.155" - cell $and $and$ls180.v:3607$180 + attribute \src "ls180.v:3655.49-3655.155" + cell $and $and$ls180.v:3655$180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3607$179_Y + connect \A $and$ls180.v:3655$179_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3607$180_Y + connect \Y $and$ls180.v:3655$180_Y end - attribute \src "ls180.v:3610.7-3610.114" - cell $and $and$ls180.v:3610$182 + attribute \src "ls180.v:3658.7-3658.114" + cell $and $and$ls180.v:3658$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231653,21 +237170,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3610$182_Y + connect \Y $and$ls180.v:3658$182_Y end - attribute \src "ls180.v:3639.66-3639.246" - cell $and $and$ls180.v:3639$188 + attribute \src "ls180.v:3687.66-3687.246" + cell $and $and$ls180.v:3687$188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3639$187_Y - connect \Y $and$ls180.v:3639$188_Y + connect \B $or$ls180.v:3687$187_Y + connect \Y $and$ls180.v:3687$188_Y end - attribute \src "ls180.v:3640.64-3640.187" - cell $and $and$ls180.v:3640$189 + attribute \src "ls180.v:3688.64-3688.187" + cell $and $and$ls180.v:3688$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231675,10 +237192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3640$189_Y + connect \Y $and$ls180.v:3688$189_Y end - attribute \src "ls180.v:3664.9-3664.86" - cell $and $and$ls180.v:3664$195 + attribute \src "ls180.v:3712.9-3712.86" + cell $and $and$ls180.v:3712$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231686,10 +237203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3664$195_Y + connect \Y $and$ls180.v:3712$195_Y end - attribute \src "ls180.v:3676.9-3676.86" - cell $and $and$ls180.v:3676$196 + attribute \src "ls180.v:3724.9-3724.86" + cell $and $and$ls180.v:3724$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231697,10 +237214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3676$196_Y + connect \Y $and$ls180.v:3724$196_Y end - attribute \src "ls180.v:3726.13-3726.87" - cell $and $and$ls180.v:3726$198 + attribute \src "ls180.v:3774.13-3774.87" + cell $and $and$ls180.v:3774$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231708,10 +237225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3726$198_Y + connect \Y $and$ls180.v:3774$198_Y end - attribute \src "ls180.v:3741.37-3741.102" - cell $and $and$ls180.v:3741$199 + attribute \src "ls180.v:3789.37-3789.102" + cell $and $and$ls180.v:3789$199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231719,43 +237236,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3741$199_Y + connect \Y $and$ls180.v:3789$199_Y end - attribute \src "ls180.v:3741.108-3741.188" - cell $and $and$ls180.v:3741$201 + attribute \src "ls180.v:3789.108-3789.188" + cell $and $and$ls180.v:3789$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3741$200_Y - connect \Y $and$ls180.v:3741$201_Y + connect \B $not$ls180.v:3789$200_Y + connect \Y $and$ls180.v:3789$201_Y end - attribute \src "ls180.v:3741.107-3741.231" - cell $and $and$ls180.v:3741$203 + attribute \src "ls180.v:3789.107-3789.231" + cell $and $and$ls180.v:3789$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3741$201_Y - connect \B $not$ls180.v:3741$202_Y - connect \Y $and$ls180.v:3741$203_Y + connect \A $and$ls180.v:3789$201_Y + connect \B $not$ls180.v:3789$202_Y + connect \Y $and$ls180.v:3789$203_Y end - attribute \src "ls180.v:3741.36-3741.232" - cell $and $and$ls180.v:3741$204 + attribute \src "ls180.v:3789.36-3789.232" + cell $and $and$ls180.v:3789$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3741$199_Y - connect \B $and$ls180.v:3741$203_Y - connect \Y $and$ls180.v:3741$204_Y + connect \A $and$ls180.v:3789$199_Y + connect \B $and$ls180.v:3789$203_Y + connect \Y $and$ls180.v:3789$204_Y end - attribute \src "ls180.v:3742.37-3742.102" - cell $and $and$ls180.v:3742$205 + attribute \src "ls180.v:3790.37-3790.102" + cell $and $and$ls180.v:3790$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231763,43 +237280,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3742$205_Y + connect \Y $and$ls180.v:3790$205_Y end - attribute \src "ls180.v:3742.108-3742.188" - cell $and $and$ls180.v:3742$207 + attribute \src "ls180.v:3790.108-3790.188" + cell $and $and$ls180.v:3790$207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3742$206_Y - connect \Y $and$ls180.v:3742$207_Y + connect \B $not$ls180.v:3790$206_Y + connect \Y $and$ls180.v:3790$207_Y end - attribute \src "ls180.v:3742.107-3742.231" - cell $and $and$ls180.v:3742$209 + attribute \src "ls180.v:3790.107-3790.231" + cell $and $and$ls180.v:3790$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3742$207_Y - connect \B $not$ls180.v:3742$208_Y - connect \Y $and$ls180.v:3742$209_Y + connect \A $and$ls180.v:3790$207_Y + connect \B $not$ls180.v:3790$208_Y + connect \Y $and$ls180.v:3790$209_Y end - attribute \src "ls180.v:3742.36-3742.232" - cell $and $and$ls180.v:3742$210 + attribute \src "ls180.v:3790.36-3790.232" + cell $and $and$ls180.v:3790$210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3742$205_Y - connect \B $and$ls180.v:3742$209_Y - connect \Y $and$ls180.v:3742$210_Y + connect \A $and$ls180.v:3790$205_Y + connect \B $and$ls180.v:3790$209_Y + connect \Y $and$ls180.v:3790$210_Y end - attribute \src "ls180.v:3743.34-3743.85" - cell $and $and$ls180.v:3743$211 + attribute \src "ls180.v:3791.34-3791.85" + cell $and $and$ls180.v:3791$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231807,10 +237324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3743$211_Y + connect \Y $and$ls180.v:3791$211_Y end - attribute \src "ls180.v:3744.37-3744.102" - cell $and $and$ls180.v:3744$212 + attribute \src "ls180.v:3792.37-3792.102" + cell $and $and$ls180.v:3792$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231818,21 +237335,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3744$212_Y + connect \Y $and$ls180.v:3792$212_Y end - attribute \src "ls180.v:3744.36-3744.194" - cell $and $and$ls180.v:3744$214 + attribute \src "ls180.v:3792.36-3792.194" + cell $and $and$ls180.v:3792$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3744$212_Y - connect \B $or$ls180.v:3744$213_Y - connect \Y $and$ls180.v:3744$214_Y + connect \A $and$ls180.v:3792$212_Y + connect \B $or$ls180.v:3792$213_Y + connect \Y $and$ls180.v:3792$214_Y end - attribute \src "ls180.v:3746.37-3746.102" - cell $and $and$ls180.v:3746$215 + attribute \src "ls180.v:3794.37-3794.102" + cell $and $and$ls180.v:3794$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231840,21 +237357,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3746$215_Y + connect \Y $and$ls180.v:3794$215_Y end - attribute \src "ls180.v:3746.36-3746.148" - cell $and $and$ls180.v:3746$216 + attribute \src "ls180.v:3794.36-3794.148" + cell $and $and$ls180.v:3794$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3746$215_Y + connect \A $and$ls180.v:3794$215_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3746$216_Y + connect \Y $and$ls180.v:3794$216_Y end - attribute \src "ls180.v:3747.40-3747.119" - cell $and $and$ls180.v:3747$217 + attribute \src "ls180.v:3795.40-3795.119" + cell $and $and$ls180.v:3795$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231862,10 +237379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3747$217_Y + connect \Y $and$ls180.v:3795$217_Y end - attribute \src "ls180.v:3747.124-3747.203" - cell $and $and$ls180.v:3747$218 + attribute \src "ls180.v:3795.124-3795.203" + cell $and $and$ls180.v:3795$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231873,10 +237390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3747$218_Y + connect \Y $and$ls180.v:3795$218_Y end - attribute \src "ls180.v:3747.209-3747.288" - cell $and $and$ls180.v:3747$220 + attribute \src "ls180.v:3795.209-3795.288" + cell $and $and$ls180.v:3795$220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231884,10 +237401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3747$220_Y + connect \Y $and$ls180.v:3795$220_Y end - attribute \src "ls180.v:3747.294-3747.373" - cell $and $and$ls180.v:3747$222 + attribute \src "ls180.v:3795.294-3795.373" + cell $and $and$ls180.v:3795$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231895,10 +237412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3747$222_Y + connect \Y $and$ls180.v:3795$222_Y end - attribute \src "ls180.v:3748.41-3748.121" - cell $and $and$ls180.v:3748$224 + attribute \src "ls180.v:3796.41-3796.121" + cell $and $and$ls180.v:3796$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231906,10 +237423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3748$224_Y + connect \Y $and$ls180.v:3796$224_Y end - attribute \src "ls180.v:3748.126-3748.206" - cell $and $and$ls180.v:3748$225 + attribute \src "ls180.v:3796.126-3796.206" + cell $and $and$ls180.v:3796$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231917,10 +237434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3748$225_Y + connect \Y $and$ls180.v:3796$225_Y end - attribute \src "ls180.v:3748.212-3748.292" - cell $and $and$ls180.v:3748$227 + attribute \src "ls180.v:3796.212-3796.292" + cell $and $and$ls180.v:3796$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231928,10 +237445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3748$227_Y + connect \Y $and$ls180.v:3796$227_Y end - attribute \src "ls180.v:3748.298-3748.378" - cell $and $and$ls180.v:3748$229 + attribute \src "ls180.v:3796.298-3796.378" + cell $and $and$ls180.v:3796$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231939,10 +237456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3748$229_Y + connect \Y $and$ls180.v:3796$229_Y end - attribute \src "ls180.v:3755.38-3755.111" - cell $and $and$ls180.v:3755$233 + attribute \src "ls180.v:3803.38-3803.111" + cell $and $and$ls180.v:3803$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231950,32 +237467,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3755$233_Y + connect \Y $and$ls180.v:3803$233_Y end - attribute \src "ls180.v:3755.37-3755.150" - cell $and $and$ls180.v:3755$234 + attribute \src "ls180.v:3803.37-3803.150" + cell $and $and$ls180.v:3803$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3755$233_Y + connect \A $and$ls180.v:3803$233_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3755$234_Y + connect \Y $and$ls180.v:3803$234_Y end - attribute \src "ls180.v:3755.36-3755.189" - cell $and $and$ls180.v:3755$235 + attribute \src "ls180.v:3803.36-3803.189" + cell $and $and$ls180.v:3803$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3755$234_Y + connect \A $and$ls180.v:3803$234_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3755$235_Y + connect \Y $and$ls180.v:3803$235_Y end - attribute \src "ls180.v:3761.77-3761.153" - cell $and $and$ls180.v:3761$238 + attribute \src "ls180.v:3809.77-3809.153" + cell $and $and$ls180.v:3809$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231983,65 +237500,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3761$238_Y + connect \Y $and$ls180.v:3809$238_Y end - attribute \src "ls180.v:3761.162-3761.246" - cell $and $and$ls180.v:3761$240 + attribute \src "ls180.v:3809.162-3809.246" + cell $and $and$ls180.v:3809$240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3761$239_Y - connect \Y $and$ls180.v:3761$240_Y + connect \B $not$ls180.v:3809$239_Y + connect \Y $and$ls180.v:3809$240_Y end - attribute \src "ls180.v:3761.161-3761.291" - cell $and $and$ls180.v:3761$242 + attribute \src "ls180.v:3809.161-3809.291" + cell $and $and$ls180.v:3809$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3761$240_Y - connect \B $not$ls180.v:3761$241_Y - connect \Y $and$ls180.v:3761$242_Y + connect \A $and$ls180.v:3809$240_Y + connect \B $not$ls180.v:3809$241_Y + connect \Y $and$ls180.v:3809$242_Y end - attribute \src "ls180.v:3761.76-3761.333" - cell $and $and$ls180.v:3761$245 + attribute \src "ls180.v:3809.76-3809.333" + cell $and $and$ls180.v:3809$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3761$238_Y - connect \B $or$ls180.v:3761$244_Y - connect \Y $and$ls180.v:3761$245_Y + connect \A $and$ls180.v:3809$238_Y + connect \B $or$ls180.v:3809$244_Y + connect \Y $and$ls180.v:3809$245_Y end - attribute \src "ls180.v:3761.338-3761.505" - cell $and $and$ls180.v:3761$248 + attribute \src "ls180.v:3809.338-3809.505" + cell $and $and$ls180.v:3809$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3761$246_Y - connect \B $eq$ls180.v:3761$247_Y - connect \Y $and$ls180.v:3761$248_Y + connect \A $eq$ls180.v:3809$246_Y + connect \B $eq$ls180.v:3809$247_Y + connect \Y $and$ls180.v:3809$248_Y end - attribute \src "ls180.v:3761.38-3761.507" - cell $and $and$ls180.v:3761$250 + attribute \src "ls180.v:3809.38-3809.507" + cell $and $and$ls180.v:3809$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3761$249_Y - connect \Y $and$ls180.v:3761$250_Y + connect \B $or$ls180.v:3809$249_Y + connect \Y $and$ls180.v:3809$250_Y end - attribute \src "ls180.v:3762.77-3762.153" - cell $and $and$ls180.v:3762$251 + attribute \src "ls180.v:3810.77-3810.153" + cell $and $and$ls180.v:3810$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232049,65 +237566,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3762$251_Y + connect \Y $and$ls180.v:3810$251_Y end - attribute \src "ls180.v:3762.162-3762.246" - cell $and $and$ls180.v:3762$253 + attribute \src "ls180.v:3810.162-3810.246" + cell $and $and$ls180.v:3810$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3762$252_Y - connect \Y $and$ls180.v:3762$253_Y + connect \B $not$ls180.v:3810$252_Y + connect \Y $and$ls180.v:3810$253_Y end - attribute \src "ls180.v:3762.161-3762.291" - cell $and $and$ls180.v:3762$255 + attribute \src "ls180.v:3810.161-3810.291" + cell $and $and$ls180.v:3810$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3762$253_Y - connect \B $not$ls180.v:3762$254_Y - connect \Y $and$ls180.v:3762$255_Y + connect \A $and$ls180.v:3810$253_Y + connect \B $not$ls180.v:3810$254_Y + connect \Y $and$ls180.v:3810$255_Y end - attribute \src "ls180.v:3762.76-3762.333" - cell $and $and$ls180.v:3762$258 + attribute \src "ls180.v:3810.76-3810.333" + cell $and $and$ls180.v:3810$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3762$251_Y - connect \B $or$ls180.v:3762$257_Y - connect \Y $and$ls180.v:3762$258_Y + connect \A $and$ls180.v:3810$251_Y + connect \B $or$ls180.v:3810$257_Y + connect \Y $and$ls180.v:3810$258_Y end - attribute \src "ls180.v:3762.338-3762.505" - cell $and $and$ls180.v:3762$261 + attribute \src "ls180.v:3810.338-3810.505" + cell $and $and$ls180.v:3810$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3762$259_Y - connect \B $eq$ls180.v:3762$260_Y - connect \Y $and$ls180.v:3762$261_Y + connect \A $eq$ls180.v:3810$259_Y + connect \B $eq$ls180.v:3810$260_Y + connect \Y $and$ls180.v:3810$261_Y end - attribute \src "ls180.v:3762.38-3762.507" - cell $and $and$ls180.v:3762$263 + attribute \src "ls180.v:3810.38-3810.507" + cell $and $and$ls180.v:3810$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3762$262_Y - connect \Y $and$ls180.v:3762$263_Y + connect \B $or$ls180.v:3810$262_Y + connect \Y $and$ls180.v:3810$263_Y end - attribute \src "ls180.v:3763.77-3763.153" - cell $and $and$ls180.v:3763$264 + attribute \src "ls180.v:3811.77-3811.153" + cell $and $and$ls180.v:3811$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232115,65 +237632,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3763$264_Y + connect \Y $and$ls180.v:3811$264_Y end - attribute \src "ls180.v:3763.162-3763.246" - cell $and $and$ls180.v:3763$266 + attribute \src "ls180.v:3811.162-3811.246" + cell $and $and$ls180.v:3811$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3763$265_Y - connect \Y $and$ls180.v:3763$266_Y + connect \B $not$ls180.v:3811$265_Y + connect \Y $and$ls180.v:3811$266_Y end - attribute \src "ls180.v:3763.161-3763.291" - cell $and $and$ls180.v:3763$268 + attribute \src "ls180.v:3811.161-3811.291" + cell $and $and$ls180.v:3811$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3763$266_Y - connect \B $not$ls180.v:3763$267_Y - connect \Y $and$ls180.v:3763$268_Y + connect \A $and$ls180.v:3811$266_Y + connect \B $not$ls180.v:3811$267_Y + connect \Y $and$ls180.v:3811$268_Y end - attribute \src "ls180.v:3763.76-3763.333" - cell $and $and$ls180.v:3763$271 + attribute \src "ls180.v:3811.76-3811.333" + cell $and $and$ls180.v:3811$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3763$264_Y - connect \B $or$ls180.v:3763$270_Y - connect \Y $and$ls180.v:3763$271_Y + connect \A $and$ls180.v:3811$264_Y + connect \B $or$ls180.v:3811$270_Y + connect \Y $and$ls180.v:3811$271_Y end - attribute \src "ls180.v:3763.338-3763.505" - cell $and $and$ls180.v:3763$274 + attribute \src "ls180.v:3811.338-3811.505" + cell $and $and$ls180.v:3811$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3763$272_Y - connect \B $eq$ls180.v:3763$273_Y - connect \Y $and$ls180.v:3763$274_Y + connect \A $eq$ls180.v:3811$272_Y + connect \B $eq$ls180.v:3811$273_Y + connect \Y $and$ls180.v:3811$274_Y end - attribute \src "ls180.v:3763.38-3763.507" - cell $and $and$ls180.v:3763$276 + attribute \src "ls180.v:3811.38-3811.507" + cell $and $and$ls180.v:3811$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3763$275_Y - connect \Y $and$ls180.v:3763$276_Y + connect \B $or$ls180.v:3811$275_Y + connect \Y $and$ls180.v:3811$276_Y end - attribute \src "ls180.v:3764.77-3764.153" - cell $and $and$ls180.v:3764$277 + attribute \src "ls180.v:3812.77-3812.153" + cell $and $and$ls180.v:3812$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232181,65 +237698,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3764$277_Y + connect \Y $and$ls180.v:3812$277_Y end - attribute \src "ls180.v:3764.162-3764.246" - cell $and $and$ls180.v:3764$279 + attribute \src "ls180.v:3812.162-3812.246" + cell $and $and$ls180.v:3812$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3764$278_Y - connect \Y $and$ls180.v:3764$279_Y + connect \B $not$ls180.v:3812$278_Y + connect \Y $and$ls180.v:3812$279_Y end - attribute \src "ls180.v:3764.161-3764.291" - cell $and $and$ls180.v:3764$281 + attribute \src "ls180.v:3812.161-3812.291" + cell $and $and$ls180.v:3812$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3764$279_Y - connect \B $not$ls180.v:3764$280_Y - connect \Y $and$ls180.v:3764$281_Y + connect \A $and$ls180.v:3812$279_Y + connect \B $not$ls180.v:3812$280_Y + connect \Y $and$ls180.v:3812$281_Y end - attribute \src "ls180.v:3764.76-3764.333" - cell $and $and$ls180.v:3764$284 + attribute \src "ls180.v:3812.76-3812.333" + cell $and $and$ls180.v:3812$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3764$277_Y - connect \B $or$ls180.v:3764$283_Y - connect \Y $and$ls180.v:3764$284_Y + connect \A $and$ls180.v:3812$277_Y + connect \B $or$ls180.v:3812$283_Y + connect \Y $and$ls180.v:3812$284_Y end - attribute \src "ls180.v:3764.338-3764.505" - cell $and $and$ls180.v:3764$287 + attribute \src "ls180.v:3812.338-3812.505" + cell $and $and$ls180.v:3812$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3764$285_Y - connect \B $eq$ls180.v:3764$286_Y - connect \Y $and$ls180.v:3764$287_Y + connect \A $eq$ls180.v:3812$285_Y + connect \B $eq$ls180.v:3812$286_Y + connect \Y $and$ls180.v:3812$287_Y end - attribute \src "ls180.v:3764.38-3764.507" - cell $and $and$ls180.v:3764$289 + attribute \src "ls180.v:3812.38-3812.507" + cell $and $and$ls180.v:3812$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3764$288_Y - connect \Y $and$ls180.v:3764$289_Y + connect \B $or$ls180.v:3812$288_Y + connect \Y $and$ls180.v:3812$289_Y end - attribute \src "ls180.v:3794.77-3794.153" - cell $and $and$ls180.v:3794$296 + attribute \src "ls180.v:3842.77-3842.153" + cell $and $and$ls180.v:3842$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232247,65 +237764,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3794$296_Y + connect \Y $and$ls180.v:3842$296_Y end - attribute \src "ls180.v:3794.162-3794.246" - cell $and $and$ls180.v:3794$298 + attribute \src "ls180.v:3842.162-3842.246" + cell $and $and$ls180.v:3842$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3794$297_Y - connect \Y $and$ls180.v:3794$298_Y + connect \B $not$ls180.v:3842$297_Y + connect \Y $and$ls180.v:3842$298_Y end - attribute \src "ls180.v:3794.161-3794.291" - cell $and $and$ls180.v:3794$300 + attribute \src "ls180.v:3842.161-3842.291" + cell $and $and$ls180.v:3842$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$298_Y - connect \B $not$ls180.v:3794$299_Y - connect \Y $and$ls180.v:3794$300_Y + connect \A $and$ls180.v:3842$298_Y + connect \B $not$ls180.v:3842$299_Y + connect \Y $and$ls180.v:3842$300_Y end - attribute \src "ls180.v:3794.76-3794.333" - cell $and $and$ls180.v:3794$303 + attribute \src "ls180.v:3842.76-3842.333" + cell $and $and$ls180.v:3842$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$296_Y - connect \B $or$ls180.v:3794$302_Y - connect \Y $and$ls180.v:3794$303_Y + connect \A $and$ls180.v:3842$296_Y + connect \B $or$ls180.v:3842$302_Y + connect \Y $and$ls180.v:3842$303_Y end - attribute \src "ls180.v:3794.338-3794.505" - cell $and $and$ls180.v:3794$306 + attribute \src "ls180.v:3842.338-3842.505" + cell $and $and$ls180.v:3842$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3794$304_Y - connect \B $eq$ls180.v:3794$305_Y - connect \Y $and$ls180.v:3794$306_Y + connect \A $eq$ls180.v:3842$304_Y + connect \B $eq$ls180.v:3842$305_Y + connect \Y $and$ls180.v:3842$306_Y end - attribute \src "ls180.v:3794.38-3794.507" - cell $and $and$ls180.v:3794$308 + attribute \src "ls180.v:3842.38-3842.507" + cell $and $and$ls180.v:3842$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3794$307_Y - connect \Y $and$ls180.v:3794$308_Y + connect \B $or$ls180.v:3842$307_Y + connect \Y $and$ls180.v:3842$308_Y end - attribute \src "ls180.v:3795.77-3795.153" - cell $and $and$ls180.v:3795$309 + attribute \src "ls180.v:3843.77-3843.153" + cell $and $and$ls180.v:3843$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232313,65 +237830,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3795$309_Y + connect \Y $and$ls180.v:3843$309_Y end - attribute \src "ls180.v:3795.162-3795.246" - cell $and $and$ls180.v:3795$311 + attribute \src "ls180.v:3843.162-3843.246" + cell $and $and$ls180.v:3843$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3795$310_Y - connect \Y $and$ls180.v:3795$311_Y + connect \B $not$ls180.v:3843$310_Y + connect \Y $and$ls180.v:3843$311_Y end - attribute \src "ls180.v:3795.161-3795.291" - cell $and $and$ls180.v:3795$313 + attribute \src "ls180.v:3843.161-3843.291" + cell $and $and$ls180.v:3843$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$311_Y - connect \B $not$ls180.v:3795$312_Y - connect \Y $and$ls180.v:3795$313_Y + connect \A $and$ls180.v:3843$311_Y + connect \B $not$ls180.v:3843$312_Y + connect \Y $and$ls180.v:3843$313_Y end - attribute \src "ls180.v:3795.76-3795.333" - cell $and $and$ls180.v:3795$316 + attribute \src "ls180.v:3843.76-3843.333" + cell $and $and$ls180.v:3843$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$309_Y - connect \B $or$ls180.v:3795$315_Y - connect \Y $and$ls180.v:3795$316_Y + connect \A $and$ls180.v:3843$309_Y + connect \B $or$ls180.v:3843$315_Y + connect \Y $and$ls180.v:3843$316_Y end - attribute \src "ls180.v:3795.338-3795.505" - cell $and $and$ls180.v:3795$319 + attribute \src "ls180.v:3843.338-3843.505" + cell $and $and$ls180.v:3843$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3795$317_Y - connect \B $eq$ls180.v:3795$318_Y - connect \Y $and$ls180.v:3795$319_Y + connect \A $eq$ls180.v:3843$317_Y + connect \B $eq$ls180.v:3843$318_Y + connect \Y $and$ls180.v:3843$319_Y end - attribute \src "ls180.v:3795.38-3795.507" - cell $and $and$ls180.v:3795$321 + attribute \src "ls180.v:3843.38-3843.507" + cell $and $and$ls180.v:3843$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3795$320_Y - connect \Y $and$ls180.v:3795$321_Y + connect \B $or$ls180.v:3843$320_Y + connect \Y $and$ls180.v:3843$321_Y end - attribute \src "ls180.v:3796.77-3796.153" - cell $and $and$ls180.v:3796$322 + attribute \src "ls180.v:3844.77-3844.153" + cell $and $and$ls180.v:3844$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232379,65 +237896,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3796$322_Y + connect \Y $and$ls180.v:3844$322_Y end - attribute \src "ls180.v:3796.162-3796.246" - cell $and $and$ls180.v:3796$324 + attribute \src "ls180.v:3844.162-3844.246" + cell $and $and$ls180.v:3844$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3796$323_Y - connect \Y $and$ls180.v:3796$324_Y + connect \B $not$ls180.v:3844$323_Y + connect \Y $and$ls180.v:3844$324_Y end - attribute \src "ls180.v:3796.161-3796.291" - cell $and $and$ls180.v:3796$326 + attribute \src "ls180.v:3844.161-3844.291" + cell $and $and$ls180.v:3844$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3796$324_Y - connect \B $not$ls180.v:3796$325_Y - connect \Y $and$ls180.v:3796$326_Y + connect \A $and$ls180.v:3844$324_Y + connect \B $not$ls180.v:3844$325_Y + connect \Y $and$ls180.v:3844$326_Y end - attribute \src "ls180.v:3796.76-3796.333" - cell $and $and$ls180.v:3796$329 + attribute \src "ls180.v:3844.76-3844.333" + cell $and $and$ls180.v:3844$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3796$322_Y - connect \B $or$ls180.v:3796$328_Y - connect \Y $and$ls180.v:3796$329_Y + connect \A $and$ls180.v:3844$322_Y + connect \B $or$ls180.v:3844$328_Y + connect \Y $and$ls180.v:3844$329_Y end - attribute \src "ls180.v:3796.338-3796.505" - cell $and $and$ls180.v:3796$332 + attribute \src "ls180.v:3844.338-3844.505" + cell $and $and$ls180.v:3844$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3796$330_Y - connect \B $eq$ls180.v:3796$331_Y - connect \Y $and$ls180.v:3796$332_Y + connect \A $eq$ls180.v:3844$330_Y + connect \B $eq$ls180.v:3844$331_Y + connect \Y $and$ls180.v:3844$332_Y end - attribute \src "ls180.v:3796.38-3796.507" - cell $and $and$ls180.v:3796$334 + attribute \src "ls180.v:3844.38-3844.507" + cell $and $and$ls180.v:3844$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3796$333_Y - connect \Y $and$ls180.v:3796$334_Y + connect \B $or$ls180.v:3844$333_Y + connect \Y $and$ls180.v:3844$334_Y end - attribute \src "ls180.v:3797.77-3797.153" - cell $and $and$ls180.v:3797$335 + attribute \src "ls180.v:3845.77-3845.153" + cell $and $and$ls180.v:3845$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232445,65 +237962,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3797$335_Y + connect \Y $and$ls180.v:3845$335_Y end - attribute \src "ls180.v:3797.162-3797.246" - cell $and $and$ls180.v:3797$337 + attribute \src "ls180.v:3845.162-3845.246" + cell $and $and$ls180.v:3845$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3797$336_Y - connect \Y $and$ls180.v:3797$337_Y + connect \B $not$ls180.v:3845$336_Y + connect \Y $and$ls180.v:3845$337_Y end - attribute \src "ls180.v:3797.161-3797.291" - cell $and $and$ls180.v:3797$339 + attribute \src "ls180.v:3845.161-3845.291" + cell $and $and$ls180.v:3845$339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3797$337_Y - connect \B $not$ls180.v:3797$338_Y - connect \Y $and$ls180.v:3797$339_Y + connect \A $and$ls180.v:3845$337_Y + connect \B $not$ls180.v:3845$338_Y + connect \Y $and$ls180.v:3845$339_Y end - attribute \src "ls180.v:3797.76-3797.333" - cell $and $and$ls180.v:3797$342 + attribute \src "ls180.v:3845.76-3845.333" + cell $and $and$ls180.v:3845$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3797$335_Y - connect \B $or$ls180.v:3797$341_Y - connect \Y $and$ls180.v:3797$342_Y + connect \A $and$ls180.v:3845$335_Y + connect \B $or$ls180.v:3845$341_Y + connect \Y $and$ls180.v:3845$342_Y end - attribute \src "ls180.v:3797.338-3797.505" - cell $and $and$ls180.v:3797$345 + attribute \src "ls180.v:3845.338-3845.505" + cell $and $and$ls180.v:3845$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3797$343_Y - connect \B $eq$ls180.v:3797$344_Y - connect \Y $and$ls180.v:3797$345_Y + connect \A $eq$ls180.v:3845$343_Y + connect \B $eq$ls180.v:3845$344_Y + connect \Y $and$ls180.v:3845$345_Y end - attribute \src "ls180.v:3797.38-3797.507" - cell $and $and$ls180.v:3797$347 + attribute \src "ls180.v:3845.38-3845.507" + cell $and $and$ls180.v:3845$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3797$346_Y - connect \Y $and$ls180.v:3797$347_Y + connect \B $or$ls180.v:3845$346_Y + connect \Y $and$ls180.v:3845$347_Y end - attribute \src "ls180.v:3826.8-3826.73" - cell $and $and$ls180.v:3826$352 + attribute \src "ls180.v:3874.8-3874.73" + cell $and $and$ls180.v:3874$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232511,21 +238028,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3826$352_Y + connect \Y $and$ls180.v:3874$352_Y end - attribute \src "ls180.v:3826.7-3826.114" - cell $and $and$ls180.v:3826$354 + attribute \src "ls180.v:3874.7-3874.114" + cell $and $and$ls180.v:3874$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3826$352_Y - connect \B $eq$ls180.v:3826$353_Y - connect \Y $and$ls180.v:3826$354_Y + connect \A $and$ls180.v:3874$352_Y + connect \B $eq$ls180.v:3874$353_Y + connect \Y $and$ls180.v:3874$354_Y end - attribute \src "ls180.v:3829.8-3829.73" - cell $and $and$ls180.v:3829$355 + attribute \src "ls180.v:3877.8-3877.73" + cell $and $and$ls180.v:3877$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232533,21 +238050,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3829$355_Y + connect \Y $and$ls180.v:3877$355_Y end - attribute \src "ls180.v:3829.7-3829.114" - cell $and $and$ls180.v:3829$357 + attribute \src "ls180.v:3877.7-3877.114" + cell $and $and$ls180.v:3877$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3829$355_Y - connect \B $eq$ls180.v:3829$356_Y - connect \Y $and$ls180.v:3829$357_Y + connect \A $and$ls180.v:3877$355_Y + connect \B $eq$ls180.v:3877$356_Y + connect \Y $and$ls180.v:3877$357_Y end - attribute \src "ls180.v:3835.8-3835.73" - cell $and $and$ls180.v:3835$359 + attribute \src "ls180.v:3883.8-3883.73" + cell $and $and$ls180.v:3883$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232555,21 +238072,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3835$359_Y + connect \Y $and$ls180.v:3883$359_Y end - attribute \src "ls180.v:3835.7-3835.114" - cell $and $and$ls180.v:3835$361 + attribute \src "ls180.v:3883.7-3883.114" + cell $and $and$ls180.v:3883$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3835$359_Y - connect \B $eq$ls180.v:3835$360_Y - connect \Y $and$ls180.v:3835$361_Y + connect \A $and$ls180.v:3883$359_Y + connect \B $eq$ls180.v:3883$360_Y + connect \Y $and$ls180.v:3883$361_Y end - attribute \src "ls180.v:3838.8-3838.73" - cell $and $and$ls180.v:3838$362 + attribute \src "ls180.v:3886.8-3886.73" + cell $and $and$ls180.v:3886$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232577,21 +238094,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3838$362_Y + connect \Y $and$ls180.v:3886$362_Y end - attribute \src "ls180.v:3838.7-3838.114" - cell $and $and$ls180.v:3838$364 + attribute \src "ls180.v:3886.7-3886.114" + cell $and $and$ls180.v:3886$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3838$362_Y - connect \B $eq$ls180.v:3838$363_Y - connect \Y $and$ls180.v:3838$364_Y + connect \A $and$ls180.v:3886$362_Y + connect \B $eq$ls180.v:3886$363_Y + connect \Y $and$ls180.v:3886$364_Y end - attribute \src "ls180.v:3844.8-3844.73" - cell $and $and$ls180.v:3844$366 + attribute \src "ls180.v:3892.8-3892.73" + cell $and $and$ls180.v:3892$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232599,21 +238116,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3844$366_Y + connect \Y $and$ls180.v:3892$366_Y end - attribute \src "ls180.v:3844.7-3844.114" - cell $and $and$ls180.v:3844$368 + attribute \src "ls180.v:3892.7-3892.114" + cell $and $and$ls180.v:3892$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$366_Y - connect \B $eq$ls180.v:3844$367_Y - connect \Y $and$ls180.v:3844$368_Y + connect \A $and$ls180.v:3892$366_Y + connect \B $eq$ls180.v:3892$367_Y + connect \Y $and$ls180.v:3892$368_Y end - attribute \src "ls180.v:3847.8-3847.73" - cell $and $and$ls180.v:3847$369 + attribute \src "ls180.v:3895.8-3895.73" + cell $and $and$ls180.v:3895$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232621,21 +238138,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3847$369_Y + connect \Y $and$ls180.v:3895$369_Y end - attribute \src "ls180.v:3847.7-3847.114" - cell $and $and$ls180.v:3847$371 + attribute \src "ls180.v:3895.7-3895.114" + cell $and $and$ls180.v:3895$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3847$369_Y - connect \B $eq$ls180.v:3847$370_Y - connect \Y $and$ls180.v:3847$371_Y + connect \A $and$ls180.v:3895$369_Y + connect \B $eq$ls180.v:3895$370_Y + connect \Y $and$ls180.v:3895$371_Y end - attribute \src "ls180.v:3853.8-3853.73" - cell $and $and$ls180.v:3853$373 + attribute \src "ls180.v:3901.8-3901.73" + cell $and $and$ls180.v:3901$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232643,21 +238160,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3853$373_Y + connect \Y $and$ls180.v:3901$373_Y end - attribute \src "ls180.v:3853.7-3853.114" - cell $and $and$ls180.v:3853$375 + attribute \src "ls180.v:3901.7-3901.114" + cell $and $and$ls180.v:3901$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3853$373_Y - connect \B $eq$ls180.v:3853$374_Y - connect \Y $and$ls180.v:3853$375_Y + connect \A $and$ls180.v:3901$373_Y + connect \B $eq$ls180.v:3901$374_Y + connect \Y $and$ls180.v:3901$375_Y end - attribute \src "ls180.v:3856.8-3856.73" - cell $and $and$ls180.v:3856$376 + attribute \src "ls180.v:3904.8-3904.73" + cell $and $and$ls180.v:3904$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -232665,615 +238182,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3856$376_Y + connect \Y $and$ls180.v:3904$376_Y end - attribute \src "ls180.v:3856.7-3856.114" - cell $and $and$ls180.v:3856$378 + attribute \src "ls180.v:3904.7-3904.114" + cell $and $and$ls180.v:3904$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3856$376_Y - connect \B $eq$ls180.v:3856$377_Y - connect \Y $and$ls180.v:3856$378_Y + connect \A $and$ls180.v:3904$376_Y + connect \B $eq$ls180.v:3904$377_Y + connect \Y $and$ls180.v:3904$378_Y end - attribute \src "ls180.v:3881.71-3881.151" - cell $and $and$ls180.v:3881$383 + attribute \src "ls180.v:3929.71-3929.151" + cell $and $and$ls180.v:3929$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3881$382_Y - connect \Y $and$ls180.v:3881$383_Y + connect \B $not$ls180.v:3929$382_Y + connect \Y $and$ls180.v:3929$383_Y end - attribute \src "ls180.v:3881.70-3881.194" - cell $and $and$ls180.v:3881$385 + attribute \src "ls180.v:3929.70-3929.194" + cell $and $and$ls180.v:3929$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3881$383_Y - connect \B $not$ls180.v:3881$384_Y - connect \Y $and$ls180.v:3881$385_Y + connect \A $and$ls180.v:3929$383_Y + connect \B $not$ls180.v:3929$384_Y + connect \Y $and$ls180.v:3929$385_Y end - attribute \src "ls180.v:3881.41-3881.222" - cell $and $and$ls180.v:3881$388 + attribute \src "ls180.v:3929.41-3929.222" + cell $and $and$ls180.v:3929$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3881$387_Y - connect \Y $and$ls180.v:3881$388_Y + connect \B $or$ls180.v:3929$387_Y + connect \Y $and$ls180.v:3929$388_Y end - attribute \src "ls180.v:3919.71-3919.151" - cell $and $and$ls180.v:3919$392 + attribute \src "ls180.v:3967.71-3967.151" + cell $and $and$ls180.v:3967$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3919$391_Y - connect \Y $and$ls180.v:3919$392_Y + connect \B $not$ls180.v:3967$391_Y + connect \Y $and$ls180.v:3967$392_Y end - attribute \src "ls180.v:3919.70-3919.194" - cell $and $and$ls180.v:3919$394 + attribute \src "ls180.v:3967.70-3967.194" + cell $and $and$ls180.v:3967$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$392_Y - connect \B $not$ls180.v:3919$393_Y - connect \Y $and$ls180.v:3919$394_Y + connect \A $and$ls180.v:3967$392_Y + connect \B $not$ls180.v:3967$393_Y + connect \Y $and$ls180.v:3967$394_Y end - attribute \src "ls180.v:3919.41-3919.222" - cell $and $and$ls180.v:3919$397 + attribute \src "ls180.v:3967.41-3967.222" + cell $and $and$ls180.v:3967$397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3919$396_Y - connect \Y $and$ls180.v:3919$397_Y + connect \B $or$ls180.v:3967$396_Y + connect \Y $and$ls180.v:3967$397_Y end - attribute \src "ls180.v:3937.110-3937.179" - cell $and $and$ls180.v:3937$402 + attribute \src "ls180.v:3985.110-3985.179" + cell $and $and$ls180.v:3985$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3937$401_Y - connect \Y $and$ls180.v:3937$402_Y + connect \B $eq$ls180.v:3985$401_Y + connect \Y $and$ls180.v:3985$402_Y end - attribute \src "ls180.v:3937.185-3937.254" - cell $and $and$ls180.v:3937$405 + attribute \src "ls180.v:3985.185-3985.254" + cell $and $and$ls180.v:3985$405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3937$404_Y - connect \Y $and$ls180.v:3937$405_Y + connect \B $eq$ls180.v:3985$404_Y + connect \Y $and$ls180.v:3985$405_Y end - attribute \src "ls180.v:3937.260-3937.329" - cell $and $and$ls180.v:3937$408 + attribute \src "ls180.v:3985.260-3985.329" + cell $and $and$ls180.v:3985$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3937$407_Y - connect \Y $and$ls180.v:3937$408_Y + connect \B $eq$ls180.v:3985$407_Y + connect \Y $and$ls180.v:3985$408_Y end - attribute \src "ls180.v:3937.41-3937.332" - cell $and $and$ls180.v:3937$411 + attribute \src "ls180.v:3985.41-3985.332" + cell $and $and$ls180.v:3985$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3937$400_Y - connect \B $not$ls180.v:3937$410_Y - connect \Y $and$ls180.v:3937$411_Y + connect \A $eq$ls180.v:3985$400_Y + connect \B $not$ls180.v:3985$410_Y + connect \Y $and$ls180.v:3985$411_Y end - attribute \src "ls180.v:3937.40-3937.355" - cell $and $and$ls180.v:3937$412 + attribute \src "ls180.v:3985.40-3985.355" + cell $and $and$ls180.v:3985$412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3937$411_Y + connect \A $and$ls180.v:3985$411_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3937$412_Y + connect \Y $and$ls180.v:3985$412_Y end - attribute \src "ls180.v:3938.34-3938.106" - cell $and $and$ls180.v:3938$415 + attribute \src "ls180.v:3986.34-3986.106" + cell $and $and$ls180.v:3986$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3938$413_Y - connect \B $not$ls180.v:3938$414_Y - connect \Y $and$ls180.v:3938$415_Y + connect \A $not$ls180.v:3986$413_Y + connect \B $not$ls180.v:3986$414_Y + connect \Y $and$ls180.v:3986$415_Y end - attribute \src "ls180.v:3942.110-3942.179" - cell $and $and$ls180.v:3942$418 + attribute \src "ls180.v:3990.110-3990.179" + cell $and $and$ls180.v:3990$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3942$417_Y - connect \Y $and$ls180.v:3942$418_Y + connect \B $eq$ls180.v:3990$417_Y + connect \Y $and$ls180.v:3990$418_Y end - attribute \src "ls180.v:3942.185-3942.254" - cell $and $and$ls180.v:3942$421 + attribute \src "ls180.v:3990.185-3990.254" + cell $and $and$ls180.v:3990$421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3942$420_Y - connect \Y $and$ls180.v:3942$421_Y + connect \B $eq$ls180.v:3990$420_Y + connect \Y $and$ls180.v:3990$421_Y end - attribute \src "ls180.v:3942.260-3942.329" - cell $and $and$ls180.v:3942$424 + attribute \src "ls180.v:3990.260-3990.329" + cell $and $and$ls180.v:3990$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3942$423_Y - connect \Y $and$ls180.v:3942$424_Y + connect \B $eq$ls180.v:3990$423_Y + connect \Y $and$ls180.v:3990$424_Y end - attribute \src "ls180.v:3942.41-3942.332" - cell $and $and$ls180.v:3942$427 + attribute \src "ls180.v:3990.41-3990.332" + cell $and $and$ls180.v:3990$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3942$416_Y - connect \B $not$ls180.v:3942$426_Y - connect \Y $and$ls180.v:3942$427_Y + connect \A $eq$ls180.v:3990$416_Y + connect \B $not$ls180.v:3990$426_Y + connect \Y $and$ls180.v:3990$427_Y end - attribute \src "ls180.v:3942.40-3942.355" - cell $and $and$ls180.v:3942$428 + attribute \src "ls180.v:3990.40-3990.355" + cell $and $and$ls180.v:3990$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3942$427_Y + connect \A $and$ls180.v:3990$427_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3942$428_Y + connect \Y $and$ls180.v:3990$428_Y end - attribute \src "ls180.v:3943.34-3943.106" - cell $and $and$ls180.v:3943$431 + attribute \src "ls180.v:3991.34-3991.106" + cell $and $and$ls180.v:3991$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3943$429_Y - connect \B $not$ls180.v:3943$430_Y - connect \Y $and$ls180.v:3943$431_Y + connect \A $not$ls180.v:3991$429_Y + connect \B $not$ls180.v:3991$430_Y + connect \Y $and$ls180.v:3991$431_Y end - attribute \src "ls180.v:3947.110-3947.179" - cell $and $and$ls180.v:3947$434 + attribute \src "ls180.v:3995.110-3995.179" + cell $and $and$ls180.v:3995$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3947$433_Y - connect \Y $and$ls180.v:3947$434_Y + connect \B $eq$ls180.v:3995$433_Y + connect \Y $and$ls180.v:3995$434_Y end - attribute \src "ls180.v:3947.185-3947.254" - cell $and $and$ls180.v:3947$437 + attribute \src "ls180.v:3995.185-3995.254" + cell $and $and$ls180.v:3995$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3947$436_Y - connect \Y $and$ls180.v:3947$437_Y + connect \B $eq$ls180.v:3995$436_Y + connect \Y $and$ls180.v:3995$437_Y end - attribute \src "ls180.v:3947.260-3947.329" - cell $and $and$ls180.v:3947$440 + attribute \src "ls180.v:3995.260-3995.329" + cell $and $and$ls180.v:3995$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3947$439_Y - connect \Y $and$ls180.v:3947$440_Y + connect \B $eq$ls180.v:3995$439_Y + connect \Y $and$ls180.v:3995$440_Y end - attribute \src "ls180.v:3947.41-3947.332" - cell $and $and$ls180.v:3947$443 + attribute \src "ls180.v:3995.41-3995.332" + cell $and $and$ls180.v:3995$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3947$432_Y - connect \B $not$ls180.v:3947$442_Y - connect \Y $and$ls180.v:3947$443_Y + connect \A $eq$ls180.v:3995$432_Y + connect \B $not$ls180.v:3995$442_Y + connect \Y $and$ls180.v:3995$443_Y end - attribute \src "ls180.v:3947.40-3947.355" - cell $and $and$ls180.v:3947$444 + attribute \src "ls180.v:3995.40-3995.355" + cell $and $and$ls180.v:3995$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3947$443_Y + connect \A $and$ls180.v:3995$443_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3947$444_Y + connect \Y $and$ls180.v:3995$444_Y end - attribute \src "ls180.v:3948.34-3948.106" - cell $and $and$ls180.v:3948$447 + attribute \src "ls180.v:3996.34-3996.106" + cell $and $and$ls180.v:3996$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3948$445_Y - connect \B $not$ls180.v:3948$446_Y - connect \Y $and$ls180.v:3948$447_Y + connect \A $not$ls180.v:3996$445_Y + connect \B $not$ls180.v:3996$446_Y + connect \Y $and$ls180.v:3996$447_Y end - attribute \src "ls180.v:3952.110-3952.179" - cell $and $and$ls180.v:3952$450 + attribute \src "ls180.v:4000.110-4000.179" + cell $and $and$ls180.v:4000$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3952$449_Y - connect \Y $and$ls180.v:3952$450_Y + connect \B $eq$ls180.v:4000$449_Y + connect \Y $and$ls180.v:4000$450_Y end - attribute \src "ls180.v:3952.185-3952.254" - cell $and $and$ls180.v:3952$453 + attribute \src "ls180.v:4000.185-4000.254" + cell $and $and$ls180.v:4000$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3952$452_Y - connect \Y $and$ls180.v:3952$453_Y + connect \B $eq$ls180.v:4000$452_Y + connect \Y $and$ls180.v:4000$453_Y end - attribute \src "ls180.v:3952.260-3952.329" - cell $and $and$ls180.v:3952$456 + attribute \src "ls180.v:4000.260-4000.329" + cell $and $and$ls180.v:4000$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3952$455_Y - connect \Y $and$ls180.v:3952$456_Y + connect \B $eq$ls180.v:4000$455_Y + connect \Y $and$ls180.v:4000$456_Y end - attribute \src "ls180.v:3952.41-3952.332" - cell $and $and$ls180.v:3952$459 + attribute \src "ls180.v:4000.41-4000.332" + cell $and $and$ls180.v:4000$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3952$448_Y - connect \B $not$ls180.v:3952$458_Y - connect \Y $and$ls180.v:3952$459_Y + connect \A $eq$ls180.v:4000$448_Y + connect \B $not$ls180.v:4000$458_Y + connect \Y $and$ls180.v:4000$459_Y end - attribute \src "ls180.v:3952.40-3952.355" - cell $and $and$ls180.v:3952$460 + attribute \src "ls180.v:4000.40-4000.355" + cell $and $and$ls180.v:4000$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3952$459_Y + connect \A $and$ls180.v:4000$459_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3952$460_Y + connect \Y $and$ls180.v:4000$460_Y end - attribute \src "ls180.v:3953.34-3953.106" - cell $and $and$ls180.v:3953$463 + attribute \src "ls180.v:4001.34-4001.106" + cell $and $and$ls180.v:4001$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3953$461_Y - connect \B $not$ls180.v:3953$462_Y - connect \Y $and$ls180.v:3953$463_Y + connect \A $not$ls180.v:4001$461_Y + connect \B $not$ls180.v:4001$462_Y + connect \Y $and$ls180.v:4001$463_Y end - attribute \src "ls180.v:3957.151-3957.220" - cell $and $and$ls180.v:3957$467 + attribute \src "ls180.v:4005.151-4005.220" + cell $and $and$ls180.v:4005$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3957$466_Y - connect \Y $and$ls180.v:3957$467_Y + connect \B $eq$ls180.v:4005$466_Y + connect \Y $and$ls180.v:4005$467_Y end - attribute \src "ls180.v:3957.226-3957.295" - cell $and $and$ls180.v:3957$470 + attribute \src "ls180.v:4005.226-4005.295" + cell $and $and$ls180.v:4005$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3957$469_Y - connect \Y $and$ls180.v:3957$470_Y + connect \B $eq$ls180.v:4005$469_Y + connect \Y $and$ls180.v:4005$470_Y end - attribute \src "ls180.v:3957.301-3957.370" - cell $and $and$ls180.v:3957$473 + attribute \src "ls180.v:4005.301-4005.370" + cell $and $and$ls180.v:4005$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3957$472_Y - connect \Y $and$ls180.v:3957$473_Y + connect \B $eq$ls180.v:4005$472_Y + connect \Y $and$ls180.v:4005$473_Y end - attribute \src "ls180.v:3957.82-3957.373" - cell $and $and$ls180.v:3957$476 + attribute \src "ls180.v:4005.82-4005.373" + cell $and $and$ls180.v:4005$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$465_Y - connect \B $not$ls180.v:3957$475_Y - connect \Y $and$ls180.v:3957$476_Y + connect \A $eq$ls180.v:4005$465_Y + connect \B $not$ls180.v:4005$475_Y + connect \Y $and$ls180.v:4005$476_Y end - attribute \src "ls180.v:3957.43-3957.374" - cell $and $and$ls180.v:3957$477 + attribute \src "ls180.v:4005.43-4005.374" + cell $and $and$ls180.v:4005$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$464_Y - connect \B $and$ls180.v:3957$476_Y - connect \Y $and$ls180.v:3957$477_Y + connect \A $eq$ls180.v:4005$464_Y + connect \B $and$ls180.v:4005$476_Y + connect \Y $and$ls180.v:4005$477_Y end - attribute \src "ls180.v:3957.42-3957.410" - cell $and $and$ls180.v:3957$478 + attribute \src "ls180.v:4005.42-4005.410" + cell $and $and$ls180.v:4005$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$477_Y + connect \A $and$ls180.v:4005$477_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:3957$478_Y + connect \Y $and$ls180.v:4005$478_Y end - attribute \src "ls180.v:3957.525-3957.594" - cell $and $and$ls180.v:3957$483 + attribute \src "ls180.v:4005.525-4005.594" + cell $and $and$ls180.v:4005$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3957$482_Y - connect \Y $and$ls180.v:3957$483_Y + connect \B $eq$ls180.v:4005$482_Y + connect \Y $and$ls180.v:4005$483_Y end - attribute \src "ls180.v:3957.600-3957.669" - cell $and $and$ls180.v:3957$486 + attribute \src "ls180.v:4005.600-4005.669" + cell $and $and$ls180.v:4005$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3957$485_Y - connect \Y $and$ls180.v:3957$486_Y + connect \B $eq$ls180.v:4005$485_Y + connect \Y $and$ls180.v:4005$486_Y end - attribute \src "ls180.v:3957.675-3957.744" - cell $and $and$ls180.v:3957$489 + attribute \src "ls180.v:4005.675-4005.744" + cell $and $and$ls180.v:4005$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3957$488_Y - connect \Y $and$ls180.v:3957$489_Y + connect \B $eq$ls180.v:4005$488_Y + connect \Y $and$ls180.v:4005$489_Y end - attribute \src "ls180.v:3957.456-3957.747" - cell $and $and$ls180.v:3957$492 + attribute \src "ls180.v:4005.456-4005.747" + cell $and $and$ls180.v:4005$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$481_Y - connect \B $not$ls180.v:3957$491_Y - connect \Y $and$ls180.v:3957$492_Y + connect \A $eq$ls180.v:4005$481_Y + connect \B $not$ls180.v:4005$491_Y + connect \Y $and$ls180.v:4005$492_Y end - attribute \src "ls180.v:3957.417-3957.748" - cell $and $and$ls180.v:3957$493 + attribute \src "ls180.v:4005.417-4005.748" + cell $and $and$ls180.v:4005$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$480_Y - connect \B $and$ls180.v:3957$492_Y - connect \Y $and$ls180.v:3957$493_Y + connect \A $eq$ls180.v:4005$480_Y + connect \B $and$ls180.v:4005$492_Y + connect \Y $and$ls180.v:4005$493_Y end - attribute \src "ls180.v:3957.416-3957.784" - cell $and $and$ls180.v:3957$494 + attribute \src "ls180.v:4005.416-4005.784" + cell $and $and$ls180.v:4005$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$493_Y + connect \A $and$ls180.v:4005$493_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:3957$494_Y + connect \Y $and$ls180.v:4005$494_Y end - attribute \src "ls180.v:3957.899-3957.968" - cell $and $and$ls180.v:3957$499 + attribute \src "ls180.v:4005.899-4005.968" + cell $and $and$ls180.v:4005$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3957$498_Y - connect \Y $and$ls180.v:3957$499_Y + connect \B $eq$ls180.v:4005$498_Y + connect \Y $and$ls180.v:4005$499_Y end - attribute \src "ls180.v:3957.974-3957.1043" - cell $and $and$ls180.v:3957$502 + attribute \src "ls180.v:4005.974-4005.1043" + cell $and $and$ls180.v:4005$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3957$501_Y - connect \Y $and$ls180.v:3957$502_Y + connect \B $eq$ls180.v:4005$501_Y + connect \Y $and$ls180.v:4005$502_Y end - attribute \src "ls180.v:3957.1049-3957.1118" - cell $and $and$ls180.v:3957$505 + attribute \src "ls180.v:4005.1049-4005.1118" + cell $and $and$ls180.v:4005$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3957$504_Y - connect \Y $and$ls180.v:3957$505_Y + connect \B $eq$ls180.v:4005$504_Y + connect \Y $and$ls180.v:4005$505_Y end - attribute \src "ls180.v:3957.830-3957.1121" - cell $and $and$ls180.v:3957$508 + attribute \src "ls180.v:4005.830-4005.1121" + cell $and $and$ls180.v:4005$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$497_Y - connect \B $not$ls180.v:3957$507_Y - connect \Y $and$ls180.v:3957$508_Y + connect \A $eq$ls180.v:4005$497_Y + connect \B $not$ls180.v:4005$507_Y + connect \Y $and$ls180.v:4005$508_Y end - attribute \src "ls180.v:3957.791-3957.1122" - cell $and $and$ls180.v:3957$509 + attribute \src "ls180.v:4005.791-4005.1122" + cell $and $and$ls180.v:4005$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$496_Y - connect \B $and$ls180.v:3957$508_Y - connect \Y $and$ls180.v:3957$509_Y + connect \A $eq$ls180.v:4005$496_Y + connect \B $and$ls180.v:4005$508_Y + connect \Y $and$ls180.v:4005$509_Y end - attribute \src "ls180.v:3957.790-3957.1158" - cell $and $and$ls180.v:3957$510 + attribute \src "ls180.v:4005.790-4005.1158" + cell $and $and$ls180.v:4005$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$509_Y + connect \A $and$ls180.v:4005$509_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:3957$510_Y + connect \Y $and$ls180.v:4005$510_Y end - attribute \src "ls180.v:3957.1273-3957.1342" - cell $and $and$ls180.v:3957$515 + attribute \src "ls180.v:4005.1273-4005.1342" + cell $and $and$ls180.v:4005$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3957$514_Y - connect \Y $and$ls180.v:3957$515_Y + connect \B $eq$ls180.v:4005$514_Y + connect \Y $and$ls180.v:4005$515_Y end - attribute \src "ls180.v:3957.1348-3957.1417" - cell $and $and$ls180.v:3957$518 + attribute \src "ls180.v:4005.1348-4005.1417" + cell $and $and$ls180.v:4005$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3957$517_Y - connect \Y $and$ls180.v:3957$518_Y + connect \B $eq$ls180.v:4005$517_Y + connect \Y $and$ls180.v:4005$518_Y end - attribute \src "ls180.v:3957.1423-3957.1492" - cell $and $and$ls180.v:3957$521 + attribute \src "ls180.v:4005.1423-4005.1492" + cell $and $and$ls180.v:4005$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3957$520_Y - connect \Y $and$ls180.v:3957$521_Y + connect \B $eq$ls180.v:4005$520_Y + connect \Y $and$ls180.v:4005$521_Y end - attribute \src "ls180.v:3957.1204-3957.1495" - cell $and $and$ls180.v:3957$524 + attribute \src "ls180.v:4005.1204-4005.1495" + cell $and $and$ls180.v:4005$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$513_Y - connect \B $not$ls180.v:3957$523_Y - connect \Y $and$ls180.v:3957$524_Y + connect \A $eq$ls180.v:4005$513_Y + connect \B $not$ls180.v:4005$523_Y + connect \Y $and$ls180.v:4005$524_Y end - attribute \src "ls180.v:3957.1165-3957.1496" - cell $and $and$ls180.v:3957$525 + attribute \src "ls180.v:4005.1165-4005.1496" + cell $and $and$ls180.v:4005$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3957$512_Y - connect \B $and$ls180.v:3957$524_Y - connect \Y $and$ls180.v:3957$525_Y + connect \A $eq$ls180.v:4005$512_Y + connect \B $and$ls180.v:4005$524_Y + connect \Y $and$ls180.v:4005$525_Y end - attribute \src "ls180.v:3957.1164-3957.1532" - cell $and $and$ls180.v:3957$526 + attribute \src "ls180.v:4005.1164-4005.1532" + cell $and $and$ls180.v:4005$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3957$525_Y + connect \A $and$ls180.v:4005$525_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:3957$526_Y + connect \Y $and$ls180.v:4005$526_Y end - attribute \src "ls180.v:4015.9-4015.46" - cell $and $and$ls180.v:4015$532 + attribute \src "ls180.v:4063.9-4063.46" + cell $and $and$ls180.v:4063$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233281,10 +238798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4015$532_Y + connect \Y $and$ls180.v:4063$532_Y end - attribute \src "ls180.v:4033.9-4033.46" - cell $and $and$ls180.v:4033$539 + attribute \src "ls180.v:4081.9-4081.46" + cell $and $and$ls180.v:4081$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233292,10 +238809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4033$539_Y + connect \Y $and$ls180.v:4081$539_Y end - attribute \src "ls180.v:4046.32-4046.75" - cell $and $and$ls180.v:4046$543 + attribute \src "ls180.v:4094.32-4094.75" + cell $and $and$ls180.v:4094$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233303,54 +238820,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4046$543_Y + connect \Y $and$ls180.v:4094$543_Y end - attribute \src "ls180.v:4046.31-4046.99" - cell $and $and$ls180.v:4046$545 + attribute \src "ls180.v:4094.31-4094.99" + cell $and $and$ls180.v:4094$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4046$543_Y - connect \B $not$ls180.v:4046$544_Y - connect \Y $and$ls180.v:4046$545_Y + connect \A $and$ls180.v:4094$543_Y + connect \B $not$ls180.v:4094$544_Y + connect \Y $and$ls180.v:4094$545_Y end - attribute \src "ls180.v:4047.34-4047.102" - cell $and $and$ls180.v:4047$547 + attribute \src "ls180.v:4095.34-4095.102" + cell $and $and$ls180.v:4095$547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4047$546_Y + connect \A $or$ls180.v:4095$546_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4047$547_Y + connect \Y $and$ls180.v:4095$547_Y end - attribute \src "ls180.v:4047.33-4047.128" - cell $and $and$ls180.v:4047$549 + attribute \src "ls180.v:4095.33-4095.128" + cell $and $and$ls180.v:4095$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4047$547_Y - connect \B $not$ls180.v:4047$548_Y - connect \Y $and$ls180.v:4047$549_Y + connect \A $and$ls180.v:4095$547_Y + connect \B $not$ls180.v:4095$548_Y + connect \Y $and$ls180.v:4095$549_Y end - attribute \src "ls180.v:4048.33-4048.104" - cell $and $and$ls180.v:4048$552 + attribute \src "ls180.v:4096.33-4096.104" + cell $and $and$ls180.v:4096$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4048$550_Y - connect \B $not$ls180.v:4048$551_Y - connect \Y $and$ls180.v:4048$552_Y + connect \A $or$ls180.v:4096$550_Y + connect \B $not$ls180.v:4096$551_Y + connect \Y $and$ls180.v:4096$552_Y end - attribute \src "ls180.v:4049.49-4049.85" - cell $and $and$ls180.v:4049$553 + attribute \src "ls180.v:4097.49-4097.85" + cell $and $and$ls180.v:4097$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233358,32 +238875,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4049$553_Y + connect \Y $and$ls180.v:4097$553_Y end - attribute \src "ls180.v:4049.90-4049.129" - cell $and $and$ls180.v:4049$555 + attribute \src "ls180.v:4097.90-4097.129" + cell $and $and$ls180.v:4097$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4049$554_Y + connect \A $not$ls180.v:4097$554_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4049$555_Y + connect \Y $and$ls180.v:4097$555_Y end - attribute \src "ls180.v:4049.32-4049.131" - cell $and $and$ls180.v:4049$557 + attribute \src "ls180.v:4097.32-4097.131" + cell $and $and$ls180.v:4097$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4049$556_Y - connect \Y $and$ls180.v:4049$557_Y + connect \B $or$ls180.v:4097$556_Y + connect \Y $and$ls180.v:4097$557_Y end - attribute \src "ls180.v:4050.25-4050.66" - cell $and $and$ls180.v:4050$558 + attribute \src "ls180.v:4098.25-4098.66" + cell $and $and$ls180.v:4098$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233391,10 +238908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4050$558_Y + connect \Y $and$ls180.v:4098$558_Y end - attribute \src "ls180.v:4051.27-4051.72" - cell $and $and$ls180.v:4051$560 + attribute \src "ls180.v:4099.27-4099.72" + cell $and $and$ls180.v:4099$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233402,10 +238919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4051$560_Y + connect \Y $and$ls180.v:4099$560_Y end - attribute \src "ls180.v:4052.26-4052.71" - cell $and $and$ls180.v:4052$562 + attribute \src "ls180.v:4100.26-4100.71" + cell $and $and$ls180.v:4100$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233413,10 +238930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4052$562_Y + connect \Y $and$ls180.v:4100$562_Y end - attribute \src "ls180.v:4081.64-4081.88" - cell $and $and$ls180.v:4081$568 + attribute \src "ls180.v:4129.64-4129.88" + cell $and $and$ls180.v:4129$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233424,10 +238941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4081$568_Y + connect \Y $and$ls180.v:4129$568_Y end - attribute \src "ls180.v:4085.7-4085.78" - cell $and $and$ls180.v:4085$572 + attribute \src "ls180.v:4133.7-4133.78" + cell $and $and$ls180.v:4133$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233435,10 +238952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4085$572_Y + connect \Y $and$ls180.v:4133$572_Y end - attribute \src "ls180.v:4096.7-4096.78" - cell $and $and$ls180.v:4096$575 + attribute \src "ls180.v:4144.7-4144.78" + cell $and $and$ls180.v:4144$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233446,10 +238963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4096$575_Y + connect \Y $and$ls180.v:4144$575_Y end - attribute \src "ls180.v:4105.26-4105.97" - cell $and $and$ls180.v:4105$577 + attribute \src "ls180.v:4153.26-4153.97" + cell $and $and$ls180.v:4153$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233457,10 +238974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4105$577_Y + connect \Y $and$ls180.v:4153$577_Y end - attribute \src "ls180.v:4105.102-4105.173" - cell $and $and$ls180.v:4105$578 + attribute \src "ls180.v:4153.102-4153.173" + cell $and $and$ls180.v:4153$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233468,32 +238985,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4105$578_Y + connect \Y $and$ls180.v:4153$578_Y end - attribute \src "ls180.v:4120.41-4120.133" - cell $and $and$ls180.v:4120$582 + attribute \src "ls180.v:4168.41-4168.133" + cell $and $and$ls180.v:4168$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4120$581_Y - connect \Y $and$ls180.v:4120$582_Y + connect \B $or$ls180.v:4168$581_Y + connect \Y $and$ls180.v:4168$582_Y end - attribute \src "ls180.v:4131.39-4131.136" - cell $and $and$ls180.v:4131$587 + attribute \src "ls180.v:4179.39-4179.136" + cell $and $and$ls180.v:4179$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4131$586_Y - connect \Y $and$ls180.v:4131$587_Y + connect \B $or$ls180.v:4179$586_Y + connect \Y $and$ls180.v:4179$587_Y end - attribute \src "ls180.v:4132.37-4132.104" - cell $and $and$ls180.v:4132$588 + attribute \src "ls180.v:4180.37-4180.104" + cell $and $and$ls180.v:4180$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233501,32 +239018,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4132$588_Y + connect \Y $and$ls180.v:4180$588_Y end - attribute \src "ls180.v:4150.41-4150.133" - cell $and $and$ls180.v:4150$593 + attribute \src "ls180.v:4198.41-4198.133" + cell $and $and$ls180.v:4198$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4150$592_Y - connect \Y $and$ls180.v:4150$593_Y + connect \B $or$ls180.v:4198$592_Y + connect \Y $and$ls180.v:4198$593_Y end - attribute \src "ls180.v:4161.39-4161.136" - cell $and $and$ls180.v:4161$598 + attribute \src "ls180.v:4209.39-4209.136" + cell $and $and$ls180.v:4209$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4161$597_Y - connect \Y $and$ls180.v:4161$598_Y + connect \B $or$ls180.v:4209$597_Y + connect \Y $and$ls180.v:4209$598_Y end - attribute \src "ls180.v:4162.37-4162.104" - cell $and $and$ls180.v:4162$599 + attribute \src "ls180.v:4210.37-4210.104" + cell $and $and$ls180.v:4210$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233534,21 +239051,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4162$599_Y + connect \Y $and$ls180.v:4210$599_Y end - attribute \src "ls180.v:4287.33-4287.86" - cell $and $and$ls180.v:4287$633 + attribute \src "ls180.v:4398.33-4398.86" + cell $and $and$ls180.v:4398$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4287$632_Y - connect \Y $and$ls180.v:4287$633_Y + connect \B $not$ls180.v:4398$640_Y + connect \Y $and$ls180.v:4398$641_Y end - attribute \src "ls180.v:4391.9-4391.68" - cell $and $and$ls180.v:4391$642 + attribute \src "ls180.v:4502.9-4502.68" + cell $and $and$ls180.v:4502$650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233556,21 +239073,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4391$642_Y + connect \Y $and$ls180.v:4502$650_Y end - attribute \src "ls180.v:4411.53-4411.145" - cell $and $and$ls180.v:4411$645 + attribute \src "ls180.v:4522.53-4522.145" + cell $and $and$ls180.v:4522$653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4411$644_Y - connect \Y $and$ls180.v:4411$645_Y + connect \B $or$ls180.v:4522$652_Y + connect \Y $and$ls180.v:4522$653_Y end - attribute \src "ls180.v:4430.52-4430.137" - cell $and $and$ls180.v:4430$648 + attribute \src "ls180.v:4541.52-4541.137" + cell $and $and$ls180.v:4541$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233578,10 +239095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4430$648_Y + connect \Y $and$ls180.v:4541$656_Y end - attribute \src "ls180.v:4471.9-4471.68" - cell $and $and$ls180.v:4471$656 + attribute \src "ls180.v:4582.9-4582.68" + cell $and $and$ls180.v:4582$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233589,10 +239106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4471$656_Y + connect \Y $and$ls180.v:4582$664_Y end - attribute \src "ls180.v:4509.9-4509.68" - cell $and $and$ls180.v:4509$662 + attribute \src "ls180.v:4620.9-4620.68" + cell $and $and$ls180.v:4620$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233600,10 +239117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4509$662_Y + connect \Y $and$ls180.v:4620$670_Y end - attribute \src "ls180.v:4518.10-4518.69" - cell $and $and$ls180.v:4518$663 + attribute \src "ls180.v:4629.10-4629.69" + cell $and $and$ls180.v:4629$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233611,21 +239128,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4518$663_Y + connect \Y $and$ls180.v:4629$671_Y end - attribute \src "ls180.v:4518.9-4518.93" - cell $and $and$ls180.v:4518$664 + attribute \src "ls180.v:4629.9-4629.93" + cell $and $and$ls180.v:4629$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4518$663_Y + connect \A $and$ls180.v:4629$671_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4518$664_Y + connect \Y $and$ls180.v:4629$672_Y end - attribute \src "ls180.v:4538.54-4538.117" - cell $and $and$ls180.v:4538$666 + attribute \src "ls180.v:4649.54-4649.117" + cell $and $and$ls180.v:4649$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233633,10 +239150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4538$666_Y + connect \Y $and$ls180.v:4649$674_Y end - attribute \src "ls180.v:4557.53-4557.140" - cell $and $and$ls180.v:4557$669 + attribute \src "ls180.v:4668.53-4668.140" + cell $and $and$ls180.v:4668$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233644,10 +239161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4557$669_Y + connect \Y $and$ls180.v:4668$677_Y end - attribute \src "ls180.v:4654.9-4654.70" - cell $and $and$ls180.v:4654$679 + attribute \src "ls180.v:4765.9-4765.70" + cell $and $and$ls180.v:4765$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233655,10 +239172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4654$679_Y + connect \Y $and$ls180.v:4765$687_Y end - attribute \src "ls180.v:4672.55-4672.120" - cell $and $and$ls180.v:4672$681 + attribute \src "ls180.v:4783.55-4783.120" + cell $and $and$ls180.v:4783$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233666,10 +239183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4672$681_Y + connect \Y $and$ls180.v:4783$689_Y end - attribute \src "ls180.v:4691.54-4691.143" - cell $and $and$ls180.v:4691$684 + attribute \src "ls180.v:4802.54-4802.143" + cell $and $and$ls180.v:4802$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233677,10 +239194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4691$684_Y + connect \Y $and$ls180.v:4802$692_Y end - attribute \src "ls180.v:4773.9-4773.70" - cell $and $and$ls180.v:4773$699 + attribute \src "ls180.v:4884.9-4884.70" + cell $and $and$ls180.v:4884$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233688,10 +239205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4773$699_Y + connect \Y $and$ls180.v:4884$707_Y end - attribute \src "ls180.v:4780.9-4780.70" - cell $and $and$ls180.v:4780$700 + attribute \src "ls180.v:4891.9-4891.70" + cell $and $and$ls180.v:4891$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233699,10 +239216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4780$700_Y + connect \Y $and$ls180.v:4891$708_Y end - attribute \src "ls180.v:4861.48-4861.124" - cell $and $and$ls180.v:4861$823 + attribute \src "ls180.v:4972.48-4972.124" + cell $and $and$ls180.v:4972$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233710,21 +239227,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4861$823_Y + connect \Y $and$ls180.v:4972$831_Y end - attribute \src "ls180.v:4861.47-4861.165" - cell $and $and$ls180.v:4861$824 + attribute \src "ls180.v:4972.47-4972.165" + cell $and $and$ls180.v:4972$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4861$823_Y + connect \A $and$ls180.v:4972$831_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4861$824_Y + connect \Y $and$ls180.v:4972$832_Y end - attribute \src "ls180.v:4862.50-4862.127" - cell $and $and$ls180.v:4862$825 + attribute \src "ls180.v:4973.50-4973.127" + cell $and $and$ls180.v:4973$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233732,10 +239249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4862$825_Y + connect \Y $and$ls180.v:4973$833_Y end - attribute \src "ls180.v:4864.48-4864.124" - cell $and $and$ls180.v:4864$826 + attribute \src "ls180.v:4975.48-4975.124" + cell $and $and$ls180.v:4975$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233743,21 +239260,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4864$826_Y + connect \Y $and$ls180.v:4975$834_Y end - attribute \src "ls180.v:4864.47-4864.165" - cell $and $and$ls180.v:4864$827 + attribute \src "ls180.v:4975.47-4975.165" + cell $and $and$ls180.v:4975$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4864$826_Y + connect \A $and$ls180.v:4975$834_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4864$827_Y + connect \Y $and$ls180.v:4975$835_Y end - attribute \src "ls180.v:4865.50-4865.127" - cell $and $and$ls180.v:4865$828 + attribute \src "ls180.v:4976.50-4976.127" + cell $and $and$ls180.v:4976$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233765,10 +239282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4865$828_Y + connect \Y $and$ls180.v:4976$836_Y end - attribute \src "ls180.v:4867.48-4867.124" - cell $and $and$ls180.v:4867$829 + attribute \src "ls180.v:4978.48-4978.124" + cell $and $and$ls180.v:4978$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233776,21 +239293,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4867$829_Y + connect \Y $and$ls180.v:4978$837_Y end - attribute \src "ls180.v:4867.47-4867.165" - cell $and $and$ls180.v:4867$830 + attribute \src "ls180.v:4978.47-4978.165" + cell $and $and$ls180.v:4978$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4867$829_Y + connect \A $and$ls180.v:4978$837_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4867$830_Y + connect \Y $and$ls180.v:4978$838_Y end - attribute \src "ls180.v:4868.50-4868.127" - cell $and $and$ls180.v:4868$831 + attribute \src "ls180.v:4979.50-4979.127" + cell $and $and$ls180.v:4979$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233798,10 +239315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4868$831_Y + connect \Y $and$ls180.v:4979$839_Y end - attribute \src "ls180.v:4870.48-4870.124" - cell $and $and$ls180.v:4870$832 + attribute \src "ls180.v:4981.48-4981.124" + cell $and $and$ls180.v:4981$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233809,21 +239326,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4870$832_Y + connect \Y $and$ls180.v:4981$840_Y end - attribute \src "ls180.v:4870.47-4870.165" - cell $and $and$ls180.v:4870$833 + attribute \src "ls180.v:4981.47-4981.165" + cell $and $and$ls180.v:4981$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4870$832_Y + connect \A $and$ls180.v:4981$840_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4870$833_Y + connect \Y $and$ls180.v:4981$841_Y end - attribute \src "ls180.v:4871.50-4871.127" - cell $and $and$ls180.v:4871$834 + attribute \src "ls180.v:4982.50-4982.127" + cell $and $and$ls180.v:4982$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233831,10 +239348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4871$834_Y + connect \Y $and$ls180.v:4982$842_Y end - attribute \src "ls180.v:4984.10-4984.86" - cell $and $and$ls180.v:4984$883 + attribute \src "ls180.v:5095.10-5095.86" + cell $and $and$ls180.v:5095$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233842,54 +239359,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:4984$883_Y + connect \Y $and$ls180.v:5095$891_Y end - attribute \src "ls180.v:4984.9-4984.127" - cell $and $and$ls180.v:4984$884 + attribute \src "ls180.v:5095.9-5095.127" + cell $and $and$ls180.v:5095$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4984$883_Y + connect \A $and$ls180.v:5095$891_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4984$884_Y + connect \Y $and$ls180.v:5095$892_Y end - attribute \src "ls180.v:4994.9-4994.152" - cell $and $and$ls180.v:4994$888 + attribute \src "ls180.v:5105.9-5105.152" + cell $and $and$ls180.v:5105$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4994$886_Y - connect \B $eq$ls180.v:4994$887_Y - connect \Y $and$ls180.v:4994$888_Y + connect \A $eq$ls180.v:5105$894_Y + connect \B $eq$ls180.v:5105$895_Y + connect \Y $and$ls180.v:5105$896_Y end - attribute \src "ls180.v:4994.8-4994.226" - cell $and $and$ls180.v:4994$890 + attribute \src "ls180.v:5105.8-5105.226" + cell $and $and$ls180.v:5105$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4994$888_Y - connect \B $eq$ls180.v:4994$889_Y - connect \Y $and$ls180.v:4994$890_Y + connect \A $and$ls180.v:5105$896_Y + connect \B $eq$ls180.v:5105$897_Y + connect \Y $and$ls180.v:5105$898_Y end - attribute \src "ls180.v:4994.7-4994.300" - cell $and $and$ls180.v:4994$892 + attribute \src "ls180.v:5105.7-5105.300" + cell $and $and$ls180.v:5105$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4994$890_Y - connect \B $eq$ls180.v:4994$891_Y - connect \Y $and$ls180.v:4994$892_Y + connect \A $and$ls180.v:5105$898_Y + connect \B $eq$ls180.v:5105$899_Y + connect \Y $and$ls180.v:5105$900_Y end - attribute \src "ls180.v:4999.49-4999.124" - cell $and $and$ls180.v:4999$893 + attribute \src "ls180.v:5110.49-5110.124" + cell $and $and$ls180.v:5110$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233897,10 +239414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:4999$893_Y + connect \Y $and$ls180.v:5110$901_Y end - attribute \src "ls180.v:5009.49-5009.124" - cell $and $and$ls180.v:5009$896 + attribute \src "ls180.v:5120.49-5120.124" + cell $and $and$ls180.v:5120$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233908,10 +239425,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5009$896_Y + connect \Y $and$ls180.v:5120$904_Y end - attribute \src "ls180.v:5019.49-5019.124" - cell $and $and$ls180.v:5019$899 + attribute \src "ls180.v:5130.49-5130.124" + cell $and $and$ls180.v:5130$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233919,10 +239436,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5019$899_Y + connect \Y $and$ls180.v:5130$907_Y end - attribute \src "ls180.v:5029.49-5029.124" - cell $and $and$ls180.v:5029$902 + attribute \src "ls180.v:5140.49-5140.124" + cell $and $and$ls180.v:5140$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233930,21 +239447,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5029$902_Y + connect \Y $and$ls180.v:5140$910_Y end - attribute \src "ls180.v:5041.7-5041.84" - cell $and $and$ls180.v:5041$907 + attribute \src "ls180.v:5152.7-5152.84" + cell $and $and$ls180.v:5152$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5041$906_Y - connect \Y $and$ls180.v:5041$907_Y + connect \B $gt$ls180.v:5152$914_Y + connect \Y $and$ls180.v:5152$915_Y end - attribute \src "ls180.v:5159.9-5159.64" - cell $and $and$ls180.v:5159$956 + attribute \src "ls180.v:5270.9-5270.64" + cell $and $and$ls180.v:5270$964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233952,10 +239469,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5159$956_Y + connect \Y $and$ls180.v:5270$964_Y end - attribute \src "ls180.v:5211.10-5211.66" - cell $and $and$ls180.v:5211$965 + attribute \src "ls180.v:5322.10-5322.66" + cell $and $and$ls180.v:5322$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233963,21 +239480,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5211$965_Y + connect \Y $and$ls180.v:5322$973_Y end - attribute \src "ls180.v:5211.9-5211.97" - cell $and $and$ls180.v:5211$966 + attribute \src "ls180.v:5322.9-5322.97" + cell $and $and$ls180.v:5322$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5211$965_Y + connect \A $and$ls180.v:5322$973_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5211$966_Y + connect \Y $and$ls180.v:5322$974_Y end - attribute \src "ls180.v:5237.11-5237.71" - cell $and $and$ls180.v:5237$974 + attribute \src "ls180.v:5348.11-5348.71" + cell $and $and$ls180.v:5348$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233985,21 +239502,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5237$974_Y + connect \Y $and$ls180.v:5348$982_Y end - attribute \src "ls180.v:5321.43-5321.152" - cell $and $and$ls180.v:5321$982 + attribute \src "ls180.v:5432.43-5432.152" + cell $and $and$ls180.v:5432$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5321$981_Y - connect \Y $and$ls180.v:5321$982_Y + connect \B $or$ls180.v:5432$989_Y + connect \Y $and$ls180.v:5432$990_Y end - attribute \src "ls180.v:5322.41-5322.116" - cell $and $and$ls180.v:5322$983 + attribute \src "ls180.v:5433.41-5433.116" + cell $and $and$ls180.v:5433$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234007,10 +239524,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5322$983_Y + connect \Y $and$ls180.v:5433$991_Y end - attribute \src "ls180.v:5334.48-5334.125" - cell $and $and$ls180.v:5334$988 + attribute \src "ls180.v:5445.48-5445.125" + cell $and $and$ls180.v:5445$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234018,10 +239535,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5334$988_Y + connect \Y $and$ls180.v:5445$996_Y end - attribute \src "ls180.v:5361.9-5361.102" - cell $and $and$ls180.v:5361$992 + attribute \src "ls180.v:5472.9-5472.102" + cell $and $and$ls180.v:5472$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234029,10 +239546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5361$992_Y + connect \Y $and$ls180.v:5472$1000_Y end - attribute \src "ls180.v:5434.9-5434.58" - cell $and $and$ls180.v:5434$998 + attribute \src "ls180.v:5545.9-5545.58" + cell $and $and$ls180.v:5545$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234040,10 +239557,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5434$998_Y + connect \Y $and$ls180.v:5545$1006_Y end - attribute \src "ls180.v:5487.51-5487.123" - cell $and $and$ls180.v:5487$1006 + attribute \src "ls180.v:5598.51-5598.123" + cell $and $and$ls180.v:5598$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234051,10 +239568,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5487$1006_Y + connect \Y $and$ls180.v:5598$1014_Y end - attribute \src "ls180.v:5488.50-5488.120" - cell $and $and$ls180.v:5488$1007 + attribute \src "ls180.v:5599.50-5599.120" + cell $and $and$ls180.v:5599$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234062,10 +239579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5488$1007_Y + connect \Y $and$ls180.v:5599$1015_Y end - attribute \src "ls180.v:5489.49-5489.122" - cell $and $and$ls180.v:5489$1008 + attribute \src "ls180.v:5600.49-5600.122" + cell $and $and$ls180.v:5600$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234073,21 +239590,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5489$1008_Y + connect \Y $and$ls180.v:5600$1016_Y end - attribute \src "ls180.v:5529.43-5529.152" - cell $and $and$ls180.v:5529$1013 + attribute \src "ls180.v:5640.43-5640.152" + cell $and $and$ls180.v:5640$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5529$1012_Y - connect \Y $and$ls180.v:5529$1013_Y + connect \B $or$ls180.v:5640$1020_Y + connect \Y $and$ls180.v:5640$1021_Y end - attribute \src "ls180.v:5530.41-5530.116" - cell $and $and$ls180.v:5530$1014 + attribute \src "ls180.v:5641.41-5641.116" + cell $and $and$ls180.v:5641$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234095,10 +239612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5530$1014_Y + connect \Y $and$ls180.v:5641$1022_Y end - attribute \src "ls180.v:5621.9-5621.76" - cell $and $and$ls180.v:5621$1026 + attribute \src "ls180.v:5673.9-5673.76" + cell $and $and$ls180.v:5673$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234106,131 +239623,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5621$1026_Y + connect \Y $and$ls180.v:5673$1026_Y end - attribute \src "ls180.v:5624.44-5624.120" - cell $and $and$ls180.v:5624$1028 + attribute \src "ls180.v:5676.44-5676.120" + cell $and $and$ls180.v:5676$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5624$1027_Y - connect \Y $and$ls180.v:5624$1028_Y + connect \B $ne$ls180.v:5676$1027_Y + connect \Y $and$ls180.v:5676$1028_Y end - attribute \src "ls180.v:5644.63-5644.107" - cell $and $and$ls180.v:5644$1030 + attribute \src "ls180.v:5696.63-5696.107" + cell $and $and$ls180.v:5696$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5644$1029_Y - connect \Y $and$ls180.v:5644$1030_Y + connect \B $eq$ls180.v:5696$1029_Y + connect \Y $and$ls180.v:5696$1030_Y end - attribute \src "ls180.v:5645.63-5645.107" - cell $and $and$ls180.v:5645$1032 + attribute \src "ls180.v:5697.63-5697.107" + cell $and $and$ls180.v:5697$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5645$1031_Y - connect \Y $and$ls180.v:5645$1032_Y + connect \B $eq$ls180.v:5697$1031_Y + connect \Y $and$ls180.v:5697$1032_Y end - attribute \src "ls180.v:5646.63-5646.107" - cell $and $and$ls180.v:5646$1034 + attribute \src "ls180.v:5698.63-5698.107" + cell $and $and$ls180.v:5698$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5646$1033_Y - connect \Y $and$ls180.v:5646$1034_Y + connect \B $eq$ls180.v:5698$1033_Y + connect \Y $and$ls180.v:5698$1034_Y end - attribute \src "ls180.v:5647.35-5647.79" - cell $and $and$ls180.v:5647$1036 + attribute \src "ls180.v:5699.35-5699.79" + cell $and $and$ls180.v:5699$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5647$1035_Y - connect \Y $and$ls180.v:5647$1036_Y + connect \B $eq$ls180.v:5699$1035_Y + connect \Y $and$ls180.v:5699$1036_Y end - attribute \src "ls180.v:5648.35-5648.79" - cell $and $and$ls180.v:5648$1038 + attribute \src "ls180.v:5700.35-5700.79" + cell $and $and$ls180.v:5700$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5648$1037_Y - connect \Y $and$ls180.v:5648$1038_Y + connect \B $eq$ls180.v:5700$1037_Y + connect \Y $and$ls180.v:5700$1038_Y end - attribute \src "ls180.v:5649.63-5649.107" - cell $and $and$ls180.v:5649$1040 + attribute \src "ls180.v:5701.63-5701.107" + cell $and $and$ls180.v:5701$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5649$1039_Y - connect \Y $and$ls180.v:5649$1040_Y + connect \B $eq$ls180.v:5701$1039_Y + connect \Y $and$ls180.v:5701$1040_Y end - attribute \src "ls180.v:5650.63-5650.107" - cell $and $and$ls180.v:5650$1042 + attribute \src "ls180.v:5702.63-5702.107" + cell $and $and$ls180.v:5702$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5650$1041_Y - connect \Y $and$ls180.v:5650$1042_Y + connect \B $eq$ls180.v:5702$1041_Y + connect \Y $and$ls180.v:5702$1042_Y end - attribute \src "ls180.v:5651.63-5651.107" - cell $and $and$ls180.v:5651$1044 + attribute \src "ls180.v:5703.63-5703.107" + cell $and $and$ls180.v:5703$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5651$1043_Y - connect \Y $and$ls180.v:5651$1044_Y + connect \B $eq$ls180.v:5703$1043_Y + connect \Y $and$ls180.v:5703$1044_Y end - attribute \src "ls180.v:5652.35-5652.79" - cell $and $and$ls180.v:5652$1046 + attribute \src "ls180.v:5704.35-5704.79" + cell $and $and$ls180.v:5704$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5652$1045_Y - connect \Y $and$ls180.v:5652$1046_Y + connect \B $eq$ls180.v:5704$1045_Y + connect \Y $and$ls180.v:5704$1046_Y end - attribute \src "ls180.v:5653.35-5653.79" - cell $and $and$ls180.v:5653$1048 + attribute \src "ls180.v:5705.35-5705.79" + cell $and $and$ls180.v:5705$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5653$1047_Y - connect \Y $and$ls180.v:5653$1048_Y + connect \B $eq$ls180.v:5705$1047_Y + connect \Y $and$ls180.v:5705$1048_Y end - attribute \src "ls180.v:5698.40-5698.81" - cell $and $and$ls180.v:5698$1055 + attribute \src "ls180.v:5750.40-5750.81" + cell $and $and$ls180.v:5750$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234238,10 +239755,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5698$1055_Y + connect \Y $and$ls180.v:5750$1055_Y end - attribute \src "ls180.v:5699.50-5699.91" - cell $and $and$ls180.v:5699$1056 + attribute \src "ls180.v:5751.50-5751.91" + cell $and $and$ls180.v:5751$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234249,10 +239766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5699$1056_Y + connect \Y $and$ls180.v:5751$1056_Y end - attribute \src "ls180.v:5700.50-5700.91" - cell $and $and$ls180.v:5700$1057 + attribute \src "ls180.v:5752.50-5752.91" + cell $and $and$ls180.v:5752$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234260,10 +239777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5700$1057_Y + connect \Y $and$ls180.v:5752$1057_Y end - attribute \src "ls180.v:5701.29-5701.70" - cell $and $and$ls180.v:5701$1058 + attribute \src "ls180.v:5753.29-5753.70" + cell $and $and$ls180.v:5753$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234271,10 +239788,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5701$1058_Y + connect \Y $and$ls180.v:5753$1058_Y end - attribute \src "ls180.v:5702.44-5702.85" - cell $and $and$ls180.v:5702$1059 + attribute \src "ls180.v:5754.44-5754.85" + cell $and $and$ls180.v:5754$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234282,10 +239799,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5702$1059_Y + connect \Y $and$ls180.v:5754$1059_Y end - attribute \src "ls180.v:5704.25-5704.64" - cell $and $and$ls180.v:5704$1064 + attribute \src "ls180.v:5756.25-5756.64" + cell $and $and$ls180.v:5756$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234293,21 +239810,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5704$1064_Y + connect \Y $and$ls180.v:5756$1064_Y end - attribute \src "ls180.v:5704.24-5704.89" - cell $and $and$ls180.v:5704$1066 + attribute \src "ls180.v:5756.24-5756.89" + cell $and $and$ls180.v:5756$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5704$1064_Y - connect \B $not$ls180.v:5704$1065_Y - connect \Y $and$ls180.v:5704$1066_Y + connect \A $and$ls180.v:5756$1064_Y + connect \B $not$ls180.v:5756$1065_Y + connect \Y $and$ls180.v:5756$1066_Y end - attribute \src "ls180.v:5710.31-5710.92" - cell $and $and$ls180.v:5710$1072 + attribute \src "ls180.v:5762.31-5762.92" + cell $and $and$ls180.v:5762$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -234315,10 +239832,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5710$1072_Y + connect \Y $and$ls180.v:5762$1072_Y end - attribute \src "ls180.v:5710.97-5710.168" - cell $and $and$ls180.v:5710$1073 + attribute \src "ls180.v:5762.97-5762.168" + cell $and $and$ls180.v:5762$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -234326,10 +239843,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5710$1073_Y + connect \Y $and$ls180.v:5762$1073_Y end - attribute \src "ls180.v:5710.174-5710.245" - cell $and $and$ls180.v:5710$1075 + attribute \src "ls180.v:5762.174-5762.245" + cell $and $and$ls180.v:5762$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -234337,10 +239854,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5710$1075_Y + connect \Y $and$ls180.v:5762$1075_Y end - attribute \src "ls180.v:5710.251-5710.301" - cell $and $and$ls180.v:5710$1077 + attribute \src "ls180.v:5762.251-5762.301" + cell $and $and$ls180.v:5762$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -234348,10 +239865,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5710$1077_Y + connect \Y $and$ls180.v:5762$1077_Y end - attribute \src "ls180.v:5710.307-5710.372" - cell $and $and$ls180.v:5710$1079 + attribute \src "ls180.v:5762.307-5762.372" + cell $and $and$ls180.v:5762$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -234359,10 +239876,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5710$1079_Y + connect \Y $and$ls180.v:5762$1079_Y end - attribute \src "ls180.v:5720.39-5720.92" - cell $and $and$ls180.v:5720$1083 + attribute \src "ls180.v:5772.39-5772.92" + cell $and $and$ls180.v:5772$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234370,43 +239887,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5720$1083_Y + connect \Y $and$ls180.v:5772$1083_Y end - attribute \src "ls180.v:5720.38-5720.142" - cell $and $and$ls180.v:5720$1085 + attribute \src "ls180.v:5772.38-5772.142" + cell $and $and$ls180.v:5772$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5720$1083_Y - connect \B $eq$ls180.v:5720$1084_Y - connect \Y $and$ls180.v:5720$1085_Y + connect \A $and$ls180.v:5772$1083_Y + connect \B $eq$ls180.v:5772$1084_Y + connect \Y $and$ls180.v:5772$1085_Y end - attribute \src "ls180.v:5721.39-5721.95" - cell $and $and$ls180.v:5721$1087 + attribute \src "ls180.v:5773.39-5773.95" + cell $and $and$ls180.v:5773$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5721$1086_Y - connect \Y $and$ls180.v:5721$1087_Y + connect \B $not$ls180.v:5773$1086_Y + connect \Y $and$ls180.v:5773$1087_Y end - attribute \src "ls180.v:5721.38-5721.145" - cell $and $and$ls180.v:5721$1089 + attribute \src "ls180.v:5773.38-5773.145" + cell $and $and$ls180.v:5773$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5721$1087_Y - connect \B $eq$ls180.v:5721$1088_Y - connect \Y $and$ls180.v:5721$1089_Y + connect \A $and$ls180.v:5773$1087_Y + connect \B $eq$ls180.v:5773$1088_Y + connect \Y $and$ls180.v:5773$1089_Y end - attribute \src "ls180.v:5723.41-5723.94" - cell $and $and$ls180.v:5723$1090 + attribute \src "ls180.v:5775.41-5775.94" + cell $and $and$ls180.v:5775$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234414,43 +239931,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5723$1090_Y + connect \Y $and$ls180.v:5775$1090_Y end - attribute \src "ls180.v:5723.40-5723.144" - cell $and $and$ls180.v:5723$1092 + attribute \src "ls180.v:5775.40-5775.144" + cell $and $and$ls180.v:5775$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5723$1090_Y - connect \B $eq$ls180.v:5723$1091_Y - connect \Y $and$ls180.v:5723$1092_Y + connect \A $and$ls180.v:5775$1090_Y + connect \B $eq$ls180.v:5775$1091_Y + connect \Y $and$ls180.v:5775$1092_Y end - attribute \src "ls180.v:5724.41-5724.97" - cell $and $and$ls180.v:5724$1094 + attribute \src "ls180.v:5776.41-5776.97" + cell $and $and$ls180.v:5776$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5724$1093_Y - connect \Y $and$ls180.v:5724$1094_Y + connect \B $not$ls180.v:5776$1093_Y + connect \Y $and$ls180.v:5776$1094_Y end - attribute \src "ls180.v:5724.40-5724.147" - cell $and $and$ls180.v:5724$1096 + attribute \src "ls180.v:5776.40-5776.147" + cell $and $and$ls180.v:5776$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5724$1094_Y - connect \B $eq$ls180.v:5724$1095_Y - connect \Y $and$ls180.v:5724$1096_Y + connect \A $and$ls180.v:5776$1094_Y + connect \B $eq$ls180.v:5776$1095_Y + connect \Y $and$ls180.v:5776$1096_Y end - attribute \src "ls180.v:5726.41-5726.94" - cell $and $and$ls180.v:5726$1097 + attribute \src "ls180.v:5778.41-5778.94" + cell $and $and$ls180.v:5778$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234458,43 +239975,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5726$1097_Y + connect \Y $and$ls180.v:5778$1097_Y end - attribute \src "ls180.v:5726.40-5726.144" - cell $and $and$ls180.v:5726$1099 + attribute \src "ls180.v:5778.40-5778.144" + cell $and $and$ls180.v:5778$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5726$1097_Y - connect \B $eq$ls180.v:5726$1098_Y - connect \Y $and$ls180.v:5726$1099_Y + connect \A $and$ls180.v:5778$1097_Y + connect \B $eq$ls180.v:5778$1098_Y + connect \Y $and$ls180.v:5778$1099_Y end - attribute \src "ls180.v:5727.41-5727.97" - cell $and $and$ls180.v:5727$1101 + attribute \src "ls180.v:5779.41-5779.97" + cell $and $and$ls180.v:5779$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5727$1100_Y - connect \Y $and$ls180.v:5727$1101_Y + connect \B $not$ls180.v:5779$1100_Y + connect \Y $and$ls180.v:5779$1101_Y end - attribute \src "ls180.v:5727.40-5727.147" - cell $and $and$ls180.v:5727$1103 + attribute \src "ls180.v:5779.40-5779.147" + cell $and $and$ls180.v:5779$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5727$1101_Y - connect \B $eq$ls180.v:5727$1102_Y - connect \Y $and$ls180.v:5727$1103_Y + connect \A $and$ls180.v:5779$1101_Y + connect \B $eq$ls180.v:5779$1102_Y + connect \Y $and$ls180.v:5779$1103_Y end - attribute \src "ls180.v:5729.41-5729.94" - cell $and $and$ls180.v:5729$1104 + attribute \src "ls180.v:5781.41-5781.94" + cell $and $and$ls180.v:5781$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234502,43 +240019,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5729$1104_Y + connect \Y $and$ls180.v:5781$1104_Y end - attribute \src "ls180.v:5729.40-5729.144" - cell $and $and$ls180.v:5729$1106 + attribute \src "ls180.v:5781.40-5781.144" + cell $and $and$ls180.v:5781$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5729$1104_Y - connect \B $eq$ls180.v:5729$1105_Y - connect \Y $and$ls180.v:5729$1106_Y + connect \A $and$ls180.v:5781$1104_Y + connect \B $eq$ls180.v:5781$1105_Y + connect \Y $and$ls180.v:5781$1106_Y end - attribute \src "ls180.v:5730.41-5730.97" - cell $and $and$ls180.v:5730$1108 + attribute \src "ls180.v:5782.41-5782.97" + cell $and $and$ls180.v:5782$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5730$1107_Y - connect \Y $and$ls180.v:5730$1108_Y + connect \B $not$ls180.v:5782$1107_Y + connect \Y $and$ls180.v:5782$1108_Y end - attribute \src "ls180.v:5730.40-5730.147" - cell $and $and$ls180.v:5730$1110 + attribute \src "ls180.v:5782.40-5782.147" + cell $and $and$ls180.v:5782$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5730$1108_Y - connect \B $eq$ls180.v:5730$1109_Y - connect \Y $and$ls180.v:5730$1110_Y + connect \A $and$ls180.v:5782$1108_Y + connect \B $eq$ls180.v:5782$1109_Y + connect \Y $and$ls180.v:5782$1110_Y end - attribute \src "ls180.v:5732.41-5732.94" - cell $and $and$ls180.v:5732$1111 + attribute \src "ls180.v:5784.41-5784.94" + cell $and $and$ls180.v:5784$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234546,43 +240063,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5732$1111_Y + connect \Y $and$ls180.v:5784$1111_Y end - attribute \src "ls180.v:5732.40-5732.144" - cell $and $and$ls180.v:5732$1113 + attribute \src "ls180.v:5784.40-5784.144" + cell $and $and$ls180.v:5784$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5732$1111_Y - connect \B $eq$ls180.v:5732$1112_Y - connect \Y $and$ls180.v:5732$1113_Y + connect \A $and$ls180.v:5784$1111_Y + connect \B $eq$ls180.v:5784$1112_Y + connect \Y $and$ls180.v:5784$1113_Y end - attribute \src "ls180.v:5733.41-5733.97" - cell $and $and$ls180.v:5733$1115 + attribute \src "ls180.v:5785.41-5785.97" + cell $and $and$ls180.v:5785$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5733$1114_Y - connect \Y $and$ls180.v:5733$1115_Y + connect \B $not$ls180.v:5785$1114_Y + connect \Y $and$ls180.v:5785$1115_Y end - attribute \src "ls180.v:5733.40-5733.147" - cell $and $and$ls180.v:5733$1117 + attribute \src "ls180.v:5785.40-5785.147" + cell $and $and$ls180.v:5785$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5733$1115_Y - connect \B $eq$ls180.v:5733$1116_Y - connect \Y $and$ls180.v:5733$1117_Y + connect \A $and$ls180.v:5785$1115_Y + connect \B $eq$ls180.v:5785$1116_Y + connect \Y $and$ls180.v:5785$1117_Y end - attribute \src "ls180.v:5735.44-5735.97" - cell $and $and$ls180.v:5735$1118 + attribute \src "ls180.v:5787.44-5787.97" + cell $and $and$ls180.v:5787$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234590,43 +240107,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5735$1118_Y + connect \Y $and$ls180.v:5787$1118_Y end - attribute \src "ls180.v:5735.43-5735.147" - cell $and $and$ls180.v:5735$1120 + attribute \src "ls180.v:5787.43-5787.147" + cell $and $and$ls180.v:5787$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5735$1118_Y - connect \B $eq$ls180.v:5735$1119_Y - connect \Y $and$ls180.v:5735$1120_Y + connect \A $and$ls180.v:5787$1118_Y + connect \B $eq$ls180.v:5787$1119_Y + connect \Y $and$ls180.v:5787$1120_Y end - attribute \src "ls180.v:5736.44-5736.100" - cell $and $and$ls180.v:5736$1122 + attribute \src "ls180.v:5788.44-5788.100" + cell $and $and$ls180.v:5788$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5736$1121_Y - connect \Y $and$ls180.v:5736$1122_Y + connect \B $not$ls180.v:5788$1121_Y + connect \Y $and$ls180.v:5788$1122_Y end - attribute \src "ls180.v:5736.43-5736.150" - cell $and $and$ls180.v:5736$1124 + attribute \src "ls180.v:5788.43-5788.150" + cell $and $and$ls180.v:5788$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5736$1122_Y - connect \B $eq$ls180.v:5736$1123_Y - connect \Y $and$ls180.v:5736$1124_Y + connect \A $and$ls180.v:5788$1122_Y + connect \B $eq$ls180.v:5788$1123_Y + connect \Y $and$ls180.v:5788$1124_Y end - attribute \src "ls180.v:5738.44-5738.97" - cell $and $and$ls180.v:5738$1125 + attribute \src "ls180.v:5790.44-5790.97" + cell $and $and$ls180.v:5790$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234634,43 +240151,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5738$1125_Y + connect \Y $and$ls180.v:5790$1125_Y end - attribute \src "ls180.v:5738.43-5738.147" - cell $and $and$ls180.v:5738$1127 + attribute \src "ls180.v:5790.43-5790.147" + cell $and $and$ls180.v:5790$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5738$1125_Y - connect \B $eq$ls180.v:5738$1126_Y - connect \Y $and$ls180.v:5738$1127_Y + connect \A $and$ls180.v:5790$1125_Y + connect \B $eq$ls180.v:5790$1126_Y + connect \Y $and$ls180.v:5790$1127_Y end - attribute \src "ls180.v:5739.44-5739.100" - cell $and $and$ls180.v:5739$1129 + attribute \src "ls180.v:5791.44-5791.100" + cell $and $and$ls180.v:5791$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5739$1128_Y - connect \Y $and$ls180.v:5739$1129_Y + connect \B $not$ls180.v:5791$1128_Y + connect \Y $and$ls180.v:5791$1129_Y end - attribute \src "ls180.v:5739.43-5739.150" - cell $and $and$ls180.v:5739$1131 + attribute \src "ls180.v:5791.43-5791.150" + cell $and $and$ls180.v:5791$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5739$1129_Y - connect \B $eq$ls180.v:5739$1130_Y - connect \Y $and$ls180.v:5739$1131_Y + connect \A $and$ls180.v:5791$1129_Y + connect \B $eq$ls180.v:5791$1130_Y + connect \Y $and$ls180.v:5791$1131_Y end - attribute \src "ls180.v:5741.44-5741.97" - cell $and $and$ls180.v:5741$1132 + attribute \src "ls180.v:5793.44-5793.97" + cell $and $and$ls180.v:5793$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234678,43 +240195,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5741$1132_Y + connect \Y $and$ls180.v:5793$1132_Y end - attribute \src "ls180.v:5741.43-5741.147" - cell $and $and$ls180.v:5741$1134 + attribute \src "ls180.v:5793.43-5793.147" + cell $and $and$ls180.v:5793$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5741$1132_Y - connect \B $eq$ls180.v:5741$1133_Y - connect \Y $and$ls180.v:5741$1134_Y + connect \A $and$ls180.v:5793$1132_Y + connect \B $eq$ls180.v:5793$1133_Y + connect \Y $and$ls180.v:5793$1134_Y end - attribute \src "ls180.v:5742.44-5742.100" - cell $and $and$ls180.v:5742$1136 + attribute \src "ls180.v:5794.44-5794.100" + cell $and $and$ls180.v:5794$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5742$1135_Y - connect \Y $and$ls180.v:5742$1136_Y + connect \B $not$ls180.v:5794$1135_Y + connect \Y $and$ls180.v:5794$1136_Y end - attribute \src "ls180.v:5742.43-5742.150" - cell $and $and$ls180.v:5742$1138 + attribute \src "ls180.v:5794.43-5794.150" + cell $and $and$ls180.v:5794$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5742$1136_Y - connect \B $eq$ls180.v:5742$1137_Y - connect \Y $and$ls180.v:5742$1138_Y + connect \A $and$ls180.v:5794$1136_Y + connect \B $eq$ls180.v:5794$1137_Y + connect \Y $and$ls180.v:5794$1138_Y end - attribute \src "ls180.v:5744.44-5744.97" - cell $and $and$ls180.v:5744$1139 + attribute \src "ls180.v:5796.44-5796.97" + cell $and $and$ls180.v:5796$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234722,43 +240239,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5744$1139_Y + connect \Y $and$ls180.v:5796$1139_Y end - attribute \src "ls180.v:5744.43-5744.147" - cell $and $and$ls180.v:5744$1141 + attribute \src "ls180.v:5796.43-5796.147" + cell $and $and$ls180.v:5796$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5744$1139_Y - connect \B $eq$ls180.v:5744$1140_Y - connect \Y $and$ls180.v:5744$1141_Y + connect \A $and$ls180.v:5796$1139_Y + connect \B $eq$ls180.v:5796$1140_Y + connect \Y $and$ls180.v:5796$1141_Y end - attribute \src "ls180.v:5745.44-5745.100" - cell $and $and$ls180.v:5745$1143 + attribute \src "ls180.v:5797.44-5797.100" + cell $and $and$ls180.v:5797$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5745$1142_Y - connect \Y $and$ls180.v:5745$1143_Y + connect \B $not$ls180.v:5797$1142_Y + connect \Y $and$ls180.v:5797$1143_Y end - attribute \src "ls180.v:5745.43-5745.150" - cell $and $and$ls180.v:5745$1145 + attribute \src "ls180.v:5797.43-5797.150" + cell $and $and$ls180.v:5797$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5745$1143_Y - connect \B $eq$ls180.v:5745$1144_Y - connect \Y $and$ls180.v:5745$1145_Y + connect \A $and$ls180.v:5797$1143_Y + connect \B $eq$ls180.v:5797$1144_Y + connect \Y $and$ls180.v:5797$1145_Y end - attribute \src "ls180.v:5758.36-5758.89" - cell $and $and$ls180.v:5758$1147 + attribute \src "ls180.v:5810.36-5810.89" + cell $and $and$ls180.v:5810$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234766,43 +240283,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5758$1147_Y + connect \Y $and$ls180.v:5810$1147_Y end - attribute \src "ls180.v:5758.35-5758.139" - cell $and $and$ls180.v:5758$1149 + attribute \src "ls180.v:5810.35-5810.139" + cell $and $and$ls180.v:5810$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5758$1147_Y - connect \B $eq$ls180.v:5758$1148_Y - connect \Y $and$ls180.v:5758$1149_Y + connect \A $and$ls180.v:5810$1147_Y + connect \B $eq$ls180.v:5810$1148_Y + connect \Y $and$ls180.v:5810$1149_Y end - attribute \src "ls180.v:5759.36-5759.92" - cell $and $and$ls180.v:5759$1151 + attribute \src "ls180.v:5811.36-5811.92" + cell $and $and$ls180.v:5811$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5759$1150_Y - connect \Y $and$ls180.v:5759$1151_Y + connect \B $not$ls180.v:5811$1150_Y + connect \Y $and$ls180.v:5811$1151_Y end - attribute \src "ls180.v:5759.35-5759.142" - cell $and $and$ls180.v:5759$1153 + attribute \src "ls180.v:5811.35-5811.142" + cell $and $and$ls180.v:5811$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5759$1151_Y - connect \B $eq$ls180.v:5759$1152_Y - connect \Y $and$ls180.v:5759$1153_Y + connect \A $and$ls180.v:5811$1151_Y + connect \B $eq$ls180.v:5811$1152_Y + connect \Y $and$ls180.v:5811$1153_Y end - attribute \src "ls180.v:5761.36-5761.89" - cell $and $and$ls180.v:5761$1154 + attribute \src "ls180.v:5813.36-5813.89" + cell $and $and$ls180.v:5813$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234810,43 +240327,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5761$1154_Y + connect \Y $and$ls180.v:5813$1154_Y end - attribute \src "ls180.v:5761.35-5761.139" - cell $and $and$ls180.v:5761$1156 + attribute \src "ls180.v:5813.35-5813.139" + cell $and $and$ls180.v:5813$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5761$1154_Y - connect \B $eq$ls180.v:5761$1155_Y - connect \Y $and$ls180.v:5761$1156_Y + connect \A $and$ls180.v:5813$1154_Y + connect \B $eq$ls180.v:5813$1155_Y + connect \Y $and$ls180.v:5813$1156_Y end - attribute \src "ls180.v:5762.36-5762.92" - cell $and $and$ls180.v:5762$1158 + attribute \src "ls180.v:5814.36-5814.92" + cell $and $and$ls180.v:5814$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5762$1157_Y - connect \Y $and$ls180.v:5762$1158_Y + connect \B $not$ls180.v:5814$1157_Y + connect \Y $and$ls180.v:5814$1158_Y end - attribute \src "ls180.v:5762.35-5762.142" - cell $and $and$ls180.v:5762$1160 + attribute \src "ls180.v:5814.35-5814.142" + cell $and $and$ls180.v:5814$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5762$1158_Y - connect \B $eq$ls180.v:5762$1159_Y - connect \Y $and$ls180.v:5762$1160_Y + connect \A $and$ls180.v:5814$1158_Y + connect \B $eq$ls180.v:5814$1159_Y + connect \Y $and$ls180.v:5814$1160_Y end - attribute \src "ls180.v:5764.36-5764.89" - cell $and $and$ls180.v:5764$1161 + attribute \src "ls180.v:5816.36-5816.89" + cell $and $and$ls180.v:5816$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234854,43 +240371,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5764$1161_Y + connect \Y $and$ls180.v:5816$1161_Y end - attribute \src "ls180.v:5764.35-5764.139" - cell $and $and$ls180.v:5764$1163 + attribute \src "ls180.v:5816.35-5816.139" + cell $and $and$ls180.v:5816$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5764$1161_Y - connect \B $eq$ls180.v:5764$1162_Y - connect \Y $and$ls180.v:5764$1163_Y + connect \A $and$ls180.v:5816$1161_Y + connect \B $eq$ls180.v:5816$1162_Y + connect \Y $and$ls180.v:5816$1163_Y end - attribute \src "ls180.v:5765.36-5765.92" - cell $and $and$ls180.v:5765$1165 + attribute \src "ls180.v:5817.36-5817.92" + cell $and $and$ls180.v:5817$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5765$1164_Y - connect \Y $and$ls180.v:5765$1165_Y + connect \B $not$ls180.v:5817$1164_Y + connect \Y $and$ls180.v:5817$1165_Y end - attribute \src "ls180.v:5765.35-5765.142" - cell $and $and$ls180.v:5765$1167 + attribute \src "ls180.v:5817.35-5817.142" + cell $and $and$ls180.v:5817$1167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5765$1165_Y - connect \B $eq$ls180.v:5765$1166_Y - connect \Y $and$ls180.v:5765$1167_Y + connect \A $and$ls180.v:5817$1165_Y + connect \B $eq$ls180.v:5817$1166_Y + connect \Y $and$ls180.v:5817$1167_Y end - attribute \src "ls180.v:5767.36-5767.89" - cell $and $and$ls180.v:5767$1168 + attribute \src "ls180.v:5819.36-5819.89" + cell $and $and$ls180.v:5819$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234898,43 +240415,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5767$1168_Y + connect \Y $and$ls180.v:5819$1168_Y end - attribute \src "ls180.v:5767.35-5767.139" - cell $and $and$ls180.v:5767$1170 + attribute \src "ls180.v:5819.35-5819.139" + cell $and $and$ls180.v:5819$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5767$1168_Y - connect \B $eq$ls180.v:5767$1169_Y - connect \Y $and$ls180.v:5767$1170_Y + connect \A $and$ls180.v:5819$1168_Y + connect \B $eq$ls180.v:5819$1169_Y + connect \Y $and$ls180.v:5819$1170_Y end - attribute \src "ls180.v:5768.36-5768.92" - cell $and $and$ls180.v:5768$1172 + attribute \src "ls180.v:5820.36-5820.92" + cell $and $and$ls180.v:5820$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5768$1171_Y - connect \Y $and$ls180.v:5768$1172_Y + connect \B $not$ls180.v:5820$1171_Y + connect \Y $and$ls180.v:5820$1172_Y end - attribute \src "ls180.v:5768.35-5768.142" - cell $and $and$ls180.v:5768$1174 + attribute \src "ls180.v:5820.35-5820.142" + cell $and $and$ls180.v:5820$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5768$1172_Y - connect \B $eq$ls180.v:5768$1173_Y - connect \Y $and$ls180.v:5768$1174_Y + connect \A $and$ls180.v:5820$1172_Y + connect \B $eq$ls180.v:5820$1173_Y + connect \Y $and$ls180.v:5820$1174_Y end - attribute \src "ls180.v:5770.37-5770.90" - cell $and $and$ls180.v:5770$1175 + attribute \src "ls180.v:5822.37-5822.90" + cell $and $and$ls180.v:5822$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234942,43 +240459,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5770$1175_Y + connect \Y $and$ls180.v:5822$1175_Y end - attribute \src "ls180.v:5770.36-5770.140" - cell $and $and$ls180.v:5770$1177 + attribute \src "ls180.v:5822.36-5822.140" + cell $and $and$ls180.v:5822$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5770$1175_Y - connect \B $eq$ls180.v:5770$1176_Y - connect \Y $and$ls180.v:5770$1177_Y + connect \A $and$ls180.v:5822$1175_Y + connect \B $eq$ls180.v:5822$1176_Y + connect \Y $and$ls180.v:5822$1177_Y end - attribute \src "ls180.v:5771.37-5771.93" - cell $and $and$ls180.v:5771$1179 + attribute \src "ls180.v:5823.37-5823.93" + cell $and $and$ls180.v:5823$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5771$1178_Y - connect \Y $and$ls180.v:5771$1179_Y + connect \B $not$ls180.v:5823$1178_Y + connect \Y $and$ls180.v:5823$1179_Y end - attribute \src "ls180.v:5771.36-5771.143" - cell $and $and$ls180.v:5771$1181 + attribute \src "ls180.v:5823.36-5823.143" + cell $and $and$ls180.v:5823$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5771$1179_Y - connect \B $eq$ls180.v:5771$1180_Y - connect \Y $and$ls180.v:5771$1181_Y + connect \A $and$ls180.v:5823$1179_Y + connect \B $eq$ls180.v:5823$1180_Y + connect \Y $and$ls180.v:5823$1181_Y end - attribute \src "ls180.v:5773.37-5773.90" - cell $and $and$ls180.v:5773$1182 + attribute \src "ls180.v:5825.37-5825.90" + cell $and $and$ls180.v:5825$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -234986,87 +240503,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5773$1182_Y + connect \Y $and$ls180.v:5825$1182_Y end - attribute \src "ls180.v:5773.36-5773.140" - cell $and $and$ls180.v:5773$1184 + attribute \src "ls180.v:5825.36-5825.140" + cell $and $and$ls180.v:5825$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5773$1182_Y - connect \B $eq$ls180.v:5773$1183_Y - connect \Y $and$ls180.v:5773$1184_Y + connect \A $and$ls180.v:5825$1182_Y + connect \B $eq$ls180.v:5825$1183_Y + connect \Y $and$ls180.v:5825$1184_Y end - attribute \src "ls180.v:5774.37-5774.93" - cell $and $and$ls180.v:5774$1186 + attribute \src "ls180.v:5826.37-5826.93" + cell $and $and$ls180.v:5826$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5774$1185_Y - connect \Y $and$ls180.v:5774$1186_Y - end - attribute \src "ls180.v:5774.36-5774.143" - cell $and $and$ls180.v:5774$1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5774$1186_Y - connect \B $eq$ls180.v:5774$1187_Y - connect \Y $and$ls180.v:5774$1188_Y - end - attribute \src "ls180.v:5784.40-5784.93" - cell $and $and$ls180.v:5784$1190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5784$1190_Y - end - attribute \src "ls180.v:5784.39-5784.143" - cell $and $and$ls180.v:5784$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5784$1190_Y - connect \B $eq$ls180.v:5784$1191_Y - connect \Y $and$ls180.v:5784$1192_Y + connect \B $not$ls180.v:5826$1185_Y + connect \Y $and$ls180.v:5826$1186_Y end - attribute \src "ls180.v:5785.40-5785.96" - cell $and $and$ls180.v:5785$1194 + attribute \src "ls180.v:5826.36-5826.143" + cell $and $and$ls180.v:5826$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5785$1193_Y - connect \Y $and$ls180.v:5785$1194_Y - end - attribute \src "ls180.v:5785.39-5785.146" - cell $and $and$ls180.v:5785$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5785$1194_Y - connect \B $eq$ls180.v:5785$1195_Y - connect \Y $and$ls180.v:5785$1196_Y + connect \A $and$ls180.v:5826$1186_Y + connect \B $eq$ls180.v:5826$1187_Y + connect \Y $and$ls180.v:5826$1188_Y end - attribute \src "ls180.v:5787.39-5787.92" - cell $and $and$ls180.v:5787$1197 + attribute \src "ls180.v:5836.35-5836.88" + cell $and $and$ls180.v:5836$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235074,43 +240547,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5787$1197_Y + connect \Y $and$ls180.v:5836$1190_Y end - attribute \src "ls180.v:5787.38-5787.142" - cell $and $and$ls180.v:5787$1199 + attribute \src "ls180.v:5836.34-5836.136" + cell $and $and$ls180.v:5836$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5787$1197_Y - connect \B $eq$ls180.v:5787$1198_Y - connect \Y $and$ls180.v:5787$1199_Y + connect \A $and$ls180.v:5836$1190_Y + connect \B $eq$ls180.v:5836$1191_Y + connect \Y $and$ls180.v:5836$1192_Y end - attribute \src "ls180.v:5788.39-5788.95" - cell $and $and$ls180.v:5788$1201 + attribute \src "ls180.v:5837.35-5837.91" + cell $and $and$ls180.v:5837$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5788$1200_Y - connect \Y $and$ls180.v:5788$1201_Y + connect \B $not$ls180.v:5837$1193_Y + connect \Y $and$ls180.v:5837$1194_Y end - attribute \src "ls180.v:5788.38-5788.145" - cell $and $and$ls180.v:5788$1203 + attribute \src "ls180.v:5837.34-5837.139" + cell $and $and$ls180.v:5837$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5788$1201_Y - connect \B $eq$ls180.v:5788$1202_Y - connect \Y $and$ls180.v:5788$1203_Y + connect \A $and$ls180.v:5837$1194_Y + connect \B $eq$ls180.v:5837$1195_Y + connect \Y $and$ls180.v:5837$1196_Y end - attribute \src "ls180.v:5790.39-5790.92" - cell $and $and$ls180.v:5790$1204 + attribute \src "ls180.v:5839.34-5839.87" + cell $and $and$ls180.v:5839$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235118,307 +240591,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5790$1204_Y - end - attribute \src "ls180.v:5790.38-5790.142" - cell $and $and$ls180.v:5790$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5790$1204_Y - connect \B $eq$ls180.v:5790$1205_Y - connect \Y $and$ls180.v:5790$1206_Y - end - attribute \src "ls180.v:5791.39-5791.95" - cell $and $and$ls180.v:5791$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5791$1207_Y - connect \Y $and$ls180.v:5791$1208_Y + connect \Y $and$ls180.v:5839$1197_Y end - attribute \src "ls180.v:5791.38-5791.145" - cell $and $and$ls180.v:5791$1210 + attribute \src "ls180.v:5839.33-5839.135" + cell $and $and$ls180.v:5839$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5791$1208_Y - connect \B $eq$ls180.v:5791$1209_Y - connect \Y $and$ls180.v:5791$1210_Y + connect \A $and$ls180.v:5839$1197_Y + connect \B $eq$ls180.v:5839$1198_Y + connect \Y $and$ls180.v:5839$1199_Y end - attribute \src "ls180.v:5793.39-5793.92" - cell $and $and$ls180.v:5793$1211 + attribute \src "ls180.v:5840.34-5840.90" + cell $and $and$ls180.v:5840$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5793$1211_Y - end - attribute \src "ls180.v:5793.38-5793.142" - cell $and $and$ls180.v:5793$1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5793$1211_Y - connect \B $eq$ls180.v:5793$1212_Y - connect \Y $and$ls180.v:5793$1213_Y + connect \B $not$ls180.v:5840$1200_Y + connect \Y $and$ls180.v:5840$1201_Y end - attribute \src "ls180.v:5794.39-5794.95" - cell $and $and$ls180.v:5794$1215 + attribute \src "ls180.v:5840.33-5840.138" + cell $and $and$ls180.v:5840$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5794$1214_Y - connect \Y $and$ls180.v:5794$1215_Y + connect \A $and$ls180.v:5840$1201_Y + connect \B $eq$ls180.v:5840$1202_Y + connect \Y $and$ls180.v:5840$1203_Y end - attribute \src "ls180.v:5794.38-5794.145" - cell $and $and$ls180.v:5794$1217 + attribute \src "ls180.v:5850.40-5850.93" + cell $and $and$ls180.v:5850$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5794$1215_Y - connect \B $eq$ls180.v:5794$1216_Y - connect \Y $and$ls180.v:5794$1217_Y - end - attribute \src "ls180.v:5796.39-5796.92" - cell $and $and$ls180.v:5796$1218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5796$1218_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5850$1205_Y end - attribute \src "ls180.v:5796.38-5796.142" - cell $and $and$ls180.v:5796$1220 + attribute \src "ls180.v:5850.39-5850.143" + cell $and $and$ls180.v:5850$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5796$1218_Y - connect \B $eq$ls180.v:5796$1219_Y - connect \Y $and$ls180.v:5796$1220_Y + connect \A $and$ls180.v:5850$1205_Y + connect \B $eq$ls180.v:5850$1206_Y + connect \Y $and$ls180.v:5850$1207_Y end - attribute \src "ls180.v:5797.39-5797.95" - cell $and $and$ls180.v:5797$1222 + attribute \src "ls180.v:5851.40-5851.96" + cell $and $and$ls180.v:5851$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5797$1221_Y - connect \Y $and$ls180.v:5797$1222_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5851$1208_Y + connect \Y $and$ls180.v:5851$1209_Y end - attribute \src "ls180.v:5797.38-5797.145" - cell $and $and$ls180.v:5797$1224 + attribute \src "ls180.v:5851.39-5851.146" + cell $and $and$ls180.v:5851$1211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5797$1222_Y - connect \B $eq$ls180.v:5797$1223_Y - connect \Y $and$ls180.v:5797$1224_Y + connect \A $and$ls180.v:5851$1209_Y + connect \B $eq$ls180.v:5851$1210_Y + connect \Y $and$ls180.v:5851$1211_Y end - attribute \src "ls180.v:5799.40-5799.93" - cell $and $and$ls180.v:5799$1225 + attribute \src "ls180.v:5853.39-5853.92" + cell $and $and$ls180.v:5853$1212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5799$1225_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5853$1212_Y end - attribute \src "ls180.v:5799.39-5799.143" - cell $and $and$ls180.v:5799$1227 + attribute \src "ls180.v:5853.38-5853.142" + cell $and $and$ls180.v:5853$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5799$1225_Y - connect \B $eq$ls180.v:5799$1226_Y - connect \Y $and$ls180.v:5799$1227_Y + connect \A $and$ls180.v:5853$1212_Y + connect \B $eq$ls180.v:5853$1213_Y + connect \Y $and$ls180.v:5853$1214_Y end - attribute \src "ls180.v:5800.40-5800.96" - cell $and $and$ls180.v:5800$1229 + attribute \src "ls180.v:5854.39-5854.95" + cell $and $and$ls180.v:5854$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5800$1228_Y - connect \Y $and$ls180.v:5800$1229_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5854$1215_Y + connect \Y $and$ls180.v:5854$1216_Y end - attribute \src "ls180.v:5800.39-5800.146" - cell $and $and$ls180.v:5800$1231 + attribute \src "ls180.v:5854.38-5854.145" + cell $and $and$ls180.v:5854$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5800$1229_Y - connect \B $eq$ls180.v:5800$1230_Y - connect \Y $and$ls180.v:5800$1231_Y + connect \A $and$ls180.v:5854$1216_Y + connect \B $eq$ls180.v:5854$1217_Y + connect \Y $and$ls180.v:5854$1218_Y end - attribute \src "ls180.v:5802.40-5802.93" - cell $and $and$ls180.v:5802$1232 + attribute \src "ls180.v:5856.39-5856.92" + cell $and $and$ls180.v:5856$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5802$1232_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5856$1219_Y end - attribute \src "ls180.v:5802.39-5802.143" - cell $and $and$ls180.v:5802$1234 + attribute \src "ls180.v:5856.38-5856.142" + cell $and $and$ls180.v:5856$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5802$1232_Y - connect \B $eq$ls180.v:5802$1233_Y - connect \Y $and$ls180.v:5802$1234_Y + connect \A $and$ls180.v:5856$1219_Y + connect \B $eq$ls180.v:5856$1220_Y + connect \Y $and$ls180.v:5856$1221_Y end - attribute \src "ls180.v:5803.40-5803.96" - cell $and $and$ls180.v:5803$1236 + attribute \src "ls180.v:5857.39-5857.95" + cell $and $and$ls180.v:5857$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5803$1235_Y - connect \Y $and$ls180.v:5803$1236_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5857$1222_Y + connect \Y $and$ls180.v:5857$1223_Y end - attribute \src "ls180.v:5803.39-5803.146" - cell $and $and$ls180.v:5803$1238 + attribute \src "ls180.v:5857.38-5857.145" + cell $and $and$ls180.v:5857$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5803$1236_Y - connect \B $eq$ls180.v:5803$1237_Y - connect \Y $and$ls180.v:5803$1238_Y + connect \A $and$ls180.v:5857$1223_Y + connect \B $eq$ls180.v:5857$1224_Y + connect \Y $and$ls180.v:5857$1225_Y end - attribute \src "ls180.v:5805.40-5805.93" - cell $and $and$ls180.v:5805$1239 + attribute \src "ls180.v:5859.39-5859.92" + cell $and $and$ls180.v:5859$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5805$1239_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5859$1226_Y end - attribute \src "ls180.v:5805.39-5805.143" - cell $and $and$ls180.v:5805$1241 + attribute \src "ls180.v:5859.38-5859.142" + cell $and $and$ls180.v:5859$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5805$1239_Y - connect \B $eq$ls180.v:5805$1240_Y - connect \Y $and$ls180.v:5805$1241_Y + connect \A $and$ls180.v:5859$1226_Y + connect \B $eq$ls180.v:5859$1227_Y + connect \Y $and$ls180.v:5859$1228_Y end - attribute \src "ls180.v:5806.40-5806.96" - cell $and $and$ls180.v:5806$1243 + attribute \src "ls180.v:5860.39-5860.95" + cell $and $and$ls180.v:5860$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5806$1242_Y - connect \Y $and$ls180.v:5806$1243_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5860$1229_Y + connect \Y $and$ls180.v:5860$1230_Y end - attribute \src "ls180.v:5806.39-5806.146" - cell $and $and$ls180.v:5806$1245 + attribute \src "ls180.v:5860.38-5860.145" + cell $and $and$ls180.v:5860$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5806$1243_Y - connect \B $eq$ls180.v:5806$1244_Y - connect \Y $and$ls180.v:5806$1245_Y + connect \A $and$ls180.v:5860$1230_Y + connect \B $eq$ls180.v:5860$1231_Y + connect \Y $and$ls180.v:5860$1232_Y end - attribute \src "ls180.v:5808.40-5808.93" - cell $and $and$ls180.v:5808$1246 + attribute \src "ls180.v:5862.39-5862.92" + cell $and $and$ls180.v:5862$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5808$1246_Y + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5862$1233_Y end - attribute \src "ls180.v:5808.39-5808.143" - cell $and $and$ls180.v:5808$1248 + attribute \src "ls180.v:5862.38-5862.142" + cell $and $and$ls180.v:5862$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5808$1246_Y - connect \B $eq$ls180.v:5808$1247_Y - connect \Y $and$ls180.v:5808$1248_Y + connect \A $and$ls180.v:5862$1233_Y + connect \B $eq$ls180.v:5862$1234_Y + connect \Y $and$ls180.v:5862$1235_Y end - attribute \src "ls180.v:5809.40-5809.96" - cell $and $and$ls180.v:5809$1250 + attribute \src "ls180.v:5863.39-5863.95" + cell $and $and$ls180.v:5863$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5809$1249_Y - connect \Y $and$ls180.v:5809$1250_Y + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5863$1236_Y + connect \Y $and$ls180.v:5863$1237_Y end - attribute \src "ls180.v:5809.39-5809.146" - cell $and $and$ls180.v:5809$1252 + attribute \src "ls180.v:5863.38-5863.145" + cell $and $and$ls180.v:5863$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5809$1250_Y - connect \B $eq$ls180.v:5809$1251_Y - connect \Y $and$ls180.v:5809$1252_Y + connect \A $and$ls180.v:5863$1237_Y + connect \B $eq$ls180.v:5863$1238_Y + connect \Y $and$ls180.v:5863$1239_Y end - attribute \src "ls180.v:5821.40-5821.93" - cell $and $and$ls180.v:5821$1254 + attribute \src "ls180.v:5865.40-5865.93" + cell $and $and$ls180.v:5865$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235426,43 +240855,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5821$1254_Y + connect \Y $and$ls180.v:5865$1240_Y end - attribute \src "ls180.v:5821.39-5821.143" - cell $and $and$ls180.v:5821$1256 + attribute \src "ls180.v:5865.39-5865.143" + cell $and $and$ls180.v:5865$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5821$1254_Y - connect \B $eq$ls180.v:5821$1255_Y - connect \Y $and$ls180.v:5821$1256_Y + connect \A $and$ls180.v:5865$1240_Y + connect \B $eq$ls180.v:5865$1241_Y + connect \Y $and$ls180.v:5865$1242_Y end - attribute \src "ls180.v:5822.40-5822.96" - cell $and $and$ls180.v:5822$1258 + attribute \src "ls180.v:5866.40-5866.96" + cell $and $and$ls180.v:5866$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5822$1257_Y - connect \Y $and$ls180.v:5822$1258_Y + connect \B $not$ls180.v:5866$1243_Y + connect \Y $and$ls180.v:5866$1244_Y end - attribute \src "ls180.v:5822.39-5822.146" - cell $and $and$ls180.v:5822$1260 + attribute \src "ls180.v:5866.39-5866.146" + cell $and $and$ls180.v:5866$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5822$1258_Y - connect \B $eq$ls180.v:5822$1259_Y - connect \Y $and$ls180.v:5822$1260_Y + connect \A $and$ls180.v:5866$1244_Y + connect \B $eq$ls180.v:5866$1245_Y + connect \Y $and$ls180.v:5866$1246_Y end - attribute \src "ls180.v:5824.39-5824.92" - cell $and $and$ls180.v:5824$1261 + attribute \src "ls180.v:5868.40-5868.93" + cell $and $and$ls180.v:5868$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235470,43 +240899,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5824$1261_Y + connect \Y $and$ls180.v:5868$1247_Y end - attribute \src "ls180.v:5824.38-5824.142" - cell $and $and$ls180.v:5824$1263 + attribute \src "ls180.v:5868.39-5868.143" + cell $and $and$ls180.v:5868$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5824$1261_Y - connect \B $eq$ls180.v:5824$1262_Y - connect \Y $and$ls180.v:5824$1263_Y + connect \A $and$ls180.v:5868$1247_Y + connect \B $eq$ls180.v:5868$1248_Y + connect \Y $and$ls180.v:5868$1249_Y end - attribute \src "ls180.v:5825.39-5825.95" - cell $and $and$ls180.v:5825$1265 + attribute \src "ls180.v:5869.40-5869.96" + cell $and $and$ls180.v:5869$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5825$1264_Y - connect \Y $and$ls180.v:5825$1265_Y + connect \B $not$ls180.v:5869$1250_Y + connect \Y $and$ls180.v:5869$1251_Y end - attribute \src "ls180.v:5825.38-5825.145" - cell $and $and$ls180.v:5825$1267 + attribute \src "ls180.v:5869.39-5869.146" + cell $and $and$ls180.v:5869$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5825$1265_Y - connect \B $eq$ls180.v:5825$1266_Y - connect \Y $and$ls180.v:5825$1267_Y + connect \A $and$ls180.v:5869$1251_Y + connect \B $eq$ls180.v:5869$1252_Y + connect \Y $and$ls180.v:5869$1253_Y end - attribute \src "ls180.v:5827.39-5827.92" - cell $and $and$ls180.v:5827$1268 + attribute \src "ls180.v:5871.40-5871.93" + cell $and $and$ls180.v:5871$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235514,43 +240943,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5827$1268_Y + connect \Y $and$ls180.v:5871$1254_Y end - attribute \src "ls180.v:5827.38-5827.142" - cell $and $and$ls180.v:5827$1270 + attribute \src "ls180.v:5871.39-5871.143" + cell $and $and$ls180.v:5871$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5827$1268_Y - connect \B $eq$ls180.v:5827$1269_Y - connect \Y $and$ls180.v:5827$1270_Y + connect \A $and$ls180.v:5871$1254_Y + connect \B $eq$ls180.v:5871$1255_Y + connect \Y $and$ls180.v:5871$1256_Y end - attribute \src "ls180.v:5828.39-5828.95" - cell $and $and$ls180.v:5828$1272 + attribute \src "ls180.v:5872.40-5872.96" + cell $and $and$ls180.v:5872$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5828$1271_Y - connect \Y $and$ls180.v:5828$1272_Y + connect \B $not$ls180.v:5872$1257_Y + connect \Y $and$ls180.v:5872$1258_Y end - attribute \src "ls180.v:5828.38-5828.145" - cell $and $and$ls180.v:5828$1274 + attribute \src "ls180.v:5872.39-5872.146" + cell $and $and$ls180.v:5872$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5828$1272_Y - connect \B $eq$ls180.v:5828$1273_Y - connect \Y $and$ls180.v:5828$1274_Y + connect \A $and$ls180.v:5872$1258_Y + connect \B $eq$ls180.v:5872$1259_Y + connect \Y $and$ls180.v:5872$1260_Y end - attribute \src "ls180.v:5830.39-5830.92" - cell $and $and$ls180.v:5830$1275 + attribute \src "ls180.v:5874.40-5874.93" + cell $and $and$ls180.v:5874$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235558,263 +240987,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5830$1275_Y + connect \Y $and$ls180.v:5874$1261_Y end - attribute \src "ls180.v:5830.38-5830.142" - cell $and $and$ls180.v:5830$1277 + attribute \src "ls180.v:5874.39-5874.143" + cell $and $and$ls180.v:5874$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5830$1275_Y - connect \B $eq$ls180.v:5830$1276_Y - connect \Y $and$ls180.v:5830$1277_Y + connect \A $and$ls180.v:5874$1261_Y + connect \B $eq$ls180.v:5874$1262_Y + connect \Y $and$ls180.v:5874$1263_Y end - attribute \src "ls180.v:5831.39-5831.95" - cell $and $and$ls180.v:5831$1279 + attribute \src "ls180.v:5875.40-5875.96" + cell $and $and$ls180.v:5875$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5831$1278_Y - connect \Y $and$ls180.v:5831$1279_Y + connect \B $not$ls180.v:5875$1264_Y + connect \Y $and$ls180.v:5875$1265_Y end - attribute \src "ls180.v:5831.38-5831.145" - cell $and $and$ls180.v:5831$1281 + attribute \src "ls180.v:5875.39-5875.146" + cell $and $and$ls180.v:5875$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5831$1279_Y - connect \B $eq$ls180.v:5831$1280_Y - connect \Y $and$ls180.v:5831$1281_Y + connect \A $and$ls180.v:5875$1265_Y + connect \B $eq$ls180.v:5875$1266_Y + connect \Y $and$ls180.v:5875$1267_Y end - attribute \src "ls180.v:5833.39-5833.92" - cell $and $and$ls180.v:5833$1282 + attribute \src "ls180.v:5887.40-5887.93" + cell $and $and$ls180.v:5887$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5833$1282_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5887$1269_Y end - attribute \src "ls180.v:5833.38-5833.142" - cell $and $and$ls180.v:5833$1284 + attribute \src "ls180.v:5887.39-5887.143" + cell $and $and$ls180.v:5887$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5833$1282_Y - connect \B $eq$ls180.v:5833$1283_Y - connect \Y $and$ls180.v:5833$1284_Y + connect \A $and$ls180.v:5887$1269_Y + connect \B $eq$ls180.v:5887$1270_Y + connect \Y $and$ls180.v:5887$1271_Y end - attribute \src "ls180.v:5834.39-5834.95" - cell $and $and$ls180.v:5834$1286 + attribute \src "ls180.v:5888.40-5888.96" + cell $and $and$ls180.v:5888$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5834$1285_Y - connect \Y $and$ls180.v:5834$1286_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5888$1272_Y + connect \Y $and$ls180.v:5888$1273_Y end - attribute \src "ls180.v:5834.38-5834.145" - cell $and $and$ls180.v:5834$1288 + attribute \src "ls180.v:5888.39-5888.146" + cell $and $and$ls180.v:5888$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5834$1286_Y - connect \B $eq$ls180.v:5834$1287_Y - connect \Y $and$ls180.v:5834$1288_Y + connect \A $and$ls180.v:5888$1273_Y + connect \B $eq$ls180.v:5888$1274_Y + connect \Y $and$ls180.v:5888$1275_Y end - attribute \src "ls180.v:5836.40-5836.93" - cell $and $and$ls180.v:5836$1289 + attribute \src "ls180.v:5890.39-5890.92" + cell $and $and$ls180.v:5890$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5836$1289_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5890$1276_Y end - attribute \src "ls180.v:5836.39-5836.143" - cell $and $and$ls180.v:5836$1291 + attribute \src "ls180.v:5890.38-5890.142" + cell $and $and$ls180.v:5890$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5836$1289_Y - connect \B $eq$ls180.v:5836$1290_Y - connect \Y $and$ls180.v:5836$1291_Y + connect \A $and$ls180.v:5890$1276_Y + connect \B $eq$ls180.v:5890$1277_Y + connect \Y $and$ls180.v:5890$1278_Y end - attribute \src "ls180.v:5837.40-5837.96" - cell $and $and$ls180.v:5837$1293 + attribute \src "ls180.v:5891.39-5891.95" + cell $and $and$ls180.v:5891$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5837$1292_Y - connect \Y $and$ls180.v:5837$1293_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5891$1279_Y + connect \Y $and$ls180.v:5891$1280_Y end - attribute \src "ls180.v:5837.39-5837.146" - cell $and $and$ls180.v:5837$1295 + attribute \src "ls180.v:5891.38-5891.145" + cell $and $and$ls180.v:5891$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5837$1293_Y - connect \B $eq$ls180.v:5837$1294_Y - connect \Y $and$ls180.v:5837$1295_Y + connect \A $and$ls180.v:5891$1280_Y + connect \B $eq$ls180.v:5891$1281_Y + connect \Y $and$ls180.v:5891$1282_Y end - attribute \src "ls180.v:5839.40-5839.93" - cell $and $and$ls180.v:5839$1296 + attribute \src "ls180.v:5893.39-5893.92" + cell $and $and$ls180.v:5893$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5839$1296_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5893$1283_Y end - attribute \src "ls180.v:5839.39-5839.143" - cell $and $and$ls180.v:5839$1298 + attribute \src "ls180.v:5893.38-5893.142" + cell $and $and$ls180.v:5893$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5839$1296_Y - connect \B $eq$ls180.v:5839$1297_Y - connect \Y $and$ls180.v:5839$1298_Y + connect \A $and$ls180.v:5893$1283_Y + connect \B $eq$ls180.v:5893$1284_Y + connect \Y $and$ls180.v:5893$1285_Y end - attribute \src "ls180.v:5840.40-5840.96" - cell $and $and$ls180.v:5840$1300 + attribute \src "ls180.v:5894.39-5894.95" + cell $and $and$ls180.v:5894$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5840$1299_Y - connect \Y $and$ls180.v:5840$1300_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5894$1286_Y + connect \Y $and$ls180.v:5894$1287_Y end - attribute \src "ls180.v:5840.39-5840.146" - cell $and $and$ls180.v:5840$1302 + attribute \src "ls180.v:5894.38-5894.145" + cell $and $and$ls180.v:5894$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5840$1300_Y - connect \B $eq$ls180.v:5840$1301_Y - connect \Y $and$ls180.v:5840$1302_Y + connect \A $and$ls180.v:5894$1287_Y + connect \B $eq$ls180.v:5894$1288_Y + connect \Y $and$ls180.v:5894$1289_Y end - attribute \src "ls180.v:5842.40-5842.93" - cell $and $and$ls180.v:5842$1303 + attribute \src "ls180.v:5896.39-5896.92" + cell $and $and$ls180.v:5896$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5842$1303_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5896$1290_Y end - attribute \src "ls180.v:5842.39-5842.143" - cell $and $and$ls180.v:5842$1305 + attribute \src "ls180.v:5896.38-5896.142" + cell $and $and$ls180.v:5896$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5842$1303_Y - connect \B $eq$ls180.v:5842$1304_Y - connect \Y $and$ls180.v:5842$1305_Y + connect \A $and$ls180.v:5896$1290_Y + connect \B $eq$ls180.v:5896$1291_Y + connect \Y $and$ls180.v:5896$1292_Y end - attribute \src "ls180.v:5843.40-5843.96" - cell $and $and$ls180.v:5843$1307 + attribute \src "ls180.v:5897.39-5897.95" + cell $and $and$ls180.v:5897$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5843$1306_Y - connect \Y $and$ls180.v:5843$1307_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5897$1293_Y + connect \Y $and$ls180.v:5897$1294_Y end - attribute \src "ls180.v:5843.39-5843.146" - cell $and $and$ls180.v:5843$1309 + attribute \src "ls180.v:5897.38-5897.145" + cell $and $and$ls180.v:5897$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5843$1307_Y - connect \B $eq$ls180.v:5843$1308_Y - connect \Y $and$ls180.v:5843$1309_Y + connect \A $and$ls180.v:5897$1294_Y + connect \B $eq$ls180.v:5897$1295_Y + connect \Y $and$ls180.v:5897$1296_Y end - attribute \src "ls180.v:5845.40-5845.93" - cell $and $and$ls180.v:5845$1310 + attribute \src "ls180.v:5899.39-5899.92" + cell $and $and$ls180.v:5899$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5845$1310_Y + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5899$1297_Y end - attribute \src "ls180.v:5845.39-5845.143" - cell $and $and$ls180.v:5845$1312 + attribute \src "ls180.v:5899.38-5899.142" + cell $and $and$ls180.v:5899$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5845$1310_Y - connect \B $eq$ls180.v:5845$1311_Y - connect \Y $and$ls180.v:5845$1312_Y + connect \A $and$ls180.v:5899$1297_Y + connect \B $eq$ls180.v:5899$1298_Y + connect \Y $and$ls180.v:5899$1299_Y end - attribute \src "ls180.v:5846.40-5846.96" - cell $and $and$ls180.v:5846$1314 + attribute \src "ls180.v:5900.39-5900.95" + cell $and $and$ls180.v:5900$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5846$1313_Y - connect \Y $and$ls180.v:5846$1314_Y + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5900$1300_Y + connect \Y $and$ls180.v:5900$1301_Y end - attribute \src "ls180.v:5846.39-5846.146" - cell $and $and$ls180.v:5846$1316 + attribute \src "ls180.v:5900.38-5900.145" + cell $and $and$ls180.v:5900$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5846$1314_Y - connect \B $eq$ls180.v:5846$1315_Y - connect \Y $and$ls180.v:5846$1316_Y + connect \A $and$ls180.v:5900$1301_Y + connect \B $eq$ls180.v:5900$1302_Y + connect \Y $and$ls180.v:5900$1303_Y end - attribute \src "ls180.v:5858.42-5858.95" - cell $and $and$ls180.v:5858$1318 + attribute \src "ls180.v:5902.40-5902.93" + cell $and $and$ls180.v:5902$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235822,43 +241251,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5858$1318_Y + connect \Y $and$ls180.v:5902$1304_Y end - attribute \src "ls180.v:5858.41-5858.145" - cell $and $and$ls180.v:5858$1320 + attribute \src "ls180.v:5902.39-5902.143" + cell $and $and$ls180.v:5902$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5858$1318_Y - connect \B $eq$ls180.v:5858$1319_Y - connect \Y $and$ls180.v:5858$1320_Y + connect \A $and$ls180.v:5902$1304_Y + connect \B $eq$ls180.v:5902$1305_Y + connect \Y $and$ls180.v:5902$1306_Y end - attribute \src "ls180.v:5859.42-5859.98" - cell $and $and$ls180.v:5859$1322 + attribute \src "ls180.v:5903.40-5903.96" + cell $and $and$ls180.v:5903$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5859$1321_Y - connect \Y $and$ls180.v:5859$1322_Y + connect \B $not$ls180.v:5903$1307_Y + connect \Y $and$ls180.v:5903$1308_Y end - attribute \src "ls180.v:5859.41-5859.148" - cell $and $and$ls180.v:5859$1324 + attribute \src "ls180.v:5903.39-5903.146" + cell $and $and$ls180.v:5903$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5859$1322_Y - connect \B $eq$ls180.v:5859$1323_Y - connect \Y $and$ls180.v:5859$1324_Y + connect \A $and$ls180.v:5903$1308_Y + connect \B $eq$ls180.v:5903$1309_Y + connect \Y $and$ls180.v:5903$1310_Y end - attribute \src "ls180.v:5861.42-5861.95" - cell $and $and$ls180.v:5861$1325 + attribute \src "ls180.v:5905.40-5905.93" + cell $and $and$ls180.v:5905$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235866,43 +241295,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5861$1325_Y + connect \Y $and$ls180.v:5905$1311_Y end - attribute \src "ls180.v:5861.41-5861.145" - cell $and $and$ls180.v:5861$1327 + attribute \src "ls180.v:5905.39-5905.143" + cell $and $and$ls180.v:5905$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5861$1325_Y - connect \B $eq$ls180.v:5861$1326_Y - connect \Y $and$ls180.v:5861$1327_Y + connect \A $and$ls180.v:5905$1311_Y + connect \B $eq$ls180.v:5905$1312_Y + connect \Y $and$ls180.v:5905$1313_Y end - attribute \src "ls180.v:5862.42-5862.98" - cell $and $and$ls180.v:5862$1329 + attribute \src "ls180.v:5906.40-5906.96" + cell $and $and$ls180.v:5906$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5862$1328_Y - connect \Y $and$ls180.v:5862$1329_Y + connect \B $not$ls180.v:5906$1314_Y + connect \Y $and$ls180.v:5906$1315_Y end - attribute \src "ls180.v:5862.41-5862.148" - cell $and $and$ls180.v:5862$1331 + attribute \src "ls180.v:5906.39-5906.146" + cell $and $and$ls180.v:5906$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5862$1329_Y - connect \B $eq$ls180.v:5862$1330_Y - connect \Y $and$ls180.v:5862$1331_Y + connect \A $and$ls180.v:5906$1315_Y + connect \B $eq$ls180.v:5906$1316_Y + connect \Y $and$ls180.v:5906$1317_Y end - attribute \src "ls180.v:5864.42-5864.95" - cell $and $and$ls180.v:5864$1332 + attribute \src "ls180.v:5908.40-5908.93" + cell $and $and$ls180.v:5908$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235910,43 +241339,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5864$1332_Y + connect \Y $and$ls180.v:5908$1318_Y end - attribute \src "ls180.v:5864.41-5864.145" - cell $and $and$ls180.v:5864$1334 + attribute \src "ls180.v:5908.39-5908.143" + cell $and $and$ls180.v:5908$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5864$1332_Y - connect \B $eq$ls180.v:5864$1333_Y - connect \Y $and$ls180.v:5864$1334_Y + connect \A $and$ls180.v:5908$1318_Y + connect \B $eq$ls180.v:5908$1319_Y + connect \Y $and$ls180.v:5908$1320_Y end - attribute \src "ls180.v:5865.42-5865.98" - cell $and $and$ls180.v:5865$1336 + attribute \src "ls180.v:5909.40-5909.96" + cell $and $and$ls180.v:5909$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5865$1335_Y - connect \Y $and$ls180.v:5865$1336_Y + connect \B $not$ls180.v:5909$1321_Y + connect \Y $and$ls180.v:5909$1322_Y end - attribute \src "ls180.v:5865.41-5865.148" - cell $and $and$ls180.v:5865$1338 + attribute \src "ls180.v:5909.39-5909.146" + cell $and $and$ls180.v:5909$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5865$1336_Y - connect \B $eq$ls180.v:5865$1337_Y - connect \Y $and$ls180.v:5865$1338_Y + connect \A $and$ls180.v:5909$1322_Y + connect \B $eq$ls180.v:5909$1323_Y + connect \Y $and$ls180.v:5909$1324_Y end - attribute \src "ls180.v:5867.42-5867.95" - cell $and $and$ls180.v:5867$1339 + attribute \src "ls180.v:5911.40-5911.93" + cell $and $and$ls180.v:5911$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -235954,527 +241383,527 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5867$1339_Y + connect \Y $and$ls180.v:5911$1325_Y end - attribute \src "ls180.v:5867.41-5867.145" - cell $and $and$ls180.v:5867$1341 + attribute \src "ls180.v:5911.39-5911.143" + cell $and $and$ls180.v:5911$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5867$1339_Y - connect \B $eq$ls180.v:5867$1340_Y - connect \Y $and$ls180.v:5867$1341_Y + connect \A $and$ls180.v:5911$1325_Y + connect \B $eq$ls180.v:5911$1326_Y + connect \Y $and$ls180.v:5911$1327_Y end - attribute \src "ls180.v:5868.42-5868.98" - cell $and $and$ls180.v:5868$1343 + attribute \src "ls180.v:5912.40-5912.96" + cell $and $and$ls180.v:5912$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5868$1342_Y - connect \Y $and$ls180.v:5868$1343_Y + connect \B $not$ls180.v:5912$1328_Y + connect \Y $and$ls180.v:5912$1329_Y end - attribute \src "ls180.v:5868.41-5868.148" - cell $and $and$ls180.v:5868$1345 + attribute \src "ls180.v:5912.39-5912.146" + cell $and $and$ls180.v:5912$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1343_Y - connect \B $eq$ls180.v:5868$1344_Y - connect \Y $and$ls180.v:5868$1345_Y + connect \A $and$ls180.v:5912$1329_Y + connect \B $eq$ls180.v:5912$1330_Y + connect \Y $and$ls180.v:5912$1331_Y end - attribute \src "ls180.v:5870.42-5870.95" - cell $and $and$ls180.v:5870$1346 + attribute \src "ls180.v:5924.42-5924.95" + cell $and $and$ls180.v:5924$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5870$1346_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5924$1333_Y end - attribute \src "ls180.v:5870.41-5870.145" - cell $and $and$ls180.v:5870$1348 + attribute \src "ls180.v:5924.41-5924.145" + cell $and $and$ls180.v:5924$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5870$1346_Y - connect \B $eq$ls180.v:5870$1347_Y - connect \Y $and$ls180.v:5870$1348_Y + connect \A $and$ls180.v:5924$1333_Y + connect \B $eq$ls180.v:5924$1334_Y + connect \Y $and$ls180.v:5924$1335_Y end - attribute \src "ls180.v:5871.42-5871.98" - cell $and $and$ls180.v:5871$1350 + attribute \src "ls180.v:5925.42-5925.98" + cell $and $and$ls180.v:5925$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5871$1349_Y - connect \Y $and$ls180.v:5871$1350_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5925$1336_Y + connect \Y $and$ls180.v:5925$1337_Y end - attribute \src "ls180.v:5871.41-5871.148" - cell $and $and$ls180.v:5871$1352 + attribute \src "ls180.v:5925.41-5925.148" + cell $and $and$ls180.v:5925$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1350_Y - connect \B $eq$ls180.v:5871$1351_Y - connect \Y $and$ls180.v:5871$1352_Y + connect \A $and$ls180.v:5925$1337_Y + connect \B $eq$ls180.v:5925$1338_Y + connect \Y $and$ls180.v:5925$1339_Y end - attribute \src "ls180.v:5873.42-5873.95" - cell $and $and$ls180.v:5873$1353 + attribute \src "ls180.v:5927.42-5927.95" + cell $and $and$ls180.v:5927$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5873$1353_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5927$1340_Y end - attribute \src "ls180.v:5873.41-5873.145" - cell $and $and$ls180.v:5873$1355 + attribute \src "ls180.v:5927.41-5927.145" + cell $and $and$ls180.v:5927$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1353_Y - connect \B $eq$ls180.v:5873$1354_Y - connect \Y $and$ls180.v:5873$1355_Y + connect \A $and$ls180.v:5927$1340_Y + connect \B $eq$ls180.v:5927$1341_Y + connect \Y $and$ls180.v:5927$1342_Y end - attribute \src "ls180.v:5874.42-5874.98" - cell $and $and$ls180.v:5874$1357 + attribute \src "ls180.v:5928.42-5928.98" + cell $and $and$ls180.v:5928$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5874$1356_Y - connect \Y $and$ls180.v:5874$1357_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5928$1343_Y + connect \Y $and$ls180.v:5928$1344_Y end - attribute \src "ls180.v:5874.41-5874.148" - cell $and $and$ls180.v:5874$1359 + attribute \src "ls180.v:5928.41-5928.148" + cell $and $and$ls180.v:5928$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1357_Y - connect \B $eq$ls180.v:5874$1358_Y - connect \Y $and$ls180.v:5874$1359_Y + connect \A $and$ls180.v:5928$1344_Y + connect \B $eq$ls180.v:5928$1345_Y + connect \Y $and$ls180.v:5928$1346_Y end - attribute \src "ls180.v:5876.42-5876.95" - cell $and $and$ls180.v:5876$1360 + attribute \src "ls180.v:5930.42-5930.95" + cell $and $and$ls180.v:5930$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5876$1360_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5930$1347_Y end - attribute \src "ls180.v:5876.41-5876.145" - cell $and $and$ls180.v:5876$1362 + attribute \src "ls180.v:5930.41-5930.145" + cell $and $and$ls180.v:5930$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5876$1360_Y - connect \B $eq$ls180.v:5876$1361_Y - connect \Y $and$ls180.v:5876$1362_Y + connect \A $and$ls180.v:5930$1347_Y + connect \B $eq$ls180.v:5930$1348_Y + connect \Y $and$ls180.v:5930$1349_Y end - attribute \src "ls180.v:5877.42-5877.98" - cell $and $and$ls180.v:5877$1364 + attribute \src "ls180.v:5931.42-5931.98" + cell $and $and$ls180.v:5931$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5877$1363_Y - connect \Y $and$ls180.v:5877$1364_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5931$1350_Y + connect \Y $and$ls180.v:5931$1351_Y end - attribute \src "ls180.v:5877.41-5877.148" - cell $and $and$ls180.v:5877$1366 + attribute \src "ls180.v:5931.41-5931.148" + cell $and $and$ls180.v:5931$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1364_Y - connect \B $eq$ls180.v:5877$1365_Y - connect \Y $and$ls180.v:5877$1366_Y + connect \A $and$ls180.v:5931$1351_Y + connect \B $eq$ls180.v:5931$1352_Y + connect \Y $and$ls180.v:5931$1353_Y end - attribute \src "ls180.v:5879.42-5879.95" - cell $and $and$ls180.v:5879$1367 + attribute \src "ls180.v:5933.42-5933.95" + cell $and $and$ls180.v:5933$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5879$1367_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5933$1354_Y end - attribute \src "ls180.v:5879.41-5879.145" - cell $and $and$ls180.v:5879$1369 + attribute \src "ls180.v:5933.41-5933.145" + cell $and $and$ls180.v:5933$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5879$1367_Y - connect \B $eq$ls180.v:5879$1368_Y - connect \Y $and$ls180.v:5879$1369_Y + connect \A $and$ls180.v:5933$1354_Y + connect \B $eq$ls180.v:5933$1355_Y + connect \Y $and$ls180.v:5933$1356_Y end - attribute \src "ls180.v:5880.42-5880.98" - cell $and $and$ls180.v:5880$1371 + attribute \src "ls180.v:5934.42-5934.98" + cell $and $and$ls180.v:5934$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5880$1370_Y - connect \Y $and$ls180.v:5880$1371_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5934$1357_Y + connect \Y $and$ls180.v:5934$1358_Y end - attribute \src "ls180.v:5880.41-5880.148" - cell $and $and$ls180.v:5880$1373 + attribute \src "ls180.v:5934.41-5934.148" + cell $and $and$ls180.v:5934$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5880$1371_Y - connect \B $eq$ls180.v:5880$1372_Y - connect \Y $and$ls180.v:5880$1373_Y + connect \A $and$ls180.v:5934$1358_Y + connect \B $eq$ls180.v:5934$1359_Y + connect \Y $and$ls180.v:5934$1360_Y end - attribute \src "ls180.v:5882.44-5882.97" - cell $and $and$ls180.v:5882$1374 + attribute \src "ls180.v:5936.42-5936.95" + cell $and $and$ls180.v:5936$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5882$1374_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5936$1361_Y end - attribute \src "ls180.v:5882.43-5882.147" - cell $and $and$ls180.v:5882$1376 + attribute \src "ls180.v:5936.41-5936.145" + cell $and $and$ls180.v:5936$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5882$1374_Y - connect \B $eq$ls180.v:5882$1375_Y - connect \Y $and$ls180.v:5882$1376_Y + connect \A $and$ls180.v:5936$1361_Y + connect \B $eq$ls180.v:5936$1362_Y + connect \Y $and$ls180.v:5936$1363_Y end - attribute \src "ls180.v:5883.44-5883.100" - cell $and $and$ls180.v:5883$1378 + attribute \src "ls180.v:5937.42-5937.98" + cell $and $and$ls180.v:5937$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5883$1377_Y - connect \Y $and$ls180.v:5883$1378_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5937$1364_Y + connect \Y $and$ls180.v:5937$1365_Y end - attribute \src "ls180.v:5883.43-5883.150" - cell $and $and$ls180.v:5883$1380 + attribute \src "ls180.v:5937.41-5937.148" + cell $and $and$ls180.v:5937$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5883$1378_Y - connect \B $eq$ls180.v:5883$1379_Y - connect \Y $and$ls180.v:5883$1380_Y + connect \A $and$ls180.v:5937$1365_Y + connect \B $eq$ls180.v:5937$1366_Y + connect \Y $and$ls180.v:5937$1367_Y end - attribute \src "ls180.v:5885.44-5885.97" - cell $and $and$ls180.v:5885$1381 + attribute \src "ls180.v:5939.42-5939.95" + cell $and $and$ls180.v:5939$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5885$1381_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5939$1368_Y end - attribute \src "ls180.v:5885.43-5885.147" - cell $and $and$ls180.v:5885$1383 + attribute \src "ls180.v:5939.41-5939.145" + cell $and $and$ls180.v:5939$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5885$1381_Y - connect \B $eq$ls180.v:5885$1382_Y - connect \Y $and$ls180.v:5885$1383_Y + connect \A $and$ls180.v:5939$1368_Y + connect \B $eq$ls180.v:5939$1369_Y + connect \Y $and$ls180.v:5939$1370_Y end - attribute \src "ls180.v:5886.44-5886.100" - cell $and $and$ls180.v:5886$1385 + attribute \src "ls180.v:5940.42-5940.98" + cell $and $and$ls180.v:5940$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5886$1384_Y - connect \Y $and$ls180.v:5886$1385_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5940$1371_Y + connect \Y $and$ls180.v:5940$1372_Y end - attribute \src "ls180.v:5886.43-5886.150" - cell $and $and$ls180.v:5886$1387 + attribute \src "ls180.v:5940.41-5940.148" + cell $and $and$ls180.v:5940$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5886$1385_Y - connect \B $eq$ls180.v:5886$1386_Y - connect \Y $and$ls180.v:5886$1387_Y + connect \A $and$ls180.v:5940$1372_Y + connect \B $eq$ls180.v:5940$1373_Y + connect \Y $and$ls180.v:5940$1374_Y end - attribute \src "ls180.v:5888.44-5888.97" - cell $and $and$ls180.v:5888$1388 + attribute \src "ls180.v:5942.42-5942.95" + cell $and $and$ls180.v:5942$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5888$1388_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5942$1375_Y end - attribute \src "ls180.v:5888.43-5888.148" - cell $and $and$ls180.v:5888$1390 + attribute \src "ls180.v:5942.41-5942.145" + cell $and $and$ls180.v:5942$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5888$1388_Y - connect \B $eq$ls180.v:5888$1389_Y - connect \Y $and$ls180.v:5888$1390_Y + connect \A $and$ls180.v:5942$1375_Y + connect \B $eq$ls180.v:5942$1376_Y + connect \Y $and$ls180.v:5942$1377_Y end - attribute \src "ls180.v:5889.44-5889.100" - cell $and $and$ls180.v:5889$1392 + attribute \src "ls180.v:5943.42-5943.98" + cell $and $and$ls180.v:5943$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5889$1391_Y - connect \Y $and$ls180.v:5889$1392_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5943$1378_Y + connect \Y $and$ls180.v:5943$1379_Y end - attribute \src "ls180.v:5889.43-5889.151" - cell $and $and$ls180.v:5889$1394 + attribute \src "ls180.v:5943.41-5943.148" + cell $and $and$ls180.v:5943$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5889$1392_Y - connect \B $eq$ls180.v:5889$1393_Y - connect \Y $and$ls180.v:5889$1394_Y + connect \A $and$ls180.v:5943$1379_Y + connect \B $eq$ls180.v:5943$1380_Y + connect \Y $and$ls180.v:5943$1381_Y end - attribute \src "ls180.v:5891.44-5891.97" - cell $and $and$ls180.v:5891$1395 + attribute \src "ls180.v:5945.42-5945.95" + cell $and $and$ls180.v:5945$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5891$1395_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5945$1382_Y end - attribute \src "ls180.v:5891.43-5891.148" - cell $and $and$ls180.v:5891$1397 + attribute \src "ls180.v:5945.41-5945.145" + cell $and $and$ls180.v:5945$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1395_Y - connect \B $eq$ls180.v:5891$1396_Y - connect \Y $and$ls180.v:5891$1397_Y + connect \A $and$ls180.v:5945$1382_Y + connect \B $eq$ls180.v:5945$1383_Y + connect \Y $and$ls180.v:5945$1384_Y end - attribute \src "ls180.v:5892.44-5892.100" - cell $and $and$ls180.v:5892$1399 + attribute \src "ls180.v:5946.42-5946.98" + cell $and $and$ls180.v:5946$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5892$1398_Y - connect \Y $and$ls180.v:5892$1399_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5946$1385_Y + connect \Y $and$ls180.v:5946$1386_Y end - attribute \src "ls180.v:5892.43-5892.151" - cell $and $and$ls180.v:5892$1401 + attribute \src "ls180.v:5946.41-5946.148" + cell $and $and$ls180.v:5946$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5892$1399_Y - connect \B $eq$ls180.v:5892$1400_Y - connect \Y $and$ls180.v:5892$1401_Y + connect \A $and$ls180.v:5946$1386_Y + connect \B $eq$ls180.v:5946$1387_Y + connect \Y $and$ls180.v:5946$1388_Y end - attribute \src "ls180.v:5894.44-5894.97" - cell $and $and$ls180.v:5894$1402 + attribute \src "ls180.v:5948.44-5948.97" + cell $and $and$ls180.v:5948$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5894$1402_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5948$1389_Y end - attribute \src "ls180.v:5894.43-5894.148" - cell $and $and$ls180.v:5894$1404 + attribute \src "ls180.v:5948.43-5948.147" + cell $and $and$ls180.v:5948$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1402_Y - connect \B $eq$ls180.v:5894$1403_Y - connect \Y $and$ls180.v:5894$1404_Y + connect \A $and$ls180.v:5948$1389_Y + connect \B $eq$ls180.v:5948$1390_Y + connect \Y $and$ls180.v:5948$1391_Y end - attribute \src "ls180.v:5895.44-5895.100" - cell $and $and$ls180.v:5895$1406 + attribute \src "ls180.v:5949.44-5949.100" + cell $and $and$ls180.v:5949$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5895$1405_Y - connect \Y $and$ls180.v:5895$1406_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5949$1392_Y + connect \Y $and$ls180.v:5949$1393_Y end - attribute \src "ls180.v:5895.43-5895.151" - cell $and $and$ls180.v:5895$1408 + attribute \src "ls180.v:5949.43-5949.150" + cell $and $and$ls180.v:5949$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5895$1406_Y - connect \B $eq$ls180.v:5895$1407_Y - connect \Y $and$ls180.v:5895$1408_Y + connect \A $and$ls180.v:5949$1393_Y + connect \B $eq$ls180.v:5949$1394_Y + connect \Y $and$ls180.v:5949$1395_Y end - attribute \src "ls180.v:5897.41-5897.94" - cell $and $and$ls180.v:5897$1409 + attribute \src "ls180.v:5951.44-5951.97" + cell $and $and$ls180.v:5951$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5897$1409_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5951$1396_Y end - attribute \src "ls180.v:5897.40-5897.145" - cell $and $and$ls180.v:5897$1411 + attribute \src "ls180.v:5951.43-5951.147" + cell $and $and$ls180.v:5951$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5897$1409_Y - connect \B $eq$ls180.v:5897$1410_Y - connect \Y $and$ls180.v:5897$1411_Y + connect \A $and$ls180.v:5951$1396_Y + connect \B $eq$ls180.v:5951$1397_Y + connect \Y $and$ls180.v:5951$1398_Y end - attribute \src "ls180.v:5898.41-5898.97" - cell $and $and$ls180.v:5898$1413 + attribute \src "ls180.v:5952.44-5952.100" + cell $and $and$ls180.v:5952$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5898$1412_Y - connect \Y $and$ls180.v:5898$1413_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5952$1399_Y + connect \Y $and$ls180.v:5952$1400_Y end - attribute \src "ls180.v:5898.40-5898.148" - cell $and $and$ls180.v:5898$1415 + attribute \src "ls180.v:5952.43-5952.150" + cell $and $and$ls180.v:5952$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5898$1413_Y - connect \B $eq$ls180.v:5898$1414_Y - connect \Y $and$ls180.v:5898$1415_Y + connect \A $and$ls180.v:5952$1400_Y + connect \B $eq$ls180.v:5952$1401_Y + connect \Y $and$ls180.v:5952$1402_Y end - attribute \src "ls180.v:5900.42-5900.95" - cell $and $and$ls180.v:5900$1416 + attribute \src "ls180.v:5954.44-5954.97" + cell $and $and$ls180.v:5954$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5900$1416_Y + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5954$1403_Y end - attribute \src "ls180.v:5900.41-5900.146" - cell $and $and$ls180.v:5900$1418 + attribute \src "ls180.v:5954.43-5954.148" + cell $and $and$ls180.v:5954$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5900$1416_Y - connect \B $eq$ls180.v:5900$1417_Y - connect \Y $and$ls180.v:5900$1418_Y + connect \A $and$ls180.v:5954$1403_Y + connect \B $eq$ls180.v:5954$1404_Y + connect \Y $and$ls180.v:5954$1405_Y end - attribute \src "ls180.v:5901.42-5901.98" - cell $and $and$ls180.v:5901$1420 + attribute \src "ls180.v:5955.44-5955.100" + cell $and $and$ls180.v:5955$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5901$1419_Y - connect \Y $and$ls180.v:5901$1420_Y + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5955$1406_Y + connect \Y $and$ls180.v:5955$1407_Y end - attribute \src "ls180.v:5901.41-5901.149" - cell $and $and$ls180.v:5901$1422 + attribute \src "ls180.v:5955.43-5955.151" + cell $and $and$ls180.v:5955$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5901$1420_Y - connect \B $eq$ls180.v:5901$1421_Y - connect \Y $and$ls180.v:5901$1422_Y + connect \A $and$ls180.v:5955$1407_Y + connect \B $eq$ls180.v:5955$1408_Y + connect \Y $and$ls180.v:5955$1409_Y end - attribute \src "ls180.v:5920.46-5920.99" - cell $and $and$ls180.v:5920$1424 + attribute \src "ls180.v:5957.44-5957.97" + cell $and $and$ls180.v:5957$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236482,43 +241911,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5920$1424_Y + connect \Y $and$ls180.v:5957$1410_Y end - attribute \src "ls180.v:5920.45-5920.149" - cell $and $and$ls180.v:5920$1426 + attribute \src "ls180.v:5957.43-5957.148" + cell $and $and$ls180.v:5957$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1424_Y - connect \B $eq$ls180.v:5920$1425_Y - connect \Y $and$ls180.v:5920$1426_Y + connect \A $and$ls180.v:5957$1410_Y + connect \B $eq$ls180.v:5957$1411_Y + connect \Y $and$ls180.v:5957$1412_Y end - attribute \src "ls180.v:5921.46-5921.102" - cell $and $and$ls180.v:5921$1428 + attribute \src "ls180.v:5958.44-5958.100" + cell $and $and$ls180.v:5958$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5921$1427_Y - connect \Y $and$ls180.v:5921$1428_Y + connect \B $not$ls180.v:5958$1413_Y + connect \Y $and$ls180.v:5958$1414_Y end - attribute \src "ls180.v:5921.45-5921.152" - cell $and $and$ls180.v:5921$1430 + attribute \src "ls180.v:5958.43-5958.151" + cell $and $and$ls180.v:5958$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5921$1428_Y - connect \B $eq$ls180.v:5921$1429_Y - connect \Y $and$ls180.v:5921$1430_Y + connect \A $and$ls180.v:5958$1414_Y + connect \B $eq$ls180.v:5958$1415_Y + connect \Y $and$ls180.v:5958$1416_Y end - attribute \src "ls180.v:5923.46-5923.99" - cell $and $and$ls180.v:5923$1431 + attribute \src "ls180.v:5960.44-5960.97" + cell $and $and$ls180.v:5960$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236526,43 +241955,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5923$1431_Y + connect \Y $and$ls180.v:5960$1417_Y end - attribute \src "ls180.v:5923.45-5923.149" - cell $and $and$ls180.v:5923$1433 + attribute \src "ls180.v:5960.43-5960.148" + cell $and $and$ls180.v:5960$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5923$1431_Y - connect \B $eq$ls180.v:5923$1432_Y - connect \Y $and$ls180.v:5923$1433_Y + connect \A $and$ls180.v:5960$1417_Y + connect \B $eq$ls180.v:5960$1418_Y + connect \Y $and$ls180.v:5960$1419_Y end - attribute \src "ls180.v:5924.46-5924.102" - cell $and $and$ls180.v:5924$1435 + attribute \src "ls180.v:5961.44-5961.100" + cell $and $and$ls180.v:5961$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5924$1434_Y - connect \Y $and$ls180.v:5924$1435_Y + connect \B $not$ls180.v:5961$1420_Y + connect \Y $and$ls180.v:5961$1421_Y end - attribute \src "ls180.v:5924.45-5924.152" - cell $and $and$ls180.v:5924$1437 + attribute \src "ls180.v:5961.43-5961.151" + cell $and $and$ls180.v:5961$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1435_Y - connect \B $eq$ls180.v:5924$1436_Y - connect \Y $and$ls180.v:5924$1437_Y + connect \A $and$ls180.v:5961$1421_Y + connect \B $eq$ls180.v:5961$1422_Y + connect \Y $and$ls180.v:5961$1423_Y end - attribute \src "ls180.v:5926.46-5926.99" - cell $and $and$ls180.v:5926$1438 + attribute \src "ls180.v:5963.41-5963.94" + cell $and $and$ls180.v:5963$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236570,43 +241999,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5926$1438_Y + connect \Y $and$ls180.v:5963$1424_Y end - attribute \src "ls180.v:5926.45-5926.149" - cell $and $and$ls180.v:5926$1440 + attribute \src "ls180.v:5963.40-5963.145" + cell $and $and$ls180.v:5963$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5926$1438_Y - connect \B $eq$ls180.v:5926$1439_Y - connect \Y $and$ls180.v:5926$1440_Y + connect \A $and$ls180.v:5963$1424_Y + connect \B $eq$ls180.v:5963$1425_Y + connect \Y $and$ls180.v:5963$1426_Y end - attribute \src "ls180.v:5927.46-5927.102" - cell $and $and$ls180.v:5927$1442 + attribute \src "ls180.v:5964.41-5964.97" + cell $and $and$ls180.v:5964$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5927$1441_Y - connect \Y $and$ls180.v:5927$1442_Y + connect \B $not$ls180.v:5964$1427_Y + connect \Y $and$ls180.v:5964$1428_Y end - attribute \src "ls180.v:5927.45-5927.152" - cell $and $and$ls180.v:5927$1444 + attribute \src "ls180.v:5964.40-5964.148" + cell $and $and$ls180.v:5964$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1442_Y - connect \B $eq$ls180.v:5927$1443_Y - connect \Y $and$ls180.v:5927$1444_Y + connect \A $and$ls180.v:5964$1428_Y + connect \B $eq$ls180.v:5964$1429_Y + connect \Y $and$ls180.v:5964$1430_Y end - attribute \src "ls180.v:5929.46-5929.99" - cell $and $and$ls180.v:5929$1445 + attribute \src "ls180.v:5966.42-5966.95" + cell $and $and$ls180.v:5966$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236614,1319 +242043,1187 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5929$1445_Y + connect \Y $and$ls180.v:5966$1431_Y end - attribute \src "ls180.v:5929.45-5929.149" - cell $and $and$ls180.v:5929$1447 + attribute \src "ls180.v:5966.41-5966.146" + cell $and $and$ls180.v:5966$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5929$1445_Y - connect \B $eq$ls180.v:5929$1446_Y - connect \Y $and$ls180.v:5929$1447_Y + connect \A $and$ls180.v:5966$1431_Y + connect \B $eq$ls180.v:5966$1432_Y + connect \Y $and$ls180.v:5966$1433_Y end - attribute \src "ls180.v:5930.46-5930.102" - cell $and $and$ls180.v:5930$1449 + attribute \src "ls180.v:5967.42-5967.98" + cell $and $and$ls180.v:5967$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5930$1448_Y - connect \Y $and$ls180.v:5930$1449_Y + connect \B $not$ls180.v:5967$1434_Y + connect \Y $and$ls180.v:5967$1435_Y end - attribute \src "ls180.v:5930.45-5930.152" - cell $and $and$ls180.v:5930$1451 + attribute \src "ls180.v:5967.41-5967.149" + cell $and $and$ls180.v:5967$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5930$1449_Y - connect \B $eq$ls180.v:5930$1450_Y - connect \Y $and$ls180.v:5930$1451_Y + connect \A $and$ls180.v:5967$1435_Y + connect \B $eq$ls180.v:5967$1436_Y + connect \Y $and$ls180.v:5967$1437_Y end - attribute \src "ls180.v:5932.45-5932.98" - cell $and $and$ls180.v:5932$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5932$1452_Y - end - attribute \src "ls180.v:5932.44-5932.148" - cell $and $and$ls180.v:5932$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5932$1452_Y - connect \B $eq$ls180.v:5932$1453_Y - connect \Y $and$ls180.v:5932$1454_Y - end - attribute \src "ls180.v:5933.45-5933.101" - cell $and $and$ls180.v:5933$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5933$1455_Y - connect \Y $and$ls180.v:5933$1456_Y - end - attribute \src "ls180.v:5933.44-5933.151" - cell $and $and$ls180.v:5933$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5933$1456_Y - connect \B $eq$ls180.v:5933$1457_Y - connect \Y $and$ls180.v:5933$1458_Y - end - attribute \src "ls180.v:5935.45-5935.98" - cell $and $and$ls180.v:5935$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5935$1459_Y - end - attribute \src "ls180.v:5935.44-5935.148" - cell $and $and$ls180.v:5935$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5935$1459_Y - connect \B $eq$ls180.v:5935$1460_Y - connect \Y $and$ls180.v:5935$1461_Y - end - attribute \src "ls180.v:5936.45-5936.101" - cell $and $and$ls180.v:5936$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5936$1462_Y - connect \Y $and$ls180.v:5936$1463_Y - end - attribute \src "ls180.v:5936.44-5936.151" - cell $and $and$ls180.v:5936$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5936$1463_Y - connect \B $eq$ls180.v:5936$1464_Y - connect \Y $and$ls180.v:5936$1465_Y - end - attribute \src "ls180.v:5938.45-5938.98" - cell $and $and$ls180.v:5938$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5938$1466_Y - end - attribute \src "ls180.v:5938.44-5938.148" - cell $and $and$ls180.v:5938$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5938$1466_Y - connect \B $eq$ls180.v:5938$1467_Y - connect \Y $and$ls180.v:5938$1468_Y - end - attribute \src "ls180.v:5939.45-5939.101" - cell $and $and$ls180.v:5939$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5939$1469_Y - connect \Y $and$ls180.v:5939$1470_Y - end - attribute \src "ls180.v:5939.44-5939.151" - cell $and $and$ls180.v:5939$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5939$1470_Y - connect \B $eq$ls180.v:5939$1471_Y - connect \Y $and$ls180.v:5939$1472_Y - end - attribute \src "ls180.v:5941.45-5941.98" - cell $and $and$ls180.v:5941$1473 + attribute \src "ls180.v:5986.46-5986.99" + cell $and $and$ls180.v:5986$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5941$1473_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5986$1439_Y end - attribute \src "ls180.v:5941.44-5941.148" - cell $and $and$ls180.v:5941$1475 + attribute \src "ls180.v:5986.45-5986.149" + cell $and $and$ls180.v:5986$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5941$1473_Y - connect \B $eq$ls180.v:5941$1474_Y - connect \Y $and$ls180.v:5941$1475_Y + connect \A $and$ls180.v:5986$1439_Y + connect \B $eq$ls180.v:5986$1440_Y + connect \Y $and$ls180.v:5986$1441_Y end - attribute \src "ls180.v:5942.45-5942.101" - cell $and $and$ls180.v:5942$1477 + attribute \src "ls180.v:5987.46-5987.102" + cell $and $and$ls180.v:5987$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5942$1476_Y - connect \Y $and$ls180.v:5942$1477_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5987$1442_Y + connect \Y $and$ls180.v:5987$1443_Y end - attribute \src "ls180.v:5942.44-5942.151" - cell $and $and$ls180.v:5942$1479 + attribute \src "ls180.v:5987.45-5987.152" + cell $and $and$ls180.v:5987$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5942$1477_Y - connect \B $eq$ls180.v:5942$1478_Y - connect \Y $and$ls180.v:5942$1479_Y + connect \A $and$ls180.v:5987$1443_Y + connect \B $eq$ls180.v:5987$1444_Y + connect \Y $and$ls180.v:5987$1445_Y end - attribute \src "ls180.v:5944.36-5944.89" - cell $and $and$ls180.v:5944$1480 + attribute \src "ls180.v:5989.46-5989.99" + cell $and $and$ls180.v:5989$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5944$1480_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5989$1446_Y end - attribute \src "ls180.v:5944.35-5944.139" - cell $and $and$ls180.v:5944$1482 + attribute \src "ls180.v:5989.45-5989.149" + cell $and $and$ls180.v:5989$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5944$1480_Y - connect \B $eq$ls180.v:5944$1481_Y - connect \Y $and$ls180.v:5944$1482_Y + connect \A $and$ls180.v:5989$1446_Y + connect \B $eq$ls180.v:5989$1447_Y + connect \Y $and$ls180.v:5989$1448_Y end - attribute \src "ls180.v:5945.36-5945.92" - cell $and $and$ls180.v:5945$1484 + attribute \src "ls180.v:5990.46-5990.102" + cell $and $and$ls180.v:5990$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5945$1483_Y - connect \Y $and$ls180.v:5945$1484_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5990$1449_Y + connect \Y $and$ls180.v:5990$1450_Y end - attribute \src "ls180.v:5945.35-5945.142" - cell $and $and$ls180.v:5945$1486 + attribute \src "ls180.v:5990.45-5990.152" + cell $and $and$ls180.v:5990$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5945$1484_Y - connect \B $eq$ls180.v:5945$1485_Y - connect \Y $and$ls180.v:5945$1486_Y + connect \A $and$ls180.v:5990$1450_Y + connect \B $eq$ls180.v:5990$1451_Y + connect \Y $and$ls180.v:5990$1452_Y end - attribute \src "ls180.v:5947.47-5947.100" - cell $and $and$ls180.v:5947$1487 + attribute \src "ls180.v:5992.46-5992.99" + cell $and $and$ls180.v:5992$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5947$1487_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5992$1453_Y end - attribute \src "ls180.v:5947.46-5947.150" - cell $and $and$ls180.v:5947$1489 + attribute \src "ls180.v:5992.45-5992.149" + cell $and $and$ls180.v:5992$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5947$1487_Y - connect \B $eq$ls180.v:5947$1488_Y - connect \Y $and$ls180.v:5947$1489_Y + connect \A $and$ls180.v:5992$1453_Y + connect \B $eq$ls180.v:5992$1454_Y + connect \Y $and$ls180.v:5992$1455_Y end - attribute \src "ls180.v:5948.47-5948.103" - cell $and $and$ls180.v:5948$1491 + attribute \src "ls180.v:5993.46-5993.102" + cell $and $and$ls180.v:5993$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5948$1490_Y - connect \Y $and$ls180.v:5948$1491_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5993$1456_Y + connect \Y $and$ls180.v:5993$1457_Y end - attribute \src "ls180.v:5948.46-5948.153" - cell $and $and$ls180.v:5948$1493 + attribute \src "ls180.v:5993.45-5993.152" + cell $and $and$ls180.v:5993$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5948$1491_Y - connect \B $eq$ls180.v:5948$1492_Y - connect \Y $and$ls180.v:5948$1493_Y + connect \A $and$ls180.v:5993$1457_Y + connect \B $eq$ls180.v:5993$1458_Y + connect \Y $and$ls180.v:5993$1459_Y end - attribute \src "ls180.v:5950.47-5950.100" - cell $and $and$ls180.v:5950$1494 + attribute \src "ls180.v:5995.46-5995.99" + cell $and $and$ls180.v:5995$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5950$1494_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5995$1460_Y end - attribute \src "ls180.v:5950.46-5950.151" - cell $and $and$ls180.v:5950$1496 + attribute \src "ls180.v:5995.45-5995.149" + cell $and $and$ls180.v:5995$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5950$1494_Y - connect \B $eq$ls180.v:5950$1495_Y - connect \Y $and$ls180.v:5950$1496_Y + connect \A $and$ls180.v:5995$1460_Y + connect \B $eq$ls180.v:5995$1461_Y + connect \Y $and$ls180.v:5995$1462_Y end - attribute \src "ls180.v:5951.47-5951.103" - cell $and $and$ls180.v:5951$1498 + attribute \src "ls180.v:5996.46-5996.102" + cell $and $and$ls180.v:5996$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5951$1497_Y - connect \Y $and$ls180.v:5951$1498_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5996$1463_Y + connect \Y $and$ls180.v:5996$1464_Y end - attribute \src "ls180.v:5951.46-5951.154" - cell $and $and$ls180.v:5951$1500 + attribute \src "ls180.v:5996.45-5996.152" + cell $and $and$ls180.v:5996$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1498_Y - connect \B $eq$ls180.v:5951$1499_Y - connect \Y $and$ls180.v:5951$1500_Y + connect \A $and$ls180.v:5996$1464_Y + connect \B $eq$ls180.v:5996$1465_Y + connect \Y $and$ls180.v:5996$1466_Y end - attribute \src "ls180.v:5953.47-5953.100" - cell $and $and$ls180.v:5953$1501 + attribute \src "ls180.v:5998.45-5998.98" + cell $and $and$ls180.v:5998$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5953$1501_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5998$1467_Y end - attribute \src "ls180.v:5953.46-5953.151" - cell $and $and$ls180.v:5953$1503 + attribute \src "ls180.v:5998.44-5998.148" + cell $and $and$ls180.v:5998$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5953$1501_Y - connect \B $eq$ls180.v:5953$1502_Y - connect \Y $and$ls180.v:5953$1503_Y + connect \A $and$ls180.v:5998$1467_Y + connect \B $eq$ls180.v:5998$1468_Y + connect \Y $and$ls180.v:5998$1469_Y end - attribute \src "ls180.v:5954.47-5954.103" - cell $and $and$ls180.v:5954$1505 + attribute \src "ls180.v:5999.45-5999.101" + cell $and $and$ls180.v:5999$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5954$1504_Y - connect \Y $and$ls180.v:5954$1505_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5999$1470_Y + connect \Y $and$ls180.v:5999$1471_Y end - attribute \src "ls180.v:5954.46-5954.154" - cell $and $and$ls180.v:5954$1507 + attribute \src "ls180.v:5999.44-5999.151" + cell $and $and$ls180.v:5999$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1505_Y - connect \B $eq$ls180.v:5954$1506_Y - connect \Y $and$ls180.v:5954$1507_Y + connect \A $and$ls180.v:5999$1471_Y + connect \B $eq$ls180.v:5999$1472_Y + connect \Y $and$ls180.v:5999$1473_Y end - attribute \src "ls180.v:5956.47-5956.100" - cell $and $and$ls180.v:5956$1508 + attribute \src "ls180.v:6001.45-6001.98" + cell $and $and$ls180.v:6001$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5956$1508_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6001$1474_Y end - attribute \src "ls180.v:5956.46-5956.151" - cell $and $and$ls180.v:5956$1510 + attribute \src "ls180.v:6001.44-6001.148" + cell $and $and$ls180.v:6001$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5956$1508_Y - connect \B $eq$ls180.v:5956$1509_Y - connect \Y $and$ls180.v:5956$1510_Y + connect \A $and$ls180.v:6001$1474_Y + connect \B $eq$ls180.v:6001$1475_Y + connect \Y $and$ls180.v:6001$1476_Y end - attribute \src "ls180.v:5957.47-5957.103" - cell $and $and$ls180.v:5957$1512 + attribute \src "ls180.v:6002.45-6002.101" + cell $and $and$ls180.v:6002$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5957$1511_Y - connect \Y $and$ls180.v:5957$1512_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6002$1477_Y + connect \Y $and$ls180.v:6002$1478_Y end - attribute \src "ls180.v:5957.46-5957.154" - cell $and $and$ls180.v:5957$1514 + attribute \src "ls180.v:6002.44-6002.151" + cell $and $and$ls180.v:6002$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1512_Y - connect \B $eq$ls180.v:5957$1513_Y - connect \Y $and$ls180.v:5957$1514_Y + connect \A $and$ls180.v:6002$1478_Y + connect \B $eq$ls180.v:6002$1479_Y + connect \Y $and$ls180.v:6002$1480_Y end - attribute \src "ls180.v:5959.47-5959.100" - cell $and $and$ls180.v:5959$1515 + attribute \src "ls180.v:6004.45-6004.98" + cell $and $and$ls180.v:6004$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5959$1515_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6004$1481_Y end - attribute \src "ls180.v:5959.46-5959.151" - cell $and $and$ls180.v:5959$1517 + attribute \src "ls180.v:6004.44-6004.148" + cell $and $and$ls180.v:6004$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5959$1515_Y - connect \B $eq$ls180.v:5959$1516_Y - connect \Y $and$ls180.v:5959$1517_Y + connect \A $and$ls180.v:6004$1481_Y + connect \B $eq$ls180.v:6004$1482_Y + connect \Y $and$ls180.v:6004$1483_Y end - attribute \src "ls180.v:5960.47-5960.103" - cell $and $and$ls180.v:5960$1519 + attribute \src "ls180.v:6005.45-6005.101" + cell $and $and$ls180.v:6005$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5960$1518_Y - connect \Y $and$ls180.v:5960$1519_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6005$1484_Y + connect \Y $and$ls180.v:6005$1485_Y end - attribute \src "ls180.v:5960.46-5960.154" - cell $and $and$ls180.v:5960$1521 + attribute \src "ls180.v:6005.44-6005.151" + cell $and $and$ls180.v:6005$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1519_Y - connect \B $eq$ls180.v:5960$1520_Y - connect \Y $and$ls180.v:5960$1521_Y + connect \A $and$ls180.v:6005$1485_Y + connect \B $eq$ls180.v:6005$1486_Y + connect \Y $and$ls180.v:6005$1487_Y end - attribute \src "ls180.v:5962.47-5962.100" - cell $and $and$ls180.v:5962$1522 + attribute \src "ls180.v:6007.45-6007.98" + cell $and $and$ls180.v:6007$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5962$1522_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6007$1488_Y end - attribute \src "ls180.v:5962.46-5962.151" - cell $and $and$ls180.v:5962$1524 + attribute \src "ls180.v:6007.44-6007.148" + cell $and $and$ls180.v:6007$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5962$1522_Y - connect \B $eq$ls180.v:5962$1523_Y - connect \Y $and$ls180.v:5962$1524_Y + connect \A $and$ls180.v:6007$1488_Y + connect \B $eq$ls180.v:6007$1489_Y + connect \Y $and$ls180.v:6007$1490_Y end - attribute \src "ls180.v:5963.47-5963.103" - cell $and $and$ls180.v:5963$1526 + attribute \src "ls180.v:6008.45-6008.101" + cell $and $and$ls180.v:6008$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5963$1525_Y - connect \Y $and$ls180.v:5963$1526_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6008$1491_Y + connect \Y $and$ls180.v:6008$1492_Y end - attribute \src "ls180.v:5963.46-5963.154" - cell $and $and$ls180.v:5963$1528 + attribute \src "ls180.v:6008.44-6008.151" + cell $and $and$ls180.v:6008$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1526_Y - connect \B $eq$ls180.v:5963$1527_Y - connect \Y $and$ls180.v:5963$1528_Y + connect \A $and$ls180.v:6008$1492_Y + connect \B $eq$ls180.v:6008$1493_Y + connect \Y $and$ls180.v:6008$1494_Y end - attribute \src "ls180.v:5965.46-5965.99" - cell $and $and$ls180.v:5965$1529 + attribute \src "ls180.v:6010.36-6010.89" + cell $and $and$ls180.v:6010$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5965$1529_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6010$1495_Y end - attribute \src "ls180.v:5965.45-5965.150" - cell $and $and$ls180.v:5965$1531 + attribute \src "ls180.v:6010.35-6010.139" + cell $and $and$ls180.v:6010$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5965$1529_Y - connect \B $eq$ls180.v:5965$1530_Y - connect \Y $and$ls180.v:5965$1531_Y + connect \A $and$ls180.v:6010$1495_Y + connect \B $eq$ls180.v:6010$1496_Y + connect \Y $and$ls180.v:6010$1497_Y end - attribute \src "ls180.v:5966.46-5966.102" - cell $and $and$ls180.v:5966$1533 + attribute \src "ls180.v:6011.36-6011.92" + cell $and $and$ls180.v:6011$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5966$1532_Y - connect \Y $and$ls180.v:5966$1533_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6011$1498_Y + connect \Y $and$ls180.v:6011$1499_Y end - attribute \src "ls180.v:5966.45-5966.153" - cell $and $and$ls180.v:5966$1535 + attribute \src "ls180.v:6011.35-6011.142" + cell $and $and$ls180.v:6011$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1533_Y - connect \B $eq$ls180.v:5966$1534_Y - connect \Y $and$ls180.v:5966$1535_Y + connect \A $and$ls180.v:6011$1499_Y + connect \B $eq$ls180.v:6011$1500_Y + connect \Y $and$ls180.v:6011$1501_Y end - attribute \src "ls180.v:5968.46-5968.99" - cell $and $and$ls180.v:5968$1536 + attribute \src "ls180.v:6013.47-6013.100" + cell $and $and$ls180.v:6013$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5968$1536_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6013$1502_Y end - attribute \src "ls180.v:5968.45-5968.150" - cell $and $and$ls180.v:5968$1538 + attribute \src "ls180.v:6013.46-6013.150" + cell $and $and$ls180.v:6013$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5968$1536_Y - connect \B $eq$ls180.v:5968$1537_Y - connect \Y $and$ls180.v:5968$1538_Y + connect \A $and$ls180.v:6013$1502_Y + connect \B $eq$ls180.v:6013$1503_Y + connect \Y $and$ls180.v:6013$1504_Y end - attribute \src "ls180.v:5969.46-5969.102" - cell $and $and$ls180.v:5969$1540 + attribute \src "ls180.v:6014.47-6014.103" + cell $and $and$ls180.v:6014$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5969$1539_Y - connect \Y $and$ls180.v:5969$1540_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6014$1505_Y + connect \Y $and$ls180.v:6014$1506_Y end - attribute \src "ls180.v:5969.45-5969.153" - cell $and $and$ls180.v:5969$1542 + attribute \src "ls180.v:6014.46-6014.153" + cell $and $and$ls180.v:6014$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5969$1540_Y - connect \B $eq$ls180.v:5969$1541_Y - connect \Y $and$ls180.v:5969$1542_Y + connect \A $and$ls180.v:6014$1506_Y + connect \B $eq$ls180.v:6014$1507_Y + connect \Y $and$ls180.v:6014$1508_Y end - attribute \src "ls180.v:5971.46-5971.99" - cell $and $and$ls180.v:5971$1543 + attribute \src "ls180.v:6016.47-6016.100" + cell $and $and$ls180.v:6016$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5971$1543_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6016$1509_Y end - attribute \src "ls180.v:5971.45-5971.150" - cell $and $and$ls180.v:5971$1545 + attribute \src "ls180.v:6016.46-6016.151" + cell $and $and$ls180.v:6016$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5971$1543_Y - connect \B $eq$ls180.v:5971$1544_Y - connect \Y $and$ls180.v:5971$1545_Y + connect \A $and$ls180.v:6016$1509_Y + connect \B $eq$ls180.v:6016$1510_Y + connect \Y $and$ls180.v:6016$1511_Y end - attribute \src "ls180.v:5972.46-5972.102" - cell $and $and$ls180.v:5972$1547 + attribute \src "ls180.v:6017.47-6017.103" + cell $and $and$ls180.v:6017$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5972$1546_Y - connect \Y $and$ls180.v:5972$1547_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6017$1512_Y + connect \Y $and$ls180.v:6017$1513_Y end - attribute \src "ls180.v:5972.45-5972.153" - cell $and $and$ls180.v:5972$1549 + attribute \src "ls180.v:6017.46-6017.154" + cell $and $and$ls180.v:6017$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5972$1547_Y - connect \B $eq$ls180.v:5972$1548_Y - connect \Y $and$ls180.v:5972$1549_Y + connect \A $and$ls180.v:6017$1513_Y + connect \B $eq$ls180.v:6017$1514_Y + connect \Y $and$ls180.v:6017$1515_Y end - attribute \src "ls180.v:5974.46-5974.99" - cell $and $and$ls180.v:5974$1550 + attribute \src "ls180.v:6019.47-6019.100" + cell $and $and$ls180.v:6019$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5974$1550_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6019$1516_Y end - attribute \src "ls180.v:5974.45-5974.150" - cell $and $and$ls180.v:5974$1552 + attribute \src "ls180.v:6019.46-6019.151" + cell $and $and$ls180.v:6019$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5974$1550_Y - connect \B $eq$ls180.v:5974$1551_Y - connect \Y $and$ls180.v:5974$1552_Y + connect \A $and$ls180.v:6019$1516_Y + connect \B $eq$ls180.v:6019$1517_Y + connect \Y $and$ls180.v:6019$1518_Y end - attribute \src "ls180.v:5975.46-5975.102" - cell $and $and$ls180.v:5975$1554 + attribute \src "ls180.v:6020.47-6020.103" + cell $and $and$ls180.v:6020$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5975$1553_Y - connect \Y $and$ls180.v:5975$1554_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6020$1519_Y + connect \Y $and$ls180.v:6020$1520_Y end - attribute \src "ls180.v:5975.45-5975.153" - cell $and $and$ls180.v:5975$1556 + attribute \src "ls180.v:6020.46-6020.154" + cell $and $and$ls180.v:6020$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5975$1554_Y - connect \B $eq$ls180.v:5975$1555_Y - connect \Y $and$ls180.v:5975$1556_Y + connect \A $and$ls180.v:6020$1520_Y + connect \B $eq$ls180.v:6020$1521_Y + connect \Y $and$ls180.v:6020$1522_Y end - attribute \src "ls180.v:5977.46-5977.99" - cell $and $and$ls180.v:5977$1557 + attribute \src "ls180.v:6022.47-6022.100" + cell $and $and$ls180.v:6022$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5977$1557_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6022$1523_Y end - attribute \src "ls180.v:5977.45-5977.150" - cell $and $and$ls180.v:5977$1559 + attribute \src "ls180.v:6022.46-6022.151" + cell $and $and$ls180.v:6022$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5977$1557_Y - connect \B $eq$ls180.v:5977$1558_Y - connect \Y $and$ls180.v:5977$1559_Y + connect \A $and$ls180.v:6022$1523_Y + connect \B $eq$ls180.v:6022$1524_Y + connect \Y $and$ls180.v:6022$1525_Y end - attribute \src "ls180.v:5978.46-5978.102" - cell $and $and$ls180.v:5978$1561 + attribute \src "ls180.v:6023.47-6023.103" + cell $and $and$ls180.v:6023$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5978$1560_Y - connect \Y $and$ls180.v:5978$1561_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6023$1526_Y + connect \Y $and$ls180.v:6023$1527_Y end - attribute \src "ls180.v:5978.45-5978.153" - cell $and $and$ls180.v:5978$1563 + attribute \src "ls180.v:6023.46-6023.154" + cell $and $and$ls180.v:6023$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5978$1561_Y - connect \B $eq$ls180.v:5978$1562_Y - connect \Y $and$ls180.v:5978$1563_Y + connect \A $and$ls180.v:6023$1527_Y + connect \B $eq$ls180.v:6023$1528_Y + connect \Y $and$ls180.v:6023$1529_Y end - attribute \src "ls180.v:5980.46-5980.99" - cell $and $and$ls180.v:5980$1564 + attribute \src "ls180.v:6025.47-6025.100" + cell $and $and$ls180.v:6025$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5980$1564_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6025$1530_Y end - attribute \src "ls180.v:5980.45-5980.150" - cell $and $and$ls180.v:5980$1566 + attribute \src "ls180.v:6025.46-6025.151" + cell $and $and$ls180.v:6025$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5980$1564_Y - connect \B $eq$ls180.v:5980$1565_Y - connect \Y $and$ls180.v:5980$1566_Y + connect \A $and$ls180.v:6025$1530_Y + connect \B $eq$ls180.v:6025$1531_Y + connect \Y $and$ls180.v:6025$1532_Y end - attribute \src "ls180.v:5981.46-5981.102" - cell $and $and$ls180.v:5981$1568 + attribute \src "ls180.v:6026.47-6026.103" + cell $and $and$ls180.v:6026$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5981$1567_Y - connect \Y $and$ls180.v:5981$1568_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6026$1533_Y + connect \Y $and$ls180.v:6026$1534_Y end - attribute \src "ls180.v:5981.45-5981.153" - cell $and $and$ls180.v:5981$1570 + attribute \src "ls180.v:6026.46-6026.154" + cell $and $and$ls180.v:6026$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5981$1568_Y - connect \B $eq$ls180.v:5981$1569_Y - connect \Y $and$ls180.v:5981$1570_Y + connect \A $and$ls180.v:6026$1534_Y + connect \B $eq$ls180.v:6026$1535_Y + connect \Y $and$ls180.v:6026$1536_Y end - attribute \src "ls180.v:5983.46-5983.99" - cell $and $and$ls180.v:5983$1571 + attribute \src "ls180.v:6028.47-6028.100" + cell $and $and$ls180.v:6028$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5983$1571_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6028$1537_Y end - attribute \src "ls180.v:5983.45-5983.150" - cell $and $and$ls180.v:5983$1573 + attribute \src "ls180.v:6028.46-6028.151" + cell $and $and$ls180.v:6028$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5983$1571_Y - connect \B $eq$ls180.v:5983$1572_Y - connect \Y $and$ls180.v:5983$1573_Y + connect \A $and$ls180.v:6028$1537_Y + connect \B $eq$ls180.v:6028$1538_Y + connect \Y $and$ls180.v:6028$1539_Y end - attribute \src "ls180.v:5984.46-5984.102" - cell $and $and$ls180.v:5984$1575 + attribute \src "ls180.v:6029.47-6029.103" + cell $and $and$ls180.v:6029$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5984$1574_Y - connect \Y $and$ls180.v:5984$1575_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6029$1540_Y + connect \Y $and$ls180.v:6029$1541_Y end - attribute \src "ls180.v:5984.45-5984.153" - cell $and $and$ls180.v:5984$1577 + attribute \src "ls180.v:6029.46-6029.154" + cell $and $and$ls180.v:6029$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5984$1575_Y - connect \B $eq$ls180.v:5984$1576_Y - connect \Y $and$ls180.v:5984$1577_Y + connect \A $and$ls180.v:6029$1541_Y + connect \B $eq$ls180.v:6029$1542_Y + connect \Y $and$ls180.v:6029$1543_Y end - attribute \src "ls180.v:5986.46-5986.99" - cell $and $and$ls180.v:5986$1578 + attribute \src "ls180.v:6031.46-6031.99" + cell $and $and$ls180.v:6031$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5986$1578_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6031$1544_Y end - attribute \src "ls180.v:5986.45-5986.150" - cell $and $and$ls180.v:5986$1580 + attribute \src "ls180.v:6031.45-6031.150" + cell $and $and$ls180.v:6031$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5986$1578_Y - connect \B $eq$ls180.v:5986$1579_Y - connect \Y $and$ls180.v:5986$1580_Y + connect \A $and$ls180.v:6031$1544_Y + connect \B $eq$ls180.v:6031$1545_Y + connect \Y $and$ls180.v:6031$1546_Y end - attribute \src "ls180.v:5987.46-5987.102" - cell $and $and$ls180.v:5987$1582 + attribute \src "ls180.v:6032.46-6032.102" + cell $and $and$ls180.v:6032$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5987$1581_Y - connect \Y $and$ls180.v:5987$1582_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6032$1547_Y + connect \Y $and$ls180.v:6032$1548_Y end - attribute \src "ls180.v:5987.45-5987.153" - cell $and $and$ls180.v:5987$1584 + attribute \src "ls180.v:6032.45-6032.153" + cell $and $and$ls180.v:6032$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5987$1582_Y - connect \B $eq$ls180.v:5987$1583_Y - connect \Y $and$ls180.v:5987$1584_Y + connect \A $and$ls180.v:6032$1548_Y + connect \B $eq$ls180.v:6032$1549_Y + connect \Y $and$ls180.v:6032$1550_Y end - attribute \src "ls180.v:5989.46-5989.99" - cell $and $and$ls180.v:5989$1585 + attribute \src "ls180.v:6034.46-6034.99" + cell $and $and$ls180.v:6034$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5989$1585_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6034$1551_Y end - attribute \src "ls180.v:5989.45-5989.150" - cell $and $and$ls180.v:5989$1587 + attribute \src "ls180.v:6034.45-6034.150" + cell $and $and$ls180.v:6034$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1585_Y - connect \B $eq$ls180.v:5989$1586_Y - connect \Y $and$ls180.v:5989$1587_Y + connect \A $and$ls180.v:6034$1551_Y + connect \B $eq$ls180.v:6034$1552_Y + connect \Y $and$ls180.v:6034$1553_Y end - attribute \src "ls180.v:5990.46-5990.102" - cell $and $and$ls180.v:5990$1589 + attribute \src "ls180.v:6035.46-6035.102" + cell $and $and$ls180.v:6035$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5990$1588_Y - connect \Y $and$ls180.v:5990$1589_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6035$1554_Y + connect \Y $and$ls180.v:6035$1555_Y end - attribute \src "ls180.v:5990.45-5990.153" - cell $and $and$ls180.v:5990$1591 + attribute \src "ls180.v:6035.45-6035.153" + cell $and $and$ls180.v:6035$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5990$1589_Y - connect \B $eq$ls180.v:5990$1590_Y - connect \Y $and$ls180.v:5990$1591_Y + connect \A $and$ls180.v:6035$1555_Y + connect \B $eq$ls180.v:6035$1556_Y + connect \Y $and$ls180.v:6035$1557_Y end - attribute \src "ls180.v:5992.46-5992.99" - cell $and $and$ls180.v:5992$1592 + attribute \src "ls180.v:6037.46-6037.99" + cell $and $and$ls180.v:6037$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5992$1592_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6037$1558_Y end - attribute \src "ls180.v:5992.45-5992.150" - cell $and $and$ls180.v:5992$1594 + attribute \src "ls180.v:6037.45-6037.150" + cell $and $and$ls180.v:6037$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1592_Y - connect \B $eq$ls180.v:5992$1593_Y - connect \Y $and$ls180.v:5992$1594_Y + connect \A $and$ls180.v:6037$1558_Y + connect \B $eq$ls180.v:6037$1559_Y + connect \Y $and$ls180.v:6037$1560_Y end - attribute \src "ls180.v:5993.46-5993.102" - cell $and $and$ls180.v:5993$1596 + attribute \src "ls180.v:6038.46-6038.102" + cell $and $and$ls180.v:6038$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5993$1595_Y - connect \Y $and$ls180.v:5993$1596_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6038$1561_Y + connect \Y $and$ls180.v:6038$1562_Y end - attribute \src "ls180.v:5993.45-5993.153" - cell $and $and$ls180.v:5993$1598 + attribute \src "ls180.v:6038.45-6038.153" + cell $and $and$ls180.v:6038$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5993$1596_Y - connect \B $eq$ls180.v:5993$1597_Y - connect \Y $and$ls180.v:5993$1598_Y + connect \A $and$ls180.v:6038$1562_Y + connect \B $eq$ls180.v:6038$1563_Y + connect \Y $and$ls180.v:6038$1564_Y end - attribute \src "ls180.v:5995.42-5995.95" - cell $and $and$ls180.v:5995$1599 + attribute \src "ls180.v:6040.46-6040.99" + cell $and $and$ls180.v:6040$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5995$1599_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6040$1565_Y end - attribute \src "ls180.v:5995.41-5995.146" - cell $and $and$ls180.v:5995$1601 + attribute \src "ls180.v:6040.45-6040.150" + cell $and $and$ls180.v:6040$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5995$1599_Y - connect \B $eq$ls180.v:5995$1600_Y - connect \Y $and$ls180.v:5995$1601_Y + connect \A $and$ls180.v:6040$1565_Y + connect \B $eq$ls180.v:6040$1566_Y + connect \Y $and$ls180.v:6040$1567_Y end - attribute \src "ls180.v:5996.42-5996.98" - cell $and $and$ls180.v:5996$1603 + attribute \src "ls180.v:6041.46-6041.102" + cell $and $and$ls180.v:6041$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5996$1602_Y - connect \Y $and$ls180.v:5996$1603_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6041$1568_Y + connect \Y $and$ls180.v:6041$1569_Y end - attribute \src "ls180.v:5996.41-5996.149" - cell $and $and$ls180.v:5996$1605 + attribute \src "ls180.v:6041.45-6041.153" + cell $and $and$ls180.v:6041$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5996$1603_Y - connect \B $eq$ls180.v:5996$1604_Y - connect \Y $and$ls180.v:5996$1605_Y + connect \A $and$ls180.v:6041$1569_Y + connect \B $eq$ls180.v:6041$1570_Y + connect \Y $and$ls180.v:6041$1571_Y end - attribute \src "ls180.v:5998.43-5998.96" - cell $and $and$ls180.v:5998$1606 + attribute \src "ls180.v:6043.46-6043.99" + cell $and $and$ls180.v:6043$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5998$1606_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6043$1572_Y end - attribute \src "ls180.v:5998.42-5998.147" - cell $and $and$ls180.v:5998$1608 + attribute \src "ls180.v:6043.45-6043.150" + cell $and $and$ls180.v:6043$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5998$1606_Y - connect \B $eq$ls180.v:5998$1607_Y - connect \Y $and$ls180.v:5998$1608_Y + connect \A $and$ls180.v:6043$1572_Y + connect \B $eq$ls180.v:6043$1573_Y + connect \Y $and$ls180.v:6043$1574_Y end - attribute \src "ls180.v:5999.43-5999.99" - cell $and $and$ls180.v:5999$1610 + attribute \src "ls180.v:6044.46-6044.102" + cell $and $and$ls180.v:6044$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5999$1609_Y - connect \Y $and$ls180.v:5999$1610_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6044$1575_Y + connect \Y $and$ls180.v:6044$1576_Y end - attribute \src "ls180.v:5999.42-5999.150" - cell $and $and$ls180.v:5999$1612 + attribute \src "ls180.v:6044.45-6044.153" + cell $and $and$ls180.v:6044$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5999$1610_Y - connect \B $eq$ls180.v:5999$1611_Y - connect \Y $and$ls180.v:5999$1612_Y + connect \A $and$ls180.v:6044$1576_Y + connect \B $eq$ls180.v:6044$1577_Y + connect \Y $and$ls180.v:6044$1578_Y end - attribute \src "ls180.v:6001.46-6001.99" - cell $and $and$ls180.v:6001$1613 + attribute \src "ls180.v:6046.46-6046.99" + cell $and $and$ls180.v:6046$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6001$1613_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6046$1579_Y end - attribute \src "ls180.v:6001.45-6001.150" - cell $and $and$ls180.v:6001$1615 + attribute \src "ls180.v:6046.45-6046.150" + cell $and $and$ls180.v:6046$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1613_Y - connect \B $eq$ls180.v:6001$1614_Y - connect \Y $and$ls180.v:6001$1615_Y + connect \A $and$ls180.v:6046$1579_Y + connect \B $eq$ls180.v:6046$1580_Y + connect \Y $and$ls180.v:6046$1581_Y end - attribute \src "ls180.v:6002.46-6002.102" - cell $and $and$ls180.v:6002$1617 + attribute \src "ls180.v:6047.46-6047.102" + cell $and $and$ls180.v:6047$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6002$1616_Y - connect \Y $and$ls180.v:6002$1617_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6047$1582_Y + connect \Y $and$ls180.v:6047$1583_Y end - attribute \src "ls180.v:6002.45-6002.153" - cell $and $and$ls180.v:6002$1619 + attribute \src "ls180.v:6047.45-6047.153" + cell $and $and$ls180.v:6047$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6002$1617_Y - connect \B $eq$ls180.v:6002$1618_Y - connect \Y $and$ls180.v:6002$1619_Y + connect \A $and$ls180.v:6047$1583_Y + connect \B $eq$ls180.v:6047$1584_Y + connect \Y $and$ls180.v:6047$1585_Y end - attribute \src "ls180.v:6004.46-6004.99" - cell $and $and$ls180.v:6004$1620 + attribute \src "ls180.v:6049.46-6049.99" + cell $and $and$ls180.v:6049$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6004$1620_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6049$1586_Y end - attribute \src "ls180.v:6004.45-6004.150" - cell $and $and$ls180.v:6004$1622 + attribute \src "ls180.v:6049.45-6049.150" + cell $and $and$ls180.v:6049$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1620_Y - connect \B $eq$ls180.v:6004$1621_Y - connect \Y $and$ls180.v:6004$1622_Y + connect \A $and$ls180.v:6049$1586_Y + connect \B $eq$ls180.v:6049$1587_Y + connect \Y $and$ls180.v:6049$1588_Y end - attribute \src "ls180.v:6005.46-6005.102" - cell $and $and$ls180.v:6005$1624 + attribute \src "ls180.v:6050.46-6050.102" + cell $and $and$ls180.v:6050$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6005$1623_Y - connect \Y $and$ls180.v:6005$1624_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6050$1589_Y + connect \Y $and$ls180.v:6050$1590_Y end - attribute \src "ls180.v:6005.45-6005.153" - cell $and $and$ls180.v:6005$1626 + attribute \src "ls180.v:6050.45-6050.153" + cell $and $and$ls180.v:6050$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1624_Y - connect \B $eq$ls180.v:6005$1625_Y - connect \Y $and$ls180.v:6005$1626_Y + connect \A $and$ls180.v:6050$1590_Y + connect \B $eq$ls180.v:6050$1591_Y + connect \Y $and$ls180.v:6050$1592_Y end - attribute \src "ls180.v:6007.45-6007.98" - cell $and $and$ls180.v:6007$1627 + attribute \src "ls180.v:6052.46-6052.99" + cell $and $and$ls180.v:6052$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6007$1627_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6052$1593_Y end - attribute \src "ls180.v:6007.44-6007.149" - cell $and $and$ls180.v:6007$1629 + attribute \src "ls180.v:6052.45-6052.150" + cell $and $and$ls180.v:6052$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1627_Y - connect \B $eq$ls180.v:6007$1628_Y - connect \Y $and$ls180.v:6007$1629_Y + connect \A $and$ls180.v:6052$1593_Y + connect \B $eq$ls180.v:6052$1594_Y + connect \Y $and$ls180.v:6052$1595_Y end - attribute \src "ls180.v:6008.45-6008.101" - cell $and $and$ls180.v:6008$1631 + attribute \src "ls180.v:6053.46-6053.102" + cell $and $and$ls180.v:6053$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6008$1630_Y - connect \Y $and$ls180.v:6008$1631_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6053$1596_Y + connect \Y $and$ls180.v:6053$1597_Y end - attribute \src "ls180.v:6008.44-6008.152" - cell $and $and$ls180.v:6008$1633 + attribute \src "ls180.v:6053.45-6053.153" + cell $and $and$ls180.v:6053$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1631_Y - connect \B $eq$ls180.v:6008$1632_Y - connect \Y $and$ls180.v:6008$1633_Y + connect \A $and$ls180.v:6053$1597_Y + connect \B $eq$ls180.v:6053$1598_Y + connect \Y $and$ls180.v:6053$1599_Y end - attribute \src "ls180.v:6010.45-6010.98" - cell $and $and$ls180.v:6010$1634 + attribute \src "ls180.v:6055.46-6055.99" + cell $and $and$ls180.v:6055$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6010$1634_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6055$1600_Y end - attribute \src "ls180.v:6010.44-6010.149" - cell $and $and$ls180.v:6010$1636 + attribute \src "ls180.v:6055.45-6055.150" + cell $and $and$ls180.v:6055$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1634_Y - connect \B $eq$ls180.v:6010$1635_Y - connect \Y $and$ls180.v:6010$1636_Y + connect \A $and$ls180.v:6055$1600_Y + connect \B $eq$ls180.v:6055$1601_Y + connect \Y $and$ls180.v:6055$1602_Y end - attribute \src "ls180.v:6011.45-6011.101" - cell $and $and$ls180.v:6011$1638 + attribute \src "ls180.v:6056.46-6056.102" + cell $and $and$ls180.v:6056$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6011$1637_Y - connect \Y $and$ls180.v:6011$1638_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6056$1603_Y + connect \Y $and$ls180.v:6056$1604_Y end - attribute \src "ls180.v:6011.44-6011.152" - cell $and $and$ls180.v:6011$1640 + attribute \src "ls180.v:6056.45-6056.153" + cell $and $and$ls180.v:6056$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1638_Y - connect \B $eq$ls180.v:6011$1639_Y - connect \Y $and$ls180.v:6011$1640_Y + connect \A $and$ls180.v:6056$1604_Y + connect \B $eq$ls180.v:6056$1605_Y + connect \Y $and$ls180.v:6056$1606_Y end - attribute \src "ls180.v:6013.45-6013.98" - cell $and $and$ls180.v:6013$1641 + attribute \src "ls180.v:6058.46-6058.99" + cell $and $and$ls180.v:6058$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6013$1641_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6058$1607_Y end - attribute \src "ls180.v:6013.44-6013.149" - cell $and $and$ls180.v:6013$1643 + attribute \src "ls180.v:6058.45-6058.150" + cell $and $and$ls180.v:6058$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1641_Y - connect \B $eq$ls180.v:6013$1642_Y - connect \Y $and$ls180.v:6013$1643_Y + connect \A $and$ls180.v:6058$1607_Y + connect \B $eq$ls180.v:6058$1608_Y + connect \Y $and$ls180.v:6058$1609_Y end - attribute \src "ls180.v:6014.45-6014.101" - cell $and $and$ls180.v:6014$1645 + attribute \src "ls180.v:6059.46-6059.102" + cell $and $and$ls180.v:6059$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6014$1644_Y - connect \Y $and$ls180.v:6014$1645_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6059$1610_Y + connect \Y $and$ls180.v:6059$1611_Y end - attribute \src "ls180.v:6014.44-6014.152" - cell $and $and$ls180.v:6014$1647 + attribute \src "ls180.v:6059.45-6059.153" + cell $and $and$ls180.v:6059$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1645_Y - connect \B $eq$ls180.v:6014$1646_Y - connect \Y $and$ls180.v:6014$1647_Y + connect \A $and$ls180.v:6059$1611_Y + connect \B $eq$ls180.v:6059$1612_Y + connect \Y $and$ls180.v:6059$1613_Y end - attribute \src "ls180.v:6016.45-6016.98" - cell $and $and$ls180.v:6016$1648 + attribute \src "ls180.v:6061.42-6061.95" + cell $and $and$ls180.v:6061$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6016$1648_Y + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6061$1614_Y end - attribute \src "ls180.v:6016.44-6016.149" - cell $and $and$ls180.v:6016$1650 + attribute \src "ls180.v:6061.41-6061.146" + cell $and $and$ls180.v:6061$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6016$1648_Y - connect \B $eq$ls180.v:6016$1649_Y - connect \Y $and$ls180.v:6016$1650_Y + connect \A $and$ls180.v:6061$1614_Y + connect \B $eq$ls180.v:6061$1615_Y + connect \Y $and$ls180.v:6061$1616_Y end - attribute \src "ls180.v:6017.45-6017.101" - cell $and $and$ls180.v:6017$1652 + attribute \src "ls180.v:6062.42-6062.98" + cell $and $and$ls180.v:6062$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6017$1651_Y - connect \Y $and$ls180.v:6017$1652_Y + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6062$1617_Y + connect \Y $and$ls180.v:6062$1618_Y end - attribute \src "ls180.v:6017.44-6017.152" - cell $and $and$ls180.v:6017$1654 + attribute \src "ls180.v:6062.41-6062.149" + cell $and $and$ls180.v:6062$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1652_Y - connect \B $eq$ls180.v:6017$1653_Y - connect \Y $and$ls180.v:6017$1654_Y + connect \A $and$ls180.v:6062$1618_Y + connect \B $eq$ls180.v:6062$1619_Y + connect \Y $and$ls180.v:6062$1620_Y end - attribute \src "ls180.v:6055.42-6055.95" - cell $and $and$ls180.v:6055$1656 + attribute \src "ls180.v:6064.43-6064.96" + cell $and $and$ls180.v:6064$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237934,43 +243231,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6055$1656_Y + connect \Y $and$ls180.v:6064$1621_Y end - attribute \src "ls180.v:6055.41-6055.145" - cell $and $and$ls180.v:6055$1658 + attribute \src "ls180.v:6064.42-6064.147" + cell $and $and$ls180.v:6064$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1656_Y - connect \B $eq$ls180.v:6055$1657_Y - connect \Y $and$ls180.v:6055$1658_Y + connect \A $and$ls180.v:6064$1621_Y + connect \B $eq$ls180.v:6064$1622_Y + connect \Y $and$ls180.v:6064$1623_Y end - attribute \src "ls180.v:6056.42-6056.98" - cell $and $and$ls180.v:6056$1660 + attribute \src "ls180.v:6065.43-6065.99" + cell $and $and$ls180.v:6065$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6056$1659_Y - connect \Y $and$ls180.v:6056$1660_Y + connect \B $not$ls180.v:6065$1624_Y + connect \Y $and$ls180.v:6065$1625_Y end - attribute \src "ls180.v:6056.41-6056.148" - cell $and $and$ls180.v:6056$1662 + attribute \src "ls180.v:6065.42-6065.150" + cell $and $and$ls180.v:6065$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1660_Y - connect \B $eq$ls180.v:6056$1661_Y - connect \Y $and$ls180.v:6056$1662_Y + connect \A $and$ls180.v:6065$1625_Y + connect \B $eq$ls180.v:6065$1626_Y + connect \Y $and$ls180.v:6065$1627_Y end - attribute \src "ls180.v:6058.42-6058.95" - cell $and $and$ls180.v:6058$1663 + attribute \src "ls180.v:6067.46-6067.99" + cell $and $and$ls180.v:6067$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -237978,43 +243275,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6058$1663_Y + connect \Y $and$ls180.v:6067$1628_Y end - attribute \src "ls180.v:6058.41-6058.145" - cell $and $and$ls180.v:6058$1665 + attribute \src "ls180.v:6067.45-6067.150" + cell $and $and$ls180.v:6067$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1663_Y - connect \B $eq$ls180.v:6058$1664_Y - connect \Y $and$ls180.v:6058$1665_Y + connect \A $and$ls180.v:6067$1628_Y + connect \B $eq$ls180.v:6067$1629_Y + connect \Y $and$ls180.v:6067$1630_Y end - attribute \src "ls180.v:6059.42-6059.98" - cell $and $and$ls180.v:6059$1667 + attribute \src "ls180.v:6068.46-6068.102" + cell $and $and$ls180.v:6068$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6059$1666_Y - connect \Y $and$ls180.v:6059$1667_Y + connect \B $not$ls180.v:6068$1631_Y + connect \Y $and$ls180.v:6068$1632_Y end - attribute \src "ls180.v:6059.41-6059.148" - cell $and $and$ls180.v:6059$1669 + attribute \src "ls180.v:6068.45-6068.153" + cell $and $and$ls180.v:6068$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1667_Y - connect \B $eq$ls180.v:6059$1668_Y - connect \Y $and$ls180.v:6059$1669_Y + connect \A $and$ls180.v:6068$1632_Y + connect \B $eq$ls180.v:6068$1633_Y + connect \Y $and$ls180.v:6068$1634_Y end - attribute \src "ls180.v:6061.42-6061.95" - cell $and $and$ls180.v:6061$1670 + attribute \src "ls180.v:6070.46-6070.99" + cell $and $and$ls180.v:6070$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238022,43 +243319,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6061$1670_Y + connect \Y $and$ls180.v:6070$1635_Y end - attribute \src "ls180.v:6061.41-6061.145" - cell $and $and$ls180.v:6061$1672 + attribute \src "ls180.v:6070.45-6070.150" + cell $and $and$ls180.v:6070$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1670_Y - connect \B $eq$ls180.v:6061$1671_Y - connect \Y $and$ls180.v:6061$1672_Y + connect \A $and$ls180.v:6070$1635_Y + connect \B $eq$ls180.v:6070$1636_Y + connect \Y $and$ls180.v:6070$1637_Y end - attribute \src "ls180.v:6062.42-6062.98" - cell $and $and$ls180.v:6062$1674 + attribute \src "ls180.v:6071.46-6071.102" + cell $and $and$ls180.v:6071$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6062$1673_Y - connect \Y $and$ls180.v:6062$1674_Y + connect \B $not$ls180.v:6071$1638_Y + connect \Y $and$ls180.v:6071$1639_Y end - attribute \src "ls180.v:6062.41-6062.148" - cell $and $and$ls180.v:6062$1676 + attribute \src "ls180.v:6071.45-6071.153" + cell $and $and$ls180.v:6071$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1674_Y - connect \B $eq$ls180.v:6062$1675_Y - connect \Y $and$ls180.v:6062$1676_Y + connect \A $and$ls180.v:6071$1639_Y + connect \B $eq$ls180.v:6071$1640_Y + connect \Y $and$ls180.v:6071$1641_Y end - attribute \src "ls180.v:6064.42-6064.95" - cell $and $and$ls180.v:6064$1677 + attribute \src "ls180.v:6073.45-6073.98" + cell $and $and$ls180.v:6073$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238066,43 +243363,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6064$1677_Y + connect \Y $and$ls180.v:6073$1642_Y end - attribute \src "ls180.v:6064.41-6064.145" - cell $and $and$ls180.v:6064$1679 + attribute \src "ls180.v:6073.44-6073.149" + cell $and $and$ls180.v:6073$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1677_Y - connect \B $eq$ls180.v:6064$1678_Y - connect \Y $and$ls180.v:6064$1679_Y + connect \A $and$ls180.v:6073$1642_Y + connect \B $eq$ls180.v:6073$1643_Y + connect \Y $and$ls180.v:6073$1644_Y end - attribute \src "ls180.v:6065.42-6065.98" - cell $and $and$ls180.v:6065$1681 + attribute \src "ls180.v:6074.45-6074.101" + cell $and $and$ls180.v:6074$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6065$1680_Y - connect \Y $and$ls180.v:6065$1681_Y + connect \B $not$ls180.v:6074$1645_Y + connect \Y $and$ls180.v:6074$1646_Y end - attribute \src "ls180.v:6065.41-6065.148" - cell $and $and$ls180.v:6065$1683 + attribute \src "ls180.v:6074.44-6074.152" + cell $and $and$ls180.v:6074$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1681_Y - connect \B $eq$ls180.v:6065$1682_Y - connect \Y $and$ls180.v:6065$1683_Y + connect \A $and$ls180.v:6074$1646_Y + connect \B $eq$ls180.v:6074$1647_Y + connect \Y $and$ls180.v:6074$1648_Y end - attribute \src "ls180.v:6067.42-6067.95" - cell $and $and$ls180.v:6067$1684 + attribute \src "ls180.v:6076.45-6076.98" + cell $and $and$ls180.v:6076$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238110,43 +243407,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6067$1684_Y + connect \Y $and$ls180.v:6076$1649_Y end - attribute \src "ls180.v:6067.41-6067.145" - cell $and $and$ls180.v:6067$1686 + attribute \src "ls180.v:6076.44-6076.149" + cell $and $and$ls180.v:6076$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1684_Y - connect \B $eq$ls180.v:6067$1685_Y - connect \Y $and$ls180.v:6067$1686_Y + connect \A $and$ls180.v:6076$1649_Y + connect \B $eq$ls180.v:6076$1650_Y + connect \Y $and$ls180.v:6076$1651_Y end - attribute \src "ls180.v:6068.42-6068.98" - cell $and $and$ls180.v:6068$1688 + attribute \src "ls180.v:6077.45-6077.101" + cell $and $and$ls180.v:6077$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6068$1687_Y - connect \Y $and$ls180.v:6068$1688_Y + connect \B $not$ls180.v:6077$1652_Y + connect \Y $and$ls180.v:6077$1653_Y end - attribute \src "ls180.v:6068.41-6068.148" - cell $and $and$ls180.v:6068$1690 + attribute \src "ls180.v:6077.44-6077.152" + cell $and $and$ls180.v:6077$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1688_Y - connect \B $eq$ls180.v:6068$1689_Y - connect \Y $and$ls180.v:6068$1690_Y + connect \A $and$ls180.v:6077$1653_Y + connect \B $eq$ls180.v:6077$1654_Y + connect \Y $and$ls180.v:6077$1655_Y end - attribute \src "ls180.v:6070.42-6070.95" - cell $and $and$ls180.v:6070$1691 + attribute \src "ls180.v:6079.45-6079.98" + cell $and $and$ls180.v:6079$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238154,43 +243451,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6070$1691_Y + connect \Y $and$ls180.v:6079$1656_Y end - attribute \src "ls180.v:6070.41-6070.145" - cell $and $and$ls180.v:6070$1693 + attribute \src "ls180.v:6079.44-6079.149" + cell $and $and$ls180.v:6079$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1691_Y - connect \B $eq$ls180.v:6070$1692_Y - connect \Y $and$ls180.v:6070$1693_Y + connect \A $and$ls180.v:6079$1656_Y + connect \B $eq$ls180.v:6079$1657_Y + connect \Y $and$ls180.v:6079$1658_Y end - attribute \src "ls180.v:6071.42-6071.98" - cell $and $and$ls180.v:6071$1695 + attribute \src "ls180.v:6080.45-6080.101" + cell $and $and$ls180.v:6080$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6071$1694_Y - connect \Y $and$ls180.v:6071$1695_Y + connect \B $not$ls180.v:6080$1659_Y + connect \Y $and$ls180.v:6080$1660_Y end - attribute \src "ls180.v:6071.41-6071.148" - cell $and $and$ls180.v:6071$1697 + attribute \src "ls180.v:6080.44-6080.152" + cell $and $and$ls180.v:6080$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6071$1695_Y - connect \B $eq$ls180.v:6071$1696_Y - connect \Y $and$ls180.v:6071$1697_Y + connect \A $and$ls180.v:6080$1660_Y + connect \B $eq$ls180.v:6080$1661_Y + connect \Y $and$ls180.v:6080$1662_Y end - attribute \src "ls180.v:6073.42-6073.95" - cell $and $and$ls180.v:6073$1698 + attribute \src "ls180.v:6082.45-6082.98" + cell $and $and$ls180.v:6082$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238198,571 +243495,483 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6073$1698_Y + connect \Y $and$ls180.v:6082$1663_Y end - attribute \src "ls180.v:6073.41-6073.145" - cell $and $and$ls180.v:6073$1700 + attribute \src "ls180.v:6082.44-6082.149" + cell $and $and$ls180.v:6082$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6073$1698_Y - connect \B $eq$ls180.v:6073$1699_Y - connect \Y $and$ls180.v:6073$1700_Y + connect \A $and$ls180.v:6082$1663_Y + connect \B $eq$ls180.v:6082$1664_Y + connect \Y $and$ls180.v:6082$1665_Y end - attribute \src "ls180.v:6074.42-6074.98" - cell $and $and$ls180.v:6074$1702 + attribute \src "ls180.v:6083.45-6083.101" + cell $and $and$ls180.v:6083$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6074$1701_Y - connect \Y $and$ls180.v:6074$1702_Y + connect \B $not$ls180.v:6083$1666_Y + connect \Y $and$ls180.v:6083$1667_Y end - attribute \src "ls180.v:6074.41-6074.148" - cell $and $and$ls180.v:6074$1704 + attribute \src "ls180.v:6083.44-6083.152" + cell $and $and$ls180.v:6083$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6074$1702_Y - connect \B $eq$ls180.v:6074$1703_Y - connect \Y $and$ls180.v:6074$1704_Y + connect \A $and$ls180.v:6083$1667_Y + connect \B $eq$ls180.v:6083$1668_Y + connect \Y $and$ls180.v:6083$1669_Y end - attribute \src "ls180.v:6076.42-6076.95" - cell $and $and$ls180.v:6076$1705 + attribute \src "ls180.v:6121.42-6121.95" + cell $and $and$ls180.v:6121$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6076$1705_Y - end - attribute \src "ls180.v:6076.41-6076.145" - cell $and $and$ls180.v:6076$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6076$1705_Y - connect \B $eq$ls180.v:6076$1706_Y - connect \Y $and$ls180.v:6076$1707_Y - end - attribute \src "ls180.v:6077.42-6077.98" - cell $and $and$ls180.v:6077$1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6077$1708_Y - connect \Y $and$ls180.v:6077$1709_Y - end - attribute \src "ls180.v:6077.41-6077.148" - cell $and $and$ls180.v:6077$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6077$1709_Y - connect \B $eq$ls180.v:6077$1710_Y - connect \Y $and$ls180.v:6077$1711_Y - end - attribute \src "ls180.v:6079.44-6079.97" - cell $and $and$ls180.v:6079$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6079$1712_Y - end - attribute \src "ls180.v:6079.43-6079.147" - cell $and $and$ls180.v:6079$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6079$1712_Y - connect \B $eq$ls180.v:6079$1713_Y - connect \Y $and$ls180.v:6079$1714_Y - end - attribute \src "ls180.v:6080.44-6080.100" - cell $and $and$ls180.v:6080$1716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6080$1715_Y - connect \Y $and$ls180.v:6080$1716_Y - end - attribute \src "ls180.v:6080.43-6080.150" - cell $and $and$ls180.v:6080$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6080$1716_Y - connect \B $eq$ls180.v:6080$1717_Y - connect \Y $and$ls180.v:6080$1718_Y - end - attribute \src "ls180.v:6082.44-6082.97" - cell $and $and$ls180.v:6082$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6082$1719_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6121$1671_Y end - attribute \src "ls180.v:6082.43-6082.147" - cell $and $and$ls180.v:6082$1721 + attribute \src "ls180.v:6121.41-6121.145" + cell $and $and$ls180.v:6121$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1719_Y - connect \B $eq$ls180.v:6082$1720_Y - connect \Y $and$ls180.v:6082$1721_Y + connect \A $and$ls180.v:6121$1671_Y + connect \B $eq$ls180.v:6121$1672_Y + connect \Y $and$ls180.v:6121$1673_Y end - attribute \src "ls180.v:6083.44-6083.100" - cell $and $and$ls180.v:6083$1723 + attribute \src "ls180.v:6122.42-6122.98" + cell $and $and$ls180.v:6122$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6083$1722_Y - connect \Y $and$ls180.v:6083$1723_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6122$1674_Y + connect \Y $and$ls180.v:6122$1675_Y end - attribute \src "ls180.v:6083.43-6083.150" - cell $and $and$ls180.v:6083$1725 + attribute \src "ls180.v:6122.41-6122.148" + cell $and $and$ls180.v:6122$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6083$1723_Y - connect \B $eq$ls180.v:6083$1724_Y - connect \Y $and$ls180.v:6083$1725_Y + connect \A $and$ls180.v:6122$1675_Y + connect \B $eq$ls180.v:6122$1676_Y + connect \Y $and$ls180.v:6122$1677_Y end - attribute \src "ls180.v:6085.44-6085.97" - cell $and $and$ls180.v:6085$1726 + attribute \src "ls180.v:6124.42-6124.95" + cell $and $and$ls180.v:6124$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6085$1726_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6124$1678_Y end - attribute \src "ls180.v:6085.43-6085.148" - cell $and $and$ls180.v:6085$1728 + attribute \src "ls180.v:6124.41-6124.145" + cell $and $and$ls180.v:6124$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1726_Y - connect \B $eq$ls180.v:6085$1727_Y - connect \Y $and$ls180.v:6085$1728_Y + connect \A $and$ls180.v:6124$1678_Y + connect \B $eq$ls180.v:6124$1679_Y + connect \Y $and$ls180.v:6124$1680_Y end - attribute \src "ls180.v:6086.44-6086.100" - cell $and $and$ls180.v:6086$1730 + attribute \src "ls180.v:6125.42-6125.98" + cell $and $and$ls180.v:6125$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6086$1729_Y - connect \Y $and$ls180.v:6086$1730_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6125$1681_Y + connect \Y $and$ls180.v:6125$1682_Y end - attribute \src "ls180.v:6086.43-6086.151" - cell $and $and$ls180.v:6086$1732 + attribute \src "ls180.v:6125.41-6125.148" + cell $and $and$ls180.v:6125$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6086$1730_Y - connect \B $eq$ls180.v:6086$1731_Y - connect \Y $and$ls180.v:6086$1732_Y + connect \A $and$ls180.v:6125$1682_Y + connect \B $eq$ls180.v:6125$1683_Y + connect \Y $and$ls180.v:6125$1684_Y end - attribute \src "ls180.v:6088.44-6088.97" - cell $and $and$ls180.v:6088$1733 + attribute \src "ls180.v:6127.42-6127.95" + cell $and $and$ls180.v:6127$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6088$1733_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6127$1685_Y end - attribute \src "ls180.v:6088.43-6088.148" - cell $and $and$ls180.v:6088$1735 + attribute \src "ls180.v:6127.41-6127.145" + cell $and $and$ls180.v:6127$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1733_Y - connect \B $eq$ls180.v:6088$1734_Y - connect \Y $and$ls180.v:6088$1735_Y + connect \A $and$ls180.v:6127$1685_Y + connect \B $eq$ls180.v:6127$1686_Y + connect \Y $and$ls180.v:6127$1687_Y end - attribute \src "ls180.v:6089.44-6089.100" - cell $and $and$ls180.v:6089$1737 + attribute \src "ls180.v:6128.42-6128.98" + cell $and $and$ls180.v:6128$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6089$1736_Y - connect \Y $and$ls180.v:6089$1737_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6128$1688_Y + connect \Y $and$ls180.v:6128$1689_Y end - attribute \src "ls180.v:6089.43-6089.151" - cell $and $and$ls180.v:6089$1739 + attribute \src "ls180.v:6128.41-6128.148" + cell $and $and$ls180.v:6128$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6089$1737_Y - connect \B $eq$ls180.v:6089$1738_Y - connect \Y $and$ls180.v:6089$1739_Y + connect \A $and$ls180.v:6128$1689_Y + connect \B $eq$ls180.v:6128$1690_Y + connect \Y $and$ls180.v:6128$1691_Y end - attribute \src "ls180.v:6091.44-6091.97" - cell $and $and$ls180.v:6091$1740 + attribute \src "ls180.v:6130.42-6130.95" + cell $and $and$ls180.v:6130$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6091$1740_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6130$1692_Y end - attribute \src "ls180.v:6091.43-6091.148" - cell $and $and$ls180.v:6091$1742 + attribute \src "ls180.v:6130.41-6130.145" + cell $and $and$ls180.v:6130$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1740_Y - connect \B $eq$ls180.v:6091$1741_Y - connect \Y $and$ls180.v:6091$1742_Y + connect \A $and$ls180.v:6130$1692_Y + connect \B $eq$ls180.v:6130$1693_Y + connect \Y $and$ls180.v:6130$1694_Y end - attribute \src "ls180.v:6092.44-6092.100" - cell $and $and$ls180.v:6092$1744 + attribute \src "ls180.v:6131.42-6131.98" + cell $and $and$ls180.v:6131$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6092$1743_Y - connect \Y $and$ls180.v:6092$1744_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6131$1695_Y + connect \Y $and$ls180.v:6131$1696_Y end - attribute \src "ls180.v:6092.43-6092.151" - cell $and $and$ls180.v:6092$1746 + attribute \src "ls180.v:6131.41-6131.148" + cell $and $and$ls180.v:6131$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6092$1744_Y - connect \B $eq$ls180.v:6092$1745_Y - connect \Y $and$ls180.v:6092$1746_Y + connect \A $and$ls180.v:6131$1696_Y + connect \B $eq$ls180.v:6131$1697_Y + connect \Y $and$ls180.v:6131$1698_Y end - attribute \src "ls180.v:6094.41-6094.94" - cell $and $and$ls180.v:6094$1747 + attribute \src "ls180.v:6133.42-6133.95" + cell $and $and$ls180.v:6133$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6094$1747_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6133$1699_Y end - attribute \src "ls180.v:6094.40-6094.145" - cell $and $and$ls180.v:6094$1749 + attribute \src "ls180.v:6133.41-6133.145" + cell $and $and$ls180.v:6133$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1747_Y - connect \B $eq$ls180.v:6094$1748_Y - connect \Y $and$ls180.v:6094$1749_Y + connect \A $and$ls180.v:6133$1699_Y + connect \B $eq$ls180.v:6133$1700_Y + connect \Y $and$ls180.v:6133$1701_Y end - attribute \src "ls180.v:6095.41-6095.97" - cell $and $and$ls180.v:6095$1751 + attribute \src "ls180.v:6134.42-6134.98" + cell $and $and$ls180.v:6134$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6095$1750_Y - connect \Y $and$ls180.v:6095$1751_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6134$1702_Y + connect \Y $and$ls180.v:6134$1703_Y end - attribute \src "ls180.v:6095.40-6095.148" - cell $and $and$ls180.v:6095$1753 + attribute \src "ls180.v:6134.41-6134.148" + cell $and $and$ls180.v:6134$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6095$1751_Y - connect \B $eq$ls180.v:6095$1752_Y - connect \Y $and$ls180.v:6095$1753_Y + connect \A $and$ls180.v:6134$1703_Y + connect \B $eq$ls180.v:6134$1704_Y + connect \Y $and$ls180.v:6134$1705_Y end - attribute \src "ls180.v:6097.42-6097.95" - cell $and $and$ls180.v:6097$1754 + attribute \src "ls180.v:6136.42-6136.95" + cell $and $and$ls180.v:6136$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6097$1754_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6136$1706_Y end - attribute \src "ls180.v:6097.41-6097.146" - cell $and $and$ls180.v:6097$1756 + attribute \src "ls180.v:6136.41-6136.145" + cell $and $and$ls180.v:6136$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1754_Y - connect \B $eq$ls180.v:6097$1755_Y - connect \Y $and$ls180.v:6097$1756_Y + connect \A $and$ls180.v:6136$1706_Y + connect \B $eq$ls180.v:6136$1707_Y + connect \Y $and$ls180.v:6136$1708_Y end - attribute \src "ls180.v:6098.42-6098.98" - cell $and $and$ls180.v:6098$1758 + attribute \src "ls180.v:6137.42-6137.98" + cell $and $and$ls180.v:6137$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6098$1757_Y - connect \Y $and$ls180.v:6098$1758_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6137$1709_Y + connect \Y $and$ls180.v:6137$1710_Y end - attribute \src "ls180.v:6098.41-6098.149" - cell $and $and$ls180.v:6098$1760 + attribute \src "ls180.v:6137.41-6137.148" + cell $and $and$ls180.v:6137$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6098$1758_Y - connect \B $eq$ls180.v:6098$1759_Y - connect \Y $and$ls180.v:6098$1760_Y + connect \A $and$ls180.v:6137$1710_Y + connect \B $eq$ls180.v:6137$1711_Y + connect \Y $and$ls180.v:6137$1712_Y end - attribute \src "ls180.v:6100.44-6100.97" - cell $and $and$ls180.v:6100$1761 + attribute \src "ls180.v:6139.42-6139.95" + cell $and $and$ls180.v:6139$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6100$1761_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6139$1713_Y end - attribute \src "ls180.v:6100.43-6100.148" - cell $and $and$ls180.v:6100$1763 + attribute \src "ls180.v:6139.41-6139.145" + cell $and $and$ls180.v:6139$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1761_Y - connect \B $eq$ls180.v:6100$1762_Y - connect \Y $and$ls180.v:6100$1763_Y + connect \A $and$ls180.v:6139$1713_Y + connect \B $eq$ls180.v:6139$1714_Y + connect \Y $and$ls180.v:6139$1715_Y end - attribute \src "ls180.v:6101.44-6101.100" - cell $and $and$ls180.v:6101$1765 + attribute \src "ls180.v:6140.42-6140.98" + cell $and $and$ls180.v:6140$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6101$1764_Y - connect \Y $and$ls180.v:6101$1765_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6140$1716_Y + connect \Y $and$ls180.v:6140$1717_Y end - attribute \src "ls180.v:6101.43-6101.151" - cell $and $and$ls180.v:6101$1767 + attribute \src "ls180.v:6140.41-6140.148" + cell $and $and$ls180.v:6140$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6101$1765_Y - connect \B $eq$ls180.v:6101$1766_Y - connect \Y $and$ls180.v:6101$1767_Y + connect \A $and$ls180.v:6140$1717_Y + connect \B $eq$ls180.v:6140$1718_Y + connect \Y $and$ls180.v:6140$1719_Y end - attribute \src "ls180.v:6103.44-6103.97" - cell $and $and$ls180.v:6103$1768 + attribute \src "ls180.v:6142.42-6142.95" + cell $and $and$ls180.v:6142$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6103$1768_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6142$1720_Y end - attribute \src "ls180.v:6103.43-6103.148" - cell $and $and$ls180.v:6103$1770 + attribute \src "ls180.v:6142.41-6142.145" + cell $and $and$ls180.v:6142$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6103$1768_Y - connect \B $eq$ls180.v:6103$1769_Y - connect \Y $and$ls180.v:6103$1770_Y + connect \A $and$ls180.v:6142$1720_Y + connect \B $eq$ls180.v:6142$1721_Y + connect \Y $and$ls180.v:6142$1722_Y end - attribute \src "ls180.v:6104.44-6104.100" - cell $and $and$ls180.v:6104$1772 + attribute \src "ls180.v:6143.42-6143.98" + cell $and $and$ls180.v:6143$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6104$1771_Y - connect \Y $and$ls180.v:6104$1772_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6143$1723_Y + connect \Y $and$ls180.v:6143$1724_Y end - attribute \src "ls180.v:6104.43-6104.151" - cell $and $and$ls180.v:6104$1774 + attribute \src "ls180.v:6143.41-6143.148" + cell $and $and$ls180.v:6143$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6104$1772_Y - connect \B $eq$ls180.v:6104$1773_Y - connect \Y $and$ls180.v:6104$1774_Y + connect \A $and$ls180.v:6143$1724_Y + connect \B $eq$ls180.v:6143$1725_Y + connect \Y $and$ls180.v:6143$1726_Y end - attribute \src "ls180.v:6106.44-6106.97" - cell $and $and$ls180.v:6106$1775 + attribute \src "ls180.v:6145.44-6145.97" + cell $and $and$ls180.v:6145$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6106$1775_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6145$1727_Y end - attribute \src "ls180.v:6106.43-6106.148" - cell $and $and$ls180.v:6106$1777 + attribute \src "ls180.v:6145.43-6145.147" + cell $and $and$ls180.v:6145$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6106$1775_Y - connect \B $eq$ls180.v:6106$1776_Y - connect \Y $and$ls180.v:6106$1777_Y + connect \A $and$ls180.v:6145$1727_Y + connect \B $eq$ls180.v:6145$1728_Y + connect \Y $and$ls180.v:6145$1729_Y end - attribute \src "ls180.v:6107.44-6107.100" - cell $and $and$ls180.v:6107$1779 + attribute \src "ls180.v:6146.44-6146.100" + cell $and $and$ls180.v:6146$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6107$1778_Y - connect \Y $and$ls180.v:6107$1779_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6146$1730_Y + connect \Y $and$ls180.v:6146$1731_Y end - attribute \src "ls180.v:6107.43-6107.151" - cell $and $and$ls180.v:6107$1781 + attribute \src "ls180.v:6146.43-6146.150" + cell $and $and$ls180.v:6146$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$1779_Y - connect \B $eq$ls180.v:6107$1780_Y - connect \Y $and$ls180.v:6107$1781_Y + connect \A $and$ls180.v:6146$1731_Y + connect \B $eq$ls180.v:6146$1732_Y + connect \Y $and$ls180.v:6146$1733_Y end - attribute \src "ls180.v:6109.44-6109.97" - cell $and $and$ls180.v:6109$1782 + attribute \src "ls180.v:6148.44-6148.97" + cell $and $and$ls180.v:6148$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6109$1782_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6148$1734_Y end - attribute \src "ls180.v:6109.43-6109.148" - cell $and $and$ls180.v:6109$1784 + attribute \src "ls180.v:6148.43-6148.147" + cell $and $and$ls180.v:6148$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6109$1782_Y - connect \B $eq$ls180.v:6109$1783_Y - connect \Y $and$ls180.v:6109$1784_Y + connect \A $and$ls180.v:6148$1734_Y + connect \B $eq$ls180.v:6148$1735_Y + connect \Y $and$ls180.v:6148$1736_Y end - attribute \src "ls180.v:6110.44-6110.100" - cell $and $and$ls180.v:6110$1786 + attribute \src "ls180.v:6149.44-6149.100" + cell $and $and$ls180.v:6149$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6110$1785_Y - connect \Y $and$ls180.v:6110$1786_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6149$1737_Y + connect \Y $and$ls180.v:6149$1738_Y end - attribute \src "ls180.v:6110.43-6110.151" - cell $and $and$ls180.v:6110$1788 + attribute \src "ls180.v:6149.43-6149.150" + cell $and $and$ls180.v:6149$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1786_Y - connect \B $eq$ls180.v:6110$1787_Y - connect \Y $and$ls180.v:6110$1788_Y + connect \A $and$ls180.v:6149$1738_Y + connect \B $eq$ls180.v:6149$1739_Y + connect \Y $and$ls180.v:6149$1740_Y end - attribute \src "ls180.v:6134.44-6134.97" - cell $and $and$ls180.v:6134$1790 + attribute \src "ls180.v:6151.44-6151.97" + cell $and $and$ls180.v:6151$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238770,43 +243979,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6134$1790_Y + connect \Y $and$ls180.v:6151$1741_Y end - attribute \src "ls180.v:6134.43-6134.147" - cell $and $and$ls180.v:6134$1792 + attribute \src "ls180.v:6151.43-6151.148" + cell $and $and$ls180.v:6151$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1790_Y - connect \B $eq$ls180.v:6134$1791_Y - connect \Y $and$ls180.v:6134$1792_Y + connect \A $and$ls180.v:6151$1741_Y + connect \B $eq$ls180.v:6151$1742_Y + connect \Y $and$ls180.v:6151$1743_Y end - attribute \src "ls180.v:6135.44-6135.100" - cell $and $and$ls180.v:6135$1794 + attribute \src "ls180.v:6152.44-6152.100" + cell $and $and$ls180.v:6152$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6135$1793_Y - connect \Y $and$ls180.v:6135$1794_Y + connect \B $not$ls180.v:6152$1744_Y + connect \Y $and$ls180.v:6152$1745_Y end - attribute \src "ls180.v:6135.43-6135.150" - cell $and $and$ls180.v:6135$1796 + attribute \src "ls180.v:6152.43-6152.151" + cell $and $and$ls180.v:6152$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1794_Y - connect \B $eq$ls180.v:6135$1795_Y - connect \Y $and$ls180.v:6135$1796_Y + connect \A $and$ls180.v:6152$1745_Y + connect \B $eq$ls180.v:6152$1746_Y + connect \Y $and$ls180.v:6152$1747_Y end - attribute \src "ls180.v:6137.49-6137.102" - cell $and $and$ls180.v:6137$1797 + attribute \src "ls180.v:6154.44-6154.97" + cell $and $and$ls180.v:6154$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238814,43 +244023,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6137$1797_Y + connect \Y $and$ls180.v:6154$1748_Y end - attribute \src "ls180.v:6137.48-6137.152" - cell $and $and$ls180.v:6137$1799 + attribute \src "ls180.v:6154.43-6154.148" + cell $and $and$ls180.v:6154$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1797_Y - connect \B $eq$ls180.v:6137$1798_Y - connect \Y $and$ls180.v:6137$1799_Y + connect \A $and$ls180.v:6154$1748_Y + connect \B $eq$ls180.v:6154$1749_Y + connect \Y $and$ls180.v:6154$1750_Y end - attribute \src "ls180.v:6138.49-6138.105" - cell $and $and$ls180.v:6138$1801 + attribute \src "ls180.v:6155.44-6155.100" + cell $and $and$ls180.v:6155$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6138$1800_Y - connect \Y $and$ls180.v:6138$1801_Y + connect \B $not$ls180.v:6155$1751_Y + connect \Y $and$ls180.v:6155$1752_Y end - attribute \src "ls180.v:6138.48-6138.155" - cell $and $and$ls180.v:6138$1803 + attribute \src "ls180.v:6155.43-6155.151" + cell $and $and$ls180.v:6155$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1801_Y - connect \B $eq$ls180.v:6138$1802_Y - connect \Y $and$ls180.v:6138$1803_Y + connect \A $and$ls180.v:6155$1752_Y + connect \B $eq$ls180.v:6155$1753_Y + connect \Y $and$ls180.v:6155$1754_Y end - attribute \src "ls180.v:6140.49-6140.102" - cell $and $and$ls180.v:6140$1804 + attribute \src "ls180.v:6157.44-6157.97" + cell $and $and$ls180.v:6157$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238858,43 +244067,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6140$1804_Y + connect \Y $and$ls180.v:6157$1755_Y end - attribute \src "ls180.v:6140.48-6140.152" - cell $and $and$ls180.v:6140$1806 + attribute \src "ls180.v:6157.43-6157.148" + cell $and $and$ls180.v:6157$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1804_Y - connect \B $eq$ls180.v:6140$1805_Y - connect \Y $and$ls180.v:6140$1806_Y + connect \A $and$ls180.v:6157$1755_Y + connect \B $eq$ls180.v:6157$1756_Y + connect \Y $and$ls180.v:6157$1757_Y end - attribute \src "ls180.v:6141.49-6141.105" - cell $and $and$ls180.v:6141$1808 + attribute \src "ls180.v:6158.44-6158.100" + cell $and $and$ls180.v:6158$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6141$1807_Y - connect \Y $and$ls180.v:6141$1808_Y + connect \B $not$ls180.v:6158$1758_Y + connect \Y $and$ls180.v:6158$1759_Y end - attribute \src "ls180.v:6141.48-6141.155" - cell $and $and$ls180.v:6141$1810 + attribute \src "ls180.v:6158.43-6158.151" + cell $and $and$ls180.v:6158$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1808_Y - connect \B $eq$ls180.v:6141$1809_Y - connect \Y $and$ls180.v:6141$1810_Y + connect \A $and$ls180.v:6158$1759_Y + connect \B $eq$ls180.v:6158$1760_Y + connect \Y $and$ls180.v:6158$1761_Y end - attribute \src "ls180.v:6143.42-6143.95" - cell $and $and$ls180.v:6143$1811 + attribute \src "ls180.v:6160.41-6160.94" + cell $and $and$ls180.v:6160$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238902,263 +244111,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6143$1811_Y + connect \Y $and$ls180.v:6160$1762_Y end - attribute \src "ls180.v:6143.41-6143.145" - cell $and $and$ls180.v:6143$1813 + attribute \src "ls180.v:6160.40-6160.145" + cell $and $and$ls180.v:6160$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1811_Y - connect \B $eq$ls180.v:6143$1812_Y - connect \Y $and$ls180.v:6143$1813_Y + connect \A $and$ls180.v:6160$1762_Y + connect \B $eq$ls180.v:6160$1763_Y + connect \Y $and$ls180.v:6160$1764_Y end - attribute \src "ls180.v:6144.42-6144.98" - cell $and $and$ls180.v:6144$1815 + attribute \src "ls180.v:6161.41-6161.97" + cell $and $and$ls180.v:6161$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6144$1814_Y - connect \Y $and$ls180.v:6144$1815_Y + connect \B $not$ls180.v:6161$1765_Y + connect \Y $and$ls180.v:6161$1766_Y end - attribute \src "ls180.v:6144.41-6144.148" - cell $and $and$ls180.v:6144$1817 + attribute \src "ls180.v:6161.40-6161.148" + cell $and $and$ls180.v:6161$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1815_Y - connect \B $eq$ls180.v:6144$1816_Y - connect \Y $and$ls180.v:6144$1817_Y + connect \A $and$ls180.v:6161$1766_Y + connect \B $eq$ls180.v:6161$1767_Y + connect \Y $and$ls180.v:6161$1768_Y end - attribute \src "ls180.v:6151.46-6151.99" - cell $and $and$ls180.v:6151$1819 + attribute \src "ls180.v:6163.42-6163.95" + cell $and $and$ls180.v:6163$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6151$1819_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6163$1769_Y end - attribute \src "ls180.v:6151.45-6151.149" - cell $and $and$ls180.v:6151$1821 + attribute \src "ls180.v:6163.41-6163.146" + cell $and $and$ls180.v:6163$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6151$1819_Y - connect \B $eq$ls180.v:6151$1820_Y - connect \Y $and$ls180.v:6151$1821_Y + connect \A $and$ls180.v:6163$1769_Y + connect \B $eq$ls180.v:6163$1770_Y + connect \Y $and$ls180.v:6163$1771_Y end - attribute \src "ls180.v:6152.46-6152.102" - cell $and $and$ls180.v:6152$1823 + attribute \src "ls180.v:6164.42-6164.98" + cell $and $and$ls180.v:6164$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6152$1822_Y - connect \Y $and$ls180.v:6152$1823_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6164$1772_Y + connect \Y $and$ls180.v:6164$1773_Y end - attribute \src "ls180.v:6152.45-6152.152" - cell $and $and$ls180.v:6152$1825 + attribute \src "ls180.v:6164.41-6164.149" + cell $and $and$ls180.v:6164$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6152$1823_Y - connect \B $eq$ls180.v:6152$1824_Y - connect \Y $and$ls180.v:6152$1825_Y + connect \A $and$ls180.v:6164$1773_Y + connect \B $eq$ls180.v:6164$1774_Y + connect \Y $and$ls180.v:6164$1775_Y end - attribute \src "ls180.v:6154.50-6154.103" - cell $and $and$ls180.v:6154$1826 + attribute \src "ls180.v:6166.44-6166.97" + cell $and $and$ls180.v:6166$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6154$1826_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6166$1776_Y end - attribute \src "ls180.v:6154.49-6154.153" - cell $and $and$ls180.v:6154$1828 + attribute \src "ls180.v:6166.43-6166.148" + cell $and $and$ls180.v:6166$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6154$1826_Y - connect \B $eq$ls180.v:6154$1827_Y - connect \Y $and$ls180.v:6154$1828_Y + connect \A $and$ls180.v:6166$1776_Y + connect \B $eq$ls180.v:6166$1777_Y + connect \Y $and$ls180.v:6166$1778_Y end - attribute \src "ls180.v:6155.50-6155.106" - cell $and $and$ls180.v:6155$1830 + attribute \src "ls180.v:6167.44-6167.100" + cell $and $and$ls180.v:6167$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6155$1829_Y - connect \Y $and$ls180.v:6155$1830_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6167$1779_Y + connect \Y $and$ls180.v:6167$1780_Y end - attribute \src "ls180.v:6155.49-6155.156" - cell $and $and$ls180.v:6155$1832 + attribute \src "ls180.v:6167.43-6167.151" + cell $and $and$ls180.v:6167$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6155$1830_Y - connect \B $eq$ls180.v:6155$1831_Y - connect \Y $and$ls180.v:6155$1832_Y + connect \A $and$ls180.v:6167$1780_Y + connect \B $eq$ls180.v:6167$1781_Y + connect \Y $and$ls180.v:6167$1782_Y end - attribute \src "ls180.v:6157.40-6157.93" - cell $and $and$ls180.v:6157$1833 + attribute \src "ls180.v:6169.44-6169.97" + cell $and $and$ls180.v:6169$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6157$1833_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6169$1783_Y end - attribute \src "ls180.v:6157.39-6157.143" - cell $and $and$ls180.v:6157$1835 + attribute \src "ls180.v:6169.43-6169.148" + cell $and $and$ls180.v:6169$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1833_Y - connect \B $eq$ls180.v:6157$1834_Y - connect \Y $and$ls180.v:6157$1835_Y + connect \A $and$ls180.v:6169$1783_Y + connect \B $eq$ls180.v:6169$1784_Y + connect \Y $and$ls180.v:6169$1785_Y end - attribute \src "ls180.v:6158.40-6158.96" - cell $and $and$ls180.v:6158$1837 + attribute \src "ls180.v:6170.44-6170.100" + cell $and $and$ls180.v:6170$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6158$1836_Y - connect \Y $and$ls180.v:6158$1837_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6170$1786_Y + connect \Y $and$ls180.v:6170$1787_Y end - attribute \src "ls180.v:6158.39-6158.146" - cell $and $and$ls180.v:6158$1839 + attribute \src "ls180.v:6170.43-6170.151" + cell $and $and$ls180.v:6170$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1837_Y - connect \B $eq$ls180.v:6158$1838_Y - connect \Y $and$ls180.v:6158$1839_Y + connect \A $and$ls180.v:6170$1787_Y + connect \B $eq$ls180.v:6170$1788_Y + connect \Y $and$ls180.v:6170$1789_Y end - attribute \src "ls180.v:6160.50-6160.103" - cell $and $and$ls180.v:6160$1840 + attribute \src "ls180.v:6172.44-6172.97" + cell $and $and$ls180.v:6172$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6160$1840_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6172$1790_Y end - attribute \src "ls180.v:6160.49-6160.153" - cell $and $and$ls180.v:6160$1842 + attribute \src "ls180.v:6172.43-6172.148" + cell $and $and$ls180.v:6172$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1840_Y - connect \B $eq$ls180.v:6160$1841_Y - connect \Y $and$ls180.v:6160$1842_Y + connect \A $and$ls180.v:6172$1790_Y + connect \B $eq$ls180.v:6172$1791_Y + connect \Y $and$ls180.v:6172$1792_Y end - attribute \src "ls180.v:6161.50-6161.106" - cell $and $and$ls180.v:6161$1844 + attribute \src "ls180.v:6173.44-6173.100" + cell $and $and$ls180.v:6173$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6161$1843_Y - connect \Y $and$ls180.v:6161$1844_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6173$1793_Y + connect \Y $and$ls180.v:6173$1794_Y end - attribute \src "ls180.v:6161.49-6161.156" - cell $and $and$ls180.v:6161$1846 + attribute \src "ls180.v:6173.43-6173.151" + cell $and $and$ls180.v:6173$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1844_Y - connect \B $eq$ls180.v:6161$1845_Y - connect \Y $and$ls180.v:6161$1846_Y + connect \A $and$ls180.v:6173$1794_Y + connect \B $eq$ls180.v:6173$1795_Y + connect \Y $and$ls180.v:6173$1796_Y end - attribute \src "ls180.v:6163.50-6163.103" - cell $and $and$ls180.v:6163$1847 + attribute \src "ls180.v:6175.44-6175.97" + cell $and $and$ls180.v:6175$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6163$1847_Y + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6175$1797_Y end - attribute \src "ls180.v:6163.49-6163.153" - cell $and $and$ls180.v:6163$1849 + attribute \src "ls180.v:6175.43-6175.148" + cell $and $and$ls180.v:6175$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1847_Y - connect \B $eq$ls180.v:6163$1848_Y - connect \Y $and$ls180.v:6163$1849_Y + connect \A $and$ls180.v:6175$1797_Y + connect \B $eq$ls180.v:6175$1798_Y + connect \Y $and$ls180.v:6175$1799_Y end - attribute \src "ls180.v:6164.50-6164.106" - cell $and $and$ls180.v:6164$1851 + attribute \src "ls180.v:6176.44-6176.100" + cell $and $and$ls180.v:6176$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6164$1850_Y - connect \Y $and$ls180.v:6164$1851_Y + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6176$1800_Y + connect \Y $and$ls180.v:6176$1801_Y end - attribute \src "ls180.v:6164.49-6164.156" - cell $and $and$ls180.v:6164$1853 + attribute \src "ls180.v:6176.43-6176.151" + cell $and $and$ls180.v:6176$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1851_Y - connect \B $eq$ls180.v:6164$1852_Y - connect \Y $and$ls180.v:6164$1853_Y + connect \A $and$ls180.v:6176$1801_Y + connect \B $eq$ls180.v:6176$1802_Y + connect \Y $and$ls180.v:6176$1803_Y end - attribute \src "ls180.v:6166.51-6166.104" - cell $and $and$ls180.v:6166$1854 + attribute \src "ls180.v:6200.44-6200.97" + cell $and $and$ls180.v:6200$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239166,43 +244375,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6166$1854_Y + connect \Y $and$ls180.v:6200$1805_Y end - attribute \src "ls180.v:6166.50-6166.154" - cell $and $and$ls180.v:6166$1856 + attribute \src "ls180.v:6200.43-6200.147" + cell $and $and$ls180.v:6200$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6166$1854_Y - connect \B $eq$ls180.v:6166$1855_Y - connect \Y $and$ls180.v:6166$1856_Y + connect \A $and$ls180.v:6200$1805_Y + connect \B $eq$ls180.v:6200$1806_Y + connect \Y $and$ls180.v:6200$1807_Y end - attribute \src "ls180.v:6167.51-6167.107" - cell $and $and$ls180.v:6167$1858 + attribute \src "ls180.v:6201.44-6201.100" + cell $and $and$ls180.v:6201$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6167$1857_Y - connect \Y $and$ls180.v:6167$1858_Y + connect \B $not$ls180.v:6201$1808_Y + connect \Y $and$ls180.v:6201$1809_Y end - attribute \src "ls180.v:6167.50-6167.157" - cell $and $and$ls180.v:6167$1860 + attribute \src "ls180.v:6201.43-6201.150" + cell $and $and$ls180.v:6201$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1858_Y - connect \B $eq$ls180.v:6167$1859_Y - connect \Y $and$ls180.v:6167$1860_Y + connect \A $and$ls180.v:6201$1809_Y + connect \B $eq$ls180.v:6201$1810_Y + connect \Y $and$ls180.v:6201$1811_Y end - attribute \src "ls180.v:6169.49-6169.102" - cell $and $and$ls180.v:6169$1861 + attribute \src "ls180.v:6203.49-6203.102" + cell $and $and$ls180.v:6203$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239210,43 +244419,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6169$1861_Y + connect \Y $and$ls180.v:6203$1812_Y end - attribute \src "ls180.v:6169.48-6169.152" - cell $and $and$ls180.v:6169$1863 + attribute \src "ls180.v:6203.48-6203.152" + cell $and $and$ls180.v:6203$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6169$1861_Y - connect \B $eq$ls180.v:6169$1862_Y - connect \Y $and$ls180.v:6169$1863_Y + connect \A $and$ls180.v:6203$1812_Y + connect \B $eq$ls180.v:6203$1813_Y + connect \Y $and$ls180.v:6203$1814_Y end - attribute \src "ls180.v:6170.49-6170.105" - cell $and $and$ls180.v:6170$1865 + attribute \src "ls180.v:6204.49-6204.105" + cell $and $and$ls180.v:6204$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6170$1864_Y - connect \Y $and$ls180.v:6170$1865_Y + connect \B $not$ls180.v:6204$1815_Y + connect \Y $and$ls180.v:6204$1816_Y end - attribute \src "ls180.v:6170.48-6170.155" - cell $and $and$ls180.v:6170$1867 + attribute \src "ls180.v:6204.48-6204.155" + cell $and $and$ls180.v:6204$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1865_Y - connect \B $eq$ls180.v:6170$1866_Y - connect \Y $and$ls180.v:6170$1867_Y + connect \A $and$ls180.v:6204$1816_Y + connect \B $eq$ls180.v:6204$1817_Y + connect \Y $and$ls180.v:6204$1818_Y end - attribute \src "ls180.v:6172.49-6172.102" - cell $and $and$ls180.v:6172$1868 + attribute \src "ls180.v:6206.49-6206.102" + cell $and $and$ls180.v:6206$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239254,43 +244463,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6172$1868_Y + connect \Y $and$ls180.v:6206$1819_Y end - attribute \src "ls180.v:6172.48-6172.152" - cell $and $and$ls180.v:6172$1870 + attribute \src "ls180.v:6206.48-6206.152" + cell $and $and$ls180.v:6206$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6172$1868_Y - connect \B $eq$ls180.v:6172$1869_Y - connect \Y $and$ls180.v:6172$1870_Y + connect \A $and$ls180.v:6206$1819_Y + connect \B $eq$ls180.v:6206$1820_Y + connect \Y $and$ls180.v:6206$1821_Y end - attribute \src "ls180.v:6173.49-6173.105" - cell $and $and$ls180.v:6173$1872 + attribute \src "ls180.v:6207.49-6207.105" + cell $and $and$ls180.v:6207$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6173$1871_Y - connect \Y $and$ls180.v:6173$1872_Y + connect \B $not$ls180.v:6207$1822_Y + connect \Y $and$ls180.v:6207$1823_Y end - attribute \src "ls180.v:6173.48-6173.155" - cell $and $and$ls180.v:6173$1874 + attribute \src "ls180.v:6207.48-6207.155" + cell $and $and$ls180.v:6207$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1872_Y - connect \B $eq$ls180.v:6173$1873_Y - connect \Y $and$ls180.v:6173$1874_Y + connect \A $and$ls180.v:6207$1823_Y + connect \B $eq$ls180.v:6207$1824_Y + connect \Y $and$ls180.v:6207$1825_Y end - attribute \src "ls180.v:6175.49-6175.102" - cell $and $and$ls180.v:6175$1875 + attribute \src "ls180.v:6209.42-6209.95" + cell $and $and$ls180.v:6209$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239298,87 +244507,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6175$1875_Y + connect \Y $and$ls180.v:6209$1826_Y end - attribute \src "ls180.v:6175.48-6175.152" - cell $and $and$ls180.v:6175$1877 + attribute \src "ls180.v:6209.41-6209.145" + cell $and $and$ls180.v:6209$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6175$1875_Y - connect \B $eq$ls180.v:6175$1876_Y - connect \Y $and$ls180.v:6175$1877_Y + connect \A $and$ls180.v:6209$1826_Y + connect \B $eq$ls180.v:6209$1827_Y + connect \Y $and$ls180.v:6209$1828_Y end - attribute \src "ls180.v:6176.49-6176.105" - cell $and $and$ls180.v:6176$1879 + attribute \src "ls180.v:6210.42-6210.98" + cell $and $and$ls180.v:6210$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6176$1878_Y - connect \Y $and$ls180.v:6176$1879_Y + connect \B $not$ls180.v:6210$1829_Y + connect \Y $and$ls180.v:6210$1830_Y end - attribute \src "ls180.v:6176.48-6176.155" - cell $and $and$ls180.v:6176$1881 + attribute \src "ls180.v:6210.41-6210.148" + cell $and $and$ls180.v:6210$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1879_Y - connect \B $eq$ls180.v:6176$1880_Y - connect \Y $and$ls180.v:6176$1881_Y + connect \A $and$ls180.v:6210$1830_Y + connect \B $eq$ls180.v:6210$1831_Y + connect \Y $and$ls180.v:6210$1832_Y end - attribute \src "ls180.v:6178.49-6178.102" - cell $and $and$ls180.v:6178$1882 + attribute \src "ls180.v:6217.46-6217.99" + cell $and $and$ls180.v:6217$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6178$1882_Y + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6217$1834_Y end - attribute \src "ls180.v:6178.48-6178.152" - cell $and $and$ls180.v:6178$1884 + attribute \src "ls180.v:6217.45-6217.149" + cell $and $and$ls180.v:6217$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6178$1882_Y - connect \B $eq$ls180.v:6178$1883_Y - connect \Y $and$ls180.v:6178$1884_Y + connect \A $and$ls180.v:6217$1834_Y + connect \B $eq$ls180.v:6217$1835_Y + connect \Y $and$ls180.v:6217$1836_Y end - attribute \src "ls180.v:6179.49-6179.105" - cell $and $and$ls180.v:6179$1886 + attribute \src "ls180.v:6218.46-6218.102" + cell $and $and$ls180.v:6218$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6179$1885_Y - connect \Y $and$ls180.v:6179$1886_Y + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6218$1837_Y + connect \Y $and$ls180.v:6218$1838_Y end - attribute \src "ls180.v:6179.48-6179.155" - cell $and $and$ls180.v:6179$1888 + attribute \src "ls180.v:6218.45-6218.152" + cell $and $and$ls180.v:6218$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1886_Y - connect \B $eq$ls180.v:6179$1887_Y - connect \Y $and$ls180.v:6179$1888_Y + connect \A $and$ls180.v:6218$1838_Y + connect \B $eq$ls180.v:6218$1839_Y + connect \Y $and$ls180.v:6218$1840_Y end - attribute \src "ls180.v:6196.41-6196.94" - cell $and $and$ls180.v:6196$1890 + attribute \src "ls180.v:6220.50-6220.103" + cell $and $and$ls180.v:6220$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239386,43 +244595,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6196$1890_Y + connect \Y $and$ls180.v:6220$1841_Y end - attribute \src "ls180.v:6196.40-6196.144" - cell $and $and$ls180.v:6196$1892 + attribute \src "ls180.v:6220.49-6220.153" + cell $and $and$ls180.v:6220$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6196$1890_Y - connect \B $eq$ls180.v:6196$1891_Y - connect \Y $and$ls180.v:6196$1892_Y + connect \A $and$ls180.v:6220$1841_Y + connect \B $eq$ls180.v:6220$1842_Y + connect \Y $and$ls180.v:6220$1843_Y end - attribute \src "ls180.v:6197.41-6197.97" - cell $and $and$ls180.v:6197$1894 + attribute \src "ls180.v:6221.50-6221.106" + cell $and $and$ls180.v:6221$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6197$1893_Y - connect \Y $and$ls180.v:6197$1894_Y + connect \B $not$ls180.v:6221$1844_Y + connect \Y $and$ls180.v:6221$1845_Y end - attribute \src "ls180.v:6197.40-6197.147" - cell $and $and$ls180.v:6197$1896 + attribute \src "ls180.v:6221.49-6221.156" + cell $and $and$ls180.v:6221$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6197$1894_Y - connect \B $eq$ls180.v:6197$1895_Y - connect \Y $and$ls180.v:6197$1896_Y + connect \A $and$ls180.v:6221$1845_Y + connect \B $eq$ls180.v:6221$1846_Y + connect \Y $and$ls180.v:6221$1847_Y end - attribute \src "ls180.v:6199.41-6199.94" - cell $and $and$ls180.v:6199$1897 + attribute \src "ls180.v:6223.40-6223.93" + cell $and $and$ls180.v:6223$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239430,43 +244639,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6199$1897_Y + connect \Y $and$ls180.v:6223$1848_Y end - attribute \src "ls180.v:6199.40-6199.144" - cell $and $and$ls180.v:6199$1899 + attribute \src "ls180.v:6223.39-6223.143" + cell $and $and$ls180.v:6223$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1897_Y - connect \B $eq$ls180.v:6199$1898_Y - connect \Y $and$ls180.v:6199$1899_Y + connect \A $and$ls180.v:6223$1848_Y + connect \B $eq$ls180.v:6223$1849_Y + connect \Y $and$ls180.v:6223$1850_Y end - attribute \src "ls180.v:6200.41-6200.97" - cell $and $and$ls180.v:6200$1901 + attribute \src "ls180.v:6224.40-6224.96" + cell $and $and$ls180.v:6224$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6200$1900_Y - connect \Y $and$ls180.v:6200$1901_Y + connect \B $not$ls180.v:6224$1851_Y + connect \Y $and$ls180.v:6224$1852_Y end - attribute \src "ls180.v:6200.40-6200.147" - cell $and $and$ls180.v:6200$1903 + attribute \src "ls180.v:6224.39-6224.146" + cell $and $and$ls180.v:6224$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6200$1901_Y - connect \B $eq$ls180.v:6200$1902_Y - connect \Y $and$ls180.v:6200$1903_Y + connect \A $and$ls180.v:6224$1852_Y + connect \B $eq$ls180.v:6224$1853_Y + connect \Y $and$ls180.v:6224$1854_Y end - attribute \src "ls180.v:6202.39-6202.92" - cell $and $and$ls180.v:6202$1904 + attribute \src "ls180.v:6226.50-6226.103" + cell $and $and$ls180.v:6226$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239474,43 +244683,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6202$1904_Y + connect \Y $and$ls180.v:6226$1855_Y end - attribute \src "ls180.v:6202.38-6202.142" - cell $and $and$ls180.v:6202$1906 + attribute \src "ls180.v:6226.49-6226.153" + cell $and $and$ls180.v:6226$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1904_Y - connect \B $eq$ls180.v:6202$1905_Y - connect \Y $and$ls180.v:6202$1906_Y + connect \A $and$ls180.v:6226$1855_Y + connect \B $eq$ls180.v:6226$1856_Y + connect \Y $and$ls180.v:6226$1857_Y end - attribute \src "ls180.v:6203.39-6203.95" - cell $and $and$ls180.v:6203$1908 + attribute \src "ls180.v:6227.50-6227.106" + cell $and $and$ls180.v:6227$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6203$1907_Y - connect \Y $and$ls180.v:6203$1908_Y + connect \B $not$ls180.v:6227$1858_Y + connect \Y $and$ls180.v:6227$1859_Y end - attribute \src "ls180.v:6203.38-6203.145" - cell $and $and$ls180.v:6203$1910 + attribute \src "ls180.v:6227.49-6227.156" + cell $and $and$ls180.v:6227$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6203$1908_Y - connect \B $eq$ls180.v:6203$1909_Y - connect \Y $and$ls180.v:6203$1910_Y + connect \A $and$ls180.v:6227$1859_Y + connect \B $eq$ls180.v:6227$1860_Y + connect \Y $and$ls180.v:6227$1861_Y end - attribute \src "ls180.v:6205.38-6205.91" - cell $and $and$ls180.v:6205$1911 + attribute \src "ls180.v:6229.50-6229.103" + cell $and $and$ls180.v:6229$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239518,43 +244727,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6205$1911_Y + connect \Y $and$ls180.v:6229$1862_Y end - attribute \src "ls180.v:6205.37-6205.141" - cell $and $and$ls180.v:6205$1913 + attribute \src "ls180.v:6229.49-6229.153" + cell $and $and$ls180.v:6229$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1911_Y - connect \B $eq$ls180.v:6205$1912_Y - connect \Y $and$ls180.v:6205$1913_Y + connect \A $and$ls180.v:6229$1862_Y + connect \B $eq$ls180.v:6229$1863_Y + connect \Y $and$ls180.v:6229$1864_Y end - attribute \src "ls180.v:6206.38-6206.94" - cell $and $and$ls180.v:6206$1915 + attribute \src "ls180.v:6230.50-6230.106" + cell $and $and$ls180.v:6230$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6206$1914_Y - connect \Y $and$ls180.v:6206$1915_Y + connect \B $not$ls180.v:6230$1865_Y + connect \Y $and$ls180.v:6230$1866_Y end - attribute \src "ls180.v:6206.37-6206.144" - cell $and $and$ls180.v:6206$1917 + attribute \src "ls180.v:6230.49-6230.156" + cell $and $and$ls180.v:6230$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6206$1915_Y - connect \B $eq$ls180.v:6206$1916_Y - connect \Y $and$ls180.v:6206$1917_Y + connect \A $and$ls180.v:6230$1866_Y + connect \B $eq$ls180.v:6230$1867_Y + connect \Y $and$ls180.v:6230$1868_Y end - attribute \src "ls180.v:6208.37-6208.90" - cell $and $and$ls180.v:6208$1918 + attribute \src "ls180.v:6232.51-6232.104" + cell $and $and$ls180.v:6232$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239562,43 +244771,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6208$1918_Y + connect \Y $and$ls180.v:6232$1869_Y end - attribute \src "ls180.v:6208.36-6208.140" - cell $and $and$ls180.v:6208$1920 + attribute \src "ls180.v:6232.50-6232.154" + cell $and $and$ls180.v:6232$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1918_Y - connect \B $eq$ls180.v:6208$1919_Y - connect \Y $and$ls180.v:6208$1920_Y + connect \A $and$ls180.v:6232$1869_Y + connect \B $eq$ls180.v:6232$1870_Y + connect \Y $and$ls180.v:6232$1871_Y end - attribute \src "ls180.v:6209.37-6209.93" - cell $and $and$ls180.v:6209$1922 + attribute \src "ls180.v:6233.51-6233.107" + cell $and $and$ls180.v:6233$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6209$1921_Y - connect \Y $and$ls180.v:6209$1922_Y + connect \B $not$ls180.v:6233$1872_Y + connect \Y $and$ls180.v:6233$1873_Y end - attribute \src "ls180.v:6209.36-6209.143" - cell $and $and$ls180.v:6209$1924 + attribute \src "ls180.v:6233.50-6233.157" + cell $and $and$ls180.v:6233$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6209$1922_Y - connect \B $eq$ls180.v:6209$1923_Y - connect \Y $and$ls180.v:6209$1924_Y + connect \A $and$ls180.v:6233$1873_Y + connect \B $eq$ls180.v:6233$1874_Y + connect \Y $and$ls180.v:6233$1875_Y end - attribute \src "ls180.v:6211.36-6211.89" - cell $and $and$ls180.v:6211$1925 + attribute \src "ls180.v:6235.49-6235.102" + cell $and $and$ls180.v:6235$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239606,43 +244815,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6211$1925_Y + connect \Y $and$ls180.v:6235$1876_Y end - attribute \src "ls180.v:6211.35-6211.139" - cell $and $and$ls180.v:6211$1927 + attribute \src "ls180.v:6235.48-6235.152" + cell $and $and$ls180.v:6235$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1925_Y - connect \B $eq$ls180.v:6211$1926_Y - connect \Y $and$ls180.v:6211$1927_Y + connect \A $and$ls180.v:6235$1876_Y + connect \B $eq$ls180.v:6235$1877_Y + connect \Y $and$ls180.v:6235$1878_Y end - attribute \src "ls180.v:6212.36-6212.92" - cell $and $and$ls180.v:6212$1929 + attribute \src "ls180.v:6236.49-6236.105" + cell $and $and$ls180.v:6236$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6212$1928_Y - connect \Y $and$ls180.v:6212$1929_Y + connect \B $not$ls180.v:6236$1879_Y + connect \Y $and$ls180.v:6236$1880_Y end - attribute \src "ls180.v:6212.35-6212.142" - cell $and $and$ls180.v:6212$1931 + attribute \src "ls180.v:6236.48-6236.155" + cell $and $and$ls180.v:6236$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6212$1929_Y - connect \B $eq$ls180.v:6212$1930_Y - connect \Y $and$ls180.v:6212$1931_Y + connect \A $and$ls180.v:6236$1880_Y + connect \B $eq$ls180.v:6236$1881_Y + connect \Y $and$ls180.v:6236$1882_Y end - attribute \src "ls180.v:6214.42-6214.95" - cell $and $and$ls180.v:6214$1932 + attribute \src "ls180.v:6238.49-6238.102" + cell $and $and$ls180.v:6238$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239650,131 +244859,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6214$1932_Y + connect \Y $and$ls180.v:6238$1883_Y end - attribute \src "ls180.v:6214.41-6214.145" - cell $and $and$ls180.v:6214$1934 + attribute \src "ls180.v:6238.48-6238.152" + cell $and $and$ls180.v:6238$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1932_Y - connect \B $eq$ls180.v:6214$1933_Y - connect \Y $and$ls180.v:6214$1934_Y + connect \A $and$ls180.v:6238$1883_Y + connect \B $eq$ls180.v:6238$1884_Y + connect \Y $and$ls180.v:6238$1885_Y end - attribute \src "ls180.v:6215.42-6215.98" - cell $and $and$ls180.v:6215$1936 + attribute \src "ls180.v:6239.49-6239.105" + cell $and $and$ls180.v:6239$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6215$1935_Y - connect \Y $and$ls180.v:6215$1936_Y + connect \B $not$ls180.v:6239$1886_Y + connect \Y $and$ls180.v:6239$1887_Y end - attribute \src "ls180.v:6215.41-6215.148" - cell $and $and$ls180.v:6215$1938 + attribute \src "ls180.v:6239.48-6239.155" + cell $and $and$ls180.v:6239$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6215$1936_Y - connect \B $eq$ls180.v:6215$1937_Y - connect \Y $and$ls180.v:6215$1938_Y + connect \A $and$ls180.v:6239$1887_Y + connect \B $eq$ls180.v:6239$1888_Y + connect \Y $and$ls180.v:6239$1889_Y end - attribute \src "ls180.v:6236.42-6236.97" - cell $and $and$ls180.v:6236$1941 + attribute \src "ls180.v:6241.49-6241.102" + cell $and $and$ls180.v:6241$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6236$1941_Y + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6241$1890_Y end - attribute \src "ls180.v:6236.41-6236.148" - cell $and $and$ls180.v:6236$1943 + attribute \src "ls180.v:6241.48-6241.152" + cell $and $and$ls180.v:6241$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6236$1941_Y - connect \B $eq$ls180.v:6236$1942_Y - connect \Y $and$ls180.v:6236$1943_Y + connect \A $and$ls180.v:6241$1890_Y + connect \B $eq$ls180.v:6241$1891_Y + connect \Y $and$ls180.v:6241$1892_Y end - attribute \src "ls180.v:6237.42-6237.100" - cell $and $and$ls180.v:6237$1945 + attribute \src "ls180.v:6242.49-6242.105" + cell $and $and$ls180.v:6242$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6237$1944_Y - connect \Y $and$ls180.v:6237$1945_Y + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6242$1893_Y + connect \Y $and$ls180.v:6242$1894_Y end - attribute \src "ls180.v:6237.41-6237.151" - cell $and $and$ls180.v:6237$1947 + attribute \src "ls180.v:6242.48-6242.155" + cell $and $and$ls180.v:6242$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1945_Y - connect \B $eq$ls180.v:6237$1946_Y - connect \Y $and$ls180.v:6237$1947_Y + connect \A $and$ls180.v:6242$1894_Y + connect \B $eq$ls180.v:6242$1895_Y + connect \Y $and$ls180.v:6242$1896_Y end - attribute \src "ls180.v:6239.42-6239.97" - cell $and $and$ls180.v:6239$1948 + attribute \src "ls180.v:6244.49-6244.102" + cell $and $and$ls180.v:6244$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6239$1948_Y + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6244$1897_Y end - attribute \src "ls180.v:6239.41-6239.148" - cell $and $and$ls180.v:6239$1950 + attribute \src "ls180.v:6244.48-6244.152" + cell $and $and$ls180.v:6244$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6239$1948_Y - connect \B $eq$ls180.v:6239$1949_Y - connect \Y $and$ls180.v:6239$1950_Y + connect \A $and$ls180.v:6244$1897_Y + connect \B $eq$ls180.v:6244$1898_Y + connect \Y $and$ls180.v:6244$1899_Y end - attribute \src "ls180.v:6240.42-6240.100" - cell $and $and$ls180.v:6240$1952 + attribute \src "ls180.v:6245.49-6245.105" + cell $and $and$ls180.v:6245$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6240$1951_Y - connect \Y $and$ls180.v:6240$1952_Y + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6245$1900_Y + connect \Y $and$ls180.v:6245$1901_Y end - attribute \src "ls180.v:6240.41-6240.151" - cell $and $and$ls180.v:6240$1954 + attribute \src "ls180.v:6245.48-6245.155" + cell $and $and$ls180.v:6245$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1952_Y - connect \B $eq$ls180.v:6240$1953_Y - connect \Y $and$ls180.v:6240$1954_Y + connect \A $and$ls180.v:6245$1901_Y + connect \B $eq$ls180.v:6245$1902_Y + connect \Y $and$ls180.v:6245$1903_Y end - attribute \src "ls180.v:6242.40-6242.95" - cell $and $and$ls180.v:6242$1955 + attribute \src "ls180.v:6262.42-6262.97" + cell $and $and$ls180.v:6262$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239782,43 +244991,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6242$1955_Y + connect \Y $and$ls180.v:6262$1905_Y end - attribute \src "ls180.v:6242.39-6242.146" - cell $and $and$ls180.v:6242$1957 + attribute \src "ls180.v:6262.41-6262.148" + cell $and $and$ls180.v:6262$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6242$1955_Y - connect \B $eq$ls180.v:6242$1956_Y - connect \Y $and$ls180.v:6242$1957_Y + connect \A $and$ls180.v:6262$1905_Y + connect \B $eq$ls180.v:6262$1906_Y + connect \Y $and$ls180.v:6262$1907_Y end - attribute \src "ls180.v:6243.40-6243.98" - cell $and $and$ls180.v:6243$1959 + attribute \src "ls180.v:6263.42-6263.100" + cell $and $and$ls180.v:6263$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6243$1958_Y - connect \Y $and$ls180.v:6243$1959_Y + connect \B $not$ls180.v:6263$1908_Y + connect \Y $and$ls180.v:6263$1909_Y end - attribute \src "ls180.v:6243.39-6243.149" - cell $and $and$ls180.v:6243$1961 + attribute \src "ls180.v:6263.41-6263.151" + cell $and $and$ls180.v:6263$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1959_Y - connect \B $eq$ls180.v:6243$1960_Y - connect \Y $and$ls180.v:6243$1961_Y + connect \A $and$ls180.v:6263$1909_Y + connect \B $eq$ls180.v:6263$1910_Y + connect \Y $and$ls180.v:6263$1911_Y end - attribute \src "ls180.v:6245.39-6245.94" - cell $and $and$ls180.v:6245$1962 + attribute \src "ls180.v:6265.42-6265.97" + cell $and $and$ls180.v:6265$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239826,43 +245035,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6245$1962_Y + connect \Y $and$ls180.v:6265$1912_Y end - attribute \src "ls180.v:6245.38-6245.145" - cell $and $and$ls180.v:6245$1964 + attribute \src "ls180.v:6265.41-6265.148" + cell $and $and$ls180.v:6265$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6245$1962_Y - connect \B $eq$ls180.v:6245$1963_Y - connect \Y $and$ls180.v:6245$1964_Y + connect \A $and$ls180.v:6265$1912_Y + connect \B $eq$ls180.v:6265$1913_Y + connect \Y $and$ls180.v:6265$1914_Y end - attribute \src "ls180.v:6246.39-6246.97" - cell $and $and$ls180.v:6246$1966 + attribute \src "ls180.v:6266.42-6266.100" + cell $and $and$ls180.v:6266$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6246$1965_Y - connect \Y $and$ls180.v:6246$1966_Y + connect \B $not$ls180.v:6266$1915_Y + connect \Y $and$ls180.v:6266$1916_Y end - attribute \src "ls180.v:6246.38-6246.148" - cell $and $and$ls180.v:6246$1968 + attribute \src "ls180.v:6266.41-6266.151" + cell $and $and$ls180.v:6266$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1966_Y - connect \B $eq$ls180.v:6246$1967_Y - connect \Y $and$ls180.v:6246$1968_Y + connect \A $and$ls180.v:6266$1916_Y + connect \B $eq$ls180.v:6266$1917_Y + connect \Y $and$ls180.v:6266$1918_Y end - attribute \src "ls180.v:6248.38-6248.93" - cell $and $and$ls180.v:6248$1969 + attribute \src "ls180.v:6268.40-6268.95" + cell $and $and$ls180.v:6268$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239870,43 +245079,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6248$1969_Y + connect \Y $and$ls180.v:6268$1919_Y end - attribute \src "ls180.v:6248.37-6248.144" - cell $and $and$ls180.v:6248$1971 + attribute \src "ls180.v:6268.39-6268.146" + cell $and $and$ls180.v:6268$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6248$1969_Y - connect \B $eq$ls180.v:6248$1970_Y - connect \Y $and$ls180.v:6248$1971_Y + connect \A $and$ls180.v:6268$1919_Y + connect \B $eq$ls180.v:6268$1920_Y + connect \Y $and$ls180.v:6268$1921_Y end - attribute \src "ls180.v:6249.38-6249.96" - cell $and $and$ls180.v:6249$1973 + attribute \src "ls180.v:6269.40-6269.98" + cell $and $and$ls180.v:6269$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6249$1972_Y - connect \Y $and$ls180.v:6249$1973_Y + connect \B $not$ls180.v:6269$1922_Y + connect \Y $and$ls180.v:6269$1923_Y end - attribute \src "ls180.v:6249.37-6249.147" - cell $and $and$ls180.v:6249$1975 + attribute \src "ls180.v:6269.39-6269.149" + cell $and $and$ls180.v:6269$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1973_Y - connect \B $eq$ls180.v:6249$1974_Y - connect \Y $and$ls180.v:6249$1975_Y + connect \A $and$ls180.v:6269$1923_Y + connect \B $eq$ls180.v:6269$1924_Y + connect \Y $and$ls180.v:6269$1925_Y end - attribute \src "ls180.v:6251.37-6251.92" - cell $and $and$ls180.v:6251$1976 + attribute \src "ls180.v:6271.39-6271.94" + cell $and $and$ls180.v:6271$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239914,43 +245123,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6251$1976_Y + connect \Y $and$ls180.v:6271$1926_Y end - attribute \src "ls180.v:6251.36-6251.143" - cell $and $and$ls180.v:6251$1978 + attribute \src "ls180.v:6271.38-6271.145" + cell $and $and$ls180.v:6271$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6251$1976_Y - connect \B $eq$ls180.v:6251$1977_Y - connect \Y $and$ls180.v:6251$1978_Y + connect \A $and$ls180.v:6271$1926_Y + connect \B $eq$ls180.v:6271$1927_Y + connect \Y $and$ls180.v:6271$1928_Y end - attribute \src "ls180.v:6252.37-6252.95" - cell $and $and$ls180.v:6252$1980 + attribute \src "ls180.v:6272.39-6272.97" + cell $and $and$ls180.v:6272$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6252$1979_Y - connect \Y $and$ls180.v:6252$1980_Y + connect \B $not$ls180.v:6272$1929_Y + connect \Y $and$ls180.v:6272$1930_Y end - attribute \src "ls180.v:6252.36-6252.146" - cell $and $and$ls180.v:6252$1982 + attribute \src "ls180.v:6272.38-6272.148" + cell $and $and$ls180.v:6272$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1980_Y - connect \B $eq$ls180.v:6252$1981_Y - connect \Y $and$ls180.v:6252$1982_Y + connect \A $and$ls180.v:6272$1930_Y + connect \B $eq$ls180.v:6272$1931_Y + connect \Y $and$ls180.v:6272$1932_Y end - attribute \src "ls180.v:6254.43-6254.98" - cell $and $and$ls180.v:6254$1983 + attribute \src "ls180.v:6274.38-6274.93" + cell $and $and$ls180.v:6274$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -239958,43 +245167,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6254$1983_Y + connect \Y $and$ls180.v:6274$1933_Y end - attribute \src "ls180.v:6254.42-6254.149" - cell $and $and$ls180.v:6254$1985 + attribute \src "ls180.v:6274.37-6274.144" + cell $and $and$ls180.v:6274$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6254$1983_Y - connect \B $eq$ls180.v:6254$1984_Y - connect \Y $and$ls180.v:6254$1985_Y + connect \A $and$ls180.v:6274$1933_Y + connect \B $eq$ls180.v:6274$1934_Y + connect \Y $and$ls180.v:6274$1935_Y end - attribute \src "ls180.v:6255.43-6255.101" - cell $and $and$ls180.v:6255$1987 + attribute \src "ls180.v:6275.38-6275.96" + cell $and $and$ls180.v:6275$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6255$1986_Y - connect \Y $and$ls180.v:6255$1987_Y + connect \B $not$ls180.v:6275$1936_Y + connect \Y $and$ls180.v:6275$1937_Y end - attribute \src "ls180.v:6255.42-6255.152" - cell $and $and$ls180.v:6255$1989 + attribute \src "ls180.v:6275.37-6275.147" + cell $and $and$ls180.v:6275$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1987_Y - connect \B $eq$ls180.v:6255$1988_Y - connect \Y $and$ls180.v:6255$1989_Y + connect \A $and$ls180.v:6275$1937_Y + connect \B $eq$ls180.v:6275$1938_Y + connect \Y $and$ls180.v:6275$1939_Y end - attribute \src "ls180.v:6257.46-6257.101" - cell $and $and$ls180.v:6257$1990 + attribute \src "ls180.v:6277.37-6277.92" + cell $and $and$ls180.v:6277$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240002,43 +245211,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6257$1990_Y + connect \Y $and$ls180.v:6277$1940_Y end - attribute \src "ls180.v:6257.45-6257.152" - cell $and $and$ls180.v:6257$1992 + attribute \src "ls180.v:6277.36-6277.143" + cell $and $and$ls180.v:6277$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6257$1990_Y - connect \B $eq$ls180.v:6257$1991_Y - connect \Y $and$ls180.v:6257$1992_Y + connect \A $and$ls180.v:6277$1940_Y + connect \B $eq$ls180.v:6277$1941_Y + connect \Y $and$ls180.v:6277$1942_Y end - attribute \src "ls180.v:6258.46-6258.104" - cell $and $and$ls180.v:6258$1994 + attribute \src "ls180.v:6278.37-6278.95" + cell $and $and$ls180.v:6278$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6258$1993_Y - connect \Y $and$ls180.v:6258$1994_Y + connect \B $not$ls180.v:6278$1943_Y + connect \Y $and$ls180.v:6278$1944_Y end - attribute \src "ls180.v:6258.45-6258.155" - cell $and $and$ls180.v:6258$1996 + attribute \src "ls180.v:6278.36-6278.146" + cell $and $and$ls180.v:6278$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1994_Y - connect \B $eq$ls180.v:6258$1995_Y - connect \Y $and$ls180.v:6258$1996_Y + connect \A $and$ls180.v:6278$1944_Y + connect \B $eq$ls180.v:6278$1945_Y + connect \Y $and$ls180.v:6278$1946_Y end - attribute \src "ls180.v:6260.46-6260.101" - cell $and $and$ls180.v:6260$1997 + attribute \src "ls180.v:6280.43-6280.98" + cell $and $and$ls180.v:6280$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240046,175 +245255,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6260$1997_Y + connect \Y $and$ls180.v:6280$1947_Y end - attribute \src "ls180.v:6260.45-6260.152" - cell $and $and$ls180.v:6260$1999 + attribute \src "ls180.v:6280.42-6280.149" + cell $and $and$ls180.v:6280$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1997_Y - connect \B $eq$ls180.v:6260$1998_Y - connect \Y $and$ls180.v:6260$1999_Y + connect \A $and$ls180.v:6280$1947_Y + connect \B $eq$ls180.v:6280$1948_Y + connect \Y $and$ls180.v:6280$1949_Y end - attribute \src "ls180.v:6261.46-6261.104" - cell $and $and$ls180.v:6261$2001 + attribute \src "ls180.v:6281.43-6281.101" + cell $and $and$ls180.v:6281$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6261$2000_Y - connect \Y $and$ls180.v:6261$2001_Y - end - attribute \src "ls180.v:6261.45-6261.155" - cell $and $and$ls180.v:6261$2003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$2001_Y - connect \B $eq$ls180.v:6261$2002_Y - connect \Y $and$ls180.v:6261$2003_Y - end - attribute \src "ls180.v:6284.39-6284.94" - cell $and $and$ls180.v:6284$2006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6284$2006_Y - end - attribute \src "ls180.v:6284.38-6284.145" - cell $and $and$ls180.v:6284$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$2006_Y - connect \B $eq$ls180.v:6284$2007_Y - connect \Y $and$ls180.v:6284$2008_Y - end - attribute \src "ls180.v:6285.39-6285.97" - cell $and $and$ls180.v:6285$2010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6285$2009_Y - connect \Y $and$ls180.v:6285$2010_Y - end - attribute \src "ls180.v:6285.38-6285.148" - cell $and $and$ls180.v:6285$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$2010_Y - connect \B $eq$ls180.v:6285$2011_Y - connect \Y $and$ls180.v:6285$2012_Y - end - attribute \src "ls180.v:6287.39-6287.94" - cell $and $and$ls180.v:6287$2013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6287$2013_Y - end - attribute \src "ls180.v:6287.38-6287.145" - cell $and $and$ls180.v:6287$2015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$2013_Y - connect \B $eq$ls180.v:6287$2014_Y - connect \Y $and$ls180.v:6287$2015_Y - end - attribute \src "ls180.v:6288.39-6288.97" - cell $and $and$ls180.v:6288$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6288$2016_Y - connect \Y $and$ls180.v:6288$2017_Y - end - attribute \src "ls180.v:6288.38-6288.148" - cell $and $and$ls180.v:6288$2019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$2017_Y - connect \B $eq$ls180.v:6288$2018_Y - connect \Y $and$ls180.v:6288$2019_Y - end - attribute \src "ls180.v:6290.39-6290.94" - cell $and $and$ls180.v:6290$2020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6290$2020_Y - end - attribute \src "ls180.v:6290.38-6290.145" - cell $and $and$ls180.v:6290$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$2020_Y - connect \B $eq$ls180.v:6290$2021_Y - connect \Y $and$ls180.v:6290$2022_Y - end - attribute \src "ls180.v:6291.39-6291.97" - cell $and $and$ls180.v:6291$2024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6291$2023_Y - connect \Y $and$ls180.v:6291$2024_Y + connect \B $not$ls180.v:6281$1950_Y + connect \Y $and$ls180.v:6281$1951_Y end - attribute \src "ls180.v:6291.38-6291.148" - cell $and $and$ls180.v:6291$2026 + attribute \src "ls180.v:6281.42-6281.152" + cell $and $and$ls180.v:6281$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$2024_Y - connect \B $eq$ls180.v:6291$2025_Y - connect \Y $and$ls180.v:6291$2026_Y + connect \A $and$ls180.v:6281$1951_Y + connect \B $eq$ls180.v:6281$1952_Y + connect \Y $and$ls180.v:6281$1953_Y end - attribute \src "ls180.v:6293.39-6293.94" - cell $and $and$ls180.v:6293$2027 + attribute \src "ls180.v:6302.42-6302.97" + cell $and $and$ls180.v:6302$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240222,43 +245299,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6293$2027_Y + connect \Y $and$ls180.v:6302$1956_Y end - attribute \src "ls180.v:6293.38-6293.145" - cell $and $and$ls180.v:6293$2029 + attribute \src "ls180.v:6302.41-6302.148" + cell $and $and$ls180.v:6302$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6293$2027_Y - connect \B $eq$ls180.v:6293$2028_Y - connect \Y $and$ls180.v:6293$2029_Y + connect \A $and$ls180.v:6302$1956_Y + connect \B $eq$ls180.v:6302$1957_Y + connect \Y $and$ls180.v:6302$1958_Y end - attribute \src "ls180.v:6294.39-6294.97" - cell $and $and$ls180.v:6294$2031 + attribute \src "ls180.v:6303.42-6303.100" + cell $and $and$ls180.v:6303$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6294$2030_Y - connect \Y $and$ls180.v:6294$2031_Y + connect \B $not$ls180.v:6303$1959_Y + connect \Y $and$ls180.v:6303$1960_Y end - attribute \src "ls180.v:6294.38-6294.148" - cell $and $and$ls180.v:6294$2033 + attribute \src "ls180.v:6303.41-6303.151" + cell $and $and$ls180.v:6303$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$2031_Y - connect \B $eq$ls180.v:6294$2032_Y - connect \Y $and$ls180.v:6294$2033_Y + connect \A $and$ls180.v:6303$1960_Y + connect \B $eq$ls180.v:6303$1961_Y + connect \Y $and$ls180.v:6303$1962_Y end - attribute \src "ls180.v:6296.41-6296.96" - cell $and $and$ls180.v:6296$2034 + attribute \src "ls180.v:6305.42-6305.97" + cell $and $and$ls180.v:6305$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240266,43 +245343,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6296$2034_Y + connect \Y $and$ls180.v:6305$1963_Y end - attribute \src "ls180.v:6296.40-6296.147" - cell $and $and$ls180.v:6296$2036 + attribute \src "ls180.v:6305.41-6305.148" + cell $and $and$ls180.v:6305$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6296$2034_Y - connect \B $eq$ls180.v:6296$2035_Y - connect \Y $and$ls180.v:6296$2036_Y + connect \A $and$ls180.v:6305$1963_Y + connect \B $eq$ls180.v:6305$1964_Y + connect \Y $and$ls180.v:6305$1965_Y end - attribute \src "ls180.v:6297.41-6297.99" - cell $and $and$ls180.v:6297$2038 + attribute \src "ls180.v:6306.42-6306.100" + cell $and $and$ls180.v:6306$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6297$2037_Y - connect \Y $and$ls180.v:6297$2038_Y + connect \B $not$ls180.v:6306$1966_Y + connect \Y $and$ls180.v:6306$1967_Y end - attribute \src "ls180.v:6297.40-6297.150" - cell $and $and$ls180.v:6297$2040 + attribute \src "ls180.v:6306.41-6306.151" + cell $and $and$ls180.v:6306$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$2038_Y - connect \B $eq$ls180.v:6297$2039_Y - connect \Y $and$ls180.v:6297$2040_Y + connect \A $and$ls180.v:6306$1967_Y + connect \B $eq$ls180.v:6306$1968_Y + connect \Y $and$ls180.v:6306$1969_Y end - attribute \src "ls180.v:6299.41-6299.96" - cell $and $and$ls180.v:6299$2041 + attribute \src "ls180.v:6308.40-6308.95" + cell $and $and$ls180.v:6308$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240310,43 +245387,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6299$2041_Y + connect \Y $and$ls180.v:6308$1970_Y end - attribute \src "ls180.v:6299.40-6299.147" - cell $and $and$ls180.v:6299$2043 + attribute \src "ls180.v:6308.39-6308.146" + cell $and $and$ls180.v:6308$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6299$2041_Y - connect \B $eq$ls180.v:6299$2042_Y - connect \Y $and$ls180.v:6299$2043_Y + connect \A $and$ls180.v:6308$1970_Y + connect \B $eq$ls180.v:6308$1971_Y + connect \Y $and$ls180.v:6308$1972_Y end - attribute \src "ls180.v:6300.41-6300.99" - cell $and $and$ls180.v:6300$2045 + attribute \src "ls180.v:6309.40-6309.98" + cell $and $and$ls180.v:6309$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6300$2044_Y - connect \Y $and$ls180.v:6300$2045_Y + connect \B $not$ls180.v:6309$1973_Y + connect \Y $and$ls180.v:6309$1974_Y end - attribute \src "ls180.v:6300.40-6300.150" - cell $and $and$ls180.v:6300$2047 + attribute \src "ls180.v:6309.39-6309.149" + cell $and $and$ls180.v:6309$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$2045_Y - connect \B $eq$ls180.v:6300$2046_Y - connect \Y $and$ls180.v:6300$2047_Y + connect \A $and$ls180.v:6309$1974_Y + connect \B $eq$ls180.v:6309$1975_Y + connect \Y $and$ls180.v:6309$1976_Y end - attribute \src "ls180.v:6302.41-6302.96" - cell $and $and$ls180.v:6302$2048 + attribute \src "ls180.v:6311.39-6311.94" + cell $and $and$ls180.v:6311$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240354,43 +245431,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6302$2048_Y + connect \Y $and$ls180.v:6311$1977_Y end - attribute \src "ls180.v:6302.40-6302.147" - cell $and $and$ls180.v:6302$2050 + attribute \src "ls180.v:6311.38-6311.145" + cell $and $and$ls180.v:6311$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$2048_Y - connect \B $eq$ls180.v:6302$2049_Y - connect \Y $and$ls180.v:6302$2050_Y + connect \A $and$ls180.v:6311$1977_Y + connect \B $eq$ls180.v:6311$1978_Y + connect \Y $and$ls180.v:6311$1979_Y end - attribute \src "ls180.v:6303.41-6303.99" - cell $and $and$ls180.v:6303$2052 + attribute \src "ls180.v:6312.39-6312.97" + cell $and $and$ls180.v:6312$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6303$2051_Y - connect \Y $and$ls180.v:6303$2052_Y + connect \B $not$ls180.v:6312$1980_Y + connect \Y $and$ls180.v:6312$1981_Y end - attribute \src "ls180.v:6303.40-6303.150" - cell $and $and$ls180.v:6303$2054 + attribute \src "ls180.v:6312.38-6312.148" + cell $and $and$ls180.v:6312$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$2052_Y - connect \B $eq$ls180.v:6303$2053_Y - connect \Y $and$ls180.v:6303$2054_Y + connect \A $and$ls180.v:6312$1981_Y + connect \B $eq$ls180.v:6312$1982_Y + connect \Y $and$ls180.v:6312$1983_Y end - attribute \src "ls180.v:6305.41-6305.96" - cell $and $and$ls180.v:6305$2055 + attribute \src "ls180.v:6314.38-6314.93" + cell $and $and$ls180.v:6314$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240398,43 +245475,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6305$2055_Y + connect \Y $and$ls180.v:6314$1984_Y end - attribute \src "ls180.v:6305.40-6305.147" - cell $and $and$ls180.v:6305$2057 + attribute \src "ls180.v:6314.37-6314.144" + cell $and $and$ls180.v:6314$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$2055_Y - connect \B $eq$ls180.v:6305$2056_Y - connect \Y $and$ls180.v:6305$2057_Y + connect \A $and$ls180.v:6314$1984_Y + connect \B $eq$ls180.v:6314$1985_Y + connect \Y $and$ls180.v:6314$1986_Y end - attribute \src "ls180.v:6306.41-6306.99" - cell $and $and$ls180.v:6306$2059 + attribute \src "ls180.v:6315.38-6315.96" + cell $and $and$ls180.v:6315$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6306$2058_Y - connect \Y $and$ls180.v:6306$2059_Y + connect \B $not$ls180.v:6315$1987_Y + connect \Y $and$ls180.v:6315$1988_Y end - attribute \src "ls180.v:6306.40-6306.150" - cell $and $and$ls180.v:6306$2061 + attribute \src "ls180.v:6315.37-6315.147" + cell $and $and$ls180.v:6315$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$2059_Y - connect \B $eq$ls180.v:6306$2060_Y - connect \Y $and$ls180.v:6306$2061_Y + connect \A $and$ls180.v:6315$1988_Y + connect \B $eq$ls180.v:6315$1989_Y + connect \Y $and$ls180.v:6315$1990_Y end - attribute \src "ls180.v:6308.37-6308.92" - cell $and $and$ls180.v:6308$2062 + attribute \src "ls180.v:6317.37-6317.92" + cell $and $and$ls180.v:6317$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240442,43 +245519,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6308$2062_Y + connect \Y $and$ls180.v:6317$1991_Y end - attribute \src "ls180.v:6308.36-6308.143" - cell $and $and$ls180.v:6308$2064 + attribute \src "ls180.v:6317.36-6317.143" + cell $and $and$ls180.v:6317$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$2062_Y - connect \B $eq$ls180.v:6308$2063_Y - connect \Y $and$ls180.v:6308$2064_Y + connect \A $and$ls180.v:6317$1991_Y + connect \B $eq$ls180.v:6317$1992_Y + connect \Y $and$ls180.v:6317$1993_Y end - attribute \src "ls180.v:6309.37-6309.95" - cell $and $and$ls180.v:6309$2066 + attribute \src "ls180.v:6318.37-6318.95" + cell $and $and$ls180.v:6318$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6309$2065_Y - connect \Y $and$ls180.v:6309$2066_Y + connect \B $not$ls180.v:6318$1994_Y + connect \Y $and$ls180.v:6318$1995_Y end - attribute \src "ls180.v:6309.36-6309.146" - cell $and $and$ls180.v:6309$2068 + attribute \src "ls180.v:6318.36-6318.146" + cell $and $and$ls180.v:6318$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$2066_Y - connect \B $eq$ls180.v:6309$2067_Y - connect \Y $and$ls180.v:6309$2068_Y + connect \A $and$ls180.v:6318$1995_Y + connect \B $eq$ls180.v:6318$1996_Y + connect \Y $and$ls180.v:6318$1997_Y end - attribute \src "ls180.v:6311.47-6311.102" - cell $and $and$ls180.v:6311$2069 + attribute \src "ls180.v:6320.43-6320.98" + cell $and $and$ls180.v:6320$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240486,43 +245563,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6311$2069_Y + connect \Y $and$ls180.v:6320$1998_Y end - attribute \src "ls180.v:6311.46-6311.153" - cell $and $and$ls180.v:6311$2071 + attribute \src "ls180.v:6320.42-6320.149" + cell $and $and$ls180.v:6320$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$2069_Y - connect \B $eq$ls180.v:6311$2070_Y - connect \Y $and$ls180.v:6311$2071_Y + connect \A $and$ls180.v:6320$1998_Y + connect \B $eq$ls180.v:6320$1999_Y + connect \Y $and$ls180.v:6320$2000_Y end - attribute \src "ls180.v:6312.47-6312.105" - cell $and $and$ls180.v:6312$2073 + attribute \src "ls180.v:6321.43-6321.101" + cell $and $and$ls180.v:6321$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6312$2072_Y - connect \Y $and$ls180.v:6312$2073_Y + connect \B $not$ls180.v:6321$2001_Y + connect \Y $and$ls180.v:6321$2002_Y end - attribute \src "ls180.v:6312.46-6312.156" - cell $and $and$ls180.v:6312$2075 + attribute \src "ls180.v:6321.42-6321.152" + cell $and $and$ls180.v:6321$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$2073_Y - connect \B $eq$ls180.v:6312$2074_Y - connect \Y $and$ls180.v:6312$2075_Y + connect \A $and$ls180.v:6321$2002_Y + connect \B $eq$ls180.v:6321$2003_Y + connect \Y $and$ls180.v:6321$2004_Y end - attribute \src "ls180.v:6314.40-6314.95" - cell $and $and$ls180.v:6314$2076 + attribute \src "ls180.v:6323.46-6323.101" + cell $and $and$ls180.v:6323$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240530,43 +245607,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6314$2076_Y + connect \Y $and$ls180.v:6323$2005_Y end - attribute \src "ls180.v:6314.39-6314.147" - cell $and $and$ls180.v:6314$2078 + attribute \src "ls180.v:6323.45-6323.152" + cell $and $and$ls180.v:6323$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$2076_Y - connect \B $eq$ls180.v:6314$2077_Y - connect \Y $and$ls180.v:6314$2078_Y + connect \A $and$ls180.v:6323$2005_Y + connect \B $eq$ls180.v:6323$2006_Y + connect \Y $and$ls180.v:6323$2007_Y end - attribute \src "ls180.v:6315.40-6315.98" - cell $and $and$ls180.v:6315$2080 + attribute \src "ls180.v:6324.46-6324.104" + cell $and $and$ls180.v:6324$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6315$2079_Y - connect \Y $and$ls180.v:6315$2080_Y + connect \B $not$ls180.v:6324$2008_Y + connect \Y $and$ls180.v:6324$2009_Y end - attribute \src "ls180.v:6315.39-6315.150" - cell $and $and$ls180.v:6315$2082 + attribute \src "ls180.v:6324.45-6324.155" + cell $and $and$ls180.v:6324$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$2080_Y - connect \B $eq$ls180.v:6315$2081_Y - connect \Y $and$ls180.v:6315$2082_Y + connect \A $and$ls180.v:6324$2009_Y + connect \B $eq$ls180.v:6324$2010_Y + connect \Y $and$ls180.v:6324$2011_Y end - attribute \src "ls180.v:6317.40-6317.95" - cell $and $and$ls180.v:6317$2083 + attribute \src "ls180.v:6326.46-6326.101" + cell $and $and$ls180.v:6326$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240574,263 +245651,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6317$2083_Y + connect \Y $and$ls180.v:6326$2012_Y end - attribute \src "ls180.v:6317.39-6317.147" - cell $and $and$ls180.v:6317$2085 + attribute \src "ls180.v:6326.45-6326.152" + cell $and $and$ls180.v:6326$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$2083_Y - connect \B $eq$ls180.v:6317$2084_Y - connect \Y $and$ls180.v:6317$2085_Y + connect \A $and$ls180.v:6326$2012_Y + connect \B $eq$ls180.v:6326$2013_Y + connect \Y $and$ls180.v:6326$2014_Y end - attribute \src "ls180.v:6318.40-6318.98" - cell $and $and$ls180.v:6318$2087 + attribute \src "ls180.v:6327.46-6327.104" + cell $and $and$ls180.v:6327$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6318$2086_Y - connect \Y $and$ls180.v:6318$2087_Y + connect \B $not$ls180.v:6327$2015_Y + connect \Y $and$ls180.v:6327$2016_Y end - attribute \src "ls180.v:6318.39-6318.150" - cell $and $and$ls180.v:6318$2089 + attribute \src "ls180.v:6327.45-6327.155" + cell $and $and$ls180.v:6327$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$2087_Y - connect \B $eq$ls180.v:6318$2088_Y - connect \Y $and$ls180.v:6318$2089_Y + connect \A $and$ls180.v:6327$2016_Y + connect \B $eq$ls180.v:6327$2017_Y + connect \Y $and$ls180.v:6327$2018_Y end - attribute \src "ls180.v:6320.40-6320.95" - cell $and $and$ls180.v:6320$2090 + attribute \src "ls180.v:6350.39-6350.94" + cell $and $and$ls180.v:6350$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6320$2090_Y + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6350$2021_Y end - attribute \src "ls180.v:6320.39-6320.147" - cell $and $and$ls180.v:6320$2092 + attribute \src "ls180.v:6350.38-6350.145" + cell $and $and$ls180.v:6350$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$2090_Y - connect \B $eq$ls180.v:6320$2091_Y - connect \Y $and$ls180.v:6320$2092_Y + connect \A $and$ls180.v:6350$2021_Y + connect \B $eq$ls180.v:6350$2022_Y + connect \Y $and$ls180.v:6350$2023_Y end - attribute \src "ls180.v:6321.40-6321.98" - cell $and $and$ls180.v:6321$2094 + attribute \src "ls180.v:6351.39-6351.97" + cell $and $and$ls180.v:6351$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6321$2093_Y - connect \Y $and$ls180.v:6321$2094_Y + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6351$2024_Y + connect \Y $and$ls180.v:6351$2025_Y end - attribute \src "ls180.v:6321.39-6321.150" - cell $and $and$ls180.v:6321$2096 + attribute \src "ls180.v:6351.38-6351.148" + cell $and $and$ls180.v:6351$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$2094_Y - connect \B $eq$ls180.v:6321$2095_Y - connect \Y $and$ls180.v:6321$2096_Y + connect \A $and$ls180.v:6351$2025_Y + connect \B $eq$ls180.v:6351$2026_Y + connect \Y $and$ls180.v:6351$2027_Y end - attribute \src "ls180.v:6323.40-6323.95" - cell $and $and$ls180.v:6323$2097 + attribute \src "ls180.v:6353.39-6353.94" + cell $and $and$ls180.v:6353$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6323$2097_Y + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6353$2028_Y end - attribute \src "ls180.v:6323.39-6323.147" - cell $and $and$ls180.v:6323$2099 + attribute \src "ls180.v:6353.38-6353.145" + cell $and $and$ls180.v:6353$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$2097_Y - connect \B $eq$ls180.v:6323$2098_Y - connect \Y $and$ls180.v:6323$2099_Y + connect \A $and$ls180.v:6353$2028_Y + connect \B $eq$ls180.v:6353$2029_Y + connect \Y $and$ls180.v:6353$2030_Y end - attribute \src "ls180.v:6324.40-6324.98" - cell $and $and$ls180.v:6324$2101 + attribute \src "ls180.v:6354.39-6354.97" + cell $and $and$ls180.v:6354$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6324$2100_Y - connect \Y $and$ls180.v:6324$2101_Y + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6354$2031_Y + connect \Y $and$ls180.v:6354$2032_Y end - attribute \src "ls180.v:6324.39-6324.150" - cell $and $and$ls180.v:6324$2103 + attribute \src "ls180.v:6354.38-6354.148" + cell $and $and$ls180.v:6354$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$2101_Y - connect \B $eq$ls180.v:6324$2102_Y - connect \Y $and$ls180.v:6324$2103_Y + connect \A $and$ls180.v:6354$2032_Y + connect \B $eq$ls180.v:6354$2033_Y + connect \Y $and$ls180.v:6354$2034_Y end - attribute \src "ls180.v:6326.52-6326.107" - cell $and $and$ls180.v:6326$2104 + attribute \src "ls180.v:6356.39-6356.94" + cell $and $and$ls180.v:6356$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6326$2104_Y + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6356$2035_Y end - attribute \src "ls180.v:6326.51-6326.159" - cell $and $and$ls180.v:6326$2106 + attribute \src "ls180.v:6356.38-6356.145" + cell $and $and$ls180.v:6356$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$2104_Y - connect \B $eq$ls180.v:6326$2105_Y - connect \Y $and$ls180.v:6326$2106_Y + connect \A $and$ls180.v:6356$2035_Y + connect \B $eq$ls180.v:6356$2036_Y + connect \Y $and$ls180.v:6356$2037_Y end - attribute \src "ls180.v:6327.52-6327.110" - cell $and $and$ls180.v:6327$2108 + attribute \src "ls180.v:6357.39-6357.97" + cell $and $and$ls180.v:6357$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6327$2107_Y - connect \Y $and$ls180.v:6327$2108_Y + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6357$2038_Y + connect \Y $and$ls180.v:6357$2039_Y end - attribute \src "ls180.v:6327.51-6327.162" - cell $and $and$ls180.v:6327$2110 + attribute \src "ls180.v:6357.38-6357.148" + cell $and $and$ls180.v:6357$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$2108_Y - connect \B $eq$ls180.v:6327$2109_Y - connect \Y $and$ls180.v:6327$2110_Y + connect \A $and$ls180.v:6357$2039_Y + connect \B $eq$ls180.v:6357$2040_Y + connect \Y $and$ls180.v:6357$2041_Y end - attribute \src "ls180.v:6329.53-6329.108" - cell $and $and$ls180.v:6329$2111 + attribute \src "ls180.v:6359.39-6359.94" + cell $and $and$ls180.v:6359$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6329$2111_Y + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6359$2042_Y end - attribute \src "ls180.v:6329.52-6329.160" - cell $and $and$ls180.v:6329$2113 + attribute \src "ls180.v:6359.38-6359.145" + cell $and $and$ls180.v:6359$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6329$2111_Y - connect \B $eq$ls180.v:6329$2112_Y - connect \Y $and$ls180.v:6329$2113_Y + connect \A $and$ls180.v:6359$2042_Y + connect \B $eq$ls180.v:6359$2043_Y + connect \Y $and$ls180.v:6359$2044_Y end - attribute \src "ls180.v:6330.53-6330.111" - cell $and $and$ls180.v:6330$2115 + attribute \src "ls180.v:6360.39-6360.97" + cell $and $and$ls180.v:6360$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6330$2114_Y - connect \Y $and$ls180.v:6330$2115_Y + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6360$2045_Y + connect \Y $and$ls180.v:6360$2046_Y end - attribute \src "ls180.v:6330.52-6330.163" - cell $and $and$ls180.v:6330$2117 + attribute \src "ls180.v:6360.38-6360.148" + cell $and $and$ls180.v:6360$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$2115_Y - connect \B $eq$ls180.v:6330$2116_Y - connect \Y $and$ls180.v:6330$2117_Y + connect \A $and$ls180.v:6360$2046_Y + connect \B $eq$ls180.v:6360$2047_Y + connect \Y $and$ls180.v:6360$2048_Y end - attribute \src "ls180.v:6332.44-6332.99" - cell $and $and$ls180.v:6332$2118 + attribute \src "ls180.v:6362.41-6362.96" + cell $and $and$ls180.v:6362$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6332$2118_Y + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6362$2049_Y end - attribute \src "ls180.v:6332.43-6332.151" - cell $and $and$ls180.v:6332$2120 + attribute \src "ls180.v:6362.40-6362.147" + cell $and $and$ls180.v:6362$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6332$2118_Y - connect \B $eq$ls180.v:6332$2119_Y - connect \Y $and$ls180.v:6332$2120_Y + connect \A $and$ls180.v:6362$2049_Y + connect \B $eq$ls180.v:6362$2050_Y + connect \Y $and$ls180.v:6362$2051_Y end - attribute \src "ls180.v:6333.44-6333.102" - cell $and $and$ls180.v:6333$2122 + attribute \src "ls180.v:6363.41-6363.99" + cell $and $and$ls180.v:6363$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6333$2121_Y - connect \Y $and$ls180.v:6333$2122_Y + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6363$2052_Y + connect \Y $and$ls180.v:6363$2053_Y end - attribute \src "ls180.v:6333.43-6333.154" - cell $and $and$ls180.v:6333$2124 + attribute \src "ls180.v:6363.40-6363.150" + cell $and $and$ls180.v:6363$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$2122_Y - connect \B $eq$ls180.v:6333$2123_Y - connect \Y $and$ls180.v:6333$2124_Y + connect \A $and$ls180.v:6363$2053_Y + connect \B $eq$ls180.v:6363$2054_Y + connect \Y $and$ls180.v:6363$2055_Y end - attribute \src "ls180.v:6352.30-6352.85" - cell $and $and$ls180.v:6352$2126 + attribute \src "ls180.v:6365.41-6365.96" + cell $and $and$ls180.v:6365$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240838,43 +245915,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6352$2126_Y + connect \Y $and$ls180.v:6365$2056_Y end - attribute \src "ls180.v:6352.29-6352.136" - cell $and $and$ls180.v:6352$2128 + attribute \src "ls180.v:6365.40-6365.147" + cell $and $and$ls180.v:6365$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6352$2126_Y - connect \B $eq$ls180.v:6352$2127_Y - connect \Y $and$ls180.v:6352$2128_Y + connect \A $and$ls180.v:6365$2056_Y + connect \B $eq$ls180.v:6365$2057_Y + connect \Y $and$ls180.v:6365$2058_Y end - attribute \src "ls180.v:6353.30-6353.88" - cell $and $and$ls180.v:6353$2130 + attribute \src "ls180.v:6366.41-6366.99" + cell $and $and$ls180.v:6366$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6353$2129_Y - connect \Y $and$ls180.v:6353$2130_Y + connect \B $not$ls180.v:6366$2059_Y + connect \Y $and$ls180.v:6366$2060_Y end - attribute \src "ls180.v:6353.29-6353.139" - cell $and $and$ls180.v:6353$2132 + attribute \src "ls180.v:6366.40-6366.150" + cell $and $and$ls180.v:6366$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$2130_Y - connect \B $eq$ls180.v:6353$2131_Y - connect \Y $and$ls180.v:6353$2132_Y + connect \A $and$ls180.v:6366$2060_Y + connect \B $eq$ls180.v:6366$2061_Y + connect \Y $and$ls180.v:6366$2062_Y end - attribute \src "ls180.v:6355.40-6355.95" - cell $and $and$ls180.v:6355$2133 + attribute \src "ls180.v:6368.41-6368.96" + cell $and $and$ls180.v:6368$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240882,43 +245959,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6355$2133_Y + connect \Y $and$ls180.v:6368$2063_Y end - attribute \src "ls180.v:6355.39-6355.146" - cell $and $and$ls180.v:6355$2135 + attribute \src "ls180.v:6368.40-6368.147" + cell $and $and$ls180.v:6368$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6355$2133_Y - connect \B $eq$ls180.v:6355$2134_Y - connect \Y $and$ls180.v:6355$2135_Y + connect \A $and$ls180.v:6368$2063_Y + connect \B $eq$ls180.v:6368$2064_Y + connect \Y $and$ls180.v:6368$2065_Y end - attribute \src "ls180.v:6356.40-6356.98" - cell $and $and$ls180.v:6356$2137 + attribute \src "ls180.v:6369.41-6369.99" + cell $and $and$ls180.v:6369$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6356$2136_Y - connect \Y $and$ls180.v:6356$2137_Y + connect \B $not$ls180.v:6369$2066_Y + connect \Y $and$ls180.v:6369$2067_Y end - attribute \src "ls180.v:6356.39-6356.149" - cell $and $and$ls180.v:6356$2139 + attribute \src "ls180.v:6369.40-6369.150" + cell $and $and$ls180.v:6369$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$2137_Y - connect \B $eq$ls180.v:6356$2138_Y - connect \Y $and$ls180.v:6356$2139_Y + connect \A $and$ls180.v:6369$2067_Y + connect \B $eq$ls180.v:6369$2068_Y + connect \Y $and$ls180.v:6369$2069_Y end - attribute \src "ls180.v:6358.41-6358.96" - cell $and $and$ls180.v:6358$2140 + attribute \src "ls180.v:6371.41-6371.96" + cell $and $and$ls180.v:6371$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240926,43 +246003,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6358$2140_Y + connect \Y $and$ls180.v:6371$2070_Y end - attribute \src "ls180.v:6358.40-6358.147" - cell $and $and$ls180.v:6358$2142 + attribute \src "ls180.v:6371.40-6371.147" + cell $and $and$ls180.v:6371$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6358$2140_Y - connect \B $eq$ls180.v:6358$2141_Y - connect \Y $and$ls180.v:6358$2142_Y + connect \A $and$ls180.v:6371$2070_Y + connect \B $eq$ls180.v:6371$2071_Y + connect \Y $and$ls180.v:6371$2072_Y end - attribute \src "ls180.v:6359.41-6359.99" - cell $and $and$ls180.v:6359$2144 + attribute \src "ls180.v:6372.41-6372.99" + cell $and $and$ls180.v:6372$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6359$2143_Y - connect \Y $and$ls180.v:6359$2144_Y + connect \B $not$ls180.v:6372$2073_Y + connect \Y $and$ls180.v:6372$2074_Y end - attribute \src "ls180.v:6359.40-6359.150" - cell $and $and$ls180.v:6359$2146 + attribute \src "ls180.v:6372.40-6372.150" + cell $and $and$ls180.v:6372$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6359$2144_Y - connect \B $eq$ls180.v:6359$2145_Y - connect \Y $and$ls180.v:6359$2146_Y + connect \A $and$ls180.v:6372$2074_Y + connect \B $eq$ls180.v:6372$2075_Y + connect \Y $and$ls180.v:6372$2076_Y end - attribute \src "ls180.v:6361.45-6361.100" - cell $and $and$ls180.v:6361$2147 + attribute \src "ls180.v:6374.37-6374.92" + cell $and $and$ls180.v:6374$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -240970,43 +246047,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6361$2147_Y + connect \Y $and$ls180.v:6374$2077_Y end - attribute \src "ls180.v:6361.44-6361.151" - cell $and $and$ls180.v:6361$2149 + attribute \src "ls180.v:6374.36-6374.143" + cell $and $and$ls180.v:6374$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6361$2147_Y - connect \B $eq$ls180.v:6361$2148_Y - connect \Y $and$ls180.v:6361$2149_Y + connect \A $and$ls180.v:6374$2077_Y + connect \B $eq$ls180.v:6374$2078_Y + connect \Y $and$ls180.v:6374$2079_Y end - attribute \src "ls180.v:6362.45-6362.103" - cell $and $and$ls180.v:6362$2151 + attribute \src "ls180.v:6375.37-6375.95" + cell $and $and$ls180.v:6375$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6362$2150_Y - connect \Y $and$ls180.v:6362$2151_Y + connect \B $not$ls180.v:6375$2080_Y + connect \Y $and$ls180.v:6375$2081_Y end - attribute \src "ls180.v:6362.44-6362.154" - cell $and $and$ls180.v:6362$2153 + attribute \src "ls180.v:6375.36-6375.146" + cell $and $and$ls180.v:6375$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6362$2151_Y - connect \B $eq$ls180.v:6362$2152_Y - connect \Y $and$ls180.v:6362$2153_Y + connect \A $and$ls180.v:6375$2081_Y + connect \B $eq$ls180.v:6375$2082_Y + connect \Y $and$ls180.v:6375$2083_Y end - attribute \src "ls180.v:6364.46-6364.101" - cell $and $and$ls180.v:6364$2154 + attribute \src "ls180.v:6377.47-6377.102" + cell $and $and$ls180.v:6377$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241014,43 +246091,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6364$2154_Y + connect \Y $and$ls180.v:6377$2084_Y end - attribute \src "ls180.v:6364.45-6364.152" - cell $and $and$ls180.v:6364$2156 + attribute \src "ls180.v:6377.46-6377.153" + cell $and $and$ls180.v:6377$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6364$2154_Y - connect \B $eq$ls180.v:6364$2155_Y - connect \Y $and$ls180.v:6364$2156_Y + connect \A $and$ls180.v:6377$2084_Y + connect \B $eq$ls180.v:6377$2085_Y + connect \Y $and$ls180.v:6377$2086_Y end - attribute \src "ls180.v:6365.46-6365.104" - cell $and $and$ls180.v:6365$2158 + attribute \src "ls180.v:6378.47-6378.105" + cell $and $and$ls180.v:6378$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6365$2157_Y - connect \Y $and$ls180.v:6365$2158_Y + connect \B $not$ls180.v:6378$2087_Y + connect \Y $and$ls180.v:6378$2088_Y end - attribute \src "ls180.v:6365.45-6365.155" - cell $and $and$ls180.v:6365$2160 + attribute \src "ls180.v:6378.46-6378.156" + cell $and $and$ls180.v:6378$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6365$2158_Y - connect \B $eq$ls180.v:6365$2159_Y - connect \Y $and$ls180.v:6365$2160_Y + connect \A $and$ls180.v:6378$2088_Y + connect \B $eq$ls180.v:6378$2089_Y + connect \Y $and$ls180.v:6378$2090_Y end - attribute \src "ls180.v:6367.44-6367.99" - cell $and $and$ls180.v:6367$2161 + attribute \src "ls180.v:6380.40-6380.95" + cell $and $and$ls180.v:6380$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241058,43 +246135,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6367$2161_Y + connect \Y $and$ls180.v:6380$2091_Y end - attribute \src "ls180.v:6367.43-6367.150" - cell $and $and$ls180.v:6367$2163 + attribute \src "ls180.v:6380.39-6380.147" + cell $and $and$ls180.v:6380$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6367$2161_Y - connect \B $eq$ls180.v:6367$2162_Y - connect \Y $and$ls180.v:6367$2163_Y + connect \A $and$ls180.v:6380$2091_Y + connect \B $eq$ls180.v:6380$2092_Y + connect \Y $and$ls180.v:6380$2093_Y end - attribute \src "ls180.v:6368.44-6368.102" - cell $and $and$ls180.v:6368$2165 + attribute \src "ls180.v:6381.40-6381.98" + cell $and $and$ls180.v:6381$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6368$2164_Y - connect \Y $and$ls180.v:6368$2165_Y + connect \B $not$ls180.v:6381$2094_Y + connect \Y $and$ls180.v:6381$2095_Y end - attribute \src "ls180.v:6368.43-6368.153" - cell $and $and$ls180.v:6368$2167 + attribute \src "ls180.v:6381.39-6381.150" + cell $and $and$ls180.v:6381$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6368$2165_Y - connect \B $eq$ls180.v:6368$2166_Y - connect \Y $and$ls180.v:6368$2167_Y + connect \A $and$ls180.v:6381$2095_Y + connect \B $eq$ls180.v:6381$2096_Y + connect \Y $and$ls180.v:6381$2097_Y end - attribute \src "ls180.v:6370.41-6370.96" - cell $and $and$ls180.v:6370$2168 + attribute \src "ls180.v:6383.40-6383.95" + cell $and $and$ls180.v:6383$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241102,43 +246179,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6370$2168_Y + connect \Y $and$ls180.v:6383$2098_Y end - attribute \src "ls180.v:6370.40-6370.147" - cell $and $and$ls180.v:6370$2170 + attribute \src "ls180.v:6383.39-6383.147" + cell $and $and$ls180.v:6383$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6370$2168_Y - connect \B $eq$ls180.v:6370$2169_Y - connect \Y $and$ls180.v:6370$2170_Y + connect \A $and$ls180.v:6383$2098_Y + connect \B $eq$ls180.v:6383$2099_Y + connect \Y $and$ls180.v:6383$2100_Y end - attribute \src "ls180.v:6371.41-6371.99" - cell $and $and$ls180.v:6371$2172 + attribute \src "ls180.v:6384.40-6384.98" + cell $and $and$ls180.v:6384$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6371$2171_Y - connect \Y $and$ls180.v:6371$2172_Y + connect \B $not$ls180.v:6384$2101_Y + connect \Y $and$ls180.v:6384$2102_Y end - attribute \src "ls180.v:6371.40-6371.150" - cell $and $and$ls180.v:6371$2174 + attribute \src "ls180.v:6384.39-6384.150" + cell $and $and$ls180.v:6384$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6371$2172_Y - connect \B $eq$ls180.v:6371$2173_Y - connect \Y $and$ls180.v:6371$2174_Y + connect \A $and$ls180.v:6384$2102_Y + connect \B $eq$ls180.v:6384$2103_Y + connect \Y $and$ls180.v:6384$2104_Y end - attribute \src "ls180.v:6373.40-6373.95" - cell $and $and$ls180.v:6373$2175 + attribute \src "ls180.v:6386.40-6386.95" + cell $and $and$ls180.v:6386$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241146,43 +246223,395 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6373$2175_Y + connect \Y $and$ls180.v:6386$2105_Y end - attribute \src "ls180.v:6373.39-6373.146" - cell $and $and$ls180.v:6373$2177 + attribute \src "ls180.v:6386.39-6386.147" + cell $and $and$ls180.v:6386$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6373$2175_Y - connect \B $eq$ls180.v:6373$2176_Y - connect \Y $and$ls180.v:6373$2177_Y + connect \A $and$ls180.v:6386$2105_Y + connect \B $eq$ls180.v:6386$2106_Y + connect \Y $and$ls180.v:6386$2107_Y end - attribute \src "ls180.v:6374.40-6374.98" - cell $and $and$ls180.v:6374$2179 + attribute \src "ls180.v:6387.40-6387.98" + cell $and $and$ls180.v:6387$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6374$2178_Y - connect \Y $and$ls180.v:6374$2179_Y + connect \B $not$ls180.v:6387$2108_Y + connect \Y $and$ls180.v:6387$2109_Y end - attribute \src "ls180.v:6374.39-6374.149" - cell $and $and$ls180.v:6374$2181 + attribute \src "ls180.v:6387.39-6387.150" + cell $and $and$ls180.v:6387$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6374$2179_Y - connect \B $eq$ls180.v:6374$2180_Y - connect \Y $and$ls180.v:6374$2181_Y + connect \A $and$ls180.v:6387$2109_Y + connect \B $eq$ls180.v:6387$2110_Y + connect \Y $and$ls180.v:6387$2111_Y end - attribute \src "ls180.v:6386.46-6386.101" - cell $and $and$ls180.v:6386$2183 + attribute \src "ls180.v:6389.40-6389.95" + cell $and $and$ls180.v:6389$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6389$2112_Y + end + attribute \src "ls180.v:6389.39-6389.147" + cell $and $and$ls180.v:6389$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6389$2112_Y + connect \B $eq$ls180.v:6389$2113_Y + connect \Y $and$ls180.v:6389$2114_Y + end + attribute \src "ls180.v:6390.40-6390.98" + cell $and $and$ls180.v:6390$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6390$2115_Y + connect \Y $and$ls180.v:6390$2116_Y + end + attribute \src "ls180.v:6390.39-6390.150" + cell $and $and$ls180.v:6390$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6390$2116_Y + connect \B $eq$ls180.v:6390$2117_Y + connect \Y $and$ls180.v:6390$2118_Y + end + attribute \src "ls180.v:6392.52-6392.107" + cell $and $and$ls180.v:6392$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6392$2119_Y + end + attribute \src "ls180.v:6392.51-6392.159" + cell $and $and$ls180.v:6392$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$2119_Y + connect \B $eq$ls180.v:6392$2120_Y + connect \Y $and$ls180.v:6392$2121_Y + end + attribute \src "ls180.v:6393.52-6393.110" + cell $and $and$ls180.v:6393$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6393$2122_Y + connect \Y $and$ls180.v:6393$2123_Y + end + attribute \src "ls180.v:6393.51-6393.162" + cell $and $and$ls180.v:6393$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$2123_Y + connect \B $eq$ls180.v:6393$2124_Y + connect \Y $and$ls180.v:6393$2125_Y + end + attribute \src "ls180.v:6395.53-6395.108" + cell $and $and$ls180.v:6395$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6395$2126_Y + end + attribute \src "ls180.v:6395.52-6395.160" + cell $and $and$ls180.v:6395$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$2126_Y + connect \B $eq$ls180.v:6395$2127_Y + connect \Y $and$ls180.v:6395$2128_Y + end + attribute \src "ls180.v:6396.53-6396.111" + cell $and $and$ls180.v:6396$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6396$2129_Y + connect \Y $and$ls180.v:6396$2130_Y + end + attribute \src "ls180.v:6396.52-6396.163" + cell $and $and$ls180.v:6396$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$2130_Y + connect \B $eq$ls180.v:6396$2131_Y + connect \Y $and$ls180.v:6396$2132_Y + end + attribute \src "ls180.v:6398.44-6398.99" + cell $and $and$ls180.v:6398$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6398$2133_Y + end + attribute \src "ls180.v:6398.43-6398.151" + cell $and $and$ls180.v:6398$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$2133_Y + connect \B $eq$ls180.v:6398$2134_Y + connect \Y $and$ls180.v:6398$2135_Y + end + attribute \src "ls180.v:6399.44-6399.102" + cell $and $and$ls180.v:6399$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6399$2136_Y + connect \Y $and$ls180.v:6399$2137_Y + end + attribute \src "ls180.v:6399.43-6399.154" + cell $and $and$ls180.v:6399$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$2137_Y + connect \B $eq$ls180.v:6399$2138_Y + connect \Y $and$ls180.v:6399$2139_Y + end + attribute \src "ls180.v:6418.30-6418.85" + cell $and $and$ls180.v:6418$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6418$2141_Y + end + attribute \src "ls180.v:6418.29-6418.136" + cell $and $and$ls180.v:6418$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6418$2141_Y + connect \B $eq$ls180.v:6418$2142_Y + connect \Y $and$ls180.v:6418$2143_Y + end + attribute \src "ls180.v:6419.30-6419.88" + cell $and $and$ls180.v:6419$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6419$2144_Y + connect \Y $and$ls180.v:6419$2145_Y + end + attribute \src "ls180.v:6419.29-6419.139" + cell $and $and$ls180.v:6419$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6419$2145_Y + connect \B $eq$ls180.v:6419$2146_Y + connect \Y $and$ls180.v:6419$2147_Y + end + attribute \src "ls180.v:6421.40-6421.95" + cell $and $and$ls180.v:6421$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6421$2148_Y + end + attribute \src "ls180.v:6421.39-6421.146" + cell $and $and$ls180.v:6421$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6421$2148_Y + connect \B $eq$ls180.v:6421$2149_Y + connect \Y $and$ls180.v:6421$2150_Y + end + attribute \src "ls180.v:6422.40-6422.98" + cell $and $and$ls180.v:6422$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6422$2151_Y + connect \Y $and$ls180.v:6422$2152_Y + end + attribute \src "ls180.v:6422.39-6422.149" + cell $and $and$ls180.v:6422$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$2152_Y + connect \B $eq$ls180.v:6422$2153_Y + connect \Y $and$ls180.v:6422$2154_Y + end + attribute \src "ls180.v:6424.41-6424.96" + cell $and $and$ls180.v:6424$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6424$2155_Y + end + attribute \src "ls180.v:6424.40-6424.147" + cell $and $and$ls180.v:6424$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6424$2155_Y + connect \B $eq$ls180.v:6424$2156_Y + connect \Y $and$ls180.v:6424$2157_Y + end + attribute \src "ls180.v:6425.41-6425.99" + cell $and $and$ls180.v:6425$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6425$2158_Y + connect \Y $and$ls180.v:6425$2159_Y + end + attribute \src "ls180.v:6425.40-6425.150" + cell $and $and$ls180.v:6425$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6425$2159_Y + connect \B $eq$ls180.v:6425$2160_Y + connect \Y $and$ls180.v:6425$2161_Y + end + attribute \src "ls180.v:6427.45-6427.100" + cell $and $and$ls180.v:6427$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6427$2162_Y + end + attribute \src "ls180.v:6427.44-6427.151" + cell $and $and$ls180.v:6427$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6427$2162_Y + connect \B $eq$ls180.v:6427$2163_Y + connect \Y $and$ls180.v:6427$2164_Y + end + attribute \src "ls180.v:6428.45-6428.103" + cell $and $and$ls180.v:6428$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6428$2165_Y + connect \Y $and$ls180.v:6428$2166_Y + end + attribute \src "ls180.v:6428.44-6428.154" + cell $and $and$ls180.v:6428$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6428$2166_Y + connect \B $eq$ls180.v:6428$2167_Y + connect \Y $and$ls180.v:6428$2168_Y + end + attribute \src "ls180.v:6430.46-6430.101" + cell $and $and$ls180.v:6430$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241190,43 +246619,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6386$2183_Y + connect \Y $and$ls180.v:6430$2169_Y end - attribute \src "ls180.v:6386.45-6386.152" - cell $and $and$ls180.v:6386$2185 + attribute \src "ls180.v:6430.45-6430.152" + cell $and $and$ls180.v:6430$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6386$2183_Y - connect \B $eq$ls180.v:6386$2184_Y - connect \Y $and$ls180.v:6386$2185_Y + connect \A $and$ls180.v:6430$2169_Y + connect \B $eq$ls180.v:6430$2170_Y + connect \Y $and$ls180.v:6430$2171_Y end - attribute \src "ls180.v:6387.46-6387.104" - cell $and $and$ls180.v:6387$2187 + attribute \src "ls180.v:6431.46-6431.104" + cell $and $and$ls180.v:6431$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6387$2186_Y - connect \Y $and$ls180.v:6387$2187_Y + connect \B $not$ls180.v:6431$2172_Y + connect \Y $and$ls180.v:6431$2173_Y end - attribute \src "ls180.v:6387.45-6387.155" - cell $and $and$ls180.v:6387$2189 + attribute \src "ls180.v:6431.45-6431.155" + cell $and $and$ls180.v:6431$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6387$2187_Y - connect \B $eq$ls180.v:6387$2188_Y - connect \Y $and$ls180.v:6387$2189_Y + connect \A $and$ls180.v:6431$2173_Y + connect \B $eq$ls180.v:6431$2174_Y + connect \Y $and$ls180.v:6431$2175_Y end - attribute \src "ls180.v:6389.46-6389.101" - cell $and $and$ls180.v:6389$2190 + attribute \src "ls180.v:6433.44-6433.99" + cell $and $and$ls180.v:6433$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241234,43 +246663,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6389$2190_Y + connect \Y $and$ls180.v:6433$2176_Y end - attribute \src "ls180.v:6389.45-6389.152" - cell $and $and$ls180.v:6389$2192 + attribute \src "ls180.v:6433.43-6433.150" + cell $and $and$ls180.v:6433$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6389$2190_Y - connect \B $eq$ls180.v:6389$2191_Y - connect \Y $and$ls180.v:6389$2192_Y + connect \A $and$ls180.v:6433$2176_Y + connect \B $eq$ls180.v:6433$2177_Y + connect \Y $and$ls180.v:6433$2178_Y end - attribute \src "ls180.v:6390.46-6390.104" - cell $and $and$ls180.v:6390$2194 + attribute \src "ls180.v:6434.44-6434.102" + cell $and $and$ls180.v:6434$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6390$2193_Y - connect \Y $and$ls180.v:6390$2194_Y + connect \B $not$ls180.v:6434$2179_Y + connect \Y $and$ls180.v:6434$2180_Y end - attribute \src "ls180.v:6390.45-6390.155" - cell $and $and$ls180.v:6390$2196 + attribute \src "ls180.v:6434.43-6434.153" + cell $and $and$ls180.v:6434$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6390$2194_Y - connect \B $eq$ls180.v:6390$2195_Y - connect \Y $and$ls180.v:6390$2196_Y + connect \A $and$ls180.v:6434$2180_Y + connect \B $eq$ls180.v:6434$2181_Y + connect \Y $and$ls180.v:6434$2182_Y end - attribute \src "ls180.v:6392.46-6392.101" - cell $and $and$ls180.v:6392$2197 + attribute \src "ls180.v:6436.41-6436.96" + cell $and $and$ls180.v:6436$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241278,43 +246707,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6392$2197_Y + connect \Y $and$ls180.v:6436$2183_Y end - attribute \src "ls180.v:6392.45-6392.152" - cell $and $and$ls180.v:6392$2199 + attribute \src "ls180.v:6436.40-6436.147" + cell $and $and$ls180.v:6436$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$2197_Y - connect \B $eq$ls180.v:6392$2198_Y - connect \Y $and$ls180.v:6392$2199_Y + connect \A $and$ls180.v:6436$2183_Y + connect \B $eq$ls180.v:6436$2184_Y + connect \Y $and$ls180.v:6436$2185_Y end - attribute \src "ls180.v:6393.46-6393.104" - cell $and $and$ls180.v:6393$2201 + attribute \src "ls180.v:6437.41-6437.99" + cell $and $and$ls180.v:6437$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6393$2200_Y - connect \Y $and$ls180.v:6393$2201_Y + connect \B $not$ls180.v:6437$2186_Y + connect \Y $and$ls180.v:6437$2187_Y end - attribute \src "ls180.v:6393.45-6393.155" - cell $and $and$ls180.v:6393$2203 + attribute \src "ls180.v:6437.40-6437.150" + cell $and $and$ls180.v:6437$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6393$2201_Y - connect \B $eq$ls180.v:6393$2202_Y - connect \Y $and$ls180.v:6393$2203_Y + connect \A $and$ls180.v:6437$2187_Y + connect \B $eq$ls180.v:6437$2188_Y + connect \Y $and$ls180.v:6437$2189_Y end - attribute \src "ls180.v:6395.46-6395.101" - cell $and $and$ls180.v:6395$2204 + attribute \src "ls180.v:6439.40-6439.95" + cell $and $and$ls180.v:6439$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241322,263 +246751,439 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6395$2204_Y + connect \Y $and$ls180.v:6439$2190_Y end - attribute \src "ls180.v:6395.45-6395.152" - cell $and $and$ls180.v:6395$2206 + attribute \src "ls180.v:6439.39-6439.146" + cell $and $and$ls180.v:6439$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$2204_Y - connect \B $eq$ls180.v:6395$2205_Y - connect \Y $and$ls180.v:6395$2206_Y + connect \A $and$ls180.v:6439$2190_Y + connect \B $eq$ls180.v:6439$2191_Y + connect \Y $and$ls180.v:6439$2192_Y end - attribute \src "ls180.v:6396.46-6396.104" - cell $and $and$ls180.v:6396$2208 + attribute \src "ls180.v:6440.40-6440.98" + cell $and $and$ls180.v:6440$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6396$2207_Y - connect \Y $and$ls180.v:6396$2208_Y + connect \B $not$ls180.v:6440$2193_Y + connect \Y $and$ls180.v:6440$2194_Y + end + attribute \src "ls180.v:6440.39-6440.149" + cell $and $and$ls180.v:6440$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6440$2194_Y + connect \B $eq$ls180.v:6440$2195_Y + connect \Y $and$ls180.v:6440$2196_Y + end + attribute \src "ls180.v:6452.46-6452.101" + cell $and $and$ls180.v:6452$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6452$2198_Y + end + attribute \src "ls180.v:6452.45-6452.152" + cell $and $and$ls180.v:6452$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6452$2198_Y + connect \B $eq$ls180.v:6452$2199_Y + connect \Y $and$ls180.v:6452$2200_Y + end + attribute \src "ls180.v:6453.46-6453.104" + cell $and $and$ls180.v:6453$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6453$2201_Y + connect \Y $and$ls180.v:6453$2202_Y + end + attribute \src "ls180.v:6453.45-6453.155" + cell $and $and$ls180.v:6453$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6453$2202_Y + connect \B $eq$ls180.v:6453$2203_Y + connect \Y $and$ls180.v:6453$2204_Y + end + attribute \src "ls180.v:6455.46-6455.101" + cell $and $and$ls180.v:6455$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6455$2205_Y + end + attribute \src "ls180.v:6455.45-6455.152" + cell $and $and$ls180.v:6455$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6455$2205_Y + connect \B $eq$ls180.v:6455$2206_Y + connect \Y $and$ls180.v:6455$2207_Y + end + attribute \src "ls180.v:6456.46-6456.104" + cell $and $and$ls180.v:6456$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6456$2208_Y + connect \Y $and$ls180.v:6456$2209_Y + end + attribute \src "ls180.v:6456.45-6456.155" + cell $and $and$ls180.v:6456$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6456$2209_Y + connect \B $eq$ls180.v:6456$2210_Y + connect \Y $and$ls180.v:6456$2211_Y + end + attribute \src "ls180.v:6458.46-6458.101" + cell $and $and$ls180.v:6458$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6458$2212_Y + end + attribute \src "ls180.v:6458.45-6458.152" + cell $and $and$ls180.v:6458$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6458$2212_Y + connect \B $eq$ls180.v:6458$2213_Y + connect \Y $and$ls180.v:6458$2214_Y + end + attribute \src "ls180.v:6459.46-6459.104" + cell $and $and$ls180.v:6459$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6459$2215_Y + connect \Y $and$ls180.v:6459$2216_Y + end + attribute \src "ls180.v:6459.45-6459.155" + cell $and $and$ls180.v:6459$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6459$2216_Y + connect \B $eq$ls180.v:6459$2217_Y + connect \Y $and$ls180.v:6459$2218_Y + end + attribute \src "ls180.v:6461.46-6461.101" + cell $and $and$ls180.v:6461$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6461$2219_Y + end + attribute \src "ls180.v:6461.45-6461.152" + cell $and $and$ls180.v:6461$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6461$2219_Y + connect \B $eq$ls180.v:6461$2220_Y + connect \Y $and$ls180.v:6461$2221_Y + end + attribute \src "ls180.v:6462.46-6462.104" + cell $and $and$ls180.v:6462$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6462$2222_Y + connect \Y $and$ls180.v:6462$2223_Y end - attribute \src "ls180.v:6396.45-6396.155" - cell $and $and$ls180.v:6396$2210 + attribute \src "ls180.v:6462.45-6462.155" + cell $and $and$ls180.v:6462$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$2208_Y - connect \B $eq$ls180.v:6396$2209_Y - connect \Y $and$ls180.v:6396$2210_Y + connect \A $and$ls180.v:6462$2223_Y + connect \B $eq$ls180.v:6462$2224_Y + connect \Y $and$ls180.v:6462$2225_Y end - attribute \src "ls180.v:6774.109-6774.178" - cell $and $and$ls180.v:6774$2247 + attribute \src "ls180.v:6843.109-6843.178" + cell $and $and$ls180.v:6843$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6774$2246_Y - connect \Y $and$ls180.v:6774$2247_Y + connect \B $eq$ls180.v:6843$2262_Y + connect \Y $and$ls180.v:6843$2263_Y end - attribute \src "ls180.v:6774.184-6774.253" - cell $and $and$ls180.v:6774$2250 + attribute \src "ls180.v:6843.184-6843.253" + cell $and $and$ls180.v:6843$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6774$2249_Y - connect \Y $and$ls180.v:6774$2250_Y + connect \B $eq$ls180.v:6843$2265_Y + connect \Y $and$ls180.v:6843$2266_Y end - attribute \src "ls180.v:6774.259-6774.328" - cell $and $and$ls180.v:6774$2253 + attribute \src "ls180.v:6843.259-6843.328" + cell $and $and$ls180.v:6843$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6774$2252_Y - connect \Y $and$ls180.v:6774$2253_Y + connect \B $eq$ls180.v:6843$2268_Y + connect \Y $and$ls180.v:6843$2269_Y end - attribute \src "ls180.v:6774.40-6774.331" - cell $and $and$ls180.v:6774$2256 + attribute \src "ls180.v:6843.40-6843.331" + cell $and $and$ls180.v:6843$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6774$2245_Y - connect \B $not$ls180.v:6774$2255_Y - connect \Y $and$ls180.v:6774$2256_Y + connect \A $eq$ls180.v:6843$2261_Y + connect \B $not$ls180.v:6843$2271_Y + connect \Y $and$ls180.v:6843$2272_Y end - attribute \src "ls180.v:6774.39-6774.354" - cell $and $and$ls180.v:6774$2257 + attribute \src "ls180.v:6843.39-6843.354" + cell $and $and$ls180.v:6843$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6774$2256_Y + connect \A $and$ls180.v:6843$2272_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6774$2257_Y + connect \Y $and$ls180.v:6843$2273_Y end - attribute \src "ls180.v:6798.109-6798.178" - cell $and $and$ls180.v:6798$2263 + attribute \src "ls180.v:6867.109-6867.178" + cell $and $and$ls180.v:6867$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6798$2262_Y - connect \Y $and$ls180.v:6798$2263_Y + connect \B $eq$ls180.v:6867$2278_Y + connect \Y $and$ls180.v:6867$2279_Y end - attribute \src "ls180.v:6798.184-6798.253" - cell $and $and$ls180.v:6798$2266 + attribute \src "ls180.v:6867.184-6867.253" + cell $and $and$ls180.v:6867$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6798$2265_Y - connect \Y $and$ls180.v:6798$2266_Y + connect \B $eq$ls180.v:6867$2281_Y + connect \Y $and$ls180.v:6867$2282_Y end - attribute \src "ls180.v:6798.259-6798.328" - cell $and $and$ls180.v:6798$2269 + attribute \src "ls180.v:6867.259-6867.328" + cell $and $and$ls180.v:6867$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6798$2268_Y - connect \Y $and$ls180.v:6798$2269_Y + connect \B $eq$ls180.v:6867$2284_Y + connect \Y $and$ls180.v:6867$2285_Y end - attribute \src "ls180.v:6798.40-6798.331" - cell $and $and$ls180.v:6798$2272 + attribute \src "ls180.v:6867.40-6867.331" + cell $and $and$ls180.v:6867$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6798$2261_Y - connect \B $not$ls180.v:6798$2271_Y - connect \Y $and$ls180.v:6798$2272_Y + connect \A $eq$ls180.v:6867$2277_Y + connect \B $not$ls180.v:6867$2287_Y + connect \Y $and$ls180.v:6867$2288_Y end - attribute \src "ls180.v:6798.39-6798.354" - cell $and $and$ls180.v:6798$2273 + attribute \src "ls180.v:6867.39-6867.354" + cell $and $and$ls180.v:6867$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6798$2272_Y + connect \A $and$ls180.v:6867$2288_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6798$2273_Y + connect \Y $and$ls180.v:6867$2289_Y end - attribute \src "ls180.v:6822.109-6822.178" - cell $and $and$ls180.v:6822$2279 + attribute \src "ls180.v:6891.109-6891.178" + cell $and $and$ls180.v:6891$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6822$2278_Y - connect \Y $and$ls180.v:6822$2279_Y + connect \B $eq$ls180.v:6891$2294_Y + connect \Y $and$ls180.v:6891$2295_Y end - attribute \src "ls180.v:6822.184-6822.253" - cell $and $and$ls180.v:6822$2282 + attribute \src "ls180.v:6891.184-6891.253" + cell $and $and$ls180.v:6891$2298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6822$2281_Y - connect \Y $and$ls180.v:6822$2282_Y + connect \B $eq$ls180.v:6891$2297_Y + connect \Y $and$ls180.v:6891$2298_Y end - attribute \src "ls180.v:6822.259-6822.328" - cell $and $and$ls180.v:6822$2285 + attribute \src "ls180.v:6891.259-6891.328" + cell $and $and$ls180.v:6891$2301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6822$2284_Y - connect \Y $and$ls180.v:6822$2285_Y + connect \B $eq$ls180.v:6891$2300_Y + connect \Y $and$ls180.v:6891$2301_Y end - attribute \src "ls180.v:6822.40-6822.331" - cell $and $and$ls180.v:6822$2288 + attribute \src "ls180.v:6891.40-6891.331" + cell $and $and$ls180.v:6891$2304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6822$2277_Y - connect \B $not$ls180.v:6822$2287_Y - connect \Y $and$ls180.v:6822$2288_Y + connect \A $eq$ls180.v:6891$2293_Y + connect \B $not$ls180.v:6891$2303_Y + connect \Y $and$ls180.v:6891$2304_Y end - attribute \src "ls180.v:6822.39-6822.354" - cell $and $and$ls180.v:6822$2289 + attribute \src "ls180.v:6891.39-6891.354" + cell $and $and$ls180.v:6891$2305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6822$2288_Y + connect \A $and$ls180.v:6891$2304_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6822$2289_Y + connect \Y $and$ls180.v:6891$2305_Y end - attribute \src "ls180.v:6846.109-6846.178" - cell $and $and$ls180.v:6846$2295 + attribute \src "ls180.v:6915.109-6915.178" + cell $and $and$ls180.v:6915$2311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6846$2294_Y - connect \Y $and$ls180.v:6846$2295_Y + connect \B $eq$ls180.v:6915$2310_Y + connect \Y $and$ls180.v:6915$2311_Y end - attribute \src "ls180.v:6846.184-6846.253" - cell $and $and$ls180.v:6846$2298 + attribute \src "ls180.v:6915.184-6915.253" + cell $and $and$ls180.v:6915$2314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6846$2297_Y - connect \Y $and$ls180.v:6846$2298_Y + connect \B $eq$ls180.v:6915$2313_Y + connect \Y $and$ls180.v:6915$2314_Y end - attribute \src "ls180.v:6846.259-6846.328" - cell $and $and$ls180.v:6846$2301 + attribute \src "ls180.v:6915.259-6915.328" + cell $and $and$ls180.v:6915$2317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6846$2300_Y - connect \Y $and$ls180.v:6846$2301_Y + connect \B $eq$ls180.v:6915$2316_Y + connect \Y $and$ls180.v:6915$2317_Y end - attribute \src "ls180.v:6846.40-6846.331" - cell $and $and$ls180.v:6846$2304 + attribute \src "ls180.v:6915.40-6915.331" + cell $and $and$ls180.v:6915$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6846$2293_Y - connect \B $not$ls180.v:6846$2303_Y - connect \Y $and$ls180.v:6846$2304_Y + connect \A $eq$ls180.v:6915$2309_Y + connect \B $not$ls180.v:6915$2319_Y + connect \Y $and$ls180.v:6915$2320_Y end - attribute \src "ls180.v:6846.39-6846.354" - cell $and $and$ls180.v:6846$2305 + attribute \src "ls180.v:6915.39-6915.354" + cell $and $and$ls180.v:6915$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6846$2304_Y + connect \A $and$ls180.v:6915$2320_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6846$2305_Y + connect \Y $and$ls180.v:6915$2321_Y end - attribute \src "ls180.v:7051.39-7051.104" - cell $and $and$ls180.v:7051$2317 + attribute \src "ls180.v:7120.39-7120.104" + cell $and $and$ls180.v:7120$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241586,21 +247191,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7051$2317_Y + connect \Y $and$ls180.v:7120$2333_Y end - attribute \src "ls180.v:7051.38-7051.145" - cell $and $and$ls180.v:7051$2318 + attribute \src "ls180.v:7120.38-7120.145" + cell $and $and$ls180.v:7120$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7051$2317_Y + connect \A $and$ls180.v:7120$2333_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7051$2318_Y + connect \Y $and$ls180.v:7120$2334_Y end - attribute \src "ls180.v:7054.39-7054.104" - cell $and $and$ls180.v:7054$2319 + attribute \src "ls180.v:7123.39-7123.104" + cell $and $and$ls180.v:7123$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241608,21 +247213,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7054$2319_Y + connect \Y $and$ls180.v:7123$2335_Y end - attribute \src "ls180.v:7054.38-7054.145" - cell $and $and$ls180.v:7054$2320 + attribute \src "ls180.v:7123.38-7123.145" + cell $and $and$ls180.v:7123$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7054$2319_Y + connect \A $and$ls180.v:7123$2335_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7054$2320_Y + connect \Y $and$ls180.v:7123$2336_Y end - attribute \src "ls180.v:7057.39-7057.82" - cell $and $and$ls180.v:7057$2321 + attribute \src "ls180.v:7126.39-7126.82" + cell $and $and$ls180.v:7126$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241630,21 +247235,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7057$2321_Y + connect \Y $and$ls180.v:7126$2337_Y end - attribute \src "ls180.v:7057.38-7057.112" - cell $and $and$ls180.v:7057$2322 + attribute \src "ls180.v:7126.38-7126.112" + cell $and $and$ls180.v:7126$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7057$2321_Y + connect \A $and$ls180.v:7126$2337_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7057$2322_Y + connect \Y $and$ls180.v:7126$2338_Y end - attribute \src "ls180.v:7068.39-7068.104" - cell $and $and$ls180.v:7068$2324 + attribute \src "ls180.v:7137.39-7137.104" + cell $and $and$ls180.v:7137$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241652,21 +247257,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7068$2324_Y + connect \Y $and$ls180.v:7137$2340_Y end - attribute \src "ls180.v:7068.38-7068.145" - cell $and $and$ls180.v:7068$2325 + attribute \src "ls180.v:7137.38-7137.145" + cell $and $and$ls180.v:7137$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7068$2324_Y + connect \A $and$ls180.v:7137$2340_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7068$2325_Y + connect \Y $and$ls180.v:7137$2341_Y end - attribute \src "ls180.v:7071.39-7071.104" - cell $and $and$ls180.v:7071$2326 + attribute \src "ls180.v:7140.39-7140.104" + cell $and $and$ls180.v:7140$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241674,21 +247279,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7071$2326_Y + connect \Y $and$ls180.v:7140$2342_Y end - attribute \src "ls180.v:7071.38-7071.145" - cell $and $and$ls180.v:7071$2327 + attribute \src "ls180.v:7140.38-7140.145" + cell $and $and$ls180.v:7140$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7071$2326_Y + connect \A $and$ls180.v:7140$2342_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7071$2327_Y + connect \Y $and$ls180.v:7140$2343_Y end - attribute \src "ls180.v:7074.39-7074.82" - cell $and $and$ls180.v:7074$2328 + attribute \src "ls180.v:7143.39-7143.82" + cell $and $and$ls180.v:7143$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241696,21 +247301,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7074$2328_Y + connect \Y $and$ls180.v:7143$2344_Y end - attribute \src "ls180.v:7074.38-7074.112" - cell $and $and$ls180.v:7074$2329 + attribute \src "ls180.v:7143.38-7143.112" + cell $and $and$ls180.v:7143$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7074$2328_Y + connect \A $and$ls180.v:7143$2344_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7074$2329_Y + connect \Y $and$ls180.v:7143$2345_Y end - attribute \src "ls180.v:7085.39-7085.104" - cell $and $and$ls180.v:7085$2331 + attribute \src "ls180.v:7154.39-7154.104" + cell $and $and$ls180.v:7154$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241718,21 +247323,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7085$2331_Y + connect \Y $and$ls180.v:7154$2347_Y end - attribute \src "ls180.v:7085.38-7085.144" - cell $and $and$ls180.v:7085$2332 + attribute \src "ls180.v:7154.38-7154.144" + cell $and $and$ls180.v:7154$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7085$2331_Y + connect \A $and$ls180.v:7154$2347_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7085$2332_Y + connect \Y $and$ls180.v:7154$2348_Y end - attribute \src "ls180.v:7088.39-7088.104" - cell $and $and$ls180.v:7088$2333 + attribute \src "ls180.v:7157.39-7157.104" + cell $and $and$ls180.v:7157$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241740,21 +247345,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7088$2333_Y + connect \Y $and$ls180.v:7157$2349_Y end - attribute \src "ls180.v:7088.38-7088.144" - cell $and $and$ls180.v:7088$2334 + attribute \src "ls180.v:7157.38-7157.144" + cell $and $and$ls180.v:7157$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7088$2333_Y + connect \A $and$ls180.v:7157$2349_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7088$2334_Y + connect \Y $and$ls180.v:7157$2350_Y end - attribute \src "ls180.v:7091.39-7091.82" - cell $and $and$ls180.v:7091$2335 + attribute \src "ls180.v:7160.39-7160.82" + cell $and $and$ls180.v:7160$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241762,21 +247367,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7091$2335_Y + connect \Y $and$ls180.v:7160$2351_Y end - attribute \src "ls180.v:7091.38-7091.111" - cell $and $and$ls180.v:7091$2336 + attribute \src "ls180.v:7160.38-7160.111" + cell $and $and$ls180.v:7160$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7091$2335_Y + connect \A $and$ls180.v:7160$2351_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7091$2336_Y + connect \Y $and$ls180.v:7160$2352_Y end - attribute \src "ls180.v:7102.39-7102.104" - cell $and $and$ls180.v:7102$2338 + attribute \src "ls180.v:7171.39-7171.104" + cell $and $and$ls180.v:7171$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241784,21 +247389,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7102$2338_Y + connect \Y $and$ls180.v:7171$2354_Y end - attribute \src "ls180.v:7102.38-7102.149" - cell $and $and$ls180.v:7102$2339 + attribute \src "ls180.v:7171.38-7171.149" + cell $and $and$ls180.v:7171$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7102$2338_Y + connect \A $and$ls180.v:7171$2354_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7102$2339_Y + connect \Y $and$ls180.v:7171$2355_Y end - attribute \src "ls180.v:7105.39-7105.104" - cell $and $and$ls180.v:7105$2340 + attribute \src "ls180.v:7174.39-7174.104" + cell $and $and$ls180.v:7174$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241806,21 +247411,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7105$2340_Y + connect \Y $and$ls180.v:7174$2356_Y end - attribute \src "ls180.v:7105.38-7105.149" - cell $and $and$ls180.v:7105$2341 + attribute \src "ls180.v:7174.38-7174.149" + cell $and $and$ls180.v:7174$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7105$2340_Y + connect \A $and$ls180.v:7174$2356_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7105$2341_Y + connect \Y $and$ls180.v:7174$2357_Y end - attribute \src "ls180.v:7108.39-7108.82" - cell $and $and$ls180.v:7108$2342 + attribute \src "ls180.v:7177.39-7177.82" + cell $and $and$ls180.v:7177$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241828,21 +247433,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7108$2342_Y + connect \Y $and$ls180.v:7177$2358_Y end - attribute \src "ls180.v:7108.38-7108.116" - cell $and $and$ls180.v:7108$2343 + attribute \src "ls180.v:7177.38-7177.116" + cell $and $and$ls180.v:7177$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7108$2342_Y + connect \A $and$ls180.v:7177$2358_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7108$2343_Y + connect \Y $and$ls180.v:7177$2359_Y end - attribute \src "ls180.v:7119.39-7119.104" - cell $and $and$ls180.v:7119$2345 + attribute \src "ls180.v:7188.39-7188.104" + cell $and $and$ls180.v:7188$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241850,21 +247455,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7119$2345_Y + connect \Y $and$ls180.v:7188$2361_Y end - attribute \src "ls180.v:7119.38-7119.150" - cell $and $and$ls180.v:7119$2346 + attribute \src "ls180.v:7188.38-7188.150" + cell $and $and$ls180.v:7188$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7119$2345_Y + connect \A $and$ls180.v:7188$2361_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7119$2346_Y + connect \Y $and$ls180.v:7188$2362_Y end - attribute \src "ls180.v:7122.39-7122.104" - cell $and $and$ls180.v:7122$2347 + attribute \src "ls180.v:7191.39-7191.104" + cell $and $and$ls180.v:7191$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241872,21 +247477,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7122$2347_Y + connect \Y $and$ls180.v:7191$2363_Y end - attribute \src "ls180.v:7122.38-7122.150" - cell $and $and$ls180.v:7122$2348 + attribute \src "ls180.v:7191.38-7191.150" + cell $and $and$ls180.v:7191$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7122$2347_Y + connect \A $and$ls180.v:7191$2363_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7122$2348_Y + connect \Y $and$ls180.v:7191$2364_Y end - attribute \src "ls180.v:7125.39-7125.82" - cell $and $and$ls180.v:7125$2349 + attribute \src "ls180.v:7194.39-7194.82" + cell $and $and$ls180.v:7194$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241894,32 +247499,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7125$2349_Y + connect \Y $and$ls180.v:7194$2365_Y end - attribute \src "ls180.v:7125.38-7125.117" - cell $and $and$ls180.v:7125$2350 + attribute \src "ls180.v:7194.38-7194.117" + cell $and $and$ls180.v:7194$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7125$2349_Y + connect \A $and$ls180.v:7194$2365_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7125$2350_Y + connect \Y $and$ls180.v:7194$2366_Y end - attribute \src "ls180.v:7344.17-7344.67" - cell $and $and$ls180.v:7344$2357 + attribute \src "ls180.v:7413.17-7413.67" + cell $and $and$ls180.v:7413$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7344$2356_Y + connect \A $not$ls180.v:7413$2372_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7344$2357_Y + connect \Y $and$ls180.v:7413$2373_Y end - attribute \src "ls180.v:7441.8-7441.67" - cell $and $and$ls180.v:7441$2406 + attribute \src "ls180.v:7504.8-7504.67" + cell $and $and$ls180.v:7504$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241927,54 +247532,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7441$2406_Y + connect \Y $and$ls180.v:7504$2416_Y end - attribute \src "ls180.v:7441.7-7441.102" - cell $and $and$ls180.v:7441$2408 + attribute \src "ls180.v:7504.7-7504.102" + cell $and $and$ls180.v:7504$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7441$2406_Y - connect \B $not$ls180.v:7441$2407_Y - connect \Y $and$ls180.v:7441$2408_Y + connect \A $and$ls180.v:7504$2416_Y + connect \B $not$ls180.v:7504$2417_Y + connect \Y $and$ls180.v:7504$2418_Y end - attribute \src "ls180.v:7460.7-7460.75" - cell $and $and$ls180.v:7460$2412 + attribute \src "ls180.v:7523.7-7523.75" + cell $and $and$ls180.v:7523$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7460$2411_Y + connect \A $not$ls180.v:7523$2421_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7460$2412_Y + connect \Y $and$ls180.v:7523$2422_Y end - attribute \src "ls180.v:7468.7-7468.56" - cell $and $and$ls180.v:7468$2414 + attribute \src "ls180.v:7531.7-7531.56" + cell $and $and$ls180.v:7531$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7468$2413_Y - connect \Y $and$ls180.v:7468$2414_Y + connect \B $not$ls180.v:7531$2423_Y + connect \Y $and$ls180.v:7531$2424_Y end - attribute \src "ls180.v:7496.7-7496.75" - cell $and $and$ls180.v:7496$2421 + attribute \src "ls180.v:7559.7-7559.75" + cell $and $and$ls180.v:7559$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7496$2420_Y - connect \Y $and$ls180.v:7496$2421_Y + connect \B $eq$ls180.v:7559$2430_Y + connect \Y $and$ls180.v:7559$2431_Y end - attribute \src "ls180.v:7538.8-7538.131" - cell $and $and$ls180.v:7538$2427 + attribute \src "ls180.v:7601.8-7601.131" + cell $and $and$ls180.v:7601$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -241982,21 +247587,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7538$2427_Y + connect \Y $and$ls180.v:7601$2437_Y end - attribute \src "ls180.v:7538.7-7538.190" - cell $and $and$ls180.v:7538$2429 + attribute \src "ls180.v:7601.7-7601.190" + cell $and $and$ls180.v:7601$2439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7538$2427_Y - connect \B $not$ls180.v:7538$2428_Y - connect \Y $and$ls180.v:7538$2429_Y + connect \A $and$ls180.v:7601$2437_Y + connect \B $not$ls180.v:7601$2438_Y + connect \Y $and$ls180.v:7601$2439_Y end - attribute \src "ls180.v:7544.8-7544.131" - cell $and $and$ls180.v:7544$2432 + attribute \src "ls180.v:7607.8-7607.131" + cell $and $and$ls180.v:7607$2442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242004,21 +247609,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7544$2432_Y + connect \Y $and$ls180.v:7607$2442_Y end - attribute \src "ls180.v:7544.7-7544.190" - cell $and $and$ls180.v:7544$2434 + attribute \src "ls180.v:7607.7-7607.190" + cell $and $and$ls180.v:7607$2444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7544$2432_Y - connect \B $not$ls180.v:7544$2433_Y - connect \Y $and$ls180.v:7544$2434_Y + connect \A $and$ls180.v:7607$2442_Y + connect \B $not$ls180.v:7607$2443_Y + connect \Y $and$ls180.v:7607$2444_Y end - attribute \src "ls180.v:7584.8-7584.131" - cell $and $and$ls180.v:7584$2443 + attribute \src "ls180.v:7647.8-7647.131" + cell $and $and$ls180.v:7647$2453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242026,21 +247631,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7584$2443_Y + connect \Y $and$ls180.v:7647$2453_Y end - attribute \src "ls180.v:7584.7-7584.190" - cell $and $and$ls180.v:7584$2445 + attribute \src "ls180.v:7647.7-7647.190" + cell $and $and$ls180.v:7647$2455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7584$2443_Y - connect \B $not$ls180.v:7584$2444_Y - connect \Y $and$ls180.v:7584$2445_Y + connect \A $and$ls180.v:7647$2453_Y + connect \B $not$ls180.v:7647$2454_Y + connect \Y $and$ls180.v:7647$2455_Y end - attribute \src "ls180.v:7590.8-7590.131" - cell $and $and$ls180.v:7590$2448 + attribute \src "ls180.v:7653.8-7653.131" + cell $and $and$ls180.v:7653$2458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242048,21 +247653,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7590$2448_Y + connect \Y $and$ls180.v:7653$2458_Y end - attribute \src "ls180.v:7590.7-7590.190" - cell $and $and$ls180.v:7590$2450 + attribute \src "ls180.v:7653.7-7653.190" + cell $and $and$ls180.v:7653$2460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7590$2448_Y - connect \B $not$ls180.v:7590$2449_Y - connect \Y $and$ls180.v:7590$2450_Y + connect \A $and$ls180.v:7653$2458_Y + connect \B $not$ls180.v:7653$2459_Y + connect \Y $and$ls180.v:7653$2460_Y end - attribute \src "ls180.v:7630.8-7630.131" - cell $and $and$ls180.v:7630$2459 + attribute \src "ls180.v:7693.8-7693.131" + cell $and $and$ls180.v:7693$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242070,21 +247675,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7630$2459_Y + connect \Y $and$ls180.v:7693$2469_Y end - attribute \src "ls180.v:7630.7-7630.190" - cell $and $and$ls180.v:7630$2461 + attribute \src "ls180.v:7693.7-7693.190" + cell $and $and$ls180.v:7693$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7630$2459_Y - connect \B $not$ls180.v:7630$2460_Y - connect \Y $and$ls180.v:7630$2461_Y + connect \A $and$ls180.v:7693$2469_Y + connect \B $not$ls180.v:7693$2470_Y + connect \Y $and$ls180.v:7693$2471_Y end - attribute \src "ls180.v:7636.8-7636.131" - cell $and $and$ls180.v:7636$2464 + attribute \src "ls180.v:7699.8-7699.131" + cell $and $and$ls180.v:7699$2474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242092,21 +247697,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7636$2464_Y + connect \Y $and$ls180.v:7699$2474_Y end - attribute \src "ls180.v:7636.7-7636.190" - cell $and $and$ls180.v:7636$2466 + attribute \src "ls180.v:7699.7-7699.190" + cell $and $and$ls180.v:7699$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7636$2464_Y - connect \B $not$ls180.v:7636$2465_Y - connect \Y $and$ls180.v:7636$2466_Y + connect \A $and$ls180.v:7699$2474_Y + connect \B $not$ls180.v:7699$2475_Y + connect \Y $and$ls180.v:7699$2476_Y end - attribute \src "ls180.v:7676.8-7676.131" - cell $and $and$ls180.v:7676$2475 + attribute \src "ls180.v:7739.8-7739.131" + cell $and $and$ls180.v:7739$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242114,21 +247719,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7676$2475_Y + connect \Y $and$ls180.v:7739$2485_Y end - attribute \src "ls180.v:7676.7-7676.190" - cell $and $and$ls180.v:7676$2477 + attribute \src "ls180.v:7739.7-7739.190" + cell $and $and$ls180.v:7739$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7676$2475_Y - connect \B $not$ls180.v:7676$2476_Y - connect \Y $and$ls180.v:7676$2477_Y + connect \A $and$ls180.v:7739$2485_Y + connect \B $not$ls180.v:7739$2486_Y + connect \Y $and$ls180.v:7739$2487_Y end - attribute \src "ls180.v:7682.8-7682.131" - cell $and $and$ls180.v:7682$2480 + attribute \src "ls180.v:7745.8-7745.131" + cell $and $and$ls180.v:7745$2490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242136,109 +247741,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7682$2480_Y + connect \Y $and$ls180.v:7745$2490_Y end - attribute \src "ls180.v:7682.7-7682.190" - cell $and $and$ls180.v:7682$2482 + attribute \src "ls180.v:7745.7-7745.190" + cell $and $and$ls180.v:7745$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7682$2480_Y - connect \B $not$ls180.v:7682$2481_Y - connect \Y $and$ls180.v:7682$2482_Y + connect \A $and$ls180.v:7745$2490_Y + connect \B $not$ls180.v:7745$2491_Y + connect \Y $and$ls180.v:7745$2492_Y end - attribute \src "ls180.v:7879.48-7879.124" - cell $and $and$ls180.v:7879$2507 + attribute \src "ls180.v:7942.48-7942.124" + cell $and $and$ls180.v:7942$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7879$2506_Y + connect \A $eq$ls180.v:7942$2516_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7879$2507_Y + connect \Y $and$ls180.v:7942$2517_Y end - attribute \src "ls180.v:7879.130-7879.206" - cell $and $and$ls180.v:7879$2510 + attribute \src "ls180.v:7942.130-7942.206" + cell $and $and$ls180.v:7942$2520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7879$2509_Y + connect \A $eq$ls180.v:7942$2519_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7879$2510_Y + connect \Y $and$ls180.v:7942$2520_Y end - attribute \src "ls180.v:7879.212-7879.288" - cell $and $and$ls180.v:7879$2513 + attribute \src "ls180.v:7942.212-7942.288" + cell $and $and$ls180.v:7942$2523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7879$2512_Y + connect \A $eq$ls180.v:7942$2522_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7879$2513_Y + connect \Y $and$ls180.v:7942$2523_Y end - attribute \src "ls180.v:7879.294-7879.370" - cell $and $and$ls180.v:7879$2516 + attribute \src "ls180.v:7942.294-7942.370" + cell $and $and$ls180.v:7942$2526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7879$2515_Y + connect \A $eq$ls180.v:7942$2525_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7879$2516_Y + connect \Y $and$ls180.v:7942$2526_Y end - attribute \src "ls180.v:7880.49-7880.125" - cell $and $and$ls180.v:7880$2519 + attribute \src "ls180.v:7943.49-7943.125" + cell $and $and$ls180.v:7943$2529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7880$2518_Y + connect \A $eq$ls180.v:7943$2528_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7880$2519_Y + connect \Y $and$ls180.v:7943$2529_Y end - attribute \src "ls180.v:7880.131-7880.207" - cell $and $and$ls180.v:7880$2522 + attribute \src "ls180.v:7943.131-7943.207" + cell $and $and$ls180.v:7943$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7880$2521_Y + connect \A $eq$ls180.v:7943$2531_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7880$2522_Y + connect \Y $and$ls180.v:7943$2532_Y end - attribute \src "ls180.v:7880.213-7880.289" - cell $and $and$ls180.v:7880$2525 + attribute \src "ls180.v:7943.213-7943.289" + cell $and $and$ls180.v:7943$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7880$2524_Y + connect \A $eq$ls180.v:7943$2534_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7880$2525_Y + connect \Y $and$ls180.v:7943$2535_Y end - attribute \src "ls180.v:7880.295-7880.371" - cell $and $and$ls180.v:7880$2528 + attribute \src "ls180.v:7943.295-7943.371" + cell $and $and$ls180.v:7943$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7880$2527_Y + connect \A $eq$ls180.v:7943$2537_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7880$2528_Y + connect \Y $and$ls180.v:7943$2538_Y end - attribute \src "ls180.v:7899.8-7899.49" - cell $and $and$ls180.v:7899$2531 + attribute \src "ls180.v:7962.8-7962.49" + cell $and $and$ls180.v:7962$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242246,10 +247851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7899$2531_Y + connect \Y $and$ls180.v:7962$2541_Y end - attribute \src "ls180.v:7902.8-7902.53" - cell $and $and$ls180.v:7902$2532 + attribute \src "ls180.v:7965.8-7965.53" + cell $and $and$ls180.v:7965$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242257,76 +247862,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7902$2532_Y + connect \Y $and$ls180.v:7965$2542_Y end - attribute \src "ls180.v:7907.8-7907.41" - cell $and $and$ls180.v:7907$2534 + attribute \src "ls180.v:7970.8-7970.59" + cell $and $and$ls180.v:7970$2544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sink_valid - connect \B $not$ls180.v:7907$2533_Y - connect \Y $and$ls180.v:7907$2534_Y + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:7970$2543_Y + connect \Y $and$ls180.v:7970$2544_Y end - attribute \src "ls180.v:7907.7-7907.63" - cell $and $and$ls180.v:7907$2536 + attribute \src "ls180.v:7970.7-7970.90" + cell $and $and$ls180.v:7970$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7907$2534_Y - connect \B $not$ls180.v:7907$2535_Y - connect \Y $and$ls180.v:7907$2536_Y + connect \A $and$ls180.v:7970$2544_Y + connect \B $not$ls180.v:7970$2545_Y + connect \Y $and$ls180.v:7970$2546_Y end - attribute \src "ls180.v:7913.8-7913.41" - cell $and $and$ls180.v:7913$2537 + attribute \src "ls180.v:7976.8-7976.59" + cell $and $and$ls180.v:7976$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_clk_txen - connect \B \main_tx_busy - connect \Y $and$ls180.v:7913$2537_Y + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:7976$2547_Y end - attribute \src "ls180.v:7937.8-7937.30" - cell $and $and$ls180.v:7937$2544 + attribute \src "ls180.v:8000.8-8000.48" + cell $and $and$ls180.v:8000$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7937$2543_Y - connect \B \main_rx_r - connect \Y $and$ls180.v:7937$2544_Y + connect \A $not$ls180.v:8000$2553_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:8000$2554_Y end - attribute \src "ls180.v:7970.7-7970.57" - cell $and $and$ls180.v:7970$2550 + attribute \src "ls180.v:8033.7-8033.57" + cell $and $and$ls180.v:8033$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7970$2549_Y + connect \A $not$ls180.v:8033$2559_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:7970$2550_Y + connect \Y $and$ls180.v:8033$2560_Y end - attribute \src "ls180.v:7977.7-7977.57" - cell $and $and$ls180.v:7977$2552 + attribute \src "ls180.v:8040.7-8040.57" + cell $and $and$ls180.v:8040$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7977$2551_Y + connect \A $not$ls180.v:8040$2561_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:7977$2552_Y + connect \Y $and$ls180.v:8040$2562_Y end - attribute \src "ls180.v:7987.8-7987.75" - cell $and $and$ls180.v:7987$2553 + attribute \src "ls180.v:8050.8-8050.75" + cell $and $and$ls180.v:8050$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242334,21 +247939,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7987$2553_Y + connect \Y $and$ls180.v:8050$2563_Y end - attribute \src "ls180.v:7987.7-7987.107" - cell $and $and$ls180.v:7987$2555 + attribute \src "ls180.v:8050.7-8050.107" + cell $and $and$ls180.v:8050$2565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7987$2553_Y - connect \B $not$ls180.v:7987$2554_Y - connect \Y $and$ls180.v:7987$2555_Y + connect \A $and$ls180.v:8050$2563_Y + connect \B $not$ls180.v:8050$2564_Y + connect \Y $and$ls180.v:8050$2565_Y end - attribute \src "ls180.v:7993.8-7993.75" - cell $and $and$ls180.v:7993$2558 + attribute \src "ls180.v:8056.8-8056.75" + cell $and $and$ls180.v:8056$2568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242356,21 +247961,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:7993$2558_Y + connect \Y $and$ls180.v:8056$2568_Y end - attribute \src "ls180.v:7993.7-7993.107" - cell $and $and$ls180.v:7993$2560 + attribute \src "ls180.v:8056.7-8056.107" + cell $and $and$ls180.v:8056$2570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7993$2558_Y - connect \B $not$ls180.v:7993$2559_Y - connect \Y $and$ls180.v:7993$2560_Y + connect \A $and$ls180.v:8056$2568_Y + connect \B $not$ls180.v:8056$2569_Y + connect \Y $and$ls180.v:8056$2570_Y end - attribute \src "ls180.v:8009.8-8009.75" - cell $and $and$ls180.v:8009$2564 + attribute \src "ls180.v:8072.8-8072.75" + cell $and $and$ls180.v:8072$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242378,21 +247983,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8009$2564_Y + connect \Y $and$ls180.v:8072$2574_Y end - attribute \src "ls180.v:8009.7-8009.107" - cell $and $and$ls180.v:8009$2566 + attribute \src "ls180.v:8072.7-8072.107" + cell $and $and$ls180.v:8072$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8009$2564_Y - connect \B $not$ls180.v:8009$2565_Y - connect \Y $and$ls180.v:8009$2566_Y + connect \A $and$ls180.v:8072$2574_Y + connect \B $not$ls180.v:8072$2575_Y + connect \Y $and$ls180.v:8072$2576_Y end - attribute \src "ls180.v:8015.8-8015.75" - cell $and $and$ls180.v:8015$2569 + attribute \src "ls180.v:8078.8-8078.75" + cell $and $and$ls180.v:8078$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242400,21 +248005,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8015$2569_Y + connect \Y $and$ls180.v:8078$2579_Y end - attribute \src "ls180.v:8015.7-8015.107" - cell $and $and$ls180.v:8015$2571 + attribute \src "ls180.v:8078.7-8078.107" + cell $and $and$ls180.v:8078$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8015$2569_Y - connect \B $not$ls180.v:8015$2570_Y - connect \Y $and$ls180.v:8015$2571_Y + connect \A $and$ls180.v:8078$2579_Y + connect \B $not$ls180.v:8078$2580_Y + connect \Y $and$ls180.v:8078$2581_Y end - attribute \src "ls180.v:8128.7-8128.96" - cell $and $and$ls180.v:8128$2594 + attribute \src "ls180.v:8226.7-8226.96" + cell $and $and$ls180.v:8226$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242422,10 +248027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8128$2594_Y + connect \Y $and$ls180.v:8226$2609_Y end - attribute \src "ls180.v:8129.8-8129.93" - cell $and $and$ls180.v:8129$2595 + attribute \src "ls180.v:8227.8-8227.93" + cell $and $and$ls180.v:8227$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242433,10 +248038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8129$2595_Y + connect \Y $and$ls180.v:8227$2610_Y end - attribute \src "ls180.v:8137.8-8137.93" - cell $and $and$ls180.v:8137$2596 + attribute \src "ls180.v:8235.8-8235.93" + cell $and $and$ls180.v:8235$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242444,10 +248049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8137$2596_Y + connect \Y $and$ls180.v:8235$2611_Y end - attribute \src "ls180.v:8209.7-8209.98" - cell $and $and$ls180.v:8209$2606 + attribute \src "ls180.v:8307.7-8307.98" + cell $and $and$ls180.v:8307$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242455,10 +248060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8209$2606_Y + connect \Y $and$ls180.v:8307$2621_Y end - attribute \src "ls180.v:8210.8-8210.95" - cell $and $and$ls180.v:8210$2607 + attribute \src "ls180.v:8308.8-8308.95" + cell $and $and$ls180.v:8308$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242466,10 +248071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8210$2607_Y + connect \Y $and$ls180.v:8308$2622_Y end - attribute \src "ls180.v:8218.8-8218.95" - cell $and $and$ls180.v:8218$2608 + attribute \src "ls180.v:8316.8-8316.95" + cell $and $and$ls180.v:8316$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242477,10 +248082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8218$2608_Y + connect \Y $and$ls180.v:8316$2623_Y end - attribute \src "ls180.v:8288.7-8288.100" - cell $and $and$ls180.v:8288$2618 + attribute \src "ls180.v:8386.7-8386.100" + cell $and $and$ls180.v:8386$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242488,10 +248093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8288$2618_Y + connect \Y $and$ls180.v:8386$2633_Y end - attribute \src "ls180.v:8289.8-8289.97" - cell $and $and$ls180.v:8289$2619 + attribute \src "ls180.v:8387.8-8387.97" + cell $and $and$ls180.v:8387$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242499,10 +248104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8289$2619_Y + connect \Y $and$ls180.v:8387$2634_Y end - attribute \src "ls180.v:8297.8-8297.97" - cell $and $and$ls180.v:8297$2620 + attribute \src "ls180.v:8395.8-8395.97" + cell $and $and$ls180.v:8395$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242510,10 +248115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8297$2620_Y + connect \Y $and$ls180.v:8395$2635_Y end - attribute \src "ls180.v:8388.7-8388.82" - cell $and $and$ls180.v:8388$2626 + attribute \src "ls180.v:8486.7-8486.82" + cell $and $and$ls180.v:8486$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242521,10 +248126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8388$2626_Y + connect \Y $and$ls180.v:8486$2641_Y end - attribute \src "ls180.v:8391.7-8391.82" - cell $and $and$ls180.v:8391$2627 + attribute \src "ls180.v:8489.7-8489.82" + cell $and $and$ls180.v:8489$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242532,10 +248137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8391$2627_Y + connect \Y $and$ls180.v:8489$2642_Y end - attribute \src "ls180.v:8394.7-8394.82" - cell $and $and$ls180.v:8394$2628 + attribute \src "ls180.v:8492.7-8492.82" + cell $and $and$ls180.v:8492$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242543,10 +248148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8394$2628_Y + connect \Y $and$ls180.v:8492$2643_Y end - attribute \src "ls180.v:8397.7-8397.82" - cell $and $and$ls180.v:8397$2629 + attribute \src "ls180.v:8495.7-8495.82" + cell $and $and$ls180.v:8495$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242554,10 +248159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8397$2629_Y + connect \Y $and$ls180.v:8495$2644_Y end - attribute \src "ls180.v:8400.7-8400.82" - cell $and $and$ls180.v:8400$2630 + attribute \src "ls180.v:8498.7-8498.82" + cell $and $and$ls180.v:8498$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242565,10 +248170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8400$2630_Y + connect \Y $and$ls180.v:8498$2645_Y end - attribute \src "ls180.v:8405.7-8405.82" - cell $and $and$ls180.v:8405$2631 + attribute \src "ls180.v:8503.7-8503.82" + cell $and $and$ls180.v:8503$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242576,10 +248181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8405$2631_Y + connect \Y $and$ls180.v:8503$2646_Y end - attribute \src "ls180.v:8410.7-8410.82" - cell $and $and$ls180.v:8410$2632 + attribute \src "ls180.v:8508.7-8508.82" + cell $and $and$ls180.v:8508$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242587,10 +248192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8410$2632_Y + connect \Y $and$ls180.v:8508$2647_Y end - attribute \src "ls180.v:8415.7-8415.82" - cell $and $and$ls180.v:8415$2633 + attribute \src "ls180.v:8513.7-8513.82" + cell $and $and$ls180.v:8513$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242598,10 +248203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8415$2633_Y + connect \Y $and$ls180.v:8513$2648_Y end - attribute \src "ls180.v:8420.7-8420.82" - cell $and $and$ls180.v:8420$2634 + attribute \src "ls180.v:8518.7-8518.82" + cell $and $and$ls180.v:8518$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242609,10 +248214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8420$2634_Y + connect \Y $and$ls180.v:8518$2649_Y end - attribute \src "ls180.v:8485.8-8485.83" - cell $and $and$ls180.v:8485$2637 + attribute \src "ls180.v:8583.8-8583.83" + cell $and $and$ls180.v:8583$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242620,21 +248225,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8485$2637_Y + connect \Y $and$ls180.v:8583$2652_Y end - attribute \src "ls180.v:8485.7-8485.119" - cell $and $and$ls180.v:8485$2639 + attribute \src "ls180.v:8583.7-8583.119" + cell $and $and$ls180.v:8583$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8485$2637_Y - connect \B $not$ls180.v:8485$2638_Y - connect \Y $and$ls180.v:8485$2639_Y + connect \A $and$ls180.v:8583$2652_Y + connect \B $not$ls180.v:8583$2653_Y + connect \Y $and$ls180.v:8583$2654_Y end - attribute \src "ls180.v:8491.8-8491.83" - cell $and $and$ls180.v:8491$2642 + attribute \src "ls180.v:8589.8-8589.83" + cell $and $and$ls180.v:8589$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242642,21 +248247,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8491$2642_Y + connect \Y $and$ls180.v:8589$2657_Y end - attribute \src "ls180.v:8491.7-8491.119" - cell $and $and$ls180.v:8491$2644 + attribute \src "ls180.v:8589.7-8589.119" + cell $and $and$ls180.v:8589$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8491$2642_Y - connect \B $not$ls180.v:8491$2643_Y - connect \Y $and$ls180.v:8491$2644_Y + connect \A $and$ls180.v:8589$2657_Y + connect \B $not$ls180.v:8589$2658_Y + connect \Y $and$ls180.v:8589$2659_Y end - attribute \src "ls180.v:8511.7-8511.88" - cell $and $and$ls180.v:8511$2651 + attribute \src "ls180.v:8609.7-8609.88" + cell $and $and$ls180.v:8609$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242664,10 +248269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8511$2651_Y + connect \Y $and$ls180.v:8609$2666_Y end - attribute \src "ls180.v:8512.8-8512.85" - cell $and $and$ls180.v:8512$2652 + attribute \src "ls180.v:8610.8-8610.85" + cell $and $and$ls180.v:8610$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242675,10 +248280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8512$2652_Y + connect \Y $and$ls180.v:8610$2667_Y end - attribute \src "ls180.v:8520.8-8520.85" - cell $and $and$ls180.v:8520$2653 + attribute \src "ls180.v:8618.8-8618.85" + cell $and $and$ls180.v:8618$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242686,10 +248291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8520$2653_Y + connect \Y $and$ls180.v:8618$2668_Y end - attribute \src "ls180.v:8564.7-8564.88" - cell $and $and$ls180.v:8564$2657 + attribute \src "ls180.v:8662.7-8662.88" + cell $and $and$ls180.v:8662$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242697,10 +248302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8564$2657_Y + connect \Y $and$ls180.v:8662$2672_Y end - attribute \src "ls180.v:8571.8-8571.83" - cell $and $and$ls180.v:8571$2659 + attribute \src "ls180.v:8669.8-8669.83" + cell $and $and$ls180.v:8669$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242708,21 +248313,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8571$2659_Y + connect \Y $and$ls180.v:8669$2674_Y end - attribute \src "ls180.v:8571.7-8571.119" - cell $and $and$ls180.v:8571$2661 + attribute \src "ls180.v:8669.7-8669.119" + cell $and $and$ls180.v:8669$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8571$2659_Y - connect \B $not$ls180.v:8571$2660_Y - connect \Y $and$ls180.v:8571$2661_Y + connect \A $and$ls180.v:8669$2674_Y + connect \B $not$ls180.v:8669$2675_Y + connect \Y $and$ls180.v:8669$2676_Y end - attribute \src "ls180.v:8577.8-8577.83" - cell $and $and$ls180.v:8577$2664 + attribute \src "ls180.v:8675.8-8675.83" + cell $and $and$ls180.v:8675$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242730,21 +248335,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8577$2664_Y + connect \Y $and$ls180.v:8675$2679_Y end - attribute \src "ls180.v:8577.7-8577.119" - cell $and $and$ls180.v:8577$2666 + attribute \src "ls180.v:8675.7-8675.119" + cell $and $and$ls180.v:8675$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8577$2664_Y - connect \B $not$ls180.v:8577$2665_Y - connect \Y $and$ls180.v:8577$2666_Y + connect \A $and$ls180.v:8675$2679_Y + connect \B $not$ls180.v:8675$2680_Y + connect \Y $and$ls180.v:8675$2681_Y end - attribute \src "ls180.v:2763.42-2763.101" - cell $eq $eq$ls180.v:2763$18 + attribute \src "ls180.v:2811.42-2811.101" + cell $eq $eq$ls180.v:2811$18 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -242752,10 +248357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2763$18_Y + connect \Y $eq$ls180.v:2811$18_Y end - attribute \src "ls180.v:2770.11-2770.54" - cell $eq $eq$ls180.v:2770$23 + attribute \src "ls180.v:2818.11-2818.54" + cell $eq $eq$ls180.v:2818$23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242763,10 +248368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2770$23_Y + connect \Y $eq$ls180.v:2818$23_Y end - attribute \src "ls180.v:2823.42-2823.101" - cell $eq $eq$ls180.v:2823$29 + attribute \src "ls180.v:2871.42-2871.101" + cell $eq $eq$ls180.v:2871$29 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -242774,10 +248379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2823$29_Y + connect \Y $eq$ls180.v:2871$29_Y end - attribute \src "ls180.v:2830.11-2830.54" - cell $eq $eq$ls180.v:2830$34 + attribute \src "ls180.v:2878.11-2878.54" + cell $eq $eq$ls180.v:2878$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242785,10 +248390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2830$34_Y + connect \Y $eq$ls180.v:2878$34_Y end - attribute \src "ls180.v:2883.42-2883.101" - cell $eq $eq$ls180.v:2883$40 + attribute \src "ls180.v:2931.42-2931.101" + cell $eq $eq$ls180.v:2931$40 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -242796,10 +248401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_sel connect \B 1'0 - connect \Y $eq$ls180.v:2883$40_Y + connect \Y $eq$ls180.v:2931$40_Y end - attribute \src "ls180.v:2890.11-2890.54" - cell $eq $eq$ls180.v:2890$45 + attribute \src "ls180.v:2938.11-2938.54" + cell $eq $eq$ls180.v:2938$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242807,10 +248412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_counter connect \B 1'1 - connect \Y $eq$ls180.v:2890$45_Y + connect \Y $eq$ls180.v:2938$45_Y end - attribute \src "ls180.v:3076.34-3076.65" - cell $eq $eq$ls180.v:3076$73 + attribute \src "ls180.v:3124.34-3124.65" + cell $eq $eq$ls180.v:3124$73 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -242818,10 +248423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3076$73_Y + connect \Y $eq$ls180.v:3124$73_Y end - attribute \src "ls180.v:3080.68-3080.102" - cell $eq $eq$ls180.v:3080$76 + attribute \src "ls180.v:3128.68-3128.102" + cell $eq $eq$ls180.v:3128$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242829,10 +248434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3080$76_Y + connect \Y $eq$ls180.v:3128$76_Y end - attribute \src "ls180.v:3124.43-3124.134" - cell $eq $eq$ls180.v:3124$81 + attribute \src "ls180.v:3172.43-3172.134" + cell $eq $eq$ls180.v:3172$81 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -242840,10 +248445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3124$81_Y + connect \Y $eq$ls180.v:3172$81_Y end - attribute \src "ls180.v:3141.47-3141.88" - cell $eq $eq$ls180.v:3141$94 + attribute \src "ls180.v:3189.47-3189.88" + cell $eq $eq$ls180.v:3189$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242851,10 +248456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3141$94_Y + connect \Y $eq$ls180.v:3189$94_Y end - attribute \src "ls180.v:3281.43-3281.134" - cell $eq $eq$ls180.v:3281$111 + attribute \src "ls180.v:3329.43-3329.134" + cell $eq $eq$ls180.v:3329$111 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -242862,10 +248467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3281$111_Y + connect \Y $eq$ls180.v:3329$111_Y end - attribute \src "ls180.v:3298.47-3298.88" - cell $eq $eq$ls180.v:3298$124 + attribute \src "ls180.v:3346.47-3346.88" + cell $eq $eq$ls180.v:3346$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242873,10 +248478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3298$124_Y + connect \Y $eq$ls180.v:3346$124_Y end - attribute \src "ls180.v:3438.43-3438.134" - cell $eq $eq$ls180.v:3438$141 + attribute \src "ls180.v:3486.43-3486.134" + cell $eq $eq$ls180.v:3486$141 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -242884,10 +248489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3438$141_Y + connect \Y $eq$ls180.v:3486$141_Y end - attribute \src "ls180.v:3455.47-3455.88" - cell $eq $eq$ls180.v:3455$154 + attribute \src "ls180.v:3503.47-3503.88" + cell $eq $eq$ls180.v:3503$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242895,10 +248500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3455$154_Y + connect \Y $eq$ls180.v:3503$154_Y end - attribute \src "ls180.v:3595.43-3595.134" - cell $eq $eq$ls180.v:3595$171 + attribute \src "ls180.v:3643.43-3643.134" + cell $eq $eq$ls180.v:3643$171 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -242906,10 +248511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3595$171_Y + connect \Y $eq$ls180.v:3643$171_Y end - attribute \src "ls180.v:3612.47-3612.88" - cell $eq $eq$ls180.v:3612$184 + attribute \src "ls180.v:3660.47-3660.88" + cell $eq $eq$ls180.v:3660$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242917,10 +248522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3612$184_Y + connect \Y $eq$ls180.v:3660$184_Y end - attribute \src "ls180.v:3749.32-3749.56" - cell $eq $eq$ls180.v:3749$231 + attribute \src "ls180.v:3797.32-3797.56" + cell $eq $eq$ls180.v:3797$231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -242928,10 +248533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3749$231_Y + connect \Y $eq$ls180.v:3797$231_Y end - attribute \src "ls180.v:3750.32-3750.56" - cell $eq $eq$ls180.v:3750$232 + attribute \src "ls180.v:3798.32-3798.56" + cell $eq $eq$ls180.v:3798$232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -242939,10 +248544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3750$232_Y + connect \Y $eq$ls180.v:3798$232_Y end - attribute \src "ls180.v:3761.339-3761.418" - cell $eq $eq$ls180.v:3761$246 + attribute \src "ls180.v:3809.339-3809.418" + cell $eq $eq$ls180.v:3809$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242950,10 +248555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3761$246_Y + connect \Y $eq$ls180.v:3809$246_Y end - attribute \src "ls180.v:3761.423-3761.504" - cell $eq $eq$ls180.v:3761$247 + attribute \src "ls180.v:3809.423-3809.504" + cell $eq $eq$ls180.v:3809$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242961,10 +248566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3761$247_Y + connect \Y $eq$ls180.v:3809$247_Y end - attribute \src "ls180.v:3762.339-3762.418" - cell $eq $eq$ls180.v:3762$259 + attribute \src "ls180.v:3810.339-3810.418" + cell $eq $eq$ls180.v:3810$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242972,10 +248577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3762$259_Y + connect \Y $eq$ls180.v:3810$259_Y end - attribute \src "ls180.v:3762.423-3762.504" - cell $eq $eq$ls180.v:3762$260 + attribute \src "ls180.v:3810.423-3810.504" + cell $eq $eq$ls180.v:3810$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242983,10 +248588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3762$260_Y + connect \Y $eq$ls180.v:3810$260_Y end - attribute \src "ls180.v:3763.339-3763.418" - cell $eq $eq$ls180.v:3763$272 + attribute \src "ls180.v:3811.339-3811.418" + cell $eq $eq$ls180.v:3811$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -242994,10 +248599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3763$272_Y + connect \Y $eq$ls180.v:3811$272_Y end - attribute \src "ls180.v:3763.423-3763.504" - cell $eq $eq$ls180.v:3763$273 + attribute \src "ls180.v:3811.423-3811.504" + cell $eq $eq$ls180.v:3811$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243005,10 +248610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3763$273_Y + connect \Y $eq$ls180.v:3811$273_Y end - attribute \src "ls180.v:3764.339-3764.418" - cell $eq $eq$ls180.v:3764$285 + attribute \src "ls180.v:3812.339-3812.418" + cell $eq $eq$ls180.v:3812$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243016,10 +248621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3764$285_Y + connect \Y $eq$ls180.v:3812$285_Y end - attribute \src "ls180.v:3764.423-3764.504" - cell $eq $eq$ls180.v:3764$286 + attribute \src "ls180.v:3812.423-3812.504" + cell $eq $eq$ls180.v:3812$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243027,10 +248632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3764$286_Y + connect \Y $eq$ls180.v:3812$286_Y end - attribute \src "ls180.v:3794.339-3794.418" - cell $eq $eq$ls180.v:3794$304 + attribute \src "ls180.v:3842.339-3842.418" + cell $eq $eq$ls180.v:3842$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243038,10 +248643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3794$304_Y + connect \Y $eq$ls180.v:3842$304_Y end - attribute \src "ls180.v:3794.423-3794.504" - cell $eq $eq$ls180.v:3794$305 + attribute \src "ls180.v:3842.423-3842.504" + cell $eq $eq$ls180.v:3842$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243049,10 +248654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3794$305_Y + connect \Y $eq$ls180.v:3842$305_Y end - attribute \src "ls180.v:3795.339-3795.418" - cell $eq $eq$ls180.v:3795$317 + attribute \src "ls180.v:3843.339-3843.418" + cell $eq $eq$ls180.v:3843$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243060,10 +248665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3795$317_Y + connect \Y $eq$ls180.v:3843$317_Y end - attribute \src "ls180.v:3795.423-3795.504" - cell $eq $eq$ls180.v:3795$318 + attribute \src "ls180.v:3843.423-3843.504" + cell $eq $eq$ls180.v:3843$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243071,10 +248676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3795$318_Y + connect \Y $eq$ls180.v:3843$318_Y end - attribute \src "ls180.v:3796.339-3796.418" - cell $eq $eq$ls180.v:3796$330 + attribute \src "ls180.v:3844.339-3844.418" + cell $eq $eq$ls180.v:3844$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243082,10 +248687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3796$330_Y + connect \Y $eq$ls180.v:3844$330_Y end - attribute \src "ls180.v:3796.423-3796.504" - cell $eq $eq$ls180.v:3796$331 + attribute \src "ls180.v:3844.423-3844.504" + cell $eq $eq$ls180.v:3844$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243093,10 +248698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3796$331_Y + connect \Y $eq$ls180.v:3844$331_Y end - attribute \src "ls180.v:3797.339-3797.418" - cell $eq $eq$ls180.v:3797$343 + attribute \src "ls180.v:3845.339-3845.418" + cell $eq $eq$ls180.v:3845$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243104,10 +248709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3797$343_Y + connect \Y $eq$ls180.v:3845$343_Y end - attribute \src "ls180.v:3797.423-3797.504" - cell $eq $eq$ls180.v:3797$344 + attribute \src "ls180.v:3845.423-3845.504" + cell $eq $eq$ls180.v:3845$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243115,10 +248720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3797$344_Y + connect \Y $eq$ls180.v:3845$344_Y end - attribute \src "ls180.v:3826.78-3826.113" - cell $eq $eq$ls180.v:3826$353 + attribute \src "ls180.v:3874.78-3874.113" + cell $eq $eq$ls180.v:3874$353 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243126,10 +248731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:3826$353_Y + connect \Y $eq$ls180.v:3874$353_Y end - attribute \src "ls180.v:3829.78-3829.113" - cell $eq $eq$ls180.v:3829$356 + attribute \src "ls180.v:3877.78-3877.113" + cell $eq $eq$ls180.v:3877$356 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243137,10 +248742,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:3829$356_Y + connect \Y $eq$ls180.v:3877$356_Y end - attribute \src "ls180.v:3835.78-3835.113" - cell $eq $eq$ls180.v:3835$360 + attribute \src "ls180.v:3883.78-3883.113" + cell $eq $eq$ls180.v:3883$360 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243148,10 +248753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:3835$360_Y + connect \Y $eq$ls180.v:3883$360_Y end - attribute \src "ls180.v:3838.78-3838.113" - cell $eq $eq$ls180.v:3838$363 + attribute \src "ls180.v:3886.78-3886.113" + cell $eq $eq$ls180.v:3886$363 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243159,10 +248764,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:3838$363_Y + connect \Y $eq$ls180.v:3886$363_Y end - attribute \src "ls180.v:3844.78-3844.113" - cell $eq $eq$ls180.v:3844$367 + attribute \src "ls180.v:3892.78-3892.113" + cell $eq $eq$ls180.v:3892$367 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243170,10 +248775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:3844$367_Y + connect \Y $eq$ls180.v:3892$367_Y end - attribute \src "ls180.v:3847.78-3847.113" - cell $eq $eq$ls180.v:3847$370 + attribute \src "ls180.v:3895.78-3895.113" + cell $eq $eq$ls180.v:3895$370 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243181,10 +248786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:3847$370_Y + connect \Y $eq$ls180.v:3895$370_Y end - attribute \src "ls180.v:3853.78-3853.113" - cell $eq $eq$ls180.v:3853$374 + attribute \src "ls180.v:3901.78-3901.113" + cell $eq $eq$ls180.v:3901$374 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243192,10 +248797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:3853$374_Y + connect \Y $eq$ls180.v:3901$374_Y end - attribute \src "ls180.v:3856.78-3856.113" - cell $eq $eq$ls180.v:3856$377 + attribute \src "ls180.v:3904.78-3904.113" + cell $eq $eq$ls180.v:3904$377 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243203,10 +248808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:3856$377_Y + connect \Y $eq$ls180.v:3904$377_Y end - attribute \src "ls180.v:3937.42-3937.82" - cell $eq $eq$ls180.v:3937$400 + attribute \src "ls180.v:3985.42-3985.82" + cell $eq $eq$ls180.v:3985$400 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243214,10 +248819,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3937$400_Y + connect \Y $eq$ls180.v:3985$400_Y end - attribute \src "ls180.v:3937.145-3937.178" - cell $eq $eq$ls180.v:3937$401 + attribute \src "ls180.v:3985.145-3985.178" + cell $eq $eq$ls180.v:3985$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243225,10 +248830,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3937$401_Y + connect \Y $eq$ls180.v:3985$401_Y end - attribute \src "ls180.v:3937.220-3937.253" - cell $eq $eq$ls180.v:3937$404 + attribute \src "ls180.v:3985.220-3985.253" + cell $eq $eq$ls180.v:3985$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243236,10 +248841,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3937$404_Y + connect \Y $eq$ls180.v:3985$404_Y end - attribute \src "ls180.v:3937.295-3937.328" - cell $eq $eq$ls180.v:3937$407 + attribute \src "ls180.v:3985.295-3985.328" + cell $eq $eq$ls180.v:3985$407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243247,10 +248852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3937$407_Y + connect \Y $eq$ls180.v:3985$407_Y end - attribute \src "ls180.v:3942.42-3942.82" - cell $eq $eq$ls180.v:3942$416 + attribute \src "ls180.v:3990.42-3990.82" + cell $eq $eq$ls180.v:3990$416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243258,10 +248863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3942$416_Y + connect \Y $eq$ls180.v:3990$416_Y end - attribute \src "ls180.v:3942.145-3942.178" - cell $eq $eq$ls180.v:3942$417 + attribute \src "ls180.v:3990.145-3990.178" + cell $eq $eq$ls180.v:3990$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243269,10 +248874,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3942$417_Y + connect \Y $eq$ls180.v:3990$417_Y end - attribute \src "ls180.v:3942.220-3942.253" - cell $eq $eq$ls180.v:3942$420 + attribute \src "ls180.v:3990.220-3990.253" + cell $eq $eq$ls180.v:3990$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243280,10 +248885,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3942$420_Y + connect \Y $eq$ls180.v:3990$420_Y end - attribute \src "ls180.v:3942.295-3942.328" - cell $eq $eq$ls180.v:3942$423 + attribute \src "ls180.v:3990.295-3990.328" + cell $eq $eq$ls180.v:3990$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243291,10 +248896,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3942$423_Y + connect \Y $eq$ls180.v:3990$423_Y end - attribute \src "ls180.v:3947.42-3947.82" - cell $eq $eq$ls180.v:3947$432 + attribute \src "ls180.v:3995.42-3995.82" + cell $eq $eq$ls180.v:3995$432 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243302,10 +248907,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3947$432_Y + connect \Y $eq$ls180.v:3995$432_Y end - attribute \src "ls180.v:3947.145-3947.178" - cell $eq $eq$ls180.v:3947$433 + attribute \src "ls180.v:3995.145-3995.178" + cell $eq $eq$ls180.v:3995$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243313,10 +248918,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3947$433_Y + connect \Y $eq$ls180.v:3995$433_Y end - attribute \src "ls180.v:3947.220-3947.253" - cell $eq $eq$ls180.v:3947$436 + attribute \src "ls180.v:3995.220-3995.253" + cell $eq $eq$ls180.v:3995$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243324,10 +248929,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3947$436_Y + connect \Y $eq$ls180.v:3995$436_Y end - attribute \src "ls180.v:3947.295-3947.328" - cell $eq $eq$ls180.v:3947$439 + attribute \src "ls180.v:3995.295-3995.328" + cell $eq $eq$ls180.v:3995$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243335,10 +248940,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3947$439_Y + connect \Y $eq$ls180.v:3995$439_Y end - attribute \src "ls180.v:3952.42-3952.82" - cell $eq $eq$ls180.v:3952$448 + attribute \src "ls180.v:4000.42-4000.82" + cell $eq $eq$ls180.v:4000$448 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243346,10 +248951,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3952$448_Y + connect \Y $eq$ls180.v:4000$448_Y end - attribute \src "ls180.v:3952.145-3952.178" - cell $eq $eq$ls180.v:3952$449 + attribute \src "ls180.v:4000.145-4000.178" + cell $eq $eq$ls180.v:4000$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243357,10 +248962,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3952$449_Y + connect \Y $eq$ls180.v:4000$449_Y end - attribute \src "ls180.v:3952.220-3952.253" - cell $eq $eq$ls180.v:3952$452 + attribute \src "ls180.v:4000.220-4000.253" + cell $eq $eq$ls180.v:4000$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243368,10 +248973,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3952$452_Y + connect \Y $eq$ls180.v:4000$452_Y end - attribute \src "ls180.v:3952.295-3952.328" - cell $eq $eq$ls180.v:3952$455 + attribute \src "ls180.v:4000.295-4000.328" + cell $eq $eq$ls180.v:4000$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243379,10 +248984,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3952$455_Y + connect \Y $eq$ls180.v:4000$455_Y end - attribute \src "ls180.v:3957.44-3957.77" - cell $eq $eq$ls180.v:3957$464 + attribute \src "ls180.v:4005.44-4005.77" + cell $eq $eq$ls180.v:4005$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243390,10 +248995,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$464_Y + connect \Y $eq$ls180.v:4005$464_Y end - attribute \src "ls180.v:3957.83-3957.123" - cell $eq $eq$ls180.v:3957$465 + attribute \src "ls180.v:4005.83-4005.123" + cell $eq $eq$ls180.v:4005$465 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243401,10 +249006,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:3957$465_Y + connect \Y $eq$ls180.v:4005$465_Y end - attribute \src "ls180.v:3957.186-3957.219" - cell $eq $eq$ls180.v:3957$466 + attribute \src "ls180.v:4005.186-4005.219" + cell $eq $eq$ls180.v:4005$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243412,10 +249017,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$466_Y + connect \Y $eq$ls180.v:4005$466_Y end - attribute \src "ls180.v:3957.261-3957.294" - cell $eq $eq$ls180.v:3957$469 + attribute \src "ls180.v:4005.261-4005.294" + cell $eq $eq$ls180.v:4005$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243423,10 +249028,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$469_Y + connect \Y $eq$ls180.v:4005$469_Y end - attribute \src "ls180.v:3957.336-3957.369" - cell $eq $eq$ls180.v:3957$472 + attribute \src "ls180.v:4005.336-4005.369" + cell $eq $eq$ls180.v:4005$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243434,10 +249039,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$472_Y + connect \Y $eq$ls180.v:4005$472_Y end - attribute \src "ls180.v:3957.418-3957.451" - cell $eq $eq$ls180.v:3957$480 + attribute \src "ls180.v:4005.418-4005.451" + cell $eq $eq$ls180.v:4005$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243445,10 +249050,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$480_Y + connect \Y $eq$ls180.v:4005$480_Y end - attribute \src "ls180.v:3957.457-3957.497" - cell $eq $eq$ls180.v:3957$481 + attribute \src "ls180.v:4005.457-4005.497" + cell $eq $eq$ls180.v:4005$481 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243456,10 +249061,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:3957$481_Y + connect \Y $eq$ls180.v:4005$481_Y end - attribute \src "ls180.v:3957.560-3957.593" - cell $eq $eq$ls180.v:3957$482 + attribute \src "ls180.v:4005.560-4005.593" + cell $eq $eq$ls180.v:4005$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243467,10 +249072,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$482_Y + connect \Y $eq$ls180.v:4005$482_Y end - attribute \src "ls180.v:3957.635-3957.668" - cell $eq $eq$ls180.v:3957$485 + attribute \src "ls180.v:4005.635-4005.668" + cell $eq $eq$ls180.v:4005$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243478,10 +249083,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$485_Y + connect \Y $eq$ls180.v:4005$485_Y end - attribute \src "ls180.v:3957.710-3957.743" - cell $eq $eq$ls180.v:3957$488 + attribute \src "ls180.v:4005.710-4005.743" + cell $eq $eq$ls180.v:4005$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243489,10 +249094,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$488_Y + connect \Y $eq$ls180.v:4005$488_Y end - attribute \src "ls180.v:3957.792-3957.825" - cell $eq $eq$ls180.v:3957$496 + attribute \src "ls180.v:4005.792-4005.825" + cell $eq $eq$ls180.v:4005$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243500,10 +249105,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$496_Y + connect \Y $eq$ls180.v:4005$496_Y end - attribute \src "ls180.v:3957.831-3957.871" - cell $eq $eq$ls180.v:3957$497 + attribute \src "ls180.v:4005.831-4005.871" + cell $eq $eq$ls180.v:4005$497 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243511,10 +249116,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:3957$497_Y + connect \Y $eq$ls180.v:4005$497_Y end - attribute \src "ls180.v:3957.934-3957.967" - cell $eq $eq$ls180.v:3957$498 + attribute \src "ls180.v:4005.934-4005.967" + cell $eq $eq$ls180.v:4005$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243522,10 +249127,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$498_Y + connect \Y $eq$ls180.v:4005$498_Y end - attribute \src "ls180.v:3957.1009-3957.1042" - cell $eq $eq$ls180.v:3957$501 + attribute \src "ls180.v:4005.1009-4005.1042" + cell $eq $eq$ls180.v:4005$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243533,10 +249138,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$501_Y + connect \Y $eq$ls180.v:4005$501_Y end - attribute \src "ls180.v:3957.1084-3957.1117" - cell $eq $eq$ls180.v:3957$504 + attribute \src "ls180.v:4005.1084-4005.1117" + cell $eq $eq$ls180.v:4005$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243544,10 +249149,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$504_Y + connect \Y $eq$ls180.v:4005$504_Y end - attribute \src "ls180.v:3957.1166-3957.1199" - cell $eq $eq$ls180.v:3957$512 + attribute \src "ls180.v:4005.1166-4005.1199" + cell $eq $eq$ls180.v:4005$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243555,10 +249160,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$512_Y + connect \Y $eq$ls180.v:4005$512_Y end - attribute \src "ls180.v:3957.1205-3957.1245" - cell $eq $eq$ls180.v:3957$513 + attribute \src "ls180.v:4005.1205-4005.1245" + cell $eq $eq$ls180.v:4005$513 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243566,10 +249171,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:3957$513_Y + connect \Y $eq$ls180.v:4005$513_Y end - attribute \src "ls180.v:3957.1308-3957.1341" - cell $eq $eq$ls180.v:3957$514 + attribute \src "ls180.v:4005.1308-4005.1341" + cell $eq $eq$ls180.v:4005$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243577,10 +249182,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$514_Y + connect \Y $eq$ls180.v:4005$514_Y end - attribute \src "ls180.v:3957.1383-3957.1416" - cell $eq $eq$ls180.v:3957$517 + attribute \src "ls180.v:4005.1383-4005.1416" + cell $eq $eq$ls180.v:4005$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243588,10 +249193,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$517_Y + connect \Y $eq$ls180.v:4005$517_Y end - attribute \src "ls180.v:3957.1458-3957.1491" - cell $eq $eq$ls180.v:3957$520 + attribute \src "ls180.v:4005.1458-4005.1491" + cell $eq $eq$ls180.v:4005$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243599,10 +249204,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:3957$520_Y + connect \Y $eq$ls180.v:4005$520_Y end - attribute \src "ls180.v:4016.29-4016.57" - cell $eq $eq$ls180.v:4016$533 + attribute \src "ls180.v:4064.29-4064.57" + cell $eq $eq$ls180.v:4064$533 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243610,10 +249215,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4016$533_Y + connect \Y $eq$ls180.v:4064$533_Y end - attribute \src "ls180.v:4023.11-4023.41" - cell $eq $eq$ls180.v:4023$538 + attribute \src "ls180.v:4071.11-4071.41" + cell $eq $eq$ls180.v:4071$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243621,43 +249226,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4023$538_Y + connect \Y $eq$ls180.v:4071$538_Y end - attribute \src "ls180.v:4180.36-4180.111" - cell $eq $eq$ls180.v:4180$603 + attribute \src "ls180.v:4228.37-4228.111" + cell $eq $eq$ls180.v:4228$603 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4180$602_Y - connect \Y $eq$ls180.v:4180$603_Y + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4228$602_Y + connect \Y $eq$ls180.v:4228$603_Y end - attribute \src "ls180.v:4181.36-4181.105" - cell $eq $eq$ls180.v:4181$605 + attribute \src "ls180.v:4229.37-4229.105" + cell $eq $eq$ls180.v:4229$605 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \main_spi_master_clk_divider1 - connect \B $sub$ls180.v:4181$604_Y - connect \Y $eq$ls180.v:4181$605_Y + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4229$604_Y + connect \Y $eq$ls180.v:4229$605_Y end - attribute \src "ls180.v:4208.10-4208.67" - cell $eq $eq$ls180.v:4208$609 + attribute \src "ls180.v:4256.10-4256.67" + cell $eq $eq$ls180.v:4256$609 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \main_spi_master_count - connect \B $sub$ls180.v:4208$608_Y - connect \Y $eq$ls180.v:4208$609_Y + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4256$608_Y + connect \Y $eq$ls180.v:4256$609_Y end - attribute \src "ls180.v:4308.10-4308.40" - cell $eq $eq$ls180.v:4308$636 + attribute \src "ls180.v:4286.35-4286.108" + cell $eq $eq$ls180.v:4286$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4286$610_Y + connect \Y $eq$ls180.v:4286$611_Y + end + attribute \src "ls180.v:4287.35-4287.102" + cell $eq $eq$ls180.v:4287$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4287$612_Y + connect \Y $eq$ls180.v:4287$613_Y + end + attribute \src "ls180.v:4315.10-4315.65" + cell $eq $eq$ls180.v:4315$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4315$616_Y + connect \Y $eq$ls180.v:4315$617_Y + end + attribute \src "ls180.v:4419.10-4419.40" + cell $eq $eq$ls180.v:4419$644 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243665,10 +249303,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4308$636_Y + connect \Y $eq$ls180.v:4419$644_Y end - attribute \src "ls180.v:4365.10-4365.39" - cell $eq $eq$ls180.v:4365$639 + attribute \src "ls180.v:4476.10-4476.39" + cell $eq $eq$ls180.v:4476$647 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243676,10 +249314,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4365$639_Y + connect \Y $eq$ls180.v:4476$647_Y end - attribute \src "ls180.v:4382.10-4382.39" - cell $eq $eq$ls180.v:4382$641 + attribute \src "ls180.v:4493.10-4493.39" + cell $eq $eq$ls180.v:4493$649 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243687,10 +249325,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4382$641_Y + connect \Y $eq$ls180.v:4493$649_Y end - attribute \src "ls180.v:4410.38-4410.88" - cell $eq $eq$ls180.v:4410$643 + attribute \src "ls180.v:4521.38-4521.88" + cell $eq $eq$ls180.v:4521$651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243698,10 +249336,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4410$643_Y + connect \Y $eq$ls180.v:4521$651_Y end - attribute \src "ls180.v:4460.9-4460.40" - cell $eq $eq$ls180.v:4460$653 + attribute \src "ls180.v:4571.9-4571.40" + cell $eq $eq$ls180.v:4571$661 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -243709,21 +249347,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4460$653_Y + connect \Y $eq$ls180.v:4571$661_Y end - attribute \src "ls180.v:4469.36-4469.105" - cell $eq $eq$ls180.v:4469$655 + attribute \src "ls180.v:4580.36-4580.105" + cell $eq $eq$ls180.v:4580$663 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4469$654_Y - connect \Y $eq$ls180.v:4469$655_Y + connect \B $sub$ls180.v:4580$662_Y + connect \Y $eq$ls180.v:4580$663_Y end - attribute \src "ls180.v:4488.9-4488.40" - cell $eq $eq$ls180.v:4488$659 + attribute \src "ls180.v:4599.9-4599.40" + cell $eq $eq$ls180.v:4599$667 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -243731,10 +249369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4488$659_Y + connect \Y $eq$ls180.v:4599$667_Y end - attribute \src "ls180.v:4500.10-4500.39" - cell $eq $eq$ls180.v:4500$661 + attribute \src "ls180.v:4611.10-4611.39" + cell $eq $eq$ls180.v:4611$669 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243742,10 +249380,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4500$661_Y + connect \Y $eq$ls180.v:4611$669_Y end - attribute \src "ls180.v:4537.39-4537.94" - cell $eq $eq$ls180.v:4537$665 + attribute \src "ls180.v:4648.39-4648.94" + cell $eq $eq$ls180.v:4648$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -243753,10 +249391,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4537$665_Y + connect \Y $eq$ls180.v:4648$673_Y end - attribute \src "ls180.v:4574.32-4574.89" - cell $eq $eq$ls180.v:4574$674 + attribute \src "ls180.v:4685.32-4685.89" + cell $eq $eq$ls180.v:4685$682 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243764,10 +249402,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4574$674_Y + connect \Y $eq$ls180.v:4685$682_Y end - attribute \src "ls180.v:4622.10-4622.40" - cell $eq $eq$ls180.v:4622$678 + attribute \src "ls180.v:4733.10-4733.40" + cell $eq $eq$ls180.v:4733$686 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -243775,10 +249413,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4622$678_Y + connect \Y $eq$ls180.v:4733$686_Y end - attribute \src "ls180.v:4671.40-4671.98" - cell $eq $eq$ls180.v:4671$680 + attribute \src "ls180.v:4782.40-4782.98" + cell $eq $eq$ls180.v:4782$688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -243786,10 +249424,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4671$680_Y + connect \Y $eq$ls180.v:4782$688_Y end - attribute \src "ls180.v:4722.9-4722.41" - cell $eq $eq$ls180.v:4722$690 + attribute \src "ls180.v:4833.9-4833.41" + cell $eq $eq$ls180.v:4833$698 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -243797,21 +249435,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4722$690_Y + connect \Y $eq$ls180.v:4833$698_Y end - attribute \src "ls180.v:4731.37-4731.123" - cell $eq $eq$ls180.v:4731$693 + attribute \src "ls180.v:4842.37-4842.123" + cell $eq $eq$ls180.v:4842$701 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4731$692_Y - connect \Y $eq$ls180.v:4731$693_Y + connect \B $sub$ls180.v:4842$700_Y + connect \Y $eq$ls180.v:4842$701_Y end - attribute \src "ls180.v:4754.9-4754.41" - cell $eq $eq$ls180.v:4754$696 + attribute \src "ls180.v:4865.9-4865.41" + cell $eq $eq$ls180.v:4865$704 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -243819,10 +249457,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4754$696_Y + connect \Y $eq$ls180.v:4865$704_Y end - attribute \src "ls180.v:4764.10-4764.41" - cell $eq $eq$ls180.v:4764$698 + attribute \src "ls180.v:4875.10-4875.41" + cell $eq $eq$ls180.v:4875$706 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -243830,10 +249468,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:4764$698_Y + connect \Y $eq$ls180.v:4875$706_Y end - attribute \src "ls180.v:4933.9-4933.47" - cell $eq $eq$ls180.v:4933$880 + attribute \src "ls180.v:5044.9-5044.47" + cell $eq $eq$ls180.v:5044$888 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -243841,10 +249479,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:4933$880_Y + connect \Y $eq$ls180.v:5044$888_Y end - attribute \src "ls180.v:4963.10-4963.48" - cell $eq $eq$ls180.v:4963$881 + attribute \src "ls180.v:5074.10-5074.48" + cell $eq $eq$ls180.v:5074$889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -243852,10 +249490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:4963$881_Y + connect \Y $eq$ls180.v:5074$889_Y end - attribute \src "ls180.v:4994.10-4994.78" - cell $eq $eq$ls180.v:4994$886 + attribute \src "ls180.v:5105.10-5105.78" + cell $eq $eq$ls180.v:5105$894 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -243863,10 +249501,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:4994$886_Y + connect \Y $eq$ls180.v:5105$894_Y end - attribute \src "ls180.v:4994.83-4994.151" - cell $eq $eq$ls180.v:4994$887 + attribute \src "ls180.v:5105.83-5105.151" + cell $eq $eq$ls180.v:5105$895 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -243874,10 +249512,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:4994$887_Y + connect \Y $eq$ls180.v:5105$895_Y end - attribute \src "ls180.v:4994.157-4994.225" - cell $eq $eq$ls180.v:4994$889 + attribute \src "ls180.v:5105.157-5105.225" + cell $eq $eq$ls180.v:5105$897 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -243885,10 +249523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:4994$889_Y + connect \Y $eq$ls180.v:5105$897_Y end - attribute \src "ls180.v:4994.231-4994.299" - cell $eq $eq$ls180.v:4994$891 + attribute \src "ls180.v:5105.231-5105.299" + cell $eq $eq$ls180.v:5105$899 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -243896,10 +249534,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:4994$891_Y + connect \Y $eq$ls180.v:5105$899_Y end - attribute \src "ls180.v:5002.7-5002.44" - cell $eq $eq$ls180.v:5002$895 + attribute \src "ls180.v:5113.7-5113.44" + cell $eq $eq$ls180.v:5113$903 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -243907,10 +249545,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5002$895_Y + connect \Y $eq$ls180.v:5113$903_Y end - attribute \src "ls180.v:5012.7-5012.44" - cell $eq $eq$ls180.v:5012$898 + attribute \src "ls180.v:5123.7-5123.44" + cell $eq $eq$ls180.v:5123$906 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -243918,10 +249556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5012$898_Y + connect \Y $eq$ls180.v:5123$906_Y end - attribute \src "ls180.v:5022.7-5022.44" - cell $eq $eq$ls180.v:5022$901 + attribute \src "ls180.v:5133.7-5133.44" + cell $eq $eq$ls180.v:5133$909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -243929,10 +249567,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5022$901_Y + connect \Y $eq$ls180.v:5133$909_Y end - attribute \src "ls180.v:5032.7-5032.44" - cell $eq $eq$ls180.v:5032$904 + attribute \src "ls180.v:5143.7-5143.44" + cell $eq $eq$ls180.v:5143$912 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -243940,10 +249578,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5032$904_Y + connect \Y $eq$ls180.v:5143$912_Y end - attribute \src "ls180.v:5156.36-5156.64" - cell $eq $eq$ls180.v:5156$955 + attribute \src "ls180.v:5267.36-5267.64" + cell $eq $eq$ls180.v:5267$963 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243951,10 +249589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5156$955_Y + connect \Y $eq$ls180.v:5267$963_Y end - attribute \src "ls180.v:5162.10-5162.39" - cell $eq $eq$ls180.v:5162$958 + attribute \src "ls180.v:5273.10-5273.39" + cell $eq $eq$ls180.v:5273$966 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -243962,10 +249600,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5162$958_Y + connect \Y $eq$ls180.v:5273$966_Y end - attribute \src "ls180.v:5163.11-5163.39" - cell $eq $eq$ls180.v:5163$959 + attribute \src "ls180.v:5274.11-5274.39" + cell $eq $eq$ls180.v:5274$967 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243973,10 +249611,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5163$959_Y + connect \Y $eq$ls180.v:5274$967_Y end - attribute \src "ls180.v:5175.34-5175.63" - cell $eq $eq$ls180.v:5175$960 + attribute \src "ls180.v:5286.34-5286.63" + cell $eq $eq$ls180.v:5286$968 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243984,10 +249622,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5175$960_Y + connect \Y $eq$ls180.v:5286$968_Y end - attribute \src "ls180.v:5176.9-5176.37" - cell $eq $eq$ls180.v:5176$961 + attribute \src "ls180.v:5287.9-5287.37" + cell $eq $eq$ls180.v:5287$969 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -243995,10 +249633,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5176$961_Y + connect \Y $eq$ls180.v:5287$969_Y end - attribute \src "ls180.v:5183.10-5183.55" - cell $eq $eq$ls180.v:5183$962 + attribute \src "ls180.v:5294.10-5294.55" + cell $eq $eq$ls180.v:5294$970 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244006,10 +249644,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5183$962_Y + connect \Y $eq$ls180.v:5294$970_Y end - attribute \src "ls180.v:5189.12-5189.41" - cell $eq $eq$ls180.v:5189$963 + attribute \src "ls180.v:5300.12-5300.41" + cell $eq $eq$ls180.v:5300$971 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -244017,10 +249655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5189$963_Y + connect \Y $eq$ls180.v:5300$971_Y end - attribute \src "ls180.v:5192.13-5192.42" - cell $eq $eq$ls180.v:5192$964 + attribute \src "ls180.v:5303.13-5303.42" + cell $eq $eq$ls180.v:5303$972 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -244028,32 +249666,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5192$964_Y + connect \Y $eq$ls180.v:5303$972_Y end - attribute \src "ls180.v:5214.10-5214.76" - cell $eq $eq$ls180.v:5214$969 + attribute \src "ls180.v:5325.10-5325.76" + cell $eq $eq$ls180.v:5325$977 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5214$968_Y - connect \Y $eq$ls180.v:5214$969_Y + connect \B $sub$ls180.v:5325$976_Y + connect \Y $eq$ls180.v:5325$977_Y end - attribute \src "ls180.v:5229.35-5229.101" - cell $eq $eq$ls180.v:5229$972 + attribute \src "ls180.v:5340.35-5340.101" + cell $eq $eq$ls180.v:5340$980 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5229$971_Y - connect \Y $eq$ls180.v:5229$972_Y + connect \B $sub$ls180.v:5340$979_Y + connect \Y $eq$ls180.v:5340$980_Y end - attribute \src "ls180.v:5231.10-5231.56" - cell $eq $eq$ls180.v:5231$973 + attribute \src "ls180.v:5342.10-5342.56" + cell $eq $eq$ls180.v:5342$981 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244061,21 +249699,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5231$973_Y + connect \Y $eq$ls180.v:5342$981_Y end - attribute \src "ls180.v:5240.12-5240.78" - cell $eq $eq$ls180.v:5240$977 + attribute \src "ls180.v:5351.12-5351.78" + cell $eq $eq$ls180.v:5351$985 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5240$976_Y - connect \Y $eq$ls180.v:5240$977_Y + connect \B $sub$ls180.v:5351$984_Y + connect \Y $eq$ls180.v:5351$985_Y end - attribute \src "ls180.v:5247.11-5247.57" - cell $eq $eq$ls180.v:5247$978 + attribute \src "ls180.v:5358.11-5358.57" + cell $eq $eq$ls180.v:5358$986 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244083,32 +249721,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5247$978_Y + connect \Y $eq$ls180.v:5358$986_Y end - attribute \src "ls180.v:5364.10-5364.105" - cell $eq $eq$ls180.v:5364$995 + attribute \src "ls180.v:5475.10-5475.105" + cell $eq $eq$ls180.v:5475$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5364$994_Y - connect \Y $eq$ls180.v:5364$995_Y + connect \B $sub$ls180.v:5475$1002_Y + connect \Y $eq$ls180.v:5475$1003_Y end - attribute \src "ls180.v:5454.39-5454.106" - cell $eq $eq$ls180.v:5454$1001 + attribute \src "ls180.v:5565.39-5565.106" + cell $eq $eq$ls180.v:5565$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5454$1000_Y - connect \Y $eq$ls180.v:5454$1001_Y + connect \B $sub$ls180.v:5565$1008_Y + connect \Y $eq$ls180.v:5565$1009_Y end - attribute \src "ls180.v:5484.44-5484.82" - cell $eq $eq$ls180.v:5484$1004 + attribute \src "ls180.v:5595.44-5595.82" + cell $eq $eq$ls180.v:5595$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -244116,10 +249754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5484$1004_Y + connect \Y $eq$ls180.v:5595$1012_Y end - attribute \src "ls180.v:5485.43-5485.81" - cell $eq $eq$ls180.v:5485$1005 + attribute \src "ls180.v:5596.43-5596.81" + cell $eq $eq$ls180.v:5596$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -244127,43 +249765,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 2'11 - connect \Y $eq$ls180.v:5485$1005_Y - end - attribute \src "ls180.v:5542.32-5542.99" - cell $eq $eq$ls180.v:5542$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5542$1017_Y - connect \Y $eq$ls180.v:5542$1018_Y - end - attribute \src "ls180.v:5543.32-5543.93" - cell $eq $eq$ls180.v:5543$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \libresocsim_clk_divider1 - connect \B $sub$ls180.v:5543$1019_Y - connect \Y $eq$ls180.v:5543$1020_Y + connect \Y $eq$ls180.v:5596$1013_Y end - attribute \src "ls180.v:5571.10-5571.59" - cell $eq $eq$ls180.v:5571$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \libresocsim_count - connect \B $sub$ls180.v:5571$1023_Y - connect \Y $eq$ls180.v:5571$1024_Y - end - attribute \src "ls180.v:5644.85-5644.106" - cell $eq $eq$ls180.v:5644$1029 + attribute \src "ls180.v:5696.85-5696.106" + cell $eq $eq$ls180.v:5696$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244171,10 +249776,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5644$1029_Y + connect \Y $eq$ls180.v:5696$1029_Y end - attribute \src "ls180.v:5645.85-5645.106" - cell $eq $eq$ls180.v:5645$1031 + attribute \src "ls180.v:5697.85-5697.106" + cell $eq $eq$ls180.v:5697$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244182,10 +249787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5645$1031_Y + connect \Y $eq$ls180.v:5697$1031_Y end - attribute \src "ls180.v:5646.85-5646.106" - cell $eq $eq$ls180.v:5646$1033 + attribute \src "ls180.v:5698.85-5698.106" + cell $eq $eq$ls180.v:5698$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244193,10 +249798,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5646$1033_Y + connect \Y $eq$ls180.v:5698$1033_Y end - attribute \src "ls180.v:5647.57-5647.78" - cell $eq $eq$ls180.v:5647$1035 + attribute \src "ls180.v:5699.57-5699.78" + cell $eq $eq$ls180.v:5699$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244204,10 +249809,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5647$1035_Y + connect \Y $eq$ls180.v:5699$1035_Y end - attribute \src "ls180.v:5648.57-5648.78" - cell $eq $eq$ls180.v:5648$1037 + attribute \src "ls180.v:5700.57-5700.78" + cell $eq $eq$ls180.v:5700$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244215,10 +249820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5648$1037_Y + connect \Y $eq$ls180.v:5700$1037_Y end - attribute \src "ls180.v:5649.85-5649.106" - cell $eq $eq$ls180.v:5649$1039 + attribute \src "ls180.v:5701.85-5701.106" + cell $eq $eq$ls180.v:5701$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244226,10 +249831,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5649$1039_Y + connect \Y $eq$ls180.v:5701$1039_Y end - attribute \src "ls180.v:5650.85-5650.106" - cell $eq $eq$ls180.v:5650$1041 + attribute \src "ls180.v:5702.85-5702.106" + cell $eq $eq$ls180.v:5702$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244237,10 +249842,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5650$1041_Y + connect \Y $eq$ls180.v:5702$1041_Y end - attribute \src "ls180.v:5651.85-5651.106" - cell $eq $eq$ls180.v:5651$1043 + attribute \src "ls180.v:5703.85-5703.106" + cell $eq $eq$ls180.v:5703$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244248,10 +249853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5651$1043_Y + connect \Y $eq$ls180.v:5703$1043_Y end - attribute \src "ls180.v:5652.57-5652.78" - cell $eq $eq$ls180.v:5652$1045 + attribute \src "ls180.v:5704.57-5704.78" + cell $eq $eq$ls180.v:5704$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244259,10 +249864,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5652$1045_Y + connect \Y $eq$ls180.v:5704$1045_Y end - attribute \src "ls180.v:5653.57-5653.78" - cell $eq $eq$ls180.v:5653$1047 + attribute \src "ls180.v:5705.57-5705.78" + cell $eq $eq$ls180.v:5705$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244270,10 +249875,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5653$1047_Y + connect \Y $eq$ls180.v:5705$1047_Y end - attribute \src "ls180.v:5657.27-5657.59" - cell $eq $eq$ls180.v:5657$1050 + attribute \src "ls180.v:5709.27-5709.59" + cell $eq $eq$ls180.v:5709$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 23 parameter \B_SIGNED 0 @@ -244281,10 +249886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:7] connect \B 1'0 - connect \Y $eq$ls180.v:5657$1050_Y + connect \Y $eq$ls180.v:5709$1050_Y end - attribute \src "ls180.v:5658.27-5658.68" - cell $eq $eq$ls180.v:5658$1051 + attribute \src "ls180.v:5710.27-5710.68" + cell $eq $eq$ls180.v:5710$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 27 parameter \B_SIGNED 0 @@ -244292,10 +249897,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:3] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5658$1051_Y + connect \Y $eq$ls180.v:5710$1051_Y end - attribute \src "ls180.v:5659.27-5659.66" - cell $eq $eq$ls180.v:5659$1052 + attribute \src "ls180.v:5711.27-5711.66" + cell $eq $eq$ls180.v:5711$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -244303,10 +249908,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:10] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5659$1052_Y + connect \Y $eq$ls180.v:5711$1052_Y end - attribute \src "ls180.v:5660.27-5660.61" - cell $eq $eq$ls180.v:5660$1053 + attribute \src "ls180.v:5712.27-5712.61" + cell $eq $eq$ls180.v:5712$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -244314,10 +249919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:23] connect \B 7'1001000 - connect \Y $eq$ls180.v:5660$1053_Y + connect \Y $eq$ls180.v:5712$1053_Y end - attribute \src "ls180.v:5661.27-5661.65" - cell $eq $eq$ls180.v:5661$1054 + attribute \src "ls180.v:5713.27-5713.65" + cell $eq $eq$ls180.v:5713$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -244325,10 +249930,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:14] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5661$1054_Y + connect \Y $eq$ls180.v:5713$1054_Y end - attribute \src "ls180.v:5717.24-5717.45" - cell $eq $eq$ls180.v:5717$1081 + attribute \src "ls180.v:5769.24-5769.45" + cell $eq $eq$ls180.v:5769$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -244336,10 +249941,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:5717$1081_Y + connect \Y $eq$ls180.v:5769$1081_Y end - attribute \src "ls180.v:5718.32-5718.77" - cell $eq $eq$ls180.v:5718$1082 + attribute \src "ls180.v:5770.32-5770.77" + cell $eq $eq$ls180.v:5770$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -244347,10 +249952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [13:9] connect \B 1'0 - connect \Y $eq$ls180.v:5718$1082_Y + connect \Y $eq$ls180.v:5770$1082_Y end - attribute \src "ls180.v:5720.97-5720.141" - cell $eq $eq$ls180.v:5720$1084 + attribute \src "ls180.v:5772.97-5772.141" + cell $eq $eq$ls180.v:5772$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244358,10 +249963,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5720$1084_Y + connect \Y $eq$ls180.v:5772$1084_Y end - attribute \src "ls180.v:5721.100-5721.144" - cell $eq $eq$ls180.v:5721$1088 + attribute \src "ls180.v:5773.100-5773.144" + cell $eq $eq$ls180.v:5773$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244369,10 +249974,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5721$1088_Y + connect \Y $eq$ls180.v:5773$1088_Y end - attribute \src "ls180.v:5723.99-5723.143" - cell $eq $eq$ls180.v:5723$1091 + attribute \src "ls180.v:5775.99-5775.143" + cell $eq $eq$ls180.v:5775$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244380,10 +249985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5723$1091_Y + connect \Y $eq$ls180.v:5775$1091_Y end - attribute \src "ls180.v:5724.102-5724.146" - cell $eq $eq$ls180.v:5724$1095 + attribute \src "ls180.v:5776.102-5776.146" + cell $eq $eq$ls180.v:5776$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244391,10 +249996,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5724$1095_Y + connect \Y $eq$ls180.v:5776$1095_Y end - attribute \src "ls180.v:5726.99-5726.143" - cell $eq $eq$ls180.v:5726$1098 + attribute \src "ls180.v:5778.99-5778.143" + cell $eq $eq$ls180.v:5778$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244402,10 +250007,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5726$1098_Y + connect \Y $eq$ls180.v:5778$1098_Y end - attribute \src "ls180.v:5727.102-5727.146" - cell $eq $eq$ls180.v:5727$1102 + attribute \src "ls180.v:5779.102-5779.146" + cell $eq $eq$ls180.v:5779$1102 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244413,10 +250018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5727$1102_Y + connect \Y $eq$ls180.v:5779$1102_Y end - attribute \src "ls180.v:5729.99-5729.143" - cell $eq $eq$ls180.v:5729$1105 + attribute \src "ls180.v:5781.99-5781.143" + cell $eq $eq$ls180.v:5781$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244424,10 +250029,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5729$1105_Y + connect \Y $eq$ls180.v:5781$1105_Y end - attribute \src "ls180.v:5730.102-5730.146" - cell $eq $eq$ls180.v:5730$1109 + attribute \src "ls180.v:5782.102-5782.146" + cell $eq $eq$ls180.v:5782$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244435,10 +250040,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5730$1109_Y + connect \Y $eq$ls180.v:5782$1109_Y end - attribute \src "ls180.v:5732.99-5732.143" - cell $eq $eq$ls180.v:5732$1112 + attribute \src "ls180.v:5784.99-5784.143" + cell $eq $eq$ls180.v:5784$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244446,10 +250051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5732$1112_Y + connect \Y $eq$ls180.v:5784$1112_Y end - attribute \src "ls180.v:5733.102-5733.146" - cell $eq $eq$ls180.v:5733$1116 + attribute \src "ls180.v:5785.102-5785.146" + cell $eq $eq$ls180.v:5785$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244457,10 +250062,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5733$1116_Y + connect \Y $eq$ls180.v:5785$1116_Y end - attribute \src "ls180.v:5735.102-5735.146" - cell $eq $eq$ls180.v:5735$1119 + attribute \src "ls180.v:5787.102-5787.146" + cell $eq $eq$ls180.v:5787$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244468,10 +250073,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5735$1119_Y + connect \Y $eq$ls180.v:5787$1119_Y end - attribute \src "ls180.v:5736.105-5736.149" - cell $eq $eq$ls180.v:5736$1123 + attribute \src "ls180.v:5788.105-5788.149" + cell $eq $eq$ls180.v:5788$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244479,10 +250084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5736$1123_Y + connect \Y $eq$ls180.v:5788$1123_Y end - attribute \src "ls180.v:5738.102-5738.146" - cell $eq $eq$ls180.v:5738$1126 + attribute \src "ls180.v:5790.102-5790.146" + cell $eq $eq$ls180.v:5790$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244490,10 +250095,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5738$1126_Y + connect \Y $eq$ls180.v:5790$1126_Y end - attribute \src "ls180.v:5739.105-5739.149" - cell $eq $eq$ls180.v:5739$1130 + attribute \src "ls180.v:5791.105-5791.149" + cell $eq $eq$ls180.v:5791$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244501,10 +250106,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5739$1130_Y + connect \Y $eq$ls180.v:5791$1130_Y end - attribute \src "ls180.v:5741.102-5741.146" - cell $eq $eq$ls180.v:5741$1133 + attribute \src "ls180.v:5793.102-5793.146" + cell $eq $eq$ls180.v:5793$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244512,10 +250117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5741$1133_Y + connect \Y $eq$ls180.v:5793$1133_Y end - attribute \src "ls180.v:5742.105-5742.149" - cell $eq $eq$ls180.v:5742$1137 + attribute \src "ls180.v:5794.105-5794.149" + cell $eq $eq$ls180.v:5794$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244523,10 +250128,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5742$1137_Y + connect \Y $eq$ls180.v:5794$1137_Y end - attribute \src "ls180.v:5744.102-5744.146" - cell $eq $eq$ls180.v:5744$1140 + attribute \src "ls180.v:5796.102-5796.146" + cell $eq $eq$ls180.v:5796$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244534,10 +250139,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5744$1140_Y + connect \Y $eq$ls180.v:5796$1140_Y end - attribute \src "ls180.v:5745.105-5745.149" - cell $eq $eq$ls180.v:5745$1144 + attribute \src "ls180.v:5797.105-5797.149" + cell $eq $eq$ls180.v:5797$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -244545,10 +250150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5745$1144_Y + connect \Y $eq$ls180.v:5797$1144_Y end - attribute \src "ls180.v:5756.32-5756.77" - cell $eq $eq$ls180.v:5756$1146 + attribute \src "ls180.v:5808.32-5808.77" + cell $eq $eq$ls180.v:5808$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -244556,10 +250161,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [13:9] connect \B 3'110 - connect \Y $eq$ls180.v:5756$1146_Y + connect \Y $eq$ls180.v:5808$1146_Y end - attribute \src "ls180.v:5758.94-5758.138" - cell $eq $eq$ls180.v:5758$1148 + attribute \src "ls180.v:5810.94-5810.138" + cell $eq $eq$ls180.v:5810$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244567,10 +250172,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5758$1148_Y + connect \Y $eq$ls180.v:5810$1148_Y end - attribute \src "ls180.v:5759.97-5759.141" - cell $eq $eq$ls180.v:5759$1152 + attribute \src "ls180.v:5811.97-5811.141" + cell $eq $eq$ls180.v:5811$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244578,10 +250183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:5759$1152_Y + connect \Y $eq$ls180.v:5811$1152_Y end - attribute \src "ls180.v:5761.94-5761.138" - cell $eq $eq$ls180.v:5761$1155 + attribute \src "ls180.v:5813.94-5813.138" + cell $eq $eq$ls180.v:5813$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244589,10 +250194,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5761$1155_Y + connect \Y $eq$ls180.v:5813$1155_Y end - attribute \src "ls180.v:5762.97-5762.141" - cell $eq $eq$ls180.v:5762$1159 + attribute \src "ls180.v:5814.97-5814.141" + cell $eq $eq$ls180.v:5814$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244600,10 +250205,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:5762$1159_Y + connect \Y $eq$ls180.v:5814$1159_Y end - attribute \src "ls180.v:5764.94-5764.138" - cell $eq $eq$ls180.v:5764$1162 + attribute \src "ls180.v:5816.94-5816.138" + cell $eq $eq$ls180.v:5816$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244611,10 +250216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5764$1162_Y + connect \Y $eq$ls180.v:5816$1162_Y end - attribute \src "ls180.v:5765.97-5765.141" - cell $eq $eq$ls180.v:5765$1166 + attribute \src "ls180.v:5817.97-5817.141" + cell $eq $eq$ls180.v:5817$1166 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244622,10 +250227,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:5765$1166_Y + connect \Y $eq$ls180.v:5817$1166_Y end - attribute \src "ls180.v:5767.94-5767.138" - cell $eq $eq$ls180.v:5767$1169 + attribute \src "ls180.v:5819.94-5819.138" + cell $eq $eq$ls180.v:5819$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244633,10 +250238,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5767$1169_Y + connect \Y $eq$ls180.v:5819$1169_Y end - attribute \src "ls180.v:5768.97-5768.141" - cell $eq $eq$ls180.v:5768$1173 + attribute \src "ls180.v:5820.97-5820.141" + cell $eq $eq$ls180.v:5820$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244644,10 +250249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:5768$1173_Y + connect \Y $eq$ls180.v:5820$1173_Y end - attribute \src "ls180.v:5770.95-5770.139" - cell $eq $eq$ls180.v:5770$1176 + attribute \src "ls180.v:5822.95-5822.139" + cell $eq $eq$ls180.v:5822$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244655,10 +250260,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5770$1176_Y + connect \Y $eq$ls180.v:5822$1176_Y end - attribute \src "ls180.v:5771.98-5771.142" - cell $eq $eq$ls180.v:5771$1180 + attribute \src "ls180.v:5823.98-5823.142" + cell $eq $eq$ls180.v:5823$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244666,10 +250271,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:5771$1180_Y + connect \Y $eq$ls180.v:5823$1180_Y end - attribute \src "ls180.v:5773.95-5773.139" - cell $eq $eq$ls180.v:5773$1183 + attribute \src "ls180.v:5825.95-5825.139" + cell $eq $eq$ls180.v:5825$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244677,10 +250282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5773$1183_Y + connect \Y $eq$ls180.v:5825$1183_Y end - attribute \src "ls180.v:5774.98-5774.142" - cell $eq $eq$ls180.v:5774$1187 + attribute \src "ls180.v:5826.98-5826.142" + cell $eq $eq$ls180.v:5826$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -244688,3310 +250293,3365 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:5774$1187_Y + connect \Y $eq$ls180.v:5826$1187_Y end - attribute \src "ls180.v:5782.32-5782.77" - cell $eq $eq$ls180.v:5782$1189 + attribute \src "ls180.v:5834.32-5834.78" + cell $eq $eq$ls180.v:5834$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:5782$1189_Y + connect \B 4'1011 + connect \Y $eq$ls180.v:5834$1189_Y + end + attribute \src "ls180.v:5836.93-5836.135" + cell $eq $eq$ls180.v:5836$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5836$1191_Y + end + attribute \src "ls180.v:5837.96-5837.138" + cell $eq $eq$ls180.v:5837$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5837$1195_Y + end + attribute \src "ls180.v:5839.92-5839.134" + cell $eq $eq$ls180.v:5839$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5839$1198_Y + end + attribute \src "ls180.v:5840.95-5840.137" + cell $eq $eq$ls180.v:5840$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5840$1202_Y + end + attribute \src "ls180.v:5848.32-5848.77" + cell $eq $eq$ls180.v:5848$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5848$1204_Y end - attribute \src "ls180.v:5784.98-5784.142" - cell $eq $eq$ls180.v:5784$1191 + attribute \src "ls180.v:5850.98-5850.142" + cell $eq $eq$ls180.v:5850$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5784$1191_Y + connect \Y $eq$ls180.v:5850$1206_Y end - attribute \src "ls180.v:5785.101-5785.145" - cell $eq $eq$ls180.v:5785$1195 + attribute \src "ls180.v:5851.101-5851.145" + cell $eq $eq$ls180.v:5851$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5785$1195_Y + connect \Y $eq$ls180.v:5851$1210_Y end - attribute \src "ls180.v:5787.97-5787.141" - cell $eq $eq$ls180.v:5787$1198 + attribute \src "ls180.v:5853.97-5853.141" + cell $eq $eq$ls180.v:5853$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5787$1198_Y + connect \Y $eq$ls180.v:5853$1213_Y end - attribute \src "ls180.v:5788.100-5788.144" - cell $eq $eq$ls180.v:5788$1202 + attribute \src "ls180.v:5854.100-5854.144" + cell $eq $eq$ls180.v:5854$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5788$1202_Y + connect \Y $eq$ls180.v:5854$1217_Y end - attribute \src "ls180.v:5790.97-5790.141" - cell $eq $eq$ls180.v:5790$1205 + attribute \src "ls180.v:5856.97-5856.141" + cell $eq $eq$ls180.v:5856$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5790$1205_Y + connect \Y $eq$ls180.v:5856$1220_Y end - attribute \src "ls180.v:5791.100-5791.144" - cell $eq $eq$ls180.v:5791$1209 + attribute \src "ls180.v:5857.100-5857.144" + cell $eq $eq$ls180.v:5857$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5791$1209_Y + connect \Y $eq$ls180.v:5857$1224_Y end - attribute \src "ls180.v:5793.97-5793.141" - cell $eq $eq$ls180.v:5793$1212 + attribute \src "ls180.v:5859.97-5859.141" + cell $eq $eq$ls180.v:5859$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5793$1212_Y + connect \Y $eq$ls180.v:5859$1227_Y end - attribute \src "ls180.v:5794.100-5794.144" - cell $eq $eq$ls180.v:5794$1216 + attribute \src "ls180.v:5860.100-5860.144" + cell $eq $eq$ls180.v:5860$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5794$1216_Y + connect \Y $eq$ls180.v:5860$1231_Y end - attribute \src "ls180.v:5796.97-5796.141" - cell $eq $eq$ls180.v:5796$1219 + attribute \src "ls180.v:5862.97-5862.141" + cell $eq $eq$ls180.v:5862$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5796$1219_Y + connect \Y $eq$ls180.v:5862$1234_Y end - attribute \src "ls180.v:5797.100-5797.144" - cell $eq $eq$ls180.v:5797$1223 + attribute \src "ls180.v:5863.100-5863.144" + cell $eq $eq$ls180.v:5863$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5797$1223_Y + connect \Y $eq$ls180.v:5863$1238_Y end - attribute \src "ls180.v:5799.98-5799.142" - cell $eq $eq$ls180.v:5799$1226 + attribute \src "ls180.v:5865.98-5865.142" + cell $eq $eq$ls180.v:5865$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5799$1226_Y + connect \Y $eq$ls180.v:5865$1241_Y end - attribute \src "ls180.v:5800.101-5800.145" - cell $eq $eq$ls180.v:5800$1230 + attribute \src "ls180.v:5866.101-5866.145" + cell $eq $eq$ls180.v:5866$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5800$1230_Y + connect \Y $eq$ls180.v:5866$1245_Y end - attribute \src "ls180.v:5802.98-5802.142" - cell $eq $eq$ls180.v:5802$1233 + attribute \src "ls180.v:5868.98-5868.142" + cell $eq $eq$ls180.v:5868$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5802$1233_Y + connect \Y $eq$ls180.v:5868$1248_Y end - attribute \src "ls180.v:5803.101-5803.145" - cell $eq $eq$ls180.v:5803$1237 + attribute \src "ls180.v:5869.101-5869.145" + cell $eq $eq$ls180.v:5869$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5803$1237_Y + connect \Y $eq$ls180.v:5869$1252_Y end - attribute \src "ls180.v:5805.98-5805.142" - cell $eq $eq$ls180.v:5805$1240 + attribute \src "ls180.v:5871.98-5871.142" + cell $eq $eq$ls180.v:5871$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5805$1240_Y + connect \Y $eq$ls180.v:5871$1255_Y end - attribute \src "ls180.v:5806.101-5806.145" - cell $eq $eq$ls180.v:5806$1244 + attribute \src "ls180.v:5872.101-5872.145" + cell $eq $eq$ls180.v:5872$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5806$1244_Y + connect \Y $eq$ls180.v:5872$1259_Y end - attribute \src "ls180.v:5808.98-5808.142" - cell $eq $eq$ls180.v:5808$1247 + attribute \src "ls180.v:5874.98-5874.142" + cell $eq $eq$ls180.v:5874$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5808$1247_Y + connect \Y $eq$ls180.v:5874$1262_Y end - attribute \src "ls180.v:5809.101-5809.145" - cell $eq $eq$ls180.v:5809$1251 + attribute \src "ls180.v:5875.101-5875.145" + cell $eq $eq$ls180.v:5875$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [3:0] + connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5809$1251_Y + connect \Y $eq$ls180.v:5875$1266_Y end - attribute \src "ls180.v:5819.32-5819.77" - cell $eq $eq$ls180.v:5819$1253 + attribute \src "ls180.v:5885.32-5885.78" + cell $eq $eq$ls180.v:5885$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5819$1253_Y + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:5885$1268_Y end - attribute \src "ls180.v:5821.98-5821.142" - cell $eq $eq$ls180.v:5821$1255 + attribute \src "ls180.v:5887.98-5887.142" + cell $eq $eq$ls180.v:5887$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5821$1255_Y + connect \Y $eq$ls180.v:5887$1270_Y end - attribute \src "ls180.v:5822.101-5822.145" - cell $eq $eq$ls180.v:5822$1259 + attribute \src "ls180.v:5888.101-5888.145" + cell $eq $eq$ls180.v:5888$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5822$1259_Y + connect \Y $eq$ls180.v:5888$1274_Y end - attribute \src "ls180.v:5824.97-5824.141" - cell $eq $eq$ls180.v:5824$1262 + attribute \src "ls180.v:5890.97-5890.141" + cell $eq $eq$ls180.v:5890$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5824$1262_Y + connect \Y $eq$ls180.v:5890$1277_Y end - attribute \src "ls180.v:5825.100-5825.144" - cell $eq $eq$ls180.v:5825$1266 + attribute \src "ls180.v:5891.100-5891.144" + cell $eq $eq$ls180.v:5891$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5825$1266_Y + connect \Y $eq$ls180.v:5891$1281_Y end - attribute \src "ls180.v:5827.97-5827.141" - cell $eq $eq$ls180.v:5827$1269 + attribute \src "ls180.v:5893.97-5893.141" + cell $eq $eq$ls180.v:5893$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5827$1269_Y + connect \Y $eq$ls180.v:5893$1284_Y end - attribute \src "ls180.v:5828.100-5828.144" - cell $eq $eq$ls180.v:5828$1273 + attribute \src "ls180.v:5894.100-5894.144" + cell $eq $eq$ls180.v:5894$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5828$1273_Y + connect \Y $eq$ls180.v:5894$1288_Y end - attribute \src "ls180.v:5830.97-5830.141" - cell $eq $eq$ls180.v:5830$1276 + attribute \src "ls180.v:5896.97-5896.141" + cell $eq $eq$ls180.v:5896$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5830$1276_Y + connect \Y $eq$ls180.v:5896$1291_Y end - attribute \src "ls180.v:5831.100-5831.144" - cell $eq $eq$ls180.v:5831$1280 + attribute \src "ls180.v:5897.100-5897.144" + cell $eq $eq$ls180.v:5897$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5831$1280_Y + connect \Y $eq$ls180.v:5897$1295_Y end - attribute \src "ls180.v:5833.97-5833.141" - cell $eq $eq$ls180.v:5833$1283 + attribute \src "ls180.v:5899.97-5899.141" + cell $eq $eq$ls180.v:5899$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5833$1283_Y + connect \Y $eq$ls180.v:5899$1298_Y end - attribute \src "ls180.v:5834.100-5834.144" - cell $eq $eq$ls180.v:5834$1287 + attribute \src "ls180.v:5900.100-5900.144" + cell $eq $eq$ls180.v:5900$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5834$1287_Y + connect \Y $eq$ls180.v:5900$1302_Y end - attribute \src "ls180.v:5836.98-5836.142" - cell $eq $eq$ls180.v:5836$1290 + attribute \src "ls180.v:5902.98-5902.142" + cell $eq $eq$ls180.v:5902$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5836$1290_Y + connect \Y $eq$ls180.v:5902$1305_Y end - attribute \src "ls180.v:5837.101-5837.145" - cell $eq $eq$ls180.v:5837$1294 + attribute \src "ls180.v:5903.101-5903.145" + cell $eq $eq$ls180.v:5903$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5837$1294_Y + connect \Y $eq$ls180.v:5903$1309_Y end - attribute \src "ls180.v:5839.98-5839.142" - cell $eq $eq$ls180.v:5839$1297 + attribute \src "ls180.v:5905.98-5905.142" + cell $eq $eq$ls180.v:5905$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5839$1297_Y + connect \Y $eq$ls180.v:5905$1312_Y end - attribute \src "ls180.v:5840.101-5840.145" - cell $eq $eq$ls180.v:5840$1301 + attribute \src "ls180.v:5906.101-5906.145" + cell $eq $eq$ls180.v:5906$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5840$1301_Y + connect \Y $eq$ls180.v:5906$1316_Y end - attribute \src "ls180.v:5842.98-5842.142" - cell $eq $eq$ls180.v:5842$1304 + attribute \src "ls180.v:5908.98-5908.142" + cell $eq $eq$ls180.v:5908$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5842$1304_Y + connect \Y $eq$ls180.v:5908$1319_Y end - attribute \src "ls180.v:5843.101-5843.145" - cell $eq $eq$ls180.v:5843$1308 + attribute \src "ls180.v:5909.101-5909.145" + cell $eq $eq$ls180.v:5909$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5843$1308_Y + connect \Y $eq$ls180.v:5909$1323_Y end - attribute \src "ls180.v:5845.98-5845.142" - cell $eq $eq$ls180.v:5845$1311 + attribute \src "ls180.v:5911.98-5911.142" + cell $eq $eq$ls180.v:5911$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5845$1311_Y + connect \Y $eq$ls180.v:5911$1326_Y end - attribute \src "ls180.v:5846.101-5846.145" - cell $eq $eq$ls180.v:5846$1315 + attribute \src "ls180.v:5912.101-5912.145" + cell $eq $eq$ls180.v:5912$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5846$1315_Y + connect \Y $eq$ls180.v:5912$1330_Y end - attribute \src "ls180.v:5856.32-5856.78" - cell $eq $eq$ls180.v:5856$1317 + attribute \src "ls180.v:5922.32-5922.78" + cell $eq $eq$ls180.v:5922$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:5856$1317_Y + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:5922$1332_Y end - attribute \src "ls180.v:5858.100-5858.144" - cell $eq $eq$ls180.v:5858$1319 + attribute \src "ls180.v:5924.100-5924.144" + cell $eq $eq$ls180.v:5924$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5858$1319_Y + connect \Y $eq$ls180.v:5924$1334_Y end - attribute \src "ls180.v:5859.103-5859.147" - cell $eq $eq$ls180.v:5859$1323 + attribute \src "ls180.v:5925.103-5925.147" + cell $eq $eq$ls180.v:5925$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:5859$1323_Y + connect \Y $eq$ls180.v:5925$1338_Y end - attribute \src "ls180.v:5861.100-5861.144" - cell $eq $eq$ls180.v:5861$1326 + attribute \src "ls180.v:5927.100-5927.144" + cell $eq $eq$ls180.v:5927$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5861$1326_Y + connect \Y $eq$ls180.v:5927$1341_Y end - attribute \src "ls180.v:5862.103-5862.147" - cell $eq $eq$ls180.v:5862$1330 + attribute \src "ls180.v:5928.103-5928.147" + cell $eq $eq$ls180.v:5928$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:5862$1330_Y + connect \Y $eq$ls180.v:5928$1345_Y end - attribute \src "ls180.v:5864.100-5864.144" - cell $eq $eq$ls180.v:5864$1333 + attribute \src "ls180.v:5930.100-5930.144" + cell $eq $eq$ls180.v:5930$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5864$1333_Y + connect \Y $eq$ls180.v:5930$1348_Y end - attribute \src "ls180.v:5865.103-5865.147" - cell $eq $eq$ls180.v:5865$1337 + attribute \src "ls180.v:5931.103-5931.147" + cell $eq $eq$ls180.v:5931$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:5865$1337_Y + connect \Y $eq$ls180.v:5931$1352_Y end - attribute \src "ls180.v:5867.100-5867.144" - cell $eq $eq$ls180.v:5867$1340 + attribute \src "ls180.v:5933.100-5933.144" + cell $eq $eq$ls180.v:5933$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5867$1340_Y + connect \Y $eq$ls180.v:5933$1355_Y end - attribute \src "ls180.v:5868.103-5868.147" - cell $eq $eq$ls180.v:5868$1344 + attribute \src "ls180.v:5934.103-5934.147" + cell $eq $eq$ls180.v:5934$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:5868$1344_Y + connect \Y $eq$ls180.v:5934$1359_Y end - attribute \src "ls180.v:5870.100-5870.144" - cell $eq $eq$ls180.v:5870$1347 + attribute \src "ls180.v:5936.100-5936.144" + cell $eq $eq$ls180.v:5936$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5870$1347_Y + connect \Y $eq$ls180.v:5936$1362_Y end - attribute \src "ls180.v:5871.103-5871.147" - cell $eq $eq$ls180.v:5871$1351 + attribute \src "ls180.v:5937.103-5937.147" + cell $eq $eq$ls180.v:5937$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:5871$1351_Y + connect \Y $eq$ls180.v:5937$1366_Y end - attribute \src "ls180.v:5873.100-5873.144" - cell $eq $eq$ls180.v:5873$1354 + attribute \src "ls180.v:5939.100-5939.144" + cell $eq $eq$ls180.v:5939$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5873$1354_Y + connect \Y $eq$ls180.v:5939$1369_Y end - attribute \src "ls180.v:5874.103-5874.147" - cell $eq $eq$ls180.v:5874$1358 + attribute \src "ls180.v:5940.103-5940.147" + cell $eq $eq$ls180.v:5940$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:5874$1358_Y + connect \Y $eq$ls180.v:5940$1373_Y end - attribute \src "ls180.v:5876.100-5876.144" - cell $eq $eq$ls180.v:5876$1361 + attribute \src "ls180.v:5942.100-5942.144" + cell $eq $eq$ls180.v:5942$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5876$1361_Y + connect \Y $eq$ls180.v:5942$1376_Y end - attribute \src "ls180.v:5877.103-5877.147" - cell $eq $eq$ls180.v:5877$1365 + attribute \src "ls180.v:5943.103-5943.147" + cell $eq $eq$ls180.v:5943$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:5877$1365_Y + connect \Y $eq$ls180.v:5943$1380_Y end - attribute \src "ls180.v:5879.100-5879.144" - cell $eq $eq$ls180.v:5879$1368 + attribute \src "ls180.v:5945.100-5945.144" + cell $eq $eq$ls180.v:5945$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5879$1368_Y + connect \Y $eq$ls180.v:5945$1383_Y end - attribute \src "ls180.v:5880.103-5880.147" - cell $eq $eq$ls180.v:5880$1372 + attribute \src "ls180.v:5946.103-5946.147" + cell $eq $eq$ls180.v:5946$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:5880$1372_Y + connect \Y $eq$ls180.v:5946$1387_Y end - attribute \src "ls180.v:5882.102-5882.146" - cell $eq $eq$ls180.v:5882$1375 + attribute \src "ls180.v:5948.102-5948.146" + cell $eq $eq$ls180.v:5948$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5882$1375_Y + connect \Y $eq$ls180.v:5948$1390_Y end - attribute \src "ls180.v:5883.105-5883.149" - cell $eq $eq$ls180.v:5883$1379 + attribute \src "ls180.v:5949.105-5949.149" + cell $eq $eq$ls180.v:5949$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5883$1379_Y + connect \Y $eq$ls180.v:5949$1394_Y end - attribute \src "ls180.v:5885.102-5885.146" - cell $eq $eq$ls180.v:5885$1382 + attribute \src "ls180.v:5951.102-5951.146" + cell $eq $eq$ls180.v:5951$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5885$1382_Y + connect \Y $eq$ls180.v:5951$1397_Y end - attribute \src "ls180.v:5886.105-5886.149" - cell $eq $eq$ls180.v:5886$1386 + attribute \src "ls180.v:5952.105-5952.149" + cell $eq $eq$ls180.v:5952$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5886$1386_Y + connect \Y $eq$ls180.v:5952$1401_Y end - attribute \src "ls180.v:5888.102-5888.147" - cell $eq $eq$ls180.v:5888$1389 + attribute \src "ls180.v:5954.102-5954.147" + cell $eq $eq$ls180.v:5954$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5888$1389_Y + connect \Y $eq$ls180.v:5954$1404_Y end - attribute \src "ls180.v:5889.105-5889.150" - cell $eq $eq$ls180.v:5889$1393 + attribute \src "ls180.v:5955.105-5955.150" + cell $eq $eq$ls180.v:5955$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5889$1393_Y + connect \Y $eq$ls180.v:5955$1408_Y end - attribute \src "ls180.v:5891.102-5891.147" - cell $eq $eq$ls180.v:5891$1396 + attribute \src "ls180.v:5957.102-5957.147" + cell $eq $eq$ls180.v:5957$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5891$1396_Y + connect \Y $eq$ls180.v:5957$1411_Y end - attribute \src "ls180.v:5892.105-5892.150" - cell $eq $eq$ls180.v:5892$1400 + attribute \src "ls180.v:5958.105-5958.150" + cell $eq $eq$ls180.v:5958$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5892$1400_Y + connect \Y $eq$ls180.v:5958$1415_Y end - attribute \src "ls180.v:5894.102-5894.147" - cell $eq $eq$ls180.v:5894$1403 + attribute \src "ls180.v:5960.102-5960.147" + cell $eq $eq$ls180.v:5960$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5894$1403_Y + connect \Y $eq$ls180.v:5960$1418_Y end - attribute \src "ls180.v:5895.105-5895.150" - cell $eq $eq$ls180.v:5895$1407 + attribute \src "ls180.v:5961.105-5961.150" + cell $eq $eq$ls180.v:5961$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5895$1407_Y + connect \Y $eq$ls180.v:5961$1422_Y end - attribute \src "ls180.v:5897.99-5897.144" - cell $eq $eq$ls180.v:5897$1410 + attribute \src "ls180.v:5963.99-5963.144" + cell $eq $eq$ls180.v:5963$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5897$1410_Y + connect \Y $eq$ls180.v:5963$1425_Y end - attribute \src "ls180.v:5898.102-5898.147" - cell $eq $eq$ls180.v:5898$1414 + attribute \src "ls180.v:5964.102-5964.147" + cell $eq $eq$ls180.v:5964$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5898$1414_Y + connect \Y $eq$ls180.v:5964$1429_Y end - attribute \src "ls180.v:5900.100-5900.145" - cell $eq $eq$ls180.v:5900$1417 + attribute \src "ls180.v:5966.100-5966.145" + cell $eq $eq$ls180.v:5966$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5900$1417_Y + connect \Y $eq$ls180.v:5966$1432_Y end - attribute \src "ls180.v:5901.103-5901.148" - cell $eq $eq$ls180.v:5901$1421 + attribute \src "ls180.v:5967.103-5967.148" + cell $eq $eq$ls180.v:5967$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5901$1421_Y + connect \Y $eq$ls180.v:5967$1436_Y end - attribute \src "ls180.v:5918.32-5918.78" - cell $eq $eq$ls180.v:5918$1423 + attribute \src "ls180.v:5984.32-5984.78" + cell $eq $eq$ls180.v:5984$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:5918$1423_Y + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:5984$1438_Y end - attribute \src "ls180.v:5920.104-5920.148" - cell $eq $eq$ls180.v:5920$1425 + attribute \src "ls180.v:5986.104-5986.148" + cell $eq $eq$ls180.v:5986$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5920$1425_Y + connect \Y $eq$ls180.v:5986$1440_Y end - attribute \src "ls180.v:5921.107-5921.151" - cell $eq $eq$ls180.v:5921$1429 + attribute \src "ls180.v:5987.107-5987.151" + cell $eq $eq$ls180.v:5987$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:5921$1429_Y + connect \Y $eq$ls180.v:5987$1444_Y end - attribute \src "ls180.v:5923.104-5923.148" - cell $eq $eq$ls180.v:5923$1432 + attribute \src "ls180.v:5989.104-5989.148" + cell $eq $eq$ls180.v:5989$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5923$1432_Y + connect \Y $eq$ls180.v:5989$1447_Y end - attribute \src "ls180.v:5924.107-5924.151" - cell $eq $eq$ls180.v:5924$1436 + attribute \src "ls180.v:5990.107-5990.151" + cell $eq $eq$ls180.v:5990$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:5924$1436_Y + connect \Y $eq$ls180.v:5990$1451_Y end - attribute \src "ls180.v:5926.104-5926.148" - cell $eq $eq$ls180.v:5926$1439 + attribute \src "ls180.v:5992.104-5992.148" + cell $eq $eq$ls180.v:5992$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5926$1439_Y + connect \Y $eq$ls180.v:5992$1454_Y end - attribute \src "ls180.v:5927.107-5927.151" - cell $eq $eq$ls180.v:5927$1443 + attribute \src "ls180.v:5993.107-5993.151" + cell $eq $eq$ls180.v:5993$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:5927$1443_Y + connect \Y $eq$ls180.v:5993$1458_Y end - attribute \src "ls180.v:5929.104-5929.148" - cell $eq $eq$ls180.v:5929$1446 + attribute \src "ls180.v:5995.104-5995.148" + cell $eq $eq$ls180.v:5995$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5929$1446_Y + connect \Y $eq$ls180.v:5995$1461_Y end - attribute \src "ls180.v:5930.107-5930.151" - cell $eq $eq$ls180.v:5930$1450 + attribute \src "ls180.v:5996.107-5996.151" + cell $eq $eq$ls180.v:5996$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:5930$1450_Y + connect \Y $eq$ls180.v:5996$1465_Y end - attribute \src "ls180.v:5932.103-5932.147" - cell $eq $eq$ls180.v:5932$1453 + attribute \src "ls180.v:5998.103-5998.147" + cell $eq $eq$ls180.v:5998$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5932$1453_Y + connect \Y $eq$ls180.v:5998$1468_Y end - attribute \src "ls180.v:5933.106-5933.150" - cell $eq $eq$ls180.v:5933$1457 + attribute \src "ls180.v:5999.106-5999.150" + cell $eq $eq$ls180.v:5999$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:5933$1457_Y + connect \Y $eq$ls180.v:5999$1472_Y end - attribute \src "ls180.v:5935.103-5935.147" - cell $eq $eq$ls180.v:5935$1460 + attribute \src "ls180.v:6001.103-6001.147" + cell $eq $eq$ls180.v:6001$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:5935$1460_Y + connect \Y $eq$ls180.v:6001$1475_Y end - attribute \src "ls180.v:5936.106-5936.150" - cell $eq $eq$ls180.v:5936$1464 + attribute \src "ls180.v:6002.106-6002.150" + cell $eq $eq$ls180.v:6002$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:5936$1464_Y + connect \Y $eq$ls180.v:6002$1479_Y end - attribute \src "ls180.v:5938.103-5938.147" - cell $eq $eq$ls180.v:5938$1467 + attribute \src "ls180.v:6004.103-6004.147" + cell $eq $eq$ls180.v:6004$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:5938$1467_Y + connect \Y $eq$ls180.v:6004$1482_Y end - attribute \src "ls180.v:5939.106-5939.150" - cell $eq $eq$ls180.v:5939$1471 + attribute \src "ls180.v:6005.106-6005.150" + cell $eq $eq$ls180.v:6005$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:5939$1471_Y + connect \Y $eq$ls180.v:6005$1486_Y end - attribute \src "ls180.v:5941.103-5941.147" - cell $eq $eq$ls180.v:5941$1474 + attribute \src "ls180.v:6007.103-6007.147" + cell $eq $eq$ls180.v:6007$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:5941$1474_Y + connect \Y $eq$ls180.v:6007$1489_Y end - attribute \src "ls180.v:5942.106-5942.150" - cell $eq $eq$ls180.v:5942$1478 + attribute \src "ls180.v:6008.106-6008.150" + cell $eq $eq$ls180.v:6008$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:5942$1478_Y + connect \Y $eq$ls180.v:6008$1493_Y end - attribute \src "ls180.v:5944.94-5944.138" - cell $eq $eq$ls180.v:5944$1481 + attribute \src "ls180.v:6010.94-6010.138" + cell $eq $eq$ls180.v:6010$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5944$1481_Y + connect \Y $eq$ls180.v:6010$1496_Y end - attribute \src "ls180.v:5945.97-5945.141" - cell $eq $eq$ls180.v:5945$1485 + attribute \src "ls180.v:6011.97-6011.141" + cell $eq $eq$ls180.v:6011$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:5945$1485_Y + connect \Y $eq$ls180.v:6011$1500_Y end - attribute \src "ls180.v:5947.105-5947.149" - cell $eq $eq$ls180.v:5947$1488 + attribute \src "ls180.v:6013.105-6013.149" + cell $eq $eq$ls180.v:6013$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5947$1488_Y + connect \Y $eq$ls180.v:6013$1503_Y end - attribute \src "ls180.v:5948.108-5948.152" - cell $eq $eq$ls180.v:5948$1492 + attribute \src "ls180.v:6014.108-6014.152" + cell $eq $eq$ls180.v:6014$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:5948$1492_Y + connect \Y $eq$ls180.v:6014$1507_Y end - attribute \src "ls180.v:5950.105-5950.150" - cell $eq $eq$ls180.v:5950$1495 + attribute \src "ls180.v:6016.105-6016.150" + cell $eq $eq$ls180.v:6016$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5950$1495_Y + connect \Y $eq$ls180.v:6016$1510_Y end - attribute \src "ls180.v:5951.108-5951.153" - cell $eq $eq$ls180.v:5951$1499 + attribute \src "ls180.v:6017.108-6017.153" + cell $eq $eq$ls180.v:6017$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:5951$1499_Y + connect \Y $eq$ls180.v:6017$1514_Y end - attribute \src "ls180.v:5953.105-5953.150" - cell $eq $eq$ls180.v:5953$1502 + attribute \src "ls180.v:6019.105-6019.150" + cell $eq $eq$ls180.v:6019$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5953$1502_Y + connect \Y $eq$ls180.v:6019$1517_Y end - attribute \src "ls180.v:5954.108-5954.153" - cell $eq $eq$ls180.v:5954$1506 + attribute \src "ls180.v:6020.108-6020.153" + cell $eq $eq$ls180.v:6020$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:5954$1506_Y + connect \Y $eq$ls180.v:6020$1521_Y end - attribute \src "ls180.v:5956.105-5956.150" - cell $eq $eq$ls180.v:5956$1509 + attribute \src "ls180.v:6022.105-6022.150" + cell $eq $eq$ls180.v:6022$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5956$1509_Y + connect \Y $eq$ls180.v:6022$1524_Y end - attribute \src "ls180.v:5957.108-5957.153" - cell $eq $eq$ls180.v:5957$1513 + attribute \src "ls180.v:6023.108-6023.153" + cell $eq $eq$ls180.v:6023$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:5957$1513_Y + connect \Y $eq$ls180.v:6023$1528_Y end - attribute \src "ls180.v:5959.105-5959.150" - cell $eq $eq$ls180.v:5959$1516 + attribute \src "ls180.v:6025.105-6025.150" + cell $eq $eq$ls180.v:6025$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5959$1516_Y + connect \Y $eq$ls180.v:6025$1531_Y end - attribute \src "ls180.v:5960.108-5960.153" - cell $eq $eq$ls180.v:5960$1520 + attribute \src "ls180.v:6026.108-6026.153" + cell $eq $eq$ls180.v:6026$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:5960$1520_Y + connect \Y $eq$ls180.v:6026$1535_Y end - attribute \src "ls180.v:5962.105-5962.150" - cell $eq $eq$ls180.v:5962$1523 + attribute \src "ls180.v:6028.105-6028.150" + cell $eq $eq$ls180.v:6028$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5962$1523_Y + connect \Y $eq$ls180.v:6028$1538_Y end - attribute \src "ls180.v:5963.108-5963.153" - cell $eq $eq$ls180.v:5963$1527 + attribute \src "ls180.v:6029.108-6029.153" + cell $eq $eq$ls180.v:6029$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:5963$1527_Y + connect \Y $eq$ls180.v:6029$1542_Y end - attribute \src "ls180.v:5965.104-5965.149" - cell $eq $eq$ls180.v:5965$1530 + attribute \src "ls180.v:6031.104-6031.149" + cell $eq $eq$ls180.v:6031$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:5965$1530_Y + connect \Y $eq$ls180.v:6031$1545_Y end - attribute \src "ls180.v:5966.107-5966.152" - cell $eq $eq$ls180.v:5966$1534 + attribute \src "ls180.v:6032.107-6032.152" + cell $eq $eq$ls180.v:6032$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:5966$1534_Y + connect \Y $eq$ls180.v:6032$1549_Y end - attribute \src "ls180.v:5968.104-5968.149" - cell $eq $eq$ls180.v:5968$1537 + attribute \src "ls180.v:6034.104-6034.149" + cell $eq $eq$ls180.v:6034$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:5968$1537_Y + connect \Y $eq$ls180.v:6034$1552_Y end - attribute \src "ls180.v:5969.107-5969.152" - cell $eq $eq$ls180.v:5969$1541 + attribute \src "ls180.v:6035.107-6035.152" + cell $eq $eq$ls180.v:6035$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:5969$1541_Y + connect \Y $eq$ls180.v:6035$1556_Y end - attribute \src "ls180.v:5971.104-5971.149" - cell $eq $eq$ls180.v:5971$1544 + attribute \src "ls180.v:6037.104-6037.149" + cell $eq $eq$ls180.v:6037$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:5971$1544_Y + connect \Y $eq$ls180.v:6037$1559_Y end - attribute \src "ls180.v:5972.107-5972.152" - cell $eq $eq$ls180.v:5972$1548 + attribute \src "ls180.v:6038.107-6038.152" + cell $eq $eq$ls180.v:6038$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:5972$1548_Y + connect \Y $eq$ls180.v:6038$1563_Y end - attribute \src "ls180.v:5974.104-5974.149" - cell $eq $eq$ls180.v:5974$1551 + attribute \src "ls180.v:6040.104-6040.149" + cell $eq $eq$ls180.v:6040$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:5974$1551_Y + connect \Y $eq$ls180.v:6040$1566_Y end - attribute \src "ls180.v:5975.107-5975.152" - cell $eq $eq$ls180.v:5975$1555 + attribute \src "ls180.v:6041.107-6041.152" + cell $eq $eq$ls180.v:6041$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:5975$1555_Y + connect \Y $eq$ls180.v:6041$1570_Y end - attribute \src "ls180.v:5977.104-5977.149" - cell $eq $eq$ls180.v:5977$1558 + attribute \src "ls180.v:6043.104-6043.149" + cell $eq $eq$ls180.v:6043$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:5977$1558_Y + connect \Y $eq$ls180.v:6043$1573_Y end - attribute \src "ls180.v:5978.107-5978.152" - cell $eq $eq$ls180.v:5978$1562 + attribute \src "ls180.v:6044.107-6044.152" + cell $eq $eq$ls180.v:6044$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:5978$1562_Y + connect \Y $eq$ls180.v:6044$1577_Y end - attribute \src "ls180.v:5980.104-5980.149" - cell $eq $eq$ls180.v:5980$1565 + attribute \src "ls180.v:6046.104-6046.149" + cell $eq $eq$ls180.v:6046$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:5980$1565_Y + connect \Y $eq$ls180.v:6046$1580_Y end - attribute \src "ls180.v:5981.107-5981.152" - cell $eq $eq$ls180.v:5981$1569 + attribute \src "ls180.v:6047.107-6047.152" + cell $eq $eq$ls180.v:6047$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:5981$1569_Y + connect \Y $eq$ls180.v:6047$1584_Y end - attribute \src "ls180.v:5983.104-5983.149" - cell $eq $eq$ls180.v:5983$1572 + attribute \src "ls180.v:6049.104-6049.149" + cell $eq $eq$ls180.v:6049$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:5983$1572_Y + connect \Y $eq$ls180.v:6049$1587_Y end - attribute \src "ls180.v:5984.107-5984.152" - cell $eq $eq$ls180.v:5984$1576 + attribute \src "ls180.v:6050.107-6050.152" + cell $eq $eq$ls180.v:6050$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:5984$1576_Y + connect \Y $eq$ls180.v:6050$1591_Y end - attribute \src "ls180.v:5986.104-5986.149" - cell $eq $eq$ls180.v:5986$1579 + attribute \src "ls180.v:6052.104-6052.149" + cell $eq $eq$ls180.v:6052$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:5986$1579_Y + connect \Y $eq$ls180.v:6052$1594_Y end - attribute \src "ls180.v:5987.107-5987.152" - cell $eq $eq$ls180.v:5987$1583 + attribute \src "ls180.v:6053.107-6053.152" + cell $eq $eq$ls180.v:6053$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:5987$1583_Y + connect \Y $eq$ls180.v:6053$1598_Y end - attribute \src "ls180.v:5989.104-5989.149" - cell $eq $eq$ls180.v:5989$1586 + attribute \src "ls180.v:6055.104-6055.149" + cell $eq $eq$ls180.v:6055$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:5989$1586_Y + connect \Y $eq$ls180.v:6055$1601_Y end - attribute \src "ls180.v:5990.107-5990.152" - cell $eq $eq$ls180.v:5990$1590 + attribute \src "ls180.v:6056.107-6056.152" + cell $eq $eq$ls180.v:6056$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:5990$1590_Y + connect \Y $eq$ls180.v:6056$1605_Y end - attribute \src "ls180.v:5992.104-5992.149" - cell $eq $eq$ls180.v:5992$1593 + attribute \src "ls180.v:6058.104-6058.149" + cell $eq $eq$ls180.v:6058$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:5992$1593_Y + connect \Y $eq$ls180.v:6058$1608_Y end - attribute \src "ls180.v:5993.107-5993.152" - cell $eq $eq$ls180.v:5993$1597 + attribute \src "ls180.v:6059.107-6059.152" + cell $eq $eq$ls180.v:6059$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:5993$1597_Y + connect \Y $eq$ls180.v:6059$1612_Y end - attribute \src "ls180.v:5995.100-5995.145" - cell $eq $eq$ls180.v:5995$1600 + attribute \src "ls180.v:6061.100-6061.145" + cell $eq $eq$ls180.v:6061$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:5995$1600_Y + connect \Y $eq$ls180.v:6061$1615_Y end - attribute \src "ls180.v:5996.103-5996.148" - cell $eq $eq$ls180.v:5996$1604 + attribute \src "ls180.v:6062.103-6062.148" + cell $eq $eq$ls180.v:6062$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:5996$1604_Y + connect \Y $eq$ls180.v:6062$1619_Y end - attribute \src "ls180.v:5998.101-5998.146" - cell $eq $eq$ls180.v:5998$1607 + attribute \src "ls180.v:6064.101-6064.146" + cell $eq $eq$ls180.v:6064$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:5998$1607_Y + connect \Y $eq$ls180.v:6064$1622_Y end - attribute \src "ls180.v:5999.104-5999.149" - cell $eq $eq$ls180.v:5999$1611 + attribute \src "ls180.v:6065.104-6065.149" + cell $eq $eq$ls180.v:6065$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:5999$1611_Y + connect \Y $eq$ls180.v:6065$1626_Y end - attribute \src "ls180.v:6001.104-6001.149" - cell $eq $eq$ls180.v:6001$1614 + attribute \src "ls180.v:6067.104-6067.149" + cell $eq $eq$ls180.v:6067$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6001$1614_Y + connect \Y $eq$ls180.v:6067$1629_Y end - attribute \src "ls180.v:6002.107-6002.152" - cell $eq $eq$ls180.v:6002$1618 + attribute \src "ls180.v:6068.107-6068.152" + cell $eq $eq$ls180.v:6068$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6002$1618_Y + connect \Y $eq$ls180.v:6068$1633_Y end - attribute \src "ls180.v:6004.104-6004.149" - cell $eq $eq$ls180.v:6004$1621 + attribute \src "ls180.v:6070.104-6070.149" + cell $eq $eq$ls180.v:6070$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6004$1621_Y + connect \Y $eq$ls180.v:6070$1636_Y end - attribute \src "ls180.v:6005.107-6005.152" - cell $eq $eq$ls180.v:6005$1625 + attribute \src "ls180.v:6071.107-6071.152" + cell $eq $eq$ls180.v:6071$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6005$1625_Y + connect \Y $eq$ls180.v:6071$1640_Y end - attribute \src "ls180.v:6007.103-6007.148" - cell $eq $eq$ls180.v:6007$1628 + attribute \src "ls180.v:6073.103-6073.148" + cell $eq $eq$ls180.v:6073$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6007$1628_Y + connect \Y $eq$ls180.v:6073$1643_Y end - attribute \src "ls180.v:6008.106-6008.151" - cell $eq $eq$ls180.v:6008$1632 + attribute \src "ls180.v:6074.106-6074.151" + cell $eq $eq$ls180.v:6074$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6008$1632_Y + connect \Y $eq$ls180.v:6074$1647_Y end - attribute \src "ls180.v:6010.103-6010.148" - cell $eq $eq$ls180.v:6010$1635 + attribute \src "ls180.v:6076.103-6076.148" + cell $eq $eq$ls180.v:6076$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6010$1635_Y + connect \Y $eq$ls180.v:6076$1650_Y end - attribute \src "ls180.v:6011.106-6011.151" - cell $eq $eq$ls180.v:6011$1639 + attribute \src "ls180.v:6077.106-6077.151" + cell $eq $eq$ls180.v:6077$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6011$1639_Y + connect \Y $eq$ls180.v:6077$1654_Y end - attribute \src "ls180.v:6013.103-6013.148" - cell $eq $eq$ls180.v:6013$1642 + attribute \src "ls180.v:6079.103-6079.148" + cell $eq $eq$ls180.v:6079$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6013$1642_Y + connect \Y $eq$ls180.v:6079$1657_Y end - attribute \src "ls180.v:6014.106-6014.151" - cell $eq $eq$ls180.v:6014$1646 + attribute \src "ls180.v:6080.106-6080.151" + cell $eq $eq$ls180.v:6080$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6014$1646_Y + connect \Y $eq$ls180.v:6080$1661_Y end - attribute \src "ls180.v:6016.103-6016.148" - cell $eq $eq$ls180.v:6016$1649 + attribute \src "ls180.v:6082.103-6082.148" + cell $eq $eq$ls180.v:6082$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6016$1649_Y + connect \Y $eq$ls180.v:6082$1664_Y end - attribute \src "ls180.v:6017.106-6017.151" - cell $eq $eq$ls180.v:6017$1653 + attribute \src "ls180.v:6083.106-6083.151" + cell $eq $eq$ls180.v:6083$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [5:0] + connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6017$1653_Y + connect \Y $eq$ls180.v:6083$1668_Y end - attribute \src "ls180.v:6053.32-6053.78" - cell $eq $eq$ls180.v:6053$1655 + attribute \src "ls180.v:6119.32-6119.78" + cell $eq $eq$ls180.v:6119$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:6053$1655_Y + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1111 + connect \Y $eq$ls180.v:6119$1670_Y end - attribute \src "ls180.v:6055.100-6055.144" - cell $eq $eq$ls180.v:6055$1657 + attribute \src "ls180.v:6121.100-6121.144" + cell $eq $eq$ls180.v:6121$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6055$1657_Y + connect \Y $eq$ls180.v:6121$1672_Y end - attribute \src "ls180.v:6056.103-6056.147" - cell $eq $eq$ls180.v:6056$1661 + attribute \src "ls180.v:6122.103-6122.147" + cell $eq $eq$ls180.v:6122$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6056$1661_Y + connect \Y $eq$ls180.v:6122$1676_Y end - attribute \src "ls180.v:6058.100-6058.144" - cell $eq $eq$ls180.v:6058$1664 + attribute \src "ls180.v:6124.100-6124.144" + cell $eq $eq$ls180.v:6124$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6058$1664_Y + connect \Y $eq$ls180.v:6124$1679_Y end - attribute \src "ls180.v:6059.103-6059.147" - cell $eq $eq$ls180.v:6059$1668 + attribute \src "ls180.v:6125.103-6125.147" + cell $eq $eq$ls180.v:6125$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6059$1668_Y + connect \Y $eq$ls180.v:6125$1683_Y end - attribute \src "ls180.v:6061.100-6061.144" - cell $eq $eq$ls180.v:6061$1671 + attribute \src "ls180.v:6127.100-6127.144" + cell $eq $eq$ls180.v:6127$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6061$1671_Y + connect \Y $eq$ls180.v:6127$1686_Y end - attribute \src "ls180.v:6062.103-6062.147" - cell $eq $eq$ls180.v:6062$1675 + attribute \src "ls180.v:6128.103-6128.147" + cell $eq $eq$ls180.v:6128$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6062$1675_Y + connect \Y $eq$ls180.v:6128$1690_Y end - attribute \src "ls180.v:6064.100-6064.144" - cell $eq $eq$ls180.v:6064$1678 + attribute \src "ls180.v:6130.100-6130.144" + cell $eq $eq$ls180.v:6130$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6064$1678_Y + connect \Y $eq$ls180.v:6130$1693_Y end - attribute \src "ls180.v:6065.103-6065.147" - cell $eq $eq$ls180.v:6065$1682 + attribute \src "ls180.v:6131.103-6131.147" + cell $eq $eq$ls180.v:6131$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6065$1682_Y + connect \Y $eq$ls180.v:6131$1697_Y end - attribute \src "ls180.v:6067.100-6067.144" - cell $eq $eq$ls180.v:6067$1685 + attribute \src "ls180.v:6133.100-6133.144" + cell $eq $eq$ls180.v:6133$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6067$1685_Y + connect \Y $eq$ls180.v:6133$1700_Y end - attribute \src "ls180.v:6068.103-6068.147" - cell $eq $eq$ls180.v:6068$1689 + attribute \src "ls180.v:6134.103-6134.147" + cell $eq $eq$ls180.v:6134$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6068$1689_Y + connect \Y $eq$ls180.v:6134$1704_Y end - attribute \src "ls180.v:6070.100-6070.144" - cell $eq $eq$ls180.v:6070$1692 + attribute \src "ls180.v:6136.100-6136.144" + cell $eq $eq$ls180.v:6136$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6070$1692_Y + connect \Y $eq$ls180.v:6136$1707_Y end - attribute \src "ls180.v:6071.103-6071.147" - cell $eq $eq$ls180.v:6071$1696 + attribute \src "ls180.v:6137.103-6137.147" + cell $eq $eq$ls180.v:6137$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6071$1696_Y + connect \Y $eq$ls180.v:6137$1711_Y end - attribute \src "ls180.v:6073.100-6073.144" - cell $eq $eq$ls180.v:6073$1699 + attribute \src "ls180.v:6139.100-6139.144" + cell $eq $eq$ls180.v:6139$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6073$1699_Y + connect \Y $eq$ls180.v:6139$1714_Y end - attribute \src "ls180.v:6074.103-6074.147" - cell $eq $eq$ls180.v:6074$1703 + attribute \src "ls180.v:6140.103-6140.147" + cell $eq $eq$ls180.v:6140$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6074$1703_Y + connect \Y $eq$ls180.v:6140$1718_Y end - attribute \src "ls180.v:6076.100-6076.144" - cell $eq $eq$ls180.v:6076$1706 + attribute \src "ls180.v:6142.100-6142.144" + cell $eq $eq$ls180.v:6142$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6076$1706_Y + connect \Y $eq$ls180.v:6142$1721_Y end - attribute \src "ls180.v:6077.103-6077.147" - cell $eq $eq$ls180.v:6077$1710 + attribute \src "ls180.v:6143.103-6143.147" + cell $eq $eq$ls180.v:6143$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6077$1710_Y + connect \Y $eq$ls180.v:6143$1725_Y end - attribute \src "ls180.v:6079.102-6079.146" - cell $eq $eq$ls180.v:6079$1713 + attribute \src "ls180.v:6145.102-6145.146" + cell $eq $eq$ls180.v:6145$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6079$1713_Y + connect \Y $eq$ls180.v:6145$1728_Y end - attribute \src "ls180.v:6080.105-6080.149" - cell $eq $eq$ls180.v:6080$1717 + attribute \src "ls180.v:6146.105-6146.149" + cell $eq $eq$ls180.v:6146$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6080$1717_Y + connect \Y $eq$ls180.v:6146$1732_Y end - attribute \src "ls180.v:6082.102-6082.146" - cell $eq $eq$ls180.v:6082$1720 + attribute \src "ls180.v:6148.102-6148.146" + cell $eq $eq$ls180.v:6148$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6082$1720_Y + connect \Y $eq$ls180.v:6148$1735_Y end - attribute \src "ls180.v:6083.105-6083.149" - cell $eq $eq$ls180.v:6083$1724 + attribute \src "ls180.v:6149.105-6149.149" + cell $eq $eq$ls180.v:6149$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6083$1724_Y + connect \Y $eq$ls180.v:6149$1739_Y end - attribute \src "ls180.v:6085.102-6085.147" - cell $eq $eq$ls180.v:6085$1727 + attribute \src "ls180.v:6151.102-6151.147" + cell $eq $eq$ls180.v:6151$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6085$1727_Y + connect \Y $eq$ls180.v:6151$1742_Y end - attribute \src "ls180.v:6086.105-6086.150" - cell $eq $eq$ls180.v:6086$1731 + attribute \src "ls180.v:6152.105-6152.150" + cell $eq $eq$ls180.v:6152$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6086$1731_Y + connect \Y $eq$ls180.v:6152$1746_Y end - attribute \src "ls180.v:6088.102-6088.147" - cell $eq $eq$ls180.v:6088$1734 + attribute \src "ls180.v:6154.102-6154.147" + cell $eq $eq$ls180.v:6154$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6088$1734_Y + connect \Y $eq$ls180.v:6154$1749_Y end - attribute \src "ls180.v:6089.105-6089.150" - cell $eq $eq$ls180.v:6089$1738 + attribute \src "ls180.v:6155.105-6155.150" + cell $eq $eq$ls180.v:6155$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6089$1738_Y + connect \Y $eq$ls180.v:6155$1753_Y end - attribute \src "ls180.v:6091.102-6091.147" - cell $eq $eq$ls180.v:6091$1741 + attribute \src "ls180.v:6157.102-6157.147" + cell $eq $eq$ls180.v:6157$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6091$1741_Y + connect \Y $eq$ls180.v:6157$1756_Y end - attribute \src "ls180.v:6092.105-6092.150" - cell $eq $eq$ls180.v:6092$1745 + attribute \src "ls180.v:6158.105-6158.150" + cell $eq $eq$ls180.v:6158$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6092$1745_Y + connect \Y $eq$ls180.v:6158$1760_Y end - attribute \src "ls180.v:6094.99-6094.144" - cell $eq $eq$ls180.v:6094$1748 + attribute \src "ls180.v:6160.99-6160.144" + cell $eq $eq$ls180.v:6160$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6094$1748_Y + connect \Y $eq$ls180.v:6160$1763_Y end - attribute \src "ls180.v:6095.102-6095.147" - cell $eq $eq$ls180.v:6095$1752 + attribute \src "ls180.v:6161.102-6161.147" + cell $eq $eq$ls180.v:6161$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6095$1752_Y + connect \Y $eq$ls180.v:6161$1767_Y end - attribute \src "ls180.v:6097.100-6097.145" - cell $eq $eq$ls180.v:6097$1755 + attribute \src "ls180.v:6163.100-6163.145" + cell $eq $eq$ls180.v:6163$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6097$1755_Y + connect \Y $eq$ls180.v:6163$1770_Y end - attribute \src "ls180.v:6098.103-6098.148" - cell $eq $eq$ls180.v:6098$1759 + attribute \src "ls180.v:6164.103-6164.148" + cell $eq $eq$ls180.v:6164$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6098$1759_Y + connect \Y $eq$ls180.v:6164$1774_Y end - attribute \src "ls180.v:6100.102-6100.147" - cell $eq $eq$ls180.v:6100$1762 + attribute \src "ls180.v:6166.102-6166.147" + cell $eq $eq$ls180.v:6166$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6100$1762_Y + connect \Y $eq$ls180.v:6166$1777_Y end - attribute \src "ls180.v:6101.105-6101.150" - cell $eq $eq$ls180.v:6101$1766 + attribute \src "ls180.v:6167.105-6167.150" + cell $eq $eq$ls180.v:6167$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6101$1766_Y + connect \Y $eq$ls180.v:6167$1781_Y end - attribute \src "ls180.v:6103.102-6103.147" - cell $eq $eq$ls180.v:6103$1769 + attribute \src "ls180.v:6169.102-6169.147" + cell $eq $eq$ls180.v:6169$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6103$1769_Y + connect \Y $eq$ls180.v:6169$1784_Y end - attribute \src "ls180.v:6104.105-6104.150" - cell $eq $eq$ls180.v:6104$1773 + attribute \src "ls180.v:6170.105-6170.150" + cell $eq $eq$ls180.v:6170$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6104$1773_Y + connect \Y $eq$ls180.v:6170$1788_Y end - attribute \src "ls180.v:6106.102-6106.147" - cell $eq $eq$ls180.v:6106$1776 + attribute \src "ls180.v:6172.102-6172.147" + cell $eq $eq$ls180.v:6172$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6106$1776_Y + connect \Y $eq$ls180.v:6172$1791_Y end - attribute \src "ls180.v:6107.105-6107.150" - cell $eq $eq$ls180.v:6107$1780 + attribute \src "ls180.v:6173.105-6173.150" + cell $eq $eq$ls180.v:6173$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6107$1780_Y + connect \Y $eq$ls180.v:6173$1795_Y end - attribute \src "ls180.v:6109.102-6109.147" - cell $eq $eq$ls180.v:6109$1783 + attribute \src "ls180.v:6175.102-6175.147" + cell $eq $eq$ls180.v:6175$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6109$1783_Y + connect \Y $eq$ls180.v:6175$1798_Y end - attribute \src "ls180.v:6110.105-6110.150" - cell $eq $eq$ls180.v:6110$1787 + attribute \src "ls180.v:6176.105-6176.150" + cell $eq $eq$ls180.v:6176$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [4:0] + connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6110$1787_Y + connect \Y $eq$ls180.v:6176$1802_Y end - attribute \src "ls180.v:6132.32-6132.78" - cell $eq $eq$ls180.v:6132$1789 + attribute \src "ls180.v:6198.32-6198.78" + cell $eq $eq$ls180.v:6198$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:6132$1789_Y + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:6198$1804_Y end - attribute \src "ls180.v:6134.102-6134.146" - cell $eq $eq$ls180.v:6134$1791 + attribute \src "ls180.v:6200.102-6200.146" + cell $eq $eq$ls180.v:6200$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6134$1791_Y + connect \Y $eq$ls180.v:6200$1806_Y end - attribute \src "ls180.v:6135.105-6135.149" - cell $eq $eq$ls180.v:6135$1795 + attribute \src "ls180.v:6201.105-6201.149" + cell $eq $eq$ls180.v:6201$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6135$1795_Y + connect \Y $eq$ls180.v:6201$1810_Y end - attribute \src "ls180.v:6137.107-6137.151" - cell $eq $eq$ls180.v:6137$1798 + attribute \src "ls180.v:6203.107-6203.151" + cell $eq $eq$ls180.v:6203$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6137$1798_Y + connect \Y $eq$ls180.v:6203$1813_Y end - attribute \src "ls180.v:6138.110-6138.154" - cell $eq $eq$ls180.v:6138$1802 + attribute \src "ls180.v:6204.110-6204.154" + cell $eq $eq$ls180.v:6204$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6138$1802_Y + connect \Y $eq$ls180.v:6204$1817_Y end - attribute \src "ls180.v:6140.107-6140.151" - cell $eq $eq$ls180.v:6140$1805 + attribute \src "ls180.v:6206.107-6206.151" + cell $eq $eq$ls180.v:6206$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6140$1805_Y + connect \Y $eq$ls180.v:6206$1820_Y end - attribute \src "ls180.v:6141.110-6141.154" - cell $eq $eq$ls180.v:6141$1809 + attribute \src "ls180.v:6207.110-6207.154" + cell $eq $eq$ls180.v:6207$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6141$1809_Y + connect \Y $eq$ls180.v:6207$1824_Y end - attribute \src "ls180.v:6143.100-6143.144" - cell $eq $eq$ls180.v:6143$1812 + attribute \src "ls180.v:6209.100-6209.144" + cell $eq $eq$ls180.v:6209$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6143$1812_Y + connect \Y $eq$ls180.v:6209$1827_Y end - attribute \src "ls180.v:6144.103-6144.147" - cell $eq $eq$ls180.v:6144$1816 + attribute \src "ls180.v:6210.103-6210.147" + cell $eq $eq$ls180.v:6210$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [1:0] + connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6144$1816_Y + connect \Y $eq$ls180.v:6210$1831_Y end - attribute \src "ls180.v:6149.32-6149.77" - cell $eq $eq$ls180.v:6149$1818 + attribute \src "ls180.v:6215.32-6215.77" + cell $eq $eq$ls180.v:6215$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] + connect \A \builder_interface9_bank_bus_adr [13:9] connect \B 2'11 - connect \Y $eq$ls180.v:6149$1818_Y + connect \Y $eq$ls180.v:6215$1833_Y end - attribute \src "ls180.v:6151.104-6151.148" - cell $eq $eq$ls180.v:6151$1820 + attribute \src "ls180.v:6217.104-6217.148" + cell $eq $eq$ls180.v:6217$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6151$1820_Y + connect \Y $eq$ls180.v:6217$1835_Y end - attribute \src "ls180.v:6152.107-6152.151" - cell $eq $eq$ls180.v:6152$1824 + attribute \src "ls180.v:6218.107-6218.151" + cell $eq $eq$ls180.v:6218$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6152$1824_Y + connect \Y $eq$ls180.v:6218$1839_Y end - attribute \src "ls180.v:6154.108-6154.152" - cell $eq $eq$ls180.v:6154$1827 + attribute \src "ls180.v:6220.108-6220.152" + cell $eq $eq$ls180.v:6220$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6154$1827_Y + connect \Y $eq$ls180.v:6220$1842_Y end - attribute \src "ls180.v:6155.111-6155.155" - cell $eq $eq$ls180.v:6155$1831 + attribute \src "ls180.v:6221.111-6221.155" + cell $eq $eq$ls180.v:6221$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6155$1831_Y + connect \Y $eq$ls180.v:6221$1846_Y end - attribute \src "ls180.v:6157.98-6157.142" - cell $eq $eq$ls180.v:6157$1834 + attribute \src "ls180.v:6223.98-6223.142" + cell $eq $eq$ls180.v:6223$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6157$1834_Y + connect \Y $eq$ls180.v:6223$1849_Y end - attribute \src "ls180.v:6158.101-6158.145" - cell $eq $eq$ls180.v:6158$1838 + attribute \src "ls180.v:6224.101-6224.145" + cell $eq $eq$ls180.v:6224$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6158$1838_Y + connect \Y $eq$ls180.v:6224$1853_Y end - attribute \src "ls180.v:6160.108-6160.152" - cell $eq $eq$ls180.v:6160$1841 + attribute \src "ls180.v:6226.108-6226.152" + cell $eq $eq$ls180.v:6226$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6160$1841_Y + connect \Y $eq$ls180.v:6226$1856_Y end - attribute \src "ls180.v:6161.111-6161.155" - cell $eq $eq$ls180.v:6161$1845 + attribute \src "ls180.v:6227.111-6227.155" + cell $eq $eq$ls180.v:6227$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6161$1845_Y + connect \Y $eq$ls180.v:6227$1860_Y end - attribute \src "ls180.v:6163.108-6163.152" - cell $eq $eq$ls180.v:6163$1848 + attribute \src "ls180.v:6229.108-6229.152" + cell $eq $eq$ls180.v:6229$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6163$1848_Y + connect \Y $eq$ls180.v:6229$1863_Y end - attribute \src "ls180.v:6164.111-6164.155" - cell $eq $eq$ls180.v:6164$1852 + attribute \src "ls180.v:6230.111-6230.155" + cell $eq $eq$ls180.v:6230$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6164$1852_Y + connect \Y $eq$ls180.v:6230$1867_Y end - attribute \src "ls180.v:6166.109-6166.153" - cell $eq $eq$ls180.v:6166$1855 + attribute \src "ls180.v:6232.109-6232.153" + cell $eq $eq$ls180.v:6232$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6166$1855_Y + connect \Y $eq$ls180.v:6232$1870_Y end - attribute \src "ls180.v:6167.112-6167.156" - cell $eq $eq$ls180.v:6167$1859 + attribute \src "ls180.v:6233.112-6233.156" + cell $eq $eq$ls180.v:6233$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6167$1859_Y + connect \Y $eq$ls180.v:6233$1874_Y end - attribute \src "ls180.v:6169.107-6169.151" - cell $eq $eq$ls180.v:6169$1862 + attribute \src "ls180.v:6235.107-6235.151" + cell $eq $eq$ls180.v:6235$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6169$1862_Y + connect \Y $eq$ls180.v:6235$1877_Y end - attribute \src "ls180.v:6170.110-6170.154" - cell $eq $eq$ls180.v:6170$1866 + attribute \src "ls180.v:6236.110-6236.154" + cell $eq $eq$ls180.v:6236$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6170$1866_Y + connect \Y $eq$ls180.v:6236$1881_Y end - attribute \src "ls180.v:6172.107-6172.151" - cell $eq $eq$ls180.v:6172$1869 + attribute \src "ls180.v:6238.107-6238.151" + cell $eq $eq$ls180.v:6238$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6172$1869_Y + connect \Y $eq$ls180.v:6238$1884_Y end - attribute \src "ls180.v:6173.110-6173.154" - cell $eq $eq$ls180.v:6173$1873 + attribute \src "ls180.v:6239.110-6239.154" + cell $eq $eq$ls180.v:6239$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6173$1873_Y + connect \Y $eq$ls180.v:6239$1888_Y end - attribute \src "ls180.v:6175.107-6175.151" - cell $eq $eq$ls180.v:6175$1876 + attribute \src "ls180.v:6241.107-6241.151" + cell $eq $eq$ls180.v:6241$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6175$1876_Y + connect \Y $eq$ls180.v:6241$1891_Y end - attribute \src "ls180.v:6176.110-6176.154" - cell $eq $eq$ls180.v:6176$1880 + attribute \src "ls180.v:6242.110-6242.154" + cell $eq $eq$ls180.v:6242$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6176$1880_Y + connect \Y $eq$ls180.v:6242$1895_Y end - attribute \src "ls180.v:6178.107-6178.151" - cell $eq $eq$ls180.v:6178$1883 + attribute \src "ls180.v:6244.107-6244.151" + cell $eq $eq$ls180.v:6244$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6178$1883_Y + connect \Y $eq$ls180.v:6244$1898_Y end - attribute \src "ls180.v:6179.110-6179.154" - cell $eq $eq$ls180.v:6179$1887 + attribute \src "ls180.v:6245.110-6245.154" + cell $eq $eq$ls180.v:6245$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [3:0] + connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6179$1887_Y + connect \Y $eq$ls180.v:6245$1902_Y end - attribute \src "ls180.v:6194.32-6194.77" - cell $eq $eq$ls180.v:6194$1889 + attribute \src "ls180.v:6260.33-6260.79" + cell $eq $eq$ls180.v:6260$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] + connect \A \builder_interface10_bank_bus_adr [13:9] connect \B 3'111 - connect \Y $eq$ls180.v:6194$1889_Y + connect \Y $eq$ls180.v:6260$1904_Y end - attribute \src "ls180.v:6196.99-6196.143" - cell $eq $eq$ls180.v:6196$1891 + attribute \src "ls180.v:6262.102-6262.147" + cell $eq $eq$ls180.v:6262$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6196$1891_Y + connect \Y $eq$ls180.v:6262$1906_Y end - attribute \src "ls180.v:6197.102-6197.146" - cell $eq $eq$ls180.v:6197$1895 + attribute \src "ls180.v:6263.105-6263.150" + cell $eq $eq$ls180.v:6263$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6197$1895_Y + connect \Y $eq$ls180.v:6263$1910_Y end - attribute \src "ls180.v:6199.99-6199.143" - cell $eq $eq$ls180.v:6199$1898 + attribute \src "ls180.v:6265.102-6265.147" + cell $eq $eq$ls180.v:6265$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6199$1898_Y + connect \Y $eq$ls180.v:6265$1913_Y end - attribute \src "ls180.v:6200.102-6200.146" - cell $eq $eq$ls180.v:6200$1902 + attribute \src "ls180.v:6266.105-6266.150" + cell $eq $eq$ls180.v:6266$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6200$1902_Y + connect \Y $eq$ls180.v:6266$1917_Y end - attribute \src "ls180.v:6202.97-6202.141" - cell $eq $eq$ls180.v:6202$1905 + attribute \src "ls180.v:6268.100-6268.145" + cell $eq $eq$ls180.v:6268$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6202$1905_Y + connect \Y $eq$ls180.v:6268$1920_Y end - attribute \src "ls180.v:6203.100-6203.144" - cell $eq $eq$ls180.v:6203$1909 + attribute \src "ls180.v:6269.103-6269.148" + cell $eq $eq$ls180.v:6269$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6203$1909_Y + connect \Y $eq$ls180.v:6269$1924_Y end - attribute \src "ls180.v:6205.96-6205.140" - cell $eq $eq$ls180.v:6205$1912 + attribute \src "ls180.v:6271.99-6271.144" + cell $eq $eq$ls180.v:6271$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6205$1912_Y + connect \Y $eq$ls180.v:6271$1927_Y end - attribute \src "ls180.v:6206.99-6206.143" - cell $eq $eq$ls180.v:6206$1916 + attribute \src "ls180.v:6272.102-6272.147" + cell $eq $eq$ls180.v:6272$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6206$1916_Y + connect \Y $eq$ls180.v:6272$1931_Y end - attribute \src "ls180.v:6208.95-6208.139" - cell $eq $eq$ls180.v:6208$1919 + attribute \src "ls180.v:6274.98-6274.143" + cell $eq $eq$ls180.v:6274$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6208$1919_Y + connect \Y $eq$ls180.v:6274$1934_Y end - attribute \src "ls180.v:6209.98-6209.142" - cell $eq $eq$ls180.v:6209$1923 + attribute \src "ls180.v:6275.101-6275.146" + cell $eq $eq$ls180.v:6275$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6209$1923_Y + connect \Y $eq$ls180.v:6275$1938_Y end - attribute \src "ls180.v:6211.94-6211.138" - cell $eq $eq$ls180.v:6211$1926 + attribute \src "ls180.v:6277.97-6277.142" + cell $eq $eq$ls180.v:6277$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6211$1926_Y + connect \Y $eq$ls180.v:6277$1941_Y end - attribute \src "ls180.v:6212.97-6212.141" - cell $eq $eq$ls180.v:6212$1930 + attribute \src "ls180.v:6278.100-6278.145" + cell $eq $eq$ls180.v:6278$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6212$1930_Y + connect \Y $eq$ls180.v:6278$1945_Y end - attribute \src "ls180.v:6214.100-6214.144" - cell $eq $eq$ls180.v:6214$1933 + attribute \src "ls180.v:6280.103-6280.148" + cell $eq $eq$ls180.v:6280$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6214$1933_Y + connect \Y $eq$ls180.v:6280$1948_Y end - attribute \src "ls180.v:6215.103-6215.147" - cell $eq $eq$ls180.v:6215$1937 + attribute \src "ls180.v:6281.106-6281.151" + cell $eq $eq$ls180.v:6281$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [2:0] + connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6215$1937_Y + connect \Y $eq$ls180.v:6281$1952_Y end - attribute \src "ls180.v:6234.33-6234.80" - cell $eq $eq$ls180.v:6234$1940 + attribute \src "ls180.v:6300.33-6300.79" + cell $eq $eq$ls180.v:6300$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 4'1110 - connect \Y $eq$ls180.v:6234$1940_Y + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:6300$1955_Y end - attribute \src "ls180.v:6236.102-6236.147" - cell $eq $eq$ls180.v:6236$1942 + attribute \src "ls180.v:6302.102-6302.147" + cell $eq $eq$ls180.v:6302$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6236$1942_Y + connect \Y $eq$ls180.v:6302$1957_Y end - attribute \src "ls180.v:6237.105-6237.150" - cell $eq $eq$ls180.v:6237$1946 + attribute \src "ls180.v:6303.105-6303.150" + cell $eq $eq$ls180.v:6303$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6237$1946_Y + connect \Y $eq$ls180.v:6303$1961_Y end - attribute \src "ls180.v:6239.102-6239.147" - cell $eq $eq$ls180.v:6239$1949 + attribute \src "ls180.v:6305.102-6305.147" + cell $eq $eq$ls180.v:6305$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6239$1949_Y + connect \Y $eq$ls180.v:6305$1964_Y end - attribute \src "ls180.v:6240.105-6240.150" - cell $eq $eq$ls180.v:6240$1953 + attribute \src "ls180.v:6306.105-6306.150" + cell $eq $eq$ls180.v:6306$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6240$1953_Y + connect \Y $eq$ls180.v:6306$1968_Y end - attribute \src "ls180.v:6242.100-6242.145" - cell $eq $eq$ls180.v:6242$1956 + attribute \src "ls180.v:6308.100-6308.145" + cell $eq $eq$ls180.v:6308$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6242$1956_Y + connect \Y $eq$ls180.v:6308$1971_Y end - attribute \src "ls180.v:6243.103-6243.148" - cell $eq $eq$ls180.v:6243$1960 + attribute \src "ls180.v:6309.103-6309.148" + cell $eq $eq$ls180.v:6309$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6243$1960_Y + connect \Y $eq$ls180.v:6309$1975_Y end - attribute \src "ls180.v:6245.99-6245.144" - cell $eq $eq$ls180.v:6245$1963 + attribute \src "ls180.v:6311.99-6311.144" + cell $eq $eq$ls180.v:6311$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6245$1963_Y + connect \Y $eq$ls180.v:6311$1978_Y end - attribute \src "ls180.v:6246.102-6246.147" - cell $eq $eq$ls180.v:6246$1967 + attribute \src "ls180.v:6312.102-6312.147" + cell $eq $eq$ls180.v:6312$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6246$1967_Y + connect \Y $eq$ls180.v:6312$1982_Y end - attribute \src "ls180.v:6248.98-6248.143" - cell $eq $eq$ls180.v:6248$1970 + attribute \src "ls180.v:6314.98-6314.143" + cell $eq $eq$ls180.v:6314$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6248$1970_Y + connect \Y $eq$ls180.v:6314$1985_Y end - attribute \src "ls180.v:6249.101-6249.146" - cell $eq $eq$ls180.v:6249$1974 + attribute \src "ls180.v:6315.101-6315.146" + cell $eq $eq$ls180.v:6315$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6249$1974_Y + connect \Y $eq$ls180.v:6315$1989_Y end - attribute \src "ls180.v:6251.97-6251.142" - cell $eq $eq$ls180.v:6251$1977 + attribute \src "ls180.v:6317.97-6317.142" + cell $eq $eq$ls180.v:6317$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6251$1977_Y + connect \Y $eq$ls180.v:6317$1992_Y end - attribute \src "ls180.v:6252.100-6252.145" - cell $eq $eq$ls180.v:6252$1981 + attribute \src "ls180.v:6318.100-6318.145" + cell $eq $eq$ls180.v:6318$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6252$1981_Y + connect \Y $eq$ls180.v:6318$1996_Y end - attribute \src "ls180.v:6254.103-6254.148" - cell $eq $eq$ls180.v:6254$1984 + attribute \src "ls180.v:6320.103-6320.148" + cell $eq $eq$ls180.v:6320$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6254$1984_Y + connect \Y $eq$ls180.v:6320$1999_Y end - attribute \src "ls180.v:6255.106-6255.151" - cell $eq $eq$ls180.v:6255$1988 + attribute \src "ls180.v:6321.106-6321.151" + cell $eq $eq$ls180.v:6321$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6255$1988_Y + connect \Y $eq$ls180.v:6321$2003_Y end - attribute \src "ls180.v:6257.106-6257.151" - cell $eq $eq$ls180.v:6257$1991 + attribute \src "ls180.v:6323.106-6323.151" + cell $eq $eq$ls180.v:6323$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6257$1991_Y + connect \Y $eq$ls180.v:6323$2006_Y end - attribute \src "ls180.v:6258.109-6258.154" - cell $eq $eq$ls180.v:6258$1995 + attribute \src "ls180.v:6324.109-6324.154" + cell $eq $eq$ls180.v:6324$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6258$1995_Y + connect \Y $eq$ls180.v:6324$2010_Y end - attribute \src "ls180.v:6260.106-6260.151" - cell $eq $eq$ls180.v:6260$1998 + attribute \src "ls180.v:6326.106-6326.151" + cell $eq $eq$ls180.v:6326$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6260$1998_Y + connect \Y $eq$ls180.v:6326$2013_Y end - attribute \src "ls180.v:6261.109-6261.154" - cell $eq $eq$ls180.v:6261$2002 + attribute \src "ls180.v:6327.109-6327.154" + cell $eq $eq$ls180.v:6327$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [3:0] + connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6261$2002_Y + connect \Y $eq$ls180.v:6327$2017_Y end - attribute \src "ls180.v:6282.33-6282.79" - cell $eq $eq$ls180.v:6282$2005 + attribute \src "ls180.v:6348.33-6348.79" + cell $eq $eq$ls180.v:6348$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] + connect \A \builder_interface12_bank_bus_adr [13:9] connect \B 2'10 - connect \Y $eq$ls180.v:6282$2005_Y + connect \Y $eq$ls180.v:6348$2020_Y end - attribute \src "ls180.v:6284.99-6284.144" - cell $eq $eq$ls180.v:6284$2007 + attribute \src "ls180.v:6350.99-6350.144" + cell $eq $eq$ls180.v:6350$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6284$2007_Y + connect \Y $eq$ls180.v:6350$2022_Y end - attribute \src "ls180.v:6285.102-6285.147" - cell $eq $eq$ls180.v:6285$2011 + attribute \src "ls180.v:6351.102-6351.147" + cell $eq $eq$ls180.v:6351$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6285$2011_Y + connect \Y $eq$ls180.v:6351$2026_Y end - attribute \src "ls180.v:6287.99-6287.144" - cell $eq $eq$ls180.v:6287$2014 + attribute \src "ls180.v:6353.99-6353.144" + cell $eq $eq$ls180.v:6353$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6287$2014_Y + connect \Y $eq$ls180.v:6353$2029_Y end - attribute \src "ls180.v:6288.102-6288.147" - cell $eq $eq$ls180.v:6288$2018 + attribute \src "ls180.v:6354.102-6354.147" + cell $eq $eq$ls180.v:6354$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6288$2018_Y + connect \Y $eq$ls180.v:6354$2033_Y end - attribute \src "ls180.v:6290.99-6290.144" - cell $eq $eq$ls180.v:6290$2021 + attribute \src "ls180.v:6356.99-6356.144" + cell $eq $eq$ls180.v:6356$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6290$2021_Y + connect \Y $eq$ls180.v:6356$2036_Y end - attribute \src "ls180.v:6291.102-6291.147" - cell $eq $eq$ls180.v:6291$2025 + attribute \src "ls180.v:6357.102-6357.147" + cell $eq $eq$ls180.v:6357$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6291$2025_Y + connect \Y $eq$ls180.v:6357$2040_Y end - attribute \src "ls180.v:6293.99-6293.144" - cell $eq $eq$ls180.v:6293$2028 + attribute \src "ls180.v:6359.99-6359.144" + cell $eq $eq$ls180.v:6359$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6293$2028_Y + connect \Y $eq$ls180.v:6359$2043_Y end - attribute \src "ls180.v:6294.102-6294.147" - cell $eq $eq$ls180.v:6294$2032 + attribute \src "ls180.v:6360.102-6360.147" + cell $eq $eq$ls180.v:6360$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6294$2032_Y + connect \Y $eq$ls180.v:6360$2047_Y end - attribute \src "ls180.v:6296.101-6296.146" - cell $eq $eq$ls180.v:6296$2035 + attribute \src "ls180.v:6362.101-6362.146" + cell $eq $eq$ls180.v:6362$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6296$2035_Y + connect \Y $eq$ls180.v:6362$2050_Y end - attribute \src "ls180.v:6297.104-6297.149" - cell $eq $eq$ls180.v:6297$2039 + attribute \src "ls180.v:6363.104-6363.149" + cell $eq $eq$ls180.v:6363$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6297$2039_Y + connect \Y $eq$ls180.v:6363$2054_Y end - attribute \src "ls180.v:6299.101-6299.146" - cell $eq $eq$ls180.v:6299$2042 + attribute \src "ls180.v:6365.101-6365.146" + cell $eq $eq$ls180.v:6365$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6299$2042_Y + connect \Y $eq$ls180.v:6365$2057_Y end - attribute \src "ls180.v:6300.104-6300.149" - cell $eq $eq$ls180.v:6300$2046 + attribute \src "ls180.v:6366.104-6366.149" + cell $eq $eq$ls180.v:6366$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6300$2046_Y + connect \Y $eq$ls180.v:6366$2061_Y end - attribute \src "ls180.v:6302.101-6302.146" - cell $eq $eq$ls180.v:6302$2049 + attribute \src "ls180.v:6368.101-6368.146" + cell $eq $eq$ls180.v:6368$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6302$2049_Y + connect \Y $eq$ls180.v:6368$2064_Y end - attribute \src "ls180.v:6303.104-6303.149" - cell $eq $eq$ls180.v:6303$2053 + attribute \src "ls180.v:6369.104-6369.149" + cell $eq $eq$ls180.v:6369$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6303$2053_Y + connect \Y $eq$ls180.v:6369$2068_Y end - attribute \src "ls180.v:6305.101-6305.146" - cell $eq $eq$ls180.v:6305$2056 + attribute \src "ls180.v:6371.101-6371.146" + cell $eq $eq$ls180.v:6371$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6305$2056_Y + connect \Y $eq$ls180.v:6371$2071_Y end - attribute \src "ls180.v:6306.104-6306.149" - cell $eq $eq$ls180.v:6306$2060 + attribute \src "ls180.v:6372.104-6372.149" + cell $eq $eq$ls180.v:6372$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6306$2060_Y + connect \Y $eq$ls180.v:6372$2075_Y end - attribute \src "ls180.v:6308.97-6308.142" - cell $eq $eq$ls180.v:6308$2063 + attribute \src "ls180.v:6374.97-6374.142" + cell $eq $eq$ls180.v:6374$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6308$2063_Y + connect \Y $eq$ls180.v:6374$2078_Y end - attribute \src "ls180.v:6309.100-6309.145" - cell $eq $eq$ls180.v:6309$2067 + attribute \src "ls180.v:6375.100-6375.145" + cell $eq $eq$ls180.v:6375$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6309$2067_Y + connect \Y $eq$ls180.v:6375$2082_Y end - attribute \src "ls180.v:6311.107-6311.152" - cell $eq $eq$ls180.v:6311$2070 + attribute \src "ls180.v:6377.107-6377.152" + cell $eq $eq$ls180.v:6377$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6311$2070_Y + connect \Y $eq$ls180.v:6377$2085_Y end - attribute \src "ls180.v:6312.110-6312.155" - cell $eq $eq$ls180.v:6312$2074 + attribute \src "ls180.v:6378.110-6378.155" + cell $eq $eq$ls180.v:6378$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6312$2074_Y + connect \Y $eq$ls180.v:6378$2089_Y end - attribute \src "ls180.v:6314.100-6314.146" - cell $eq $eq$ls180.v:6314$2077 + attribute \src "ls180.v:6380.100-6380.146" + cell $eq $eq$ls180.v:6380$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6314$2077_Y + connect \Y $eq$ls180.v:6380$2092_Y end - attribute \src "ls180.v:6315.103-6315.149" - cell $eq $eq$ls180.v:6315$2081 + attribute \src "ls180.v:6381.103-6381.149" + cell $eq $eq$ls180.v:6381$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6315$2081_Y + connect \Y $eq$ls180.v:6381$2096_Y end - attribute \src "ls180.v:6317.100-6317.146" - cell $eq $eq$ls180.v:6317$2084 + attribute \src "ls180.v:6383.100-6383.146" + cell $eq $eq$ls180.v:6383$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6317$2084_Y + connect \Y $eq$ls180.v:6383$2099_Y end - attribute \src "ls180.v:6318.103-6318.149" - cell $eq $eq$ls180.v:6318$2088 + attribute \src "ls180.v:6384.103-6384.149" + cell $eq $eq$ls180.v:6384$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6318$2088_Y + connect \Y $eq$ls180.v:6384$2103_Y end - attribute \src "ls180.v:6320.100-6320.146" - cell $eq $eq$ls180.v:6320$2091 + attribute \src "ls180.v:6386.100-6386.146" + cell $eq $eq$ls180.v:6386$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6320$2091_Y + connect \Y $eq$ls180.v:6386$2106_Y end - attribute \src "ls180.v:6321.103-6321.149" - cell $eq $eq$ls180.v:6321$2095 + attribute \src "ls180.v:6387.103-6387.149" + cell $eq $eq$ls180.v:6387$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6321$2095_Y + connect \Y $eq$ls180.v:6387$2110_Y end - attribute \src "ls180.v:6323.100-6323.146" - cell $eq $eq$ls180.v:6323$2098 + attribute \src "ls180.v:6389.100-6389.146" + cell $eq $eq$ls180.v:6389$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6323$2098_Y + connect \Y $eq$ls180.v:6389$2113_Y end - attribute \src "ls180.v:6324.103-6324.149" - cell $eq $eq$ls180.v:6324$2102 + attribute \src "ls180.v:6390.103-6390.149" + cell $eq $eq$ls180.v:6390$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6324$2102_Y + connect \Y $eq$ls180.v:6390$2117_Y end - attribute \src "ls180.v:6326.112-6326.158" - cell $eq $eq$ls180.v:6326$2105 + attribute \src "ls180.v:6392.112-6392.158" + cell $eq $eq$ls180.v:6392$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6326$2105_Y + connect \Y $eq$ls180.v:6392$2120_Y end - attribute \src "ls180.v:6327.115-6327.161" - cell $eq $eq$ls180.v:6327$2109 + attribute \src "ls180.v:6393.115-6393.161" + cell $eq $eq$ls180.v:6393$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6327$2109_Y + connect \Y $eq$ls180.v:6393$2124_Y end - attribute \src "ls180.v:6329.113-6329.159" - cell $eq $eq$ls180.v:6329$2112 + attribute \src "ls180.v:6395.113-6395.159" + cell $eq $eq$ls180.v:6395$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6329$2112_Y + connect \Y $eq$ls180.v:6395$2127_Y end - attribute \src "ls180.v:6330.116-6330.162" - cell $eq $eq$ls180.v:6330$2116 + attribute \src "ls180.v:6396.116-6396.162" + cell $eq $eq$ls180.v:6396$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6330$2116_Y + connect \Y $eq$ls180.v:6396$2131_Y end - attribute \src "ls180.v:6332.104-6332.150" - cell $eq $eq$ls180.v:6332$2119 + attribute \src "ls180.v:6398.104-6398.150" + cell $eq $eq$ls180.v:6398$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6332$2119_Y + connect \Y $eq$ls180.v:6398$2134_Y end - attribute \src "ls180.v:6333.107-6333.153" - cell $eq $eq$ls180.v:6333$2123 + attribute \src "ls180.v:6399.107-6399.153" + cell $eq $eq$ls180.v:6399$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [4:0] + connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6333$2123_Y + connect \Y $eq$ls180.v:6399$2138_Y end - attribute \src "ls180.v:6350.33-6350.79" - cell $eq $eq$ls180.v:6350$2125 + attribute \src "ls180.v:6416.33-6416.79" + cell $eq $eq$ls180.v:6416$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] + connect \A \builder_interface13_bank_bus_adr [13:9] connect \B 3'101 - connect \Y $eq$ls180.v:6350$2125_Y + connect \Y $eq$ls180.v:6416$2140_Y end - attribute \src "ls180.v:6352.90-6352.135" - cell $eq $eq$ls180.v:6352$2127 + attribute \src "ls180.v:6418.90-6418.135" + cell $eq $eq$ls180.v:6418$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6352$2127_Y + connect \Y $eq$ls180.v:6418$2142_Y end - attribute \src "ls180.v:6353.93-6353.138" - cell $eq $eq$ls180.v:6353$2131 + attribute \src "ls180.v:6419.93-6419.138" + cell $eq $eq$ls180.v:6419$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6353$2131_Y + connect \Y $eq$ls180.v:6419$2146_Y end - attribute \src "ls180.v:6355.100-6355.145" - cell $eq $eq$ls180.v:6355$2134 + attribute \src "ls180.v:6421.100-6421.145" + cell $eq $eq$ls180.v:6421$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6355$2134_Y + connect \Y $eq$ls180.v:6421$2149_Y end - attribute \src "ls180.v:6356.103-6356.148" - cell $eq $eq$ls180.v:6356$2138 + attribute \src "ls180.v:6422.103-6422.148" + cell $eq $eq$ls180.v:6422$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6356$2138_Y + connect \Y $eq$ls180.v:6422$2153_Y end - attribute \src "ls180.v:6358.101-6358.146" - cell $eq $eq$ls180.v:6358$2141 + attribute \src "ls180.v:6424.101-6424.146" + cell $eq $eq$ls180.v:6424$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6358$2141_Y + connect \Y $eq$ls180.v:6424$2156_Y end - attribute \src "ls180.v:6359.104-6359.149" - cell $eq $eq$ls180.v:6359$2145 + attribute \src "ls180.v:6425.104-6425.149" + cell $eq $eq$ls180.v:6425$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6359$2145_Y + connect \Y $eq$ls180.v:6425$2160_Y end - attribute \src "ls180.v:6361.105-6361.150" - cell $eq $eq$ls180.v:6361$2148 + attribute \src "ls180.v:6427.105-6427.150" + cell $eq $eq$ls180.v:6427$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6361$2148_Y + connect \Y $eq$ls180.v:6427$2163_Y end - attribute \src "ls180.v:6362.108-6362.153" - cell $eq $eq$ls180.v:6362$2152 + attribute \src "ls180.v:6428.108-6428.153" + cell $eq $eq$ls180.v:6428$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6362$2152_Y + connect \Y $eq$ls180.v:6428$2167_Y end - attribute \src "ls180.v:6364.106-6364.151" - cell $eq $eq$ls180.v:6364$2155 + attribute \src "ls180.v:6430.106-6430.151" + cell $eq $eq$ls180.v:6430$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6364$2155_Y + connect \Y $eq$ls180.v:6430$2170_Y end - attribute \src "ls180.v:6365.109-6365.154" - cell $eq $eq$ls180.v:6365$2159 + attribute \src "ls180.v:6431.109-6431.154" + cell $eq $eq$ls180.v:6431$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6365$2159_Y + connect \Y $eq$ls180.v:6431$2174_Y end - attribute \src "ls180.v:6367.104-6367.149" - cell $eq $eq$ls180.v:6367$2162 + attribute \src "ls180.v:6433.104-6433.149" + cell $eq $eq$ls180.v:6433$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6367$2162_Y + connect \Y $eq$ls180.v:6433$2177_Y end - attribute \src "ls180.v:6368.107-6368.152" - cell $eq $eq$ls180.v:6368$2166 + attribute \src "ls180.v:6434.107-6434.152" + cell $eq $eq$ls180.v:6434$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6368$2166_Y + connect \Y $eq$ls180.v:6434$2181_Y end - attribute \src "ls180.v:6370.101-6370.146" - cell $eq $eq$ls180.v:6370$2169 + attribute \src "ls180.v:6436.101-6436.146" + cell $eq $eq$ls180.v:6436$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6370$2169_Y + connect \Y $eq$ls180.v:6436$2184_Y end - attribute \src "ls180.v:6371.104-6371.149" - cell $eq $eq$ls180.v:6371$2173 + attribute \src "ls180.v:6437.104-6437.149" + cell $eq $eq$ls180.v:6437$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6371$2173_Y + connect \Y $eq$ls180.v:6437$2188_Y end - attribute \src "ls180.v:6373.100-6373.145" - cell $eq $eq$ls180.v:6373$2176 + attribute \src "ls180.v:6439.100-6439.145" + cell $eq $eq$ls180.v:6439$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6373$2176_Y + connect \Y $eq$ls180.v:6439$2191_Y end - attribute \src "ls180.v:6374.103-6374.148" - cell $eq $eq$ls180.v:6374$2180 + attribute \src "ls180.v:6440.103-6440.148" + cell $eq $eq$ls180.v:6440$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [2:0] + connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6374$2180_Y + connect \Y $eq$ls180.v:6440$2195_Y end - attribute \src "ls180.v:6384.33-6384.79" - cell $eq $eq$ls180.v:6384$2182 + attribute \src "ls180.v:6450.33-6450.79" + cell $eq $eq$ls180.v:6450$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] + connect \A \builder_interface14_bank_bus_adr [13:9] connect \B 3'100 - connect \Y $eq$ls180.v:6384$2182_Y + connect \Y $eq$ls180.v:6450$2197_Y end - attribute \src "ls180.v:6386.106-6386.151" - cell $eq $eq$ls180.v:6386$2184 + attribute \src "ls180.v:6452.106-6452.151" + cell $eq $eq$ls180.v:6452$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6386$2184_Y + connect \Y $eq$ls180.v:6452$2199_Y end - attribute \src "ls180.v:6387.109-6387.154" - cell $eq $eq$ls180.v:6387$2188 + attribute \src "ls180.v:6453.109-6453.154" + cell $eq $eq$ls180.v:6453$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6387$2188_Y + connect \Y $eq$ls180.v:6453$2203_Y end - attribute \src "ls180.v:6389.106-6389.151" - cell $eq $eq$ls180.v:6389$2191 + attribute \src "ls180.v:6455.106-6455.151" + cell $eq $eq$ls180.v:6455$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6389$2191_Y + connect \Y $eq$ls180.v:6455$2206_Y end - attribute \src "ls180.v:6390.109-6390.154" - cell $eq $eq$ls180.v:6390$2195 + attribute \src "ls180.v:6456.109-6456.154" + cell $eq $eq$ls180.v:6456$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6390$2195_Y + connect \Y $eq$ls180.v:6456$2210_Y end - attribute \src "ls180.v:6392.106-6392.151" - cell $eq $eq$ls180.v:6392$2198 + attribute \src "ls180.v:6458.106-6458.151" + cell $eq $eq$ls180.v:6458$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6392$2198_Y + connect \Y $eq$ls180.v:6458$2213_Y end - attribute \src "ls180.v:6393.109-6393.154" - cell $eq $eq$ls180.v:6393$2202 + attribute \src "ls180.v:6459.109-6459.154" + cell $eq $eq$ls180.v:6459$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6393$2202_Y + connect \Y $eq$ls180.v:6459$2217_Y end - attribute \src "ls180.v:6395.106-6395.151" - cell $eq $eq$ls180.v:6395$2205 + attribute \src "ls180.v:6461.106-6461.151" + cell $eq $eq$ls180.v:6461$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6395$2205_Y + connect \Y $eq$ls180.v:6461$2220_Y end - attribute \src "ls180.v:6396.109-6396.154" - cell $eq $eq$ls180.v:6396$2209 + attribute \src "ls180.v:6462.109-6462.154" + cell $eq $eq$ls180.v:6462$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [1:0] + connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6396$2209_Y + connect \Y $eq$ls180.v:6462$2224_Y end - attribute \src "ls180.v:6774.41-6774.81" - cell $eq $eq$ls180.v:6774$2245 + attribute \src "ls180.v:6843.41-6843.81" + cell $eq $eq$ls180.v:6843$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -247999,10 +253659,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:6774$2245_Y + connect \Y $eq$ls180.v:6843$2261_Y end - attribute \src "ls180.v:6774.144-6774.177" - cell $eq $eq$ls180.v:6774$2246 + attribute \src "ls180.v:6843.144-6843.177" + cell $eq $eq$ls180.v:6843$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248010,10 +253670,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6774$2246_Y + connect \Y $eq$ls180.v:6843$2262_Y end - attribute \src "ls180.v:6774.219-6774.252" - cell $eq $eq$ls180.v:6774$2249 + attribute \src "ls180.v:6843.219-6843.252" + cell $eq $eq$ls180.v:6843$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248021,10 +253681,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6774$2249_Y + connect \Y $eq$ls180.v:6843$2265_Y end - attribute \src "ls180.v:6774.294-6774.327" - cell $eq $eq$ls180.v:6774$2252 + attribute \src "ls180.v:6843.294-6843.327" + cell $eq $eq$ls180.v:6843$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248032,10 +253692,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6774$2252_Y + connect \Y $eq$ls180.v:6843$2268_Y end - attribute \src "ls180.v:6798.41-6798.81" - cell $eq $eq$ls180.v:6798$2261 + attribute \src "ls180.v:6867.41-6867.81" + cell $eq $eq$ls180.v:6867$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248043,10 +253703,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:6798$2261_Y + connect \Y $eq$ls180.v:6867$2277_Y end - attribute \src "ls180.v:6798.144-6798.177" - cell $eq $eq$ls180.v:6798$2262 + attribute \src "ls180.v:6867.144-6867.177" + cell $eq $eq$ls180.v:6867$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248054,10 +253714,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6798$2262_Y + connect \Y $eq$ls180.v:6867$2278_Y end - attribute \src "ls180.v:6798.219-6798.252" - cell $eq $eq$ls180.v:6798$2265 + attribute \src "ls180.v:6867.219-6867.252" + cell $eq $eq$ls180.v:6867$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248065,10 +253725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6798$2265_Y + connect \Y $eq$ls180.v:6867$2281_Y end - attribute \src "ls180.v:6798.294-6798.327" - cell $eq $eq$ls180.v:6798$2268 + attribute \src "ls180.v:6867.294-6867.327" + cell $eq $eq$ls180.v:6867$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248076,10 +253736,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6798$2268_Y + connect \Y $eq$ls180.v:6867$2284_Y end - attribute \src "ls180.v:6822.41-6822.81" - cell $eq $eq$ls180.v:6822$2277 + attribute \src "ls180.v:6891.41-6891.81" + cell $eq $eq$ls180.v:6891$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248087,10 +253747,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:6822$2277_Y + connect \Y $eq$ls180.v:6891$2293_Y end - attribute \src "ls180.v:6822.144-6822.177" - cell $eq $eq$ls180.v:6822$2278 + attribute \src "ls180.v:6891.144-6891.177" + cell $eq $eq$ls180.v:6891$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248098,10 +253758,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6822$2278_Y + connect \Y $eq$ls180.v:6891$2294_Y end - attribute \src "ls180.v:6822.219-6822.252" - cell $eq $eq$ls180.v:6822$2281 + attribute \src "ls180.v:6891.219-6891.252" + cell $eq $eq$ls180.v:6891$2297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248109,10 +253769,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6822$2281_Y + connect \Y $eq$ls180.v:6891$2297_Y end - attribute \src "ls180.v:6822.294-6822.327" - cell $eq $eq$ls180.v:6822$2284 + attribute \src "ls180.v:6891.294-6891.327" + cell $eq $eq$ls180.v:6891$2300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248120,10 +253780,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:6822$2284_Y + connect \Y $eq$ls180.v:6891$2300_Y end - attribute \src "ls180.v:6846.41-6846.81" - cell $eq $eq$ls180.v:6846$2293 + attribute \src "ls180.v:6915.41-6915.81" + cell $eq $eq$ls180.v:6915$2309 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248131,10 +253791,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:6846$2293_Y + connect \Y $eq$ls180.v:6915$2309_Y end - attribute \src "ls180.v:6846.144-6846.177" - cell $eq $eq$ls180.v:6846$2294 + attribute \src "ls180.v:6915.144-6915.177" + cell $eq $eq$ls180.v:6915$2310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248142,10 +253802,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:6846$2294_Y + connect \Y $eq$ls180.v:6915$2310_Y end - attribute \src "ls180.v:6846.219-6846.252" - cell $eq $eq$ls180.v:6846$2297 + attribute \src "ls180.v:6915.219-6915.252" + cell $eq $eq$ls180.v:6915$2313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248153,10 +253813,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:6846$2297_Y + connect \Y $eq$ls180.v:6915$2313_Y end - attribute \src "ls180.v:6846.294-6846.327" - cell $eq $eq$ls180.v:6846$2300 + attribute \src "ls180.v:6915.294-6915.327" + cell $eq $eq$ls180.v:6915$2316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248164,10 +253824,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:6846$2300_Y + connect \Y $eq$ls180.v:6915$2316_Y end - attribute \src "ls180.v:7445.8-7445.38" - cell $eq $eq$ls180.v:7445$2409 + attribute \src "ls180.v:7508.8-7508.38" + cell $eq $eq$ls180.v:7508$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248175,10 +253835,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7445$2409_Y + connect \Y $eq$ls180.v:7508$2419_Y end - attribute \src "ls180.v:7476.8-7476.42" - cell $eq $eq$ls180.v:7476$2417 + attribute \src "ls180.v:7539.8-7539.42" + cell $eq $eq$ls180.v:7539$2427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248186,10 +253846,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7476$2417_Y + connect \Y $eq$ls180.v:7539$2427_Y end - attribute \src "ls180.v:7496.38-7496.74" - cell $eq $eq$ls180.v:7496$2420 + attribute \src "ls180.v:7559.38-7559.74" + cell $eq $eq$ls180.v:7559$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248197,10 +253857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7496$2420_Y + connect \Y $eq$ls180.v:7559$2430_Y end - attribute \src "ls180.v:7503.7-7503.43" - cell $eq $eq$ls180.v:7503$2422 + attribute \src "ls180.v:7566.7-7566.43" + cell $eq $eq$ls180.v:7566$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248208,10 +253868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7503$2422_Y + connect \Y $eq$ls180.v:7566$2432_Y end - attribute \src "ls180.v:7510.7-7510.43" - cell $eq $eq$ls180.v:7510$2423 + attribute \src "ls180.v:7573.7-7573.43" + cell $eq $eq$ls180.v:7573$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248219,10 +253879,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7510$2423_Y + connect \Y $eq$ls180.v:7573$2433_Y end - attribute \src "ls180.v:7518.7-7518.43" - cell $eq $eq$ls180.v:7518$2424 + attribute \src "ls180.v:7581.7-7581.43" + cell $eq $eq$ls180.v:7581$2434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248230,10 +253890,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7518$2424_Y + connect \Y $eq$ls180.v:7581$2434_Y end - attribute \src "ls180.v:7570.9-7570.54" - cell $eq $eq$ls180.v:7570$2442 + attribute \src "ls180.v:7633.9-7633.54" + cell $eq $eq$ls180.v:7633$2452 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248241,10 +253901,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7570$2442_Y + connect \Y $eq$ls180.v:7633$2452_Y end - attribute \src "ls180.v:7616.9-7616.54" - cell $eq $eq$ls180.v:7616$2458 + attribute \src "ls180.v:7679.9-7679.54" + cell $eq $eq$ls180.v:7679$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248252,10 +253912,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7616$2458_Y + connect \Y $eq$ls180.v:7679$2468_Y end - attribute \src "ls180.v:7662.9-7662.54" - cell $eq $eq$ls180.v:7662$2474 + attribute \src "ls180.v:7725.9-7725.54" + cell $eq $eq$ls180.v:7725$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248263,10 +253923,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7662$2474_Y + connect \Y $eq$ls180.v:7725$2484_Y end - attribute \src "ls180.v:7708.9-7708.54" - cell $eq $eq$ls180.v:7708$2490 + attribute \src "ls180.v:7771.9-7771.54" + cell $eq $eq$ls180.v:7771$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248274,10 +253934,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7708$2490_Y + connect \Y $eq$ls180.v:7771$2500_Y end - attribute \src "ls180.v:7858.9-7858.41" - cell $eq $eq$ls180.v:7858$2502 + attribute \src "ls180.v:7921.9-7921.41" + cell $eq $eq$ls180.v:7921$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248285,10 +253945,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7858$2502_Y + connect \Y $eq$ls180.v:7921$2512_Y end - attribute \src "ls180.v:7873.9-7873.41" - cell $eq $eq$ls180.v:7873$2505 + attribute \src "ls180.v:7936.9-7936.41" + cell $eq $eq$ls180.v:7936$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248296,10 +253956,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7873$2505_Y + connect \Y $eq$ls180.v:7936$2515_Y end - attribute \src "ls180.v:7879.49-7879.82" - cell $eq $eq$ls180.v:7879$2506 + attribute \src "ls180.v:7942.49-7942.82" + cell $eq $eq$ls180.v:7942$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248307,10 +253967,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7879$2506_Y + connect \Y $eq$ls180.v:7942$2516_Y end - attribute \src "ls180.v:7879.131-7879.164" - cell $eq $eq$ls180.v:7879$2509 + attribute \src "ls180.v:7942.131-7942.164" + cell $eq $eq$ls180.v:7942$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248318,10 +253978,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7879$2509_Y + connect \Y $eq$ls180.v:7942$2519_Y end - attribute \src "ls180.v:7879.213-7879.246" - cell $eq $eq$ls180.v:7879$2512 + attribute \src "ls180.v:7942.213-7942.246" + cell $eq $eq$ls180.v:7942$2522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248329,10 +253989,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7879$2512_Y + connect \Y $eq$ls180.v:7942$2522_Y end - attribute \src "ls180.v:7879.295-7879.328" - cell $eq $eq$ls180.v:7879$2515 + attribute \src "ls180.v:7942.295-7942.328" + cell $eq $eq$ls180.v:7942$2525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248340,10 +254000,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7879$2515_Y + connect \Y $eq$ls180.v:7942$2525_Y end - attribute \src "ls180.v:7880.50-7880.83" - cell $eq $eq$ls180.v:7880$2518 + attribute \src "ls180.v:7943.50-7943.83" + cell $eq $eq$ls180.v:7943$2528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248351,10 +254011,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7880$2518_Y + connect \Y $eq$ls180.v:7943$2528_Y end - attribute \src "ls180.v:7880.132-7880.165" - cell $eq $eq$ls180.v:7880$2521 + attribute \src "ls180.v:7943.132-7943.165" + cell $eq $eq$ls180.v:7943$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248362,10 +254022,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7880$2521_Y + connect \Y $eq$ls180.v:7943$2531_Y end - attribute \src "ls180.v:7880.214-7880.247" - cell $eq $eq$ls180.v:7880$2524 + attribute \src "ls180.v:7943.214-7943.247" + cell $eq $eq$ls180.v:7943$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248373,10 +254033,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7880$2524_Y + connect \Y $eq$ls180.v:7943$2534_Y end - attribute \src "ls180.v:7880.296-7880.329" - cell $eq $eq$ls180.v:7880$2527 + attribute \src "ls180.v:7943.296-7943.329" + cell $eq $eq$ls180.v:7943$2537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248384,54 +254044,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7880$2527_Y + connect \Y $eq$ls180.v:7943$2537_Y end - attribute \src "ls180.v:7915.9-7915.33" - cell $eq $eq$ls180.v:7915$2539 + attribute \src "ls180.v:7978.9-7978.42" + cell $eq $eq$ls180.v:7978$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \main_tx_bitcount + connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:7915$2539_Y + connect \Y $eq$ls180.v:7978$2549_Y end - attribute \src "ls180.v:7918.10-7918.34" - cell $eq $eq$ls180.v:7918$2540 + attribute \src "ls180.v:7981.10-7981.43" + cell $eq $eq$ls180.v:7981$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \main_tx_bitcount + connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7918$2540_Y + connect \Y $eq$ls180.v:7981$2550_Y end - attribute \src "ls180.v:7944.9-7944.33" - cell $eq $eq$ls180.v:7944$2546 + attribute \src "ls180.v:8007.9-8007.42" + cell $eq $eq$ls180.v:8007$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_rx_bitcount + connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:7944$2546_Y + connect \Y $eq$ls180.v:8007$2556_Y end - attribute \src "ls180.v:7949.10-7949.34" - cell $eq $eq$ls180.v:7949$2547 + attribute \src "ls180.v:8012.10-8012.43" + cell $eq $eq$ls180.v:8012$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \main_rx_bitcount + connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:7949$2547_Y + connect \Y $eq$ls180.v:8012$2557_Y end - attribute \src "ls180.v:8121.9-8121.53" - cell $eq $eq$ls180.v:8121$2591 + attribute \src "ls180.v:8219.9-8219.53" + cell $eq $eq$ls180.v:8219$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248439,10 +254099,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8121$2591_Y + connect \Y $eq$ls180.v:8219$2606_Y end - attribute \src "ls180.v:8202.9-8202.54" - cell $eq $eq$ls180.v:8202$2603 + attribute \src "ls180.v:8300.9-8300.54" + cell $eq $eq$ls180.v:8300$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -248450,10 +254110,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8202$2603_Y + connect \Y $eq$ls180.v:8300$2618_Y end - attribute \src "ls180.v:8281.9-8281.55" - cell $eq $eq$ls180.v:8281$2615 + attribute \src "ls180.v:8379.9-8379.55" + cell $eq $eq$ls180.v:8379$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248461,10 +254121,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8281$2615_Y + connect \Y $eq$ls180.v:8379$2630_Y end - attribute \src "ls180.v:8504.9-8504.49" - cell $eq $eq$ls180.v:8504$2648 + attribute \src "ls180.v:8602.9-8602.49" + cell $eq $eq$ls180.v:8602$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -248472,32 +254132,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 2'11 - connect \Y $eq$ls180.v:8504$2648_Y + connect \Y $eq$ls180.v:8602$2663_Y end - attribute \src "ls180.v:8080.8-8080.54" - cell $ge $ge$ls180.v:8080$2583 + attribute \src "ls180.v:8178.8-8178.54" + cell $ge $ge$ls180.v:8178$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8080$2582_Y - connect \Y $ge$ls180.v:8080$2583_Y + connect \B $sub$ls180.v:8178$2597_Y + connect \Y $ge$ls180.v:8178$2598_Y end - attribute \src "ls180.v:8094.8-8094.54" - cell $ge $ge$ls180.v:8094$2587 + attribute \src "ls180.v:8192.8-8192.54" + cell $ge $ge$ls180.v:8192$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8094$2586_Y - connect \Y $ge$ls180.v:8094$2587_Y + connect \B $sub$ls180.v:8192$2601_Y + connect \Y $ge$ls180.v:8192$2602_Y end - attribute \src "ls180.v:5041.47-5041.83" - cell $gt $gt$ls180.v:5041$906 + attribute \src "ls180.v:5152.47-5152.83" + cell $gt $gt$ls180.v:5152$914 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248505,10 +254165,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5041$906_Y + connect \Y $gt$ls180.v:5152$914_Y end - attribute \src "ls180.v:5047.7-5047.43" - cell $lt $lt$ls180.v:5047$909 + attribute \src "ls180.v:5158.7-5158.43" + cell $lt $lt$ls180.v:5158$917 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248516,10 +254176,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5047$909_Y + connect \Y $lt$ls180.v:5158$917_Y end - attribute \src "ls180.v:8075.8-8075.43" - cell $lt $lt$ls180.v:8075$2581 + attribute \src "ls180.v:8173.8-8173.43" + cell $lt $lt$ls180.v:8173$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248527,10 +254187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8075$2581_Y + connect \Y $lt$ls180.v:8173$2596_Y end - attribute \src "ls180.v:8089.8-8089.43" - cell $lt $lt$ls180.v:8089$2585 + attribute \src "ls180.v:8187.8-8187.43" + cell $lt $lt$ls180.v:8187$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248538,10 +254198,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8089$2585_Y + connect \Y $lt$ls180.v:8187$2600_Y end - attribute \src "ls180.v:9989.33-9989.36" - cell $memrd $memrd$\mem$ls180.v:9989$2695 + attribute \src "ls180.v:10068.33-10068.36" + cell $memrd $memrd$\mem$ls180.v:10068$2705 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248550,11 +254210,11 @@ module \ls180 parameter \WIDTH 32 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:9989$2695_DATA + connect \DATA $memrd$\mem$ls180.v:10068$2705_DATA connect \EN 1'x end - attribute \src "ls180.v:10000.12-10000.19" - cell $memrd $memrd$\storage$ls180.v:10000$2700 + attribute \src "ls180.v:10079.12-10079.19" + cell $memrd $memrd$\storage$ls180.v:10079$2710 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248563,11 +254223,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10000$2700_DATA + connect \DATA $memrd$\storage$ls180.v:10079$2710_DATA connect \EN 1'x end - attribute \src "ls180.v:10007.68-10007.75" - cell $memrd $memrd$\storage$ls180.v:10007$2702 + attribute \src "ls180.v:10086.68-10086.75" + cell $memrd $memrd$\storage$ls180.v:10086$2712 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248576,11 +254236,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10007$2702_DATA + connect \DATA $memrd$\storage$ls180.v:10086$2712_DATA connect \EN 1'x end - attribute \src "ls180.v:10014.14-10014.23" - cell $memrd $memrd$\storage_1$ls180.v:10014$2707 + attribute \src "ls180.v:10093.14-10093.23" + cell $memrd $memrd$\storage_1$ls180.v:10093$2717 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248589,11 +254249,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10014$2707_DATA + connect \DATA $memrd$\storage_1$ls180.v:10093$2717_DATA connect \EN 1'x end - attribute \src "ls180.v:10021.68-10021.77" - cell $memrd $memrd$\storage_1$ls180.v:10021$2709 + attribute \src "ls180.v:10100.68-10100.77" + cell $memrd $memrd$\storage_1$ls180.v:10100$2719 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248602,11 +254262,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10021$2709_DATA + connect \DATA $memrd$\storage_1$ls180.v:10100$2719_DATA connect \EN 1'x end - attribute \src "ls180.v:10028.14-10028.23" - cell $memrd $memrd$\storage_2$ls180.v:10028$2714 + attribute \src "ls180.v:10107.14-10107.23" + cell $memrd $memrd$\storage_2$ls180.v:10107$2724 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248615,11 +254275,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10028$2714_DATA + connect \DATA $memrd$\storage_2$ls180.v:10107$2724_DATA connect \EN 1'x end - attribute \src "ls180.v:10035.68-10035.77" - cell $memrd $memrd$\storage_2$ls180.v:10035$2716 + attribute \src "ls180.v:10114.68-10114.77" + cell $memrd $memrd$\storage_2$ls180.v:10114$2726 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248628,11 +254288,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10035$2716_DATA + connect \DATA $memrd$\storage_2$ls180.v:10114$2726_DATA connect \EN 1'x end - attribute \src "ls180.v:10042.14-10042.23" - cell $memrd $memrd$\storage_3$ls180.v:10042$2721 + attribute \src "ls180.v:10121.14-10121.23" + cell $memrd $memrd$\storage_3$ls180.v:10121$2731 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248641,11 +254301,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10042$2721_DATA + connect \DATA $memrd$\storage_3$ls180.v:10121$2731_DATA connect \EN 1'x end - attribute \src "ls180.v:10049.68-10049.77" - cell $memrd $memrd$\storage_3$ls180.v:10049$2723 + attribute \src "ls180.v:10128.68-10128.77" + cell $memrd $memrd$\storage_3$ls180.v:10128$2733 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248654,11 +254314,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10049$2723_DATA + connect \DATA $memrd$\storage_3$ls180.v:10128$2733_DATA connect \EN 1'x end - attribute \src "ls180.v:10057.14-10057.23" - cell $memrd $memrd$\storage_4$ls180.v:10057$2728 + attribute \src "ls180.v:10136.14-10136.23" + cell $memrd $memrd$\storage_4$ls180.v:10136$2738 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248667,11 +254327,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10057$2728_DATA + connect \DATA $memrd$\storage_4$ls180.v:10136$2738_DATA connect \EN 1'x end - attribute \src "ls180.v:10062.15-10062.24" - cell $memrd $memrd$\storage_4$ls180.v:10062$2730 + attribute \src "ls180.v:10141.15-10141.24" + cell $memrd $memrd$\storage_4$ls180.v:10141$2740 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248680,11 +254340,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10062$2730_DATA + connect \DATA $memrd$\storage_4$ls180.v:10141$2740_DATA connect \EN 1'x end - attribute \src "ls180.v:10074.14-10074.23" - cell $memrd $memrd$\storage_5$ls180.v:10074$2735 + attribute \src "ls180.v:10153.14-10153.23" + cell $memrd $memrd$\storage_5$ls180.v:10153$2745 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248693,11 +254353,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10074$2735_DATA + connect \DATA $memrd$\storage_5$ls180.v:10153$2745_DATA connect \EN 1'x end - attribute \src "ls180.v:10079.15-10079.24" - cell $memrd $memrd$\storage_5$ls180.v:10079$2737 + attribute \src "ls180.v:10158.15-10158.24" + cell $memrd $memrd$\storage_5$ls180.v:10158$2747 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248706,11 +254366,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10079$2737_DATA + connect \DATA $memrd$\storage_5$ls180.v:10158$2747_DATA connect \EN 1'x end - attribute \src "ls180.v:10090.14-10090.23" - cell $memrd $memrd$\storage_6$ls180.v:10090$2742 + attribute \src "ls180.v:10169.14-10169.23" + cell $memrd $memrd$\storage_6$ls180.v:10169$2752 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248719,11 +254379,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10090$2742_DATA + connect \DATA $memrd$\storage_6$ls180.v:10169$2752_DATA connect \EN 1'x end - attribute \src "ls180.v:10097.45-10097.54" - cell $memrd $memrd$\storage_6$ls180.v:10097$2744 + attribute \src "ls180.v:10176.45-10176.54" + cell $memrd $memrd$\storage_6$ls180.v:10176$2754 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248732,11 +254392,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10097$2744_DATA + connect \DATA $memrd$\storage_6$ls180.v:10176$2754_DATA connect \EN 1'x end - attribute \src "ls180.v:10104.14-10104.23" - cell $memrd $memrd$\storage_7$ls180.v:10104$2749 + attribute \src "ls180.v:10183.14-10183.23" + cell $memrd $memrd$\storage_7$ls180.v:10183$2759 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248745,11 +254405,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10104$2749_DATA + connect \DATA $memrd$\storage_7$ls180.v:10183$2759_DATA connect \EN 1'x end - attribute \src "ls180.v:10111.45-10111.54" - cell $memrd $memrd$\storage_7$ls180.v:10111$2751 + attribute \src "ls180.v:10190.45-10190.54" + cell $memrd $memrd$\storage_7$ls180.v:10190$2761 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -248758,167 +254418,167 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10111$2751_DATA + connect \DATA $memrd$\storage_7$ls180.v:10190$2761_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2753 + cell $memwr $memwr$\mem$ls180.v:0$2763 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2753 + parameter \PRIORITY 2763 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9979$1_ADDR + connect \ADDR $memwr$\mem$ls180.v:10058$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9979$1_DATA - connect \EN $memwr$\mem$ls180.v:9979$1_EN + connect \DATA $memwr$\mem$ls180.v:10058$1_DATA + connect \EN $memwr$\mem$ls180.v:10058$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2754 + cell $memwr $memwr$\mem$ls180.v:0$2764 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2754 + parameter \PRIORITY 2764 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9981$2_ADDR + connect \ADDR $memwr$\mem$ls180.v:10060$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9981$2_DATA - connect \EN $memwr$\mem$ls180.v:9981$2_EN + connect \DATA $memwr$\mem$ls180.v:10060$2_DATA + connect \EN $memwr$\mem$ls180.v:10060$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2755 + cell $memwr $memwr$\mem$ls180.v:0$2765 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2755 + parameter \PRIORITY 2765 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9983$3_ADDR + connect \ADDR $memwr$\mem$ls180.v:10062$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9983$3_DATA - connect \EN $memwr$\mem$ls180.v:9983$3_EN + connect \DATA $memwr$\mem$ls180.v:10062$3_DATA + connect \EN $memwr$\mem$ls180.v:10062$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2756 + cell $memwr $memwr$\mem$ls180.v:0$2766 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 2756 + parameter \PRIORITY 2766 parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:9985$4_ADDR + connect \ADDR $memwr$\mem$ls180.v:10064$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:9985$4_DATA - connect \EN $memwr$\mem$ls180.v:9985$4_EN + connect \DATA $memwr$\mem$ls180.v:10064$4_DATA + connect \EN $memwr$\mem$ls180.v:10064$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2757 + cell $memwr $memwr$\storage$ls180.v:0$2767 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 2757 + parameter \PRIORITY 2767 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:9999$5_ADDR + connect \ADDR $memwr$\storage$ls180.v:10078$5_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:9999$5_DATA - connect \EN $memwr$\storage$ls180.v:9999$5_EN + connect \DATA $memwr$\storage$ls180.v:10078$5_DATA + connect \EN $memwr$\storage$ls180.v:10078$5_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2758 + cell $memwr $memwr$\storage_1$ls180.v:0$2768 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 2758 + parameter \PRIORITY 2768 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10013$6_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10092$6_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10013$6_DATA - connect \EN $memwr$\storage_1$ls180.v:10013$6_EN + connect \DATA $memwr$\storage_1$ls180.v:10092$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10092$6_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2759 + cell $memwr $memwr$\storage_2$ls180.v:0$2769 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 2759 + parameter \PRIORITY 2769 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10027$7_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10106$7_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10027$7_DATA - connect \EN $memwr$\storage_2$ls180.v:10027$7_EN + connect \DATA $memwr$\storage_2$ls180.v:10106$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10106$7_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2760 + cell $memwr $memwr$\storage_3$ls180.v:0$2770 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 2760 + parameter \PRIORITY 2770 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10041$8_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10120$8_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10041$8_DATA - connect \EN $memwr$\storage_3$ls180.v:10041$8_EN + connect \DATA $memwr$\storage_3$ls180.v:10120$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10120$8_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2761 + cell $memwr $memwr$\storage_4$ls180.v:0$2771 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 2761 + parameter \PRIORITY 2771 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10056$9_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10135$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10056$9_DATA - connect \EN $memwr$\storage_4$ls180.v:10056$9_EN + connect \DATA $memwr$\storage_4$ls180.v:10135$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10135$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2762 + cell $memwr $memwr$\storage_5$ls180.v:0$2772 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 2762 + parameter \PRIORITY 2772 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10073$10_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10152$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10073$10_DATA - connect \EN $memwr$\storage_5$ls180.v:10073$10_EN + connect \DATA $memwr$\storage_5$ls180.v:10152$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10152$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2763 + cell $memwr $memwr$\storage_6$ls180.v:0$2773 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 2763 + parameter \PRIORITY 2773 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10089$11_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10168$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10089$11_DATA - connect \EN $memwr$\storage_6$ls180.v:10089$11_EN + connect \DATA $memwr$\storage_6$ls180.v:10168$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10168$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2764 + cell $memwr $memwr$\storage_7$ls180.v:0$2774 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 2764 + parameter \PRIORITY 2774 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10103$12_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10182$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10103$12_DATA - connect \EN $memwr$\storage_7$ls180.v:10103$12_EN + connect \DATA $memwr$\storage_7$ls180.v:10182$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10182$12_EN end - attribute \src "ls180.v:2918.41-2918.71" - cell $ne $ne$ls180.v:2918$60 + attribute \src "ls180.v:2966.41-2966.71" + cell $ne $ne$ls180.v:2966$60 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -248926,10 +254586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:2918$60_Y + connect \Y $ne$ls180.v:2966$60_Y end - attribute \src "ls180.v:3079.70-3079.104" - cell $ne $ne$ls180.v:3079$74 + attribute \src "ls180.v:3127.70-3127.104" + cell $ne $ne$ls180.v:3127$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -248937,10 +254597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3079$74_Y + connect \Y $ne$ls180.v:3127$74_Y end - attribute \src "ls180.v:3140.8-3140.142" - cell $ne $ne$ls180.v:3140$93 + attribute \src "ls180.v:3188.8-3188.142" + cell $ne $ne$ls180.v:3188$93 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248948,10 +254608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3140$93_Y + connect \Y $ne$ls180.v:3188$93_Y end - attribute \src "ls180.v:3172.75-3172.133" - cell $ne $ne$ls180.v:3172$100 + attribute \src "ls180.v:3220.75-3220.133" + cell $ne $ne$ls180.v:3220$100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248959,10 +254619,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3172$100_Y + connect \Y $ne$ls180.v:3220$100_Y end - attribute \src "ls180.v:3173.75-3173.133" - cell $ne $ne$ls180.v:3173$101 + attribute \src "ls180.v:3221.75-3221.133" + cell $ne $ne$ls180.v:3221$101 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248970,10 +254630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3173$101_Y + connect \Y $ne$ls180.v:3221$101_Y end - attribute \src "ls180.v:3297.8-3297.142" - cell $ne $ne$ls180.v:3297$123 + attribute \src "ls180.v:3345.8-3345.142" + cell $ne $ne$ls180.v:3345$123 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -248981,10 +254641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3297$123_Y + connect \Y $ne$ls180.v:3345$123_Y end - attribute \src "ls180.v:3329.75-3329.133" - cell $ne $ne$ls180.v:3329$130 + attribute \src "ls180.v:3377.75-3377.133" + cell $ne $ne$ls180.v:3377$130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -248992,10 +254652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3329$130_Y + connect \Y $ne$ls180.v:3377$130_Y end - attribute \src "ls180.v:3330.75-3330.133" - cell $ne $ne$ls180.v:3330$131 + attribute \src "ls180.v:3378.75-3378.133" + cell $ne $ne$ls180.v:3378$131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249003,10 +254663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3330$131_Y + connect \Y $ne$ls180.v:3378$131_Y end - attribute \src "ls180.v:3454.8-3454.142" - cell $ne $ne$ls180.v:3454$153 + attribute \src "ls180.v:3502.8-3502.142" + cell $ne $ne$ls180.v:3502$153 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -249014,10 +254674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3454$153_Y + connect \Y $ne$ls180.v:3502$153_Y end - attribute \src "ls180.v:3486.75-3486.133" - cell $ne $ne$ls180.v:3486$160 + attribute \src "ls180.v:3534.75-3534.133" + cell $ne $ne$ls180.v:3534$160 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249025,10 +254685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3486$160_Y + connect \Y $ne$ls180.v:3534$160_Y end - attribute \src "ls180.v:3487.75-3487.133" - cell $ne $ne$ls180.v:3487$161 + attribute \src "ls180.v:3535.75-3535.133" + cell $ne $ne$ls180.v:3535$161 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249036,10 +254696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3487$161_Y + connect \Y $ne$ls180.v:3535$161_Y end - attribute \src "ls180.v:3611.8-3611.142" - cell $ne $ne$ls180.v:3611$183 + attribute \src "ls180.v:3659.8-3659.142" + cell $ne $ne$ls180.v:3659$183 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -249047,10 +254707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3611$183_Y + connect \Y $ne$ls180.v:3659$183_Y end - attribute \src "ls180.v:3643.75-3643.133" - cell $ne $ne$ls180.v:3643$190 + attribute \src "ls180.v:3691.75-3691.133" + cell $ne $ne$ls180.v:3691$190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249058,10 +254718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3643$190_Y + connect \Y $ne$ls180.v:3691$190_Y end - attribute \src "ls180.v:3644.75-3644.133" - cell $ne $ne$ls180.v:3644$191 + attribute \src "ls180.v:3692.75-3692.133" + cell $ne $ne$ls180.v:3692$191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249069,10 +254729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3644$191_Y + connect \Y $ne$ls180.v:3692$191_Y end - attribute \src "ls180.v:4136.47-4136.80" - cell $ne $ne$ls180.v:4136$589 + attribute \src "ls180.v:4184.47-4184.80" + cell $ne $ne$ls180.v:4184$589 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249080,10 +254740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4136$589_Y + connect \Y $ne$ls180.v:4184$589_Y end - attribute \src "ls180.v:4137.47-4137.79" - cell $ne $ne$ls180.v:4137$590 + attribute \src "ls180.v:4185.47-4185.79" + cell $ne $ne$ls180.v:4185$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249091,10 +254751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4137$590_Y + connect \Y $ne$ls180.v:4185$590_Y end - attribute \src "ls180.v:4166.47-4166.80" - cell $ne $ne$ls180.v:4166$600 + attribute \src "ls180.v:4214.47-4214.80" + cell $ne $ne$ls180.v:4214$600 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249102,10 +254762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4166$600_Y + connect \Y $ne$ls180.v:4214$600_Y end - attribute \src "ls180.v:4167.47-4167.79" - cell $ne $ne$ls180.v:4167$601 + attribute \src "ls180.v:4215.47-4215.79" + cell $ne $ne$ls180.v:4215$601 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -249113,10 +254773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4167$601_Y + connect \Y $ne$ls180.v:4215$601_Y end - attribute \src "ls180.v:4573.32-4573.89" - cell $ne $ne$ls180.v:4573$673 + attribute \src "ls180.v:4684.32-4684.89" + cell $ne $ne$ls180.v:4684$681 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -249124,10 +254784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4573$673_Y + connect \Y $ne$ls180.v:4684$681_Y end - attribute \src "ls180.v:5220.10-5220.56" - cell $ne $ne$ls180.v:5220$970 + attribute \src "ls180.v:5331.10-5331.56" + cell $ne $ne$ls180.v:5331$978 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -249135,10 +254795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5220$970_Y + connect \Y $ne$ls180.v:5331$978_Y end - attribute \src "ls180.v:5325.51-5325.87" - cell $ne $ne$ls180.v:5325$984 + attribute \src "ls180.v:5436.51-5436.87" + cell $ne $ne$ls180.v:5436$992 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -249146,10 +254806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5325$984_Y + connect \Y $ne$ls180.v:5436$992_Y end - attribute \src "ls180.v:5326.51-5326.86" - cell $ne $ne$ls180.v:5326$985 + attribute \src "ls180.v:5437.51-5437.86" + cell $ne $ne$ls180.v:5437$993 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -249157,10 +254817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5326$985_Y + connect \Y $ne$ls180.v:5437$993_Y end - attribute \src "ls180.v:5533.51-5533.87" - cell $ne $ne$ls180.v:5533$1015 + attribute \src "ls180.v:5644.51-5644.87" + cell $ne $ne$ls180.v:5644$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -249168,10 +254828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5533$1015_Y + connect \Y $ne$ls180.v:5644$1023_Y end - attribute \src "ls180.v:5534.51-5534.86" - cell $ne $ne$ls180.v:5534$1016 + attribute \src "ls180.v:5645.51-5645.86" + cell $ne $ne$ls180.v:5645$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -249179,10 +254839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5534$1016_Y + connect \Y $ne$ls180.v:5645$1024_Y end - attribute \src "ls180.v:5624.79-5624.119" - cell $ne $ne$ls180.v:5624$1027 + attribute \src "ls180.v:5676.79-5676.119" + cell $ne $ne$ls180.v:5676$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249190,10 +254850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5624$1027_Y + connect \Y $ne$ls180.v:5676$1027_Y end - attribute \src "ls180.v:7435.7-7435.52" - cell $ne $ne$ls180.v:7435$2404 + attribute \src "ls180.v:7498.7-7498.52" + cell $ne $ne$ls180.v:7498$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -249201,10 +254861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7435$2404_Y + connect \Y $ne$ls180.v:7498$2414_Y end - attribute \src "ls180.v:7485.9-7485.43" - cell $ne $ne$ls180.v:7485$2418 + attribute \src "ls180.v:7548.9-7548.43" + cell $ne $ne$ls180.v:7548$2428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -249212,10 +254872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7485$2418_Y + connect \Y $ne$ls180.v:7548$2428_Y end - attribute \src "ls180.v:7521.8-7521.44" - cell $ne $ne$ls180.v:7521$2425 + attribute \src "ls180.v:7584.8-7584.44" + cell $ne $ne$ls180.v:7584$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249223,10 +254883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7521$2425_Y + connect \Y $ne$ls180.v:7584$2435_Y end - attribute \src "ls180.v:8424.9-8424.47" - cell $ne $ne$ls180.v:8424$2635 + attribute \src "ls180.v:8522.9-8522.47" + cell $ne $ne$ls180.v:8522$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -249234,2690 +254894,2706 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8424$2635_Y + connect \Y $ne$ls180.v:8522$2650_Y end - attribute \src "ls180.v:2726.45-2726.80" - cell $not $not$ls180.v:2726$14 + attribute \src "ls180.v:2774.45-2774.80" + cell $not $not$ls180.v:2774$14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2726$14_Y + connect \Y $not$ls180.v:2774$14_Y end - attribute \src "ls180.v:2765.61-2765.94" - cell $not $not$ls180.v:2765$19 + attribute \src "ls180.v:2813.61-2813.94" + cell $not $not$ls180.v:2813$19 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2765$19_Y + connect \Y $not$ls180.v:2813$19_Y end - attribute \src "ls180.v:2766.61-2766.94" - cell $not $not$ls180.v:2766$20 + attribute \src "ls180.v:2814.61-2814.94" + cell $not $not$ls180.v:2814$20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2766$20_Y + connect \Y $not$ls180.v:2814$20_Y end - attribute \src "ls180.v:2786.45-2786.80" - cell $not $not$ls180.v:2786$25 + attribute \src "ls180.v:2834.45-2834.80" + cell $not $not$ls180.v:2834$25 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2786$25_Y + connect \Y $not$ls180.v:2834$25_Y end - attribute \src "ls180.v:2825.61-2825.94" - cell $not $not$ls180.v:2825$30 + attribute \src "ls180.v:2873.61-2873.94" + cell $not $not$ls180.v:2873$30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2825$30_Y + connect \Y $not$ls180.v:2873$30_Y end - attribute \src "ls180.v:2826.61-2826.94" - cell $not $not$ls180.v:2826$31 + attribute \src "ls180.v:2874.61-2874.94" + cell $not $not$ls180.v:2874$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2826$31_Y + connect \Y $not$ls180.v:2874$31_Y end - attribute \src "ls180.v:2846.45-2846.83" - cell $not $not$ls180.v:2846$36 + attribute \src "ls180.v:2894.45-2894.83" + cell $not $not$ls180.v:2894$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2846$36_Y + connect \Y $not$ls180.v:2894$36_Y end - attribute \src "ls180.v:2885.61-2885.94" - cell $not $not$ls180.v:2885$41 + attribute \src "ls180.v:2933.61-2933.94" + cell $not $not$ls180.v:2933$41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2885$41_Y + connect \Y $not$ls180.v:2933$41_Y end - attribute \src "ls180.v:2886.61-2886.94" - cell $not $not$ls180.v:2886$42 + attribute \src "ls180.v:2934.61-2934.94" + cell $not $not$ls180.v:2934$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2886$42_Y + connect \Y $not$ls180.v:2934$42_Y end - attribute \src "ls180.v:3028.34-3028.64" - cell $not $not$ls180.v:3028$66 + attribute \src "ls180.v:3076.34-3076.64" + cell $not $not$ls180.v:3076$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3028$66_Y + connect \Y $not$ls180.v:3076$66_Y end - attribute \src "ls180.v:3029.31-3029.61" - cell $not $not$ls180.v:3029$67 + attribute \src "ls180.v:3077.31-3077.61" + cell $not $not$ls180.v:3077$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3029$67_Y + connect \Y $not$ls180.v:3077$67_Y end - attribute \src "ls180.v:3030.32-3030.62" - cell $not $not$ls180.v:3030$68 + attribute \src "ls180.v:3078.32-3078.62" + cell $not $not$ls180.v:3078$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3030$68_Y + connect \Y $not$ls180.v:3078$68_Y end - attribute \src "ls180.v:3031.32-3031.62" - cell $not $not$ls180.v:3031$69 + attribute \src "ls180.v:3079.32-3079.62" + cell $not $not$ls180.v:3079$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3031$69_Y + connect \Y $not$ls180.v:3079$69_Y end - attribute \src "ls180.v:3073.33-3073.56" - cell $not $not$ls180.v:3073$72 + attribute \src "ls180.v:3121.33-3121.56" + cell $not $not$ls180.v:3121$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3073$72_Y + connect \Y $not$ls180.v:3121$72_Y end - attribute \src "ls180.v:3174.58-3174.106" - cell $not $not$ls180.v:3174$102 + attribute \src "ls180.v:3222.58-3222.106" + cell $not $not$ls180.v:3222$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3174$102_Y + connect \Y $not$ls180.v:3222$102_Y end - attribute \src "ls180.v:3228.9-3228.45" - cell $not $not$ls180.v:3228$107 + attribute \src "ls180.v:3276.9-3276.45" + cell $not $not$ls180.v:3276$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3228$107_Y + connect \Y $not$ls180.v:3276$107_Y end - attribute \src "ls180.v:3331.58-3331.106" - cell $not $not$ls180.v:3331$132 + attribute \src "ls180.v:3379.58-3379.106" + cell $not $not$ls180.v:3379$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3331$132_Y + connect \Y $not$ls180.v:3379$132_Y end - attribute \src "ls180.v:3385.9-3385.45" - cell $not $not$ls180.v:3385$137 + attribute \src "ls180.v:3433.9-3433.45" + cell $not $not$ls180.v:3433$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3385$137_Y + connect \Y $not$ls180.v:3433$137_Y end - attribute \src "ls180.v:3488.58-3488.106" - cell $not $not$ls180.v:3488$162 + attribute \src "ls180.v:3536.58-3536.106" + cell $not $not$ls180.v:3536$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3488$162_Y + connect \Y $not$ls180.v:3536$162_Y end - attribute \src "ls180.v:3542.9-3542.45" - cell $not $not$ls180.v:3542$167 + attribute \src "ls180.v:3590.9-3590.45" + cell $not $not$ls180.v:3590$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3542$167_Y + connect \Y $not$ls180.v:3590$167_Y end - attribute \src "ls180.v:3645.58-3645.106" - cell $not $not$ls180.v:3645$192 + attribute \src "ls180.v:3693.58-3693.106" + cell $not $not$ls180.v:3693$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3645$192_Y + connect \Y $not$ls180.v:3693$192_Y end - attribute \src "ls180.v:3699.9-3699.45" - cell $not $not$ls180.v:3699$197 + attribute \src "ls180.v:3747.9-3747.45" + cell $not $not$ls180.v:3747$197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3699$197_Y + connect \Y $not$ls180.v:3747$197_Y end - attribute \src "ls180.v:3741.149-3741.187" - cell $not $not$ls180.v:3741$200 + attribute \src "ls180.v:3789.149-3789.187" + cell $not $not$ls180.v:3789$200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3741$200_Y + connect \Y $not$ls180.v:3789$200_Y end - attribute \src "ls180.v:3741.193-3741.230" - cell $not $not$ls180.v:3741$202 + attribute \src "ls180.v:3789.193-3789.230" + cell $not $not$ls180.v:3789$202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3741$202_Y + connect \Y $not$ls180.v:3789$202_Y end - attribute \src "ls180.v:3742.149-3742.187" - cell $not $not$ls180.v:3742$206 + attribute \src "ls180.v:3790.149-3790.187" + cell $not $not$ls180.v:3790$206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3742$206_Y + connect \Y $not$ls180.v:3790$206_Y end - attribute \src "ls180.v:3742.193-3742.230" - cell $not $not$ls180.v:3742$208 + attribute \src "ls180.v:3790.193-3790.230" + cell $not $not$ls180.v:3790$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3742$208_Y + connect \Y $not$ls180.v:3790$208_Y end - attribute \src "ls180.v:3758.43-3758.73" - cell $not $not$ls180.v:3758$236 + attribute \src "ls180.v:3806.43-3806.73" + cell $not $not$ls180.v:3806$236 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3758$236_Y + connect \Y $not$ls180.v:3806$236_Y end - attribute \src "ls180.v:3761.205-3761.245" - cell $not $not$ls180.v:3761$239 + attribute \src "ls180.v:3809.205-3809.245" + cell $not $not$ls180.v:3809$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3761$239_Y + connect \Y $not$ls180.v:3809$239_Y end - attribute \src "ls180.v:3761.251-3761.290" - cell $not $not$ls180.v:3761$241 + attribute \src "ls180.v:3809.251-3809.290" + cell $not $not$ls180.v:3809$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3761$241_Y + connect \Y $not$ls180.v:3809$241_Y end - attribute \src "ls180.v:3761.159-3761.292" - cell $not $not$ls180.v:3761$243 + attribute \src "ls180.v:3809.159-3809.292" + cell $not $not$ls180.v:3809$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3761$242_Y - connect \Y $not$ls180.v:3761$243_Y + connect \A $and$ls180.v:3809$242_Y + connect \Y $not$ls180.v:3809$243_Y end - attribute \src "ls180.v:3762.205-3762.245" - cell $not $not$ls180.v:3762$252 + attribute \src "ls180.v:3810.205-3810.245" + cell $not $not$ls180.v:3810$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3762$252_Y + connect \Y $not$ls180.v:3810$252_Y end - attribute \src "ls180.v:3762.251-3762.290" - cell $not $not$ls180.v:3762$254 + attribute \src "ls180.v:3810.251-3810.290" + cell $not $not$ls180.v:3810$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3762$254_Y + connect \Y $not$ls180.v:3810$254_Y end - attribute \src "ls180.v:3762.159-3762.292" - cell $not $not$ls180.v:3762$256 + attribute \src "ls180.v:3810.159-3810.292" + cell $not $not$ls180.v:3810$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3762$255_Y - connect \Y $not$ls180.v:3762$256_Y + connect \A $and$ls180.v:3810$255_Y + connect \Y $not$ls180.v:3810$256_Y end - attribute \src "ls180.v:3763.205-3763.245" - cell $not $not$ls180.v:3763$265 + attribute \src "ls180.v:3811.205-3811.245" + cell $not $not$ls180.v:3811$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3763$265_Y + connect \Y $not$ls180.v:3811$265_Y end - attribute \src "ls180.v:3763.251-3763.290" - cell $not $not$ls180.v:3763$267 + attribute \src "ls180.v:3811.251-3811.290" + cell $not $not$ls180.v:3811$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3763$267_Y + connect \Y $not$ls180.v:3811$267_Y end - attribute \src "ls180.v:3763.159-3763.292" - cell $not $not$ls180.v:3763$269 + attribute \src "ls180.v:3811.159-3811.292" + cell $not $not$ls180.v:3811$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3763$268_Y - connect \Y $not$ls180.v:3763$269_Y + connect \A $and$ls180.v:3811$268_Y + connect \Y $not$ls180.v:3811$269_Y end - attribute \src "ls180.v:3764.205-3764.245" - cell $not $not$ls180.v:3764$278 + attribute \src "ls180.v:3812.205-3812.245" + cell $not $not$ls180.v:3812$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3764$278_Y + connect \Y $not$ls180.v:3812$278_Y end - attribute \src "ls180.v:3764.251-3764.290" - cell $not $not$ls180.v:3764$280 + attribute \src "ls180.v:3812.251-3812.290" + cell $not $not$ls180.v:3812$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3764$280_Y + connect \Y $not$ls180.v:3812$280_Y end - attribute \src "ls180.v:3764.159-3764.292" - cell $not $not$ls180.v:3764$282 + attribute \src "ls180.v:3812.159-3812.292" + cell $not $not$ls180.v:3812$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3764$281_Y - connect \Y $not$ls180.v:3764$282_Y + connect \A $and$ls180.v:3812$281_Y + connect \Y $not$ls180.v:3812$282_Y end - attribute \src "ls180.v:3791.71-3791.103" - cell $not $not$ls180.v:3791$293 + attribute \src "ls180.v:3839.71-3839.103" + cell $not $not$ls180.v:3839$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3791$293_Y + connect \Y $not$ls180.v:3839$293_Y end - attribute \src "ls180.v:3794.205-3794.245" - cell $not $not$ls180.v:3794$297 + attribute \src "ls180.v:3842.205-3842.245" + cell $not $not$ls180.v:3842$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3794$297_Y + connect \Y $not$ls180.v:3842$297_Y end - attribute \src "ls180.v:3794.251-3794.290" - cell $not $not$ls180.v:3794$299 + attribute \src "ls180.v:3842.251-3842.290" + cell $not $not$ls180.v:3842$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3794$299_Y + connect \Y $not$ls180.v:3842$299_Y end - attribute \src "ls180.v:3794.159-3794.292" - cell $not $not$ls180.v:3794$301 + attribute \src "ls180.v:3842.159-3842.292" + cell $not $not$ls180.v:3842$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$300_Y - connect \Y $not$ls180.v:3794$301_Y + connect \A $and$ls180.v:3842$300_Y + connect \Y $not$ls180.v:3842$301_Y end - attribute \src "ls180.v:3795.205-3795.245" - cell $not $not$ls180.v:3795$310 + attribute \src "ls180.v:3843.205-3843.245" + cell $not $not$ls180.v:3843$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3795$310_Y + connect \Y $not$ls180.v:3843$310_Y end - attribute \src "ls180.v:3795.251-3795.290" - cell $not $not$ls180.v:3795$312 + attribute \src "ls180.v:3843.251-3843.290" + cell $not $not$ls180.v:3843$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3795$312_Y + connect \Y $not$ls180.v:3843$312_Y end - attribute \src "ls180.v:3795.159-3795.292" - cell $not $not$ls180.v:3795$314 + attribute \src "ls180.v:3843.159-3843.292" + cell $not $not$ls180.v:3843$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$313_Y - connect \Y $not$ls180.v:3795$314_Y + connect \A $and$ls180.v:3843$313_Y + connect \Y $not$ls180.v:3843$314_Y end - attribute \src "ls180.v:3796.205-3796.245" - cell $not $not$ls180.v:3796$323 + attribute \src "ls180.v:3844.205-3844.245" + cell $not $not$ls180.v:3844$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3796$323_Y + connect \Y $not$ls180.v:3844$323_Y end - attribute \src "ls180.v:3796.251-3796.290" - cell $not $not$ls180.v:3796$325 + attribute \src "ls180.v:3844.251-3844.290" + cell $not $not$ls180.v:3844$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3796$325_Y + connect \Y $not$ls180.v:3844$325_Y end - attribute \src "ls180.v:3796.159-3796.292" - cell $not $not$ls180.v:3796$327 + attribute \src "ls180.v:3844.159-3844.292" + cell $not $not$ls180.v:3844$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3796$326_Y - connect \Y $not$ls180.v:3796$327_Y + connect \A $and$ls180.v:3844$326_Y + connect \Y $not$ls180.v:3844$327_Y end - attribute \src "ls180.v:3797.205-3797.245" - cell $not $not$ls180.v:3797$336 + attribute \src "ls180.v:3845.205-3845.245" + cell $not $not$ls180.v:3845$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3797$336_Y + connect \Y $not$ls180.v:3845$336_Y end - attribute \src "ls180.v:3797.251-3797.290" - cell $not $not$ls180.v:3797$338 + attribute \src "ls180.v:3845.251-3845.290" + cell $not $not$ls180.v:3845$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3797$338_Y + connect \Y $not$ls180.v:3845$338_Y end - attribute \src "ls180.v:3797.159-3797.292" - cell $not $not$ls180.v:3797$340 + attribute \src "ls180.v:3845.159-3845.292" + cell $not $not$ls180.v:3845$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3797$339_Y - connect \Y $not$ls180.v:3797$340_Y + connect \A $and$ls180.v:3845$339_Y + connect \Y $not$ls180.v:3845$340_Y end - attribute \src "ls180.v:3860.71-3860.103" - cell $not $not$ls180.v:3860$379 + attribute \src "ls180.v:3908.71-3908.103" + cell $not $not$ls180.v:3908$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3860$379_Y + connect \Y $not$ls180.v:3908$379_Y end - attribute \src "ls180.v:3881.112-3881.150" - cell $not $not$ls180.v:3881$382 + attribute \src "ls180.v:3929.112-3929.150" + cell $not $not$ls180.v:3929$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3881$382_Y + connect \Y $not$ls180.v:3929$382_Y end - attribute \src "ls180.v:3881.156-3881.193" - cell $not $not$ls180.v:3881$384 + attribute \src "ls180.v:3929.156-3929.193" + cell $not $not$ls180.v:3929$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3881$384_Y + connect \Y $not$ls180.v:3929$384_Y end - attribute \src "ls180.v:3881.68-3881.195" - cell $not $not$ls180.v:3881$386 + attribute \src "ls180.v:3929.68-3929.195" + cell $not $not$ls180.v:3929$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3881$385_Y - connect \Y $not$ls180.v:3881$386_Y + connect \A $and$ls180.v:3929$385_Y + connect \Y $not$ls180.v:3929$386_Y end - attribute \src "ls180.v:3889.11-3889.38" - cell $not $not$ls180.v:3889$389 + attribute \src "ls180.v:3937.11-3937.38" + cell $not $not$ls180.v:3937$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3889$389_Y + connect \Y $not$ls180.v:3937$389_Y end - attribute \src "ls180.v:3919.112-3919.150" - cell $not $not$ls180.v:3919$391 + attribute \src "ls180.v:3967.112-3967.150" + cell $not $not$ls180.v:3967$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3919$391_Y + connect \Y $not$ls180.v:3967$391_Y end - attribute \src "ls180.v:3919.156-3919.193" - cell $not $not$ls180.v:3919$393 + attribute \src "ls180.v:3967.156-3967.193" + cell $not $not$ls180.v:3967$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3919$393_Y + connect \Y $not$ls180.v:3967$393_Y end - attribute \src "ls180.v:3919.68-3919.195" - cell $not $not$ls180.v:3919$395 + attribute \src "ls180.v:3967.68-3967.195" + cell $not $not$ls180.v:3967$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3919$394_Y - connect \Y $not$ls180.v:3919$395_Y + connect \A $and$ls180.v:3967$394_Y + connect \Y $not$ls180.v:3967$395_Y end - attribute \src "ls180.v:3927.11-3927.37" - cell $not $not$ls180.v:3927$398 + attribute \src "ls180.v:3975.11-3975.37" + cell $not $not$ls180.v:3975$398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3927$398_Y + connect \Y $not$ls180.v:3975$398_Y end - attribute \src "ls180.v:3937.87-3937.331" - cell $not $not$ls180.v:3937$410 + attribute \src "ls180.v:3985.87-3985.331" + cell $not $not$ls180.v:3985$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3937$409_Y - connect \Y $not$ls180.v:3937$410_Y + connect \A $or$ls180.v:3985$409_Y + connect \Y $not$ls180.v:3985$410_Y end - attribute \src "ls180.v:3938.35-3938.68" - cell $not $not$ls180.v:3938$413 + attribute \src "ls180.v:3986.35-3986.68" + cell $not $not$ls180.v:3986$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3938$413_Y + connect \Y $not$ls180.v:3986$413_Y end - attribute \src "ls180.v:3938.73-3938.105" - cell $not $not$ls180.v:3938$414 + attribute \src "ls180.v:3986.73-3986.105" + cell $not $not$ls180.v:3986$414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3938$414_Y + connect \Y $not$ls180.v:3986$414_Y end - attribute \src "ls180.v:3942.87-3942.331" - cell $not $not$ls180.v:3942$426 + attribute \src "ls180.v:3990.87-3990.331" + cell $not $not$ls180.v:3990$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3942$425_Y - connect \Y $not$ls180.v:3942$426_Y + connect \A $or$ls180.v:3990$425_Y + connect \Y $not$ls180.v:3990$426_Y end - attribute \src "ls180.v:3943.35-3943.68" - cell $not $not$ls180.v:3943$429 + attribute \src "ls180.v:3991.35-3991.68" + cell $not $not$ls180.v:3991$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3943$429_Y + connect \Y $not$ls180.v:3991$429_Y end - attribute \src "ls180.v:3943.73-3943.105" - cell $not $not$ls180.v:3943$430 + attribute \src "ls180.v:3991.73-3991.105" + cell $not $not$ls180.v:3991$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3943$430_Y + connect \Y $not$ls180.v:3991$430_Y end - attribute \src "ls180.v:3947.87-3947.331" - cell $not $not$ls180.v:3947$442 + attribute \src "ls180.v:3995.87-3995.331" + cell $not $not$ls180.v:3995$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3947$441_Y - connect \Y $not$ls180.v:3947$442_Y + connect \A $or$ls180.v:3995$441_Y + connect \Y $not$ls180.v:3995$442_Y end - attribute \src "ls180.v:3948.35-3948.68" - cell $not $not$ls180.v:3948$445 + attribute \src "ls180.v:3996.35-3996.68" + cell $not $not$ls180.v:3996$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3948$445_Y + connect \Y $not$ls180.v:3996$445_Y end - attribute \src "ls180.v:3948.73-3948.105" - cell $not $not$ls180.v:3948$446 + attribute \src "ls180.v:3996.73-3996.105" + cell $not $not$ls180.v:3996$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3948$446_Y + connect \Y $not$ls180.v:3996$446_Y end - attribute \src "ls180.v:3952.87-3952.331" - cell $not $not$ls180.v:3952$458 + attribute \src "ls180.v:4000.87-4000.331" + cell $not $not$ls180.v:4000$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3952$457_Y - connect \Y $not$ls180.v:3952$458_Y + connect \A $or$ls180.v:4000$457_Y + connect \Y $not$ls180.v:4000$458_Y end - attribute \src "ls180.v:3953.35-3953.68" - cell $not $not$ls180.v:3953$461 + attribute \src "ls180.v:4001.35-4001.68" + cell $not $not$ls180.v:4001$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:3953$461_Y + connect \Y $not$ls180.v:4001$461_Y end - attribute \src "ls180.v:3953.73-3953.105" - cell $not $not$ls180.v:3953$462 + attribute \src "ls180.v:4001.73-4001.105" + cell $not $not$ls180.v:4001$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:3953$462_Y + connect \Y $not$ls180.v:4001$462_Y end - attribute \src "ls180.v:3957.128-3957.372" - cell $not $not$ls180.v:3957$475 + attribute \src "ls180.v:4005.128-4005.372" + cell $not $not$ls180.v:4005$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$474_Y - connect \Y $not$ls180.v:3957$475_Y + connect \A $or$ls180.v:4005$474_Y + connect \Y $not$ls180.v:4005$475_Y end - attribute \src "ls180.v:3957.502-3957.746" - cell $not $not$ls180.v:3957$491 + attribute \src "ls180.v:4005.502-4005.746" + cell $not $not$ls180.v:4005$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$490_Y - connect \Y $not$ls180.v:3957$491_Y + connect \A $or$ls180.v:4005$490_Y + connect \Y $not$ls180.v:4005$491_Y end - attribute \src "ls180.v:3957.876-3957.1120" - cell $not $not$ls180.v:3957$507 + attribute \src "ls180.v:4005.876-4005.1120" + cell $not $not$ls180.v:4005$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$506_Y - connect \Y $not$ls180.v:3957$507_Y + connect \A $or$ls180.v:4005$506_Y + connect \Y $not$ls180.v:4005$507_Y end - attribute \src "ls180.v:3957.1250-3957.1494" - cell $not $not$ls180.v:3957$523 + attribute \src "ls180.v:4005.1250-4005.1494" + cell $not $not$ls180.v:4005$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$522_Y - connect \Y $not$ls180.v:3957$523_Y + connect \A $or$ls180.v:4005$522_Y + connect \Y $not$ls180.v:4005$523_Y end - attribute \src "ls180.v:3979.32-3979.50" - cell $not $not$ls180.v:3979$529 + attribute \src "ls180.v:4027.32-4027.50" + cell $not $not$ls180.v:4027$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:3979$529_Y + connect \Y $not$ls180.v:4027$529_Y end - attribute \src "ls180.v:4018.30-4018.50" - cell $not $not$ls180.v:4018$534 + attribute \src "ls180.v:4066.30-4066.50" + cell $not $not$ls180.v:4066$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4018$534_Y + connect \Y $not$ls180.v:4066$534_Y end - attribute \src "ls180.v:4019.30-4019.50" - cell $not $not$ls180.v:4019$535 + attribute \src "ls180.v:4067.30-4067.50" + cell $not $not$ls180.v:4067$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4019$535_Y + connect \Y $not$ls180.v:4067$535_Y end - attribute \src "ls180.v:4044.27-4044.48" - cell $not $not$ls180.v:4044$541 + attribute \src "ls180.v:4092.27-4092.48" + cell $not $not$ls180.v:4092$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4044$541_Y + connect \Y $not$ls180.v:4092$541_Y end - attribute \src "ls180.v:4045.30-4045.50" - cell $not $not$ls180.v:4045$542 + attribute \src "ls180.v:4093.30-4093.50" + cell $not $not$ls180.v:4093$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4045$542_Y + connect \Y $not$ls180.v:4093$542_Y end - attribute \src "ls180.v:4046.80-4046.98" - cell $not $not$ls180.v:4046$544 + attribute \src "ls180.v:4094.80-4094.98" + cell $not $not$ls180.v:4094$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4046$544_Y + connect \Y $not$ls180.v:4094$544_Y end - attribute \src "ls180.v:4047.107-4047.127" - cell $not $not$ls180.v:4047$548 + attribute \src "ls180.v:4095.107-4095.127" + cell $not $not$ls180.v:4095$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4047$548_Y + connect \Y $not$ls180.v:4095$548_Y end - attribute \src "ls180.v:4048.78-4048.103" - cell $not $not$ls180.v:4048$551 + attribute \src "ls180.v:4096.78-4096.103" + cell $not $not$ls180.v:4096$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4048$551_Y + connect \Y $not$ls180.v:4096$551_Y end - attribute \src "ls180.v:4049.91-4049.111" - cell $not $not$ls180.v:4049$554 + attribute \src "ls180.v:4097.91-4097.111" + cell $not $not$ls180.v:4097$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4049$554_Y + connect \Y $not$ls180.v:4097$554_Y end - attribute \src "ls180.v:4065.35-4065.64" - cell $not $not$ls180.v:4065$563 + attribute \src "ls180.v:4113.35-4113.64" + cell $not $not$ls180.v:4113$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4065$563_Y + connect \Y $not$ls180.v:4113$563_Y end - attribute \src "ls180.v:4066.36-4066.67" - cell $not $not$ls180.v:4066$564 + attribute \src "ls180.v:4114.36-4114.67" + cell $not $not$ls180.v:4114$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4066$564_Y + connect \Y $not$ls180.v:4114$564_Y end - attribute \src "ls180.v:4072.32-4072.61" - cell $not $not$ls180.v:4072$565 + attribute \src "ls180.v:4120.32-4120.61" + cell $not $not$ls180.v:4120$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4072$565_Y + connect \Y $not$ls180.v:4120$565_Y end - attribute \src "ls180.v:4078.36-4078.67" - cell $not $not$ls180.v:4078$566 + attribute \src "ls180.v:4126.36-4126.67" + cell $not $not$ls180.v:4126$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4078$566_Y + connect \Y $not$ls180.v:4126$566_Y end - attribute \src "ls180.v:4079.35-4079.64" - cell $not $not$ls180.v:4079$567 + attribute \src "ls180.v:4127.35-4127.64" + cell $not $not$ls180.v:4127$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4079$567_Y + connect \Y $not$ls180.v:4127$567_Y end - attribute \src "ls180.v:4082.32-4082.63" - cell $not $not$ls180.v:4082$570 + attribute \src "ls180.v:4130.32-4130.63" + cell $not $not$ls180.v:4130$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4082$570_Y + connect \Y $not$ls180.v:4130$570_Y end - attribute \src "ls180.v:4120.81-4120.108" - cell $not $not$ls180.v:4120$580 + attribute \src "ls180.v:4168.81-4168.108" + cell $not $not$ls180.v:4168$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4120$580_Y + connect \Y $not$ls180.v:4168$580_Y end - attribute \src "ls180.v:4150.81-4150.108" - cell $not $not$ls180.v:4150$591 + attribute \src "ls180.v:4198.81-4198.108" + cell $not $not$ls180.v:4198$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4150$591_Y + connect \Y $not$ls180.v:4198$591_Y end - attribute \src "ls180.v:4287.60-4287.85" - cell $not $not$ls180.v:4287$632 + attribute \src "ls180.v:4398.60-4398.85" + cell $not $not$ls180.v:4398$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4287$632_Y + connect \Y $not$ls180.v:4398$640_Y end - attribute \src "ls180.v:4428.54-4428.96" - cell $not $not$ls180.v:4428$646 + attribute \src "ls180.v:4539.54-4539.96" + cell $not $not$ls180.v:4539$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4428$646_Y + connect \Y $not$ls180.v:4539$654_Y end - attribute \src "ls180.v:4431.48-4431.86" - cell $not $not$ls180.v:4431$649 + attribute \src "ls180.v:4542.48-4542.86" + cell $not $not$ls180.v:4542$657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4431$649_Y + connect \Y $not$ls180.v:4542$657_Y end - attribute \src "ls180.v:4555.55-4555.98" - cell $not $not$ls180.v:4555$667 + attribute \src "ls180.v:4666.55-4666.98" + cell $not $not$ls180.v:4666$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4555$667_Y + connect \Y $not$ls180.v:4666$675_Y end - attribute \src "ls180.v:4558.49-4558.88" - cell $not $not$ls180.v:4558$670 + attribute \src "ls180.v:4669.49-4669.88" + cell $not $not$ls180.v:4669$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4558$670_Y + connect \Y $not$ls180.v:4669$678_Y end - attribute \src "ls180.v:4608.30-4608.58" - cell $not $not$ls180.v:4608$676 + attribute \src "ls180.v:4719.30-4719.58" + cell $not $not$ls180.v:4719$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4608$676_Y + connect \Y $not$ls180.v:4719$684_Y end - attribute \src "ls180.v:4689.56-4689.100" - cell $not $not$ls180.v:4689$682 + attribute \src "ls180.v:4800.56-4800.100" + cell $not $not$ls180.v:4800$690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4689$682_Y + connect \Y $not$ls180.v:4800$690_Y end - attribute \src "ls180.v:4692.50-4692.90" - cell $not $not$ls180.v:4692$685 + attribute \src "ls180.v:4803.50-4803.90" + cell $not $not$ls180.v:4803$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4692$685_Y + connect \Y $not$ls180.v:4803$693_Y end - attribute \src "ls180.v:4808.42-4808.74" - cell $not $not$ls180.v:4808$701 + attribute \src "ls180.v:4919.42-4919.74" + cell $not $not$ls180.v:4919$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4808$701_Y + connect \Y $not$ls180.v:4919$709_Y end - attribute \src "ls180.v:5332.50-5332.88" - cell $not $not$ls180.v:5332$986 + attribute \src "ls180.v:5443.50-5443.88" + cell $not $not$ls180.v:5443$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5332$986_Y + connect \Y $not$ls180.v:5443$994_Y end - attribute \src "ls180.v:5344.52-5344.102" - cell $not $not$ls180.v:5344$989 + attribute \src "ls180.v:5455.52-5455.102" + cell $not $not$ls180.v:5455$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5344$989_Y + connect \Y $not$ls180.v:5455$997_Y end - attribute \src "ls180.v:5403.38-5403.74" - cell $not $not$ls180.v:5403$996 + attribute \src "ls180.v:5514.38-5514.74" + cell $not $not$ls180.v:5514$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5403$996_Y + connect \Y $not$ls180.v:5514$1004_Y end - attribute \src "ls180.v:5704.69-5704.88" - cell $not $not$ls180.v:5704$1065 + attribute \src "ls180.v:5756.69-5756.88" + cell $not $not$ls180.v:5756$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:5704$1065_Y + connect \Y $not$ls180.v:5756$1065_Y end - attribute \src "ls180.v:5721.63-5721.94" - cell $not $not$ls180.v:5721$1086 + attribute \src "ls180.v:5773.63-5773.94" + cell $not $not$ls180.v:5773$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5721$1086_Y + connect \Y $not$ls180.v:5773$1086_Y end - attribute \src "ls180.v:5724.65-5724.96" - cell $not $not$ls180.v:5724$1093 + attribute \src "ls180.v:5776.65-5776.96" + cell $not $not$ls180.v:5776$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5724$1093_Y + connect \Y $not$ls180.v:5776$1093_Y end - attribute \src "ls180.v:5727.65-5727.96" - cell $not $not$ls180.v:5727$1100 + attribute \src "ls180.v:5779.65-5779.96" + cell $not $not$ls180.v:5779$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5727$1100_Y + connect \Y $not$ls180.v:5779$1100_Y end - attribute \src "ls180.v:5730.65-5730.96" - cell $not $not$ls180.v:5730$1107 + attribute \src "ls180.v:5782.65-5782.96" + cell $not $not$ls180.v:5782$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5730$1107_Y + connect \Y $not$ls180.v:5782$1107_Y end - attribute \src "ls180.v:5733.65-5733.96" - cell $not $not$ls180.v:5733$1114 + attribute \src "ls180.v:5785.65-5785.96" + cell $not $not$ls180.v:5785$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5733$1114_Y + connect \Y $not$ls180.v:5785$1114_Y end - attribute \src "ls180.v:5736.68-5736.99" - cell $not $not$ls180.v:5736$1121 + attribute \src "ls180.v:5788.68-5788.99" + cell $not $not$ls180.v:5788$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5736$1121_Y + connect \Y $not$ls180.v:5788$1121_Y end - attribute \src "ls180.v:5739.68-5739.99" - cell $not $not$ls180.v:5739$1128 + attribute \src "ls180.v:5791.68-5791.99" + cell $not $not$ls180.v:5791$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5739$1128_Y + connect \Y $not$ls180.v:5791$1128_Y end - attribute \src "ls180.v:5742.68-5742.99" - cell $not $not$ls180.v:5742$1135 + attribute \src "ls180.v:5794.68-5794.99" + cell $not $not$ls180.v:5794$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5742$1135_Y + connect \Y $not$ls180.v:5794$1135_Y end - attribute \src "ls180.v:5745.68-5745.99" - cell $not $not$ls180.v:5745$1142 + attribute \src "ls180.v:5797.68-5797.99" + cell $not $not$ls180.v:5797$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5745$1142_Y + connect \Y $not$ls180.v:5797$1142_Y end - attribute \src "ls180.v:5759.60-5759.91" - cell $not $not$ls180.v:5759$1150 + attribute \src "ls180.v:5811.60-5811.91" + cell $not $not$ls180.v:5811$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5759$1150_Y + connect \Y $not$ls180.v:5811$1150_Y end - attribute \src "ls180.v:5762.60-5762.91" - cell $not $not$ls180.v:5762$1157 + attribute \src "ls180.v:5814.60-5814.91" + cell $not $not$ls180.v:5814$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5762$1157_Y + connect \Y $not$ls180.v:5814$1157_Y end - attribute \src "ls180.v:5765.60-5765.91" - cell $not $not$ls180.v:5765$1164 + attribute \src "ls180.v:5817.60-5817.91" + cell $not $not$ls180.v:5817$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5765$1164_Y + connect \Y $not$ls180.v:5817$1164_Y end - attribute \src "ls180.v:5768.60-5768.91" - cell $not $not$ls180.v:5768$1171 + attribute \src "ls180.v:5820.60-5820.91" + cell $not $not$ls180.v:5820$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5768$1171_Y + connect \Y $not$ls180.v:5820$1171_Y end - attribute \src "ls180.v:5771.61-5771.92" - cell $not $not$ls180.v:5771$1178 + attribute \src "ls180.v:5823.61-5823.92" + cell $not $not$ls180.v:5823$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5771$1178_Y + connect \Y $not$ls180.v:5823$1178_Y end - attribute \src "ls180.v:5774.61-5774.92" - cell $not $not$ls180.v:5774$1185 + attribute \src "ls180.v:5826.61-5826.92" + cell $not $not$ls180.v:5826$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5774$1185_Y - end - attribute \src "ls180.v:5785.64-5785.95" - cell $not $not$ls180.v:5785$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5785$1193_Y - end - attribute \src "ls180.v:5788.63-5788.94" - cell $not $not$ls180.v:5788$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5788$1200_Y - end - attribute \src "ls180.v:5791.63-5791.94" - cell $not $not$ls180.v:5791$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5791$1207_Y - end - attribute \src "ls180.v:5794.63-5794.94" - cell $not $not$ls180.v:5794$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5794$1214_Y - end - attribute \src "ls180.v:5797.63-5797.94" - cell $not $not$ls180.v:5797$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5797$1221_Y - end - attribute \src "ls180.v:5800.64-5800.95" - cell $not $not$ls180.v:5800$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5800$1228_Y + connect \Y $not$ls180.v:5826$1185_Y end - attribute \src "ls180.v:5803.64-5803.95" - cell $not $not$ls180.v:5803$1235 + attribute \src "ls180.v:5837.59-5837.90" + cell $not $not$ls180.v:5837$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5803$1235_Y + connect \Y $not$ls180.v:5837$1193_Y end - attribute \src "ls180.v:5806.64-5806.95" - cell $not $not$ls180.v:5806$1242 + attribute \src "ls180.v:5840.58-5840.89" + cell $not $not$ls180.v:5840$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5806$1242_Y + connect \Y $not$ls180.v:5840$1200_Y end - attribute \src "ls180.v:5809.64-5809.95" - cell $not $not$ls180.v:5809$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5809$1249_Y - end - attribute \src "ls180.v:5822.64-5822.95" - cell $not $not$ls180.v:5822$1257 + attribute \src "ls180.v:5851.64-5851.95" + cell $not $not$ls180.v:5851$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5822$1257_Y + connect \Y $not$ls180.v:5851$1208_Y end - attribute \src "ls180.v:5825.63-5825.94" - cell $not $not$ls180.v:5825$1264 + attribute \src "ls180.v:5854.63-5854.94" + cell $not $not$ls180.v:5854$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5825$1264_Y + connect \Y $not$ls180.v:5854$1215_Y end - attribute \src "ls180.v:5828.63-5828.94" - cell $not $not$ls180.v:5828$1271 + attribute \src "ls180.v:5857.63-5857.94" + cell $not $not$ls180.v:5857$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5828$1271_Y + connect \Y $not$ls180.v:5857$1222_Y end - attribute \src "ls180.v:5831.63-5831.94" - cell $not $not$ls180.v:5831$1278 + attribute \src "ls180.v:5860.63-5860.94" + cell $not $not$ls180.v:5860$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5831$1278_Y + connect \Y $not$ls180.v:5860$1229_Y end - attribute \src "ls180.v:5834.63-5834.94" - cell $not $not$ls180.v:5834$1285 + attribute \src "ls180.v:5863.63-5863.94" + cell $not $not$ls180.v:5863$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5834$1285_Y + connect \Y $not$ls180.v:5863$1236_Y end - attribute \src "ls180.v:5837.64-5837.95" - cell $not $not$ls180.v:5837$1292 + attribute \src "ls180.v:5866.64-5866.95" + cell $not $not$ls180.v:5866$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5837$1292_Y + connect \Y $not$ls180.v:5866$1243_Y end - attribute \src "ls180.v:5840.64-5840.95" - cell $not $not$ls180.v:5840$1299 + attribute \src "ls180.v:5869.64-5869.95" + cell $not $not$ls180.v:5869$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5840$1299_Y + connect \Y $not$ls180.v:5869$1250_Y end - attribute \src "ls180.v:5843.64-5843.95" - cell $not $not$ls180.v:5843$1306 + attribute \src "ls180.v:5872.64-5872.95" + cell $not $not$ls180.v:5872$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5843$1306_Y + connect \Y $not$ls180.v:5872$1257_Y end - attribute \src "ls180.v:5846.64-5846.95" - cell $not $not$ls180.v:5846$1313 + attribute \src "ls180.v:5875.64-5875.95" + cell $not $not$ls180.v:5875$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5846$1313_Y - end - attribute \src "ls180.v:5859.66-5859.97" - cell $not $not$ls180.v:5859$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5859$1321_Y - end - attribute \src "ls180.v:5862.66-5862.97" - cell $not $not$ls180.v:5862$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5862$1328_Y - end - attribute \src "ls180.v:5865.66-5865.97" - cell $not $not$ls180.v:5865$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5865$1335_Y - end - attribute \src "ls180.v:5868.66-5868.97" - cell $not $not$ls180.v:5868$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5868$1342_Y - end - attribute \src "ls180.v:5871.66-5871.97" - cell $not $not$ls180.v:5871$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5871$1349_Y + connect \Y $not$ls180.v:5875$1264_Y end - attribute \src "ls180.v:5874.66-5874.97" - cell $not $not$ls180.v:5874$1356 + attribute \src "ls180.v:5888.64-5888.95" + cell $not $not$ls180.v:5888$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5874$1356_Y + connect \Y $not$ls180.v:5888$1272_Y end - attribute \src "ls180.v:5877.66-5877.97" - cell $not $not$ls180.v:5877$1363 + attribute \src "ls180.v:5891.63-5891.94" + cell $not $not$ls180.v:5891$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5877$1363_Y + connect \Y $not$ls180.v:5891$1279_Y end - attribute \src "ls180.v:5880.66-5880.97" - cell $not $not$ls180.v:5880$1370 + attribute \src "ls180.v:5894.63-5894.94" + cell $not $not$ls180.v:5894$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5880$1370_Y + connect \Y $not$ls180.v:5894$1286_Y end - attribute \src "ls180.v:5883.68-5883.99" - cell $not $not$ls180.v:5883$1377 + attribute \src "ls180.v:5897.63-5897.94" + cell $not $not$ls180.v:5897$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5883$1377_Y + connect \Y $not$ls180.v:5897$1293_Y end - attribute \src "ls180.v:5886.68-5886.99" - cell $not $not$ls180.v:5886$1384 + attribute \src "ls180.v:5900.63-5900.94" + cell $not $not$ls180.v:5900$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5886$1384_Y + connect \Y $not$ls180.v:5900$1300_Y end - attribute \src "ls180.v:5889.68-5889.99" - cell $not $not$ls180.v:5889$1391 + attribute \src "ls180.v:5903.64-5903.95" + cell $not $not$ls180.v:5903$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5889$1391_Y + connect \Y $not$ls180.v:5903$1307_Y end - attribute \src "ls180.v:5892.68-5892.99" - cell $not $not$ls180.v:5892$1398 + attribute \src "ls180.v:5906.64-5906.95" + cell $not $not$ls180.v:5906$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5892$1398_Y + connect \Y $not$ls180.v:5906$1314_Y end - attribute \src "ls180.v:5895.68-5895.99" - cell $not $not$ls180.v:5895$1405 + attribute \src "ls180.v:5909.64-5909.95" + cell $not $not$ls180.v:5909$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5895$1405_Y + connect \Y $not$ls180.v:5909$1321_Y end - attribute \src "ls180.v:5898.65-5898.96" - cell $not $not$ls180.v:5898$1412 + attribute \src "ls180.v:5912.64-5912.95" + cell $not $not$ls180.v:5912$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5898$1412_Y + connect \Y $not$ls180.v:5912$1328_Y end - attribute \src "ls180.v:5901.66-5901.97" - cell $not $not$ls180.v:5901$1419 + attribute \src "ls180.v:5925.66-5925.97" + cell $not $not$ls180.v:5925$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5901$1419_Y + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5925$1336_Y end - attribute \src "ls180.v:5921.70-5921.101" - cell $not $not$ls180.v:5921$1427 + attribute \src "ls180.v:5928.66-5928.97" + cell $not $not$ls180.v:5928$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5921$1427_Y + connect \Y $not$ls180.v:5928$1343_Y end - attribute \src "ls180.v:5924.70-5924.101" - cell $not $not$ls180.v:5924$1434 + attribute \src "ls180.v:5931.66-5931.97" + cell $not $not$ls180.v:5931$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5924$1434_Y + connect \Y $not$ls180.v:5931$1350_Y end - attribute \src "ls180.v:5927.70-5927.101" - cell $not $not$ls180.v:5927$1441 + attribute \src "ls180.v:5934.66-5934.97" + cell $not $not$ls180.v:5934$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5927$1441_Y + connect \Y $not$ls180.v:5934$1357_Y end - attribute \src "ls180.v:5930.70-5930.101" - cell $not $not$ls180.v:5930$1448 + attribute \src "ls180.v:5937.66-5937.97" + cell $not $not$ls180.v:5937$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5930$1448_Y + connect \Y $not$ls180.v:5937$1364_Y end - attribute \src "ls180.v:5933.69-5933.100" - cell $not $not$ls180.v:5933$1455 + attribute \src "ls180.v:5940.66-5940.97" + cell $not $not$ls180.v:5940$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5933$1455_Y + connect \Y $not$ls180.v:5940$1371_Y end - attribute \src "ls180.v:5936.69-5936.100" - cell $not $not$ls180.v:5936$1462 + attribute \src "ls180.v:5943.66-5943.97" + cell $not $not$ls180.v:5943$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5936$1462_Y + connect \Y $not$ls180.v:5943$1378_Y end - attribute \src "ls180.v:5939.69-5939.100" - cell $not $not$ls180.v:5939$1469 + attribute \src "ls180.v:5946.66-5946.97" + cell $not $not$ls180.v:5946$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5939$1469_Y + connect \Y $not$ls180.v:5946$1385_Y end - attribute \src "ls180.v:5942.69-5942.100" - cell $not $not$ls180.v:5942$1476 + attribute \src "ls180.v:5949.68-5949.99" + cell $not $not$ls180.v:5949$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5942$1476_Y + connect \Y $not$ls180.v:5949$1392_Y end - attribute \src "ls180.v:5945.60-5945.91" - cell $not $not$ls180.v:5945$1483 + attribute \src "ls180.v:5952.68-5952.99" + cell $not $not$ls180.v:5952$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5945$1483_Y + connect \Y $not$ls180.v:5952$1399_Y end - attribute \src "ls180.v:5948.71-5948.102" - cell $not $not$ls180.v:5948$1490 + attribute \src "ls180.v:5955.68-5955.99" + cell $not $not$ls180.v:5955$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5948$1490_Y + connect \Y $not$ls180.v:5955$1406_Y end - attribute \src "ls180.v:5951.71-5951.102" - cell $not $not$ls180.v:5951$1497 + attribute \src "ls180.v:5958.68-5958.99" + cell $not $not$ls180.v:5958$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5951$1497_Y + connect \Y $not$ls180.v:5958$1413_Y end - attribute \src "ls180.v:5954.71-5954.102" - cell $not $not$ls180.v:5954$1504 + attribute \src "ls180.v:5961.68-5961.99" + cell $not $not$ls180.v:5961$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5954$1504_Y + connect \Y $not$ls180.v:5961$1420_Y end - attribute \src "ls180.v:5957.71-5957.102" - cell $not $not$ls180.v:5957$1511 + attribute \src "ls180.v:5964.65-5964.96" + cell $not $not$ls180.v:5964$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5957$1511_Y + connect \Y $not$ls180.v:5964$1427_Y end - attribute \src "ls180.v:5960.71-5960.102" - cell $not $not$ls180.v:5960$1518 + attribute \src "ls180.v:5967.66-5967.97" + cell $not $not$ls180.v:5967$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5960$1518_Y + connect \Y $not$ls180.v:5967$1434_Y end - attribute \src "ls180.v:5963.71-5963.102" - cell $not $not$ls180.v:5963$1525 + attribute \src "ls180.v:5987.70-5987.101" + cell $not $not$ls180.v:5987$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5963$1525_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5987$1442_Y end - attribute \src "ls180.v:5966.70-5966.101" - cell $not $not$ls180.v:5966$1532 + attribute \src "ls180.v:5990.70-5990.101" + cell $not $not$ls180.v:5990$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5966$1532_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5990$1449_Y end - attribute \src "ls180.v:5969.70-5969.101" - cell $not $not$ls180.v:5969$1539 + attribute \src "ls180.v:5993.70-5993.101" + cell $not $not$ls180.v:5993$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5969$1539_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5993$1456_Y end - attribute \src "ls180.v:5972.70-5972.101" - cell $not $not$ls180.v:5972$1546 + attribute \src "ls180.v:5996.70-5996.101" + cell $not $not$ls180.v:5996$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5972$1546_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5996$1463_Y end - attribute \src "ls180.v:5975.70-5975.101" - cell $not $not$ls180.v:5975$1553 + attribute \src "ls180.v:5999.69-5999.100" + cell $not $not$ls180.v:5999$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5975$1553_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5999$1470_Y end - attribute \src "ls180.v:5978.70-5978.101" - cell $not $not$ls180.v:5978$1560 + attribute \src "ls180.v:6002.69-6002.100" + cell $not $not$ls180.v:6002$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5978$1560_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6002$1477_Y end - attribute \src "ls180.v:5981.70-5981.101" - cell $not $not$ls180.v:5981$1567 + attribute \src "ls180.v:6005.69-6005.100" + cell $not $not$ls180.v:6005$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5981$1567_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6005$1484_Y end - attribute \src "ls180.v:5984.70-5984.101" - cell $not $not$ls180.v:5984$1574 + attribute \src "ls180.v:6008.69-6008.100" + cell $not $not$ls180.v:6008$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5984$1574_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6008$1491_Y end - attribute \src "ls180.v:5987.70-5987.101" - cell $not $not$ls180.v:5987$1581 + attribute \src "ls180.v:6011.60-6011.91" + cell $not $not$ls180.v:6011$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5987$1581_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6011$1498_Y end - attribute \src "ls180.v:5990.70-5990.101" - cell $not $not$ls180.v:5990$1588 + attribute \src "ls180.v:6014.71-6014.102" + cell $not $not$ls180.v:6014$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5990$1588_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6014$1505_Y end - attribute \src "ls180.v:5993.70-5993.101" - cell $not $not$ls180.v:5993$1595 + attribute \src "ls180.v:6017.71-6017.102" + cell $not $not$ls180.v:6017$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5993$1595_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6017$1512_Y end - attribute \src "ls180.v:5996.66-5996.97" - cell $not $not$ls180.v:5996$1602 + attribute \src "ls180.v:6020.71-6020.102" + cell $not $not$ls180.v:6020$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5996$1602_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6020$1519_Y end - attribute \src "ls180.v:5999.67-5999.98" - cell $not $not$ls180.v:5999$1609 + attribute \src "ls180.v:6023.71-6023.102" + cell $not $not$ls180.v:6023$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5999$1609_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6023$1526_Y end - attribute \src "ls180.v:6002.70-6002.101" - cell $not $not$ls180.v:6002$1616 + attribute \src "ls180.v:6026.71-6026.102" + cell $not $not$ls180.v:6026$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6002$1616_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6026$1533_Y end - attribute \src "ls180.v:6005.70-6005.101" - cell $not $not$ls180.v:6005$1623 + attribute \src "ls180.v:6029.71-6029.102" + cell $not $not$ls180.v:6029$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6005$1623_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6029$1540_Y end - attribute \src "ls180.v:6008.69-6008.100" - cell $not $not$ls180.v:6008$1630 + attribute \src "ls180.v:6032.70-6032.101" + cell $not $not$ls180.v:6032$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6008$1630_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6032$1547_Y end - attribute \src "ls180.v:6011.69-6011.100" - cell $not $not$ls180.v:6011$1637 + attribute \src "ls180.v:6035.70-6035.101" + cell $not $not$ls180.v:6035$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6011$1637_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6035$1554_Y end - attribute \src "ls180.v:6014.69-6014.100" - cell $not $not$ls180.v:6014$1644 + attribute \src "ls180.v:6038.70-6038.101" + cell $not $not$ls180.v:6038$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6014$1644_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6038$1561_Y end - attribute \src "ls180.v:6017.69-6017.100" - cell $not $not$ls180.v:6017$1651 + attribute \src "ls180.v:6041.70-6041.101" + cell $not $not$ls180.v:6041$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6017$1651_Y + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6041$1568_Y end - attribute \src "ls180.v:6056.66-6056.97" - cell $not $not$ls180.v:6056$1659 + attribute \src "ls180.v:6044.70-6044.101" + cell $not $not$ls180.v:6044$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6056$1659_Y + connect \Y $not$ls180.v:6044$1575_Y end - attribute \src "ls180.v:6059.66-6059.97" - cell $not $not$ls180.v:6059$1666 + attribute \src "ls180.v:6047.70-6047.101" + cell $not $not$ls180.v:6047$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6059$1666_Y + connect \Y $not$ls180.v:6047$1582_Y end - attribute \src "ls180.v:6062.66-6062.97" - cell $not $not$ls180.v:6062$1673 + attribute \src "ls180.v:6050.70-6050.101" + cell $not $not$ls180.v:6050$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6062$1673_Y + connect \Y $not$ls180.v:6050$1589_Y end - attribute \src "ls180.v:6065.66-6065.97" - cell $not $not$ls180.v:6065$1680 + attribute \src "ls180.v:6053.70-6053.101" + cell $not $not$ls180.v:6053$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6065$1680_Y + connect \Y $not$ls180.v:6053$1596_Y end - attribute \src "ls180.v:6068.66-6068.97" - cell $not $not$ls180.v:6068$1687 + attribute \src "ls180.v:6056.70-6056.101" + cell $not $not$ls180.v:6056$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6068$1687_Y + connect \Y $not$ls180.v:6056$1603_Y end - attribute \src "ls180.v:6071.66-6071.97" - cell $not $not$ls180.v:6071$1694 + attribute \src "ls180.v:6059.70-6059.101" + cell $not $not$ls180.v:6059$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6071$1694_Y + connect \Y $not$ls180.v:6059$1610_Y end - attribute \src "ls180.v:6074.66-6074.97" - cell $not $not$ls180.v:6074$1701 + attribute \src "ls180.v:6062.66-6062.97" + cell $not $not$ls180.v:6062$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6074$1701_Y + connect \Y $not$ls180.v:6062$1617_Y end - attribute \src "ls180.v:6077.66-6077.97" - cell $not $not$ls180.v:6077$1708 + attribute \src "ls180.v:6065.67-6065.98" + cell $not $not$ls180.v:6065$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6077$1708_Y + connect \Y $not$ls180.v:6065$1624_Y end - attribute \src "ls180.v:6080.68-6080.99" - cell $not $not$ls180.v:6080$1715 + attribute \src "ls180.v:6068.70-6068.101" + cell $not $not$ls180.v:6068$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6080$1715_Y + connect \Y $not$ls180.v:6068$1631_Y end - attribute \src "ls180.v:6083.68-6083.99" - cell $not $not$ls180.v:6083$1722 + attribute \src "ls180.v:6071.70-6071.101" + cell $not $not$ls180.v:6071$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6083$1722_Y + connect \Y $not$ls180.v:6071$1638_Y end - attribute \src "ls180.v:6086.68-6086.99" - cell $not $not$ls180.v:6086$1729 + attribute \src "ls180.v:6074.69-6074.100" + cell $not $not$ls180.v:6074$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6086$1729_Y + connect \Y $not$ls180.v:6074$1645_Y end - attribute \src "ls180.v:6089.68-6089.99" - cell $not $not$ls180.v:6089$1736 + attribute \src "ls180.v:6077.69-6077.100" + cell $not $not$ls180.v:6077$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6089$1736_Y + connect \Y $not$ls180.v:6077$1652_Y end - attribute \src "ls180.v:6092.68-6092.99" - cell $not $not$ls180.v:6092$1743 + attribute \src "ls180.v:6080.69-6080.100" + cell $not $not$ls180.v:6080$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6092$1743_Y + connect \Y $not$ls180.v:6080$1659_Y end - attribute \src "ls180.v:6095.65-6095.96" - cell $not $not$ls180.v:6095$1750 + attribute \src "ls180.v:6083.69-6083.100" + cell $not $not$ls180.v:6083$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6095$1750_Y + connect \Y $not$ls180.v:6083$1666_Y end - attribute \src "ls180.v:6098.66-6098.97" - cell $not $not$ls180.v:6098$1757 + attribute \src "ls180.v:6122.66-6122.97" + cell $not $not$ls180.v:6122$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6098$1757_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6122$1674_Y end - attribute \src "ls180.v:6101.68-6101.99" - cell $not $not$ls180.v:6101$1764 + attribute \src "ls180.v:6125.66-6125.97" + cell $not $not$ls180.v:6125$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6101$1764_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6125$1681_Y end - attribute \src "ls180.v:6104.68-6104.99" - cell $not $not$ls180.v:6104$1771 + attribute \src "ls180.v:6128.66-6128.97" + cell $not $not$ls180.v:6128$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6104$1771_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6128$1688_Y end - attribute \src "ls180.v:6107.68-6107.99" - cell $not $not$ls180.v:6107$1778 + attribute \src "ls180.v:6131.66-6131.97" + cell $not $not$ls180.v:6131$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6107$1778_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6131$1695_Y end - attribute \src "ls180.v:6110.68-6110.99" - cell $not $not$ls180.v:6110$1785 + attribute \src "ls180.v:6134.66-6134.97" + cell $not $not$ls180.v:6134$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6110$1785_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6134$1702_Y end - attribute \src "ls180.v:6135.68-6135.99" - cell $not $not$ls180.v:6135$1793 + attribute \src "ls180.v:6137.66-6137.97" + cell $not $not$ls180.v:6137$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6135$1793_Y + connect \Y $not$ls180.v:6137$1709_Y end - attribute \src "ls180.v:6138.73-6138.104" - cell $not $not$ls180.v:6138$1800 + attribute \src "ls180.v:6140.66-6140.97" + cell $not $not$ls180.v:6140$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6138$1800_Y + connect \Y $not$ls180.v:6140$1716_Y end - attribute \src "ls180.v:6141.73-6141.104" - cell $not $not$ls180.v:6141$1807 + attribute \src "ls180.v:6143.66-6143.97" + cell $not $not$ls180.v:6143$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6141$1807_Y + connect \Y $not$ls180.v:6143$1723_Y end - attribute \src "ls180.v:6144.66-6144.97" - cell $not $not$ls180.v:6144$1814 + attribute \src "ls180.v:6146.68-6146.99" + cell $not $not$ls180.v:6146$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6144$1814_Y + connect \Y $not$ls180.v:6146$1730_Y end - attribute \src "ls180.v:6152.70-6152.101" - cell $not $not$ls180.v:6152$1822 + attribute \src "ls180.v:6149.68-6149.99" + cell $not $not$ls180.v:6149$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6152$1822_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6149$1737_Y end - attribute \src "ls180.v:6155.74-6155.105" - cell $not $not$ls180.v:6155$1829 + attribute \src "ls180.v:6152.68-6152.99" + cell $not $not$ls180.v:6152$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6155$1829_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6152$1744_Y end - attribute \src "ls180.v:6158.64-6158.95" - cell $not $not$ls180.v:6158$1836 + attribute \src "ls180.v:6155.68-6155.99" + cell $not $not$ls180.v:6155$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6158$1836_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6155$1751_Y end - attribute \src "ls180.v:6161.74-6161.105" - cell $not $not$ls180.v:6161$1843 + attribute \src "ls180.v:6158.68-6158.99" + cell $not $not$ls180.v:6158$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6161$1843_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6158$1758_Y end - attribute \src "ls180.v:6164.74-6164.105" - cell $not $not$ls180.v:6164$1850 + attribute \src "ls180.v:6161.65-6161.96" + cell $not $not$ls180.v:6161$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6164$1850_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6161$1765_Y end - attribute \src "ls180.v:6167.75-6167.106" - cell $not $not$ls180.v:6167$1857 + attribute \src "ls180.v:6164.66-6164.97" + cell $not $not$ls180.v:6164$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6167$1857_Y + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6164$1772_Y + end + attribute \src "ls180.v:6167.68-6167.99" + cell $not $not$ls180.v:6167$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6167$1779_Y + end + attribute \src "ls180.v:6170.68-6170.99" + cell $not $not$ls180.v:6170$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6170$1786_Y + end + attribute \src "ls180.v:6173.68-6173.99" + cell $not $not$ls180.v:6173$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6173$1793_Y + end + attribute \src "ls180.v:6176.68-6176.99" + cell $not $not$ls180.v:6176$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6176$1800_Y end - attribute \src "ls180.v:6170.73-6170.104" - cell $not $not$ls180.v:6170$1864 + attribute \src "ls180.v:6201.68-6201.99" + cell $not $not$ls180.v:6201$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6170$1864_Y + connect \Y $not$ls180.v:6201$1808_Y end - attribute \src "ls180.v:6173.73-6173.104" - cell $not $not$ls180.v:6173$1871 + attribute \src "ls180.v:6204.73-6204.104" + cell $not $not$ls180.v:6204$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6173$1871_Y + connect \Y $not$ls180.v:6204$1815_Y end - attribute \src "ls180.v:6176.73-6176.104" - cell $not $not$ls180.v:6176$1878 + attribute \src "ls180.v:6207.73-6207.104" + cell $not $not$ls180.v:6207$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6176$1878_Y + connect \Y $not$ls180.v:6207$1822_Y end - attribute \src "ls180.v:6179.73-6179.104" - cell $not $not$ls180.v:6179$1885 + attribute \src "ls180.v:6210.66-6210.97" + cell $not $not$ls180.v:6210$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6179$1885_Y + connect \Y $not$ls180.v:6210$1829_Y end - attribute \src "ls180.v:6197.65-6197.96" - cell $not $not$ls180.v:6197$1893 + attribute \src "ls180.v:6218.70-6218.101" + cell $not $not$ls180.v:6218$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6197$1893_Y + connect \Y $not$ls180.v:6218$1837_Y end - attribute \src "ls180.v:6200.65-6200.96" - cell $not $not$ls180.v:6200$1900 + attribute \src "ls180.v:6221.74-6221.105" + cell $not $not$ls180.v:6221$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6200$1900_Y + connect \Y $not$ls180.v:6221$1844_Y end - attribute \src "ls180.v:6203.63-6203.94" - cell $not $not$ls180.v:6203$1907 + attribute \src "ls180.v:6224.64-6224.95" + cell $not $not$ls180.v:6224$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6203$1907_Y + connect \Y $not$ls180.v:6224$1851_Y end - attribute \src "ls180.v:6206.62-6206.93" - cell $not $not$ls180.v:6206$1914 + attribute \src "ls180.v:6227.74-6227.105" + cell $not $not$ls180.v:6227$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6206$1914_Y + connect \Y $not$ls180.v:6227$1858_Y end - attribute \src "ls180.v:6209.61-6209.92" - cell $not $not$ls180.v:6209$1921 + attribute \src "ls180.v:6230.74-6230.105" + cell $not $not$ls180.v:6230$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6209$1921_Y + connect \Y $not$ls180.v:6230$1865_Y end - attribute \src "ls180.v:6212.60-6212.91" - cell $not $not$ls180.v:6212$1928 + attribute \src "ls180.v:6233.75-6233.106" + cell $not $not$ls180.v:6233$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6212$1928_Y + connect \Y $not$ls180.v:6233$1872_Y end - attribute \src "ls180.v:6215.66-6215.97" - cell $not $not$ls180.v:6215$1935 + attribute \src "ls180.v:6236.73-6236.104" + cell $not $not$ls180.v:6236$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6215$1935_Y + connect \Y $not$ls180.v:6236$1879_Y end - attribute \src "ls180.v:6237.67-6237.99" - cell $not $not$ls180.v:6237$1944 + attribute \src "ls180.v:6239.73-6239.104" + cell $not $not$ls180.v:6239$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6237$1944_Y + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6239$1886_Y end - attribute \src "ls180.v:6240.67-6240.99" - cell $not $not$ls180.v:6240$1951 + attribute \src "ls180.v:6242.73-6242.104" + cell $not $not$ls180.v:6242$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6240$1951_Y + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6242$1893_Y end - attribute \src "ls180.v:6243.65-6243.97" - cell $not $not$ls180.v:6243$1958 + attribute \src "ls180.v:6245.73-6245.104" + cell $not $not$ls180.v:6245$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6245$1900_Y + end + attribute \src "ls180.v:6263.67-6263.99" + cell $not $not$ls180.v:6263$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6243$1958_Y + connect \Y $not$ls180.v:6263$1908_Y end - attribute \src "ls180.v:6246.64-6246.96" - cell $not $not$ls180.v:6246$1965 + attribute \src "ls180.v:6266.67-6266.99" + cell $not $not$ls180.v:6266$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6246$1965_Y + connect \Y $not$ls180.v:6266$1915_Y end - attribute \src "ls180.v:6249.63-6249.95" - cell $not $not$ls180.v:6249$1972 + attribute \src "ls180.v:6269.65-6269.97" + cell $not $not$ls180.v:6269$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6249$1972_Y + connect \Y $not$ls180.v:6269$1922_Y end - attribute \src "ls180.v:6252.62-6252.94" - cell $not $not$ls180.v:6252$1979 + attribute \src "ls180.v:6272.64-6272.96" + cell $not $not$ls180.v:6272$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6252$1979_Y + connect \Y $not$ls180.v:6272$1929_Y end - attribute \src "ls180.v:6255.68-6255.100" - cell $not $not$ls180.v:6255$1986 + attribute \src "ls180.v:6275.63-6275.95" + cell $not $not$ls180.v:6275$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6255$1986_Y + connect \Y $not$ls180.v:6275$1936_Y end - attribute \src "ls180.v:6258.71-6258.103" - cell $not $not$ls180.v:6258$1993 + attribute \src "ls180.v:6278.62-6278.94" + cell $not $not$ls180.v:6278$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6258$1993_Y + connect \Y $not$ls180.v:6278$1943_Y end - attribute \src "ls180.v:6261.71-6261.103" - cell $not $not$ls180.v:6261$2000 + attribute \src "ls180.v:6281.68-6281.100" + cell $not $not$ls180.v:6281$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6261$2000_Y + connect \Y $not$ls180.v:6281$1950_Y end - attribute \src "ls180.v:6285.64-6285.96" - cell $not $not$ls180.v:6285$2009 + attribute \src "ls180.v:6303.67-6303.99" + cell $not $not$ls180.v:6303$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6285$2009_Y + connect \Y $not$ls180.v:6303$1959_Y end - attribute \src "ls180.v:6288.64-6288.96" - cell $not $not$ls180.v:6288$2016 + attribute \src "ls180.v:6306.67-6306.99" + cell $not $not$ls180.v:6306$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6288$2016_Y + connect \Y $not$ls180.v:6306$1966_Y end - attribute \src "ls180.v:6291.64-6291.96" - cell $not $not$ls180.v:6291$2023 + attribute \src "ls180.v:6309.65-6309.97" + cell $not $not$ls180.v:6309$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6291$2023_Y + connect \Y $not$ls180.v:6309$1973_Y end - attribute \src "ls180.v:6294.64-6294.96" - cell $not $not$ls180.v:6294$2030 + attribute \src "ls180.v:6312.64-6312.96" + cell $not $not$ls180.v:6312$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6294$2030_Y + connect \Y $not$ls180.v:6312$1980_Y end - attribute \src "ls180.v:6297.66-6297.98" - cell $not $not$ls180.v:6297$2037 + attribute \src "ls180.v:6315.63-6315.95" + cell $not $not$ls180.v:6315$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6297$2037_Y + connect \Y $not$ls180.v:6315$1987_Y end - attribute \src "ls180.v:6300.66-6300.98" - cell $not $not$ls180.v:6300$2044 + attribute \src "ls180.v:6318.62-6318.94" + cell $not $not$ls180.v:6318$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6300$2044_Y + connect \Y $not$ls180.v:6318$1994_Y end - attribute \src "ls180.v:6303.66-6303.98" - cell $not $not$ls180.v:6303$2051 + attribute \src "ls180.v:6321.68-6321.100" + cell $not $not$ls180.v:6321$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6303$2051_Y + connect \Y $not$ls180.v:6321$2001_Y end - attribute \src "ls180.v:6306.66-6306.98" - cell $not $not$ls180.v:6306$2058 + attribute \src "ls180.v:6324.71-6324.103" + cell $not $not$ls180.v:6324$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6306$2058_Y + connect \Y $not$ls180.v:6324$2008_Y end - attribute \src "ls180.v:6309.62-6309.94" - cell $not $not$ls180.v:6309$2065 + attribute \src "ls180.v:6327.71-6327.103" + cell $not $not$ls180.v:6327$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6309$2065_Y + connect \Y $not$ls180.v:6327$2015_Y end - attribute \src "ls180.v:6312.72-6312.104" - cell $not $not$ls180.v:6312$2072 + attribute \src "ls180.v:6351.64-6351.96" + cell $not $not$ls180.v:6351$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6312$2072_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6351$2024_Y end - attribute \src "ls180.v:6315.65-6315.97" - cell $not $not$ls180.v:6315$2079 + attribute \src "ls180.v:6354.64-6354.96" + cell $not $not$ls180.v:6354$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6315$2079_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6354$2031_Y end - attribute \src "ls180.v:6318.65-6318.97" - cell $not $not$ls180.v:6318$2086 + attribute \src "ls180.v:6357.64-6357.96" + cell $not $not$ls180.v:6357$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6318$2086_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6357$2038_Y end - attribute \src "ls180.v:6321.65-6321.97" - cell $not $not$ls180.v:6321$2093 + attribute \src "ls180.v:6360.64-6360.96" + cell $not $not$ls180.v:6360$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6321$2093_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6360$2045_Y end - attribute \src "ls180.v:6324.65-6324.97" - cell $not $not$ls180.v:6324$2100 + attribute \src "ls180.v:6363.66-6363.98" + cell $not $not$ls180.v:6363$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6324$2100_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6363$2052_Y end - attribute \src "ls180.v:6327.77-6327.109" - cell $not $not$ls180.v:6327$2107 + attribute \src "ls180.v:6366.66-6366.98" + cell $not $not$ls180.v:6366$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6327$2107_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6366$2059_Y end - attribute \src "ls180.v:6330.78-6330.110" - cell $not $not$ls180.v:6330$2114 + attribute \src "ls180.v:6369.66-6369.98" + cell $not $not$ls180.v:6369$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6330$2114_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6369$2066_Y end - attribute \src "ls180.v:6333.69-6333.101" - cell $not $not$ls180.v:6333$2121 + attribute \src "ls180.v:6372.66-6372.98" + cell $not $not$ls180.v:6372$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6333$2121_Y + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6372$2073_Y + end + attribute \src "ls180.v:6375.62-6375.94" + cell $not $not$ls180.v:6375$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6375$2080_Y end - attribute \src "ls180.v:6353.55-6353.87" - cell $not $not$ls180.v:6353$2129 + attribute \src "ls180.v:6378.72-6378.104" + cell $not $not$ls180.v:6378$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6353$2129_Y + connect \Y $not$ls180.v:6378$2087_Y end - attribute \src "ls180.v:6356.65-6356.97" - cell $not $not$ls180.v:6356$2136 + attribute \src "ls180.v:6381.65-6381.97" + cell $not $not$ls180.v:6381$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6356$2136_Y + connect \Y $not$ls180.v:6381$2094_Y end - attribute \src "ls180.v:6359.66-6359.98" - cell $not $not$ls180.v:6359$2143 + attribute \src "ls180.v:6384.65-6384.97" + cell $not $not$ls180.v:6384$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6359$2143_Y + connect \Y $not$ls180.v:6384$2101_Y end - attribute \src "ls180.v:6362.70-6362.102" - cell $not $not$ls180.v:6362$2150 + attribute \src "ls180.v:6387.65-6387.97" + cell $not $not$ls180.v:6387$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6362$2150_Y + connect \Y $not$ls180.v:6387$2108_Y end - attribute \src "ls180.v:6365.71-6365.103" - cell $not $not$ls180.v:6365$2157 + attribute \src "ls180.v:6390.65-6390.97" + cell $not $not$ls180.v:6390$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6365$2157_Y + connect \Y $not$ls180.v:6390$2115_Y end - attribute \src "ls180.v:6368.69-6368.101" - cell $not $not$ls180.v:6368$2164 + attribute \src "ls180.v:6393.77-6393.109" + cell $not $not$ls180.v:6393$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6368$2164_Y + connect \Y $not$ls180.v:6393$2122_Y end - attribute \src "ls180.v:6371.66-6371.98" - cell $not $not$ls180.v:6371$2171 + attribute \src "ls180.v:6396.78-6396.110" + cell $not $not$ls180.v:6396$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6371$2171_Y + connect \Y $not$ls180.v:6396$2129_Y end - attribute \src "ls180.v:6374.65-6374.97" - cell $not $not$ls180.v:6374$2178 + attribute \src "ls180.v:6399.69-6399.101" + cell $not $not$ls180.v:6399$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6374$2178_Y + connect \Y $not$ls180.v:6399$2136_Y + end + attribute \src "ls180.v:6419.55-6419.87" + cell $not $not$ls180.v:6419$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6419$2144_Y + end + attribute \src "ls180.v:6422.65-6422.97" + cell $not $not$ls180.v:6422$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6422$2151_Y + end + attribute \src "ls180.v:6425.66-6425.98" + cell $not $not$ls180.v:6425$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6425$2158_Y + end + attribute \src "ls180.v:6428.70-6428.102" + cell $not $not$ls180.v:6428$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6428$2165_Y end - attribute \src "ls180.v:6387.71-6387.103" - cell $not $not$ls180.v:6387$2186 + attribute \src "ls180.v:6431.71-6431.103" + cell $not $not$ls180.v:6431$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6387$2186_Y + connect \Y $not$ls180.v:6431$2172_Y end - attribute \src "ls180.v:6390.71-6390.103" - cell $not $not$ls180.v:6390$2193 + attribute \src "ls180.v:6434.69-6434.101" + cell $not $not$ls180.v:6434$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6390$2193_Y + connect \Y $not$ls180.v:6434$2179_Y end - attribute \src "ls180.v:6393.71-6393.103" - cell $not $not$ls180.v:6393$2200 + attribute \src "ls180.v:6437.66-6437.98" + cell $not $not$ls180.v:6437$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6393$2200_Y + connect \Y $not$ls180.v:6437$2186_Y end - attribute \src "ls180.v:6396.71-6396.103" - cell $not $not$ls180.v:6396$2207 + attribute \src "ls180.v:6440.65-6440.97" + cell $not $not$ls180.v:6440$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6396$2207_Y + connect \Y $not$ls180.v:6440$2193_Y + end + attribute \src "ls180.v:6453.71-6453.103" + cell $not $not$ls180.v:6453$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6453$2201_Y + end + attribute \src "ls180.v:6456.71-6456.103" + cell $not $not$ls180.v:6456$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6456$2208_Y end - attribute \src "ls180.v:6774.86-6774.330" - cell $not $not$ls180.v:6774$2255 + attribute \src "ls180.v:6459.71-6459.103" + cell $not $not$ls180.v:6459$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6774$2254_Y - connect \Y $not$ls180.v:6774$2255_Y + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6459$2215_Y end - attribute \src "ls180.v:6798.86-6798.330" - cell $not $not$ls180.v:6798$2271 + attribute \src "ls180.v:6462.71-6462.103" + cell $not $not$ls180.v:6462$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6798$2270_Y - connect \Y $not$ls180.v:6798$2271_Y + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6462$2222_Y end - attribute \src "ls180.v:6822.86-6822.330" - cell $not $not$ls180.v:6822$2287 + attribute \src "ls180.v:6843.86-6843.330" + cell $not $not$ls180.v:6843$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6822$2286_Y - connect \Y $not$ls180.v:6822$2287_Y + connect \A $or$ls180.v:6843$2270_Y + connect \Y $not$ls180.v:6843$2271_Y end - attribute \src "ls180.v:6846.86-6846.330" - cell $not $not$ls180.v:6846$2303 + attribute \src "ls180.v:6867.86-6867.330" + cell $not $not$ls180.v:6867$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6846$2302_Y - connect \Y $not$ls180.v:6846$2303_Y + connect \A $or$ls180.v:6867$2286_Y + connect \Y $not$ls180.v:6867$2287_Y end - attribute \src "ls180.v:7344.18-7344.42" - cell $not $not$ls180.v:7344$2356 + attribute \src "ls180.v:6891.86-6891.330" + cell $not $not$ls180.v:6891$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6891$2302_Y + connect \Y $not$ls180.v:6891$2303_Y + end + attribute \src "ls180.v:6915.86-6915.330" + cell $not $not$ls180.v:6915$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6915$2318_Y + connect \Y $not$ls180.v:6915$2319_Y + end + attribute \src "ls180.v:7413.18-7413.42" + cell $not $not$ls180.v:7413$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7344$2356_Y + connect \Y $not$ls180.v:7413$2372_Y end - attribute \src "ls180.v:7441.72-7441.101" - cell $not $not$ls180.v:7441$2407 + attribute \src "ls180.v:7504.72-7504.101" + cell $not $not$ls180.v:7504$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7441$2407_Y + connect \Y $not$ls180.v:7504$2417_Y end - attribute \src "ls180.v:7460.8-7460.38" - cell $not $not$ls180.v:7460$2411 + attribute \src "ls180.v:7523.8-7523.38" + cell $not $not$ls180.v:7523$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7460$2411_Y + connect \Y $not$ls180.v:7523$2421_Y end - attribute \src "ls180.v:7468.32-7468.55" - cell $not $not$ls180.v:7468$2413 + attribute \src "ls180.v:7531.32-7531.55" + cell $not $not$ls180.v:7531$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7468$2413_Y + connect \Y $not$ls180.v:7531$2423_Y end - attribute \src "ls180.v:7538.136-7538.189" - cell $not $not$ls180.v:7538$2428 + attribute \src "ls180.v:7601.136-7601.189" + cell $not $not$ls180.v:7601$2438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7538$2428_Y + connect \Y $not$ls180.v:7601$2438_Y end - attribute \src "ls180.v:7544.136-7544.189" - cell $not $not$ls180.v:7544$2433 + attribute \src "ls180.v:7607.136-7607.189" + cell $not $not$ls180.v:7607$2443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7544$2433_Y + connect \Y $not$ls180.v:7607$2443_Y end - attribute \src "ls180.v:7545.8-7545.61" - cell $not $not$ls180.v:7545$2435 + attribute \src "ls180.v:7608.8-7608.61" + cell $not $not$ls180.v:7608$2445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7545$2435_Y + connect \Y $not$ls180.v:7608$2445_Y end - attribute \src "ls180.v:7553.8-7553.56" - cell $not $not$ls180.v:7553$2438 + attribute \src "ls180.v:7616.8-7616.56" + cell $not $not$ls180.v:7616$2448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7553$2438_Y + connect \Y $not$ls180.v:7616$2448_Y end - attribute \src "ls180.v:7568.8-7568.46" - cell $not $not$ls180.v:7568$2440 + attribute \src "ls180.v:7631.8-7631.46" + cell $not $not$ls180.v:7631$2450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7568$2440_Y + connect \Y $not$ls180.v:7631$2450_Y end - attribute \src "ls180.v:7584.136-7584.189" - cell $not $not$ls180.v:7584$2444 + attribute \src "ls180.v:7647.136-7647.189" + cell $not $not$ls180.v:7647$2454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7584$2444_Y + connect \Y $not$ls180.v:7647$2454_Y end - attribute \src "ls180.v:7590.136-7590.189" - cell $not $not$ls180.v:7590$2449 + attribute \src "ls180.v:7653.136-7653.189" + cell $not $not$ls180.v:7653$2459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7590$2449_Y + connect \Y $not$ls180.v:7653$2459_Y end - attribute \src "ls180.v:7591.8-7591.61" - cell $not $not$ls180.v:7591$2451 + attribute \src "ls180.v:7654.8-7654.61" + cell $not $not$ls180.v:7654$2461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7591$2451_Y + connect \Y $not$ls180.v:7654$2461_Y end - attribute \src "ls180.v:7599.8-7599.56" - cell $not $not$ls180.v:7599$2454 + attribute \src "ls180.v:7662.8-7662.56" + cell $not $not$ls180.v:7662$2464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7599$2454_Y + connect \Y $not$ls180.v:7662$2464_Y end - attribute \src "ls180.v:7614.8-7614.46" - cell $not $not$ls180.v:7614$2456 + attribute \src "ls180.v:7677.8-7677.46" + cell $not $not$ls180.v:7677$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7614$2456_Y + connect \Y $not$ls180.v:7677$2466_Y end - attribute \src "ls180.v:7630.136-7630.189" - cell $not $not$ls180.v:7630$2460 + attribute \src "ls180.v:7693.136-7693.189" + cell $not $not$ls180.v:7693$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7630$2460_Y + connect \Y $not$ls180.v:7693$2470_Y end - attribute \src "ls180.v:7636.136-7636.189" - cell $not $not$ls180.v:7636$2465 + attribute \src "ls180.v:7699.136-7699.189" + cell $not $not$ls180.v:7699$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7636$2465_Y + connect \Y $not$ls180.v:7699$2475_Y end - attribute \src "ls180.v:7637.8-7637.61" - cell $not $not$ls180.v:7637$2467 + attribute \src "ls180.v:7700.8-7700.61" + cell $not $not$ls180.v:7700$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7637$2467_Y + connect \Y $not$ls180.v:7700$2477_Y end - attribute \src "ls180.v:7645.8-7645.56" - cell $not $not$ls180.v:7645$2470 + attribute \src "ls180.v:7708.8-7708.56" + cell $not $not$ls180.v:7708$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7645$2470_Y + connect \Y $not$ls180.v:7708$2480_Y end - attribute \src "ls180.v:7660.8-7660.46" - cell $not $not$ls180.v:7660$2472 + attribute \src "ls180.v:7723.8-7723.46" + cell $not $not$ls180.v:7723$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7660$2472_Y + connect \Y $not$ls180.v:7723$2482_Y end - attribute \src "ls180.v:7676.136-7676.189" - cell $not $not$ls180.v:7676$2476 + attribute \src "ls180.v:7739.136-7739.189" + cell $not $not$ls180.v:7739$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7676$2476_Y + connect \Y $not$ls180.v:7739$2486_Y end - attribute \src "ls180.v:7682.136-7682.189" - cell $not $not$ls180.v:7682$2481 + attribute \src "ls180.v:7745.136-7745.189" + cell $not $not$ls180.v:7745$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7682$2481_Y + connect \Y $not$ls180.v:7745$2491_Y end - attribute \src "ls180.v:7683.8-7683.61" - cell $not $not$ls180.v:7683$2483 + attribute \src "ls180.v:7746.8-7746.61" + cell $not $not$ls180.v:7746$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7683$2483_Y + connect \Y $not$ls180.v:7746$2493_Y end - attribute \src "ls180.v:7691.8-7691.56" - cell $not $not$ls180.v:7691$2486 + attribute \src "ls180.v:7754.8-7754.56" + cell $not $not$ls180.v:7754$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7691$2486_Y + connect \Y $not$ls180.v:7754$2496_Y end - attribute \src "ls180.v:7706.8-7706.46" - cell $not $not$ls180.v:7706$2488 + attribute \src "ls180.v:7769.8-7769.46" + cell $not $not$ls180.v:7769$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7706$2488_Y + connect \Y $not$ls180.v:7769$2498_Y end - attribute \src "ls180.v:7714.7-7714.22" - cell $not $not$ls180.v:7714$2491 + attribute \src "ls180.v:7777.7-7777.22" + cell $not $not$ls180.v:7777$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7714$2491_Y + connect \Y $not$ls180.v:7777$2501_Y end - attribute \src "ls180.v:7717.8-7717.29" - cell $not $not$ls180.v:7717$2492 + attribute \src "ls180.v:7780.8-7780.29" + cell $not $not$ls180.v:7780$2502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7717$2492_Y + connect \Y $not$ls180.v:7780$2502_Y end - attribute \src "ls180.v:7721.7-7721.22" - cell $not $not$ls180.v:7721$2494 + attribute \src "ls180.v:7784.7-7784.22" + cell $not $not$ls180.v:7784$2504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7721$2494_Y + connect \Y $not$ls180.v:7784$2504_Y end - attribute \src "ls180.v:7724.8-7724.29" - cell $not $not$ls180.v:7724$2495 + attribute \src "ls180.v:7787.8-7787.29" + cell $not $not$ls180.v:7787$2505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7724$2495_Y + connect \Y $not$ls180.v:7787$2505_Y end - attribute \src "ls180.v:7843.30-7843.60" - cell $not $not$ls180.v:7843$2497 + attribute \src "ls180.v:7906.30-7906.60" + cell $not $not$ls180.v:7906$2507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7843$2497_Y + connect \Y $not$ls180.v:7906$2507_Y end - attribute \src "ls180.v:7844.30-7844.60" - cell $not $not$ls180.v:7844$2498 + attribute \src "ls180.v:7907.30-7907.60" + cell $not $not$ls180.v:7907$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7844$2498_Y + connect \Y $not$ls180.v:7907$2508_Y end - attribute \src "ls180.v:7845.29-7845.59" - cell $not $not$ls180.v:7845$2499 + attribute \src "ls180.v:7908.29-7908.59" + cell $not $not$ls180.v:7908$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7845$2499_Y + connect \Y $not$ls180.v:7908$2509_Y end - attribute \src "ls180.v:7856.8-7856.33" - cell $not $not$ls180.v:7856$2500 + attribute \src "ls180.v:7919.8-7919.33" + cell $not $not$ls180.v:7919$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7856$2500_Y + connect \Y $not$ls180.v:7919$2510_Y end - attribute \src "ls180.v:7871.8-7871.33" - cell $not $not$ls180.v:7871$2503 + attribute \src "ls180.v:7934.8-7934.33" + cell $not $not$ls180.v:7934$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7871$2503_Y + connect \Y $not$ls180.v:7934$2513_Y end - attribute \src "ls180.v:7907.27-7907.40" - cell $not $not$ls180.v:7907$2533 + attribute \src "ls180.v:7970.36-7970.58" + cell $not $not$ls180.v:7970$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_tx_busy - connect \Y $not$ls180.v:7907$2533_Y + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:7970$2543_Y end - attribute \src "ls180.v:7907.46-7907.62" - cell $not $not$ls180.v:7907$2535 + attribute \src "ls180.v:7970.64-7970.89" + cell $not $not$ls180.v:7970$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sink_ready - connect \Y $not$ls180.v:7907$2535_Y + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:7970$2545_Y end - attribute \src "ls180.v:7936.7-7936.20" - cell $not $not$ls180.v:7936$2542 + attribute \src "ls180.v:7999.7-7999.29" + cell $not $not$ls180.v:7999$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_rx_busy - connect \Y $not$ls180.v:7936$2542_Y + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:7999$2552_Y end - attribute \src "ls180.v:7937.9-7937.17" - cell $not $not$ls180.v:7937$2543 + attribute \src "ls180.v:8000.9-8000.26" + cell $not $not$ls180.v:8000$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_rx - connect \Y $not$ls180.v:7937$2543_Y + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:8000$2553_Y end - attribute \src "ls180.v:7970.8-7970.29" - cell $not $not$ls180.v:7970$2549 + attribute \src "ls180.v:8033.8-8033.29" + cell $not $not$ls180.v:8033$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:7970$2549_Y + connect \Y $not$ls180.v:8033$2559_Y end - attribute \src "ls180.v:7977.8-7977.29" - cell $not $not$ls180.v:7977$2551 + attribute \src "ls180.v:8040.8-8040.29" + cell $not $not$ls180.v:8040$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:7977$2551_Y + connect \Y $not$ls180.v:8040$2561_Y end - attribute \src "ls180.v:7987.80-7987.106" - cell $not $not$ls180.v:7987$2554 + attribute \src "ls180.v:8050.80-8050.106" + cell $not $not$ls180.v:8050$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:7987$2554_Y + connect \Y $not$ls180.v:8050$2564_Y end - attribute \src "ls180.v:7993.80-7993.106" - cell $not $not$ls180.v:7993$2559 + attribute \src "ls180.v:8056.80-8056.106" + cell $not $not$ls180.v:8056$2569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:7993$2559_Y + connect \Y $not$ls180.v:8056$2569_Y end - attribute \src "ls180.v:7994.8-7994.34" - cell $not $not$ls180.v:7994$2561 + attribute \src "ls180.v:8057.8-8057.34" + cell $not $not$ls180.v:8057$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:7994$2561_Y + connect \Y $not$ls180.v:8057$2571_Y end - attribute \src "ls180.v:8009.80-8009.106" - cell $not $not$ls180.v:8009$2565 + attribute \src "ls180.v:8072.80-8072.106" + cell $not $not$ls180.v:8072$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8009$2565_Y + connect \Y $not$ls180.v:8072$2575_Y end - attribute \src "ls180.v:8015.80-8015.106" - cell $not $not$ls180.v:8015$2570 + attribute \src "ls180.v:8078.80-8078.106" + cell $not $not$ls180.v:8078$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8015$2570_Y + connect \Y $not$ls180.v:8078$2580_Y end - attribute \src "ls180.v:8016.8-8016.34" - cell $not $not$ls180.v:8016$2572 + attribute \src "ls180.v:8079.8-8079.34" + cell $not $not$ls180.v:8079$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8016$2572_Y + connect \Y $not$ls180.v:8079$2582_Y + end + attribute \src "ls180.v:8110.22-8110.41" + cell $not $not$ls180.v:8110$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8110$2586_Y + end + attribute \src "ls180.v:8110.46-8110.73" + cell $not $not$ls180.v:8110$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8110$2587_Y end - attribute \src "ls180.v:8047.23-8047.42" - cell $not $not$ls180.v:8047$2576 + attribute \src "ls180.v:8145.22-8145.40" + cell $not $not$ls180.v:8145$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_spi_master_cs - connect \Y $not$ls180.v:8047$2576_Y + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8145$2591_Y end - attribute \src "ls180.v:8047.47-8047.73" - cell $not $not$ls180.v:8047$2577 + attribute \src "ls180.v:8145.45-8145.70" + cell $not $not$ls180.v:8145$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_spi_master_cs_enable - connect \Y $not$ls180.v:8047$2577_Y + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8145$2592_Y end - attribute \src "ls180.v:8101.7-8101.31" - cell $not $not$ls180.v:8101$2588 + attribute \src "ls180.v:8199.7-8199.31" + cell $not $not$ls180.v:8199$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8101$2588_Y + connect \Y $not$ls180.v:8199$2603_Y end - attribute \src "ls180.v:8173.8-8173.46" - cell $not $not$ls180.v:8173$2600 + attribute \src "ls180.v:8271.8-8271.46" + cell $not $not$ls180.v:8271$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8173$2600_Y + connect \Y $not$ls180.v:8271$2615_Y end - attribute \src "ls180.v:8254.8-8254.47" - cell $not $not$ls180.v:8254$2612 + attribute \src "ls180.v:8352.8-8352.47" + cell $not $not$ls180.v:8352$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8254$2612_Y + connect \Y $not$ls180.v:8352$2627_Y end - attribute \src "ls180.v:8315.8-8315.48" - cell $not $not$ls180.v:8315$2624 + attribute \src "ls180.v:8413.8-8413.48" + cell $not $not$ls180.v:8413$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8315$2624_Y + connect \Y $not$ls180.v:8413$2639_Y end - attribute \src "ls180.v:8485.88-8485.118" - cell $not $not$ls180.v:8485$2638 + attribute \src "ls180.v:8583.88-8583.118" + cell $not $not$ls180.v:8583$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8485$2638_Y + connect \Y $not$ls180.v:8583$2653_Y end - attribute \src "ls180.v:8491.88-8491.118" - cell $not $not$ls180.v:8491$2643 + attribute \src "ls180.v:8589.88-8589.118" + cell $not $not$ls180.v:8589$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8491$2643_Y + connect \Y $not$ls180.v:8589$2658_Y end - attribute \src "ls180.v:8492.8-8492.38" - cell $not $not$ls180.v:8492$2645 + attribute \src "ls180.v:8590.8-8590.38" + cell $not $not$ls180.v:8590$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8492$2645_Y + connect \Y $not$ls180.v:8590$2660_Y end - attribute \src "ls180.v:8571.88-8571.118" - cell $not $not$ls180.v:8571$2660 + attribute \src "ls180.v:8669.88-8669.118" + cell $not $not$ls180.v:8669$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8571$2660_Y + connect \Y $not$ls180.v:8669$2675_Y end - attribute \src "ls180.v:8577.88-8577.118" - cell $not $not$ls180.v:8577$2665 + attribute \src "ls180.v:8675.88-8675.118" + cell $not $not$ls180.v:8675$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8577$2665_Y + connect \Y $not$ls180.v:8675$2680_Y end - attribute \src "ls180.v:8578.8-8578.38" - cell $not $not$ls180.v:8578$2667 + attribute \src "ls180.v:8676.8-8676.38" + cell $not $not$ls180.v:8676$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8578$2667_Y - end - attribute \src "ls180.v:8595.22-8595.37" - cell $not $not$ls180.v:8595$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs - connect \Y $not$ls180.v:8595$2671_Y - end - attribute \src "ls180.v:8595.42-8595.64" - cell $not $not$ls180.v:8595$2672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \libresocsim_cs_enable - connect \Y $not$ls180.v:8595$2672_Y + connect \Y $not$ls180.v:8676$2682_Y end - attribute \src "ls180.v:8633.9-8633.28" - cell $not $not$ls180.v:8633$2675 + attribute \src "ls180.v:8696.9-8696.28" + cell $not $not$ls180.v:8696$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8633$2675_Y + connect \Y $not$ls180.v:8696$2685_Y end - attribute \src "ls180.v:8652.9-8652.28" - cell $not $not$ls180.v:8652$2676 + attribute \src "ls180.v:8715.9-8715.28" + cell $not $not$ls180.v:8715$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:8652$2676_Y + connect \Y $not$ls180.v:8715$2686_Y end - attribute \src "ls180.v:8671.9-8671.28" - cell $not $not$ls180.v:8671$2677 + attribute \src "ls180.v:8734.9-8734.28" + cell $not $not$ls180.v:8734$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:8671$2677_Y + connect \Y $not$ls180.v:8734$2687_Y end - attribute \src "ls180.v:8690.9-8690.28" - cell $not $not$ls180.v:8690$2678 + attribute \src "ls180.v:8753.9-8753.28" + cell $not $not$ls180.v:8753$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:8690$2678_Y + connect \Y $not$ls180.v:8753$2688_Y end - attribute \src "ls180.v:8709.9-8709.28" - cell $not $not$ls180.v:8709$2679 + attribute \src "ls180.v:8772.9-8772.28" + cell $not $not$ls180.v:8772$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:8709$2679_Y + connect \Y $not$ls180.v:8772$2689_Y end - attribute \src "ls180.v:8730.8-8730.21" - cell $not $not$ls180.v:8730$2680 + attribute \src "ls180.v:8793.8-8793.21" + cell $not $not$ls180.v:8793$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:8730$2680_Y + connect \Y $not$ls180.v:8793$2690_Y end - attribute \src "ls180.v:10195.8-10195.51" - cell $or $or$ls180.v:10195$2752 + attribute \src "ls180.v:10292.8-10292.51" + cell $or $or$ls180.v:10292$2762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251925,10 +257601,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10195$2752_Y + connect \Y $or$ls180.v:10292$2762_Y end - attribute \src "ls180.v:2767.10-2767.96" - cell $or $or$ls180.v:2767$21 + attribute \src "ls180.v:2815.10-2815.96" + cell $or $or$ls180.v:2815$21 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251936,10 +257612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_ack connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2767$21_Y + connect \Y $or$ls180.v:2815$21_Y end - attribute \src "ls180.v:2827.10-2827.96" - cell $or $or$ls180.v:2827$32 + attribute \src "ls180.v:2875.10-2875.96" + cell $or $or$ls180.v:2875$32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251947,10 +257623,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_ack connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2827$32_Y + connect \Y $or$ls180.v:2875$32_Y end - attribute \src "ls180.v:2887.10-2887.96" - cell $or $or$ls180.v:2887$43 + attribute \src "ls180.v:2935.10-2935.96" + cell $or $or$ls180.v:2935$43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251958,21 +257634,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_ack connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2887$43_Y + connect \Y $or$ls180.v:2935$43_Y end - attribute \src "ls180.v:3079.39-3079.105" - cell $or $or$ls180.v:3079$75 + attribute \src "ls180.v:3127.39-3127.105" + cell $or $or$ls180.v:3127$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3079$74_Y - connect \Y $or$ls180.v:3079$75_Y + connect \B $ne$ls180.v:3127$74_Y + connect \Y $or$ls180.v:3127$75_Y end - attribute \src "ls180.v:3122.59-3122.140" - cell $or $or$ls180.v:3122$79 + attribute \src "ls180.v:3170.59-3170.140" + cell $or $or$ls180.v:3170$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251980,10 +257656,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3122$79_Y + connect \Y $or$ls180.v:3170$79_Y end - attribute \src "ls180.v:3123.44-3123.151" - cell $or $or$ls180.v:3123$80 + attribute \src "ls180.v:3171.44-3171.151" + cell $or $or$ls180.v:3171$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -251991,21 +257667,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3123$80_Y + connect \Y $or$ls180.v:3171$80_Y end - attribute \src "ls180.v:3131.45-3131.170" - cell $or $or$ls180.v:3131$84 + attribute \src "ls180.v:3179.45-3179.170" + cell $or $or$ls180.v:3179$84 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3131$83_Y + connect \A $sshl$ls180.v:3179$83_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3131$84_Y + connect \Y $or$ls180.v:3179$84_Y end - attribute \src "ls180.v:3168.127-3168.245" - cell $or $or$ls180.v:3168$97 + attribute \src "ls180.v:3216.127-3216.245" + cell $or $or$ls180.v:3216$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252013,21 +257689,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3168$97_Y + connect \Y $or$ls180.v:3216$97_Y end - attribute \src "ls180.v:3174.57-3174.157" - cell $or $or$ls180.v:3174$103 + attribute \src "ls180.v:3222.57-3222.157" + cell $or $or$ls180.v:3222$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3174$102_Y + connect \A $not$ls180.v:3222$102_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3174$103_Y + connect \Y $or$ls180.v:3222$103_Y end - attribute \src "ls180.v:3279.59-3279.140" - cell $or $or$ls180.v:3279$109 + attribute \src "ls180.v:3327.59-3327.140" + cell $or $or$ls180.v:3327$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252035,10 +257711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3279$109_Y + connect \Y $or$ls180.v:3327$109_Y end - attribute \src "ls180.v:3280.44-3280.151" - cell $or $or$ls180.v:3280$110 + attribute \src "ls180.v:3328.44-3328.151" + cell $or $or$ls180.v:3328$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252046,21 +257722,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3280$110_Y + connect \Y $or$ls180.v:3328$110_Y end - attribute \src "ls180.v:3288.45-3288.170" - cell $or $or$ls180.v:3288$114 + attribute \src "ls180.v:3336.45-3336.170" + cell $or $or$ls180.v:3336$114 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3288$113_Y + connect \A $sshl$ls180.v:3336$113_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3288$114_Y + connect \Y $or$ls180.v:3336$114_Y end - attribute \src "ls180.v:3325.127-3325.245" - cell $or $or$ls180.v:3325$127 + attribute \src "ls180.v:3373.127-3373.245" + cell $or $or$ls180.v:3373$127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252068,21 +257744,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3325$127_Y + connect \Y $or$ls180.v:3373$127_Y end - attribute \src "ls180.v:3331.57-3331.157" - cell $or $or$ls180.v:3331$133 + attribute \src "ls180.v:3379.57-3379.157" + cell $or $or$ls180.v:3379$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3331$132_Y + connect \A $not$ls180.v:3379$132_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3331$133_Y + connect \Y $or$ls180.v:3379$133_Y end - attribute \src "ls180.v:3436.59-3436.140" - cell $or $or$ls180.v:3436$139 + attribute \src "ls180.v:3484.59-3484.140" + cell $or $or$ls180.v:3484$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252090,10 +257766,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3436$139_Y + connect \Y $or$ls180.v:3484$139_Y end - attribute \src "ls180.v:3437.44-3437.151" - cell $or $or$ls180.v:3437$140 + attribute \src "ls180.v:3485.44-3485.151" + cell $or $or$ls180.v:3485$140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252101,21 +257777,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3437$140_Y + connect \Y $or$ls180.v:3485$140_Y end - attribute \src "ls180.v:3445.45-3445.170" - cell $or $or$ls180.v:3445$144 + attribute \src "ls180.v:3493.45-3493.170" + cell $or $or$ls180.v:3493$144 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3445$143_Y + connect \A $sshl$ls180.v:3493$143_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3445$144_Y + connect \Y $or$ls180.v:3493$144_Y end - attribute \src "ls180.v:3482.127-3482.245" - cell $or $or$ls180.v:3482$157 + attribute \src "ls180.v:3530.127-3530.245" + cell $or $or$ls180.v:3530$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252123,21 +257799,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3482$157_Y + connect \Y $or$ls180.v:3530$157_Y end - attribute \src "ls180.v:3488.57-3488.157" - cell $or $or$ls180.v:3488$163 + attribute \src "ls180.v:3536.57-3536.157" + cell $or $or$ls180.v:3536$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3488$162_Y + connect \A $not$ls180.v:3536$162_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3488$163_Y + connect \Y $or$ls180.v:3536$163_Y end - attribute \src "ls180.v:3593.59-3593.140" - cell $or $or$ls180.v:3593$169 + attribute \src "ls180.v:3641.59-3641.140" + cell $or $or$ls180.v:3641$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252145,10 +257821,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3593$169_Y + connect \Y $or$ls180.v:3641$169_Y end - attribute \src "ls180.v:3594.44-3594.151" - cell $or $or$ls180.v:3594$170 + attribute \src "ls180.v:3642.44-3642.151" + cell $or $or$ls180.v:3642$170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252156,21 +257832,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3594$170_Y + connect \Y $or$ls180.v:3642$170_Y end - attribute \src "ls180.v:3602.45-3602.170" - cell $or $or$ls180.v:3602$174 + attribute \src "ls180.v:3650.45-3650.170" + cell $or $or$ls180.v:3650$174 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3602$173_Y + connect \A $sshl$ls180.v:3650$173_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3602$174_Y + connect \Y $or$ls180.v:3650$174_Y end - attribute \src "ls180.v:3639.127-3639.245" - cell $or $or$ls180.v:3639$187 + attribute \src "ls180.v:3687.127-3687.245" + cell $or $or$ls180.v:3687$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252178,21 +257854,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3639$187_Y + connect \Y $or$ls180.v:3687$187_Y end - attribute \src "ls180.v:3645.57-3645.157" - cell $or $or$ls180.v:3645$193 + attribute \src "ls180.v:3693.57-3693.157" + cell $or $or$ls180.v:3693$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3645$192_Y + connect \A $not$ls180.v:3693$192_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3645$193_Y + connect \Y $or$ls180.v:3693$193_Y end - attribute \src "ls180.v:3744.107-3744.193" - cell $or $or$ls180.v:3744$213 + attribute \src "ls180.v:3792.107-3792.193" + cell $or $or$ls180.v:3792$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252200,626 +257876,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3744$213_Y + connect \Y $or$ls180.v:3792$213_Y end - attribute \src "ls180.v:3747.39-3747.204" - cell $or $or$ls180.v:3747$219 + attribute \src "ls180.v:3795.39-3795.204" + cell $or $or$ls180.v:3795$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3747$217_Y - connect \B $and$ls180.v:3747$218_Y - connect \Y $or$ls180.v:3747$219_Y + connect \A $and$ls180.v:3795$217_Y + connect \B $and$ls180.v:3795$218_Y + connect \Y $or$ls180.v:3795$219_Y end - attribute \src "ls180.v:3747.38-3747.289" - cell $or $or$ls180.v:3747$221 + attribute \src "ls180.v:3795.38-3795.289" + cell $or $or$ls180.v:3795$221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3747$219_Y - connect \B $and$ls180.v:3747$220_Y - connect \Y $or$ls180.v:3747$221_Y + connect \A $or$ls180.v:3795$219_Y + connect \B $and$ls180.v:3795$220_Y + connect \Y $or$ls180.v:3795$221_Y end - attribute \src "ls180.v:3747.37-3747.374" - cell $or $or$ls180.v:3747$223 + attribute \src "ls180.v:3795.37-3795.374" + cell $or $or$ls180.v:3795$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3747$221_Y - connect \B $and$ls180.v:3747$222_Y - connect \Y $or$ls180.v:3747$223_Y + connect \A $or$ls180.v:3795$221_Y + connect \B $and$ls180.v:3795$222_Y + connect \Y $or$ls180.v:3795$223_Y end - attribute \src "ls180.v:3748.40-3748.207" - cell $or $or$ls180.v:3748$226 + attribute \src "ls180.v:3796.40-3796.207" + cell $or $or$ls180.v:3796$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3748$224_Y - connect \B $and$ls180.v:3748$225_Y - connect \Y $or$ls180.v:3748$226_Y + connect \A $and$ls180.v:3796$224_Y + connect \B $and$ls180.v:3796$225_Y + connect \Y $or$ls180.v:3796$226_Y end - attribute \src "ls180.v:3748.39-3748.293" - cell $or $or$ls180.v:3748$228 + attribute \src "ls180.v:3796.39-3796.293" + cell $or $or$ls180.v:3796$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3748$226_Y - connect \B $and$ls180.v:3748$227_Y - connect \Y $or$ls180.v:3748$228_Y + connect \A $or$ls180.v:3796$226_Y + connect \B $and$ls180.v:3796$227_Y + connect \Y $or$ls180.v:3796$228_Y end - attribute \src "ls180.v:3748.38-3748.379" - cell $or $or$ls180.v:3748$230 + attribute \src "ls180.v:3796.38-3796.379" + cell $or $or$ls180.v:3796$230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3748$228_Y - connect \B $and$ls180.v:3748$229_Y - connect \Y $or$ls180.v:3748$230_Y + connect \A $or$ls180.v:3796$228_Y + connect \B $and$ls180.v:3796$229_Y + connect \Y $or$ls180.v:3796$230_Y end - attribute \src "ls180.v:3761.158-3761.332" - cell $or $or$ls180.v:3761$244 + attribute \src "ls180.v:3809.158-3809.332" + cell $or $or$ls180.v:3809$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3761$243_Y + connect \A $not$ls180.v:3809$243_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3761$244_Y + connect \Y $or$ls180.v:3809$244_Y end - attribute \src "ls180.v:3761.75-3761.506" - cell $or $or$ls180.v:3761$249 + attribute \src "ls180.v:3809.75-3809.506" + cell $or $or$ls180.v:3809$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3761$245_Y - connect \B $and$ls180.v:3761$248_Y - connect \Y $or$ls180.v:3761$249_Y + connect \A $and$ls180.v:3809$245_Y + connect \B $and$ls180.v:3809$248_Y + connect \Y $or$ls180.v:3809$249_Y end - attribute \src "ls180.v:3762.158-3762.332" - cell $or $or$ls180.v:3762$257 + attribute \src "ls180.v:3810.158-3810.332" + cell $or $or$ls180.v:3810$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3762$256_Y + connect \A $not$ls180.v:3810$256_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3762$257_Y + connect \Y $or$ls180.v:3810$257_Y end - attribute \src "ls180.v:3762.75-3762.506" - cell $or $or$ls180.v:3762$262 + attribute \src "ls180.v:3810.75-3810.506" + cell $or $or$ls180.v:3810$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3762$258_Y - connect \B $and$ls180.v:3762$261_Y - connect \Y $or$ls180.v:3762$262_Y + connect \A $and$ls180.v:3810$258_Y + connect \B $and$ls180.v:3810$261_Y + connect \Y $or$ls180.v:3810$262_Y end - attribute \src "ls180.v:3763.158-3763.332" - cell $or $or$ls180.v:3763$270 + attribute \src "ls180.v:3811.158-3811.332" + cell $or $or$ls180.v:3811$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3763$269_Y + connect \A $not$ls180.v:3811$269_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3763$270_Y + connect \Y $or$ls180.v:3811$270_Y end - attribute \src "ls180.v:3763.75-3763.506" - cell $or $or$ls180.v:3763$275 + attribute \src "ls180.v:3811.75-3811.506" + cell $or $or$ls180.v:3811$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3763$271_Y - connect \B $and$ls180.v:3763$274_Y - connect \Y $or$ls180.v:3763$275_Y + connect \A $and$ls180.v:3811$271_Y + connect \B $and$ls180.v:3811$274_Y + connect \Y $or$ls180.v:3811$275_Y end - attribute \src "ls180.v:3764.158-3764.332" - cell $or $or$ls180.v:3764$283 + attribute \src "ls180.v:3812.158-3812.332" + cell $or $or$ls180.v:3812$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3764$282_Y + connect \A $not$ls180.v:3812$282_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3764$283_Y + connect \Y $or$ls180.v:3812$283_Y end - attribute \src "ls180.v:3764.75-3764.506" - cell $or $or$ls180.v:3764$288 + attribute \src "ls180.v:3812.75-3812.506" + cell $or $or$ls180.v:3812$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3764$284_Y - connect \B $and$ls180.v:3764$287_Y - connect \Y $or$ls180.v:3764$288_Y + connect \A $and$ls180.v:3812$284_Y + connect \B $and$ls180.v:3812$287_Y + connect \Y $or$ls180.v:3812$288_Y end - attribute \src "ls180.v:3791.36-3791.104" - cell $or $or$ls180.v:3791$294 + attribute \src "ls180.v:3839.36-3839.104" + cell $or $or$ls180.v:3839$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3791$293_Y - connect \Y $or$ls180.v:3791$294_Y + connect \B $not$ls180.v:3839$293_Y + connect \Y $or$ls180.v:3839$294_Y end - attribute \src "ls180.v:3794.158-3794.332" - cell $or $or$ls180.v:3794$302 + attribute \src "ls180.v:3842.158-3842.332" + cell $or $or$ls180.v:3842$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3794$301_Y + connect \A $not$ls180.v:3842$301_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3794$302_Y + connect \Y $or$ls180.v:3842$302_Y end - attribute \src "ls180.v:3794.75-3794.506" - cell $or $or$ls180.v:3794$307 + attribute \src "ls180.v:3842.75-3842.506" + cell $or $or$ls180.v:3842$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$303_Y - connect \B $and$ls180.v:3794$306_Y - connect \Y $or$ls180.v:3794$307_Y + connect \A $and$ls180.v:3842$303_Y + connect \B $and$ls180.v:3842$306_Y + connect \Y $or$ls180.v:3842$307_Y end - attribute \src "ls180.v:3795.158-3795.332" - cell $or $or$ls180.v:3795$315 + attribute \src "ls180.v:3843.158-3843.332" + cell $or $or$ls180.v:3843$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3795$314_Y + connect \A $not$ls180.v:3843$314_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3795$315_Y + connect \Y $or$ls180.v:3843$315_Y end - attribute \src "ls180.v:3795.75-3795.506" - cell $or $or$ls180.v:3795$320 + attribute \src "ls180.v:3843.75-3843.506" + cell $or $or$ls180.v:3843$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$316_Y - connect \B $and$ls180.v:3795$319_Y - connect \Y $or$ls180.v:3795$320_Y + connect \A $and$ls180.v:3843$316_Y + connect \B $and$ls180.v:3843$319_Y + connect \Y $or$ls180.v:3843$320_Y end - attribute \src "ls180.v:3796.158-3796.332" - cell $or $or$ls180.v:3796$328 + attribute \src "ls180.v:3844.158-3844.332" + cell $or $or$ls180.v:3844$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3796$327_Y + connect \A $not$ls180.v:3844$327_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3796$328_Y + connect \Y $or$ls180.v:3844$328_Y end - attribute \src "ls180.v:3796.75-3796.506" - cell $or $or$ls180.v:3796$333 + attribute \src "ls180.v:3844.75-3844.506" + cell $or $or$ls180.v:3844$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3796$329_Y - connect \B $and$ls180.v:3796$332_Y - connect \Y $or$ls180.v:3796$333_Y + connect \A $and$ls180.v:3844$329_Y + connect \B $and$ls180.v:3844$332_Y + connect \Y $or$ls180.v:3844$333_Y end - attribute \src "ls180.v:3797.158-3797.332" - cell $or $or$ls180.v:3797$341 + attribute \src "ls180.v:3845.158-3845.332" + cell $or $or$ls180.v:3845$341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3797$340_Y + connect \A $not$ls180.v:3845$340_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3797$341_Y + connect \Y $or$ls180.v:3845$341_Y end - attribute \src "ls180.v:3797.75-3797.506" - cell $or $or$ls180.v:3797$346 + attribute \src "ls180.v:3845.75-3845.506" + cell $or $or$ls180.v:3845$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3797$342_Y - connect \B $and$ls180.v:3797$345_Y - connect \Y $or$ls180.v:3797$346_Y + connect \A $and$ls180.v:3845$342_Y + connect \B $and$ls180.v:3845$345_Y + connect \Y $or$ls180.v:3845$346_Y end - attribute \src "ls180.v:3860.36-3860.104" - cell $or $or$ls180.v:3860$380 + attribute \src "ls180.v:3908.36-3908.104" + cell $or $or$ls180.v:3908$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3860$379_Y - connect \Y $or$ls180.v:3860$380_Y + connect \B $not$ls180.v:3908$379_Y + connect \Y $or$ls180.v:3908$380_Y end - attribute \src "ls180.v:3881.67-3881.221" - cell $or $or$ls180.v:3881$387 + attribute \src "ls180.v:3929.67-3929.221" + cell $or $or$ls180.v:3929$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3881$386_Y + connect \A $not$ls180.v:3929$386_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3881$387_Y + connect \Y $or$ls180.v:3929$387_Y end - attribute \src "ls180.v:3889.10-3889.62" - cell $or $or$ls180.v:3889$390 + attribute \src "ls180.v:3937.10-3937.62" + cell $or $or$ls180.v:3937$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3889$389_Y + connect \A $not$ls180.v:3937$389_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3889$390_Y + connect \Y $or$ls180.v:3937$390_Y end - attribute \src "ls180.v:3919.67-3919.221" - cell $or $or$ls180.v:3919$396 + attribute \src "ls180.v:3967.67-3967.221" + cell $or $or$ls180.v:3967$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3919$395_Y + connect \A $not$ls180.v:3967$395_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3919$396_Y + connect \Y $or$ls180.v:3967$396_Y end - attribute \src "ls180.v:3927.10-3927.61" - cell $or $or$ls180.v:3927$399 + attribute \src "ls180.v:3975.10-3975.61" + cell $or $or$ls180.v:3975$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3927$398_Y + connect \A $not$ls180.v:3975$398_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3927$399_Y + connect \Y $or$ls180.v:3975$399_Y end - attribute \src "ls180.v:3937.91-3937.180" - cell $or $or$ls180.v:3937$403 + attribute \src "ls180.v:3985.91-3985.180" + cell $or $or$ls180.v:3985$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:3937$402_Y - connect \Y $or$ls180.v:3937$403_Y + connect \B $and$ls180.v:3985$402_Y + connect \Y $or$ls180.v:3985$403_Y end - attribute \src "ls180.v:3937.90-3937.255" - cell $or $or$ls180.v:3937$406 + attribute \src "ls180.v:3985.90-3985.255" + cell $or $or$ls180.v:3985$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3937$403_Y - connect \B $and$ls180.v:3937$405_Y - connect \Y $or$ls180.v:3937$406_Y + connect \A $or$ls180.v:3985$403_Y + connect \B $and$ls180.v:3985$405_Y + connect \Y $or$ls180.v:3985$406_Y end - attribute \src "ls180.v:3937.89-3937.330" - cell $or $or$ls180.v:3937$409 + attribute \src "ls180.v:3985.89-3985.330" + cell $or $or$ls180.v:3985$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3937$406_Y - connect \B $and$ls180.v:3937$408_Y - connect \Y $or$ls180.v:3937$409_Y + connect \A $or$ls180.v:3985$406_Y + connect \B $and$ls180.v:3985$408_Y + connect \Y $or$ls180.v:3985$409_Y end - attribute \src "ls180.v:3942.91-3942.180" - cell $or $or$ls180.v:3942$419 + attribute \src "ls180.v:3990.91-3990.180" + cell $or $or$ls180.v:3990$419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:3942$418_Y - connect \Y $or$ls180.v:3942$419_Y + connect \B $and$ls180.v:3990$418_Y + connect \Y $or$ls180.v:3990$419_Y end - attribute \src "ls180.v:3942.90-3942.255" - cell $or $or$ls180.v:3942$422 + attribute \src "ls180.v:3990.90-3990.255" + cell $or $or$ls180.v:3990$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3942$419_Y - connect \B $and$ls180.v:3942$421_Y - connect \Y $or$ls180.v:3942$422_Y + connect \A $or$ls180.v:3990$419_Y + connect \B $and$ls180.v:3990$421_Y + connect \Y $or$ls180.v:3990$422_Y end - attribute \src "ls180.v:3942.89-3942.330" - cell $or $or$ls180.v:3942$425 + attribute \src "ls180.v:3990.89-3990.330" + cell $or $or$ls180.v:3990$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3942$422_Y - connect \B $and$ls180.v:3942$424_Y - connect \Y $or$ls180.v:3942$425_Y + connect \A $or$ls180.v:3990$422_Y + connect \B $and$ls180.v:3990$424_Y + connect \Y $or$ls180.v:3990$425_Y end - attribute \src "ls180.v:3947.91-3947.180" - cell $or $or$ls180.v:3947$435 + attribute \src "ls180.v:3995.91-3995.180" + cell $or $or$ls180.v:3995$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:3947$434_Y - connect \Y $or$ls180.v:3947$435_Y + connect \B $and$ls180.v:3995$434_Y + connect \Y $or$ls180.v:3995$435_Y end - attribute \src "ls180.v:3947.90-3947.255" - cell $or $or$ls180.v:3947$438 + attribute \src "ls180.v:3995.90-3995.255" + cell $or $or$ls180.v:3995$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3947$435_Y - connect \B $and$ls180.v:3947$437_Y - connect \Y $or$ls180.v:3947$438_Y + connect \A $or$ls180.v:3995$435_Y + connect \B $and$ls180.v:3995$437_Y + connect \Y $or$ls180.v:3995$438_Y end - attribute \src "ls180.v:3947.89-3947.330" - cell $or $or$ls180.v:3947$441 + attribute \src "ls180.v:3995.89-3995.330" + cell $or $or$ls180.v:3995$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3947$438_Y - connect \B $and$ls180.v:3947$440_Y - connect \Y $or$ls180.v:3947$441_Y + connect \A $or$ls180.v:3995$438_Y + connect \B $and$ls180.v:3995$440_Y + connect \Y $or$ls180.v:3995$441_Y end - attribute \src "ls180.v:3952.91-3952.180" - cell $or $or$ls180.v:3952$451 + attribute \src "ls180.v:4000.91-4000.180" + cell $or $or$ls180.v:4000$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:3952$450_Y - connect \Y $or$ls180.v:3952$451_Y + connect \B $and$ls180.v:4000$450_Y + connect \Y $or$ls180.v:4000$451_Y end - attribute \src "ls180.v:3952.90-3952.255" - cell $or $or$ls180.v:3952$454 + attribute \src "ls180.v:4000.90-4000.255" + cell $or $or$ls180.v:4000$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3952$451_Y - connect \B $and$ls180.v:3952$453_Y - connect \Y $or$ls180.v:3952$454_Y + connect \A $or$ls180.v:4000$451_Y + connect \B $and$ls180.v:4000$453_Y + connect \Y $or$ls180.v:4000$454_Y end - attribute \src "ls180.v:3952.89-3952.330" - cell $or $or$ls180.v:3952$457 + attribute \src "ls180.v:4000.89-4000.330" + cell $or $or$ls180.v:4000$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3952$454_Y - connect \B $and$ls180.v:3952$456_Y - connect \Y $or$ls180.v:3952$457_Y + connect \A $or$ls180.v:4000$454_Y + connect \B $and$ls180.v:4000$456_Y + connect \Y $or$ls180.v:4000$457_Y end - attribute \src "ls180.v:3957.132-3957.221" - cell $or $or$ls180.v:3957$468 + attribute \src "ls180.v:4005.132-4005.221" + cell $or $or$ls180.v:4005$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:3957$467_Y - connect \Y $or$ls180.v:3957$468_Y + connect \B $and$ls180.v:4005$467_Y + connect \Y $or$ls180.v:4005$468_Y end - attribute \src "ls180.v:3957.131-3957.296" - cell $or $or$ls180.v:3957$471 + attribute \src "ls180.v:4005.131-4005.296" + cell $or $or$ls180.v:4005$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$468_Y - connect \B $and$ls180.v:3957$470_Y - connect \Y $or$ls180.v:3957$471_Y + connect \A $or$ls180.v:4005$468_Y + connect \B $and$ls180.v:4005$470_Y + connect \Y $or$ls180.v:4005$471_Y end - attribute \src "ls180.v:3957.130-3957.371" - cell $or $or$ls180.v:3957$474 + attribute \src "ls180.v:4005.130-4005.371" + cell $or $or$ls180.v:4005$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$471_Y - connect \B $and$ls180.v:3957$473_Y - connect \Y $or$ls180.v:3957$474_Y + connect \A $or$ls180.v:4005$471_Y + connect \B $and$ls180.v:4005$473_Y + connect \Y $or$ls180.v:4005$474_Y end - attribute \src "ls180.v:3957.34-3957.411" - cell $or $or$ls180.v:3957$479 + attribute \src "ls180.v:4005.34-4005.411" + cell $or $or$ls180.v:4005$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:3957$478_Y - connect \Y $or$ls180.v:3957$479_Y + connect \B $and$ls180.v:4005$478_Y + connect \Y $or$ls180.v:4005$479_Y end - attribute \src "ls180.v:3957.506-3957.595" - cell $or $or$ls180.v:3957$484 + attribute \src "ls180.v:4005.506-4005.595" + cell $or $or$ls180.v:4005$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:3957$483_Y - connect \Y $or$ls180.v:3957$484_Y + connect \B $and$ls180.v:4005$483_Y + connect \Y $or$ls180.v:4005$484_Y end - attribute \src "ls180.v:3957.505-3957.670" - cell $or $or$ls180.v:3957$487 + attribute \src "ls180.v:4005.505-4005.670" + cell $or $or$ls180.v:4005$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$484_Y - connect \B $and$ls180.v:3957$486_Y - connect \Y $or$ls180.v:3957$487_Y + connect \A $or$ls180.v:4005$484_Y + connect \B $and$ls180.v:4005$486_Y + connect \Y $or$ls180.v:4005$487_Y end - attribute \src "ls180.v:3957.504-3957.745" - cell $or $or$ls180.v:3957$490 + attribute \src "ls180.v:4005.504-4005.745" + cell $or $or$ls180.v:4005$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$487_Y - connect \B $and$ls180.v:3957$489_Y - connect \Y $or$ls180.v:3957$490_Y + connect \A $or$ls180.v:4005$487_Y + connect \B $and$ls180.v:4005$489_Y + connect \Y $or$ls180.v:4005$490_Y end - attribute \src "ls180.v:3957.33-3957.785" - cell $or $or$ls180.v:3957$495 + attribute \src "ls180.v:4005.33-4005.785" + cell $or $or$ls180.v:4005$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$479_Y - connect \B $and$ls180.v:3957$494_Y - connect \Y $or$ls180.v:3957$495_Y + connect \A $or$ls180.v:4005$479_Y + connect \B $and$ls180.v:4005$494_Y + connect \Y $or$ls180.v:4005$495_Y end - attribute \src "ls180.v:3957.880-3957.969" - cell $or $or$ls180.v:3957$500 + attribute \src "ls180.v:4005.880-4005.969" + cell $or $or$ls180.v:4005$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:3957$499_Y - connect \Y $or$ls180.v:3957$500_Y + connect \B $and$ls180.v:4005$499_Y + connect \Y $or$ls180.v:4005$500_Y end - attribute \src "ls180.v:3957.879-3957.1044" - cell $or $or$ls180.v:3957$503 + attribute \src "ls180.v:4005.879-4005.1044" + cell $or $or$ls180.v:4005$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$500_Y - connect \B $and$ls180.v:3957$502_Y - connect \Y $or$ls180.v:3957$503_Y + connect \A $or$ls180.v:4005$500_Y + connect \B $and$ls180.v:4005$502_Y + connect \Y $or$ls180.v:4005$503_Y end - attribute \src "ls180.v:3957.878-3957.1119" - cell $or $or$ls180.v:3957$506 + attribute \src "ls180.v:4005.878-4005.1119" + cell $or $or$ls180.v:4005$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$503_Y - connect \B $and$ls180.v:3957$505_Y - connect \Y $or$ls180.v:3957$506_Y + connect \A $or$ls180.v:4005$503_Y + connect \B $and$ls180.v:4005$505_Y + connect \Y $or$ls180.v:4005$506_Y end - attribute \src "ls180.v:3957.32-3957.1159" - cell $or $or$ls180.v:3957$511 + attribute \src "ls180.v:4005.32-4005.1159" + cell $or $or$ls180.v:4005$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$495_Y - connect \B $and$ls180.v:3957$510_Y - connect \Y $or$ls180.v:3957$511_Y + connect \A $or$ls180.v:4005$495_Y + connect \B $and$ls180.v:4005$510_Y + connect \Y $or$ls180.v:4005$511_Y end - attribute \src "ls180.v:3957.1254-3957.1343" - cell $or $or$ls180.v:3957$516 + attribute \src "ls180.v:4005.1254-4005.1343" + cell $or $or$ls180.v:4005$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:3957$515_Y - connect \Y $or$ls180.v:3957$516_Y + connect \B $and$ls180.v:4005$515_Y + connect \Y $or$ls180.v:4005$516_Y end - attribute \src "ls180.v:3957.1253-3957.1418" - cell $or $or$ls180.v:3957$519 + attribute \src "ls180.v:4005.1253-4005.1418" + cell $or $or$ls180.v:4005$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$516_Y - connect \B $and$ls180.v:3957$518_Y - connect \Y $or$ls180.v:3957$519_Y + connect \A $or$ls180.v:4005$516_Y + connect \B $and$ls180.v:4005$518_Y + connect \Y $or$ls180.v:4005$519_Y end - attribute \src "ls180.v:3957.1252-3957.1493" - cell $or $or$ls180.v:3957$522 + attribute \src "ls180.v:4005.1252-4005.1493" + cell $or $or$ls180.v:4005$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$519_Y - connect \B $and$ls180.v:3957$521_Y - connect \Y $or$ls180.v:3957$522_Y + connect \A $or$ls180.v:4005$519_Y + connect \B $and$ls180.v:4005$521_Y + connect \Y $or$ls180.v:4005$522_Y end - attribute \src "ls180.v:3957.31-3957.1533" - cell $or $or$ls180.v:3957$527 + attribute \src "ls180.v:4005.31-4005.1533" + cell $or $or$ls180.v:4005$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3957$511_Y - connect \B $and$ls180.v:3957$526_Y - connect \Y $or$ls180.v:3957$527_Y + connect \A $or$ls180.v:4005$511_Y + connect \B $and$ls180.v:4005$526_Y + connect \Y $or$ls180.v:4005$527_Y end - attribute \src "ls180.v:4020.10-4020.52" - cell $or $or$ls180.v:4020$536 + attribute \src "ls180.v:4068.10-4068.52" + cell $or $or$ls180.v:4068$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252827,10 +258503,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4020$536_Y + connect \Y $or$ls180.v:4068$536_Y end - attribute \src "ls180.v:4047.35-4047.74" - cell $or $or$ls180.v:4047$546 + attribute \src "ls180.v:4095.35-4095.74" + cell $or $or$ls180.v:4095$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252838,10 +258514,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4047$546_Y + connect \Y $or$ls180.v:4095$546_Y end - attribute \src "ls180.v:4048.34-4048.73" - cell $or $or$ls180.v:4048$550 + attribute \src "ls180.v:4096.34-4096.73" + cell $or $or$ls180.v:4096$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252849,76 +258525,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4048$550_Y + connect \Y $or$ls180.v:4096$550_Y end - attribute \src "ls180.v:4049.48-4049.130" - cell $or $or$ls180.v:4049$556 + attribute \src "ls180.v:4097.48-4097.130" + cell $or $or$ls180.v:4097$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4049$553_Y - connect \B $and$ls180.v:4049$555_Y - connect \Y $or$ls180.v:4049$556_Y + connect \A $and$ls180.v:4097$553_Y + connect \B $and$ls180.v:4097$555_Y + connect \Y $or$ls180.v:4097$556_Y end - attribute \src "ls180.v:4050.24-4050.87" - cell $or $or$ls180.v:4050$559 + attribute \src "ls180.v:4098.24-4098.87" + cell $or $or$ls180.v:4098$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4050$558_Y + connect \A $and$ls180.v:4098$558_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4050$559_Y + connect \Y $or$ls180.v:4098$559_Y end - attribute \src "ls180.v:4051.26-4051.95" - cell $or $or$ls180.v:4051$561 + attribute \src "ls180.v:4099.26-4099.95" + cell $or $or$ls180.v:4099$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4051$560_Y + connect \A $and$ls180.v:4099$560_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4051$561_Y + connect \Y $or$ls180.v:4099$561_Y end - attribute \src "ls180.v:4081.42-4081.89" - cell $or $or$ls180.v:4081$569 + attribute \src "ls180.v:4129.42-4129.89" + cell $or $or$ls180.v:4129$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4081$568_Y - connect \Y $or$ls180.v:4081$569_Y + connect \B $and$ls180.v:4129$568_Y + connect \Y $or$ls180.v:4129$569_Y end - attribute \src "ls180.v:4105.25-4105.174" - cell $or $or$ls180.v:4105$579 + attribute \src "ls180.v:4153.25-4153.174" + cell $or $or$ls180.v:4153$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4105$577_Y - connect \B $and$ls180.v:4105$578_Y - connect \Y $or$ls180.v:4105$579_Y + connect \A $and$ls180.v:4153$577_Y + connect \B $and$ls180.v:4153$578_Y + connect \Y $or$ls180.v:4153$579_Y end - attribute \src "ls180.v:4120.80-4120.132" - cell $or $or$ls180.v:4120$581 + attribute \src "ls180.v:4168.80-4168.132" + cell $or $or$ls180.v:4168$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4120$580_Y + connect \A $not$ls180.v:4168$580_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4120$581_Y + connect \Y $or$ls180.v:4168$581_Y end - attribute \src "ls180.v:4131.72-4131.135" - cell $or $or$ls180.v:4131$586 + attribute \src "ls180.v:4179.72-4179.135" + cell $or $or$ls180.v:4179$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252926,21 +258602,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4131$586_Y + connect \Y $or$ls180.v:4179$586_Y end - attribute \src "ls180.v:4150.80-4150.132" - cell $or $or$ls180.v:4150$592 + attribute \src "ls180.v:4198.80-4198.132" + cell $or $or$ls180.v:4198$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4150$591_Y + connect \A $not$ls180.v:4198$591_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4150$592_Y + connect \Y $or$ls180.v:4198$592_Y end - attribute \src "ls180.v:4161.72-4161.135" - cell $or $or$ls180.v:4161$597 + attribute \src "ls180.v:4209.72-4209.135" + cell $or $or$ls180.v:4209$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252948,10 +258624,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4161$597_Y + connect \Y $or$ls180.v:4209$597_Y end - attribute \src "ls180.v:4232.36-4232.111" - cell $or $or$ls180.v:4232$610 + attribute \src "ls180.v:4343.36-4343.111" + cell $or $or$ls180.v:4343$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -252959,43 +258635,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4232$610_Y + connect \Y $or$ls180.v:4343$618_Y end - attribute \src "ls180.v:4232.35-4232.151" - cell $or $or$ls180.v:4232$611 + attribute \src "ls180.v:4343.35-4343.151" + cell $or $or$ls180.v:4343$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4232$610_Y + connect \A $or$ls180.v:4343$618_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4232$611_Y + connect \Y $or$ls180.v:4343$619_Y end - attribute \src "ls180.v:4232.34-4232.192" - cell $or $or$ls180.v:4232$612 + attribute \src "ls180.v:4343.34-4343.192" + cell $or $or$ls180.v:4343$620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4232$611_Y + connect \A $or$ls180.v:4343$619_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4232$612_Y + connect \Y $or$ls180.v:4343$620_Y end - attribute \src "ls180.v:4232.33-4232.233" - cell $or $or$ls180.v:4232$613 + attribute \src "ls180.v:4343.33-4343.233" + cell $or $or$ls180.v:4343$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4232$612_Y + connect \A $or$ls180.v:4343$620_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4232$613_Y + connect \Y $or$ls180.v:4343$621_Y end - attribute \src "ls180.v:4233.39-4233.120" - cell $or $or$ls180.v:4233$614 + attribute \src "ls180.v:4344.39-4344.120" + cell $or $or$ls180.v:4344$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253003,43 +258679,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4233$614_Y + connect \Y $or$ls180.v:4344$622_Y end - attribute \src "ls180.v:4233.38-4233.163" - cell $or $or$ls180.v:4233$615 + attribute \src "ls180.v:4344.38-4344.163" + cell $or $or$ls180.v:4344$623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4233$614_Y + connect \A $or$ls180.v:4344$622_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4233$615_Y + connect \Y $or$ls180.v:4344$623_Y end - attribute \src "ls180.v:4233.37-4233.207" - cell $or $or$ls180.v:4233$616 + attribute \src "ls180.v:4344.37-4344.207" + cell $or $or$ls180.v:4344$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4233$615_Y + connect \A $or$ls180.v:4344$623_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4233$616_Y + connect \Y $or$ls180.v:4344$624_Y end - attribute \src "ls180.v:4233.36-4233.251" - cell $or $or$ls180.v:4233$617 + attribute \src "ls180.v:4344.36-4344.251" + cell $or $or$ls180.v:4344$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4233$616_Y + connect \A $or$ls180.v:4344$624_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4233$617_Y + connect \Y $or$ls180.v:4344$625_Y end - attribute \src "ls180.v:4234.38-4234.117" - cell $or $or$ls180.v:4234$618 + attribute \src "ls180.v:4345.38-4345.117" + cell $or $or$ls180.v:4345$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253047,43 +258723,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4234$618_Y + connect \Y $or$ls180.v:4345$626_Y end - attribute \src "ls180.v:4234.37-4234.159" - cell $or $or$ls180.v:4234$619 + attribute \src "ls180.v:4345.37-4345.159" + cell $or $or$ls180.v:4345$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4234$618_Y + connect \A $or$ls180.v:4345$626_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4234$619_Y + connect \Y $or$ls180.v:4345$627_Y end - attribute \src "ls180.v:4234.36-4234.202" - cell $or $or$ls180.v:4234$620 + attribute \src "ls180.v:4345.36-4345.202" + cell $or $or$ls180.v:4345$628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4234$619_Y + connect \A $or$ls180.v:4345$627_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4234$620_Y + connect \Y $or$ls180.v:4345$628_Y end - attribute \src "ls180.v:4234.35-4234.245" - cell $or $or$ls180.v:4234$621 + attribute \src "ls180.v:4345.35-4345.245" + cell $or $or$ls180.v:4345$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4234$620_Y + connect \A $or$ls180.v:4345$628_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4234$621_Y + connect \Y $or$ls180.v:4345$629_Y end - attribute \src "ls180.v:4235.40-4235.123" - cell $or $or$ls180.v:4235$622 + attribute \src "ls180.v:4346.40-4346.123" + cell $or $or$ls180.v:4346$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253091,43 +258767,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4235$622_Y + connect \Y $or$ls180.v:4346$630_Y end - attribute \src "ls180.v:4235.39-4235.167" - cell $or $or$ls180.v:4235$623 + attribute \src "ls180.v:4346.39-4346.167" + cell $or $or$ls180.v:4346$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4235$622_Y + connect \A $or$ls180.v:4346$630_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4235$623_Y + connect \Y $or$ls180.v:4346$631_Y end - attribute \src "ls180.v:4235.38-4235.212" - cell $or $or$ls180.v:4235$624 + attribute \src "ls180.v:4346.38-4346.212" + cell $or $or$ls180.v:4346$632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4235$623_Y + connect \A $or$ls180.v:4346$631_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4235$624_Y + connect \Y $or$ls180.v:4346$632_Y end - attribute \src "ls180.v:4235.37-4235.257" - cell $or $or$ls180.v:4235$625 + attribute \src "ls180.v:4346.37-4346.257" + cell $or $or$ls180.v:4346$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4235$624_Y + connect \A $or$ls180.v:4346$632_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4235$625_Y + connect \Y $or$ls180.v:4346$633_Y end - attribute \src "ls180.v:4236.39-4236.120" - cell $or $or$ls180.v:4236$626 + attribute \src "ls180.v:4347.39-4347.120" + cell $or $or$ls180.v:4347$634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -253135,43 +258811,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4236$626_Y + connect \Y $or$ls180.v:4347$634_Y end - attribute \src "ls180.v:4236.38-4236.163" - cell $or $or$ls180.v:4236$627 + attribute \src "ls180.v:4347.38-4347.163" + cell $or $or$ls180.v:4347$635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4236$626_Y + connect \A $or$ls180.v:4347$634_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4236$627_Y + connect \Y $or$ls180.v:4347$635_Y end - attribute \src "ls180.v:4236.37-4236.207" - cell $or $or$ls180.v:4236$628 + attribute \src "ls180.v:4347.37-4347.207" + cell $or $or$ls180.v:4347$636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4236$627_Y + connect \A $or$ls180.v:4347$635_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4236$628_Y + connect \Y $or$ls180.v:4347$636_Y end - attribute \src "ls180.v:4236.36-4236.251" - cell $or $or$ls180.v:4236$629 + attribute \src "ls180.v:4347.36-4347.251" + cell $or $or$ls180.v:4347$637 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4236$628_Y + connect \A $or$ls180.v:4347$636_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4236$629_Y + connect \Y $or$ls180.v:4347$637_Y end - attribute \src "ls180.v:4257.35-4257.80" - cell $or $or$ls180.v:4257$630 + attribute \src "ls180.v:4368.35-4368.80" + cell $or $or$ls180.v:4368$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253179,10 +258855,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4257$630_Y + connect \Y $or$ls180.v:4368$638_Y end - attribute \src "ls180.v:4411.91-4411.144" - cell $or $or$ls180.v:4411$644 + attribute \src "ls180.v:4522.91-4522.144" + cell $or $or$ls180.v:4522$652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253190,76 +258866,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4411$644_Y + connect \Y $or$ls180.v:4522$652_Y end - attribute \src "ls180.v:4428.53-4428.143" - cell $or $or$ls180.v:4428$647 + attribute \src "ls180.v:4539.53-4539.143" + cell $or $or$ls180.v:4539$655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4428$646_Y + connect \A $not$ls180.v:4539$654_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4428$647_Y + connect \Y $or$ls180.v:4539$655_Y end - attribute \src "ls180.v:4431.47-4431.127" - cell $or $or$ls180.v:4431$650 + attribute \src "ls180.v:4542.47-4542.127" + cell $or $or$ls180.v:4542$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4431$649_Y + connect \A $not$ls180.v:4542$657_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4431$650_Y + connect \Y $or$ls180.v:4542$658_Y end - attribute \src "ls180.v:4555.54-4555.146" - cell $or $or$ls180.v:4555$668 + attribute \src "ls180.v:4666.54-4666.146" + cell $or $or$ls180.v:4666$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4555$667_Y + connect \A $not$ls180.v:4666$675_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4555$668_Y + connect \Y $or$ls180.v:4666$676_Y end - attribute \src "ls180.v:4558.48-4558.130" - cell $or $or$ls180.v:4558$671 + attribute \src "ls180.v:4669.48-4669.130" + cell $or $or$ls180.v:4669$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4558$670_Y + connect \A $not$ls180.v:4669$678_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4558$671_Y + connect \Y $or$ls180.v:4669$679_Y end - attribute \src "ls180.v:4689.55-4689.149" - cell $or $or$ls180.v:4689$683 + attribute \src "ls180.v:4800.55-4800.149" + cell $or $or$ls180.v:4800$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4689$682_Y + connect \A $not$ls180.v:4800$690_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4689$683_Y + connect \Y $or$ls180.v:4800$691_Y end - attribute \src "ls180.v:4692.49-4692.133" - cell $or $or$ls180.v:4692$686 + attribute \src "ls180.v:4803.49-4803.133" + cell $or $or$ls180.v:4803$694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4692$685_Y + connect \A $not$ls180.v:4803$693_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4692$686_Y + connect \Y $or$ls180.v:4803$694_Y end - attribute \src "ls180.v:5321.80-5321.151" - cell $or $or$ls180.v:5321$981 + attribute \src "ls180.v:5432.80-5432.151" + cell $or $or$ls180.v:5432$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253267,21 +258943,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5321$981_Y + connect \Y $or$ls180.v:5432$989_Y end - attribute \src "ls180.v:5332.49-5332.131" - cell $or $or$ls180.v:5332$987 + attribute \src "ls180.v:5443.49-5443.131" + cell $or $or$ls180.v:5443$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5332$986_Y + connect \A $not$ls180.v:5443$994_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5332$987_Y + connect \Y $or$ls180.v:5443$995_Y end - attribute \src "ls180.v:5529.80-5529.151" - cell $or $or$ls180.v:5529$1012 + attribute \src "ls180.v:5640.80-5640.151" + cell $or $or$ls180.v:5640$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253289,10 +258965,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5529$1012_Y + connect \Y $or$ls180.v:5640$1020_Y end - attribute \src "ls180.v:5703.33-5703.102" - cell $or $or$ls180.v:5703$1060 + attribute \src "ls180.v:5755.33-5755.102" + cell $or $or$ls180.v:5755$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253300,43 +258976,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5703$1060_Y + connect \Y $or$ls180.v:5755$1060_Y end - attribute \src "ls180.v:5703.32-5703.144" - cell $or $or$ls180.v:5703$1061 + attribute \src "ls180.v:5755.32-5755.144" + cell $or $or$ls180.v:5755$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5703$1060_Y + connect \A $or$ls180.v:5755$1060_Y connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5703$1061_Y + connect \Y $or$ls180.v:5755$1061_Y end - attribute \src "ls180.v:5703.31-5703.165" - cell $or $or$ls180.v:5703$1062 + attribute \src "ls180.v:5755.31-5755.165" + cell $or $or$ls180.v:5755$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5703$1061_Y + connect \A $or$ls180.v:5755$1061_Y connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5703$1062_Y + connect \Y $or$ls180.v:5755$1062_Y end - attribute \src "ls180.v:5703.30-5703.201" - cell $or $or$ls180.v:5703$1063 + attribute \src "ls180.v:5755.30-5755.201" + cell $or $or$ls180.v:5755$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5703$1062_Y + connect \A $or$ls180.v:5755$1062_Y connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5703$1063_Y + connect \Y $or$ls180.v:5755$1063_Y end - attribute \src "ls180.v:5709.28-5709.97" - cell $or $or$ls180.v:5709$1068 + attribute \src "ls180.v:5761.28-5761.97" + cell $or $or$ls180.v:5761$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253344,87 +259020,87 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5709$1068_Y + connect \Y $or$ls180.v:5761$1068_Y end - attribute \src "ls180.v:5709.27-5709.139" - cell $or $or$ls180.v:5709$1069 + attribute \src "ls180.v:5761.27-5761.139" + cell $or $or$ls180.v:5761$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5709$1068_Y + connect \A $or$ls180.v:5761$1068_Y connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5709$1069_Y + connect \Y $or$ls180.v:5761$1069_Y end - attribute \src "ls180.v:5709.26-5709.160" - cell $or $or$ls180.v:5709$1070 + attribute \src "ls180.v:5761.26-5761.160" + cell $or $or$ls180.v:5761$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5709$1069_Y + connect \A $or$ls180.v:5761$1069_Y connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5709$1070_Y + connect \Y $or$ls180.v:5761$1070_Y end - attribute \src "ls180.v:5709.25-5709.196" - cell $or $or$ls180.v:5709$1071 + attribute \src "ls180.v:5761.25-5761.196" + cell $or $or$ls180.v:5761$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5709$1070_Y + connect \A $or$ls180.v:5761$1070_Y connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5709$1071_Y + connect \Y $or$ls180.v:5761$1071_Y end - attribute \src "ls180.v:5710.30-5710.169" - cell $or $or$ls180.v:5710$1074 + attribute \src "ls180.v:5762.30-5762.169" + cell $or $or$ls180.v:5762$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5710$1072_Y - connect \B $and$ls180.v:5710$1073_Y - connect \Y $or$ls180.v:5710$1074_Y + connect \A $and$ls180.v:5762$1072_Y + connect \B $and$ls180.v:5762$1073_Y + connect \Y $or$ls180.v:5762$1074_Y end - attribute \src "ls180.v:5710.29-5710.246" - cell $or $or$ls180.v:5710$1076 + attribute \src "ls180.v:5762.29-5762.246" + cell $or $or$ls180.v:5762$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5710$1074_Y - connect \B $and$ls180.v:5710$1075_Y - connect \Y $or$ls180.v:5710$1076_Y + connect \A $or$ls180.v:5762$1074_Y + connect \B $and$ls180.v:5762$1075_Y + connect \Y $or$ls180.v:5762$1076_Y end - attribute \src "ls180.v:5710.28-5710.302" - cell $or $or$ls180.v:5710$1078 + attribute \src "ls180.v:5762.28-5762.302" + cell $or $or$ls180.v:5762$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5710$1076_Y - connect \B $and$ls180.v:5710$1077_Y - connect \Y $or$ls180.v:5710$1078_Y + connect \A $or$ls180.v:5762$1076_Y + connect \B $and$ls180.v:5762$1077_Y + connect \Y $or$ls180.v:5762$1078_Y end - attribute \src "ls180.v:5710.27-5710.373" - cell $or $or$ls180.v:5710$1080 + attribute \src "ls180.v:5762.27-5762.373" + cell $or $or$ls180.v:5762$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5710$1078_Y - connect \B $and$ls180.v:5710$1079_Y - connect \Y $or$ls180.v:5710$1080_Y + connect \A $or$ls180.v:5762$1078_Y + connect \B $and$ls180.v:5762$1079_Y + connect \Y $or$ls180.v:5762$1080_Y end - attribute \src "ls180.v:6447.54-6447.123" - cell $or $or$ls180.v:6447$2211 + attribute \src "ls180.v:6516.55-6516.124" + cell $or $or$ls180.v:6516$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -253432,274 +259108,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2211_Y + connect \Y $or$ls180.v:6516$2226_Y end - attribute \src "ls180.v:6447.53-6447.160" - cell $or $or$ls180.v:6447$2212 + attribute \src "ls180.v:6516.54-6516.161" + cell $or $or$ls180.v:6516$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2211_Y + connect \A $or$ls180.v:6516$2226_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2212_Y + connect \Y $or$ls180.v:6516$2227_Y end - attribute \src "ls180.v:6447.52-6447.197" - cell $or $or$ls180.v:6447$2213 + attribute \src "ls180.v:6516.53-6516.198" + cell $or $or$ls180.v:6516$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2212_Y + connect \A $or$ls180.v:6516$2227_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2213_Y + connect \Y $or$ls180.v:6516$2228_Y end - attribute \src "ls180.v:6447.51-6447.234" - cell $or $or$ls180.v:6447$2214 + attribute \src "ls180.v:6516.52-6516.235" + cell $or $or$ls180.v:6516$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2213_Y + connect \A $or$ls180.v:6516$2228_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2214_Y + connect \Y $or$ls180.v:6516$2229_Y end - attribute \src "ls180.v:6447.50-6447.271" - cell $or $or$ls180.v:6447$2215 + attribute \src "ls180.v:6516.51-6516.272" + cell $or $or$ls180.v:6516$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2214_Y + connect \A $or$ls180.v:6516$2229_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2215_Y + connect \Y $or$ls180.v:6516$2230_Y end - attribute \src "ls180.v:6447.49-6447.308" - cell $or $or$ls180.v:6447$2216 + attribute \src "ls180.v:6516.50-6516.309" + cell $or $or$ls180.v:6516$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2215_Y + connect \A $or$ls180.v:6516$2230_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2216_Y + connect \Y $or$ls180.v:6516$2231_Y end - attribute \src "ls180.v:6447.48-6447.345" - cell $or $or$ls180.v:6447$2217 + attribute \src "ls180.v:6516.49-6516.346" + cell $or $or$ls180.v:6516$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2216_Y + connect \A $or$ls180.v:6516$2231_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2217_Y + connect \Y $or$ls180.v:6516$2232_Y end - attribute \src "ls180.v:6447.47-6447.382" - cell $or $or$ls180.v:6447$2218 + attribute \src "ls180.v:6516.48-6516.383" + cell $or $or$ls180.v:6516$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2217_Y + connect \A $or$ls180.v:6516$2232_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2218_Y + connect \Y $or$ls180.v:6516$2233_Y end - attribute \src "ls180.v:6447.46-6447.419" - cell $or $or$ls180.v:6447$2219 + attribute \src "ls180.v:6516.47-6516.420" + cell $or $or$ls180.v:6516$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2218_Y + connect \A $or$ls180.v:6516$2233_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2219_Y + connect \Y $or$ls180.v:6516$2234_Y end - attribute \src "ls180.v:6447.45-6447.457" - cell $or $or$ls180.v:6447$2220 + attribute \src "ls180.v:6516.46-6516.458" + cell $or $or$ls180.v:6516$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2219_Y + connect \A $or$ls180.v:6516$2234_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2220_Y + connect \Y $or$ls180.v:6516$2235_Y end - attribute \src "ls180.v:6447.44-6447.495" - cell $or $or$ls180.v:6447$2221 + attribute \src "ls180.v:6516.45-6516.496" + cell $or $or$ls180.v:6516$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2220_Y + connect \A $or$ls180.v:6516$2235_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2221_Y + connect \Y $or$ls180.v:6516$2236_Y end - attribute \src "ls180.v:6447.43-6447.533" - cell $or $or$ls180.v:6447$2222 + attribute \src "ls180.v:6516.44-6516.534" + cell $or $or$ls180.v:6516$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2221_Y + connect \A $or$ls180.v:6516$2236_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2222_Y + connect \Y $or$ls180.v:6516$2237_Y end - attribute \src "ls180.v:6447.42-6447.571" - cell $or $or$ls180.v:6447$2223 + attribute \src "ls180.v:6516.43-6516.572" + cell $or $or$ls180.v:6516$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6447$2222_Y + connect \A $or$ls180.v:6516$2237_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6447$2223_Y + connect \Y $or$ls180.v:6516$2238_Y end - attribute \src "ls180.v:6774.90-6774.179" - cell $or $or$ls180.v:6774$2248 + attribute \src "ls180.v:6516.42-6516.610" + cell $or $or$ls180.v:6516$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6516$2238_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6516$2239_Y + end + attribute \src "ls180.v:6843.90-6843.179" + cell $or $or$ls180.v:6843$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:6774$2247_Y - connect \Y $or$ls180.v:6774$2248_Y + connect \B $and$ls180.v:6843$2263_Y + connect \Y $or$ls180.v:6843$2264_Y end - attribute \src "ls180.v:6774.89-6774.254" - cell $or $or$ls180.v:6774$2251 + attribute \src "ls180.v:6843.89-6843.254" + cell $or $or$ls180.v:6843$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6774$2248_Y - connect \B $and$ls180.v:6774$2250_Y - connect \Y $or$ls180.v:6774$2251_Y + connect \A $or$ls180.v:6843$2264_Y + connect \B $and$ls180.v:6843$2266_Y + connect \Y $or$ls180.v:6843$2267_Y end - attribute \src "ls180.v:6774.88-6774.329" - cell $or $or$ls180.v:6774$2254 + attribute \src "ls180.v:6843.88-6843.329" + cell $or $or$ls180.v:6843$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6774$2251_Y - connect \B $and$ls180.v:6774$2253_Y - connect \Y $or$ls180.v:6774$2254_Y + connect \A $or$ls180.v:6843$2267_Y + connect \B $and$ls180.v:6843$2269_Y + connect \Y $or$ls180.v:6843$2270_Y end - attribute \src "ls180.v:6798.90-6798.179" - cell $or $or$ls180.v:6798$2264 + attribute \src "ls180.v:6867.90-6867.179" + cell $or $or$ls180.v:6867$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:6798$2263_Y - connect \Y $or$ls180.v:6798$2264_Y + connect \B $and$ls180.v:6867$2279_Y + connect \Y $or$ls180.v:6867$2280_Y end - attribute \src "ls180.v:6798.89-6798.254" - cell $or $or$ls180.v:6798$2267 + attribute \src "ls180.v:6867.89-6867.254" + cell $or $or$ls180.v:6867$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6798$2264_Y - connect \B $and$ls180.v:6798$2266_Y - connect \Y $or$ls180.v:6798$2267_Y + connect \A $or$ls180.v:6867$2280_Y + connect \B $and$ls180.v:6867$2282_Y + connect \Y $or$ls180.v:6867$2283_Y end - attribute \src "ls180.v:6798.88-6798.329" - cell $or $or$ls180.v:6798$2270 + attribute \src "ls180.v:6867.88-6867.329" + cell $or $or$ls180.v:6867$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6798$2267_Y - connect \B $and$ls180.v:6798$2269_Y - connect \Y $or$ls180.v:6798$2270_Y + connect \A $or$ls180.v:6867$2283_Y + connect \B $and$ls180.v:6867$2285_Y + connect \Y $or$ls180.v:6867$2286_Y end - attribute \src "ls180.v:6822.90-6822.179" - cell $or $or$ls180.v:6822$2280 + attribute \src "ls180.v:6891.90-6891.179" + cell $or $or$ls180.v:6891$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:6822$2279_Y - connect \Y $or$ls180.v:6822$2280_Y + connect \B $and$ls180.v:6891$2295_Y + connect \Y $or$ls180.v:6891$2296_Y end - attribute \src "ls180.v:6822.89-6822.254" - cell $or $or$ls180.v:6822$2283 + attribute \src "ls180.v:6891.89-6891.254" + cell $or $or$ls180.v:6891$2299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6822$2280_Y - connect \B $and$ls180.v:6822$2282_Y - connect \Y $or$ls180.v:6822$2283_Y + connect \A $or$ls180.v:6891$2296_Y + connect \B $and$ls180.v:6891$2298_Y + connect \Y $or$ls180.v:6891$2299_Y end - attribute \src "ls180.v:6822.88-6822.329" - cell $or $or$ls180.v:6822$2286 + attribute \src "ls180.v:6891.88-6891.329" + cell $or $or$ls180.v:6891$2302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6822$2283_Y - connect \B $and$ls180.v:6822$2285_Y - connect \Y $or$ls180.v:6822$2286_Y + connect \A $or$ls180.v:6891$2299_Y + connect \B $and$ls180.v:6891$2301_Y + connect \Y $or$ls180.v:6891$2302_Y end - attribute \src "ls180.v:6846.90-6846.179" - cell $or $or$ls180.v:6846$2296 + attribute \src "ls180.v:6915.90-6915.179" + cell $or $or$ls180.v:6915$2312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:6846$2295_Y - connect \Y $or$ls180.v:6846$2296_Y + connect \B $and$ls180.v:6915$2311_Y + connect \Y $or$ls180.v:6915$2312_Y end - attribute \src "ls180.v:6846.89-6846.254" - cell $or $or$ls180.v:6846$2299 + attribute \src "ls180.v:6915.89-6915.254" + cell $or $or$ls180.v:6915$2315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6846$2296_Y - connect \B $and$ls180.v:6846$2298_Y - connect \Y $or$ls180.v:6846$2299_Y + connect \A $or$ls180.v:6915$2312_Y + connect \B $and$ls180.v:6915$2314_Y + connect \Y $or$ls180.v:6915$2315_Y end - attribute \src "ls180.v:6846.88-6846.329" - cell $or $or$ls180.v:6846$2302 + attribute \src "ls180.v:6915.88-6915.329" + cell $or $or$ls180.v:6915$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6846$2299_Y - connect \B $and$ls180.v:6846$2301_Y - connect \Y $or$ls180.v:6846$2302_Y + connect \A $or$ls180.v:6915$2315_Y + connect \B $and$ls180.v:6915$2317_Y + connect \Y $or$ls180.v:6915$2318_Y end - attribute \src "ls180.v:7360.20-7360.71" - cell $or $or$ls180.v:7360$2359 + attribute \src "ls180.v:7429.20-7429.71" + cell $or $or$ls180.v:7429$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253707,10 +259394,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7360$2359_Y + connect \Y $or$ls180.v:7429$2375_Y end - attribute \src "ls180.v:7361.20-7361.71" - cell $or $or$ls180.v:7361$2360 + attribute \src "ls180.v:7430.20-7430.71" + cell $or $or$ls180.v:7430$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253718,10 +259405,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7361$2360_Y + connect \Y $or$ls180.v:7430$2376_Y end - attribute \src "ls180.v:7362.20-7362.71" - cell $or $or$ls180.v:7362$2361 + attribute \src "ls180.v:7431.20-7431.71" + cell $or $or$ls180.v:7431$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253729,10 +259416,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7362$2361_Y + connect \Y $or$ls180.v:7431$2377_Y end - attribute \src "ls180.v:7363.20-7363.71" - cell $or $or$ls180.v:7363$2362 + attribute \src "ls180.v:7432.20-7432.71" + cell $or $or$ls180.v:7432$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253740,10 +259427,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7363$2362_Y + connect \Y $or$ls180.v:7432$2378_Y end - attribute \src "ls180.v:7364.20-7364.71" - cell $or $or$ls180.v:7364$2363 + attribute \src "ls180.v:7433.20-7433.71" + cell $or $or$ls180.v:7433$2379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253751,10 +259438,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7364$2363_Y + connect \Y $or$ls180.v:7433$2379_Y end - attribute \src "ls180.v:7365.20-7365.71" - cell $or $or$ls180.v:7365$2364 + attribute \src "ls180.v:7434.20-7434.71" + cell $or $or$ls180.v:7434$2380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253762,10 +259449,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7365$2364_Y + connect \Y $or$ls180.v:7434$2380_Y end - attribute \src "ls180.v:7366.20-7366.71" - cell $or $or$ls180.v:7366$2365 + attribute \src "ls180.v:7435.20-7435.71" + cell $or $or$ls180.v:7435$2381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253773,10 +259460,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7366$2365_Y + connect \Y $or$ls180.v:7435$2381_Y end - attribute \src "ls180.v:7367.20-7367.71" - cell $or $or$ls180.v:7367$2366 + attribute \src "ls180.v:7436.20-7436.71" + cell $or $or$ls180.v:7436$2382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253784,10 +259471,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7367$2366_Y + connect \Y $or$ls180.v:7436$2382_Y end - attribute \src "ls180.v:7368.20-7368.71" - cell $or $or$ls180.v:7368$2367 + attribute \src "ls180.v:7437.20-7437.71" + cell $or $or$ls180.v:7437$2383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253795,10 +259482,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7368$2367_Y + connect \Y $or$ls180.v:7437$2383_Y end - attribute \src "ls180.v:7369.20-7369.71" - cell $or $or$ls180.v:7369$2368 + attribute \src "ls180.v:7438.20-7438.71" + cell $or $or$ls180.v:7438$2384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253806,10 +259493,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7369$2368_Y + connect \Y $or$ls180.v:7438$2384_Y end - attribute \src "ls180.v:7370.21-7370.73" - cell $or $or$ls180.v:7370$2369 + attribute \src "ls180.v:7439.21-7439.73" + cell $or $or$ls180.v:7439$2385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253817,10 +259504,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7370$2369_Y + connect \Y $or$ls180.v:7439$2385_Y end - attribute \src "ls180.v:7371.21-7371.73" - cell $or $or$ls180.v:7371$2370 + attribute \src "ls180.v:7440.21-7440.73" + cell $or $or$ls180.v:7440$2386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253828,10 +259515,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7371$2370_Y + connect \Y $or$ls180.v:7440$2386_Y end - attribute \src "ls180.v:7372.21-7372.73" - cell $or $or$ls180.v:7372$2371 + attribute \src "ls180.v:7441.21-7441.73" + cell $or $or$ls180.v:7441$2387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253839,10 +259526,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7372$2371_Y + connect \Y $or$ls180.v:7441$2387_Y end - attribute \src "ls180.v:7373.21-7373.73" - cell $or $or$ls180.v:7373$2372 + attribute \src "ls180.v:7442.21-7442.73" + cell $or $or$ls180.v:7442$2388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253850,10 +259537,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7373$2372_Y + connect \Y $or$ls180.v:7442$2388_Y end - attribute \src "ls180.v:7374.21-7374.73" - cell $or $or$ls180.v:7374$2373 + attribute \src "ls180.v:7443.21-7443.73" + cell $or $or$ls180.v:7443$2389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253861,10 +259548,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7374$2373_Y + connect \Y $or$ls180.v:7443$2389_Y end - attribute \src "ls180.v:7375.21-7375.73" - cell $or $or$ls180.v:7375$2374 + attribute \src "ls180.v:7444.21-7444.73" + cell $or $or$ls180.v:7444$2390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253872,10 +259559,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7375$2374_Y + connect \Y $or$ls180.v:7444$2390_Y end - attribute \src "ls180.v:7376.21-7376.73" - cell $or $or$ls180.v:7376$2375 + attribute \src "ls180.v:7445.21-7445.73" + cell $or $or$ls180.v:7445$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253883,10 +259570,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7376$2375_Y + connect \Y $or$ls180.v:7445$2391_Y end - attribute \src "ls180.v:7377.21-7377.73" - cell $or $or$ls180.v:7377$2376 + attribute \src "ls180.v:7446.21-7446.73" + cell $or $or$ls180.v:7446$2392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253894,10 +259581,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7377$2376_Y + connect \Y $or$ls180.v:7446$2392_Y end - attribute \src "ls180.v:7378.21-7378.73" - cell $or $or$ls180.v:7378$2377 + attribute \src "ls180.v:7447.21-7447.73" + cell $or $or$ls180.v:7447$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253905,10 +259592,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7378$2377_Y + connect \Y $or$ls180.v:7447$2393_Y end - attribute \src "ls180.v:7379.21-7379.73" - cell $or $or$ls180.v:7379$2378 + attribute \src "ls180.v:7448.21-7448.73" + cell $or $or$ls180.v:7448$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253916,10 +259603,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7379$2378_Y + connect \Y $or$ls180.v:7448$2394_Y end - attribute \src "ls180.v:7380.21-7380.73" - cell $or $or$ls180.v:7380$2379 + attribute \src "ls180.v:7449.21-7449.73" + cell $or $or$ls180.v:7449$2395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253927,10 +259614,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7380$2379_Y + connect \Y $or$ls180.v:7449$2395_Y end - attribute \src "ls180.v:7381.21-7381.73" - cell $or $or$ls180.v:7381$2380 + attribute \src "ls180.v:7450.21-7450.73" + cell $or $or$ls180.v:7450$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253938,10 +259625,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7381$2380_Y + connect \Y $or$ls180.v:7450$2396_Y end - attribute \src "ls180.v:7382.21-7382.73" - cell $or $or$ls180.v:7382$2381 + attribute \src "ls180.v:7451.21-7451.73" + cell $or $or$ls180.v:7451$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253949,10 +259636,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7382$2381_Y + connect \Y $or$ls180.v:7451$2397_Y end - attribute \src "ls180.v:7383.21-7383.73" - cell $or $or$ls180.v:7383$2382 + attribute \src "ls180.v:7452.21-7452.73" + cell $or $or$ls180.v:7452$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253960,10 +259647,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7383$2382_Y + connect \Y $or$ls180.v:7452$2398_Y end - attribute \src "ls180.v:7384.21-7384.73" - cell $or $or$ls180.v:7384$2383 + attribute \src "ls180.v:7453.21-7453.73" + cell $or $or$ls180.v:7453$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253971,10 +259658,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [24] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7384$2383_Y + connect \Y $or$ls180.v:7453$2399_Y end - attribute \src "ls180.v:7385.21-7385.73" - cell $or $or$ls180.v:7385$2384 + attribute \src "ls180.v:7454.21-7454.73" + cell $or $or$ls180.v:7454$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253982,10 +259669,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [25] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7385$2384_Y + connect \Y $or$ls180.v:7454$2400_Y end - attribute \src "ls180.v:7386.21-7386.73" - cell $or $or$ls180.v:7386$2385 + attribute \src "ls180.v:7455.21-7455.73" + cell $or $or$ls180.v:7455$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -253993,10 +259680,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [26] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7386$2385_Y + connect \Y $or$ls180.v:7455$2401_Y end - attribute \src "ls180.v:7387.21-7387.73" - cell $or $or$ls180.v:7387$2386 + attribute \src "ls180.v:7456.21-7456.73" + cell $or $or$ls180.v:7456$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254004,10 +259691,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [27] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7387$2386_Y + connect \Y $or$ls180.v:7456$2402_Y end - attribute \src "ls180.v:7388.21-7388.73" - cell $or $or$ls180.v:7388$2387 + attribute \src "ls180.v:7457.21-7457.73" + cell $or $or$ls180.v:7457$2403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254015,10 +259702,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [28] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7388$2387_Y + connect \Y $or$ls180.v:7457$2403_Y end - attribute \src "ls180.v:7389.21-7389.73" - cell $or $or$ls180.v:7389$2388 + attribute \src "ls180.v:7458.21-7458.73" + cell $or $or$ls180.v:7458$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254026,10 +259713,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [29] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7389$2388_Y + connect \Y $or$ls180.v:7458$2404_Y end - attribute \src "ls180.v:7390.21-7390.73" - cell $or $or$ls180.v:7390$2389 + attribute \src "ls180.v:7459.21-7459.73" + cell $or $or$ls180.v:7459$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254037,10 +259724,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [30] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7390$2389_Y + connect \Y $or$ls180.v:7459$2405_Y end - attribute \src "ls180.v:7391.21-7391.73" - cell $or $or$ls180.v:7391$2390 + attribute \src "ls180.v:7460.21-7460.73" + cell $or $or$ls180.v:7460$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254048,10 +259735,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [31] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7391$2390_Y + connect \Y $or$ls180.v:7460$2406_Y end - attribute \src "ls180.v:7392.21-7392.73" - cell $or $or$ls180.v:7392$2391 + attribute \src "ls180.v:7461.21-7461.73" + cell $or $or$ls180.v:7461$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254059,10 +259746,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [32] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7392$2391_Y + connect \Y $or$ls180.v:7461$2407_Y end - attribute \src "ls180.v:7393.21-7393.73" - cell $or $or$ls180.v:7393$2392 + attribute \src "ls180.v:7462.21-7462.73" + cell $or $or$ls180.v:7462$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254070,10 +259757,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [33] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7393$2392_Y + connect \Y $or$ls180.v:7462$2408_Y end - attribute \src "ls180.v:7394.21-7394.73" - cell $or $or$ls180.v:7394$2393 + attribute \src "ls180.v:7463.21-7463.73" + cell $or $or$ls180.v:7463$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254081,10 +259768,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [34] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7394$2393_Y + connect \Y $or$ls180.v:7463$2409_Y end - attribute \src "ls180.v:7395.21-7395.73" - cell $or $or$ls180.v:7395$2394 + attribute \src "ls180.v:7464.21-7464.73" + cell $or $or$ls180.v:7464$2410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254092,76 +259779,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [35] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7395$2394_Y - end - attribute \src "ls180.v:7396.21-7396.73" - cell $or $or$ls180.v:7396$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [36] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7396$2395_Y - end - attribute \src "ls180.v:7397.21-7397.73" - cell $or $or$ls180.v:7397$2396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [37] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7397$2396_Y - end - attribute \src "ls180.v:7398.21-7398.73" - cell $or $or$ls180.v:7398$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [38] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7398$2397_Y - end - attribute \src "ls180.v:7399.21-7399.73" - cell $or $or$ls180.v:7399$2398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [39] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7399$2398_Y + connect \Y $or$ls180.v:7464$2410_Y end - attribute \src "ls180.v:7400.21-7400.73" - cell $or $or$ls180.v:7400$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [40] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7400$2399_Y - end - attribute \src "ls180.v:7401.21-7401.73" - cell $or $or$ls180.v:7401$2400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [41] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7401$2400_Y - end - attribute \src "ls180.v:7402.7-7402.93" - cell $or $or$ls180.v:7402$2401 + attribute \src "ls180.v:7465.7-7465.93" + cell $or $or$ls180.v:7465$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254169,10 +259790,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface0_converted_interface_ack connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7402$2401_Y + connect \Y $or$ls180.v:7465$2411_Y end - attribute \src "ls180.v:7413.7-7413.93" - cell $or $or$ls180.v:7413$2402 + attribute \src "ls180.v:7476.7-7476.93" + cell $or $or$ls180.v:7476$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254180,10 +259801,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface1_converted_interface_ack connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7413$2402_Y + connect \Y $or$ls180.v:7476$2412_Y end - attribute \src "ls180.v:7424.7-7424.93" - cell $or $or$ls180.v:7424$2403 + attribute \src "ls180.v:7487.7-7487.93" + cell $or $or$ls180.v:7487$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254191,142 +259812,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_interface2_converted_interface_ack connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7424$2403_Y + connect \Y $or$ls180.v:7487$2413_Y end - attribute \src "ls180.v:7553.7-7553.107" - cell $or $or$ls180.v:7553$2439 + attribute \src "ls180.v:7616.7-7616.107" + cell $or $or$ls180.v:7616$2449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7553$2438_Y + connect \A $not$ls180.v:7616$2448_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7553$2439_Y + connect \Y $or$ls180.v:7616$2449_Y end - attribute \src "ls180.v:7599.7-7599.107" - cell $or $or$ls180.v:7599$2455 + attribute \src "ls180.v:7662.7-7662.107" + cell $or $or$ls180.v:7662$2465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7599$2454_Y + connect \A $not$ls180.v:7662$2464_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7599$2455_Y + connect \Y $or$ls180.v:7662$2465_Y end - attribute \src "ls180.v:7645.7-7645.107" - cell $or $or$ls180.v:7645$2471 + attribute \src "ls180.v:7708.7-7708.107" + cell $or $or$ls180.v:7708$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7645$2470_Y + connect \A $not$ls180.v:7708$2480_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7645$2471_Y + connect \Y $or$ls180.v:7708$2481_Y end - attribute \src "ls180.v:7691.7-7691.107" - cell $or $or$ls180.v:7691$2487 + attribute \src "ls180.v:7754.7-7754.107" + cell $or $or$ls180.v:7754$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7691$2486_Y + connect \A $not$ls180.v:7754$2496_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7691$2487_Y + connect \Y $or$ls180.v:7754$2497_Y end - attribute \src "ls180.v:7879.40-7879.125" - cell $or $or$ls180.v:7879$2508 + attribute \src "ls180.v:7942.40-7942.125" + cell $or $or$ls180.v:7942$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7879$2507_Y - connect \Y $or$ls180.v:7879$2508_Y + connect \B $and$ls180.v:7942$2517_Y + connect \Y $or$ls180.v:7942$2518_Y end - attribute \src "ls180.v:7879.39-7879.207" - cell $or $or$ls180.v:7879$2511 + attribute \src "ls180.v:7942.39-7942.207" + cell $or $or$ls180.v:7942$2521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7879$2508_Y - connect \B $and$ls180.v:7879$2510_Y - connect \Y $or$ls180.v:7879$2511_Y + connect \A $or$ls180.v:7942$2518_Y + connect \B $and$ls180.v:7942$2520_Y + connect \Y $or$ls180.v:7942$2521_Y end - attribute \src "ls180.v:7879.38-7879.289" - cell $or $or$ls180.v:7879$2514 + attribute \src "ls180.v:7942.38-7942.289" + cell $or $or$ls180.v:7942$2524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7879$2511_Y - connect \B $and$ls180.v:7879$2513_Y - connect \Y $or$ls180.v:7879$2514_Y + connect \A $or$ls180.v:7942$2521_Y + connect \B $and$ls180.v:7942$2523_Y + connect \Y $or$ls180.v:7942$2524_Y end - attribute \src "ls180.v:7879.37-7879.371" - cell $or $or$ls180.v:7879$2517 + attribute \src "ls180.v:7942.37-7942.371" + cell $or $or$ls180.v:7942$2527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7879$2514_Y - connect \B $and$ls180.v:7879$2516_Y - connect \Y $or$ls180.v:7879$2517_Y + connect \A $or$ls180.v:7942$2524_Y + connect \B $and$ls180.v:7942$2526_Y + connect \Y $or$ls180.v:7942$2527_Y end - attribute \src "ls180.v:7880.41-7880.126" - cell $or $or$ls180.v:7880$2520 + attribute \src "ls180.v:7943.41-7943.126" + cell $or $or$ls180.v:7943$2530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:7880$2519_Y - connect \Y $or$ls180.v:7880$2520_Y + connect \B $and$ls180.v:7943$2529_Y + connect \Y $or$ls180.v:7943$2530_Y end - attribute \src "ls180.v:7880.40-7880.208" - cell $or $or$ls180.v:7880$2523 + attribute \src "ls180.v:7943.40-7943.208" + cell $or $or$ls180.v:7943$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7880$2520_Y - connect \B $and$ls180.v:7880$2522_Y - connect \Y $or$ls180.v:7880$2523_Y + connect \A $or$ls180.v:7943$2530_Y + connect \B $and$ls180.v:7943$2532_Y + connect \Y $or$ls180.v:7943$2533_Y end - attribute \src "ls180.v:7880.39-7880.290" - cell $or $or$ls180.v:7880$2526 + attribute \src "ls180.v:7943.39-7943.290" + cell $or $or$ls180.v:7943$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7880$2523_Y - connect \B $and$ls180.v:7880$2525_Y - connect \Y $or$ls180.v:7880$2526_Y + connect \A $or$ls180.v:7943$2533_Y + connect \B $and$ls180.v:7943$2535_Y + connect \Y $or$ls180.v:7943$2536_Y end - attribute \src "ls180.v:7880.38-7880.372" - cell $or $or$ls180.v:7880$2529 + attribute \src "ls180.v:7943.38-7943.372" + cell $or $or$ls180.v:7943$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7880$2526_Y - connect \B $and$ls180.v:7880$2528_Y - connect \Y $or$ls180.v:7880$2529_Y + connect \A $or$ls180.v:7943$2536_Y + connect \B $and$ls180.v:7943$2538_Y + connect \Y $or$ls180.v:7943$2539_Y end - attribute \src "ls180.v:7884.7-7884.49" - cell $or $or$ls180.v:7884$2530 + attribute \src "ls180.v:7947.7-7947.49" + cell $or $or$ls180.v:7947$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254334,21 +259955,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:7884$2530_Y + connect \Y $or$ls180.v:7947$2540_Y + end + attribute \src "ls180.v:8110.21-8110.74" + cell $or $or$ls180.v:8110$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8110$2586_Y + connect \B $not$ls180.v:8110$2587_Y + connect \Y $or$ls180.v:8110$2588_Y end - attribute \src "ls180.v:8047.22-8047.74" - cell $or $or$ls180.v:8047$2578 + attribute \src "ls180.v:8145.21-8145.71" + cell $or $or$ls180.v:8145$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8047$2576_Y - connect \B $not$ls180.v:8047$2577_Y - connect \Y $or$ls180.v:8047$2578_Y + connect \A $not$ls180.v:8145$2591_Y + connect \B $not$ls180.v:8145$2592_Y + connect \Y $or$ls180.v:8145$2593_Y end - attribute \src "ls180.v:8115.32-8115.85" - cell $or $or$ls180.v:8115$2590 + attribute \src "ls180.v:8213.32-8213.85" + cell $or $or$ls180.v:8213$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254356,21 +259988,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8115$2590_Y + connect \Y $or$ls180.v:8213$2605_Y end - attribute \src "ls180.v:8121.8-8121.97" - cell $or $or$ls180.v:8121$2592 + attribute \src "ls180.v:8219.8-8219.97" + cell $or $or$ls180.v:8219$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8121$2591_Y + connect \A $eq$ls180.v:8219$2606_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8121$2592_Y + connect \Y $or$ls180.v:8219$2607_Y end - attribute \src "ls180.v:8138.52-8138.139" - cell $or $or$ls180.v:8138$2597 + attribute \src "ls180.v:8236.52-8236.139" + cell $or $or$ls180.v:8236$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254378,10 +260010,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8138$2597_Y + connect \Y $or$ls180.v:8236$2612_Y end - attribute \src "ls180.v:8139.51-8139.136" - cell $or $or$ls180.v:8139$2598 + attribute \src "ls180.v:8237.51-8237.136" + cell $or $or$ls180.v:8237$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254389,21 +260021,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8139$2598_Y + connect \Y $or$ls180.v:8237$2613_Y end - attribute \src "ls180.v:8173.7-8173.87" - cell $or $or$ls180.v:8173$2601 + attribute \src "ls180.v:8271.7-8271.87" + cell $or $or$ls180.v:8271$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8173$2600_Y + connect \A $not$ls180.v:8271$2615_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8173$2601_Y + connect \Y $or$ls180.v:8271$2616_Y end - attribute \src "ls180.v:8196.33-8196.88" - cell $or $or$ls180.v:8196$2602 + attribute \src "ls180.v:8294.33-8294.88" + cell $or $or$ls180.v:8294$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254411,21 +260043,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8196$2602_Y + connect \Y $or$ls180.v:8294$2617_Y end - attribute \src "ls180.v:8202.8-8202.99" - cell $or $or$ls180.v:8202$2604 + attribute \src "ls180.v:8300.8-8300.99" + cell $or $or$ls180.v:8300$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8202$2603_Y + connect \A $eq$ls180.v:8300$2618_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8202$2604_Y + connect \Y $or$ls180.v:8300$2619_Y end - attribute \src "ls180.v:8219.53-8219.142" - cell $or $or$ls180.v:8219$2609 + attribute \src "ls180.v:8317.53-8317.142" + cell $or $or$ls180.v:8317$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254433,10 +260065,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8219$2609_Y + connect \Y $or$ls180.v:8317$2624_Y end - attribute \src "ls180.v:8220.52-8220.139" - cell $or $or$ls180.v:8220$2610 + attribute \src "ls180.v:8318.52-8318.139" + cell $or $or$ls180.v:8318$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254444,21 +260076,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8220$2610_Y + connect \Y $or$ls180.v:8318$2625_Y end - attribute \src "ls180.v:8254.7-8254.89" - cell $or $or$ls180.v:8254$2613 + attribute \src "ls180.v:8352.7-8352.89" + cell $or $or$ls180.v:8352$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8254$2612_Y + connect \A $not$ls180.v:8352$2627_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8254$2613_Y + connect \Y $or$ls180.v:8352$2628_Y end - attribute \src "ls180.v:8275.34-8275.91" - cell $or $or$ls180.v:8275$2614 + attribute \src "ls180.v:8373.34-8373.91" + cell $or $or$ls180.v:8373$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254466,21 +260098,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8275$2614_Y + connect \Y $or$ls180.v:8373$2629_Y end - attribute \src "ls180.v:8281.8-8281.101" - cell $or $or$ls180.v:8281$2616 + attribute \src "ls180.v:8379.8-8379.101" + cell $or $or$ls180.v:8379$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8281$2615_Y + connect \A $eq$ls180.v:8379$2630_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8281$2616_Y + connect \Y $or$ls180.v:8379$2631_Y end - attribute \src "ls180.v:8298.54-8298.145" - cell $or $or$ls180.v:8298$2621 + attribute \src "ls180.v:8396.54-8396.145" + cell $or $or$ls180.v:8396$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254488,10 +260120,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8298$2621_Y + connect \Y $or$ls180.v:8396$2636_Y end - attribute \src "ls180.v:8299.53-8299.142" - cell $or $or$ls180.v:8299$2622 + attribute \src "ls180.v:8397.53-8397.142" + cell $or $or$ls180.v:8397$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254499,32 +260131,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8299$2622_Y + connect \Y $or$ls180.v:8397$2637_Y end - attribute \src "ls180.v:8315.7-8315.91" - cell $or $or$ls180.v:8315$2625 + attribute \src "ls180.v:8413.7-8413.91" + cell $or $or$ls180.v:8413$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8315$2624_Y + connect \A $not$ls180.v:8413$2639_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8315$2625_Y + connect \Y $or$ls180.v:8413$2640_Y end - attribute \src "ls180.v:8504.8-8504.89" - cell $or $or$ls180.v:8504$2649 + attribute \src "ls180.v:8602.8-8602.89" + cell $or $or$ls180.v:8602$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8504$2648_Y + connect \A $eq$ls180.v:8602$2663_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8504$2649_Y + connect \Y $or$ls180.v:8602$2664_Y end - attribute \src "ls180.v:8521.48-8521.127" - cell $or $or$ls180.v:8521$2654 + attribute \src "ls180.v:8619.48-8619.127" + cell $or $or$ls180.v:8619$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254532,10 +260164,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8521$2654_Y + connect \Y $or$ls180.v:8619$2669_Y end - attribute \src "ls180.v:8522.47-8522.124" - cell $or $or$ls180.v:8522$2655 + attribute \src "ls180.v:8620.47-8620.124" + cell $or $or$ls180.v:8620$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254543,21 +260175,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8522$2655_Y - end - attribute \src "ls180.v:8595.21-8595.65" - cell $or $or$ls180.v:8595$2673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8595$2671_Y - connect \B $not$ls180.v:8595$2672_Y - connect \Y $or$ls180.v:8595$2673_Y + connect \Y $or$ls180.v:8620$2670_Y end - attribute \src "ls180.v:3131.46-3131.94" - cell $sshl $sshl$ls180.v:3131$83 + attribute \src "ls180.v:3179.46-3179.94" + cell $sshl $sshl$ls180.v:3179$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254565,10 +260186,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3131$83_Y + connect \Y $sshl$ls180.v:3179$83_Y end - attribute \src "ls180.v:3288.46-3288.94" - cell $sshl $sshl$ls180.v:3288$113 + attribute \src "ls180.v:3336.46-3336.94" + cell $sshl $sshl$ls180.v:3336$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254576,10 +260197,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3288$113_Y + connect \Y $sshl$ls180.v:3336$113_Y end - attribute \src "ls180.v:3445.46-3445.94" - cell $sshl $sshl$ls180.v:3445$143 + attribute \src "ls180.v:3493.46-3493.94" + cell $sshl $sshl$ls180.v:3493$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254587,10 +260208,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3445$143_Y + connect \Y $sshl$ls180.v:3493$143_Y end - attribute \src "ls180.v:3602.46-3602.94" - cell $sshl $sshl$ls180.v:3602$173 + attribute \src "ls180.v:3650.46-3650.94" + cell $sshl $sshl$ls180.v:3650$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254598,10 +260219,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3602$173_Y + connect \Y $sshl$ls180.v:3650$173_Y end - attribute \src "ls180.v:3162.63-3162.122" - cell $sub $sub$ls180.v:3162$96 + attribute \src "ls180.v:3210.63-3210.122" + cell $sub $sub$ls180.v:3210$96 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254609,10 +260230,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3162$96_Y + connect \Y $sub$ls180.v:3210$96_Y end - attribute \src "ls180.v:3319.63-3319.122" - cell $sub $sub$ls180.v:3319$126 + attribute \src "ls180.v:3367.63-3367.122" + cell $sub $sub$ls180.v:3367$126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254620,10 +260241,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3319$126_Y + connect \Y $sub$ls180.v:3367$126_Y end - attribute \src "ls180.v:3476.63-3476.122" - cell $sub $sub$ls180.v:3476$156 + attribute \src "ls180.v:3524.63-3524.122" + cell $sub $sub$ls180.v:3524$156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254631,10 +260252,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3476$156_Y + connect \Y $sub$ls180.v:3524$156_Y end - attribute \src "ls180.v:3633.63-3633.122" - cell $sub $sub$ls180.v:3633$186 + attribute \src "ls180.v:3681.63-3681.122" + cell $sub $sub$ls180.v:3681$186 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254642,10 +260263,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3633$186_Y + connect \Y $sub$ls180.v:3681$186_Y end - attribute \src "ls180.v:4039.38-4039.75" - cell $sub $sub$ls180.v:4039$540 + attribute \src "ls180.v:4087.38-4087.75" + cell $sub $sub$ls180.v:4087$540 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -254653,10 +260274,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4039$540_Y + connect \Y $sub$ls180.v:4087$540_Y end - attribute \src "ls180.v:4125.36-4125.68" - cell $sub $sub$ls180.v:4125$585 + attribute \src "ls180.v:4173.36-4173.68" + cell $sub $sub$ls180.v:4173$585 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254664,10 +260285,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4125$585_Y + connect \Y $sub$ls180.v:4173$585_Y end - attribute \src "ls180.v:4155.36-4155.68" - cell $sub $sub$ls180.v:4155$596 + attribute \src "ls180.v:4203.36-4203.68" + cell $sub $sub$ls180.v:4203$596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254675,43 +260296,76 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4155$596_Y + connect \Y $sub$ls180.v:4203$596_Y + end + attribute \src "ls180.v:4228.70-4228.110" + cell $sub $sub$ls180.v:4228$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4228$602_Y + end + attribute \src "ls180.v:4229.70-4229.104" + cell $sub $sub$ls180.v:4229$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4229$604_Y end - attribute \src "ls180.v:4180.69-4180.110" - cell $sub $sub$ls180.v:4180$602 + attribute \src "ls180.v:4256.37-4256.66" + cell $sub $sub$ls180.v:4256$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4256$608_Y + end + attribute \src "ls180.v:4286.67-4286.107" + cell $sub $sub$ls180.v:4286$610 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider0 [15:1] + connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4180$602_Y + connect \Y $sub$ls180.v:4286$610_Y end - attribute \src "ls180.v:4181.69-4181.104" - cell $sub $sub$ls180.v:4181$604 + attribute \src "ls180.v:4287.67-4287.101" + cell $sub $sub$ls180.v:4287$612 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 16 - connect \A \main_spi_master_clk_divider0 + connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4181$604_Y + connect \Y $sub$ls180.v:4287$612_Y end - attribute \src "ls180.v:4208.36-4208.66" - cell $sub $sub$ls180.v:4208$608 + attribute \src "ls180.v:4315.35-4315.64" + cell $sub $sub$ls180.v:4315$616 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 8 - connect \A \main_spi_master_length0 + connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4208$608_Y + connect \Y $sub$ls180.v:4315$616_Y end - attribute \src "ls180.v:4458.60-4458.90" - cell $sub $sub$ls180.v:4458$652 + attribute \src "ls180.v:4569.60-4569.90" + cell $sub $sub$ls180.v:4569$660 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254719,10 +260373,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4458$652_Y + connect \Y $sub$ls180.v:4569$660_Y end - attribute \src "ls180.v:4469.62-4469.104" - cell $sub $sub$ls180.v:4469$654 + attribute \src "ls180.v:4580.62-4580.104" + cell $sub $sub$ls180.v:4580$662 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254730,10 +260384,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4469$654_Y + connect \Y $sub$ls180.v:4580$662_Y end - attribute \src "ls180.v:4486.60-4486.90" - cell $sub $sub$ls180.v:4486$658 + attribute \src "ls180.v:4597.60-4597.90" + cell $sub $sub$ls180.v:4597$666 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254741,10 +260395,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4486$658_Y + connect \Y $sub$ls180.v:4597$666_Y end - attribute \src "ls180.v:4715.62-4715.93" - cell $sub $sub$ls180.v:4715$688 + attribute \src "ls180.v:4826.62-4826.93" + cell $sub $sub$ls180.v:4826$696 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254752,10 +260406,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4715$688_Y + connect \Y $sub$ls180.v:4826$696_Y end - attribute \src "ls180.v:4720.62-4720.93" - cell $sub $sub$ls180.v:4720$689 + attribute \src "ls180.v:4831.62-4831.93" + cell $sub $sub$ls180.v:4831$697 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254763,21 +260417,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4720$689_Y + connect \Y $sub$ls180.v:4831$697_Y end - attribute \src "ls180.v:4731.64-4731.122" - cell $sub $sub$ls180.v:4731$692 + attribute \src "ls180.v:4842.64-4842.122" + cell $sub $sub$ls180.v:4842$700 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4731$691_Y + connect \A $add$ls180.v:4842$699_Y connect \B 1'1 - connect \Y $sub$ls180.v:4731$692_Y + connect \Y $sub$ls180.v:4842$700_Y end - attribute \src "ls180.v:4752.62-4752.93" - cell $sub $sub$ls180.v:4752$695 + attribute \src "ls180.v:4863.62-4863.93" + cell $sub $sub$ls180.v:4863$703 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254785,10 +260439,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4752$695_Y + connect \Y $sub$ls180.v:4863$703_Y end - attribute \src "ls180.v:5214.37-5214.75" - cell $sub $sub$ls180.v:5214$968 + attribute \src "ls180.v:5325.37-5325.75" + cell $sub $sub$ls180.v:5325$976 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254796,10 +260450,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5214$968_Y + connect \Y $sub$ls180.v:5325$976_Y end - attribute \src "ls180.v:5229.62-5229.100" - cell $sub $sub$ls180.v:5229$971 + attribute \src "ls180.v:5340.62-5340.100" + cell $sub $sub$ls180.v:5340$979 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254807,10 +260461,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5229$971_Y + connect \Y $sub$ls180.v:5340$979_Y end - attribute \src "ls180.v:5240.39-5240.77" - cell $sub $sub$ls180.v:5240$976 + attribute \src "ls180.v:5351.39-5351.77" + cell $sub $sub$ls180.v:5351$984 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254818,10 +260472,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5240$976_Y + connect \Y $sub$ls180.v:5351$984_Y end - attribute \src "ls180.v:5315.40-5315.76" - cell $sub $sub$ls180.v:5315$980 + attribute \src "ls180.v:5426.40-5426.76" + cell $sub $sub$ls180.v:5426$988 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254829,10 +260483,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5315$980_Y + connect \Y $sub$ls180.v:5426$988_Y end - attribute \src "ls180.v:5364.56-5364.104" - cell $sub $sub$ls180.v:5364$994 + attribute \src "ls180.v:5475.56-5475.104" + cell $sub $sub$ls180.v:5475$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254840,10 +260494,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5364$994_Y + connect \Y $sub$ls180.v:5475$1002_Y end - attribute \src "ls180.v:5454.71-5454.105" - cell $sub $sub$ls180.v:5454$1000 + attribute \src "ls180.v:5565.71-5565.105" + cell $sub $sub$ls180.v:5565$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254851,10 +260505,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5454$1000_Y + connect \Y $sub$ls180.v:5565$1008_Y end - attribute \src "ls180.v:5523.40-5523.76" - cell $sub $sub$ls180.v:5523$1011 + attribute \src "ls180.v:5634.40-5634.76" + cell $sub $sub$ls180.v:5634$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254862,43 +260516,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5523$1011_Y - end - attribute \src "ls180.v:5542.61-5542.98" - cell $sub $sub$ls180.v:5542$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:5542$1017_Y - end - attribute \src "ls180.v:5543.61-5543.92" - cell $sub $sub$ls180.v:5543$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \libresocsim_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:5543$1019_Y - end - attribute \src "ls180.v:5571.32-5571.58" - cell $sub $sub$ls180.v:5571$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \libresocsim_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:5571$1023_Y + connect \Y $sub$ls180.v:5634$1019_Y end - attribute \src "ls180.v:7448.31-7448.60" - cell $sub $sub$ls180.v:7448$2410 + attribute \src "ls180.v:7511.31-7511.60" + cell $sub $sub$ls180.v:7511$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254906,10 +260527,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7448$2410_Y + connect \Y $sub$ls180.v:7511$2420_Y end - attribute \src "ls180.v:7469.31-7469.61" - cell $sub $sub$ls180.v:7469$2415 + attribute \src "ls180.v:7532.31-7532.61" + cell $sub $sub$ls180.v:7532$2425 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -254917,10 +260538,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7469$2415_Y + connect \Y $sub$ls180.v:7532$2425_Y end - attribute \src "ls180.v:7475.34-7475.67" - cell $sub $sub$ls180.v:7475$2416 + attribute \src "ls180.v:7538.34-7538.67" + cell $sub $sub$ls180.v:7538$2426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254928,10 +260549,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7475$2416_Y + connect \Y $sub$ls180.v:7538$2426_Y end - attribute \src "ls180.v:7486.36-7486.69" - cell $sub $sub$ls180.v:7486$2419 + attribute \src "ls180.v:7549.36-7549.69" + cell $sub $sub$ls180.v:7549$2429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254939,10 +260560,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7486$2419_Y + connect \Y $sub$ls180.v:7549$2429_Y end - attribute \src "ls180.v:7550.59-7550.116" - cell $sub $sub$ls180.v:7550$2437 + attribute \src "ls180.v:7613.59-7613.116" + cell $sub $sub$ls180.v:7613$2447 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254950,10 +260571,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7550$2437_Y + connect \Y $sub$ls180.v:7613$2447_Y end - attribute \src "ls180.v:7569.46-7569.90" - cell $sub $sub$ls180.v:7569$2441 + attribute \src "ls180.v:7632.46-7632.90" + cell $sub $sub$ls180.v:7632$2451 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254961,10 +260582,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7569$2441_Y + connect \Y $sub$ls180.v:7632$2451_Y end - attribute \src "ls180.v:7596.59-7596.116" - cell $sub $sub$ls180.v:7596$2453 + attribute \src "ls180.v:7659.59-7659.116" + cell $sub $sub$ls180.v:7659$2463 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254972,10 +260593,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7596$2453_Y + connect \Y $sub$ls180.v:7659$2463_Y end - attribute \src "ls180.v:7615.46-7615.90" - cell $sub $sub$ls180.v:7615$2457 + attribute \src "ls180.v:7678.46-7678.90" + cell $sub $sub$ls180.v:7678$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254983,10 +260604,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7615$2457_Y + connect \Y $sub$ls180.v:7678$2467_Y end - attribute \src "ls180.v:7642.59-7642.116" - cell $sub $sub$ls180.v:7642$2469 + attribute \src "ls180.v:7705.59-7705.116" + cell $sub $sub$ls180.v:7705$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254994,10 +260615,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7642$2469_Y + connect \Y $sub$ls180.v:7705$2479_Y end - attribute \src "ls180.v:7661.46-7661.90" - cell $sub $sub$ls180.v:7661$2473 + attribute \src "ls180.v:7724.46-7724.90" + cell $sub $sub$ls180.v:7724$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255005,10 +260626,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7661$2473_Y + connect \Y $sub$ls180.v:7724$2483_Y end - attribute \src "ls180.v:7688.59-7688.116" - cell $sub $sub$ls180.v:7688$2485 + attribute \src "ls180.v:7751.59-7751.116" + cell $sub $sub$ls180.v:7751$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255016,10 +260637,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7688$2485_Y + connect \Y $sub$ls180.v:7751$2495_Y end - attribute \src "ls180.v:7707.46-7707.90" - cell $sub $sub$ls180.v:7707$2489 + attribute \src "ls180.v:7770.46-7770.90" + cell $sub $sub$ls180.v:7770$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255027,10 +260648,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7707$2489_Y + connect \Y $sub$ls180.v:7770$2499_Y end - attribute \src "ls180.v:7718.25-7718.48" - cell $sub $sub$ls180.v:7718$2493 + attribute \src "ls180.v:7781.25-7781.48" + cell $sub $sub$ls180.v:7781$2503 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255038,10 +260659,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:7718$2493_Y + connect \Y $sub$ls180.v:7781$2503_Y end - attribute \src "ls180.v:7725.25-7725.48" - cell $sub $sub$ls180.v:7725$2496 + attribute \src "ls180.v:7788.25-7788.48" + cell $sub $sub$ls180.v:7788$2506 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255049,10 +260670,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:7725$2496_Y + connect \Y $sub$ls180.v:7788$2506_Y end - attribute \src "ls180.v:7857.33-7857.64" - cell $sub $sub$ls180.v:7857$2501 + attribute \src "ls180.v:7920.33-7920.64" + cell $sub $sub$ls180.v:7920$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255060,10 +260681,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7857$2501_Y + connect \Y $sub$ls180.v:7920$2511_Y end - attribute \src "ls180.v:7872.33-7872.64" - cell $sub $sub$ls180.v:7872$2504 + attribute \src "ls180.v:7935.33-7935.64" + cell $sub $sub$ls180.v:7935$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255071,10 +260692,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7872$2504_Y + connect \Y $sub$ls180.v:7935$2514_Y end - attribute \src "ls180.v:7999.33-7999.64" - cell $sub $sub$ls180.v:7999$2563 + attribute \src "ls180.v:8062.33-8062.64" + cell $sub $sub$ls180.v:8062$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255082,10 +260703,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:7999$2563_Y + connect \Y $sub$ls180.v:8062$2573_Y end - attribute \src "ls180.v:8021.33-8021.64" - cell $sub $sub$ls180.v:8021$2574 + attribute \src "ls180.v:8084.33-8084.64" + cell $sub $sub$ls180.v:8084$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255093,21 +260714,32 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8021$2574_Y + connect \Y $sub$ls180.v:8084$2584_Y end - attribute \src "ls180.v:8056.33-8056.64" - cell $sub $sub$ls180.v:8056$2579 + attribute \src "ls180.v:8119.34-8119.66" + cell $sub $sub$ls180.v:8119$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_spi_master_mosi_sel + connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8056$2579_Y + connect \Y $sub$ls180.v:8119$2589_Y end - attribute \src "ls180.v:8080.30-8080.53" - cell $sub $sub$ls180.v:8080$2582 + attribute \src "ls180.v:8154.32-8154.62" + cell $sub $sub$ls180.v:8154$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8154$2594_Y + end + attribute \src "ls180.v:8178.30-8178.53" + cell $sub $sub$ls180.v:8178$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255115,10 +260747,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8080$2582_Y + connect \Y $sub$ls180.v:8178$2597_Y end - attribute \src "ls180.v:8094.30-8094.53" - cell $sub $sub$ls180.v:8094$2586 + attribute \src "ls180.v:8192.30-8192.53" + cell $sub $sub$ls180.v:8192$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255126,10 +260758,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8094$2586_Y + connect \Y $sub$ls180.v:8192$2601_Y end - attribute \src "ls180.v:8497.36-8497.70" - cell $sub $sub$ls180.v:8497$2647 + attribute \src "ls180.v:8595.36-8595.70" + cell $sub $sub$ls180.v:8595$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255137,10 +260769,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8497$2647_Y + connect \Y $sub$ls180.v:8595$2662_Y end - attribute \src "ls180.v:8583.36-8583.70" - cell $sub $sub$ls180.v:8583$2669 + attribute \src "ls180.v:8681.36-8681.70" + cell $sub $sub$ls180.v:8681$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255148,21 +260780,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8583$2669_Y + connect \Y $sub$ls180.v:8681$2684_Y end - attribute \src "ls180.v:8604.29-8604.56" - cell $sub $sub$ls180.v:8604$2674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \libresocsim_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8604$2674_Y - end - attribute \src "ls180.v:8731.22-8731.42" - cell $sub $sub$ls180.v:8731$2681 + attribute \src "ls180.v:8794.22-8794.42" + cell $sub $sub$ls180.v:8794$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -255170,10 +260791,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:8731$2681_Y + connect \Y $sub$ls180.v:8794$2691_Y end - attribute \src "ls180.v:4812.353-4812.425" - cell $xor $xor$ls180.v:4812$702 + attribute \src "ls180.v:4923.353-4923.425" + cell $xor $xor$ls180.v:4923$710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255181,10 +260802,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4812$702_Y + connect \Y $xor$ls180.v:4923$710_Y end - attribute \src "ls180.v:4812.200-4812.272" - cell $xor $xor$ls180.v:4812$703 + attribute \src "ls180.v:4923.200-4923.272" + cell $xor $xor$ls180.v:4923$711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255192,21 +260813,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4812$703_Y + connect \Y $xor$ls180.v:4923$711_Y end - attribute \src "ls180.v:4812.160-4812.273" - cell $xor $xor$ls180.v:4812$704 + attribute \src "ls180.v:4923.160-4923.273" + cell $xor $xor$ls180.v:4923$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4812$703_Y - connect \Y $xor$ls180.v:4812$704_Y + connect \B $xor$ls180.v:4923$711_Y + connect \Y $xor$ls180.v:4923$712_Y end - attribute \src "ls180.v:4813.353-4813.425" - cell $xor $xor$ls180.v:4813$705 + attribute \src "ls180.v:4924.353-4924.425" + cell $xor $xor$ls180.v:4924$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255214,10 +260835,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4813$705_Y + connect \Y $xor$ls180.v:4924$713_Y end - attribute \src "ls180.v:4813.200-4813.272" - cell $xor $xor$ls180.v:4813$706 + attribute \src "ls180.v:4924.200-4924.272" + cell $xor $xor$ls180.v:4924$714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255225,21 +260846,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4813$706_Y + connect \Y $xor$ls180.v:4924$714_Y end - attribute \src "ls180.v:4813.160-4813.273" - cell $xor $xor$ls180.v:4813$707 + attribute \src "ls180.v:4924.160-4924.273" + cell $xor $xor$ls180.v:4924$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4813$706_Y - connect \Y $xor$ls180.v:4813$707_Y + connect \B $xor$ls180.v:4924$714_Y + connect \Y $xor$ls180.v:4924$715_Y end - attribute \src "ls180.v:4814.353-4814.425" - cell $xor $xor$ls180.v:4814$708 + attribute \src "ls180.v:4925.353-4925.425" + cell $xor $xor$ls180.v:4925$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255247,10 +260868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4814$708_Y + connect \Y $xor$ls180.v:4925$716_Y end - attribute \src "ls180.v:4814.200-4814.272" - cell $xor $xor$ls180.v:4814$709 + attribute \src "ls180.v:4925.200-4925.272" + cell $xor $xor$ls180.v:4925$717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255258,21 +260879,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4814$709_Y + connect \Y $xor$ls180.v:4925$717_Y end - attribute \src "ls180.v:4814.160-4814.273" - cell $xor $xor$ls180.v:4814$710 + attribute \src "ls180.v:4925.160-4925.273" + cell $xor $xor$ls180.v:4925$718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4814$709_Y - connect \Y $xor$ls180.v:4814$710_Y + connect \B $xor$ls180.v:4925$717_Y + connect \Y $xor$ls180.v:4925$718_Y end - attribute \src "ls180.v:4815.353-4815.425" - cell $xor $xor$ls180.v:4815$711 + attribute \src "ls180.v:4926.353-4926.425" + cell $xor $xor$ls180.v:4926$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255280,10 +260901,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4815$711_Y + connect \Y $xor$ls180.v:4926$719_Y end - attribute \src "ls180.v:4815.200-4815.272" - cell $xor $xor$ls180.v:4815$712 + attribute \src "ls180.v:4926.200-4926.272" + cell $xor $xor$ls180.v:4926$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255291,21 +260912,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4815$712_Y + connect \Y $xor$ls180.v:4926$720_Y end - attribute \src "ls180.v:4815.160-4815.273" - cell $xor $xor$ls180.v:4815$713 + attribute \src "ls180.v:4926.160-4926.273" + cell $xor $xor$ls180.v:4926$721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4815$712_Y - connect \Y $xor$ls180.v:4815$713_Y + connect \B $xor$ls180.v:4926$720_Y + connect \Y $xor$ls180.v:4926$721_Y end - attribute \src "ls180.v:4816.353-4816.425" - cell $xor $xor$ls180.v:4816$714 + attribute \src "ls180.v:4927.353-4927.425" + cell $xor $xor$ls180.v:4927$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255313,10 +260934,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4816$714_Y + connect \Y $xor$ls180.v:4927$722_Y end - attribute \src "ls180.v:4816.200-4816.272" - cell $xor $xor$ls180.v:4816$715 + attribute \src "ls180.v:4927.200-4927.272" + cell $xor $xor$ls180.v:4927$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255324,21 +260945,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4816$715_Y + connect \Y $xor$ls180.v:4927$723_Y end - attribute \src "ls180.v:4816.160-4816.273" - cell $xor $xor$ls180.v:4816$716 + attribute \src "ls180.v:4927.160-4927.273" + cell $xor $xor$ls180.v:4927$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4816$715_Y - connect \Y $xor$ls180.v:4816$716_Y + connect \B $xor$ls180.v:4927$723_Y + connect \Y $xor$ls180.v:4927$724_Y end - attribute \src "ls180.v:4817.353-4817.425" - cell $xor $xor$ls180.v:4817$717 + attribute \src "ls180.v:4928.353-4928.425" + cell $xor $xor$ls180.v:4928$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255346,10 +260967,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4817$717_Y + connect \Y $xor$ls180.v:4928$725_Y end - attribute \src "ls180.v:4817.200-4817.272" - cell $xor $xor$ls180.v:4817$718 + attribute \src "ls180.v:4928.200-4928.272" + cell $xor $xor$ls180.v:4928$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255357,21 +260978,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4817$718_Y + connect \Y $xor$ls180.v:4928$726_Y end - attribute \src "ls180.v:4817.160-4817.273" - cell $xor $xor$ls180.v:4817$719 + attribute \src "ls180.v:4928.160-4928.273" + cell $xor $xor$ls180.v:4928$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4817$718_Y - connect \Y $xor$ls180.v:4817$719_Y + connect \B $xor$ls180.v:4928$726_Y + connect \Y $xor$ls180.v:4928$727_Y end - attribute \src "ls180.v:4818.353-4818.425" - cell $xor $xor$ls180.v:4818$720 + attribute \src "ls180.v:4929.353-4929.425" + cell $xor $xor$ls180.v:4929$728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255379,10 +261000,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4818$720_Y + connect \Y $xor$ls180.v:4929$728_Y end - attribute \src "ls180.v:4818.200-4818.272" - cell $xor $xor$ls180.v:4818$721 + attribute \src "ls180.v:4929.200-4929.272" + cell $xor $xor$ls180.v:4929$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255390,21 +261011,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4818$721_Y + connect \Y $xor$ls180.v:4929$729_Y end - attribute \src "ls180.v:4818.160-4818.273" - cell $xor $xor$ls180.v:4818$722 + attribute \src "ls180.v:4929.160-4929.273" + cell $xor $xor$ls180.v:4929$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4818$721_Y - connect \Y $xor$ls180.v:4818$722_Y + connect \B $xor$ls180.v:4929$729_Y + connect \Y $xor$ls180.v:4929$730_Y end - attribute \src "ls180.v:4819.353-4819.425" - cell $xor $xor$ls180.v:4819$723 + attribute \src "ls180.v:4930.353-4930.425" + cell $xor $xor$ls180.v:4930$731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255412,10 +261033,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4819$723_Y + connect \Y $xor$ls180.v:4930$731_Y end - attribute \src "ls180.v:4819.200-4819.272" - cell $xor $xor$ls180.v:4819$724 + attribute \src "ls180.v:4930.200-4930.272" + cell $xor $xor$ls180.v:4930$732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255423,21 +261044,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4819$724_Y + connect \Y $xor$ls180.v:4930$732_Y end - attribute \src "ls180.v:4819.160-4819.273" - cell $xor $xor$ls180.v:4819$725 + attribute \src "ls180.v:4930.160-4930.273" + cell $xor $xor$ls180.v:4930$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4819$724_Y - connect \Y $xor$ls180.v:4819$725_Y + connect \B $xor$ls180.v:4930$732_Y + connect \Y $xor$ls180.v:4930$733_Y end - attribute \src "ls180.v:4820.353-4820.425" - cell $xor $xor$ls180.v:4820$726 + attribute \src "ls180.v:4931.353-4931.425" + cell $xor $xor$ls180.v:4931$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255445,10 +261066,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4820$726_Y + connect \Y $xor$ls180.v:4931$734_Y end - attribute \src "ls180.v:4820.200-4820.272" - cell $xor $xor$ls180.v:4820$727 + attribute \src "ls180.v:4931.200-4931.272" + cell $xor $xor$ls180.v:4931$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255456,21 +261077,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4820$727_Y + connect \Y $xor$ls180.v:4931$735_Y end - attribute \src "ls180.v:4820.160-4820.273" - cell $xor $xor$ls180.v:4820$728 + attribute \src "ls180.v:4931.160-4931.273" + cell $xor $xor$ls180.v:4931$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4820$727_Y - connect \Y $xor$ls180.v:4820$728_Y + connect \B $xor$ls180.v:4931$735_Y + connect \Y $xor$ls180.v:4931$736_Y end - attribute \src "ls180.v:4821.354-4821.426" - cell $xor $xor$ls180.v:4821$729 + attribute \src "ls180.v:4932.354-4932.426" + cell $xor $xor$ls180.v:4932$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255478,10 +261099,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4821$729_Y + connect \Y $xor$ls180.v:4932$737_Y end - attribute \src "ls180.v:4821.201-4821.273" - cell $xor $xor$ls180.v:4821$730 + attribute \src "ls180.v:4932.201-4932.273" + cell $xor $xor$ls180.v:4932$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255489,21 +261110,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4821$730_Y + connect \Y $xor$ls180.v:4932$738_Y end - attribute \src "ls180.v:4821.161-4821.274" - cell $xor $xor$ls180.v:4821$731 + attribute \src "ls180.v:4932.161-4932.274" + cell $xor $xor$ls180.v:4932$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4821$730_Y - connect \Y $xor$ls180.v:4821$731_Y + connect \B $xor$ls180.v:4932$738_Y + connect \Y $xor$ls180.v:4932$739_Y end - attribute \src "ls180.v:4822.361-4822.434" - cell $xor $xor$ls180.v:4822$732 + attribute \src "ls180.v:4933.361-4933.434" + cell $xor $xor$ls180.v:4933$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255511,10 +261132,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4822$732_Y + connect \Y $xor$ls180.v:4933$740_Y end - attribute \src "ls180.v:4822.205-4822.278" - cell $xor $xor$ls180.v:4822$733 + attribute \src "ls180.v:4933.205-4933.278" + cell $xor $xor$ls180.v:4933$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255522,21 +261143,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4822$733_Y + connect \Y $xor$ls180.v:4933$741_Y end - attribute \src "ls180.v:4822.164-4822.279" - cell $xor $xor$ls180.v:4822$734 + attribute \src "ls180.v:4933.164-4933.279" + cell $xor $xor$ls180.v:4933$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4822$733_Y - connect \Y $xor$ls180.v:4822$734_Y + connect \B $xor$ls180.v:4933$741_Y + connect \Y $xor$ls180.v:4933$742_Y end - attribute \src "ls180.v:4823.361-4823.434" - cell $xor $xor$ls180.v:4823$735 + attribute \src "ls180.v:4934.361-4934.434" + cell $xor $xor$ls180.v:4934$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255544,10 +261165,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4823$735_Y + connect \Y $xor$ls180.v:4934$743_Y end - attribute \src "ls180.v:4823.205-4823.278" - cell $xor $xor$ls180.v:4823$736 + attribute \src "ls180.v:4934.205-4934.278" + cell $xor $xor$ls180.v:4934$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255555,21 +261176,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4823$736_Y + connect \Y $xor$ls180.v:4934$744_Y end - attribute \src "ls180.v:4823.164-4823.279" - cell $xor $xor$ls180.v:4823$737 + attribute \src "ls180.v:4934.164-4934.279" + cell $xor $xor$ls180.v:4934$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4823$736_Y - connect \Y $xor$ls180.v:4823$737_Y + connect \B $xor$ls180.v:4934$744_Y + connect \Y $xor$ls180.v:4934$745_Y end - attribute \src "ls180.v:4824.361-4824.434" - cell $xor $xor$ls180.v:4824$738 + attribute \src "ls180.v:4935.361-4935.434" + cell $xor $xor$ls180.v:4935$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255577,10 +261198,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4824$738_Y + connect \Y $xor$ls180.v:4935$746_Y end - attribute \src "ls180.v:4824.205-4824.278" - cell $xor $xor$ls180.v:4824$739 + attribute \src "ls180.v:4935.205-4935.278" + cell $xor $xor$ls180.v:4935$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255588,21 +261209,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4824$739_Y + connect \Y $xor$ls180.v:4935$747_Y end - attribute \src "ls180.v:4824.164-4824.279" - cell $xor $xor$ls180.v:4824$740 + attribute \src "ls180.v:4935.164-4935.279" + cell $xor $xor$ls180.v:4935$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4824$739_Y - connect \Y $xor$ls180.v:4824$740_Y + connect \B $xor$ls180.v:4935$747_Y + connect \Y $xor$ls180.v:4935$748_Y end - attribute \src "ls180.v:4825.361-4825.434" - cell $xor $xor$ls180.v:4825$741 + attribute \src "ls180.v:4936.361-4936.434" + cell $xor $xor$ls180.v:4936$749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255610,10 +261231,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4825$741_Y + connect \Y $xor$ls180.v:4936$749_Y end - attribute \src "ls180.v:4825.205-4825.278" - cell $xor $xor$ls180.v:4825$742 + attribute \src "ls180.v:4936.205-4936.278" + cell $xor $xor$ls180.v:4936$750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255621,21 +261242,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4825$742_Y + connect \Y $xor$ls180.v:4936$750_Y end - attribute \src "ls180.v:4825.164-4825.279" - cell $xor $xor$ls180.v:4825$743 + attribute \src "ls180.v:4936.164-4936.279" + cell $xor $xor$ls180.v:4936$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4825$742_Y - connect \Y $xor$ls180.v:4825$743_Y + connect \B $xor$ls180.v:4936$750_Y + connect \Y $xor$ls180.v:4936$751_Y end - attribute \src "ls180.v:4826.361-4826.434" - cell $xor $xor$ls180.v:4826$744 + attribute \src "ls180.v:4937.361-4937.434" + cell $xor $xor$ls180.v:4937$752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255643,10 +261264,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4826$744_Y + connect \Y $xor$ls180.v:4937$752_Y end - attribute \src "ls180.v:4826.205-4826.278" - cell $xor $xor$ls180.v:4826$745 + attribute \src "ls180.v:4937.205-4937.278" + cell $xor $xor$ls180.v:4937$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255654,21 +261275,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4826$745_Y + connect \Y $xor$ls180.v:4937$753_Y end - attribute \src "ls180.v:4826.164-4826.279" - cell $xor $xor$ls180.v:4826$746 + attribute \src "ls180.v:4937.164-4937.279" + cell $xor $xor$ls180.v:4937$754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4826$745_Y - connect \Y $xor$ls180.v:4826$746_Y + connect \B $xor$ls180.v:4937$753_Y + connect \Y $xor$ls180.v:4937$754_Y end - attribute \src "ls180.v:4827.361-4827.434" - cell $xor $xor$ls180.v:4827$747 + attribute \src "ls180.v:4938.361-4938.434" + cell $xor $xor$ls180.v:4938$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255676,10 +261297,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4827$747_Y + connect \Y $xor$ls180.v:4938$755_Y end - attribute \src "ls180.v:4827.205-4827.278" - cell $xor $xor$ls180.v:4827$748 + attribute \src "ls180.v:4938.205-4938.278" + cell $xor $xor$ls180.v:4938$756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255687,21 +261308,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4827$748_Y + connect \Y $xor$ls180.v:4938$756_Y end - attribute \src "ls180.v:4827.164-4827.279" - cell $xor $xor$ls180.v:4827$749 + attribute \src "ls180.v:4938.164-4938.279" + cell $xor $xor$ls180.v:4938$757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4827$748_Y - connect \Y $xor$ls180.v:4827$749_Y + connect \B $xor$ls180.v:4938$756_Y + connect \Y $xor$ls180.v:4938$757_Y end - attribute \src "ls180.v:4828.361-4828.434" - cell $xor $xor$ls180.v:4828$750 + attribute \src "ls180.v:4939.361-4939.434" + cell $xor $xor$ls180.v:4939$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255709,10 +261330,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4828$750_Y + connect \Y $xor$ls180.v:4939$758_Y end - attribute \src "ls180.v:4828.205-4828.278" - cell $xor $xor$ls180.v:4828$751 + attribute \src "ls180.v:4939.205-4939.278" + cell $xor $xor$ls180.v:4939$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255720,21 +261341,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4828$751_Y + connect \Y $xor$ls180.v:4939$759_Y end - attribute \src "ls180.v:4828.164-4828.279" - cell $xor $xor$ls180.v:4828$752 + attribute \src "ls180.v:4939.164-4939.279" + cell $xor $xor$ls180.v:4939$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4828$751_Y - connect \Y $xor$ls180.v:4828$752_Y + connect \B $xor$ls180.v:4939$759_Y + connect \Y $xor$ls180.v:4939$760_Y end - attribute \src "ls180.v:4829.361-4829.434" - cell $xor $xor$ls180.v:4829$753 + attribute \src "ls180.v:4940.361-4940.434" + cell $xor $xor$ls180.v:4940$761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255742,10 +261363,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4829$753_Y + connect \Y $xor$ls180.v:4940$761_Y end - attribute \src "ls180.v:4829.205-4829.278" - cell $xor $xor$ls180.v:4829$754 + attribute \src "ls180.v:4940.205-4940.278" + cell $xor $xor$ls180.v:4940$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255753,21 +261374,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4829$754_Y + connect \Y $xor$ls180.v:4940$762_Y end - attribute \src "ls180.v:4829.164-4829.279" - cell $xor $xor$ls180.v:4829$755 + attribute \src "ls180.v:4940.164-4940.279" + cell $xor $xor$ls180.v:4940$763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4829$754_Y - connect \Y $xor$ls180.v:4829$755_Y + connect \B $xor$ls180.v:4940$762_Y + connect \Y $xor$ls180.v:4940$763_Y end - attribute \src "ls180.v:4830.361-4830.434" - cell $xor $xor$ls180.v:4830$756 + attribute \src "ls180.v:4941.361-4941.434" + cell $xor $xor$ls180.v:4941$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255775,10 +261396,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4830$756_Y + connect \Y $xor$ls180.v:4941$764_Y end - attribute \src "ls180.v:4830.205-4830.278" - cell $xor $xor$ls180.v:4830$757 + attribute \src "ls180.v:4941.205-4941.278" + cell $xor $xor$ls180.v:4941$765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255786,21 +261407,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4830$757_Y + connect \Y $xor$ls180.v:4941$765_Y end - attribute \src "ls180.v:4830.164-4830.279" - cell $xor $xor$ls180.v:4830$758 + attribute \src "ls180.v:4941.164-4941.279" + cell $xor $xor$ls180.v:4941$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4830$757_Y - connect \Y $xor$ls180.v:4830$758_Y + connect \B $xor$ls180.v:4941$765_Y + connect \Y $xor$ls180.v:4941$766_Y end - attribute \src "ls180.v:4831.361-4831.434" - cell $xor $xor$ls180.v:4831$759 + attribute \src "ls180.v:4942.361-4942.434" + cell $xor $xor$ls180.v:4942$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255808,10 +261429,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4831$759_Y + connect \Y $xor$ls180.v:4942$767_Y end - attribute \src "ls180.v:4831.205-4831.278" - cell $xor $xor$ls180.v:4831$760 + attribute \src "ls180.v:4942.205-4942.278" + cell $xor $xor$ls180.v:4942$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255819,21 +261440,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4831$760_Y + connect \Y $xor$ls180.v:4942$768_Y end - attribute \src "ls180.v:4831.164-4831.279" - cell $xor $xor$ls180.v:4831$761 + attribute \src "ls180.v:4942.164-4942.279" + cell $xor $xor$ls180.v:4942$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4831$760_Y - connect \Y $xor$ls180.v:4831$761_Y + connect \B $xor$ls180.v:4942$768_Y + connect \Y $xor$ls180.v:4942$769_Y end - attribute \src "ls180.v:4832.361-4832.434" - cell $xor $xor$ls180.v:4832$762 + attribute \src "ls180.v:4943.361-4943.434" + cell $xor $xor$ls180.v:4943$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255841,10 +261462,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4832$762_Y + connect \Y $xor$ls180.v:4943$770_Y end - attribute \src "ls180.v:4832.205-4832.278" - cell $xor $xor$ls180.v:4832$763 + attribute \src "ls180.v:4943.205-4943.278" + cell $xor $xor$ls180.v:4943$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255852,21 +261473,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4832$763_Y + connect \Y $xor$ls180.v:4943$771_Y end - attribute \src "ls180.v:4832.164-4832.279" - cell $xor $xor$ls180.v:4832$764 + attribute \src "ls180.v:4943.164-4943.279" + cell $xor $xor$ls180.v:4943$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4832$763_Y - connect \Y $xor$ls180.v:4832$764_Y + connect \B $xor$ls180.v:4943$771_Y + connect \Y $xor$ls180.v:4943$772_Y end - attribute \src "ls180.v:4833.361-4833.434" - cell $xor $xor$ls180.v:4833$765 + attribute \src "ls180.v:4944.361-4944.434" + cell $xor $xor$ls180.v:4944$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255874,10 +261495,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4833$765_Y + connect \Y $xor$ls180.v:4944$773_Y end - attribute \src "ls180.v:4833.205-4833.278" - cell $xor $xor$ls180.v:4833$766 + attribute \src "ls180.v:4944.205-4944.278" + cell $xor $xor$ls180.v:4944$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255885,21 +261506,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4833$766_Y + connect \Y $xor$ls180.v:4944$774_Y end - attribute \src "ls180.v:4833.164-4833.279" - cell $xor $xor$ls180.v:4833$767 + attribute \src "ls180.v:4944.164-4944.279" + cell $xor $xor$ls180.v:4944$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4833$766_Y - connect \Y $xor$ls180.v:4833$767_Y + connect \B $xor$ls180.v:4944$774_Y + connect \Y $xor$ls180.v:4944$775_Y end - attribute \src "ls180.v:4834.361-4834.434" - cell $xor $xor$ls180.v:4834$768 + attribute \src "ls180.v:4945.361-4945.434" + cell $xor $xor$ls180.v:4945$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255907,10 +261528,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4834$768_Y + connect \Y $xor$ls180.v:4945$776_Y end - attribute \src "ls180.v:4834.205-4834.278" - cell $xor $xor$ls180.v:4834$769 + attribute \src "ls180.v:4945.205-4945.278" + cell $xor $xor$ls180.v:4945$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255918,21 +261539,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4834$769_Y + connect \Y $xor$ls180.v:4945$777_Y end - attribute \src "ls180.v:4834.164-4834.279" - cell $xor $xor$ls180.v:4834$770 + attribute \src "ls180.v:4945.164-4945.279" + cell $xor $xor$ls180.v:4945$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4834$769_Y - connect \Y $xor$ls180.v:4834$770_Y + connect \B $xor$ls180.v:4945$777_Y + connect \Y $xor$ls180.v:4945$778_Y end - attribute \src "ls180.v:4835.361-4835.434" - cell $xor $xor$ls180.v:4835$771 + attribute \src "ls180.v:4946.361-4946.434" + cell $xor $xor$ls180.v:4946$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255940,10 +261561,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4835$771_Y + connect \Y $xor$ls180.v:4946$779_Y end - attribute \src "ls180.v:4835.205-4835.278" - cell $xor $xor$ls180.v:4835$772 + attribute \src "ls180.v:4946.205-4946.278" + cell $xor $xor$ls180.v:4946$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255951,21 +261572,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4835$772_Y + connect \Y $xor$ls180.v:4946$780_Y end - attribute \src "ls180.v:4835.164-4835.279" - cell $xor $xor$ls180.v:4835$773 + attribute \src "ls180.v:4946.164-4946.279" + cell $xor $xor$ls180.v:4946$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4835$772_Y - connect \Y $xor$ls180.v:4835$773_Y + connect \B $xor$ls180.v:4946$780_Y + connect \Y $xor$ls180.v:4946$781_Y end - attribute \src "ls180.v:4836.361-4836.434" - cell $xor $xor$ls180.v:4836$774 + attribute \src "ls180.v:4947.361-4947.434" + cell $xor $xor$ls180.v:4947$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255973,10 +261594,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4836$774_Y + connect \Y $xor$ls180.v:4947$782_Y end - attribute \src "ls180.v:4836.205-4836.278" - cell $xor $xor$ls180.v:4836$775 + attribute \src "ls180.v:4947.205-4947.278" + cell $xor $xor$ls180.v:4947$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255984,21 +261605,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4836$775_Y + connect \Y $xor$ls180.v:4947$783_Y end - attribute \src "ls180.v:4836.164-4836.279" - cell $xor $xor$ls180.v:4836$776 + attribute \src "ls180.v:4947.164-4947.279" + cell $xor $xor$ls180.v:4947$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4836$775_Y - connect \Y $xor$ls180.v:4836$776_Y + connect \B $xor$ls180.v:4947$783_Y + connect \Y $xor$ls180.v:4947$784_Y end - attribute \src "ls180.v:4837.361-4837.434" - cell $xor $xor$ls180.v:4837$777 + attribute \src "ls180.v:4948.361-4948.434" + cell $xor $xor$ls180.v:4948$785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256006,10 +261627,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4837$777_Y + connect \Y $xor$ls180.v:4948$785_Y end - attribute \src "ls180.v:4837.205-4837.278" - cell $xor $xor$ls180.v:4837$778 + attribute \src "ls180.v:4948.205-4948.278" + cell $xor $xor$ls180.v:4948$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256017,21 +261638,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4837$778_Y + connect \Y $xor$ls180.v:4948$786_Y end - attribute \src "ls180.v:4837.164-4837.279" - cell $xor $xor$ls180.v:4837$779 + attribute \src "ls180.v:4948.164-4948.279" + cell $xor $xor$ls180.v:4948$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4837$778_Y - connect \Y $xor$ls180.v:4837$779_Y + connect \B $xor$ls180.v:4948$786_Y + connect \Y $xor$ls180.v:4948$787_Y end - attribute \src "ls180.v:4838.361-4838.434" - cell $xor $xor$ls180.v:4838$780 + attribute \src "ls180.v:4949.361-4949.434" + cell $xor $xor$ls180.v:4949$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256039,10 +261660,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4838$780_Y + connect \Y $xor$ls180.v:4949$788_Y end - attribute \src "ls180.v:4838.205-4838.278" - cell $xor $xor$ls180.v:4838$781 + attribute \src "ls180.v:4949.205-4949.278" + cell $xor $xor$ls180.v:4949$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256050,21 +261671,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4838$781_Y + connect \Y $xor$ls180.v:4949$789_Y end - attribute \src "ls180.v:4838.164-4838.279" - cell $xor $xor$ls180.v:4838$782 + attribute \src "ls180.v:4949.164-4949.279" + cell $xor $xor$ls180.v:4949$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4838$781_Y - connect \Y $xor$ls180.v:4838$782_Y + connect \B $xor$ls180.v:4949$789_Y + connect \Y $xor$ls180.v:4949$790_Y end - attribute \src "ls180.v:4839.361-4839.434" - cell $xor $xor$ls180.v:4839$783 + attribute \src "ls180.v:4950.361-4950.434" + cell $xor $xor$ls180.v:4950$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256072,10 +261693,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4839$783_Y + connect \Y $xor$ls180.v:4950$791_Y end - attribute \src "ls180.v:4839.205-4839.278" - cell $xor $xor$ls180.v:4839$784 + attribute \src "ls180.v:4950.205-4950.278" + cell $xor $xor$ls180.v:4950$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256083,21 +261704,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4839$784_Y + connect \Y $xor$ls180.v:4950$792_Y end - attribute \src "ls180.v:4839.164-4839.279" - cell $xor $xor$ls180.v:4839$785 + attribute \src "ls180.v:4950.164-4950.279" + cell $xor $xor$ls180.v:4950$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4839$784_Y - connect \Y $xor$ls180.v:4839$785_Y + connect \B $xor$ls180.v:4950$792_Y + connect \Y $xor$ls180.v:4950$793_Y end - attribute \src "ls180.v:4840.361-4840.434" - cell $xor $xor$ls180.v:4840$786 + attribute \src "ls180.v:4951.361-4951.434" + cell $xor $xor$ls180.v:4951$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256105,10 +261726,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4840$786_Y + connect \Y $xor$ls180.v:4951$794_Y end - attribute \src "ls180.v:4840.205-4840.278" - cell $xor $xor$ls180.v:4840$787 + attribute \src "ls180.v:4951.205-4951.278" + cell $xor $xor$ls180.v:4951$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256116,21 +261737,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4840$787_Y + connect \Y $xor$ls180.v:4951$795_Y end - attribute \src "ls180.v:4840.164-4840.279" - cell $xor $xor$ls180.v:4840$788 + attribute \src "ls180.v:4951.164-4951.279" + cell $xor $xor$ls180.v:4951$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4840$787_Y - connect \Y $xor$ls180.v:4840$788_Y + connect \B $xor$ls180.v:4951$795_Y + connect \Y $xor$ls180.v:4951$796_Y end - attribute \src "ls180.v:4841.361-4841.434" - cell $xor $xor$ls180.v:4841$789 + attribute \src "ls180.v:4952.361-4952.434" + cell $xor $xor$ls180.v:4952$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256138,10 +261759,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4841$789_Y + connect \Y $xor$ls180.v:4952$797_Y end - attribute \src "ls180.v:4841.205-4841.278" - cell $xor $xor$ls180.v:4841$790 + attribute \src "ls180.v:4952.205-4952.278" + cell $xor $xor$ls180.v:4952$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256149,21 +261770,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4841$790_Y + connect \Y $xor$ls180.v:4952$798_Y end - attribute \src "ls180.v:4841.164-4841.279" - cell $xor $xor$ls180.v:4841$791 + attribute \src "ls180.v:4952.164-4952.279" + cell $xor $xor$ls180.v:4952$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4841$790_Y - connect \Y $xor$ls180.v:4841$791_Y + connect \B $xor$ls180.v:4952$798_Y + connect \Y $xor$ls180.v:4952$799_Y end - attribute \src "ls180.v:4842.360-4842.432" - cell $xor $xor$ls180.v:4842$792 + attribute \src "ls180.v:4953.360-4953.432" + cell $xor $xor$ls180.v:4953$800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256171,10 +261792,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4842$792_Y + connect \Y $xor$ls180.v:4953$800_Y end - attribute \src "ls180.v:4842.205-4842.277" - cell $xor $xor$ls180.v:4842$793 + attribute \src "ls180.v:4953.205-4953.277" + cell $xor $xor$ls180.v:4953$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256182,21 +261803,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4842$793_Y + connect \Y $xor$ls180.v:4953$801_Y end - attribute \src "ls180.v:4842.164-4842.278" - cell $xor $xor$ls180.v:4842$794 + attribute \src "ls180.v:4953.164-4953.278" + cell $xor $xor$ls180.v:4953$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4842$793_Y - connect \Y $xor$ls180.v:4842$794_Y + connect \B $xor$ls180.v:4953$801_Y + connect \Y $xor$ls180.v:4953$802_Y end - attribute \src "ls180.v:4843.360-4843.432" - cell $xor $xor$ls180.v:4843$795 + attribute \src "ls180.v:4954.360-4954.432" + cell $xor $xor$ls180.v:4954$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256204,10 +261825,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4843$795_Y + connect \Y $xor$ls180.v:4954$803_Y end - attribute \src "ls180.v:4843.205-4843.277" - cell $xor $xor$ls180.v:4843$796 + attribute \src "ls180.v:4954.205-4954.277" + cell $xor $xor$ls180.v:4954$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256215,21 +261836,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4843$796_Y + connect \Y $xor$ls180.v:4954$804_Y end - attribute \src "ls180.v:4843.164-4843.278" - cell $xor $xor$ls180.v:4843$797 + attribute \src "ls180.v:4954.164-4954.278" + cell $xor $xor$ls180.v:4954$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4843$796_Y - connect \Y $xor$ls180.v:4843$797_Y + connect \B $xor$ls180.v:4954$804_Y + connect \Y $xor$ls180.v:4954$805_Y end - attribute \src "ls180.v:4844.360-4844.432" - cell $xor $xor$ls180.v:4844$798 + attribute \src "ls180.v:4955.360-4955.432" + cell $xor $xor$ls180.v:4955$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256237,10 +261858,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4844$798_Y + connect \Y $xor$ls180.v:4955$806_Y end - attribute \src "ls180.v:4844.205-4844.277" - cell $xor $xor$ls180.v:4844$799 + attribute \src "ls180.v:4955.205-4955.277" + cell $xor $xor$ls180.v:4955$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256248,21 +261869,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4844$799_Y + connect \Y $xor$ls180.v:4955$807_Y end - attribute \src "ls180.v:4844.164-4844.278" - cell $xor $xor$ls180.v:4844$800 + attribute \src "ls180.v:4955.164-4955.278" + cell $xor $xor$ls180.v:4955$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4844$799_Y - connect \Y $xor$ls180.v:4844$800_Y + connect \B $xor$ls180.v:4955$807_Y + connect \Y $xor$ls180.v:4955$808_Y end - attribute \src "ls180.v:4845.360-4845.432" - cell $xor $xor$ls180.v:4845$801 + attribute \src "ls180.v:4956.360-4956.432" + cell $xor $xor$ls180.v:4956$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256270,10 +261891,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4845$801_Y + connect \Y $xor$ls180.v:4956$809_Y end - attribute \src "ls180.v:4845.205-4845.277" - cell $xor $xor$ls180.v:4845$802 + attribute \src "ls180.v:4956.205-4956.277" + cell $xor $xor$ls180.v:4956$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256281,21 +261902,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4845$802_Y + connect \Y $xor$ls180.v:4956$810_Y end - attribute \src "ls180.v:4845.164-4845.278" - cell $xor $xor$ls180.v:4845$803 + attribute \src "ls180.v:4956.164-4956.278" + cell $xor $xor$ls180.v:4956$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4845$802_Y - connect \Y $xor$ls180.v:4845$803_Y + connect \B $xor$ls180.v:4956$810_Y + connect \Y $xor$ls180.v:4956$811_Y end - attribute \src "ls180.v:4846.360-4846.432" - cell $xor $xor$ls180.v:4846$804 + attribute \src "ls180.v:4957.360-4957.432" + cell $xor $xor$ls180.v:4957$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256303,10 +261924,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4846$804_Y + connect \Y $xor$ls180.v:4957$812_Y end - attribute \src "ls180.v:4846.205-4846.277" - cell $xor $xor$ls180.v:4846$805 + attribute \src "ls180.v:4957.205-4957.277" + cell $xor $xor$ls180.v:4957$813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256314,21 +261935,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4846$805_Y + connect \Y $xor$ls180.v:4957$813_Y end - attribute \src "ls180.v:4846.164-4846.278" - cell $xor $xor$ls180.v:4846$806 + attribute \src "ls180.v:4957.164-4957.278" + cell $xor $xor$ls180.v:4957$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4846$805_Y - connect \Y $xor$ls180.v:4846$806_Y + connect \B $xor$ls180.v:4957$813_Y + connect \Y $xor$ls180.v:4957$814_Y end - attribute \src "ls180.v:4847.360-4847.432" - cell $xor $xor$ls180.v:4847$807 + attribute \src "ls180.v:4958.360-4958.432" + cell $xor $xor$ls180.v:4958$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256336,10 +261957,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4847$807_Y + connect \Y $xor$ls180.v:4958$815_Y end - attribute \src "ls180.v:4847.205-4847.277" - cell $xor $xor$ls180.v:4847$808 + attribute \src "ls180.v:4958.205-4958.277" + cell $xor $xor$ls180.v:4958$816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256347,21 +261968,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4847$808_Y + connect \Y $xor$ls180.v:4958$816_Y end - attribute \src "ls180.v:4847.164-4847.278" - cell $xor $xor$ls180.v:4847$809 + attribute \src "ls180.v:4958.164-4958.278" + cell $xor $xor$ls180.v:4958$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4847$808_Y - connect \Y $xor$ls180.v:4847$809_Y + connect \B $xor$ls180.v:4958$816_Y + connect \Y $xor$ls180.v:4958$817_Y end - attribute \src "ls180.v:4848.360-4848.432" - cell $xor $xor$ls180.v:4848$810 + attribute \src "ls180.v:4959.360-4959.432" + cell $xor $xor$ls180.v:4959$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256369,10 +261990,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4848$810_Y + connect \Y $xor$ls180.v:4959$818_Y end - attribute \src "ls180.v:4848.205-4848.277" - cell $xor $xor$ls180.v:4848$811 + attribute \src "ls180.v:4959.205-4959.277" + cell $xor $xor$ls180.v:4959$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256380,21 +262001,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4848$811_Y + connect \Y $xor$ls180.v:4959$819_Y end - attribute \src "ls180.v:4848.164-4848.278" - cell $xor $xor$ls180.v:4848$812 + attribute \src "ls180.v:4959.164-4959.278" + cell $xor $xor$ls180.v:4959$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4848$811_Y - connect \Y $xor$ls180.v:4848$812_Y + connect \B $xor$ls180.v:4959$819_Y + connect \Y $xor$ls180.v:4959$820_Y end - attribute \src "ls180.v:4849.360-4849.432" - cell $xor $xor$ls180.v:4849$813 + attribute \src "ls180.v:4960.360-4960.432" + cell $xor $xor$ls180.v:4960$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256402,10 +262023,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4849$813_Y + connect \Y $xor$ls180.v:4960$821_Y end - attribute \src "ls180.v:4849.205-4849.277" - cell $xor $xor$ls180.v:4849$814 + attribute \src "ls180.v:4960.205-4960.277" + cell $xor $xor$ls180.v:4960$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256413,21 +262034,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4849$814_Y + connect \Y $xor$ls180.v:4960$822_Y end - attribute \src "ls180.v:4849.164-4849.278" - cell $xor $xor$ls180.v:4849$815 + attribute \src "ls180.v:4960.164-4960.278" + cell $xor $xor$ls180.v:4960$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4849$814_Y - connect \Y $xor$ls180.v:4849$815_Y + connect \B $xor$ls180.v:4960$822_Y + connect \Y $xor$ls180.v:4960$823_Y end - attribute \src "ls180.v:4850.360-4850.432" - cell $xor $xor$ls180.v:4850$816 + attribute \src "ls180.v:4961.360-4961.432" + cell $xor $xor$ls180.v:4961$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256435,10 +262056,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4850$816_Y + connect \Y $xor$ls180.v:4961$824_Y end - attribute \src "ls180.v:4850.205-4850.277" - cell $xor $xor$ls180.v:4850$817 + attribute \src "ls180.v:4961.205-4961.277" + cell $xor $xor$ls180.v:4961$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256446,21 +262067,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4850$817_Y + connect \Y $xor$ls180.v:4961$825_Y end - attribute \src "ls180.v:4850.164-4850.278" - cell $xor $xor$ls180.v:4850$818 + attribute \src "ls180.v:4961.164-4961.278" + cell $xor $xor$ls180.v:4961$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4850$817_Y - connect \Y $xor$ls180.v:4850$818_Y + connect \B $xor$ls180.v:4961$825_Y + connect \Y $xor$ls180.v:4961$826_Y end - attribute \src "ls180.v:4851.360-4851.432" - cell $xor $xor$ls180.v:4851$819 + attribute \src "ls180.v:4962.360-4962.432" + cell $xor $xor$ls180.v:4962$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256468,10 +262089,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4851$819_Y + connect \Y $xor$ls180.v:4962$827_Y end - attribute \src "ls180.v:4851.205-4851.277" - cell $xor $xor$ls180.v:4851$820 + attribute \src "ls180.v:4962.205-4962.277" + cell $xor $xor$ls180.v:4962$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256479,21 +262100,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4851$820_Y + connect \Y $xor$ls180.v:4962$828_Y end - attribute \src "ls180.v:4851.164-4851.278" - cell $xor $xor$ls180.v:4851$821 + attribute \src "ls180.v:4962.164-4962.278" + cell $xor $xor$ls180.v:4962$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4851$820_Y - connect \Y $xor$ls180.v:4851$821_Y + connect \B $xor$ls180.v:4962$828_Y + connect \Y $xor$ls180.v:4962$829_Y end - attribute \src "ls180.v:4872.899-4872.983" - cell $xor $xor$ls180.v:4872$835 + attribute \src "ls180.v:4983.899-4983.983" + cell $xor $xor$ls180.v:4983$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256501,10 +262122,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4872$835_Y + connect \Y $xor$ls180.v:4983$843_Y end - attribute \src "ls180.v:4872.634-4872.718" - cell $xor $xor$ls180.v:4872$836 + attribute \src "ls180.v:4983.634-4983.718" + cell $xor $xor$ls180.v:4983$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256512,21 +262133,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4872$836_Y + connect \Y $xor$ls180.v:4983$844_Y end - attribute \src "ls180.v:4872.588-4872.719" - cell $xor $xor$ls180.v:4872$837 + attribute \src "ls180.v:4983.588-4983.719" + cell $xor $xor$ls180.v:4983$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4872$836_Y - connect \Y $xor$ls180.v:4872$837_Y + connect \B $xor$ls180.v:4983$844_Y + connect \Y $xor$ls180.v:4983$845_Y end - attribute \src "ls180.v:4872.234-4872.318" - cell $xor $xor$ls180.v:4872$838 + attribute \src "ls180.v:4983.234-4983.318" + cell $xor $xor$ls180.v:4983$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256534,21 +262155,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4872$838_Y + connect \Y $xor$ls180.v:4983$846_Y end - attribute \src "ls180.v:4872.187-4872.319" - cell $xor $xor$ls180.v:4872$839 + attribute \src "ls180.v:4983.187-4983.319" + cell $xor $xor$ls180.v:4983$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4872$838_Y - connect \Y $xor$ls180.v:4872$839_Y + connect \B $xor$ls180.v:4983$846_Y + connect \Y $xor$ls180.v:4983$847_Y end - attribute \src "ls180.v:4873.899-4873.983" - cell $xor $xor$ls180.v:4873$840 + attribute \src "ls180.v:4984.899-4984.983" + cell $xor $xor$ls180.v:4984$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256556,10 +262177,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4873$840_Y + connect \Y $xor$ls180.v:4984$848_Y end - attribute \src "ls180.v:4873.634-4873.718" - cell $xor $xor$ls180.v:4873$841 + attribute \src "ls180.v:4984.634-4984.718" + cell $xor $xor$ls180.v:4984$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256567,21 +262188,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4873$841_Y + connect \Y $xor$ls180.v:4984$849_Y end - attribute \src "ls180.v:4873.588-4873.719" - cell $xor $xor$ls180.v:4873$842 + attribute \src "ls180.v:4984.588-4984.719" + cell $xor $xor$ls180.v:4984$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4873$841_Y - connect \Y $xor$ls180.v:4873$842_Y + connect \B $xor$ls180.v:4984$849_Y + connect \Y $xor$ls180.v:4984$850_Y end - attribute \src "ls180.v:4873.234-4873.318" - cell $xor $xor$ls180.v:4873$843 + attribute \src "ls180.v:4984.234-4984.318" + cell $xor $xor$ls180.v:4984$851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256589,21 +262210,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4873$843_Y + connect \Y $xor$ls180.v:4984$851_Y end - attribute \src "ls180.v:4873.187-4873.319" - cell $xor $xor$ls180.v:4873$844 + attribute \src "ls180.v:4984.187-4984.319" + cell $xor $xor$ls180.v:4984$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4873$843_Y - connect \Y $xor$ls180.v:4873$844_Y + connect \B $xor$ls180.v:4984$851_Y + connect \Y $xor$ls180.v:4984$852_Y end - attribute \src "ls180.v:4882.899-4882.983" - cell $xor $xor$ls180.v:4882$846 + attribute \src "ls180.v:4993.899-4993.983" + cell $xor $xor$ls180.v:4993$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256611,10 +262232,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4882$846_Y + connect \Y $xor$ls180.v:4993$854_Y end - attribute \src "ls180.v:4882.634-4882.718" - cell $xor $xor$ls180.v:4882$847 + attribute \src "ls180.v:4993.634-4993.718" + cell $xor $xor$ls180.v:4993$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256622,21 +262243,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4882$847_Y + connect \Y $xor$ls180.v:4993$855_Y end - attribute \src "ls180.v:4882.588-4882.719" - cell $xor $xor$ls180.v:4882$848 + attribute \src "ls180.v:4993.588-4993.719" + cell $xor $xor$ls180.v:4993$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4882$847_Y - connect \Y $xor$ls180.v:4882$848_Y + connect \B $xor$ls180.v:4993$855_Y + connect \Y $xor$ls180.v:4993$856_Y end - attribute \src "ls180.v:4882.234-4882.318" - cell $xor $xor$ls180.v:4882$849 + attribute \src "ls180.v:4993.234-4993.318" + cell $xor $xor$ls180.v:4993$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256644,21 +262265,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4882$849_Y + connect \Y $xor$ls180.v:4993$857_Y end - attribute \src "ls180.v:4882.187-4882.319" - cell $xor $xor$ls180.v:4882$850 + attribute \src "ls180.v:4993.187-4993.319" + cell $xor $xor$ls180.v:4993$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4882$849_Y - connect \Y $xor$ls180.v:4882$850_Y + connect \B $xor$ls180.v:4993$857_Y + connect \Y $xor$ls180.v:4993$858_Y end - attribute \src "ls180.v:4883.899-4883.983" - cell $xor $xor$ls180.v:4883$851 + attribute \src "ls180.v:4994.899-4994.983" + cell $xor $xor$ls180.v:4994$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256666,10 +262287,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4883$851_Y + connect \Y $xor$ls180.v:4994$859_Y end - attribute \src "ls180.v:4883.634-4883.718" - cell $xor $xor$ls180.v:4883$852 + attribute \src "ls180.v:4994.634-4994.718" + cell $xor $xor$ls180.v:4994$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256677,21 +262298,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4883$852_Y + connect \Y $xor$ls180.v:4994$860_Y end - attribute \src "ls180.v:4883.588-4883.719" - cell $xor $xor$ls180.v:4883$853 + attribute \src "ls180.v:4994.588-4994.719" + cell $xor $xor$ls180.v:4994$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4883$852_Y - connect \Y $xor$ls180.v:4883$853_Y + connect \B $xor$ls180.v:4994$860_Y + connect \Y $xor$ls180.v:4994$861_Y end - attribute \src "ls180.v:4883.234-4883.318" - cell $xor $xor$ls180.v:4883$854 + attribute \src "ls180.v:4994.234-4994.318" + cell $xor $xor$ls180.v:4994$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256699,21 +262320,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4883$854_Y + connect \Y $xor$ls180.v:4994$862_Y end - attribute \src "ls180.v:4883.187-4883.319" - cell $xor $xor$ls180.v:4883$855 + attribute \src "ls180.v:4994.187-4994.319" + cell $xor $xor$ls180.v:4994$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4883$854_Y - connect \Y $xor$ls180.v:4883$855_Y + connect \B $xor$ls180.v:4994$862_Y + connect \Y $xor$ls180.v:4994$863_Y end - attribute \src "ls180.v:4892.899-4892.983" - cell $xor $xor$ls180.v:4892$857 + attribute \src "ls180.v:5003.899-5003.983" + cell $xor $xor$ls180.v:5003$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256721,10 +262342,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4892$857_Y + connect \Y $xor$ls180.v:5003$865_Y end - attribute \src "ls180.v:4892.634-4892.718" - cell $xor $xor$ls180.v:4892$858 + attribute \src "ls180.v:5003.634-5003.718" + cell $xor $xor$ls180.v:5003$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256732,21 +262353,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4892$858_Y + connect \Y $xor$ls180.v:5003$866_Y end - attribute \src "ls180.v:4892.588-4892.719" - cell $xor $xor$ls180.v:4892$859 + attribute \src "ls180.v:5003.588-5003.719" + cell $xor $xor$ls180.v:5003$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:4892$858_Y - connect \Y $xor$ls180.v:4892$859_Y + connect \B $xor$ls180.v:5003$866_Y + connect \Y $xor$ls180.v:5003$867_Y end - attribute \src "ls180.v:4892.234-4892.318" - cell $xor $xor$ls180.v:4892$860 + attribute \src "ls180.v:5003.234-5003.318" + cell $xor $xor$ls180.v:5003$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256754,21 +262375,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:4892$860_Y + connect \Y $xor$ls180.v:5003$868_Y end - attribute \src "ls180.v:4892.187-4892.319" - cell $xor $xor$ls180.v:4892$861 + attribute \src "ls180.v:5003.187-5003.319" + cell $xor $xor$ls180.v:5003$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:4892$860_Y - connect \Y $xor$ls180.v:4892$861_Y + connect \B $xor$ls180.v:5003$868_Y + connect \Y $xor$ls180.v:5003$869_Y end - attribute \src "ls180.v:4893.899-4893.983" - cell $xor $xor$ls180.v:4893$862 + attribute \src "ls180.v:5004.899-5004.983" + cell $xor $xor$ls180.v:5004$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256776,10 +262397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4893$862_Y + connect \Y $xor$ls180.v:5004$870_Y end - attribute \src "ls180.v:4893.634-4893.718" - cell $xor $xor$ls180.v:4893$863 + attribute \src "ls180.v:5004.634-5004.718" + cell $xor $xor$ls180.v:5004$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256787,21 +262408,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4893$863_Y + connect \Y $xor$ls180.v:5004$871_Y end - attribute \src "ls180.v:4893.588-4893.719" - cell $xor $xor$ls180.v:4893$864 + attribute \src "ls180.v:5004.588-5004.719" + cell $xor $xor$ls180.v:5004$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:4893$863_Y - connect \Y $xor$ls180.v:4893$864_Y + connect \B $xor$ls180.v:5004$871_Y + connect \Y $xor$ls180.v:5004$872_Y end - attribute \src "ls180.v:4893.234-4893.318" - cell $xor $xor$ls180.v:4893$865 + attribute \src "ls180.v:5004.234-5004.318" + cell $xor $xor$ls180.v:5004$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256809,21 +262430,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:4893$865_Y + connect \Y $xor$ls180.v:5004$873_Y end - attribute \src "ls180.v:4893.187-4893.319" - cell $xor $xor$ls180.v:4893$866 + attribute \src "ls180.v:5004.187-5004.319" + cell $xor $xor$ls180.v:5004$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:4893$865_Y - connect \Y $xor$ls180.v:4893$866_Y + connect \B $xor$ls180.v:5004$873_Y + connect \Y $xor$ls180.v:5004$874_Y end - attribute \src "ls180.v:4902.899-4902.983" - cell $xor $xor$ls180.v:4902$868 + attribute \src "ls180.v:5013.899-5013.983" + cell $xor $xor$ls180.v:5013$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256831,10 +262452,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4902$868_Y + connect \Y $xor$ls180.v:5013$876_Y end - attribute \src "ls180.v:4902.634-4902.718" - cell $xor $xor$ls180.v:4902$869 + attribute \src "ls180.v:5013.634-5013.718" + cell $xor $xor$ls180.v:5013$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256842,21 +262463,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4902$869_Y + connect \Y $xor$ls180.v:5013$877_Y end - attribute \src "ls180.v:4902.588-4902.719" - cell $xor $xor$ls180.v:4902$870 + attribute \src "ls180.v:5013.588-5013.719" + cell $xor $xor$ls180.v:5013$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:4902$869_Y - connect \Y $xor$ls180.v:4902$870_Y + connect \B $xor$ls180.v:5013$877_Y + connect \Y $xor$ls180.v:5013$878_Y end - attribute \src "ls180.v:4902.234-4902.318" - cell $xor $xor$ls180.v:4902$871 + attribute \src "ls180.v:5013.234-5013.318" + cell $xor $xor$ls180.v:5013$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256864,21 +262485,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:4902$871_Y + connect \Y $xor$ls180.v:5013$879_Y end - attribute \src "ls180.v:4902.187-4902.319" - cell $xor $xor$ls180.v:4902$872 + attribute \src "ls180.v:5013.187-5013.319" + cell $xor $xor$ls180.v:5013$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:4902$871_Y - connect \Y $xor$ls180.v:4902$872_Y + connect \B $xor$ls180.v:5013$879_Y + connect \Y $xor$ls180.v:5013$880_Y end - attribute \src "ls180.v:4903.899-4903.983" - cell $xor $xor$ls180.v:4903$873 + attribute \src "ls180.v:5014.899-5014.983" + cell $xor $xor$ls180.v:5014$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256886,10 +262507,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4903$873_Y + connect \Y $xor$ls180.v:5014$881_Y end - attribute \src "ls180.v:4903.634-4903.718" - cell $xor $xor$ls180.v:4903$874 + attribute \src "ls180.v:5014.634-5014.718" + cell $xor $xor$ls180.v:5014$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256897,21 +262518,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4903$874_Y + connect \Y $xor$ls180.v:5014$882_Y end - attribute \src "ls180.v:4903.588-4903.719" - cell $xor $xor$ls180.v:4903$875 + attribute \src "ls180.v:5014.588-5014.719" + cell $xor $xor$ls180.v:5014$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:4903$874_Y - connect \Y $xor$ls180.v:4903$875_Y + connect \B $xor$ls180.v:5014$882_Y + connect \Y $xor$ls180.v:5014$883_Y end - attribute \src "ls180.v:4903.234-4903.318" - cell $xor $xor$ls180.v:4903$876 + attribute \src "ls180.v:5014.234-5014.318" + cell $xor $xor$ls180.v:5014$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256919,21 +262540,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:4903$876_Y + connect \Y $xor$ls180.v:5014$884_Y end - attribute \src "ls180.v:4903.187-4903.319" - cell $xor $xor$ls180.v:4903$877 + attribute \src "ls180.v:5014.187-5014.319" + cell $xor $xor$ls180.v:5014$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:4903$876_Y - connect \Y $xor$ls180.v:4903$877_Y + connect \B $xor$ls180.v:5014$884_Y + connect \Y $xor$ls180.v:5014$885_Y end - attribute \src "ls180.v:5054.879-5054.961" - cell $xor $xor$ls180.v:5054$910 + attribute \src "ls180.v:5165.879-5165.961" + cell $xor $xor$ls180.v:5165$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256941,10 +262562,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5054$910_Y + connect \Y $xor$ls180.v:5165$918_Y end - attribute \src "ls180.v:5054.620-5054.702" - cell $xor $xor$ls180.v:5054$911 + attribute \src "ls180.v:5165.620-5165.702" + cell $xor $xor$ls180.v:5165$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256952,21 +262573,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5054$911_Y + connect \Y $xor$ls180.v:5165$919_Y end - attribute \src "ls180.v:5054.575-5054.703" - cell $xor $xor$ls180.v:5054$912 + attribute \src "ls180.v:5165.575-5165.703" + cell $xor $xor$ls180.v:5165$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5054$911_Y - connect \Y $xor$ls180.v:5054$912_Y + connect \B $xor$ls180.v:5165$919_Y + connect \Y $xor$ls180.v:5165$920_Y end - attribute \src "ls180.v:5054.229-5054.311" - cell $xor $xor$ls180.v:5054$913 + attribute \src "ls180.v:5165.229-5165.311" + cell $xor $xor$ls180.v:5165$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256974,21 +262595,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5054$913_Y + connect \Y $xor$ls180.v:5165$921_Y end - attribute \src "ls180.v:5054.183-5054.312" - cell $xor $xor$ls180.v:5054$914 + attribute \src "ls180.v:5165.183-5165.312" + cell $xor $xor$ls180.v:5165$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5054$913_Y - connect \Y $xor$ls180.v:5054$914_Y + connect \B $xor$ls180.v:5165$921_Y + connect \Y $xor$ls180.v:5165$922_Y end - attribute \src "ls180.v:5055.879-5055.961" - cell $xor $xor$ls180.v:5055$915 + attribute \src "ls180.v:5166.879-5166.961" + cell $xor $xor$ls180.v:5166$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256996,10 +262617,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5055$915_Y + connect \Y $xor$ls180.v:5166$923_Y end - attribute \src "ls180.v:5055.620-5055.702" - cell $xor $xor$ls180.v:5055$916 + attribute \src "ls180.v:5166.620-5166.702" + cell $xor $xor$ls180.v:5166$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257007,21 +262628,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5055$916_Y + connect \Y $xor$ls180.v:5166$924_Y end - attribute \src "ls180.v:5055.575-5055.703" - cell $xor $xor$ls180.v:5055$917 + attribute \src "ls180.v:5166.575-5166.703" + cell $xor $xor$ls180.v:5166$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5055$916_Y - connect \Y $xor$ls180.v:5055$917_Y + connect \B $xor$ls180.v:5166$924_Y + connect \Y $xor$ls180.v:5166$925_Y end - attribute \src "ls180.v:5055.229-5055.311" - cell $xor $xor$ls180.v:5055$918 + attribute \src "ls180.v:5166.229-5166.311" + cell $xor $xor$ls180.v:5166$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257029,21 +262650,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5055$918_Y + connect \Y $xor$ls180.v:5166$926_Y end - attribute \src "ls180.v:5055.183-5055.312" - cell $xor $xor$ls180.v:5055$919 + attribute \src "ls180.v:5166.183-5166.312" + cell $xor $xor$ls180.v:5166$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5055$918_Y - connect \Y $xor$ls180.v:5055$919_Y + connect \B $xor$ls180.v:5166$926_Y + connect \Y $xor$ls180.v:5166$927_Y end - attribute \src "ls180.v:5064.879-5064.961" - cell $xor $xor$ls180.v:5064$921 + attribute \src "ls180.v:5175.879-5175.961" + cell $xor $xor$ls180.v:5175$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257051,10 +262672,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5064$921_Y + connect \Y $xor$ls180.v:5175$929_Y end - attribute \src "ls180.v:5064.620-5064.702" - cell $xor $xor$ls180.v:5064$922 + attribute \src "ls180.v:5175.620-5175.702" + cell $xor $xor$ls180.v:5175$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257062,21 +262683,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5064$922_Y + connect \Y $xor$ls180.v:5175$930_Y end - attribute \src "ls180.v:5064.575-5064.703" - cell $xor $xor$ls180.v:5064$923 + attribute \src "ls180.v:5175.575-5175.703" + cell $xor $xor$ls180.v:5175$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5064$922_Y - connect \Y $xor$ls180.v:5064$923_Y + connect \B $xor$ls180.v:5175$930_Y + connect \Y $xor$ls180.v:5175$931_Y end - attribute \src "ls180.v:5064.229-5064.311" - cell $xor $xor$ls180.v:5064$924 + attribute \src "ls180.v:5175.229-5175.311" + cell $xor $xor$ls180.v:5175$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257084,21 +262705,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5064$924_Y + connect \Y $xor$ls180.v:5175$932_Y end - attribute \src "ls180.v:5064.183-5064.312" - cell $xor $xor$ls180.v:5064$925 + attribute \src "ls180.v:5175.183-5175.312" + cell $xor $xor$ls180.v:5175$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5064$924_Y - connect \Y $xor$ls180.v:5064$925_Y + connect \B $xor$ls180.v:5175$932_Y + connect \Y $xor$ls180.v:5175$933_Y end - attribute \src "ls180.v:5065.879-5065.961" - cell $xor $xor$ls180.v:5065$926 + attribute \src "ls180.v:5176.879-5176.961" + cell $xor $xor$ls180.v:5176$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257106,10 +262727,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5065$926_Y + connect \Y $xor$ls180.v:5176$934_Y end - attribute \src "ls180.v:5065.620-5065.702" - cell $xor $xor$ls180.v:5065$927 + attribute \src "ls180.v:5176.620-5176.702" + cell $xor $xor$ls180.v:5176$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257117,21 +262738,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5065$927_Y + connect \Y $xor$ls180.v:5176$935_Y end - attribute \src "ls180.v:5065.575-5065.703" - cell $xor $xor$ls180.v:5065$928 + attribute \src "ls180.v:5176.575-5176.703" + cell $xor $xor$ls180.v:5176$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5065$927_Y - connect \Y $xor$ls180.v:5065$928_Y + connect \B $xor$ls180.v:5176$935_Y + connect \Y $xor$ls180.v:5176$936_Y end - attribute \src "ls180.v:5065.229-5065.311" - cell $xor $xor$ls180.v:5065$929 + attribute \src "ls180.v:5176.229-5176.311" + cell $xor $xor$ls180.v:5176$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257139,21 +262760,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5065$929_Y + connect \Y $xor$ls180.v:5176$937_Y end - attribute \src "ls180.v:5065.183-5065.312" - cell $xor $xor$ls180.v:5065$930 + attribute \src "ls180.v:5176.183-5176.312" + cell $xor $xor$ls180.v:5176$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5065$929_Y - connect \Y $xor$ls180.v:5065$930_Y + connect \B $xor$ls180.v:5176$937_Y + connect \Y $xor$ls180.v:5176$938_Y end - attribute \src "ls180.v:5074.879-5074.961" - cell $xor $xor$ls180.v:5074$932 + attribute \src "ls180.v:5185.879-5185.961" + cell $xor $xor$ls180.v:5185$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257161,10 +262782,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5074$932_Y + connect \Y $xor$ls180.v:5185$940_Y end - attribute \src "ls180.v:5074.620-5074.702" - cell $xor $xor$ls180.v:5074$933 + attribute \src "ls180.v:5185.620-5185.702" + cell $xor $xor$ls180.v:5185$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257172,21 +262793,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5074$933_Y + connect \Y $xor$ls180.v:5185$941_Y end - attribute \src "ls180.v:5074.575-5074.703" - cell $xor $xor$ls180.v:5074$934 + attribute \src "ls180.v:5185.575-5185.703" + cell $xor $xor$ls180.v:5185$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5074$933_Y - connect \Y $xor$ls180.v:5074$934_Y + connect \B $xor$ls180.v:5185$941_Y + connect \Y $xor$ls180.v:5185$942_Y end - attribute \src "ls180.v:5074.229-5074.311" - cell $xor $xor$ls180.v:5074$935 + attribute \src "ls180.v:5185.229-5185.311" + cell $xor $xor$ls180.v:5185$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257194,21 +262815,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5074$935_Y + connect \Y $xor$ls180.v:5185$943_Y end - attribute \src "ls180.v:5074.183-5074.312" - cell $xor $xor$ls180.v:5074$936 + attribute \src "ls180.v:5185.183-5185.312" + cell $xor $xor$ls180.v:5185$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5074$935_Y - connect \Y $xor$ls180.v:5074$936_Y + connect \B $xor$ls180.v:5185$943_Y + connect \Y $xor$ls180.v:5185$944_Y end - attribute \src "ls180.v:5075.879-5075.961" - cell $xor $xor$ls180.v:5075$937 + attribute \src "ls180.v:5186.879-5186.961" + cell $xor $xor$ls180.v:5186$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257216,10 +262837,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5075$937_Y + connect \Y $xor$ls180.v:5186$945_Y end - attribute \src "ls180.v:5075.620-5075.702" - cell $xor $xor$ls180.v:5075$938 + attribute \src "ls180.v:5186.620-5186.702" + cell $xor $xor$ls180.v:5186$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257227,21 +262848,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5075$938_Y + connect \Y $xor$ls180.v:5186$946_Y end - attribute \src "ls180.v:5075.575-5075.703" - cell $xor $xor$ls180.v:5075$939 + attribute \src "ls180.v:5186.575-5186.703" + cell $xor $xor$ls180.v:5186$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5075$938_Y - connect \Y $xor$ls180.v:5075$939_Y + connect \B $xor$ls180.v:5186$946_Y + connect \Y $xor$ls180.v:5186$947_Y end - attribute \src "ls180.v:5075.229-5075.311" - cell $xor $xor$ls180.v:5075$940 + attribute \src "ls180.v:5186.229-5186.311" + cell $xor $xor$ls180.v:5186$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257249,21 +262870,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5075$940_Y + connect \Y $xor$ls180.v:5186$948_Y end - attribute \src "ls180.v:5075.183-5075.312" - cell $xor $xor$ls180.v:5075$941 + attribute \src "ls180.v:5186.183-5186.312" + cell $xor $xor$ls180.v:5186$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5075$940_Y - connect \Y $xor$ls180.v:5075$941_Y + connect \B $xor$ls180.v:5186$948_Y + connect \Y $xor$ls180.v:5186$949_Y end - attribute \src "ls180.v:5084.879-5084.961" - cell $xor $xor$ls180.v:5084$943 + attribute \src "ls180.v:5195.879-5195.961" + cell $xor $xor$ls180.v:5195$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257271,10 +262892,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5084$943_Y + connect \Y $xor$ls180.v:5195$951_Y end - attribute \src "ls180.v:5084.620-5084.702" - cell $xor $xor$ls180.v:5084$944 + attribute \src "ls180.v:5195.620-5195.702" + cell $xor $xor$ls180.v:5195$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257282,21 +262903,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5084$944_Y + connect \Y $xor$ls180.v:5195$952_Y end - attribute \src "ls180.v:5084.575-5084.703" - cell $xor $xor$ls180.v:5084$945 + attribute \src "ls180.v:5195.575-5195.703" + cell $xor $xor$ls180.v:5195$953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5084$944_Y - connect \Y $xor$ls180.v:5084$945_Y + connect \B $xor$ls180.v:5195$952_Y + connect \Y $xor$ls180.v:5195$953_Y end - attribute \src "ls180.v:5084.229-5084.311" - cell $xor $xor$ls180.v:5084$946 + attribute \src "ls180.v:5195.229-5195.311" + cell $xor $xor$ls180.v:5195$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257304,21 +262925,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5084$946_Y + connect \Y $xor$ls180.v:5195$954_Y end - attribute \src "ls180.v:5084.183-5084.312" - cell $xor $xor$ls180.v:5084$947 + attribute \src "ls180.v:5195.183-5195.312" + cell $xor $xor$ls180.v:5195$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5084$946_Y - connect \Y $xor$ls180.v:5084$947_Y + connect \B $xor$ls180.v:5195$954_Y + connect \Y $xor$ls180.v:5195$955_Y end - attribute \src "ls180.v:5085.879-5085.961" - cell $xor $xor$ls180.v:5085$948 + attribute \src "ls180.v:5196.879-5196.961" + cell $xor $xor$ls180.v:5196$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257326,10 +262947,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5085$948_Y + connect \Y $xor$ls180.v:5196$956_Y end - attribute \src "ls180.v:5085.620-5085.702" - cell $xor $xor$ls180.v:5085$949 + attribute \src "ls180.v:5196.620-5196.702" + cell $xor $xor$ls180.v:5196$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257337,21 +262958,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5085$949_Y + connect \Y $xor$ls180.v:5196$957_Y end - attribute \src "ls180.v:5085.575-5085.703" - cell $xor $xor$ls180.v:5085$950 + attribute \src "ls180.v:5196.575-5196.703" + cell $xor $xor$ls180.v:5196$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5085$949_Y - connect \Y $xor$ls180.v:5085$950_Y + connect \B $xor$ls180.v:5196$957_Y + connect \Y $xor$ls180.v:5196$958_Y end - attribute \src "ls180.v:5085.229-5085.311" - cell $xor $xor$ls180.v:5085$951 + attribute \src "ls180.v:5196.229-5196.311" + cell $xor $xor$ls180.v:5196$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257359,21 +262980,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5085$951_Y + connect \Y $xor$ls180.v:5196$959_Y end - attribute \src "ls180.v:5085.183-5085.312" - cell $xor $xor$ls180.v:5085$952 + attribute \src "ls180.v:5196.183-5196.312" + cell $xor $xor$ls180.v:5196$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5085$951_Y - connect \Y $xor$ls180.v:5085$952_Y + connect \B $xor$ls180.v:5196$959_Y + connect \Y $xor$ls180.v:5196$960_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10113.13-10280.2" + attribute \src "ls180.v:10192.13-10569.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -257381,6 +263002,7 @@ module \ls180 connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms connect \busy_o \main_libresocsim_libresoc0 connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel connect \core_bigendian_i 1'0 connect \dbus__ack \main_libresocsim_libresoc_dbus_ack connect \dbus__adr \main_libresocsim_libresoc_dbus_adr @@ -257393,102 +263015,108 @@ module \ls180 connect \dbus__sel \main_libresocsim_libresoc_dbus_sel connect \dbus__stb \main_libresocsim_libresoc_dbus_stb connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \gpio_gpio0__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [0] - connect \gpio_gpio0__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [0] - connect \gpio_gpio0__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [0] - connect \gpio_gpio0__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [0] - connect \gpio_gpio0__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [0] - connect \gpio_gpio0__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [0] - connect \gpio_gpio10__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [10] - connect \gpio_gpio10__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [10] - connect \gpio_gpio10__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [10] - connect \gpio_gpio10__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [10] - connect \gpio_gpio10__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [10] - connect \gpio_gpio10__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [10] - connect \gpio_gpio11__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [11] - connect \gpio_gpio11__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [11] - connect \gpio_gpio11__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [11] - connect \gpio_gpio11__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [11] - connect \gpio_gpio11__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [11] - connect \gpio_gpio11__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [11] - connect \gpio_gpio12__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [12] - connect \gpio_gpio12__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [12] - connect \gpio_gpio12__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [12] - connect \gpio_gpio12__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [12] - connect \gpio_gpio12__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [12] - connect \gpio_gpio12__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [12] - connect \gpio_gpio13__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [13] - connect \gpio_gpio13__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [13] - connect \gpio_gpio13__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [13] - connect \gpio_gpio13__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [13] - connect \gpio_gpio13__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [13] - connect \gpio_gpio13__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [13] - connect \gpio_gpio14__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [14] - connect \gpio_gpio14__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [14] - connect \gpio_gpio14__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [14] - connect \gpio_gpio14__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [14] - connect \gpio_gpio14__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [14] - connect \gpio_gpio14__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [14] - connect \gpio_gpio15__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [15] - connect \gpio_gpio15__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [15] - connect \gpio_gpio15__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [15] - connect \gpio_gpio15__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [15] - connect \gpio_gpio15__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [15] - connect \gpio_gpio15__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [15] - connect \gpio_gpio1__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [1] - connect \gpio_gpio1__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [1] - connect \gpio_gpio1__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [1] - connect \gpio_gpio1__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [1] - connect \gpio_gpio1__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [1] - connect \gpio_gpio1__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [1] - connect \gpio_gpio2__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [2] - connect \gpio_gpio2__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [2] - connect \gpio_gpio2__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [2] - connect \gpio_gpio2__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [2] - connect \gpio_gpio2__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [2] - connect \gpio_gpio2__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [2] - connect \gpio_gpio3__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [3] - connect \gpio_gpio3__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [3] - connect \gpio_gpio3__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [3] - connect \gpio_gpio3__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [3] - connect \gpio_gpio3__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [3] - connect \gpio_gpio3__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [3] - connect \gpio_gpio4__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [4] - connect \gpio_gpio4__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [4] - connect \gpio_gpio4__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [4] - connect \gpio_gpio4__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [4] - connect \gpio_gpio4__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [4] - connect \gpio_gpio4__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [4] - connect \gpio_gpio5__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [5] - connect \gpio_gpio5__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [5] - connect \gpio_gpio5__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [5] - connect \gpio_gpio5__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [5] - connect \gpio_gpio5__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [5] - connect \gpio_gpio5__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [5] - connect \gpio_gpio6__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [6] - connect \gpio_gpio6__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [6] - connect \gpio_gpio6__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [6] - connect \gpio_gpio6__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [6] - connect \gpio_gpio6__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [6] - connect \gpio_gpio6__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [6] - connect \gpio_gpio7__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [7] - connect \gpio_gpio7__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [7] - connect \gpio_gpio7__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [7] - connect \gpio_gpio7__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [7] - connect \gpio_gpio7__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [7] - connect \gpio_gpio7__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [7] - connect \gpio_gpio8__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [8] - connect \gpio_gpio8__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [8] - connect \gpio_gpio8__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [8] - connect \gpio_gpio8__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [8] - connect \gpio_gpio8__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [8] - connect \gpio_gpio8__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [8] - connect \gpio_gpio9__core__i \main_libresocsim_libresoc_constraintmanager0_gpio0_i [9] - connect \gpio_gpio9__core__o \main_libresocsim_libresoc_constraintmanager0_gpio0_o [9] - connect \gpio_gpio9__core__oe \main_libresocsim_libresoc_constraintmanager0_gpio0_oe [9] - connect \gpio_gpio9__pad__i \main_libresocsim_libresoc_constraintmanager1_gpio0_i [9] - connect \gpio_gpio9__pad__o \main_libresocsim_libresoc_constraintmanager1_gpio0_o [9] - connect \gpio_gpio9__pad__oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe [9] + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] connect \ibus__ack \main_libresocsim_libresoc_ibus_ack connect \ibus__adr \main_libresocsim_libresoc_ibus_adr connect \ibus__bte \main_libresocsim_libresoc_ibus_bte @@ -257533,5215 +263161,5674 @@ module \ls180 connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe connect \pc_i 1'0 connect \pc_i_ok 1'0 connect \pc_o \main_libresocsim_libresoc2 - connect \rst $or$ls180.v:10195$2752_Y - connect \uart_rx__core__i \main_libresocsim_libresoc_constraintmanager0_uart0_rx - connect \uart_rx__pad__i \main_libresocsim_libresoc_constraintmanager1_uart0_rx - connect \uart_tx__core__o \main_libresocsim_libresoc_constraintmanager0_uart0_tx - connect \uart_tx__pad__o \main_libresocsim_libresoc_constraintmanager1_uart0_tx + connect \pll_48_o \main_libresocsim_libresoc_pll_48_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10292$2762_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_cmd_i + connect \sd0_data0__core__o \sdcard_cmd_o + connect \sd0_data0__core__oe \sdcard_cmd_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data1__core__i \sdcard_cmd_i + connect \sd0_data1__core__o \sdcard_cmd_o + connect \sd0_data1__core__oe \sdcard_cmd_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data2__core__i \sdcard_cmd_i + connect \sd0_data2__core__o \sdcard_cmd_o + connect \sd0_data2__core__oe \sdcard_cmd_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data3__core__i \sdcard_cmd_i + connect \sd0_data3__core__o \sdcard_cmd_o + connect \sd0_data3__core__oe \sdcard_cmd_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__i \sdram_dq_i [1] + connect \sdr_dm_1__core__o \sdram_dq_o [1] + connect \sdr_dm_1__core__oe \sdram_dq_oe + connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3701 + process $proc$ls180.v:0$3720 sync always sync init end - attribute \src "ls180.v:10003.1-10004.4" - process $proc$ls180.v:10003$2701 - sync posedge \sys_clk_1 + attribute \src "ls180.v:1001.12-1001.44" + process $proc$ls180.v:1001$3148 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end - attribute \src "ls180.v:1001.12-1001.37" - process $proc$ls180.v:1001$3150 + attribute \src "ls180.v:1002.5-1002.31" + process $proc$ls180.v:1002$3149 assign { } { } - assign $1\main_pwm0_counter[31:0] 0 + assign $1\main_spimaster12_re[0:0] 1'0 sync always sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] + update \main_spimaster12_re $1\main_spimaster12_re[0:0] end - attribute \src "ls180.v:10011.1-10015.4" - process $proc$ls180.v:10011$2703 + attribute \src "ls180.v:10056.1-10066.4" + process $proc$ls180.v:10056$2692 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 3'xxx - assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10014$2707_DATA - attribute \src "ls180.v:10012.2-10013.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10012.6-10012.60" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 0 + assign $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 0 + assign $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 0 + assign $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:10057.2-10058.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10057.6-10057.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 255 + case + end + attribute \src "ls180.v:10059.2-10060.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10059.6-10059.28" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 25'1111111111111111111111111 + assign $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 65280 + case + end + attribute \src "ls180.v:10061.2-10062.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10061.6-10061.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 16711680 + case + end + attribute \src "ls180.v:10063.2-10064.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10063.6-10063.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 32'11111111000000000000000000000000 case end sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10013$6_ADDR $0$memwr$\storage_1$ls180.v:10013$6_ADDR[2:0]$2704 - update $memwr$\storage_1$ls180.v:10013$6_DATA $0$memwr$\storage_1$ls180.v:10013$6_DATA[24:0]$2705 - update $memwr$\storage_1$ls180.v:10013$6_EN $0$memwr$\storage_1$ls180.v:10013$6_EN[24:0]$2706 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:10058$1_ADDR $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 + update $memwr$\mem$ls180.v:10058$1_DATA $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 + update $memwr$\mem$ls180.v:10058$1_EN $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 + update $memwr$\mem$ls180.v:10060$2_ADDR $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 + update $memwr$\mem$ls180.v:10060$2_DATA $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 + update $memwr$\mem$ls180.v:10060$2_EN $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 + update $memwr$\mem$ls180.v:10062$3_ADDR $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 + update $memwr$\mem$ls180.v:10062$3_DATA $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 + update $memwr$\mem$ls180.v:10062$3_EN $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 + update $memwr$\mem$ls180.v:10064$4_ADDR $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 + update $memwr$\mem$ls180.v:10064$4_DATA $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 + update $memwr$\mem$ls180.v:10064$4_EN $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 end - attribute \src "ls180.v:10017.1-10018.4" - process $proc$ls180.v:10017$2708 - sync posedge \sys_clk_1 + attribute \src "ls180.v:1006.11-1006.42" + process $proc$ls180.v:1006$3150 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] end - attribute \src "ls180.v:1002.5-1002.36" - process $proc$ls180.v:1002$3151 + attribute \src "ls180.v:1007.5-1007.31" + process $proc$ls180.v:1007$3151 assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 + assign $1\main_spimaster17_re[0:0] 1'0 sync always sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + update \main_spimaster17_re $1\main_spimaster17_re[0:0] end - attribute \src "ls180.v:10025.1-10029.4" - process $proc$ls180.v:10025$2710 + attribute \src "ls180.v:10076.1-10080.4" + process $proc$ls180.v:10076$2706 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 3'xxx - assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10028$2714_DATA - attribute \src "ls180.v:10026.2-10027.131" + assign $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 3'xxx + assign $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10079$2710_DATA + attribute \src "ls180.v:10077.2-10078.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10077.6-10077.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10078$5_ADDR $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 + update $memwr$\storage$ls180.v:10078$5_DATA $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 + update $memwr$\storage$ls180.v:10078$5_EN $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 + end + attribute \src "ls180.v:10082.1-10083.4" + process $proc$ls180.v:10082$2711 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10090.1-10094.4" + process $proc$ls180.v:10090$2713 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 3'xxx + assign $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10093$2717_DATA + attribute \src "ls180.v:10091.2-10092.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10091.6-10091.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10092$6_ADDR $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 + update $memwr$\storage_1$ls180.v:10092$6_DATA $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 + update $memwr$\storage_1$ls180.v:10092$6_EN $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 + end + attribute \src "ls180.v:10096.1-10097.4" + process $proc$ls180.v:10096$2718 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10104.1-10108.4" + process $proc$ls180.v:10104$2720 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 3'xxx + assign $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10107$2724_DATA + attribute \src "ls180.v:10105.2-10106.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10026.6-10026.60" + attribute \src "ls180.v:10105.6-10105.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10027$7_ADDR $0$memwr$\storage_2$ls180.v:10027$7_ADDR[2:0]$2711 - update $memwr$\storage_2$ls180.v:10027$7_DATA $0$memwr$\storage_2$ls180.v:10027$7_DATA[24:0]$2712 - update $memwr$\storage_2$ls180.v:10027$7_EN $0$memwr$\storage_2$ls180.v:10027$7_EN[24:0]$2713 + update $memwr$\storage_2$ls180.v:10106$7_ADDR $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 + update $memwr$\storage_2$ls180.v:10106$7_DATA $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 + update $memwr$\storage_2$ls180.v:10106$7_EN $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 end - attribute \src "ls180.v:1003.5-1003.31" - process $proc$ls180.v:1003$3152 + attribute \src "ls180.v:1011.5-1011.36" + process $proc$ls180.v:1011$3152 assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 + assign $1\main_spimaster21_storage[0:0] 1'1 sync always sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end - attribute \src "ls180.v:10031.1-10032.4" - process $proc$ls180.v:10031$2715 + attribute \src "ls180.v:10110.1-10111.4" + process $proc$ls180.v:10110$2725 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10039.1-10043.4" - process $proc$ls180.v:10039$2717 + attribute \src "ls180.v:10118.1-10122.4" + process $proc$ls180.v:10118$2727 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 3'xxx - assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10042$2721_DATA - attribute \src "ls180.v:10040.2-10041.131" + assign $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 3'xxx + assign $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10121$2731_DATA + attribute \src "ls180.v:10119.2-10120.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10040.6-10040.60" + attribute \src "ls180.v:10119.6-10119.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10041$8_ADDR $0$memwr$\storage_3$ls180.v:10041$8_ADDR[2:0]$2718 - update $memwr$\storage_3$ls180.v:10041$8_DATA $0$memwr$\storage_3$ls180.v:10041$8_DATA[24:0]$2719 - update $memwr$\storage_3$ls180.v:10041$8_EN $0$memwr$\storage_3$ls180.v:10041$8_EN[24:0]$2720 + update $memwr$\storage_3$ls180.v:10120$8_ADDR $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 + update $memwr$\storage_3$ls180.v:10120$8_DATA $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 + update $memwr$\storage_3$ls180.v:10120$8_EN $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 end - attribute \src "ls180.v:1004.12-1004.43" - process $proc$ls180.v:1004$3153 + attribute \src "ls180.v:1012.5-1012.31" + process $proc$ls180.v:1012$3153 assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 + assign $1\main_spimaster22_re[0:0] 1'0 sync always sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + update \main_spimaster22_re $1\main_spimaster22_re[0:0] end - attribute \src "ls180.v:10045.1-10046.4" - process $proc$ls180.v:10045$2722 + attribute \src "ls180.v:10124.1-10125.4" + process $proc$ls180.v:10124$2732 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1005.5-1005.30" - process $proc$ls180.v:1005$3154 + attribute \src "ls180.v:1013.5-1013.36" + process $proc$ls180.v:1013$3154 assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 + assign $1\main_spimaster23_storage[0:0] 1'0 sync always sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end - attribute \src "ls180.v:10054.1-10058.4" - process $proc$ls180.v:10054$2724 + attribute \src "ls180.v:10133.1-10137.4" + process $proc$ls180.v:10133$2734 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10057$2728_DATA - attribute \src "ls180.v:10055.2-10056.77" + assign $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10136$2738_DATA + attribute \src "ls180.v:10134.2-10135.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10055.6-10055.33" + attribute \src "ls180.v:10134.6-10134.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10056$9_ADDR $0$memwr$\storage_4$ls180.v:10056$9_ADDR[3:0]$2725 - update $memwr$\storage_4$ls180.v:10056$9_DATA $0$memwr$\storage_4$ls180.v:10056$9_DATA[9:0]$2726 - update $memwr$\storage_4$ls180.v:10056$9_EN $0$memwr$\storage_4$ls180.v:10056$9_EN[9:0]$2727 + update $memwr$\storage_4$ls180.v:10135$9_ADDR $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 + update $memwr$\storage_4$ls180.v:10135$9_DATA $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 + update $memwr$\storage_4$ls180.v:10135$9_EN $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 end - attribute \src "ls180.v:1006.12-1006.44" - process $proc$ls180.v:1006$3155 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:10060.1-10063.4" - process $proc$ls180.v:10060$2729 + attribute \src "ls180.v:10139.1-10142.4" + process $proc$ls180.v:10139$2739 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10061.2-10062.55" + attribute \src "ls180.v:10140.2-10141.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10061.6-10061.33" + attribute \src "ls180.v:10140.6-10140.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10062$2730_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10141$2740_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:1007.5-1007.31" - process $proc$ls180.v:1007$3156 + attribute \src "ls180.v:1014.5-1014.31" + process $proc$ls180.v:1014$3155 assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 + assign $1\main_spimaster24_re[0:0] 1'0 sync always sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + update \main_spimaster24_re $1\main_spimaster24_re[0:0] end - attribute \src "ls180.v:10071.1-10075.4" - process $proc$ls180.v:10071$2731 + attribute \src "ls180.v:1015.5-1015.39" + process $proc$ls180.v:1015$3156 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:10150.1-10154.4" + process $proc$ls180.v:10150$2741 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10074$2735_DATA - attribute \src "ls180.v:10072.2-10073.77" + assign $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10153$2745_DATA + attribute \src "ls180.v:10151.2-10152.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10072.6-10072.33" + attribute \src "ls180.v:10151.6-10151.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10073$10_ADDR $0$memwr$\storage_5$ls180.v:10073$10_ADDR[3:0]$2732 - update $memwr$\storage_5$ls180.v:10073$10_DATA $0$memwr$\storage_5$ls180.v:10073$10_DATA[9:0]$2733 - update $memwr$\storage_5$ls180.v:10073$10_EN $0$memwr$\storage_5$ls180.v:10073$10_EN[9:0]$2734 + update $memwr$\storage_5$ls180.v:10152$10_ADDR $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 + update $memwr$\storage_5$ls180.v:10152$10_DATA $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 + update $memwr$\storage_5$ls180.v:10152$10_EN $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 end - attribute \src "ls180.v:10077.1-10080.4" - process $proc$ls180.v:10077$2736 + attribute \src "ls180.v:10156.1-10159.4" + process $proc$ls180.v:10156$2746 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10078.2-10079.55" + attribute \src "ls180.v:10157.2-10158.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10078.6-10078.33" + attribute \src "ls180.v:10157.6-10157.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10079$2737_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10158$2747_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:10087.1-10091.4" - process $proc$ls180.v:10087$2738 + attribute \src "ls180.v:1016.5-1016.38" + process $proc$ls180.v:1016$3157 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:10166.1-10170.4" + process $proc$ls180.v:10166$2748 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10090$2742_DATA - attribute \src "ls180.v:10088.2-10089.85" + assign $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10169$2752_DATA + attribute \src "ls180.v:10167.2-10168.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10088.6-10088.37" + attribute \src "ls180.v:10167.6-10167.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10089$11_ADDR $0$memwr$\storage_6$ls180.v:10089$11_ADDR[4:0]$2739 - update $memwr$\storage_6$ls180.v:10089$11_DATA $0$memwr$\storage_6$ls180.v:10089$11_DATA[9:0]$2740 - update $memwr$\storage_6$ls180.v:10089$11_EN $0$memwr$\storage_6$ls180.v:10089$11_EN[9:0]$2741 + update $memwr$\storage_6$ls180.v:10168$11_ADDR $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 + update $memwr$\storage_6$ls180.v:10168$11_DATA $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 + update $memwr$\storage_6$ls180.v:10168$11_EN $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 end - attribute \src "ls180.v:10093.1-10094.4" - process $proc$ls180.v:10093$2743 + attribute \src "ls180.v:1017.11-1017.40" + process $proc$ls180.v:1017$3158 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:10172.1-10173.4" + process $proc$ls180.v:10172$2753 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10101.1-10105.4" - process $proc$ls180.v:10101$2745 + attribute \src "ls180.v:1018.5-1018.39" + process $proc$ls180.v:1018$3159 assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:10180.1-10184.4" + process $proc$ls180.v:10180$2755 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10104$2749_DATA - attribute \src "ls180.v:10102.2-10103.85" + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10183$2759_DATA + attribute \src "ls180.v:10181.2-10182.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10102.6-10102.37" + attribute \src "ls180.v:10181.6-10181.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10103$12_ADDR $0$memwr$\storage_7$ls180.v:10103$12_ADDR[4:0]$2746 - update $memwr$\storage_7$ls180.v:10103$12_DATA $0$memwr$\storage_7$ls180.v:10103$12_DATA[9:0]$2747 - update $memwr$\storage_7$ls180.v:10103$12_EN $0$memwr$\storage_7$ls180.v:10103$12_EN[9:0]$2748 + update $memwr$\storage_7$ls180.v:10182$12_ADDR $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 + update $memwr$\storage_7$ls180.v:10182$12_DATA $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 + update $memwr$\storage_7$ls180.v:10182$12_EN $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 end - attribute \src "ls180.v:10107.1-10108.4" - process $proc$ls180.v:10107$2750 + attribute \src "ls180.v:10186.1-10187.4" + process $proc$ls180.v:10186$2760 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1011.12-1011.37" - process $proc$ls180.v:1011$3157 + attribute \src "ls180.v:1019.5-1019.39" + process $proc$ls180.v:1019$3160 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:1020.12-1020.48" + process $proc$ls180.v:1020$3161 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1023.11-1023.44" + process $proc$ls180.v:1023$3162 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1024.11-1024.43" + process $proc$ls180.v:1024$3163 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1025.11-1025.44" + process $proc$ls180.v:1025$3164 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1028.5-1028.32" + process $proc$ls180.v:1028$3165 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1029.5-1029.30" + process $proc$ls180.v:1029$3166 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1031.11-1031.37" + process $proc$ls180.v:1031$3167 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:1035.5-1035.33" + process $proc$ls180.v:1035$3168 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1037.12-1037.50" + process $proc$ls180.v:1037$3169 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1038.5-1038.37" + process $proc$ls180.v:1038$3170 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1042.11-1042.45" + process $proc$ls180.v:1042$3171 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:1043.5-1043.34" + process $proc$ls180.v:1043$3172 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1047.5-1047.37" + process $proc$ls180.v:1047$3173 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1048.5-1048.32" + process $proc$ls180.v:1048$3174 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1049.5-1049.43" + process $proc$ls180.v:1049$3175 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1050.5-1050.38" + process $proc$ls180.v:1050$3176 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1051.5-1051.37" + process $proc$ls180.v:1051$3177 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1052.5-1052.36" + process $proc$ls180.v:1052$3178 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1053.11-1053.38" + process $proc$ls180.v:1053$3179 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1054.5-1054.37" + process $proc$ls180.v:1054$3180 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1055.5-1055.37" + process $proc$ls180.v:1055$3181 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1056.12-1056.47" + process $proc$ls180.v:1056$3182 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1059.11-1059.42" + process $proc$ls180.v:1059$3183 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1060.11-1060.41" + process $proc$ls180.v:1060$3184 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1061.11-1061.42" + process $proc$ls180.v:1061$3185 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1062.12-1062.45" + process $proc$ls180.v:1062$3186 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1063.5-1063.30" + process $proc$ls180.v:1063$3187 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1065.12-1065.30" + process $proc$ls180.v:1065$3188 + assign { } { } + assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[35:0] + end + attribute \src "ls180.v:1069.12-1069.37" + process $proc$ls180.v:1069$3189 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1070.5-1070.36" + process $proc$ls180.v:1070$3190 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1071.5-1071.31" + process $proc$ls180.v:1071$3191 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1072.12-1072.43" + process $proc$ls180.v:1072$3192 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1073.5-1073.30" + process $proc$ls180.v:1073$3193 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1074.12-1074.44" + process $proc$ls180.v:1074$3194 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:1075.5-1075.31" + process $proc$ls180.v:1075$3195 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1079.12-1079.37" + process $proc$ls180.v:1079$3196 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1012.5-1012.36" - process $proc$ls180.v:1012$3158 + attribute \src "ls180.v:1080.5-1080.36" + process $proc$ls180.v:1080$3197 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1013.5-1013.31" - process $proc$ls180.v:1013$3159 + attribute \src "ls180.v:1081.5-1081.31" + process $proc$ls180.v:1081$3198 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1014.12-1014.43" - process $proc$ls180.v:1014$3160 + attribute \src "ls180.v:1082.12-1082.43" + process $proc$ls180.v:1082$3199 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1015.5-1015.30" - process $proc$ls180.v:1015$3161 + attribute \src "ls180.v:1083.5-1083.30" + process $proc$ls180.v:1083$3200 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1016.12-1016.44" - process $proc$ls180.v:1016$3162 + attribute \src "ls180.v:1084.12-1084.44" + process $proc$ls180.v:1084$3201 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1017.5-1017.31" - process $proc$ls180.v:1017$3163 + attribute \src "ls180.v:1085.5-1085.31" + process $proc$ls180.v:1085$3202 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1020.11-1020.46" - process $proc$ls180.v:1020$3164 + attribute \src "ls180.v:1089.11-1089.34" + process $proc$ls180.v:1089$3203 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1090.5-1090.23" + process $proc$ls180.v:1090$3204 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1096.11-1096.46" + process $proc$ls180.v:1096$3205 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1021.5-1021.33" - process $proc$ls180.v:1021$3165 + attribute \src "ls180.v:1097.5-1097.33" + process $proc$ls180.v:1097$3206 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1023.5-1023.35" - process $proc$ls180.v:1023$3166 + attribute \src "ls180.v:1099.5-1099.35" + process $proc$ls180.v:1099$3207 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1025.11-1025.41" - process $proc$ls180.v:1025$3167 + attribute \src "ls180.v:1101.11-1101.41" + process $proc$ls180.v:1101$3208 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1026.5-1026.35" - process $proc$ls180.v:1026$3168 + attribute \src "ls180.v:1102.5-1102.35" + process $proc$ls180.v:1102$3209 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1027.5-1027.36" - process $proc$ls180.v:1027$3169 + attribute \src "ls180.v:1103.5-1103.36" + process $proc$ls180.v:1103$3210 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1031.5-1031.40" - process $proc$ls180.v:1031$3170 + attribute \src "ls180.v:1107.5-1107.40" + process $proc$ls180.v:1107$3211 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1036.5-1036.48" - process $proc$ls180.v:1036$3171 + attribute \src "ls180.v:1112.5-1112.48" + process $proc$ls180.v:1112$3212 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1037.5-1037.50" - process $proc$ls180.v:1037$3172 + attribute \src "ls180.v:1113.5-1113.50" + process $proc$ls180.v:1113$3213 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1038.5-1038.51" - process $proc$ls180.v:1038$3173 + attribute \src "ls180.v:1114.5-1114.51" + process $proc$ls180.v:1114$3214 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1039.11-1039.57" - process $proc$ls180.v:1039$3174 + attribute \src "ls180.v:1115.11-1115.57" + process $proc$ls180.v:1115$3215 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1040.5-1040.52" - process $proc$ls180.v:1040$3175 + attribute \src "ls180.v:1116.5-1116.52" + process $proc$ls180.v:1116$3216 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1041.11-1041.39" - process $proc$ls180.v:1041$3176 + attribute \src "ls180.v:1117.11-1117.39" + process $proc$ls180.v:1117$3217 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1046.5-1046.48" - process $proc$ls180.v:1046$3177 + attribute \src "ls180.v:1122.5-1122.48" + process $proc$ls180.v:1122$3218 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1047.5-1047.50" - process $proc$ls180.v:1047$3178 + attribute \src "ls180.v:1123.5-1123.50" + process $proc$ls180.v:1123$3219 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1048.5-1048.51" - process $proc$ls180.v:1048$3179 + attribute \src "ls180.v:1124.5-1124.51" + process $proc$ls180.v:1124$3220 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1049.11-1049.57" - process $proc$ls180.v:1049$3180 + attribute \src "ls180.v:1125.11-1125.57" + process $proc$ls180.v:1125$3221 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1050.5-1050.52" - process $proc$ls180.v:1050$3181 + attribute \src "ls180.v:1126.5-1126.52" + process $proc$ls180.v:1126$3222 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1051.5-1051.38" - process $proc$ls180.v:1051$3182 + attribute \src "ls180.v:1127.5-1127.38" + process $proc$ls180.v:1127$3223 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1052.5-1052.38" - process $proc$ls180.v:1052$3183 + attribute \src "ls180.v:1128.5-1128.38" + process $proc$ls180.v:1128$3224 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1053.5-1053.37" - process $proc$ls180.v:1053$3184 + attribute \src "ls180.v:1129.5-1129.37" + process $proc$ls180.v:1129$3225 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1054.11-1054.51" - process $proc$ls180.v:1054$3185 + attribute \src "ls180.v:1130.11-1130.51" + process $proc$ls180.v:1130$3226 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1055.5-1055.32" - process $proc$ls180.v:1055$3186 + attribute \src "ls180.v:1131.5-1131.32" + process $proc$ls180.v:1131$3227 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1056.11-1056.39" - process $proc$ls180.v:1056$3187 + attribute \src "ls180.v:1132.11-1132.39" + process $proc$ls180.v:1132$3228 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1059.5-1059.49" - process $proc$ls180.v:1059$3188 + attribute \src "ls180.v:1135.5-1135.49" + process $proc$ls180.v:1135$3229 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1060.5-1060.48" - process $proc$ls180.v:1060$3189 + attribute \src "ls180.v:1136.5-1136.48" + process $proc$ls180.v:1136$3230 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1061.5-1061.55" - process $proc$ls180.v:1061$3190 + attribute \src "ls180.v:1137.5-1137.55" + process $proc$ls180.v:1137$3231 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1063.5-1063.57" - process $proc$ls180.v:1063$3191 + attribute \src "ls180.v:1139.5-1139.57" + process $proc$ls180.v:1139$3232 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1064.5-1064.58" - process $proc$ls180.v:1064$3192 + attribute \src "ls180.v:1140.5-1140.58" + process $proc$ls180.v:1140$3233 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1066.11-1066.64" - process $proc$ls180.v:1066$3193 + attribute \src "ls180.v:1142.11-1142.64" + process $proc$ls180.v:1142$3234 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1067.5-1067.59" - process $proc$ls180.v:1067$3194 + attribute \src "ls180.v:1143.5-1143.59" + process $proc$ls180.v:1143$3235 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1069.5-1069.48" - process $proc$ls180.v:1069$3195 + attribute \src "ls180.v:1145.5-1145.48" + process $proc$ls180.v:1145$3236 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1070.5-1070.50" - process $proc$ls180.v:1070$3196 + attribute \src "ls180.v:1146.5-1146.50" + process $proc$ls180.v:1146$3237 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1071.5-1071.51" - process $proc$ls180.v:1071$3197 + attribute \src "ls180.v:1147.5-1147.51" + process $proc$ls180.v:1147$3238 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1072.11-1072.57" - process $proc$ls180.v:1072$3198 + attribute \src "ls180.v:1148.11-1148.57" + process $proc$ls180.v:1148$3239 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1073.5-1073.52" - process $proc$ls180.v:1073$3199 + attribute \src "ls180.v:1149.5-1149.52" + process $proc$ls180.v:1149$3240 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1074.5-1074.38" - process $proc$ls180.v:1074$3200 + attribute \src "ls180.v:115.5-115.49" + process $proc$ls180.v:115$2785 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1150.5-1150.38" + process $proc$ls180.v:1150$3241 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1075.5-1075.38" - process $proc$ls180.v:1075$3201 + attribute \src "ls180.v:1151.5-1151.38" + process $proc$ls180.v:1151$3242 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1076.5-1076.37" - process $proc$ls180.v:1076$3202 + attribute \src "ls180.v:1152.5-1152.37" + process $proc$ls180.v:1152$3243 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1077.11-1077.53" - process $proc$ls180.v:1077$3203 + attribute \src "ls180.v:1153.11-1153.53" + process $proc$ls180.v:1153$3244 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1078.5-1078.40" - process $proc$ls180.v:1078$3204 + attribute \src "ls180.v:1154.5-1154.40" + process $proc$ls180.v:1154$3245 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1079.5-1079.40" - process $proc$ls180.v:1079$3205 + attribute \src "ls180.v:1155.5-1155.40" + process $proc$ls180.v:1155$3246 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1080.5-1080.39" - process $proc$ls180.v:1080$3206 + attribute \src "ls180.v:1156.5-1156.39" + process $proc$ls180.v:1156$3247 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1081.11-1081.53" - process $proc$ls180.v:1081$3207 + attribute \src "ls180.v:1157.11-1157.53" + process $proc$ls180.v:1157$3248 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1082.11-1082.55" - process $proc$ls180.v:1082$3208 + attribute \src "ls180.v:1158.11-1158.55" + process $proc$ls180.v:1158$3249 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1083.12-1083.48" - process $proc$ls180.v:1083$3209 + attribute \src "ls180.v:1159.12-1159.48" + process $proc$ls180.v:1159$3250 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1084.11-1084.39" - process $proc$ls180.v:1084$3210 + attribute \src "ls180.v:1160.11-1160.39" + process $proc$ls180.v:1160$3251 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1086.5-1086.46" - process $proc$ls180.v:1086$3211 + attribute \src "ls180.v:1162.5-1162.46" + process $proc$ls180.v:1162$3252 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1097.5-1097.53" - process $proc$ls180.v:1097$3212 + attribute \src "ls180.v:117.5-117.49" + process $proc$ls180.v:117$2786 assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:110.5-110.49" - process $proc$ls180.v:110$2775 + attribute \src "ls180.v:1173.5-1173.53" + process $proc$ls180.v:1173$3253 assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1102.5-1102.36" - process $proc$ls180.v:1102$3213 + attribute \src "ls180.v:1178.5-1178.36" + process $proc$ls180.v:1178$3254 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1105.5-1105.53" - process $proc$ls180.v:1105$3214 + attribute \src "ls180.v:1181.5-1181.53" + process $proc$ls180.v:1181$3255 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1106.5-1106.52" - process $proc$ls180.v:1106$3215 + attribute \src "ls180.v:1182.5-1182.52" + process $proc$ls180.v:1182$3256 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1110.5-1110.55" - process $proc$ls180.v:1110$3216 + attribute \src "ls180.v:1186.5-1186.55" + process $proc$ls180.v:1186$3257 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1111.5-1111.54" - process $proc$ls180.v:1111$3217 + attribute \src "ls180.v:1187.5-1187.54" + process $proc$ls180.v:1187$3258 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1112.11-1112.68" - process $proc$ls180.v:1112$3218 + attribute \src "ls180.v:1188.11-1188.68" + process $proc$ls180.v:1188$3259 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1113.11-1113.81" - process $proc$ls180.v:1113$3219 + attribute \src "ls180.v:1189.11-1189.81" + process $proc$ls180.v:1189$3260 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1114.11-1114.54" - process $proc$ls180.v:1114$3220 + attribute \src "ls180.v:1190.11-1190.54" + process $proc$ls180.v:1190$3261 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1116.5-1116.53" - process $proc$ls180.v:1116$3221 + attribute \src "ls180.v:1192.5-1192.53" + process $proc$ls180.v:1192$3262 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:112.5-112.49" - process $proc$ls180.v:112$2776 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1127.5-1127.49" - process $proc$ls180.v:1127$3222 + attribute \src "ls180.v:1203.5-1203.49" + process $proc$ls180.v:1203$3263 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1129.5-1129.49" - process $proc$ls180.v:1129$3223 + attribute \src "ls180.v:1205.5-1205.49" + process $proc$ls180.v:1205$3264 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1130.5-1130.48" - process $proc$ls180.v:1130$3224 + attribute \src "ls180.v:1206.5-1206.48" + process $proc$ls180.v:1206$3265 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1131.11-1131.62" - process $proc$ls180.v:1131$3225 + attribute \src "ls180.v:1207.11-1207.62" + process $proc$ls180.v:1207$3266 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1132.5-1132.38" - process $proc$ls180.v:1132$3226 + attribute \src "ls180.v:1208.5-1208.38" + process $proc$ls180.v:1208$3267 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1137.5-1137.49" - process $proc$ls180.v:1137$3227 + attribute \src "ls180.v:1213.5-1213.49" + process $proc$ls180.v:1213$3268 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1138.5-1138.51" - process $proc$ls180.v:1138$3228 + attribute \src "ls180.v:1214.5-1214.51" + process $proc$ls180.v:1214$3269 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1139.5-1139.52" - process $proc$ls180.v:1139$3229 + attribute \src "ls180.v:1215.5-1215.52" + process $proc$ls180.v:1215$3270 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1140.11-1140.58" - process $proc$ls180.v:1140$3230 + attribute \src "ls180.v:1216.11-1216.58" + process $proc$ls180.v:1216$3271 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1141.5-1141.53" - process $proc$ls180.v:1141$3231 + attribute \src "ls180.v:1217.5-1217.53" + process $proc$ls180.v:1217$3272 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1142.5-1142.39" - process $proc$ls180.v:1142$3232 + attribute \src "ls180.v:1218.5-1218.39" + process $proc$ls180.v:1218$3273 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1143.5-1143.39" - process $proc$ls180.v:1143$3233 + attribute \src "ls180.v:1219.5-1219.39" + process $proc$ls180.v:1219$3274 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1144.5-1144.39" - process $proc$ls180.v:1144$3234 + attribute \src "ls180.v:1220.5-1220.39" + process $proc$ls180.v:1220$3275 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1145.5-1145.38" - process $proc$ls180.v:1145$3235 + attribute \src "ls180.v:1221.5-1221.38" + process $proc$ls180.v:1221$3276 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1146.11-1146.52" - process $proc$ls180.v:1146$3236 + attribute \src "ls180.v:1222.11-1222.52" + process $proc$ls180.v:1222$3277 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1147.5-1147.33" - process $proc$ls180.v:1147$3237 + attribute \src "ls180.v:1223.5-1223.33" + process $proc$ls180.v:1223$3278 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1148.11-1148.40" - process $proc$ls180.v:1148$3238 + attribute \src "ls180.v:1224.11-1224.40" + process $proc$ls180.v:1224$3279 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1149.5-1149.50" - process $proc$ls180.v:1149$3239 + attribute \src "ls180.v:1225.5-1225.50" + process $proc$ls180.v:1225$3280 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1151.5-1151.50" - process $proc$ls180.v:1151$3240 + attribute \src "ls180.v:1227.5-1227.50" + process $proc$ls180.v:1227$3281 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1152.5-1152.49" - process $proc$ls180.v:1152$3241 + attribute \src "ls180.v:1228.5-1228.49" + process $proc$ls180.v:1228$3282 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1153.5-1153.56" - process $proc$ls180.v:1153$3242 + attribute \src "ls180.v:1229.5-1229.56" + process $proc$ls180.v:1229$3283 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1154.5-1154.58" - process $proc$ls180.v:1154$3243 + attribute \src "ls180.v:1230.5-1230.58" + process $proc$ls180.v:1230$3284 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1155.5-1155.58" - process $proc$ls180.v:1155$3244 + attribute \src "ls180.v:1231.5-1231.58" + process $proc$ls180.v:1231$3285 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1156.5-1156.59" - process $proc$ls180.v:1156$3245 + attribute \src "ls180.v:1232.5-1232.59" + process $proc$ls180.v:1232$3286 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1157.11-1157.65" - process $proc$ls180.v:1157$3246 + attribute \src "ls180.v:1233.11-1233.65" + process $proc$ls180.v:1233$3287 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1158.11-1158.65" - process $proc$ls180.v:1158$3247 + attribute \src "ls180.v:1234.11-1234.65" + process $proc$ls180.v:1234$3288 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1159.5-1159.60" - process $proc$ls180.v:1159$3248 + attribute \src "ls180.v:1235.5-1235.60" + process $proc$ls180.v:1235$3289 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1160.5-1160.34" - process $proc$ls180.v:1160$3249 + attribute \src "ls180.v:1236.5-1236.34" + process $proc$ls180.v:1236$3290 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1161.5-1161.34" - process $proc$ls180.v:1161$3250 + attribute \src "ls180.v:1237.5-1237.34" + process $proc$ls180.v:1237$3291 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1162.5-1162.34" - process $proc$ls180.v:1162$3251 + attribute \src "ls180.v:1238.5-1238.34" + process $proc$ls180.v:1238$3292 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1164.5-1164.47" - process $proc$ls180.v:1164$3252 + attribute \src "ls180.v:1240.5-1240.47" + process $proc$ls180.v:1240$3293 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1175.5-1175.54" - process $proc$ls180.v:1175$3253 + attribute \src "ls180.v:1251.5-1251.54" + process $proc$ls180.v:1251$3294 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1180.5-1180.37" - process $proc$ls180.v:1180$3254 + attribute \src "ls180.v:1256.5-1256.37" + process $proc$ls180.v:1256$3295 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1183.5-1183.54" - process $proc$ls180.v:1183$3255 + attribute \src "ls180.v:1259.5-1259.54" + process $proc$ls180.v:1259$3296 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1184.5-1184.53" - process $proc$ls180.v:1184$3256 + attribute \src "ls180.v:1260.5-1260.53" + process $proc$ls180.v:1260$3297 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1188.5-1188.56" - process $proc$ls180.v:1188$3257 + attribute \src "ls180.v:1264.5-1264.56" + process $proc$ls180.v:1264$3298 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1189.5-1189.55" - process $proc$ls180.v:1189$3258 + attribute \src "ls180.v:1265.5-1265.55" + process $proc$ls180.v:1265$3299 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1190.11-1190.69" - process $proc$ls180.v:1190$3259 + attribute \src "ls180.v:1266.11-1266.69" + process $proc$ls180.v:1266$3300 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1191.11-1191.82" - process $proc$ls180.v:1191$3260 + attribute \src "ls180.v:1267.11-1267.82" + process $proc$ls180.v:1267$3301 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1192.11-1192.55" - process $proc$ls180.v:1192$3261 + attribute \src "ls180.v:1268.11-1268.55" + process $proc$ls180.v:1268$3302 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1194.5-1194.54" - process $proc$ls180.v:1194$3262 + attribute \src "ls180.v:127.12-127.74" + process $proc$ls180.v:127$2787 assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:120.5-120.65" - process $proc$ls180.v:120$2777 + attribute \src "ls180.v:1270.5-1270.54" + process $proc$ls180.v:1270$3303 assign { } { } - assign $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $1\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1205.5-1205.50" - process $proc$ls180.v:1205$3263 + attribute \src "ls180.v:1281.5-1281.50" + process $proc$ls180.v:1281$3304 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1207.5-1207.50" - process $proc$ls180.v:1207$3264 + attribute \src "ls180.v:1283.5-1283.50" + process $proc$ls180.v:1283$3305 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1208.5-1208.49" - process $proc$ls180.v:1208$3265 + attribute \src "ls180.v:1284.5-1284.49" + process $proc$ls180.v:1284$3306 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1209.11-1209.63" - process $proc$ls180.v:1209$3266 + attribute \src "ls180.v:1285.11-1285.63" + process $proc$ls180.v:1285$3307 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1210.5-1210.39" - process $proc$ls180.v:1210$3267 + attribute \src "ls180.v:1286.5-1286.39" + process $proc$ls180.v:1286$3308 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1213.5-1213.50" - process $proc$ls180.v:1213$3268 + attribute \src "ls180.v:1289.5-1289.50" + process $proc$ls180.v:1289$3309 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1214.5-1214.49" - process $proc$ls180.v:1214$3269 + attribute \src "ls180.v:1290.5-1290.49" + process $proc$ls180.v:1290$3310 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1215.5-1215.56" - process $proc$ls180.v:1215$3270 + attribute \src "ls180.v:1291.5-1291.56" + process $proc$ls180.v:1291$3311 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1217.5-1217.58" - process $proc$ls180.v:1217$3271 + attribute \src "ls180.v:1293.5-1293.58" + process $proc$ls180.v:1293$3312 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1218.5-1218.59" - process $proc$ls180.v:1218$3272 + attribute \src "ls180.v:1294.5-1294.59" + process $proc$ls180.v:1294$3313 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1220.11-1220.65" - process $proc$ls180.v:1220$3273 + attribute \src "ls180.v:1296.11-1296.65" + process $proc$ls180.v:1296$3314 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1221.5-1221.60" - process $proc$ls180.v:1221$3274 + attribute \src "ls180.v:1297.5-1297.60" + process $proc$ls180.v:1297$3315 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1223.5-1223.49" - process $proc$ls180.v:1223$3275 + attribute \src "ls180.v:1299.5-1299.49" + process $proc$ls180.v:1299$3316 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1224.5-1224.51" - process $proc$ls180.v:1224$3276 + attribute \src "ls180.v:1300.5-1300.51" + process $proc$ls180.v:1300$3317 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1225.5-1225.52" - process $proc$ls180.v:1225$3277 + attribute \src "ls180.v:1301.5-1301.52" + process $proc$ls180.v:1301$3318 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1226.11-1226.58" - process $proc$ls180.v:1226$3278 + attribute \src "ls180.v:1302.11-1302.58" + process $proc$ls180.v:1302$3319 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1227.5-1227.53" - process $proc$ls180.v:1227$3279 + attribute \src "ls180.v:1303.5-1303.53" + process $proc$ls180.v:1303$3320 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1228.5-1228.39" - process $proc$ls180.v:1228$3280 + attribute \src "ls180.v:1304.5-1304.39" + process $proc$ls180.v:1304$3321 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1229.5-1229.39" - process $proc$ls180.v:1229$3281 + attribute \src "ls180.v:1305.5-1305.39" + process $proc$ls180.v:1305$3322 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1230.5-1230.38" - process $proc$ls180.v:1230$3282 + attribute \src "ls180.v:1306.5-1306.38" + process $proc$ls180.v:1306$3323 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1231.11-1231.61" - process $proc$ls180.v:1231$3283 + attribute \src "ls180.v:1307.11-1307.61" + process $proc$ls180.v:1307$3324 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1232.5-1232.41" - process $proc$ls180.v:1232$3284 + attribute \src "ls180.v:1308.5-1308.41" + process $proc$ls180.v:1308$3325 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1233.5-1233.41" - process $proc$ls180.v:1233$3285 + attribute \src "ls180.v:1309.5-1309.41" + process $proc$ls180.v:1309$3326 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1234.5-1234.41" - process $proc$ls180.v:1234$3286 + attribute \src "ls180.v:131.5-131.72" + process $proc$ls180.v:131$2788 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1310.5-1310.41" + process $proc$ls180.v:1310$3327 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1235.5-1235.40" - process $proc$ls180.v:1235$3287 + attribute \src "ls180.v:1311.5-1311.40" + process $proc$ls180.v:1311$3328 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1236.11-1236.54" - process $proc$ls180.v:1236$3288 + attribute \src "ls180.v:1312.11-1312.54" + process $proc$ls180.v:1312$3329 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1237.11-1237.56" - process $proc$ls180.v:1237$3289 + attribute \src "ls180.v:1313.11-1313.56" + process $proc$ls180.v:1313$3330 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1238.5-1238.33" - process $proc$ls180.v:1238$3290 + attribute \src "ls180.v:1314.5-1314.33" + process $proc$ls180.v:1314$3331 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1239.12-1239.49" - process $proc$ls180.v:1239$3291 + attribute \src "ls180.v:1315.12-1315.49" + process $proc$ls180.v:1315$3332 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1240.11-1240.41" - process $proc$ls180.v:1240$3292 + attribute \src "ls180.v:1316.11-1316.41" + process $proc$ls180.v:1316$3333 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1242.5-1242.48" - process $proc$ls180.v:1242$3293 + attribute \src "ls180.v:1318.5-1318.48" + process $proc$ls180.v:1318$3334 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1253.5-1253.55" - process $proc$ls180.v:1253$3294 + attribute \src "ls180.v:1329.5-1329.55" + process $proc$ls180.v:1329$3335 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1258.5-1258.38" - process $proc$ls180.v:1258$3295 + attribute \src "ls180.v:1334.5-1334.38" + process $proc$ls180.v:1334$3336 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1261.5-1261.55" - process $proc$ls180.v:1261$3296 + attribute \src "ls180.v:1337.5-1337.55" + process $proc$ls180.v:1337$3337 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1262.5-1262.54" - process $proc$ls180.v:1262$3297 + attribute \src "ls180.v:1338.5-1338.54" + process $proc$ls180.v:1338$3338 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1266.5-1266.57" - process $proc$ls180.v:1266$3298 + attribute \src "ls180.v:1342.5-1342.57" + process $proc$ls180.v:1342$3339 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1267.5-1267.56" - process $proc$ls180.v:1267$3299 + attribute \src "ls180.v:1343.5-1343.56" + process $proc$ls180.v:1343$3340 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1268.11-1268.70" - process $proc$ls180.v:1268$3300 + attribute \src "ls180.v:1344.11-1344.70" + process $proc$ls180.v:1344$3341 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1269.11-1269.83" - process $proc$ls180.v:1269$3301 + attribute \src "ls180.v:1345.11-1345.83" + process $proc$ls180.v:1345$3342 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1270.5-1270.50" - process $proc$ls180.v:1270$3302 + attribute \src "ls180.v:1346.5-1346.50" + process $proc$ls180.v:1346$3343 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1272.5-1272.55" - process $proc$ls180.v:1272$3303 + attribute \src "ls180.v:1348.5-1348.55" + process $proc$ls180.v:1348$3344 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1283.5-1283.51" - process $proc$ls180.v:1283$3304 + attribute \src "ls180.v:135.5-135.69" + process $proc$ls180.v:135$2789 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end + attribute \src "ls180.v:1359.5-1359.51" + process $proc$ls180.v:1359$3345 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1285.5-1285.51" - process $proc$ls180.v:1285$3305 + attribute \src "ls180.v:1361.5-1361.51" + process $proc$ls180.v:1361$3346 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1286.5-1286.50" - process $proc$ls180.v:1286$3306 + attribute \src "ls180.v:1362.5-1362.50" + process $proc$ls180.v:1362$3347 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1287.11-1287.64" - process $proc$ls180.v:1287$3307 + attribute \src "ls180.v:1363.11-1363.64" + process $proc$ls180.v:1363$3348 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1288.5-1288.40" - process $proc$ls180.v:1288$3308 + attribute \src "ls180.v:1364.5-1364.40" + process $proc$ls180.v:1364$3349 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1290.5-1290.35" - process $proc$ls180.v:1290$3309 + attribute \src "ls180.v:1366.5-1366.35" + process $proc$ls180.v:1366$3350 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1293.11-1293.42" - process $proc$ls180.v:1293$3310 + attribute \src "ls180.v:1369.11-1369.42" + process $proc$ls180.v:1369$3351 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:130.12-130.71" - process $proc$ls180.v:130$2778 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1306.12-1306.52" - process $proc$ls180.v:1306$3311 + attribute \src "ls180.v:1382.12-1382.52" + process $proc$ls180.v:1382$3352 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1307.5-1307.39" - process $proc$ls180.v:1307$3312 + attribute \src "ls180.v:1383.5-1383.39" + process $proc$ls180.v:1383$3353 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1308.12-1308.51" - process $proc$ls180.v:1308$3313 + attribute \src "ls180.v:1384.12-1384.51" + process $proc$ls180.v:1384$3354 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1309.5-1309.38" - process $proc$ls180.v:1309$3314 + attribute \src "ls180.v:1385.5-1385.38" + process $proc$ls180.v:1385$3355 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:131.12-131.73" - process $proc$ls180.v:131$2779 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1313.5-1313.34" - process $proc$ls180.v:1313$3315 + attribute \src "ls180.v:1389.5-1389.34" + process $proc$ls180.v:1389$3356 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1314.13-1314.53" - process $proc$ls180.v:1314$3316 + attribute \src "ls180.v:1390.13-1390.53" + process $proc$ls180.v:1390$3357 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1320.11-1320.51" - process $proc$ls180.v:1320$3317 + attribute \src "ls180.v:1396.11-1396.51" + process $proc$ls180.v:1396$3358 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1321.5-1321.39" - process $proc$ls180.v:1321$3318 + attribute \src "ls180.v:1397.5-1397.39" + process $proc$ls180.v:1397$3359 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1322.12-1322.51" - process $proc$ls180.v:1322$3319 + attribute \src "ls180.v:1398.12-1398.51" + process $proc$ls180.v:1398$3360 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1323.5-1323.38" - process $proc$ls180.v:1323$3320 + attribute \src "ls180.v:1399.5-1399.38" + process $proc$ls180.v:1399$3361 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1324.11-1324.51" - process $proc$ls180.v:1324$3321 + attribute \src "ls180.v:1400.11-1400.51" + process $proc$ls180.v:1400$3362 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:133.11-133.69" - process $proc$ls180.v:133$2780 + attribute \src "ls180.v:141.5-141.74" + process $proc$ls180.v:141$2790 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] end - attribute \src "ls180.v:134.5-134.63" - process $proc$ls180.v:134$2781 + attribute \src "ls180.v:143.12-143.78" + process $proc$ls180.v:143$2791 assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] end - attribute \src "ls180.v:135.5-135.63" - process $proc$ls180.v:135$2782 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1366.11-1366.47" - process $proc$ls180.v:1366$3322 + attribute \src "ls180.v:1442.11-1442.47" + process $proc$ls180.v:1442$3363 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:137.5-137.62" - process $proc$ls180.v:137$2783 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] - end - attribute \src "ls180.v:1370.5-1370.49" - process $proc$ls180.v:1370$3323 + attribute \src "ls180.v:1446.5-1446.49" + process $proc$ls180.v:1446$3364 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1374.5-1374.51" - process $proc$ls180.v:1374$3324 + attribute \src "ls180.v:1450.5-1450.51" + process $proc$ls180.v:1450$3365 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1375.5-1375.51" - process $proc$ls180.v:1375$3325 + attribute \src "ls180.v:1451.5-1451.51" + process $proc$ls180.v:1451$3366 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1376.5-1376.51" - process $proc$ls180.v:1376$3326 + attribute \src "ls180.v:1452.5-1452.51" + process $proc$ls180.v:1452$3367 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1377.5-1377.50" - process $proc$ls180.v:1377$3327 + attribute \src "ls180.v:1453.5-1453.50" + process $proc$ls180.v:1453$3368 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1378.11-1378.64" - process $proc$ls180.v:1378$3328 + attribute \src "ls180.v:1454.11-1454.64" + process $proc$ls180.v:1454$3369 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1379.11-1379.48" - process $proc$ls180.v:1379$3329 + attribute \src "ls180.v:1455.11-1455.48" + process $proc$ls180.v:1455$3370 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:138.11-138.69" - process $proc$ls180.v:138$2784 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1380.12-1380.59" - process $proc$ls180.v:1380$3330 + attribute \src "ls180.v:1456.12-1456.59" + process $proc$ls180.v:1456$3371 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1384.12-1384.55" - process $proc$ls180.v:1384$3331 + attribute \src "ls180.v:1460.12-1460.55" + process $proc$ls180.v:1460$3372 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1387.12-1387.59" - process $proc$ls180.v:1387$3332 + attribute \src "ls180.v:1463.12-1463.59" + process $proc$ls180.v:1463$3373 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:139.11-139.69" - process $proc$ls180.v:139$2785 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1391.12-1391.55" - process $proc$ls180.v:1391$3333 + attribute \src "ls180.v:1467.12-1467.55" + process $proc$ls180.v:1467$3374 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1394.12-1394.59" - process $proc$ls180.v:1394$3334 + attribute \src "ls180.v:1470.12-1470.59" + process $proc$ls180.v:1470$3375 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1398.12-1398.55" - process $proc$ls180.v:1398$3335 + attribute \src "ls180.v:1474.12-1474.55" + process $proc$ls180.v:1474$3376 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1401.12-1401.59" - process $proc$ls180.v:1401$3336 + attribute \src "ls180.v:1477.12-1477.59" + process $proc$ls180.v:1477$3377 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1405.12-1405.55" - process $proc$ls180.v:1405$3337 + attribute \src "ls180.v:1481.12-1481.55" + process $proc$ls180.v:1481$3378 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1408.12-1408.54" - process $proc$ls180.v:1408$3338 + attribute \src "ls180.v:1484.12-1484.54" + process $proc$ls180.v:1484$3379 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1409.12-1409.54" - process $proc$ls180.v:1409$3339 + attribute \src "ls180.v:1485.12-1485.54" + process $proc$ls180.v:1485$3380 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:141.5-141.44" - process $proc$ls180.v:141$2786 - assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] - end - attribute \src "ls180.v:1410.12-1410.54" - process $proc$ls180.v:1410$3340 + attribute \src "ls180.v:1486.12-1486.54" + process $proc$ls180.v:1486$3381 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1411.12-1411.54" - process $proc$ls180.v:1411$3341 + attribute \src "ls180.v:1487.12-1487.54" + process $proc$ls180.v:1487$3382 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1412.5-1412.48" - process $proc$ls180.v:1412$3342 + attribute \src "ls180.v:1488.5-1488.48" + process $proc$ls180.v:1488$3383 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1413.5-1413.48" - process $proc$ls180.v:1413$3343 + attribute \src "ls180.v:1489.5-1489.48" + process $proc$ls180.v:1489$3384 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1414.5-1414.48" - process $proc$ls180.v:1414$3344 + attribute \src "ls180.v:1490.5-1490.48" + process $proc$ls180.v:1490$3385 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1415.5-1415.47" - process $proc$ls180.v:1415$3345 + attribute \src "ls180.v:1491.5-1491.47" + process $proc$ls180.v:1491$3386 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1416.11-1416.61" - process $proc$ls180.v:1416$3346 + attribute \src "ls180.v:1492.11-1492.61" + process $proc$ls180.v:1492$3387 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1417.5-1417.50" - process $proc$ls180.v:1417$3347 + attribute \src "ls180.v:1493.5-1493.50" + process $proc$ls180.v:1493$3388 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1419.5-1419.50" - process $proc$ls180.v:1419$3348 + attribute \src "ls180.v:1495.5-1495.50" + process $proc$ls180.v:1495$3389 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:142.5-142.47" - process $proc$ls180.v:142$2787 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1422.11-1422.47" - process $proc$ls180.v:1422$3349 + attribute \src "ls180.v:1498.11-1498.47" + process $proc$ls180.v:1498$3390 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1423.11-1423.47" - process $proc$ls180.v:1423$3350 + attribute \src "ls180.v:1499.11-1499.47" + process $proc$ls180.v:1499$3391 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1424.12-1424.58" - process $proc$ls180.v:1424$3351 + attribute \src "ls180.v:1500.12-1500.58" + process $proc$ls180.v:1500$3392 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1428.12-1428.54" - process $proc$ls180.v:1428$3352 + attribute \src "ls180.v:1504.12-1504.54" + process $proc$ls180.v:1504$3393 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1429.5-1429.46" - process $proc$ls180.v:1429$3353 + attribute \src "ls180.v:1505.5-1505.46" + process $proc$ls180.v:1505$3394 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1431.12-1431.58" - process $proc$ls180.v:1431$3354 + attribute \src "ls180.v:1507.12-1507.58" + process $proc$ls180.v:1507$3395 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1435.12-1435.54" - process $proc$ls180.v:1435$3355 + attribute \src "ls180.v:1511.12-1511.54" + process $proc$ls180.v:1511$3396 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1436.5-1436.46" - process $proc$ls180.v:1436$3356 + attribute \src "ls180.v:1512.5-1512.46" + process $proc$ls180.v:1512$3397 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1438.12-1438.58" - process $proc$ls180.v:1438$3357 + attribute \src "ls180.v:1514.12-1514.58" + process $proc$ls180.v:1514$3398 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:144.12-144.53" - process $proc$ls180.v:144$2788 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1442.12-1442.54" - process $proc$ls180.v:1442$3358 + attribute \src "ls180.v:1518.12-1518.54" + process $proc$ls180.v:1518$3399 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1443.5-1443.46" - process $proc$ls180.v:1443$3359 + attribute \src "ls180.v:1519.5-1519.46" + process $proc$ls180.v:1519$3400 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1445.12-1445.58" - process $proc$ls180.v:1445$3360 + attribute \src "ls180.v:1521.12-1521.58" + process $proc$ls180.v:1521$3401 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1449.12-1449.54" - process $proc$ls180.v:1449$3361 + attribute \src "ls180.v:1525.12-1525.54" + process $proc$ls180.v:1525$3402 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:145.12-145.71" - process $proc$ls180.v:145$2789 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1450.5-1450.46" - process $proc$ls180.v:1450$3362 + attribute \src "ls180.v:1526.5-1526.46" + process $proc$ls180.v:1526$3403 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1452.12-1452.53" - process $proc$ls180.v:1452$3363 + attribute \src "ls180.v:1528.12-1528.53" + process $proc$ls180.v:1528$3404 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1453.12-1453.53" - process $proc$ls180.v:1453$3364 + attribute \src "ls180.v:1529.12-1529.53" + process $proc$ls180.v:1529$3405 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1454.12-1454.53" - process $proc$ls180.v:1454$3365 + attribute \src "ls180.v:1530.12-1530.53" + process $proc$ls180.v:1530$3406 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1455.12-1455.53" - process $proc$ls180.v:1455$3366 + attribute \src "ls180.v:1531.12-1531.53" + process $proc$ls180.v:1531$3407 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1456.5-1456.43" - process $proc$ls180.v:1456$3367 + attribute \src "ls180.v:1532.5-1532.43" + process $proc$ls180.v:1532$3408 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1457.12-1457.51" - process $proc$ls180.v:1457$3368 + attribute \src "ls180.v:1533.12-1533.51" + process $proc$ls180.v:1533$3409 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1458.12-1458.51" - process $proc$ls180.v:1458$3369 + attribute \src "ls180.v:1534.12-1534.51" + process $proc$ls180.v:1534$3410 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1459.12-1459.51" - process $proc$ls180.v:1459$3370 + attribute \src "ls180.v:1535.12-1535.51" + process $proc$ls180.v:1535$3411 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:146.12-146.73" - process $proc$ls180.v:146$2790 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1460.12-1460.51" - process $proc$ls180.v:1460$3371 + attribute \src "ls180.v:1536.12-1536.51" + process $proc$ls180.v:1536$3412 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:1462.11-1462.39" - process $proc$ls180.v:1462$3372 + attribute \src "ls180.v:1538.11-1538.39" + process $proc$ls180.v:1538$3413 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1463.5-1463.32" - process $proc$ls180.v:1463$3373 + attribute \src "ls180.v:1539.5-1539.32" + process $proc$ls180.v:1539$3414 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1464.5-1464.33" - process $proc$ls180.v:1464$3374 + attribute \src "ls180.v:154.11-154.24" + process $proc$ls180.v:154$2792 + assign { } { } + assign $0\eint_1[2:0] 3'000 + sync always + update \eint_1 $0\eint_1[2:0] + sync init + end + attribute \src "ls180.v:1540.5-1540.33" + process $proc$ls180.v:1540$3415 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1465.5-1465.35" - process $proc$ls180.v:1465$3375 + attribute \src "ls180.v:1541.5-1541.35" + process $proc$ls180.v:1541$3416 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1467.12-1467.42" - process $proc$ls180.v:1467$3376 + attribute \src "ls180.v:1543.12-1543.42" + process $proc$ls180.v:1543$3417 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1468.5-1468.33" - process $proc$ls180.v:1468$3377 + attribute \src "ls180.v:1544.5-1544.33" + process $proc$ls180.v:1544$3418 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1469.5-1469.34" - process $proc$ls180.v:1469$3378 + attribute \src "ls180.v:1545.5-1545.34" + process $proc$ls180.v:1545$3419 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1470.5-1470.36" - process $proc$ls180.v:1470$3379 + attribute \src "ls180.v:1546.5-1546.36" + process $proc$ls180.v:1546$3420 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:1479.11-1479.41" - process $proc$ls180.v:1479$3380 + attribute \src "ls180.v:1555.11-1555.41" + process $proc$ls180.v:1555$3421 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:148.11-148.69" - process $proc$ls180.v:148$2791 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1480.11-1480.41" - process $proc$ls180.v:1480$3381 + attribute \src "ls180.v:1556.11-1556.41" + process $proc$ls180.v:1556$3422 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:149.5-149.63" - process $proc$ls180.v:149$2792 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:150.5-150.63" - process $proc$ls180.v:150$2793 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1503.11-1503.45" - process $proc$ls180.v:1503$3382 + attribute \src "ls180.v:1579.11-1579.45" + process $proc$ls180.v:1579$3423 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1504.5-1504.41" - process $proc$ls180.v:1504$3383 + attribute \src "ls180.v:1580.5-1580.41" + process $proc$ls180.v:1580$3424 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1505.11-1505.47" - process $proc$ls180.v:1505$3384 + attribute \src "ls180.v:1581.11-1581.47" + process $proc$ls180.v:1581$3425 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1506.11-1506.47" - process $proc$ls180.v:1506$3385 + attribute \src "ls180.v:1582.11-1582.47" + process $proc$ls180.v:1582$3426 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1507.11-1507.50" - process $proc$ls180.v:1507$3386 + attribute \src "ls180.v:1583.11-1583.50" + process $proc$ls180.v:1583$3427 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:152.5-152.62" - process $proc$ls180.v:152$2794 + attribute \src "ls180.v:159.5-159.74" + process $proc$ls180.v:159$2793 assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0 sync always + update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] end - attribute \src "ls180.v:1527.5-1527.51" - process $proc$ls180.v:1527$3387 + attribute \src "ls180.v:160.12-160.71" + process $proc$ls180.v:160$2794 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1603.5-1603.51" + process $proc$ls180.v:1603$3428 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1528.5-1528.50" - process $proc$ls180.v:1528$3388 + attribute \src "ls180.v:1604.5-1604.50" + process $proc$ls180.v:1604$3429 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1529.12-1529.66" - process $proc$ls180.v:1529$3389 + attribute \src "ls180.v:1605.12-1605.66" + process $proc$ls180.v:1605$3430 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 sync always sync init update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] end - attribute \src "ls180.v:153.11-153.69" - process $proc$ls180.v:153$2795 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1530.11-1530.77" - process $proc$ls180.v:1530$3390 + attribute \src "ls180.v:1606.11-1606.77" + process $proc$ls180.v:1606$3431 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 sync always sync init update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] end - attribute \src "ls180.v:1531.11-1531.50" - process $proc$ls180.v:1531$3391 + attribute \src "ls180.v:1607.11-1607.50" + process $proc$ls180.v:1607$3432 assign { } { } assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 sync always sync init update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] end - attribute \src "ls180.v:1533.5-1533.49" - process $proc$ls180.v:1533$3392 + attribute \src "ls180.v:1609.5-1609.49" + process $proc$ls180.v:1609$3433 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:1539.5-1539.45" - process $proc$ls180.v:1539$3393 + attribute \src "ls180.v:161.12-161.73" + process $proc$ls180.v:161$2795 assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 sync always sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:154.11-154.69" - process $proc$ls180.v:154$2796 + attribute \src "ls180.v:1615.5-1615.45" + process $proc$ls180.v:1615$3434 assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1541.12-1541.62" - process $proc$ls180.v:1541$3394 + attribute \src "ls180.v:1617.12-1617.62" + process $proc$ls180.v:1617$3435 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1542.12-1542.60" - process $proc$ls180.v:1542$3395 + attribute \src "ls180.v:1618.12-1618.60" + process $proc$ls180.v:1618$3436 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] end - attribute \src "ls180.v:1544.5-1544.57" - process $proc$ls180.v:1544$3396 + attribute \src "ls180.v:1620.5-1620.57" + process $proc$ls180.v:1620$3437 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1548.12-1548.67" - process $proc$ls180.v:1548$3397 + attribute \src "ls180.v:1624.12-1624.67" + process $proc$ls180.v:1624$3438 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1549.5-1549.54" - process $proc$ls180.v:1549$3398 + attribute \src "ls180.v:1625.5-1625.54" + process $proc$ls180.v:1625$3439 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1550.12-1550.69" - process $proc$ls180.v:1550$3399 + attribute \src "ls180.v:1626.12-1626.69" + process $proc$ls180.v:1626$3440 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:1551.5-1551.56" - process $proc$ls180.v:1551$3400 + attribute \src "ls180.v:1627.5-1627.56" + process $proc$ls180.v:1627$3441 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1552.5-1552.61" - process $proc$ls180.v:1552$3401 + attribute \src "ls180.v:1628.5-1628.61" + process $proc$ls180.v:1628$3442 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1553.5-1553.56" - process $proc$ls180.v:1553$3402 + attribute \src "ls180.v:1629.5-1629.56" + process $proc$ls180.v:1629$3443 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1554.5-1554.53" - process $proc$ls180.v:1554$3403 + attribute \src "ls180.v:163.11-163.69" + process $proc$ls180.v:163$2796 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1630.5-1630.53" + process $proc$ls180.v:1630$3444 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1556.5-1556.59" - process $proc$ls180.v:1556$3404 + attribute \src "ls180.v:1632.5-1632.59" + process $proc$ls180.v:1632$3445 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1557.5-1557.54" - process $proc$ls180.v:1557$3405 + attribute \src "ls180.v:1633.5-1633.54" + process $proc$ls180.v:1633$3446 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1559.12-1559.61" - process $proc$ls180.v:1559$3406 + attribute \src "ls180.v:1635.12-1635.61" + process $proc$ls180.v:1635$3447 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:156.5-156.44" - process $proc$ls180.v:156$2797 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1562.12-1562.43" - process $proc$ls180.v:1562$3407 + attribute \src "ls180.v:1638.12-1638.43" + process $proc$ls180.v:1638$3448 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1563.12-1563.45" - process $proc$ls180.v:1563$3408 + attribute \src "ls180.v:1639.12-1639.45" + process $proc$ls180.v:1639$3449 assign { } { } assign $0\main_interface1_bus_dat_w[31:0] 0 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] sync init end - attribute \src "ls180.v:1565.11-1565.41" - process $proc$ls180.v:1565$3409 + attribute \src "ls180.v:164.5-164.63" + process $proc$ls180.v:164$2797 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1641.11-1641.41" + process $proc$ls180.v:1641$3450 assign { } { } assign $1\main_interface1_bus_sel[3:0] 4'0000 sync always sync init update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] end - attribute \src "ls180.v:1566.5-1566.35" - process $proc$ls180.v:1566$3410 + attribute \src "ls180.v:1642.5-1642.35" + process $proc$ls180.v:1642$3451 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1567.5-1567.35" - process $proc$ls180.v:1567$3411 + attribute \src "ls180.v:1643.5-1643.35" + process $proc$ls180.v:1643$3452 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1569.5-1569.34" - process $proc$ls180.v:1569$3412 + attribute \src "ls180.v:1645.5-1645.34" + process $proc$ls180.v:1645$3453 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:157.5-157.47" - process $proc$ls180.v:157$2798 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1570.11-1570.41" - process $proc$ls180.v:1570$3413 + attribute \src "ls180.v:1646.11-1646.41" + process $proc$ls180.v:1646$3454 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:1571.11-1571.41" - process $proc$ls180.v:1571$3414 + attribute \src "ls180.v:1647.11-1647.41" + process $proc$ls180.v:1647$3455 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:1578.5-1578.43" - process $proc$ls180.v:1578$3415 + attribute \src "ls180.v:165.5-165.63" + process $proc$ls180.v:165$2798 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1654.5-1654.43" + process $proc$ls180.v:1654$3456 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1579.5-1579.43" - process $proc$ls180.v:1579$3416 + attribute \src "ls180.v:1655.5-1655.43" + process $proc$ls180.v:1655$3457 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1580.5-1580.42" - process $proc$ls180.v:1580$3417 + attribute \src "ls180.v:1656.5-1656.42" + process $proc$ls180.v:1656$3458 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:1581.12-1581.61" - process $proc$ls180.v:1581$3418 + attribute \src "ls180.v:1657.12-1657.61" + process $proc$ls180.v:1657$3459 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1582.5-1582.45" - process $proc$ls180.v:1582$3419 + attribute \src "ls180.v:1658.5-1658.45" + process $proc$ls180.v:1658$3460 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1584.5-1584.45" - process $proc$ls180.v:1584$3420 + attribute \src "ls180.v:1660.5-1660.45" + process $proc$ls180.v:1660$3461 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1585.5-1585.44" - process $proc$ls180.v:1585$3421 + attribute \src "ls180.v:1661.5-1661.44" + process $proc$ls180.v:1661$3462 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1586.12-1586.60" - process $proc$ls180.v:1586$3422 + attribute \src "ls180.v:1662.12-1662.60" + process $proc$ls180.v:1662$3463 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 sync always sync init update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] end - attribute \src "ls180.v:1587.12-1587.45" - process $proc$ls180.v:1587$3423 + attribute \src "ls180.v:1663.12-1663.45" + process $proc$ls180.v:1663$3464 assign { } { } assign $1\main_sdmem2block_dma_data[31:0] 0 sync always sync init update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] end - attribute \src "ls180.v:1588.12-1588.53" - process $proc$ls180.v:1588$3424 + attribute \src "ls180.v:1664.12-1664.53" + process $proc$ls180.v:1664$3465 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1589.5-1589.40" - process $proc$ls180.v:1589$3425 + attribute \src "ls180.v:1665.5-1665.40" + process $proc$ls180.v:1665$3466 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:159.12-159.53" - process $proc$ls180.v:159$2799 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1590.12-1590.55" - process $proc$ls180.v:1590$3426 + attribute \src "ls180.v:1666.12-1666.55" + process $proc$ls180.v:1666$3467 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1591.5-1591.42" - process $proc$ls180.v:1591$3427 + attribute \src "ls180.v:1667.5-1667.42" + process $proc$ls180.v:1667$3468 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1592.5-1592.47" - process $proc$ls180.v:1592$3428 + attribute \src "ls180.v:1668.5-1668.47" + process $proc$ls180.v:1668$3469 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1593.5-1593.42" - process $proc$ls180.v:1593$3429 + attribute \src "ls180.v:1669.5-1669.42" + process $proc$ls180.v:1669$3470 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1594.5-1594.44" - process $proc$ls180.v:1594$3430 + attribute \src "ls180.v:167.5-167.62" + process $proc$ls180.v:167$2799 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1670.5-1670.44" + process $proc$ls180.v:1670$3471 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1596.5-1596.45" - process $proc$ls180.v:1596$3431 + attribute \src "ls180.v:1672.5-1672.45" + process $proc$ls180.v:1672$3472 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1597.5-1597.40" - process $proc$ls180.v:1597$3432 + attribute \src "ls180.v:1673.5-1673.40" + process $proc$ls180.v:1673$3473 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:160.12-160.71" - process $proc$ls180.v:160$2800 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1601.12-1601.47" - process $proc$ls180.v:1601$3433 + attribute \src "ls180.v:1677.12-1677.47" + process $proc$ls180.v:1677$3474 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:161.12-161.73" - process $proc$ls180.v:161$2801 + attribute \src "ls180.v:168.11-168.69" + process $proc$ls180.v:168$2800 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1613.11-1613.64" - process $proc$ls180.v:1613$3434 + attribute \src "ls180.v:1689.11-1689.64" + process $proc$ls180.v:1689$3475 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1615.11-1615.48" - process $proc$ls180.v:1615$3435 + attribute \src "ls180.v:169.11-169.69" + process $proc$ls180.v:169$2801 assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] end - attribute \src "ls180.v:163.11-163.69" - process $proc$ls180.v:163$2802 + attribute \src "ls180.v:1691.11-1691.48" + process $proc$ls180.v:1691$3476 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 sync always sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] end - attribute \src "ls180.v:1639.11-1639.45" - process $proc$ls180.v:1639$3436 + attribute \src "ls180.v:171.5-171.44" + process $proc$ls180.v:171$2802 assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 sync always sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] end - attribute \src "ls180.v:164.5-164.63" - process $proc$ls180.v:164$2803 + attribute \src "ls180.v:1715.11-1715.45" + process $proc$ls180.v:1715$3477 assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1640.5-1640.41" - process $proc$ls180.v:1640$3437 + attribute \src "ls180.v:1716.5-1716.41" + process $proc$ls180.v:1716$3478 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1641.11-1641.47" - process $proc$ls180.v:1641$3438 + attribute \src "ls180.v:1717.11-1717.47" + process $proc$ls180.v:1717$3479 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1642.11-1642.47" - process $proc$ls180.v:1642$3439 + attribute \src "ls180.v:1718.11-1718.47" + process $proc$ls180.v:1718$3480 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1643.11-1643.50" - process $proc$ls180.v:1643$3440 + attribute \src "ls180.v:1719.11-1719.50" + process $proc$ls180.v:1719$3481 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:165.5-165.63" - process $proc$ls180.v:165$2804 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1658.5-1658.29" - process $proc$ls180.v:1658$3441 - assign { } { } - assign $1\libresocsim_done0[0:0] 1'0 - sync always - sync init - update \libresocsim_done0 $1\libresocsim_done0[0:0] - end - attribute \src "ls180.v:1659.5-1659.27" - process $proc$ls180.v:1659$3442 - assign { } { } - assign $1\libresocsim_irq[0:0] 1'0 - sync always - sync init - update \libresocsim_irq $1\libresocsim_irq[0:0] - end - attribute \src "ls180.v:1661.11-1661.34" - process $proc$ls180.v:1661$3443 - assign { } { } - assign $1\libresocsim_miso[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso $1\libresocsim_miso[7:0] - end - attribute \src "ls180.v:1665.5-1665.30" - process $proc$ls180.v:1665$3444 - assign { } { } - assign $1\libresocsim_start1[0:0] 1'0 - sync always - sync init - update \libresocsim_start1 $1\libresocsim_start1[0:0] - end - attribute \src "ls180.v:1667.12-1667.47" - process $proc$ls180.v:1667$3445 - assign { } { } - assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] - end - attribute \src "ls180.v:1668.5-1668.34" - process $proc$ls180.v:1668$3446 - assign { } { } - assign $1\libresocsim_control_re[0:0] 1'0 - sync always - sync init - update \libresocsim_control_re $1\libresocsim_control_re[0:0] - end - attribute \src "ls180.v:167.5-167.62" - process $proc$ls180.v:167$2805 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] - end - attribute \src "ls180.v:1672.11-1672.42" - process $proc$ls180.v:1672$3447 - assign { } { } - assign $1\libresocsim_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] - end - attribute \src "ls180.v:1673.5-1673.31" - process $proc$ls180.v:1673$3448 - assign { } { } - assign $1\libresocsim_mosi_re[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] - end - attribute \src "ls180.v:1677.5-1677.34" - process $proc$ls180.v:1677$3449 - assign { } { } - assign $1\libresocsim_cs_storage[0:0] 1'1 - sync always - sync init - update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] - end - attribute \src "ls180.v:1678.5-1678.29" - process $proc$ls180.v:1678$3450 - assign { } { } - assign $1\libresocsim_cs_re[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] - end - attribute \src "ls180.v:1679.5-1679.40" - process $proc$ls180.v:1679$3451 - assign { } { } - assign $1\libresocsim_loopback_storage[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] - end - attribute \src "ls180.v:168.11-168.69" - process $proc$ls180.v:168$2806 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1680.5-1680.35" - process $proc$ls180.v:1680$3452 - assign { } { } - assign $1\libresocsim_loopback_re[0:0] 1'0 - sync always - sync init - update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] - end - attribute \src "ls180.v:1681.5-1681.34" - process $proc$ls180.v:1681$3453 - assign { } { } - assign $1\libresocsim_clk_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] - end - attribute \src "ls180.v:1682.5-1682.33" - process $proc$ls180.v:1682$3454 - assign { } { } - assign $1\libresocsim_cs_enable[0:0] 1'0 - sync always - sync init - update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] - end - attribute \src "ls180.v:1683.11-1683.35" - process $proc$ls180.v:1683$3455 - assign { } { } - assign $1\libresocsim_count[2:0] 3'000 - sync always - sync init - update \libresocsim_count $1\libresocsim_count[2:0] - end - attribute \src "ls180.v:1684.5-1684.34" - process $proc$ls180.v:1684$3456 - assign { } { } - assign $1\libresocsim_mosi_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] - end - attribute \src "ls180.v:1685.5-1685.34" - process $proc$ls180.v:1685$3457 - assign { } { } - assign $1\libresocsim_miso_latch[0:0] 1'0 - sync always - sync init - update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] - end - attribute \src "ls180.v:1686.12-1686.44" - process $proc$ls180.v:1686$3458 - assign { } { } - assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] - end - attribute \src "ls180.v:1689.11-1689.39" - process $proc$ls180.v:1689$3459 - assign { } { } - assign $1\libresocsim_mosi_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] - end - attribute \src "ls180.v:169.11-169.69" - process $proc$ls180.v:169$2807 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1690.11-1690.38" - process $proc$ls180.v:1690$3460 - assign { } { } - assign $1\libresocsim_mosi_sel[2:0] 3'000 - sync always - sync init - update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] - end - attribute \src "ls180.v:1691.11-1691.39" - process $proc$ls180.v:1691$3461 - assign { } { } - assign $1\libresocsim_miso_data[7:0] 8'00000000 - sync always - sync init - update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] - end - attribute \src "ls180.v:1692.12-1692.41" - process $proc$ls180.v:1692$3462 - assign { } { } - assign $1\libresocsim_storage[15:0] 16'0000000001111101 - sync always - sync init - update \libresocsim_storage $1\libresocsim_storage[15:0] - end - attribute \src "ls180.v:1693.5-1693.26" - process $proc$ls180.v:1693$3463 + attribute \src "ls180.v:172.5-172.47" + process $proc$ls180.v:172$2803 assign { } { } - assign $1\libresocsim_re[0:0] 1'0 + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 sync always sync init - update \libresocsim_re $1\libresocsim_re[0:0] + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] end - attribute \src "ls180.v:1694.5-1694.36" - process $proc$ls180.v:1694$3464 + attribute \src "ls180.v:1732.5-1732.36" + process $proc$ls180.v:1732$3482 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1695.5-1695.41" - process $proc$ls180.v:1695$3465 + attribute \src "ls180.v:1733.5-1733.41" + process $proc$ls180.v:1733$3483 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1696.5-1696.69" - process $proc$ls180.v:1696$3466 + attribute \src "ls180.v:1734.5-1734.69" + process $proc$ls180.v:1734$3484 assign { } { } assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1697.5-1697.72" - process $proc$ls180.v:1697$3467 + attribute \src "ls180.v:1735.5-1735.72" + process $proc$ls180.v:1735$3485 assign { } { } assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1698.5-1698.36" - process $proc$ls180.v:1698$3468 + attribute \src "ls180.v:1736.5-1736.36" + process $proc$ls180.v:1736$3486 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:1699.5-1699.41" - process $proc$ls180.v:1699$3469 + attribute \src "ls180.v:1737.5-1737.41" + process $proc$ls180.v:1737$3487 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1700.5-1700.69" - process $proc$ls180.v:1700$3470 + attribute \src "ls180.v:1738.5-1738.69" + process $proc$ls180.v:1738$3488 assign { } { } assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1701.5-1701.72" - process $proc$ls180.v:1701$3471 + attribute \src "ls180.v:1739.5-1739.72" + process $proc$ls180.v:1739$3489 assign { } { } assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1702.5-1702.36" - process $proc$ls180.v:1702$3472 + attribute \src "ls180.v:174.12-174.53" + process $proc$ls180.v:174$2804 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:1740.5-1740.36" + process $proc$ls180.v:1740$3490 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1703.5-1703.41" - process $proc$ls180.v:1703$3473 + attribute \src "ls180.v:1741.5-1741.41" + process $proc$ls180.v:1741$3491 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1704.5-1704.69" - process $proc$ls180.v:1704$3474 + attribute \src "ls180.v:1742.5-1742.69" + process $proc$ls180.v:1742$3492 assign { } { } assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 sync always sync init update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1705.5-1705.72" - process $proc$ls180.v:1705$3475 + attribute \src "ls180.v:1743.5-1743.72" + process $proc$ls180.v:1743$3493 assign { } { } assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1706.11-1706.41" - process $proc$ls180.v:1706$3476 + attribute \src "ls180.v:1744.11-1744.41" + process $proc$ls180.v:1744$3494 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1707.11-1707.46" - process $proc$ls180.v:1707$3477 + attribute \src "ls180.v:1745.11-1745.46" + process $proc$ls180.v:1745$3495 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1708.11-1708.44" - process $proc$ls180.v:1708$3478 + attribute \src "ls180.v:1746.11-1746.44" + process $proc$ls180.v:1746$3496 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1709.11-1709.49" - process $proc$ls180.v:1709$3479 + attribute \src "ls180.v:1747.11-1747.49" + process $proc$ls180.v:1747$3497 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:171.5-171.44" - process $proc$ls180.v:171$2808 - assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] - end - attribute \src "ls180.v:1710.11-1710.44" - process $proc$ls180.v:1710$3480 + attribute \src "ls180.v:1748.11-1748.44" + process $proc$ls180.v:1748$3498 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1711.11-1711.49" - process $proc$ls180.v:1711$3481 + attribute \src "ls180.v:1749.11-1749.49" + process $proc$ls180.v:1749$3499 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1712.11-1712.44" - process $proc$ls180.v:1712$3482 + attribute \src "ls180.v:175.12-175.71" + process $proc$ls180.v:175$2805 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1750.11-1750.44" + process $proc$ls180.v:1750$3500 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1713.11-1713.49" - process $proc$ls180.v:1713$3483 + attribute \src "ls180.v:1751.11-1751.49" + process $proc$ls180.v:1751$3501 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1714.11-1714.44" - process $proc$ls180.v:1714$3484 + attribute \src "ls180.v:1752.11-1752.44" + process $proc$ls180.v:1752$3502 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1715.11-1715.49" - process $proc$ls180.v:1715$3485 + attribute \src "ls180.v:1753.11-1753.49" + process $proc$ls180.v:1753$3503 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1716.11-1716.43" - process $proc$ls180.v:1716$3486 + attribute \src "ls180.v:1754.11-1754.43" + process $proc$ls180.v:1754$3504 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1717.11-1717.48" - process $proc$ls180.v:1717$3487 + attribute \src "ls180.v:1755.11-1755.48" + process $proc$ls180.v:1755$3505 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:172.5-172.47" - process $proc$ls180.v:172$2809 + attribute \src "ls180.v:176.12-176.73" + process $proc$ls180.v:176$2806 assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 sync always sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:1730.5-1730.27" - process $proc$ls180.v:1730$3488 + attribute \src "ls180.v:1768.5-1768.27" + process $proc$ls180.v:1768$3506 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1731.5-1731.27" - process $proc$ls180.v:1731$3489 + attribute \src "ls180.v:1769.5-1769.27" + process $proc$ls180.v:1769$3507 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1732.5-1732.27" - process $proc$ls180.v:1732$3490 + attribute \src "ls180.v:1770.5-1770.27" + process $proc$ls180.v:1770$3508 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1733.5-1733.27" - process $proc$ls180.v:1733$3491 + attribute \src "ls180.v:1771.5-1771.27" + process $proc$ls180.v:1771$3509 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1734.5-1734.42" - process $proc$ls180.v:1734$3492 + attribute \src "ls180.v:1772.5-1772.42" + process $proc$ls180.v:1772$3510 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1735.5-1735.43" - process $proc$ls180.v:1735$3493 + attribute \src "ls180.v:1773.5-1773.43" + process $proc$ls180.v:1773$3511 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1736.5-1736.43" - process $proc$ls180.v:1736$3494 + attribute \src "ls180.v:1774.5-1774.43" + process $proc$ls180.v:1774$3512 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1737.5-1737.43" - process $proc$ls180.v:1737$3495 + attribute \src "ls180.v:1775.5-1775.43" + process $proc$ls180.v:1775$3513 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1738.5-1738.43" - process $proc$ls180.v:1738$3496 + attribute \src "ls180.v:1776.5-1776.43" + process $proc$ls180.v:1776$3514 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:1739.5-1739.35" - process $proc$ls180.v:1739$3497 + attribute \src "ls180.v:1777.5-1777.35" + process $proc$ls180.v:1777$3515 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:174.12-174.53" - process $proc$ls180.v:174$2810 - assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] - end - attribute \src "ls180.v:1740.5-1740.40" - process $proc$ls180.v:1740$3498 + attribute \src "ls180.v:1778.5-1778.40" + process $proc$ls180.v:1778$3516 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1741.5-1741.55" - process $proc$ls180.v:1741$3499 + attribute \src "ls180.v:1779.5-1779.55" + process $proc$ls180.v:1779$3517 assign { } { } assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1742.5-1742.58" - process $proc$ls180.v:1742$3500 + attribute \src "ls180.v:178.11-178.69" + process $proc$ls180.v:178$2807 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1780.5-1780.58" + process $proc$ls180.v:1780$3518 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1743.11-1743.42" - process $proc$ls180.v:1743$3501 + attribute \src "ls180.v:1781.11-1781.42" + process $proc$ls180.v:1781$3519 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1744.11-1744.47" - process $proc$ls180.v:1744$3502 + attribute \src "ls180.v:1782.11-1782.47" + process $proc$ls180.v:1782$3520 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1745.11-1745.61" - process $proc$ls180.v:1745$3503 + attribute \src "ls180.v:1783.11-1783.62" + process $proc$ls180.v:1783$3521 assign { } { } - assign $1\main_spi_master_count_spimaster0_next_value[2:0] 3'000 + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init - update \main_spi_master_count_spimaster0_next_value $1\main_spi_master_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1746.5-1746.58" - process $proc$ls180.v:1746$3504 + attribute \src "ls180.v:1784.5-1784.59" + process $proc$ls180.v:1784$3522 assign { } { } - assign $1\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init - update \main_spi_master_count_spimaster0_next_value_ce $1\main_spi_master_count_spimaster0_next_value_ce[0:0] + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1747.5-1747.41" - process $proc$ls180.v:1747$3505 + attribute \src "ls180.v:1785.11-1785.42" + process $proc$ls180.v:1785$3523 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1786.11-1786.47" + process $proc$ls180.v:1786$3524 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1787.11-1787.60" + process $proc$ls180.v:1787$3525 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1788.5-1788.57" + process $proc$ls180.v:1788$3526 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1789.5-1789.41" + process $proc$ls180.v:1789$3527 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1748.5-1748.46" - process $proc$ls180.v:1748$3506 + attribute \src "ls180.v:179.5-179.63" + process $proc$ls180.v:179$2808 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1790.5-1790.46" + process $proc$ls180.v:1790$3528 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1749.11-1749.66" - process $proc$ls180.v:1749$3507 + attribute \src "ls180.v:1791.11-1791.66" + process $proc$ls180.v:1791$3529 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1750.5-1750.63" - process $proc$ls180.v:1750$3508 + attribute \src "ls180.v:1792.5-1792.63" + process $proc$ls180.v:1792$3530 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1751.11-1751.47" - process $proc$ls180.v:1751$3509 + attribute \src "ls180.v:1793.11-1793.47" + process $proc$ls180.v:1793$3531 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1752.11-1752.52" - process $proc$ls180.v:1752$3510 + attribute \src "ls180.v:1794.11-1794.52" + process $proc$ls180.v:1794$3532 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1753.11-1753.66" - process $proc$ls180.v:1753$3511 + attribute \src "ls180.v:1795.11-1795.66" + process $proc$ls180.v:1795$3533 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1754.5-1754.63" - process $proc$ls180.v:1754$3512 + attribute \src "ls180.v:1796.5-1796.63" + process $proc$ls180.v:1796$3534 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:1755.11-1755.47" - process $proc$ls180.v:1755$3513 + attribute \src "ls180.v:1797.11-1797.47" + process $proc$ls180.v:1797$3535 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1756.11-1756.52" - process $proc$ls180.v:1756$3514 + attribute \src "ls180.v:1798.11-1798.52" + process $proc$ls180.v:1798$3536 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1757.11-1757.67" - process $proc$ls180.v:1757$3515 + attribute \src "ls180.v:1799.11-1799.67" + process $proc$ls180.v:1799$3537 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1758.5-1758.64" - process $proc$ls180.v:1758$3516 + attribute \src "ls180.v:180.5-180.63" + process $proc$ls180.v:180$2809 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1800.5-1800.64" + process $proc$ls180.v:1800$3538 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1759.12-1759.71" - process $proc$ls180.v:1759$3517 + attribute \src "ls180.v:1801.12-1801.71" + process $proc$ls180.v:1801$3539 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1760.5-1760.66" - process $proc$ls180.v:1760$3518 + attribute \src "ls180.v:1802.5-1802.66" + process $proc$ls180.v:1802$3540 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1761.5-1761.66" - process $proc$ls180.v:1761$3519 + attribute \src "ls180.v:1803.5-1803.66" + process $proc$ls180.v:1803$3541 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1762.5-1762.69" - process $proc$ls180.v:1762$3520 + attribute \src "ls180.v:1804.5-1804.69" + process $proc$ls180.v:1804$3542 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1763.5-1763.41" - process $proc$ls180.v:1763$3521 + attribute \src "ls180.v:1805.5-1805.41" + process $proc$ls180.v:1805$3543 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1764.5-1764.46" - process $proc$ls180.v:1764$3522 + attribute \src "ls180.v:1806.5-1806.46" + process $proc$ls180.v:1806$3544 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:1765.5-1765.66" - process $proc$ls180.v:1765$3523 + attribute \src "ls180.v:1807.5-1807.66" + process $proc$ls180.v:1807$3545 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1766.5-1766.69" - process $proc$ls180.v:1766$3524 + attribute \src "ls180.v:1808.5-1808.69" + process $proc$ls180.v:1808$3546 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1767.11-1767.41" - process $proc$ls180.v:1767$3525 + attribute \src "ls180.v:1809.11-1809.41" + process $proc$ls180.v:1809$3547 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1768.11-1768.46" - process $proc$ls180.v:1768$3526 + attribute \src "ls180.v:1810.11-1810.46" + process $proc$ls180.v:1810$3548 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1769.11-1769.61" - process $proc$ls180.v:1769$3527 + attribute \src "ls180.v:1811.11-1811.61" + process $proc$ls180.v:1811$3549 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1770.5-1770.58" - process $proc$ls180.v:1770$3528 + attribute \src "ls180.v:1812.5-1812.58" + process $proc$ls180.v:1812$3550 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1771.11-1771.48" - process $proc$ls180.v:1771$3529 + attribute \src "ls180.v:1813.11-1813.48" + process $proc$ls180.v:1813$3551 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1772.11-1772.53" - process $proc$ls180.v:1772$3530 + attribute \src "ls180.v:1814.11-1814.53" + process $proc$ls180.v:1814$3552 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1773.11-1773.70" - process $proc$ls180.v:1773$3531 + attribute \src "ls180.v:1815.11-1815.70" + process $proc$ls180.v:1815$3553 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1774.5-1774.66" - process $proc$ls180.v:1774$3532 + attribute \src "ls180.v:1816.5-1816.66" + process $proc$ls180.v:1816$3554 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1775.12-1775.73" - process $proc$ls180.v:1775$3533 + attribute \src "ls180.v:1817.12-1817.73" + process $proc$ls180.v:1817$3555 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1776.5-1776.68" - process $proc$ls180.v:1776$3534 + attribute \src "ls180.v:1818.5-1818.68" + process $proc$ls180.v:1818$3556 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1777.5-1777.69" - process $proc$ls180.v:1777$3535 + attribute \src "ls180.v:1819.5-1819.69" + process $proc$ls180.v:1819$3557 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1778.5-1778.72" - process $proc$ls180.v:1778$3536 + attribute \src "ls180.v:182.5-182.62" + process $proc$ls180.v:182$2810 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1820.5-1820.72" + process $proc$ls180.v:1820$3558 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1779.5-1779.52" - process $proc$ls180.v:1779$3537 + attribute \src "ls180.v:1821.5-1821.52" + process $proc$ls180.v:1821$3559 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1780.5-1780.57" - process $proc$ls180.v:1780$3538 + attribute \src "ls180.v:1822.5-1822.57" + process $proc$ls180.v:1822$3560 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1781.12-1781.93" - process $proc$ls180.v:1781$3539 + attribute \src "ls180.v:1823.12-1823.93" + process $proc$ls180.v:1823$3561 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1782.5-1782.88" - process $proc$ls180.v:1782$3540 + attribute \src "ls180.v:1824.5-1824.88" + process $proc$ls180.v:1824$3562 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1783.12-1783.93" - process $proc$ls180.v:1783$3541 + attribute \src "ls180.v:1825.12-1825.93" + process $proc$ls180.v:1825$3563 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1784.5-1784.88" - process $proc$ls180.v:1784$3542 + attribute \src "ls180.v:1826.5-1826.88" + process $proc$ls180.v:1826$3564 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:1785.12-1785.93" - process $proc$ls180.v:1785$3543 + attribute \src "ls180.v:1827.12-1827.93" + process $proc$ls180.v:1827$3565 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1786.5-1786.88" - process $proc$ls180.v:1786$3544 + attribute \src "ls180.v:1828.5-1828.88" + process $proc$ls180.v:1828$3566 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1787.12-1787.93" - process $proc$ls180.v:1787$3545 + attribute \src "ls180.v:1829.12-1829.93" + process $proc$ls180.v:1829$3567 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1788.5-1788.88" - process $proc$ls180.v:1788$3546 + attribute \src "ls180.v:183.11-183.69" + process $proc$ls180.v:183$2811 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1830.5-1830.88" + process $proc$ls180.v:1830$3568 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1789.11-1789.87" - process $proc$ls180.v:1789$3547 + attribute \src "ls180.v:1831.11-1831.87" + process $proc$ls180.v:1831$3569 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1790.5-1790.84" - process $proc$ls180.v:1790$3548 + attribute \src "ls180.v:1832.5-1832.84" + process $proc$ls180.v:1832$3570 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1791.11-1791.42" - process $proc$ls180.v:1791$3549 + attribute \src "ls180.v:1833.11-1833.42" + process $proc$ls180.v:1833$3571 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1792.11-1792.47" - process $proc$ls180.v:1792$3550 + attribute \src "ls180.v:1834.11-1834.47" + process $proc$ls180.v:1834$3572 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1793.5-1793.55" - process $proc$ls180.v:1793$3551 + attribute \src "ls180.v:1835.5-1835.55" + process $proc$ls180.v:1835$3573 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1794.5-1794.58" - process $proc$ls180.v:1794$3552 + attribute \src "ls180.v:1836.5-1836.58" + process $proc$ls180.v:1836$3574 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:1795.5-1795.56" - process $proc$ls180.v:1795$3553 + attribute \src "ls180.v:1837.5-1837.56" + process $proc$ls180.v:1837$3575 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1796.5-1796.59" - process $proc$ls180.v:1796$3554 + attribute \src "ls180.v:1838.5-1838.59" + process $proc$ls180.v:1838$3576 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1797.11-1797.62" - process $proc$ls180.v:1797$3555 + attribute \src "ls180.v:1839.11-1839.62" + process $proc$ls180.v:1839$3577 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1798.5-1798.59" - process $proc$ls180.v:1798$3556 + attribute \src "ls180.v:184.11-184.69" + process $proc$ls180.v:184$2812 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1840.5-1840.59" + process $proc$ls180.v:1840$3578 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1799.12-1799.65" - process $proc$ls180.v:1799$3557 + attribute \src "ls180.v:1841.12-1841.65" + process $proc$ls180.v:1841$3579 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1800.5-1800.60" - process $proc$ls180.v:1800$3558 + attribute \src "ls180.v:1842.5-1842.60" + process $proc$ls180.v:1842$3580 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1801.5-1801.56" - process $proc$ls180.v:1801$3559 + attribute \src "ls180.v:1843.5-1843.56" + process $proc$ls180.v:1843$3581 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1802.5-1802.59" - process $proc$ls180.v:1802$3560 + attribute \src "ls180.v:1844.5-1844.59" + process $proc$ls180.v:1844$3582 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1803.5-1803.58" - process $proc$ls180.v:1803$3561 + attribute \src "ls180.v:1845.5-1845.58" + process $proc$ls180.v:1845$3583 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1804.5-1804.61" - process $proc$ls180.v:1804$3562 + attribute \src "ls180.v:1846.5-1846.61" + process $proc$ls180.v:1846$3584 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:1805.5-1805.57" - process $proc$ls180.v:1805$3563 + attribute \src "ls180.v:1847.5-1847.57" + process $proc$ls180.v:1847$3585 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1806.5-1806.60" - process $proc$ls180.v:1806$3564 + attribute \src "ls180.v:1848.5-1848.60" + process $proc$ls180.v:1848$3586 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1807.5-1807.59" - process $proc$ls180.v:1807$3565 + attribute \src "ls180.v:1849.5-1849.59" + process $proc$ls180.v:1849$3587 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1808.5-1808.62" - process $proc$ls180.v:1808$3566 + attribute \src "ls180.v:1850.5-1850.62" + process $proc$ls180.v:1850$3588 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1809.13-1809.76" - process $proc$ls180.v:1809$3567 + attribute \src "ls180.v:1851.13-1851.76" + process $proc$ls180.v:1851$3589 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:181.5-181.40" - process $proc$ls180.v:181$2811 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:1810.5-1810.69" - process $proc$ls180.v:1810$3568 + attribute \src "ls180.v:1852.5-1852.69" + process $proc$ls180.v:1852$3590 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1811.11-1811.46" - process $proc$ls180.v:1811$3569 + attribute \src "ls180.v:1853.11-1853.46" + process $proc$ls180.v:1853$3591 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1812.11-1812.51" - process $proc$ls180.v:1812$3570 + attribute \src "ls180.v:1854.11-1854.51" + process $proc$ls180.v:1854$3592 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1813.12-1813.87" - process $proc$ls180.v:1813$3571 + attribute \src "ls180.v:1855.12-1855.87" + process $proc$ls180.v:1855$3593 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1814.5-1814.82" - process $proc$ls180.v:1814$3572 + attribute \src "ls180.v:1856.5-1856.82" + process $proc$ls180.v:1856$3594 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1815.5-1815.44" - process $proc$ls180.v:1815$3573 + attribute \src "ls180.v:1857.5-1857.44" + process $proc$ls180.v:1857$3595 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1816.5-1816.49" - process $proc$ls180.v:1816$3574 + attribute \src "ls180.v:1858.5-1858.49" + process $proc$ls180.v:1858$3596 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1817.12-1817.75" - process $proc$ls180.v:1817$3575 + attribute \src "ls180.v:1859.12-1859.75" + process $proc$ls180.v:1859$3597 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] end - attribute \src "ls180.v:1818.5-1818.70" - process $proc$ls180.v:1818$3576 + attribute \src "ls180.v:186.5-186.44" + process $proc$ls180.v:186$2813 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1860.5-1860.70" + process $proc$ls180.v:1860$3598 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1819.11-1819.60" - process $proc$ls180.v:1819$3577 + attribute \src "ls180.v:1861.11-1861.60" + process $proc$ls180.v:1861$3599 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1820.11-1820.65" - process $proc$ls180.v:1820$3578 + attribute \src "ls180.v:1862.11-1862.65" + process $proc$ls180.v:1862$3600 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1821.12-1821.87" - process $proc$ls180.v:1821$3579 + attribute \src "ls180.v:1863.12-1863.87" + process $proc$ls180.v:1863$3601 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1822.5-1822.82" - process $proc$ls180.v:1822$3580 + attribute \src "ls180.v:1864.5-1864.82" + process $proc$ls180.v:1864$3602 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1823.11-1823.42" - process $proc$ls180.v:1823$3581 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1824.11-1824.47" - process $proc$ls180.v:1824$3582 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1825.11-1825.57" - process $proc$ls180.v:1825$3583 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1826.5-1826.54" - process $proc$ls180.v:1826$3584 - assign { } { } - assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1827.12-1827.43" - process $proc$ls180.v:1827$3585 + attribute \src "ls180.v:1865.12-1865.43" + process $proc$ls180.v:1865$3603 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1828.5-1828.34" - process $proc$ls180.v:1828$3586 + attribute \src "ls180.v:1866.5-1866.34" + process $proc$ls180.v:1866$3604 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:1829.11-1829.43" - process $proc$ls180.v:1829$3587 + attribute \src "ls180.v:1867.11-1867.43" + process $proc$ls180.v:1867$3605 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1833.12-1833.54" - process $proc$ls180.v:1833$3588 + attribute \src "ls180.v:187.5-187.47" + process $proc$ls180.v:187$2814 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1871.12-1871.54" + process $proc$ls180.v:1871$3606 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1837.5-1837.44" - process $proc$ls180.v:1837$3589 + attribute \src "ls180.v:1875.5-1875.44" + process $proc$ls180.v:1875$3607 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1841.5-1841.44" - process $proc$ls180.v:1841$3590 + attribute \src "ls180.v:1879.5-1879.44" + process $proc$ls180.v:1879$3608 assign { } { } assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 sync always update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] sync init end - attribute \src "ls180.v:1844.12-1844.40" - process $proc$ls180.v:1844$3591 + attribute \src "ls180.v:1882.12-1882.40" + process $proc$ls180.v:1882$3609 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always sync init update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:1848.5-1848.30" - process $proc$ls180.v:1848$3592 + attribute \src "ls180.v:1886.5-1886.30" + process $proc$ls180.v:1886$3610 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always sync init update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:185.5-185.40" - process $proc$ls180.v:185$2812 + attribute \src "ls180.v:189.12-189.53" + process $proc$ls180.v:189$2815 assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] end - attribute \src "ls180.v:1854.11-1854.31" - process $proc$ls180.v:1854$3593 + attribute \src "ls180.v:1892.11-1892.31" + process $proc$ls180.v:1892$3611 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always sync init update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:1855.11-1855.35" - process $proc$ls180.v:1855$3594 + attribute \src "ls180.v:1893.11-1893.35" + process $proc$ls180.v:1893$3612 assign { } { } assign $1\builder_slave_sel[4:0] 5'00000 sync always sync init update \builder_slave_sel $1\builder_slave_sel[4:0] end - attribute \src "ls180.v:1856.11-1856.37" - process $proc$ls180.v:1856$3595 + attribute \src "ls180.v:1894.11-1894.37" + process $proc$ls180.v:1894$3613 assign { } { } assign $1\builder_slave_sel_r[4:0] 5'00000 sync always sync init update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] end - attribute \src "ls180.v:1857.5-1857.25" - process $proc$ls180.v:1857$3596 + attribute \src "ls180.v:1895.5-1895.25" + process $proc$ls180.v:1895$3614 assign { } { } assign $1\builder_error[0:0] 1'0 sync always sync init update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:1860.12-1860.39" - process $proc$ls180.v:1860$3597 + attribute \src "ls180.v:1898.12-1898.39" + process $proc$ls180.v:1898$3615 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:1864.11-1864.51" - process $proc$ls180.v:1864$3598 + attribute \src "ls180.v:190.12-190.71" + process $proc$ls180.v:190$2816 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1902.11-1902.51" + process $proc$ls180.v:1902$3616 assign { } { } assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:188.11-188.37" - process $proc$ls180.v:188$2813 + attribute \src "ls180.v:191.12-191.73" + process $proc$ls180.v:191$2817 assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 sync always sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:190.12-190.49" - process $proc$ls180.v:190$2814 + attribute \src "ls180.v:193.11-193.69" + process $proc$ls180.v:193$2818 assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 sync always sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] end - attribute \src "ls180.v:1905.11-1905.51" - process $proc$ls180.v:1905$3599 + attribute \src "ls180.v:194.5-194.63" + process $proc$ls180.v:194$2819 assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 sync always sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] end - attribute \src "ls180.v:191.5-191.36" - process $proc$ls180.v:191$2815 + attribute \src "ls180.v:1943.11-1943.51" + process $proc$ls180.v:1943$3617 assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:192.12-192.51" - process $proc$ls180.v:192$2816 + attribute \src "ls180.v:195.5-195.63" + process $proc$ls180.v:195$2820 assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 sync always sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] end - attribute \src "ls180.v:193.5-193.38" - process $proc$ls180.v:193$2817 + attribute \src "ls180.v:197.5-197.62" + process $proc$ls180.v:197$2821 assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 sync always sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] end - attribute \src "ls180.v:1934.11-1934.51" - process $proc$ls180.v:1934$3600 + attribute \src "ls180.v:1972.11-1972.51" + process $proc$ls180.v:1972$3618 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:194.5-194.39" - process $proc$ls180.v:194$2818 + attribute \src "ls180.v:198.11-198.69" + process $proc$ls180.v:198$2822 assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end - attribute \src "ls180.v:195.5-195.34" - process $proc$ls180.v:195$2819 + attribute \src "ls180.v:1985.11-1985.51" + process $proc$ls180.v:1985$3619 assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:196.5-196.49" - process $proc$ls180.v:196$2820 + attribute \src "ls180.v:199.11-199.69" + process $proc$ls180.v:199$2823 assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:197.5-197.44" - process $proc$ls180.v:197$2821 + attribute \src "ls180.v:201.5-201.44" + process $proc$ls180.v:201$2824 assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 sync always sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] end - attribute \src "ls180.v:1975.11-1975.51" - process $proc$ls180.v:1975$3601 + attribute \src "ls180.v:202.5-202.47" + process $proc$ls180.v:202$2825 assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 sync always sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] end - attribute \src "ls180.v:198.12-198.49" - process $proc$ls180.v:198$2822 + attribute \src "ls180.v:2026.11-2026.51" + process $proc$ls180.v:2026$3620 assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2016.11-2016.51" - process $proc$ls180.v:2016$3602 + attribute \src "ls180.v:204.12-204.53" + process $proc$ls180.v:204$2826 assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] end - attribute \src "ls180.v:202.5-202.41" - process $proc$ls180.v:202$2823 + attribute \src "ls180.v:2067.11-2067.51" + process $proc$ls180.v:2067$3621 assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:204.5-204.39" - process $proc$ls180.v:204$2824 + attribute \src "ls180.v:211.5-211.40" + process $proc$ls180.v:211$2827 assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:205.5-205.45" - process $proc$ls180.v:205$2825 + attribute \src "ls180.v:2132.11-2132.51" + process $proc$ls180.v:2132$3622 assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2081.11-2081.51" - process $proc$ls180.v:2081$3603 + attribute \src "ls180.v:215.5-215.40" + process $proc$ls180.v:215$2828 assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:214.5-214.49" - process $proc$ls180.v:214$2826 + attribute \src "ls180.v:218.11-218.37" + process $proc$ls180.v:218$2829 assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $1\main_libresocsim_we[3:0] 4'0000 sync always sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_we $1\main_libresocsim_we[3:0] end - attribute \src "ls180.v:215.5-215.44" - process $proc$ls180.v:215$2827 + attribute \src "ls180.v:220.12-220.49" + process $proc$ls180.v:220$2830 assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $1\main_libresocsim_load_storage[31:0] 0 sync always sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] end - attribute \src "ls180.v:216.12-216.42" - process $proc$ls180.v:216$2828 + attribute \src "ls180.v:221.5-221.36" + process $proc$ls180.v:221$2831 assign { } { } - assign $1\main_libresocsim_value[31:0] 0 + assign $1\main_libresocsim_load_re[0:0] 1'0 sync always sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] end - attribute \src "ls180.v:220.5-220.24" - process $proc$ls180.v:220$2829 + attribute \src "ls180.v:222.12-222.51" + process $proc$ls180.v:222$2832 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\main_libresocsim_reload_storage[31:0] 0 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:2214.11-2214.51" - process $proc$ls180.v:2214$3604 + attribute \src "ls180.v:223.5-223.38" + process $proc$ls180.v:223$2833 assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_reload_re[0:0] 1'0 sync always sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] end - attribute \src "ls180.v:2295.11-2295.51" - process $proc$ls180.v:2295$3605 + attribute \src "ls180.v:224.5-224.39" + process $proc$ls180.v:224$2834 assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_en_storage[0:0] 1'0 sync always sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] end - attribute \src "ls180.v:2312.11-2312.51" - process $proc$ls180.v:2312$3606 + attribute \src "ls180.v:225.5-225.34" + process $proc$ls180.v:225$2835 assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_en_re[0:0] 1'0 sync always sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] end - attribute \src "ls180.v:235.12-235.38" - process $proc$ls180.v:235$2830 + attribute \src "ls180.v:226.5-226.49" + process $proc$ls180.v:226$2836 assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:2353.11-2353.51" - process $proc$ls180.v:2353$3607 + attribute \src "ls180.v:2265.11-2265.51" + process $proc$ls180.v:2265$3623 assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:236.5-236.36" - process $proc$ls180.v:236$2831 + attribute \src "ls180.v:227.5-227.44" + process $proc$ls180.v:227$2837 assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $1\main_libresocsim_update_value_re[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] end - attribute \src "ls180.v:237.11-237.32" - process $proc$ls180.v:237$2832 + attribute \src "ls180.v:228.12-228.49" + process $proc$ls180.v:228$2838 assign { } { } - assign $1\main_rddata_en[2:0] 3'000 + assign $1\main_libresocsim_value_status[31:0] 0 sync always sync init - update \main_rddata_en $1\main_rddata_en[2:0] + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] end - attribute \src "ls180.v:2386.11-2386.52" - process $proc$ls180.v:2386$3608 + attribute \src "ls180.v:232.5-232.41" + process $proc$ls180.v:232$2839 assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_zero_pending[0:0] 1'0 sync always sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:240.5-240.36" - process $proc$ls180.v:240$2833 + attribute \src "ls180.v:234.5-234.39" + process $proc$ls180.v:234$2840 assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:241.5-241.35" - process $proc$ls180.v:241$2834 + attribute \src "ls180.v:2346.11-2346.51" + process $proc$ls180.v:2346$3624 assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:242.5-242.36" - process $proc$ls180.v:242$2835 + attribute \src "ls180.v:235.5-235.45" + process $proc$ls180.v:235$2841 assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2363.11-2363.51" + process $proc$ls180.v:2363$3625 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2427.11-2427.52" - process $proc$ls180.v:2427$3609 + attribute \src "ls180.v:2404.11-2404.52" + process $proc$ls180.v:2404$3626 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2437.11-2437.52" + process $proc$ls180.v:2437$3627 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:243.5-243.35" - process $proc$ls180.v:243$2836 + attribute \src "ls180.v:244.5-244.49" + process $proc$ls180.v:244$2842 assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:247.5-247.36" - process $proc$ls180.v:247$2837 + attribute \src "ls180.v:245.5-245.44" + process $proc$ls180.v:245$2843 assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:246.12-246.42" + process $proc$ls180.v:246$2844 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:2492.11-2492.52" - process $proc$ls180.v:2492$3610 + attribute \src "ls180.v:2478.11-2478.52" + process $proc$ls180.v:2478$3628 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2517.11-2517.52" - process $proc$ls180.v:2517$3611 + attribute \src "ls180.v:250.5-250.24" + process $proc$ls180.v:250$2845 assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_int_rst[0:0] 1'1 sync always sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:252.12-252.45" - process $proc$ls180.v:252$2838 + attribute \src "ls180.v:2543.11-2543.52" + process $proc$ls180.v:2543$3629 assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:253.5-253.43" - process $proc$ls180.v:253$2839 + attribute \src "ls180.v:2568.11-2568.52" + process $proc$ls180.v:2568$3630 assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2539.11-2539.31" - process $proc$ls180.v:2539$3612 + attribute \src "ls180.v:2590.11-2590.31" + process $proc$ls180.v:2590$3631 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2540.11-2540.36" - process $proc$ls180.v:2540$3613 + attribute \src "ls180.v:2591.11-2591.36" + process $proc$ls180.v:2591$3632 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2541.11-2541.55" - process $proc$ls180.v:2541$3614 + attribute \src "ls180.v:2592.11-2592.55" + process $proc$ls180.v:2592$3633 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2542.5-2542.52" - process $proc$ls180.v:2542$3615 + attribute \src "ls180.v:2593.5-2593.52" + process $proc$ls180.v:2593$3634 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2543.12-2543.55" - process $proc$ls180.v:2543$3616 + attribute \src "ls180.v:2594.12-2594.55" + process $proc$ls180.v:2594$3635 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2544.5-2544.50" - process $proc$ls180.v:2544$3617 + attribute \src "ls180.v:2595.5-2595.50" + process $proc$ls180.v:2595$3636 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2545.5-2545.46" - process $proc$ls180.v:2545$3618 + attribute \src "ls180.v:2596.5-2596.46" + process $proc$ls180.v:2596$3637 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2546.5-2546.49" - process $proc$ls180.v:2546$3619 + attribute \src "ls180.v:2597.5-2597.49" + process $proc$ls180.v:2597$3638 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2547.5-2547.41" - process $proc$ls180.v:2547$3620 + attribute \src "ls180.v:2598.5-2598.41" + process $proc$ls180.v:2598$3639 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2548.12-2548.49" - process $proc$ls180.v:2548$3621 + attribute \src "ls180.v:2599.12-2599.49" + process $proc$ls180.v:2599$3640 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2549.11-2549.47" - process $proc$ls180.v:2549$3622 + attribute \src "ls180.v:2600.11-2600.47" + process $proc$ls180.v:2600$3641 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2550.5-2550.41" - process $proc$ls180.v:2550$3623 + attribute \src "ls180.v:2601.5-2601.41" + process $proc$ls180.v:2601$3642 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2551.5-2551.41" - process $proc$ls180.v:2551$3624 + attribute \src "ls180.v:2602.5-2602.41" + process $proc$ls180.v:2602$3643 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2552.5-2552.41" - process $proc$ls180.v:2552$3625 + attribute \src "ls180.v:2603.5-2603.41" + process $proc$ls180.v:2603$3644 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2553.5-2553.39" - process $proc$ls180.v:2553$3626 + attribute \src "ls180.v:2604.5-2604.39" + process $proc$ls180.v:2604$3645 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2554.5-2554.39" - process $proc$ls180.v:2554$3627 + attribute \src "ls180.v:2605.5-2605.39" + process $proc$ls180.v:2605$3646 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2555.5-2555.39" - process $proc$ls180.v:2555$3628 + attribute \src "ls180.v:2606.5-2606.39" + process $proc$ls180.v:2606$3647 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2556.5-2556.41" - process $proc$ls180.v:2556$3629 + attribute \src "ls180.v:2607.5-2607.41" + process $proc$ls180.v:2607$3648 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2557.12-2557.49" - process $proc$ls180.v:2557$3630 + attribute \src "ls180.v:2608.12-2608.49" + process $proc$ls180.v:2608$3649 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2558.11-2558.47" - process $proc$ls180.v:2558$3631 + attribute \src "ls180.v:2609.11-2609.47" + process $proc$ls180.v:2609$3650 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2559.5-2559.41" - process $proc$ls180.v:2559$3632 + attribute \src "ls180.v:2610.5-2610.41" + process $proc$ls180.v:2610$3651 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2560.5-2560.42" - process $proc$ls180.v:2560$3633 + attribute \src "ls180.v:2611.5-2611.42" + process $proc$ls180.v:2611$3652 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2561.5-2561.42" - process $proc$ls180.v:2561$3634 + attribute \src "ls180.v:2612.5-2612.42" + process $proc$ls180.v:2612$3653 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2562.5-2562.39" - process $proc$ls180.v:2562$3635 + attribute \src "ls180.v:2613.5-2613.39" + process $proc$ls180.v:2613$3654 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2563.5-2563.39" - process $proc$ls180.v:2563$3636 + attribute \src "ls180.v:2614.5-2614.39" + process $proc$ls180.v:2614$3655 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2564.5-2564.39" - process $proc$ls180.v:2564$3637 + attribute \src "ls180.v:2615.5-2615.39" + process $proc$ls180.v:2615$3656 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2565.12-2565.50" - process $proc$ls180.v:2565$3638 + attribute \src "ls180.v:2616.12-2616.50" + process $proc$ls180.v:2616$3657 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2566.5-2566.42" - process $proc$ls180.v:2566$3639 + attribute \src "ls180.v:2617.5-2617.42" + process $proc$ls180.v:2617$3658 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2567.5-2567.42" - process $proc$ls180.v:2567$3640 + attribute \src "ls180.v:2618.5-2618.42" + process $proc$ls180.v:2618$3659 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2568.12-2568.50" - process $proc$ls180.v:2568$3641 + attribute \src "ls180.v:2619.12-2619.50" + process $proc$ls180.v:2619$3660 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2569.5-2569.42" - process $proc$ls180.v:2569$3642 + attribute \src "ls180.v:2620.5-2620.42" + process $proc$ls180.v:2620$3661 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2570.5-2570.42" - process $proc$ls180.v:2570$3643 + attribute \src "ls180.v:2621.5-2621.42" + process $proc$ls180.v:2621$3662 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2571.12-2571.50" - process $proc$ls180.v:2571$3644 + attribute \src "ls180.v:2622.12-2622.50" + process $proc$ls180.v:2622$3663 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2572.5-2572.42" - process $proc$ls180.v:2572$3645 + attribute \src "ls180.v:2623.5-2623.42" + process $proc$ls180.v:2623$3664 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2573.5-2573.42" - process $proc$ls180.v:2573$3646 + attribute \src "ls180.v:2624.5-2624.42" + process $proc$ls180.v:2624$3665 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2574.12-2574.50" - process $proc$ls180.v:2574$3647 + attribute \src "ls180.v:2625.12-2625.50" + process $proc$ls180.v:2625$3666 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2575.5-2575.42" - process $proc$ls180.v:2575$3648 + attribute \src "ls180.v:2626.5-2626.42" + process $proc$ls180.v:2626$3667 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2576.5-2576.42" - process $proc$ls180.v:2576$3649 + attribute \src "ls180.v:2627.5-2627.42" + process $proc$ls180.v:2627$3668 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2577.12-2577.50" - process $proc$ls180.v:2577$3650 + attribute \src "ls180.v:2628.12-2628.50" + process $proc$ls180.v:2628$3669 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2578.12-2578.50" - process $proc$ls180.v:2578$3651 + attribute \src "ls180.v:2629.12-2629.50" + process $proc$ls180.v:2629$3670 assign { } { } assign $1\builder_comb_rhs_array_muxed25[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] end - attribute \src "ls180.v:2579.11-2579.48" - process $proc$ls180.v:2579$3652 + attribute \src "ls180.v:2630.11-2630.48" + process $proc$ls180.v:2630$3671 assign { } { } assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 sync always sync init update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] end - attribute \src "ls180.v:2580.5-2580.42" - process $proc$ls180.v:2580$3653 + attribute \src "ls180.v:2631.5-2631.42" + process $proc$ls180.v:2631$3672 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2581.5-2581.42" - process $proc$ls180.v:2581$3654 + attribute \src "ls180.v:2632.5-2632.42" + process $proc$ls180.v:2632$3673 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2582.5-2582.42" - process $proc$ls180.v:2582$3655 + attribute \src "ls180.v:2633.5-2633.42" + process $proc$ls180.v:2633$3674 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2583.11-2583.48" - process $proc$ls180.v:2583$3656 + attribute \src "ls180.v:2634.11-2634.48" + process $proc$ls180.v:2634$3675 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2584.11-2584.48" - process $proc$ls180.v:2584$3657 + attribute \src "ls180.v:2635.11-2635.48" + process $proc$ls180.v:2635$3676 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2585.11-2585.47" - process $proc$ls180.v:2585$3658 + attribute \src "ls180.v:2636.11-2636.47" + process $proc$ls180.v:2636$3677 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2586.12-2586.49" - process $proc$ls180.v:2586$3659 + attribute \src "ls180.v:2637.12-2637.49" + process $proc$ls180.v:2637$3678 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2587.5-2587.41" - process $proc$ls180.v:2587$3660 + attribute \src "ls180.v:2638.5-2638.41" + process $proc$ls180.v:2638$3679 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2588.5-2588.41" - process $proc$ls180.v:2588$3661 + attribute \src "ls180.v:2639.5-2639.41" + process $proc$ls180.v:2639$3680 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2589.5-2589.41" - process $proc$ls180.v:2589$3662 + attribute \src "ls180.v:2640.5-2640.41" + process $proc$ls180.v:2640$3681 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2590.5-2590.41" - process $proc$ls180.v:2590$3663 + attribute \src "ls180.v:2641.5-2641.41" + process $proc$ls180.v:2641$3682 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2591.5-2591.41" - process $proc$ls180.v:2591$3664 + attribute \src "ls180.v:2642.5-2642.41" + process $proc$ls180.v:2642$3683 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2592.5-2592.39" - process $proc$ls180.v:2592$3665 + attribute \src "ls180.v:2643.5-2643.39" + process $proc$ls180.v:2643$3684 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2593.5-2593.39" - process $proc$ls180.v:2593$3666 + attribute \src "ls180.v:2644.5-2644.39" + process $proc$ls180.v:2644$3685 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:2650.32-2650.66" - process $proc$ls180.v:2650$3667 + attribute \src "ls180.v:265.12-265.38" + process $proc$ls180.v:265$2846 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:266.5-266.36" + process $proc$ls180.v:266$2847 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:267.11-267.32" + process $proc$ls180.v:267$2848 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:270.5-270.36" + process $proc$ls180.v:270$2849 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:2701.32-2701.66" + process $proc$ls180.v:2701$3686 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2651.32-2651.66" - process $proc$ls180.v:2651$3668 + attribute \src "ls180.v:2702.32-2702.66" + process $proc$ls180.v:2702$3687 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2652.32-2652.66" - process $proc$ls180.v:2652$3669 + attribute \src "ls180.v:2703.32-2703.66" + process $proc$ls180.v:2703$3688 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2653.32-2653.66" - process $proc$ls180.v:2653$3670 + attribute \src "ls180.v:2704.32-2704.66" + process $proc$ls180.v:2704$3689 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2654.32-2654.66" - process $proc$ls180.v:2654$3671 + attribute \src "ls180.v:2705.32-2705.66" + process $proc$ls180.v:2705$3690 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2655.32-2655.66" - process $proc$ls180.v:2655$3672 + attribute \src "ls180.v:2706.32-2706.66" + process $proc$ls180.v:2706$3691 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2656.32-2656.66" - process $proc$ls180.v:2656$3673 + attribute \src "ls180.v:2707.32-2707.66" + process $proc$ls180.v:2707$3692 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2657.32-2657.66" - process $proc$ls180.v:2657$3674 + attribute \src "ls180.v:2708.32-2708.66" + process $proc$ls180.v:2708$3693 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2658.32-2658.66" - process $proc$ls180.v:2658$3675 + attribute \src "ls180.v:2709.32-2709.66" + process $proc$ls180.v:2709$3694 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2659.32-2659.66" - process $proc$ls180.v:2659$3676 + attribute \src "ls180.v:271.5-271.35" + process $proc$ls180.v:271$2850 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:2710.32-2710.66" + process $proc$ls180.v:2710$3695 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2660.32-2660.66" - process $proc$ls180.v:2660$3677 + attribute \src "ls180.v:2711.32-2711.66" + process $proc$ls180.v:2711$3696 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2661.32-2661.66" - process $proc$ls180.v:2661$3678 + attribute \src "ls180.v:2712.32-2712.66" + process $proc$ls180.v:2712$3697 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2662.32-2662.66" - process $proc$ls180.v:2662$3679 + attribute \src "ls180.v:2713.32-2713.66" + process $proc$ls180.v:2713$3698 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2663.32-2663.66" - process $proc$ls180.v:2663$3680 + attribute \src "ls180.v:2714.32-2714.66" + process $proc$ls180.v:2714$3699 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2664.32-2664.66" - process $proc$ls180.v:2664$3681 + attribute \src "ls180.v:2715.32-2715.66" + process $proc$ls180.v:2715$3700 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2665.32-2665.66" - process $proc$ls180.v:2665$3682 + attribute \src "ls180.v:2716.32-2716.66" + process $proc$ls180.v:2716$3701 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2666.32-2666.66" - process $proc$ls180.v:2666$3683 + attribute \src "ls180.v:2717.32-2717.66" + process $proc$ls180.v:2717$3702 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2667.32-2667.66" - process $proc$ls180.v:2667$3684 + attribute \src "ls180.v:2718.32-2718.66" + process $proc$ls180.v:2718$3703 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2668.32-2668.66" - process $proc$ls180.v:2668$3685 + attribute \src "ls180.v:2719.32-2719.66" + process $proc$ls180.v:2719$3704 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2669.32-2669.66" - process $proc$ls180.v:2669$3686 + attribute \src "ls180.v:272.5-272.36" + process $proc$ls180.v:272$2851 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:2720.32-2720.66" + process $proc$ls180.v:2720$3705 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2670.32-2670.67" - process $proc$ls180.v:2670$3687 + attribute \src "ls180.v:2721.32-2721.67" + process $proc$ls180.v:2721$3706 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2671.32-2671.67" - process $proc$ls180.v:2671$3688 + attribute \src "ls180.v:2722.32-2722.67" + process $proc$ls180.v:2722$3707 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2672.32-2672.67" - process $proc$ls180.v:2672$3689 + attribute \src "ls180.v:2723.32-2723.67" + process $proc$ls180.v:2723$3708 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2673.32-2673.67" - process $proc$ls180.v:2673$3690 + attribute \src "ls180.v:2724.32-2724.67" + process $proc$ls180.v:2724$3709 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2674.32-2674.67" - process $proc$ls180.v:2674$3691 + attribute \src "ls180.v:2725.32-2725.67" + process $proc$ls180.v:2725$3710 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2675.32-2675.67" - process $proc$ls180.v:2675$3692 + attribute \src "ls180.v:2726.32-2726.67" + process $proc$ls180.v:2726$3711 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2676.32-2676.67" - process $proc$ls180.v:2676$3693 + attribute \src "ls180.v:2727.32-2727.67" + process $proc$ls180.v:2727$3712 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2677.32-2677.67" - process $proc$ls180.v:2677$3694 + attribute \src "ls180.v:2728.32-2728.67" + process $proc$ls180.v:2728$3713 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2678.32-2678.67" - process $proc$ls180.v:2678$3695 + attribute \src "ls180.v:2729.32-2729.67" + process $proc$ls180.v:2729$3714 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2679.32-2679.67" - process $proc$ls180.v:2679$3696 + attribute \src "ls180.v:273.5-273.35" + process $proc$ls180.v:273$2852 assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:268.12-268.46" - process $proc$ls180.v:268$2840 + attribute \src "ls180.v:2730.32-2730.67" + process $proc$ls180.v:2730$3715 assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2680.32-2680.67" - process $proc$ls180.v:2680$3697 + attribute \src "ls180.v:2731.32-2731.67" + process $proc$ls180.v:2731$3716 assign { } { } assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2681.32-2681.67" - process $proc$ls180.v:2681$3698 + attribute \src "ls180.v:2732.32-2732.67" + process $proc$ls180.v:2732$3717 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2682.32-2682.67" - process $proc$ls180.v:2682$3699 + attribute \src "ls180.v:2733.32-2733.67" + process $proc$ls180.v:2733$3718 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2683.32-2683.67" - process $proc$ls180.v:2683$3700 + attribute \src "ls180.v:2734.32-2734.67" + process $proc$ls180.v:2734$3719 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:269.5-269.44" - process $proc$ls180.v:269$2841 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:270.12-270.48" - process $proc$ls180.v:270$2842 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:271.11-271.43" - process $proc$ls180.v:271$2843 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:272.5-272.38" - process $proc$ls180.v:272$2844 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:2720.1-2725.4" - process $proc$ls180.v:2720$13 + attribute \src "ls180.v:2768.1-2773.4" + process $proc$ls180.v:2768$13 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -262750,11 +268837,19 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:2727.1-2737.4" - process $proc$ls180.v:2727$15 + attribute \src "ls180.v:277.5-277.36" + process $proc$ls180.v:277$2853 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2775.1-2785.4" + process $proc$ls180.v:2775$15 assign { } { } assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2729.2-2736.9" + attribute \src "ls180.v:2777.2-2784.9" switch \main_libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262767,16 +268862,8 @@ module \ls180 sync always update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:273.5-273.37" - process $proc$ls180.v:273$2845 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:2739.1-2785.4" - process $proc$ls180.v:2739$16 + attribute \src "ls180.v:2787.1-2833.4" + process $proc$ls180.v:2787$16 assign { } { } assign { } { } assign { } { } @@ -262788,22 +268875,22 @@ module \ls180 assign { } { } assign { } { } assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 assign $0\main_libresocsim_converter0_skip[0:0] 1'0 assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign { } { } assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2751.2-2784.9" + attribute \src "ls180.v:2799.2-2832.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2754.4-2761.11" + attribute \src "ls180.v:2802.4-2809.11" switch \main_libresocsim_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262813,23 +268900,23 @@ module \ls180 assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] case end - attribute \src "ls180.v:2762.4-2775.7" - switch $and$ls180.v:2762$17_Y - attribute \src "ls180.v:2762.8-2762.81" + attribute \src "ls180.v:2810.4-2823.7" + switch $and$ls180.v:2810$17_Y + attribute \src "ls180.v:2810.8-2810.81" case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2763$18_Y + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2811$18_Y assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2765$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2766$20_Y - attribute \src "ls180.v:2767.5-2774.8" - switch $or$ls180.v:2767$21_Y - attribute \src "ls180.v:2767.9-2767.97" + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2813$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2814$20_Y + attribute \src "ls180.v:2815.5-2822.8" + switch $or$ls180.v:2815$21_Y + attribute \src "ls180.v:2815.9-2815.97" case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2768$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2816$22_Y assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2770.6-2773.9" - switch $eq$ls180.v:2770$23_Y - attribute \src "ls180.v:2770.10-2770.55" + attribute \src "ls180.v:2818.6-2821.9" + switch $eq$ls180.v:2818$23_Y + attribute \src "ls180.v:2818.10-2818.55" case 1'1 assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 @@ -262843,9 +268930,9 @@ module \ls180 case assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2780.4-2782.7" - switch $and$ls180.v:2780$24_Y - attribute \src "ls180.v:2780.8-2780.81" + attribute \src "ls180.v:2828.4-2830.7" + switch $and$ls180.v:2828$24_Y + attribute \src "ls180.v:2828.8-2828.81" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case @@ -262863,51 +268950,27 @@ module \ls180 update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:274.5-274.38" - process $proc$ls180.v:274$2846 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:275.5-275.37" - process $proc$ls180.v:275$2847 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:276.5-276.36" - process $proc$ls180.v:276$2848 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:277.5-277.36" - process $proc$ls180.v:277$2849 + attribute \src "ls180.v:282.12-282.45" + process $proc$ls180.v:282$2854 assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:278.5-278.40" - process $proc$ls180.v:278$2850 + attribute \src "ls180.v:283.5-283.43" + process $proc$ls180.v:283$2855 assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2787.1-2797.4" - process $proc$ls180.v:2787$26 + attribute \src "ls180.v:2835.1-2845.4" + process $proc$ls180.v:2835$26 assign { } { } assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2789.2-2796.9" + attribute \src "ls180.v:2837.2-2844.9" switch \main_libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262920,16 +268983,8 @@ module \ls180 sync always update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:279.5-279.38" - process $proc$ls180.v:279$2851 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:2799.1-2845.4" - process $proc$ls180.v:2799$27 + attribute \src "ls180.v:2847.1-2893.4" + process $proc$ls180.v:2847$27 assign { } { } assign { } { } assign { } { } @@ -262940,23 +268995,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 assign { } { } assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2811.2-2844.9" + attribute \src "ls180.v:2859.2-2892.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2814.4-2821.11" + attribute \src "ls180.v:2862.4-2869.11" switch \main_libresocsim_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -262966,23 +269021,23 @@ module \ls180 assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] case end - attribute \src "ls180.v:2822.4-2835.7" - switch $and$ls180.v:2822$28_Y - attribute \src "ls180.v:2822.8-2822.81" + attribute \src "ls180.v:2870.4-2883.7" + switch $and$ls180.v:2870$28_Y + attribute \src "ls180.v:2870.8-2870.81" case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2823$29_Y + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2871$29_Y assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2825$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2826$31_Y - attribute \src "ls180.v:2827.5-2834.8" - switch $or$ls180.v:2827$32_Y - attribute \src "ls180.v:2827.9-2827.97" + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2873$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2874$31_Y + attribute \src "ls180.v:2875.5-2882.8" + switch $or$ls180.v:2875$32_Y + attribute \src "ls180.v:2875.9-2875.97" case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2828$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2876$33_Y assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2830.6-2833.9" - switch $eq$ls180.v:2830$34_Y - attribute \src "ls180.v:2830.10-2830.55" + attribute \src "ls180.v:2878.6-2881.9" + switch $eq$ls180.v:2878$34_Y + attribute \src "ls180.v:2878.10-2878.55" case 1'1 assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 @@ -262996,9 +269051,9 @@ module \ls180 case assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2840.4-2842.7" - switch $and$ls180.v:2840$35_Y - attribute \src "ls180.v:2840.8-2840.81" + attribute \src "ls180.v:2888.4-2890.7" + switch $and$ls180.v:2888$35_Y + attribute \src "ls180.v:2888.8-2888.81" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case @@ -263016,43 +269071,11 @@ module \ls180 update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:280.12-280.47" - process $proc$ls180.v:280$2852 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:281.5-281.42" - process $proc$ls180.v:281$2853 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:282.11-282.50" - process $proc$ls180.v:282$2854 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:283.5-283.42" - process $proc$ls180.v:283$2855 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:2847.1-2857.4" - process $proc$ls180.v:2847$37 + attribute \src "ls180.v:2895.1-2905.4" + process $proc$ls180.v:2895$37 assign { } { } assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2849.2-2856.9" + attribute \src "ls180.v:2897.2-2904.9" switch \main_libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -263065,8 +269088,8 @@ module \ls180 sync always update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] end - attribute \src "ls180.v:2859.1-2905.4" - process $proc$ls180.v:2859$38 + attribute \src "ls180.v:2907.1-2953.4" + process $proc$ls180.v:2907$38 assign { } { } assign { } { } assign { } { } @@ -263077,23 +269100,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 assign { } { } + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2871.2-2904.9" + attribute \src "ls180.v:2919.2-2952.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2874.4-2881.11" + attribute \src "ls180.v:2922.4-2929.11" switch \main_libresocsim_converter2_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -263103,23 +269126,23 @@ module \ls180 assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] case end - attribute \src "ls180.v:2882.4-2895.7" - switch $and$ls180.v:2882$39_Y - attribute \src "ls180.v:2882.8-2882.87" + attribute \src "ls180.v:2930.4-2943.7" + switch $and$ls180.v:2930$39_Y + attribute \src "ls180.v:2930.8-2930.87" case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2883$40_Y + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2931$40_Y assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2885$41_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2886$42_Y - attribute \src "ls180.v:2887.5-2894.8" - switch $or$ls180.v:2887$43_Y - attribute \src "ls180.v:2887.9-2887.97" + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2933$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2934$42_Y + attribute \src "ls180.v:2935.5-2942.8" + switch $or$ls180.v:2935$43_Y + attribute \src "ls180.v:2935.9-2935.97" case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2888$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2936$44_Y assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2890.6-2893.9" - switch $eq$ls180.v:2890$45_Y - attribute \src "ls180.v:2890.10-2890.55" + attribute \src "ls180.v:2938.6-2941.9" + switch $eq$ls180.v:2938$45_Y + attribute \src "ls180.v:2938.10-2938.55" case 1'1 assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 @@ -263133,9 +269156,9 @@ module \ls180 case assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2900.4-2902.7" - switch $and$ls180.v:2900$46_Y - attribute \src "ls180.v:2900.8-2900.87" + attribute \src "ls180.v:2948.4-2950.7" + switch $and$ls180.v:2948$46_Y + attribute \src "ls180.v:2948.8-2948.87" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case @@ -263153,65 +269176,65 @@ module \ls180 update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:290.11-290.36" - process $proc$ls180.v:290$2856 + attribute \src "ls180.v:2956.1-2962.4" + process $proc$ls180.v:2956$47 assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2958$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2959$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2960$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2961$59_Y sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] + update \main_libresocsim_we $0\main_libresocsim_we[3:0] end - attribute \src "ls180.v:2908.1-2914.4" - process $proc$ls180.v:2908$47 + attribute \src "ls180.v:2968.1-2973.4" + process $proc$ls180.v:2968$61 assign { } { } - assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2910$50_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2911$53_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2912$56_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2913$59_Y + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2970.2-2972.5" + switch $and$ls180.v:2970$62_Y + attribute \src "ls180.v:2970.6-2970.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:291.5-291.25" - process $proc$ls180.v:291$2857 + attribute \src "ls180.v:298.12-298.46" + process $proc$ls180.v:298$2856 assign { } { } - assign $1\main_sdram_re[0:0] 1'0 + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_re $1\main_sdram_re[0:0] + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:292.11-292.44" - process $proc$ls180.v:292$2858 + attribute \src "ls180.v:299.5-299.44" + process $proc$ls180.v:299$2857 assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2920.1-2925.4" - process $proc$ls180.v:2920$61 + attribute \src "ls180.v:300.12-300.48" + process $proc$ls180.v:300$2858 assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2922.2-2924.5" - switch $and$ls180.v:2922$62_Y - attribute \src "ls180.v:2922.6-2922.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end - attribute \src "ls180.v:293.5-293.33" - process $proc$ls180.v:293$2859 + attribute \src "ls180.v:301.11-301.43" + process $proc$ls180.v:301$2859 assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 + assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:2964.1-3018.4" - process $proc$ls180.v:2964$64 + attribute \src "ls180.v:3012.1-3066.4" + process $proc$ls180.v:3012$64 assign { } { } assign { } { } assign { } { } @@ -263230,6 +269253,13 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 assign $0\main_sdram_master_p0_bank[1:0] 2'00 assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 @@ -263238,19 +269268,12 @@ module \ls180 assign $0\main_sdram_master_p0_cke[0:0] 1'0 assign $0\main_sdram_master_p0_odt[0:0] 1'0 assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - attribute \src "ls180.v:2983.2-3017.5" + attribute \src "ls180.v:3031.2-3065.5" switch \main_sdram_sel - attribute \src "ls180.v:2983.6-2983.20" + attribute \src "ls180.v:3031.6-3031.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -263268,7 +269291,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3000.6-3000.10" + attribute \src "ls180.v:3048.6-3048.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -263307,73 +269330,73 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:297.5-297.38" - process $proc$ls180.v:297$2860 + attribute \src "ls180.v:302.5-302.38" + process $proc$ls180.v:302$2860 assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:298.12-298.46" - process $proc$ls180.v:298$2861 + attribute \src "ls180.v:303.5-303.37" + process $proc$ls180.v:303$2861 assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:299.5-299.33" - process $proc$ls180.v:299$2862 + attribute \src "ls180.v:304.5-304.38" + process $proc$ls180.v:304$2862 assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:300.11-300.45" - process $proc$ls180.v:300$2863 + attribute \src "ls180.v:305.5-305.37" + process $proc$ls180.v:305$2863 assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:301.5-301.34" - process $proc$ls180.v:301$2864 + attribute \src "ls180.v:306.5-306.36" + process $proc$ls180.v:306$2864 assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 + assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:302.12-302.45" - process $proc$ls180.v:302$2865 + attribute \src "ls180.v:307.5-307.36" + process $proc$ls180.v:307$2865 assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:3022.1-3038.4" - process $proc$ls180.v:3022$65 + attribute \src "ls180.v:3070.1-3086.4" + process $proc$ls180.v:3070$65 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3027.2-3037.5" + attribute \src "ls180.v:3075.2-3085.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3027.6-3027.33" + attribute \src "ls180.v:3075.6-3075.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3028$66_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3029$67_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3030$68_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3031$69_Y - attribute \src "ls180.v:3032.6-3032.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3076$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3077$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3078$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3079$69_Y + attribute \src "ls180.v:3080.6-3080.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -263386,41 +269409,65 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:303.5-303.32" - process $proc$ls180.v:303$2866 + attribute \src "ls180.v:308.5-308.40" + process $proc$ls180.v:308$2866 assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:304.12-304.37" - process $proc$ls180.v:304$2867 + attribute \src "ls180.v:309.5-309.38" + process $proc$ls180.v:309$2867 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:3081.1-3111.4" - process $proc$ls180.v:3081$78 + attribute \src "ls180.v:310.12-310.47" + process $proc$ls180.v:310$2868 assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:311.5-311.42" + process $proc$ls180.v:311$2869 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:312.11-312.50" + process $proc$ls180.v:312$2870 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:3129.1-3159.4" + process $proc$ls180.v:3129$78 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign { } { } assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3087.2-3110.9" + attribute \src "ls180.v:3135.2-3158.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3090.4-3093.7" + attribute \src "ls180.v:3138.4-3141.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3090.8-3090.28" + attribute \src "ls180.v:3138.8-3138.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -263429,9 +269476,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3097.4-3101.7" + attribute \src "ls180.v:3145.4-3149.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3097.8-3097.34" + attribute \src "ls180.v:3145.8-3145.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -263440,13 +269487,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3104.4-3108.7" + attribute \src "ls180.v:3152.4-3156.7" switch 1'1 - attribute \src "ls180.v:3104.8-3104.12" + attribute \src "ls180.v:3152.8-3152.12" case 1'1 - attribute \src "ls180.v:3105.5-3107.8" + attribute \src "ls180.v:3153.5-3155.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3105.9-3105.33" + attribute \src "ls180.v:3153.9-3153.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -263460,35 +269507,43 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:3126.1-3133.4" - process $proc$ls180.v:3126$82 + attribute \src "ls180.v:313.5-313.42" + process $proc$ls180.v:313$2871 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3174.1-3181.4" + process $proc$ls180.v:3174$82 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3128.2-3132.5" + attribute \src "ls180.v:3176.2-3180.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3128.6-3128.48" + attribute \src "ls180.v:3176.6-3176.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3130.6-3130.10" + attribute \src "ls180.v:3178.6-3178.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3131$84_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3179$84_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:3137.1-3144.4" - process $proc$ls180.v:3137$91 + attribute \src "ls180.v:3185.1-3192.4" + process $proc$ls180.v:3185$91 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3139.2-3143.5" - switch $and$ls180.v:3139$92_Y - attribute \src "ls180.v:3139.6-3139.115" + attribute \src "ls180.v:3187.2-3191.5" + switch $and$ls180.v:3187$92_Y + attribute \src "ls180.v:3187.6-3187.115" case 1'1 - attribute \src "ls180.v:3140.3-3142.6" - switch $ne$ls180.v:3140$93_Y - attribute \src "ls180.v:3140.7-3140.143" + attribute \src "ls180.v:3188.3-3190.6" + switch $ne$ls180.v:3188$93_Y + attribute \src "ls180.v:3188.7-3188.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3141$94_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3189$94_Y case end case @@ -263496,24 +269551,48 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:3159.1-3166.4" - process $proc$ls180.v:3159$95 + attribute \src "ls180.v:320.11-320.36" + process $proc$ls180.v:320$2872 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:3207.1-3214.4" + process $proc$ls180.v:3207$95 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3161.2-3165.5" + attribute \src "ls180.v:3209.2-3213.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3161.6-3161.58" + attribute \src "ls180.v:3209.6-3209.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3162$96_Y - attribute \src "ls180.v:3163.6-3163.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3210$96_Y + attribute \src "ls180.v:3211.6-3211.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3175.1-3268.4" - process $proc$ls180.v:3175$104 + attribute \src "ls180.v:321.5-321.25" + process $proc$ls180.v:321$2873 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:322.11-322.44" + process $proc$ls180.v:322$2874 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:3223.1-3316.4" + process $proc$ls180.v:3223$104 assign { } { } assign { } { } assign { } { } @@ -263529,6 +269608,8 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 @@ -263540,25 +269621,23 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3191.2-3267.9" + attribute \src "ls180.v:3239.2-3315.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3193.4-3201.7" - switch $and$ls180.v:3193$105_Y - attribute \src "ls180.v:3193.8-3193.87" + attribute \src "ls180.v:3241.4-3249.7" + switch $and$ls180.v:3241$105_Y + attribute \src "ls180.v:3241.8-3241.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3195.5-3197.8" + attribute \src "ls180.v:3243.5-3245.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3195.9-3195.42" + attribute \src "ls180.v:3243.9-3243.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -263568,27 +269647,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3205.4-3207.7" - switch $and$ls180.v:3205$106_Y - attribute \src "ls180.v:3205.8-3205.87" + attribute \src "ls180.v:3253.4-3255.7" + switch $and$ls180.v:3253$106_Y + attribute \src "ls180.v:3253.8-3253.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3211.4-3220.7" + attribute \src "ls180.v:3259.4-3268.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3211.8-3211.44" + attribute \src "ls180.v:3259.8-3259.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3216.5-3218.8" + attribute \src "ls180.v:3264.5-3266.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3216.9-3216.42" + attribute \src "ls180.v:3264.9-3264.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -263599,16 +269678,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3223.4-3225.7" + attribute \src "ls180.v:3271.4-3273.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3223.8-3223.45" + attribute \src "ls180.v:3271.8-3271.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3228.4-3230.7" - switch $not$ls180.v:3228$107_Y - attribute \src "ls180.v:3228.8-3228.46" + attribute \src "ls180.v:3276.4-3278.7" + switch $not$ls180.v:3276$107_Y + attribute \src "ls180.v:3276.8-3276.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -263621,51 +269700,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3239.4-3265.7" + attribute \src "ls180.v:3287.4-3313.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3239.8-3239.43" + attribute \src "ls180.v:3287.8-3287.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3241.8-3241.12" + attribute \src "ls180.v:3289.8-3289.12" case - attribute \src "ls180.v:3242.5-3264.8" + attribute \src "ls180.v:3290.5-3312.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3242.9-3242.56" + attribute \src "ls180.v:3290.9-3290.56" case 1'1 - attribute \src "ls180.v:3243.6-3263.9" + attribute \src "ls180.v:3291.6-3311.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3243.10-3243.44" + attribute \src "ls180.v:3291.10-3291.44" case 1'1 - attribute \src "ls180.v:3244.7-3260.10" + attribute \src "ls180.v:3292.7-3308.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3244.11-3244.42" + attribute \src "ls180.v:3292.11-3292.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3246.8-3253.11" + attribute \src "ls180.v:3294.8-3301.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3246.12-3246.64" + attribute \src "ls180.v:3294.12-3294.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3250.12-3250.16" + attribute \src "ls180.v:3298.12-3298.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3255.8-3257.11" - switch $and$ls180.v:3255$108_Y - attribute \src "ls180.v:3255.12-3255.88" + attribute \src "ls180.v:3303.8-3305.11" + switch $and$ls180.v:3303$108_Y + attribute \src "ls180.v:3303.12-3303.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3258.11-3258.15" + attribute \src "ls180.v:3306.11-3306.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3261.10-3261.14" + attribute \src "ls180.v:3309.10-3309.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -263689,35 +269768,107 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:3283.1-3290.4" - process $proc$ls180.v:3283$112 + attribute \src "ls180.v:323.5-323.33" + process $proc$ls180.v:323$2875 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:327.5-327.38" + process $proc$ls180.v:327$2876 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:328.12-328.46" + process $proc$ls180.v:328$2877 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:329.5-329.33" + process $proc$ls180.v:329$2878 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:330.11-330.45" + process $proc$ls180.v:330$2879 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:331.5-331.34" + process $proc$ls180.v:331$2880 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:332.12-332.45" + process $proc$ls180.v:332$2881 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:333.5-333.32" + process $proc$ls180.v:333$2882 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:3331.1-3338.4" + process $proc$ls180.v:3331$112 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3285.2-3289.5" + attribute \src "ls180.v:3333.2-3337.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3285.6-3285.48" + attribute \src "ls180.v:3333.6-3333.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3287.6-3287.10" + attribute \src "ls180.v:3335.6-3335.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3288$114_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3336$114_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:3294.1-3301.4" - process $proc$ls180.v:3294$121 + attribute \src "ls180.v:334.12-334.37" + process $proc$ls180.v:334$2883 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3342.1-3349.4" + process $proc$ls180.v:3342$121 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3296.2-3300.5" - switch $and$ls180.v:3296$122_Y - attribute \src "ls180.v:3296.6-3296.115" + attribute \src "ls180.v:3344.2-3348.5" + switch $and$ls180.v:3344$122_Y + attribute \src "ls180.v:3344.6-3344.115" case 1'1 - attribute \src "ls180.v:3297.3-3299.6" - switch $ne$ls180.v:3297$123_Y - attribute \src "ls180.v:3297.7-3297.143" + attribute \src "ls180.v:3345.3-3347.6" + switch $ne$ls180.v:3345$123_Y + attribute \src "ls180.v:3345.7-3345.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3298$124_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3346$124_Y case end case @@ -263725,24 +269876,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:3316.1-3323.4" - process $proc$ls180.v:3316$125 + attribute \src "ls180.v:3364.1-3371.4" + process $proc$ls180.v:3364$125 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3318.2-3322.5" + attribute \src "ls180.v:3366.2-3370.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3318.6-3318.58" + attribute \src "ls180.v:3366.6-3366.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3319$126_Y - attribute \src "ls180.v:3320.6-3320.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3367$126_Y + attribute \src "ls180.v:3368.6-3368.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3332.1-3425.4" - process $proc$ls180.v:3332$134 + attribute \src "ls180.v:3380.1-3473.4" + process $proc$ls180.v:3380$134 assign { } { } assign { } { } assign { } { } @@ -263757,37 +269908,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign { } { } assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3348.2-3424.9" + attribute \src "ls180.v:3396.2-3472.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3350.4-3358.7" - switch $and$ls180.v:3350$135_Y - attribute \src "ls180.v:3350.8-3350.87" + attribute \src "ls180.v:3398.4-3406.7" + switch $and$ls180.v:3398$135_Y + attribute \src "ls180.v:3398.8-3398.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3352.5-3354.8" + attribute \src "ls180.v:3400.5-3402.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3352.9-3352.42" + attribute \src "ls180.v:3400.9-3400.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -263797,27 +269948,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3362.4-3364.7" - switch $and$ls180.v:3362$136_Y - attribute \src "ls180.v:3362.8-3362.87" + attribute \src "ls180.v:3410.4-3412.7" + switch $and$ls180.v:3410$136_Y + attribute \src "ls180.v:3410.8-3410.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3368.4-3377.7" + attribute \src "ls180.v:3416.4-3425.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3368.8-3368.44" + attribute \src "ls180.v:3416.8-3416.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3373.5-3375.8" + attribute \src "ls180.v:3421.5-3423.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3373.9-3373.42" + attribute \src "ls180.v:3421.9-3421.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -263828,16 +269979,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3380.4-3382.7" + attribute \src "ls180.v:3428.4-3430.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3380.8-3380.45" + attribute \src "ls180.v:3428.8-3428.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3385.4-3387.7" - switch $not$ls180.v:3385$137_Y - attribute \src "ls180.v:3385.8-3385.46" + attribute \src "ls180.v:3433.4-3435.7" + switch $not$ls180.v:3433$137_Y + attribute \src "ls180.v:3433.8-3433.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -263850,51 +270001,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3396.4-3422.7" + attribute \src "ls180.v:3444.4-3470.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3396.8-3396.43" + attribute \src "ls180.v:3444.8-3444.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3398.8-3398.12" + attribute \src "ls180.v:3446.8-3446.12" case - attribute \src "ls180.v:3399.5-3421.8" + attribute \src "ls180.v:3447.5-3469.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3399.9-3399.56" + attribute \src "ls180.v:3447.9-3447.56" case 1'1 - attribute \src "ls180.v:3400.6-3420.9" + attribute \src "ls180.v:3448.6-3468.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3400.10-3400.44" + attribute \src "ls180.v:3448.10-3448.44" case 1'1 - attribute \src "ls180.v:3401.7-3417.10" + attribute \src "ls180.v:3449.7-3465.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3401.11-3401.42" + attribute \src "ls180.v:3449.11-3449.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3403.8-3410.11" + attribute \src "ls180.v:3451.8-3458.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3403.12-3403.64" + attribute \src "ls180.v:3451.12-3451.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3407.12-3407.16" + attribute \src "ls180.v:3455.12-3455.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3412.8-3414.11" - switch $and$ls180.v:3412$138_Y - attribute \src "ls180.v:3412.12-3412.88" + attribute \src "ls180.v:3460.8-3462.11" + switch $and$ls180.v:3460$138_Y + attribute \src "ls180.v:3460.12-3460.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3415.11-3415.15" + attribute \src "ls180.v:3463.11-3463.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3418.10-3418.14" + attribute \src "ls180.v:3466.10-3466.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -263918,99 +270069,35 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:334.12-334.46" - process $proc$ls180.v:334$2868 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:335.11-335.47" - process $proc$ls180.v:335$2869 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:337.12-337.45" - process $proc$ls180.v:337$2870 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:338.11-338.40" - process $proc$ls180.v:338$2871 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:339.5-339.35" - process $proc$ls180.v:339$2872 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:340.5-340.34" - process $proc$ls180.v:340$2873 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:341.5-341.35" - process $proc$ls180.v:341$2874 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:342.5-342.34" - process $proc$ls180.v:342$2875 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:3440.1-3447.4" - process $proc$ls180.v:3440$142 + attribute \src "ls180.v:3488.1-3495.4" + process $proc$ls180.v:3488$142 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3442.2-3446.5" + attribute \src "ls180.v:3490.2-3494.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3442.6-3442.48" + attribute \src "ls180.v:3490.6-3490.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3444.6-3444.10" + attribute \src "ls180.v:3492.6-3492.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3445$144_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3493$144_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3451.1-3458.4" - process $proc$ls180.v:3451$151 + attribute \src "ls180.v:3499.1-3506.4" + process $proc$ls180.v:3499$151 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3453.2-3457.5" - switch $and$ls180.v:3453$152_Y - attribute \src "ls180.v:3453.6-3453.115" + attribute \src "ls180.v:3501.2-3505.5" + switch $and$ls180.v:3501$152_Y + attribute \src "ls180.v:3501.6-3501.115" case 1'1 - attribute \src "ls180.v:3454.3-3456.6" - switch $ne$ls180.v:3454$153_Y - attribute \src "ls180.v:3454.7-3454.143" + attribute \src "ls180.v:3502.3-3504.6" + switch $ne$ls180.v:3502$153_Y + attribute \src "ls180.v:3502.7-3502.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3455$154_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3503$154_Y case end case @@ -264018,40 +270105,24 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:346.5-346.35" - process $proc$ls180.v:346$2876 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3473.1-3480.4" - process $proc$ls180.v:3473$155 + attribute \src "ls180.v:3521.1-3528.4" + process $proc$ls180.v:3521$155 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3475.2-3479.5" + attribute \src "ls180.v:3523.2-3527.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3475.6-3475.58" + attribute \src "ls180.v:3523.6-3523.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3476$156_Y - attribute \src "ls180.v:3477.6-3477.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3524$156_Y + attribute \src "ls180.v:3525.6-3525.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:348.5-348.39" - process $proc$ls180.v:348$2877 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:3489.1-3582.4" - process $proc$ls180.v:3489$164 + attribute \src "ls180.v:3537.1-3630.4" + process $proc$ls180.v:3537$164 assign { } { } assign { } { } assign { } { } @@ -264066,37 +270137,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3505.2-3581.9" + attribute \src "ls180.v:3553.2-3629.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3507.4-3515.7" - switch $and$ls180.v:3507$165_Y - attribute \src "ls180.v:3507.8-3507.87" + attribute \src "ls180.v:3555.4-3563.7" + switch $and$ls180.v:3555$165_Y + attribute \src "ls180.v:3555.8-3555.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3509.5-3511.8" + attribute \src "ls180.v:3557.5-3559.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3509.9-3509.42" + attribute \src "ls180.v:3557.9-3557.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -264106,27 +270177,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3519.4-3521.7" - switch $and$ls180.v:3519$166_Y - attribute \src "ls180.v:3519.8-3519.87" + attribute \src "ls180.v:3567.4-3569.7" + switch $and$ls180.v:3567$166_Y + attribute \src "ls180.v:3567.8-3567.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3525.4-3534.7" + attribute \src "ls180.v:3573.4-3582.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3525.8-3525.44" + attribute \src "ls180.v:3573.8-3573.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3530.5-3532.8" + attribute \src "ls180.v:3578.5-3580.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3530.9-3530.42" + attribute \src "ls180.v:3578.9-3578.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -264137,16 +270208,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3537.4-3539.7" + attribute \src "ls180.v:3585.4-3587.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3537.8-3537.45" + attribute \src "ls180.v:3585.8-3585.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3542.4-3544.7" - switch $not$ls180.v:3542$167_Y - attribute \src "ls180.v:3542.8-3542.46" + attribute \src "ls180.v:3590.4-3592.7" + switch $not$ls180.v:3590$167_Y + attribute \src "ls180.v:3590.8-3590.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -264159,51 +270230,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3553.4-3579.7" + attribute \src "ls180.v:3601.4-3627.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3553.8-3553.43" + attribute \src "ls180.v:3601.8-3601.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3555.8-3555.12" + attribute \src "ls180.v:3603.8-3603.12" case - attribute \src "ls180.v:3556.5-3578.8" + attribute \src "ls180.v:3604.5-3626.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3556.9-3556.56" + attribute \src "ls180.v:3604.9-3604.56" case 1'1 - attribute \src "ls180.v:3557.6-3577.9" + attribute \src "ls180.v:3605.6-3625.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3557.10-3557.44" + attribute \src "ls180.v:3605.10-3605.44" case 1'1 - attribute \src "ls180.v:3558.7-3574.10" + attribute \src "ls180.v:3606.7-3622.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3558.11-3558.42" + attribute \src "ls180.v:3606.11-3606.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3560.8-3567.11" + attribute \src "ls180.v:3608.8-3615.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3560.12-3560.64" + attribute \src "ls180.v:3608.12-3608.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3564.12-3564.16" + attribute \src "ls180.v:3612.12-3612.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3569.8-3571.11" - switch $and$ls180.v:3569$168_Y - attribute \src "ls180.v:3569.12-3569.88" + attribute \src "ls180.v:3617.8-3619.11" + switch $and$ls180.v:3617$168_Y + attribute \src "ls180.v:3617.12-3617.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3572.11-3572.15" + attribute \src "ls180.v:3620.11-3620.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3575.10-3575.14" + attribute \src "ls180.v:3623.10-3623.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -264227,107 +270298,51 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:350.5-350.39" - process $proc$ls180.v:350$2878 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:353.5-353.32" - process $proc$ls180.v:353$2879 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:354.5-354.32" - process $proc$ls180.v:354$2880 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:355.5-355.31" - process $proc$ls180.v:355$2881 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:356.12-356.44" - process $proc$ls180.v:356$2882 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:357.11-357.43" - process $proc$ls180.v:357$2883 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:358.5-358.38" - process $proc$ls180.v:358$2884 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:359.5-359.38" - process $proc$ls180.v:359$2885 + attribute \src "ls180.v:364.12-364.46" + process $proc$ls180.v:364$2884 assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "ls180.v:3597.1-3604.4" - process $proc$ls180.v:3597$172 + attribute \src "ls180.v:3645.1-3652.4" + process $proc$ls180.v:3645$172 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3599.2-3603.5" + attribute \src "ls180.v:3647.2-3651.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3599.6-3599.48" + attribute \src "ls180.v:3647.6-3647.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3601.6-3601.10" + attribute \src "ls180.v:3649.6-3649.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3602$174_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3650$174_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:360.5-360.37" - process $proc$ls180.v:360$2886 + attribute \src "ls180.v:365.11-365.47" + process $proc$ls180.v:365$2885 assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:3608.1-3615.4" - process $proc$ls180.v:3608$181 + attribute \src "ls180.v:3656.1-3663.4" + process $proc$ls180.v:3656$181 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3610.2-3614.5" - switch $and$ls180.v:3610$182_Y - attribute \src "ls180.v:3610.6-3610.115" + attribute \src "ls180.v:3658.2-3662.5" + switch $and$ls180.v:3658$182_Y + attribute \src "ls180.v:3658.6-3658.115" case 1'1 - attribute \src "ls180.v:3611.3-3613.6" - switch $ne$ls180.v:3611$183_Y - attribute \src "ls180.v:3611.7-3611.143" + attribute \src "ls180.v:3659.3-3661.6" + switch $ne$ls180.v:3659$183_Y + attribute \src "ls180.v:3659.7-3659.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3612$184_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3660$184_Y case end case @@ -264335,40 +270350,48 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:361.5-361.42" - process $proc$ls180.v:361$2887 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:362.5-362.43" - process $proc$ls180.v:362$2888 + attribute \src "ls180.v:367.12-367.45" + process $proc$ls180.v:367$2886 assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:3630.1-3637.4" - process $proc$ls180.v:3630$185 + attribute \src "ls180.v:3678.1-3685.4" + process $proc$ls180.v:3678$185 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3632.2-3636.5" + attribute \src "ls180.v:3680.2-3684.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3632.6-3632.58" + attribute \src "ls180.v:3680.6-3680.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3633$186_Y - attribute \src "ls180.v:3634.6-3634.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3681$186_Y + attribute \src "ls180.v:3682.6-3682.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3646.1-3739.4" - process $proc$ls180.v:3646$194 + attribute \src "ls180.v:368.11-368.40" + process $proc$ls180.v:368$2887 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:369.5-369.35" + process $proc$ls180.v:369$2888 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3694.1-3787.4" + process $proc$ls180.v:3694$194 assign { } { } assign { } { } assign { } { } @@ -264383,6 +270406,9 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 @@ -264390,30 +270416,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3662.2-3738.9" + attribute \src "ls180.v:3710.2-3786.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3664.4-3672.7" - switch $and$ls180.v:3664$195_Y - attribute \src "ls180.v:3664.8-3664.87" + attribute \src "ls180.v:3712.4-3720.7" + switch $and$ls180.v:3712$195_Y + attribute \src "ls180.v:3712.8-3712.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3666.5-3668.8" + attribute \src "ls180.v:3714.5-3716.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3666.9-3666.42" + attribute \src "ls180.v:3714.9-3714.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -264423,27 +270446,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3676.4-3678.7" - switch $and$ls180.v:3676$196_Y - attribute \src "ls180.v:3676.8-3676.87" + attribute \src "ls180.v:3724.4-3726.7" + switch $and$ls180.v:3724$196_Y + attribute \src "ls180.v:3724.8-3724.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3682.4-3691.7" + attribute \src "ls180.v:3730.4-3739.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3682.8-3682.44" + attribute \src "ls180.v:3730.8-3730.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3687.5-3689.8" + attribute \src "ls180.v:3735.5-3737.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3687.9-3687.42" + attribute \src "ls180.v:3735.9-3735.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -264454,16 +270477,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3694.4-3696.7" + attribute \src "ls180.v:3742.4-3744.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3694.8-3694.45" + attribute \src "ls180.v:3742.8-3742.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3699.4-3701.7" - switch $not$ls180.v:3699$197_Y - attribute \src "ls180.v:3699.8-3699.46" + attribute \src "ls180.v:3747.4-3749.7" + switch $not$ls180.v:3747$197_Y + attribute \src "ls180.v:3747.8-3747.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -264476,51 +270499,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3710.4-3736.7" + attribute \src "ls180.v:3758.4-3784.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3710.8-3710.43" + attribute \src "ls180.v:3758.8-3758.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3712.8-3712.12" + attribute \src "ls180.v:3760.8-3760.12" case - attribute \src "ls180.v:3713.5-3735.8" + attribute \src "ls180.v:3761.5-3783.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3713.9-3713.56" + attribute \src "ls180.v:3761.9-3761.56" case 1'1 - attribute \src "ls180.v:3714.6-3734.9" + attribute \src "ls180.v:3762.6-3782.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3714.10-3714.44" + attribute \src "ls180.v:3762.10-3762.44" case 1'1 - attribute \src "ls180.v:3715.7-3731.10" + attribute \src "ls180.v:3763.7-3779.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3715.11-3715.42" + attribute \src "ls180.v:3763.11-3763.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3717.8-3724.11" + attribute \src "ls180.v:3765.8-3772.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3717.12-3717.64" + attribute \src "ls180.v:3765.12-3765.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3721.12-3721.16" + attribute \src "ls180.v:3769.12-3769.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3726.8-3728.11" - switch $and$ls180.v:3726$198_Y - attribute \src "ls180.v:3726.12-3726.88" + attribute \src "ls180.v:3774.8-3776.11" + switch $and$ls180.v:3774$198_Y + attribute \src "ls180.v:3774.12-3774.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3729.11-3729.15" + attribute \src "ls180.v:3777.11-3777.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3732.10-3732.14" + attribute \src "ls180.v:3780.10-3780.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -264544,80 +270567,72 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:368.11-368.44" - process $proc$ls180.v:368$2889 + attribute \src "ls180.v:370.5-370.34" + process $proc$ls180.v:370$2889 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:370.5-370.38" - process $proc$ls180.v:370$2890 + attribute \src "ls180.v:371.5-371.35" + process $proc$ls180.v:371$2890 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:371.5-371.38" - process $proc$ls180.v:371$2891 + attribute \src "ls180.v:372.5-372.34" + process $proc$ls180.v:372$2891 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:372.5-372.39" - process $proc$ls180.v:372$2892 + attribute \src "ls180.v:376.5-376.35" + process $proc$ls180.v:376$2892 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:375.5-375.38" - process $proc$ls180.v:375$2893 + attribute \src "ls180.v:378.5-378.39" + process $proc$ls180.v:378$2893 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:3759.1-3765.4" - process $proc$ls180.v:3759$237 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3761$250_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3762$263_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3763$276_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3764$289_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:376.11-376.46" - process $proc$ls180.v:376$2894 + attribute \src "ls180.v:380.5-380.39" + process $proc$ls180.v:380$2894 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:377.5-377.38" - process $proc$ls180.v:377$2895 + attribute \src "ls180.v:3807.1-3813.4" + process $proc$ls180.v:3807$237 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3809$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3810$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3811$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3812$289_Y sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:3773.1-3778.4" - process $proc$ls180.v:3773$290 + attribute \src "ls180.v:3821.1-3826.4" + process $proc$ls180.v:3821$290 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3775.2-3777.5" + attribute \src "ls180.v:3823.2-3825.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3775.6-3775.37" + attribute \src "ls180.v:3823.6-3823.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -264625,13 +270640,13 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3779.1-3784.4" - process $proc$ls180.v:3779$291 + attribute \src "ls180.v:3827.1-3832.4" + process $proc$ls180.v:3827$291 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3781.2-3783.5" + attribute \src "ls180.v:3829.2-3831.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3781.6-3781.37" + attribute \src "ls180.v:3829.6-3829.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -264639,13 +270654,21 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3785.1-3790.4" - process $proc$ls180.v:3785$292 + attribute \src "ls180.v:383.5-383.32" + process $proc$ls180.v:383$2895 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:3833.1-3838.4" + process $proc$ls180.v:3833$292 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3787.2-3789.5" + attribute \src "ls180.v:3835.2-3837.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3787.6-3787.37" + attribute \src "ls180.v:3835.6-3835.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -264653,24 +270676,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:3792.1-3798.4" - process $proc$ls180.v:3792$295 + attribute \src "ls180.v:384.5-384.32" + process $proc$ls180.v:384$2896 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3840.1-3846.4" + process $proc$ls180.v:3840$295 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3794$308_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3795$321_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3796$334_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3797$347_Y + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3842$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3843$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3844$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3845$347_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:3806.1-3811.4" - process $proc$ls180.v:3806$348 + attribute \src "ls180.v:385.5-385.31" + process $proc$ls180.v:385$2897 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:3854.1-3859.4" + process $proc$ls180.v:3854$348 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3808.2-3810.5" + attribute \src "ls180.v:3856.2-3858.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3808.6-3808.37" + attribute \src "ls180.v:3856.6-3856.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -264678,13 +270717,21 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3812.1-3817.4" - process $proc$ls180.v:3812$349 + attribute \src "ls180.v:386.12-386.44" + process $proc$ls180.v:386$2898 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3860.1-3865.4" + process $proc$ls180.v:3860$349 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3814.2-3816.5" + attribute \src "ls180.v:3862.2-3864.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3814.6-3814.37" + attribute \src "ls180.v:3862.6-3862.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -264692,13 +270739,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3818.1-3823.4" - process $proc$ls180.v:3818$350 + attribute \src "ls180.v:3866.1-3871.4" + process $proc$ls180.v:3866$350 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3820.2-3822.5" + attribute \src "ls180.v:3868.2-3870.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3820.6-3820.37" + attribute \src "ls180.v:3868.6-3868.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -264706,20 +270753,28 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:3824.1-3832.4" - process $proc$ls180.v:3824$351 + attribute \src "ls180.v:387.11-387.43" + process $proc$ls180.v:387$2899 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:3872.1-3880.4" + process $proc$ls180.v:3872$351 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3826.2-3828.5" - switch $and$ls180.v:3826$354_Y - attribute \src "ls180.v:3826.6-3826.115" + attribute \src "ls180.v:3874.2-3876.5" + switch $and$ls180.v:3874$354_Y + attribute \src "ls180.v:3874.6-3874.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3829.2-3831.5" - switch $and$ls180.v:3829$357_Y - attribute \src "ls180.v:3829.6-3829.115" + attribute \src "ls180.v:3877.2-3879.5" + switch $and$ls180.v:3877$357_Y + attribute \src "ls180.v:3877.6-3877.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -264727,28 +270782,28 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:383.5-383.51" - process $proc$ls180.v:383$2896 + attribute \src "ls180.v:388.5-388.38" + process $proc$ls180.v:388$2900 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:3833.1-3841.4" - process $proc$ls180.v:3833$358 + attribute \src "ls180.v:3881.1-3889.4" + process $proc$ls180.v:3881$358 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3835.2-3837.5" - switch $and$ls180.v:3835$361_Y - attribute \src "ls180.v:3835.6-3835.115" + attribute \src "ls180.v:3883.2-3885.5" + switch $and$ls180.v:3883$361_Y + attribute \src "ls180.v:3883.6-3883.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3838.2-3840.5" - switch $and$ls180.v:3838$364_Y - attribute \src "ls180.v:3838.6-3838.115" + attribute \src "ls180.v:3886.2-3888.5" + switch $and$ls180.v:3886$364_Y + attribute \src "ls180.v:3886.6-3886.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -264756,28 +270811,28 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:384.5-384.51" - process $proc$ls180.v:384$2897 + attribute \src "ls180.v:389.5-389.38" + process $proc$ls180.v:389$2901 assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:3842.1-3850.4" - process $proc$ls180.v:3842$365 + attribute \src "ls180.v:3890.1-3898.4" + process $proc$ls180.v:3890$365 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3844.2-3846.5" - switch $and$ls180.v:3844$368_Y - attribute \src "ls180.v:3844.6-3844.115" + attribute \src "ls180.v:3892.2-3894.5" + switch $and$ls180.v:3892$368_Y + attribute \src "ls180.v:3892.6-3892.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3847.2-3849.5" - switch $and$ls180.v:3847$371_Y - attribute \src "ls180.v:3847.6-3847.115" + attribute \src "ls180.v:3895.2-3897.5" + switch $and$ls180.v:3895$371_Y + attribute \src "ls180.v:3895.6-3895.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -264785,20 +270840,20 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:3851.1-3859.4" - process $proc$ls180.v:3851$372 + attribute \src "ls180.v:3899.1-3907.4" + process $proc$ls180.v:3899$372 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3853.2-3855.5" - switch $and$ls180.v:3853$375_Y - attribute \src "ls180.v:3853.6-3853.115" + attribute \src "ls180.v:3901.2-3903.5" + switch $and$ls180.v:3901$375_Y + attribute \src "ls180.v:3901.6-3901.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:3856.2-3858.5" - switch $and$ls180.v:3856$378_Y - attribute \src "ls180.v:3856.6-3856.115" + attribute \src "ls180.v:3904.2-3906.5" + switch $and$ls180.v:3904$378_Y + attribute \src "ls180.v:3904.6-3904.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -264806,16 +270861,24 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:386.5-386.47" - process $proc$ls180.v:386$2898 + attribute \src "ls180.v:390.5-390.37" + process $proc$ls180.v:390$2902 assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:391.5-391.42" + process $proc$ls180.v:391$2903 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init end - attribute \src "ls180.v:3864.1-3936.4" - process $proc$ls180.v:3864$381 + attribute \src "ls180.v:3912.1-3984.4" + process $proc$ls180.v:3912$381 assign { } { } assign { } { } assign { } { } @@ -264825,47 +270888,47 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } assign $0\main_sdram_en1[0:0] 1'0 assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign { } { } - assign { } { } assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3876.2-3935.9" + attribute \src "ls180.v:3924.2-3983.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3880.4-3886.7" + attribute \src "ls180.v:3928.4-3934.7" switch 1'1 - attribute \src "ls180.v:3880.8-3880.12" + attribute \src "ls180.v:3928.8-3928.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3881$388_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3929$388_Y case end - attribute \src "ls180.v:3888.4-3892.7" + attribute \src "ls180.v:3936.4-3940.7" switch \main_sdram_read_available - attribute \src "ls180.v:3888.8-3888.33" + attribute \src "ls180.v:3936.8-3936.33" case 1'1 - attribute \src "ls180.v:3889.5-3891.8" - switch $or$ls180.v:3889$390_Y - attribute \src "ls180.v:3889.9-3889.63" + attribute \src "ls180.v:3937.5-3939.8" + switch $or$ls180.v:3937$390_Y + attribute \src "ls180.v:3937.9-3937.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:3893.4-3895.7" + attribute \src "ls180.v:3941.4-3943.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3893.8-3893.32" + attribute \src "ls180.v:3941.8-3941.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -264874,18 +270937,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3900.4-3902.7" + attribute \src "ls180.v:3948.4-3950.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:3900.8-3900.27" + attribute \src "ls180.v:3948.8-3948.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3905.4-3907.7" + attribute \src "ls180.v:3953.4-3955.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3905.8-3905.32" + attribute \src "ls180.v:3953.8-3953.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -264901,29 +270964,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3918.4-3924.7" + attribute \src "ls180.v:3966.4-3972.7" switch 1'1 - attribute \src "ls180.v:3918.8-3918.12" + attribute \src "ls180.v:3966.8-3966.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3919$397_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3967$397_Y case end - attribute \src "ls180.v:3926.4-3930.7" + attribute \src "ls180.v:3974.4-3978.7" switch \main_sdram_write_available - attribute \src "ls180.v:3926.8-3926.34" + attribute \src "ls180.v:3974.8-3974.34" case 1'1 - attribute \src "ls180.v:3927.5-3929.8" - switch $or$ls180.v:3927$399_Y - attribute \src "ls180.v:3927.9-3927.62" + attribute \src "ls180.v:3975.5-3977.8" + switch $or$ls180.v:3975$399_Y + attribute \src "ls180.v:3975.9-3975.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:3931.4-3933.7" + attribute \src "ls180.v:3979.4-3981.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3931.8-3931.32" + attribute \src "ls180.v:3979.8-3979.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -264940,85 +271003,37 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:387.5-387.45" - process $proc$ls180.v:387$2899 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:388.5-388.45" - process $proc$ls180.v:388$2900 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:389.12-389.57" - process $proc$ls180.v:389$2901 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:391.5-391.51" - process $proc$ls180.v:391$2902 + attribute \src "ls180.v:392.5-392.43" + process $proc$ls180.v:392$2904 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:392.5-392.51" - process $proc$ls180.v:392$2903 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:393.5-393.50" - process $proc$ls180.v:393$2904 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:394.5-394.54" - process $proc$ls180.v:394$2905 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:395.5-395.55" - process $proc$ls180.v:395$2906 + attribute \src "ls180.v:398.11-398.44" + process $proc$ls180.v:398$2905 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "ls180.v:396.5-396.56" - process $proc$ls180.v:396$2907 + attribute \src "ls180.v:400.5-400.38" + process $proc$ls180.v:400$2906 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:3960.1-3973.4" - process $proc$ls180.v:3960$528 + attribute \src "ls180.v:4008.1-4021.4" + process $proc$ls180.v:4008$528 assign { } { } assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:3963.2-3972.9" + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + attribute \src "ls180.v:4011.2-4020.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -265033,19 +271048,27 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:397.5-397.50" - process $proc$ls180.v:397$2908 + attribute \src "ls180.v:401.5-401.38" + process $proc$ls180.v:401$2907 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:402.5-402.39" + process $proc$ls180.v:402$2908 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:3980.1-3990.4" - process $proc$ls180.v:3980$530 + attribute \src "ls180.v:4028.1-4038.4" + process $proc$ls180.v:4028$530 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:3982.2-3989.9" + attribute \src "ls180.v:4030.2-4037.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -265058,8 +271081,8 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:3992.1-4038.4" - process $proc$ls180.v:3992$531 + attribute \src "ls180.v:4040.1-4086.4" + process $proc$ls180.v:4040$531 assign { } { } assign { } { } assign { } { } @@ -265070,23 +271093,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter_skip[0:0] 1'0 assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 assign { } { } + assign $0\main_litedram_wb_stb[0:0] 1'0 assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4004.2-4037.9" + attribute \src "ls180.v:4052.2-4085.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4007.4-4014.11" + attribute \src "ls180.v:4055.4-4062.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -265096,23 +271119,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4015.4-4028.7" - switch $and$ls180.v:4015$532_Y - attribute \src "ls180.v:4015.8-4015.47" + attribute \src "ls180.v:4063.4-4076.7" + switch $and$ls180.v:4063$532_Y + attribute \src "ls180.v:4063.8-4063.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4016$533_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4064$533_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4018$534_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4019$535_Y - attribute \src "ls180.v:4020.5-4027.8" - switch $or$ls180.v:4020$536_Y - attribute \src "ls180.v:4020.9-4020.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4066$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4067$535_Y + attribute \src "ls180.v:4068.5-4075.8" + switch $or$ls180.v:4068$536_Y + attribute \src "ls180.v:4068.9-4068.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4021$537_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4069$537_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4023.6-4026.9" - switch $eq$ls180.v:4023$538_Y - attribute \src "ls180.v:4023.10-4023.42" + attribute \src "ls180.v:4071.6-4074.9" + switch $eq$ls180.v:4071$538_Y + attribute \src "ls180.v:4071.10-4071.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -265126,9 +271149,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4033.4-4035.7" - switch $and$ls180.v:4033$539_Y - attribute \src "ls180.v:4033.8-4033.47" + attribute \src "ls180.v:4081.4-4083.7" + switch $and$ls180.v:4081$539_Y + attribute \src "ls180.v:4081.8-4081.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -265146,29 +271169,45 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:400.5-400.67" - process $proc$ls180.v:400$2909 + attribute \src "ls180.v:405.5-405.38" + process $proc$ls180.v:405$2909 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:401.5-401.66" - process $proc$ls180.v:401$2910 + attribute \src "ls180.v:406.11-406.46" + process $proc$ls180.v:406$2910 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:4083.1-4088.4" - process $proc$ls180.v:4083$571 + attribute \src "ls180.v:407.5-407.38" + process $proc$ls180.v:407$2911 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:413.5-413.51" + process $proc$ls180.v:413$2912 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:4131.1-4136.4" + process $proc$ls180.v:4131$571 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4085.2-4087.5" - switch $and$ls180.v:4085$572_Y - attribute \src "ls180.v:4085.6-4085.79" + attribute \src "ls180.v:4133.2-4135.5" + switch $and$ls180.v:4133$572_Y + attribute \src "ls180.v:4133.6-4133.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -265176,8 +271215,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:4089.1-4093.4" - process $proc$ls180.v:4089$573 + attribute \src "ls180.v:4137.1-4141.4" + process $proc$ls180.v:4137$573 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -265185,13 +271224,21 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4094.1-4099.4" - process $proc$ls180.v:4094$574 + attribute \src "ls180.v:414.5-414.51" + process $proc$ls180.v:414$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:4142.1-4147.4" + process $proc$ls180.v:4142$574 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4096.2-4098.5" - switch $and$ls180.v:4096$575_Y - attribute \src "ls180.v:4096.6-4096.79" + attribute \src "ls180.v:4144.2-4146.5" + switch $and$ls180.v:4144$575_Y + attribute \src "ls180.v:4144.6-4144.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -265199,8 +271246,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4100.1-4104.4" - process $proc$ls180.v:4100$576 + attribute \src "ls180.v:4148.1-4152.4" + process $proc$ls180.v:4148$576 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -265208,64 +271255,96 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:4122.1-4129.4" - process $proc$ls180.v:4122$584 + attribute \src "ls180.v:416.5-416.47" + process $proc$ls180.v:416$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:417.5-417.45" + process $proc$ls180.v:417$2915 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:4170.1-4177.4" + process $proc$ls180.v:4170$584 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4124.2-4128.5" + attribute \src "ls180.v:4172.2-4176.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4124.6-4124.31" + attribute \src "ls180.v:4172.6-4172.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4125$585_Y - attribute \src "ls180.v:4126.6-4126.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4173$585_Y + attribute \src "ls180.v:4174.6-4174.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4152.1-4159.4" - process $proc$ls180.v:4152$595 + attribute \src "ls180.v:418.5-418.45" + process $proc$ls180.v:418$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:419.12-419.57" + process $proc$ls180.v:419$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:4200.1-4207.4" + process $proc$ls180.v:4200$595 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4154.2-4158.5" + attribute \src "ls180.v:4202.2-4206.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4154.6-4154.31" + attribute \src "ls180.v:4202.6-4202.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4155$596_Y - attribute \src "ls180.v:4156.6-4156.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4203$596_Y + attribute \src "ls180.v:4204.6-4204.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:416.11-416.68" - process $proc$ls180.v:416$2911 + attribute \src "ls180.v:421.5-421.51" + process $proc$ls180.v:421$2918 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:417.5-417.64" - process $proc$ls180.v:417$2912 + attribute \src "ls180.v:422.5-422.51" + process $proc$ls180.v:422$2919 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "ls180.v:418.11-418.70" - process $proc$ls180.v:418$2913 + attribute \src "ls180.v:423.5-423.50" + process $proc$ls180.v:423$2920 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] end - attribute \src "ls180.v:4182.1-4230.4" - process $proc$ls180.v:4182$606 + attribute \src "ls180.v:4230.1-4278.4" + process $proc$ls180.v:4230$606 assign { } { } assign { } { } assign { } { } @@ -265275,43 +271354,43 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spi_master_miso_latch[0:0] 1'0 - assign $0\main_spi_master_clk_enable[0:0] 1'0 - assign $0\main_spi_master_irq[0:0] 1'0 - assign $0\main_spi_master_cs_enable[0:0] 1'0 + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 assign { } { } - assign $0\main_spi_master_mosi_latch[0:0] 1'0 - assign $0\main_spi_master_done0[0:0] 1'0 - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4193.2-4229.9" + attribute \src "ls180.v:4241.2-4277.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\main_spi_master_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4197.4-4200.7" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:4197.8-4197.32" + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4245.4-4248.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4245.8-4245.33" case 1'1 - assign $0\main_spi_master_cs_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 case end attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\main_spi_master_clk_enable[0:0] 1'1 - assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4205.4-4211.7" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:4205.8-4205.32" + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4253.4-4259.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4253.8-4253.33" case 1'1 - assign $0\main_spi_master_count_spimaster0_next_value[2:0] $add$ls180.v:4206$607_Y - assign $0\main_spi_master_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4208.5-4210.8" - switch $eq$ls180.v:4208$609_Y - attribute \src "ls180.v:4208.9-4208.68" + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4254$607_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4256.5-4258.8" + switch $eq$ls180.v:4256$609_Y + attribute \src "ls180.v:4256.9-4256.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -265320,61 +271399,183 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - assign $0\main_spi_master_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4215.4-4219.7" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:4215.8-4215.32" + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4263.4-4267.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4263.8-4263.33" case 1'1 - assign $0\main_spi_master_miso_latch[0:0] 1'1 - assign $0\main_spi_master_irq[0:0] 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'00 case end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_spi_master_done0[0:0] 1'1 - attribute \src "ls180.v:4223.4-4227.7" - switch \main_spi_master_start0 - attribute \src "ls180.v:4223.8-4223.30" + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4271.4-4275.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4271.8-4271.29" case 1'1 - assign $0\main_spi_master_done0[0:0] 1'0 - assign $0\main_spi_master_mosi_latch[0:0] 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'01 case end end sync always - update \main_spi_master_done0 $0\main_spi_master_done0[0:0] - update \main_spi_master_irq $0\main_spi_master_irq[0:0] - update \main_spi_master_clk_enable $0\main_spi_master_clk_enable[0:0] - update \main_spi_master_cs_enable $0\main_spi_master_cs_enable[0:0] - update \main_spi_master_mosi_latch $0\main_spi_master_mosi_latch[0:0] - update \main_spi_master_miso_latch $0\main_spi_master_miso_latch[0:0] + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spi_master_count_spimaster0_next_value $0\main_spi_master_count_spimaster0_next_value[2:0] - update \main_spi_master_count_spimaster0_next_value_ce $0\main_spi_master_count_spimaster0_next_value_ce[0:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:419.11-419.70" - process $proc$ls180.v:419$2914 + attribute \src "ls180.v:424.5-424.54" + process $proc$ls180.v:424$2921 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:420.11-420.73" - process $proc$ls180.v:420$2915 + attribute \src "ls180.v:425.5-425.55" + process $proc$ls180.v:425$2922 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:426.5-426.56" + process $proc$ls180.v:426$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:427.5-427.50" + process $proc$ls180.v:427$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:4289.1-4337.4" + process $proc$ls180.v:4289$614 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign { } { } + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4300.2-4336.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4304.4-4307.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4304.8-4304.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4312.4-4318.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4312.8-4312.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4313$615_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4315.5-4317.8" + switch $eq$ls180.v:4315$617_Y + attribute \src "ls180.v:4315.9-4315.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4322.4-4326.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4322.8-4322.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4330.4-4334.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4330.8-4330.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:430.5-430.67" + process $proc$ls180.v:430$2925 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:431.5-431.66" + process $proc$ls180.v:431$2926 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init end - attribute \src "ls180.v:4258.1-4286.4" - process $proc$ls180.v:4258$631 + attribute \src "ls180.v:4369.1-4397.4" + process $proc$ls180.v:4369$639 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4260.2-4285.9" + attribute \src "ls180.v:4371.2-4396.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -265404,8 +271605,8 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:4288.1-4321.4" - process $proc$ls180.v:4288$634 + attribute \src "ls180.v:4399.1-4432.4" + process $proc$ls180.v:4399$642 assign { } { } assign { } { } assign { } { } @@ -265414,16 +271615,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4298.2-4320.9" + attribute \src "ls180.v:4409.2-4431.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -265432,15 +271633,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4305.4-4311.7" + attribute \src "ls180.v:4416.4-4422.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4305.8-4305.38" + attribute \src "ls180.v:4416.8-4416.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4306$635_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4417$643_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4308.5-4310.8" - switch $eq$ls180.v:4308$636_Y - attribute \src "ls180.v:4308.9-4308.41" + attribute \src "ls180.v:4419.5-4421.8" + switch $eq$ls180.v:4419$644_Y + attribute \src "ls180.v:4419.9-4419.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -265451,9 +271652,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4316.4-4318.7" + attribute \src "ls180.v:4427.4-4429.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4316.8-4316.37" + attribute \src "ls180.v:4427.8-4427.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -265469,8 +271670,8 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:4322.1-4398.4" - process $proc$ls180.v:4322$637 + attribute \src "ls180.v:4433.1-4509.4" + process $proc$ls180.v:4433$645 assign { } { } assign { } { } assign { } { } @@ -265479,22 +271680,22 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4332.2-4397.9" + attribute \src "ls180.v:4443.2-4508.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4336.4-4361.11" + attribute \src "ls180.v:4447.4-4472.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -265522,22 +271723,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4362.4-4373.7" + attribute \src "ls180.v:4473.4-4484.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4362.8-4362.38" + attribute \src "ls180.v:4473.8-4473.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4363$638_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4474$646_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4365.5-4372.8" - switch $eq$ls180.v:4365$639_Y - attribute \src "ls180.v:4365.9-4365.40" + attribute \src "ls180.v:4476.5-4483.8" + switch $eq$ls180.v:4476$647_Y + attribute \src "ls180.v:4476.9-4476.40" case 1'1 - attribute \src "ls180.v:4366.6-4371.9" + attribute \src "ls180.v:4477.6-4482.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4366.10-4366.35" + attribute \src "ls180.v:4477.10-4477.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4368.10-4368.14" + attribute \src "ls180.v:4479.10-4479.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -265551,15 +271752,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4379.4-4386.7" + attribute \src "ls180.v:4490.4-4497.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4379.8-4379.38" + attribute \src "ls180.v:4490.8-4490.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4380$640_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4491$648_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4382.5-4385.8" - switch $eq$ls180.v:4382$641_Y - attribute \src "ls180.v:4382.9-4382.40" + attribute \src "ls180.v:4493.5-4496.8" + switch $eq$ls180.v:4493$649_Y + attribute \src "ls180.v:4493.9-4493.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -265571,12 +271772,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4391.4-4395.7" - switch $and$ls180.v:4391$642_Y - attribute \src "ls180.v:4391.8-4391.69" + attribute \src "ls180.v:4502.4-4506.7" + switch $and$ls180.v:4502$650_Y + attribute \src "ls180.v:4502.8-4502.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4393.8-4393.12" + attribute \src "ls180.v:4504.8-4504.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -265591,26 +271792,48 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:441.5-441.59" - process $proc$ls180.v:441$2916 + attribute \src "ls180.v:446.11-446.68" + process $proc$ls180.v:446$2927 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:443.5-443.59" - process $proc$ls180.v:443$2917 + attribute \src "ls180.v:447.5-447.64" + process $proc$ls180.v:447$2928 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:448.11-448.70" + process $proc$ls180.v:448$2929 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:4432.1-4525.4" - process $proc$ls180.v:4432$651 + attribute \src "ls180.v:449.11-449.70" + process $proc$ls180.v:449$2930 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:450.11-450.73" + process $proc$ls180.v:450$2931 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4543.1-4636.4" + process $proc$ls180.v:4543$659 assign { } { } assign { } { } assign { } { } @@ -265625,42 +271848,44 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4450.2-4524.9" + attribute \src "ls180.v:4561.2-4635.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4458$652_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4569$660_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4455.4-4457.7" + attribute \src "ls180.v:4566.4-4568.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4455.8-4455.49" + attribute \src "ls180.v:4566.8-4566.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4460.4-4463.7" - switch $eq$ls180.v:4460$653_Y - attribute \src "ls180.v:4460.8-4460.41" + attribute \src "ls180.v:4571.4-4574.7" + switch $eq$ls180.v:4571$661_Y + attribute \src "ls180.v:4571.8-4571.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -265671,30 +271896,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4469$655_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4580$663_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4486$658_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4597$666_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4471.4-4485.7" - switch $and$ls180.v:4471$656_Y - attribute \src "ls180.v:4471.8-4471.69" + attribute \src "ls180.v:4582.4-4596.7" + switch $and$ls180.v:4582$664_Y + attribute \src "ls180.v:4582.8-4582.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4473$657_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4584$665_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4475.5-4484.8" + attribute \src "ls180.v:4586.5-4595.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4475.9-4475.36" + attribute \src "ls180.v:4586.9-4586.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4477.6-4483.9" + attribute \src "ls180.v:4588.6-4594.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4477.10-4477.35" + attribute \src "ls180.v:4588.10-4588.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4481.10-4481.14" + attribute \src "ls180.v:4592.10-4592.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -265702,9 +271927,9 @@ module \ls180 end case end - attribute \src "ls180.v:4488.4-4491.7" - switch $eq$ls180.v:4488$659_Y - attribute \src "ls180.v:4488.8-4488.41" + attribute \src "ls180.v:4599.4-4602.7" + switch $eq$ls180.v:4599$667_Y + attribute \src "ls180.v:4599.8-4599.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -265715,15 +271940,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4497.4-4503.7" + attribute \src "ls180.v:4608.4-4614.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4497.8-4497.38" + attribute \src "ls180.v:4608.8-4608.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4498$660_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4609$668_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4500.5-4502.8" - switch $eq$ls180.v:4500$661_Y - attribute \src "ls180.v:4500.9-4500.40" + attribute \src "ls180.v:4611.5-4613.8" + switch $eq$ls180.v:4611$669_Y + attribute \src "ls180.v:4611.9-4611.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -265735,9 +271960,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4509.4-4511.7" - switch $and$ls180.v:4509$662_Y - attribute \src "ls180.v:4509.8-4509.69" + attribute \src "ls180.v:4620.4-4622.7" + switch $and$ls180.v:4620$670_Y + attribute \src "ls180.v:4620.8-4620.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -265748,9 +271973,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4518.4-4522.7" - switch $and$ls180.v:4518$664_Y - attribute \src "ls180.v:4518.8-4518.94" + attribute \src "ls180.v:4629.4-4633.7" + switch $and$ls180.v:4629$672_Y + attribute \src "ls180.v:4629.8-4629.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -265776,122 +272001,42 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:444.5-444.58" - process $proc$ls180.v:444$2918 + attribute \src "ls180.v:4670.1-4697.4" + process $proc$ls180.v:4670$680 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:445.5-445.64" - process $proc$ls180.v:445$2919 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:446.12-446.74" - process $proc$ls180.v:446$2920 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:447.12-447.47" - process $proc$ls180.v:447$2921 assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:448.5-448.46" - process $proc$ls180.v:448$2922 assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:450.5-450.44" - process $proc$ls180.v:450$2923 assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:451.5-451.45" - process $proc$ls180.v:451$2924 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:452.5-452.54" - process $proc$ls180.v:452$2925 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:454.32-454.76" - process $proc$ls180.v:454$2926 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:455.11-455.55" - process $proc$ls180.v:455$2927 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:4559.1-4586.4" - process $proc$ls180.v:4559$672 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign { } { } assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4567.2-4585.9" + attribute \src "ls180.v:4678.2-4696.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4572.4-4576.7" + attribute \src "ls180.v:4683.4-4687.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4572.8-4572.50" + attribute \src "ls180.v:4683.8-4683.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4573$673_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4574$674_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4684$681_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4685$682_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4579.4-4583.7" + attribute \src "ls180.v:4690.4-4694.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4579.8-4579.30" + attribute \src "ls180.v:4690.8-4690.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -265907,16 +272052,9 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:457.32-457.75" - process $proc$ls180.v:457$2928 + attribute \src "ls180.v:4698.1-4770.4" + process $proc$ls180.v:4698$683 assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:4587.1-4659.4" - process $proc$ls180.v:4587$675 assign { } { } assign { } { } assign { } { } @@ -265925,37 +272063,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 assign { } { } + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4598.2-4658.9" + attribute \src "ls180.v:4709.2-4769.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4603.4-4605.7" + attribute \src "ls180.v:4714.4-4716.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4603.8-4603.39" + attribute \src "ls180.v:4714.8-4714.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4608$676_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4719$684_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4611.4-4618.11" + attribute \src "ls180.v:4722.4-4729.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -265965,24 +272102,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4619.4-4631.7" + attribute \src "ls180.v:4730.4-4742.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4619.8-4619.39" + attribute \src "ls180.v:4730.8-4730.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4620$677_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4731$685_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4622.5-4630.8" - switch $eq$ls180.v:4622$678_Y - attribute \src "ls180.v:4622.9-4622.41" + attribute \src "ls180.v:4733.5-4741.8" + switch $eq$ls180.v:4733$686_Y + attribute \src "ls180.v:4733.9-4733.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4625.6-4629.9" + attribute \src "ls180.v:4736.6-4740.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4625.10-4625.36" + attribute \src "ls180.v:4736.10-4736.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4627.10-4627.14" + attribute \src "ls180.v:4738.10-4738.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -265995,9 +272132,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4637.4-4640.7" + attribute \src "ls180.v:4748.4-4751.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4637.8-4637.39" + attribute \src "ls180.v:4748.8-4748.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -266006,13 +272143,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4644.4-4649.7" + attribute \src "ls180.v:4755.4-4760.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4644.8-4644.39" + attribute \src "ls180.v:4755.8-4755.39" case 1'1 - attribute \src "ls180.v:4645.5-4648.8" + attribute \src "ls180.v:4756.5-4759.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4645.9-4645.51" + attribute \src "ls180.v:4756.9-4756.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -266024,9 +272161,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4654.4-4656.7" - switch $and$ls180.v:4654$679_Y - attribute \src "ls180.v:4654.8-4654.71" + attribute \src "ls180.v:4765.4-4767.7" + switch $and$ls180.v:4765$687_Y + attribute \src "ls180.v:4765.8-4765.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -266043,48 +272180,72 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:459.32-459.76" - process $proc$ls180.v:459$2929 + attribute \src "ls180.v:471.5-471.59" + process $proc$ls180.v:471$2932 assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:465.5-465.51" - process $proc$ls180.v:465$2930 + attribute \src "ls180.v:473.5-473.59" + process $proc$ls180.v:473$2933 assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:466.5-466.51" - process $proc$ls180.v:466$2931 + attribute \src "ls180.v:474.5-474.58" + process $proc$ls180.v:474$2934 assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:468.5-468.47" - process $proc$ls180.v:468$2932 + attribute \src "ls180.v:475.5-475.64" + process $proc$ls180.v:475$2935 assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:469.5-469.45" - process $proc$ls180.v:469$2933 + attribute \src "ls180.v:476.12-476.74" + process $proc$ls180.v:476$2936 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:477.12-477.47" + process $proc$ls180.v:477$2937 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:4693.1-4794.4" - process $proc$ls180.v:4693$687 + attribute \src "ls180.v:478.5-478.46" + process $proc$ls180.v:478$2938 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:480.5-480.44" + process $proc$ls180.v:480$2939 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:4804.1-4905.4" + process $proc$ls180.v:4804$695 assign { } { } assign { } { } assign { } { } @@ -266100,23 +272261,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 assign { } { } assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4710.2-4793.9" + attribute \src "ls180.v:4821.2-4904.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -266125,18 +272286,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4720$689_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4831$697_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4717.4-4719.7" + attribute \src "ls180.v:4828.4-4830.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4717.8-4717.51" + attribute \src "ls180.v:4828.8-4828.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4722.4-4725.7" - switch $eq$ls180.v:4722$690_Y - attribute \src "ls180.v:4722.8-4722.42" + attribute \src "ls180.v:4833.4-4836.7" + switch $eq$ls180.v:4833$698_Y + attribute \src "ls180.v:4833.8-4833.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -266147,48 +272308,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4731$693_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4842$701_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4752$695_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4863$703_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4733.4-4751.7" + attribute \src "ls180.v:4844.4-4862.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4733.8-4733.37" + attribute \src "ls180.v:4844.8-4844.37" case 1'1 - attribute \src "ls180.v:4734.5-4750.8" + attribute \src "ls180.v:4845.5-4861.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4734.9-4734.38" + attribute \src "ls180.v:4845.9-4845.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4736$694_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4847$702_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4738.6-4747.9" + attribute \src "ls180.v:4849.6-4858.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4738.10-4738.38" + attribute \src "ls180.v:4849.10-4849.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4740.7-4746.10" + attribute \src "ls180.v:4851.7-4857.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4740.11-4740.37" + attribute \src "ls180.v:4851.11-4851.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4744.11-4744.15" + attribute \src "ls180.v:4855.11-4855.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:4748.9-4748.13" + attribute \src "ls180.v:4859.9-4859.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4754.4-4757.7" - switch $eq$ls180.v:4754$696_Y - attribute \src "ls180.v:4754.8-4754.42" + attribute \src "ls180.v:4865.4-4868.7" + switch $eq$ls180.v:4865$704_Y + attribute \src "ls180.v:4865.8-4865.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -266197,15 +272358,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4761.4-4767.7" + attribute \src "ls180.v:4872.4-4878.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4761.8-4761.39" + attribute \src "ls180.v:4872.8-4872.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4762$697_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4873$705_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4764.5-4766.8" - switch $eq$ls180.v:4764$698_Y - attribute \src "ls180.v:4764.9-4764.42" + attribute \src "ls180.v:4875.5-4877.8" + switch $eq$ls180.v:4875$706_Y + attribute \src "ls180.v:4875.9-4875.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -266217,9 +272378,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4773.4-4775.7" - switch $and$ls180.v:4773$699_Y - attribute \src "ls180.v:4773.8-4773.71" + attribute \src "ls180.v:4884.4-4886.7" + switch $and$ls180.v:4884$707_Y + attribute \src "ls180.v:4884.8-4884.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -266228,14 +272389,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4780.4-4791.7" - switch $and$ls180.v:4780$700_Y - attribute \src "ls180.v:4780.8-4780.71" + attribute \src "ls180.v:4891.4-4902.7" + switch $and$ls180.v:4891$708_Y + attribute \src "ls180.v:4891.8-4891.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4782.5-4790.8" + attribute \src "ls180.v:4893.5-4901.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4782.9-4782.40" + attribute \src "ls180.v:4893.9-4893.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -266266,184 +272427,184 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:470.5-470.45" - process $proc$ls180.v:470$2934 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:471.12-471.57" - process $proc$ls180.v:471$2935 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:473.5-473.51" - process $proc$ls180.v:473$2936 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:474.5-474.51" - process $proc$ls180.v:474$2937 + attribute \src "ls180.v:481.5-481.45" + process $proc$ls180.v:481$2940 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end - attribute \src "ls180.v:475.5-475.50" - process $proc$ls180.v:475$2938 + attribute \src "ls180.v:482.5-482.54" + process $proc$ls180.v:482$2941 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:476.5-476.54" - process $proc$ls180.v:476$2939 + attribute \src "ls180.v:484.32-484.76" + process $proc$ls180.v:484$2942 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:477.5-477.55" - process $proc$ls180.v:477$2940 + attribute \src "ls180.v:485.11-485.55" + process $proc$ls180.v:485$2943 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:478.5-478.56" - process $proc$ls180.v:478$2941 + attribute \src "ls180.v:487.32-487.75" + process $proc$ls180.v:487$2944 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:479.5-479.50" - process $proc$ls180.v:479$2942 + attribute \src "ls180.v:489.32-489.76" + process $proc$ls180.v:489$2945 assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:482.5-482.67" - process $proc$ls180.v:482$2943 + attribute \src "ls180.v:495.5-495.51" + process $proc$ls180.v:495$2946 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:483.5-483.66" - process $proc$ls180.v:483$2944 + attribute \src "ls180.v:496.5-496.51" + process $proc$ls180.v:496$2947 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:4852.1-4859.4" - process $proc$ls180.v:4852$822 + attribute \src "ls180.v:4963.1-4970.4" + process $proc$ls180.v:4963$830 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4854.2-4858.5" + attribute \src "ls180.v:4965.2-4969.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4854.6-4854.38" + attribute \src "ls180.v:4965.6-4965.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4856.6-4856.10" + attribute \src "ls180.v:4967.6-4967.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:4874.1-4881.4" - process $proc$ls180.v:4874$845 + attribute \src "ls180.v:498.5-498.47" + process $proc$ls180.v:498$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:4985.1-4992.4" + process $proc$ls180.v:4985$853 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4876.2-4880.5" + attribute \src "ls180.v:4987.2-4991.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4876.6-4876.44" + attribute \src "ls180.v:4987.6-4987.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4878.6-4878.10" + attribute \src "ls180.v:4989.6-4989.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:4884.1-4891.4" - process $proc$ls180.v:4884$856 + attribute \src "ls180.v:499.5-499.45" + process $proc$ls180.v:499$2949 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:4995.1-5002.4" + process $proc$ls180.v:4995$864 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4886.2-4890.5" + attribute \src "ls180.v:4997.2-5001.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4886.6-4886.44" + attribute \src "ls180.v:4997.6-4997.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4888.6-4888.10" + attribute \src "ls180.v:4999.6-4999.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:4894.1-4901.4" - process $proc$ls180.v:4894$867 + attribute \src "ls180.v:500.5-500.45" + process $proc$ls180.v:500$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:5005.1-5012.4" + process $proc$ls180.v:5005$875 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4896.2-4900.5" + attribute \src "ls180.v:5007.2-5011.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:4896.6-4896.44" + attribute \src "ls180.v:5007.6-5007.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:4898.6-4898.10" + attribute \src "ls180.v:5009.6-5009.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:49.5-49.42" - process $proc$ls180.v:49$2765 + attribute \src "ls180.v:501.12-501.57" + process $proc$ls180.v:501$2951 assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:4904.1-4911.4" - process $proc$ls180.v:4904$878 + attribute \src "ls180.v:5015.1-5022.4" + process $proc$ls180.v:5015$886 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4906.2-4910.5" + attribute \src "ls180.v:5017.2-5021.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:4906.6-4906.44" + attribute \src "ls180.v:5017.6-5017.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:4908.6-4908.10" + attribute \src "ls180.v:5019.6-5019.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:4912.1-4991.4" - process $proc$ls180.v:4912$879 + attribute \src "ls180.v:5023.1-5102.4" + process $proc$ls180.v:5023$887 assign { } { } assign { } { } assign { } { } @@ -266459,36 +272620,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:4929.2-4990.9" + attribute \src "ls180.v:5040.2-5101.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:4933.4-4935.7" - switch $eq$ls180.v:4933$880_Y - attribute \src "ls180.v:4933.8-4933.48" + attribute \src "ls180.v:5044.4-5046.7" + switch $eq$ls180.v:5044$888_Y + attribute \src "ls180.v:5044.8-5044.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:4936.4-4961.11" + attribute \src "ls180.v:5047.4-5072.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -266516,18 +272677,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:4962.4-4969.7" + attribute \src "ls180.v:5073.4-5080.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:4962.8-4962.47" + attribute \src "ls180.v:5073.8-5073.47" case 1'1 - attribute \src "ls180.v:4963.5-4968.8" - switch $eq$ls180.v:4963$881_Y - attribute \src "ls180.v:4963.9-4963.49" + attribute \src "ls180.v:5074.5-5079.8" + switch $eq$ls180.v:5074$889_Y + attribute \src "ls180.v:5074.9-5074.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:4965.9-4965.13" + attribute \src "ls180.v:5076.9-5076.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:4966$882_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5077$890_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -266546,9 +272707,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:4984.4-4988.7" - switch $and$ls180.v:4984$884_Y - attribute \src "ls180.v:4984.8-4984.128" + attribute \src "ls180.v:5095.4-5099.7" + switch $and$ls180.v:5095$892_Y + attribute \src "ls180.v:5095.8-5095.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -266573,139 +272734,163 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:498.11-498.68" - process $proc$ls180.v:498$2945 + attribute \src "ls180.v:503.5-503.51" + process $proc$ls180.v:503$2952 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:499.5-499.64" - process $proc$ls180.v:499$2946 + attribute \src "ls180.v:504.5-504.51" + process $proc$ls180.v:504$2953 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] end - attribute \src "ls180.v:4992.1-4997.4" - process $proc$ls180.v:4992$885 + attribute \src "ls180.v:505.5-505.50" + process $proc$ls180.v:505$2954 assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:4994.2-4996.5" - switch $and$ls180.v:4994$892_Y - attribute \src "ls180.v:4994.6-4994.301" - case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 - case - end + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] end - attribute \src "ls180.v:50.5-50.37" - process $proc$ls180.v:50$2766 + attribute \src "ls180.v:506.5-506.54" + process $proc$ls180.v:506$2955 assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:500.11-500.70" - process $proc$ls180.v:500$2947 + attribute \src "ls180.v:507.5-507.55" + process $proc$ls180.v:507$2956 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:508.5-508.56" + process $proc$ls180.v:508$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:509.5-509.50" + process $proc$ls180.v:509$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:5000.1-5007.4" - process $proc$ls180.v:5000$894 + attribute \src "ls180.v:5103.1-5108.4" + process $proc$ls180.v:5103$893 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5105.2-5107.5" + switch $and$ls180.v:5105$900_Y + attribute \src "ls180.v:5105.6-5105.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:5111.1-5118.4" + process $proc$ls180.v:5111$902 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5002.2-5006.5" - switch $eq$ls180.v:5002$895_Y - attribute \src "ls180.v:5002.6-5002.45" + attribute \src "ls180.v:5113.2-5117.5" + switch $eq$ls180.v:5113$903_Y + attribute \src "ls180.v:5113.6-5113.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5004.6-5004.10" + attribute \src "ls180.v:5115.6-5115.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:501.11-501.70" - process $proc$ls180.v:501$2948 + attribute \src "ls180.v:512.5-512.67" + process $proc$ls180.v:512$2959 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:5010.1-5017.4" - process $proc$ls180.v:5010$897 + attribute \src "ls180.v:5121.1-5128.4" + process $proc$ls180.v:5121$905 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5012.2-5016.5" - switch $eq$ls180.v:5012$898_Y - attribute \src "ls180.v:5012.6-5012.45" + attribute \src "ls180.v:5123.2-5127.5" + switch $eq$ls180.v:5123$906_Y + attribute \src "ls180.v:5123.6-5123.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5014.6-5014.10" + attribute \src "ls180.v:5125.6-5125.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:502.11-502.73" - process $proc$ls180.v:502$2949 + attribute \src "ls180.v:513.5-513.66" + process $proc$ls180.v:513$2960 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5020.1-5027.4" - process $proc$ls180.v:5020$900 + attribute \src "ls180.v:5131.1-5138.4" + process $proc$ls180.v:5131$908 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5022.2-5026.5" - switch $eq$ls180.v:5022$901_Y - attribute \src "ls180.v:5022.6-5022.45" + attribute \src "ls180.v:5133.2-5137.5" + switch $eq$ls180.v:5133$909_Y + attribute \src "ls180.v:5133.6-5133.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5024.6-5024.10" + attribute \src "ls180.v:5135.6-5135.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:5030.1-5037.4" - process $proc$ls180.v:5030$903 + attribute \src "ls180.v:5141.1-5148.4" + process $proc$ls180.v:5141$911 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5032.2-5036.5" - switch $eq$ls180.v:5032$904_Y - attribute \src "ls180.v:5032.6-5032.45" + attribute \src "ls180.v:5143.2-5147.5" + switch $eq$ls180.v:5143$912_Y + attribute \src "ls180.v:5143.6-5143.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5034.6-5034.10" + attribute \src "ls180.v:5145.6-5145.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5039.1-5044.4" - process $proc$ls180.v:5039$905 + attribute \src "ls180.v:5150.1-5155.4" + process $proc$ls180.v:5150$913 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5041.2-5043.5" - switch $and$ls180.v:5041$907_Y - attribute \src "ls180.v:5041.6-5041.85" + attribute \src "ls180.v:5152.2-5154.5" + switch $and$ls180.v:5152$915_Y + attribute \src "ls180.v:5152.6-5152.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -266713,88 +272898,88 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:5045.1-5052.4" - process $proc$ls180.v:5045$908 + attribute \src "ls180.v:5156.1-5163.4" + process $proc$ls180.v:5156$916 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5047.2-5051.5" - switch $lt$ls180.v:5047$909_Y - attribute \src "ls180.v:5047.6-5047.44" + attribute \src "ls180.v:5158.2-5162.5" + switch $lt$ls180.v:5158$917_Y + attribute \src "ls180.v:5158.6-5158.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5049.6-5049.10" + attribute \src "ls180.v:5160.6-5160.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:5056.1-5063.4" - process $proc$ls180.v:5056$920 + attribute \src "ls180.v:5167.1-5174.4" + process $proc$ls180.v:5167$928 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5058.2-5062.5" + attribute \src "ls180.v:5169.2-5173.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5058.6-5058.43" + attribute \src "ls180.v:5169.6-5169.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5060.6-5060.10" + attribute \src "ls180.v:5171.6-5171.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:5066.1-5073.4" - process $proc$ls180.v:5066$931 + attribute \src "ls180.v:5177.1-5184.4" + process $proc$ls180.v:5177$939 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5068.2-5072.5" + attribute \src "ls180.v:5179.2-5183.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5068.6-5068.43" + attribute \src "ls180.v:5179.6-5179.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5070.6-5070.10" + attribute \src "ls180.v:5181.6-5181.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5076.1-5083.4" - process $proc$ls180.v:5076$942 + attribute \src "ls180.v:5187.1-5194.4" + process $proc$ls180.v:5187$950 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5078.2-5082.5" + attribute \src "ls180.v:5189.2-5193.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5078.6-5078.43" + attribute \src "ls180.v:5189.6-5189.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5080.6-5080.10" + attribute \src "ls180.v:5191.6-5191.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:5086.1-5093.4" - process $proc$ls180.v:5086$953 + attribute \src "ls180.v:5197.1-5204.4" + process $proc$ls180.v:5197$961 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5088.2-5092.5" + attribute \src "ls180.v:5199.2-5203.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5088.6-5088.43" + attribute \src "ls180.v:5199.6-5199.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5090.6-5090.10" + attribute \src "ls180.v:5201.6-5201.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:5094.1-5284.4" - process $proc$ls180.v:5094$954 + attribute \src "ls180.v:5205.1-5395.4" + process $proc$ls180.v:5205$962 assign { } { } assign { } { } assign { } { } @@ -266834,52 +273019,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5135.2-5283.9" + attribute \src "ls180.v:5246.2-5394.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5138.4-5158.11" + attribute \src "ls180.v:5249.4-5269.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -266899,27 +273084,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5156$955_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5267$963_Y case end - attribute \src "ls180.v:5159.4-5171.7" - switch $and$ls180.v:5159$956_Y - attribute \src "ls180.v:5159.8-5159.65" + attribute \src "ls180.v:5270.4-5282.7" + switch $and$ls180.v:5270$964_Y + attribute \src "ls180.v:5270.8-5270.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5160$957_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5271$965_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5162.5-5170.8" - switch $eq$ls180.v:5162$958_Y - attribute \src "ls180.v:5162.9-5162.40" + attribute \src "ls180.v:5273.5-5281.8" + switch $eq$ls180.v:5273$966_Y + attribute \src "ls180.v:5273.9-5273.40" case 1'1 - attribute \src "ls180.v:5163.6-5169.9" - switch $eq$ls180.v:5163$959_Y - attribute \src "ls180.v:5163.10-5163.40" + attribute \src "ls180.v:5274.6-5280.9" + switch $eq$ls180.v:5274$967_Y + attribute \src "ls180.v:5274.10-5274.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5167.10-5167.14" + attribute \src "ls180.v:5278.10-5278.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -266930,52 +273115,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5175$960_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5286$968_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5176.4-5180.7" - switch $eq$ls180.v:5176$961_Y - attribute \src "ls180.v:5176.8-5176.38" + attribute \src "ls180.v:5287.4-5291.7" + switch $eq$ls180.v:5287$969_Y + attribute \src "ls180.v:5287.8-5287.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5178.8-5178.12" + attribute \src "ls180.v:5289.8-5289.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5182.4-5203.7" + attribute \src "ls180.v:5293.4-5314.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5182.8-5182.36" + attribute \src "ls180.v:5293.8-5293.36" case 1'1 - attribute \src "ls180.v:5183.5-5202.8" - switch $eq$ls180.v:5183$962_Y - attribute \src "ls180.v:5183.9-5183.56" + attribute \src "ls180.v:5294.5-5313.8" + switch $eq$ls180.v:5294$970_Y + attribute \src "ls180.v:5294.9-5294.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5187.9-5187.13" + attribute \src "ls180.v:5298.9-5298.13" case - attribute \src "ls180.v:5188.6-5201.9" + attribute \src "ls180.v:5299.6-5312.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5188.10-5188.37" + attribute \src "ls180.v:5299.10-5299.37" case 1'1 - attribute \src "ls180.v:5189.7-5197.10" - switch $eq$ls180.v:5189$963_Y - attribute \src "ls180.v:5189.11-5189.42" + attribute \src "ls180.v:5300.7-5308.10" + switch $eq$ls180.v:5300$971_Y + attribute \src "ls180.v:5300.11-5300.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5191.11-5191.15" + attribute \src "ls180.v:5302.11-5302.15" case - attribute \src "ls180.v:5192.8-5196.11" - switch $eq$ls180.v:5192$964_Y - attribute \src "ls180.v:5192.12-5192.43" + attribute \src "ls180.v:5303.8-5307.11" + switch $eq$ls180.v:5303$972_Y + attribute \src "ls180.v:5303.12-5303.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5194.12-5194.16" + attribute \src "ls180.v:5305.12-5305.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5198.10-5198.14" + attribute \src "ls180.v:5309.10-5309.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -266991,28 +273176,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5211.4-5217.7" - switch $and$ls180.v:5211$966_Y - attribute \src "ls180.v:5211.8-5211.98" + attribute \src "ls180.v:5322.4-5328.7" + switch $and$ls180.v:5322$974_Y + attribute \src "ls180.v:5322.8-5322.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5212$967_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5323$975_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5214.5-5216.8" - switch $eq$ls180.v:5214$969_Y - attribute \src "ls180.v:5214.9-5214.77" + attribute \src "ls180.v:5325.5-5327.8" + switch $eq$ls180.v:5325$977_Y + attribute \src "ls180.v:5325.9-5325.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5219.4-5224.7" + attribute \src "ls180.v:5330.4-5335.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5219.8-5219.37" + attribute \src "ls180.v:5330.8-5330.37" case 1'1 - attribute \src "ls180.v:5220.5-5223.8" - switch $ne$ls180.v:5220$970_Y - attribute \src "ls180.v:5220.9-5220.57" + attribute \src "ls180.v:5331.5-5334.8" + switch $ne$ls180.v:5331$978_Y + attribute \src "ls180.v:5331.9-5331.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -267024,42 +273209,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5229$972_Y - attribute \src "ls180.v:5230.4-5256.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5340$980_Y + attribute \src "ls180.v:5341.4-5367.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5230.8-5230.37" + attribute \src "ls180.v:5341.8-5341.37" case 1'1 - attribute \src "ls180.v:5231.5-5255.8" - switch $eq$ls180.v:5231$973_Y - attribute \src "ls180.v:5231.9-5231.57" + attribute \src "ls180.v:5342.5-5366.8" + switch $eq$ls180.v:5342$981_Y + attribute \src "ls180.v:5342.9-5342.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5237.6-5245.9" - switch $and$ls180.v:5237$974_Y - attribute \src "ls180.v:5237.10-5237.72" + attribute \src "ls180.v:5348.6-5356.9" + switch $and$ls180.v:5348$982_Y + attribute \src "ls180.v:5348.10-5348.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5238$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5349$983_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5240.7-5244.10" - switch $eq$ls180.v:5240$977_Y - attribute \src "ls180.v:5240.11-5240.79" + attribute \src "ls180.v:5351.7-5355.10" + switch $eq$ls180.v:5351$985_Y + attribute \src "ls180.v:5351.11-5351.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5242.11-5242.15" + attribute \src "ls180.v:5353.11-5353.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5246.9-5246.13" + attribute \src "ls180.v:5357.9-5357.13" case - attribute \src "ls180.v:5247.6-5254.9" - switch $eq$ls180.v:5247$978_Y - attribute \src "ls180.v:5247.10-5247.58" + attribute \src "ls180.v:5358.6-5365.9" + switch $eq$ls180.v:5358$986_Y + attribute \src "ls180.v:5358.10-5358.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -267082,9 +273267,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5267.4-5281.7" + attribute \src "ls180.v:5378.4-5392.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5267.8-5267.31" + attribute \src "ls180.v:5378.8-5378.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -267143,120 +273328,73 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:51.12-51.60" - process $proc$ls180.v:51$2767 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:52.5-52.39" - process $proc$ls180.v:52$2768 + attribute \src "ls180.v:528.11-528.68" + process $proc$ls180.v:528$2961 assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:523.5-523.59" - process $proc$ls180.v:523$2950 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:525.5-525.59" - process $proc$ls180.v:525$2951 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:526.5-526.58" - process $proc$ls180.v:526$2952 + attribute \src "ls180.v:529.5-529.64" + process $proc$ls180.v:529$2962 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:527.5-527.64" - process $proc$ls180.v:527$2953 + attribute \src "ls180.v:530.11-530.70" + process $proc$ls180.v:530$2963 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:528.12-528.74" - process $proc$ls180.v:528$2954 + attribute \src "ls180.v:531.11-531.70" + process $proc$ls180.v:531$2964 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:529.12-529.47" - process $proc$ls180.v:529$2955 + attribute \src "ls180.v:532.11-532.73" + process $proc$ls180.v:532$2965 assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:530.5-530.46" - process $proc$ls180.v:530$2956 + attribute \src "ls180.v:54.5-54.42" + process $proc$ls180.v:54$2775 assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:5312.1-5319.4" - process $proc$ls180.v:5312$979 + attribute \src "ls180.v:5423.1-5430.4" + process $proc$ls180.v:5423$987 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5314.2-5318.5" + attribute \src "ls180.v:5425.2-5429.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5314.6-5314.35" + attribute \src "ls180.v:5425.6-5425.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5315$980_Y - attribute \src "ls180.v:5316.6-5316.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5426$988_Y + attribute \src "ls180.v:5427.6-5427.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:532.5-532.44" - process $proc$ls180.v:532$2957 + attribute \src "ls180.v:5456.1-5495.4" + process $proc$ls180.v:5456$998 assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:533.5-533.45" - process $proc$ls180.v:533$2958 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:534.5-534.54" - process $proc$ls180.v:534$2959 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5345.1-5384.4" - process $proc$ls180.v:5345$990 assign { } { } assign { } { } assign { } { } @@ -267264,41 +273402,40 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign { } { } assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5355.2-5383.9" + attribute \src "ls180.v:5466.2-5494.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5359$991_Y + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5470$999_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5361.4-5372.7" - switch $and$ls180.v:5361$992_Y - attribute \src "ls180.v:5361.8-5361.103" + attribute \src "ls180.v:5472.4-5483.7" + switch $and$ls180.v:5472$1000_Y + attribute \src "ls180.v:5472.8-5472.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5362$993_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5473$1001_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5364.5-5371.8" - switch $eq$ls180.v:5364$995_Y - attribute \src "ls180.v:5364.9-5364.106" + attribute \src "ls180.v:5475.5-5482.8" + switch $eq$ls180.v:5475$1003_Y + attribute \src "ls180.v:5475.9-5475.106" case 1'1 - attribute \src "ls180.v:5365.6-5370.9" + attribute \src "ls180.v:5476.6-5481.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5365.10-5365.57" + attribute \src "ls180.v:5476.10-5476.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5368.10-5368.14" + attribute \src "ls180.v:5479.10-5479.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -267326,32 +273463,17 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:536.32-536.76" - process $proc$ls180.v:536$2960 + attribute \src "ls180.v:55.5-55.37" + process $proc$ls180.v:55$2776 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:537.11-537.55" - process $proc$ls180.v:537$2961 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "ls180.v:539.32-539.75" - process $proc$ls180.v:539$2962 + attribute \src "ls180.v:5515.1-5552.4" + process $proc$ls180.v:5515$1005 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:5404.1-5441.4" - process $proc$ls180.v:5404$997 assign { } { } assign { } { } assign { } { } @@ -267364,29 +273486,28 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign { } { } assign $0\main_interface1_bus_sel[3:0] 4'0000 assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5418.2-5440.9" + attribute \src "ls180.v:5529.2-5551.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5423.4-5426.7" + attribute \src "ls180.v:5534.4-5537.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5423.8-5423.41" + attribute \src "ls180.v:5534.8-5534.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -267399,9 +273520,9 @@ module \ls180 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_interface1_bus_sel[3:0] 4'1111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5434.4-5438.7" - switch $and$ls180.v:5434$998_Y - attribute \src "ls180.v:5434.8-5434.59" + attribute \src "ls180.v:5545.4-5549.7" + switch $and$ls180.v:5545$1006_Y + attribute \src "ls180.v:5545.8-5545.59" case 1'1 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 @@ -267423,16 +273544,25 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:541.32-541.76" - process $proc$ls180.v:541$2963 + attribute \src "ls180.v:553.5-553.59" + process $proc$ls180.v:553$2966 assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:555.5-555.59" + process $proc$ls180.v:555$2967 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:5442.1-5478.4" - process $proc$ls180.v:5442$999 + attribute \src "ls180.v:5553.1-5589.4" + process $proc$ls180.v:5553$1007 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -267440,38 +273570,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign { } { } - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5451.2-5477.9" + attribute \src "ls180.v:5562.2-5588.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5454$1001_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5455$1002_Y - attribute \src "ls180.v:5456.4-5467.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5565$1009_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5566$1010_Y + attribute \src "ls180.v:5567.4-5578.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5456.8-5456.39" + attribute \src "ls180.v:5567.8-5567.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5457$1003_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5568$1011_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5459.5-5466.8" + attribute \src "ls180.v:5570.5-5577.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5459.9-5459.39" + attribute \src "ls180.v:5570.9-5570.39" case 1'1 - attribute \src "ls180.v:5460.6-5465.9" + attribute \src "ls180.v:5571.6-5576.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5460.10-5460.43" + attribute \src "ls180.v:5571.10-5571.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5463.10-5463.14" + attribute \src "ls180.v:5574.10-5574.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -267497,225 +273626,118 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:547.5-547.51" - process $proc$ls180.v:547$2964 + attribute \src "ls180.v:556.5-556.58" + process $proc$ls180.v:556$2968 assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:548.5-548.51" - process $proc$ls180.v:548$2965 + attribute \src "ls180.v:557.5-557.64" + process $proc$ls180.v:557$2969 assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - end - attribute \src "ls180.v:5490.1-5506.4" - process $proc$ls180.v:5490$1009 - assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5492.2-5505.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] - end - sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:550.5-550.47" - process $proc$ls180.v:550$2966 + attribute \src "ls180.v:558.12-558.74" + process $proc$ls180.v:558$2970 assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:551.5-551.45" - process $proc$ls180.v:551$2967 + attribute \src "ls180.v:559.12-559.47" + process $proc$ls180.v:559$2971 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:552.5-552.45" - process $proc$ls180.v:552$2968 + attribute \src "ls180.v:56.12-56.60" + process $proc$ls180.v:56$2777 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:5520.1-5527.4" - process $proc$ls180.v:5520$1010 - assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5522.2-5526.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5522.6-5522.35" - case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5523$1011_Y - attribute \src "ls180.v:5524.6-5524.10" - case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce - end - sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end - attribute \src "ls180.v:553.12-553.57" - process $proc$ls180.v:553$2969 + attribute \src "ls180.v:560.5-560.46" + process $proc$ls180.v:560$2972 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:5545.1-5593.4" - process $proc$ls180.v:5545$1021 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:5601.1-5617.4" + process $proc$ls180.v:5601$1017 assign { } { } - assign { } { } - assign $0\libresocsim_clk_enable[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_cs_enable[0:0] 1'0 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\libresocsim_mosi_latch[0:0] 1'0 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_irq[0:0] 1'0 - assign $0\libresocsim_miso_latch[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:5556.2-5592.9" - switch \builder_spimaster1_state + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5603.2-5616.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5560.4-5563.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5560.8-5560.28" - case 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\libresocsim_clk_enable[0:0] 1'1 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5568.4-5574.7" - switch \libresocsim_clk_fall - attribute \src "ls180.v:5568.8-5568.28" - case 1'1 - assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$ls180.v:5569$1022_Y - assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5571.5-5573.8" - switch $eq$ls180.v:5571$1024_Y - attribute \src "ls180.v:5571.9-5571.60" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\libresocsim_cs_enable[0:0] 1'1 - attribute \src "ls180.v:5578.4-5582.7" - switch \libresocsim_clk_rise - attribute \src "ls180.v:5578.8-5578.28" - case 1'1 - assign $0\libresocsim_miso_latch[0:0] 1'1 - assign $0\libresocsim_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] attribute \src "ls180.v:0.0-0.0" case - assign $0\libresocsim_done0[0:0] 1'1 - attribute \src "ls180.v:5586.4-5590.7" - switch \libresocsim_start0 - attribute \src "ls180.v:5586.8-5586.26" - case 1'1 - assign $0\libresocsim_done0[0:0] 1'0 - assign $0\libresocsim_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] end sync always - update \libresocsim_done0 $0\libresocsim_done0[0:0] - update \libresocsim_irq $0\libresocsim_irq[0:0] - update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] - update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] - update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] - update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] - update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:555.5-555.51" - process $proc$ls180.v:555$2970 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:556.5-556.51" - process $proc$ls180.v:556$2971 + attribute \src "ls180.v:562.5-562.44" + process $proc$ls180.v:562$2973 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "ls180.v:557.5-557.50" - process $proc$ls180.v:557$2972 + attribute \src "ls180.v:563.5-563.45" + process $proc$ls180.v:563$2974 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:558.5-558.54" - process $proc$ls180.v:558$2973 + attribute \src "ls180.v:5631.1-5638.4" + process $proc$ls180.v:5631$1018 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5633.2-5637.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5633.6-5633.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5634$1019_Y + attribute \src "ls180.v:5635.6-5635.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:559.5-559.55" - process $proc$ls180.v:559$2974 + attribute \src "ls180.v:564.5-564.54" + process $proc$ls180.v:564$2975 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:5594.1-5630.4" - process $proc$ls180.v:5594$1025 - assign { } { } + attribute \src "ls180.v:5646.1-5682.4" + process $proc$ls180.v:5646$1025 assign { } { } assign { } { } assign { } { } @@ -267733,8 +273755,9 @@ module \ls180 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5605.2-5629.9" + attribute \src "ls180.v:5657.2-5681.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -267752,13 +273775,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5621.4-5627.7" - switch $and$ls180.v:5621$1026_Y - attribute \src "ls180.v:5621.8-5621.77" + attribute \src "ls180.v:5673.4-5679.7" + switch $and$ls180.v:5673$1026_Y + attribute \src "ls180.v:5673.8-5673.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5624$1028_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5676$1028_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -267775,71 +273798,71 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:560.5-560.56" - process $proc$ls180.v:560$2975 + attribute \src "ls180.v:566.32-566.76" + process $proc$ls180.v:566$2976 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "ls180.v:561.5-561.50" - process $proc$ls180.v:561$2976 + attribute \src "ls180.v:567.11-567.55" + process $proc$ls180.v:567$2977 assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:564.5-564.67" - process $proc$ls180.v:564$2977 + attribute \src "ls180.v:569.32-569.75" + process $proc$ls180.v:569$2978 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init end - attribute \src "ls180.v:565.5-565.66" - process $proc$ls180.v:565$2978 + attribute \src "ls180.v:57.5-57.39" + process $proc$ls180.v:57$2778 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:5655.1-5662.4" - process $proc$ls180.v:5655$1049 + attribute \src "ls180.v:5707.1-5714.4" + process $proc$ls180.v:5707$1049 assign { } { } assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5657$1050_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5658$1051_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5659$1052_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5660$1053_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5661$1054_Y + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5709$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5710$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5711$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5712$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5713$1054_Y sync always update \builder_slave_sel $0\builder_slave_sel[4:0] end - attribute \src "ls180.v:57.12-57.47" - process $proc$ls180.v:57$2769 + attribute \src "ls180.v:571.32-571.76" + process $proc$ls180.v:571$2979 assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:5705.1-5716.4" - process $proc$ls180.v:5705$1067 + attribute \src "ls180.v:5757.1-5768.4" + process $proc$ls180.v:5757$1067 assign { } { } assign { } { } assign { } { } assign $0\builder_error[0:0] 1'0 assign { } { } assign { } { } - assign $0\builder_shared_ack[0:0] $or$ls180.v:5709$1071_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5710$1080_Y - attribute \src "ls180.v:5711.2-5715.5" + assign $0\builder_shared_ack[0:0] $or$ls180.v:5761$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5762$1080_Y + attribute \src "ls180.v:5763.2-5767.5" switch \builder_done - attribute \src "ls180.v:5711.6-5711.18" + attribute \src "ls180.v:5763.6-5763.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -267851,303 +273874,319 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:580.11-580.68" - process $proc$ls180.v:580$2979 + attribute \src "ls180.v:577.5-577.51" + process $proc$ls180.v:577$2980 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:581.5-581.64" - process $proc$ls180.v:581$2980 + attribute \src "ls180.v:578.5-578.51" + process $proc$ls180.v:578$2981 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:582.11-582.70" - process $proc$ls180.v:582$2981 + attribute \src "ls180.v:580.5-580.47" + process $proc$ls180.v:580$2982 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:583.11-583.70" - process $proc$ls180.v:583$2982 + attribute \src "ls180.v:581.5-581.45" + process $proc$ls180.v:581$2983 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:584.11-584.73" - process $proc$ls180.v:584$2983 + attribute \src "ls180.v:582.5-582.45" + process $proc$ls180.v:582$2984 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:59.12-59.55" - process $proc$ls180.v:59$2770 + attribute \src "ls180.v:583.12-583.57" + process $proc$ls180.v:583$2985 assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:605.5-605.59" - process $proc$ls180.v:605$2984 + attribute \src "ls180.v:585.5-585.51" + process $proc$ls180.v:585$2986 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:607.5-607.59" - process $proc$ls180.v:607$2985 + attribute \src "ls180.v:586.5-586.51" + process $proc$ls180.v:586$2987 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:608.5-608.58" - process $proc$ls180.v:608$2986 + attribute \src "ls180.v:587.5-587.50" + process $proc$ls180.v:587$2988 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:609.5-609.64" - process $proc$ls180.v:609$2987 + attribute \src "ls180.v:588.5-588.54" + process $proc$ls180.v:588$2989 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:610.12-610.74" - process $proc$ls180.v:610$2988 + attribute \src "ls180.v:589.5-589.55" + process $proc$ls180.v:589$2990 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:611.12-611.47" - process $proc$ls180.v:611$2989 + attribute \src "ls180.v:590.5-590.56" + process $proc$ls180.v:590$2991 assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:612.5-612.46" - process $proc$ls180.v:612$2990 + attribute \src "ls180.v:591.5-591.50" + process $proc$ls180.v:591$2992 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:614.5-614.44" - process $proc$ls180.v:614$2991 + attribute \src "ls180.v:594.5-594.67" + process $proc$ls180.v:594$2993 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:615.5-615.45" - process $proc$ls180.v:615$2992 + attribute \src "ls180.v:595.5-595.66" + process $proc$ls180.v:595$2994 assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:616.5-616.54" - process $proc$ls180.v:616$2993 + attribute \src "ls180.v:610.11-610.68" + process $proc$ls180.v:610$2995 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:618.32-618.76" - process $proc$ls180.v:618$2994 + attribute \src "ls180.v:611.5-611.64" + process $proc$ls180.v:611$2996 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:619.11-619.55" - process $proc$ls180.v:619$2995 + attribute \src "ls180.v:612.11-612.70" + process $proc$ls180.v:612$2997 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:621.32-621.75" - process $proc$ls180.v:621$2996 + attribute \src "ls180.v:613.11-613.70" + process $proc$ls180.v:613$2998 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:6216.1-6221.4" - process $proc$ls180.v:6216$1939 + attribute \src "ls180.v:614.11-614.73" + process $proc$ls180.v:614$2999 assign { } { } - assign $0\main_spi_master_start1[0:0] 1'0 - attribute \src "ls180.v:6218.2-6220.5" - switch \main_spi_master_control_re - attribute \src "ls180.v:6218.6-6218.32" - case 1'1 - assign $0\main_spi_master_start1[0:0] \main_spi_master_control_storage [0] - case - end + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always - update \main_spi_master_start1 $0\main_spi_master_start1[0:0] + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:623.32-623.76" - process $proc$ls180.v:623$2997 + attribute \src "ls180.v:62.12-62.47" + process $proc$ls180.v:62$2779 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $1\main_libresocsim_bus_errors[31:0] 0 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:6262.1-6267.4" - process $proc$ls180.v:6262$2004 + attribute \src "ls180.v:6282.1-6287.4" + process $proc$ls180.v:6282$1954 assign { } { } - assign $0\libresocsim_start1[0:0] 1'0 - attribute \src "ls180.v:6264.2-6266.5" - switch \libresocsim_control_re - attribute \src "ls180.v:6264.6-6264.28" + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6284.2-6286.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6284.6-6284.25" case 1'1 - assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] case end sync always - update \libresocsim_start1 $0\libresocsim_start1[0:0] + update \main_spimaster9_start $0\main_spimaster9_start[0:0] end - attribute \src "ls180.v:629.5-629.51" - process $proc$ls180.v:629$2998 + attribute \src "ls180.v:6328.1-6333.4" + process $proc$ls180.v:6328$2019 assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6330.2-6332.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6330.6-6330.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:635.5-635.59" + process $proc$ls180.v:635$3000 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:630.5-630.51" - process $proc$ls180.v:630$2999 + attribute \src "ls180.v:637.5-637.59" + process $proc$ls180.v:637$3001 assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:632.5-632.47" - process $proc$ls180.v:632$3000 + attribute \src "ls180.v:638.5-638.58" + process $proc$ls180.v:638$3002 assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:633.5-633.45" - process $proc$ls180.v:633$3001 + attribute \src "ls180.v:639.5-639.64" + process $proc$ls180.v:639$3003 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:634.5-634.45" - process $proc$ls180.v:634$3002 + attribute \src "ls180.v:64.12-64.55" + process $proc$ls180.v:64$2780 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:635.12-635.57" - process $proc$ls180.v:635$3003 + attribute \src "ls180.v:640.12-640.74" + process $proc$ls180.v:640$3004 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:637.5-637.51" - process $proc$ls180.v:637$3004 + attribute \src "ls180.v:641.12-641.47" + process $proc$ls180.v:641$3005 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:638.5-638.51" - process $proc$ls180.v:638$3005 + attribute \src "ls180.v:642.5-642.46" + process $proc$ls180.v:642$3006 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:639.5-639.50" - process $proc$ls180.v:639$3006 + attribute \src "ls180.v:644.5-644.44" + process $proc$ls180.v:644$3007 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:640.5-640.54" - process $proc$ls180.v:640$3007 + attribute \src "ls180.v:645.5-645.45" + process $proc$ls180.v:645$3008 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:641.5-641.55" - process $proc$ls180.v:641$3008 + attribute \src "ls180.v:646.5-646.54" + process $proc$ls180.v:646$3009 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:642.5-642.56" - process $proc$ls180.v:642$3009 + attribute \src "ls180.v:648.32-648.76" + process $proc$ls180.v:648$3010 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:643.5-643.50" - process $proc$ls180.v:643$3010 + attribute \src "ls180.v:649.11-649.55" + process $proc$ls180.v:649$3011 assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:651.32-651.75" + process $proc$ls180.v:651$3012 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init end - attribute \src "ls180.v:6448.1-6464.4" - process $proc$ls180.v:6448$2224 + attribute \src "ls180.v:6517.1-6533.4" + process $proc$ls180.v:6517$2240 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6450.2-6463.9" + attribute \src "ls180.v:6519.2-6532.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268165,19 +274204,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:646.5-646.67" - process $proc$ls180.v:646$3011 + attribute \src "ls180.v:653.32-653.76" + process $proc$ls180.v:653$3013 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init end - attribute \src "ls180.v:6465.1-6481.4" - process $proc$ls180.v:6465$2225 + attribute \src "ls180.v:6534.1-6550.4" + process $proc$ls180.v:6534$2241 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6467.2-6480.9" + attribute \src "ls180.v:6536.2-6549.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268195,19 +274234,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:647.5-647.66" - process $proc$ls180.v:647$3012 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6482.1-6498.4" - process $proc$ls180.v:6482$2226 + attribute \src "ls180.v:6551.1-6567.4" + process $proc$ls180.v:6551$2242 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6484.2-6497.9" + attribute \src "ls180.v:6553.2-6566.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268225,11 +274256,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:6499.1-6515.4" - process $proc$ls180.v:6499$2227 + attribute \src "ls180.v:6568.1-6584.4" + process $proc$ls180.v:6568$2243 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6501.2-6514.9" + attribute \src "ls180.v:6570.2-6583.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268247,11 +274278,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6516.1-6532.4" - process $proc$ls180.v:6516$2228 + attribute \src "ls180.v:6585.1-6601.4" + process $proc$ls180.v:6585$2244 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6518.2-6531.9" + attribute \src "ls180.v:6587.2-6600.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268269,11 +274300,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:6533.1-6549.4" - process $proc$ls180.v:6533$2229 + attribute \src "ls180.v:659.5-659.51" + process $proc$ls180.v:659$3014 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:660.5-660.51" + process $proc$ls180.v:660$3015 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:6602.1-6618.4" + process $proc$ls180.v:6602$2245 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6535.2-6548.9" + attribute \src "ls180.v:6604.2-6617.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268291,11 +274338,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6550.1-6566.4" - process $proc$ls180.v:6550$2230 + attribute \src "ls180.v:6619.1-6635.4" + process $proc$ls180.v:6619$2246 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6552.2-6565.9" + attribute \src "ls180.v:6621.2-6634.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268313,11 +274360,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6567.1-6583.4" - process $proc$ls180.v:6567$2231 + attribute \src "ls180.v:662.5-662.47" + process $proc$ls180.v:662$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:663.5-663.45" + process $proc$ls180.v:663$3017 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:6636.1-6652.4" + process $proc$ls180.v:6636$2247 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6569.2-6582.9" + attribute \src "ls180.v:6638.2-6651.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268335,11 +274398,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6584.1-6600.4" - process $proc$ls180.v:6584$2232 + attribute \src "ls180.v:664.5-664.45" + process $proc$ls180.v:664$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:665.12-665.57" + process $proc$ls180.v:665$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:6653.1-6669.4" + process $proc$ls180.v:6653$2248 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6586.2-6599.9" + attribute \src "ls180.v:6655.2-6668.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268357,19 +274436,19 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:66.5-66.46" - process $proc$ls180.v:66$2771 + attribute \src "ls180.v:667.5-667.51" + process $proc$ls180.v:667$3020 assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:6601.1-6617.4" - process $proc$ls180.v:6601$2233 + attribute \src "ls180.v:6670.1-6686.4" + process $proc$ls180.v:6670$2249 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6603.2-6616.9" + attribute \src "ls180.v:6672.2-6685.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268387,11 +274466,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6618.1-6634.4" - process $proc$ls180.v:6618$2234 + attribute \src "ls180.v:668.5-668.51" + process $proc$ls180.v:668$3021 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:6687.1-6703.4" + process $proc$ls180.v:6687$2250 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6620.2-6633.9" + attribute \src "ls180.v:6689.2-6702.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268409,27 +274496,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:662.11-662.68" - process $proc$ls180.v:662$3013 + attribute \src "ls180.v:669.5-669.50" + process $proc$ls180.v:669$3022 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:663.5-663.64" - process $proc$ls180.v:663$3014 + attribute \src "ls180.v:670.5-670.54" + process $proc$ls180.v:670$3023 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:6635.1-6651.4" - process $proc$ls180.v:6635$2235 + attribute \src "ls180.v:6704.1-6720.4" + process $proc$ls180.v:6704$2251 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6637.2-6650.9" + attribute \src "ls180.v:6706.2-6719.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268447,27 +274534,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:664.11-664.70" - process $proc$ls180.v:664$3015 + attribute \src "ls180.v:671.5-671.55" + process $proc$ls180.v:671$3024 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:665.11-665.70" - process $proc$ls180.v:665$3016 + attribute \src "ls180.v:672.5-672.56" + process $proc$ls180.v:672$3025 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:6652.1-6668.4" - process $proc$ls180.v:6652$2236 + attribute \src "ls180.v:6721.1-6737.4" + process $proc$ls180.v:6721$2252 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6654.2-6667.9" + attribute \src "ls180.v:6723.2-6736.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268485,19 +274572,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:666.11-666.73" - process $proc$ls180.v:666$3017 + attribute \src "ls180.v:673.5-673.50" + process $proc$ls180.v:673$3026 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:6669.1-6685.4" - process $proc$ls180.v:6669$2237 + attribute \src "ls180.v:6738.1-6754.4" + process $proc$ls180.v:6738$2253 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6671.2-6684.9" + attribute \src "ls180.v:6740.2-6753.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268515,11 +274602,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:6686.1-6702.4" - process $proc$ls180.v:6686$2238 + attribute \src "ls180.v:6755.1-6771.4" + process $proc$ls180.v:6755$2254 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6688.2-6701.9" + attribute \src "ls180.v:6757.2-6770.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268537,11 +274624,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:6703.1-6719.4" - process $proc$ls180.v:6703$2239 + attribute \src "ls180.v:676.5-676.67" + process $proc$ls180.v:676$3027 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:677.5-677.66" + process $proc$ls180.v:677$3028 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6772.1-6788.4" + process $proc$ls180.v:6772$2255 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6705.2-6718.9" + attribute \src "ls180.v:6774.2-6787.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268559,11 +274662,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:6720.1-6736.4" - process $proc$ls180.v:6720$2240 + attribute \src "ls180.v:6789.1-6805.4" + process $proc$ls180.v:6789$2256 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6722.2-6735.9" + attribute \src "ls180.v:6791.2-6804.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268581,11 +274684,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:6737.1-6753.4" - process $proc$ls180.v:6737$2241 + attribute \src "ls180.v:6806.1-6822.4" + process $proc$ls180.v:6806$2257 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6739.2-6752.9" + attribute \src "ls180.v:6808.2-6821.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -268603,11 +274706,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:6754.1-6761.4" - process $proc$ls180.v:6754$2242 + attribute \src "ls180.v:6823.1-6830.4" + process $proc$ls180.v:6823$2258 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6756.2-6760.9" + attribute \src "ls180.v:6825.2-6829.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -268616,11 +274719,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6762.1-6769.4" - process $proc$ls180.v:6762$2243 + attribute \src "ls180.v:6831.1-6838.4" + process $proc$ls180.v:6831$2259 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6764.2-6768.9" + attribute \src "ls180.v:6833.2-6837.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -268629,24 +274732,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:6770.1-6777.4" - process $proc$ls180.v:6770$2244 + attribute \src "ls180.v:6839.1-6846.4" + process $proc$ls180.v:6839$2260 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6772.2-6776.9" + attribute \src "ls180.v:6841.2-6845.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6774$2257_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6843$2273_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6778.1-6785.4" - process $proc$ls180.v:6778$2258 + attribute \src "ls180.v:6847.1-6854.4" + process $proc$ls180.v:6847$2274 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6780.2-6784.9" + attribute \src "ls180.v:6849.2-6853.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -268655,11 +274758,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6786.1-6793.4" - process $proc$ls180.v:6786$2259 + attribute \src "ls180.v:6855.1-6862.4" + process $proc$ls180.v:6855$2275 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6788.2-6792.9" + attribute \src "ls180.v:6857.2-6861.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -268668,24 +274771,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:6794.1-6801.4" - process $proc$ls180.v:6794$2260 + attribute \src "ls180.v:6863.1-6870.4" + process $proc$ls180.v:6863$2276 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6796.2-6800.9" + attribute \src "ls180.v:6865.2-6869.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6798$2273_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6867$2289_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:6802.1-6809.4" - process $proc$ls180.v:6802$2274 + attribute \src "ls180.v:6871.1-6878.4" + process $proc$ls180.v:6871$2290 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6804.2-6808.9" + attribute \src "ls180.v:6873.2-6877.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -268694,11 +274797,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6810.1-6817.4" - process $proc$ls180.v:6810$2275 + attribute \src "ls180.v:6879.1-6886.4" + process $proc$ls180.v:6879$2291 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6812.2-6816.9" + attribute \src "ls180.v:6881.2-6885.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -268707,24 +274810,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6818.1-6825.4" - process $proc$ls180.v:6818$2276 + attribute \src "ls180.v:6887.1-6894.4" + process $proc$ls180.v:6887$2292 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6820.2-6824.9" + attribute \src "ls180.v:6889.2-6893.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6822$2289_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6891$2305_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:6826.1-6833.4" - process $proc$ls180.v:6826$2290 + attribute \src "ls180.v:6895.1-6902.4" + process $proc$ls180.v:6895$2306 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6828.2-6832.9" + attribute \src "ls180.v:6897.2-6901.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -268733,11 +274836,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:6834.1-6841.4" - process $proc$ls180.v:6834$2291 + attribute \src "ls180.v:6903.1-6910.4" + process $proc$ls180.v:6903$2307 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6836.2-6840.9" + attribute \src "ls180.v:6905.2-6909.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -268746,24 +274849,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:6842.1-6849.4" - process $proc$ls180.v:6842$2292 + attribute \src "ls180.v:6911.1-6918.4" + process $proc$ls180.v:6911$2308 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6844.2-6848.9" + attribute \src "ls180.v:6913.2-6917.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6846$2305_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6915$2321_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:6850.1-6869.4" - process $proc$ls180.v:6850$2306 + attribute \src "ls180.v:6919.1-6938.4" + process $proc$ls180.v:6919$2322 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6852.2-6868.9" + attribute \src "ls180.v:6921.2-6937.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268784,19 +274887,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:687.5-687.59" - process $proc$ls180.v:687$3018 + attribute \src "ls180.v:692.11-692.68" + process $proc$ls180.v:692$3029 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:6870.1-6889.4" - process $proc$ls180.v:6870$2307 + attribute \src "ls180.v:693.5-693.64" + process $proc$ls180.v:693$3030 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:6939.1-6958.4" + process $proc$ls180.v:6939$2323 assign { } { } assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6872.2-6888.9" + attribute \src "ls180.v:6941.2-6957.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268817,19 +274928,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] end - attribute \src "ls180.v:689.5-689.59" - process $proc$ls180.v:689$3019 + attribute \src "ls180.v:694.11-694.70" + process $proc$ls180.v:694$3031 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:6890.1-6909.4" - process $proc$ls180.v:6890$2308 + attribute \src "ls180.v:695.11-695.70" + process $proc$ls180.v:695$3032 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:6959.1-6978.4" + process $proc$ls180.v:6959$2324 assign { } { } assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6892.2-6908.9" + attribute \src "ls180.v:6961.2-6977.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268850,27 +274969,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] end - attribute \src "ls180.v:690.5-690.58" - process $proc$ls180.v:690$3020 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:691.5-691.64" - process $proc$ls180.v:691$3021 + attribute \src "ls180.v:696.11-696.73" + process $proc$ls180.v:696$3033 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:6910.1-6929.4" - process $proc$ls180.v:6910$2309 + attribute \src "ls180.v:6979.1-6998.4" + process $proc$ls180.v:6979$2325 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6912.2-6928.9" + attribute \src "ls180.v:6981.2-6997.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268891,27 +275002,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:692.12-692.74" - process $proc$ls180.v:692$3022 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:693.12-693.47" - process $proc$ls180.v:693$3023 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:6930.1-6949.4" - process $proc$ls180.v:6930$2310 + attribute \src "ls180.v:6999.1-7018.4" + process $proc$ls180.v:6999$2326 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:6932.2-6948.9" + attribute \src "ls180.v:7001.2-7017.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268932,19 +275027,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:694.5-694.46" - process $proc$ls180.v:694$3024 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:6950.1-6969.4" - process $proc$ls180.v:6950$2311 + attribute \src "ls180.v:7019.1-7038.4" + process $proc$ls180.v:7019$2327 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:6952.2-6968.9" + attribute \src "ls180.v:7021.2-7037.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -268965,27 +275052,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:696.5-696.44" - process $proc$ls180.v:696$3025 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:697.5-697.45" - process $proc$ls180.v:697$3026 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:6970.1-6989.4" - process $proc$ls180.v:6970$2312 + attribute \src "ls180.v:7039.1-7058.4" + process $proc$ls180.v:7039$2328 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:6972.2-6988.9" + attribute \src "ls180.v:7041.2-7057.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -269006,19 +275077,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:698.5-698.54" - process $proc$ls180.v:698$3027 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:6990.1-7009.4" - process $proc$ls180.v:6990$2313 + attribute \src "ls180.v:7059.1-7078.4" + process $proc$ls180.v:7059$2329 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:6992.2-7008.9" + attribute \src "ls180.v:7061.2-7077.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -269039,35 +275102,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:70.5-70.46" - process $proc$ls180.v:70$2772 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] - sync init - end - attribute \src "ls180.v:700.32-700.76" - process $proc$ls180.v:700$3028 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:701.11-701.55" - process $proc$ls180.v:701$3029 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:7010.1-7026.4" - process $proc$ls180.v:7010$2314 + attribute \src "ls180.v:7079.1-7095.4" + process $proc$ls180.v:7079$2330 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7012.2-7025.9" + attribute \src "ls180.v:7081.2-7094.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -269085,11 +275124,11 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:7027.1-7043.4" - process $proc$ls180.v:7027$2315 + attribute \src "ls180.v:7096.1-7112.4" + process $proc$ls180.v:7096$2331 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7029.2-7042.9" + attribute \src "ls180.v:7098.2-7111.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -269107,282 +275146,290 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:703.32-703.75" - process $proc$ls180.v:703$3030 + attribute \src "ls180.v:71.5-71.46" + process $proc$ls180.v:71$2781 assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] end - attribute \src "ls180.v:7044.1-7060.4" - process $proc$ls180.v:7044$2316 + attribute \src "ls180.v:7113.1-7129.4" + process $proc$ls180.v:7113$2332 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7046.2-7059.9" + attribute \src "ls180.v:7115.2-7128.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7051$2318_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7120$2334_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7054$2320_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7123$2336_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7057$2322_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7126$2338_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:705.32-705.76" - process $proc$ls180.v:705$3031 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:7061.1-7077.4" - process $proc$ls180.v:7061$2323 + attribute \src "ls180.v:7130.1-7146.4" + process $proc$ls180.v:7130$2339 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7063.2-7076.9" + attribute \src "ls180.v:7132.2-7145.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7068$2325_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7137$2341_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7071$2327_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7140$2343_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7074$2329_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7143$2345_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:7078.1-7094.4" - process $proc$ls180.v:7078$2330 + attribute \src "ls180.v:7147.1-7163.4" + process $proc$ls180.v:7147$2346 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7080.2-7093.9" + attribute \src "ls180.v:7149.2-7162.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7085$2332_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7154$2348_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7088$2334_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7157$2350_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7091$2336_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7160$2352_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:708.5-708.44" - process $proc$ls180.v:708$3032 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:709.5-709.45" - process $proc$ls180.v:709$3033 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:7095.1-7111.4" - process $proc$ls180.v:7095$2337 + attribute \src "ls180.v:7164.1-7180.4" + process $proc$ls180.v:7164$2353 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7097.2-7110.9" + attribute \src "ls180.v:7166.2-7179.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7102$2339_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7171$2355_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7105$2341_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7174$2357_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7108$2343_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7177$2359_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:710.5-710.43" - process $proc$ls180.v:710$3034 + attribute \src "ls180.v:717.5-717.59" + process $proc$ls180.v:717$3034 assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:711.5-711.48" - process $proc$ls180.v:711$3035 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:7112.1-7128.4" - process $proc$ls180.v:7112$2344 + attribute \src "ls180.v:7181.1-7197.4" + process $proc$ls180.v:7181$2360 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7114.2-7127.9" + attribute \src "ls180.v:7183.2-7196.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7119$2346_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7188$2362_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7122$2348_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7191$2364_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7125$2350_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7194$2366_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:7129.1-7157.4" - process $proc$ls180.v:7129$2351 + attribute \src "ls180.v:719.5-719.59" + process $proc$ls180.v:719$3035 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:7198.1-7226.4" + process $proc$ls180.v:7198$2367 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7131.2-7156.9" - switch \main_spi_master_mosi_sel + attribute \src "ls180.v:7200.2-7225.9" + switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [0] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [1] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [2] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [3] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [4] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [5] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [6] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spi_master_mosi_data [7] + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] end sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:713.5-713.43" - process $proc$ls180.v:713$3036 + attribute \src "ls180.v:720.5-720.58" + process $proc$ls180.v:720$3036 assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:721.5-721.64" + process $proc$ls180.v:721$3037 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:722.12-722.74" + process $proc$ls180.v:722$3038 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:7158.1-7186.4" - process $proc$ls180.v:7158$2352 + attribute \src "ls180.v:7227.1-7255.4" + process $proc$ls180.v:7227$2368 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7160.2-7185.9" - switch \libresocsim_mosi_sel + attribute \src "ls180.v:7229.2-7254.9" + switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] end sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:716.5-716.49" - process $proc$ls180.v:716$3037 + attribute \src "ls180.v:723.12-723.47" + process $proc$ls180.v:723$3039 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:717.5-717.49" - process $proc$ls180.v:717$3038 + attribute \src "ls180.v:724.5-724.46" + process $proc$ls180.v:724$3040 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "ls180.v:718.5-718.48" - process $proc$ls180.v:718$3039 + attribute \src "ls180.v:726.5-726.44" + process $proc$ls180.v:726$3041 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "ls180.v:722.11-722.46" - process $proc$ls180.v:722$3040 + attribute \src "ls180.v:727.5-727.45" + process $proc$ls180.v:727$3042 assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "ls180.v:724.11-724.45" - process $proc$ls180.v:724$3041 + attribute \src "ls180.v:728.5-728.54" + process $proc$ls180.v:728$3043 assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:730.32-730.76" + process $proc$ls180.v:730$3044 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:7244.1-7262.4" - process $proc$ls180.v:7244$2353 + attribute \src "ls180.v:731.11-731.55" + process $proc$ls180.v:731$3045 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:7313.1-7331.4" + process $proc$ls180.v:7313$2369 assign { } { } assign { } { } assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 @@ -269404,31 +275451,31 @@ module \ls180 sync always update \main_gpio_status $0\main_gpio_status[15:0] end - attribute \src "ls180.v:726.5-726.44" - process $proc$ls180.v:726$3042 + attribute \src "ls180.v:733.32-733.75" + process $proc$ls180.v:733$3046 assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:727.5-727.45" - process $proc$ls180.v:727$3043 + attribute \src "ls180.v:735.32-735.76" + process $proc$ls180.v:735$3047 assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:7283.1-7285.4" - process $proc$ls180.v:7283$2354 + attribute \src "ls180.v:7352.1-7354.4" + process $proc$ls180.v:7352$2370 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:7287.1-7357.4" - process $proc$ls180.v:7287$2355 + attribute \src "ls180.v:7356.1-7426.4" + process $proc$ls180.v:7356$2371 assign { } { } assign { } { } assign { } { } @@ -269504,7 +275551,7 @@ module \ls180 assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7344$2357_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7413$2373_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -269518,6 +275565,11 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -269529,54 +275581,49 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:729.5-729.48" - process $proc$ls180.v:729$3044 + attribute \src "ls180.v:738.5-738.44" + process $proc$ls180.v:738$3048 assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:731.5-731.43" - process $proc$ls180.v:731$3045 + attribute \src "ls180.v:739.5-739.45" + process $proc$ls180.v:739$3049 assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:734.5-734.49" - process $proc$ls180.v:734$3046 + attribute \src "ls180.v:740.5-740.43" + process $proc$ls180.v:740$3050 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:735.5-735.49" - process $proc$ls180.v:735$3047 + attribute \src "ls180.v:741.5-741.48" + process $proc$ls180.v:741$3051 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:7359.1-9973.4" - process $proc$ls180.v:7359$2358 - assign $0\spi_master_clk[0:0] \spi_master_clk - assign $0\spi_master_mosi[0:0] \spi_master_mosi + attribute \src "ls180.v:7428.1-10052.4" + process $proc$ls180.v:7428$2374 + assign $0\uart_tx[0:0] \uart_tx + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } - assign $0\pwm0[0:0] \pwm0 - assign $0\pwm1[0:0] \pwm1 + assign $0\pwm[1:0] \pwm assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } @@ -269585,7 +275632,6 @@ module \ls180 assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage assign { } { } assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_tx assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter @@ -269699,22 +275745,22 @@ module \ls180 assign $0\main_converter_dat_r[31:0] \main_converter_dat_r assign $0\main_cmd_consumed[0:0] \main_cmd_consumed assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_storage[31:0] \main_storage + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage assign { } { } assign { } { } - assign $0\main_uart_clk_txen[0:0] \main_uart_clk_txen - assign $0\main_phase_accumulator_tx[31:0] \main_phase_accumulator_tx - assign $0\main_tx_reg[7:0] \main_tx_reg - assign $0\main_tx_bitcount[3:0] \main_tx_bitcount - assign $0\main_tx_busy[0:0] \main_tx_busy + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy assign { } { } - assign $0\main_source_payload_data[7:0] \main_source_payload_data - assign $0\main_uart_clk_rxen[0:0] \main_uart_clk_rxen - assign $0\main_phase_accumulator_rx[31:0] \main_phase_accumulator_rx + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx assign { } { } - assign $0\main_rx_reg[7:0] \main_rx_reg - assign $0\main_rx_bitcount[3:0] \main_rx_bitcount - assign $0\main_rx_busy[0:0] \main_rx_busy + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending assign { } { } assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending @@ -269733,20 +275779,36 @@ module \ls180 assign { } { } assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage assign { } { } - assign $0\main_spi_master_miso[7:0] \main_spi_master_miso - assign $0\main_spi_master_control_storage[15:0] \main_spi_master_control_storage + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage assign { } { } - assign $0\main_spi_master_mosi_storage[7:0] \main_spi_master_mosi_storage + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count assign { } { } - assign $0\main_spi_master_cs_storage[0:0] \main_spi_master_cs_storage + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage assign { } { } - assign $0\main_spi_master_loopback_storage[0:0] \main_spi_master_loopback_storage + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage assign { } { } - assign $0\main_spi_master_count[2:0] \main_spi_master_count + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage assign { } { } - assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi_data - assign $0\main_spi_master_mosi_sel[2:0] \main_spi_master_mosi_sel - assign $0\main_spi_master_miso_data[7:0] \main_spi_master_miso_data assign { } { } assign $0\main_pwm0_counter[31:0] \main_pwm0_counter assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage @@ -269762,6 +275824,8 @@ module \ls180 assign { } { } assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage assign { } { } assign { } { } @@ -269883,22 +275947,6 @@ module \ls180 assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign $0\libresocsim_miso[7:0] \libresocsim_miso - assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage - assign { } { } - assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage - assign { } { } - assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage - assign { } { } - assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage - assign { } { } - assign $0\libresocsim_count[2:0] \libresocsim_count - assign { } { } - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data - assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel - assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data - assign $0\libresocsim_storage[15:0] \libresocsim_storage - assign { } { } assign { } { } assign { } { } assign { } { } @@ -269982,48 +276030,43 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[41:0] [0] $or$ls180.v:7360$2359_Y - assign $0\main_dummy[41:0] [1] $or$ls180.v:7361$2360_Y - assign $0\main_dummy[41:0] [2] $or$ls180.v:7362$2361_Y - assign $0\main_dummy[41:0] [3] $or$ls180.v:7363$2362_Y - assign $0\main_dummy[41:0] [4] $or$ls180.v:7364$2363_Y - assign $0\main_dummy[41:0] [5] $or$ls180.v:7365$2364_Y - assign $0\main_dummy[41:0] [6] $or$ls180.v:7366$2365_Y - assign $0\main_dummy[41:0] [7] $or$ls180.v:7367$2366_Y - assign $0\main_dummy[41:0] [8] $or$ls180.v:7368$2367_Y - assign $0\main_dummy[41:0] [9] $or$ls180.v:7369$2368_Y - assign $0\main_dummy[41:0] [10] $or$ls180.v:7370$2369_Y - assign $0\main_dummy[41:0] [11] $or$ls180.v:7371$2370_Y - assign $0\main_dummy[41:0] [12] $or$ls180.v:7372$2371_Y - assign $0\main_dummy[41:0] [13] $or$ls180.v:7373$2372_Y - assign $0\main_dummy[41:0] [14] $or$ls180.v:7374$2373_Y - assign $0\main_dummy[41:0] [15] $or$ls180.v:7375$2374_Y - assign $0\main_dummy[41:0] [16] $or$ls180.v:7376$2375_Y - assign $0\main_dummy[41:0] [17] $or$ls180.v:7377$2376_Y - assign $0\main_dummy[41:0] [18] $or$ls180.v:7378$2377_Y - assign $0\main_dummy[41:0] [19] $or$ls180.v:7379$2378_Y - assign $0\main_dummy[41:0] [20] $or$ls180.v:7380$2379_Y - assign $0\main_dummy[41:0] [21] $or$ls180.v:7381$2380_Y - assign $0\main_dummy[41:0] [22] $or$ls180.v:7382$2381_Y - assign $0\main_dummy[41:0] [23] $or$ls180.v:7383$2382_Y - assign $0\main_dummy[41:0] [24] $or$ls180.v:7384$2383_Y - assign $0\main_dummy[41:0] [25] $or$ls180.v:7385$2384_Y - assign $0\main_dummy[41:0] [26] $or$ls180.v:7386$2385_Y - assign $0\main_dummy[41:0] [27] $or$ls180.v:7387$2386_Y - assign $0\main_dummy[41:0] [28] $or$ls180.v:7388$2387_Y - assign $0\main_dummy[41:0] [29] $or$ls180.v:7389$2388_Y - assign $0\main_dummy[41:0] [30] $or$ls180.v:7390$2389_Y - assign $0\main_dummy[41:0] [31] $or$ls180.v:7391$2390_Y - assign $0\main_dummy[41:0] [32] $or$ls180.v:7392$2391_Y - assign $0\main_dummy[41:0] [33] $or$ls180.v:7393$2392_Y - assign $0\main_dummy[41:0] [34] $or$ls180.v:7394$2393_Y - assign $0\main_dummy[41:0] [35] $or$ls180.v:7395$2394_Y - assign $0\main_dummy[41:0] [36] $or$ls180.v:7396$2395_Y - assign $0\main_dummy[41:0] [37] $or$ls180.v:7397$2396_Y - assign $0\main_dummy[41:0] [38] $or$ls180.v:7398$2397_Y - assign $0\main_dummy[41:0] [39] $or$ls180.v:7399$2398_Y - assign $0\main_dummy[41:0] [40] $or$ls180.v:7400$2399_Y - assign $0\main_dummy[41:0] [41] $or$ls180.v:7401$2400_Y + assign { } { } + assign $0\main_dummy[35:0] [0] $or$ls180.v:7429$2375_Y + assign $0\main_dummy[35:0] [1] $or$ls180.v:7430$2376_Y + assign $0\main_dummy[35:0] [2] $or$ls180.v:7431$2377_Y + assign $0\main_dummy[35:0] [3] $or$ls180.v:7432$2378_Y + assign $0\main_dummy[35:0] [4] $or$ls180.v:7433$2379_Y + assign $0\main_dummy[35:0] [5] $or$ls180.v:7434$2380_Y + assign $0\main_dummy[35:0] [6] $or$ls180.v:7435$2381_Y + assign $0\main_dummy[35:0] [7] $or$ls180.v:7436$2382_Y + assign $0\main_dummy[35:0] [8] $or$ls180.v:7437$2383_Y + assign $0\main_dummy[35:0] [9] $or$ls180.v:7438$2384_Y + assign $0\main_dummy[35:0] [10] $or$ls180.v:7439$2385_Y + assign $0\main_dummy[35:0] [11] $or$ls180.v:7440$2386_Y + assign $0\main_dummy[35:0] [12] $or$ls180.v:7441$2387_Y + assign $0\main_dummy[35:0] [13] $or$ls180.v:7442$2388_Y + assign $0\main_dummy[35:0] [14] $or$ls180.v:7443$2389_Y + assign $0\main_dummy[35:0] [15] $or$ls180.v:7444$2390_Y + assign $0\main_dummy[35:0] [16] $or$ls180.v:7445$2391_Y + assign $0\main_dummy[35:0] [17] $or$ls180.v:7446$2392_Y + assign $0\main_dummy[35:0] [18] $or$ls180.v:7447$2393_Y + assign $0\main_dummy[35:0] [19] $or$ls180.v:7448$2394_Y + assign $0\main_dummy[35:0] [20] $or$ls180.v:7449$2395_Y + assign $0\main_dummy[35:0] [21] $or$ls180.v:7450$2396_Y + assign $0\main_dummy[35:0] [22] $or$ls180.v:7451$2397_Y + assign $0\main_dummy[35:0] [23] $or$ls180.v:7452$2398_Y + assign $0\main_dummy[35:0] [24] $or$ls180.v:7453$2399_Y + assign $0\main_dummy[35:0] [25] $or$ls180.v:7454$2400_Y + assign $0\main_dummy[35:0] [26] $or$ls180.v:7455$2401_Y + assign $0\main_dummy[35:0] [27] $or$ls180.v:7456$2402_Y + assign $0\main_dummy[35:0] [28] $or$ls180.v:7457$2403_Y + assign $0\main_dummy[35:0] [29] $or$ls180.v:7458$2404_Y + assign $0\main_dummy[35:0] [30] $or$ls180.v:7459$2405_Y + assign $0\main_dummy[35:0] [31] $or$ls180.v:7460$2406_Y + assign $0\main_dummy[35:0] [32] $or$ls180.v:7461$2407_Y + assign $0\main_dummy[35:0] [33] $or$ls180.v:7462$2408_Y + assign $0\main_dummy[35:0] [34] $or$ls180.v:7463$2409_Y + assign $0\main_dummy[35:0] [35] $or$ls180.v:7464$2410_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state @@ -270046,26 +276089,29 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7843$2497_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7844$2498_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7845$2499_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7906$2507_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7907$2508_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7908$2509_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7879$2517_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7880$2529_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7942$2527_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7943$2539_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_sink_ready[0:0] 1'0 - assign $0\main_source_valid[0:0] 1'0 - assign $0\main_rx_r[0:0] \main_rx + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spi_master_clk_divider1[15:0] $add$ls180.v:8038$2575_Y - assign $0\spi_master_cs_n[0:0] $or$ls180.v:8047$2578_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8101$2585_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8110$2588_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8136$2590_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8145$2593_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state @@ -270079,9 +276125,6 @@ module \ls180 assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\libresocsim_clk_divider1[15:0] $add$ls180.v:8586$2670_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8595$2673_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\builder_state[1:0] \builder_next_state assign $0\builder_slave_sel_r[4:0] \builder_slave_sel assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 @@ -270091,58 +276134,60 @@ module \ls180 assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank2_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank2_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank2_period0_re + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank3_period0_re + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank4_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank4_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank4_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank4_dma_loop0_re + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank5_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank5_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank5_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank5_block_count0_re + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank6_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank6_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank6_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank6_dma_loop0_re + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank7_clocker_divider0_re + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank8_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank8_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank8_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank8_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank8_dfii_pi0_wrdata0_re + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spi_master_control_re[0:0] \builder_csrbank9_control0_re - assign $0\main_spi_master_mosi_re[0:0] \builder_csrbank9_mosi0_re - assign $0\main_spi_master_cs_re[0:0] \builder_csrbank9_cs0_re - assign $0\main_spi_master_loopback_re[0:0] \builder_csrbank9_loopback0_re + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\libresocsim_control_re[0:0] \builder_csrbank10_control0_re - assign $0\libresocsim_mosi_re[0:0] \builder_csrbank10_mosi0_re - assign $0\libresocsim_cs_re[0:0] \builder_csrbank10_cs0_re - assign $0\libresocsim_loopback_re[0:0] \builder_csrbank10_loopback0_re - assign $0\libresocsim_re[0:0] \builder_csrbank10_clk_divider0_re + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank11_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank11_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank11_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank11_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_re[0:0] \builder_csrbank13_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \main_libresocsim_libresoc_constraintmanager0_uart0_rx + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 @@ -270176,154 +276221,154 @@ module \ls180 assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7402.2-7404.5" - switch $or$ls180.v:7402$2401_Y - attribute \src "ls180.v:7402.6-7402.94" + attribute \src "ls180.v:7465.2-7467.5" + switch $or$ls180.v:7465$2411_Y + attribute \src "ls180.v:7465.6-7465.94" case 1'1 assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r case end - attribute \src "ls180.v:7406.2-7408.5" + attribute \src "ls180.v:7469.2-7471.5" switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7406.6-7406.66" + attribute \src "ls180.v:7469.6-7469.66" case 1'1 assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7409.2-7412.5" + attribute \src "ls180.v:7472.2-7475.5" switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7409.6-7409.39" + attribute \src "ls180.v:7472.6-7472.39" case 1'1 assign $0\main_libresocsim_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7413.2-7415.5" - switch $or$ls180.v:7413$2402_Y - attribute \src "ls180.v:7413.6-7413.94" + attribute \src "ls180.v:7476.2-7478.5" + switch $or$ls180.v:7476$2412_Y + attribute \src "ls180.v:7476.6-7476.94" case 1'1 assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r case end - attribute \src "ls180.v:7417.2-7419.5" + attribute \src "ls180.v:7480.2-7482.5" switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7417.6-7417.66" + attribute \src "ls180.v:7480.6-7480.66" case 1'1 assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7420.2-7423.5" + attribute \src "ls180.v:7483.2-7486.5" switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7420.6-7420.39" + attribute \src "ls180.v:7483.6-7483.39" case 1'1 assign $0\main_libresocsim_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7424.2-7426.5" - switch $or$ls180.v:7424$2403_Y - attribute \src "ls180.v:7424.6-7424.94" + attribute \src "ls180.v:7487.2-7489.5" + switch $or$ls180.v:7487$2413_Y + attribute \src "ls180.v:7487.6-7487.94" case 1'1 assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r case end - attribute \src "ls180.v:7428.2-7430.5" + attribute \src "ls180.v:7491.2-7493.5" switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7428.6-7428.66" + attribute \src "ls180.v:7491.6-7491.66" case 1'1 assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value case end - attribute \src "ls180.v:7431.2-7434.5" + attribute \src "ls180.v:7494.2-7497.5" switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7431.6-7431.39" + attribute \src "ls180.v:7494.6-7494.39" case 1'1 assign $0\main_libresocsim_converter2_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7435.2-7439.5" - switch $ne$ls180.v:7435$2404_Y - attribute \src "ls180.v:7435.6-7435.53" + attribute \src "ls180.v:7498.2-7502.5" + switch $ne$ls180.v:7498$2414_Y + attribute \src "ls180.v:7498.6-7498.53" case 1'1 - attribute \src "ls180.v:7436.3-7438.6" + attribute \src "ls180.v:7499.3-7501.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7436.7-7436.33" + attribute \src "ls180.v:7499.7-7499.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7437$2405_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7500$2415_Y case end case end - attribute \src "ls180.v:7441.2-7443.5" - switch $and$ls180.v:7441$2408_Y - attribute \src "ls180.v:7441.6-7441.103" + attribute \src "ls180.v:7504.2-7506.5" + switch $and$ls180.v:7504$2418_Y + attribute \src "ls180.v:7504.6-7504.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7444.2-7452.5" + attribute \src "ls180.v:7507.2-7515.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7444.6-7444.33" + attribute \src "ls180.v:7507.6-7507.33" case 1'1 - attribute \src "ls180.v:7445.3-7449.6" - switch $eq$ls180.v:7445$2409_Y - attribute \src "ls180.v:7445.7-7445.39" + attribute \src "ls180.v:7508.3-7512.6" + switch $eq$ls180.v:7508$2419_Y + attribute \src "ls180.v:7508.7-7508.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7447.7-7447.11" + attribute \src "ls180.v:7510.7-7510.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7448$2410_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7511$2420_Y end - attribute \src "ls180.v:7450.6-7450.10" + attribute \src "ls180.v:7513.6-7513.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7453.2-7455.5" + attribute \src "ls180.v:7516.2-7518.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7453.6-7453.38" + attribute \src "ls180.v:7516.6-7516.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7456.2-7458.5" + attribute \src "ls180.v:7519.2-7521.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7456.6-7456.33" + attribute \src "ls180.v:7519.6-7519.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7460.2-7462.5" - switch $and$ls180.v:7460$2412_Y - attribute \src "ls180.v:7460.6-7460.76" + attribute \src "ls180.v:7523.2-7525.5" + switch $and$ls180.v:7523$2422_Y + attribute \src "ls180.v:7523.6-7523.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7465.2-7467.5" + attribute \src "ls180.v:7528.2-7530.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7465.6-7465.37" + attribute \src "ls180.v:7528.6-7528.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7468.2-7472.5" - switch $and$ls180.v:7468$2414_Y - attribute \src "ls180.v:7468.6-7468.57" + attribute \src "ls180.v:7531.2-7535.5" + switch $and$ls180.v:7531$2424_Y + attribute \src "ls180.v:7531.6-7531.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7469$2415_Y - attribute \src "ls180.v:7470.6-7470.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7532$2425_Y + attribute \src "ls180.v:7533.6-7533.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7474.2-7480.5" + attribute \src "ls180.v:7537.2-7543.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7474.6-7474.32" + attribute \src "ls180.v:7537.6-7537.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7475$2416_Y - attribute \src "ls180.v:7476.3-7479.6" - switch $eq$ls180.v:7476$2417_Y - attribute \src "ls180.v:7476.7-7476.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7538$2426_Y + attribute \src "ls180.v:7539.3-7542.6" + switch $eq$ls180.v:7539$2427_Y + attribute \src "ls180.v:7539.7-7539.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -270331,30 +276376,30 @@ module \ls180 end case end - attribute \src "ls180.v:7481.2-7489.5" + attribute \src "ls180.v:7544.2-7552.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7481.6-7481.33" + attribute \src "ls180.v:7544.6-7544.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7483.6-7483.10" + attribute \src "ls180.v:7546.6-7546.10" case - attribute \src "ls180.v:7484.3-7488.6" + attribute \src "ls180.v:7547.3-7551.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7484.7-7484.33" + attribute \src "ls180.v:7547.7-7547.33" case 1'1 - attribute \src "ls180.v:7485.4-7487.7" - switch $ne$ls180.v:7485$2418_Y - attribute \src "ls180.v:7485.8-7485.44" + attribute \src "ls180.v:7548.4-7550.7" + switch $ne$ls180.v:7548$2428_Y + attribute \src "ls180.v:7548.8-7548.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7486$2419_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7549$2429_Y case end case end end - attribute \src "ls180.v:7496.2-7502.5" - switch $and$ls180.v:7496$2421_Y - attribute \src "ls180.v:7496.6-7496.76" + attribute \src "ls180.v:7559.2-7565.5" + switch $and$ls180.v:7559$2431_Y + attribute \src "ls180.v:7559.6-7559.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -270363,9 +276408,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7503.2-7509.5" - switch $eq$ls180.v:7503$2422_Y - attribute \src "ls180.v:7503.6-7503.44" + attribute \src "ls180.v:7566.2-7572.5" + switch $eq$ls180.v:7566$2432_Y + attribute \src "ls180.v:7566.6-7566.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -270374,9 +276419,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7510.2-7517.5" - switch $eq$ls180.v:7510$2423_Y - attribute \src "ls180.v:7510.6-7510.44" + attribute \src "ls180.v:7573.2-7580.5" + switch $eq$ls180.v:7573$2433_Y + attribute \src "ls180.v:7573.6-7573.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -270386,83 +276431,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7518.2-7528.5" - switch $eq$ls180.v:7518$2424_Y - attribute \src "ls180.v:7518.6-7518.44" + attribute \src "ls180.v:7581.2-7591.5" + switch $eq$ls180.v:7581$2434_Y + attribute \src "ls180.v:7581.6-7581.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7520.6-7520.10" + attribute \src "ls180.v:7583.6-7583.10" case - attribute \src "ls180.v:7521.3-7527.6" - switch $ne$ls180.v:7521$2425_Y - attribute \src "ls180.v:7521.7-7521.45" + attribute \src "ls180.v:7584.3-7590.6" + switch $ne$ls180.v:7584$2435_Y + attribute \src "ls180.v:7584.7-7584.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7522$2426_Y - attribute \src "ls180.v:7523.7-7523.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7585$2436_Y + attribute \src "ls180.v:7586.7-7586.11" case - attribute \src "ls180.v:7524.4-7526.7" + attribute \src "ls180.v:7587.4-7589.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7524.8-7524.35" + attribute \src "ls180.v:7587.8-7587.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7530.2-7537.5" + attribute \src "ls180.v:7593.2-7600.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7530.6-7530.39" + attribute \src "ls180.v:7593.6-7593.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7532.6-7532.10" + attribute \src "ls180.v:7595.6-7595.10" case - attribute \src "ls180.v:7533.3-7536.6" + attribute \src "ls180.v:7596.3-7599.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7533.7-7533.39" + attribute \src "ls180.v:7596.7-7596.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7538.2-7540.5" - switch $and$ls180.v:7538$2429_Y - attribute \src "ls180.v:7538.6-7538.191" + attribute \src "ls180.v:7601.2-7603.5" + switch $and$ls180.v:7601$2439_Y + attribute \src "ls180.v:7601.6-7601.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7539$2430_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7602$2440_Y case end - attribute \src "ls180.v:7541.2-7543.5" + attribute \src "ls180.v:7604.2-7606.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7541.6-7541.58" + attribute \src "ls180.v:7604.6-7604.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7542$2431_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7605$2441_Y case end - attribute \src "ls180.v:7544.2-7552.5" - switch $and$ls180.v:7544$2434_Y - attribute \src "ls180.v:7544.6-7544.191" + attribute \src "ls180.v:7607.2-7615.5" + switch $and$ls180.v:7607$2444_Y + attribute \src "ls180.v:7607.6-7607.191" case 1'1 - attribute \src "ls180.v:7545.3-7547.6" - switch $not$ls180.v:7545$2435_Y - attribute \src "ls180.v:7545.7-7545.62" + attribute \src "ls180.v:7608.3-7610.6" + switch $not$ls180.v:7608$2445_Y + attribute \src "ls180.v:7608.7-7608.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7546$2436_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7609$2446_Y case end - attribute \src "ls180.v:7548.6-7548.10" + attribute \src "ls180.v:7611.6-7611.10" case - attribute \src "ls180.v:7549.3-7551.6" + attribute \src "ls180.v:7612.3-7614.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7549.7-7549.59" + attribute \src "ls180.v:7612.7-7612.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7550$2437_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7613$2447_Y case end end - attribute \src "ls180.v:7553.2-7559.5" - switch $or$ls180.v:7553$2439_Y - attribute \src "ls180.v:7553.6-7553.108" + attribute \src "ls180.v:7616.2-7622.5" + switch $or$ls180.v:7616$2449_Y + attribute \src "ls180.v:7616.6-7616.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -270471,27 +276516,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7560.2-7574.5" + attribute \src "ls180.v:7623.2-7637.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7560.6-7560.43" + attribute \src "ls180.v:7623.6-7623.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7562.3-7566.6" + attribute \src "ls180.v:7625.3-7629.6" switch 1'0 - attribute \src "ls180.v:7564.7-7564.11" + attribute \src "ls180.v:7627.7-7627.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7567.6-7567.10" + attribute \src "ls180.v:7630.6-7630.10" case - attribute \src "ls180.v:7568.3-7573.6" - switch $not$ls180.v:7568$2440_Y - attribute \src "ls180.v:7568.7-7568.47" + attribute \src "ls180.v:7631.3-7636.6" + switch $not$ls180.v:7631$2450_Y + attribute \src "ls180.v:7631.7-7631.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7569$2441_Y - attribute \src "ls180.v:7570.4-7572.7" - switch $eq$ls180.v:7570$2442_Y - attribute \src "ls180.v:7570.8-7570.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7632$2451_Y + attribute \src "ls180.v:7633.4-7635.7" + switch $eq$ls180.v:7633$2452_Y + attribute \src "ls180.v:7633.8-7633.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -270499,60 +276544,60 @@ module \ls180 case end end - attribute \src "ls180.v:7576.2-7583.5" + attribute \src "ls180.v:7639.2-7646.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7576.6-7576.39" + attribute \src "ls180.v:7639.6-7639.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7578.6-7578.10" + attribute \src "ls180.v:7641.6-7641.10" case - attribute \src "ls180.v:7579.3-7582.6" + attribute \src "ls180.v:7642.3-7645.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7579.7-7579.39" + attribute \src "ls180.v:7642.7-7642.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7584.2-7586.5" - switch $and$ls180.v:7584$2445_Y - attribute \src "ls180.v:7584.6-7584.191" + attribute \src "ls180.v:7647.2-7649.5" + switch $and$ls180.v:7647$2455_Y + attribute \src "ls180.v:7647.6-7647.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7585$2446_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7648$2456_Y case end - attribute \src "ls180.v:7587.2-7589.5" + attribute \src "ls180.v:7650.2-7652.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7587.6-7587.58" + attribute \src "ls180.v:7650.6-7650.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7588$2447_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7651$2457_Y case end - attribute \src "ls180.v:7590.2-7598.5" - switch $and$ls180.v:7590$2450_Y - attribute \src "ls180.v:7590.6-7590.191" + attribute \src "ls180.v:7653.2-7661.5" + switch $and$ls180.v:7653$2460_Y + attribute \src "ls180.v:7653.6-7653.191" case 1'1 - attribute \src "ls180.v:7591.3-7593.6" - switch $not$ls180.v:7591$2451_Y - attribute \src "ls180.v:7591.7-7591.62" + attribute \src "ls180.v:7654.3-7656.6" + switch $not$ls180.v:7654$2461_Y + attribute \src "ls180.v:7654.7-7654.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7592$2452_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7655$2462_Y case end - attribute \src "ls180.v:7594.6-7594.10" + attribute \src "ls180.v:7657.6-7657.10" case - attribute \src "ls180.v:7595.3-7597.6" + attribute \src "ls180.v:7658.3-7660.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7595.7-7595.59" + attribute \src "ls180.v:7658.7-7658.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7596$2453_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7659$2463_Y case end end - attribute \src "ls180.v:7599.2-7605.5" - switch $or$ls180.v:7599$2455_Y - attribute \src "ls180.v:7599.6-7599.108" + attribute \src "ls180.v:7662.2-7668.5" + switch $or$ls180.v:7662$2465_Y + attribute \src "ls180.v:7662.6-7662.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -270561,27 +276606,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7606.2-7620.5" + attribute \src "ls180.v:7669.2-7683.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7606.6-7606.43" + attribute \src "ls180.v:7669.6-7669.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7608.3-7612.6" + attribute \src "ls180.v:7671.3-7675.6" switch 1'0 - attribute \src "ls180.v:7610.7-7610.11" + attribute \src "ls180.v:7673.7-7673.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7613.6-7613.10" + attribute \src "ls180.v:7676.6-7676.10" case - attribute \src "ls180.v:7614.3-7619.6" - switch $not$ls180.v:7614$2456_Y - attribute \src "ls180.v:7614.7-7614.47" + attribute \src "ls180.v:7677.3-7682.6" + switch $not$ls180.v:7677$2466_Y + attribute \src "ls180.v:7677.7-7677.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7615$2457_Y - attribute \src "ls180.v:7616.4-7618.7" - switch $eq$ls180.v:7616$2458_Y - attribute \src "ls180.v:7616.8-7616.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7678$2467_Y + attribute \src "ls180.v:7679.4-7681.7" + switch $eq$ls180.v:7679$2468_Y + attribute \src "ls180.v:7679.8-7679.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -270589,60 +276634,60 @@ module \ls180 case end end - attribute \src "ls180.v:7622.2-7629.5" + attribute \src "ls180.v:7685.2-7692.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7622.6-7622.39" + attribute \src "ls180.v:7685.6-7685.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7624.6-7624.10" + attribute \src "ls180.v:7687.6-7687.10" case - attribute \src "ls180.v:7625.3-7628.6" + attribute \src "ls180.v:7688.3-7691.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7625.7-7625.39" + attribute \src "ls180.v:7688.7-7688.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7630.2-7632.5" - switch $and$ls180.v:7630$2461_Y - attribute \src "ls180.v:7630.6-7630.191" + attribute \src "ls180.v:7693.2-7695.5" + switch $and$ls180.v:7693$2471_Y + attribute \src "ls180.v:7693.6-7693.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7631$2462_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7694$2472_Y case end - attribute \src "ls180.v:7633.2-7635.5" + attribute \src "ls180.v:7696.2-7698.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7633.6-7633.58" + attribute \src "ls180.v:7696.6-7696.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7634$2463_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7697$2473_Y case end - attribute \src "ls180.v:7636.2-7644.5" - switch $and$ls180.v:7636$2466_Y - attribute \src "ls180.v:7636.6-7636.191" + attribute \src "ls180.v:7699.2-7707.5" + switch $and$ls180.v:7699$2476_Y + attribute \src "ls180.v:7699.6-7699.191" case 1'1 - attribute \src "ls180.v:7637.3-7639.6" - switch $not$ls180.v:7637$2467_Y - attribute \src "ls180.v:7637.7-7637.62" + attribute \src "ls180.v:7700.3-7702.6" + switch $not$ls180.v:7700$2477_Y + attribute \src "ls180.v:7700.7-7700.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7638$2468_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7701$2478_Y case end - attribute \src "ls180.v:7640.6-7640.10" + attribute \src "ls180.v:7703.6-7703.10" case - attribute \src "ls180.v:7641.3-7643.6" + attribute \src "ls180.v:7704.3-7706.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7641.7-7641.59" + attribute \src "ls180.v:7704.7-7704.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7642$2469_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7705$2479_Y case end end - attribute \src "ls180.v:7645.2-7651.5" - switch $or$ls180.v:7645$2471_Y - attribute \src "ls180.v:7645.6-7645.108" + attribute \src "ls180.v:7708.2-7714.5" + switch $or$ls180.v:7708$2481_Y + attribute \src "ls180.v:7708.6-7708.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -270651,27 +276696,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7652.2-7666.5" + attribute \src "ls180.v:7715.2-7729.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7652.6-7652.43" + attribute \src "ls180.v:7715.6-7715.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7654.3-7658.6" + attribute \src "ls180.v:7717.3-7721.6" switch 1'0 - attribute \src "ls180.v:7656.7-7656.11" + attribute \src "ls180.v:7719.7-7719.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7659.6-7659.10" + attribute \src "ls180.v:7722.6-7722.10" case - attribute \src "ls180.v:7660.3-7665.6" - switch $not$ls180.v:7660$2472_Y - attribute \src "ls180.v:7660.7-7660.47" + attribute \src "ls180.v:7723.3-7728.6" + switch $not$ls180.v:7723$2482_Y + attribute \src "ls180.v:7723.7-7723.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7661$2473_Y - attribute \src "ls180.v:7662.4-7664.7" - switch $eq$ls180.v:7662$2474_Y - attribute \src "ls180.v:7662.8-7662.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7724$2483_Y + attribute \src "ls180.v:7725.4-7727.7" + switch $eq$ls180.v:7725$2484_Y + attribute \src "ls180.v:7725.8-7725.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -270679,60 +276724,60 @@ module \ls180 case end end - attribute \src "ls180.v:7668.2-7675.5" + attribute \src "ls180.v:7731.2-7738.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7668.6-7668.39" + attribute \src "ls180.v:7731.6-7731.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7670.6-7670.10" + attribute \src "ls180.v:7733.6-7733.10" case - attribute \src "ls180.v:7671.3-7674.6" + attribute \src "ls180.v:7734.3-7737.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7671.7-7671.39" + attribute \src "ls180.v:7734.7-7734.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7676.2-7678.5" - switch $and$ls180.v:7676$2477_Y - attribute \src "ls180.v:7676.6-7676.191" + attribute \src "ls180.v:7739.2-7741.5" + switch $and$ls180.v:7739$2487_Y + attribute \src "ls180.v:7739.6-7739.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2478_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7740$2488_Y case end - attribute \src "ls180.v:7679.2-7681.5" + attribute \src "ls180.v:7742.2-7744.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7679.6-7679.58" + attribute \src "ls180.v:7742.6-7742.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2479_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7743$2489_Y case end - attribute \src "ls180.v:7682.2-7690.5" - switch $and$ls180.v:7682$2482_Y - attribute \src "ls180.v:7682.6-7682.191" + attribute \src "ls180.v:7745.2-7753.5" + switch $and$ls180.v:7745$2492_Y + attribute \src "ls180.v:7745.6-7745.191" case 1'1 - attribute \src "ls180.v:7683.3-7685.6" - switch $not$ls180.v:7683$2483_Y - attribute \src "ls180.v:7683.7-7683.62" + attribute \src "ls180.v:7746.3-7748.6" + switch $not$ls180.v:7746$2493_Y + attribute \src "ls180.v:7746.7-7746.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2484_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7747$2494_Y case end - attribute \src "ls180.v:7686.6-7686.10" + attribute \src "ls180.v:7749.6-7749.10" case - attribute \src "ls180.v:7687.3-7689.6" + attribute \src "ls180.v:7750.3-7752.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7687.7-7687.59" + attribute \src "ls180.v:7750.7-7750.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2485_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7751$2495_Y case end end - attribute \src "ls180.v:7691.2-7697.5" - switch $or$ls180.v:7691$2487_Y - attribute \src "ls180.v:7691.6-7691.108" + attribute \src "ls180.v:7754.2-7760.5" + switch $or$ls180.v:7754$2497_Y + attribute \src "ls180.v:7754.6-7754.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -270741,27 +276786,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7698.2-7712.5" + attribute \src "ls180.v:7761.2-7775.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7698.6-7698.43" + attribute \src "ls180.v:7761.6-7761.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7700.3-7704.6" + attribute \src "ls180.v:7763.3-7767.6" switch 1'0 - attribute \src "ls180.v:7702.7-7702.11" + attribute \src "ls180.v:7765.7-7765.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7705.6-7705.10" + attribute \src "ls180.v:7768.6-7768.10" case - attribute \src "ls180.v:7706.3-7711.6" - switch $not$ls180.v:7706$2488_Y - attribute \src "ls180.v:7706.7-7706.47" + attribute \src "ls180.v:7769.3-7774.6" + switch $not$ls180.v:7769$2498_Y + attribute \src "ls180.v:7769.7-7769.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7707$2489_Y - attribute \src "ls180.v:7708.4-7710.7" - switch $eq$ls180.v:7708$2490_Y - attribute \src "ls180.v:7708.8-7708.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7770$2499_Y + attribute \src "ls180.v:7771.4-7773.7" + switch $eq$ls180.v:7771$2500_Y + attribute \src "ls180.v:7771.8-7771.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -270769,61 +276814,61 @@ module \ls180 case end end - attribute \src "ls180.v:7714.2-7720.5" - switch $not$ls180.v:7714$2491_Y - attribute \src "ls180.v:7714.6-7714.23" + attribute \src "ls180.v:7777.2-7783.5" + switch $not$ls180.v:7777$2501_Y + attribute \src "ls180.v:7777.6-7777.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7716.6-7716.10" + attribute \src "ls180.v:7779.6-7779.10" case - attribute \src "ls180.v:7717.3-7719.6" - switch $not$ls180.v:7717$2492_Y - attribute \src "ls180.v:7717.7-7717.30" + attribute \src "ls180.v:7780.3-7782.6" + switch $not$ls180.v:7780$2502_Y + attribute \src "ls180.v:7780.7-7780.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7718$2493_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7781$2503_Y case end end - attribute \src "ls180.v:7721.2-7727.5" - switch $not$ls180.v:7721$2494_Y - attribute \src "ls180.v:7721.6-7721.23" + attribute \src "ls180.v:7784.2-7790.5" + switch $not$ls180.v:7784$2504_Y + attribute \src "ls180.v:7784.6-7784.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7723.6-7723.10" + attribute \src "ls180.v:7786.6-7786.10" case - attribute \src "ls180.v:7724.3-7726.6" - switch $not$ls180.v:7724$2495_Y - attribute \src "ls180.v:7724.7-7724.30" + attribute \src "ls180.v:7787.3-7789.6" + switch $not$ls180.v:7787$2505_Y + attribute \src "ls180.v:7787.7-7787.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7725$2496_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7788$2506_Y case end end - attribute \src "ls180.v:7728.2-7783.5" + attribute \src "ls180.v:7791.2-7846.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7728.6-7728.30" + attribute \src "ls180.v:7791.6-7791.30" case 1'1 - attribute \src "ls180.v:7729.3-7782.10" + attribute \src "ls180.v:7792.3-7845.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7731.5-7741.8" + attribute \src "ls180.v:7794.5-7804.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7731.9-7731.41" + attribute \src "ls180.v:7794.9-7794.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7733.9-7733.13" + attribute \src "ls180.v:7796.9-7796.13" case - attribute \src "ls180.v:7734.6-7740.9" + attribute \src "ls180.v:7797.6-7803.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7734.10-7734.42" + attribute \src "ls180.v:7797.10-7797.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7736.10-7736.14" + attribute \src "ls180.v:7799.10-7799.14" case - attribute \src "ls180.v:7737.7-7739.10" + attribute \src "ls180.v:7800.7-7802.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7737.11-7737.43" + attribute \src "ls180.v:7800.11-7800.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -270832,23 +276877,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7744.5-7754.8" + attribute \src "ls180.v:7807.5-7817.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7744.9-7744.41" + attribute \src "ls180.v:7807.9-7807.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7746.9-7746.13" + attribute \src "ls180.v:7809.9-7809.13" case - attribute \src "ls180.v:7747.6-7753.9" + attribute \src "ls180.v:7810.6-7816.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7747.10-7747.42" + attribute \src "ls180.v:7810.10-7810.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7749.10-7749.14" + attribute \src "ls180.v:7812.10-7812.14" case - attribute \src "ls180.v:7750.7-7752.10" + attribute \src "ls180.v:7813.7-7815.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7750.11-7750.43" + attribute \src "ls180.v:7813.11-7813.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -270857,23 +276902,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7757.5-7767.8" + attribute \src "ls180.v:7820.5-7830.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7757.9-7757.41" + attribute \src "ls180.v:7820.9-7820.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7759.9-7759.13" + attribute \src "ls180.v:7822.9-7822.13" case - attribute \src "ls180.v:7760.6-7766.9" + attribute \src "ls180.v:7823.6-7829.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7760.10-7760.42" + attribute \src "ls180.v:7823.10-7823.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7762.10-7762.14" + attribute \src "ls180.v:7825.10-7825.14" case - attribute \src "ls180.v:7763.7-7765.10" + attribute \src "ls180.v:7826.7-7828.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7763.11-7763.43" + attribute \src "ls180.v:7826.11-7826.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -270882,23 +276927,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7770.5-7780.8" + attribute \src "ls180.v:7833.5-7843.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7770.9-7770.41" + attribute \src "ls180.v:7833.9-7833.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7772.9-7772.13" + attribute \src "ls180.v:7835.9-7835.13" case - attribute \src "ls180.v:7773.6-7779.9" + attribute \src "ls180.v:7836.6-7842.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7773.10-7773.42" + attribute \src "ls180.v:7836.10-7836.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7775.10-7775.14" + attribute \src "ls180.v:7838.10-7838.14" case - attribute \src "ls180.v:7776.7-7778.10" + attribute \src "ls180.v:7839.7-7841.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7776.11-7776.43" + attribute \src "ls180.v:7839.11-7839.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -270909,31 +276954,31 @@ module \ls180 end case end - attribute \src "ls180.v:7784.2-7839.5" + attribute \src "ls180.v:7847.2-7902.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7784.6-7784.30" + attribute \src "ls180.v:7847.6-7847.30" case 1'1 - attribute \src "ls180.v:7785.3-7838.10" + attribute \src "ls180.v:7848.3-7901.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7787.5-7797.8" + attribute \src "ls180.v:7850.5-7860.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7787.9-7787.41" + attribute \src "ls180.v:7850.9-7850.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7789.9-7789.13" + attribute \src "ls180.v:7852.9-7852.13" case - attribute \src "ls180.v:7790.6-7796.9" + attribute \src "ls180.v:7853.6-7859.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7790.10-7790.42" + attribute \src "ls180.v:7853.10-7853.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7792.10-7792.14" + attribute \src "ls180.v:7855.10-7855.14" case - attribute \src "ls180.v:7793.7-7795.10" + attribute \src "ls180.v:7856.7-7858.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7793.11-7793.43" + attribute \src "ls180.v:7856.11-7856.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -270942,23 +276987,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7800.5-7810.8" + attribute \src "ls180.v:7863.5-7873.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7800.9-7800.41" + attribute \src "ls180.v:7863.9-7863.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7802.9-7802.13" + attribute \src "ls180.v:7865.9-7865.13" case - attribute \src "ls180.v:7803.6-7809.9" + attribute \src "ls180.v:7866.6-7872.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7803.10-7803.42" + attribute \src "ls180.v:7866.10-7866.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7805.10-7805.14" + attribute \src "ls180.v:7868.10-7868.14" case - attribute \src "ls180.v:7806.7-7808.10" + attribute \src "ls180.v:7869.7-7871.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7806.11-7806.43" + attribute \src "ls180.v:7869.11-7869.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -270967,23 +277012,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7813.5-7823.8" + attribute \src "ls180.v:7876.5-7886.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7813.9-7813.41" + attribute \src "ls180.v:7876.9-7876.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7815.9-7815.13" + attribute \src "ls180.v:7878.9-7878.13" case - attribute \src "ls180.v:7816.6-7822.9" + attribute \src "ls180.v:7879.6-7885.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7816.10-7816.42" + attribute \src "ls180.v:7879.10-7879.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7818.10-7818.14" + attribute \src "ls180.v:7881.10-7881.14" case - attribute \src "ls180.v:7819.7-7821.10" + attribute \src "ls180.v:7882.7-7884.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7819.11-7819.43" + attribute \src "ls180.v:7882.11-7882.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -270992,23 +277037,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7826.5-7836.8" + attribute \src "ls180.v:7889.5-7899.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7826.9-7826.41" + attribute \src "ls180.v:7889.9-7889.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7828.9-7828.13" + attribute \src "ls180.v:7891.9-7891.13" case - attribute \src "ls180.v:7829.6-7835.9" + attribute \src "ls180.v:7892.6-7898.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7829.10-7829.42" + attribute \src "ls180.v:7892.10-7892.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7831.10-7831.14" + attribute \src "ls180.v:7894.10-7894.14" case - attribute \src "ls180.v:7832.7-7834.10" + attribute \src "ls180.v:7895.7-7897.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7832.11-7832.43" + attribute \src "ls180.v:7895.11-7895.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -271019,28 +277064,28 @@ module \ls180 end case end - attribute \src "ls180.v:7848.2-7862.5" + attribute \src "ls180.v:7911.2-7925.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7848.6-7848.30" + attribute \src "ls180.v:7911.6-7911.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7850.3-7854.6" + attribute \src "ls180.v:7913.3-7917.6" switch 1'1 - attribute \src "ls180.v:7850.7-7850.11" + attribute \src "ls180.v:7913.7-7913.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:7855.6-7855.10" + attribute \src "ls180.v:7918.6-7918.10" case - attribute \src "ls180.v:7856.3-7861.6" - switch $not$ls180.v:7856$2500_Y - attribute \src "ls180.v:7856.7-7856.34" + attribute \src "ls180.v:7919.3-7924.6" + switch $not$ls180.v:7919$2510_Y + attribute \src "ls180.v:7919.7-7919.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7857$2501_Y - attribute \src "ls180.v:7858.4-7860.7" - switch $eq$ls180.v:7858$2502_Y - attribute \src "ls180.v:7858.8-7858.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7920$2511_Y + attribute \src "ls180.v:7921.4-7923.7" + switch $eq$ls180.v:7921$2512_Y + attribute \src "ls180.v:7921.8-7921.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -271048,27 +277093,27 @@ module \ls180 case end end - attribute \src "ls180.v:7863.2-7877.5" + attribute \src "ls180.v:7926.2-7940.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7863.6-7863.30" + attribute \src "ls180.v:7926.6-7926.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7865.3-7869.6" + attribute \src "ls180.v:7928.3-7932.6" switch 1'0 - attribute \src "ls180.v:7867.7-7867.11" + attribute \src "ls180.v:7930.7-7930.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7870.6-7870.10" + attribute \src "ls180.v:7933.6-7933.10" case - attribute \src "ls180.v:7871.3-7876.6" - switch $not$ls180.v:7871$2503_Y - attribute \src "ls180.v:7871.7-7871.34" + attribute \src "ls180.v:7934.3-7939.6" + switch $not$ls180.v:7934$2513_Y + attribute \src "ls180.v:7934.7-7934.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7872$2504_Y - attribute \src "ls180.v:7873.4-7875.7" - switch $eq$ls180.v:7873$2505_Y - attribute \src "ls180.v:7873.8-7873.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7935$2514_Y + attribute \src "ls180.v:7936.4-7938.7" + switch $eq$ls180.v:7936$2515_Y + attribute \src "ls180.v:7936.8-7936.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -271076,291 +277121,291 @@ module \ls180 case end end - attribute \src "ls180.v:7884.2-7886.5" - switch $or$ls180.v:7884$2530_Y - attribute \src "ls180.v:7884.6-7884.50" + attribute \src "ls180.v:7947.2-7949.5" + switch $or$ls180.v:7947$2540_Y + attribute \src "ls180.v:7947.6-7947.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:7888.2-7890.5" + attribute \src "ls180.v:7951.2-7953.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7888.6-7888.52" + attribute \src "ls180.v:7951.6-7951.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:7891.2-7894.5" + attribute \src "ls180.v:7954.2-7957.5" switch \main_converter_reset - attribute \src "ls180.v:7891.6-7891.26" + attribute \src "ls180.v:7954.6-7954.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:7895.2-7905.5" + attribute \src "ls180.v:7958.2-7968.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:7895.6-7895.26" + attribute \src "ls180.v:7958.6-7958.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7898.6-7898.10" + attribute \src "ls180.v:7961.6-7961.10" case - attribute \src "ls180.v:7899.3-7901.6" - switch $and$ls180.v:7899$2531_Y - attribute \src "ls180.v:7899.7-7899.50" + attribute \src "ls180.v:7962.3-7964.6" + switch $and$ls180.v:7962$2541_Y + attribute \src "ls180.v:7962.7-7962.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:7902.3-7904.6" - switch $and$ls180.v:7902$2532_Y - attribute \src "ls180.v:7902.7-7902.54" + attribute \src "ls180.v:7965.3-7967.6" + switch $and$ls180.v:7965$2542_Y + attribute \src "ls180.v:7965.7-7965.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:7907.2-7928.5" - switch $and$ls180.v:7907$2536_Y - attribute \src "ls180.v:7907.6-7907.64" + attribute \src "ls180.v:7970.2-7991.5" + switch $and$ls180.v:7970$2546_Y + attribute \src "ls180.v:7970.6-7970.91" case 1'1 - assign $0\main_tx_reg[7:0] \main_sink_payload_data - assign $0\main_tx_bitcount[3:0] 4'0000 - assign $0\main_tx_busy[0:0] 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'0 - attribute \src "ls180.v:7912.6-7912.10" + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:7975.6-7975.10" case - attribute \src "ls180.v:7913.3-7927.6" - switch $and$ls180.v:7913$2537_Y - attribute \src "ls180.v:7913.7-7913.42" + attribute \src "ls180.v:7976.3-7990.6" + switch $and$ls180.v:7976$2547_Y + attribute \src "ls180.v:7976.7-7976.60" case 1'1 - assign $0\main_tx_bitcount[3:0] $add$ls180.v:7914$2538_Y - attribute \src "ls180.v:7915.4-7926.7" - switch $eq$ls180.v:7915$2539_Y - attribute \src "ls180.v:7915.8-7915.34" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7977$2548_Y + attribute \src "ls180.v:7978.4-7989.7" + switch $eq$ls180.v:7978$2549_Y + attribute \src "ls180.v:7978.8-7978.43" case 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - attribute \src "ls180.v:7917.8-7917.12" + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:7980.8-7980.12" case - attribute \src "ls180.v:7918.5-7925.8" - switch $eq$ls180.v:7918$2540_Y - attribute \src "ls180.v:7918.9-7918.35" + attribute \src "ls180.v:7981.5-7988.8" + switch $eq$ls180.v:7981$2550_Y + attribute \src "ls180.v:7981.9-7981.44" case 1'1 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 - assign $0\main_tx_busy[0:0] 1'0 - assign $0\main_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7922.9-7922.13" + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7985.9-7985.13" case - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] \main_tx_reg [0] - assign $0\main_tx_reg[7:0] { 1'0 \main_tx_reg [7:1] } + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } end end case end end - attribute \src "ls180.v:7929.2-7933.5" - switch \main_tx_busy - attribute \src "ls180.v:7929.6-7929.18" + attribute \src "ls180.v:7992.2-7996.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:7992.6-7992.27" case 1'1 - assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } $add$ls180.v:7930$2541_Y - attribute \src "ls180.v:7931.6-7931.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7993$2551_Y + attribute \src "ls180.v:7994.6-7994.10" case - assign { $0\main_uart_clk_txen[0:0] $0\main_phase_accumulator_tx[31:0] } { 1'0 \main_storage } + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:7936.2-7960.5" - switch $not$ls180.v:7936$2542_Y - attribute \src "ls180.v:7936.6-7936.21" + attribute \src "ls180.v:7999.2-8023.5" + switch $not$ls180.v:7999$2552_Y + attribute \src "ls180.v:7999.6-7999.30" case 1'1 - attribute \src "ls180.v:7937.3-7940.6" - switch $and$ls180.v:7937$2544_Y - attribute \src "ls180.v:7937.7-7937.31" + attribute \src "ls180.v:8000.3-8003.6" + switch $and$ls180.v:8000$2554_Y + attribute \src "ls180.v:8000.7-8000.49" case 1'1 - assign $0\main_rx_busy[0:0] 1'1 - assign $0\main_rx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:7941.6-7941.10" + attribute \src "ls180.v:8004.6-8004.10" case - attribute \src "ls180.v:7942.3-7959.6" - switch \main_uart_clk_rxen - attribute \src "ls180.v:7942.7-7942.25" + attribute \src "ls180.v:8005.3-8022.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:8005.7-8005.34" case 1'1 - assign $0\main_rx_bitcount[3:0] $add$ls180.v:7943$2545_Y - attribute \src "ls180.v:7944.4-7958.7" - switch $eq$ls180.v:7944$2546_Y - attribute \src "ls180.v:7944.8-7944.34" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8006$2555_Y + attribute \src "ls180.v:8007.4-8021.7" + switch $eq$ls180.v:8007$2556_Y + attribute \src "ls180.v:8007.8-8007.43" case 1'1 - attribute \src "ls180.v:7945.5-7947.8" - switch \main_rx - attribute \src "ls180.v:7945.9-7945.16" + attribute \src "ls180.v:8008.5-8010.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:8008.9-8008.25" case 1'1 - assign $0\main_rx_busy[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:7948.8-7948.12" + attribute \src "ls180.v:8011.8-8011.12" case - attribute \src "ls180.v:7949.5-7957.8" - switch $eq$ls180.v:7949$2547_Y - attribute \src "ls180.v:7949.9-7949.35" + attribute \src "ls180.v:8012.5-8020.8" + switch $eq$ls180.v:8012$2557_Y + attribute \src "ls180.v:8012.9-8012.44" case 1'1 - assign $0\main_rx_busy[0:0] 1'0 - attribute \src "ls180.v:7951.6-7954.9" - switch \main_rx - attribute \src "ls180.v:7951.10-7951.17" + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8014.6-8017.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8014.10-8014.26" case 1'1 - assign $0\main_source_payload_data[7:0] \main_rx_reg - assign $0\main_source_valid[0:0] 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:7955.9-7955.13" + attribute \src "ls180.v:8018.9-8018.13" case - assign $0\main_rx_reg[7:0] { \main_rx \main_rx_reg [7:1] } + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end end case end end - attribute \src "ls180.v:7961.2-7965.5" - switch \main_rx_busy - attribute \src "ls180.v:7961.6-7961.18" + attribute \src "ls180.v:8024.2-8028.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8024.6-8024.27" case 1'1 - assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } $add$ls180.v:7962$2548_Y - attribute \src "ls180.v:7963.6-7963.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8025$2558_Y + attribute \src "ls180.v:8026.6-8026.10" case - assign { $0\main_uart_clk_rxen[0:0] $0\main_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:7966.2-7968.5" + attribute \src "ls180.v:8029.2-8031.5" switch \main_uart_tx_clear - attribute \src "ls180.v:7966.6-7966.24" + attribute \src "ls180.v:8029.6-8029.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:7970.2-7972.5" - switch $and$ls180.v:7970$2550_Y - attribute \src "ls180.v:7970.6-7970.58" + attribute \src "ls180.v:8033.2-8035.5" + switch $and$ls180.v:8033$2560_Y + attribute \src "ls180.v:8033.6-8033.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:7973.2-7975.5" + attribute \src "ls180.v:8036.2-8038.5" switch \main_uart_rx_clear - attribute \src "ls180.v:7973.6-7973.24" + attribute \src "ls180.v:8036.6-8036.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:7977.2-7979.5" - switch $and$ls180.v:7977$2552_Y - attribute \src "ls180.v:7977.6-7977.58" + attribute \src "ls180.v:8040.2-8042.5" + switch $and$ls180.v:8040$2562_Y + attribute \src "ls180.v:8040.6-8040.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:7980.2-7986.5" + attribute \src "ls180.v:8043.2-8049.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:7980.6-7980.35" + attribute \src "ls180.v:8043.6-8043.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:7982.6-7982.10" + attribute \src "ls180.v:8045.6-8045.10" case - attribute \src "ls180.v:7983.3-7985.6" + attribute \src "ls180.v:8046.3-8048.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:7983.7-7983.27" + attribute \src "ls180.v:8046.7-8046.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:7987.2-7989.5" - switch $and$ls180.v:7987$2555_Y - attribute \src "ls180.v:7987.6-7987.108" + attribute \src "ls180.v:8050.2-8052.5" + switch $and$ls180.v:8050$2565_Y + attribute \src "ls180.v:8050.6-8050.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:7988$2556_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8051$2566_Y case end - attribute \src "ls180.v:7990.2-7992.5" + attribute \src "ls180.v:8053.2-8055.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:7990.6-7990.31" + attribute \src "ls180.v:8053.6-8053.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:7991$2557_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8054$2567_Y case end - attribute \src "ls180.v:7993.2-8001.5" - switch $and$ls180.v:7993$2560_Y - attribute \src "ls180.v:7993.6-7993.108" + attribute \src "ls180.v:8056.2-8064.5" + switch $and$ls180.v:8056$2570_Y + attribute \src "ls180.v:8056.6-8056.108" case 1'1 - attribute \src "ls180.v:7994.3-7996.6" - switch $not$ls180.v:7994$2561_Y - attribute \src "ls180.v:7994.7-7994.35" + attribute \src "ls180.v:8057.3-8059.6" + switch $not$ls180.v:8057$2571_Y + attribute \src "ls180.v:8057.7-8057.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:7995$2562_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8058$2572_Y case end - attribute \src "ls180.v:7997.6-7997.10" + attribute \src "ls180.v:8060.6-8060.10" case - attribute \src "ls180.v:7998.3-8000.6" + attribute \src "ls180.v:8061.3-8063.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:7998.7-7998.32" + attribute \src "ls180.v:8061.7-8061.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:7999$2563_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8062$2573_Y case end end - attribute \src "ls180.v:8002.2-8008.5" + attribute \src "ls180.v:8065.2-8071.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8002.6-8002.35" + attribute \src "ls180.v:8065.6-8065.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8004.6-8004.10" + attribute \src "ls180.v:8067.6-8067.10" case - attribute \src "ls180.v:8005.3-8007.6" + attribute \src "ls180.v:8068.3-8070.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8005.7-8005.27" + attribute \src "ls180.v:8068.7-8068.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8009.2-8011.5" - switch $and$ls180.v:8009$2566_Y - attribute \src "ls180.v:8009.6-8009.108" + attribute \src "ls180.v:8072.2-8074.5" + switch $and$ls180.v:8072$2576_Y + attribute \src "ls180.v:8072.6-8072.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8010$2567_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8073$2577_Y case end - attribute \src "ls180.v:8012.2-8014.5" + attribute \src "ls180.v:8075.2-8077.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8012.6-8012.31" + attribute \src "ls180.v:8075.6-8075.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8013$2568_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8076$2578_Y case end - attribute \src "ls180.v:8015.2-8023.5" - switch $and$ls180.v:8015$2571_Y - attribute \src "ls180.v:8015.6-8015.108" + attribute \src "ls180.v:8078.2-8086.5" + switch $and$ls180.v:8078$2581_Y + attribute \src "ls180.v:8078.6-8078.108" case 1'1 - attribute \src "ls180.v:8016.3-8018.6" - switch $not$ls180.v:8016$2572_Y - attribute \src "ls180.v:8016.7-8016.35" + attribute \src "ls180.v:8079.3-8081.6" + switch $not$ls180.v:8079$2582_Y + attribute \src "ls180.v:8079.7-8079.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8017$2573_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8080$2583_Y case end - attribute \src "ls180.v:8019.6-8019.10" + attribute \src "ls180.v:8082.6-8082.10" case - attribute \src "ls180.v:8020.3-8022.6" + attribute \src "ls180.v:8083.3-8085.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8020.7-8020.32" + attribute \src "ls180.v:8083.7-8083.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8021$2574_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8084$2584_Y case end end - attribute \src "ls180.v:8024.2-8037.5" + attribute \src "ls180.v:8087.2-8100.5" switch \main_uart_reset - attribute \src "ls180.v:8024.6-8024.21" + attribute \src "ls180.v:8087.6-8087.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -271376,208 +277421,276 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8039.2-8046.5" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:8039.6-8039.30" + attribute \src "ls180.v:8102.2-8109.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8102.6-8102.31" case 1'1 - assign $0\spi_master_clk[0:0] \main_spi_master_clk_enable - attribute \src "ls180.v:8041.6-8041.10" + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8104.6-8104.10" case - attribute \src "ls180.v:8042.3-8045.6" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:8042.7-8042.31" + attribute \src "ls180.v:8105.3-8108.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8105.7-8105.32" case 1'1 - assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 - assign $0\spi_master_clk[0:0] 1'0 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8048.2-8058.5" - switch \main_spi_master_mosi_latch - attribute \src "ls180.v:8048.6-8048.32" + attribute \src "ls180.v:8111.2-8121.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8111.6-8111.33" case 1'1 - assign $0\main_spi_master_mosi_data[7:0] \main_spi_master_mosi - assign $0\main_spi_master_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8051.6-8051.10" + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8114.6-8114.10" case - attribute \src "ls180.v:8052.3-8057.6" - switch \main_spi_master_clk_fall - attribute \src "ls180.v:8052.7-8052.31" + attribute \src "ls180.v:8115.3-8120.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8115.7-8115.32" case 1'1 - assign $0\main_spi_master_mosi_sel[2:0] $sub$ls180.v:8056$2579_Y - attribute \src "ls180.v:8053.4-8055.7" - switch \main_spi_master_cs_enable - attribute \src "ls180.v:8053.8-8053.33" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8119$2589_Y + attribute \src "ls180.v:8116.4-8118.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8116.8-8116.34" case 1'1 - assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case end case end end - attribute \src "ls180.v:8059.2-8065.5" - switch \main_spi_master_clk_rise - attribute \src "ls180.v:8059.6-8059.30" + attribute \src "ls180.v:8122.2-8128.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8122.6-8122.31" case 1'1 - attribute \src "ls180.v:8060.3-8064.6" - switch \main_spi_master_loopback - attribute \src "ls180.v:8060.7-8060.31" + attribute \src "ls180.v:8123.3-8127.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8123.7-8123.31" case 1'1 - assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_mosi } - attribute \src "ls180.v:8062.7-8062.11" + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8125.7-8125.11" case - assign $0\main_spi_master_miso_data[7:0] { \main_spi_master_miso_data [6:0] \spi_master_miso } + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8066.2-8068.5" - switch \main_spi_master_miso_latch - attribute \src "ls180.v:8066.6-8066.32" + attribute \src "ls180.v:8129.2-8131.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8129.6-8129.33" case 1'1 - assign $0\main_spi_master_miso[7:0] \main_spi_master_miso_data + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8070.2-8072.5" - switch \main_spi_master_count_spimaster0_next_value_ce - attribute \src "ls180.v:8070.6-8070.52" + attribute \src "ls180.v:8133.2-8135.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8133.6-8133.53" case 1'1 - assign $0\main_spi_master_count[2:0] \main_spi_master_count_spimaster0_next_value + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8073.2-8086.5" + attribute \src "ls180.v:8137.2-8144.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8137.6-8137.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8139.6-8139.10" + case + attribute \src "ls180.v:8140.3-8143.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8140.7-8140.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8146.2-8156.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8146.6-8146.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8149.6-8149.10" + case + attribute \src "ls180.v:8150.3-8155.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8150.7-8150.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8154$2594_Y + attribute \src "ls180.v:8151.4-8153.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8151.8-8151.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8157.2-8163.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8157.6-8157.29" + case 1'1 + attribute \src "ls180.v:8158.3-8162.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8158.7-8158.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8160.7-8160.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8164.2-8166.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8164.6-8164.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8168.2-8170.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8168.6-8168.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8171.2-8184.5" switch \main_pwm0_enable - attribute \src "ls180.v:8073.6-8073.22" + attribute \src "ls180.v:8171.6-8171.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8074$2580_Y - attribute \src "ls180.v:8075.3-8079.6" - switch $lt$ls180.v:8075$2581_Y - attribute \src "ls180.v:8075.7-8075.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8172$2595_Y + attribute \src "ls180.v:8173.3-8177.6" + switch $lt$ls180.v:8173$2596_Y + attribute \src "ls180.v:8173.7-8173.44" case 1'1 - assign $0\pwm0[0:0] 1'1 - attribute \src "ls180.v:8077.7-8077.11" + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8175.7-8175.11" case - assign $0\pwm0[0:0] 1'0 + assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8080.3-8082.6" - switch $ge$ls180.v:8080$2583_Y - attribute \src "ls180.v:8080.7-8080.55" + attribute \src "ls180.v:8178.3-8180.6" + switch $ge$ls180.v:8178$2598_Y + attribute \src "ls180.v:8178.7-8178.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8083.6-8083.10" + attribute \src "ls180.v:8181.6-8181.10" case assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm0[0:0] 1'0 + assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8087.2-8100.5" + attribute \src "ls180.v:8185.2-8198.5" switch \main_pwm1_enable - attribute \src "ls180.v:8087.6-8087.22" + attribute \src "ls180.v:8185.6-8185.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8088$2584_Y - attribute \src "ls180.v:8089.3-8093.6" - switch $lt$ls180.v:8089$2585_Y - attribute \src "ls180.v:8089.7-8089.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8186$2599_Y + attribute \src "ls180.v:8187.3-8191.6" + switch $lt$ls180.v:8187$2600_Y + attribute \src "ls180.v:8187.7-8187.44" case 1'1 - assign $0\pwm1[0:0] 1'1 - attribute \src "ls180.v:8091.7-8091.11" + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8189.7-8189.11" case - assign $0\pwm1[0:0] 1'0 + assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8094.3-8096.6" - switch $ge$ls180.v:8094$2587_Y - attribute \src "ls180.v:8094.7-8094.55" + attribute \src "ls180.v:8192.3-8194.6" + switch $ge$ls180.v:8192$2602_Y + attribute \src "ls180.v:8192.7-8192.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8097.6-8097.10" + attribute \src "ls180.v:8195.6-8195.10" case assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm1[0:0] 1'0 + assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8101.2-8103.5" - switch $not$ls180.v:8101$2588_Y - attribute \src "ls180.v:8101.6-8101.32" + attribute \src "ls180.v:8199.2-8201.5" + switch $not$ls180.v:8199$2603_Y + attribute \src "ls180.v:8199.6-8199.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8102$2589_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8200$2604_Y case end - attribute \src "ls180.v:8107.2-8109.5" + attribute \src "ls180.v:8205.2-8207.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8107.6-8107.57" + attribute \src "ls180.v:8205.6-8205.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8111.2-8113.5" + attribute \src "ls180.v:8209.2-8211.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8111.6-8111.57" + attribute \src "ls180.v:8209.6-8209.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8114.2-8116.5" + attribute \src "ls180.v:8212.2-8214.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8114.6-8114.40" + attribute \src "ls180.v:8212.6-8212.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8115$2590_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8213$2605_Y case end - attribute \src "ls180.v:8117.2-8119.5" + attribute \src "ls180.v:8215.2-8217.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8117.6-8117.49" + attribute \src "ls180.v:8215.6-8215.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8120.2-8127.5" + attribute \src "ls180.v:8218.2-8225.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8120.6-8120.46" + attribute \src "ls180.v:8218.6-8218.46" case 1'1 - attribute \src "ls180.v:8121.3-8126.6" - switch $or$ls180.v:8121$2592_Y - attribute \src "ls180.v:8121.7-8121.98" + attribute \src "ls180.v:8219.3-8224.6" + switch $or$ls180.v:8219$2607_Y + attribute \src "ls180.v:8219.7-8219.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8124.7-8124.11" + attribute \src "ls180.v:8222.7-8222.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8125$2593_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8223$2608_Y end case end - attribute \src "ls180.v:8128.2-8141.5" - switch $and$ls180.v:8128$2594_Y - attribute \src "ls180.v:8128.6-8128.97" + attribute \src "ls180.v:8226.2-8239.5" + switch $and$ls180.v:8226$2609_Y + attribute \src "ls180.v:8226.6-8226.97" case 1'1 - attribute \src "ls180.v:8129.3-8135.6" - switch $and$ls180.v:8129$2595_Y - attribute \src "ls180.v:8129.7-8129.94" + attribute \src "ls180.v:8227.3-8233.6" + switch $and$ls180.v:8227$2610_Y + attribute \src "ls180.v:8227.7-8227.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8132.7-8132.11" + attribute \src "ls180.v:8230.7-8230.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8136.6-8136.10" + attribute \src "ls180.v:8234.6-8234.10" case - attribute \src "ls180.v:8137.3-8140.6" - switch $and$ls180.v:8137$2596_Y - attribute \src "ls180.v:8137.7-8137.94" + attribute \src "ls180.v:8235.3-8238.6" + switch $and$ls180.v:8235$2611_Y + attribute \src "ls180.v:8235.7-8235.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8138$2597_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8139$2598_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8236$2612_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8237$2613_Y case end end - attribute \src "ls180.v:8142.2-8169.5" + attribute \src "ls180.v:8240.2-8267.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8142.6-8142.46" + attribute \src "ls180.v:8240.6-8240.46" case 1'1 - attribute \src "ls180.v:8143.3-8168.10" + attribute \src "ls180.v:8241.3-8266.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -271607,16 +277720,16 @@ module \ls180 end case end - attribute \src "ls180.v:8170.2-8172.5" + attribute \src "ls180.v:8268.2-8270.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8170.6-8170.46" + attribute \src "ls180.v:8268.6-8268.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8171$2599_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8269$2614_Y case end - attribute \src "ls180.v:8173.2-8178.5" - switch $or$ls180.v:8173$2601_Y - attribute \src "ls180.v:8173.6-8173.88" + attribute \src "ls180.v:8271.2-8276.5" + switch $or$ls180.v:8271$2616_Y + attribute \src "ls180.v:8271.6-8271.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -271624,9 +277737,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8179.2-8184.5" + attribute \src "ls180.v:8277.2-8282.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8179.6-8179.32" + attribute \src "ls180.v:8277.6-8277.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -271634,88 +277747,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8186.2-8188.5" + attribute \src "ls180.v:8284.2-8286.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8186.6-8186.58" + attribute \src "ls180.v:8284.6-8284.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8189.2-8191.5" + attribute \src "ls180.v:8287.2-8289.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8189.6-8189.60" + attribute \src "ls180.v:8287.6-8287.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8192.2-8194.5" + attribute \src "ls180.v:8290.2-8292.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8192.6-8192.63" + attribute \src "ls180.v:8290.6-8290.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8195.2-8197.5" + attribute \src "ls180.v:8293.2-8295.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8195.6-8195.41" + attribute \src "ls180.v:8293.6-8293.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8196$2602_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8294$2617_Y case end - attribute \src "ls180.v:8198.2-8200.5" + attribute \src "ls180.v:8296.2-8298.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8198.6-8198.50" + attribute \src "ls180.v:8296.6-8296.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8201.2-8208.5" + attribute \src "ls180.v:8299.2-8306.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8201.6-8201.47" + attribute \src "ls180.v:8299.6-8299.47" case 1'1 - attribute \src "ls180.v:8202.3-8207.6" - switch $or$ls180.v:8202$2604_Y - attribute \src "ls180.v:8202.7-8202.100" + attribute \src "ls180.v:8300.3-8305.6" + switch $or$ls180.v:8300$2619_Y + attribute \src "ls180.v:8300.7-8300.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8205.7-8205.11" + attribute \src "ls180.v:8303.7-8303.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8206$2605_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8304$2620_Y end case end - attribute \src "ls180.v:8209.2-8222.5" - switch $and$ls180.v:8209$2606_Y - attribute \src "ls180.v:8209.6-8209.99" + attribute \src "ls180.v:8307.2-8320.5" + switch $and$ls180.v:8307$2621_Y + attribute \src "ls180.v:8307.6-8307.99" case 1'1 - attribute \src "ls180.v:8210.3-8216.6" - switch $and$ls180.v:8210$2607_Y - attribute \src "ls180.v:8210.7-8210.96" + attribute \src "ls180.v:8308.3-8314.6" + switch $and$ls180.v:8308$2622_Y + attribute \src "ls180.v:8308.7-8308.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8213.7-8213.11" + attribute \src "ls180.v:8311.7-8311.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8217.6-8217.10" + attribute \src "ls180.v:8315.6-8315.10" case - attribute \src "ls180.v:8218.3-8221.6" - switch $and$ls180.v:8218$2608_Y - attribute \src "ls180.v:8218.7-8218.96" + attribute \src "ls180.v:8316.3-8319.6" + switch $and$ls180.v:8316$2623_Y + attribute \src "ls180.v:8316.7-8316.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8219$2609_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8220$2610_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8317$2624_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8318$2625_Y case end end - attribute \src "ls180.v:8223.2-8250.5" + attribute \src "ls180.v:8321.2-8348.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8223.6-8223.47" + attribute \src "ls180.v:8321.6-8321.47" case 1'1 - attribute \src "ls180.v:8224.3-8249.10" + attribute \src "ls180.v:8322.3-8347.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -271745,16 +277858,16 @@ module \ls180 end case end - attribute \src "ls180.v:8251.2-8253.5" + attribute \src "ls180.v:8349.2-8351.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8251.6-8251.47" + attribute \src "ls180.v:8349.6-8349.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8252$2611_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8350$2626_Y case end - attribute \src "ls180.v:8254.2-8259.5" - switch $or$ls180.v:8254$2613_Y - attribute \src "ls180.v:8254.6-8254.90" + attribute \src "ls180.v:8352.2-8357.5" + switch $or$ls180.v:8352$2628_Y + attribute \src "ls180.v:8352.6-8352.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -271762,9 +277875,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8260.2-8265.5" + attribute \src "ls180.v:8358.2-8363.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8260.6-8260.33" + attribute \src "ls180.v:8358.6-8358.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -271772,81 +277885,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8267.2-8269.5" + attribute \src "ls180.v:8365.2-8367.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8267.6-8267.63" + attribute \src "ls180.v:8365.6-8365.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8271.2-8273.5" + attribute \src "ls180.v:8369.2-8371.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8271.6-8271.52" + attribute \src "ls180.v:8369.6-8369.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8274.2-8276.5" + attribute \src "ls180.v:8372.2-8374.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8274.6-8274.42" + attribute \src "ls180.v:8372.6-8372.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8275$2614_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8373$2629_Y case end - attribute \src "ls180.v:8277.2-8279.5" + attribute \src "ls180.v:8375.2-8377.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8277.6-8277.51" + attribute \src "ls180.v:8375.6-8375.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8280.2-8287.5" + attribute \src "ls180.v:8378.2-8385.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8280.6-8280.48" + attribute \src "ls180.v:8378.6-8378.48" case 1'1 - attribute \src "ls180.v:8281.3-8286.6" - switch $or$ls180.v:8281$2616_Y - attribute \src "ls180.v:8281.7-8281.102" + attribute \src "ls180.v:8379.3-8384.6" + switch $or$ls180.v:8379$2631_Y + attribute \src "ls180.v:8379.7-8379.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8284.7-8284.11" + attribute \src "ls180.v:8382.7-8382.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8285$2617_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8383$2632_Y end case end - attribute \src "ls180.v:8288.2-8301.5" - switch $and$ls180.v:8288$2618_Y - attribute \src "ls180.v:8288.6-8288.101" + attribute \src "ls180.v:8386.2-8399.5" + switch $and$ls180.v:8386$2633_Y + attribute \src "ls180.v:8386.6-8386.101" case 1'1 - attribute \src "ls180.v:8289.3-8295.6" - switch $and$ls180.v:8289$2619_Y - attribute \src "ls180.v:8289.7-8289.98" + attribute \src "ls180.v:8387.3-8393.6" + switch $and$ls180.v:8387$2634_Y + attribute \src "ls180.v:8387.7-8387.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8292.7-8292.11" + attribute \src "ls180.v:8390.7-8390.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8296.6-8296.10" + attribute \src "ls180.v:8394.6-8394.10" case - attribute \src "ls180.v:8297.3-8300.6" - switch $and$ls180.v:8297$2620_Y - attribute \src "ls180.v:8297.7-8297.98" + attribute \src "ls180.v:8395.3-8398.6" + switch $and$ls180.v:8395$2635_Y + attribute \src "ls180.v:8395.7-8395.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8298$2621_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8299$2622_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8396$2636_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8397$2637_Y case end end - attribute \src "ls180.v:8302.2-8311.5" + attribute \src "ls180.v:8400.2-8409.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8302.6-8302.48" + attribute \src "ls180.v:8400.6-8400.48" case 1'1 - attribute \src "ls180.v:8303.3-8310.10" + attribute \src "ls180.v:8401.3-8408.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -271858,16 +277971,16 @@ module \ls180 end case end - attribute \src "ls180.v:8312.2-8314.5" + attribute \src "ls180.v:8410.2-8412.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8312.6-8312.48" + attribute \src "ls180.v:8410.6-8410.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8313$2623_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8411$2638_Y case end - attribute \src "ls180.v:8315.2-8320.5" - switch $or$ls180.v:8315$2625_Y - attribute \src "ls180.v:8315.6-8315.92" + attribute \src "ls180.v:8413.2-8418.5" + switch $or$ls180.v:8413$2640_Y + attribute \src "ls180.v:8413.6-8413.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -271875,9 +277988,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8321.2-8326.5" + attribute \src "ls180.v:8419.2-8424.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8321.6-8321.34" + attribute \src "ls180.v:8419.6-8419.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -271885,434 +277998,434 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8328.2-8330.5" + attribute \src "ls180.v:8426.2-8428.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8328.6-8328.60" + attribute \src "ls180.v:8426.6-8426.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8331.2-8333.5" + attribute \src "ls180.v:8429.2-8431.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8331.6-8331.62" + attribute \src "ls180.v:8429.6-8429.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8334.2-8336.5" + attribute \src "ls180.v:8432.2-8434.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8334.6-8334.66" + attribute \src "ls180.v:8432.6-8432.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8337.2-8343.5" + attribute \src "ls180.v:8435.2-8441.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8337.6-8337.35" + attribute \src "ls180.v:8435.6-8435.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8339.6-8339.10" + attribute \src "ls180.v:8437.6-8437.10" case - attribute \src "ls180.v:8340.3-8342.6" + attribute \src "ls180.v:8438.3-8440.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8340.7-8340.39" + attribute \src "ls180.v:8438.7-8438.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8344.2-8350.5" + attribute \src "ls180.v:8442.2-8448.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8344.6-8344.41" + attribute \src "ls180.v:8442.6-8442.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8346.6-8346.10" + attribute \src "ls180.v:8444.6-8444.10" case - attribute \src "ls180.v:8347.3-8349.6" + attribute \src "ls180.v:8445.3-8447.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8347.7-8347.45" + attribute \src "ls180.v:8445.7-8445.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8351.2-8357.5" + attribute \src "ls180.v:8449.2-8455.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8351.6-8351.41" + attribute \src "ls180.v:8449.6-8449.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8353.6-8353.10" + attribute \src "ls180.v:8451.6-8451.10" case - attribute \src "ls180.v:8354.3-8356.6" + attribute \src "ls180.v:8452.3-8454.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8354.7-8354.45" + attribute \src "ls180.v:8452.7-8452.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8358.2-8364.5" + attribute \src "ls180.v:8456.2-8462.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8358.6-8358.41" + attribute \src "ls180.v:8456.6-8456.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8360.6-8360.10" + attribute \src "ls180.v:8458.6-8458.10" case - attribute \src "ls180.v:8361.3-8363.6" + attribute \src "ls180.v:8459.3-8461.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8361.7-8361.45" + attribute \src "ls180.v:8459.7-8459.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8365.2-8371.5" + attribute \src "ls180.v:8463.2-8469.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8365.6-8365.41" + attribute \src "ls180.v:8463.6-8463.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8367.6-8367.10" + attribute \src "ls180.v:8465.6-8465.10" case - attribute \src "ls180.v:8368.3-8370.6" + attribute \src "ls180.v:8466.3-8468.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8368.7-8368.45" + attribute \src "ls180.v:8466.7-8466.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8373.2-8375.5" + attribute \src "ls180.v:8471.2-8473.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8373.6-8373.82" + attribute \src "ls180.v:8471.6-8471.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8376.2-8378.5" + attribute \src "ls180.v:8474.2-8476.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8376.6-8376.82" + attribute \src "ls180.v:8474.6-8474.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8379.2-8381.5" + attribute \src "ls180.v:8477.2-8479.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8379.6-8379.82" + attribute \src "ls180.v:8477.6-8477.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8382.2-8384.5" + attribute \src "ls180.v:8480.2-8482.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8382.6-8382.82" + attribute \src "ls180.v:8480.6-8480.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8385.2-8387.5" + attribute \src "ls180.v:8483.2-8485.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8385.6-8385.78" + attribute \src "ls180.v:8483.6-8483.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8388.2-8390.5" - switch $and$ls180.v:8388$2626_Y - attribute \src "ls180.v:8388.6-8388.83" + attribute \src "ls180.v:8486.2-8488.5" + switch $and$ls180.v:8486$2641_Y + attribute \src "ls180.v:8486.6-8486.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8391.2-8393.5" - switch $and$ls180.v:8391$2627_Y - attribute \src "ls180.v:8391.6-8391.83" + attribute \src "ls180.v:8489.2-8491.5" + switch $and$ls180.v:8489$2642_Y + attribute \src "ls180.v:8489.6-8489.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8394.2-8396.5" - switch $and$ls180.v:8394$2628_Y - attribute \src "ls180.v:8394.6-8394.83" + attribute \src "ls180.v:8492.2-8494.5" + switch $and$ls180.v:8492$2643_Y + attribute \src "ls180.v:8492.6-8492.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8397.2-8399.5" - switch $and$ls180.v:8397$2629_Y - attribute \src "ls180.v:8397.6-8397.83" + attribute \src "ls180.v:8495.2-8497.5" + switch $and$ls180.v:8495$2644_Y + attribute \src "ls180.v:8495.6-8495.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8400.2-8404.5" - switch $and$ls180.v:8400$2630_Y - attribute \src "ls180.v:8400.6-8400.83" + attribute \src "ls180.v:8498.2-8502.5" + switch $and$ls180.v:8498$2645_Y + attribute \src "ls180.v:8498.6-8498.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8405.2-8409.5" - switch $and$ls180.v:8405$2631_Y - attribute \src "ls180.v:8405.6-8405.83" + attribute \src "ls180.v:8503.2-8507.5" + switch $and$ls180.v:8503$2646_Y + attribute \src "ls180.v:8503.6-8503.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8410.2-8414.5" - switch $and$ls180.v:8410$2632_Y - attribute \src "ls180.v:8410.6-8410.83" + attribute \src "ls180.v:8508.2-8512.5" + switch $and$ls180.v:8508$2647_Y + attribute \src "ls180.v:8508.6-8508.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8415.2-8419.5" - switch $and$ls180.v:8415$2633_Y - attribute \src "ls180.v:8415.6-8415.83" + attribute \src "ls180.v:8513.2-8517.5" + switch $and$ls180.v:8513$2648_Y + attribute \src "ls180.v:8513.6-8513.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8420.2-8428.5" - switch $and$ls180.v:8420$2634_Y - attribute \src "ls180.v:8420.6-8420.83" + attribute \src "ls180.v:8518.2-8526.5" + switch $and$ls180.v:8518$2649_Y + attribute \src "ls180.v:8518.6-8518.83" case 1'1 - attribute \src "ls180.v:8421.3-8427.6" + attribute \src "ls180.v:8519.3-8525.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8421.7-8421.42" + attribute \src "ls180.v:8519.7-8519.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8423.7-8423.11" + attribute \src "ls180.v:8521.7-8521.11" case - attribute \src "ls180.v:8424.4-8426.7" - switch $ne$ls180.v:8424$2635_Y - attribute \src "ls180.v:8424.8-8424.48" + attribute \src "ls180.v:8522.4-8524.7" + switch $ne$ls180.v:8522$2650_Y + attribute \src "ls180.v:8522.8-8522.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8425$2636_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8523$2651_Y case end end case end - attribute \src "ls180.v:8429.2-8435.5" + attribute \src "ls180.v:8527.2-8533.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8429.6-8429.40" + attribute \src "ls180.v:8527.6-8527.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8431.6-8431.10" + attribute \src "ls180.v:8529.6-8529.10" case - attribute \src "ls180.v:8432.3-8434.6" + attribute \src "ls180.v:8530.3-8532.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8432.7-8432.44" + attribute \src "ls180.v:8530.7-8530.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8436.2-8442.5" + attribute \src "ls180.v:8534.2-8540.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8436.6-8436.40" + attribute \src "ls180.v:8534.6-8534.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8438.6-8438.10" + attribute \src "ls180.v:8536.6-8536.10" case - attribute \src "ls180.v:8439.3-8441.6" + attribute \src "ls180.v:8537.3-8539.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8439.7-8439.44" + attribute \src "ls180.v:8537.7-8537.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8443.2-8449.5" + attribute \src "ls180.v:8541.2-8547.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8443.6-8443.40" + attribute \src "ls180.v:8541.6-8541.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8445.6-8445.10" + attribute \src "ls180.v:8543.6-8543.10" case - attribute \src "ls180.v:8446.3-8448.6" + attribute \src "ls180.v:8544.3-8546.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8446.7-8446.44" + attribute \src "ls180.v:8544.7-8544.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8450.2-8456.5" + attribute \src "ls180.v:8548.2-8554.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8450.6-8450.40" + attribute \src "ls180.v:8548.6-8548.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8452.6-8452.10" + attribute \src "ls180.v:8550.6-8550.10" case - attribute \src "ls180.v:8453.3-8455.6" + attribute \src "ls180.v:8551.3-8553.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8453.7-8453.44" + attribute \src "ls180.v:8551.7-8551.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8458.2-8460.5" + attribute \src "ls180.v:8556.2-8558.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8458.6-8458.52" + attribute \src "ls180.v:8556.6-8556.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8461.2-8463.5" + attribute \src "ls180.v:8559.2-8561.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8461.6-8461.53" + attribute \src "ls180.v:8559.6-8559.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8464.2-8466.5" + attribute \src "ls180.v:8562.2-8564.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8464.6-8464.53" + attribute \src "ls180.v:8562.6-8562.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8467.2-8469.5" + attribute \src "ls180.v:8565.2-8567.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8467.6-8467.54" + attribute \src "ls180.v:8565.6-8565.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8470.2-8472.5" + attribute \src "ls180.v:8568.2-8570.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8470.6-8470.53" + attribute \src "ls180.v:8568.6-8568.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8473.2-8475.5" + attribute \src "ls180.v:8571.2-8573.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8473.6-8473.55" + attribute \src "ls180.v:8571.6-8571.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8476.2-8478.5" + attribute \src "ls180.v:8574.2-8576.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8476.6-8476.54" + attribute \src "ls180.v:8574.6-8574.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8479.2-8481.5" + attribute \src "ls180.v:8577.2-8579.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8479.6-8479.56" + attribute \src "ls180.v:8577.6-8577.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8482.2-8484.5" + attribute \src "ls180.v:8580.2-8582.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8482.6-8482.63" + attribute \src "ls180.v:8580.6-8580.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8485.2-8487.5" - switch $and$ls180.v:8485$2639_Y - attribute \src "ls180.v:8485.6-8485.120" + attribute \src "ls180.v:8583.2-8585.5" + switch $and$ls180.v:8583$2654_Y + attribute \src "ls180.v:8583.6-8583.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8486$2640_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8584$2655_Y case end - attribute \src "ls180.v:8488.2-8490.5" + attribute \src "ls180.v:8586.2-8588.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8488.6-8488.35" + attribute \src "ls180.v:8586.6-8586.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8489$2641_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8587$2656_Y case end - attribute \src "ls180.v:8491.2-8499.5" - switch $and$ls180.v:8491$2644_Y - attribute \src "ls180.v:8491.6-8491.120" + attribute \src "ls180.v:8589.2-8597.5" + switch $and$ls180.v:8589$2659_Y + attribute \src "ls180.v:8589.6-8589.120" case 1'1 - attribute \src "ls180.v:8492.3-8494.6" - switch $not$ls180.v:8492$2645_Y - attribute \src "ls180.v:8492.7-8492.39" + attribute \src "ls180.v:8590.3-8592.6" + switch $not$ls180.v:8590$2660_Y + attribute \src "ls180.v:8590.7-8590.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8493$2646_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8591$2661_Y case end - attribute \src "ls180.v:8495.6-8495.10" + attribute \src "ls180.v:8593.6-8593.10" case - attribute \src "ls180.v:8496.3-8498.6" + attribute \src "ls180.v:8594.3-8596.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8496.7-8496.36" + attribute \src "ls180.v:8594.7-8594.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8497$2647_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8595$2662_Y case end end - attribute \src "ls180.v:8500.2-8502.5" + attribute \src "ls180.v:8598.2-8600.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8500.6-8500.45" + attribute \src "ls180.v:8598.6-8598.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8503.2-8510.5" + attribute \src "ls180.v:8601.2-8608.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8503.6-8503.42" + attribute \src "ls180.v:8601.6-8601.42" case 1'1 - attribute \src "ls180.v:8504.3-8509.6" - switch $or$ls180.v:8504$2649_Y - attribute \src "ls180.v:8504.7-8504.90" + attribute \src "ls180.v:8602.3-8607.6" + switch $or$ls180.v:8602$2664_Y + attribute \src "ls180.v:8602.7-8602.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8507.7-8507.11" + attribute \src "ls180.v:8605.7-8605.11" case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8508$2650_Y + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8606$2665_Y end case end - attribute \src "ls180.v:8511.2-8524.5" - switch $and$ls180.v:8511$2651_Y - attribute \src "ls180.v:8511.6-8511.89" + attribute \src "ls180.v:8609.2-8622.5" + switch $and$ls180.v:8609$2666_Y + attribute \src "ls180.v:8609.6-8609.89" case 1'1 - attribute \src "ls180.v:8512.3-8518.6" - switch $and$ls180.v:8512$2652_Y - attribute \src "ls180.v:8512.7-8512.86" + attribute \src "ls180.v:8610.3-8616.6" + switch $and$ls180.v:8610$2667_Y + attribute \src "ls180.v:8610.7-8610.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8515.7-8515.11" + attribute \src "ls180.v:8613.7-8613.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8519.6-8519.10" + attribute \src "ls180.v:8617.6-8617.10" case - attribute \src "ls180.v:8520.3-8523.6" - switch $and$ls180.v:8520$2653_Y - attribute \src "ls180.v:8520.7-8520.86" + attribute \src "ls180.v:8618.3-8621.6" + switch $and$ls180.v:8618$2668_Y + attribute \src "ls180.v:8618.7-8618.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8521$2654_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8522$2655_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8619$2669_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8620$2670_Y case end end - attribute \src "ls180.v:8525.2-8540.5" + attribute \src "ls180.v:8623.2-8638.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8525.6-8525.42" + attribute \src "ls180.v:8623.6-8623.42" case 1'1 - attribute \src "ls180.v:8526.3-8539.10" + attribute \src "ls180.v:8624.3-8637.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -272330,221 +278443,153 @@ module \ls180 end case end - attribute \src "ls180.v:8541.2-8543.5" + attribute \src "ls180.v:8639.2-8641.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8541.6-8541.42" + attribute \src "ls180.v:8639.6-8639.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8542$2656_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8640$2671_Y case end - attribute \src "ls180.v:8545.2-8547.5" + attribute \src "ls180.v:8643.2-8645.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8545.6-8545.76" + attribute \src "ls180.v:8643.6-8643.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8548.2-8551.5" + attribute \src "ls180.v:8646.2-8649.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8548.6-8548.46" + attribute \src "ls180.v:8646.6-8646.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8553.2-8555.5" + attribute \src "ls180.v:8651.2-8653.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8553.6-8553.64" + attribute \src "ls180.v:8651.6-8651.64" case 1'1 assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8557.2-8559.5" + attribute \src "ls180.v:8655.2-8657.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8557.6-8557.76" + attribute \src "ls180.v:8655.6-8655.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8560.2-8563.5" + attribute \src "ls180.v:8658.2-8661.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8560.6-8560.32" + attribute \src "ls180.v:8658.6-8658.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8564.2-8570.5" - switch $and$ls180.v:8564$2657_Y - attribute \src "ls180.v:8564.6-8564.89" + attribute \src "ls180.v:8662.2-8668.5" + switch $and$ls180.v:8662$2672_Y + attribute \src "ls180.v:8662.6-8662.89" case 1'1 - attribute \src "ls180.v:8565.3-8569.6" + attribute \src "ls180.v:8663.3-8667.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8565.7-8565.38" + attribute \src "ls180.v:8663.7-8663.38" case 1'1 assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8567.7-8567.11" + attribute \src "ls180.v:8665.7-8665.11" case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8568$2658_Y + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8666$2673_Y end case end - attribute \src "ls180.v:8571.2-8573.5" - switch $and$ls180.v:8571$2661_Y - attribute \src "ls180.v:8571.6-8571.120" + attribute \src "ls180.v:8669.2-8671.5" + switch $and$ls180.v:8669$2676_Y + attribute \src "ls180.v:8669.6-8669.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8572$2662_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8670$2677_Y case end - attribute \src "ls180.v:8574.2-8576.5" + attribute \src "ls180.v:8672.2-8674.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8574.6-8574.35" + attribute \src "ls180.v:8672.6-8672.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8575$2663_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8673$2678_Y case end - attribute \src "ls180.v:8577.2-8585.5" - switch $and$ls180.v:8577$2666_Y - attribute \src "ls180.v:8577.6-8577.120" + attribute \src "ls180.v:8675.2-8683.5" + switch $and$ls180.v:8675$2681_Y + attribute \src "ls180.v:8675.6-8675.120" case 1'1 - attribute \src "ls180.v:8578.3-8580.6" - switch $not$ls180.v:8578$2667_Y - attribute \src "ls180.v:8578.7-8578.39" + attribute \src "ls180.v:8676.3-8678.6" + switch $not$ls180.v:8676$2682_Y + attribute \src "ls180.v:8676.7-8676.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8579$2668_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8677$2683_Y case end - attribute \src "ls180.v:8581.6-8581.10" + attribute \src "ls180.v:8679.6-8679.10" case - attribute \src "ls180.v:8582.3-8584.6" + attribute \src "ls180.v:8680.3-8682.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8582.7-8582.36" + attribute \src "ls180.v:8680.7-8680.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8583$2669_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8681$2684_Y case end end - attribute \src "ls180.v:8587.2-8594.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8587.6-8587.26" - case 1'1 - assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable - attribute \src "ls180.v:8589.6-8589.10" - case - attribute \src "ls180.v:8590.3-8593.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8590.7-8590.27" - case 1'1 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8596.2-8606.5" - switch \libresocsim_mosi_latch - attribute \src "ls180.v:8596.6-8596.28" - case 1'1 - assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi - assign $0\libresocsim_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8599.6-8599.10" - case - attribute \src "ls180.v:8600.3-8605.6" - switch \libresocsim_clk_fall - attribute \src "ls180.v:8600.7-8600.27" - case 1'1 - assign $0\libresocsim_mosi_sel[2:0] $sub$ls180.v:8604$2674_Y - attribute \src "ls180.v:8601.4-8603.7" - switch \libresocsim_cs_enable - attribute \src "ls180.v:8601.8-8601.29" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8607.2-8613.5" - switch \libresocsim_clk_rise - attribute \src "ls180.v:8607.6-8607.26" - case 1'1 - attribute \src "ls180.v:8608.3-8612.6" - switch \libresocsim_loopback - attribute \src "ls180.v:8608.7-8608.27" - case 1'1 - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8610.7-8610.11" - case - assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8614.2-8616.5" - switch \libresocsim_miso_latch - attribute \src "ls180.v:8614.6-8614.28" - case 1'1 - assign $0\libresocsim_miso[7:0] \libresocsim_miso_data - case - end - attribute \src "ls180.v:8618.2-8620.5" - switch \libresocsim_count_spimaster1_next_value_ce - attribute \src "ls180.v:8618.6-8618.48" - case 1'1 - assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8622.2-8624.5" + attribute \src "ls180.v:8685.2-8687.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8622.6-8622.46" + attribute \src "ls180.v:8685.6-8685.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8625.2-8627.5" + attribute \src "ls180.v:8688.2-8690.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8625.6-8625.44" + attribute \src "ls180.v:8688.6-8688.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8628.2-8630.5" + attribute \src "ls180.v:8691.2-8693.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8628.6-8628.43" + attribute \src "ls180.v:8691.6-8691.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8631.2-8727.9" + attribute \src "ls180.v:8694.2-8790.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8633.4-8649.7" - switch $not$ls180.v:8633$2675_Y - attribute \src "ls180.v:8633.8-8633.29" + attribute \src "ls180.v:8696.4-8712.7" + switch $not$ls180.v:8696$2685_Y + attribute \src "ls180.v:8696.8-8696.29" case 1'1 - attribute \src "ls180.v:8634.5-8648.8" + attribute \src "ls180.v:8697.5-8711.8" switch \builder_request [1] - attribute \src "ls180.v:8634.9-8634.27" + attribute \src "ls180.v:8697.9-8697.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8636.9-8636.13" + attribute \src "ls180.v:8699.9-8699.13" case - attribute \src "ls180.v:8637.6-8647.9" + attribute \src "ls180.v:8700.6-8710.9" switch \builder_request [2] - attribute \src "ls180.v:8637.10-8637.28" + attribute \src "ls180.v:8700.10-8700.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8639.10-8639.14" + attribute \src "ls180.v:8702.10-8702.14" case - attribute \src "ls180.v:8640.7-8646.10" + attribute \src "ls180.v:8703.7-8709.10" switch \builder_request [3] - attribute \src "ls180.v:8640.11-8640.29" + attribute \src "ls180.v:8703.11-8703.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8642.11-8642.15" + attribute \src "ls180.v:8705.11-8705.15" case - attribute \src "ls180.v:8643.8-8645.11" + attribute \src "ls180.v:8706.8-8708.11" switch \builder_request [4] - attribute \src "ls180.v:8643.12-8643.30" + attribute \src "ls180.v:8706.12-8706.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -272556,34 +278601,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:8652.4-8668.7" - switch $not$ls180.v:8652$2676_Y - attribute \src "ls180.v:8652.8-8652.29" + attribute \src "ls180.v:8715.4-8731.7" + switch $not$ls180.v:8715$2686_Y + attribute \src "ls180.v:8715.8-8715.29" case 1'1 - attribute \src "ls180.v:8653.5-8667.8" + attribute \src "ls180.v:8716.5-8730.8" switch \builder_request [2] - attribute \src "ls180.v:8653.9-8653.27" + attribute \src "ls180.v:8716.9-8716.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8655.9-8655.13" + attribute \src "ls180.v:8718.9-8718.13" case - attribute \src "ls180.v:8656.6-8666.9" + attribute \src "ls180.v:8719.6-8729.9" switch \builder_request [3] - attribute \src "ls180.v:8656.10-8656.28" + attribute \src "ls180.v:8719.10-8719.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8658.10-8658.14" + attribute \src "ls180.v:8721.10-8721.14" case - attribute \src "ls180.v:8659.7-8665.10" + attribute \src "ls180.v:8722.7-8728.10" switch \builder_request [4] - attribute \src "ls180.v:8659.11-8659.29" + attribute \src "ls180.v:8722.11-8722.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8661.11-8661.15" + attribute \src "ls180.v:8724.11-8724.15" case - attribute \src "ls180.v:8662.8-8664.11" + attribute \src "ls180.v:8725.8-8727.11" switch \builder_request [0] - attribute \src "ls180.v:8662.12-8662.30" + attribute \src "ls180.v:8725.12-8725.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -272595,34 +278640,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:8671.4-8687.7" - switch $not$ls180.v:8671$2677_Y - attribute \src "ls180.v:8671.8-8671.29" + attribute \src "ls180.v:8734.4-8750.7" + switch $not$ls180.v:8734$2687_Y + attribute \src "ls180.v:8734.8-8734.29" case 1'1 - attribute \src "ls180.v:8672.5-8686.8" + attribute \src "ls180.v:8735.5-8749.8" switch \builder_request [3] - attribute \src "ls180.v:8672.9-8672.27" + attribute \src "ls180.v:8735.9-8735.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8674.9-8674.13" + attribute \src "ls180.v:8737.9-8737.13" case - attribute \src "ls180.v:8675.6-8685.9" + attribute \src "ls180.v:8738.6-8748.9" switch \builder_request [4] - attribute \src "ls180.v:8675.10-8675.28" + attribute \src "ls180.v:8738.10-8738.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8677.10-8677.14" + attribute \src "ls180.v:8740.10-8740.14" case - attribute \src "ls180.v:8678.7-8684.10" + attribute \src "ls180.v:8741.7-8747.10" switch \builder_request [0] - attribute \src "ls180.v:8678.11-8678.29" + attribute \src "ls180.v:8741.11-8741.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8680.11-8680.15" + attribute \src "ls180.v:8743.11-8743.15" case - attribute \src "ls180.v:8681.8-8683.11" + attribute \src "ls180.v:8744.8-8746.11" switch \builder_request [1] - attribute \src "ls180.v:8681.12-8681.30" + attribute \src "ls180.v:8744.12-8744.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -272634,34 +278679,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:8690.4-8706.7" - switch $not$ls180.v:8690$2678_Y - attribute \src "ls180.v:8690.8-8690.29" + attribute \src "ls180.v:8753.4-8769.7" + switch $not$ls180.v:8753$2688_Y + attribute \src "ls180.v:8753.8-8753.29" case 1'1 - attribute \src "ls180.v:8691.5-8705.8" + attribute \src "ls180.v:8754.5-8768.8" switch \builder_request [4] - attribute \src "ls180.v:8691.9-8691.27" + attribute \src "ls180.v:8754.9-8754.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8693.9-8693.13" + attribute \src "ls180.v:8756.9-8756.13" case - attribute \src "ls180.v:8694.6-8704.9" + attribute \src "ls180.v:8757.6-8767.9" switch \builder_request [0] - attribute \src "ls180.v:8694.10-8694.28" + attribute \src "ls180.v:8757.10-8757.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8696.10-8696.14" + attribute \src "ls180.v:8759.10-8759.14" case - attribute \src "ls180.v:8697.7-8703.10" + attribute \src "ls180.v:8760.7-8766.10" switch \builder_request [1] - attribute \src "ls180.v:8697.11-8697.29" + attribute \src "ls180.v:8760.11-8760.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8699.11-8699.15" + attribute \src "ls180.v:8762.11-8762.15" case - attribute \src "ls180.v:8700.8-8702.11" + attribute \src "ls180.v:8763.8-8765.11" switch \builder_request [2] - attribute \src "ls180.v:8700.12-8700.30" + attribute \src "ls180.v:8763.12-8763.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -272673,34 +278718,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:8709.4-8725.7" - switch $not$ls180.v:8709$2679_Y - attribute \src "ls180.v:8709.8-8709.29" + attribute \src "ls180.v:8772.4-8788.7" + switch $not$ls180.v:8772$2689_Y + attribute \src "ls180.v:8772.8-8772.29" case 1'1 - attribute \src "ls180.v:8710.5-8724.8" + attribute \src "ls180.v:8773.5-8787.8" switch \builder_request [0] - attribute \src "ls180.v:8710.9-8710.27" + attribute \src "ls180.v:8773.9-8773.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8712.9-8712.13" + attribute \src "ls180.v:8775.9-8775.13" case - attribute \src "ls180.v:8713.6-8723.9" + attribute \src "ls180.v:8776.6-8786.9" switch \builder_request [1] - attribute \src "ls180.v:8713.10-8713.28" + attribute \src "ls180.v:8776.10-8776.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8715.10-8715.14" + attribute \src "ls180.v:8778.10-8778.14" case - attribute \src "ls180.v:8716.7-8722.10" + attribute \src "ls180.v:8779.7-8785.10" switch \builder_request [2] - attribute \src "ls180.v:8716.11-8716.29" + attribute \src "ls180.v:8779.11-8779.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8718.11-8718.15" + attribute \src "ls180.v:8781.11-8781.15" case - attribute \src "ls180.v:8719.8-8721.11" + attribute \src "ls180.v:8782.8-8784.11" switch \builder_request [3] - attribute \src "ls180.v:8719.12-8719.30" + attribute \src "ls180.v:8782.12-8782.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -272712,26 +278757,26 @@ module \ls180 end case end - attribute \src "ls180.v:8729.2-8735.5" + attribute \src "ls180.v:8792.2-8798.5" switch \builder_wait - attribute \src "ls180.v:8729.6-8729.18" + attribute \src "ls180.v:8792.6-8792.18" case 1'1 - attribute \src "ls180.v:8730.3-8732.6" - switch $not$ls180.v:8730$2680_Y - attribute \src "ls180.v:8730.7-8730.22" + attribute \src "ls180.v:8793.3-8795.6" + switch $not$ls180.v:8793$2690_Y + attribute \src "ls180.v:8793.7-8793.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8731$2681_Y + assign $0\builder_count[19:0] $sub$ls180.v:8794$2691_Y case end - attribute \src "ls180.v:8733.6-8733.10" + attribute \src "ls180.v:8796.6-8796.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:8737.2-8767.5" + attribute \src "ls180.v:8800.2-8830.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:8737.6-8737.26" + attribute \src "ls180.v:8800.6-8800.26" case 1'1 - attribute \src "ls180.v:8738.3-8766.10" + attribute \src "ls180.v:8801.3-8829.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -272764,46 +278809,46 @@ module \ls180 end case end - attribute \src "ls180.v:8768.2-8770.5" + attribute \src "ls180.v:8831.2-8833.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8768.6-8768.32" + attribute \src "ls180.v:8831.6-8831.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:8772.2-8774.5" + attribute \src "ls180.v:8835.2-8837.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8772.6-8772.34" + attribute \src "ls180.v:8835.6-8835.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:8775.2-8777.5" + attribute \src "ls180.v:8838.2-8840.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8775.6-8775.34" + attribute \src "ls180.v:8838.6-8838.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:8778.2-8780.5" + attribute \src "ls180.v:8841.2-8843.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8778.6-8778.34" + attribute \src "ls180.v:8841.6-8841.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:8781.2-8783.5" + attribute \src "ls180.v:8844.2-8846.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8781.6-8781.34" + attribute \src "ls180.v:8844.6-8844.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:8786.2-8807.5" + attribute \src "ls180.v:8849.2-8870.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:8786.6-8786.26" + attribute \src "ls180.v:8849.6-8849.26" case 1'1 - attribute \src "ls180.v:8787.3-8806.10" + attribute \src "ls180.v:8850.3-8869.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -272827,1275 +278872,1305 @@ module \ls180 end case end - attribute \src "ls180.v:8808.2-8810.5" + attribute \src "ls180.v:8871.2-8873.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8808.6-8808.29" + attribute \src "ls180.v:8871.6-8871.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:8811.2-8813.5" + attribute \src "ls180.v:8874.2-8876.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8811.6-8811.29" + attribute \src "ls180.v:8874.6-8874.29" case 1'1 assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:8815.2-8817.5" + attribute \src "ls180.v:8878.2-8880.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8815.6-8815.30" + attribute \src "ls180.v:8878.6-8878.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:8818.2-8820.5" + attribute \src "ls180.v:8881.2-8883.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8818.6-8818.30" + attribute \src "ls180.v:8881.6-8881.30" case 1'1 assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:8823.2-8853.5" + attribute \src "ls180.v:8886.2-8895.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:8823.6-8823.26" + attribute \src "ls180.v:8886.6-8886.26" case 1'1 - attribute \src "ls180.v:8824.3-8852.10" - switch \builder_interface2_bank_bus_adr [3:0] + attribute \src "ls180.v:8887.3-8894.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:8896.2-8898.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:8896.6-8896.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:8901.2-8931.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8901.6-8901.26" + case 1'1 + attribute \src "ls180.v:8902.3-8930.10" + switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_enable0_w } + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width3_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width2_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width1_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_width0_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period3_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period2_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period1_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_period0_w + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w case end case end - attribute \src "ls180.v:8854.2-8856.5" - switch \builder_csrbank2_enable0_re - attribute \src "ls180.v:8854.6-8854.33" + attribute \src "ls180.v:8932.2-8934.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8932.6-8932.33" case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank2_enable0_r + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:8858.2-8860.5" - switch \builder_csrbank2_width3_re - attribute \src "ls180.v:8858.6-8858.32" + attribute \src "ls180.v:8936.2-8938.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8936.6-8936.32" case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank2_width3_r + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:8861.2-8863.5" - switch \builder_csrbank2_width2_re - attribute \src "ls180.v:8861.6-8861.32" + attribute \src "ls180.v:8939.2-8941.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8939.6-8939.32" case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank2_width2_r + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:8864.2-8866.5" - switch \builder_csrbank2_width1_re - attribute \src "ls180.v:8864.6-8864.32" + attribute \src "ls180.v:8942.2-8944.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8942.6-8942.32" case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank2_width1_r + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:8867.2-8869.5" - switch \builder_csrbank2_width0_re - attribute \src "ls180.v:8867.6-8867.32" + attribute \src "ls180.v:8945.2-8947.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8945.6-8945.32" case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank2_width0_r + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:8871.2-8873.5" - switch \builder_csrbank2_period3_re - attribute \src "ls180.v:8871.6-8871.33" + attribute \src "ls180.v:8949.2-8951.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8949.6-8949.33" case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank2_period3_r + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:8874.2-8876.5" - switch \builder_csrbank2_period2_re - attribute \src "ls180.v:8874.6-8874.33" + attribute \src "ls180.v:8952.2-8954.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8952.6-8952.33" case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank2_period2_r + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:8877.2-8879.5" - switch \builder_csrbank2_period1_re - attribute \src "ls180.v:8877.6-8877.33" + attribute \src "ls180.v:8955.2-8957.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8955.6-8955.33" case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank2_period1_r + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:8880.2-8882.5" - switch \builder_csrbank2_period0_re - attribute \src "ls180.v:8880.6-8880.33" + attribute \src "ls180.v:8958.2-8960.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8958.6-8958.33" case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank2_period0_r + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:8885.2-8915.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:8885.6-8885.26" + attribute \src "ls180.v:8963.2-8993.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8963.6-8963.26" case 1'1 - attribute \src "ls180.v:8886.3-8914.10" - switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:8964.3-8992.10" + switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w case end case end - attribute \src "ls180.v:8916.2-8918.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:8916.6-8916.33" + attribute \src "ls180.v:8994.2-8996.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:8994.6-8994.33" case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank3_enable0_r + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:8920.2-8922.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:8920.6-8920.32" + attribute \src "ls180.v:8998.2-9000.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:8998.6-8998.32" case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:8923.2-8925.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:8923.6-8923.32" + attribute \src "ls180.v:9001.2-9003.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:9001.6-9001.32" case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:8926.2-8928.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:8926.6-8926.32" + attribute \src "ls180.v:9004.2-9006.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:9004.6-9004.32" case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:8929.2-8931.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:8929.6-8929.32" + attribute \src "ls180.v:9007.2-9009.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:9007.6-9007.32" case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:8933.2-8935.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:8933.6-8933.33" + attribute \src "ls180.v:9011.2-9013.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:9011.6-9011.33" case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:8936.2-8938.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:8936.6-8936.33" + attribute \src "ls180.v:9014.2-9016.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9014.6-9014.33" case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:8939.2-8941.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:8939.6-8939.33" + attribute \src "ls180.v:9017.2-9019.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9017.6-9017.33" case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:8942.2-8944.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:8942.6-8942.33" + attribute \src "ls180.v:9020.2-9022.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9020.6-9020.33" case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:8947.2-8995.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:8947.6-8947.26" + attribute \src "ls180.v:9025.2-9073.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9025.6-9025.26" case 1'1 - attribute \src "ls180.v:8948.3-8994.10" - switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:9026.3-9072.10" + switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base7_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base6_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base5_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base4_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base3_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base2_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base1_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_base0_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length3_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w attribute \src "ls180.v:0.0-0.0" case 4'1001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length2_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w attribute \src "ls180.v:0.0-0.0" case 4'1010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length1_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w attribute \src "ls180.v:0.0-0.0" case 4'1011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_dma_length0_w + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w attribute \src "ls180.v:0.0-0.0" case 4'1100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_enable0_w } + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } attribute \src "ls180.v:0.0-0.0" case 4'1101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_done_w } + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } attribute \src "ls180.v:0.0-0.0" case 4'1110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_dma_loop0_w } + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } case end case end - attribute \src "ls180.v:8996.2-8998.5" - switch \builder_csrbank4_dma_base7_re - attribute \src "ls180.v:8996.6-8996.35" + attribute \src "ls180.v:9074.2-9076.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9074.6-9074.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank4_dma_base7_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:8999.2-9001.5" - switch \builder_csrbank4_dma_base6_re - attribute \src "ls180.v:8999.6-8999.35" + attribute \src "ls180.v:9077.2-9079.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9077.6-9077.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank4_dma_base6_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9002.2-9004.5" - switch \builder_csrbank4_dma_base5_re - attribute \src "ls180.v:9002.6-9002.35" + attribute \src "ls180.v:9080.2-9082.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9080.6-9080.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank4_dma_base5_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9005.2-9007.5" - switch \builder_csrbank4_dma_base4_re - attribute \src "ls180.v:9005.6-9005.35" + attribute \src "ls180.v:9083.2-9085.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9083.6-9083.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank4_dma_base4_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9008.2-9010.5" - switch \builder_csrbank4_dma_base3_re - attribute \src "ls180.v:9008.6-9008.35" + attribute \src "ls180.v:9086.2-9088.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9086.6-9086.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank4_dma_base3_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9011.2-9013.5" - switch \builder_csrbank4_dma_base2_re - attribute \src "ls180.v:9011.6-9011.35" + attribute \src "ls180.v:9089.2-9091.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9089.6-9089.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank4_dma_base2_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9014.2-9016.5" - switch \builder_csrbank4_dma_base1_re - attribute \src "ls180.v:9014.6-9014.35" + attribute \src "ls180.v:9092.2-9094.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9092.6-9092.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank4_dma_base1_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9017.2-9019.5" - switch \builder_csrbank4_dma_base0_re - attribute \src "ls180.v:9017.6-9017.35" + attribute \src "ls180.v:9095.2-9097.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9095.6-9095.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank4_dma_base0_r + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9021.2-9023.5" - switch \builder_csrbank4_dma_length3_re - attribute \src "ls180.v:9021.6-9021.37" + attribute \src "ls180.v:9099.2-9101.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9099.6-9099.37" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank4_dma_length3_r + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9024.2-9026.5" - switch \builder_csrbank4_dma_length2_re - attribute \src "ls180.v:9024.6-9024.37" + attribute \src "ls180.v:9102.2-9104.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9102.6-9102.37" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank4_dma_length2_r + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9027.2-9029.5" - switch \builder_csrbank4_dma_length1_re - attribute \src "ls180.v:9027.6-9027.37" + attribute \src "ls180.v:9105.2-9107.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9105.6-9105.37" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank4_dma_length1_r + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9030.2-9032.5" - switch \builder_csrbank4_dma_length0_re - attribute \src "ls180.v:9030.6-9030.37" + attribute \src "ls180.v:9108.2-9110.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9108.6-9108.37" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank4_dma_length0_r + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9034.2-9036.5" - switch \builder_csrbank4_dma_enable0_re - attribute \src "ls180.v:9034.6-9034.37" + attribute \src "ls180.v:9112.2-9114.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9112.6-9112.37" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank4_dma_enable0_r + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9038.2-9040.5" - switch \builder_csrbank4_dma_loop0_re - attribute \src "ls180.v:9038.6-9038.35" + attribute \src "ls180.v:9116.2-9118.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9116.6-9116.35" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank4_dma_loop0_r + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9043.2-9145.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9043.6-9043.26" + attribute \src "ls180.v:9121.2-9223.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9121.6-9121.26" case 1'1 - attribute \src "ls180.v:9044.3-9144.10" - switch \builder_interface5_bank_bus_adr [5:0] + attribute \src "ls180.v:9122.3-9222.10" + switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument3_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w attribute \src "ls180.v:0.0-0.0" case 6'000001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument2_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w attribute \src "ls180.v:0.0-0.0" case 6'000010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument1_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w attribute \src "ls180.v:0.0-0.0" case 6'000011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_argument0_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w attribute \src "ls180.v:0.0-0.0" case 6'000100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command3_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w attribute \src "ls180.v:0.0-0.0" case 6'000101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command2_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w attribute \src "ls180.v:0.0-0.0" case 6'000110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command1_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w attribute \src "ls180.v:0.0-0.0" case 6'000111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_command0_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w attribute \src "ls180.v:0.0-0.0" case 6'001000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } attribute \src "ls180.v:0.0-0.0" case 6'001001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response15_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w attribute \src "ls180.v:0.0-0.0" case 6'001010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response14_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w attribute \src "ls180.v:0.0-0.0" case 6'001011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response13_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w attribute \src "ls180.v:0.0-0.0" case 6'001100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response12_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w attribute \src "ls180.v:0.0-0.0" case 6'001101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response11_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w attribute \src "ls180.v:0.0-0.0" case 6'001110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response10_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w attribute \src "ls180.v:0.0-0.0" case 6'001111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response9_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w attribute \src "ls180.v:0.0-0.0" case 6'010000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response8_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w attribute \src "ls180.v:0.0-0.0" case 6'010001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response7_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w attribute \src "ls180.v:0.0-0.0" case 6'010010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response6_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w attribute \src "ls180.v:0.0-0.0" case 6'010011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response5_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w attribute \src "ls180.v:0.0-0.0" case 6'010100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response4_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w attribute \src "ls180.v:0.0-0.0" case 6'010101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response3_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w attribute \src "ls180.v:0.0-0.0" case 6'010110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response2_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w attribute \src "ls180.v:0.0-0.0" case 6'010111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response1_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w attribute \src "ls180.v:0.0-0.0" case 6'011000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_cmd_response0_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w attribute \src "ls180.v:0.0-0.0" case 6'011001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_cmd_event_w } + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } attribute \src "ls180.v:0.0-0.0" case 6'011010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank5_data_event_w } + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } attribute \src "ls180.v:0.0-0.0" case 6'011011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank5_block_length1_w } + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } attribute \src "ls180.v:0.0-0.0" case 6'011100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_length0_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w attribute \src "ls180.v:0.0-0.0" case 6'011101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count3_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w attribute \src "ls180.v:0.0-0.0" case 6'011110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count2_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w attribute \src "ls180.v:0.0-0.0" case 6'011111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count1_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w attribute \src "ls180.v:0.0-0.0" case 6'100000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_block_count0_w + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w case end case end - attribute \src "ls180.v:9146.2-9148.5" - switch \builder_csrbank5_cmd_argument3_re - attribute \src "ls180.v:9146.6-9146.39" + attribute \src "ls180.v:9224.2-9226.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9224.6-9224.39" case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank5_cmd_argument3_r + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9149.2-9151.5" - switch \builder_csrbank5_cmd_argument2_re - attribute \src "ls180.v:9149.6-9149.39" + attribute \src "ls180.v:9227.2-9229.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9227.6-9227.39" case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank5_cmd_argument2_r + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9152.2-9154.5" - switch \builder_csrbank5_cmd_argument1_re - attribute \src "ls180.v:9152.6-9152.39" + attribute \src "ls180.v:9230.2-9232.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9230.6-9230.39" case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank5_cmd_argument1_r + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9155.2-9157.5" - switch \builder_csrbank5_cmd_argument0_re - attribute \src "ls180.v:9155.6-9155.39" + attribute \src "ls180.v:9233.2-9235.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9233.6-9233.39" case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank5_cmd_argument0_r + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9159.2-9161.5" - switch \builder_csrbank5_cmd_command3_re - attribute \src "ls180.v:9159.6-9159.38" + attribute \src "ls180.v:9237.2-9239.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9237.6-9237.38" case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank5_cmd_command3_r + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9162.2-9164.5" - switch \builder_csrbank5_cmd_command2_re - attribute \src "ls180.v:9162.6-9162.38" + attribute \src "ls180.v:9240.2-9242.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9240.6-9240.38" case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank5_cmd_command2_r + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9165.2-9167.5" - switch \builder_csrbank5_cmd_command1_re - attribute \src "ls180.v:9165.6-9165.38" + attribute \src "ls180.v:9243.2-9245.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9243.6-9243.38" case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank5_cmd_command1_r + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9168.2-9170.5" - switch \builder_csrbank5_cmd_command0_re - attribute \src "ls180.v:9168.6-9168.38" + attribute \src "ls180.v:9246.2-9248.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9246.6-9246.38" case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank5_cmd_command0_r + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9172.2-9174.5" - switch \builder_csrbank5_block_length1_re - attribute \src "ls180.v:9172.6-9172.39" + attribute \src "ls180.v:9250.2-9252.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9250.6-9250.39" case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank5_block_length1_r + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9175.2-9177.5" - switch \builder_csrbank5_block_length0_re - attribute \src "ls180.v:9175.6-9175.39" + attribute \src "ls180.v:9253.2-9255.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9253.6-9253.39" case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank5_block_length0_r + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9179.2-9181.5" - switch \builder_csrbank5_block_count3_re - attribute \src "ls180.v:9179.6-9179.38" + attribute \src "ls180.v:9257.2-9259.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9257.6-9257.38" case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank5_block_count3_r + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9182.2-9184.5" - switch \builder_csrbank5_block_count2_re - attribute \src "ls180.v:9182.6-9182.38" + attribute \src "ls180.v:9260.2-9262.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9260.6-9260.38" case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank5_block_count2_r + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9185.2-9187.5" - switch \builder_csrbank5_block_count1_re - attribute \src "ls180.v:9185.6-9185.38" + attribute \src "ls180.v:9263.2-9265.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9263.6-9263.38" case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank5_block_count1_r + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9188.2-9190.5" - switch \builder_csrbank5_block_count0_re - attribute \src "ls180.v:9188.6-9188.38" + attribute \src "ls180.v:9266.2-9268.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9266.6-9266.38" case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank5_block_count0_r + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9193.2-9253.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9193.6-9193.26" + attribute \src "ls180.v:9271.2-9331.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9271.6-9271.26" case 1'1 - attribute \src "ls180.v:9194.3-9252.10" - switch \builder_interface6_bank_bus_adr [4:0] + attribute \src "ls180.v:9272.3-9330.10" + switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base7_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w attribute \src "ls180.v:0.0-0.0" case 5'00001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base6_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w attribute \src "ls180.v:0.0-0.0" case 5'00010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base5_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w attribute \src "ls180.v:0.0-0.0" case 5'00011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base4_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w attribute \src "ls180.v:0.0-0.0" case 5'00100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base3_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w attribute \src "ls180.v:0.0-0.0" case 5'00101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base2_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w attribute \src "ls180.v:0.0-0.0" case 5'00110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base1_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w attribute \src "ls180.v:0.0-0.0" case 5'00111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_base0_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w attribute \src "ls180.v:0.0-0.0" case 5'01000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length3_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w attribute \src "ls180.v:0.0-0.0" case 5'01001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length2_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w attribute \src "ls180.v:0.0-0.0" case 5'01010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length1_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w attribute \src "ls180.v:0.0-0.0" case 5'01011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_length0_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w attribute \src "ls180.v:0.0-0.0" case 5'01100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_enable0_w } + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } attribute \src "ls180.v:0.0-0.0" case 5'01101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_done_w } + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } attribute \src "ls180.v:0.0-0.0" case 5'01110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_dma_loop0_w } + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } attribute \src "ls180.v:0.0-0.0" case 5'01111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset3_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w attribute \src "ls180.v:0.0-0.0" case 5'10000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset2_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w attribute \src "ls180.v:0.0-0.0" case 5'10001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset1_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w attribute \src "ls180.v:0.0-0.0" case 5'10010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_dma_offset0_w + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w case end case end - attribute \src "ls180.v:9254.2-9256.5" - switch \builder_csrbank6_dma_base7_re - attribute \src "ls180.v:9254.6-9254.35" + attribute \src "ls180.v:9332.2-9334.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9332.6-9332.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank6_dma_base7_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9257.2-9259.5" - switch \builder_csrbank6_dma_base6_re - attribute \src "ls180.v:9257.6-9257.35" + attribute \src "ls180.v:9335.2-9337.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9335.6-9335.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank6_dma_base6_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9260.2-9262.5" - switch \builder_csrbank6_dma_base5_re - attribute \src "ls180.v:9260.6-9260.35" + attribute \src "ls180.v:9338.2-9340.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9338.6-9338.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank6_dma_base5_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9263.2-9265.5" - switch \builder_csrbank6_dma_base4_re - attribute \src "ls180.v:9263.6-9263.35" + attribute \src "ls180.v:9341.2-9343.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9341.6-9341.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank6_dma_base4_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9266.2-9268.5" - switch \builder_csrbank6_dma_base3_re - attribute \src "ls180.v:9266.6-9266.35" + attribute \src "ls180.v:9344.2-9346.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9344.6-9344.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank6_dma_base3_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9269.2-9271.5" - switch \builder_csrbank6_dma_base2_re - attribute \src "ls180.v:9269.6-9269.35" + attribute \src "ls180.v:9347.2-9349.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9347.6-9347.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank6_dma_base2_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9272.2-9274.5" - switch \builder_csrbank6_dma_base1_re - attribute \src "ls180.v:9272.6-9272.35" + attribute \src "ls180.v:9350.2-9352.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9350.6-9350.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank6_dma_base1_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9275.2-9277.5" - switch \builder_csrbank6_dma_base0_re - attribute \src "ls180.v:9275.6-9275.35" + attribute \src "ls180.v:9353.2-9355.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9353.6-9353.35" case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank6_dma_base0_r + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9279.2-9281.5" - switch \builder_csrbank6_dma_length3_re - attribute \src "ls180.v:9279.6-9279.37" + attribute \src "ls180.v:9357.2-9359.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9357.6-9357.37" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank6_dma_length3_r + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9282.2-9284.5" - switch \builder_csrbank6_dma_length2_re - attribute \src "ls180.v:9282.6-9282.37" + attribute \src "ls180.v:9360.2-9362.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9360.6-9360.37" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank6_dma_length2_r + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9285.2-9287.5" - switch \builder_csrbank6_dma_length1_re - attribute \src "ls180.v:9285.6-9285.37" + attribute \src "ls180.v:9363.2-9365.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9363.6-9363.37" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank6_dma_length1_r + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9288.2-9290.5" - switch \builder_csrbank6_dma_length0_re - attribute \src "ls180.v:9288.6-9288.37" + attribute \src "ls180.v:9366.2-9368.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9366.6-9366.37" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank6_dma_length0_r + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9292.2-9294.5" - switch \builder_csrbank6_dma_enable0_re - attribute \src "ls180.v:9292.6-9292.37" + attribute \src "ls180.v:9370.2-9372.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9370.6-9370.37" case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank6_dma_enable0_r + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9296.2-9298.5" - switch \builder_csrbank6_dma_loop0_re - attribute \src "ls180.v:9296.6-9296.35" + attribute \src "ls180.v:9374.2-9376.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9374.6-9374.35" case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank6_dma_loop0_r + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9301.2-9316.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9301.6-9301.26" + attribute \src "ls180.v:9379.2-9394.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9379.6-9379.26" case 1'1 - attribute \src "ls180.v:9302.3-9315.10" - switch \builder_interface7_bank_bus_adr [1:0] + attribute \src "ls180.v:9380.3-9393.10" + switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_card_detect_w } + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_clocker_divider1_w } + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_clocker_divider0_w + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w attribute \src "ls180.v:0.0-0.0" case 2'11 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } case end case end - attribute \src "ls180.v:9317.2-9319.5" - switch \builder_csrbank7_clocker_divider1_re - attribute \src "ls180.v:9317.6-9317.42" + attribute \src "ls180.v:9395.2-9397.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9395.6-9395.42" case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank7_clocker_divider1_r + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9320.2-9322.5" - switch \builder_csrbank7_clocker_divider0_re - attribute \src "ls180.v:9320.6-9320.42" + attribute \src "ls180.v:9398.2-9400.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9398.6-9398.42" case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank7_clocker_divider0_r + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9325.2-9358.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9325.6-9325.26" + attribute \src "ls180.v:9403.2-9436.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9403.6-9403.26" case 1'1 - attribute \src "ls180.v:9326.3-9357.10" - switch \builder_interface8_bank_bus_adr [3:0] + attribute \src "ls180.v:9404.3-9435.10" + switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank8_dfii_control0_w } + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank8_dfii_pi0_command0_w } + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank8_dfii_pi0_address1_w } + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_address0_w + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank8_dfii_pi0_baddress0_w } + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata1_w + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_wrdata0_w + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata1_w + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w attribute \src "ls180.v:0.0-0.0" case 4'1001 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_dfii_pi0_rddata0_w + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w case end case end - attribute \src "ls180.v:9359.2-9361.5" - switch \builder_csrbank8_dfii_control0_re - attribute \src "ls180.v:9359.6-9359.39" + attribute \src "ls180.v:9437.2-9439.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9437.6-9437.39" case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank8_dfii_control0_r + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9363.2-9365.5" - switch \builder_csrbank8_dfii_pi0_command0_re - attribute \src "ls180.v:9363.6-9363.43" + attribute \src "ls180.v:9441.2-9443.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9441.6-9441.43" case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank8_dfii_pi0_command0_r + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9367.2-9369.5" - switch \builder_csrbank8_dfii_pi0_address1_re - attribute \src "ls180.v:9367.6-9367.43" + attribute \src "ls180.v:9445.2-9447.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9445.6-9445.43" case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank8_dfii_pi0_address1_r + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9370.2-9372.5" - switch \builder_csrbank8_dfii_pi0_address0_re - attribute \src "ls180.v:9370.6-9370.43" + attribute \src "ls180.v:9448.2-9450.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9448.6-9448.43" case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank8_dfii_pi0_address0_r + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9374.2-9376.5" - switch \builder_csrbank8_dfii_pi0_baddress0_re - attribute \src "ls180.v:9374.6-9374.44" + attribute \src "ls180.v:9452.2-9454.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9452.6-9452.44" case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank8_dfii_pi0_baddress0_r + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9378.2-9380.5" - switch \builder_csrbank8_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9378.6-9378.42" + attribute \src "ls180.v:9456.2-9458.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9456.6-9456.42" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank8_dfii_pi0_wrdata1_r + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9381.2-9383.5" - switch \builder_csrbank8_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9381.6-9381.42" + attribute \src "ls180.v:9459.2-9461.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9459.6-9459.42" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank8_dfii_pi0_wrdata0_r + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9386.2-9410.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9386.6-9386.26" + attribute \src "ls180.v:9464.2-9488.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9464.6-9464.27" case 1'1 - attribute \src "ls180.v:9387.3-9409.10" - switch \builder_interface9_bank_bus_adr [2:0] + attribute \src "ls180.v:9465.3-9487.10" + switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w } + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w } + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w } + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } case end case end - attribute \src "ls180.v:9411.2-9413.5" - switch \builder_csrbank9_control1_re - attribute \src "ls180.v:9411.6-9411.34" + attribute \src "ls180.v:9489.2-9491.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9489.6-9489.35" case 1'1 - assign $0\main_spi_master_control_storage[15:0] [15:8] \builder_csrbank9_control1_r + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9414.2-9416.5" - switch \builder_csrbank9_control0_re - attribute \src "ls180.v:9414.6-9414.34" + attribute \src "ls180.v:9492.2-9494.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9492.6-9492.35" case 1'1 - assign $0\main_spi_master_control_storage[15:0] [7:0] \builder_csrbank9_control0_r + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9418.2-9420.5" - switch \builder_csrbank9_mosi0_re - attribute \src "ls180.v:9418.6-9418.31" + attribute \src "ls180.v:9496.2-9498.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9496.6-9496.32" case 1'1 - assign $0\main_spi_master_mosi_storage[7:0] \builder_csrbank9_mosi0_r + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9422.2-9424.5" - switch \builder_csrbank9_cs0_re - attribute \src "ls180.v:9422.6-9422.29" + attribute \src "ls180.v:9500.2-9502.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9500.6-9500.30" case 1'1 - assign $0\main_spi_master_cs_storage[0:0] \builder_csrbank9_cs0_r + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9426.2-9428.5" - switch \builder_csrbank9_loopback0_re - attribute \src "ls180.v:9426.6-9426.35" + attribute \src "ls180.v:9504.2-9506.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9504.6-9504.36" case 1'1 - assign $0\main_spi_master_loopback_storage[0:0] \builder_csrbank9_loopback0_r + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9431.2-9461.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9431.6-9431.27" + attribute \src "ls180.v:9509.2-9539.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9509.6-9509.27" case 1'1 - attribute \src "ls180.v:9432.3-9460.10" - switch \builder_interface10_bank_bus_adr [3:0] + attribute \src "ls180.v:9510.3-9538.10" + switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider1_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_clk_divider0_w + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w case end case end - attribute \src "ls180.v:9462.2-9464.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9462.6-9462.35" + attribute \src "ls180.v:9540.2-9542.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9540.6-9540.35" case 1'1 - assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank10_control1_r + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9465.2-9467.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9465.6-9465.35" + attribute \src "ls180.v:9543.2-9545.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9543.6-9543.35" case 1'1 - assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank10_control0_r + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9469.2-9471.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9469.6-9469.32" + attribute \src "ls180.v:9547.2-9549.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9547.6-9547.32" case 1'1 - assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank10_mosi0_r + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9473.2-9475.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9473.6-9473.30" + attribute \src "ls180.v:9551.2-9553.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9551.6-9551.30" case 1'1 - assign $0\libresocsim_cs_storage[0:0] \builder_csrbank10_cs0_r + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9477.2-9479.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9477.6-9477.36" + attribute \src "ls180.v:9555.2-9557.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9555.6-9555.36" case 1'1 - assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank10_loopback0_r + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9481.2-9483.5" - switch \builder_csrbank10_clk_divider1_re - attribute \src "ls180.v:9481.6-9481.39" + attribute \src "ls180.v:9559.2-9561.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9559.6-9559.39" case 1'1 - assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank10_clk_divider1_r + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9484.2-9486.5" - switch \builder_csrbank10_clk_divider0_re - attribute \src "ls180.v:9484.6-9484.39" + attribute \src "ls180.v:9562.2-9564.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9562.6-9562.39" case 1'1 - assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank10_clk_divider0_r + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9489.2-9543.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9489.6-9489.27" + attribute \src "ls180.v:9567.2-9621.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9567.6-9567.27" case 1'1 - attribute \src "ls180.v:9490.3-9542.10" - switch \builder_interface11_bank_bus_adr [4:0] + attribute \src "ls180.v:9568.3-9620.10" + switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load3_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w attribute \src "ls180.v:0.0-0.0" case 5'00001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load2_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w attribute \src "ls180.v:0.0-0.0" case 5'00010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load1_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w attribute \src "ls180.v:0.0-0.0" case 5'00011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_load0_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w attribute \src "ls180.v:0.0-0.0" case 5'00100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload3_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w attribute \src "ls180.v:0.0-0.0" case 5'00101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload2_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w attribute \src "ls180.v:0.0-0.0" case 5'00110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload1_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w attribute \src "ls180.v:0.0-0.0" case 5'00111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_reload0_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w attribute \src "ls180.v:0.0-0.0" case 5'01000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_en0_w } + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } attribute \src "ls180.v:0.0-0.0" case 5'01001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_update_value0_w } + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } attribute \src "ls180.v:0.0-0.0" case 5'01010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value3_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w attribute \src "ls180.v:0.0-0.0" case 5'01011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value2_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w attribute \src "ls180.v:0.0-0.0" case 5'01100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value1_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w attribute \src "ls180.v:0.0-0.0" case 5'01101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_value0_w + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w attribute \src "ls180.v:0.0-0.0" case 5'01110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 5'01111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 5'10000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_ev_enable0_w } + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } case end case end - attribute \src "ls180.v:9544.2-9546.5" - switch \builder_csrbank11_load3_re - attribute \src "ls180.v:9544.6-9544.32" + attribute \src "ls180.v:9622.2-9624.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9622.6-9622.32" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank11_load3_r + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9547.2-9549.5" - switch \builder_csrbank11_load2_re - attribute \src "ls180.v:9547.6-9547.32" + attribute \src "ls180.v:9625.2-9627.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9625.6-9625.32" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank11_load2_r + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9550.2-9552.5" - switch \builder_csrbank11_load1_re - attribute \src "ls180.v:9550.6-9550.32" + attribute \src "ls180.v:9628.2-9630.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9628.6-9628.32" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank11_load1_r + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9553.2-9555.5" - switch \builder_csrbank11_load0_re - attribute \src "ls180.v:9553.6-9553.32" + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9631.6-9631.32" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank11_load0_r + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9557.2-9559.5" - switch \builder_csrbank11_reload3_re - attribute \src "ls180.v:9557.6-9557.34" + attribute \src "ls180.v:9635.2-9637.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9635.6-9635.34" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank11_reload3_r + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9560.2-9562.5" - switch \builder_csrbank11_reload2_re - attribute \src "ls180.v:9560.6-9560.34" + attribute \src "ls180.v:9638.2-9640.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9638.6-9638.34" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank11_reload2_r + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9563.2-9565.5" - switch \builder_csrbank11_reload1_re - attribute \src "ls180.v:9563.6-9563.34" + attribute \src "ls180.v:9641.2-9643.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9641.6-9641.34" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank11_reload1_r + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9566.2-9568.5" - switch \builder_csrbank11_reload0_re - attribute \src "ls180.v:9566.6-9566.34" + attribute \src "ls180.v:9644.2-9646.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9644.6-9644.34" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank11_reload0_r + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9570.2-9572.5" - switch \builder_csrbank11_en0_re - attribute \src "ls180.v:9570.6-9570.30" + attribute \src "ls180.v:9648.2-9650.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9648.6-9648.30" case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank11_en0_r + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9574.2-9576.5" - switch \builder_csrbank11_update_value0_re - attribute \src "ls180.v:9574.6-9574.40" + attribute \src "ls180.v:9652.2-9654.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9652.6-9652.40" case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank11_update_value0_r + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9578.2-9580.5" - switch \builder_csrbank11_ev_enable0_re - attribute \src "ls180.v:9578.6-9578.37" + attribute \src "ls180.v:9656.2-9658.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9656.6-9656.37" case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank11_ev_enable0_r + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9583.2-9610.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9583.6-9583.27" + attribute \src "ls180.v:9661.2-9688.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9661.6-9661.27" case 1'1 - attribute \src "ls180.v:9584.3-9609.10" - switch \builder_interface12_bank_bus_adr [2:0] + attribute \src "ls180.v:9662.3-9687.10" + switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \main_uart_rxtx_w + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txfull_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxempty_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank12_ev_enable0_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_txempty_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } attribute \src "ls180.v:0.0-0.0" case 3'111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_rxfull_w } + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } case end case end - attribute \src "ls180.v:9611.2-9613.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9611.6-9611.37" + attribute \src "ls180.v:9689.2-9691.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9689.6-9689.37" case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank12_ev_enable0_r + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9616.2-9631.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9616.6-9616.27" + attribute \src "ls180.v:9694.2-9709.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9694.6-9694.27" case 1'1 - attribute \src "ls180.v:9617.3-9630.10" - switch \builder_interface13_bank_bus_adr [1:0] + attribute \src "ls180.v:9695.3-9708.10" + switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word3_w + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word2_w + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word1_w + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w attribute \src "ls180.v:0.0-0.0" case 2'11 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \builder_csrbank13_tuning_word0_w + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w case end case end - attribute \src "ls180.v:9632.2-9634.5" - switch \builder_csrbank13_tuning_word3_re - attribute \src "ls180.v:9632.6-9632.39" + attribute \src "ls180.v:9710.2-9712.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:9710.6-9710.39" case 1'1 - assign $0\main_storage[31:0] [31:24] \builder_csrbank13_tuning_word3_r + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:9635.2-9637.5" - switch \builder_csrbank13_tuning_word2_re - attribute \src "ls180.v:9635.6-9635.39" + attribute \src "ls180.v:9713.2-9715.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:9713.6-9713.39" case 1'1 - assign $0\main_storage[31:0] [23:16] \builder_csrbank13_tuning_word2_r + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:9638.2-9640.5" - switch \builder_csrbank13_tuning_word1_re - attribute \src "ls180.v:9638.6-9638.39" + attribute \src "ls180.v:9716.2-9718.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:9716.6-9716.39" case 1'1 - assign $0\main_storage[31:0] [15:8] \builder_csrbank13_tuning_word1_r + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:9641.2-9643.5" - switch \builder_csrbank13_tuning_word0_re - attribute \src "ls180.v:9641.6-9641.39" + attribute \src "ls180.v:9719.2-9721.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:9719.6-9719.39" case 1'1 - assign $0\main_storage[31:0] [7:0] \builder_csrbank13_tuning_word0_r + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:9645.2-9938.5" + attribute \src "ls180.v:9723.2-10017.5" switch \sys_rst_1 - attribute \src "ls180.v:9645.6-9645.15" + attribute \src "ls180.v:9723.6-9723.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\pwm[1:0] 2'00 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 assign $0\main_libresocsim_converter0_counter[0:0] 1'0 assign $0\main_libresocsim_converter1_counter[0:0] 1'0 assign $0\main_libresocsim_converter2_counter[0:0] 1'0 @@ -274181,15 +280256,15 @@ module \ls180 assign $0\main_converter_counter[0:0] 1'0 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_storage[31:0] 9895604 - assign $0\main_re[0:0] 1'0 - assign $0\main_sink_ready[0:0] 1'0 - assign $0\main_uart_clk_txen[0:0] 1'0 - assign $0\main_tx_busy[0:0] 1'0 - assign $0\main_source_valid[0:0] 1'0 - assign $0\main_uart_clk_rxen[0:0] 1'0 - assign $0\main_rx_r[0:0] 1'0 - assign $0\main_rx_busy[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 assign $0\main_uart_rx_pending[0:0] 1'0 @@ -274208,33 +280283,45 @@ module \ls180 assign $0\main_gpio_oe_re[0:0] 1'0 assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 assign $0\main_gpio_out_re[0:0] 1'0 - assign $0\spi_master_clk[0:0] 1'0 - assign $0\spi_master_mosi[0:0] 1'0 - assign $0\spi_master_cs_n[0:0] 1'0 - assign $0\main_spi_master_miso[7:0] 8'00000000 - assign $0\main_spi_master_control_storage[15:0] 16'0000000000000000 - assign $0\main_spi_master_control_re[0:0] 1'0 - assign $0\main_spi_master_mosi_re[0:0] 1'0 - assign $0\main_spi_master_cs_storage[0:0] 1'1 - assign $0\main_spi_master_cs_re[0:0] 1'0 - assign $0\main_spi_master_loopback_storage[0:0] 1'0 - assign $0\main_spi_master_loopback_re[0:0] 1'0 - assign $0\main_spi_master_count[2:0] 3'000 - assign $0\main_spi_master_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spi_master_mosi_data[7:0] 8'00000000 - assign $0\main_spi_master_mosi_sel[2:0] 3'000 - assign $0\main_spi_master_miso_data[7:0] 8'00000000 - assign $0\main_dummy[41:0] 42'000000000000000000000000000000000000000000 - assign $0\pwm0[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000 assign $0\main_pwm0_enable_storage[0:0] 1'0 assign $0\main_pwm0_enable_re[0:0] 1'0 assign $0\main_pwm0_width_re[0:0] 1'0 assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\pwm1[0:0] 1'0 assign $0\main_pwm1_enable_storage[0:0] 1'0 assign $0\main_pwm1_enable_re[0:0] 1'0 assign $0\main_pwm1_width_re[0:0] 1'0 assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 assign $0\main_sdphy_clocker_re[0:0] 1'0 assign $0\main_sdphy_clocker_clk0[0:0] 1'0 @@ -274331,24 +280418,6 @@ module \ls180 assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\libresocsim_miso[7:0] 8'00000000 - assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 - assign $0\libresocsim_control_re[0:0] 1'0 - assign $0\libresocsim_mosi_re[0:0] 1'0 - assign $0\libresocsim_cs_storage[0:0] 1'1 - assign $0\libresocsim_cs_re[0:0] 1'0 - assign $0\libresocsim_loopback_storage[0:0] 1'0 - assign $0\libresocsim_loopback_re[0:0] 1'0 - assign $0\libresocsim_count[2:0] 3'000 - assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 - assign $0\libresocsim_mosi_data[7:0] 8'00000000 - assign $0\libresocsim_mosi_sel[2:0] 3'000 - assign $0\libresocsim_miso_data[7:0] 8'00000000 - assign $0\libresocsim_storage[15:0] 16'0000000001111101 - assign $0\libresocsim_re[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 @@ -274365,6 +280434,7 @@ module \ls180 assign $0\builder_new_master_rdata_valid3[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 @@ -274376,7 +280446,6 @@ module \ls180 assign $0\builder_sdblock2memdma_state[1:0] 2'00 assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 assign $0\builder_libresocsim_we[0:0] 1'0 assign $0\builder_grant[2:0] 3'000 assign $0\builder_slave_sel_r[4:0] 5'00000 @@ -274385,11 +280454,11 @@ module \ls180 case end sync posedge \sys_clk_1 - update \spi_master_clk $0\spi_master_clk[0:0] - update \spi_master_mosi $0\spi_master_mosi[0:0] - update \spi_master_cs_n $0\spi_master_cs_n[0:0] - update \pwm0 $0\pwm0[0:0] - update \pwm1 $0\pwm1[0:0] + update \uart_tx $0\uart_tx[0:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \pwm $0\pwm[1:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] @@ -274398,7 +280467,6 @@ module \ls180 update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_libresoc_constraintmanager0_uart0_tx $0\main_libresocsim_libresoc_constraintmanager0_uart0_tx[0:0] update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] @@ -274512,22 +280580,22 @@ module \ls180 update \main_converter_dat_r $0\main_converter_dat_r[31:0] update \main_cmd_consumed $0\main_cmd_consumed[0:0] update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_storage $0\main_storage[31:0] - update \main_re $0\main_re[0:0] - update \main_sink_ready $0\main_sink_ready[0:0] - update \main_uart_clk_txen $0\main_uart_clk_txen[0:0] - update \main_phase_accumulator_tx $0\main_phase_accumulator_tx[31:0] - update \main_tx_reg $0\main_tx_reg[7:0] - update \main_tx_bitcount $0\main_tx_bitcount[3:0] - update \main_tx_busy $0\main_tx_busy[0:0] - update \main_source_valid $0\main_source_valid[0:0] - update \main_source_payload_data $0\main_source_payload_data[7:0] - update \main_uart_clk_rxen $0\main_uart_clk_rxen[0:0] - update \main_phase_accumulator_rx $0\main_phase_accumulator_rx[31:0] - update \main_rx_r $0\main_rx_r[0:0] - update \main_rx_reg $0\main_rx_reg[7:0] - update \main_rx_bitcount $0\main_rx_bitcount[3:0] - update \main_rx_busy $0\main_rx_busy[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] @@ -274546,21 +280614,37 @@ module \ls180 update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] update \main_gpio_out_re $0\main_gpio_out_re[0:0] - update \main_spi_master_miso $0\main_spi_master_miso[7:0] - update \main_spi_master_control_storage $0\main_spi_master_control_storage[15:0] - update \main_spi_master_control_re $0\main_spi_master_control_re[0:0] - update \main_spi_master_mosi_storage $0\main_spi_master_mosi_storage[7:0] - update \main_spi_master_mosi_re $0\main_spi_master_mosi_re[0:0] - update \main_spi_master_cs_storage $0\main_spi_master_cs_storage[0:0] - update \main_spi_master_cs_re $0\main_spi_master_cs_re[0:0] - update \main_spi_master_loopback_storage $0\main_spi_master_loopback_storage[0:0] - update \main_spi_master_loopback_re $0\main_spi_master_loopback_re[0:0] - update \main_spi_master_count $0\main_spi_master_count[2:0] - update \main_spi_master_clk_divider1 $0\main_spi_master_clk_divider1[15:0] - update \main_spi_master_mosi_data $0\main_spi_master_mosi_data[7:0] - update \main_spi_master_mosi_sel $0\main_spi_master_mosi_sel[2:0] - update \main_spi_master_miso_data $0\main_spi_master_miso_data[7:0] - update \main_dummy $0\main_dummy[41:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[35:0] update \main_pwm0_counter $0\main_pwm0_counter[31:0] update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] @@ -274575,6 +280659,8 @@ module \ls180 update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] @@ -274696,22 +280782,6 @@ module \ls180 update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \libresocsim_miso $0\libresocsim_miso[7:0] - update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] - update \libresocsim_control_re $0\libresocsim_control_re[0:0] - update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] - update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] - update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] - update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] - update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] - update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] - update \libresocsim_count $0\libresocsim_count[2:0] - update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] - update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] - update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] - update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] - update \libresocsim_storage $0\libresocsim_storage[15:0] - update \libresocsim_re $0\libresocsim_re[0:0] update \builder_converter0_state $0\builder_converter0_state[0:0] update \builder_converter1_state $0\builder_converter1_state[0:0] update \builder_converter2_state $0\builder_converter2_state[0:0] @@ -274728,6 +280798,7 @@ module \ls180 update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] update \builder_converter_state $0\builder_converter_state[0:0] update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] @@ -274739,7 +280810,6 @@ module \ls180 update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] @@ -274760,6 +280830,7 @@ module \ls180 update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] update \builder_state $0\builder_state[1:0] update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] @@ -274796,948 +280867,801 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:736.5-736.48" - process $proc$ls180.v:736$3048 + attribute \src "ls180.v:743.5-743.43" + process $proc$ls180.v:743$3052 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:746.5-746.49" + process $proc$ls180.v:746$3053 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:747.5-747.49" + process $proc$ls180.v:747$3054 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:748.5-748.48" + process $proc$ls180.v:748$3055 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:75.5-75.46" + process $proc$ls180.v:75$2782 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "ls180.v:752.11-752.46" + process $proc$ls180.v:752$3056 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:754.11-754.45" + process $proc$ls180.v:754$3057 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:756.5-756.44" + process $proc$ls180.v:756$3058 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:757.5-757.45" + process $proc$ls180.v:757$3059 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:759.5-759.48" + process $proc$ls180.v:759$3060 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:761.5-761.43" + process $proc$ls180.v:761$3061 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:764.5-764.49" + process $proc$ls180.v:764$3062 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:765.5-765.49" + process $proc$ls180.v:765$3063 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:766.5-766.48" + process $proc$ls180.v:766$3064 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:740.11-740.46" - process $proc$ls180.v:740$3049 + attribute \src "ls180.v:770.11-770.46" + process $proc$ls180.v:770$3065 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:742.11-742.45" - process $proc$ls180.v:742$3050 + attribute \src "ls180.v:772.11-772.45" + process $proc$ls180.v:772$3066 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:744.12-744.36" - process $proc$ls180.v:744$3051 + attribute \src "ls180.v:774.12-774.36" + process $proc$ls180.v:774$3067 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:745.11-745.35" - process $proc$ls180.v:745$3052 + attribute \src "ls180.v:775.11-775.35" + process $proc$ls180.v:775$3068 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:746.11-746.40" - process $proc$ls180.v:746$3053 + attribute \src "ls180.v:776.11-776.40" + process $proc$ls180.v:776$3069 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:747.5-747.31" - process $proc$ls180.v:747$3054 + attribute \src "ls180.v:777.5-777.31" + process $proc$ls180.v:777$3070 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:748.5-748.31" - process $proc$ls180.v:748$3055 + attribute \src "ls180.v:778.5-778.31" + process $proc$ls180.v:778$3071 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:750.32-750.63" - process $proc$ls180.v:750$3056 + attribute \src "ls180.v:780.32-780.63" + process $proc$ls180.v:780$3072 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:752.32-752.63" - process $proc$ls180.v:752$3057 + attribute \src "ls180.v:782.32-782.63" + process $proc$ls180.v:782$3073 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:754.32-754.63" - process $proc$ls180.v:754$3058 + attribute \src "ls180.v:784.32-784.63" + process $proc$ls180.v:784$3074 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:755.5-755.36" - process $proc$ls180.v:755$3059 + attribute \src "ls180.v:785.5-785.36" + process $proc$ls180.v:785$3075 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:757.32-757.63" - process $proc$ls180.v:757$3060 + attribute \src "ls180.v:787.32-787.63" + process $proc$ls180.v:787$3076 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:758.11-758.42" - process $proc$ls180.v:758$3061 + attribute \src "ls180.v:788.11-788.42" + process $proc$ls180.v:788$3077 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:761.5-761.26" - process $proc$ls180.v:761$3062 + attribute \src "ls180.v:791.5-791.26" + process $proc$ls180.v:791$3078 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:763.11-763.34" - process $proc$ls180.v:763$3063 + attribute \src "ls180.v:793.11-793.34" + process $proc$ls180.v:793$3079 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:764.5-764.26" - process $proc$ls180.v:764$3064 + attribute \src "ls180.v:794.5-794.26" + process $proc$ls180.v:794$3080 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:766.11-766.34" - process $proc$ls180.v:766$3065 + attribute \src "ls180.v:796.11-796.34" + process $proc$ls180.v:796$3081 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:77.5-77.46" - process $proc$ls180.v:77$2773 + attribute \src "ls180.v:817.5-817.29" + process $proc$ls180.v:817$3082 assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:787.5-787.29" - process $proc$ls180.v:787$3066 + attribute \src "ls180.v:82.5-82.46" + process $proc$ls180.v:82$2783 assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 sync always sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "ls180.v:791.5-791.29" - process $proc$ls180.v:791$3067 + attribute \src "ls180.v:821.5-821.29" + process $proc$ls180.v:821$3083 assign { } { } assign $0\main_wb_sdram_err[0:0] 1'0 sync always update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init end - attribute \src "ls180.v:792.12-792.40" - process $proc$ls180.v:792$3068 + attribute \src "ls180.v:822.12-822.40" + process $proc$ls180.v:822$3084 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:793.12-793.42" - process $proc$ls180.v:793$3069 + attribute \src "ls180.v:823.12-823.42" + process $proc$ls180.v:823$3085 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:795.11-795.38" - process $proc$ls180.v:795$3070 + attribute \src "ls180.v:825.11-825.38" + process $proc$ls180.v:825$3086 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:796.5-796.32" - process $proc$ls180.v:796$3071 + attribute \src "ls180.v:826.5-826.32" + process $proc$ls180.v:826$3087 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:797.5-797.32" - process $proc$ls180.v:797$3072 + attribute \src "ls180.v:827.5-827.32" + process $proc$ls180.v:827$3088 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:799.5-799.31" - process $proc$ls180.v:799$3073 + attribute \src "ls180.v:829.5-829.31" + process $proc$ls180.v:829$3089 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:800.5-800.31" - process $proc$ls180.v:800$3074 + attribute \src "ls180.v:830.5-830.31" + process $proc$ls180.v:830$3090 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:801.5-801.34" - process $proc$ls180.v:801$3075 + attribute \src "ls180.v:831.5-831.34" + process $proc$ls180.v:831$3091 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:803.12-803.40" - process $proc$ls180.v:803$3076 + attribute \src "ls180.v:833.12-833.40" + process $proc$ls180.v:833$3092 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:804.5-804.29" - process $proc$ls180.v:804$3077 + attribute \src "ls180.v:834.5-834.29" + process $proc$ls180.v:834$3093 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:805.5-805.31" - process $proc$ls180.v:805$3078 + attribute \src "ls180.v:835.5-835.31" + process $proc$ls180.v:835$3094 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:809.12-809.38" - process $proc$ls180.v:809$3079 + attribute \src "ls180.v:839.12-839.47" + process $proc$ls180.v:839$3095 assign { } { } - assign $1\main_storage[31:0] 9895604 + assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init - update \main_storage $1\main_storage[31:0] + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:81.5-81.46" - process $proc$ls180.v:81$2774 + attribute \src "ls180.v:840.5-840.28" + process $proc$ls180.v:840$3096 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + assign $1\main_uart_phy_re[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:810.5-810.19" - process $proc$ls180.v:810$3080 + attribute \src "ls180.v:842.5-842.36" + process $proc$ls180.v:842$3097 assign { } { } - assign $1\main_re[0:0] 1'0 + assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init - update \main_re $1\main_re[0:0] + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:812.5-812.27" - process $proc$ls180.v:812$3081 + attribute \src "ls180.v:846.5-846.39" + process $proc$ls180.v:846$3098 assign { } { } - assign $1\main_sink_ready[0:0] 1'0 + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init - update \main_sink_ready $1\main_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:816.5-816.30" - process $proc$ls180.v:816$3082 + attribute \src "ls180.v:847.12-847.54" + process $proc$ls180.v:847$3099 assign { } { } - assign $1\main_uart_clk_txen[0:0] 1'0 + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init - update \main_uart_clk_txen $1\main_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:817.12-817.45" - process $proc$ls180.v:817$3083 + attribute \src "ls180.v:848.11-848.38" + process $proc$ls180.v:848$3100 assign { } { } - assign $1\main_phase_accumulator_tx[31:0] 0 + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init - update \main_phase_accumulator_tx $1\main_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:818.11-818.29" - process $proc$ls180.v:818$3084 + attribute \src "ls180.v:849.11-849.43" + process $proc$ls180.v:849$3101 assign { } { } - assign $1\main_tx_reg[7:0] 8'00000000 + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init - update \main_tx_reg $1\main_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:819.11-819.34" - process $proc$ls180.v:819$3085 + attribute \src "ls180.v:850.5-850.33" + process $proc$ls180.v:850$3102 assign { } { } - assign $1\main_tx_bitcount[3:0] 4'0000 + assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init - update \main_tx_bitcount $1\main_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:820.5-820.24" - process $proc$ls180.v:820$3086 + attribute \src "ls180.v:851.5-851.38" + process $proc$ls180.v:851$3103 assign { } { } - assign $1\main_tx_busy[0:0] 1'0 + assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init - update \main_tx_busy $1\main_tx_busy[0:0] + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:821.5-821.29" - process $proc$ls180.v:821$3087 + attribute \src "ls180.v:853.5-853.38" + process $proc$ls180.v:853$3104 assign { } { } - assign $1\main_source_valid[0:0] 1'0 + assign $0\main_uart_phy_source_first[0:0] 1'0 sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init - update \main_source_valid $1\main_source_valid[0:0] end - attribute \src "ls180.v:823.5-823.29" - process $proc$ls180.v:823$3088 + attribute \src "ls180.v:854.5-854.37" + process $proc$ls180.v:854$3105 assign { } { } - assign $0\main_source_first[0:0] 1'0 + assign $0\main_uart_phy_source_last[0:0] 1'0 sync always - update \main_source_first $0\main_source_first[0:0] + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:824.5-824.28" - process $proc$ls180.v:824$3089 + attribute \src "ls180.v:855.11-855.51" + process $proc$ls180.v:855$3106 assign { } { } - assign $0\main_source_last[0:0] 1'0 + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always - update \main_source_last $0\main_source_last[0:0] sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:825.11-825.42" - process $proc$ls180.v:825$3090 + attribute \src "ls180.v:856.5-856.39" + process $proc$ls180.v:856$3107 assign { } { } - assign $1\main_source_payload_data[7:0] 8'00000000 + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init - update \main_source_payload_data $1\main_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:826.5-826.30" - process $proc$ls180.v:826$3091 + attribute \src "ls180.v:857.12-857.54" + process $proc$ls180.v:857$3108 assign { } { } - assign $1\main_uart_clk_rxen[0:0] 1'0 + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init - update \main_uart_clk_rxen $1\main_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:827.12-827.45" - process $proc$ls180.v:827$3092 + attribute \src "ls180.v:859.5-859.30" + process $proc$ls180.v:859$3109 assign { } { } - assign $1\main_phase_accumulator_rx[31:0] 0 + assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init - update \main_phase_accumulator_rx $1\main_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:829.5-829.21" - process $proc$ls180.v:829$3093 + attribute \src "ls180.v:86.5-86.46" + process $proc$ls180.v:86$2784 assign { } { } - assign $1\main_rx_r[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init - update \main_rx_r $1\main_rx_r[0:0] end - attribute \src "ls180.v:830.11-830.29" - process $proc$ls180.v:830$3094 + attribute \src "ls180.v:860.11-860.38" + process $proc$ls180.v:860$3110 assign { } { } - assign $1\main_rx_reg[7:0] 8'00000000 + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init - update \main_rx_reg $1\main_rx_reg[7:0] + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:831.11-831.34" - process $proc$ls180.v:831$3095 + attribute \src "ls180.v:861.11-861.43" + process $proc$ls180.v:861$3111 assign { } { } - assign $1\main_rx_bitcount[3:0] 4'0000 + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init - update \main_rx_bitcount $1\main_rx_bitcount[3:0] + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:832.5-832.24" - process $proc$ls180.v:832$3096 + attribute \src "ls180.v:862.5-862.33" + process $proc$ls180.v:862$3112 assign { } { } - assign $1\main_rx_busy[0:0] 1'0 + assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init - update \main_rx_busy $1\main_rx_busy[0:0] + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:843.5-843.32" - process $proc$ls180.v:843$3097 + attribute \src "ls180.v:873.5-873.32" + process $proc$ls180.v:873$3113 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:845.5-845.30" - process $proc$ls180.v:845$3098 + attribute \src "ls180.v:875.5-875.30" + process $proc$ls180.v:875$3114 assign { } { } assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:846.5-846.36" - process $proc$ls180.v:846$3099 + attribute \src "ls180.v:876.5-876.36" + process $proc$ls180.v:876$3115 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:848.5-848.32" - process $proc$ls180.v:848$3100 + attribute \src "ls180.v:878.5-878.32" + process $proc$ls180.v:878$3116 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:850.5-850.30" - process $proc$ls180.v:850$3101 + attribute \src "ls180.v:880.5-880.30" + process $proc$ls180.v:880$3117 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:851.5-851.36" - process $proc$ls180.v:851$3102 + attribute \src "ls180.v:881.5-881.36" + process $proc$ls180.v:881$3118 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:855.11-855.49" - process $proc$ls180.v:855$3103 + attribute \src "ls180.v:885.11-885.49" + process $proc$ls180.v:885$3119 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:859.11-859.50" - process $proc$ls180.v:859$3104 + attribute \src "ls180.v:889.11-889.50" + process $proc$ls180.v:889$3120 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:860.11-860.48" - process $proc$ls180.v:860$3105 + attribute \src "ls180.v:890.11-890.48" + process $proc$ls180.v:890$3121 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:861.5-861.37" - process $proc$ls180.v:861$3106 + attribute \src "ls180.v:891.5-891.37" + process $proc$ls180.v:891$3122 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "ls180.v:878.5-878.40" - process $proc$ls180.v:878$3107 + attribute \src "ls180.v:908.5-908.40" + process $proc$ls180.v:908$3123 assign { } { } assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init end - attribute \src "ls180.v:879.5-879.39" - process $proc$ls180.v:879$3108 + attribute \src "ls180.v:909.5-909.39" + process $proc$ls180.v:909$3124 assign { } { } assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init end - attribute \src "ls180.v:887.5-887.38" - process $proc$ls180.v:887$3109 + attribute \src "ls180.v:917.5-917.38" + process $proc$ls180.v:917$3125 assign { } { } assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "ls180.v:894.11-894.42" - process $proc$ls180.v:894$3110 + attribute \src "ls180.v:924.11-924.42" + process $proc$ls180.v:924$3126 assign { } { } assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "ls180.v:895.5-895.37" - process $proc$ls180.v:895$3111 + attribute \src "ls180.v:925.5-925.37" + process $proc$ls180.v:925$3127 assign { } { } assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:896.11-896.43" - process $proc$ls180.v:896$3112 + attribute \src "ls180.v:926.11-926.43" + process $proc$ls180.v:926$3128 assign { } { } assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "ls180.v:897.11-897.43" - process $proc$ls180.v:897$3113 + attribute \src "ls180.v:927.11-927.43" + process $proc$ls180.v:927$3129 assign { } { } assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "ls180.v:898.11-898.46" - process $proc$ls180.v:898$3114 + attribute \src "ls180.v:928.11-928.46" + process $proc$ls180.v:928$3130 assign { } { } assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:924.5-924.38" - process $proc$ls180.v:924$3115 + attribute \src "ls180.v:954.5-954.38" + process $proc$ls180.v:954$3131 assign { } { } assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always sync init update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end - attribute \src "ls180.v:931.11-931.42" - process $proc$ls180.v:931$3116 + attribute \src "ls180.v:961.11-961.42" + process $proc$ls180.v:961$3132 assign { } { } assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "ls180.v:932.5-932.37" - process $proc$ls180.v:932$3117 + attribute \src "ls180.v:962.5-962.37" + process $proc$ls180.v:962$3133 assign { } { } assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init end - attribute \src "ls180.v:933.11-933.43" - process $proc$ls180.v:933$3118 + attribute \src "ls180.v:963.11-963.43" + process $proc$ls180.v:963$3134 assign { } { } assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "ls180.v:934.11-934.43" - process $proc$ls180.v:934$3119 + attribute \src "ls180.v:964.11-964.43" + process $proc$ls180.v:964$3135 assign { } { } assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "ls180.v:935.11-935.46" - process $proc$ls180.v:935$3120 + attribute \src "ls180.v:965.11-965.46" + process $proc$ls180.v:965$3136 assign { } { } assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:950.5-950.27" - process $proc$ls180.v:950$3121 + attribute \src "ls180.v:980.5-980.27" + process $proc$ls180.v:980$3137 assign { } { } assign $0\main_uart_reset[0:0] 1'0 sync always update \main_uart_reset $0\main_uart_reset[0:0] sync init end - attribute \src "ls180.v:951.12-951.40" - process $proc$ls180.v:951$3122 + attribute \src "ls180.v:981.12-981.40" + process $proc$ls180.v:981$3138 assign { } { } assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] end - attribute \src "ls180.v:952.5-952.27" - process $proc$ls180.v:952$3123 + attribute \src "ls180.v:982.5-982.27" + process $proc$ls180.v:982$3139 assign { } { } assign $1\main_gpio_oe_re[0:0] 1'0 sync always sync init update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] end - attribute \src "ls180.v:953.12-953.36" - process $proc$ls180.v:953$3124 + attribute \src "ls180.v:983.12-983.36" + process $proc$ls180.v:983$3140 assign { } { } assign $1\main_gpio_status[15:0] 16'0000000000000000 sync always sync init update \main_gpio_status $1\main_gpio_status[15:0] end - attribute \src "ls180.v:955.12-955.41" - process $proc$ls180.v:955$3125 + attribute \src "ls180.v:985.12-985.41" + process $proc$ls180.v:985$3141 assign { } { } assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 sync always sync init update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] end - attribute \src "ls180.v:956.5-956.28" - process $proc$ls180.v:956$3126 + attribute \src "ls180.v:986.5-986.28" + process $proc$ls180.v:986$3142 assign { } { } assign $1\main_gpio_out_re[0:0] 1'0 sync always sync init update \main_gpio_out_re $1\main_gpio_out_re[0:0] end - attribute \src "ls180.v:962.5-962.33" - process $proc$ls180.v:962$3127 - assign { } { } - assign $1\main_spi_master_done0[0:0] 1'0 - sync always - sync init - update \main_spi_master_done0 $1\main_spi_master_done0[0:0] - end - attribute \src "ls180.v:963.5-963.31" - process $proc$ls180.v:963$3128 - assign { } { } - assign $1\main_spi_master_irq[0:0] 1'0 - sync always - sync init - update \main_spi_master_irq $1\main_spi_master_irq[0:0] - end - attribute \src "ls180.v:965.11-965.38" - process $proc$ls180.v:965$3129 - assign { } { } - assign $1\main_spi_master_miso[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_miso $1\main_spi_master_miso[7:0] - end - attribute \src "ls180.v:968.12-968.48" - process $proc$ls180.v:968$3130 - assign { } { } - assign $0\main_spi_master_clk_divider0[15:0] 16'0000000000000111 - sync always - update \main_spi_master_clk_divider0 $0\main_spi_master_clk_divider0[15:0] - sync init - end - attribute \src "ls180.v:969.5-969.34" - process $proc$ls180.v:969$3131 - assign { } { } - assign $1\main_spi_master_start1[0:0] 1'0 - sync always - sync init - update \main_spi_master_start1 $1\main_spi_master_start1[0:0] - end - attribute \src "ls180.v:971.12-971.51" - process $proc$ls180.v:971$3132 - assign { } { } - assign $1\main_spi_master_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spi_master_control_storage $1\main_spi_master_control_storage[15:0] - end - attribute \src "ls180.v:972.5-972.38" - process $proc$ls180.v:972$3133 - assign { } { } - assign $1\main_spi_master_control_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_control_re $1\main_spi_master_control_re[0:0] - end - attribute \src "ls180.v:976.11-976.46" - process $proc$ls180.v:976$3134 - assign { } { } - assign $1\main_spi_master_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spi_master_mosi_storage $1\main_spi_master_mosi_storage[7:0] - end - attribute \src "ls180.v:977.5-977.35" - process $proc$ls180.v:977$3135 - assign { } { } - assign $1\main_spi_master_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_mosi_re $1\main_spi_master_mosi_re[0:0] - end - attribute \src "ls180.v:981.5-981.38" - process $proc$ls180.v:981$3136 - assign { } { } - assign $1\main_spi_master_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spi_master_cs_storage $1\main_spi_master_cs_storage[0:0] - end - attribute \src "ls180.v:982.5-982.33" - process $proc$ls180.v:982$3137 - assign { } { } - assign $1\main_spi_master_cs_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_cs_re $1\main_spi_master_cs_re[0:0] - end - attribute \src "ls180.v:983.5-983.44" - process $proc$ls180.v:983$3138 - assign { } { } - assign $1\main_spi_master_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spi_master_loopback_storage $1\main_spi_master_loopback_storage[0:0] - end - attribute \src "ls180.v:984.5-984.39" - process $proc$ls180.v:984$3139 - assign { } { } - assign $1\main_spi_master_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spi_master_loopback_re $1\main_spi_master_loopback_re[0:0] - end - attribute \src "ls180.v:985.5-985.38" - process $proc$ls180.v:985$3140 - assign { } { } - assign $1\main_spi_master_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spi_master_clk_enable $1\main_spi_master_clk_enable[0:0] - end - attribute \src "ls180.v:986.5-986.37" - process $proc$ls180.v:986$3141 - assign { } { } - assign $1\main_spi_master_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spi_master_cs_enable $1\main_spi_master_cs_enable[0:0] - end - attribute \src "ls180.v:987.11-987.39" - process $proc$ls180.v:987$3142 - assign { } { } - assign $1\main_spi_master_count[2:0] 3'000 - sync always - sync init - update \main_spi_master_count $1\main_spi_master_count[2:0] - end - attribute \src "ls180.v:988.5-988.38" - process $proc$ls180.v:988$3143 - assign { } { } - assign $1\main_spi_master_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spi_master_mosi_latch $1\main_spi_master_mosi_latch[0:0] - end - attribute \src "ls180.v:989.5-989.38" - process $proc$ls180.v:989$3144 - assign { } { } - assign $1\main_spi_master_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spi_master_miso_latch $1\main_spi_master_miso_latch[0:0] - end - attribute \src "ls180.v:990.12-990.48" - process $proc$ls180.v:990$3145 + attribute \src "ls180.v:992.5-992.32" + process $proc$ls180.v:992$3143 assign { } { } - assign $1\main_spi_master_clk_divider1[15:0] 16'0000000000000000 + assign $1\main_spimaster2_done[0:0] 1'0 sync always sync init - update \main_spi_master_clk_divider1 $1\main_spi_master_clk_divider1[15:0] + update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:993.11-993.43" - process $proc$ls180.v:993$3146 + attribute \src "ls180.v:993.5-993.31" + process $proc$ls180.v:993$3144 assign { } { } - assign $1\main_spi_master_mosi_data[7:0] 8'00000000 + assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init - update \main_spi_master_mosi_data $1\main_spi_master_mosi_data[7:0] + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "ls180.v:994.11-994.42" - process $proc$ls180.v:994$3147 + attribute \src "ls180.v:995.11-995.38" + process $proc$ls180.v:995$3145 assign { } { } - assign $1\main_spi_master_mosi_sel[2:0] 3'000 + assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init - update \main_spi_master_mosi_sel $1\main_spi_master_mosi_sel[2:0] + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:995.11-995.43" - process $proc$ls180.v:995$3148 + attribute \src "ls180.v:998.12-998.47" + process $proc$ls180.v:998$3146 assign { } { } - assign $1\main_spi_master_miso_data[7:0] 8'00000000 + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init - update \main_spi_master_miso_data $1\main_spi_master_miso_data[7:0] end - attribute \src "ls180.v:997.12-997.30" - process $proc$ls180.v:997$3149 + attribute \src "ls180.v:999.5-999.33" + process $proc$ls180.v:999$3147 assign { } { } - assign $1\main_dummy[41:0] 42'000000000000000000000000000000000000000000 + assign $1\main_spimaster9_start[0:0] 1'0 sync always sync init - update \main_dummy $1\main_dummy[41:0] - end - attribute \src "ls180.v:9977.1-9987.4" - process $proc$ls180.v:9977$2682 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 0 - assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 0 - assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 0 - assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:9978.2-9979.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:9978.6-9978.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 255 - case - end - attribute \src "ls180.v:9980.2-9981.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:9980.6-9980.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 65280 - case - end - attribute \src "ls180.v:9982.2-9983.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:9982.6-9982.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 16711680 - case - end - attribute \src "ls180.v:9984.2-9985.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:9984.6-9984.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 32'11111111000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:9979$1_ADDR $0$memwr$\mem$ls180.v:9979$1_ADDR[6:0]$2683 - update $memwr$\mem$ls180.v:9979$1_DATA $0$memwr$\mem$ls180.v:9979$1_DATA[31:0]$2684 - update $memwr$\mem$ls180.v:9979$1_EN $0$memwr$\mem$ls180.v:9979$1_EN[31:0]$2685 - update $memwr$\mem$ls180.v:9981$2_ADDR $0$memwr$\mem$ls180.v:9981$2_ADDR[6:0]$2686 - update $memwr$\mem$ls180.v:9981$2_DATA $0$memwr$\mem$ls180.v:9981$2_DATA[31:0]$2687 - update $memwr$\mem$ls180.v:9981$2_EN $0$memwr$\mem$ls180.v:9981$2_EN[31:0]$2688 - update $memwr$\mem$ls180.v:9983$3_ADDR $0$memwr$\mem$ls180.v:9983$3_ADDR[6:0]$2689 - update $memwr$\mem$ls180.v:9983$3_DATA $0$memwr$\mem$ls180.v:9983$3_DATA[31:0]$2690 - update $memwr$\mem$ls180.v:9983$3_EN $0$memwr$\mem$ls180.v:9983$3_EN[31:0]$2691 - update $memwr$\mem$ls180.v:9985$4_ADDR $0$memwr$\mem$ls180.v:9985$4_ADDR[6:0]$2692 - update $memwr$\mem$ls180.v:9985$4_DATA $0$memwr$\mem$ls180.v:9985$4_DATA[31:0]$2693 - update $memwr$\mem$ls180.v:9985$4_EN $0$memwr$\mem$ls180.v:9985$4_EN[31:0]$2694 - end - attribute \src "ls180.v:9997.1-10001.4" - process $proc$ls180.v:9997$2696 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 3'xxx - assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10000$2700_DATA - attribute \src "ls180.v:9998.2-9999.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:9998.6-9998.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:9999$5_ADDR $0$memwr$\storage$ls180.v:9999$5_ADDR[2:0]$2697 - update $memwr$\storage$ls180.v:9999$5_DATA $0$memwr$\storage$ls180.v:9999$5_DATA[24:0]$2698 - update $memwr$\storage$ls180.v:9999$5_EN $0$memwr$\storage$ls180.v:9999$5_EN[24:0]$2699 + update \main_spimaster9_start $1\main_spimaster9_start[0:0] end connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \uart_tx \main_libresocsim_libresoc_constraintmanager1_uart0_tx - connect \main_libresocsim_libresoc_constraintmanager1_uart0_rx \uart_rx - connect \main_libresocsim_libresoc_constraintmanager1_gpio0_i \gpio_i - connect \gpio_o \main_libresocsim_libresoc_constraintmanager1_gpio0_o - connect \gpio_oe \main_libresocsim_libresoc_constraintmanager1_gpio0_oe + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_48_o \main_libresocsim_libresoc_pll_48_o connect \main_libresocsim_libresoc_jtag_tck \jtag_tck connect \main_libresocsim_libresoc_jtag_tms \jtag_tms connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi @@ -275754,21 +281678,21 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2726$14_Y + connect \main_libresocsim_converter0_reset $not$ls180.v:2774$14_Y connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2786$25_Y + connect \main_libresocsim_converter1_reset $not$ls180.v:2834$25_Y connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2846$36_Y + connect \main_libresocsim_converter2_reset $not$ls180.v:2894$36_Y connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:2918$60_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:2966$60_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:2927$63_Y + connect \main_libresocsim_irq $and$ls180.v:2975$63_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk @@ -275810,8 +281734,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3041$70_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3042$71_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3089$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3090$71_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -275842,14 +281766,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3073$72_Y + connect \main_sdram_timer_wait $not$ls180.v:3121$72_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3076$73_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3124$73_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3079$75_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3080$77_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3127$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3128$77_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -275860,13 +281784,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3122$79_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3123$80_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3124$81_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3170$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3171$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3172$81_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3134$86_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3135$88_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3136$90_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3182$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3183$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3184$90_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -275882,13 +281806,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3168$98_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3169$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3216$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3217$99_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3172$100_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3173$101_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3174$103_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3220$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3221$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3222$103_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -275899,13 +281823,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3279$109_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3280$110_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3281$111_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3327$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3328$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3329$111_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3291$116_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3292$118_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3293$120_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3339$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3340$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3341$120_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -275921,13 +281845,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3325$128_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3326$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3373$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3374$129_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3329$130_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3330$131_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3331$133_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3377$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3378$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3379$133_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -275938,13 +281862,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3436$139_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3437$140_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3438$141_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3484$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3485$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3486$141_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3448$146_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3449$148_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3450$150_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3496$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3497$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3498$150_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -275960,13 +281884,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3482$158_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3483$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3530$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3531$159_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3486$160_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3487$161_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3488$163_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3534$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3535$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3536$163_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -275977,13 +281901,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3593$169_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3594$170_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3595$171_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3641$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3642$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3643$171_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3605$176_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3606$178_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3607$180_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3653$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3654$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3655$180_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -275999,32 +281923,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3639$188_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3640$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3687$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3688$189_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3643$190_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3644$191_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3645$193_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3691$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3692$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3693$193_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3741$204_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3742$210_Y - connect \main_sdram_ras_allowed $and$ls180.v:3743$211_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3744$214_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3789$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3790$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3791$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3792$214_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3746$216_Y - connect \main_sdram_read_available $or$ls180.v:3747$223_Y - connect \main_sdram_write_available $or$ls180.v:3748$230_Y - connect \main_sdram_max_time0 $eq$ls180.v:3749$231_Y - connect \main_sdram_max_time1 $eq$ls180.v:3750$232_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3794$216_Y + connect \main_sdram_read_available $or$ls180.v:3795$223_Y + connect \main_sdram_write_available $or$ls180.v:3796$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3797$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3798$232_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3755$235_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3803$235_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3758$236_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3806$236_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -276032,7 +281956,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3791$294_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:3839$294_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -276040,31 +281964,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3860$380_Y + connect \main_sdram_choose_req_ce $or$ls180.v:3908$380_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3937$412_Y - connect \builder_roundrobin0_ce $and$ls180.v:3938$415_Y + connect \builder_roundrobin0_request $and$ls180.v:3985$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3986$415_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3942$428_Y - connect \builder_roundrobin1_ce $and$ls180.v:3943$431_Y + connect \builder_roundrobin1_request $and$ls180.v:3990$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3991$431_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3947$444_Y - connect \builder_roundrobin2_ce $and$ls180.v:3948$447_Y + connect \builder_roundrobin2_request $and$ls180.v:3995$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3996$447_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:3952$460_Y - connect \builder_roundrobin3_ce $and$ls180.v:3953$463_Y + connect \builder_roundrobin3_request $and$ls180.v:4000$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:4001$463_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:3957$527_Y + connect \main_port_cmd_ready $or$ls180.v:4005$527_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -276072,53 +281996,53 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:3979$529_Y + connect \main_converter_reset $not$ls180.v:4027$529_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4039$540_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4087$540_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4044$541_Y - connect \main_port_cmd_last $not$ls180.v:4045$542_Y - connect \main_port_cmd_valid $and$ls180.v:4046$545_Y - connect \main_port_wdata_valid $and$ls180.v:4047$549_Y - connect \main_port_rdata_ready $and$ls180.v:4048$552_Y - connect \main_litedram_wb_ack $and$ls180.v:4049$557_Y - connect \main_ack_cmd $or$ls180.v:4050$559_Y - connect \main_ack_wdata $or$ls180.v:4051$561_Y - connect \main_ack_rdata $and$ls180.v:4052$562_Y - connect \main_uart_uart_sink_valid \main_source_valid - connect \main_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_source_first - connect \main_uart_uart_sink_last \main_source_last - connect \main_uart_uart_sink_payload_data \main_source_payload_data - connect \main_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_sink_ready - connect \main_sink_first \main_uart_uart_source_first - connect \main_sink_last \main_uart_uart_source_last - connect \main_sink_payload_data \main_uart_uart_source_payload_data + connect \main_port_flush $not$ls180.v:4092$541_Y + connect \main_port_cmd_last $not$ls180.v:4093$542_Y + connect \main_port_cmd_valid $and$ls180.v:4094$545_Y + connect \main_port_wdata_valid $and$ls180.v:4095$549_Y + connect \main_port_rdata_ready $and$ls180.v:4096$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4097$557_Y + connect \main_ack_cmd $or$ls180.v:4098$559_Y + connect \main_ack_wdata $or$ls180.v:4099$561_Y + connect \main_ack_rdata $and$ls180.v:4100$562_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4065$563_Y - connect \main_uart_txempty_status $not$ls180.v:4066$564_Y + connect \main_uart_txfull_status $not$ls180.v:4113$563_Y + connect \main_uart_txempty_status $not$ls180.v:4114$564_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4072$565_Y + connect \main_uart_tx_trigger $not$ls180.v:4120$565_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4078$566_Y - connect \main_uart_rxfull_status $not$ls180.v:4079$567_Y + connect \main_uart_rxempty_status $not$ls180.v:4126$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4127$567_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4081$569_Y - connect \main_uart_rx_trigger $not$ls180.v:4082$570_Y - connect \main_uart_irq $or$ls180.v:4105$579_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4129$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4130$570_Y + connect \main_uart_irq $or$ls180.v:4153$579_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -276133,16 +282057,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4120$582_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4121$583_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4168$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4169$583_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4131$587_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4132$588_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4179$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4180$588_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4136$589_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4137$590_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4184$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4185$590_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -276155,36 +282079,50 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4150$593_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4151$594_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4198$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4199$594_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4161$598_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4162$599_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4209$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4210$599_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4166$600_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4167$601_Y - connect \main_gpio_pads_i \main_libresocsim_libresoc_constraintmanager0_gpio0_i - connect \main_libresocsim_libresoc_constraintmanager0_gpio0_o \main_gpio_pads_o - connect \main_libresocsim_libresoc_constraintmanager0_gpio0_oe \main_gpio_pads_oe + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4214$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4215$601_Y + connect \main_gpio_pads_i \gpio_i + connect \gpio_o \main_gpio_pads_o + connect \gpio_oe \main_gpio_pads_oe connect \main_gpio_pads_oe \main_gpio_oe_storage connect \main_gpio_pads_o \main_gpio_out_storage - connect \main_spi_master_start0 \main_spi_master_start1 - connect \main_spi_master_length0 \main_spi_master_length1 - connect \main_spi_master_mosi \main_spi_master_mosi_storage - connect \main_spi_master_done1 \main_spi_master_done0 - connect \main_spi_master_miso_status \main_spi_master_miso - connect \main_spi_master_cs \main_spi_master_cs_storage - connect \main_spi_master_loopback \main_spi_master_loopback_storage - connect \main_spi_master_clk_rise $eq$ls180.v:4180$603_Y - connect \main_spi_master_clk_fall $eq$ls180.v:4181$605_Y + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4228$603_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4229$605_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4286$611_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4287$613_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4232$613_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4233$617_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4234$621_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4235$625_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4236$629_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4343$621_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4344$625_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4345$629_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4346$633_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4347$637_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -276205,8 +282143,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4257$630_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4287$633_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4368$638_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4398$641_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -276218,8 +282156,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4410$643_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4411$645_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4521$651_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4522$653_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -276236,10 +282174,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4428$647_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4539$655_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4430$648_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4431$650_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4541$656_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4542$658_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -276251,8 +282189,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4537$665_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4538$666_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4648$673_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4649$674_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -276269,10 +282207,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4555$668_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4666$676_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4557$669_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4558$671_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4668$677_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4669$679_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -276284,8 +282222,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4671$680_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4672$681_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4782$688_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4783$689_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -276302,10 +282240,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4689$683_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4800$691_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4691$684_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4692$686_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4802$692_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4803$694_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -276319,88 +282257,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4808$701_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4919$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4812$704_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4812$702_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4813$707_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4813$705_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4814$710_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4814$708_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4815$713_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4815$711_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4816$716_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4816$714_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4817$719_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4817$717_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4818$722_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4818$720_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4819$725_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4819$723_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4820$728_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4820$726_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4821$731_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4821$729_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4822$734_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4822$732_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4823$737_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4823$735_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4824$740_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4824$738_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4825$743_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4825$741_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4826$746_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4826$744_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4827$749_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4827$747_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4828$752_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4828$750_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4829$755_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4829$753_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4830$758_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4830$756_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4831$761_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4831$759_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4832$764_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4832$762_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4833$767_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4833$765_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4834$770_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4834$768_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4835$773_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4835$771_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4836$776_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4836$774_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4837$779_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4837$777_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4838$782_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4838$780_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4839$785_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4839$783_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4840$788_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4840$786_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4841$791_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4841$789_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4842$794_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4842$792_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4843$797_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4843$795_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4844$800_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4844$798_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4845$803_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4845$801_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4846$806_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4846$804_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4847$809_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4847$807_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4848$812_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4848$810_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4849$815_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4849$813_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4850$818_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4850$816_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4851$821_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4851$819_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4923$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4923$710_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4924$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4924$713_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4925$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4925$716_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4926$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4926$719_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4927$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4927$722_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4928$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4928$725_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4929$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4929$728_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4930$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4930$731_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4931$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4931$734_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4932$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4932$737_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4933$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4933$740_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4934$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4934$743_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4935$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4935$746_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4936$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4936$749_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4937$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4937$752_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4938$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4938$755_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4939$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4939$758_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4940$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4940$761_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4941$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4941$764_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4942$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4942$767_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4943$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4943$770_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4944$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4944$773_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4945$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4945$776_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4946$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4946$779_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4947$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4947$782_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4948$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4948$785_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4949$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4949$788_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4950$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4950$791_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4951$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4951$794_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4952$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4952$797_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4953$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4953$800_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4954$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4954$803_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4955$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4955$806_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4956$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4956$809_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4957$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4957$812_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4958$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4958$815_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4959$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4959$818_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4960$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4960$821_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4961$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4961$824_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4962$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4962$827_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4861$824_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4862$825_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4972$832_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4973$833_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4864$827_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4865$828_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4975$835_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4976$836_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4867$830_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4868$831_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4978$838_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4979$839_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4870$833_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4871$834_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4872$839_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4872$837_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4872$835_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4873$844_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4873$842_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4873$840_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4882$850_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4882$848_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4882$846_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4883$855_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4883$853_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4883$851_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:4892$861_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:4892$859_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:4892$857_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:4893$866_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:4893$864_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:4893$862_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:4902$872_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:4902$870_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:4902$868_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:4903$877_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:4903$875_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:4903$873_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4981$841_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4982$842_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4983$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4983$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4983$843_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4984$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4984$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4984$848_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4993$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4993$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4993$854_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4994$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4994$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4994$859_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5003$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5003$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5003$865_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5004$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5004$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5004$870_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5013$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5013$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5013$876_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5014$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5014$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5014$881_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:4999$893_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5110$901_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5009$896_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5120$904_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5019$899_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5130$907_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5029$902_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5140$910_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5054$914_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5054$912_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5054$910_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5055$919_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5055$917_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5055$915_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5064$925_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5064$923_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5064$921_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5065$930_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5065$928_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5065$926_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5074$936_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5074$934_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5074$932_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5075$941_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5075$939_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5075$937_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5084$947_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5084$945_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5084$943_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5085$952_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5085$950_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5085$948_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5165$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5165$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5165$918_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5166$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5166$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5166$923_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5175$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5175$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5175$929_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5176$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5176$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5176$934_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5185$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5185$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5185$940_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5186$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5186$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5186$945_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5195$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5195$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5195$951_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5196$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5196$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5196$956_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -276429,20 +282367,20 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5321$982_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5322$983_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5432$990_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5433$991_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5325$984_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5326$985_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5436$992_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5437$993_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5332$987_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5443$995_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5334$988_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5445$996_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 @@ -276452,7 +282390,7 @@ module \ls180 connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5344$989_Y + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5455$997_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -276471,18 +282409,18 @@ module \ls180 connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5403$996_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5514$1004_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5484$1004_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5485$1005_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5595$1012_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5596$1013_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5487$1006_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5488$1007_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5489$1008_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5598$1014_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5599$1015_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5600$1016_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -276497,22 +282435,12 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5529$1013_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5530$1014_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5640$1021_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5641$1022_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5533$1015_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5534$1016_Y - connect \libresocsim_start0 \libresocsim_start1 - connect \libresocsim_length0 \libresocsim_length1 - connect \libresocsim_mosi \libresocsim_mosi_storage - connect \libresocsim_done1 \libresocsim_done0 - connect \libresocsim_miso_status \libresocsim_miso - connect \libresocsim_cs \libresocsim_cs_storage - connect \libresocsim_loopback \libresocsim_loopback_storage - connect \libresocsim_clk_rise $eq$ls180.v:5542$1018_Y - connect \libresocsim_clk_fall $eq$ls180.v:5543$1020_Y - connect \libresocsim_clk_divider0 \libresocsim_storage + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5644$1023_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5645$1024_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 connect \builder_shared_sel \builder_comb_rhs_array_muxed26 @@ -276526,16 +282454,16 @@ module \ls180 connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r connect \main_interface0_bus_dat_r \builder_shared_dat_r connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5644$1030_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5645$1032_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5646$1034_Y - connect \main_interface0_bus_ack $and$ls180.v:5647$1036_Y - connect \main_interface1_bus_ack $and$ls180.v:5648$1038_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5649$1040_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5650$1042_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5651$1044_Y - connect \main_interface0_bus_err $and$ls180.v:5652$1046_Y - connect \main_interface1_bus_err $and$ls180.v:5653$1048_Y + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5696$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5697$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5698$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5699$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5700$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5701$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5702$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5703$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5704$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5705$1048_Y connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w @@ -276572,42 +282500,42 @@ module \ls180 connect \builder_libresocsim_wishbone_we \builder_shared_we connect \builder_libresocsim_wishbone_cti \builder_shared_cti connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5698$1055_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5699$1056_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5700$1057_Y - connect \main_wb_sdram_cyc $and$ls180.v:5701$1058_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5702$1059_Y - connect \builder_shared_err $or$ls180.v:5703$1063_Y - connect \builder_wait $and$ls180.v:5704$1066_Y - connect \builder_done $eq$ls180.v:5717$1081_Y - connect \builder_csrbank0_sel $eq$ls180.v:5718$1082_Y + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5750$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5751$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5752$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5753$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5754$1059_Y + connect \builder_shared_err $or$ls180.v:5755$1063_Y + connect \builder_wait $and$ls180.v:5756$1066_Y + connect \builder_done $eq$ls180.v:5769$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5770$1082_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5720$1085_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5721$1089_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:5772$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5773$1089_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5723$1092_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5724$1096_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:5775$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5776$1096_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5726$1099_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5727$1103_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:5778$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5779$1103_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5729$1106_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5730$1110_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:5781$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5782$1110_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5732$1113_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5733$1117_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:5784$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5785$1117_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5735$1120_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5736$1124_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5787$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5788$1124_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5738$1127_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5739$1131_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5790$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5791$1131_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5741$1134_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5742$1138_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5793$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5794$1138_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5744$1141_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5745$1145_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5796$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5797$1145_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -276618,25 +282546,25 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5756$1146_Y + connect \builder_csrbank1_sel $eq$ls180.v:5808$1146_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5758$1149_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5759$1153_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:5810$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5811$1153_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5761$1156_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5762$1160_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:5813$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5814$1160_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5764$1163_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5765$1167_Y + connect \builder_csrbank1_in1_re $and$ls180.v:5816$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5817$1167_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5767$1170_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5768$1174_Y + connect \builder_csrbank1_in0_re $and$ls180.v:5819$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5820$1174_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5770$1177_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5771$1181_Y + connect \builder_csrbank1_out1_re $and$ls180.v:5822$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5823$1181_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5773$1184_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5774$1188_Y + connect \builder_csrbank1_out0_re $and$ls180.v:5825$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5826$1188_Y connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] connect \builder_csrbank1_in1_w \main_gpio_status [15:8] @@ -276644,613 +282572,627 @@ module \ls180 connect \main_gpio_we \builder_csrbank1_in0_we connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5782$1189_Y - connect \builder_csrbank2_enable0_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_enable0_re $and$ls180.v:5784$1192_Y - connect \builder_csrbank2_enable0_we $and$ls180.v:5785$1196_Y - connect \builder_csrbank2_width3_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width3_re $and$ls180.v:5787$1199_Y - connect \builder_csrbank2_width3_we $and$ls180.v:5788$1203_Y - connect \builder_csrbank2_width2_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width2_re $and$ls180.v:5790$1206_Y - connect \builder_csrbank2_width2_we $and$ls180.v:5791$1210_Y - connect \builder_csrbank2_width1_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width1_re $and$ls180.v:5793$1213_Y - connect \builder_csrbank2_width1_we $and$ls180.v:5794$1217_Y - connect \builder_csrbank2_width0_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_width0_re $and$ls180.v:5796$1220_Y - connect \builder_csrbank2_width0_we $and$ls180.v:5797$1224_Y - connect \builder_csrbank2_period3_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period3_re $and$ls180.v:5799$1227_Y - connect \builder_csrbank2_period3_we $and$ls180.v:5800$1231_Y - connect \builder_csrbank2_period2_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period2_re $and$ls180.v:5802$1234_Y - connect \builder_csrbank2_period2_we $and$ls180.v:5803$1238_Y - connect \builder_csrbank2_period1_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period1_re $and$ls180.v:5805$1241_Y - connect \builder_csrbank2_period1_we $and$ls180.v:5806$1245_Y - connect \builder_csrbank2_period0_r \builder_interface2_bank_bus_dat_w - connect \builder_csrbank2_period0_re $and$ls180.v:5808$1248_Y - connect \builder_csrbank2_period0_we $and$ls180.v:5809$1252_Y - connect \builder_csrbank2_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank2_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank2_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank2_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank2_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank2_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank2_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank2_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank2_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank3_sel $eq$ls180.v:5819$1253_Y + connect \builder_csrbank2_sel $eq$ls180.v:5834$1189_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:5836$1192_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5837$1196_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:5839$1199_Y + connect \builder_csrbank2_r_we $and$ls180.v:5840$1203_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:5848$1204_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5821$1256_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5822$1260_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:5850$1207_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5851$1211_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5824$1263_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5825$1267_Y + connect \builder_csrbank3_width3_re $and$ls180.v:5853$1214_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5854$1218_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5827$1270_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5828$1274_Y + connect \builder_csrbank3_width2_re $and$ls180.v:5856$1221_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5857$1225_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5830$1277_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5831$1281_Y + connect \builder_csrbank3_width1_re $and$ls180.v:5859$1228_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5860$1232_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5833$1284_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5834$1288_Y + connect \builder_csrbank3_width0_re $and$ls180.v:5862$1235_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5863$1239_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5836$1291_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5837$1295_Y + connect \builder_csrbank3_period3_re $and$ls180.v:5865$1242_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5866$1246_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5839$1298_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5840$1302_Y + connect \builder_csrbank3_period2_re $and$ls180.v:5868$1249_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5869$1253_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5842$1305_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5843$1309_Y + connect \builder_csrbank3_period1_re $and$ls180.v:5871$1256_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5872$1260_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5845$1312_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5846$1316_Y - connect \builder_csrbank3_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank3_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5856$1317_Y - connect \builder_csrbank4_dma_base7_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base7_re $and$ls180.v:5858$1320_Y - connect \builder_csrbank4_dma_base7_we $and$ls180.v:5859$1324_Y - connect \builder_csrbank4_dma_base6_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base6_re $and$ls180.v:5861$1327_Y - connect \builder_csrbank4_dma_base6_we $and$ls180.v:5862$1331_Y - connect \builder_csrbank4_dma_base5_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base5_re $and$ls180.v:5864$1334_Y - connect \builder_csrbank4_dma_base5_we $and$ls180.v:5865$1338_Y - connect \builder_csrbank4_dma_base4_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base4_re $and$ls180.v:5867$1341_Y - connect \builder_csrbank4_dma_base4_we $and$ls180.v:5868$1345_Y - connect \builder_csrbank4_dma_base3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base3_re $and$ls180.v:5870$1348_Y - connect \builder_csrbank4_dma_base3_we $and$ls180.v:5871$1352_Y - connect \builder_csrbank4_dma_base2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base2_re $and$ls180.v:5873$1355_Y - connect \builder_csrbank4_dma_base2_we $and$ls180.v:5874$1359_Y - connect \builder_csrbank4_dma_base1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base1_re $and$ls180.v:5876$1362_Y - connect \builder_csrbank4_dma_base1_we $and$ls180.v:5877$1366_Y - connect \builder_csrbank4_dma_base0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_base0_re $and$ls180.v:5879$1369_Y - connect \builder_csrbank4_dma_base0_we $and$ls180.v:5880$1373_Y - connect \builder_csrbank4_dma_length3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length3_re $and$ls180.v:5882$1376_Y - connect \builder_csrbank4_dma_length3_we $and$ls180.v:5883$1380_Y - connect \builder_csrbank4_dma_length2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length2_re $and$ls180.v:5885$1383_Y - connect \builder_csrbank4_dma_length2_we $and$ls180.v:5886$1387_Y - connect \builder_csrbank4_dma_length1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length1_re $and$ls180.v:5888$1390_Y - connect \builder_csrbank4_dma_length1_we $and$ls180.v:5889$1394_Y - connect \builder_csrbank4_dma_length0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_dma_length0_re $and$ls180.v:5891$1397_Y - connect \builder_csrbank4_dma_length0_we $and$ls180.v:5892$1401_Y - connect \builder_csrbank4_dma_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_enable0_re $and$ls180.v:5894$1404_Y - connect \builder_csrbank4_dma_enable0_we $and$ls180.v:5895$1408_Y - connect \builder_csrbank4_dma_done_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_done_re $and$ls180.v:5897$1411_Y - connect \builder_csrbank4_dma_done_we $and$ls180.v:5898$1415_Y - connect \builder_csrbank4_dma_loop0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_dma_loop0_re $and$ls180.v:5900$1418_Y - connect \builder_csrbank4_dma_loop0_we $and$ls180.v:5901$1422_Y - connect \builder_csrbank4_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank4_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank4_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank4_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank4_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank4_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank4_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank4_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank4_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank4_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank4_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank4_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank4_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank4_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank4_dma_done_we - connect \builder_csrbank4_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank5_sel $eq$ls180.v:5918$1423_Y - connect \builder_csrbank5_cmd_argument3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument3_re $and$ls180.v:5920$1426_Y - connect \builder_csrbank5_cmd_argument3_we $and$ls180.v:5921$1430_Y - connect \builder_csrbank5_cmd_argument2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument2_re $and$ls180.v:5923$1433_Y - connect \builder_csrbank5_cmd_argument2_we $and$ls180.v:5924$1437_Y - connect \builder_csrbank5_cmd_argument1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument1_re $and$ls180.v:5926$1440_Y - connect \builder_csrbank5_cmd_argument1_we $and$ls180.v:5927$1444_Y - connect \builder_csrbank5_cmd_argument0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_argument0_re $and$ls180.v:5929$1447_Y - connect \builder_csrbank5_cmd_argument0_we $and$ls180.v:5930$1451_Y - connect \builder_csrbank5_cmd_command3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command3_re $and$ls180.v:5932$1454_Y - connect \builder_csrbank5_cmd_command3_we $and$ls180.v:5933$1458_Y - connect \builder_csrbank5_cmd_command2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command2_re $and$ls180.v:5935$1461_Y - connect \builder_csrbank5_cmd_command2_we $and$ls180.v:5936$1465_Y - connect \builder_csrbank5_cmd_command1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command1_re $and$ls180.v:5938$1468_Y - connect \builder_csrbank5_cmd_command1_we $and$ls180.v:5939$1472_Y - connect \builder_csrbank5_cmd_command0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_command0_re $and$ls180.v:5941$1475_Y - connect \builder_csrbank5_cmd_command0_we $and$ls180.v:5942$1479_Y - connect \main_sdcore_cmd_send_r \builder_interface5_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:5944$1482_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:5945$1486_Y - connect \builder_csrbank5_cmd_response15_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response15_re $and$ls180.v:5947$1489_Y - connect \builder_csrbank5_cmd_response15_we $and$ls180.v:5948$1493_Y - connect \builder_csrbank5_cmd_response14_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response14_re $and$ls180.v:5950$1496_Y - connect \builder_csrbank5_cmd_response14_we $and$ls180.v:5951$1500_Y - connect \builder_csrbank5_cmd_response13_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response13_re $and$ls180.v:5953$1503_Y - connect \builder_csrbank5_cmd_response13_we $and$ls180.v:5954$1507_Y - connect \builder_csrbank5_cmd_response12_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response12_re $and$ls180.v:5956$1510_Y - connect \builder_csrbank5_cmd_response12_we $and$ls180.v:5957$1514_Y - connect \builder_csrbank5_cmd_response11_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response11_re $and$ls180.v:5959$1517_Y - connect \builder_csrbank5_cmd_response11_we $and$ls180.v:5960$1521_Y - connect \builder_csrbank5_cmd_response10_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response10_re $and$ls180.v:5962$1524_Y - connect \builder_csrbank5_cmd_response10_we $and$ls180.v:5963$1528_Y - connect \builder_csrbank5_cmd_response9_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response9_re $and$ls180.v:5965$1531_Y - connect \builder_csrbank5_cmd_response9_we $and$ls180.v:5966$1535_Y - connect \builder_csrbank5_cmd_response8_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response8_re $and$ls180.v:5968$1538_Y - connect \builder_csrbank5_cmd_response8_we $and$ls180.v:5969$1542_Y - connect \builder_csrbank5_cmd_response7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response7_re $and$ls180.v:5971$1545_Y - connect \builder_csrbank5_cmd_response7_we $and$ls180.v:5972$1549_Y - connect \builder_csrbank5_cmd_response6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response6_re $and$ls180.v:5974$1552_Y - connect \builder_csrbank5_cmd_response6_we $and$ls180.v:5975$1556_Y - connect \builder_csrbank5_cmd_response5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response5_re $and$ls180.v:5977$1559_Y - connect \builder_csrbank5_cmd_response5_we $and$ls180.v:5978$1563_Y - connect \builder_csrbank5_cmd_response4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response4_re $and$ls180.v:5980$1566_Y - connect \builder_csrbank5_cmd_response4_we $and$ls180.v:5981$1570_Y - connect \builder_csrbank5_cmd_response3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response3_re $and$ls180.v:5983$1573_Y - connect \builder_csrbank5_cmd_response3_we $and$ls180.v:5984$1577_Y - connect \builder_csrbank5_cmd_response2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response2_re $and$ls180.v:5986$1580_Y - connect \builder_csrbank5_cmd_response2_we $and$ls180.v:5987$1584_Y - connect \builder_csrbank5_cmd_response1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response1_re $and$ls180.v:5989$1587_Y - connect \builder_csrbank5_cmd_response1_we $and$ls180.v:5990$1591_Y - connect \builder_csrbank5_cmd_response0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_cmd_response0_re $and$ls180.v:5992$1594_Y - connect \builder_csrbank5_cmd_response0_we $and$ls180.v:5993$1598_Y - connect \builder_csrbank5_cmd_event_r \builder_interface5_bank_bus_dat_w [3:0] - connect \builder_csrbank5_cmd_event_re $and$ls180.v:5995$1601_Y - connect \builder_csrbank5_cmd_event_we $and$ls180.v:5996$1605_Y - connect \builder_csrbank5_data_event_r \builder_interface5_bank_bus_dat_w [3:0] - connect \builder_csrbank5_data_event_re $and$ls180.v:5998$1608_Y - connect \builder_csrbank5_data_event_we $and$ls180.v:5999$1612_Y - connect \builder_csrbank5_block_length1_r \builder_interface5_bank_bus_dat_w [1:0] - connect \builder_csrbank5_block_length1_re $and$ls180.v:6001$1615_Y - connect \builder_csrbank5_block_length1_we $and$ls180.v:6002$1619_Y - connect \builder_csrbank5_block_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_length0_re $and$ls180.v:6004$1622_Y - connect \builder_csrbank5_block_length0_we $and$ls180.v:6005$1626_Y - connect \builder_csrbank5_block_count3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count3_re $and$ls180.v:6007$1629_Y - connect \builder_csrbank5_block_count3_we $and$ls180.v:6008$1633_Y - connect \builder_csrbank5_block_count2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count2_re $and$ls180.v:6010$1636_Y - connect \builder_csrbank5_block_count2_we $and$ls180.v:6011$1640_Y - connect \builder_csrbank5_block_count1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count1_re $and$ls180.v:6013$1643_Y - connect \builder_csrbank5_block_count1_we $and$ls180.v:6014$1647_Y - connect \builder_csrbank5_block_count0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_block_count0_re $and$ls180.v:6016$1650_Y - connect \builder_csrbank5_block_count0_we $and$ls180.v:6017$1654_Y - connect \builder_csrbank5_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank5_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank5_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank5_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank5_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank5_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank5_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank5_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank5_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank5_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank5_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank5_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank5_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank5_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank5_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank5_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank5_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank5_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank5_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank5_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank5_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank5_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank5_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank5_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank5_cmd_response0_we - connect \builder_csrbank5_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank5_cmd_event_we - connect \builder_csrbank5_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank5_data_event_we - connect \builder_csrbank5_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank5_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank5_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank5_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank5_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank5_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank6_sel $eq$ls180.v:6053$1655_Y - connect \builder_csrbank6_dma_base7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base7_re $and$ls180.v:6055$1658_Y - connect \builder_csrbank6_dma_base7_we $and$ls180.v:6056$1662_Y - connect \builder_csrbank6_dma_base6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base6_re $and$ls180.v:6058$1665_Y - connect \builder_csrbank6_dma_base6_we $and$ls180.v:6059$1669_Y - connect \builder_csrbank6_dma_base5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base5_re $and$ls180.v:6061$1672_Y - connect \builder_csrbank6_dma_base5_we $and$ls180.v:6062$1676_Y - connect \builder_csrbank6_dma_base4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base4_re $and$ls180.v:6064$1679_Y - connect \builder_csrbank6_dma_base4_we $and$ls180.v:6065$1683_Y - connect \builder_csrbank6_dma_base3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base3_re $and$ls180.v:6067$1686_Y - connect \builder_csrbank6_dma_base3_we $and$ls180.v:6068$1690_Y - connect \builder_csrbank6_dma_base2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base2_re $and$ls180.v:6070$1693_Y - connect \builder_csrbank6_dma_base2_we $and$ls180.v:6071$1697_Y - connect \builder_csrbank6_dma_base1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base1_re $and$ls180.v:6073$1700_Y - connect \builder_csrbank6_dma_base1_we $and$ls180.v:6074$1704_Y - connect \builder_csrbank6_dma_base0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_base0_re $and$ls180.v:6076$1707_Y - connect \builder_csrbank6_dma_base0_we $and$ls180.v:6077$1711_Y - connect \builder_csrbank6_dma_length3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length3_re $and$ls180.v:6079$1714_Y - connect \builder_csrbank6_dma_length3_we $and$ls180.v:6080$1718_Y - connect \builder_csrbank6_dma_length2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length2_re $and$ls180.v:6082$1721_Y - connect \builder_csrbank6_dma_length2_we $and$ls180.v:6083$1725_Y - connect \builder_csrbank6_dma_length1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length1_re $and$ls180.v:6085$1728_Y - connect \builder_csrbank6_dma_length1_we $and$ls180.v:6086$1732_Y - connect \builder_csrbank6_dma_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_length0_re $and$ls180.v:6088$1735_Y - connect \builder_csrbank6_dma_length0_we $and$ls180.v:6089$1739_Y - connect \builder_csrbank6_dma_enable0_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_enable0_re $and$ls180.v:6091$1742_Y - connect \builder_csrbank6_dma_enable0_we $and$ls180.v:6092$1746_Y - connect \builder_csrbank6_dma_done_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_done_re $and$ls180.v:6094$1749_Y - connect \builder_csrbank6_dma_done_we $and$ls180.v:6095$1753_Y - connect \builder_csrbank6_dma_loop0_r \builder_interface6_bank_bus_dat_w [0] - connect \builder_csrbank6_dma_loop0_re $and$ls180.v:6097$1756_Y - connect \builder_csrbank6_dma_loop0_we $and$ls180.v:6098$1760_Y - connect \builder_csrbank6_dma_offset3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset3_re $and$ls180.v:6100$1763_Y - connect \builder_csrbank6_dma_offset3_we $and$ls180.v:6101$1767_Y - connect \builder_csrbank6_dma_offset2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset2_re $and$ls180.v:6103$1770_Y - connect \builder_csrbank6_dma_offset2_we $and$ls180.v:6104$1774_Y - connect \builder_csrbank6_dma_offset1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset1_re $and$ls180.v:6106$1777_Y - connect \builder_csrbank6_dma_offset1_we $and$ls180.v:6107$1781_Y - connect \builder_csrbank6_dma_offset0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_dma_offset0_re $and$ls180.v:6109$1784_Y - connect \builder_csrbank6_dma_offset0_we $and$ls180.v:6110$1788_Y - connect \builder_csrbank6_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank6_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank6_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank6_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank6_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank6_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank6_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank6_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank6_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank6_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank6_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank6_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank6_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank6_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank6_dma_done_we - connect \builder_csrbank6_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank6_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank6_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank6_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank6_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank6_dma_offset0_we - connect \builder_csrbank7_sel $eq$ls180.v:6132$1789_Y - connect \builder_csrbank7_card_detect_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_card_detect_re $and$ls180.v:6134$1792_Y - connect \builder_csrbank7_card_detect_we $and$ls180.v:6135$1796_Y - connect \builder_csrbank7_clocker_divider1_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_clocker_divider1_re $and$ls180.v:6137$1799_Y - connect \builder_csrbank7_clocker_divider1_we $and$ls180.v:6138$1803_Y - connect \builder_csrbank7_clocker_divider0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_clocker_divider0_re $and$ls180.v:6140$1806_Y - connect \builder_csrbank7_clocker_divider0_we $and$ls180.v:6141$1810_Y - connect \main_sdphy_init_initialize_r \builder_interface7_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6143$1813_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6144$1817_Y - connect \builder_csrbank7_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank7_card_detect_we - connect \builder_csrbank7_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank7_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank8_sel $eq$ls180.v:6149$1818_Y - connect \builder_csrbank8_dfii_control0_r \builder_interface8_bank_bus_dat_w [3:0] - connect \builder_csrbank8_dfii_control0_re $and$ls180.v:6151$1821_Y - connect \builder_csrbank8_dfii_control0_we $and$ls180.v:6152$1825_Y - connect \builder_csrbank8_dfii_pi0_command0_r \builder_interface8_bank_bus_dat_w [5:0] - connect \builder_csrbank8_dfii_pi0_command0_re $and$ls180.v:6154$1828_Y - connect \builder_csrbank8_dfii_pi0_command0_we $and$ls180.v:6155$1832_Y - connect \main_sdram_command_issue_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6157$1835_Y - connect \main_sdram_command_issue_we $and$ls180.v:6158$1839_Y - connect \builder_csrbank8_dfii_pi0_address1_r \builder_interface8_bank_bus_dat_w [4:0] - connect \builder_csrbank8_dfii_pi0_address1_re $and$ls180.v:6160$1842_Y - connect \builder_csrbank8_dfii_pi0_address1_we $and$ls180.v:6161$1846_Y - connect \builder_csrbank8_dfii_pi0_address0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_address0_re $and$ls180.v:6163$1849_Y - connect \builder_csrbank8_dfii_pi0_address0_we $and$ls180.v:6164$1853_Y - connect \builder_csrbank8_dfii_pi0_baddress0_r \builder_interface8_bank_bus_dat_w [1:0] - connect \builder_csrbank8_dfii_pi0_baddress0_re $and$ls180.v:6166$1856_Y - connect \builder_csrbank8_dfii_pi0_baddress0_we $and$ls180.v:6167$1860_Y - connect \builder_csrbank8_dfii_pi0_wrdata1_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_wrdata1_re $and$ls180.v:6169$1863_Y - connect \builder_csrbank8_dfii_pi0_wrdata1_we $and$ls180.v:6170$1867_Y - connect \builder_csrbank8_dfii_pi0_wrdata0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_wrdata0_re $and$ls180.v:6172$1870_Y - connect \builder_csrbank8_dfii_pi0_wrdata0_we $and$ls180.v:6173$1874_Y - connect \builder_csrbank8_dfii_pi0_rddata1_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_rddata1_re $and$ls180.v:6175$1877_Y - connect \builder_csrbank8_dfii_pi0_rddata1_we $and$ls180.v:6176$1881_Y - connect \builder_csrbank8_dfii_pi0_rddata0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_dfii_pi0_rddata0_re $and$ls180.v:6178$1884_Y - connect \builder_csrbank8_dfii_pi0_rddata0_we $and$ls180.v:6179$1888_Y + connect \builder_csrbank3_period0_re $and$ls180.v:5874$1263_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5875$1267_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5885$1268_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:5887$1271_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:5888$1275_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:5890$1278_Y + connect \builder_csrbank4_width3_we $and$ls180.v:5891$1282_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:5893$1285_Y + connect \builder_csrbank4_width2_we $and$ls180.v:5894$1289_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:5896$1292_Y + connect \builder_csrbank4_width1_we $and$ls180.v:5897$1296_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:5899$1299_Y + connect \builder_csrbank4_width0_we $and$ls180.v:5900$1303_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:5902$1306_Y + connect \builder_csrbank4_period3_we $and$ls180.v:5903$1310_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:5905$1313_Y + connect \builder_csrbank4_period2_we $and$ls180.v:5906$1317_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:5908$1320_Y + connect \builder_csrbank4_period1_we $and$ls180.v:5909$1324_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:5911$1327_Y + connect \builder_csrbank4_period0_we $and$ls180.v:5912$1331_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:5922$1332_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:5924$1335_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:5925$1339_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:5927$1342_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:5928$1346_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:5930$1349_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:5931$1353_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:5933$1356_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:5934$1360_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:5936$1363_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:5937$1367_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:5939$1370_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:5940$1374_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:5942$1377_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:5943$1381_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:5945$1384_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:5946$1388_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:5948$1391_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:5949$1395_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:5951$1398_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:5952$1402_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:5954$1405_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:5955$1409_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:5957$1412_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:5958$1416_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5960$1419_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5961$1423_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:5963$1426_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:5964$1430_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5966$1433_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5967$1437_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:5984$1438_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5986$1441_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5987$1445_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5989$1448_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5990$1452_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5992$1455_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5993$1459_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5995$1462_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5996$1466_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5998$1469_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5999$1473_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6001$1476_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6002$1480_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6004$1483_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6005$1487_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6007$1490_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6008$1494_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6010$1497_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6011$1501_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6013$1504_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6014$1508_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6016$1511_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6017$1515_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6019$1518_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6020$1522_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6022$1525_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6023$1529_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6025$1532_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6026$1536_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6028$1539_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6029$1543_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6031$1546_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6032$1550_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6034$1553_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6035$1557_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6037$1560_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6038$1564_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6040$1567_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6041$1571_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6043$1574_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6044$1578_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6046$1581_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6047$1585_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6049$1588_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6050$1592_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6052$1595_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6053$1599_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6055$1602_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6056$1606_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6058$1609_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6059$1613_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6061$1616_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6062$1620_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6064$1623_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6065$1627_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6067$1630_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6068$1634_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6070$1637_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6071$1641_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6073$1644_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6074$1648_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6076$1651_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6077$1655_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6079$1658_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6080$1662_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6082$1665_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6083$1669_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6119$1670_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6121$1673_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6122$1677_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6124$1680_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6125$1684_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6127$1687_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6128$1691_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6130$1694_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6131$1698_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6133$1701_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6134$1705_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6136$1708_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6137$1712_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6139$1715_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6140$1719_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6142$1722_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6143$1726_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6145$1729_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6146$1733_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6148$1736_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6149$1740_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6151$1743_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6152$1747_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6154$1750_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6155$1754_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6157$1757_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6158$1761_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6160$1764_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6161$1768_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6163$1771_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6164$1775_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6166$1778_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6167$1782_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6169$1785_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6170$1789_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6172$1792_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6173$1796_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6175$1799_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6176$1803_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6198$1804_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6200$1807_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6201$1811_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6203$1814_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6204$1818_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6206$1821_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6207$1825_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6209$1828_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6210$1832_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6215$1833_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6217$1836_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6218$1840_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6220$1843_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6221$1847_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6223$1850_Y + connect \main_sdram_command_issue_we $and$ls180.v:6224$1854_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6226$1857_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6227$1861_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6229$1864_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6230$1868_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6232$1871_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6233$1875_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6235$1878_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6236$1882_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6238$1885_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6239$1889_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6241$1892_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6242$1896_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6244$1899_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6245$1903_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank8_dfii_control0_w \main_sdram_storage - connect \builder_csrbank8_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank8_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank8_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank8_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank8_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank8_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank8_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank8_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank8_dfii_pi0_rddata0_we - connect \builder_csrbank9_sel $eq$ls180.v:6194$1889_Y - connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control1_re $and$ls180.v:6196$1892_Y - connect \builder_csrbank9_control1_we $and$ls180.v:6197$1896_Y - connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_control0_re $and$ls180.v:6199$1899_Y - connect \builder_csrbank9_control0_we $and$ls180.v:6200$1903_Y - connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_status_re $and$ls180.v:6202$1906_Y - connect \builder_csrbank9_status_we $and$ls180.v:6203$1910_Y - connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_mosi0_re $and$ls180.v:6205$1913_Y - connect \builder_csrbank9_mosi0_we $and$ls180.v:6206$1917_Y - connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_miso_re $and$ls180.v:6208$1920_Y - connect \builder_csrbank9_miso_we $and$ls180.v:6209$1924_Y - connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_cs0_re $and$ls180.v:6211$1927_Y - connect \builder_csrbank9_cs0_we $and$ls180.v:6212$1931_Y - connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] - connect \builder_csrbank9_loopback0_re $and$ls180.v:6214$1934_Y - connect \builder_csrbank9_loopback0_we $and$ls180.v:6215$1938_Y - connect \main_spi_master_length1 \main_spi_master_control_storage [15:8] - connect \builder_csrbank9_control1_w \main_spi_master_control_storage [15:8] - connect \builder_csrbank9_control0_w \main_spi_master_control_storage [7:0] - connect \main_spi_master_status_status \main_spi_master_done1 - connect \builder_csrbank9_status_w \main_spi_master_status_status - connect \main_spi_master_status_we \builder_csrbank9_status_we - connect \builder_csrbank9_mosi0_w \main_spi_master_mosi_storage - connect \builder_csrbank9_miso_w \main_spi_master_miso_status - connect \main_spi_master_miso_we \builder_csrbank9_miso_we - connect \main_spi_master_sel \main_spi_master_cs_storage - connect \builder_csrbank9_cs0_w \main_spi_master_cs_storage - connect \builder_csrbank9_loopback0_w \main_spi_master_loopback_storage - connect \builder_csrbank10_sel $eq$ls180.v:6234$1940_Y + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6260$1904_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6236$1943_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6237$1947_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6262$1907_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6263$1911_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6239$1950_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6240$1954_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6265$1914_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6266$1918_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6242$1957_Y - connect \builder_csrbank10_status_we $and$ls180.v:6243$1961_Y + connect \builder_csrbank10_status_re $and$ls180.v:6268$1921_Y + connect \builder_csrbank10_status_we $and$ls180.v:6269$1925_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6245$1964_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6246$1968_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6271$1928_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6272$1932_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6248$1971_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6249$1975_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6274$1935_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6275$1939_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6251$1978_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6252$1982_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6277$1942_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6278$1946_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6254$1985_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6255$1989_Y - connect \builder_csrbank10_clk_divider1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_clk_divider1_re $and$ls180.v:6257$1992_Y - connect \builder_csrbank10_clk_divider1_we $and$ls180.v:6258$1996_Y - connect \builder_csrbank10_clk_divider0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_clk_divider0_re $and$ls180.v:6260$1999_Y - connect \builder_csrbank10_clk_divider0_we $and$ls180.v:6261$2003_Y - connect \libresocsim_length1 \libresocsim_control_storage [15:8] - connect \builder_csrbank10_control1_w \libresocsim_control_storage [15:8] - connect \builder_csrbank10_control0_w \libresocsim_control_storage [7:0] - connect \libresocsim_status_status \libresocsim_done1 - connect \builder_csrbank10_status_w \libresocsim_status_status - connect \libresocsim_status_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \libresocsim_mosi_storage - connect \builder_csrbank10_miso_w \libresocsim_miso_status - connect \libresocsim_miso_we \builder_csrbank10_miso_we - connect \libresocsim_sel \libresocsim_cs_storage - connect \builder_csrbank10_cs0_w \libresocsim_cs_storage - connect \builder_csrbank10_loopback0_w \libresocsim_loopback_storage - connect \builder_csrbank10_clk_divider1_w \libresocsim_storage [15:8] - connect \builder_csrbank10_clk_divider0_w \libresocsim_storage [7:0] - connect \builder_csrbank11_sel $eq$ls180.v:6282$2005_Y - connect \builder_csrbank11_load3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load3_re $and$ls180.v:6284$2008_Y - connect \builder_csrbank11_load3_we $and$ls180.v:6285$2012_Y - connect \builder_csrbank11_load2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load2_re $and$ls180.v:6287$2015_Y - connect \builder_csrbank11_load2_we $and$ls180.v:6288$2019_Y - connect \builder_csrbank11_load1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load1_re $and$ls180.v:6290$2022_Y - connect \builder_csrbank11_load1_we $and$ls180.v:6291$2026_Y - connect \builder_csrbank11_load0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_load0_re $and$ls180.v:6293$2029_Y - connect \builder_csrbank11_load0_we $and$ls180.v:6294$2033_Y - connect \builder_csrbank11_reload3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload3_re $and$ls180.v:6296$2036_Y - connect \builder_csrbank11_reload3_we $and$ls180.v:6297$2040_Y - connect \builder_csrbank11_reload2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload2_re $and$ls180.v:6299$2043_Y - connect \builder_csrbank11_reload2_we $and$ls180.v:6300$2047_Y - connect \builder_csrbank11_reload1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload1_re $and$ls180.v:6302$2050_Y - connect \builder_csrbank11_reload1_we $and$ls180.v:6303$2054_Y - connect \builder_csrbank11_reload0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_reload0_re $and$ls180.v:6305$2057_Y - connect \builder_csrbank11_reload0_we $and$ls180.v:6306$2061_Y - connect \builder_csrbank11_en0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_en0_re $and$ls180.v:6308$2064_Y - connect \builder_csrbank11_en0_we $and$ls180.v:6309$2068_Y - connect \builder_csrbank11_update_value0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_update_value0_re $and$ls180.v:6311$2071_Y - connect \builder_csrbank11_update_value0_we $and$ls180.v:6312$2075_Y - connect \builder_csrbank11_value3_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value3_re $and$ls180.v:6314$2078_Y - connect \builder_csrbank11_value3_we $and$ls180.v:6315$2082_Y - connect \builder_csrbank11_value2_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value2_re $and$ls180.v:6317$2085_Y - connect \builder_csrbank11_value2_we $and$ls180.v:6318$2089_Y - connect \builder_csrbank11_value1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value1_re $and$ls180.v:6320$2092_Y - connect \builder_csrbank11_value1_we $and$ls180.v:6321$2096_Y - connect \builder_csrbank11_value0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_value0_re $and$ls180.v:6323$2099_Y - connect \builder_csrbank11_value0_we $and$ls180.v:6324$2103_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface11_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6326$2106_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6327$2110_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6329$2113_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6330$2117_Y - connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_ev_enable0_re $and$ls180.v:6332$2120_Y - connect \builder_csrbank11_ev_enable0_we $and$ls180.v:6333$2124_Y - connect \builder_csrbank11_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank11_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank11_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank11_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank11_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank11_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank11_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank11_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank11_en0_w \main_libresocsim_en_storage - connect \builder_csrbank11_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank11_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank11_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank11_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank11_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank11_value0_we - connect \builder_csrbank11_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank12_sel $eq$ls180.v:6350$2125_Y - connect \main_uart_rxtx_r \builder_interface12_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6352$2128_Y - connect \main_uart_rxtx_we $and$ls180.v:6353$2132_Y - connect \builder_csrbank12_txfull_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_txfull_re $and$ls180.v:6355$2135_Y - connect \builder_csrbank12_txfull_we $and$ls180.v:6356$2139_Y - connect \builder_csrbank12_rxempty_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_rxempty_re $and$ls180.v:6358$2142_Y - connect \builder_csrbank12_rxempty_we $and$ls180.v:6359$2146_Y - connect \main_uart_eventmanager_status_r \builder_interface12_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6361$2149_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6362$2153_Y - connect \main_uart_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6364$2156_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6365$2160_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [1:0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6367$2163_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6368$2167_Y - connect \builder_csrbank12_txempty_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_txempty_re $and$ls180.v:6370$2170_Y - connect \builder_csrbank12_txempty_we $and$ls180.v:6371$2174_Y - connect \builder_csrbank12_rxfull_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_rxfull_re $and$ls180.v:6373$2177_Y - connect \builder_csrbank12_rxfull_we $and$ls180.v:6374$2181_Y - connect \builder_csrbank12_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank12_txfull_we - connect \builder_csrbank12_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank12_rxempty_we - connect \builder_csrbank12_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank12_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank12_txempty_we - connect \builder_csrbank12_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank12_rxfull_we - connect \builder_csrbank13_sel $eq$ls180.v:6384$2182_Y - connect \builder_csrbank13_tuning_word3_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word3_re $and$ls180.v:6386$2185_Y - connect \builder_csrbank13_tuning_word3_we $and$ls180.v:6387$2189_Y - connect \builder_csrbank13_tuning_word2_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word2_re $and$ls180.v:6389$2192_Y - connect \builder_csrbank13_tuning_word2_we $and$ls180.v:6390$2196_Y - connect \builder_csrbank13_tuning_word1_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word1_re $and$ls180.v:6392$2199_Y - connect \builder_csrbank13_tuning_word1_we $and$ls180.v:6393$2203_Y - connect \builder_csrbank13_tuning_word0_r \builder_interface13_bank_bus_dat_w - connect \builder_csrbank13_tuning_word0_re $and$ls180.v:6395$2206_Y - connect \builder_csrbank13_tuning_word0_we $and$ls180.v:6396$2210_Y - connect \builder_csrbank13_tuning_word3_w \main_storage [31:24] - connect \builder_csrbank13_tuning_word2_w \main_storage [23:16] - connect \builder_csrbank13_tuning_word1_w \main_storage [15:8] - connect \builder_csrbank13_tuning_word0_w \main_storage [7:0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6280$1949_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6281$1953_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6300$1955_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6302$1958_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6303$1962_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6305$1965_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6306$1969_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6308$1972_Y + connect \builder_csrbank11_status_we $and$ls180.v:6309$1976_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6311$1979_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6312$1983_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6314$1986_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6315$1990_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6317$1993_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6318$1997_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6320$2000_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6321$2004_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6323$2007_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6324$2011_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6326$2014_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6327$2018_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6348$2020_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6350$2023_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6351$2027_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6353$2030_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6354$2034_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6356$2037_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6357$2041_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6359$2044_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6360$2048_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6362$2051_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6363$2055_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6365$2058_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6366$2062_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6368$2065_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6369$2069_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6371$2072_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6372$2076_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6374$2079_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6375$2083_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6377$2086_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6378$2090_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6380$2093_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6381$2097_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6383$2100_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6384$2104_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6386$2107_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6387$2111_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6389$2114_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6390$2118_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6392$2121_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6393$2125_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6395$2128_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6396$2132_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6398$2135_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6399$2139_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6416$2140_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6418$2143_Y + connect \main_uart_rxtx_we $and$ls180.v:6419$2147_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6421$2150_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6422$2154_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6424$2157_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6425$2161_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6427$2164_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6428$2168_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6430$2171_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6431$2175_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6433$2178_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6434$2182_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6436$2185_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6437$2189_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6439$2192_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6440$2196_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6450$2197_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6452$2200_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6453$2204_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6455$2207_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6456$2211_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6458$2214_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6459$2218_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6461$2221_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6462$2225_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] connect \builder_csr_interconnect_adr \builder_libresocsim_adr connect \builder_csr_interconnect_we \builder_libresocsim_we connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w @@ -277269,6 +283211,7 @@ module \ls180 connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we @@ -277283,6 +283226,7 @@ module \ls180 connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w @@ -277297,7 +283241,8 @@ module \ls180 connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6447$2223_Y + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6516$2239_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -277354,7 +283299,7 @@ module \ls180 connect \sdrio_clk_53 \sys_clk_1 connect \sdrio_clk_54 \sys_clk_1 connect \sdrio_clk_55 \sys_clk_1 - connect \main_rx \builder_multiregimpl0_regs1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 connect \main_pwm0_enable \main_pwm0_enable_storage connect \main_pwm0_width \main_pwm0_width_storage connect \main_pwm0_period \main_pwm0_period_storage @@ -277374,55 +283319,55 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:9989$2695_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10068$2705_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10007$2702_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10086$2712_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10021$2709_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10100$2719_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10035$2716_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10114$2726_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10049$2723_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10128$2733_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10097$2744_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10176$2754_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10111$2751_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10190$2761_DATA end -attribute \src "libresoc.v:133011.1-133069.10" +attribute \src "libresoc.v:135346.1-135404.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:133012.7-133012.20" + attribute \src "libresoc.v:135347.7-135347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133057.3-133065.6" - wire $0\q_int$next[0:0]$6560 - attribute \src "libresoc.v:133055.3-133056.27" + attribute \src "libresoc.v:135392.3-135400.6" + wire $0\q_int$next[0:0]$6819 + attribute \src "libresoc.v:135390.3-135391.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:133057.3-133065.6" - wire $1\q_int$next[0:0]$6561 - attribute \src "libresoc.v:133034.7-133034.19" + attribute \src "libresoc.v:135392.3-135400.6" + wire $1\q_int$next[0:0]$6820 + attribute \src "libresoc.v:135369.7-135369.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:133047.17-133047.96" - wire $and$libresoc.v:133047$6550_Y - attribute \src "libresoc.v:133052.17-133052.96" - wire $and$libresoc.v:133052$6555_Y - attribute \src "libresoc.v:133049.18-133049.93" - wire $not$libresoc.v:133049$6552_Y - attribute \src "libresoc.v:133051.17-133051.92" - wire $not$libresoc.v:133051$6554_Y - attribute \src "libresoc.v:133054.17-133054.92" - wire $not$libresoc.v:133054$6557_Y - attribute \src "libresoc.v:133048.18-133048.98" - wire $or$libresoc.v:133048$6551_Y - attribute \src "libresoc.v:133050.18-133050.99" - wire $or$libresoc.v:133050$6553_Y - attribute \src "libresoc.v:133053.17-133053.97" - wire $or$libresoc.v:133053$6556_Y + attribute \src "libresoc.v:135382.17-135382.96" + wire $and$libresoc.v:135382$6809_Y + attribute \src "libresoc.v:135387.17-135387.96" + wire $and$libresoc.v:135387$6814_Y + attribute \src "libresoc.v:135384.18-135384.93" + wire $not$libresoc.v:135384$6811_Y + attribute \src "libresoc.v:135386.17-135386.92" + wire $not$libresoc.v:135386$6813_Y + attribute \src "libresoc.v:135389.17-135389.92" + wire $not$libresoc.v:135389$6816_Y + attribute \src "libresoc.v:135383.18-135383.98" + wire $or$libresoc.v:135383$6810_Y + attribute \src "libresoc.v:135385.18-135385.99" + wire $or$libresoc.v:135385$6812_Y + attribute \src "libresoc.v:135388.17-135388.97" + wire $or$libresoc.v:135388$6815_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -277439,11 +283384,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:133012.7-133012.15" + attribute \src "libresoc.v:135347.7-135347.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -277460,7 +283405,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:133047$6550 + cell $and $and$libresoc.v:135382$6809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277468,10 +283413,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:133047$6550_Y + connect \Y $and$libresoc.v:135382$6809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:133052$6555 + cell $and $and$libresoc.v:135387$6814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277479,34 +283424,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:133052$6555_Y + connect \Y $and$libresoc.v:135387$6814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:133049$6552 + cell $not $not$libresoc.v:135384$6811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:133049$6552_Y + connect \Y $not$libresoc.v:135384$6811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:133051$6554 + cell $not $not$libresoc.v:135386$6813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:133051$6554_Y + connect \Y $not$libresoc.v:135386$6813_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:133054$6557 + cell $not $not$libresoc.v:135389$6816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:133054$6557_Y + connect \Y $not$libresoc.v:135389$6816_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:133048$6551 + cell $or $or$libresoc.v:135383$6810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277514,10 +283459,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:133048$6551_Y + connect \Y $or$libresoc.v:135383$6810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:133050$6553 + cell $or $or$libresoc.v:135385$6812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277525,10 +283470,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:133050$6553_Y + connect \Y $or$libresoc.v:135385$6812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:133053$6556 + cell $or $or$libresoc.v:135388$6815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277536,39 +283481,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:133053$6556_Y + connect \Y $or$libresoc.v:135388$6815_Y end - attribute \src "libresoc.v:133012.7-133012.20" - process $proc$libresoc.v:133012$6562 + attribute \src "libresoc.v:135347.7-135347.20" + process $proc$libresoc.v:135347$6821 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133034.7-133034.19" - process $proc$libresoc.v:133034$6563 + attribute \src "libresoc.v:135369.7-135369.19" + process $proc$libresoc.v:135369$6822 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:133055.3-133056.27" - process $proc$libresoc.v:133055$6558 + attribute \src "libresoc.v:135390.3-135391.27" + process $proc$libresoc.v:135390$6817 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:133057.3-133065.6" - process $proc$libresoc.v:133057$6559 + attribute \src "libresoc.v:135392.3-135400.6" + process $proc$libresoc.v:135392$6818 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6560 $1\q_int$next[0:0]$6561 - attribute \src "libresoc.v:133058.5-133058.29" + assign $0\q_int$next[0:0]$6819 $1\q_int$next[0:0]$6820 + attribute \src "libresoc.v:135393.5-135393.29" switch \initial - attribute \src "libresoc.v:133058.9-133058.17" + attribute \src "libresoc.v:135393.9-135393.17" case 1'1 case end @@ -277577,412 +283522,440 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6561 1'0 + assign $1\q_int$next[0:0]$6820 1'0 case - assign $1\q_int$next[0:0]$6561 \$5 + assign $1\q_int$next[0:0]$6820 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6560 + update \q_int$next $0\q_int$next[0:0]$6819 end - connect \$9 $and$libresoc.v:133047$6550_Y - connect \$11 $or$libresoc.v:133048$6551_Y - connect \$13 $not$libresoc.v:133049$6552_Y - connect \$15 $or$libresoc.v:133050$6553_Y - connect \$1 $not$libresoc.v:133051$6554_Y - connect \$3 $and$libresoc.v:133052$6555_Y - connect \$5 $or$libresoc.v:133053$6556_Y - connect \$7 $not$libresoc.v:133054$6557_Y + connect \$9 $and$libresoc.v:135382$6809_Y + connect \$11 $or$libresoc.v:135383$6810_Y + connect \$13 $not$libresoc.v:135384$6811_Y + connect \$15 $or$libresoc.v:135385$6812_Y + connect \$1 $not$libresoc.v:135386$6813_Y + connect \$3 $and$libresoc.v:135387$6814_Y + connect \$5 $or$libresoc.v:135388$6815_Y + connect \$7 $not$libresoc.v:135389$6816_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:133073.1-133539.10" +attribute \src "libresoc.v:135408.1-135942.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:133422.3-133442.6" - wire width 45 $0\dbus__adr$next[44:0]$6644 - attribute \src "libresoc.v:133308.3-133309.35" + attribute \src "libresoc.v:135796.3-135821.6" + wire width 45 $0\dbus__adr$next[44:0]$6908 + attribute \src "libresoc.v:135646.3-135647.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:133318.3-133340.6" - wire $0\dbus__cyc$next[0:0]$6623 - attribute \src "libresoc.v:133316.3-133317.35" + attribute \src "libresoc.v:135656.3-135683.6" + wire $0\dbus__cyc$next[0:0]$6882 + attribute \src "libresoc.v:135654.3-135655.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:133464.3-133484.6" - wire width 64 $0\dbus__dat_w$next[63:0]$6652 - attribute \src "libresoc.v:133304.3-133305.39" + attribute \src "libresoc.v:135848.3-135873.6" + wire width 64 $0\dbus__dat_w$next[63:0]$6918 + attribute \src "libresoc.v:135642.3-135643.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:133376.3-133401.6" - wire width 8 $0\dbus__sel$next[7:0]$6634 - attribute \src "libresoc.v:133312.3-133313.35" + attribute \src "libresoc.v:135740.3-135770.6" + wire width 8 $0\dbus__sel$next[7:0]$6896 + attribute \src "libresoc.v:135650.3-135651.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:133341.3-133363.6" - wire $0\dbus__stb$next[0:0]$6628 - attribute \src "libresoc.v:133314.3-133315.35" + attribute \src "libresoc.v:135684.3-135711.6" + wire $0\dbus__stb$next[0:0]$6888 + attribute \src "libresoc.v:135652.3-135653.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:133443.3-133463.6" - wire $0\dbus__we$next[0:0]$6648 - attribute \src "libresoc.v:133306.3-133307.33" + attribute \src "libresoc.v:135822.3-135847.6" + wire $0\dbus__we$next[0:0]$6913 + attribute \src "libresoc.v:135644.3-135645.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:133074.7-133074.20" + attribute \src "libresoc.v:135409.7-135409.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133521.3-133535.6" - wire width 45 $0\m_badaddr_o$next[44:0]$6664 - attribute \src "libresoc.v:133298.3-133299.39" + attribute \src "libresoc.v:135920.3-135939.6" + wire width 45 $0\m_badaddr_o$next[44:0]$6933 + attribute \src "libresoc.v:135636.3-135637.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:133364.3-133375.6" + attribute \src "libresoc.v:135722.3-135739.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:133402.3-133421.6" - wire width 64 $0\m_ld_data_o$next[63:0]$6639 - attribute \src "libresoc.v:133310.3-133311.39" + attribute \src "libresoc.v:135771.3-135795.6" + wire width 64 $0\m_ld_data_o$next[63:0]$6902 + attribute \src "libresoc.v:135648.3-135649.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:133485.3-133502.6" - wire $0\m_load_err_o$next[0:0]$6656 - attribute \src "libresoc.v:133302.3-133303.41" + attribute \src "libresoc.v:135874.3-135896.6" + wire $0\m_load_err_o$next[0:0]$6923 + attribute \src "libresoc.v:135640.3-135641.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:133503.3-133520.6" - wire $0\m_store_err_o$next[0:0]$6660 - attribute \src "libresoc.v:133300.3-133301.43" + attribute \src "libresoc.v:135897.3-135919.6" + wire $0\m_store_err_o$next[0:0]$6928 + attribute \src "libresoc.v:135638.3-135639.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:133422.3-133442.6" - wire width 45 $1\dbus__adr$next[44:0]$6645 - attribute \src "libresoc.v:133179.14-133179.42" + attribute \src "libresoc.v:135712.3-135721.6" + wire $0\x_busy_o[0:0] + attribute \src "libresoc.v:135796.3-135821.6" + wire width 45 $1\dbus__adr$next[44:0]$6909 + attribute \src "libresoc.v:135514.14-135514.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:133318.3-133340.6" - wire $1\dbus__cyc$next[0:0]$6624 - attribute \src "libresoc.v:133184.7-133184.23" + attribute \src "libresoc.v:135656.3-135683.6" + wire $1\dbus__cyc$next[0:0]$6883 + attribute \src "libresoc.v:135519.7-135519.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:133464.3-133484.6" - wire width 64 $1\dbus__dat_w$next[63:0]$6653 - attribute \src "libresoc.v:133191.14-133191.48" + attribute \src "libresoc.v:135848.3-135873.6" + wire width 64 $1\dbus__dat_w$next[63:0]$6919 + attribute \src "libresoc.v:135526.14-135526.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:133376.3-133401.6" - wire width 8 $1\dbus__sel$next[7:0]$6635 - attribute \src "libresoc.v:133198.13-133198.30" + attribute \src "libresoc.v:135740.3-135770.6" + wire width 8 $1\dbus__sel$next[7:0]$6897 + attribute \src "libresoc.v:135533.13-135533.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:133341.3-133363.6" - wire $1\dbus__stb$next[0:0]$6629 - attribute \src "libresoc.v:133203.7-133203.23" + attribute \src "libresoc.v:135684.3-135711.6" + wire $1\dbus__stb$next[0:0]$6889 + attribute \src "libresoc.v:135538.7-135538.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:133443.3-133463.6" - wire $1\dbus__we$next[0:0]$6649 - attribute \src "libresoc.v:133208.7-133208.22" + attribute \src "libresoc.v:135822.3-135847.6" + wire $1\dbus__we$next[0:0]$6914 + attribute \src "libresoc.v:135543.7-135543.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:133521.3-133535.6" - wire width 45 $1\m_badaddr_o$next[44:0]$6665 - attribute \src "libresoc.v:133212.14-133212.44" + attribute \src "libresoc.v:135920.3-135939.6" + wire width 45 $1\m_badaddr_o$next[44:0]$6934 + attribute \src "libresoc.v:135547.14-135547.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:133364.3-133375.6" + attribute \src "libresoc.v:135722.3-135739.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:133402.3-133421.6" - wire width 64 $1\m_ld_data_o$next[63:0]$6640 - attribute \src "libresoc.v:133219.14-133219.48" + attribute \src "libresoc.v:135771.3-135795.6" + wire width 64 $1\m_ld_data_o$next[63:0]$6903 + attribute \src "libresoc.v:135554.14-135554.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:133485.3-133502.6" - wire $1\m_load_err_o$next[0:0]$6657 - attribute \src "libresoc.v:133223.7-133223.26" + attribute \src "libresoc.v:135874.3-135896.6" + wire $1\m_load_err_o$next[0:0]$6924 + attribute \src "libresoc.v:135558.7-135558.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:133503.3-133520.6" - wire $1\m_store_err_o$next[0:0]$6661 - attribute \src "libresoc.v:133229.7-133229.27" + attribute \src "libresoc.v:135897.3-135919.6" + wire $1\m_store_err_o$next[0:0]$6929 + attribute \src "libresoc.v:135564.7-135564.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:133422.3-133442.6" - wire width 45 $2\dbus__adr$next[44:0]$6646 - attribute \src "libresoc.v:133318.3-133340.6" - wire $2\dbus__cyc$next[0:0]$6625 - attribute \src "libresoc.v:133464.3-133484.6" - wire width 64 $2\dbus__dat_w$next[63:0]$6654 - attribute \src "libresoc.v:133376.3-133401.6" - wire width 8 $2\dbus__sel$next[7:0]$6636 - attribute \src "libresoc.v:133341.3-133363.6" - wire $2\dbus__stb$next[0:0]$6630 - attribute \src "libresoc.v:133443.3-133463.6" - wire $2\dbus__we$next[0:0]$6650 - attribute \src "libresoc.v:133521.3-133535.6" - wire width 45 $2\m_badaddr_o$next[44:0]$6666 - attribute \src "libresoc.v:133402.3-133421.6" - wire width 64 $2\m_ld_data_o$next[63:0]$6641 - attribute \src "libresoc.v:133485.3-133502.6" - wire $2\m_load_err_o$next[0:0]$6658 - attribute \src "libresoc.v:133503.3-133520.6" - wire $2\m_store_err_o$next[0:0]$6662 - attribute \src "libresoc.v:133318.3-133340.6" - wire $3\dbus__cyc$next[0:0]$6626 - attribute \src "libresoc.v:133376.3-133401.6" - wire width 8 $3\dbus__sel$next[7:0]$6637 - attribute \src "libresoc.v:133341.3-133363.6" - wire $3\dbus__stb$next[0:0]$6631 - attribute \src "libresoc.v:133402.3-133421.6" - wire width 64 $3\m_ld_data_o$next[63:0]$6642 - attribute \src "libresoc.v:133254.18-133254.116" - wire $and$libresoc.v:133254$6568_Y - attribute \src "libresoc.v:133257.18-133257.111" - wire $and$libresoc.v:133257$6571_Y - attribute \src "libresoc.v:133262.18-133262.116" - wire $and$libresoc.v:133262$6576_Y - attribute \src "libresoc.v:133264.18-133264.111" - wire $and$libresoc.v:133264$6578_Y - attribute \src "libresoc.v:133266.17-133266.114" - wire $and$libresoc.v:133266$6580_Y - attribute \src "libresoc.v:133270.18-133270.116" - wire $and$libresoc.v:133270$6584_Y - attribute \src "libresoc.v:133272.18-133272.111" - wire $and$libresoc.v:133272$6586_Y - attribute \src "libresoc.v:133278.18-133278.116" - wire $and$libresoc.v:133278$6592_Y - attribute \src "libresoc.v:133280.18-133280.111" - wire $and$libresoc.v:133280$6594_Y - attribute \src "libresoc.v:133282.18-133282.116" - wire $and$libresoc.v:133282$6596_Y - attribute \src "libresoc.v:133284.18-133284.111" - wire $and$libresoc.v:133284$6598_Y - attribute \src "libresoc.v:133286.18-133286.116" - wire $and$libresoc.v:133286$6600_Y - attribute \src "libresoc.v:133288.17-133288.108" - wire $and$libresoc.v:133288$6602_Y - attribute \src "libresoc.v:133289.18-133289.111" - wire $and$libresoc.v:133289$6603_Y - attribute \src "libresoc.v:133290.18-133290.120" - wire $and$libresoc.v:133290$6604_Y - attribute \src "libresoc.v:133293.18-133293.120" - wire $and$libresoc.v:133293$6607_Y - attribute \src "libresoc.v:133295.18-133295.120" - wire $and$libresoc.v:133295$6609_Y - attribute \src "libresoc.v:133251.18-133251.110" - wire $not$libresoc.v:133251$6565_Y - attribute \src "libresoc.v:133256.18-133256.110" - wire $not$libresoc.v:133256$6570_Y - attribute \src "libresoc.v:133259.18-133259.110" - wire $not$libresoc.v:133259$6573_Y - attribute \src "libresoc.v:133263.18-133263.110" - wire $not$libresoc.v:133263$6577_Y - attribute \src "libresoc.v:133267.18-133267.110" - wire $not$libresoc.v:133267$6581_Y - attribute \src "libresoc.v:133271.18-133271.110" - wire $not$libresoc.v:133271$6585_Y - attribute \src "libresoc.v:133274.18-133274.110" - wire $not$libresoc.v:133274$6588_Y - attribute \src "libresoc.v:133277.17-133277.109" - wire $not$libresoc.v:133277$6591_Y - attribute \src "libresoc.v:133279.18-133279.110" - wire $not$libresoc.v:133279$6593_Y - attribute \src "libresoc.v:133283.18-133283.110" - wire $not$libresoc.v:133283$6597_Y - attribute \src "libresoc.v:133287.18-133287.110" - wire $not$libresoc.v:133287$6601_Y - attribute \src "libresoc.v:133291.18-133291.110" - wire $not$libresoc.v:133291$6605_Y - attribute \src "libresoc.v:133292.18-133292.109" - wire $not$libresoc.v:133292$6606_Y - attribute \src "libresoc.v:133294.18-133294.110" - wire $not$libresoc.v:133294$6608_Y - attribute \src "libresoc.v:133296.18-133296.110" - wire $not$libresoc.v:133296$6610_Y - attribute \src "libresoc.v:133250.17-133250.119" - wire $or$libresoc.v:133250$6564_Y - attribute \src "libresoc.v:133252.18-133252.110" - wire $or$libresoc.v:133252$6566_Y - attribute \src "libresoc.v:133253.18-133253.114" - wire $or$libresoc.v:133253$6567_Y - attribute \src "libresoc.v:133255.17-133255.113" - wire $or$libresoc.v:133255$6569_Y - attribute \src "libresoc.v:133258.18-133258.120" - wire $or$libresoc.v:133258$6572_Y - attribute \src "libresoc.v:133260.18-133260.111" - wire $or$libresoc.v:133260$6574_Y - attribute \src "libresoc.v:133261.18-133261.114" - wire $or$libresoc.v:133261$6575_Y - attribute \src "libresoc.v:133265.18-133265.120" - wire $or$libresoc.v:133265$6579_Y - attribute \src "libresoc.v:133268.18-133268.111" - wire $or$libresoc.v:133268$6582_Y - attribute \src "libresoc.v:133269.18-133269.114" - wire $or$libresoc.v:133269$6583_Y - attribute \src "libresoc.v:133273.18-133273.120" - wire $or$libresoc.v:133273$6587_Y - attribute \src "libresoc.v:133275.18-133275.111" - wire $or$libresoc.v:133275$6589_Y - attribute \src "libresoc.v:133276.18-133276.114" - wire $or$libresoc.v:133276$6590_Y - attribute \src "libresoc.v:133281.18-133281.114" - wire $or$libresoc.v:133281$6595_Y - attribute \src "libresoc.v:133285.18-133285.114" - wire $or$libresoc.v:133285$6599_Y - attribute \src "libresoc.v:133297.18-133297.127" - wire $or$libresoc.v:133297$6611_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "libresoc.v:135712.3-135721.6" + wire $1\x_busy_o[0:0] + attribute \src "libresoc.v:135796.3-135821.6" + wire width 45 $2\dbus__adr$next[44:0]$6910 + attribute \src "libresoc.v:135656.3-135683.6" + wire $2\dbus__cyc$next[0:0]$6884 + attribute \src "libresoc.v:135848.3-135873.6" + wire width 64 $2\dbus__dat_w$next[63:0]$6920 + attribute \src "libresoc.v:135740.3-135770.6" + wire width 8 $2\dbus__sel$next[7:0]$6898 + attribute \src "libresoc.v:135684.3-135711.6" + wire $2\dbus__stb$next[0:0]$6890 + attribute \src "libresoc.v:135822.3-135847.6" + wire $2\dbus__we$next[0:0]$6915 + attribute \src "libresoc.v:135920.3-135939.6" + wire width 45 $2\m_badaddr_o$next[44:0]$6935 + attribute \src "libresoc.v:135722.3-135739.6" + wire $2\m_busy_o[0:0] + attribute \src "libresoc.v:135771.3-135795.6" + wire width 64 $2\m_ld_data_o$next[63:0]$6904 + attribute \src "libresoc.v:135874.3-135896.6" + wire $2\m_load_err_o$next[0:0]$6925 + attribute \src "libresoc.v:135897.3-135919.6" + wire $2\m_store_err_o$next[0:0]$6930 + attribute \src "libresoc.v:135796.3-135821.6" + wire width 45 $3\dbus__adr$next[44:0]$6911 + attribute \src "libresoc.v:135656.3-135683.6" + wire $3\dbus__cyc$next[0:0]$6885 + attribute \src "libresoc.v:135848.3-135873.6" + wire width 64 $3\dbus__dat_w$next[63:0]$6921 + attribute \src "libresoc.v:135740.3-135770.6" + wire width 8 $3\dbus__sel$next[7:0]$6899 + attribute \src "libresoc.v:135684.3-135711.6" + wire $3\dbus__stb$next[0:0]$6891 + attribute \src "libresoc.v:135822.3-135847.6" + wire $3\dbus__we$next[0:0]$6916 + attribute \src "libresoc.v:135920.3-135939.6" + wire width 45 $3\m_badaddr_o$next[44:0]$6936 + attribute \src "libresoc.v:135771.3-135795.6" + wire width 64 $3\m_ld_data_o$next[63:0]$6905 + attribute \src "libresoc.v:135874.3-135896.6" + wire $3\m_load_err_o$next[0:0]$6926 + attribute \src "libresoc.v:135897.3-135919.6" + wire $3\m_store_err_o$next[0:0]$6931 + attribute \src "libresoc.v:135656.3-135683.6" + wire $4\dbus__cyc$next[0:0]$6886 + attribute \src "libresoc.v:135740.3-135770.6" + wire width 8 $4\dbus__sel$next[7:0]$6900 + attribute \src "libresoc.v:135684.3-135711.6" + wire $4\dbus__stb$next[0:0]$6892 + attribute \src "libresoc.v:135771.3-135795.6" + wire width 64 $4\m_ld_data_o$next[63:0]$6906 + attribute \src "libresoc.v:135592.18-135592.116" + wire $and$libresoc.v:135592$6827_Y + attribute \src "libresoc.v:135595.18-135595.111" + wire $and$libresoc.v:135595$6830_Y + attribute \src "libresoc.v:135600.18-135600.116" + wire $and$libresoc.v:135600$6835_Y + attribute \src "libresoc.v:135602.18-135602.111" + wire $and$libresoc.v:135602$6837_Y + attribute \src "libresoc.v:135604.17-135604.114" + wire $and$libresoc.v:135604$6839_Y + attribute \src "libresoc.v:135608.18-135608.116" + wire $and$libresoc.v:135608$6843_Y + attribute \src "libresoc.v:135610.18-135610.111" + wire $and$libresoc.v:135610$6845_Y + attribute \src "libresoc.v:135616.18-135616.116" + wire $and$libresoc.v:135616$6851_Y + attribute \src "libresoc.v:135618.18-135618.111" + wire $and$libresoc.v:135618$6853_Y + attribute \src "libresoc.v:135620.18-135620.116" + wire $and$libresoc.v:135620$6855_Y + attribute \src "libresoc.v:135622.18-135622.111" + wire $and$libresoc.v:135622$6857_Y + attribute \src "libresoc.v:135624.18-135624.116" + wire $and$libresoc.v:135624$6859_Y + attribute \src "libresoc.v:135626.17-135626.108" + wire $and$libresoc.v:135626$6861_Y + attribute \src "libresoc.v:135627.18-135627.111" + wire $and$libresoc.v:135627$6862_Y + attribute \src "libresoc.v:135628.18-135628.120" + wire $and$libresoc.v:135628$6863_Y + attribute \src "libresoc.v:135631.18-135631.120" + wire $and$libresoc.v:135631$6866_Y + attribute \src "libresoc.v:135633.18-135633.120" + wire $and$libresoc.v:135633$6868_Y + attribute \src "libresoc.v:135589.18-135589.110" + wire $not$libresoc.v:135589$6824_Y + attribute \src "libresoc.v:135594.18-135594.110" + wire $not$libresoc.v:135594$6829_Y + attribute \src "libresoc.v:135597.18-135597.110" + wire $not$libresoc.v:135597$6832_Y + attribute \src "libresoc.v:135601.18-135601.110" + wire $not$libresoc.v:135601$6836_Y + attribute \src "libresoc.v:135605.18-135605.110" + wire $not$libresoc.v:135605$6840_Y + attribute \src "libresoc.v:135609.18-135609.110" + wire $not$libresoc.v:135609$6844_Y + attribute \src "libresoc.v:135612.18-135612.110" + wire $not$libresoc.v:135612$6847_Y + attribute \src "libresoc.v:135615.17-135615.109" + wire $not$libresoc.v:135615$6850_Y + attribute \src "libresoc.v:135617.18-135617.110" + wire $not$libresoc.v:135617$6852_Y + attribute \src "libresoc.v:135621.18-135621.110" + wire $not$libresoc.v:135621$6856_Y + attribute \src "libresoc.v:135625.18-135625.110" + wire $not$libresoc.v:135625$6860_Y + attribute \src "libresoc.v:135629.18-135629.110" + wire $not$libresoc.v:135629$6864_Y + attribute \src "libresoc.v:135630.18-135630.109" + wire $not$libresoc.v:135630$6865_Y + attribute \src "libresoc.v:135632.18-135632.110" + wire $not$libresoc.v:135632$6867_Y + attribute \src "libresoc.v:135634.18-135634.110" + wire $not$libresoc.v:135634$6869_Y + attribute \src "libresoc.v:135588.17-135588.119" + wire $or$libresoc.v:135588$6823_Y + attribute \src "libresoc.v:135590.18-135590.110" + wire $or$libresoc.v:135590$6825_Y + attribute \src "libresoc.v:135591.18-135591.114" + wire $or$libresoc.v:135591$6826_Y + attribute \src "libresoc.v:135593.17-135593.113" + wire $or$libresoc.v:135593$6828_Y + attribute \src "libresoc.v:135596.18-135596.120" + wire $or$libresoc.v:135596$6831_Y + attribute \src "libresoc.v:135598.18-135598.111" + wire $or$libresoc.v:135598$6833_Y + attribute \src "libresoc.v:135599.18-135599.114" + wire $or$libresoc.v:135599$6834_Y + attribute \src "libresoc.v:135603.18-135603.120" + wire $or$libresoc.v:135603$6838_Y + attribute \src "libresoc.v:135606.18-135606.111" + wire $or$libresoc.v:135606$6841_Y + attribute \src "libresoc.v:135607.18-135607.114" + wire $or$libresoc.v:135607$6842_Y + attribute \src "libresoc.v:135611.18-135611.120" + wire $or$libresoc.v:135611$6846_Y + attribute \src "libresoc.v:135613.18-135613.111" + wire $or$libresoc.v:135613$6848_Y + attribute \src "libresoc.v:135614.18-135614.114" + wire $or$libresoc.v:135614$6849_Y + attribute \src "libresoc.v:135619.18-135619.114" + wire $or$libresoc.v:135619$6854_Y + attribute \src "libresoc.v:135623.18-135623.114" + wire $or$libresoc.v:135623$6858_Y + attribute \src "libresoc.v:135635.18-135635.127" + wire $or$libresoc.v:135635$6870_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 12 \dbus__ack + wire input 13 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 17 \dbus__adr + wire width 45 output 18 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 45 \dbus__adr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 11 \dbus__cyc + wire output 12 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__cyc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 16 \dbus__dat_r + wire width 64 input 17 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 19 \dbus__dat_w + wire width 64 output 20 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 64 \dbus__dat_w$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 13 \dbus__err + wire input 14 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 15 \dbus__sel + wire width 8 output 16 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire width 8 \dbus__sel$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 14 \dbus__stb + wire output 15 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__stb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 18 \dbus__we + wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:133074.7-133074.15" + attribute \src "libresoc.v:135409.7-135409.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" wire \m_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 output 4 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 \m_ld_data_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" wire \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" wire \m_load_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" wire \m_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" wire \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" wire \m_store_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire input 9 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 11 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 input 3 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire output 6 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire input 7 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 input 2 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 input 5 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire input 8 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:49" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" wire \x_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133254$6568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135592$6827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -277990,10 +283963,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:133254$6568_Y + connect \Y $and$libresoc.v:135592$6827_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133257$6571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135595$6830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278001,10 +283974,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:133257$6571_Y + connect \Y $and$libresoc.v:135595$6830_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133262$6576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135600$6835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278012,10 +283985,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:133262$6576_Y + connect \Y $and$libresoc.v:135600$6835_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133264$6578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135602$6837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278023,10 +283996,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:133264$6578_Y + connect \Y $and$libresoc.v:135602$6837_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133266$6580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135604$6839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278034,10 +284007,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:133266$6580_Y + connect \Y $and$libresoc.v:135604$6839_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133270$6584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135608$6843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278045,10 +284018,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:133270$6584_Y + connect \Y $and$libresoc.v:135608$6843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133272$6586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135610$6845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278056,10 +284029,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:133272$6586_Y + connect \Y $and$libresoc.v:135610$6845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133278$6592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135616$6851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278067,10 +284040,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:133278$6592_Y + connect \Y $and$libresoc.v:135616$6851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133280$6594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135618$6853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278078,10 +284051,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:133280$6594_Y + connect \Y $and$libresoc.v:135618$6853_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133282$6596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135620$6855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278089,10 +284062,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:133282$6596_Y + connect \Y $and$libresoc.v:135620$6855_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133284$6598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135622$6857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278100,10 +284073,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:133284$6598_Y + connect \Y $and$libresoc.v:135622$6857_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133286$6600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135624$6859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278111,10 +284084,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:133286$6600_Y + connect \Y $and$libresoc.v:135624$6859_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133288$6602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135626$6861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278122,10 +284095,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:133288$6602_Y + connect \Y $and$libresoc.v:135626$6861_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $and$libresoc.v:133289$6603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:135627$6862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278133,10 +284106,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:133289$6603_Y + connect \Y $and$libresoc.v:135627$6862_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $and$libresoc.v:133290$6604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:135628$6863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278144,10 +284117,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:133290$6604_Y + connect \Y $and$libresoc.v:135628$6863_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $and$libresoc.v:133293$6607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:135631$6866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278155,10 +284128,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:133293$6607_Y + connect \Y $and$libresoc.v:135631$6866_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $and$libresoc.v:133295$6609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:135633$6868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278166,130 +284139,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:133295$6609_Y + connect \Y $and$libresoc.v:135633$6868_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $not$libresoc.v:133251$6565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:135589$6824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:133251$6565_Y + connect \Y $not$libresoc.v:135589$6824_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133256$6570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135594$6829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133256$6570_Y + connect \Y $not$libresoc.v:135594$6829_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $not$libresoc.v:133259$6573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:135597$6832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:133259$6573_Y + connect \Y $not$libresoc.v:135597$6832_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133263$6577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135601$6836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133263$6577_Y + connect \Y $not$libresoc.v:135601$6836_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $not$libresoc.v:133267$6581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:135605$6840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:133267$6581_Y + connect \Y $not$libresoc.v:135605$6840_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133271$6585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135609$6844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133271$6585_Y + connect \Y $not$libresoc.v:135609$6844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $not$libresoc.v:133274$6588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:135612$6847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:133274$6588_Y + connect \Y $not$libresoc.v:135612$6847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133277$6591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135615$6850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133277$6591_Y + connect \Y $not$libresoc.v:135615$6850_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133279$6593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135617$6852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133279$6593_Y + connect \Y $not$libresoc.v:135617$6852_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133283$6597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135621$6856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133283$6597_Y + connect \Y $not$libresoc.v:135621$6856_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $not$libresoc.v:133287$6601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:135625$6860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:133287$6601_Y + connect \Y $not$libresoc.v:135625$6860_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $not$libresoc.v:133291$6605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:135629$6864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:133291$6605_Y + connect \Y $not$libresoc.v:135629$6864_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" - cell $not $not$libresoc.v:133292$6606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" + cell $not $not$libresoc.v:135630$6865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:133292$6606_Y + connect \Y $not$libresoc.v:135630$6865_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $not$libresoc.v:133294$6608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:135632$6867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:133294$6608_Y + connect \Y $not$libresoc.v:135632$6867_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $not$libresoc.v:133296$6610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:135634$6869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:133296$6610_Y + connect \Y $not$libresoc.v:135634$6869_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133250$6564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135588$6823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278297,10 +284270,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:133250$6564_Y + connect \Y $or$libresoc.v:135588$6823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133252$6566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135590$6825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278308,10 +284281,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:133252$6566_Y + connect \Y $or$libresoc.v:135590$6825_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133253$6567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135591$6826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278319,10 +284292,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133253$6567_Y + connect \Y $or$libresoc.v:135591$6826_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133255$6569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135593$6828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278330,10 +284303,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133255$6569_Y + connect \Y $or$libresoc.v:135593$6828_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133258$6572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135596$6831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278341,10 +284314,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:133258$6572_Y + connect \Y $or$libresoc.v:135596$6831_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133260$6574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135598$6833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278352,10 +284325,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:133260$6574_Y + connect \Y $or$libresoc.v:135598$6833_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133261$6575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135599$6834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278363,10 +284336,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133261$6575_Y + connect \Y $or$libresoc.v:135599$6834_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133265$6579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135603$6838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278374,10 +284347,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:133265$6579_Y + connect \Y $or$libresoc.v:135603$6838_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133268$6582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135606$6841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278385,10 +284358,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:133268$6582_Y + connect \Y $or$libresoc.v:135606$6841_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133269$6583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135607$6842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278396,10 +284369,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133269$6583_Y + connect \Y $or$libresoc.v:135607$6842_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133273$6587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135611$6846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278407,10 +284380,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:133273$6587_Y + connect \Y $or$libresoc.v:135611$6846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $or$libresoc.v:133275$6589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:135613$6848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278418,10 +284391,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:133275$6589_Y + connect \Y $or$libresoc.v:135613$6848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133276$6590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135614$6849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278429,10 +284402,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133276$6590_Y + connect \Y $or$libresoc.v:135614$6849_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133281$6595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135619$6854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278440,10 +284413,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133281$6595_Y + connect \Y $or$libresoc.v:135619$6854_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $or$libresoc.v:133285$6599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:135623$6858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278451,10 +284424,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:133285$6599_Y + connect \Y $or$libresoc.v:135623$6858_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - cell $or $or$libresoc.v:133297$6611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + cell $or $or$libresoc.v:135635$6870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278462,1041 +284435,1163 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:133297$6611_Y + connect \Y $or$libresoc.v:135635$6870_Y end - attribute \src "libresoc.v:133074.7-133074.20" - process $proc$libresoc.v:133074$6667 + attribute \src "libresoc.v:135409.7-135409.20" + process $proc$libresoc.v:135409$6937 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133179.14-133179.42" - process $proc$libresoc.v:133179$6668 + attribute \src "libresoc.v:135514.14-135514.42" + process $proc$libresoc.v:135514$6938 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:133184.7-133184.23" - process $proc$libresoc.v:133184$6669 + attribute \src "libresoc.v:135519.7-135519.23" + process $proc$libresoc.v:135519$6939 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:133191.14-133191.48" - process $proc$libresoc.v:133191$6670 + attribute \src "libresoc.v:135526.14-135526.48" + process $proc$libresoc.v:135526$6940 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:133198.13-133198.30" - process $proc$libresoc.v:133198$6671 + attribute \src "libresoc.v:135533.13-135533.30" + process $proc$libresoc.v:135533$6941 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:133203.7-133203.23" - process $proc$libresoc.v:133203$6672 + attribute \src "libresoc.v:135538.7-135538.23" + process $proc$libresoc.v:135538$6942 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:133208.7-133208.22" - process $proc$libresoc.v:133208$6673 + attribute \src "libresoc.v:135543.7-135543.22" + process $proc$libresoc.v:135543$6943 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:133212.14-133212.44" - process $proc$libresoc.v:133212$6674 + attribute \src "libresoc.v:135547.14-135547.44" + process $proc$libresoc.v:135547$6944 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:133219.14-133219.48" - process $proc$libresoc.v:133219$6675 + attribute \src "libresoc.v:135554.14-135554.48" + process $proc$libresoc.v:135554$6945 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:133223.7-133223.26" - process $proc$libresoc.v:133223$6676 + attribute \src "libresoc.v:135558.7-135558.26" + process $proc$libresoc.v:135558$6946 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:133229.7-133229.27" - process $proc$libresoc.v:133229$6677 + attribute \src "libresoc.v:135564.7-135564.27" + process $proc$libresoc.v:135564$6947 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:133298.3-133299.39" - process $proc$libresoc.v:133298$6612 + attribute \src "libresoc.v:135636.3-135637.39" + process $proc$libresoc.v:135636$6871 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:133300.3-133301.43" - process $proc$libresoc.v:133300$6613 + attribute \src "libresoc.v:135638.3-135639.43" + process $proc$libresoc.v:135638$6872 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:133302.3-133303.41" - process $proc$libresoc.v:133302$6614 + attribute \src "libresoc.v:135640.3-135641.41" + process $proc$libresoc.v:135640$6873 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:133304.3-133305.39" - process $proc$libresoc.v:133304$6615 + attribute \src "libresoc.v:135642.3-135643.39" + process $proc$libresoc.v:135642$6874 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:133306.3-133307.33" - process $proc$libresoc.v:133306$6616 + attribute \src "libresoc.v:135644.3-135645.33" + process $proc$libresoc.v:135644$6875 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:133308.3-133309.35" - process $proc$libresoc.v:133308$6617 + attribute \src "libresoc.v:135646.3-135647.35" + process $proc$libresoc.v:135646$6876 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:133310.3-133311.39" - process $proc$libresoc.v:133310$6618 + attribute \src "libresoc.v:135648.3-135649.39" + process $proc$libresoc.v:135648$6877 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:133312.3-133313.35" - process $proc$libresoc.v:133312$6619 + attribute \src "libresoc.v:135650.3-135651.35" + process $proc$libresoc.v:135650$6878 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:133314.3-133315.35" - process $proc$libresoc.v:133314$6620 + attribute \src "libresoc.v:135652.3-135653.35" + process $proc$libresoc.v:135652$6879 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:133316.3-133317.35" - process $proc$libresoc.v:133316$6621 + attribute \src "libresoc.v:135654.3-135655.35" + process $proc$libresoc.v:135654$6880 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:133318.3-133340.6" - process $proc$libresoc.v:133318$6622 + attribute \src "libresoc.v:135656.3-135683.6" + process $proc$libresoc.v:135656$6881 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$6623 $3\dbus__cyc$next[0:0]$6626 - attribute \src "libresoc.v:133319.5-133319.29" + assign $0\dbus__cyc$next[0:0]$6882 $4\dbus__cyc$next[0:0]$6886 + attribute \src "libresoc.v:135657.5-135657.29" switch \initial - attribute \src "libresoc.v:133319.9-133319.17" + attribute \src "libresoc.v:135657.9-135657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$7 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$6624 $2\dbus__cyc$next[0:0]$6625 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$13 + assign $1\dbus__cyc$next[0:0]$6883 $2\dbus__cyc$next[0:0]$6884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$6884 $3\dbus__cyc$next[0:0]$6885 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$6885 1'0 + case + assign $3\dbus__cyc$next[0:0]$6885 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$6625 1'0 + assign $2\dbus__cyc$next[0:0]$6884 1'1 case - assign $2\dbus__cyc$next[0:0]$6625 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$6884 \dbus__cyc end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__cyc$next[0:0]$6624 1'1 case - assign $1\dbus__cyc$next[0:0]$6624 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$6883 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$6626 1'0 + assign $4\dbus__cyc$next[0:0]$6886 1'0 case - assign $3\dbus__cyc$next[0:0]$6626 $1\dbus__cyc$next[0:0]$6624 + assign $4\dbus__cyc$next[0:0]$6886 $1\dbus__cyc$next[0:0]$6883 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6623 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6882 end - attribute \src "libresoc.v:133341.3-133363.6" - process $proc$libresoc.v:133341$6627 + attribute \src "libresoc.v:135684.3-135711.6" + process $proc$libresoc.v:135684$6887 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$6628 $3\dbus__stb$next[0:0]$6631 - attribute \src "libresoc.v:133342.5-133342.29" + assign $0\dbus__stb$next[0:0]$6888 $4\dbus__stb$next[0:0]$6892 + attribute \src "libresoc.v:135685.5-135685.29" switch \initial - attribute \src "libresoc.v:133342.9-133342.17" + attribute \src "libresoc.v:135685.9-135685.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$21 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$6629 $2\dbus__stb$next[0:0]$6630 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$27 + assign $1\dbus__stb$next[0:0]$6889 $2\dbus__stb$next[0:0]$6890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $2\dbus__stb$next[0:0]$6890 $3\dbus__stb$next[0:0]$6891 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$6891 1'0 + case + assign $3\dbus__stb$next[0:0]$6891 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$6630 1'0 + assign $2\dbus__stb$next[0:0]$6890 1'1 case - assign $2\dbus__stb$next[0:0]$6630 \dbus__stb + assign $2\dbus__stb$next[0:0]$6890 \dbus__stb end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dbus__stb$next[0:0]$6629 1'1 case - assign $1\dbus__stb$next[0:0]$6629 \dbus__stb + assign $1\dbus__stb$next[0:0]$6889 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$6631 1'0 + assign $4\dbus__stb$next[0:0]$6892 1'0 case - assign $3\dbus__stb$next[0:0]$6631 $1\dbus__stb$next[0:0]$6629 + assign $4\dbus__stb$next[0:0]$6892 $1\dbus__stb$next[0:0]$6889 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$6628 + update \dbus__stb$next $0\dbus__stb$next[0:0]$6888 end - attribute \src "libresoc.v:133364.3-133375.6" - process $proc$libresoc.v:133364$6632 + attribute \src "libresoc.v:135712.3-135721.6" + process $proc$libresoc.v:135712$6893 assign { } { } - assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:133365.5-133365.29" + assign { } { } + assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] + attribute \src "libresoc.v:135713.5-135713.29" switch \initial - attribute \src "libresoc.v:133365.9-133365.17" + attribute \src "libresoc.v:135713.9-135713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - switch \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $1\x_busy_o[0:0] \dbus__cyc case - assign { } { } - assign $1\m_busy_o[0:0] \dbus__cyc + assign $1\x_busy_o[0:0] 1'0 end sync always - update \m_busy_o $0\m_busy_o[0:0] + update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:133376.3-133401.6" - process $proc$libresoc.v:133376$6633 - assign { } { } + attribute \src "libresoc.v:135722.3-135739.6" + process $proc$libresoc.v:135722$6894 assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$6634 $3\dbus__sel$next[7:0]$6637 - attribute \src "libresoc.v:133377.5-133377.29" + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:135723.5-135723.29" switch \initial - attribute \src "libresoc.v:133377.9-133377.17" + attribute \src "libresoc.v:135723.9-135723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$35 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$6635 $2\dbus__sel$next[7:0]$6636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$41 + assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dbus__sel$next[7:0]$6636 8'00000000 + assign $2\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case - assign $2\dbus__sel$next[7:0]$6636 \dbus__sel + assign { } { } + assign $2\m_busy_o[0:0] \dbus__cyc end + case + assign $1\m_busy_o[0:0] 1'0 + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "libresoc.v:135740.3-135770.6" + process $proc$libresoc.v:135740$6895 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$6896 $4\dbus__sel$next[7:0]$6900 + attribute \src "libresoc.v:135741.5-135741.29" + switch \initial + attribute \src "libresoc.v:135741.9-135741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$6635 \x_mask_i - attribute \src "libresoc.v:0.0-0.0" + assign $1\dbus__sel$next[7:0]$6897 $2\dbus__sel$next[7:0]$6898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__sel$next[7:0]$6898 $3\dbus__sel$next[7:0]$6899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$6899 8'00000000 + case + assign $3\dbus__sel$next[7:0]$6899 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__sel$next[7:0]$6898 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__sel$next[7:0]$6898 8'00000000 + end case - assign { } { } - assign $1\dbus__sel$next[7:0]$6635 8'00000000 + assign $1\dbus__sel$next[7:0]$6897 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$6637 8'00000000 + assign $4\dbus__sel$next[7:0]$6900 8'00000000 case - assign $3\dbus__sel$next[7:0]$6637 $1\dbus__sel$next[7:0]$6635 + assign $4\dbus__sel$next[7:0]$6900 $1\dbus__sel$next[7:0]$6897 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$6634 + update \dbus__sel$next $0\dbus__sel$next[7:0]$6896 end - attribute \src "libresoc.v:133402.3-133421.6" - process $proc$libresoc.v:133402$6638 + attribute \src "libresoc.v:135771.3-135795.6" + process $proc$libresoc.v:135771$6901 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$6639 $3\m_ld_data_o$next[63:0]$6642 - attribute \src "libresoc.v:133403.5-133403.29" + assign $0\m_ld_data_o$next[63:0]$6902 $4\m_ld_data_o$next[63:0]$6906 + attribute \src "libresoc.v:135772.5-135772.29" switch \initial - attribute \src "libresoc.v:133403.9-133403.17" + attribute \src "libresoc.v:135772.9-135772.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$49 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$6640 $2\m_ld_data_o$next[63:0]$6641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch \$55 + assign $1\m_ld_data_o$next[63:0]$6903 $2\m_ld_data_o$next[63:0]$6904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$6641 \dbus__dat_r + assign $2\m_ld_data_o$next[63:0]$6904 $3\m_ld_data_o$next[63:0]$6905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$6905 \dbus__dat_r + case + assign $3\m_ld_data_o$next[63:0]$6905 \m_ld_data_o + end case - assign $2\m_ld_data_o$next[63:0]$6641 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$6904 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$6640 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$6903 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$6642 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$6906 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\m_ld_data_o$next[63:0]$6642 $1\m_ld_data_o$next[63:0]$6640 + assign $4\m_ld_data_o$next[63:0]$6906 $1\m_ld_data_o$next[63:0]$6903 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6639 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6902 end - attribute \src "libresoc.v:133422.3-133442.6" - process $proc$libresoc.v:133422$6643 + attribute \src "libresoc.v:135796.3-135821.6" + process $proc$libresoc.v:135796$6907 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$6644 $2\dbus__adr$next[44:0]$6646 - attribute \src "libresoc.v:133423.5-133423.29" + assign $0\dbus__adr$next[44:0]$6908 $3\dbus__adr$next[44:0]$6911 + attribute \src "libresoc.v:135797.5-135797.29" switch \initial - attribute \src "libresoc.v:133423.9-133423.17" + attribute \src "libresoc.v:135797.9-135797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$63 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $1\dbus__adr$next[44:0]$6645 \dbus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$6645 \x_addr_i [47:3] - attribute \src "libresoc.v:0.0-0.0" + assign $1\dbus__adr$next[44:0]$6909 $2\dbus__adr$next[44:0]$6910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__adr$next[44:0]$6910 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__adr$next[44:0]$6910 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__adr$next[44:0]$6910 45'000000000000000000000000000000000000000000000 + end case - assign { } { } - assign $1\dbus__adr$next[44:0]$6645 45'000000000000000000000000000000000000000000000 + assign $1\dbus__adr$next[44:0]$6909 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dbus__adr$next[44:0]$6646 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$6911 45'000000000000000000000000000000000000000000000 case - assign $2\dbus__adr$next[44:0]$6646 $1\dbus__adr$next[44:0]$6645 + assign $3\dbus__adr$next[44:0]$6911 $1\dbus__adr$next[44:0]$6909 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$6644 + update \dbus__adr$next $0\dbus__adr$next[44:0]$6908 end - attribute \src "libresoc.v:133443.3-133463.6" - process $proc$libresoc.v:133443$6647 + attribute \src "libresoc.v:135822.3-135847.6" + process $proc$libresoc.v:135822$6912 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$6648 $2\dbus__we$next[0:0]$6650 - attribute \src "libresoc.v:133444.5-133444.29" + assign $0\dbus__we$next[0:0]$6913 $3\dbus__we$next[0:0]$6916 + attribute \src "libresoc.v:135823.5-135823.29" switch \initial - attribute \src "libresoc.v:133444.9-133444.17" + attribute \src "libresoc.v:135823.9-135823.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$71 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $1\dbus__we$next[0:0]$6649 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$6649 \x_st_i - attribute \src "libresoc.v:0.0-0.0" + assign $1\dbus__we$next[0:0]$6914 $2\dbus__we$next[0:0]$6915 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__we$next[0:0]$6915 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__we$next[0:0]$6915 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__we$next[0:0]$6915 1'0 + end case - assign { } { } - assign $1\dbus__we$next[0:0]$6649 1'0 + assign $1\dbus__we$next[0:0]$6914 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dbus__we$next[0:0]$6650 1'0 + assign $3\dbus__we$next[0:0]$6916 1'0 case - assign $2\dbus__we$next[0:0]$6650 $1\dbus__we$next[0:0]$6649 + assign $3\dbus__we$next[0:0]$6916 $1\dbus__we$next[0:0]$6914 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$6648 + update \dbus__we$next $0\dbus__we$next[0:0]$6913 end - attribute \src "libresoc.v:133464.3-133484.6" - process $proc$libresoc.v:133464$6651 + attribute \src "libresoc.v:135848.3-135873.6" + process $proc$libresoc.v:135848$6917 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$6652 $2\dbus__dat_w$next[63:0]$6654 - attribute \src "libresoc.v:133465.5-133465.29" + assign $0\dbus__dat_w$next[63:0]$6918 $3\dbus__dat_w$next[63:0]$6921 + attribute \src "libresoc.v:135849.5-135849.29" switch \initial - attribute \src "libresoc.v:133465.9-133465.17" + attribute \src "libresoc.v:135849.9-135849.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { \$79 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $1\dbus__dat_w$next[63:0]$6653 \dbus__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$6653 \x_st_data_i - attribute \src "libresoc.v:0.0-0.0" + assign $1\dbus__dat_w$next[63:0]$6919 $2\dbus__dat_w$next[63:0]$6920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__dat_w$next[63:0]$6920 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6920 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6920 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign { } { } - assign $1\dbus__dat_w$next[63:0]$6653 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbus__dat_w$next[63:0]$6919 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dbus__dat_w$next[63:0]$6654 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$6921 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dbus__dat_w$next[63:0]$6654 $1\dbus__dat_w$next[63:0]$6653 + assign $3\dbus__dat_w$next[63:0]$6921 $1\dbus__dat_w$next[63:0]$6919 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6652 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6918 end - attribute \src "libresoc.v:133485.3-133502.6" - process $proc$libresoc.v:133485$6655 + attribute \src "libresoc.v:135874.3-135896.6" + process $proc$libresoc.v:135874$6922 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$6656 $2\m_load_err_o$next[0:0]$6658 - attribute \src "libresoc.v:133486.5-133486.29" + assign $0\m_load_err_o$next[0:0]$6923 $3\m_load_err_o$next[0:0]$6926 + attribute \src "libresoc.v:135875.5-135875.29" switch \initial - attribute \src "libresoc.v:133486.9-133486.17" + attribute \src "libresoc.v:135875.9-135875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$83 \$81 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_load_err_o$next[0:0]$6657 \$85 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$6657 1'0 + assign $1\m_load_err_o$next[0:0]$6924 $2\m_load_err_o$next[0:0]$6925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$6925 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_load_err_o$next[0:0]$6925 1'0 + case + assign $2\m_load_err_o$next[0:0]$6925 \m_load_err_o + end case - assign $1\m_load_err_o$next[0:0]$6657 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$6924 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\m_load_err_o$next[0:0]$6658 1'0 + assign $3\m_load_err_o$next[0:0]$6926 1'0 case - assign $2\m_load_err_o$next[0:0]$6658 $1\m_load_err_o$next[0:0]$6657 + assign $3\m_load_err_o$next[0:0]$6926 $1\m_load_err_o$next[0:0]$6924 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6656 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6923 end - attribute \src "libresoc.v:133503.3-133520.6" - process $proc$libresoc.v:133503$6659 + attribute \src "libresoc.v:135897.3-135919.6" + process $proc$libresoc.v:135897$6927 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$6660 $2\m_store_err_o$next[0:0]$6662 - attribute \src "libresoc.v:133504.5-133504.29" + assign $0\m_store_err_o$next[0:0]$6928 $3\m_store_err_o$next[0:0]$6931 + attribute \src "libresoc.v:135898.5-135898.29" switch \initial - attribute \src "libresoc.v:133504.9-133504.17" + attribute \src "libresoc.v:135898.9-135898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$89 \$87 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\m_store_err_o$next[0:0]$6661 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$6661 1'0 + assign $1\m_store_err_o$next[0:0]$6929 $2\m_store_err_o$next[0:0]$6930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$6930 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_store_err_o$next[0:0]$6930 1'0 + case + assign $2\m_store_err_o$next[0:0]$6930 \m_store_err_o + end case - assign $1\m_store_err_o$next[0:0]$6661 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$6929 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\m_store_err_o$next[0:0]$6662 1'0 + assign $3\m_store_err_o$next[0:0]$6931 1'0 case - assign $2\m_store_err_o$next[0:0]$6662 $1\m_store_err_o$next[0:0]$6661 + assign $3\m_store_err_o$next[0:0]$6931 $1\m_store_err_o$next[0:0]$6929 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6660 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6928 end - attribute \src "libresoc.v:133521.3-133535.6" - process $proc$libresoc.v:133521$6663 + attribute \src "libresoc.v:135920.3-135939.6" + process $proc$libresoc.v:135920$6932 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$6664 $2\m_badaddr_o$next[44:0]$6666 - attribute \src "libresoc.v:133522.5-133522.29" + assign $0\m_badaddr_o$next[44:0]$6933 $3\m_badaddr_o$next[44:0]$6936 + attribute \src "libresoc.v:135921.5-135921.29" switch \initial - attribute \src "libresoc.v:133522.9-133522.17" + attribute \src "libresoc.v:135921.9-135921.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { \$93 \$91 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$6665 \dbus__adr + assign $1\m_badaddr_o$next[44:0]$6934 $2\m_badaddr_o$next[44:0]$6935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$6935 \dbus__adr + case + assign $2\m_badaddr_o$next[44:0]$6935 \m_badaddr_o + end case - assign $1\m_badaddr_o$next[44:0]$6665 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$6934 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$6666 45'000000000000000000000000000000000000000000000 - case - assign $2\m_badaddr_o$next[44:0]$6666 $1\m_badaddr_o$next[44:0]$6665 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6664 - end - connect \$9 $or$libresoc.v:133250$6564_Y - connect \$11 $not$libresoc.v:133251$6565_Y - connect \$13 $or$libresoc.v:133252$6566_Y - connect \$15 $or$libresoc.v:133253$6567_Y - connect \$17 $and$libresoc.v:133254$6568_Y - connect \$1 $or$libresoc.v:133255$6569_Y - connect \$19 $not$libresoc.v:133256$6570_Y - connect \$21 $and$libresoc.v:133257$6571_Y - connect \$23 $or$libresoc.v:133258$6572_Y - connect \$25 $not$libresoc.v:133259$6573_Y - connect \$27 $or$libresoc.v:133260$6574_Y - connect \$29 $or$libresoc.v:133261$6575_Y - connect \$31 $and$libresoc.v:133262$6576_Y - connect \$33 $not$libresoc.v:133263$6577_Y - connect \$35 $and$libresoc.v:133264$6578_Y - connect \$37 $or$libresoc.v:133265$6579_Y - connect \$3 $and$libresoc.v:133266$6580_Y - connect \$39 $not$libresoc.v:133267$6581_Y - connect \$41 $or$libresoc.v:133268$6582_Y - connect \$43 $or$libresoc.v:133269$6583_Y - connect \$45 $and$libresoc.v:133270$6584_Y - connect \$47 $not$libresoc.v:133271$6585_Y - connect \$49 $and$libresoc.v:133272$6586_Y - connect \$51 $or$libresoc.v:133273$6587_Y - connect \$53 $not$libresoc.v:133274$6588_Y - connect \$55 $or$libresoc.v:133275$6589_Y - connect \$57 $or$libresoc.v:133276$6590_Y - connect \$5 $not$libresoc.v:133277$6591_Y - connect \$59 $and$libresoc.v:133278$6592_Y - connect \$61 $not$libresoc.v:133279$6593_Y - connect \$63 $and$libresoc.v:133280$6594_Y - connect \$65 $or$libresoc.v:133281$6595_Y - connect \$67 $and$libresoc.v:133282$6596_Y - connect \$69 $not$libresoc.v:133283$6597_Y - connect \$71 $and$libresoc.v:133284$6598_Y - connect \$73 $or$libresoc.v:133285$6599_Y - connect \$75 $and$libresoc.v:133286$6600_Y - connect \$77 $not$libresoc.v:133287$6601_Y - connect \$7 $and$libresoc.v:133288$6602_Y - connect \$79 $and$libresoc.v:133289$6603_Y - connect \$81 $and$libresoc.v:133290$6604_Y - connect \$83 $not$libresoc.v:133291$6605_Y - connect \$85 $not$libresoc.v:133292$6606_Y - connect \$87 $and$libresoc.v:133293$6607_Y - connect \$89 $not$libresoc.v:133294$6608_Y - connect \$91 $and$libresoc.v:133295$6609_Y - connect \$93 $not$libresoc.v:133296$6610_Y - connect \$95 $or$libresoc.v:133297$6611_Y + assign $3\m_badaddr_o$next[44:0]$6936 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$6936 $1\m_badaddr_o$next[44:0]$6934 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6933 + end + connect \$9 $or$libresoc.v:135588$6823_Y + connect \$11 $not$libresoc.v:135589$6824_Y + connect \$13 $or$libresoc.v:135590$6825_Y + connect \$15 $or$libresoc.v:135591$6826_Y + connect \$17 $and$libresoc.v:135592$6827_Y + connect \$1 $or$libresoc.v:135593$6828_Y + connect \$19 $not$libresoc.v:135594$6829_Y + connect \$21 $and$libresoc.v:135595$6830_Y + connect \$23 $or$libresoc.v:135596$6831_Y + connect \$25 $not$libresoc.v:135597$6832_Y + connect \$27 $or$libresoc.v:135598$6833_Y + connect \$29 $or$libresoc.v:135599$6834_Y + connect \$31 $and$libresoc.v:135600$6835_Y + connect \$33 $not$libresoc.v:135601$6836_Y + connect \$35 $and$libresoc.v:135602$6837_Y + connect \$37 $or$libresoc.v:135603$6838_Y + connect \$3 $and$libresoc.v:135604$6839_Y + connect \$39 $not$libresoc.v:135605$6840_Y + connect \$41 $or$libresoc.v:135606$6841_Y + connect \$43 $or$libresoc.v:135607$6842_Y + connect \$45 $and$libresoc.v:135608$6843_Y + connect \$47 $not$libresoc.v:135609$6844_Y + connect \$49 $and$libresoc.v:135610$6845_Y + connect \$51 $or$libresoc.v:135611$6846_Y + connect \$53 $not$libresoc.v:135612$6847_Y + connect \$55 $or$libresoc.v:135613$6848_Y + connect \$57 $or$libresoc.v:135614$6849_Y + connect \$5 $not$libresoc.v:135615$6850_Y + connect \$59 $and$libresoc.v:135616$6851_Y + connect \$61 $not$libresoc.v:135617$6852_Y + connect \$63 $and$libresoc.v:135618$6853_Y + connect \$65 $or$libresoc.v:135619$6854_Y + connect \$67 $and$libresoc.v:135620$6855_Y + connect \$69 $not$libresoc.v:135621$6856_Y + connect \$71 $and$libresoc.v:135622$6857_Y + connect \$73 $or$libresoc.v:135623$6858_Y + connect \$75 $and$libresoc.v:135624$6859_Y + connect \$77 $not$libresoc.v:135625$6860_Y + connect \$7 $and$libresoc.v:135626$6861_Y + connect \$79 $and$libresoc.v:135627$6862_Y + connect \$81 $and$libresoc.v:135628$6863_Y + connect \$83 $not$libresoc.v:135629$6864_Y + connect \$85 $not$libresoc.v:135630$6865_Y + connect \$87 $and$libresoc.v:135631$6866_Y + connect \$89 $not$libresoc.v:135632$6867_Y + connect \$91 $and$libresoc.v:135633$6868_Y + connect \$93 $not$libresoc.v:135634$6869_Y + connect \$95 $or$libresoc.v:135635$6870_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 - connect \x_busy_o \dbus__cyc end -attribute \src "libresoc.v:133543.1-134498.10" +attribute \src "libresoc.v:135946.1-136901.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:134070.3-134092.6" + attribute \src "libresoc.v:136473.3-136495.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:134169.3-134195.6" + attribute \src "libresoc.v:136572.3-136598.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:134450.3-134460.6" + attribute \src "libresoc.v:136853.3-136863.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:134420.3-134429.6" + attribute \src "libresoc.v:136823.3-136832.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:134430.3-134439.6" + attribute \src "libresoc.v:136833.3-136842.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:134440.3-134449.6" + attribute \src "libresoc.v:136843.3-136852.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:134308.3-134330.6" + attribute \src "libresoc.v:136711.3-136733.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:134294.3-134307.6" + attribute \src "libresoc.v:136697.3-136710.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:134461.3-134471.6" + attribute \src "libresoc.v:136864.3-136874.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:134472.3-134482.6" + attribute \src "libresoc.v:136875.3-136885.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:134196.3-134221.6" + attribute \src "libresoc.v:136599.3-136624.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:134222.3-134236.6" + attribute \src "libresoc.v:136625.3-136639.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:134400.3-134419.6" + attribute \src "libresoc.v:136803.3-136822.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:133544.7-133544.20" + attribute \src "libresoc.v:135947.7-135947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134060.3-134069.6" + attribute \src "libresoc.v:136463.3-136472.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:134131.3-134149.6" + attribute \src "libresoc.v:136534.3-136552.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:134150.3-134168.6" + attribute \src "libresoc.v:136553.3-136571.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:134237.3-134274.6" + attribute \src "libresoc.v:136640.3-136677.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:134275.3-134293.6" + attribute \src "libresoc.v:136678.3-136696.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:134353.3-134366.6" + attribute \src "libresoc.v:136756.3-136769.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:134389.3-134399.6" + attribute \src "libresoc.v:136792.3-136802.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:134104.3-134130.6" + attribute \src "libresoc.v:136507.3-136533.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:134331.3-134341.6" - wire width 2 $0\xer_ca$20[1:0]$6753 - attribute \src "libresoc.v:134342.3-134352.6" + attribute \src "libresoc.v:136734.3-136744.6" + wire width 2 $0\xer_ca$20[1:0]$7023 + attribute \src "libresoc.v:136745.3-136755.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:134367.3-134377.6" + attribute \src "libresoc.v:136770.3-136780.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:134378.3-134388.6" + attribute \src "libresoc.v:136781.3-136791.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:134093.3-134103.6" + attribute \src "libresoc.v:136496.3-136506.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:134483.3-134493.6" + attribute \src "libresoc.v:136886.3-136896.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:134070.3-134092.6" + attribute \src "libresoc.v:136473.3-136495.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:134169.3-134195.6" + attribute \src "libresoc.v:136572.3-136598.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:134450.3-134460.6" + attribute \src "libresoc.v:136853.3-136863.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:134420.3-134429.6" + attribute \src "libresoc.v:136823.3-136832.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:134430.3-134439.6" + attribute \src "libresoc.v:136833.3-136842.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:134440.3-134449.6" + attribute \src "libresoc.v:136843.3-136852.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:134308.3-134330.6" + attribute \src "libresoc.v:136711.3-136733.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:134294.3-134307.6" + attribute \src "libresoc.v:136697.3-136710.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:134461.3-134471.6" + attribute \src "libresoc.v:136864.3-136874.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:134472.3-134482.6" + attribute \src "libresoc.v:136875.3-136885.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:134196.3-134221.6" + attribute \src "libresoc.v:136599.3-136624.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:134222.3-134236.6" + attribute \src "libresoc.v:136625.3-136639.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:134400.3-134419.6" + attribute \src "libresoc.v:136803.3-136822.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:134060.3-134069.6" + attribute \src "libresoc.v:136463.3-136472.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:134131.3-134149.6" + attribute \src "libresoc.v:136534.3-136552.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:134150.3-134168.6" + attribute \src "libresoc.v:136553.3-136571.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:134237.3-134274.6" + attribute \src "libresoc.v:136640.3-136677.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:134275.3-134293.6" + attribute \src "libresoc.v:136678.3-136696.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:134353.3-134366.6" + attribute \src "libresoc.v:136756.3-136769.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:134389.3-134399.6" + attribute \src "libresoc.v:136792.3-136802.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:134104.3-134130.6" + attribute \src "libresoc.v:136507.3-136533.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:134331.3-134341.6" - wire width 2 $1\xer_ca$20[1:0]$6754 - attribute \src "libresoc.v:134342.3-134352.6" + attribute \src "libresoc.v:136734.3-136744.6" + wire width 2 $1\xer_ca$20[1:0]$7024 + attribute \src "libresoc.v:136745.3-136755.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:134367.3-134377.6" + attribute \src "libresoc.v:136770.3-136780.6" wire width 2 $1\xer_ov[1:0] - attribute \src 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"libresoc.v:136553.3-136571.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:134237.3-134274.6" + attribute \src "libresoc.v:136640.3-136677.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:134104.3-134130.6" + attribute \src "libresoc.v:136507.3-136533.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:134169.3-134195.6" + attribute \src "libresoc.v:136572.3-136598.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:134237.3-134274.6" + attribute \src "libresoc.v:136640.3-136677.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:134104.3-134130.6" + attribute \src "libresoc.v:136507.3-136533.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:134237.3-134274.6" + attribute \src "libresoc.v:136640.3-136677.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:134035.18-134035.105" - wire width 67 $add$libresoc.v:134035$6714_Y - attribute \src "libresoc.v:134009.19-134009.107" - wire $and$libresoc.v:134009$6688_Y - attribute \src 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"libresoc.v:134043.18-134043.99" - wire $reduce_or$libresoc.v:134043$6722_Y - attribute \src "libresoc.v:134052.18-134052.121" - wire $ternary$libresoc.v:134052$6731_Y - attribute \src "libresoc.v:134055.18-134055.119" - wire $ternary$libresoc.v:134055$6734_Y - attribute \src "libresoc.v:134059.18-134059.123" - wire $ternary$libresoc.v:134059$6738_Y - attribute \src "libresoc.v:134004.19-134004.111" - wire $xor$libresoc.v:134004$6683_Y - attribute \src "libresoc.v:134005.19-134005.111" - wire $xor$libresoc.v:134005$6684_Y - attribute \src "libresoc.v:134006.19-134006.110" - wire $xor$libresoc.v:134006$6685_Y - attribute \src "libresoc.v:134007.19-134007.110" - wire $xor$libresoc.v:134007$6686_Y - attribute \src "libresoc.v:134010.19-134010.110" - wire $xor$libresoc.v:134010$6689_Y - attribute \src "libresoc.v:134011.19-134011.110" - wire $xor$libresoc.v:134011$6690_Y - attribute \src "libresoc.v:134037.18-134037.111" - wire $xor$libresoc.v:134037$6716_Y - attribute \src "libresoc.v:134038.18-134038.107" - wire $xor$libresoc.v:134038$6717_Y - attribute \src "libresoc.v:134039.18-134039.113" - wire width 32 $xor$libresoc.v:134039$6718_Y - attribute \src "libresoc.v:134042.18-134042.115" - wire width 32 $xor$libresoc.v:134042$6721_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + attribute \src "libresoc.v:136438.18-136438.105" + wire width 67 $add$libresoc.v:136438$6984_Y + attribute \src "libresoc.v:136412.19-136412.107" + wire $and$libresoc.v:136412$6958_Y + attribute \src "libresoc.v:136416.19-136416.107" + wire $and$libresoc.v:136416$6962_Y + attribute \src "libresoc.v:136449.18-136449.106" + wire $and$libresoc.v:136449$6995_Y + attribute \src "libresoc.v:136454.18-136454.106" + wire $and$libresoc.v:136454$7000_Y + attribute \src "libresoc.v:136457.18-136457.106" + wire $and$libresoc.v:136457$7003_Y + attribute \src "libresoc.v:136460.18-136460.106" + wire $and$libresoc.v:136460$7006_Y + attribute \src "libresoc.v:136403.19-136403.118" + wire $eq$libresoc.v:136403$6949_Y + attribute \src "libresoc.v:136404.19-136404.118" + wire $eq$libresoc.v:136404$6950_Y + attribute \src "libresoc.v:136405.19-136405.118" + wire $eq$libresoc.v:136405$6951_Y + attribute \src "libresoc.v:136417.19-136417.109" + wire $eq$libresoc.v:136417$6963_Y + attribute \src "libresoc.v:136418.19-136418.110" + wire $eq$libresoc.v:136418$6964_Y + attribute \src "libresoc.v:136419.19-136419.111" + wire $eq$libresoc.v:136419$6965_Y + attribute \src "libresoc.v:136420.19-136420.111" + wire $eq$libresoc.v:136420$6966_Y + attribute \src "libresoc.v:136421.19-136421.111" + wire $eq$libresoc.v:136421$6967_Y + attribute \src "libresoc.v:136422.19-136422.111" + wire $eq$libresoc.v:136422$6968_Y + attribute \src "libresoc.v:136423.19-136423.111" + wire $eq$libresoc.v:136423$6969_Y + attribute \src "libresoc.v:136424.19-136424.111" + wire $eq$libresoc.v:136424$6970_Y + attribute \src "libresoc.v:136425.18-136425.118" + wire $eq$libresoc.v:136425$6971_Y + attribute \src "libresoc.v:136427.18-136427.118" + wire $eq$libresoc.v:136427$6973_Y + attribute \src "libresoc.v:136428.18-136428.118" + wire $eq$libresoc.v:136428$6974_Y + attribute \src "libresoc.v:136429.18-136429.118" + wire $eq$libresoc.v:136429$6975_Y + attribute \src "libresoc.v:136430.18-136430.118" + wire $eq$libresoc.v:136430$6976_Y + attribute \src "libresoc.v:136432.18-136432.118" + wire $eq$libresoc.v:136432$6978_Y + attribute \src "libresoc.v:136433.18-136433.118" + wire $eq$libresoc.v:136433$6979_Y + attribute \src "libresoc.v:136435.18-136435.118" + wire $eq$libresoc.v:136435$6981_Y + attribute \src "libresoc.v:136436.18-136436.118" + wire $eq$libresoc.v:136436$6982_Y + attribute \src "libresoc.v:136450.18-136450.107" + wire $ne$libresoc.v:136450$6996_Y + attribute \src "libresoc.v:136461.18-136461.107" + wire $ne$libresoc.v:136461$7007_Y + attribute \src "libresoc.v:136411.19-136411.100" + wire $not$libresoc.v:136411$6957_Y + attribute \src "libresoc.v:136415.19-136415.100" + wire $not$libresoc.v:136415$6961_Y + attribute \src "libresoc.v:136426.18-136426.110" + wire $not$libresoc.v:136426$6972_Y + attribute \src "libresoc.v:136439.18-136439.97" + wire width 64 $not$libresoc.v:136439$6985_Y + attribute \src "libresoc.v:136444.18-136444.99" + wire $not$libresoc.v:136444$6990_Y + attribute \src "libresoc.v:136447.18-136447.99" + wire $not$libresoc.v:136447$6993_Y + attribute \src "libresoc.v:136451.18-136451.99" + wire $not$libresoc.v:136451$6997_Y + attribute \src "libresoc.v:136452.18-136452.99" + wire $not$libresoc.v:136452$6998_Y + attribute \src "libresoc.v:136431.18-136431.104" + wire $or$libresoc.v:136431$6977_Y + attribute \src "libresoc.v:136434.18-136434.104" + wire $or$libresoc.v:136434$6980_Y + attribute \src "libresoc.v:136437.18-136437.104" + wire $or$libresoc.v:136437$6983_Y + attribute \src "libresoc.v:136448.18-136448.110" + wire $or$libresoc.v:136448$6994_Y + attribute \src "libresoc.v:136453.18-136453.110" + wire $or$libresoc.v:136453$6999_Y + attribute \src "libresoc.v:136456.18-136456.110" + wire $or$libresoc.v:136456$7002_Y + attribute \src "libresoc.v:136459.18-136459.110" + wire $or$libresoc.v:136459$7005_Y + attribute \src "libresoc.v:136402.18-136402.98" + wire $reduce_or$libresoc.v:136402$6948_Y + attribute \src "libresoc.v:136406.19-136406.99" + wire $reduce_or$libresoc.v:136406$6952_Y + attribute \src "libresoc.v:136443.18-136443.99" + wire $reduce_or$libresoc.v:136443$6989_Y + attribute \src "libresoc.v:136446.18-136446.99" + wire $reduce_or$libresoc.v:136446$6992_Y + attribute \src "libresoc.v:136455.18-136455.121" + wire $ternary$libresoc.v:136455$7001_Y + attribute \src "libresoc.v:136458.18-136458.119" + wire $ternary$libresoc.v:136458$7004_Y + attribute \src "libresoc.v:136462.18-136462.123" + wire $ternary$libresoc.v:136462$7008_Y + attribute \src "libresoc.v:136407.19-136407.111" + wire $xor$libresoc.v:136407$6953_Y + attribute \src "libresoc.v:136408.19-136408.111" + wire $xor$libresoc.v:136408$6954_Y + attribute \src "libresoc.v:136409.19-136409.110" + wire $xor$libresoc.v:136409$6955_Y + attribute \src "libresoc.v:136410.19-136410.110" + wire $xor$libresoc.v:136410$6956_Y + attribute \src "libresoc.v:136413.19-136413.110" + wire $xor$libresoc.v:136413$6959_Y + attribute \src "libresoc.v:136414.19-136414.110" + wire $xor$libresoc.v:136414$6960_Y + attribute \src "libresoc.v:136440.18-136440.111" + wire $xor$libresoc.v:136440$6986_Y + attribute \src "libresoc.v:136441.18-136441.107" + wire $xor$libresoc.v:136441$6987_Y + attribute \src "libresoc.v:136442.18-136442.113" + wire width 32 $xor$libresoc.v:136442$6988_Y + attribute \src "libresoc.v:136445.18-136445.115" + wire width 32 $xor$libresoc.v:136445$6991_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" wire \$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" wire \$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire \$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" wire width 67 \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" wire width 67 \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" wire width 64 \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" wire width 32 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" wire width 32 \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire \$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" wire width 64 \a_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" wire \a_lt - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" wire width 64 \a_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" wire width 66 \add_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" wire width 66 \add_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" wire width 66 \add_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \alu_op__data_len @@ -279752,66 +285847,66 @@ module \main wire input 10 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" wire width 64 \b_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" wire \carry_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" wire \carry_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:133544.7-133544.15" + attribute \src "libresoc.v:135947.7-135947.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" wire \msb_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" wire \msb_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" wire width 2 \ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" wire width 8 \src1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" wire width 5 \tval attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" wire \zerohi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $add $add$libresoc.v:134035$6714 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" + cell $add $add$libresoc.v:136438$6984 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -279819,10 +285914,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:134035$6714_Y + connect \Y $add$libresoc.v:136438$6984_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $and$libresoc.v:134009$6688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:136412$6958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279830,10 +285925,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:134009$6688_Y + connect \Y $and$libresoc.v:136412$6958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $and$libresoc.v:134013$6692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:136416$6962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279841,10 +285936,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:134013$6692_Y + connect \Y $and$libresoc.v:136416$6962_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$libresoc.v:134046$6725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136449$6995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279852,10 +285947,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:134046$6725_Y + connect \Y $and$libresoc.v:136449$6995_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$libresoc.v:134051$6730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136454$7000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279863,10 +285958,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:134051$6730_Y + connect \Y $and$libresoc.v:136454$7000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$libresoc.v:134054$6733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136457$7003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279874,10 +285969,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:134054$6733_Y + connect \Y $and$libresoc.v:136457$7003_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $and$libresoc.v:134057$6736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:136460$7006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279885,10 +285980,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:134057$6736_Y + connect \Y $and$libresoc.v:136460$7006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - cell $eq $eq$libresoc.v:134000$6679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$libresoc.v:136403$6949 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -279896,10 +285991,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:134000$6679_Y + connect \Y $eq$libresoc.v:136403$6949_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - cell $eq $eq$libresoc.v:134001$6680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + cell $eq $eq$libresoc.v:136404$6950 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -279907,10 +286002,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:134001$6680_Y + connect \Y $eq$libresoc.v:136404$6950_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:134002$6681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + cell $eq $eq$libresoc.v:136405$6951 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -279918,10 +286013,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:134002$6681_Y + connect \Y $eq$libresoc.v:136405$6951_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134014$6693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136417$6963 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279929,10 +286024,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:134014$6693_Y + connect \Y $eq$libresoc.v:136417$6963_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134015$6694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136418$6964 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279940,10 +286035,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:134015$6694_Y + connect \Y $eq$libresoc.v:136418$6964_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134016$6695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136419$6965 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279951,10 +286046,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:134016$6695_Y + connect \Y $eq$libresoc.v:136419$6965_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134017$6696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136420$6966 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279962,10 +286057,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:134017$6696_Y + connect \Y $eq$libresoc.v:136420$6966_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134018$6697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136421$6967 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279973,10 +286068,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:134018$6697_Y + connect \Y $eq$libresoc.v:136421$6967_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134019$6698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136422$6968 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279984,10 +286079,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:134019$6698_Y + connect \Y $eq$libresoc.v:136422$6968_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134020$6699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136423$6969 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -279995,10 +286090,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:134020$6699_Y + connect \Y $eq$libresoc.v:136423$6969_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $eq$libresoc.v:134021$6700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:136424$6970 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280006,10 +286101,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:134021$6700_Y + connect \Y $eq$libresoc.v:136424$6970_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - cell $eq $eq$libresoc.v:134022$6701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + cell $eq $eq$libresoc.v:136425$6971 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280017,10 +286112,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134022$6701_Y + connect \Y $eq$libresoc.v:136425$6971_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $eq$libresoc.v:134024$6703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:136427$6973 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280028,10 +286123,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134024$6703_Y + connect \Y $eq$libresoc.v:136427$6973_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $eq$libresoc.v:134025$6704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:136428$6974 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280039,10 +286134,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134025$6704_Y + connect \Y $eq$libresoc.v:136428$6974_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$libresoc.v:134026$6705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136429$6975 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280050,10 +286145,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:134026$6705_Y + connect \Y $eq$libresoc.v:136429$6975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$libresoc.v:134027$6706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136430$6976 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280061,10 +286156,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134027$6706_Y + connect \Y $eq$libresoc.v:136430$6976_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$libresoc.v:134029$6708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136432$6978 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280072,10 +286167,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:134029$6708_Y + connect \Y $eq$libresoc.v:136432$6978_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$libresoc.v:134030$6709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136433$6979 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280083,10 +286178,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134030$6709_Y + connect \Y $eq$libresoc.v:136433$6979_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $eq$libresoc.v:134032$6711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:136435$6981 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280094,10 +286189,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:134032$6711_Y + connect \Y $eq$libresoc.v:136435$6981_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $eq$libresoc.v:134033$6712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:136436$6982 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -280105,10 +286200,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:134033$6712_Y + connect \Y $eq$libresoc.v:136436$6982_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $ne$libresoc.v:134047$6726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:136450$6996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280116,10 +286211,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:134047$6726_Y + connect \Y $ne$libresoc.v:136450$6996_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $ne$libresoc.v:134058$6737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:136461$7007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280127,74 +286222,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:134058$6737_Y + connect \Y $ne$libresoc.v:136461$7007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $not$libresoc.v:134008$6687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:136411$6957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:134008$6687_Y + connect \Y $not$libresoc.v:136411$6957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $not$libresoc.v:134012$6691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:136415$6961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:134012$6691_Y + connect \Y $not$libresoc.v:136415$6961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" - cell $not $not$libresoc.v:134023$6702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + cell $not $not$libresoc.v:136426$6972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:134023$6702_Y + connect \Y $not$libresoc.v:136426$6972_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - cell $not $not$libresoc.v:134036$6715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $not$libresoc.v:136439$6985 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:134036$6715_Y + connect \Y $not$libresoc.v:136439$6985_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:134041$6720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $not $not$libresoc.v:136444$6990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:134041$6720_Y + connect \Y $not$libresoc.v:136444$6990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $not $not$libresoc.v:134044$6723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $not $not$libresoc.v:136447$6993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:134044$6723_Y + connect \Y $not$libresoc.v:136447$6993_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $not$libresoc.v:134048$6727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:136451$6997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:134048$6727_Y + connect \Y $not$libresoc.v:136451$6997_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $not$libresoc.v:134049$6728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:136452$6998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:134049$6728_Y + connect \Y $not$libresoc.v:136452$6998_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$libresoc.v:134028$6707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136431$6977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280202,10 +286297,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:134028$6707_Y + connect \Y $or$libresoc.v:136431$6977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$libresoc.v:134031$6710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136434$6980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280213,10 +286308,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:134031$6710_Y + connect \Y $or$libresoc.v:136434$6980_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $or$libresoc.v:134034$6713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:136437$6983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280224,10 +286319,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:134034$6713_Y + connect \Y $or$libresoc.v:136437$6983_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$libresoc.v:134045$6724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136448$6994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280235,10 +286330,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:134045$6724_Y + connect \Y $or$libresoc.v:136448$6994_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$libresoc.v:134050$6729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136453$6999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280246,10 +286341,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:134050$6729_Y + connect \Y $or$libresoc.v:136453$6999_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$libresoc.v:134053$6732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136456$7002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280257,10 +286352,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:134053$6732_Y + connect \Y $or$libresoc.v:136456$7002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $or$libresoc.v:134056$6735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:136459$7005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280268,66 +286363,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:134056$6735_Y + connect \Y $or$libresoc.v:136459$7005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" - cell $reduce_or $reduce_or$libresoc.v:133999$6678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" + cell $reduce_or $reduce_or$libresoc.v:136402$6948 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:133999$6678_Y + connect \Y $reduce_or$libresoc.v:136402$6948_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - cell $reduce_or $reduce_or$libresoc.v:134003$6682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" + cell $reduce_or $reduce_or$libresoc.v:136406$6952 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:134003$6682_Y + connect \Y $reduce_or$libresoc.v:136406$6952_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $reduce_or $reduce_or$libresoc.v:134040$6719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $reduce_or $reduce_or$libresoc.v:136443$6989 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:134040$6719_Y + connect \Y $reduce_or$libresoc.v:136443$6989_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $reduce_or $reduce_or$libresoc.v:134043$6722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $reduce_or $reduce_or$libresoc.v:136446$6992 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:134043$6722_Y + connect \Y $reduce_or$libresoc.v:136446$6992_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $mux $ternary$libresoc.v:134052$6731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" + cell $mux $ternary$libresoc.v:136455$7001 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:134052$6731_Y + connect \Y $ternary$libresoc.v:136455$7001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - cell $mux $ternary$libresoc.v:134055$6734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $mux $ternary$libresoc.v:136458$7004 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:134055$6734_Y + connect \Y $ternary$libresoc.v:136458$7004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" - cell $mux $ternary$libresoc.v:134059$6738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + cell $mux $ternary$libresoc.v:136462$7008 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:134059$6738_Y + connect \Y $ternary$libresoc.v:136462$7008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $xor$libresoc.v:134004$6683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:136407$6953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280335,10 +286430,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:134004$6683_Y + connect \Y $xor$libresoc.v:136407$6953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $xor$libresoc.v:134005$6684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:136408$6954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280346,10 +286441,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:134005$6684_Y + connect \Y $xor$libresoc.v:136408$6954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$libresoc.v:134006$6685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136409$6955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280357,10 +286452,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:134006$6685_Y + connect \Y $xor$libresoc.v:136409$6955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$libresoc.v:134007$6686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136410$6956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280368,10 +286463,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:134007$6686_Y + connect \Y $xor$libresoc.v:136410$6956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$libresoc.v:134010$6689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136413$6959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280379,10 +286474,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:134010$6689_Y + connect \Y $xor$libresoc.v:136413$6959_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $xor$libresoc.v:134011$6690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:136414$6960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280390,10 +286485,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:134011$6690_Y + connect \Y $xor$libresoc.v:136414$6960_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $xor$libresoc.v:134037$6716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:136440$6986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280401,10 +286496,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:134037$6716_Y + connect \Y $xor$libresoc.v:136440$6986_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $xor$libresoc.v:134038$6717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:136441$6987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280412,10 +286507,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:134038$6717_Y + connect \Y $xor$libresoc.v:136441$6987_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $xor $xor$libresoc.v:134039$6718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $xor $xor$libresoc.v:136442$6988 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -280423,10 +286518,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:134039$6718_Y + connect \Y $xor$libresoc.v:136442$6988_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:134042$6721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $xor $xor$libresoc.v:136445$6991 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -280434,28 +286529,28 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:134042$6721_Y + connect \Y $xor$libresoc.v:136445$6991_Y end - attribute \src "libresoc.v:133544.7-133544.20" - process $proc$libresoc.v:133544$6768 + attribute \src "libresoc.v:135947.7-135947.20" + process $proc$libresoc.v:135947$7038 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134060.3-134069.6" - process $proc$libresoc.v:134060$6739 + attribute \src "libresoc.v:136463.3-136472.6" + process $proc$libresoc.v:136463$7009 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:134061.5-134061.29" + attribute \src "libresoc.v:136464.5-136464.29" switch \initial - attribute \src "libresoc.v:134061.9-134061.17" + attribute \src "libresoc.v:136464.9-136464.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" switch \$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280467,17 +286562,17 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:134070.3-134092.6" - process $proc$libresoc.v:134070$6740 + attribute \src "libresoc.v:136473.3-136495.6" + process $proc$libresoc.v:136473$7010 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:134071.5-134071.29" + attribute \src "libresoc.v:136474.5-136474.29" switch \initial - attribute \src "libresoc.v:134071.9-134071.17" + attribute \src "libresoc.v:136474.9-136474.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" switch { \is_32bit \$26 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -280487,7 +286582,7 @@ module \main case 2'1- assign { } { } assign $1\a_i[63:0] $2\a_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280506,18 +286601,18 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:134093.3-134103.6" - process $proc$libresoc.v:134093$6741 + attribute \src "libresoc.v:136496.3-136506.6" + process $proc$libresoc.v:136496$7011 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:134094.5-134094.29" + attribute \src "libresoc.v:136497.5-136497.29" switch \initial - attribute \src "libresoc.v:134094.9-134094.17" + attribute \src "libresoc.v:136497.9-136497.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -280529,24 +286624,24 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:134104.3-134130.6" - process $proc$libresoc.v:134104$6742 + attribute \src "libresoc.v:136507.3-136533.6" + process $proc$libresoc.v:136507$7012 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:134105.5-134105.29" + attribute \src "libresoc.v:136508.5-136508.29" switch \initial - attribute \src "libresoc.v:134105.9-134105.17" + attribute \src "libresoc.v:136508.9-136508.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\tval[4:0] $2\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280556,7 +286651,7 @@ module \main case assign { } { } assign $2\tval[4:0] $3\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" switch \$73 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280574,24 +286669,24 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:134131.3-134149.6" - process $proc$libresoc.v:134131$6743 + attribute \src "libresoc.v:136534.3-136552.6" + process $proc$libresoc.v:136534$7013 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:134132.5-134132.29" + attribute \src "libresoc.v:136535.5-136535.29" switch \initial - attribute \src "libresoc.v:134132.9-134132.17" + attribute \src "libresoc.v:136535.9-136535.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\msb_a[0:0] $2\msb_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280607,24 +286702,24 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:134150.3-134168.6" - process $proc$libresoc.v:134150$6744 + attribute \src "libresoc.v:136553.3-136571.6" + process $proc$libresoc.v:136553$7014 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:134151.5-134151.29" + attribute \src "libresoc.v:136554.5-136554.29" switch \initial - attribute \src "libresoc.v:134151.9-134151.17" + attribute \src "libresoc.v:136554.9-136554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\msb_b[0:0] $2\msb_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280640,24 +286735,24 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:134169.3-134195.6" - process $proc$libresoc.v:134169$6745 + attribute \src "libresoc.v:136572.3-136598.6" + process $proc$libresoc.v:136572$7015 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:134170.5-134170.29" + attribute \src "libresoc.v:136573.5-136573.29" switch \initial - attribute \src "libresoc.v:134170.9-134170.17" + attribute \src "libresoc.v:136573.9-136573.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\a_lt[0:0] $2\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280666,7 +286761,7 @@ module \main case assign { } { } assign $2\a_lt[0:0] $3\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280683,25 +286778,25 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:134196.3-134221.6" - process $proc$libresoc.v:134196$6746 + attribute \src "libresoc.v:136599.3-136624.6" + process $proc$libresoc.v:136599$7016 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:134197.5-134197.29" + attribute \src "libresoc.v:136600.5-136600.29" switch \initial - attribute \src "libresoc.v:134197.9-134197.17" + attribute \src "libresoc.v:136600.9-136600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 assign { } { } assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280722,18 +286817,18 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:134222.3-134236.6" - process $proc$libresoc.v:134222$6747 + attribute \src "libresoc.v:136625.3-136639.6" + process $proc$libresoc.v:136625$7017 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:134223.5-134223.29" + attribute \src "libresoc.v:136626.5-136626.29" switch \initial - attribute \src "libresoc.v:134223.9-134223.17" + attribute \src "libresoc.v:136626.9-136626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -280749,18 +286844,18 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:134237.3-134274.6" - process $proc$libresoc.v:134237$6748 + attribute \src "libresoc.v:136640.3-136677.6" + process $proc$libresoc.v:136640$7018 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:134238.5-134238.29" + attribute \src "libresoc.v:136641.5-136641.29" switch \initial - attribute \src "libresoc.v:134238.9-134238.17" + attribute \src "libresoc.v:136641.9-136641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280772,7 +286867,7 @@ module \main assign { } { } assign { } { } assign $1\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280781,7 +286876,7 @@ module \main case assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280790,7 +286885,7 @@ module \main case assign $3\o[63:0] $2\o[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" switch \$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280809,18 +286904,18 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:134275.3-134293.6" - process $proc$libresoc.v:134275$6749 + attribute \src "libresoc.v:136678.3-136696.6" + process $proc$libresoc.v:136678$7019 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:134276.5-134276.29" + attribute \src "libresoc.v:136679.5-136679.29" switch \initial - attribute \src "libresoc.v:134276.9-134276.17" + attribute \src "libresoc.v:136679.9-136679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280840,18 +286935,18 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:134294.3-134307.6" - process $proc$libresoc.v:134294$6750 + attribute \src "libresoc.v:136697.3-136710.6" + process $proc$libresoc.v:136697$7020 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:134295.5-134295.29" + attribute \src "libresoc.v:136698.5-136698.29" switch \initial - attribute \src "libresoc.v:134295.9-134295.17" + attribute \src "libresoc.v:136698.9-136698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280864,17 +286959,17 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:134308.3-134330.6" - process $proc$libresoc.v:134308$6751 + attribute \src "libresoc.v:136711.3-136733.6" + process $proc$libresoc.v:136711$7021 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:134309.5-134309.29" + attribute \src "libresoc.v:136712.5-136712.29" switch \initial - attribute \src "libresoc.v:134309.9-134309.17" + attribute \src "libresoc.v:136712.9-136712.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" switch { \is_32bit \$28 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -280884,7 +286979,7 @@ module \main case 2'1- assign { } { } assign $1\b_i[63:0] $2\b_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" switch \alu_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -280903,41 +286998,41 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:134331.3-134341.6" - process $proc$libresoc.v:134331$6752 + attribute \src "libresoc.v:136734.3-136744.6" + process $proc$libresoc.v:136734$7022 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$6753 $1\xer_ca$20[1:0]$6754 - attribute \src "libresoc.v:134332.5-134332.29" + assign $0\xer_ca$20[1:0]$7023 $1\xer_ca$20[1:0]$7024 + attribute \src "libresoc.v:136735.5-136735.29" switch \initial - attribute \src "libresoc.v:134332.9-134332.17" + attribute \src "libresoc.v:136735.9-136735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$6754 \ca + assign $1\xer_ca$20[1:0]$7024 \ca case - assign $1\xer_ca$20[1:0]$6754 2'00 + assign $1\xer_ca$20[1:0]$7024 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$6753 + update \xer_ca$20 $0\xer_ca$20[1:0]$7023 end - attribute \src "libresoc.v:134342.3-134352.6" - process $proc$libresoc.v:134342$6755 + attribute \src "libresoc.v:136745.3-136755.6" + process $proc$libresoc.v:136745$7025 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:134343.5-134343.29" + attribute \src "libresoc.v:136746.5-136746.29" switch \initial - attribute \src "libresoc.v:134343.9-134343.17" + attribute \src "libresoc.v:136746.9-136746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280949,18 +287044,18 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:134353.3-134366.6" - process $proc$libresoc.v:134353$6756 + attribute \src "libresoc.v:136756.3-136769.6" + process $proc$libresoc.v:136756$7026 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:134354.5-134354.29" + attribute \src "libresoc.v:136757.5-136757.29" switch \initial - attribute \src "libresoc.v:134354.9-134354.17" + attribute \src "libresoc.v:136757.9-136757.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280973,18 +287068,18 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:134367.3-134377.6" - process $proc$libresoc.v:134367$6757 + attribute \src "libresoc.v:136770.3-136780.6" + process $proc$libresoc.v:136770$7027 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:134368.5-134368.29" + attribute \src "libresoc.v:136771.5-136771.29" switch \initial - attribute \src "libresoc.v:134368.9-134368.17" + attribute \src "libresoc.v:136771.9-136771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -280996,18 +287091,18 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:134378.3-134388.6" - process $proc$libresoc.v:134378$6758 + attribute \src "libresoc.v:136781.3-136791.6" + process $proc$libresoc.v:136781$7028 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:134379.5-134379.29" + attribute \src "libresoc.v:136782.5-136782.29" switch \initial - attribute \src "libresoc.v:134379.9-134379.17" + attribute \src "libresoc.v:136782.9-136782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0000010 @@ -281019,18 +287114,18 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:134389.3-134399.6" - process $proc$libresoc.v:134389$6759 + attribute \src "libresoc.v:136792.3-136802.6" + process $proc$libresoc.v:136792$7029 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:134390.5-134390.29" + attribute \src "libresoc.v:136793.5-136793.29" switch \initial - attribute \src "libresoc.v:134390.9-134390.17" + attribute \src "libresoc.v:136793.9-136793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001100 @@ -281042,18 +287137,18 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:134400.3-134419.6" - process $proc$libresoc.v:134400$6760 + attribute \src "libresoc.v:136803.3-136822.6" + process $proc$libresoc.v:136803$7030 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:134401.5-134401.29" + attribute \src "libresoc.v:136804.5-136804.29" switch \initial - attribute \src "libresoc.v:134401.9-134401.17" + attribute \src "libresoc.v:136804.9-136804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001100 @@ -281072,18 +287167,18 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:134420.3-134429.6" - process $proc$libresoc.v:134420$6761 + attribute \src "libresoc.v:136823.3-136832.6" + process $proc$libresoc.v:136823$7031 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:134421.5-134421.29" + attribute \src "libresoc.v:136824.5-136824.29" switch \initial - attribute \src "libresoc.v:134421.9-134421.17" + attribute \src "libresoc.v:136824.9-136824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -281095,18 +287190,18 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:134430.3-134439.6" - process $proc$libresoc.v:134430$6762 + attribute \src "libresoc.v:136833.3-136842.6" + process $proc$libresoc.v:136833$7032 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:134431.5-134431.29" + attribute \src "libresoc.v:136834.5-136834.29" switch \initial - attribute \src "libresoc.v:134431.9-134431.17" + attribute \src "libresoc.v:136834.9-136834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -281118,18 +287213,18 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:134440.3-134449.6" - process $proc$libresoc.v:134440$6763 + attribute \src "libresoc.v:136843.3-136852.6" + process $proc$libresoc.v:136843$7033 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:134441.5-134441.29" + attribute \src "libresoc.v:136844.5-136844.29" switch \initial - attribute \src "libresoc.v:134441.9-134441.17" + attribute \src "libresoc.v:136844.9-136844.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -281141,18 +287236,18 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:134450.3-134460.6" - process $proc$libresoc.v:134450$6764 + attribute \src "libresoc.v:136853.3-136863.6" + process $proc$libresoc.v:136853$7034 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:134451.5-134451.29" + attribute \src "libresoc.v:136854.5-136854.29" switch \initial - attribute \src "libresoc.v:134451.9-134451.17" + attribute \src "libresoc.v:136854.9-136854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -281164,18 +287259,18 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:134461.3-134471.6" - process $proc$libresoc.v:134461$6765 + attribute \src "libresoc.v:136864.3-136874.6" + process $proc$libresoc.v:136864$7035 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:134462.5-134462.29" + attribute \src "libresoc.v:136865.5-136865.29" switch \initial - attribute \src "libresoc.v:134462.9-134462.17" + attribute \src "libresoc.v:136865.9-136865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -281187,18 +287282,18 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:134472.3-134482.6" - process $proc$libresoc.v:134472$6766 + attribute \src "libresoc.v:136875.3-136885.6" + process $proc$libresoc.v:136875$7036 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:134473.5-134473.29" + attribute \src "libresoc.v:136876.5-136876.29" switch \initial - attribute \src "libresoc.v:134473.9-134473.17" + attribute \src "libresoc.v:136876.9-136876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -281210,18 +287305,18 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:134483.3-134493.6" - process $proc$libresoc.v:134483$6767 + attribute \src "libresoc.v:136886.3-136896.6" + process $proc$libresoc.v:136886$7037 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:134484.5-134484.29" + attribute \src "libresoc.v:136887.5-136887.29" switch \initial - attribute \src "libresoc.v:134484.9-134484.17" + attribute \src "libresoc.v:136887.9-136887.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0001010 @@ -281233,88 +287328,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:133999$6678_Y - connect \$101 $eq$libresoc.v:134000$6679_Y - connect \$103 $eq$libresoc.v:134001$6680_Y - connect \$105 $eq$libresoc.v:134002$6681_Y - connect \$107 $reduce_or$libresoc.v:134003$6682_Y - connect \$109 $xor$libresoc.v:134004$6683_Y - connect \$111 $xor$libresoc.v:134005$6684_Y - connect \$113 $xor$libresoc.v:134006$6685_Y - connect \$116 $xor$libresoc.v:134007$6686_Y - connect \$115 $not$libresoc.v:134008$6687_Y - connect \$119 $and$libresoc.v:134009$6688_Y - connect \$121 $xor$libresoc.v:134010$6689_Y - connect \$124 $xor$libresoc.v:134011$6690_Y - connect \$123 $not$libresoc.v:134012$6691_Y - connect \$127 $and$libresoc.v:134013$6692_Y - connect \$129 $eq$libresoc.v:134014$6693_Y - connect \$131 $eq$libresoc.v:134015$6694_Y - connect \$133 $eq$libresoc.v:134016$6695_Y - connect \$135 $eq$libresoc.v:134017$6696_Y - connect \$137 $eq$libresoc.v:134018$6697_Y - connect \$139 $eq$libresoc.v:134019$6698_Y - connect \$141 $eq$libresoc.v:134020$6699_Y - connect \$143 $eq$libresoc.v:134021$6700_Y - connect \$22 $eq$libresoc.v:134022$6701_Y - connect \$24 $not$libresoc.v:134023$6702_Y - connect \$26 $eq$libresoc.v:134024$6703_Y - connect \$28 $eq$libresoc.v:134025$6704_Y - connect \$30 $eq$libresoc.v:134026$6705_Y - connect \$32 $eq$libresoc.v:134027$6706_Y - connect \$34 $or$libresoc.v:134028$6707_Y - connect \$36 $eq$libresoc.v:134029$6708_Y - connect \$38 $eq$libresoc.v:134030$6709_Y - connect \$40 $or$libresoc.v:134031$6710_Y - connect \$42 $eq$libresoc.v:134032$6711_Y - connect \$44 $eq$libresoc.v:134033$6712_Y - connect \$46 $or$libresoc.v:134034$6713_Y - connect \$49 $add$libresoc.v:134035$6714_Y - connect \$51 $not$libresoc.v:134036$6715_Y - connect \$53 $xor$libresoc.v:134037$6716_Y - connect \$55 $xor$libresoc.v:134038$6717_Y - connect \$59 $xor$libresoc.v:134039$6718_Y - connect \$58 $reduce_or$libresoc.v:134040$6719_Y - connect \$57 $not$libresoc.v:134041$6720_Y - connect \$65 $xor$libresoc.v:134042$6721_Y - connect \$64 $reduce_or$libresoc.v:134043$6722_Y - connect \$63 $not$libresoc.v:134044$6723_Y - connect \$69 $or$libresoc.v:134045$6724_Y - connect \$71 $and$libresoc.v:134046$6725_Y - connect \$73 $ne$libresoc.v:134047$6726_Y - connect \$75 $not$libresoc.v:134048$6727_Y - connect \$77 $not$libresoc.v:134049$6728_Y - connect \$79 $or$libresoc.v:134050$6729_Y - connect \$81 $and$libresoc.v:134051$6730_Y - connect \$83 $ternary$libresoc.v:134052$6731_Y - connect \$85 $or$libresoc.v:134053$6732_Y - connect \$87 $and$libresoc.v:134054$6733_Y - connect \$89 $ternary$libresoc.v:134055$6734_Y - connect \$91 $or$libresoc.v:134056$6735_Y - connect \$93 $and$libresoc.v:134057$6736_Y - connect \$95 $ne$libresoc.v:134058$6737_Y - connect \$97 $ternary$libresoc.v:134059$6738_Y + connect \$99 $reduce_or$libresoc.v:136402$6948_Y + connect \$101 $eq$libresoc.v:136403$6949_Y + connect \$103 $eq$libresoc.v:136404$6950_Y + connect \$105 $eq$libresoc.v:136405$6951_Y + connect \$107 $reduce_or$libresoc.v:136406$6952_Y + connect \$109 $xor$libresoc.v:136407$6953_Y + connect \$111 $xor$libresoc.v:136408$6954_Y + connect \$113 $xor$libresoc.v:136409$6955_Y + connect \$116 $xor$libresoc.v:136410$6956_Y + connect \$115 $not$libresoc.v:136411$6957_Y + connect \$119 $and$libresoc.v:136412$6958_Y + connect \$121 $xor$libresoc.v:136413$6959_Y + connect \$124 $xor$libresoc.v:136414$6960_Y + connect \$123 $not$libresoc.v:136415$6961_Y + connect \$127 $and$libresoc.v:136416$6962_Y + connect \$129 $eq$libresoc.v:136417$6963_Y + connect \$131 $eq$libresoc.v:136418$6964_Y + connect \$133 $eq$libresoc.v:136419$6965_Y + connect \$135 $eq$libresoc.v:136420$6966_Y + connect \$137 $eq$libresoc.v:136421$6967_Y + connect \$139 $eq$libresoc.v:136422$6968_Y + connect \$141 $eq$libresoc.v:136423$6969_Y + connect \$143 $eq$libresoc.v:136424$6970_Y + connect \$22 $eq$libresoc.v:136425$6971_Y + connect \$24 $not$libresoc.v:136426$6972_Y + connect \$26 $eq$libresoc.v:136427$6973_Y + connect \$28 $eq$libresoc.v:136428$6974_Y + connect \$30 $eq$libresoc.v:136429$6975_Y + connect \$32 $eq$libresoc.v:136430$6976_Y + connect \$34 $or$libresoc.v:136431$6977_Y + connect \$36 $eq$libresoc.v:136432$6978_Y + connect \$38 $eq$libresoc.v:136433$6979_Y + connect \$40 $or$libresoc.v:136434$6980_Y + connect \$42 $eq$libresoc.v:136435$6981_Y + connect \$44 $eq$libresoc.v:136436$6982_Y + connect \$46 $or$libresoc.v:136437$6983_Y + connect \$49 $add$libresoc.v:136438$6984_Y + connect \$51 $not$libresoc.v:136439$6985_Y + connect \$53 $xor$libresoc.v:136440$6986_Y + connect \$55 $xor$libresoc.v:136441$6987_Y + connect \$59 $xor$libresoc.v:136442$6988_Y + connect \$58 $reduce_or$libresoc.v:136443$6989_Y + connect \$57 $not$libresoc.v:136444$6990_Y + connect \$65 $xor$libresoc.v:136445$6991_Y + connect \$64 $reduce_or$libresoc.v:136446$6992_Y + connect \$63 $not$libresoc.v:136447$6993_Y + connect \$69 $or$libresoc.v:136448$6994_Y + connect \$71 $and$libresoc.v:136449$6995_Y + connect \$73 $ne$libresoc.v:136450$6996_Y + connect \$75 $not$libresoc.v:136451$6997_Y + connect \$77 $not$libresoc.v:136452$6998_Y + connect \$79 $or$libresoc.v:136453$6999_Y + connect \$81 $and$libresoc.v:136454$7000_Y + connect \$83 $ternary$libresoc.v:136455$7001_Y + connect \$85 $or$libresoc.v:136456$7002_Y + connect \$87 $and$libresoc.v:136457$7003_Y + connect \$89 $ternary$libresoc.v:136458$7004_Y + connect \$91 $or$libresoc.v:136459$7005_Y + connect \$93 $and$libresoc.v:136460$7006_Y + connect \$95 $ne$libresoc.v:136461$7007_Y + connect \$97 $ternary$libresoc.v:136462$7008_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:134502.1-134906.10" +attribute \src "libresoc.v:136905.1-137313.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" -module \main$111 - attribute \src "libresoc.v:134503.7-134503.20" +module \main$114 + attribute \src "libresoc.v:136906.7-136906.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134858.3-134888.6" + attribute \src "libresoc.v:137265.3-137295.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:134823.3-134857.6" + attribute \src "libresoc.v:137230.3-137264.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:134858.3-134888.6" + attribute \src "libresoc.v:137265.3-137295.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:134823.3-134857.6" + attribute \src "libresoc.v:137230.3-137264.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:134503.7-134503.15" + attribute \src "libresoc.v:136906.7-136906.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -281325,19 +287420,19 @@ module \main$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" wire width 4 \mode attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 42 \muxid + wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 38 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 39 \o_ok + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 40 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra + wire width 64 input 18 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb + wire width 64 input 19 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rc + wire width 64 input 20 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" wire \rotator_arith attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" @@ -281395,35 +287490,35 @@ module \main$111 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 23 \sr_op__fn_unit$3 + wire width 12 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \sr_op__imm_data__data$4 + wire width 64 output 25 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \sr_op__imm_data__ok$5 + wire output 26 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry + wire width 2 input 11 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$11 + wire width 2 output 33 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__input_cr + wire input 13 \sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__input_cr$13 + wire output 35 \sr_op__input_cr$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn + wire width 32 input 17 \sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$17 + wire width 32 output 39 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -281575,51 +287670,55 @@ module \main$111 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \sr_op__insn_type$2 + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__is_32bit + wire output 32 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__is_32bit$15 + wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_signed + wire output 37 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__is_signed$16 + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__oe__oe$8 + wire output 29 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__oe__ok$9 + wire output 30 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__output_carry + wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \sr_op__output_carry$12 + wire output 34 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__output_cr + wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \sr_op__output_cr$14 + wire output 36 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__rc__ok$7 + wire output 28 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \sr_op__rc__rc$6 + wire output 27 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 41 \xer_ca + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 43 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 20 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 40 \xer_so$18 + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:134807.11-134822.4" + attribute \src "libresoc.v:137214.11-137229.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -281636,22 +287735,22 @@ module \main$111 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:134503.7-134503.20" - process $proc$libresoc.v:134503$6771 + attribute \src "libresoc.v:136906.7-136906.20" + process $proc$libresoc.v:136906$7041 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134823.3-134857.6" - process $proc$libresoc.v:134823$6769 + attribute \src "libresoc.v:137230.3-137264.6" + process $proc$libresoc.v:137230$7039 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:134824.5-134824.29" + attribute \src "libresoc.v:137231.5-137231.29" switch \initial - attribute \src "libresoc.v:134824.9-134824.17" + attribute \src "libresoc.v:137231.9-137231.17" case 1'1 case end @@ -281683,14 +287782,14 @@ module \main$111 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:134858.3-134888.6" - process $proc$libresoc.v:134858$6770 + attribute \src "libresoc.v:137265.3-137295.6" + process $proc$libresoc.v:137265$7040 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:134859.5-134859.29" + attribute \src "libresoc.v:137266.5-137266.29" switch \initial - attribute \src "libresoc.v:134859.9-134859.17" + attribute \src "libresoc.v:137266.9-137266.17" case 1'1 case end @@ -281726,9 +287825,9 @@ module \main$111 sync always update \mode $0\mode[3:0] end - connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid - connect \xer_so$18 \xer_so + connect \xer_so$19 \xer_so connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } connect \o \rotator_result_o connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode @@ -281744,109 +287843,109 @@ module \main$111 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:134910.1-135440.10" +attribute \src "libresoc.v:137317.1-137847.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:135347.3-135370.6" + attribute \src "libresoc.v:137754.3-137777.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:135226.3-135237.6" + attribute \src "libresoc.v:137633.3-137644.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:135238.3-135264.6" + attribute \src "libresoc.v:137645.3-137671.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:135265.3-135283.6" + attribute \src "libresoc.v:137672.3-137690.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:135319.3-135333.6" + attribute \src "libresoc.v:137726.3-137740.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:135397.3-135417.6" + attribute \src "libresoc.v:137804.3-137824.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:135371.3-135383.6" + attribute \src "libresoc.v:137778.3-137790.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:135334.3-135346.6" + attribute \src "libresoc.v:137741.3-137753.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:135418.3-135430.6" + attribute \src "libresoc.v:137825.3-137837.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:135384.3-135396.6" - wire width 64 $0\fast1$10[63:0]$6804 - attribute \src "libresoc.v:135284.3-135298.6" + attribute \src "libresoc.v:137791.3-137803.6" + wire width 64 $0\fast1$10[63:0]$7074 + attribute \src "libresoc.v:137691.3-137705.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:135299.3-135308.6" - wire width 64 $0\fast2$11[63:0]$6796 - attribute \src "libresoc.v:135309.3-135318.6" + attribute \src "libresoc.v:137706.3-137715.6" + wire width 64 $0\fast2$11[63:0]$7066 + attribute \src "libresoc.v:137716.3-137725.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:134911.7-134911.20" + attribute \src "libresoc.v:137318.7-137318.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135347.3-135370.6" + attribute \src "libresoc.v:137754.3-137777.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:135226.3-135237.6" + attribute \src "libresoc.v:137633.3-137644.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:135238.3-135264.6" + attribute \src "libresoc.v:137645.3-137671.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:135265.3-135283.6" + attribute \src "libresoc.v:137672.3-137690.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:135319.3-135333.6" + attribute \src "libresoc.v:137726.3-137740.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:135397.3-135417.6" + attribute \src "libresoc.v:137804.3-137824.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:135371.3-135383.6" + attribute \src "libresoc.v:137778.3-137790.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:135334.3-135346.6" + attribute \src "libresoc.v:137741.3-137753.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:135418.3-135430.6" + attribute \src "libresoc.v:137825.3-137837.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:135384.3-135396.6" - wire width 64 $1\fast1$10[63:0]$6805 - attribute \src "libresoc.v:135284.3-135298.6" + attribute \src "libresoc.v:137791.3-137803.6" + wire width 64 $1\fast1$10[63:0]$7075 + attribute \src "libresoc.v:137691.3-137705.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:135299.3-135308.6" - wire width 64 $1\fast2$11[63:0]$6797 - attribute \src "libresoc.v:135309.3-135318.6" + attribute \src "libresoc.v:137706.3-137715.6" + wire width 64 $1\fast2$11[63:0]$7067 + attribute \src "libresoc.v:137716.3-137725.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:135347.3-135370.6" + attribute \src "libresoc.v:137754.3-137777.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:135238.3-135264.6" + attribute \src "libresoc.v:137645.3-137671.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:135397.3-135417.6" + attribute \src "libresoc.v:137804.3-137824.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:135210.18-135210.119" - wire width 65 $add$libresoc.v:135210$6774_Y - attribute \src "libresoc.v:135225.18-135225.113" - wire width 65 $add$libresoc.v:135225$6790_Y - attribute \src "libresoc.v:135217.18-135217.115" - wire $and$libresoc.v:135217$6781_Y - attribute \src "libresoc.v:135218.18-135218.117" - wire $and$libresoc.v:135218$6782_Y - attribute \src "libresoc.v:135224.18-135224.118" - wire $and$libresoc.v:135224$6789_Y - attribute \src "libresoc.v:135208.18-135208.120" - wire $eq$libresoc.v:135208$6772_Y - attribute \src "libresoc.v:135211.18-135211.111" - wire $eq$libresoc.v:135211$6775_Y - attribute \src "libresoc.v:135213.18-135213.111" - wire $eq$libresoc.v:135213$6777_Y - attribute \src "libresoc.v:135214.18-135214.111" - wire $eq$libresoc.v:135214$6778_Y - attribute \src "libresoc.v:135215.18-135215.109" - wire $eq$libresoc.v:135215$6779_Y - attribute \src "libresoc.v:135220.18-135220.98" - wire width 64 $extend$libresoc.v:135220$6784_Y - attribute \src "libresoc.v:135216.18-135216.104" - wire $not$libresoc.v:135216$6780_Y - attribute \src "libresoc.v:135223.18-135223.112" - wire $not$libresoc.v:135223$6788_Y - attribute \src "libresoc.v:135209.18-135209.116" - wire $or$libresoc.v:135209$6773_Y - attribute \src "libresoc.v:135212.18-135212.109" - wire $or$libresoc.v:135212$6776_Y - attribute \src "libresoc.v:135220.18-135220.98" - wire width 64 $pos$libresoc.v:135220$6785_Y - attribute \src "libresoc.v:135221.18-135221.103" - wire $reduce_or$libresoc.v:135221$6786_Y - attribute \src "libresoc.v:135219.18-135219.108" - wire width 65 $sub$libresoc.v:135219$6783_Y - attribute \src "libresoc.v:135222.18-135222.108" - wire $xor$libresoc.v:135222$6787_Y + attribute \src "libresoc.v:137617.18-137617.119" + wire width 65 $add$libresoc.v:137617$7044_Y + attribute \src "libresoc.v:137632.18-137632.113" + wire width 65 $add$libresoc.v:137632$7060_Y + attribute \src "libresoc.v:137624.18-137624.115" + wire $and$libresoc.v:137624$7051_Y + attribute \src "libresoc.v:137625.18-137625.117" + wire $and$libresoc.v:137625$7052_Y + attribute \src "libresoc.v:137631.18-137631.118" + wire $and$libresoc.v:137631$7059_Y + attribute \src "libresoc.v:137615.18-137615.120" + wire $eq$libresoc.v:137615$7042_Y + attribute \src "libresoc.v:137618.18-137618.111" + wire $eq$libresoc.v:137618$7045_Y + attribute \src "libresoc.v:137620.18-137620.111" + wire $eq$libresoc.v:137620$7047_Y + attribute \src "libresoc.v:137621.18-137621.111" + wire $eq$libresoc.v:137621$7048_Y + attribute \src "libresoc.v:137622.18-137622.109" + wire $eq$libresoc.v:137622$7049_Y + attribute \src "libresoc.v:137627.18-137627.98" + wire width 64 $extend$libresoc.v:137627$7054_Y + attribute \src "libresoc.v:137623.18-137623.104" + wire $not$libresoc.v:137623$7050_Y + attribute \src "libresoc.v:137630.18-137630.112" + wire $not$libresoc.v:137630$7058_Y + attribute \src "libresoc.v:137616.18-137616.116" + wire $or$libresoc.v:137616$7043_Y + attribute \src "libresoc.v:137619.18-137619.109" + wire $or$libresoc.v:137619$7046_Y + attribute \src "libresoc.v:137627.18-137627.98" + wire width 64 $pos$libresoc.v:137627$7055_Y + attribute \src "libresoc.v:137628.18-137628.103" + wire $reduce_or$libresoc.v:137628$7056_Y + attribute \src "libresoc.v:137626.18-137626.108" + wire width 65 $sub$libresoc.v:137626$7053_Y + attribute \src "libresoc.v:137629.18-137629.108" + wire $xor$libresoc.v:137629$7057_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -282121,28 +288220,28 @@ module \main$22 wire \ctr_zero_bo1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 21 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 10 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 23 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:134911.7-134911.15" + attribute \src "libresoc.v:137318.7-137318.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 27 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:135210$6774 + cell $add $add$libresoc.v:137617$7044 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -282150,10 +288249,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:135210$6774_Y + connect \Y $add$libresoc.v:137617$7044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:135225$6790 + cell $add $add$libresoc.v:137632$7060 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -282161,10 +288260,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:135225$6790_Y + connect \Y $add$libresoc.v:137632$7060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:135217$6781 + cell $and $and$libresoc.v:137624$7051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282172,10 +288271,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:135217$6781_Y + connect \Y $and$libresoc.v:137624$7051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:135218$6782 + cell $and $and$libresoc.v:137625$7052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282183,10 +288282,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:135218$6782_Y + connect \Y $and$libresoc.v:137625$7052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:135224$6789 + cell $and $and$libresoc.v:137631$7059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282194,10 +288293,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:135224$6789_Y + connect \Y $and$libresoc.v:137631$7059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:135208$6772 + cell $eq $eq$libresoc.v:137615$7042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -282205,10 +288304,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:135208$6772_Y + connect \Y $eq$libresoc.v:137615$7042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:135211$6775 + cell $eq $eq$libresoc.v:137618$7045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282216,10 +288315,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:135211$6775_Y + connect \Y $eq$libresoc.v:137618$7045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:135213$6777 + cell $eq $eq$libresoc.v:137620$7047 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -282227,10 +288326,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:135213$6777_Y + connect \Y $eq$libresoc.v:137620$7047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:135214$6778 + cell $eq $eq$libresoc.v:137621$7048 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -282238,10 +288337,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:135214$6778_Y + connect \Y $eq$libresoc.v:137621$7048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:135215$6779 + cell $eq $eq$libresoc.v:137622$7049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282249,34 +288348,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:135215$6779_Y + connect \Y $eq$libresoc.v:137622$7049_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:135220$6784 + cell $pos $extend$libresoc.v:137627$7054 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:135220$6784_Y + connect \Y $extend$libresoc.v:137627$7054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:135216$6780 + cell $not $not$libresoc.v:137623$7050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:135216$6780_Y + connect \Y $not$libresoc.v:137623$7050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:135223$6788 + cell $not $not$libresoc.v:137630$7058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:135223$6788_Y + connect \Y $not$libresoc.v:137630$7058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:135209$6773 + cell $or $or$libresoc.v:137616$7043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282284,10 +288383,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:135209$6773_Y + connect \Y $or$libresoc.v:137616$7043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:135212$6776 + cell $or $or$libresoc.v:137619$7046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282295,26 +288394,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:135212$6776_Y + connect \Y $or$libresoc.v:137619$7046_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:135220$6785 + cell $pos $pos$libresoc.v:137627$7055 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:135220$6784_Y - connect \Y $pos$libresoc.v:135220$6785_Y + connect \A $extend$libresoc.v:137627$7054_Y + connect \Y $pos$libresoc.v:137627$7055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:135221$6786 + cell $reduce_or $reduce_or$libresoc.v:137628$7056 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:135221$6786_Y + connect \Y $reduce_or$libresoc.v:137628$7056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:135219$6783 + cell $sub $sub$libresoc.v:137626$7053 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -282322,10 +288421,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:135219$6783_Y + connect \Y $sub$libresoc.v:137626$7053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:135222$6787 + cell $xor $xor$libresoc.v:137629$7057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282333,23 +288432,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:135222$6787_Y + connect \Y $xor$libresoc.v:137629$7057_Y end - attribute \src "libresoc.v:134911.7-134911.20" - process $proc$libresoc.v:134911$6808 + attribute \src "libresoc.v:137318.7-137318.20" + process $proc$libresoc.v:137318$7078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135226.3-135237.6" - process $proc$libresoc.v:135226$6791 + attribute \src "libresoc.v:137633.3-137644.6" + process $proc$libresoc.v:137633$7061 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:135227.5-135227.29" + attribute \src "libresoc.v:137634.5-137634.29" switch \initial - attribute \src "libresoc.v:135227.9-135227.17" + attribute \src "libresoc.v:137634.9-137634.17" case 1'1 case end @@ -282367,14 +288466,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:135238.3-135264.6" - process $proc$libresoc.v:135238$6792 + attribute \src "libresoc.v:137645.3-137671.6" + process $proc$libresoc.v:137645$7062 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:135239.5-135239.29" + attribute \src "libresoc.v:137646.5-137646.29" switch \initial - attribute \src "libresoc.v:135239.9-135239.17" + attribute \src "libresoc.v:137646.9-137646.17" case 1'1 case end @@ -282409,14 +288508,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:135265.3-135283.6" - process $proc$libresoc.v:135265$6793 + attribute \src "libresoc.v:137672.3-137690.6" + process $proc$libresoc.v:137672$7063 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:135266.5-135266.29" + attribute \src "libresoc.v:137673.5-137673.29" switch \initial - attribute \src "libresoc.v:135266.9-135266.17" + attribute \src "libresoc.v:137673.9-137673.17" case 1'1 case end @@ -282440,14 +288539,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:135284.3-135298.6" - process $proc$libresoc.v:135284$6794 + attribute \src "libresoc.v:137691.3-137705.6" + process $proc$libresoc.v:137691$7064 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:135285.5-135285.29" + attribute \src "libresoc.v:137692.5-137692.29" switch \initial - attribute \src "libresoc.v:135285.9-135285.17" + attribute \src "libresoc.v:137692.9-137692.17" case 1'1 case end @@ -282467,14 +288566,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:135299.3-135308.6" - process $proc$libresoc.v:135299$6795 + attribute \src "libresoc.v:137706.3-137715.6" + process $proc$libresoc.v:137706$7065 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$6796 $1\fast2$11[63:0]$6797 - attribute \src "libresoc.v:135300.5-135300.29" + assign $0\fast2$11[63:0]$7066 $1\fast2$11[63:0]$7067 + attribute \src "libresoc.v:137707.5-137707.29" switch \initial - attribute \src "libresoc.v:135300.9-135300.17" + attribute \src "libresoc.v:137707.9-137707.17" case 1'1 case end @@ -282483,21 +288582,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$6797 \$48 [63:0] + assign $1\fast2$11[63:0]$7067 \$48 [63:0] case - assign $1\fast2$11[63:0]$6797 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$6796 + update \fast2$11 $0\fast2$11[63:0]$7066 end - attribute \src "libresoc.v:135309.3-135318.6" - process $proc$libresoc.v:135309$6798 + attribute \src "libresoc.v:137716.3-137725.6" + process $proc$libresoc.v:137716$7068 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:135310.5-135310.29" + attribute \src "libresoc.v:137717.5-137717.29" switch \initial - attribute \src "libresoc.v:135310.9-135310.17" + attribute \src "libresoc.v:137717.9-137717.17" case 1'1 case end @@ -282513,14 +288612,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:135319.3-135333.6" - process $proc$libresoc.v:135319$6799 + attribute \src "libresoc.v:137726.3-137740.6" + process $proc$libresoc.v:137726$7069 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:135320.5-135320.29" + attribute \src "libresoc.v:137727.5-137727.29" switch \initial - attribute \src "libresoc.v:135320.9-135320.17" + attribute \src "libresoc.v:137727.9-137727.17" case 1'1 case end @@ -282548,14 +288647,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:135334.3-135346.6" - process $proc$libresoc.v:135334$6800 + attribute \src "libresoc.v:137741.3-137753.6" + process $proc$libresoc.v:137741$7070 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:135335.5-135335.29" + attribute \src "libresoc.v:137742.5-137742.29" switch \initial - attribute \src "libresoc.v:135335.9-135335.17" + attribute \src "libresoc.v:137742.9-137742.17" case 1'1 case end @@ -282572,14 +288671,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:135347.3-135370.6" - process $proc$libresoc.v:135347$6801 + attribute \src "libresoc.v:137754.3-137777.6" + process $proc$libresoc.v:137754$7071 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:135348.5-135348.29" + attribute \src "libresoc.v:137755.5-137755.29" switch \initial - attribute \src "libresoc.v:135348.9-135348.17" + attribute \src "libresoc.v:137755.9-137755.17" case 1'1 case end @@ -282614,14 +288713,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:135371.3-135383.6" - process $proc$libresoc.v:135371$6802 + attribute \src "libresoc.v:137778.3-137790.6" + process $proc$libresoc.v:137778$7072 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:135372.5-135372.29" + attribute \src "libresoc.v:137779.5-137779.29" switch \initial - attribute \src "libresoc.v:135372.9-135372.17" + attribute \src "libresoc.v:137779.9-137779.17" case 1'1 case end @@ -282638,14 +288737,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:135384.3-135396.6" - process $proc$libresoc.v:135384$6803 + attribute \src "libresoc.v:137791.3-137803.6" + process $proc$libresoc.v:137791$7073 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$6804 $1\fast1$10[63:0]$6805 - attribute \src "libresoc.v:135385.5-135385.29" + assign $0\fast1$10[63:0]$7074 $1\fast1$10[63:0]$7075 + attribute \src "libresoc.v:137792.5-137792.29" switch \initial - attribute \src "libresoc.v:135385.9-135385.17" + attribute \src "libresoc.v:137792.9-137792.17" case 1'1 case end @@ -282653,23 +288752,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$6805 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7075 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$6805 \ctr_n + assign $1\fast1$10[63:0]$7075 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$6804 + update \fast1$10 $0\fast1$10[63:0]$7074 end - attribute \src "libresoc.v:135397.3-135417.6" - process $proc$libresoc.v:135397$6806 + attribute \src "libresoc.v:137804.3-137824.6" + process $proc$libresoc.v:137804$7076 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:135398.5-135398.29" + attribute \src "libresoc.v:137805.5-137805.29" switch \initial - attribute \src "libresoc.v:135398.9-135398.17" + attribute \src "libresoc.v:137805.9-137805.17" case 1'1 case end @@ -282697,14 +288796,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:135418.3-135430.6" - process $proc$libresoc.v:135418$6807 + attribute \src "libresoc.v:137825.3-137837.6" + process $proc$libresoc.v:137825$7077 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:135419.5-135419.29" + attribute \src "libresoc.v:137826.5-137826.29" switch \initial - attribute \src "libresoc.v:135419.9-135419.17" + attribute \src "libresoc.v:137826.9-137826.17" case 1'1 case end @@ -282721,24 +288820,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:135208$6772_Y - connect \$14 $or$libresoc.v:135209$6773_Y - connect \$17 $add$libresoc.v:135210$6774_Y - connect \$19 $eq$libresoc.v:135211$6775_Y - connect \$21 $or$libresoc.v:135212$6776_Y - connect \$23 $eq$libresoc.v:135213$6777_Y - connect \$25 $eq$libresoc.v:135214$6778_Y - connect \$27 $eq$libresoc.v:135215$6779_Y - connect \$29 $not$libresoc.v:135216$6780_Y - connect \$31 $and$libresoc.v:135217$6781_Y - connect \$33 $and$libresoc.v:135218$6782_Y - connect \$36 $sub$libresoc.v:135219$6783_Y - connect \$38 $pos$libresoc.v:135220$6785_Y - connect \$40 $reduce_or$libresoc.v:135221$6786_Y - connect \$42 $xor$libresoc.v:135222$6787_Y - connect \$44 $not$libresoc.v:135223$6788_Y - connect \$46 $and$libresoc.v:135224$6789_Y - connect \$49 $add$libresoc.v:135225$6790_Y + connect \$12 $eq$libresoc.v:137615$7042_Y + connect \$14 $or$libresoc.v:137616$7043_Y + connect \$17 $add$libresoc.v:137617$7044_Y + connect \$19 $eq$libresoc.v:137618$7045_Y + connect \$21 $or$libresoc.v:137619$7046_Y + connect \$23 $eq$libresoc.v:137620$7047_Y + connect \$25 $eq$libresoc.v:137621$7048_Y + connect \$27 $eq$libresoc.v:137622$7049_Y + connect \$29 $not$libresoc.v:137623$7050_Y + connect \$31 $and$libresoc.v:137624$7051_Y + connect \$33 $and$libresoc.v:137625$7052_Y + connect \$36 $sub$libresoc.v:137626$7053_Y + connect \$38 $pos$libresoc.v:137627$7055_Y + connect \$40 $reduce_or$libresoc.v:137628$7056_Y + connect \$42 $xor$libresoc.v:137629$7057_Y + connect \$44 $not$libresoc.v:137630$7058_Y + connect \$46 $and$libresoc.v:137631$7059_Y + connect \$49 $add$libresoc.v:137632$7060_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -282749,331 +288848,417 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:135444.1-136317.10" +attribute \src "libresoc.v:137851.1-138795.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" -module \main$35 - attribute \src "libresoc.v:136282.3-136293.6" +module \main$38 + attribute \src "libresoc.v:138760.3-138771.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:135819.3-135830.6" + attribute \src "libresoc.v:138258.3-138269.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:136294.3-136305.6" + attribute \src "libresoc.v:138772.3-138783.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:136232.3-136243.6" + attribute \src "libresoc.v:138541.3-138552.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:135895.3-135926.6" - wire width 64 $0\fast1$10[63:0]$6850 - attribute \src "libresoc.v:135927.3-135958.6" + attribute \src "libresoc.v:138334.3-138365.6" + wire width 64 $0\fast1$11[63:0]$7124 + attribute \src "libresoc.v:138366.3-138397.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:135959.3-136030.6" - wire width 64 $0\fast2$11[63:0]$6855 - attribute \src "libresoc.v:136031.3-136062.6" + attribute \src "libresoc.v:138398.3-138480.6" + wire width 64 $0\fast2$12[63:0]$7129 + attribute \src "libresoc.v:138481.3-138512.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:135445.7-135445.20" + attribute \src "libresoc.v:137852.7-137852.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:135831.3-135862.6" + attribute \src "libresoc.v:138270.3-138301.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:135863.3-135894.6" + attribute \src "libresoc.v:138302.3-138333.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:136244.3-136262.6" + attribute \src "libresoc.v:138722.3-138740.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:136263.3-136281.6" + attribute \src "libresoc.v:138741.3-138759.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$60[0:0]$7143 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$61[0:0]$7144 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$62[0:0]$7145 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$67[0:0]$7146 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$68[0:0]$7147 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$69[0:0]$7148 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal$70[0:0]$7149 + attribute \src "libresoc.v:138513.3-138540.6" + wire $0\trapexc_$signal[0:0]$7142 + attribute \src "libresoc.v:138398.3-138480.6" + wire $10\fast2$12[19:19]$7139 + attribute \src "libresoc.v:138553.3-138721.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $11\msr[15:15] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $12\msr[12:12] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $13\msr[60:60] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $14\msr[12:12] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $15\msr[12:12] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $17\msr[15:15] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:136282.3-136293.6" + attribute \src "libresoc.v:138760.3-138771.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:135819.3-135830.6" + attribute \src "libresoc.v:138258.3-138269.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:136294.3-136305.6" + attribute \src "libresoc.v:138772.3-138783.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:136232.3-136243.6" + attribute \src "libresoc.v:138541.3-138552.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:135895.3-135926.6" - wire width 64 $1\fast1$10[63:0]$6851 - attribute \src "libresoc.v:135927.3-135958.6" + attribute \src "libresoc.v:138334.3-138365.6" + wire width 64 $1\fast1$11[63:0]$7125 + attribute \src "libresoc.v:138366.3-138397.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:135959.3-136030.6" - wire width 64 $1\fast2$11[63:0]$6856 - attribute \src "libresoc.v:136031.3-136062.6" + attribute \src "libresoc.v:138398.3-138480.6" + wire width 64 $1\fast2$12[63:0]$7130 + attribute \src "libresoc.v:138481.3-138512.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:135831.3-135862.6" + attribute \src "libresoc.v:138270.3-138301.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:135863.3-135894.6" + attribute \src "libresoc.v:138302.3-138333.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:136244.3-136262.6" + attribute \src "libresoc.v:138722.3-138740.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:136263.3-136281.6" + attribute \src "libresoc.v:138741.3-138759.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:135895.3-135926.6" - wire width 64 $2\fast1$10[63:0]$6852 - attribute \src "libresoc.v:135927.3-135958.6" + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$60[0:0]$7151 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$61[0:0]$7152 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$62[0:0]$7153 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$67[0:0]$7154 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$68[0:0]$7155 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$69[0:0]$7156 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal$70[0:0]$7157 + attribute \src "libresoc.v:138513.3-138540.6" + wire $1\trapexc_$signal[0:0]$7150 + attribute \src "libresoc.v:138334.3-138365.6" + wire width 64 $2\fast1$11[63:0]$7126 + attribute \src "libresoc.v:138366.3-138397.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:135959.3-136030.6" - wire width 64 $2\fast2$11[63:0]$6857 - attribute \src "libresoc.v:136031.3-136062.6" + attribute \src "libresoc.v:138398.3-138480.6" + wire width 64 $2\fast2$12[63:0]$7131 + attribute \src "libresoc.v:138481.3-138512.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138553.3-138721.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:135831.3-135862.6" + attribute \src "libresoc.v:138270.3-138301.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:135863.3-135894.6" + attribute \src "libresoc.v:138302.3-138333.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:135959.3-136030.6" - wire $3\fast2$11[17:17]$6858 - attribute \src "libresoc.v:136063.3-136231.6" + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$60[0:0]$7159 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$61[0:0]$7160 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$62[0:0]$7161 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$67[0:0]$7162 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$68[0:0]$7163 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$69[0:0]$7164 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal$70[0:0]$7165 + attribute \src "libresoc.v:138513.3-138540.6" + wire $2\trapexc_$signal[0:0]$7158 + attribute \src "libresoc.v:138398.3-138480.6" + wire $3\fast2$12[17:17]$7132 + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + wire width 8 \$64 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + wire width 8 \$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 65 \$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" wire width 64 \a_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" wire width 64 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" wire width 64 \b_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" wire \equal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \fast1_ok + wire width 64 input 12 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \fast1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 12 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire width 64 input 13 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 28 \fast2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" wire \gt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:135445.7-135445.15" + attribute \src "libresoc.v:137852.7-137852.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" wire \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 32 \muxid + wire width 2 input 34 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 13 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 28 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \o_ok + wire width 2 output 14 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra + wire width 64 input 10 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" wire \should_trap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" wire width 5 \to - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" wire width 5 \trap_bits attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 input 5 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 18 \trap_op__cia$6 + wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -283103,11 +289288,11 @@ module \main$35 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 15 \trap_op__fn_unit$3 + wire width 12 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \trap_op__insn$4 + wire width 32 output 17 \trap_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -283259,25 +289444,45 @@ module \main$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \trap_op__insn_type$2 + wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \trap_op__is_32bit$7 + wire output 20 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \trap_op__msr + wire width 8 input 9 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \trap_op__msr$5 + wire width 8 output 23 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \trap_op__trapaddr + wire width 64 input 4 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 21 \trap_op__trapaddr$9 + wire width 64 output 18 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \trap_op__traptype + wire width 13 input 8 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \trap_op__traptype$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" - cell $add $add$libresoc.v:135799$6825 + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" + cell $add $add$libresoc.v:138234$7095 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -283285,10 +289490,10 @@ module \main$35 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:135799$6825_Y + connect \Y $add$libresoc.v:138234$7095_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $and $and$libresoc.v:135793$6818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $and $and$libresoc.v:138228$7088 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -283296,76 +289501,98 @@ module \main$35 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:135793$6818_Y + connect \Y $and$libresoc.v:138228$7088_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - cell $and $and$libresoc.v:135801$6827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + cell $and $and$libresoc.v:138236$7097 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 7 + parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:135801$6827_Y + connect \Y $and$libresoc.v:138236$7097_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - cell $and $and$libresoc.v:135803$6829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + cell $and $and$libresoc.v:138238$7099 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 7 + parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:135803$6829_Y + connect \Y $and$libresoc.v:138238$7099_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - cell $and $and$libresoc.v:135805$6831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + cell $and $and$libresoc.v:138240$7101 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 7 + parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:135805$6831_Y + connect \Y $and$libresoc.v:138240$7101_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - cell $and $and$libresoc.v:135807$6833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:138242$7103 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:138242$7103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + cell $and $and$libresoc.v:138244$7105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 8'10000000 + connect \Y $and$libresoc.v:138244$7105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:138246$7107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:135807$6833_Y + connect \Y $and$libresoc.v:138246$7107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $and $and$libresoc.v:135813$6840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $and $and$libresoc.v:138252$7114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \$65 - connect \Y $and$libresoc.v:135813$6840_Y + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:138252$7114_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $and $and$libresoc.v:135818$6845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $and $and$libresoc.v:138257$7119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$libresoc.v:135818$6845_Y + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:138257$7119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $eq $eq$libresoc.v:135792$6817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + cell $eq $eq$libresoc.v:138227$7087 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -283373,21 +289600,21 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:135792$6817_Y + connect \Y $eq$libresoc.v:138227$7087_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $eq $eq$libresoc.v:135800$6826 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + cell $eq $eq$libresoc.v:138235$7096 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:135800$6826_Y + connect \Y $eq$libresoc.v:138235$7096_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - cell $eq $eq$libresoc.v:135810$6837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + cell $eq $eq$libresoc.v:138249$7111 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -283395,10 +289622,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:135810$6837_Y + connect \Y $eq$libresoc.v:138249$7111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" - cell $eq $eq$libresoc.v:135811$6838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + cell $eq $eq$libresoc.v:138250$7112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -283406,10 +289633,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:135811$6838_Y + connect \Y $eq$libresoc.v:138250$7112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $eq $eq$libresoc.v:135812$6839 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $eq $eq$libresoc.v:138251$7113 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -283417,10 +289644,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:135812$6839_Y + connect \Y $eq$libresoc.v:138251$7113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" - cell $eq $eq$libresoc.v:135816$6843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + cell $eq $eq$libresoc.v:138255$7117 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -283428,10 +289655,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:135816$6843_Y + connect \Y $eq$libresoc.v:138255$7117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $eq $eq$libresoc.v:135817$6844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $eq $eq$libresoc.v:138256$7118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -283439,42 +289666,42 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:135817$6844_Y + connect \Y $eq$libresoc.v:138256$7118_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:135786$6809 + cell $pos $extend$libresoc.v:138221$7079 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:135786$6809_Y + connect \Y $extend$libresoc.v:138221$7079_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:135787$6811 + cell $pos $extend$libresoc.v:138222$7081 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:135787$6811_Y + connect \Y $extend$libresoc.v:138222$7081_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $extend$libresoc.v:135798$6823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $extend$libresoc.v:138233$7093 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 - connect \A \$35 - connect \Y $extend$libresoc.v:135798$6823_Y + connect \A \$36 + connect \Y $extend$libresoc.v:138233$7093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:135809$6835 + cell $pos $extend$libresoc.v:138248$7109 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:135809$6835_Y + connect \Y $extend$libresoc.v:138248$7109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $gt $gt$libresoc.v:135789$6814 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $gt $gt$libresoc.v:138224$7084 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -283482,10 +289709,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:135789$6814_Y + connect \Y $gt$libresoc.v:138224$7084_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $gt $gt$libresoc.v:135791$6816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $gt $gt$libresoc.v:138226$7086 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -283493,10 +289720,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:135791$6816_Y + connect \Y $gt$libresoc.v:138226$7086_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - cell $lt $lt$libresoc.v:135788$6813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $lt $lt$libresoc.v:138223$7083 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -283504,10 +289731,10 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:135788$6813_Y + connect \Y $lt$libresoc.v:138223$7083_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $lt $lt$libresoc.v:135790$6815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $lt $lt$libresoc.v:138225$7085 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -283515,117 +289742,133 @@ module \main$35 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:135790$6815_Y + connect \Y $lt$libresoc.v:138225$7085_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - cell $not $not$libresoc.v:135814$6841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + cell $not $not$libresoc.v:138253$7115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:135814$6841_Y + connect \Y $not$libresoc.v:138253$7115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - cell $not $not$libresoc.v:135815$6842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + cell $not $not$libresoc.v:138254$7116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:135815$6842_Y + connect \Y $not$libresoc.v:138254$7116_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $or $or$libresoc.v:135796$6821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $or $or$libresoc.v:138231$7091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$26 - connect \B \$30 - connect \Y $or$libresoc.v:135796$6821_Y + connect \A \$27 + connect \B \$31 + connect \Y $or$libresoc.v:138231$7091_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:135786$6810 + cell $pos $pos$libresoc.v:138221$7080 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:135786$6809_Y - connect \Y $pos$libresoc.v:135786$6810_Y + connect \A $extend$libresoc.v:138221$7079_Y + connect \Y $pos$libresoc.v:138221$7080_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:135787$6812 + cell $pos $pos$libresoc.v:138222$7082 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:135787$6811_Y - connect \Y $pos$libresoc.v:135787$6812_Y + connect \A $extend$libresoc.v:138222$7081_Y + connect \Y $pos$libresoc.v:138222$7082_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $pos$libresoc.v:135798$6824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $pos$libresoc.v:138233$7094 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:135798$6823_Y - connect \Y $pos$libresoc.v:135798$6824_Y + connect \A $extend$libresoc.v:138233$7093_Y + connect \Y $pos$libresoc.v:138233$7094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:135809$6836 + cell $pos $pos$libresoc.v:138248$7110 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:135809$6835_Y - connect \Y $pos$libresoc.v:135809$6836_Y + connect \A $extend$libresoc.v:138248$7109_Y + connect \Y $pos$libresoc.v:138248$7110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $reduce_or$libresoc.v:135794$6819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:138229$7089 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$libresoc.v:135794$6819_Y + connect \A \$28 + connect \Y $reduce_or$libresoc.v:138229$7089_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $reduce_or$libresoc.v:135795$6820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:138230$7090 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:135795$6820_Y + connect \Y $reduce_or$libresoc.v:138230$7090_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:135802$6828 + cell $reduce_or $reduce_or$libresoc.v:138237$7098 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \$44 - connect \Y $reduce_or$libresoc.v:135802$6828_Y + connect \A \$45 + connect \Y $reduce_or$libresoc.v:138237$7098_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:135804$6830 + cell $reduce_or $reduce_or$libresoc.v:138239$7100 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \$48 - connect \Y $reduce_or$libresoc.v:135804$6830_Y + connect \A \$49 + connect \Y $reduce_or$libresoc.v:138239$7100_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:135806$6832 + cell $reduce_or $reduce_or$libresoc.v:138241$7102 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \$52 - connect \Y $reduce_or$libresoc.v:135806$6832_Y + connect \A \$53 + connect \Y $reduce_or$libresoc.v:138241$7102_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:135808$6834 + cell $reduce_or $reduce_or$libresoc.v:138243$7104 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \$56 - connect \Y $reduce_or$libresoc.v:135808$6834_Y + connect \A \$57 + connect \Y $reduce_or$libresoc.v:138243$7104_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138245$7106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $reduce_or$libresoc.v:138245$7106_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $sshl $sshl$libresoc.v:135797$6822 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:138247$7108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$72 + connect \Y $reduce_or$libresoc.v:138247$7108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $sshl $sshl$libresoc.v:138232$7092 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -283633,27 +289876,27 @@ module \main$35 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:135797$6822_Y + connect \Y $sshl$libresoc.v:138232$7092_Y end - attribute \src "libresoc.v:135445.7-135445.20" - process $proc$libresoc.v:135445$6870 + attribute \src "libresoc.v:137852.7-137852.20" + process $proc$libresoc.v:137852$7180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135819.3-135830.6" - process $proc$libresoc.v:135819$6846 + attribute \src "libresoc.v:138258.3-138269.6" + process $proc$libresoc.v:138258$7120 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:135820.5-135820.29" + attribute \src "libresoc.v:138259.5-138259.29" switch \initial - attribute \src "libresoc.v:135820.9-135820.17" + attribute \src "libresoc.v:138259.9-138259.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -283667,29 +289910,29 @@ module \main$35 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:135831.3-135862.6" - process $proc$libresoc.v:135831$6847 + attribute \src "libresoc.v:138270.3-138301.6" + process $proc$libresoc.v:138270$7121 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:135832.5-135832.29" + attribute \src "libresoc.v:138271.5-138271.29" switch \initial - attribute \src "libresoc.v:135832.9-135832.17" + attribute \src "libresoc.v:138271.9-138271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\nia[63:0] $2\nia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia[63:0] \$34 + assign $2\nia[63:0] \$35 case assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end @@ -283713,24 +289956,24 @@ module \main$35 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:135863.3-135894.6" - process $proc$libresoc.v:135863$6848 + attribute \src "libresoc.v:138302.3-138333.6" + process $proc$libresoc.v:138302$7122 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:135864.5-135864.29" + attribute \src "libresoc.v:138303.5-138303.29" switch \initial - attribute \src "libresoc.v:135864.9-135864.17" + attribute \src "libresoc.v:138303.9-138303.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\nia_ok[0:0] $2\nia_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -283759,69 +290002,69 @@ module \main$35 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:135895.3-135926.6" - process $proc$libresoc.v:135895$6849 + attribute \src "libresoc.v:138334.3-138365.6" + process $proc$libresoc.v:138334$7123 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$6850 $1\fast1$10[63:0]$6851 - attribute \src "libresoc.v:135896.5-135896.29" + assign $0\fast1$11[63:0]$7124 $1\fast1$11[63:0]$7125 + attribute \src "libresoc.v:138335.5-138335.29" switch \initial - attribute \src "libresoc.v:135896.9-135896.17" + attribute \src "libresoc.v:138335.9-138335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$10[63:0]$6851 $2\fast1$10[63:0]$6852 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + assign $1\fast1$11[63:0]$7125 $2\fast1$11[63:0]$7126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$10[63:0]$6852 \trap_op__cia + assign $2\fast1$11[63:0]$7126 \trap_op__cia case - assign $2\fast1$10[63:0]$6852 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7126 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$10[63:0]$6851 \$38 [63:0] + assign $1\fast1$11[63:0]$7125 \$39 [63:0] case - assign $1\fast1$10[63:0]$6851 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$10 $0\fast1$10[63:0]$6850 + update \fast1$11 $0\fast1$11[63:0]$7124 end - attribute \src "libresoc.v:135927.3-135958.6" - process $proc$libresoc.v:135927$6853 + attribute \src "libresoc.v:138366.3-138397.6" + process $proc$libresoc.v:138366$7127 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:135928.5-135928.29" + attribute \src "libresoc.v:138367.5-138367.29" switch \initial - attribute \src "libresoc.v:135928.9-135928.17" + attribute \src "libresoc.v:138367.9-138367.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -283849,125 +290092,144 @@ module \main$35 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:135959.3-136030.6" - process $proc$libresoc.v:135959$6854 + attribute \src "libresoc.v:138398.3-138480.6" + process $proc$libresoc.v:138398$7128 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$6855 $1\fast2$11[63:0]$6856 - attribute \src "libresoc.v:135960.5-135960.29" + assign $0\fast2$12[63:0]$7129 $1\fast2$12[63:0]$7130 + attribute \src "libresoc.v:138399.5-138399.29" switch \initial - attribute \src "libresoc.v:135960.9-135960.17" + attribute \src "libresoc.v:138399.9-138399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$11[63:0]$6856 $2\fast2$11[63:0]$6857 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + assign $1\fast2$12[63:0]$7130 $2\fast2$12[63:0]$7131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$11[63:0]$6857 [30:27] $2\fast2$11[63:0]$6857 [21] } 5'00000 - assign $2\fast2$11[63:0]$6857 [15:0] \trap_op__msr [15:0] - assign $2\fast2$11[63:0]$6857 [26:22] \trap_op__msr [26:22] - assign $2\fast2$11[63:0]$6857 [63:31] \trap_op__msr [63:31] - assign $2\fast2$11[63:0]$6857 [17] $3\fast2$11[17:17]$6858 - assign $2\fast2$11[63:0]$6857 [18] $4\fast2$11[18:18]$6859 - assign $2\fast2$11[63:0]$6857 [20] $5\fast2$11[20:20]$6860 - assign $2\fast2$11[63:0]$6857 [16] $6\fast2$11[16:16]$6861 - assign $2\fast2$11[63:0]$6857 [19] $7\fast2$11[19:19]$6862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - switch \$41 + assign { $2\fast2$12[63:0]$7131 [29] $2\fast2$12[63:0]$7131 [27] $2\fast2$12[63:0]$7131 [21] } 3'000 + assign $2\fast2$12[63:0]$7131 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7131 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7131 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7131 [17] $3\fast2$12[17:17]$7132 + assign { } { } + assign $2\fast2$12[63:0]$7131 [20] $5\fast2$12[20:20]$7134 + assign $2\fast2$12[63:0]$7131 [16] $6\fast2$12[16:16]$7135 + assign $2\fast2$12[63:0]$7131 [18] $7\fast2$12[19:18]$7136 [0] + assign $2\fast2$12[63:0]$7131 [28] $8\fast2$12[28:28]$7137 + assign $2\fast2$12[63:0]$7131 [30] $9\fast2$12[30:30]$7138 + assign $2\fast2$12[63:0]$7131 [19] $10\fast2$12[19:19]$7139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$11[17:17]$6858 1'1 + assign $3\fast2$12[17:17]$7132 1'1 case - assign $3\fast2$11[17:17]$6858 1'0 + assign $3\fast2$12[17:17]$7132 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - switch \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$11[18:18]$6859 1'1 + assign $4\fast2$12[18:18]$7133 1'1 case - assign $4\fast2$11[18:18]$6859 1'0 + assign $4\fast2$12[18:18]$7133 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - switch \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$11[20:20]$6860 1'1 + assign $5\fast2$12[20:20]$7134 1'1 case - assign $5\fast2$11[20:20]$6860 1'0 + assign $5\fast2$12[20:20]$7134 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - switch \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$11[16:16]$6861 1'1 + assign $6\fast2$12[16:16]$7135 1'1 case - assign $6\fast2$11[16:16]$6861 1'0 + assign $6\fast2$12[16:16]$7135 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - switch \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$56 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $9\fast2$12[30:30]$7138 \trapexc_$signal + assign $8\fast2$12[28:28]$7137 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7136 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7136 [0] \trapexc_$signal$62 + case + assign $7\fast2$12[19:18]$7136 { 1'0 $4\fast2$12[18:18]$7133 } + assign $8\fast2$12[28:28]$7137 1'0 + assign $9\fast2$12[30:30]$7138 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\fast2$11[19:19]$6862 1'1 + assign $10\fast2$12[19:19]$7139 1'1 case - assign $7\fast2$11[19:19]$6862 1'0 + assign $10\fast2$12[19:19]$7139 $7\fast2$12[19:18]$7136 [1] end case - assign $2\fast2$11[63:0]$6857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7131 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$11[63:0]$6856 [30:27] $1\fast2$11[63:0]$6856 [21:16] } 10'0000000000 - assign $1\fast2$11[63:0]$6856 [15:0] \trap_op__msr [15:0] - assign $1\fast2$11[63:0]$6856 [26:22] \trap_op__msr [26:22] - assign $1\fast2$11[63:0]$6856 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7130 [30:27] $1\fast2$12[63:0]$7130 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7130 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7130 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7130 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$11[63:0]$6856 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$6855 + update \fast2$12 $0\fast2$12[63:0]$7129 end - attribute \src "libresoc.v:136031.3-136062.6" - process $proc$libresoc.v:136031$6863 + attribute \src "libresoc.v:138481.3-138512.6" + process $proc$libresoc.v:138481$7140 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:136032.5-136032.29" + attribute \src "libresoc.v:138482.5-138482.29" switch \initial - attribute \src "libresoc.v:136032.9-136032.17" + attribute \src "libresoc.v:138482.9-138482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -283995,21 +290257,170 @@ module \main$35 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:136063.3-136231.6" - process $proc$libresoc.v:136063$6864 + attribute \src "libresoc.v:138513.3-138540.6" + process $proc$libresoc.v:138513$7141 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trapexc_$signal[0:0]$7142 $1\trapexc_$signal[0:0]$7150 + assign $0\trapexc_$signal$60[0:0]$7143 $1\trapexc_$signal$60[0:0]$7151 + assign $0\trapexc_$signal$61[0:0]$7144 $1\trapexc_$signal$61[0:0]$7152 + assign $0\trapexc_$signal$62[0:0]$7145 $1\trapexc_$signal$62[0:0]$7153 + assign $0\trapexc_$signal$67[0:0]$7146 $1\trapexc_$signal$67[0:0]$7154 + assign $0\trapexc_$signal$68[0:0]$7147 $1\trapexc_$signal$68[0:0]$7155 + assign $0\trapexc_$signal$69[0:0]$7148 $1\trapexc_$signal$69[0:0]$7156 + assign $0\trapexc_$signal$70[0:0]$7149 $1\trapexc_$signal$70[0:0]$7157 + attribute \src "libresoc.v:138514.5-138514.29" + switch \initial + attribute \src "libresoc.v:138514.9-138514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\trapexc_$signal[0:0]$7150 $2\trapexc_$signal[0:0]$7158 + assign $1\trapexc_$signal$60[0:0]$7151 $2\trapexc_$signal$60[0:0]$7159 + assign $1\trapexc_$signal$61[0:0]$7152 $2\trapexc_$signal$61[0:0]$7160 + assign $1\trapexc_$signal$62[0:0]$7153 $2\trapexc_$signal$62[0:0]$7161 + assign $1\trapexc_$signal$67[0:0]$7154 $2\trapexc_$signal$67[0:0]$7162 + assign $1\trapexc_$signal$68[0:0]$7155 $2\trapexc_$signal$68[0:0]$7163 + assign $1\trapexc_$signal$69[0:0]$7156 $2\trapexc_$signal$69[0:0]$7164 + assign $1\trapexc_$signal$70[0:0]$7157 $2\trapexc_$signal$70[0:0]$7165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\trapexc_$signal[0:0]$7158 $3\trapexc_$signal[0:0]$7166 + assign $2\trapexc_$signal$60[0:0]$7159 $3\trapexc_$signal$60[0:0]$7167 + assign $2\trapexc_$signal$61[0:0]$7160 $3\trapexc_$signal$61[0:0]$7168 + assign $2\trapexc_$signal$62[0:0]$7161 $3\trapexc_$signal$62[0:0]$7169 + assign $2\trapexc_$signal$67[0:0]$7162 $3\trapexc_$signal$67[0:0]$7170 + assign $2\trapexc_$signal$68[0:0]$7163 $3\trapexc_$signal$68[0:0]$7171 + assign $2\trapexc_$signal$69[0:0]$7164 $3\trapexc_$signal$69[0:0]$7172 + assign $2\trapexc_$signal$70[0:0]$7165 $3\trapexc_$signal$70[0:0]$7173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\trapexc_$signal$70[0:0]$7173 $3\trapexc_$signal$62[0:0]$7169 $3\trapexc_$signal$60[0:0]$7167 $3\trapexc_$signal$61[0:0]$7168 $3\trapexc_$signal[0:0]$7166 $3\trapexc_$signal$69[0:0]$7172 $3\trapexc_$signal$68[0:0]$7171 $3\trapexc_$signal$67[0:0]$7170 } \trap_op__ldst_exc + case + assign $3\trapexc_$signal[0:0]$7166 1'0 + assign $3\trapexc_$signal$60[0:0]$7167 1'0 + assign $3\trapexc_$signal$61[0:0]$7168 1'0 + assign $3\trapexc_$signal$62[0:0]$7169 1'0 + assign $3\trapexc_$signal$67[0:0]$7170 1'0 + assign $3\trapexc_$signal$68[0:0]$7171 1'0 + assign $3\trapexc_$signal$69[0:0]$7172 1'0 + assign $3\trapexc_$signal$70[0:0]$7173 1'0 + end + case + assign $2\trapexc_$signal[0:0]$7158 1'0 + assign $2\trapexc_$signal$60[0:0]$7159 1'0 + assign $2\trapexc_$signal$61[0:0]$7160 1'0 + assign $2\trapexc_$signal$62[0:0]$7161 1'0 + assign $2\trapexc_$signal$67[0:0]$7162 1'0 + assign $2\trapexc_$signal$68[0:0]$7163 1'0 + assign $2\trapexc_$signal$69[0:0]$7164 1'0 + assign $2\trapexc_$signal$70[0:0]$7165 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7150 1'0 + assign $1\trapexc_$signal$60[0:0]$7151 1'0 + assign $1\trapexc_$signal$61[0:0]$7152 1'0 + assign $1\trapexc_$signal$62[0:0]$7153 1'0 + assign $1\trapexc_$signal$67[0:0]$7154 1'0 + assign $1\trapexc_$signal$68[0:0]$7155 1'0 + assign $1\trapexc_$signal$69[0:0]$7156 1'0 + assign $1\trapexc_$signal$70[0:0]$7157 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7142 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7143 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7144 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7145 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7146 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7147 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7148 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7149 + end + attribute \src "libresoc.v:138541.3-138552.6" + process $proc$libresoc.v:138541$7174 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:138542.5-138542.29" + switch \initial + attribute \src "libresoc.v:138542.9-138542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "libresoc.v:138553.3-138721.6" + process $proc$libresoc.v:138553$7175 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:136064.5-136064.29" + attribute \src "libresoc.v:138554.5-138554.29" switch \initial - attribute \src "libresoc.v:136064.9-136064.17" + attribute \src "libresoc.v:138554.9-138554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 @@ -284017,7 +290428,7 @@ module \main$35 assign { } { } assign $1\msr[63:0] $2\msr[63:0] assign $1\msr_ok[0:0] $2\msr_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -284050,20 +290461,20 @@ module \main$35 case 7'1001000 , 7'1001010 assign { } { } assign { } { } - assign $1\msr[63:0] [0] \$59 [0] + assign $1\msr[63:0] [0] \$75 [0] assign $1\msr[63:0] [11:1] $3\msr[11:1] assign $1\msr[63:0] [59:13] $4\msr[59:13] assign $1\msr[63:0] [63:61] $5\msr[63:61] assign $1\msr[63:0] [12] $12\msr[12:12] assign $1\msr[63:0] [60] $13\msr[60:60] assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" switch \trap_op__insn [21] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\msr[11:1] [10:1] \$59 [11:2] - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$59 [59:16] \$59 [14:13] } - assign $5\msr[63:61] \$59 [63:61] + assign $3\msr[11:1] [10:1] \$75 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } + assign $5\msr[63:61] \$75 [63:61] assign $3\msr[11:1] [0] \ra [1] assign $4\msr[59:13] [2] \ra [15] attribute \src "libresoc.v:0.0-0.0" @@ -284076,8 +290487,8 @@ module \main$35 assign $5\msr[63:61] $8\msr[63:61] assign $3\msr[11:1] [4:3] $10\msr[5:4] assign $4\msr[59:13] [2] $11\msr[15:15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - switch \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -284087,8 +290498,8 @@ module \main$35 assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } assign $8\msr[63:61] \ra [63:61] assign $7\msr[59:13] [21:19] $9\msr[34:32] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - switch \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch \$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -284099,12 +290510,12 @@ module \main$35 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $7\msr[59:13] [46:19] \$59 [59:32] - assign $8\msr[63:61] \$59 [63:61] + assign $7\msr[59:13] [46:19] \$75 [59:32] + assign $8\msr[63:61] \$75 [63:61] assign $6\msr[11:1] \ra [11:1] assign $7\msr[59:13] [18:0] \ra [31:13] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" switch $7\msr[59:13] [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -284118,8 +290529,8 @@ module \main$35 assign $11\msr[15:15] $7\msr[59:13] [2] end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - switch \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + switch \$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -284127,8 +290538,8 @@ module \main$35 assign $13\msr[60:60] \trap_op__msr [60] assign $12\msr[12:12] \trap_op__msr [12] case - assign $12\msr[12:12] \$59 [12] - assign $13\msr[60:60] \$59 [60] + assign $12\msr[12:12] \$75 [12] + assign $13\msr[60:60] \$75 [60] end attribute \src "libresoc.v:0.0-0.0" case 7'1000111 @@ -284146,13 +290557,13 @@ module \main$35 assign $1\msr[63:0] [15] $17\msr[15:15] assign $1\msr[63:0] [34:32] $18\msr[34:32] assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - switch \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $14\msr[12:12] $15\msr[12:12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" switch \trap_op__msr [60] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -284166,7 +290577,7 @@ module \main$35 case assign $14\msr[12:12] \fast2 [12] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" switch \fast2 [14] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -284179,8 +290590,8 @@ module \main$35 assign $16\msr[5:4] \fast2 [5:4] assign $17\msr[15:15] \fast2 [15] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - switch \$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -284219,42 +290630,18 @@ module \main$35 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:136232.3-136243.6" - process $proc$libresoc.v:136232$6865 - assign { } { } - assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:136233.5-136233.29" - switch \initial - attribute \src "libresoc.v:136233.9-136233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b_s[63:0] \rb - end - sync always - update \b_s $0\b_s[63:0] - end - attribute \src "libresoc.v:136244.3-136262.6" - process $proc$libresoc.v:136244$6866 + attribute \src "libresoc.v:138722.3-138740.6" + process $proc$libresoc.v:138722$7176 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:136245.5-136245.29" + attribute \src "libresoc.v:138723.5-138723.29" switch \initial - attribute \src "libresoc.v:136245.9-136245.17" + attribute \src "libresoc.v:138723.9-138723.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 @@ -284272,18 +290659,18 @@ module \main$35 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:136263.3-136281.6" - process $proc$libresoc.v:136263$6867 + attribute \src "libresoc.v:138741.3-138759.6" + process $proc$libresoc.v:138741$7177 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:136264.5-136264.29" + attribute \src "libresoc.v:138742.5-138742.29" switch \initial - attribute \src "libresoc.v:136264.9-136264.17" + attribute \src "libresoc.v:138742.9-138742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0111111 @@ -284301,22 +290688,22 @@ module \main$35 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:136282.3-136293.6" - process $proc$libresoc.v:136282$6868 + attribute \src "libresoc.v:138760.3-138771.6" + process $proc$libresoc.v:138760$7178 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136283.5-136283.29" + attribute \src "libresoc.v:138761.5-138761.29" switch \initial - attribute \src "libresoc.v:136283.9-136283.17" + attribute \src "libresoc.v:138761.9-138761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a[63:0] \$12 + assign $1\a[63:0] \$13 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -284325,22 +290712,22 @@ module \main$35 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136294.3-136305.6" - process $proc$libresoc.v:136294$6869 + attribute \src "libresoc.v:138772.3-138783.6" + process $proc$libresoc.v:138772$7179 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:136295.5-136295.29" + attribute \src "libresoc.v:138773.5-138773.29" switch \initial - attribute \src "libresoc.v:136295.9-136295.17" + attribute \src "libresoc.v:138773.9-138773.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\b[63:0] \$14 + assign $1\b[63:0] \$15 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -284349,284 +290736,288 @@ module \main$35 sync always update \b $0\b[63:0] end - connect \$12 $pos$libresoc.v:135786$6810_Y - connect \$14 $pos$libresoc.v:135787$6812_Y - connect \$16 $lt$libresoc.v:135788$6813_Y - connect \$18 $gt$libresoc.v:135789$6814_Y - connect \$20 $lt$libresoc.v:135790$6815_Y - connect \$22 $gt$libresoc.v:135791$6816_Y - connect \$24 $eq$libresoc.v:135792$6817_Y - connect \$27 $and$libresoc.v:135793$6818_Y - connect \$26 $reduce_or$libresoc.v:135794$6819_Y - connect \$30 $reduce_or$libresoc.v:135795$6820_Y - connect \$32 $or$libresoc.v:135796$6821_Y - connect \$35 $sshl$libresoc.v:135797$6822_Y - connect \$34 $pos$libresoc.v:135798$6824_Y - connect \$39 $add$libresoc.v:135799$6825_Y - connect \$41 $eq$libresoc.v:135800$6826_Y - connect \$44 $and$libresoc.v:135801$6827_Y - connect \$43 $reduce_or$libresoc.v:135802$6828_Y - connect \$48 $and$libresoc.v:135803$6829_Y - connect \$47 $reduce_or$libresoc.v:135804$6830_Y - connect \$52 $and$libresoc.v:135805$6831_Y - connect \$51 $reduce_or$libresoc.v:135806$6832_Y - connect \$56 $and$libresoc.v:135807$6833_Y - connect \$55 $reduce_or$libresoc.v:135808$6834_Y - connect \$59 $pos$libresoc.v:135809$6836_Y - connect \$61 $eq$libresoc.v:135810$6837_Y - connect \$63 $eq$libresoc.v:135811$6838_Y - connect \$65 $eq$libresoc.v:135812$6839_Y - connect \$67 $and$libresoc.v:135813$6840_Y - connect \$69 $not$libresoc.v:135814$6841_Y - connect \$71 $not$libresoc.v:135815$6842_Y - connect \$73 $eq$libresoc.v:135816$6843_Y - connect \$75 $eq$libresoc.v:135817$6844_Y - connect \$77 $and$libresoc.v:135818$6845_Y - connect \$38 \$39 - connect { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \$13 $pos$libresoc.v:138221$7080_Y + connect \$15 $pos$libresoc.v:138222$7082_Y + connect \$17 $lt$libresoc.v:138223$7083_Y + connect \$19 $gt$libresoc.v:138224$7084_Y + connect \$21 $lt$libresoc.v:138225$7085_Y + connect \$23 $gt$libresoc.v:138226$7086_Y + connect \$25 $eq$libresoc.v:138227$7087_Y + connect \$28 $and$libresoc.v:138228$7088_Y + connect \$27 $reduce_or$libresoc.v:138229$7089_Y + connect \$31 $reduce_or$libresoc.v:138230$7090_Y + connect \$33 $or$libresoc.v:138231$7091_Y + connect \$36 $sshl$libresoc.v:138232$7092_Y + connect \$35 $pos$libresoc.v:138233$7094_Y + connect \$40 $add$libresoc.v:138234$7095_Y + connect \$42 $eq$libresoc.v:138235$7096_Y + connect \$45 $and$libresoc.v:138236$7097_Y + connect \$44 $reduce_or$libresoc.v:138237$7098_Y + connect \$49 $and$libresoc.v:138238$7099_Y + connect \$48 $reduce_or$libresoc.v:138239$7100_Y + connect \$53 $and$libresoc.v:138240$7101_Y + connect \$52 $reduce_or$libresoc.v:138241$7102_Y + connect \$57 $and$libresoc.v:138242$7103_Y + connect \$56 $reduce_or$libresoc.v:138243$7104_Y + connect \$64 $and$libresoc.v:138244$7105_Y + connect \$63 $reduce_or$libresoc.v:138245$7106_Y + connect \$72 $and$libresoc.v:138246$7107_Y + connect \$71 $reduce_or$libresoc.v:138247$7108_Y + connect \$75 $pos$libresoc.v:138248$7110_Y + connect \$77 $eq$libresoc.v:138249$7111_Y + connect \$79 $eq$libresoc.v:138250$7112_Y + connect \$81 $eq$libresoc.v:138251$7113_Y + connect \$83 $and$libresoc.v:138252$7114_Y + connect \$85 $not$libresoc.v:138253$7115_Y + connect \$87 $not$libresoc.v:138254$7116_Y + connect \$89 $eq$libresoc.v:138255$7117_Y + connect \$91 $eq$libresoc.v:138256$7118_Y + connect \$93 $and$libresoc.v:138257$7119_Y + connect \$39 \$40 + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid - connect \should_trap \$32 + connect \should_trap \$33 connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } - connect \equal \$24 - connect \gt_u \$22 - connect \lt_u \$20 - connect \gt_s \$18 - connect \lt_s \$16 + connect \equal \$25 + connect \gt_u \$23 + connect \lt_u \$21 + connect \gt_s \$19 + connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:136321.1-137064.10" +attribute \src "libresoc.v:138799.1-139542.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" -module \main$48 - attribute \src "libresoc.v:137031.3-137041.6" +module \main$51 + attribute \src "libresoc.v:139509.3-139519.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:136976.3-136986.6" + attribute \src "libresoc.v:139454.3-139464.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:136954.3-136964.6" + attribute \src "libresoc.v:139432.3-139442.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:136943.3-136953.6" + attribute \src "libresoc.v:139421.3-139431.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:136932.3-136942.6" + attribute \src "libresoc.v:139410.3-139420.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:137042.3-137060.6" + attribute \src "libresoc.v:139520.3-139538.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:137020.3-137030.6" + attribute \src "libresoc.v:139498.3-139508.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:136322.7-136322.20" + attribute \src "libresoc.v:138800.7-138800.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136877.3-136931.6" + attribute \src "libresoc.v:139355.3-139409.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:136877.3-136931.6" + attribute \src "libresoc.v:139355.3-139409.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:136998.3-137008.6" + attribute \src "libresoc.v:139476.3-139486.6" wire $0\par0[0:0] - attribute \src "libresoc.v:137009.3-137019.6" + attribute \src "libresoc.v:139487.3-139497.6" wire $0\par1[0:0] - attribute \src "libresoc.v:136965.3-136975.6" + attribute \src "libresoc.v:139443.3-139453.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:136987.3-136997.6" + attribute \src "libresoc.v:139465.3-139475.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:137031.3-137041.6" + attribute \src "libresoc.v:139509.3-139519.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:136976.3-136986.6" + attribute \src "libresoc.v:139454.3-139464.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:136954.3-136964.6" + attribute \src "libresoc.v:139432.3-139442.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:136943.3-136953.6" + attribute \src "libresoc.v:139421.3-139431.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:136932.3-136942.6" + attribute \src "libresoc.v:139410.3-139420.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:137042.3-137060.6" + attribute \src "libresoc.v:139520.3-139538.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:137020.3-137030.6" + attribute \src "libresoc.v:139498.3-139508.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:136877.3-136931.6" + attribute \src "libresoc.v:139355.3-139409.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:136877.3-136931.6" + attribute \src "libresoc.v:139355.3-139409.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:136998.3-137008.6" + attribute \src "libresoc.v:139476.3-139486.6" wire $1\par0[0:0] - attribute \src "libresoc.v:137009.3-137019.6" + attribute \src "libresoc.v:139487.3-139497.6" wire $1\par1[0:0] - attribute \src "libresoc.v:136965.3-136975.6" + attribute \src "libresoc.v:139443.3-139453.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:136987.3-136997.6" + attribute \src "libresoc.v:139465.3-139475.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:137042.3-137060.6" + attribute \src "libresoc.v:139520.3-139538.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:136877.3-136931.6" + attribute \src "libresoc.v:139355.3-139409.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:136824.18-136824.103" - wire width 64 $and$libresoc.v:136824$6917_Y - attribute \src "libresoc.v:136783.18-136783.118" - wire $eq$libresoc.v:136783$6871_Y - attribute \src "libresoc.v:136784.19-136784.119" - wire $eq$libresoc.v:136784$6872_Y - attribute \src "libresoc.v:136785.19-136785.119" - wire $eq$libresoc.v:136785$6873_Y - attribute \src "libresoc.v:136786.19-136786.119" - wire $eq$libresoc.v:136786$6874_Y - attribute \src "libresoc.v:136787.19-136787.119" - wire $eq$libresoc.v:136787$6875_Y - attribute \src "libresoc.v:136788.19-136788.119" - wire $eq$libresoc.v:136788$6876_Y - attribute \src "libresoc.v:136789.19-136789.119" - wire $eq$libresoc.v:136789$6877_Y - attribute \src "libresoc.v:136790.19-136790.119" - wire $eq$libresoc.v:136790$6878_Y - attribute \src "libresoc.v:136791.19-136791.119" - wire $eq$libresoc.v:136791$6879_Y - attribute \src "libresoc.v:136792.19-136792.119" - wire $eq$libresoc.v:136792$6880_Y - attribute \src "libresoc.v:136793.19-136793.119" - wire $eq$libresoc.v:136793$6881_Y - attribute \src "libresoc.v:136794.19-136794.119" - wire $eq$libresoc.v:136794$6882_Y - attribute \src "libresoc.v:136795.19-136795.119" - wire $eq$libresoc.v:136795$6883_Y - attribute \src "libresoc.v:136796.19-136796.119" - wire $eq$libresoc.v:136796$6884_Y - attribute \src "libresoc.v:136797.19-136797.119" - wire $eq$libresoc.v:136797$6885_Y - attribute \src "libresoc.v:136798.19-136798.119" - wire $eq$libresoc.v:136798$6886_Y - attribute \src "libresoc.v:136799.19-136799.119" - wire $eq$libresoc.v:136799$6887_Y - attribute \src "libresoc.v:136800.19-136800.119" - wire $eq$libresoc.v:136800$6888_Y - attribute \src "libresoc.v:136801.19-136801.119" - wire $eq$libresoc.v:136801$6889_Y - attribute \src "libresoc.v:136802.19-136802.119" - wire $eq$libresoc.v:136802$6890_Y - attribute \src "libresoc.v:136803.19-136803.119" - wire $eq$libresoc.v:136803$6891_Y - attribute \src "libresoc.v:136804.19-136804.119" - wire $eq$libresoc.v:136804$6892_Y - attribute \src "libresoc.v:136805.19-136805.119" - wire $eq$libresoc.v:136805$6893_Y - attribute \src "libresoc.v:136806.19-136806.119" - wire $eq$libresoc.v:136806$6894_Y - attribute \src "libresoc.v:136807.19-136807.119" - wire $eq$libresoc.v:136807$6895_Y - attribute \src "libresoc.v:136808.19-136808.119" - wire $eq$libresoc.v:136808$6896_Y - attribute \src "libresoc.v:136809.19-136809.119" - wire $eq$libresoc.v:136809$6897_Y - attribute \src "libresoc.v:136810.19-136810.119" - wire $eq$libresoc.v:136810$6898_Y - attribute \src "libresoc.v:136811.19-136811.128" - wire $eq$libresoc.v:136811$6899_Y - attribute \src "libresoc.v:136827.18-136827.114" - wire $eq$libresoc.v:136827$6920_Y - attribute \src "libresoc.v:136828.18-136828.114" - wire $eq$libresoc.v:136828$6921_Y - attribute \src "libresoc.v:136829.18-136829.114" - wire $eq$libresoc.v:136829$6922_Y - attribute \src "libresoc.v:136830.18-136830.114" - wire $eq$libresoc.v:136830$6923_Y - attribute \src "libresoc.v:136831.18-136831.114" - wire $eq$libresoc.v:136831$6924_Y - attribute \src "libresoc.v:136832.18-136832.114" - wire $eq$libresoc.v:136832$6925_Y - attribute \src "libresoc.v:136833.18-136833.114" - wire $eq$libresoc.v:136833$6926_Y - attribute \src "libresoc.v:136834.18-136834.114" - wire $eq$libresoc.v:136834$6927_Y - attribute \src "libresoc.v:136835.18-136835.116" - wire $eq$libresoc.v:136835$6928_Y - attribute \src "libresoc.v:136836.18-136836.116" - wire $eq$libresoc.v:136836$6929_Y - attribute \src "libresoc.v:136837.18-136837.116" - wire $eq$libresoc.v:136837$6930_Y - attribute \src "libresoc.v:136838.18-136838.116" - wire $eq$libresoc.v:136838$6931_Y - attribute \src "libresoc.v:136839.18-136839.116" - wire $eq$libresoc.v:136839$6932_Y - attribute \src "libresoc.v:136840.18-136840.116" - wire $eq$libresoc.v:136840$6933_Y - attribute \src "libresoc.v:136841.18-136841.116" - wire $eq$libresoc.v:136841$6934_Y - attribute \src "libresoc.v:136842.18-136842.116" - wire $eq$libresoc.v:136842$6935_Y - attribute \src "libresoc.v:136843.18-136843.118" - wire $eq$libresoc.v:136843$6936_Y - attribute \src "libresoc.v:136844.18-136844.118" - wire $eq$libresoc.v:136844$6937_Y - attribute \src "libresoc.v:136845.18-136845.118" - wire $eq$libresoc.v:136845$6938_Y - attribute \src "libresoc.v:136846.18-136846.118" - wire $eq$libresoc.v:136846$6939_Y - attribute \src "libresoc.v:136847.18-136847.118" - wire $eq$libresoc.v:136847$6940_Y - attribute \src "libresoc.v:136848.18-136848.118" - wire $eq$libresoc.v:136848$6941_Y - attribute \src "libresoc.v:136849.18-136849.118" - wire $eq$libresoc.v:136849$6942_Y - attribute \src "libresoc.v:136850.18-136850.118" - wire $eq$libresoc.v:136850$6943_Y - attribute \src "libresoc.v:136851.18-136851.118" - wire $eq$libresoc.v:136851$6944_Y - attribute \src "libresoc.v:136852.18-136852.118" - wire $eq$libresoc.v:136852$6945_Y - attribute \src "libresoc.v:136853.18-136853.118" - wire $eq$libresoc.v:136853$6946_Y - attribute \src "libresoc.v:136854.18-136854.118" - wire $eq$libresoc.v:136854$6947_Y - attribute \src "libresoc.v:136855.18-136855.118" - wire $eq$libresoc.v:136855$6948_Y - attribute \src "libresoc.v:136856.18-136856.118" - wire $eq$libresoc.v:136856$6949_Y - attribute \src "libresoc.v:136857.18-136857.118" - wire $eq$libresoc.v:136857$6950_Y - attribute \src "libresoc.v:136858.18-136858.118" - wire $eq$libresoc.v:136858$6951_Y - attribute \src "libresoc.v:136859.18-136859.118" - wire $eq$libresoc.v:136859$6952_Y - attribute \src "libresoc.v:136860.18-136860.118" - wire $eq$libresoc.v:136860$6953_Y - attribute \src "libresoc.v:136861.18-136861.118" - wire $eq$libresoc.v:136861$6954_Y - attribute \src "libresoc.v:136862.18-136862.118" - wire $eq$libresoc.v:136862$6955_Y - attribute \src "libresoc.v:136813.19-136813.104" - wire width 64 $extend$libresoc.v:136813$6901_Y - attribute \src "libresoc.v:136815.19-136815.93" - wire width 8 $extend$libresoc.v:136815$6904_Y - attribute \src "libresoc.v:136817.19-136817.105" - wire width 64 $extend$libresoc.v:136817$6907_Y - attribute \src "libresoc.v:136818.19-136818.118" - wire width 64 $extend$libresoc.v:136818$6909_Y - attribute \src "libresoc.v:136822.19-136822.105" - wire width 64 $extend$libresoc.v:136822$6914_Y - attribute \src "libresoc.v:136825.18-136825.103" - wire width 64 $or$libresoc.v:136825$6918_Y - attribute \src "libresoc.v:136813.19-136813.104" - wire width 64 $pos$libresoc.v:136813$6902_Y - attribute \src "libresoc.v:136815.19-136815.93" - wire width 8 $pos$libresoc.v:136815$6905_Y - attribute \src "libresoc.v:136817.19-136817.105" - wire width 64 $pos$libresoc.v:136817$6908_Y - attribute \src "libresoc.v:136818.19-136818.118" - wire width 64 $pos$libresoc.v:136818$6910_Y - attribute \src "libresoc.v:136822.19-136822.105" - wire width 64 $pos$libresoc.v:136822$6915_Y - attribute \src "libresoc.v:136819.19-136819.131" - wire $reduce_xor$libresoc.v:136819$6911_Y - attribute \src "libresoc.v:136820.19-136820.133" - wire $reduce_xor$libresoc.v:136820$6912_Y - attribute \src "libresoc.v:136814.19-136814.112" - wire width 8 $sub$libresoc.v:136814$6903_Y - attribute \src "libresoc.v:136816.19-136816.135" - wire width 8 $ternary$libresoc.v:136816$6906_Y - attribute \src "libresoc.v:136821.19-136821.398" - wire width 32 $ternary$libresoc.v:136821$6913_Y - attribute \src "libresoc.v:136823.19-136823.621" - wire width 64 $ternary$libresoc.v:136823$6916_Y - attribute \src "libresoc.v:136812.19-136812.108" - wire $xor$libresoc.v:136812$6900_Y - attribute \src "libresoc.v:136826.18-136826.103" - wire width 64 $xor$libresoc.v:136826$6919_Y + attribute \src "libresoc.v:139302.18-139302.103" + wire width 64 $and$libresoc.v:139302$7227_Y + attribute \src "libresoc.v:139261.18-139261.118" + wire $eq$libresoc.v:139261$7181_Y + attribute \src "libresoc.v:139262.19-139262.119" + wire $eq$libresoc.v:139262$7182_Y + attribute \src "libresoc.v:139263.19-139263.119" + wire $eq$libresoc.v:139263$7183_Y + attribute \src "libresoc.v:139264.19-139264.119" + wire $eq$libresoc.v:139264$7184_Y + attribute \src "libresoc.v:139265.19-139265.119" + wire $eq$libresoc.v:139265$7185_Y + attribute \src "libresoc.v:139266.19-139266.119" + wire $eq$libresoc.v:139266$7186_Y + attribute \src "libresoc.v:139267.19-139267.119" + wire $eq$libresoc.v:139267$7187_Y + attribute \src "libresoc.v:139268.19-139268.119" + wire $eq$libresoc.v:139268$7188_Y + attribute \src "libresoc.v:139269.19-139269.119" + wire $eq$libresoc.v:139269$7189_Y + attribute \src "libresoc.v:139270.19-139270.119" + wire $eq$libresoc.v:139270$7190_Y + attribute \src "libresoc.v:139271.19-139271.119" + wire $eq$libresoc.v:139271$7191_Y + attribute \src "libresoc.v:139272.19-139272.119" + wire $eq$libresoc.v:139272$7192_Y + attribute \src "libresoc.v:139273.19-139273.119" + wire $eq$libresoc.v:139273$7193_Y + attribute \src "libresoc.v:139274.19-139274.119" + wire $eq$libresoc.v:139274$7194_Y + attribute \src "libresoc.v:139275.19-139275.119" + wire $eq$libresoc.v:139275$7195_Y + attribute \src "libresoc.v:139276.19-139276.119" + wire $eq$libresoc.v:139276$7196_Y + attribute \src "libresoc.v:139277.19-139277.119" + wire $eq$libresoc.v:139277$7197_Y + attribute \src "libresoc.v:139278.19-139278.119" + wire $eq$libresoc.v:139278$7198_Y + attribute \src "libresoc.v:139279.19-139279.119" + wire $eq$libresoc.v:139279$7199_Y + attribute \src "libresoc.v:139280.19-139280.119" + wire $eq$libresoc.v:139280$7200_Y + attribute \src "libresoc.v:139281.19-139281.119" + wire $eq$libresoc.v:139281$7201_Y + attribute \src "libresoc.v:139282.19-139282.119" + wire $eq$libresoc.v:139282$7202_Y + attribute \src "libresoc.v:139283.19-139283.119" + wire $eq$libresoc.v:139283$7203_Y + attribute \src "libresoc.v:139284.19-139284.119" + wire $eq$libresoc.v:139284$7204_Y + attribute \src "libresoc.v:139285.19-139285.119" + wire $eq$libresoc.v:139285$7205_Y + attribute \src "libresoc.v:139286.19-139286.119" + wire $eq$libresoc.v:139286$7206_Y + attribute \src "libresoc.v:139287.19-139287.119" + wire $eq$libresoc.v:139287$7207_Y + attribute \src "libresoc.v:139288.19-139288.119" + wire $eq$libresoc.v:139288$7208_Y + attribute \src "libresoc.v:139289.19-139289.128" + wire $eq$libresoc.v:139289$7209_Y + attribute \src "libresoc.v:139305.18-139305.114" + wire $eq$libresoc.v:139305$7230_Y + attribute \src "libresoc.v:139306.18-139306.114" + wire $eq$libresoc.v:139306$7231_Y + attribute \src "libresoc.v:139307.18-139307.114" + wire $eq$libresoc.v:139307$7232_Y + attribute \src "libresoc.v:139308.18-139308.114" + wire $eq$libresoc.v:139308$7233_Y + attribute \src "libresoc.v:139309.18-139309.114" + wire $eq$libresoc.v:139309$7234_Y + attribute \src "libresoc.v:139310.18-139310.114" + wire $eq$libresoc.v:139310$7235_Y + attribute \src "libresoc.v:139311.18-139311.114" + wire $eq$libresoc.v:139311$7236_Y + attribute \src "libresoc.v:139312.18-139312.114" + wire $eq$libresoc.v:139312$7237_Y + attribute \src "libresoc.v:139313.18-139313.116" + wire $eq$libresoc.v:139313$7238_Y + attribute \src "libresoc.v:139314.18-139314.116" + wire $eq$libresoc.v:139314$7239_Y + attribute \src "libresoc.v:139315.18-139315.116" + wire $eq$libresoc.v:139315$7240_Y + attribute \src "libresoc.v:139316.18-139316.116" + wire $eq$libresoc.v:139316$7241_Y + attribute \src "libresoc.v:139317.18-139317.116" + wire $eq$libresoc.v:139317$7242_Y + attribute \src "libresoc.v:139318.18-139318.116" + wire $eq$libresoc.v:139318$7243_Y + attribute \src "libresoc.v:139319.18-139319.116" + wire $eq$libresoc.v:139319$7244_Y + attribute \src "libresoc.v:139320.18-139320.116" + wire $eq$libresoc.v:139320$7245_Y + attribute \src "libresoc.v:139321.18-139321.118" + wire $eq$libresoc.v:139321$7246_Y + attribute \src "libresoc.v:139322.18-139322.118" + wire $eq$libresoc.v:139322$7247_Y + attribute \src "libresoc.v:139323.18-139323.118" + wire $eq$libresoc.v:139323$7248_Y + attribute \src "libresoc.v:139324.18-139324.118" + wire $eq$libresoc.v:139324$7249_Y + attribute \src "libresoc.v:139325.18-139325.118" + wire $eq$libresoc.v:139325$7250_Y + attribute \src "libresoc.v:139326.18-139326.118" + wire $eq$libresoc.v:139326$7251_Y + attribute \src "libresoc.v:139327.18-139327.118" + wire $eq$libresoc.v:139327$7252_Y + attribute \src "libresoc.v:139328.18-139328.118" + wire $eq$libresoc.v:139328$7253_Y + attribute \src "libresoc.v:139329.18-139329.118" + wire $eq$libresoc.v:139329$7254_Y + attribute \src "libresoc.v:139330.18-139330.118" + wire $eq$libresoc.v:139330$7255_Y + attribute \src "libresoc.v:139331.18-139331.118" + wire $eq$libresoc.v:139331$7256_Y + attribute \src "libresoc.v:139332.18-139332.118" + wire $eq$libresoc.v:139332$7257_Y + attribute \src "libresoc.v:139333.18-139333.118" + wire $eq$libresoc.v:139333$7258_Y + attribute \src "libresoc.v:139334.18-139334.118" + wire $eq$libresoc.v:139334$7259_Y + attribute \src "libresoc.v:139335.18-139335.118" + wire $eq$libresoc.v:139335$7260_Y + attribute \src "libresoc.v:139336.18-139336.118" + wire $eq$libresoc.v:139336$7261_Y + attribute \src "libresoc.v:139337.18-139337.118" + wire $eq$libresoc.v:139337$7262_Y + attribute \src "libresoc.v:139338.18-139338.118" + wire $eq$libresoc.v:139338$7263_Y + attribute \src "libresoc.v:139339.18-139339.118" + wire $eq$libresoc.v:139339$7264_Y + attribute \src "libresoc.v:139340.18-139340.118" + wire $eq$libresoc.v:139340$7265_Y + attribute \src "libresoc.v:139291.19-139291.104" + wire width 64 $extend$libresoc.v:139291$7211_Y + attribute \src "libresoc.v:139293.19-139293.93" + wire width 8 $extend$libresoc.v:139293$7214_Y + attribute \src "libresoc.v:139295.19-139295.105" + wire width 64 $extend$libresoc.v:139295$7217_Y + attribute \src "libresoc.v:139296.19-139296.118" + wire width 64 $extend$libresoc.v:139296$7219_Y + attribute \src "libresoc.v:139300.19-139300.105" + wire width 64 $extend$libresoc.v:139300$7224_Y + attribute \src "libresoc.v:139303.18-139303.103" + wire width 64 $or$libresoc.v:139303$7228_Y + attribute \src "libresoc.v:139291.19-139291.104" + wire width 64 $pos$libresoc.v:139291$7212_Y + attribute \src "libresoc.v:139293.19-139293.93" + wire width 8 $pos$libresoc.v:139293$7215_Y + attribute \src "libresoc.v:139295.19-139295.105" + wire width 64 $pos$libresoc.v:139295$7218_Y + attribute \src "libresoc.v:139296.19-139296.118" + wire width 64 $pos$libresoc.v:139296$7220_Y + attribute \src "libresoc.v:139300.19-139300.105" + wire width 64 $pos$libresoc.v:139300$7225_Y + attribute \src "libresoc.v:139297.19-139297.131" + wire $reduce_xor$libresoc.v:139297$7221_Y + attribute \src "libresoc.v:139298.19-139298.133" + wire $reduce_xor$libresoc.v:139298$7222_Y + attribute \src "libresoc.v:139292.19-139292.112" + wire width 8 $sub$libresoc.v:139292$7213_Y + attribute \src "libresoc.v:139294.19-139294.135" + wire width 8 $ternary$libresoc.v:139294$7216_Y + attribute \src "libresoc.v:139299.19-139299.398" + wire width 32 $ternary$libresoc.v:139299$7223_Y + attribute \src "libresoc.v:139301.19-139301.621" + wire width 64 $ternary$libresoc.v:139301$7226_Y + attribute \src "libresoc.v:139290.19-139290.108" + wire $xor$libresoc.v:139290$7210_Y + attribute \src "libresoc.v:139304.18-139304.103" + wire width 64 $xor$libresoc.v:139304$7229_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -284805,7 +291196,7 @@ module \main$48 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:136322.7-136322.15" + attribute \src "libresoc.v:138800.7-138800.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -285065,9 +291456,9 @@ module \main$48 wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" wire \par0 @@ -285085,10 +291476,10 @@ module \main$48 wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:136824$6917 + cell $and $and$libresoc.v:139302$7227 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -285096,10 +291487,10 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:136824$6917_Y + connect \Y $and$libresoc.v:139302$7227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136783$6871 + cell $eq $eq$libresoc.v:139261$7181 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285107,10 +291498,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136783$6871_Y + connect \Y $eq$libresoc.v:139261$7181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136784$6872 + cell $eq $eq$libresoc.v:139262$7182 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285118,10 +291509,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136784$6872_Y + connect \Y $eq$libresoc.v:139262$7182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136785$6873 + cell $eq $eq$libresoc.v:139263$7183 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285129,10 +291520,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136785$6873_Y + connect \Y $eq$libresoc.v:139263$7183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136786$6874 + cell $eq $eq$libresoc.v:139264$7184 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285140,10 +291531,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136786$6874_Y + connect \Y $eq$libresoc.v:139264$7184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136787$6875 + cell $eq $eq$libresoc.v:139265$7185 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285151,10 +291542,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136787$6875_Y + connect \Y $eq$libresoc.v:139265$7185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136788$6876 + cell $eq $eq$libresoc.v:139266$7186 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285162,10 +291553,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136788$6876_Y + connect \Y $eq$libresoc.v:139266$7186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136789$6877 + cell $eq $eq$libresoc.v:139267$7187 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285173,10 +291564,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136789$6877_Y + connect \Y $eq$libresoc.v:139267$7187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136790$6878 + cell $eq $eq$libresoc.v:139268$7188 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285184,10 +291575,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136790$6878_Y + connect \Y $eq$libresoc.v:139268$7188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136791$6879 + cell $eq $eq$libresoc.v:139269$7189 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285195,10 +291586,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136791$6879_Y + connect \Y $eq$libresoc.v:139269$7189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136792$6880 + cell $eq $eq$libresoc.v:139270$7190 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285206,10 +291597,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136792$6880_Y + connect \Y $eq$libresoc.v:139270$7190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136793$6881 + cell $eq $eq$libresoc.v:139271$7191 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285217,10 +291608,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136793$6881_Y + connect \Y $eq$libresoc.v:139271$7191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136794$6882 + cell $eq $eq$libresoc.v:139272$7192 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285228,10 +291619,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136794$6882_Y + connect \Y $eq$libresoc.v:139272$7192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136795$6883 + cell $eq $eq$libresoc.v:139273$7193 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285239,10 +291630,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136795$6883_Y + connect \Y $eq$libresoc.v:139273$7193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136796$6884 + cell $eq $eq$libresoc.v:139274$7194 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285250,10 +291641,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136796$6884_Y + connect \Y $eq$libresoc.v:139274$7194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136797$6885 + cell $eq $eq$libresoc.v:139275$7195 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285261,10 +291652,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136797$6885_Y + connect \Y $eq$libresoc.v:139275$7195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136798$6886 + cell $eq $eq$libresoc.v:139276$7196 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285272,10 +291663,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136798$6886_Y + connect \Y $eq$libresoc.v:139276$7196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136799$6887 + cell $eq $eq$libresoc.v:139277$7197 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285283,10 +291674,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136799$6887_Y + connect \Y $eq$libresoc.v:139277$7197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136800$6888 + cell $eq $eq$libresoc.v:139278$7198 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285294,10 +291685,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136800$6888_Y + connect \Y $eq$libresoc.v:139278$7198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136801$6889 + cell $eq $eq$libresoc.v:139279$7199 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285305,10 +291696,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136801$6889_Y + connect \Y $eq$libresoc.v:139279$7199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136802$6890 + cell $eq $eq$libresoc.v:139280$7200 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285316,10 +291707,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136802$6890_Y + connect \Y $eq$libresoc.v:139280$7200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136803$6891 + cell $eq $eq$libresoc.v:139281$7201 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285327,10 +291718,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136803$6891_Y + connect \Y $eq$libresoc.v:139281$7201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136804$6892 + cell $eq $eq$libresoc.v:139282$7202 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285338,10 +291729,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136804$6892_Y + connect \Y $eq$libresoc.v:139282$7202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136805$6893 + cell $eq $eq$libresoc.v:139283$7203 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285349,10 +291740,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136805$6893_Y + connect \Y $eq$libresoc.v:139283$7203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136806$6894 + cell $eq $eq$libresoc.v:139284$7204 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285360,10 +291751,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136806$6894_Y + connect \Y $eq$libresoc.v:139284$7204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136807$6895 + cell $eq $eq$libresoc.v:139285$7205 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285371,10 +291762,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136807$6895_Y + connect \Y $eq$libresoc.v:139285$7205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136808$6896 + cell $eq $eq$libresoc.v:139286$7206 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285382,10 +291773,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136808$6896_Y + connect \Y $eq$libresoc.v:139286$7206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136809$6897 + cell $eq $eq$libresoc.v:139287$7207 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285393,10 +291784,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136809$6897_Y + connect \Y $eq$libresoc.v:139287$7207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136810$6898 + cell $eq $eq$libresoc.v:139288$7208 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285404,10 +291795,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136810$6898_Y + connect \Y $eq$libresoc.v:139288$7208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:136811$6899 + cell $eq $eq$libresoc.v:139289$7209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285415,10 +291806,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:136811$6899_Y + connect \Y $eq$libresoc.v:139289$7209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136827$6920 + cell $eq $eq$libresoc.v:139305$7230 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285426,10 +291817,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136827$6920_Y + connect \Y $eq$libresoc.v:139305$7230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136828$6921 + cell $eq $eq$libresoc.v:139306$7231 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285437,10 +291828,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136828$6921_Y + connect \Y $eq$libresoc.v:139306$7231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136829$6922 + cell $eq $eq$libresoc.v:139307$7232 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285448,10 +291839,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136829$6922_Y + connect \Y $eq$libresoc.v:139307$7232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136830$6923 + cell $eq $eq$libresoc.v:139308$7233 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285459,10 +291850,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136830$6923_Y + connect \Y $eq$libresoc.v:139308$7233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136831$6924 + cell $eq $eq$libresoc.v:139309$7234 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285470,10 +291861,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136831$6924_Y + connect \Y $eq$libresoc.v:139309$7234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136832$6925 + cell $eq $eq$libresoc.v:139310$7235 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285481,10 +291872,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136832$6925_Y + connect \Y $eq$libresoc.v:139310$7235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136833$6926 + cell $eq $eq$libresoc.v:139311$7236 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285492,10 +291883,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136833$6926_Y + connect \Y $eq$libresoc.v:139311$7236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136834$6927 + cell $eq $eq$libresoc.v:139312$7237 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285503,10 +291894,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136834$6927_Y + connect \Y $eq$libresoc.v:139312$7237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136835$6928 + cell $eq $eq$libresoc.v:139313$7238 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285514,10 +291905,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136835$6928_Y + connect \Y $eq$libresoc.v:139313$7238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136836$6929 + cell $eq $eq$libresoc.v:139314$7239 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285525,10 +291916,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136836$6929_Y + connect \Y $eq$libresoc.v:139314$7239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136837$6930 + cell $eq $eq$libresoc.v:139315$7240 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285536,10 +291927,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136837$6930_Y + connect \Y $eq$libresoc.v:139315$7240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136838$6931 + cell $eq $eq$libresoc.v:139316$7241 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285547,10 +291938,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136838$6931_Y + connect \Y $eq$libresoc.v:139316$7241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136839$6932 + cell $eq $eq$libresoc.v:139317$7242 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285558,10 +291949,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136839$6932_Y + connect \Y $eq$libresoc.v:139317$7242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136840$6933 + cell $eq $eq$libresoc.v:139318$7243 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285569,10 +291960,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136840$6933_Y + connect \Y $eq$libresoc.v:139318$7243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136841$6934 + cell $eq $eq$libresoc.v:139319$7244 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285580,10 +291971,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136841$6934_Y + connect \Y $eq$libresoc.v:139319$7244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136842$6935 + cell $eq $eq$libresoc.v:139320$7245 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285591,10 +291982,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136842$6935_Y + connect \Y $eq$libresoc.v:139320$7245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136843$6936 + cell $eq $eq$libresoc.v:139321$7246 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285602,10 +291993,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136843$6936_Y + connect \Y $eq$libresoc.v:139321$7246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136844$6937 + cell $eq $eq$libresoc.v:139322$7247 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285613,10 +292004,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136844$6937_Y + connect \Y $eq$libresoc.v:139322$7247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136845$6938 + cell $eq $eq$libresoc.v:139323$7248 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285624,10 +292015,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136845$6938_Y + connect \Y $eq$libresoc.v:139323$7248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136846$6939 + cell $eq $eq$libresoc.v:139324$7249 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285635,10 +292026,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136846$6939_Y + connect \Y $eq$libresoc.v:139324$7249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136847$6940 + cell $eq $eq$libresoc.v:139325$7250 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285646,10 +292037,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136847$6940_Y + connect \Y $eq$libresoc.v:139325$7250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136848$6941 + cell $eq $eq$libresoc.v:139326$7251 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285657,10 +292048,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136848$6941_Y + connect \Y $eq$libresoc.v:139326$7251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136849$6942 + cell $eq $eq$libresoc.v:139327$7252 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285668,10 +292059,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136849$6942_Y + connect \Y $eq$libresoc.v:139327$7252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136850$6943 + cell $eq $eq$libresoc.v:139328$7253 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285679,10 +292070,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136850$6943_Y + connect \Y $eq$libresoc.v:139328$7253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136851$6944 + cell $eq $eq$libresoc.v:139329$7254 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285690,10 +292081,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136851$6944_Y + connect \Y $eq$libresoc.v:139329$7254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136852$6945 + cell $eq $eq$libresoc.v:139330$7255 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285701,10 +292092,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136852$6945_Y + connect \Y $eq$libresoc.v:139330$7255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136853$6946 + cell $eq $eq$libresoc.v:139331$7256 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285712,10 +292103,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136853$6946_Y + connect \Y $eq$libresoc.v:139331$7256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136854$6947 + cell $eq $eq$libresoc.v:139332$7257 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285723,10 +292114,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136854$6947_Y + connect \Y $eq$libresoc.v:139332$7257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136855$6948 + cell $eq $eq$libresoc.v:139333$7258 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285734,10 +292125,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136855$6948_Y + connect \Y $eq$libresoc.v:139333$7258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136856$6949 + cell $eq $eq$libresoc.v:139334$7259 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285745,10 +292136,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136856$6949_Y + connect \Y $eq$libresoc.v:139334$7259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136857$6950 + cell $eq $eq$libresoc.v:139335$7260 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285756,10 +292147,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136857$6950_Y + connect \Y $eq$libresoc.v:139335$7260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136858$6951 + cell $eq $eq$libresoc.v:139336$7261 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285767,10 +292158,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136858$6951_Y + connect \Y $eq$libresoc.v:139336$7261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136859$6952 + cell $eq $eq$libresoc.v:139337$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285778,10 +292169,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136859$6952_Y + connect \Y $eq$libresoc.v:139337$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136860$6953 + cell $eq $eq$libresoc.v:139338$7263 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285789,10 +292180,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136860$6953_Y + connect \Y $eq$libresoc.v:139338$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136861$6954 + cell $eq $eq$libresoc.v:139339$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285800,10 +292191,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136861$6954_Y + connect \Y $eq$libresoc.v:139339$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:136862$6955 + cell $eq $eq$libresoc.v:139340$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -285811,50 +292202,50 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136862$6955_Y + connect \Y $eq$libresoc.v:139340$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:136813$6901 + cell $pos $extend$libresoc.v:139291$7211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:136813$6901_Y + connect \Y $extend$libresoc.v:139291$7211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $extend$libresoc.v:136815$6904 + cell $pos $extend$libresoc.v:139293$7214 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:136815$6904_Y + connect \Y $extend$libresoc.v:139293$7214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:136817$6907 + cell $pos $extend$libresoc.v:139295$7217 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:136817$6907_Y + connect \Y $extend$libresoc.v:139295$7217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:136818$6909 + cell $pos $extend$libresoc.v:139296$7219 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:136818$6909_Y + connect \Y $extend$libresoc.v:139296$7219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:136822$6914 + cell $pos $extend$libresoc.v:139300$7224 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:136822$6914_Y + connect \Y $extend$libresoc.v:139300$7224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:136825$6918 + cell $or $or$libresoc.v:139303$7228 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -285862,66 +292253,66 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:136825$6918_Y + connect \Y $or$libresoc.v:139303$7228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:136813$6902 + cell $pos $pos$libresoc.v:139291$7212 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:136813$6901_Y - connect \Y $pos$libresoc.v:136813$6902_Y + connect \A $extend$libresoc.v:139291$7211_Y + connect \Y $pos$libresoc.v:139291$7212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $pos$libresoc.v:136815$6905 + cell $pos $pos$libresoc.v:139293$7215 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:136815$6904_Y - connect \Y $pos$libresoc.v:136815$6905_Y + connect \A $extend$libresoc.v:139293$7214_Y + connect \Y $pos$libresoc.v:139293$7215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:136817$6908 + cell $pos $pos$libresoc.v:139295$7218 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:136817$6907_Y - connect \Y $pos$libresoc.v:136817$6908_Y + connect \A $extend$libresoc.v:139295$7217_Y + connect \Y $pos$libresoc.v:139295$7218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:136818$6910 + cell $pos $pos$libresoc.v:139296$7220 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:136818$6909_Y - connect \Y $pos$libresoc.v:136818$6910_Y + connect \A $extend$libresoc.v:139296$7219_Y + connect \Y $pos$libresoc.v:139296$7220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:136822$6915 + cell $pos $pos$libresoc.v:139300$7225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:136822$6914_Y - connect \Y $pos$libresoc.v:136822$6915_Y + connect \A $extend$libresoc.v:139300$7224_Y + connect \Y $pos$libresoc.v:139300$7225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:136819$6911 + cell $reduce_xor $reduce_xor$libresoc.v:139297$7221 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:136819$6911_Y + connect \Y $reduce_xor$libresoc.v:139297$7221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:136820$6912 + cell $reduce_xor $reduce_xor$libresoc.v:139298$7222 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:136820$6912_Y + connect \Y $reduce_xor$libresoc.v:139298$7222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:136814$6903 + cell $sub $sub$libresoc.v:139292$7213 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -285929,34 +292320,34 @@ module \main$48 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:136814$6903_Y + connect \Y $sub$libresoc.v:139292$7213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:136816$6906 + cell $mux $ternary$libresoc.v:139294$7216 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:136816$6906_Y + connect \Y $ternary$libresoc.v:139294$7216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:136821$6913 + cell $mux $ternary$libresoc.v:139299$7223 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:136821$6913_Y + connect \Y $ternary$libresoc.v:139299$7223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:136823$6916 + cell $mux $ternary$libresoc.v:139301$7226 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:136823$6916_Y + connect \Y $ternary$libresoc.v:139301$7226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:136812$6900 + cell $xor $xor$libresoc.v:139290$7210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -285964,10 +292355,10 @@ module \main$48 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:136812$6900_Y + connect \Y $xor$libresoc.v:139290$7210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:136826$6919 + cell $xor $xor$libresoc.v:139304$7229 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -285975,47 +292366,47 @@ module \main$48 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:136826$6919_Y + connect \Y $xor$libresoc.v:139304$7229_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:136863.10-136867.4" + attribute \src "libresoc.v:139341.10-139345.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:136868.7-136871.4" + attribute \src "libresoc.v:139346.7-139349.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:136872.12-136876.4" + attribute \src "libresoc.v:139350.12-139354.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:136322.7-136322.20" - process $proc$libresoc.v:136322$6968 + attribute \src "libresoc.v:138800.7-138800.20" + process $proc$libresoc.v:138800$7278 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136877.3-136931.6" - process $proc$libresoc.v:136877$6956 + attribute \src "libresoc.v:139355.3-139409.6" + process $proc$libresoc.v:139355$7266 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:136878.5-136878.29" + attribute \src "libresoc.v:139356.5-139356.29" switch \initial - attribute \src "libresoc.v:136878.9-136878.17" + attribute \src "libresoc.v:139356.9-139356.17" case 1'1 case end @@ -286083,14 +292474,14 @@ module \main$48 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:136932.3-136942.6" - process $proc$libresoc.v:136932$6957 + attribute \src "libresoc.v:139410.3-139420.6" + process $proc$libresoc.v:139410$7267 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:136933.5-136933.29" + attribute \src "libresoc.v:139411.5-139411.29" switch \initial - attribute \src "libresoc.v:136933.9-136933.17" + attribute \src "libresoc.v:139411.9-139411.17" case 1'1 case end @@ -286106,14 +292497,14 @@ module \main$48 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:136943.3-136953.6" - process $proc$libresoc.v:136943$6958 + attribute \src "libresoc.v:139421.3-139431.6" + process $proc$libresoc.v:139421$7268 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:136944.5-136944.29" + attribute \src "libresoc.v:139422.5-139422.29" switch \initial - attribute \src "libresoc.v:136944.9-136944.17" + attribute \src "libresoc.v:139422.9-139422.17" case 1'1 case end @@ -286129,14 +292520,14 @@ module \main$48 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:136954.3-136964.6" - process $proc$libresoc.v:136954$6959 + attribute \src "libresoc.v:139432.3-139442.6" + process $proc$libresoc.v:139432$7269 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:136955.5-136955.29" + attribute \src "libresoc.v:139433.5-139433.29" switch \initial - attribute \src "libresoc.v:136955.9-136955.17" + attribute \src "libresoc.v:139433.9-139433.17" case 1'1 case end @@ -286152,14 +292543,14 @@ module \main$48 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:136965.3-136975.6" - process $proc$libresoc.v:136965$6960 + attribute \src "libresoc.v:139443.3-139453.6" + process $proc$libresoc.v:139443$7270 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:136966.5-136966.29" + attribute \src "libresoc.v:139444.5-139444.29" switch \initial - attribute \src "libresoc.v:136966.9-136966.17" + attribute \src "libresoc.v:139444.9-139444.17" case 1'1 case end @@ -286175,14 +292566,14 @@ module \main$48 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:136976.3-136986.6" - process $proc$libresoc.v:136976$6961 + attribute \src "libresoc.v:139454.3-139464.6" + process $proc$libresoc.v:139454$7271 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:136977.5-136977.29" + attribute \src "libresoc.v:139455.5-139455.29" switch \initial - attribute \src "libresoc.v:136977.9-136977.17" + attribute \src "libresoc.v:139455.9-139455.17" case 1'1 case end @@ -286198,14 +292589,14 @@ module \main$48 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:136987.3-136997.6" - process $proc$libresoc.v:136987$6962 + attribute \src "libresoc.v:139465.3-139475.6" + process $proc$libresoc.v:139465$7272 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:136988.5-136988.29" + attribute \src "libresoc.v:139466.5-139466.29" switch \initial - attribute \src "libresoc.v:136988.9-136988.17" + attribute \src "libresoc.v:139466.9-139466.17" case 1'1 case end @@ -286221,14 +292612,14 @@ module \main$48 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:136998.3-137008.6" - process $proc$libresoc.v:136998$6963 + attribute \src "libresoc.v:139476.3-139486.6" + process $proc$libresoc.v:139476$7273 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:136999.5-136999.29" + attribute \src "libresoc.v:139477.5-139477.29" switch \initial - attribute \src "libresoc.v:136999.9-136999.17" + attribute \src "libresoc.v:139477.9-139477.17" case 1'1 case end @@ -286244,14 +292635,14 @@ module \main$48 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:137009.3-137019.6" - process $proc$libresoc.v:137009$6964 + attribute \src "libresoc.v:139487.3-139497.6" + process $proc$libresoc.v:139487$7274 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:137010.5-137010.29" + attribute \src "libresoc.v:139488.5-139488.29" switch \initial - attribute \src "libresoc.v:137010.9-137010.17" + attribute \src "libresoc.v:139488.9-139488.17" case 1'1 case end @@ -286267,14 +292658,14 @@ module \main$48 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:137020.3-137030.6" - process $proc$libresoc.v:137020$6965 + attribute \src "libresoc.v:139498.3-139508.6" + process $proc$libresoc.v:139498$7275 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:137021.5-137021.29" + attribute \src "libresoc.v:139499.5-139499.29" switch \initial - attribute \src "libresoc.v:137021.9-137021.17" + attribute \src "libresoc.v:139499.9-139499.17" case 1'1 case end @@ -286290,14 +292681,14 @@ module \main$48 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:137031.3-137041.6" - process $proc$libresoc.v:137031$6966 + attribute \src "libresoc.v:139509.3-139519.6" + process $proc$libresoc.v:139509$7276 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:137032.5-137032.29" + attribute \src "libresoc.v:139510.5-139510.29" switch \initial - attribute \src "libresoc.v:137032.9-137032.17" + attribute \src "libresoc.v:139510.9-139510.17" case 1'1 case end @@ -286313,14 +292704,14 @@ module \main$48 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:137042.3-137060.6" - process $proc$libresoc.v:137042$6967 + attribute \src "libresoc.v:139520.3-139538.6" + process $proc$libresoc.v:139520$7277 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:137043.5-137043.29" + attribute \src "libresoc.v:139521.5-139521.29" switch \initial - attribute \src "libresoc.v:137043.9-137043.17" + attribute \src "libresoc.v:139521.9-139521.17" case 1'1 case end @@ -286347,193 +292738,193 @@ module \main$48 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:136783$6871_Y - connect \$101 $eq$libresoc.v:136784$6872_Y - connect \$103 $eq$libresoc.v:136785$6873_Y - connect \$105 $eq$libresoc.v:136786$6874_Y - connect \$107 $eq$libresoc.v:136787$6875_Y - connect \$109 $eq$libresoc.v:136788$6876_Y - connect \$111 $eq$libresoc.v:136789$6877_Y - connect \$113 $eq$libresoc.v:136790$6878_Y - connect \$115 $eq$libresoc.v:136791$6879_Y - connect \$117 $eq$libresoc.v:136792$6880_Y - connect \$119 $eq$libresoc.v:136793$6881_Y - connect \$121 $eq$libresoc.v:136794$6882_Y - connect \$123 $eq$libresoc.v:136795$6883_Y - connect \$125 $eq$libresoc.v:136796$6884_Y - connect \$127 $eq$libresoc.v:136797$6885_Y - connect \$129 $eq$libresoc.v:136798$6886_Y - connect \$131 $eq$libresoc.v:136799$6887_Y - connect \$133 $eq$libresoc.v:136800$6888_Y - connect \$135 $eq$libresoc.v:136801$6889_Y - connect \$137 $eq$libresoc.v:136802$6890_Y - connect \$139 $eq$libresoc.v:136803$6891_Y - connect \$141 $eq$libresoc.v:136804$6892_Y - connect \$143 $eq$libresoc.v:136805$6893_Y - connect \$145 $eq$libresoc.v:136806$6894_Y - connect \$147 $eq$libresoc.v:136807$6895_Y - connect \$149 $eq$libresoc.v:136808$6896_Y - connect \$151 $eq$libresoc.v:136809$6897_Y - connect \$153 $eq$libresoc.v:136810$6898_Y - connect \$155 $eq$libresoc.v:136811$6899_Y - connect \$158 $xor$libresoc.v:136812$6900_Y - connect \$157 $pos$libresoc.v:136813$6902_Y - connect \$162 $sub$libresoc.v:136814$6903_Y - connect \$164 $pos$libresoc.v:136815$6905_Y - connect \$166 $ternary$libresoc.v:136816$6906_Y - connect \$161 $pos$libresoc.v:136817$6908_Y - connect \$169 $pos$libresoc.v:136818$6910_Y - connect \$171 $reduce_xor$libresoc.v:136819$6911_Y - connect \$173 $reduce_xor$libresoc.v:136820$6912_Y - connect \$176 $ternary$libresoc.v:136821$6913_Y - connect \$175 $pos$libresoc.v:136822$6915_Y - connect \$179 $ternary$libresoc.v:136823$6916_Y - connect \$21 $and$libresoc.v:136824$6917_Y - connect \$23 $or$libresoc.v:136825$6918_Y - connect \$25 $xor$libresoc.v:136826$6919_Y - connect \$27 $eq$libresoc.v:136827$6920_Y - connect \$29 $eq$libresoc.v:136828$6921_Y - connect \$31 $eq$libresoc.v:136829$6922_Y - connect \$33 $eq$libresoc.v:136830$6923_Y - connect \$35 $eq$libresoc.v:136831$6924_Y - connect \$37 $eq$libresoc.v:136832$6925_Y - connect \$39 $eq$libresoc.v:136833$6926_Y - connect \$41 $eq$libresoc.v:136834$6927_Y - connect \$43 $eq$libresoc.v:136835$6928_Y - connect \$45 $eq$libresoc.v:136836$6929_Y - connect \$47 $eq$libresoc.v:136837$6930_Y - connect \$49 $eq$libresoc.v:136838$6931_Y - connect \$51 $eq$libresoc.v:136839$6932_Y - connect \$53 $eq$libresoc.v:136840$6933_Y - connect \$55 $eq$libresoc.v:136841$6934_Y - connect \$57 $eq$libresoc.v:136842$6935_Y - connect \$59 $eq$libresoc.v:136843$6936_Y - connect \$61 $eq$libresoc.v:136844$6937_Y - connect \$63 $eq$libresoc.v:136845$6938_Y - connect \$65 $eq$libresoc.v:136846$6939_Y - connect \$67 $eq$libresoc.v:136847$6940_Y - connect \$69 $eq$libresoc.v:136848$6941_Y - connect \$71 $eq$libresoc.v:136849$6942_Y - connect \$73 $eq$libresoc.v:136850$6943_Y - connect \$75 $eq$libresoc.v:136851$6944_Y - connect \$77 $eq$libresoc.v:136852$6945_Y - connect \$79 $eq$libresoc.v:136853$6946_Y - connect \$81 $eq$libresoc.v:136854$6947_Y - connect \$83 $eq$libresoc.v:136855$6948_Y - connect \$85 $eq$libresoc.v:136856$6949_Y - connect \$87 $eq$libresoc.v:136857$6950_Y - connect \$89 $eq$libresoc.v:136858$6951_Y - connect \$91 $eq$libresoc.v:136859$6952_Y - connect \$93 $eq$libresoc.v:136860$6953_Y - connect \$95 $eq$libresoc.v:136861$6954_Y - connect \$97 $eq$libresoc.v:136862$6955_Y + connect \$99 $eq$libresoc.v:139261$7181_Y + connect \$101 $eq$libresoc.v:139262$7182_Y + connect \$103 $eq$libresoc.v:139263$7183_Y + connect \$105 $eq$libresoc.v:139264$7184_Y + connect \$107 $eq$libresoc.v:139265$7185_Y + connect \$109 $eq$libresoc.v:139266$7186_Y + connect \$111 $eq$libresoc.v:139267$7187_Y + connect \$113 $eq$libresoc.v:139268$7188_Y + connect \$115 $eq$libresoc.v:139269$7189_Y + connect \$117 $eq$libresoc.v:139270$7190_Y + connect \$119 $eq$libresoc.v:139271$7191_Y + connect \$121 $eq$libresoc.v:139272$7192_Y + connect \$123 $eq$libresoc.v:139273$7193_Y + connect \$125 $eq$libresoc.v:139274$7194_Y + connect \$127 $eq$libresoc.v:139275$7195_Y + connect \$129 $eq$libresoc.v:139276$7196_Y + connect \$131 $eq$libresoc.v:139277$7197_Y + connect \$133 $eq$libresoc.v:139278$7198_Y + connect \$135 $eq$libresoc.v:139279$7199_Y + connect \$137 $eq$libresoc.v:139280$7200_Y + connect \$139 $eq$libresoc.v:139281$7201_Y + connect \$141 $eq$libresoc.v:139282$7202_Y + connect \$143 $eq$libresoc.v:139283$7203_Y + connect \$145 $eq$libresoc.v:139284$7204_Y + connect \$147 $eq$libresoc.v:139285$7205_Y + connect \$149 $eq$libresoc.v:139286$7206_Y + connect \$151 $eq$libresoc.v:139287$7207_Y + connect \$153 $eq$libresoc.v:139288$7208_Y + connect \$155 $eq$libresoc.v:139289$7209_Y + connect \$158 $xor$libresoc.v:139290$7210_Y + connect \$157 $pos$libresoc.v:139291$7212_Y + connect \$162 $sub$libresoc.v:139292$7213_Y + connect \$164 $pos$libresoc.v:139293$7215_Y + connect \$166 $ternary$libresoc.v:139294$7216_Y + connect \$161 $pos$libresoc.v:139295$7218_Y + connect \$169 $pos$libresoc.v:139296$7220_Y + connect \$171 $reduce_xor$libresoc.v:139297$7221_Y + connect \$173 $reduce_xor$libresoc.v:139298$7222_Y + connect \$176 $ternary$libresoc.v:139299$7223_Y + connect \$175 $pos$libresoc.v:139300$7225_Y + connect \$179 $ternary$libresoc.v:139301$7226_Y + connect \$21 $and$libresoc.v:139302$7227_Y + connect \$23 $or$libresoc.v:139303$7228_Y + connect \$25 $xor$libresoc.v:139304$7229_Y + connect \$27 $eq$libresoc.v:139305$7230_Y + connect \$29 $eq$libresoc.v:139306$7231_Y + connect \$31 $eq$libresoc.v:139307$7232_Y + connect \$33 $eq$libresoc.v:139308$7233_Y + connect \$35 $eq$libresoc.v:139309$7234_Y + connect \$37 $eq$libresoc.v:139310$7235_Y + connect \$39 $eq$libresoc.v:139311$7236_Y + connect \$41 $eq$libresoc.v:139312$7237_Y + connect \$43 $eq$libresoc.v:139313$7238_Y + connect \$45 $eq$libresoc.v:139314$7239_Y + connect \$47 $eq$libresoc.v:139315$7240_Y + connect \$49 $eq$libresoc.v:139316$7241_Y + connect \$51 $eq$libresoc.v:139317$7242_Y + connect \$53 $eq$libresoc.v:139318$7243_Y + connect \$55 $eq$libresoc.v:139319$7244_Y + connect \$57 $eq$libresoc.v:139320$7245_Y + connect \$59 $eq$libresoc.v:139321$7246_Y + connect \$61 $eq$libresoc.v:139322$7247_Y + connect \$63 $eq$libresoc.v:139323$7248_Y + connect \$65 $eq$libresoc.v:139324$7249_Y + connect \$67 $eq$libresoc.v:139325$7250_Y + connect \$69 $eq$libresoc.v:139326$7251_Y + connect \$71 $eq$libresoc.v:139327$7252_Y + connect \$73 $eq$libresoc.v:139328$7253_Y + connect \$75 $eq$libresoc.v:139329$7254_Y + connect \$77 $eq$libresoc.v:139330$7255_Y + connect \$79 $eq$libresoc.v:139331$7256_Y + connect \$81 $eq$libresoc.v:139332$7257_Y + connect \$83 $eq$libresoc.v:139333$7258_Y + connect \$85 $eq$libresoc.v:139334$7259_Y + connect \$87 $eq$libresoc.v:139335$7260_Y + connect \$89 $eq$libresoc.v:139336$7261_Y + connect \$91 $eq$libresoc.v:139337$7262_Y + connect \$93 $eq$libresoc.v:139338$7263_Y + connect \$95 $eq$libresoc.v:139339$7264_Y + connect \$97 $eq$libresoc.v:139340$7265_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:137068.1-137577.10" +attribute \src "libresoc.v:139546.1-140055.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:137432.3-137442.6" + attribute \src "libresoc.v:139910.3-139920.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:137486.3-137496.6" + attribute \src "libresoc.v:139964.3-139974.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:137497.3-137507.6" + attribute \src "libresoc.v:139975.3-139985.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:137508.3-137528.6" + attribute \src "libresoc.v:139986.3-140006.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:137529.3-137549.6" + attribute \src "libresoc.v:140007.3-140027.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:137550.3-137560.6" + attribute \src "libresoc.v:140028.3-140038.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:137475.3-137485.6" + attribute \src "libresoc.v:139953.3-139963.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:137344.3-137378.6" - wire width 4 $0\cr_a$6[3:0]$6983 - attribute \src "libresoc.v:137344.3-137378.6" + attribute \src "libresoc.v:139822.3-139856.6" + wire width 4 $0\cr_a$6[3:0]$7293 + attribute \src "libresoc.v:139822.3-139856.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:137443.3-137463.6" + attribute \src "libresoc.v:139921.3-139941.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:137561.3-137571.6" - wire width 32 $0\full_cr$5[31:0]$6998 - attribute \src "libresoc.v:137379.3-137389.6" + attribute \src "libresoc.v:140039.3-140049.6" + wire width 32 $0\full_cr$5[31:0]$7308 + attribute \src "libresoc.v:139857.3-139867.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:137069.7-137069.20" + attribute \src "libresoc.v:139547.7-139547.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137464.3-137474.6" + attribute \src "libresoc.v:139942.3-139952.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:137390.3-137431.6" + attribute \src "libresoc.v:139868.3-139909.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:137390.3-137431.6" + attribute \src "libresoc.v:139868.3-139909.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:137432.3-137442.6" + attribute \src "libresoc.v:139910.3-139920.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:137486.3-137496.6" + attribute \src "libresoc.v:139964.3-139974.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:137497.3-137507.6" + attribute \src "libresoc.v:139975.3-139985.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:137508.3-137528.6" + attribute \src "libresoc.v:139986.3-140006.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:137529.3-137549.6" + attribute \src "libresoc.v:140007.3-140027.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:137550.3-137560.6" + attribute \src "libresoc.v:140028.3-140038.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:137475.3-137485.6" + attribute \src "libresoc.v:139953.3-139963.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:137344.3-137378.6" - wire width 4 $1\cr_a$6[3:0]$6984 - attribute \src "libresoc.v:137344.3-137378.6" + attribute \src "libresoc.v:139822.3-139856.6" + wire width 4 $1\cr_a$6[3:0]$7294 + attribute \src "libresoc.v:139822.3-139856.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:137443.3-137463.6" + attribute \src "libresoc.v:139921.3-139941.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:137561.3-137571.6" - wire width 32 $1\full_cr$5[31:0]$6999 - attribute \src "libresoc.v:137379.3-137389.6" + attribute \src "libresoc.v:140039.3-140049.6" + wire width 32 $1\full_cr$5[31:0]$7309 + attribute \src "libresoc.v:139857.3-139867.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:137464.3-137474.6" + attribute \src "libresoc.v:139942.3-139952.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:137390.3-137431.6" + attribute \src "libresoc.v:139868.3-139909.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:137390.3-137431.6" + attribute \src "libresoc.v:139868.3-139909.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:137508.3-137528.6" + attribute \src "libresoc.v:139986.3-140006.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:137529.3-137549.6" + attribute \src "libresoc.v:140007.3-140027.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:137344.3-137378.6" - wire width 4 $2\cr_a$6[3:0]$6985 - attribute \src "libresoc.v:137443.3-137463.6" + attribute \src "libresoc.v:139822.3-139856.6" + wire width 4 $2\cr_a$6[3:0]$7295 + attribute \src "libresoc.v:139921.3-139941.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:137390.3-137431.6" + attribute \src "libresoc.v:139868.3-139909.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:137340.18-137340.96" - wire width 64 $extend$libresoc.v:137340$6975_Y - attribute \src "libresoc.v:137342.18-137342.98" - wire width 65 $extend$libresoc.v:137342$6978_Y - attribute \src "libresoc.v:137343.17-137343.92" - wire width 5 $extend$libresoc.v:137343$6980_Y - attribute \src "libresoc.v:137340.18-137340.96" - wire width 64 $pos$libresoc.v:137340$6976_Y - attribute \src "libresoc.v:137342.18-137342.98" - wire width 65 $pos$libresoc.v:137342$6979_Y - attribute \src "libresoc.v:137343.17-137343.92" - wire width 5 $pos$libresoc.v:137343$6981_Y - attribute \src "libresoc.v:137334.18-137334.116" - wire width 3 $sub$libresoc.v:137334$6969_Y - attribute \src "libresoc.v:137335.18-137335.116" - wire width 3 $sub$libresoc.v:137335$6970_Y - attribute \src "libresoc.v:137336.18-137336.116" - wire width 3 $sub$libresoc.v:137336$6971_Y - attribute \src "libresoc.v:137337.18-137337.114" - wire $ternary$libresoc.v:137337$6972_Y - attribute \src "libresoc.v:137338.18-137338.115" - wire $ternary$libresoc.v:137338$6973_Y - attribute \src "libresoc.v:137339.18-137339.112" - wire $ternary$libresoc.v:137339$6974_Y - attribute \src "libresoc.v:137341.18-137341.108" - wire width 64 $ternary$libresoc.v:137341$6977_Y + attribute \src "libresoc.v:139818.18-139818.96" + wire width 64 $extend$libresoc.v:139818$7285_Y + attribute \src "libresoc.v:139820.18-139820.98" + wire width 65 $extend$libresoc.v:139820$7288_Y + attribute \src "libresoc.v:139821.17-139821.92" + wire width 5 $extend$libresoc.v:139821$7290_Y + attribute \src "libresoc.v:139818.18-139818.96" + wire width 64 $pos$libresoc.v:139818$7286_Y + attribute \src "libresoc.v:139820.18-139820.98" + wire width 65 $pos$libresoc.v:139820$7289_Y + attribute \src "libresoc.v:139821.17-139821.92" + wire width 5 $pos$libresoc.v:139821$7291_Y + attribute \src "libresoc.v:139812.18-139812.116" + wire width 3 $sub$libresoc.v:139812$7279_Y + attribute \src "libresoc.v:139813.18-139813.116" + wire width 3 $sub$libresoc.v:139813$7280_Y + attribute \src "libresoc.v:139814.18-139814.116" + wire width 3 $sub$libresoc.v:139814$7281_Y + attribute \src "libresoc.v:139815.18-139815.114" + wire $ternary$libresoc.v:139815$7282_Y + attribute \src "libresoc.v:139816.18-139816.115" + wire $ternary$libresoc.v:139816$7283_Y + attribute \src "libresoc.v:139817.18-139817.112" + wire $ternary$libresoc.v:139817$7284_Y + attribute \src "libresoc.v:139819.18-139819.108" + wire width 64 $ternary$libresoc.v:139819$7287_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -286576,9 +292967,9 @@ module \main$9 wire width 2 \bt attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 7 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 18 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 8 \cr_b @@ -286774,11 +293165,11 @@ module \main$9 wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 6 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 output 16 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:137069.7-137069.15" + attribute \src "libresoc.v:139547.7-139547.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -286786,64 +293177,64 @@ module \main$9 wire width 2 input 20 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 10 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 4 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:137340$6975 + cell $pos $extend$libresoc.v:139818$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:137340$6975_Y + connect \Y $extend$libresoc.v:139818$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:137342$6978 + cell $pos $extend$libresoc.v:139820$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:137342$6978_Y + connect \Y $extend$libresoc.v:139820$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:137343$6980 + cell $pos $extend$libresoc.v:139821$7290 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:137343$6980_Y + connect \Y $extend$libresoc.v:139821$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:137340$6976 + cell $pos $pos$libresoc.v:139818$7286 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:137340$6975_Y - connect \Y $pos$libresoc.v:137340$6976_Y + connect \A $extend$libresoc.v:139818$7285_Y + connect \Y $pos$libresoc.v:139818$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:137342$6979 + cell $pos $pos$libresoc.v:139820$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:137342$6978_Y - connect \Y $pos$libresoc.v:137342$6979_Y + connect \A $extend$libresoc.v:139820$7288_Y + connect \Y $pos$libresoc.v:139820$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:137343$6981 + cell $pos $pos$libresoc.v:139821$7291 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:137343$6980_Y - connect \Y $pos$libresoc.v:137343$6981_Y + connect \A $extend$libresoc.v:139821$7290_Y + connect \Y $pos$libresoc.v:139821$7291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:137334$6969 + cell $sub $sub$libresoc.v:139812$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -286851,10 +293242,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:137334$6969_Y + connect \Y $sub$libresoc.v:139812$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:137335$6970 + cell $sub $sub$libresoc.v:139813$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -286862,10 +293253,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:137335$6970_Y + connect \Y $sub$libresoc.v:139813$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:137336$6971 + cell $sub $sub$libresoc.v:139814$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -286873,59 +293264,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:137336$6971_Y + connect \Y $sub$libresoc.v:139814$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:137337$6972 + cell $mux $ternary$libresoc.v:139815$7282 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:137337$6972_Y + connect \Y $ternary$libresoc.v:139815$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:137338$6973 + cell $mux $ternary$libresoc.v:139816$7283 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:137338$6973_Y + connect \Y $ternary$libresoc.v:139816$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:137339$6974 + cell $mux $ternary$libresoc.v:139817$7284 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:137339$6974_Y + connect \Y $ternary$libresoc.v:139817$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:137341$6977 + cell $mux $ternary$libresoc.v:139819$7287 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:137341$6977_Y + connect \Y $ternary$libresoc.v:139819$7287_Y end - attribute \src "libresoc.v:137069.7-137069.20" - process $proc$libresoc.v:137069$7000 + attribute \src "libresoc.v:139547.7-139547.20" + process $proc$libresoc.v:139547$7310 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137344.3-137378.6" - process $proc$libresoc.v:137344$6982 + attribute \src "libresoc.v:139822.3-139856.6" + process $proc$libresoc.v:139822$7292 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$6983 $1\cr_a$6[3:0]$6984 - attribute \src "libresoc.v:137345.5-137345.29" + assign $0\cr_a$6[3:0]$7293 $1\cr_a$6[3:0]$7294 + attribute \src "libresoc.v:139823.5-139823.29" switch \initial - attribute \src "libresoc.v:137345.9-137345.17" + attribute \src "libresoc.v:139823.9-139823.17" case 1'1 case end @@ -286935,52 +293326,52 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$6984 \$7 [3:0] + assign $1\cr_a$6[3:0]$7294 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$6984 $2\cr_a$6[3:0]$6985 + assign $1\cr_a$6[3:0]$7294 $2\cr_a$6[3:0]$7295 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$6985 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$6985 [0] \bit_o + assign $2\cr_a$6[3:0]$7295 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7295 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$6985 [3:2] $2\cr_a$6[3:0]$6985 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$6985 [1] \bit_o + assign { $2\cr_a$6[3:0]$7295 [3:2] $2\cr_a$6[3:0]$7295 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7295 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$6985 [3] $2\cr_a$6[3:0]$6985 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$6985 [2] \bit_o + assign { $2\cr_a$6[3:0]$7295 [3] $2\cr_a$6[3:0]$7295 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7295 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$6985 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$6985 [3] \bit_o + assign $2\cr_a$6[3:0]$7295 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7295 [3] \bit_o case - assign $2\cr_a$6[3:0]$6985 \cr_c + assign $2\cr_a$6[3:0]$7295 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$6984 4'0000 + assign $1\cr_a$6[3:0]$7294 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$6983 + update \cr_a$6 $0\cr_a$6[3:0]$7293 end - attribute \src "libresoc.v:137379.3-137389.6" - process $proc$libresoc.v:137379$6986 + attribute \src "libresoc.v:139857.3-139867.6" + process $proc$libresoc.v:139857$7296 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:137380.5-137380.29" + attribute \src "libresoc.v:139858.5-139858.29" switch \initial - attribute \src "libresoc.v:137380.9-137380.17" + attribute \src "libresoc.v:139858.9-139858.17" case 1'1 case end @@ -286996,17 +293387,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:137390.3-137431.6" - process $proc$libresoc.v:137390$6987 + attribute \src "libresoc.v:139868.3-139909.6" + process $proc$libresoc.v:139868$7297 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:137391.5-137391.29" + attribute \src "libresoc.v:139869.5-139869.29" switch \initial - attribute \src "libresoc.v:137391.9-137391.17" + attribute \src "libresoc.v:139869.9-139869.17" case 1'1 case end @@ -287053,14 +293444,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:137432.3-137442.6" - process $proc$libresoc.v:137432$6988 + attribute \src "libresoc.v:139910.3-139920.6" + process $proc$libresoc.v:139910$7298 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:137433.5-137433.29" + attribute \src "libresoc.v:139911.5-139911.29" switch \initial - attribute \src "libresoc.v:137433.9-137433.17" + attribute \src "libresoc.v:139911.9-139911.17" case 1'1 case end @@ -287076,14 +293467,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:137443.3-137463.6" - process $proc$libresoc.v:137443$6989 + attribute \src "libresoc.v:139921.3-139941.6" + process $proc$libresoc.v:139921$7299 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:137444.5-137444.29" + attribute \src "libresoc.v:139922.5-139922.29" switch \initial - attribute \src "libresoc.v:137444.9-137444.17" + attribute \src "libresoc.v:139922.9-139922.17" case 1'1 case end @@ -287120,14 +293511,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:137464.3-137474.6" - process $proc$libresoc.v:137464$6990 + attribute \src "libresoc.v:139942.3-139952.6" + process $proc$libresoc.v:139942$7300 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:137465.5-137465.29" + attribute \src "libresoc.v:139943.5-139943.29" switch \initial - attribute \src "libresoc.v:137465.9-137465.17" + attribute \src "libresoc.v:139943.9-139943.17" case 1'1 case end @@ -287143,14 +293534,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:137475.3-137485.6" - process $proc$libresoc.v:137475$6991 + attribute \src "libresoc.v:139953.3-139963.6" + process $proc$libresoc.v:139953$7301 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:137476.5-137476.29" + attribute \src "libresoc.v:139954.5-139954.29" switch \initial - attribute \src "libresoc.v:137476.9-137476.17" + attribute \src "libresoc.v:139954.9-139954.17" case 1'1 case end @@ -287166,14 +293557,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:137486.3-137496.6" - process $proc$libresoc.v:137486$6992 + attribute \src "libresoc.v:139964.3-139974.6" + process $proc$libresoc.v:139964$7302 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:137487.5-137487.29" + attribute \src "libresoc.v:139965.5-139965.29" switch \initial - attribute \src "libresoc.v:137487.9-137487.17" + attribute \src "libresoc.v:139965.9-139965.17" case 1'1 case end @@ -287189,14 +293580,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:137497.3-137507.6" - process $proc$libresoc.v:137497$6993 + attribute \src "libresoc.v:139975.3-139985.6" + process $proc$libresoc.v:139975$7303 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:137498.5-137498.29" + attribute \src "libresoc.v:139976.5-139976.29" switch \initial - attribute \src "libresoc.v:137498.9-137498.17" + attribute \src "libresoc.v:139976.9-139976.17" case 1'1 case end @@ -287212,14 +293603,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:137508.3-137528.6" - process $proc$libresoc.v:137508$6994 + attribute \src "libresoc.v:139986.3-140006.6" + process $proc$libresoc.v:139986$7304 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:137509.5-137509.29" + attribute \src "libresoc.v:139987.5-139987.29" switch \initial - attribute \src "libresoc.v:137509.9-137509.17" + attribute \src "libresoc.v:139987.9-139987.17" case 1'1 case end @@ -287256,14 +293647,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:137529.3-137549.6" - process $proc$libresoc.v:137529$6995 + attribute \src "libresoc.v:140007.3-140027.6" + process $proc$libresoc.v:140007$7305 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:137530.5-137530.29" + attribute \src "libresoc.v:140008.5-140008.29" switch \initial - attribute \src "libresoc.v:137530.9-137530.17" + attribute \src "libresoc.v:140008.9-140008.17" case 1'1 case end @@ -287300,14 +293691,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:137550.3-137560.6" - process $proc$libresoc.v:137550$6996 + attribute \src "libresoc.v:140028.3-140038.6" + process $proc$libresoc.v:140028$7306 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:137551.5-137551.29" + attribute \src "libresoc.v:140029.5-140029.29" switch \initial - attribute \src "libresoc.v:137551.9-137551.17" + attribute \src "libresoc.v:140029.9-140029.17" case 1'1 case end @@ -287323,14 +293714,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:137561.3-137571.6" - process $proc$libresoc.v:137561$6997 + attribute \src "libresoc.v:140039.3-140049.6" + process $proc$libresoc.v:140039$7307 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$6998 $1\full_cr$5[31:0]$6999 - attribute \src "libresoc.v:137562.5-137562.29" + assign $0\full_cr$5[31:0]$7308 $1\full_cr$5[31:0]$7309 + attribute \src "libresoc.v:140040.5-140040.29" switch \initial - attribute \src "libresoc.v:137562.9-137562.17" + attribute \src "libresoc.v:140040.9-140040.17" case 1'1 case end @@ -287339,508 +293730,508 @@ module \main$9 attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$6999 \ra [31:0] + assign $1\full_cr$5[31:0]$7309 \ra [31:0] case - assign $1\full_cr$5[31:0]$6999 0 + assign $1\full_cr$5[31:0]$7309 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$6998 + update \full_cr$5 $0\full_cr$5[31:0]$7308 end - connect \$10 $sub$libresoc.v:137334$6969_Y - connect \$13 $sub$libresoc.v:137335$6970_Y - connect \$16 $sub$libresoc.v:137336$6971_Y - connect \$18 $ternary$libresoc.v:137337$6972_Y - connect \$20 $ternary$libresoc.v:137338$6973_Y - connect \$22 $ternary$libresoc.v:137339$6974_Y - connect \$24 $pos$libresoc.v:137340$6976_Y - connect \$27 $ternary$libresoc.v:137341$6977_Y - connect \$26 $pos$libresoc.v:137342$6979_Y - connect \$7 $pos$libresoc.v:137343$6981_Y + connect \$10 $sub$libresoc.v:139812$7279_Y + connect \$13 $sub$libresoc.v:139813$7280_Y + connect \$16 $sub$libresoc.v:139814$7281_Y + connect \$18 $ternary$libresoc.v:139815$7282_Y + connect \$20 $ternary$libresoc.v:139816$7283_Y + connect \$22 $ternary$libresoc.v:139817$7284_Y + connect \$24 $pos$libresoc.v:139818$7286_Y + connect \$27 $ternary$libresoc.v:139819$7287_Y + connect \$26 $pos$libresoc.v:139820$7289_Y + connect \$7 $pos$libresoc.v:139821$7291_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:137581.1-138736.10" +attribute \src "libresoc.v:140059.1-141214.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:138307.3-138308.25" + attribute \src "libresoc.v:140785.3-140786.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:138305.3-138306.40" + attribute \src "libresoc.v:140783.3-140784.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:138648.3-138656.6" - wire $0\alu_l_r_alu$next[0:0]$7206 - attribute \src "libresoc.v:138233.3-138234.39" + attribute \src "libresoc.v:141126.3-141134.6" + wire $0\alu_l_r_alu$next[0:0]$7516 + attribute \src "libresoc.v:140711.3-140712.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 - attribute \src "libresoc.v:138261.3-138262.65" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 + attribute \src "libresoc.v:140739.3-140740.65" wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 - attribute \src "libresoc.v:138263.3-138264.79" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 + attribute \src "libresoc.v:140741.3-140742.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 - attribute \src "libresoc.v:138265.3-138266.75" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 + attribute \src "libresoc.v:140743.3-140744.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7134 - attribute \src "libresoc.v:138281.3-138282.59" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7444 + attribute \src "libresoc.v:140759.3-140760.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 - attribute \src "libresoc.v:138259.3-138260.69" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 + attribute \src "libresoc.v:140737.3-140738.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 - attribute \src "libresoc.v:138277.3-138278.67" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 + attribute \src "libresoc.v:140755.3-140756.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 - attribute \src "libresoc.v:138279.3-138280.69" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 + attribute \src "libresoc.v:140757.3-140758.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 - attribute \src "libresoc.v:138271.3-138272.63" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 + attribute \src "libresoc.v:140749.3-140750.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 - attribute \src "libresoc.v:138273.3-138274.63" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 + attribute \src "libresoc.v:140751.3-140752.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 - attribute \src "libresoc.v:138269.3-138270.63" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 + attribute \src "libresoc.v:140747.3-140748.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 - attribute \src "libresoc.v:138267.3-138268.63" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 + attribute \src "libresoc.v:140745.3-140746.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 - attribute \src "libresoc.v:138275.3-138276.69" + attribute \src "libresoc.v:140966.3-140998.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 + attribute \src "libresoc.v:140753.3-140754.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:138639.3-138647.6" - wire $0\alui_l_r_alui$next[0:0]$7203 - attribute \src "libresoc.v:138235.3-138236.43" + attribute \src "libresoc.v:141117.3-141125.6" + wire $0\alui_l_r_alui$next[0:0]$7513 + attribute \src "libresoc.v:140713.3-140714.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:138521.3-138542.6" - wire width 64 $0\data_r0__o$next[63:0]$7162 - attribute \src "libresoc.v:138255.3-138256.37" + attribute \src "libresoc.v:140999.3-141020.6" + wire width 64 $0\data_r0__o$next[63:0]$7472 + attribute \src "libresoc.v:140733.3-140734.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:138521.3-138542.6" - wire $0\data_r0__o_ok$next[0:0]$7163 - attribute \src "libresoc.v:138257.3-138258.43" + attribute \src "libresoc.v:140999.3-141020.6" + wire $0\data_r0__o_ok$next[0:0]$7473 + attribute \src "libresoc.v:140735.3-140736.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:138543.3-138564.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7170 - attribute \src "libresoc.v:138251.3-138252.43" + attribute \src "libresoc.v:141021.3-141042.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7480 + attribute \src "libresoc.v:140729.3-140730.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:138543.3-138564.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7171 - attribute \src "libresoc.v:138253.3-138254.49" + attribute \src "libresoc.v:141021.3-141042.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7481 + attribute \src "libresoc.v:140731.3-140732.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:138565.3-138586.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7178 - attribute \src "libresoc.v:138247.3-138248.47" + attribute \src "libresoc.v:141043.3-141064.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7488 + attribute \src "libresoc.v:140725.3-140726.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:138565.3-138586.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7179 - attribute \src "libresoc.v:138249.3-138250.53" + attribute \src "libresoc.v:141043.3-141064.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7489 + attribute \src "libresoc.v:140727.3-140728.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:138587.3-138608.6" - wire $0\data_r3__xer_so$next[0:0]$7186 - attribute \src "libresoc.v:138243.3-138244.47" + attribute \src "libresoc.v:141065.3-141086.6" + wire $0\data_r3__xer_so$next[0:0]$7496 + attribute \src "libresoc.v:140721.3-140722.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:138587.3-138608.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7187 - attribute \src "libresoc.v:138245.3-138246.53" + attribute \src "libresoc.v:141065.3-141086.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7497 + attribute \src "libresoc.v:140723.3-140724.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:138657.3-138666.6" + attribute \src "libresoc.v:141135.3-141144.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:138667.3-138676.6" + attribute \src "libresoc.v:141145.3-141154.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:138677.3-138686.6" + attribute \src "libresoc.v:141155.3-141164.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:138687.3-138696.6" + attribute \src "libresoc.v:141165.3-141174.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:137582.7-137582.20" + attribute \src "libresoc.v:140060.7-140060.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138443.3-138451.6" - wire $0\opc_l_r_opc$next[0:0]$7116 - attribute \src "libresoc.v:138291.3-138292.39" + attribute \src "libresoc.v:140921.3-140929.6" + wire $0\opc_l_r_opc$next[0:0]$7426 + attribute \src "libresoc.v:140769.3-140770.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:138434.3-138442.6" - wire $0\opc_l_s_opc$next[0:0]$7113 - attribute \src "libresoc.v:138293.3-138294.39" + attribute \src "libresoc.v:140912.3-140920.6" + wire $0\opc_l_s_opc$next[0:0]$7423 + attribute \src "libresoc.v:140771.3-140772.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:138697.3-138705.6" - wire width 4 $0\prev_wr_go$next[3:0]$7213 - attribute \src "libresoc.v:138303.3-138304.37" + attribute \src "libresoc.v:141175.3-141183.6" + wire width 4 $0\prev_wr_go$next[3:0]$7523 + attribute \src "libresoc.v:140781.3-140782.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:138388.3-138397.6" + attribute \src "libresoc.v:140866.3-140875.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:138479.3-138487.6" - wire width 4 $0\req_l_r_req$next[3:0]$7128 - attribute \src "libresoc.v:138283.3-138284.39" + attribute \src "libresoc.v:140957.3-140965.6" + wire width 4 $0\req_l_r_req$next[3:0]$7438 + attribute \src "libresoc.v:140761.3-140762.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:138470.3-138478.6" - wire width 4 $0\req_l_s_req$next[3:0]$7125 - attribute \src "libresoc.v:138285.3-138286.39" + attribute \src "libresoc.v:140948.3-140956.6" + wire width 4 $0\req_l_s_req$next[3:0]$7435 + attribute \src "libresoc.v:140763.3-140764.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:138407.3-138415.6" - wire $0\rok_l_r_rdok$next[0:0]$7104 - attribute \src "libresoc.v:138299.3-138300.41" + attribute \src "libresoc.v:140885.3-140893.6" + wire $0\rok_l_r_rdok$next[0:0]$7414 + attribute \src "libresoc.v:140777.3-140778.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:138398.3-138406.6" - wire $0\rok_l_s_rdok$next[0:0]$7101 - attribute \src "libresoc.v:138301.3-138302.41" + attribute \src "libresoc.v:140876.3-140884.6" + wire $0\rok_l_s_rdok$next[0:0]$7411 + attribute \src "libresoc.v:140779.3-140780.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:138425.3-138433.6" - wire $0\rst_l_r_rst$next[0:0]$7110 - attribute \src "libresoc.v:138295.3-138296.39" + attribute \src "libresoc.v:140903.3-140911.6" + wire $0\rst_l_r_rst$next[0:0]$7420 + attribute \src "libresoc.v:140773.3-140774.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:138416.3-138424.6" - wire $0\rst_l_s_rst$next[0:0]$7107 - attribute \src "libresoc.v:138297.3-138298.39" + attribute \src "libresoc.v:140894.3-140902.6" + wire $0\rst_l_s_rst$next[0:0]$7417 + attribute \src "libresoc.v:140775.3-140776.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:138461.3-138469.6" - wire width 3 $0\src_l_r_src$next[2:0]$7122 - attribute \src "libresoc.v:138287.3-138288.39" + attribute \src "libresoc.v:140939.3-140947.6" + wire width 3 $0\src_l_r_src$next[2:0]$7432 + attribute \src "libresoc.v:140765.3-140766.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:138452.3-138460.6" - wire width 3 $0\src_l_s_src$next[2:0]$7119 - attribute \src "libresoc.v:138289.3-138290.39" + attribute \src "libresoc.v:140930.3-140938.6" + wire width 3 $0\src_l_s_src$next[2:0]$7429 + attribute \src "libresoc.v:140767.3-140768.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:138609.3-138618.6" - wire width 64 $0\src_r0$next[63:0]$7194 - attribute \src "libresoc.v:138241.3-138242.29" + attribute \src "libresoc.v:141087.3-141096.6" + wire width 64 $0\src_r0$next[63:0]$7504 + attribute \src "libresoc.v:140719.3-140720.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:138619.3-138628.6" - wire width 64 $0\src_r1$next[63:0]$7197 - attribute \src "libresoc.v:138239.3-138240.29" + attribute \src "libresoc.v:141097.3-141106.6" + wire width 64 $0\src_r1$next[63:0]$7507 + attribute \src "libresoc.v:140717.3-140718.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:138629.3-138638.6" - wire $0\src_r2$next[0:0]$7200 - attribute \src "libresoc.v:138237.3-138238.29" + attribute \src "libresoc.v:141107.3-141116.6" + wire $0\src_r2$next[0:0]$7510 + attribute \src "libresoc.v:140715.3-140716.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:137706.7-137706.24" + attribute \src "libresoc.v:140184.7-140184.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:137716.7-137716.26" + attribute \src "libresoc.v:140194.7-140194.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:138648.3-138656.6" - wire $1\alu_l_r_alu$next[0:0]$7207 - attribute \src "libresoc.v:137724.7-137724.25" + attribute \src "libresoc.v:141126.3-141134.6" + wire $1\alu_l_r_alu$next[0:0]$7517 + attribute \src "libresoc.v:140202.7-140202.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 - attribute \src "libresoc.v:137745.14-137745.48" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 + attribute \src "libresoc.v:140223.14-140223.48" wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 - attribute \src "libresoc.v:137749.14-137749.68" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 + attribute \src "libresoc.v:140227.14-140227.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 - attribute \src "libresoc.v:137753.7-137753.43" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 + attribute \src "libresoc.v:140231.7-140231.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7146 - attribute \src "libresoc.v:137757.14-137757.43" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7456 + attribute \src "libresoc.v:140235.14-140235.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 - attribute \src "libresoc.v:137835.13-137835.47" + attribute \src "libresoc.v:140966.3-140998.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 + attribute \src "libresoc.v:140313.13-140313.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 - attribute \src "libresoc.v:137839.7-137839.39" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 + attribute \src "libresoc.v:140317.7-140317.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 - attribute \src "libresoc.v:137843.7-137843.40" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 + attribute \src "libresoc.v:140321.7-140321.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 - attribute \src "libresoc.v:137847.7-137847.37" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 + attribute \src "libresoc.v:140325.7-140325.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 - attribute \src "libresoc.v:137851.7-137851.37" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 + attribute \src "libresoc.v:140329.7-140329.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 - attribute \src "libresoc.v:137855.7-137855.37" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 + attribute \src "libresoc.v:140333.7-140333.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 - attribute \src "libresoc.v:137859.7-137859.37" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 + attribute \src "libresoc.v:140337.7-140337.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 - attribute \src "libresoc.v:137863.7-137863.40" + attribute \src "libresoc.v:140966.3-140998.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 + attribute \src "libresoc.v:140341.7-140341.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:138639.3-138647.6" - wire $1\alui_l_r_alui$next[0:0]$7204 - attribute \src "libresoc.v:137893.7-137893.27" + attribute \src "libresoc.v:141117.3-141125.6" + wire $1\alui_l_r_alui$next[0:0]$7514 + attribute \src "libresoc.v:140371.7-140371.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:138521.3-138542.6" - wire width 64 $1\data_r0__o$next[63:0]$7164 - attribute \src "libresoc.v:137927.14-137927.47" + attribute \src "libresoc.v:140999.3-141020.6" + wire width 64 $1\data_r0__o$next[63:0]$7474 + attribute \src "libresoc.v:140405.14-140405.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:138521.3-138542.6" - wire $1\data_r0__o_ok$next[0:0]$7165 - attribute \src "libresoc.v:137931.7-137931.27" + attribute \src "libresoc.v:140999.3-141020.6" + wire $1\data_r0__o_ok$next[0:0]$7475 + attribute \src "libresoc.v:140409.7-140409.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:138543.3-138564.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7172 - attribute \src "libresoc.v:137935.13-137935.33" + attribute \src "libresoc.v:141021.3-141042.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7482 + attribute \src "libresoc.v:140413.13-140413.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:138543.3-138564.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7173 - attribute \src "libresoc.v:137939.7-137939.30" + attribute \src "libresoc.v:141021.3-141042.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7483 + attribute \src "libresoc.v:140417.7-140417.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:138565.3-138586.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7180 - attribute \src "libresoc.v:137943.13-137943.35" + attribute \src "libresoc.v:141043.3-141064.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7490 + attribute \src "libresoc.v:140421.13-140421.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:138565.3-138586.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7181 - attribute \src "libresoc.v:137947.7-137947.32" + attribute \src "libresoc.v:141043.3-141064.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7491 + attribute \src "libresoc.v:140425.7-140425.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:138587.3-138608.6" - wire $1\data_r3__xer_so$next[0:0]$7188 - attribute \src "libresoc.v:137951.7-137951.29" + attribute \src "libresoc.v:141065.3-141086.6" + wire $1\data_r3__xer_so$next[0:0]$7498 + attribute \src "libresoc.v:140429.7-140429.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:138587.3-138608.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7189 - attribute \src "libresoc.v:137955.7-137955.32" + attribute \src "libresoc.v:141065.3-141086.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7499 + attribute \src "libresoc.v:140433.7-140433.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:138657.3-138666.6" + attribute \src "libresoc.v:141135.3-141144.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:138667.3-138676.6" + attribute \src "libresoc.v:141145.3-141154.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:138677.3-138686.6" + attribute \src "libresoc.v:141155.3-141164.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:138687.3-138696.6" + attribute \src "libresoc.v:141165.3-141174.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:138443.3-138451.6" - wire $1\opc_l_r_opc$next[0:0]$7117 - attribute \src "libresoc.v:137975.7-137975.25" + attribute \src "libresoc.v:140921.3-140929.6" + wire $1\opc_l_r_opc$next[0:0]$7427 + attribute \src "libresoc.v:140453.7-140453.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:138434.3-138442.6" - wire $1\opc_l_s_opc$next[0:0]$7114 - attribute \src "libresoc.v:137979.7-137979.25" + attribute \src "libresoc.v:140912.3-140920.6" + wire $1\opc_l_s_opc$next[0:0]$7424 + attribute \src "libresoc.v:140457.7-140457.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:138697.3-138705.6" - wire width 4 $1\prev_wr_go$next[3:0]$7214 - attribute \src "libresoc.v:138094.13-138094.30" + attribute \src "libresoc.v:141175.3-141183.6" + wire width 4 $1\prev_wr_go$next[3:0]$7524 + attribute \src "libresoc.v:140572.13-140572.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:138388.3-138397.6" + attribute \src "libresoc.v:140866.3-140875.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:138479.3-138487.6" - wire width 4 $1\req_l_r_req$next[3:0]$7129 - attribute \src "libresoc.v:138102.13-138102.31" + attribute \src "libresoc.v:140957.3-140965.6" + wire width 4 $1\req_l_r_req$next[3:0]$7439 + attribute \src "libresoc.v:140580.13-140580.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:138470.3-138478.6" - wire width 4 $1\req_l_s_req$next[3:0]$7126 - attribute \src "libresoc.v:138106.13-138106.31" + attribute \src "libresoc.v:140948.3-140956.6" + wire width 4 $1\req_l_s_req$next[3:0]$7436 + attribute \src "libresoc.v:140584.13-140584.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:138407.3-138415.6" - wire $1\rok_l_r_rdok$next[0:0]$7105 - attribute \src "libresoc.v:138118.7-138118.26" + attribute \src "libresoc.v:140885.3-140893.6" + wire $1\rok_l_r_rdok$next[0:0]$7415 + attribute \src "libresoc.v:140596.7-140596.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:138398.3-138406.6" - wire $1\rok_l_s_rdok$next[0:0]$7102 - attribute \src "libresoc.v:138122.7-138122.26" + attribute \src "libresoc.v:140876.3-140884.6" + wire $1\rok_l_s_rdok$next[0:0]$7412 + attribute \src "libresoc.v:140600.7-140600.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:138425.3-138433.6" - wire $1\rst_l_r_rst$next[0:0]$7111 - attribute \src "libresoc.v:138126.7-138126.25" + attribute \src "libresoc.v:140903.3-140911.6" + wire $1\rst_l_r_rst$next[0:0]$7421 + attribute \src "libresoc.v:140604.7-140604.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:138416.3-138424.6" - wire $1\rst_l_s_rst$next[0:0]$7108 - attribute \src "libresoc.v:138130.7-138130.25" + attribute \src "libresoc.v:140894.3-140902.6" + wire $1\rst_l_s_rst$next[0:0]$7418 + attribute \src "libresoc.v:140608.7-140608.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:138461.3-138469.6" - wire width 3 $1\src_l_r_src$next[2:0]$7123 - attribute \src "libresoc.v:138144.13-138144.31" + attribute \src "libresoc.v:140939.3-140947.6" + wire width 3 $1\src_l_r_src$next[2:0]$7433 + attribute \src "libresoc.v:140622.13-140622.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:138452.3-138460.6" - wire width 3 $1\src_l_s_src$next[2:0]$7120 - attribute \src "libresoc.v:138148.13-138148.31" + attribute \src "libresoc.v:140930.3-140938.6" + wire width 3 $1\src_l_s_src$next[2:0]$7430 + attribute \src "libresoc.v:140626.13-140626.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:138609.3-138618.6" - wire width 64 $1\src_r0$next[63:0]$7195 - attribute \src "libresoc.v:138154.14-138154.43" + attribute \src "libresoc.v:141087.3-141096.6" + wire width 64 $1\src_r0$next[63:0]$7505 + attribute \src "libresoc.v:140632.14-140632.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:138619.3-138628.6" - wire width 64 $1\src_r1$next[63:0]$7198 - attribute \src "libresoc.v:138158.14-138158.43" + attribute \src "libresoc.v:141097.3-141106.6" + wire width 64 $1\src_r1$next[63:0]$7508 + attribute \src "libresoc.v:140636.14-140636.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:138629.3-138638.6" - wire $1\src_r2$next[0:0]$7201 - attribute \src "libresoc.v:138162.7-138162.20" + attribute \src "libresoc.v:141107.3-141116.6" + wire $1\src_r2$next[0:0]$7511 + attribute \src "libresoc.v:140640.7-140640.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:138488.3-138520.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 - attribute \src "libresoc.v:138488.3-138520.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 - attribute \src "libresoc.v:138488.3-138520.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 - attribute \src "libresoc.v:138488.3-138520.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 - attribute \src "libresoc.v:138488.3-138520.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 - attribute \src "libresoc.v:138488.3-138520.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 - attribute \src "libresoc.v:138521.3-138542.6" - wire width 64 $2\data_r0__o$next[63:0]$7166 - attribute \src "libresoc.v:138521.3-138542.6" - wire $2\data_r0__o_ok$next[0:0]$7167 - attribute \src "libresoc.v:138543.3-138564.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7174 - attribute \src "libresoc.v:138543.3-138564.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7175 - attribute \src "libresoc.v:138565.3-138586.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7182 - attribute \src "libresoc.v:138565.3-138586.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7183 - attribute \src "libresoc.v:138587.3-138608.6" - wire $2\data_r3__xer_so$next[0:0]$7190 - attribute \src "libresoc.v:138587.3-138608.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7191 - attribute \src "libresoc.v:138521.3-138542.6" - wire $3\data_r0__o_ok$next[0:0]$7168 - attribute \src "libresoc.v:138543.3-138564.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7176 - attribute \src "libresoc.v:138565.3-138586.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7184 - attribute \src "libresoc.v:138587.3-138608.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7192 - attribute \src "libresoc.v:138173.19-138173.113" - wire width 3 $and$libresoc.v:138173$7001_Y - attribute \src "libresoc.v:138174.19-138174.125" - wire $and$libresoc.v:138174$7002_Y - attribute \src "libresoc.v:138175.19-138175.125" - wire $and$libresoc.v:138175$7003_Y - attribute \src "libresoc.v:138176.19-138176.125" - wire $and$libresoc.v:138176$7004_Y - attribute \src "libresoc.v:138177.19-138177.125" - wire $and$libresoc.v:138177$7005_Y - attribute \src "libresoc.v:138178.18-138178.110" - wire $and$libresoc.v:138178$7006_Y - attribute \src "libresoc.v:138179.19-138179.149" - wire width 4 $and$libresoc.v:138179$7007_Y - attribute \src "libresoc.v:138180.19-138180.121" - wire width 4 $and$libresoc.v:138180$7008_Y - attribute \src "libresoc.v:138181.19-138181.127" - wire $and$libresoc.v:138181$7009_Y - attribute \src "libresoc.v:138182.19-138182.127" - wire $and$libresoc.v:138182$7010_Y - attribute \src "libresoc.v:138183.19-138183.127" - wire $and$libresoc.v:138183$7011_Y - attribute \src "libresoc.v:138184.19-138184.127" - wire $and$libresoc.v:138184$7012_Y - attribute \src "libresoc.v:138186.18-138186.98" - wire $and$libresoc.v:138186$7014_Y - attribute \src "libresoc.v:138188.18-138188.100" - wire $and$libresoc.v:138188$7016_Y - attribute \src "libresoc.v:138189.18-138189.160" - wire width 4 $and$libresoc.v:138189$7017_Y - attribute \src "libresoc.v:138191.18-138191.119" - wire width 4 $and$libresoc.v:138191$7019_Y - attribute \src "libresoc.v:138194.17-138194.123" - wire $and$libresoc.v:138194$7022_Y - attribute \src "libresoc.v:138195.18-138195.116" - wire $and$libresoc.v:138195$7023_Y - attribute \src "libresoc.v:138200.18-138200.113" - wire $and$libresoc.v:138200$7028_Y - attribute \src "libresoc.v:138201.18-138201.125" - wire width 4 $and$libresoc.v:138201$7029_Y - attribute \src "libresoc.v:138203.18-138203.112" - wire $and$libresoc.v:138203$7031_Y - attribute \src "libresoc.v:138205.18-138205.126" - wire $and$libresoc.v:138205$7033_Y - attribute \src "libresoc.v:138206.18-138206.126" - wire $and$libresoc.v:138206$7034_Y - attribute \src "libresoc.v:138207.18-138207.117" - wire $and$libresoc.v:138207$7035_Y - attribute \src "libresoc.v:138213.18-138213.130" - wire $and$libresoc.v:138213$7041_Y - attribute \src "libresoc.v:138214.18-138214.124" - wire width 4 $and$libresoc.v:138214$7042_Y - attribute \src "libresoc.v:138216.18-138216.116" - wire $and$libresoc.v:138216$7044_Y - attribute \src "libresoc.v:138217.18-138217.119" - wire $and$libresoc.v:138217$7045_Y - attribute \src "libresoc.v:138218.18-138218.121" - wire $and$libresoc.v:138218$7046_Y - attribute \src "libresoc.v:138219.18-138219.121" - wire $and$libresoc.v:138219$7047_Y - attribute \src "libresoc.v:138226.18-138226.134" - wire $and$libresoc.v:138226$7054_Y - attribute \src "libresoc.v:138228.18-138228.132" - wire $and$libresoc.v:138228$7056_Y - attribute \src "libresoc.v:138229.18-138229.149" - wire width 3 $and$libresoc.v:138229$7057_Y - attribute \src "libresoc.v:138231.18-138231.129" - wire width 3 $and$libresoc.v:138231$7059_Y - attribute \src "libresoc.v:138202.18-138202.113" - wire $eq$libresoc.v:138202$7030_Y - attribute \src "libresoc.v:138204.18-138204.119" - wire $eq$libresoc.v:138204$7032_Y - attribute \src "libresoc.v:138185.18-138185.97" - wire $not$libresoc.v:138185$7013_Y - attribute \src "libresoc.v:138187.18-138187.99" - wire $not$libresoc.v:138187$7015_Y - attribute \src "libresoc.v:138190.18-138190.113" - wire width 4 $not$libresoc.v:138190$7018_Y - attribute \src "libresoc.v:138193.18-138193.106" - wire $not$libresoc.v:138193$7021_Y - attribute \src "libresoc.v:138199.18-138199.120" - wire $not$libresoc.v:138199$7027_Y - attribute \src "libresoc.v:138210.17-138210.113" - wire width 3 $not$libresoc.v:138210$7038_Y - attribute \src "libresoc.v:138230.18-138230.131" - wire $not$libresoc.v:138230$7058_Y - attribute \src "libresoc.v:138232.18-138232.114" - wire width 3 $not$libresoc.v:138232$7060_Y - attribute \src "libresoc.v:138198.18-138198.112" - wire $or$libresoc.v:138198$7026_Y - attribute \src "libresoc.v:138208.18-138208.122" - wire $or$libresoc.v:138208$7036_Y - attribute \src "libresoc.v:138209.18-138209.124" - wire $or$libresoc.v:138209$7037_Y - attribute \src "libresoc.v:138211.18-138211.168" - wire width 4 $or$libresoc.v:138211$7039_Y - attribute \src "libresoc.v:138212.18-138212.155" - wire width 3 $or$libresoc.v:138212$7040_Y - attribute \src "libresoc.v:138215.18-138215.120" - wire width 4 $or$libresoc.v:138215$7043_Y - attribute \src "libresoc.v:138221.17-138221.117" - wire width 3 $or$libresoc.v:138221$7049_Y - attribute \src "libresoc.v:138227.17-138227.104" - wire $reduce_and$libresoc.v:138227$7055_Y - attribute \src "libresoc.v:138192.18-138192.106" - wire $reduce_or$libresoc.v:138192$7020_Y - attribute \src "libresoc.v:138196.18-138196.113" - wire $reduce_or$libresoc.v:138196$7024_Y - attribute \src "libresoc.v:138197.18-138197.112" - wire $reduce_or$libresoc.v:138197$7025_Y - attribute \src "libresoc.v:138220.18-138220.160" - wire $ternary$libresoc.v:138220$7048_Y - attribute \src "libresoc.v:138222.18-138222.172" - wire width 64 $ternary$libresoc.v:138222$7050_Y - attribute \src "libresoc.v:138223.18-138223.118" - wire width 64 $ternary$libresoc.v:138223$7051_Y - attribute \src "libresoc.v:138224.18-138224.115" - wire width 64 $ternary$libresoc.v:138224$7052_Y - attribute \src "libresoc.v:138225.18-138225.118" - wire $ternary$libresoc.v:138225$7053_Y + attribute \src "libresoc.v:140966.3-140998.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 + attribute \src "libresoc.v:140966.3-140998.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 + attribute \src "libresoc.v:140966.3-140998.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 + attribute \src "libresoc.v:140966.3-140998.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 + attribute \src "libresoc.v:140966.3-140998.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 + attribute \src "libresoc.v:140966.3-140998.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 + attribute \src "libresoc.v:140999.3-141020.6" + wire width 64 $2\data_r0__o$next[63:0]$7476 + attribute \src "libresoc.v:140999.3-141020.6" + wire $2\data_r0__o_ok$next[0:0]$7477 + attribute \src "libresoc.v:141021.3-141042.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7484 + attribute \src "libresoc.v:141021.3-141042.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7485 + attribute \src "libresoc.v:141043.3-141064.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7492 + attribute \src "libresoc.v:141043.3-141064.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7493 + attribute \src "libresoc.v:141065.3-141086.6" + wire $2\data_r3__xer_so$next[0:0]$7500 + attribute \src "libresoc.v:141065.3-141086.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7501 + attribute \src "libresoc.v:140999.3-141020.6" + wire $3\data_r0__o_ok$next[0:0]$7478 + attribute \src "libresoc.v:141021.3-141042.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7486 + attribute \src "libresoc.v:141043.3-141064.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7494 + attribute \src "libresoc.v:141065.3-141086.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7502 + attribute \src "libresoc.v:140651.19-140651.113" + wire width 3 $and$libresoc.v:140651$7311_Y + attribute \src "libresoc.v:140652.19-140652.125" + wire $and$libresoc.v:140652$7312_Y + attribute \src "libresoc.v:140653.19-140653.125" + wire $and$libresoc.v:140653$7313_Y + attribute \src "libresoc.v:140654.19-140654.125" + wire $and$libresoc.v:140654$7314_Y + attribute \src "libresoc.v:140655.19-140655.125" + wire $and$libresoc.v:140655$7315_Y + attribute \src "libresoc.v:140656.18-140656.110" + wire $and$libresoc.v:140656$7316_Y + attribute \src "libresoc.v:140657.19-140657.149" + wire width 4 $and$libresoc.v:140657$7317_Y + attribute \src "libresoc.v:140658.19-140658.121" + wire width 4 $and$libresoc.v:140658$7318_Y + attribute \src "libresoc.v:140659.19-140659.127" + wire $and$libresoc.v:140659$7319_Y + attribute \src "libresoc.v:140660.19-140660.127" + wire $and$libresoc.v:140660$7320_Y + attribute \src "libresoc.v:140661.19-140661.127" + wire $and$libresoc.v:140661$7321_Y + attribute \src "libresoc.v:140662.19-140662.127" + wire $and$libresoc.v:140662$7322_Y + attribute \src "libresoc.v:140664.18-140664.98" + wire $and$libresoc.v:140664$7324_Y + attribute \src "libresoc.v:140666.18-140666.100" + wire $and$libresoc.v:140666$7326_Y + attribute \src "libresoc.v:140667.18-140667.160" + wire width 4 $and$libresoc.v:140667$7327_Y + attribute \src "libresoc.v:140669.18-140669.119" + wire width 4 $and$libresoc.v:140669$7329_Y + attribute \src "libresoc.v:140672.17-140672.123" + wire $and$libresoc.v:140672$7332_Y + attribute \src "libresoc.v:140673.18-140673.116" + wire $and$libresoc.v:140673$7333_Y + attribute \src "libresoc.v:140678.18-140678.113" + wire $and$libresoc.v:140678$7338_Y + attribute \src "libresoc.v:140679.18-140679.125" + wire width 4 $and$libresoc.v:140679$7339_Y + attribute \src "libresoc.v:140681.18-140681.112" + wire $and$libresoc.v:140681$7341_Y + attribute \src "libresoc.v:140683.18-140683.126" + wire $and$libresoc.v:140683$7343_Y + attribute \src "libresoc.v:140684.18-140684.126" + wire $and$libresoc.v:140684$7344_Y + attribute \src "libresoc.v:140685.18-140685.117" + wire $and$libresoc.v:140685$7345_Y + attribute \src "libresoc.v:140691.18-140691.130" + wire $and$libresoc.v:140691$7351_Y + attribute \src "libresoc.v:140692.18-140692.124" + wire width 4 $and$libresoc.v:140692$7352_Y + attribute \src "libresoc.v:140694.18-140694.116" + wire $and$libresoc.v:140694$7354_Y + attribute \src "libresoc.v:140695.18-140695.119" + wire $and$libresoc.v:140695$7355_Y + attribute \src "libresoc.v:140696.18-140696.121" + wire $and$libresoc.v:140696$7356_Y + attribute \src "libresoc.v:140697.18-140697.121" + wire $and$libresoc.v:140697$7357_Y + attribute \src "libresoc.v:140704.18-140704.134" + wire $and$libresoc.v:140704$7364_Y + attribute \src "libresoc.v:140706.18-140706.132" + wire $and$libresoc.v:140706$7366_Y + attribute \src "libresoc.v:140707.18-140707.149" + wire width 3 $and$libresoc.v:140707$7367_Y + attribute \src "libresoc.v:140709.18-140709.129" + wire width 3 $and$libresoc.v:140709$7369_Y + attribute \src "libresoc.v:140680.18-140680.113" + wire $eq$libresoc.v:140680$7340_Y + attribute \src "libresoc.v:140682.18-140682.119" + wire $eq$libresoc.v:140682$7342_Y + attribute \src "libresoc.v:140663.18-140663.97" + wire $not$libresoc.v:140663$7323_Y + attribute \src "libresoc.v:140665.18-140665.99" + wire $not$libresoc.v:140665$7325_Y + attribute \src "libresoc.v:140668.18-140668.113" + wire width 4 $not$libresoc.v:140668$7328_Y + attribute \src "libresoc.v:140671.18-140671.106" + wire $not$libresoc.v:140671$7331_Y + attribute \src "libresoc.v:140677.18-140677.120" + wire $not$libresoc.v:140677$7337_Y + attribute \src "libresoc.v:140688.17-140688.113" + wire width 3 $not$libresoc.v:140688$7348_Y + attribute \src "libresoc.v:140708.18-140708.131" + wire $not$libresoc.v:140708$7368_Y + attribute \src "libresoc.v:140710.18-140710.114" + wire width 3 $not$libresoc.v:140710$7370_Y + attribute \src "libresoc.v:140676.18-140676.112" + wire $or$libresoc.v:140676$7336_Y + attribute \src "libresoc.v:140686.18-140686.122" + wire $or$libresoc.v:140686$7346_Y + attribute \src "libresoc.v:140687.18-140687.124" + wire $or$libresoc.v:140687$7347_Y + attribute \src "libresoc.v:140689.18-140689.168" + wire width 4 $or$libresoc.v:140689$7349_Y + attribute \src "libresoc.v:140690.18-140690.155" + wire width 3 $or$libresoc.v:140690$7350_Y + attribute \src "libresoc.v:140693.18-140693.120" + wire width 4 $or$libresoc.v:140693$7353_Y + attribute \src "libresoc.v:140699.17-140699.117" + wire width 3 $or$libresoc.v:140699$7359_Y + attribute \src "libresoc.v:140705.17-140705.104" + wire $reduce_and$libresoc.v:140705$7365_Y + attribute \src "libresoc.v:140670.18-140670.106" + wire $reduce_or$libresoc.v:140670$7330_Y + attribute \src "libresoc.v:140674.18-140674.113" + wire $reduce_or$libresoc.v:140674$7334_Y + attribute \src "libresoc.v:140675.18-140675.112" + wire $reduce_or$libresoc.v:140675$7335_Y + attribute \src "libresoc.v:140698.18-140698.160" + wire $ternary$libresoc.v:140698$7358_Y + attribute \src "libresoc.v:140700.18-140700.172" + wire width 64 $ternary$libresoc.v:140700$7360_Y + attribute \src "libresoc.v:140701.18-140701.118" + wire width 64 $ternary$libresoc.v:140701$7361_Y + attribute \src "libresoc.v:140702.18-140702.115" + wire width 64 $ternary$libresoc.v:140702$7362_Y + attribute \src "libresoc.v:140703.18-140703.118" + wire $ternary$libresoc.v:140703$7363_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -287987,7 +294378,7 @@ module \mul0 wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_mul0_cr_a attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -288128,7 +294519,7 @@ module \mul0 wire \alu_mul0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_mul0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_mul0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_mul0_p_ready_o @@ -288138,9 +294529,9 @@ module \mul0 wire width 64 \alu_mul0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_mul0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_mul0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \alu_mul0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_mul0_xer_so$1 @@ -288156,32 +294547,32 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 31 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 14 \cu_busy_o + wire output 15 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 13 \cu_issue_i + wire input 14 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 17 \cu_rd__go_i + wire width 3 input 18 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 16 \cu_rd__rel_o + wire width 3 output 17 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 15 \cu_rdmaskn_i + wire width 3 input 16 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 23 \cu_wr__go_i + wire width 4 input 24 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 22 \cu_wr__rel_o + wire width 4 output 23 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 4 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -288217,17 +294608,17 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r3__xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest1_o + wire width 64 output 25 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 26 \dest2_o + wire width 4 output 27 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 28 \dest3_o + wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 30 \dest4_o - attribute \src "libresoc.v:137582.7-137582.15" + wire output 31 \dest4_o + attribute \src "libresoc.v:140060.7-140060.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -288252,13 +294643,13 @@ module \mul0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_mul0__fn_unit + wire width 12 input 3 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_mul0__imm_data__data + wire width 64 input 4 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_mul0__imm_data__ok + wire input 5 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \oper_i_alu_mul0__insn + wire width 32 input 13 \oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -288334,21 +294725,21 @@ module \mul0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_mul0__insn_type + wire width 7 input 2 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_mul0__is_32bit + wire input 11 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_mul0__is_signed + wire input 12 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_mul0__oe__oe + wire input 8 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_mul0__oe__ok + wire input 9 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_mul0__rc__ok + wire input 7 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_mul0__rc__rc + wire input 6 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_mul0__write_cr0 + wire input 10 \oper_i_alu_mul0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 4 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -288392,11 +294783,11 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 18 \src1_i + wire width 64 input 19 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 19 \src2_i + wire width 64 input 20 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 20 \src3_i + wire input 21 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -288425,12 +294816,12 @@ module \mul0 wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:138173$7001 + cell $and $and$libresoc.v:140651$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -288438,10 +294829,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:138173$7001_Y + connect \Y $and$libresoc.v:140651$7311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:138174$7002 + cell $and $and$libresoc.v:140652$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288449,10 +294840,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138174$7002_Y + connect \Y $and$libresoc.v:140652$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:138175$7003 + cell $and $and$libresoc.v:140653$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288460,10 +294851,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138175$7003_Y + connect \Y $and$libresoc.v:140653$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:138176$7004 + cell $and $and$libresoc.v:140654$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288471,10 +294862,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138176$7004_Y + connect \Y $and$libresoc.v:140654$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:138177$7005 + cell $and $and$libresoc.v:140655$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288482,10 +294873,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:138177$7005_Y + connect \Y $and$libresoc.v:140655$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:138178$7006 + cell $and $and$libresoc.v:140656$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288493,10 +294884,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:138178$7006_Y + connect \Y $and$libresoc.v:140656$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:138179$7007 + cell $and $and$libresoc.v:140657$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288504,10 +294895,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:138179$7007_Y + connect \Y $and$libresoc.v:140657$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:138180$7008 + cell $and $and$libresoc.v:140658$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288515,10 +294906,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:138180$7008_Y + connect \Y $and$libresoc.v:140658$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:138181$7009 + cell $and $and$libresoc.v:140659$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288526,10 +294917,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:138181$7009_Y + connect \Y $and$libresoc.v:140659$7319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:138182$7010 + cell $and $and$libresoc.v:140660$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288537,10 +294928,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:138182$7010_Y + connect \Y $and$libresoc.v:140660$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:138183$7011 + cell $and $and$libresoc.v:140661$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288548,10 +294939,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:138183$7011_Y + connect \Y $and$libresoc.v:140661$7321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:138184$7012 + cell $and $and$libresoc.v:140662$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288559,10 +294950,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:138184$7012_Y + connect \Y $and$libresoc.v:140662$7322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:138186$7014 + cell $and $and$libresoc.v:140664$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288570,10 +294961,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:138186$7014_Y + connect \Y $and$libresoc.v:140664$7324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:138188$7016 + cell $and $and$libresoc.v:140666$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288581,10 +294972,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:138188$7016_Y + connect \Y $and$libresoc.v:140666$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:138189$7017 + cell $and $and$libresoc.v:140667$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288592,10 +294983,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:138189$7017_Y + connect \Y $and$libresoc.v:140667$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:138191$7019 + cell $and $and$libresoc.v:140669$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288603,10 +294994,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:138191$7019_Y + connect \Y $and$libresoc.v:140669$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:138194$7022 + cell $and $and$libresoc.v:140672$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288614,10 +295005,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:138194$7022_Y + connect \Y $and$libresoc.v:140672$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:138195$7023 + cell $and $and$libresoc.v:140673$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288625,10 +295016,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:138195$7023_Y + connect \Y $and$libresoc.v:140673$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:138200$7028 + cell $and $and$libresoc.v:140678$7338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288636,10 +295027,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:138200$7028_Y + connect \Y $and$libresoc.v:140678$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:138201$7029 + cell $and $and$libresoc.v:140679$7339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288647,10 +295038,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:138201$7029_Y + connect \Y $and$libresoc.v:140679$7339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:138203$7031 + cell $and $and$libresoc.v:140681$7341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288658,10 +295049,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:138203$7031_Y + connect \Y $and$libresoc.v:140681$7341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:138205$7033 + cell $and $and$libresoc.v:140683$7343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288669,10 +295060,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:138205$7033_Y + connect \Y $and$libresoc.v:140683$7343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:138206$7034 + cell $and $and$libresoc.v:140684$7344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288680,10 +295071,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:138206$7034_Y + connect \Y $and$libresoc.v:140684$7344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:138207$7035 + cell $and $and$libresoc.v:140685$7345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288691,10 +295082,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:138207$7035_Y + connect \Y $and$libresoc.v:140685$7345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:138213$7041 + cell $and $and$libresoc.v:140691$7351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288702,10 +295093,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:138213$7041_Y + connect \Y $and$libresoc.v:140691$7351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:138214$7042 + cell $and $and$libresoc.v:140692$7352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288713,10 +295104,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:138214$7042_Y + connect \Y $and$libresoc.v:140692$7352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:138216$7044 + cell $and $and$libresoc.v:140694$7354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288724,10 +295115,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:138216$7044_Y + connect \Y $and$libresoc.v:140694$7354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:138217$7045 + cell $and $and$libresoc.v:140695$7355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288735,10 +295126,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:138217$7045_Y + connect \Y $and$libresoc.v:140695$7355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:138218$7046 + cell $and $and$libresoc.v:140696$7356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288746,10 +295137,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:138218$7046_Y + connect \Y $and$libresoc.v:140696$7356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:138219$7047 + cell $and $and$libresoc.v:140697$7357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288757,10 +295148,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:138219$7047_Y + connect \Y $and$libresoc.v:140697$7357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:138226$7054 + cell $and $and$libresoc.v:140704$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288768,10 +295159,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:138226$7054_Y + connect \Y $and$libresoc.v:140704$7364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:138228$7056 + cell $and $and$libresoc.v:140706$7366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288779,10 +295170,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:138228$7056_Y + connect \Y $and$libresoc.v:140706$7366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:138229$7057 + cell $and $and$libresoc.v:140707$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -288790,10 +295181,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:138229$7057_Y + connect \Y $and$libresoc.v:140707$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:138231$7059 + cell $and $and$libresoc.v:140709$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -288801,10 +295192,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:138231$7059_Y + connect \Y $and$libresoc.v:140709$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:138202$7030 + cell $eq $eq$libresoc.v:140680$7340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288812,10 +295203,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:138202$7030_Y + connect \Y $eq$libresoc.v:140680$7340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:138204$7032 + cell $eq $eq$libresoc.v:140682$7342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288823,74 +295214,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:138204$7032_Y + connect \Y $eq$libresoc.v:140682$7342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:138185$7013 + cell $not $not$libresoc.v:140663$7323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:138185$7013_Y + connect \Y $not$libresoc.v:140663$7323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:138187$7015 + cell $not $not$libresoc.v:140665$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:138187$7015_Y + connect \Y $not$libresoc.v:140665$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:138190$7018 + cell $not $not$libresoc.v:140668$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:138190$7018_Y + connect \Y $not$libresoc.v:140668$7328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:138193$7021 + cell $not $not$libresoc.v:140671$7331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:138193$7021_Y + connect \Y $not$libresoc.v:140671$7331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:138199$7027 + cell $not $not$libresoc.v:140677$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:138199$7027_Y + connect \Y $not$libresoc.v:140677$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:138210$7038 + cell $not $not$libresoc.v:140688$7348 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:138210$7038_Y + connect \Y $not$libresoc.v:140688$7348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:138230$7058 + cell $not $not$libresoc.v:140708$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:138230$7058_Y + connect \Y $not$libresoc.v:140708$7368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:138232$7060 + cell $not $not$libresoc.v:140710$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:138232$7060_Y + connect \Y $not$libresoc.v:140710$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:138198$7026 + cell $or $or$libresoc.v:140676$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288898,10 +295289,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:138198$7026_Y + connect \Y $or$libresoc.v:140676$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:138208$7036 + cell $or $or$libresoc.v:140686$7346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288909,10 +295300,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138208$7036_Y + connect \Y $or$libresoc.v:140686$7346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:138209$7037 + cell $or $or$libresoc.v:140687$7347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -288920,10 +295311,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:138209$7037_Y + connect \Y $or$libresoc.v:140687$7347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:138211$7039 + cell $or $or$libresoc.v:140689$7349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288931,10 +295322,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:138211$7039_Y + connect \Y $or$libresoc.v:140689$7349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:138212$7040 + cell $or $or$libresoc.v:140690$7350 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -288942,10 +295333,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:138212$7040_Y + connect \Y $or$libresoc.v:140690$7350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:138215$7043 + cell $or $or$libresoc.v:140693$7353 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -288953,10 +295344,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:138215$7043_Y + connect \Y $or$libresoc.v:140693$7353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:138221$7049 + cell $or $or$libresoc.v:140699$7359 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -288964,83 +295355,83 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:138221$7049_Y + connect \Y $or$libresoc.v:140699$7359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:138227$7055 + cell $reduce_and $reduce_and$libresoc.v:140705$7365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:138227$7055_Y + connect \Y $reduce_and$libresoc.v:140705$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:138192$7020 + cell $reduce_or $reduce_or$libresoc.v:140670$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:138192$7020_Y + connect \Y $reduce_or$libresoc.v:140670$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:138196$7024 + cell $reduce_or $reduce_or$libresoc.v:140674$7334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:138196$7024_Y + connect \Y $reduce_or$libresoc.v:140674$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:138197$7025 + cell $reduce_or $reduce_or$libresoc.v:140675$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:138197$7025_Y + connect \Y $reduce_or$libresoc.v:140675$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:138220$7048 + cell $mux $ternary$libresoc.v:140698$7358 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:138220$7048_Y + connect \Y $ternary$libresoc.v:140698$7358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:138222$7050 + cell $mux $ternary$libresoc.v:140700$7360 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:138222$7050_Y + connect \Y $ternary$libresoc.v:140700$7360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:138223$7051 + cell $mux $ternary$libresoc.v:140701$7361 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:138223$7051_Y + connect \Y $ternary$libresoc.v:140701$7361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:138224$7052 + cell $mux $ternary$libresoc.v:140702$7362 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:138224$7052_Y + connect \Y $ternary$libresoc.v:140702$7362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:138225$7053 + cell $mux $ternary$libresoc.v:140703$7363 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:138225$7053_Y + connect \Y $ternary$libresoc.v:140703$7363_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:138309.15-138315.4" - cell \alu_l$104 \alu_l + attribute \src "libresoc.v:140787.15-140793.4" + cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -289048,7 +295439,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:138316.12-138346.4" + attribute \src "libresoc.v:140794.12-140824.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -289081,8 +295472,8 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:138347.16-138353.4" - cell \alui_l$103 \alui_l + attribute \src "libresoc.v:140825.16-140831.4" + cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -289090,8 +295481,8 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:138354.14-138360.4" - cell \opc_l$99 \opc_l + attribute \src "libresoc.v:140832.15-140838.4" + cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -289099,8 +295490,8 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:138361.15-138367.4" - cell \req_l$100 \req_l + attribute \src "libresoc.v:140839.15-140845.4" + cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -289108,8 +295499,8 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:138368.15-138374.4" - cell \rok_l$102 \rok_l + attribute \src "libresoc.v:140846.15-140852.4" + cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -289117,608 +295508,608 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:138375.15-138380.4" - cell \rst_l$101 \rst_l + attribute \src "libresoc.v:140853.15-140858.4" + cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:138381.14-138387.4" - cell \src_l$98 \src_l + attribute \src "libresoc.v:140859.15-140865.4" + cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:137582.7-137582.20" - process $proc$libresoc.v:137582$7215 + attribute \src "libresoc.v:140060.7-140060.20" + process $proc$libresoc.v:140060$7525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137706.7-137706.24" - process $proc$libresoc.v:137706$7216 + attribute \src "libresoc.v:140184.7-140184.24" + process $proc$libresoc.v:140184$7526 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:137716.7-137716.26" - process $proc$libresoc.v:137716$7217 + attribute \src "libresoc.v:140194.7-140194.26" + process $proc$libresoc.v:140194$7527 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:137724.7-137724.25" - process $proc$libresoc.v:137724$7218 + attribute \src "libresoc.v:140202.7-140202.25" + process $proc$libresoc.v:140202$7528 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:137745.14-137745.48" - process $proc$libresoc.v:137745$7219 + attribute \src "libresoc.v:140223.14-140223.48" + process $proc$libresoc.v:140223$7529 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] end - attribute \src "libresoc.v:137749.14-137749.68" - process $proc$libresoc.v:137749$7220 + attribute \src "libresoc.v:140227.14-140227.68" + process $proc$libresoc.v:140227$7530 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:137753.7-137753.43" - process $proc$libresoc.v:137753$7221 + attribute \src "libresoc.v:140231.7-140231.43" + process $proc$libresoc.v:140231$7531 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:137757.14-137757.43" - process $proc$libresoc.v:137757$7222 + attribute \src "libresoc.v:140235.14-140235.43" + process $proc$libresoc.v:140235$7532 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:137835.13-137835.47" - process $proc$libresoc.v:137835$7223 + attribute \src "libresoc.v:140313.13-140313.47" + process $proc$libresoc.v:140313$7533 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:137839.7-137839.39" - process $proc$libresoc.v:137839$7224 + attribute \src "libresoc.v:140317.7-140317.39" + process $proc$libresoc.v:140317$7534 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:137843.7-137843.40" - process $proc$libresoc.v:137843$7225 + attribute \src "libresoc.v:140321.7-140321.40" + process $proc$libresoc.v:140321$7535 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:137847.7-137847.37" - process $proc$libresoc.v:137847$7226 + attribute \src "libresoc.v:140325.7-140325.37" + process $proc$libresoc.v:140325$7536 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:137851.7-137851.37" - process $proc$libresoc.v:137851$7227 + attribute \src "libresoc.v:140329.7-140329.37" + process $proc$libresoc.v:140329$7537 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:137855.7-137855.37" - process $proc$libresoc.v:137855$7228 + attribute \src "libresoc.v:140333.7-140333.37" + process $proc$libresoc.v:140333$7538 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:137859.7-137859.37" - process $proc$libresoc.v:137859$7229 + attribute \src "libresoc.v:140337.7-140337.37" + process $proc$libresoc.v:140337$7539 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:137863.7-137863.40" - process $proc$libresoc.v:137863$7230 + attribute \src "libresoc.v:140341.7-140341.40" + process $proc$libresoc.v:140341$7540 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:137893.7-137893.27" - process $proc$libresoc.v:137893$7231 + attribute \src "libresoc.v:140371.7-140371.27" + process $proc$libresoc.v:140371$7541 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:137927.14-137927.47" - process $proc$libresoc.v:137927$7232 + attribute \src "libresoc.v:140405.14-140405.47" + process $proc$libresoc.v:140405$7542 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:137931.7-137931.27" - process $proc$libresoc.v:137931$7233 + attribute \src "libresoc.v:140409.7-140409.27" + process $proc$libresoc.v:140409$7543 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:137935.13-137935.33" - process $proc$libresoc.v:137935$7234 + attribute \src "libresoc.v:140413.13-140413.33" + process $proc$libresoc.v:140413$7544 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:137939.7-137939.30" - process $proc$libresoc.v:137939$7235 + attribute \src "libresoc.v:140417.7-140417.30" + process $proc$libresoc.v:140417$7545 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:137943.13-137943.35" - process $proc$libresoc.v:137943$7236 + attribute \src "libresoc.v:140421.13-140421.35" + process $proc$libresoc.v:140421$7546 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:137947.7-137947.32" - process $proc$libresoc.v:137947$7237 + attribute \src "libresoc.v:140425.7-140425.32" + process $proc$libresoc.v:140425$7547 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:137951.7-137951.29" - process $proc$libresoc.v:137951$7238 + attribute \src "libresoc.v:140429.7-140429.29" + process $proc$libresoc.v:140429$7548 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:137955.7-137955.32" - process $proc$libresoc.v:137955$7239 + attribute \src "libresoc.v:140433.7-140433.32" + process $proc$libresoc.v:140433$7549 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:137975.7-137975.25" - process $proc$libresoc.v:137975$7240 + attribute \src "libresoc.v:140453.7-140453.25" + process $proc$libresoc.v:140453$7550 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:137979.7-137979.25" - process $proc$libresoc.v:137979$7241 + attribute \src "libresoc.v:140457.7-140457.25" + process $proc$libresoc.v:140457$7551 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:138094.13-138094.30" - process $proc$libresoc.v:138094$7242 + attribute \src "libresoc.v:140572.13-140572.30" + process $proc$libresoc.v:140572$7552 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:138102.13-138102.31" - process $proc$libresoc.v:138102$7243 + attribute \src "libresoc.v:140580.13-140580.31" + process $proc$libresoc.v:140580$7553 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:138106.13-138106.31" - process $proc$libresoc.v:138106$7244 + attribute \src "libresoc.v:140584.13-140584.31" + process $proc$libresoc.v:140584$7554 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:138118.7-138118.26" - process $proc$libresoc.v:138118$7245 + attribute \src "libresoc.v:140596.7-140596.26" + process $proc$libresoc.v:140596$7555 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:138122.7-138122.26" - process $proc$libresoc.v:138122$7246 + attribute \src "libresoc.v:140600.7-140600.26" + process $proc$libresoc.v:140600$7556 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:138126.7-138126.25" - process $proc$libresoc.v:138126$7247 + attribute \src "libresoc.v:140604.7-140604.25" + process $proc$libresoc.v:140604$7557 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:138130.7-138130.25" - process $proc$libresoc.v:138130$7248 + attribute \src "libresoc.v:140608.7-140608.25" + process $proc$libresoc.v:140608$7558 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:138144.13-138144.31" - process $proc$libresoc.v:138144$7249 + attribute \src "libresoc.v:140622.13-140622.31" + process $proc$libresoc.v:140622$7559 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:138148.13-138148.31" - process $proc$libresoc.v:138148$7250 + attribute \src "libresoc.v:140626.13-140626.31" + process $proc$libresoc.v:140626$7560 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:138154.14-138154.43" - process $proc$libresoc.v:138154$7251 + attribute \src "libresoc.v:140632.14-140632.43" + process $proc$libresoc.v:140632$7561 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:138158.14-138158.43" - process $proc$libresoc.v:138158$7252 + attribute \src "libresoc.v:140636.14-140636.43" + process $proc$libresoc.v:140636$7562 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:138162.7-138162.20" - process $proc$libresoc.v:138162$7253 + attribute \src "libresoc.v:140640.7-140640.20" + process $proc$libresoc.v:140640$7563 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:138233.3-138234.39" - process $proc$libresoc.v:138233$7061 + attribute \src "libresoc.v:140711.3-140712.39" + process $proc$libresoc.v:140711$7371 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:138235.3-138236.43" - process $proc$libresoc.v:138235$7062 + attribute \src "libresoc.v:140713.3-140714.43" + process $proc$libresoc.v:140713$7372 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:138237.3-138238.29" - process $proc$libresoc.v:138237$7063 + attribute \src "libresoc.v:140715.3-140716.29" + process $proc$libresoc.v:140715$7373 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:138239.3-138240.29" - process $proc$libresoc.v:138239$7064 + attribute \src "libresoc.v:140717.3-140718.29" + process $proc$libresoc.v:140717$7374 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:138241.3-138242.29" - process $proc$libresoc.v:138241$7065 + attribute \src "libresoc.v:140719.3-140720.29" + process $proc$libresoc.v:140719$7375 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:138243.3-138244.47" - process $proc$libresoc.v:138243$7066 + attribute \src "libresoc.v:140721.3-140722.47" + process $proc$libresoc.v:140721$7376 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:138245.3-138246.53" - process $proc$libresoc.v:138245$7067 + attribute \src "libresoc.v:140723.3-140724.53" + process $proc$libresoc.v:140723$7377 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:138247.3-138248.47" - process $proc$libresoc.v:138247$7068 + attribute \src "libresoc.v:140725.3-140726.47" + process $proc$libresoc.v:140725$7378 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:138249.3-138250.53" - process $proc$libresoc.v:138249$7069 + attribute \src "libresoc.v:140727.3-140728.53" + process $proc$libresoc.v:140727$7379 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:138251.3-138252.43" - process $proc$libresoc.v:138251$7070 + attribute \src "libresoc.v:140729.3-140730.43" + process $proc$libresoc.v:140729$7380 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:138253.3-138254.49" - process $proc$libresoc.v:138253$7071 + attribute \src "libresoc.v:140731.3-140732.49" + process $proc$libresoc.v:140731$7381 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:138255.3-138256.37" - process $proc$libresoc.v:138255$7072 + attribute \src "libresoc.v:140733.3-140734.37" + process $proc$libresoc.v:140733$7382 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:138257.3-138258.43" - process $proc$libresoc.v:138257$7073 + attribute \src "libresoc.v:140735.3-140736.43" + process $proc$libresoc.v:140735$7383 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:138259.3-138260.69" - process $proc$libresoc.v:138259$7074 + attribute \src "libresoc.v:140737.3-140738.69" + process $proc$libresoc.v:140737$7384 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:138261.3-138262.65" - process $proc$libresoc.v:138261$7075 + attribute \src "libresoc.v:140739.3-140740.65" + process $proc$libresoc.v:140739$7385 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] end - attribute \src "libresoc.v:138263.3-138264.79" - process $proc$libresoc.v:138263$7076 + attribute \src "libresoc.v:140741.3-140742.79" + process $proc$libresoc.v:140741$7386 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:138265.3-138266.75" - process $proc$libresoc.v:138265$7077 + attribute \src "libresoc.v:140743.3-140744.75" + process $proc$libresoc.v:140743$7387 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:138267.3-138268.63" - process $proc$libresoc.v:138267$7078 + attribute \src "libresoc.v:140745.3-140746.63" + process $proc$libresoc.v:140745$7388 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:138269.3-138270.63" - process $proc$libresoc.v:138269$7079 + attribute \src "libresoc.v:140747.3-140748.63" + process $proc$libresoc.v:140747$7389 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:138271.3-138272.63" - process $proc$libresoc.v:138271$7080 + attribute \src "libresoc.v:140749.3-140750.63" + process $proc$libresoc.v:140749$7390 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:138273.3-138274.63" - process $proc$libresoc.v:138273$7081 + attribute \src "libresoc.v:140751.3-140752.63" + process $proc$libresoc.v:140751$7391 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:138275.3-138276.69" - process $proc$libresoc.v:138275$7082 + attribute \src "libresoc.v:140753.3-140754.69" + process $proc$libresoc.v:140753$7392 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:138277.3-138278.67" - process $proc$libresoc.v:138277$7083 + attribute \src "libresoc.v:140755.3-140756.67" + process $proc$libresoc.v:140755$7393 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:138279.3-138280.69" - process $proc$libresoc.v:138279$7084 + attribute \src "libresoc.v:140757.3-140758.69" + process $proc$libresoc.v:140757$7394 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:138281.3-138282.59" - process $proc$libresoc.v:138281$7085 + attribute \src "libresoc.v:140759.3-140760.59" + process $proc$libresoc.v:140759$7395 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:138283.3-138284.39" - process $proc$libresoc.v:138283$7086 + attribute \src "libresoc.v:140761.3-140762.39" + process $proc$libresoc.v:140761$7396 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:138285.3-138286.39" - process $proc$libresoc.v:138285$7087 + attribute \src "libresoc.v:140763.3-140764.39" + process $proc$libresoc.v:140763$7397 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:138287.3-138288.39" - process $proc$libresoc.v:138287$7088 + attribute \src "libresoc.v:140765.3-140766.39" + process $proc$libresoc.v:140765$7398 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:138289.3-138290.39" - process $proc$libresoc.v:138289$7089 + attribute \src "libresoc.v:140767.3-140768.39" + process $proc$libresoc.v:140767$7399 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:138291.3-138292.39" - process $proc$libresoc.v:138291$7090 + attribute \src "libresoc.v:140769.3-140770.39" + process $proc$libresoc.v:140769$7400 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:138293.3-138294.39" - process $proc$libresoc.v:138293$7091 + attribute \src "libresoc.v:140771.3-140772.39" + process $proc$libresoc.v:140771$7401 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:138295.3-138296.39" - process $proc$libresoc.v:138295$7092 + attribute \src "libresoc.v:140773.3-140774.39" + process $proc$libresoc.v:140773$7402 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:138297.3-138298.39" - process $proc$libresoc.v:138297$7093 + attribute \src "libresoc.v:140775.3-140776.39" + process $proc$libresoc.v:140775$7403 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:138299.3-138300.41" - process $proc$libresoc.v:138299$7094 + attribute \src "libresoc.v:140777.3-140778.41" + process $proc$libresoc.v:140777$7404 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:138301.3-138302.41" - process $proc$libresoc.v:138301$7095 + attribute \src "libresoc.v:140779.3-140780.41" + process $proc$libresoc.v:140779$7405 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:138303.3-138304.37" - process $proc$libresoc.v:138303$7096 + attribute \src "libresoc.v:140781.3-140782.37" + process $proc$libresoc.v:140781$7406 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:138305.3-138306.40" - process $proc$libresoc.v:138305$7097 + attribute \src "libresoc.v:140783.3-140784.40" + process $proc$libresoc.v:140783$7407 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:138307.3-138308.25" - process $proc$libresoc.v:138307$7098 + attribute \src "libresoc.v:140785.3-140786.25" + process $proc$libresoc.v:140785$7408 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:138388.3-138397.6" - process $proc$libresoc.v:138388$7099 + attribute \src "libresoc.v:140866.3-140875.6" + process $proc$libresoc.v:140866$7409 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:138389.5-138389.29" + attribute \src "libresoc.v:140867.5-140867.29" switch \initial - attribute \src "libresoc.v:138389.9-138389.17" + attribute \src "libresoc.v:140867.9-140867.17" case 1'1 case end @@ -289734,14 +296125,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:138398.3-138406.6" - process $proc$libresoc.v:138398$7100 + attribute \src "libresoc.v:140876.3-140884.6" + process $proc$libresoc.v:140876$7410 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7101 $1\rok_l_s_rdok$next[0:0]$7102 - attribute \src "libresoc.v:138399.5-138399.29" + assign $0\rok_l_s_rdok$next[0:0]$7411 $1\rok_l_s_rdok$next[0:0]$7412 + attribute \src "libresoc.v:140877.5-140877.29" switch \initial - attribute \src "libresoc.v:138399.9-138399.17" + attribute \src "libresoc.v:140877.9-140877.17" case 1'1 case end @@ -289750,21 +296141,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7102 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7412 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7102 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7412 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7101 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7411 end - attribute \src "libresoc.v:138407.3-138415.6" - process $proc$libresoc.v:138407$7103 + attribute \src "libresoc.v:140885.3-140893.6" + process $proc$libresoc.v:140885$7413 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7104 $1\rok_l_r_rdok$next[0:0]$7105 - attribute \src "libresoc.v:138408.5-138408.29" + assign $0\rok_l_r_rdok$next[0:0]$7414 $1\rok_l_r_rdok$next[0:0]$7415 + attribute \src "libresoc.v:140886.5-140886.29" switch \initial - attribute \src "libresoc.v:138408.9-138408.17" + attribute \src "libresoc.v:140886.9-140886.17" case 1'1 case end @@ -289773,21 +296164,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7105 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7415 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7105 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7415 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7104 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7414 end - attribute \src "libresoc.v:138416.3-138424.6" - process $proc$libresoc.v:138416$7106 + attribute \src "libresoc.v:140894.3-140902.6" + process $proc$libresoc.v:140894$7416 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7107 $1\rst_l_s_rst$next[0:0]$7108 - attribute \src "libresoc.v:138417.5-138417.29" + assign $0\rst_l_s_rst$next[0:0]$7417 $1\rst_l_s_rst$next[0:0]$7418 + attribute \src "libresoc.v:140895.5-140895.29" switch \initial - attribute \src "libresoc.v:138417.9-138417.17" + attribute \src "libresoc.v:140895.9-140895.17" case 1'1 case end @@ -289796,21 +296187,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7108 1'0 + assign $1\rst_l_s_rst$next[0:0]$7418 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7108 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7418 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7107 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7417 end - attribute \src "libresoc.v:138425.3-138433.6" - process $proc$libresoc.v:138425$7109 + attribute \src "libresoc.v:140903.3-140911.6" + process $proc$libresoc.v:140903$7419 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7110 $1\rst_l_r_rst$next[0:0]$7111 - attribute \src "libresoc.v:138426.5-138426.29" + assign $0\rst_l_r_rst$next[0:0]$7420 $1\rst_l_r_rst$next[0:0]$7421 + attribute \src "libresoc.v:140904.5-140904.29" switch \initial - attribute \src "libresoc.v:138426.9-138426.17" + attribute \src "libresoc.v:140904.9-140904.17" case 1'1 case end @@ -289819,21 +296210,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7111 1'1 + assign $1\rst_l_r_rst$next[0:0]$7421 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7111 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7421 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7110 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7420 end - attribute \src "libresoc.v:138434.3-138442.6" - process $proc$libresoc.v:138434$7112 + attribute \src "libresoc.v:140912.3-140920.6" + process $proc$libresoc.v:140912$7422 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7113 $1\opc_l_s_opc$next[0:0]$7114 - attribute \src "libresoc.v:138435.5-138435.29" + assign $0\opc_l_s_opc$next[0:0]$7423 $1\opc_l_s_opc$next[0:0]$7424 + attribute \src "libresoc.v:140913.5-140913.29" switch \initial - attribute \src "libresoc.v:138435.9-138435.17" + attribute \src "libresoc.v:140913.9-140913.17" case 1'1 case end @@ -289842,21 +296233,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7114 1'0 + assign $1\opc_l_s_opc$next[0:0]$7424 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7114 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7424 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7113 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7423 end - attribute \src "libresoc.v:138443.3-138451.6" - process $proc$libresoc.v:138443$7115 + attribute \src "libresoc.v:140921.3-140929.6" + process $proc$libresoc.v:140921$7425 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7116 $1\opc_l_r_opc$next[0:0]$7117 - attribute \src "libresoc.v:138444.5-138444.29" + assign $0\opc_l_r_opc$next[0:0]$7426 $1\opc_l_r_opc$next[0:0]$7427 + attribute \src "libresoc.v:140922.5-140922.29" switch \initial - attribute \src "libresoc.v:138444.9-138444.17" + attribute \src "libresoc.v:140922.9-140922.17" case 1'1 case end @@ -289865,21 +296256,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7117 1'1 + assign $1\opc_l_r_opc$next[0:0]$7427 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7117 \req_done + assign $1\opc_l_r_opc$next[0:0]$7427 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7116 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7426 end - attribute \src "libresoc.v:138452.3-138460.6" - process $proc$libresoc.v:138452$7118 + attribute \src "libresoc.v:140930.3-140938.6" + process $proc$libresoc.v:140930$7428 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7119 $1\src_l_s_src$next[2:0]$7120 - attribute \src "libresoc.v:138453.5-138453.29" + assign $0\src_l_s_src$next[2:0]$7429 $1\src_l_s_src$next[2:0]$7430 + attribute \src "libresoc.v:140931.5-140931.29" switch \initial - attribute \src "libresoc.v:138453.9-138453.17" + attribute \src "libresoc.v:140931.9-140931.17" case 1'1 case end @@ -289888,21 +296279,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7120 3'000 + assign $1\src_l_s_src$next[2:0]$7430 3'000 case - assign $1\src_l_s_src$next[2:0]$7120 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7430 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7119 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7429 end - attribute \src "libresoc.v:138461.3-138469.6" - process $proc$libresoc.v:138461$7121 + attribute \src "libresoc.v:140939.3-140947.6" + process $proc$libresoc.v:140939$7431 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7122 $1\src_l_r_src$next[2:0]$7123 - attribute \src "libresoc.v:138462.5-138462.29" + assign $0\src_l_r_src$next[2:0]$7432 $1\src_l_r_src$next[2:0]$7433 + attribute \src "libresoc.v:140940.5-140940.29" switch \initial - attribute \src "libresoc.v:138462.9-138462.17" + attribute \src "libresoc.v:140940.9-140940.17" case 1'1 case end @@ -289911,21 +296302,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7123 3'111 + assign $1\src_l_r_src$next[2:0]$7433 3'111 case - assign $1\src_l_r_src$next[2:0]$7123 \reset_r + assign $1\src_l_r_src$next[2:0]$7433 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7122 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7432 end - attribute \src "libresoc.v:138470.3-138478.6" - process $proc$libresoc.v:138470$7124 + attribute \src "libresoc.v:140948.3-140956.6" + process $proc$libresoc.v:140948$7434 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7125 $1\req_l_s_req$next[3:0]$7126 - attribute \src "libresoc.v:138471.5-138471.29" + assign $0\req_l_s_req$next[3:0]$7435 $1\req_l_s_req$next[3:0]$7436 + attribute \src "libresoc.v:140949.5-140949.29" switch \initial - attribute \src "libresoc.v:138471.9-138471.17" + attribute \src "libresoc.v:140949.9-140949.17" case 1'1 case end @@ -289934,21 +296325,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7126 4'0000 + assign $1\req_l_s_req$next[3:0]$7436 4'0000 case - assign $1\req_l_s_req$next[3:0]$7126 \$66 + assign $1\req_l_s_req$next[3:0]$7436 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7125 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7435 end - attribute \src "libresoc.v:138479.3-138487.6" - process $proc$libresoc.v:138479$7127 + attribute \src "libresoc.v:140957.3-140965.6" + process $proc$libresoc.v:140957$7437 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7128 $1\req_l_r_req$next[3:0]$7129 - attribute \src "libresoc.v:138480.5-138480.29" + assign $0\req_l_r_req$next[3:0]$7438 $1\req_l_r_req$next[3:0]$7439 + attribute \src "libresoc.v:140958.5-140958.29" switch \initial - attribute \src "libresoc.v:138480.9-138480.17" + attribute \src "libresoc.v:140958.9-140958.17" case 1'1 case end @@ -289957,15 +296348,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7129 4'1111 + assign $1\req_l_r_req$next[3:0]$7439 4'1111 case - assign $1\req_l_r_req$next[3:0]$7129 \$68 + assign $1\req_l_r_req$next[3:0]$7439 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7128 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7438 end - attribute \src "libresoc.v:138488.3-138520.6" - process $proc$libresoc.v:138488$7130 + attribute \src "libresoc.v:140966.3-140998.6" + process $proc$libresoc.v:140966$7440 assign { } { } assign { } { } assign { } { } @@ -289990,27 +296381,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 + assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7134 $1\alu_mul0_mul_op__insn$next[31:0]$7146 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7444 $1\alu_mul0_mul_op__insn$next[31:0]$7456 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 - attribute \src "libresoc.v:138489.5-138489.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 + attribute \src "libresoc.v:140967.5-140967.29" switch \initial - attribute \src "libresoc.v:138489.9-138489.17" + attribute \src "libresoc.v:140967.9-140967.17" case 1'1 case end @@ -290030,20 +296421,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7146 $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7456 $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7143 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7146 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7147 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7148 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7149 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7154 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7456 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -290055,48 +296446,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7155 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7144 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7156 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7145 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7157 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7150 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7158 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7151 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7159 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7152 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7160 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7153 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7131 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7132 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7133 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7134 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7135 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7136 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7137 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7138 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7139 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7140 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7141 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7142 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7444 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 end - attribute \src "libresoc.v:138521.3-138542.6" - process $proc$libresoc.v:138521$7161 + attribute \src "libresoc.v:140999.3-141020.6" + process $proc$libresoc.v:140999$7471 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7162 $2\data_r0__o$next[63:0]$7166 + assign $0\data_r0__o$next[63:0]$7472 $2\data_r0__o$next[63:0]$7476 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7163 $3\data_r0__o_ok$next[0:0]$7168 - attribute \src "libresoc.v:138522.5-138522.29" + assign $0\data_r0__o_ok$next[0:0]$7473 $3\data_r0__o_ok$next[0:0]$7478 + attribute \src "libresoc.v:141000.5-141000.29" switch \initial - attribute \src "libresoc.v:138522.9-138522.17" + attribute \src "libresoc.v:141000.9-141000.17" case 1'1 case end @@ -290106,10 +296497,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7165 $1\data_r0__o$next[63:0]$7164 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7475 $1\data_r0__o$next[63:0]$7474 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7164 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7165 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7474 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7475 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -290117,38 +296508,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7167 $2\data_r0__o$next[63:0]$7166 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7477 $2\data_r0__o$next[63:0]$7476 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7166 $1\data_r0__o$next[63:0]$7164 - assign $2\data_r0__o_ok$next[0:0]$7167 $1\data_r0__o_ok$next[0:0]$7165 + assign $2\data_r0__o$next[63:0]$7476 $1\data_r0__o$next[63:0]$7474 + assign $2\data_r0__o_ok$next[0:0]$7477 $1\data_r0__o_ok$next[0:0]$7475 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7168 1'0 + assign $3\data_r0__o_ok$next[0:0]$7478 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7168 $2\data_r0__o_ok$next[0:0]$7167 + assign $3\data_r0__o_ok$next[0:0]$7478 $2\data_r0__o_ok$next[0:0]$7477 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7162 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7163 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7472 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7473 end - attribute \src "libresoc.v:138543.3-138564.6" - process $proc$libresoc.v:138543$7169 + attribute \src "libresoc.v:141021.3-141042.6" + process $proc$libresoc.v:141021$7479 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7170 $2\data_r1__cr_a$next[3:0]$7174 + assign $0\data_r1__cr_a$next[3:0]$7480 $2\data_r1__cr_a$next[3:0]$7484 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7171 $3\data_r1__cr_a_ok$next[0:0]$7176 - attribute \src "libresoc.v:138544.5-138544.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7481 $3\data_r1__cr_a_ok$next[0:0]$7486 + attribute \src "libresoc.v:141022.5-141022.29" switch \initial - attribute \src "libresoc.v:138544.9-138544.17" + attribute \src "libresoc.v:141022.9-141022.17" case 1'1 case end @@ -290158,10 +296549,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7173 $1\data_r1__cr_a$next[3:0]$7172 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7483 $1\data_r1__cr_a$next[3:0]$7482 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7172 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7173 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7482 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7483 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -290169,38 +296560,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7175 $2\data_r1__cr_a$next[3:0]$7174 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7485 $2\data_r1__cr_a$next[3:0]$7484 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7174 $1\data_r1__cr_a$next[3:0]$7172 - assign $2\data_r1__cr_a_ok$next[0:0]$7175 $1\data_r1__cr_a_ok$next[0:0]$7173 + assign $2\data_r1__cr_a$next[3:0]$7484 $1\data_r1__cr_a$next[3:0]$7482 + assign $2\data_r1__cr_a_ok$next[0:0]$7485 $1\data_r1__cr_a_ok$next[0:0]$7483 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7176 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7486 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7176 $2\data_r1__cr_a_ok$next[0:0]$7175 + assign $3\data_r1__cr_a_ok$next[0:0]$7486 $2\data_r1__cr_a_ok$next[0:0]$7485 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7170 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7171 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7480 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7481 end - attribute \src "libresoc.v:138565.3-138586.6" - process $proc$libresoc.v:138565$7177 + attribute \src "libresoc.v:141043.3-141064.6" + process $proc$libresoc.v:141043$7487 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7178 $2\data_r2__xer_ov$next[1:0]$7182 + assign $0\data_r2__xer_ov$next[1:0]$7488 $2\data_r2__xer_ov$next[1:0]$7492 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7179 $3\data_r2__xer_ov_ok$next[0:0]$7184 - attribute \src "libresoc.v:138566.5-138566.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7489 $3\data_r2__xer_ov_ok$next[0:0]$7494 + attribute \src "libresoc.v:141044.5-141044.29" switch \initial - attribute \src "libresoc.v:138566.9-138566.17" + attribute \src "libresoc.v:141044.9-141044.17" case 1'1 case end @@ -290210,10 +296601,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7181 $1\data_r2__xer_ov$next[1:0]$7180 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7491 $1\data_r2__xer_ov$next[1:0]$7490 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7180 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7181 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7490 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7491 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -290221,38 +296612,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7183 $2\data_r2__xer_ov$next[1:0]$7182 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7493 $2\data_r2__xer_ov$next[1:0]$7492 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7182 $1\data_r2__xer_ov$next[1:0]$7180 - assign $2\data_r2__xer_ov_ok$next[0:0]$7183 $1\data_r2__xer_ov_ok$next[0:0]$7181 + assign $2\data_r2__xer_ov$next[1:0]$7492 $1\data_r2__xer_ov$next[1:0]$7490 + assign $2\data_r2__xer_ov_ok$next[0:0]$7493 $1\data_r2__xer_ov_ok$next[0:0]$7491 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7184 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7494 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7184 $2\data_r2__xer_ov_ok$next[0:0]$7183 + assign $3\data_r2__xer_ov_ok$next[0:0]$7494 $2\data_r2__xer_ov_ok$next[0:0]$7493 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7178 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7179 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7488 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7489 end - attribute \src "libresoc.v:138587.3-138608.6" - process $proc$libresoc.v:138587$7185 + attribute \src "libresoc.v:141065.3-141086.6" + process $proc$libresoc.v:141065$7495 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7186 $2\data_r3__xer_so$next[0:0]$7190 + assign $0\data_r3__xer_so$next[0:0]$7496 $2\data_r3__xer_so$next[0:0]$7500 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7187 $3\data_r3__xer_so_ok$next[0:0]$7192 - attribute \src "libresoc.v:138588.5-138588.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7497 $3\data_r3__xer_so_ok$next[0:0]$7502 + attribute \src "libresoc.v:141066.5-141066.29" switch \initial - attribute \src "libresoc.v:138588.9-138588.17" + attribute \src "libresoc.v:141066.9-141066.17" case 1'1 case end @@ -290262,10 +296653,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7189 $1\data_r3__xer_so$next[0:0]$7188 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7499 $1\data_r3__xer_so$next[0:0]$7498 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7188 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7189 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7498 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7499 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -290273,32 +296664,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7191 $2\data_r3__xer_so$next[0:0]$7190 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7501 $2\data_r3__xer_so$next[0:0]$7500 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7190 $1\data_r3__xer_so$next[0:0]$7188 - assign $2\data_r3__xer_so_ok$next[0:0]$7191 $1\data_r3__xer_so_ok$next[0:0]$7189 + assign $2\data_r3__xer_so$next[0:0]$7500 $1\data_r3__xer_so$next[0:0]$7498 + assign $2\data_r3__xer_so_ok$next[0:0]$7501 $1\data_r3__xer_so_ok$next[0:0]$7499 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7192 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7502 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7192 $2\data_r3__xer_so_ok$next[0:0]$7191 + assign $3\data_r3__xer_so_ok$next[0:0]$7502 $2\data_r3__xer_so_ok$next[0:0]$7501 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7186 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7187 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7496 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7497 end - attribute \src "libresoc.v:138609.3-138618.6" - process $proc$libresoc.v:138609$7193 + attribute \src "libresoc.v:141087.3-141096.6" + process $proc$libresoc.v:141087$7503 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7194 $1\src_r0$next[63:0]$7195 - attribute \src "libresoc.v:138610.5-138610.29" + assign $0\src_r0$next[63:0]$7504 $1\src_r0$next[63:0]$7505 + attribute \src "libresoc.v:141088.5-141088.29" switch \initial - attribute \src "libresoc.v:138610.9-138610.17" + attribute \src "libresoc.v:141088.9-141088.17" case 1'1 case end @@ -290307,21 +296698,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7195 \src1_i + assign $1\src_r0$next[63:0]$7505 \src1_i case - assign $1\src_r0$next[63:0]$7195 \src_r0 + assign $1\src_r0$next[63:0]$7505 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7194 + update \src_r0$next $0\src_r0$next[63:0]$7504 end - attribute \src "libresoc.v:138619.3-138628.6" - process $proc$libresoc.v:138619$7196 + attribute \src "libresoc.v:141097.3-141106.6" + process $proc$libresoc.v:141097$7506 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7197 $1\src_r1$next[63:0]$7198 - attribute \src "libresoc.v:138620.5-138620.29" + assign $0\src_r1$next[63:0]$7507 $1\src_r1$next[63:0]$7508 + attribute \src "libresoc.v:141098.5-141098.29" switch \initial - attribute \src "libresoc.v:138620.9-138620.17" + attribute \src "libresoc.v:141098.9-141098.17" case 1'1 case end @@ -290330,21 +296721,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7198 \src_or_imm + assign $1\src_r1$next[63:0]$7508 \src_or_imm case - assign $1\src_r1$next[63:0]$7198 \src_r1 + assign $1\src_r1$next[63:0]$7508 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7197 + update \src_r1$next $0\src_r1$next[63:0]$7507 end - attribute \src "libresoc.v:138629.3-138638.6" - process $proc$libresoc.v:138629$7199 + attribute \src "libresoc.v:141107.3-141116.6" + process $proc$libresoc.v:141107$7509 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7200 $1\src_r2$next[0:0]$7201 - attribute \src "libresoc.v:138630.5-138630.29" + assign $0\src_r2$next[0:0]$7510 $1\src_r2$next[0:0]$7511 + attribute \src "libresoc.v:141108.5-141108.29" switch \initial - attribute \src "libresoc.v:138630.9-138630.17" + attribute \src "libresoc.v:141108.9-141108.17" case 1'1 case end @@ -290353,21 +296744,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7201 \src3_i + assign $1\src_r2$next[0:0]$7511 \src3_i case - assign $1\src_r2$next[0:0]$7201 \src_r2 + assign $1\src_r2$next[0:0]$7511 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7200 + update \src_r2$next $0\src_r2$next[0:0]$7510 end - attribute \src "libresoc.v:138639.3-138647.6" - process $proc$libresoc.v:138639$7202 + attribute \src "libresoc.v:141117.3-141125.6" + process $proc$libresoc.v:141117$7512 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7203 $1\alui_l_r_alui$next[0:0]$7204 - attribute \src "libresoc.v:138640.5-138640.29" + assign $0\alui_l_r_alui$next[0:0]$7513 $1\alui_l_r_alui$next[0:0]$7514 + attribute \src "libresoc.v:141118.5-141118.29" switch \initial - attribute \src "libresoc.v:138640.9-138640.17" + attribute \src "libresoc.v:141118.9-141118.17" case 1'1 case end @@ -290376,21 +296767,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7204 1'1 + assign $1\alui_l_r_alui$next[0:0]$7514 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7204 \$88 + assign $1\alui_l_r_alui$next[0:0]$7514 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7203 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7513 end - attribute \src "libresoc.v:138648.3-138656.6" - process $proc$libresoc.v:138648$7205 + attribute \src "libresoc.v:141126.3-141134.6" + process $proc$libresoc.v:141126$7515 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7206 $1\alu_l_r_alu$next[0:0]$7207 - attribute \src "libresoc.v:138649.5-138649.29" + assign $0\alu_l_r_alu$next[0:0]$7516 $1\alu_l_r_alu$next[0:0]$7517 + attribute \src "libresoc.v:141127.5-141127.29" switch \initial - attribute \src "libresoc.v:138649.9-138649.17" + attribute \src "libresoc.v:141127.9-141127.17" case 1'1 case end @@ -290399,21 +296790,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7207 1'1 + assign $1\alu_l_r_alu$next[0:0]$7517 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7207 \$90 + assign $1\alu_l_r_alu$next[0:0]$7517 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7206 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7516 end - attribute \src "libresoc.v:138657.3-138666.6" - process $proc$libresoc.v:138657$7208 + attribute \src "libresoc.v:141135.3-141144.6" + process $proc$libresoc.v:141135$7518 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:138658.5-138658.29" + attribute \src "libresoc.v:141136.5-141136.29" switch \initial - attribute \src "libresoc.v:138658.9-138658.17" + attribute \src "libresoc.v:141136.9-141136.17" case 1'1 case end @@ -290429,14 +296820,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:138667.3-138676.6" - process $proc$libresoc.v:138667$7209 + attribute \src "libresoc.v:141145.3-141154.6" + process $proc$libresoc.v:141145$7519 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:138668.5-138668.29" + attribute \src "libresoc.v:141146.5-141146.29" switch \initial - attribute \src "libresoc.v:138668.9-138668.17" + attribute \src "libresoc.v:141146.9-141146.17" case 1'1 case end @@ -290452,14 +296843,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:138677.3-138686.6" - process $proc$libresoc.v:138677$7210 + attribute \src "libresoc.v:141155.3-141164.6" + process $proc$libresoc.v:141155$7520 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:138678.5-138678.29" + attribute \src "libresoc.v:141156.5-141156.29" switch \initial - attribute \src "libresoc.v:138678.9-138678.17" + attribute \src "libresoc.v:141156.9-141156.17" case 1'1 case end @@ -290475,14 +296866,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:138687.3-138696.6" - process $proc$libresoc.v:138687$7211 + attribute \src "libresoc.v:141165.3-141174.6" + process $proc$libresoc.v:141165$7521 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:138688.5-138688.29" + attribute \src "libresoc.v:141166.5-141166.29" switch \initial - attribute \src "libresoc.v:138688.9-138688.17" + attribute \src "libresoc.v:141166.9-141166.17" case 1'1 case end @@ -290498,14 +296889,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:138697.3-138705.6" - process $proc$libresoc.v:138697$7212 + attribute \src "libresoc.v:141175.3-141183.6" + process $proc$libresoc.v:141175$7522 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7213 $1\prev_wr_go$next[3:0]$7214 - attribute \src "libresoc.v:138698.5-138698.29" + assign $0\prev_wr_go$next[3:0]$7523 $1\prev_wr_go$next[3:0]$7524 + attribute \src "libresoc.v:141176.5-141176.29" switch \initial - attribute \src "libresoc.v:138698.9-138698.17" + attribute \src "libresoc.v:141176.9-141176.17" case 1'1 case end @@ -290514,73 +296905,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7214 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7214 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7213 - end - connect \$100 $and$libresoc.v:138173$7001_Y - connect \$102 $and$libresoc.v:138174$7002_Y - connect \$104 $and$libresoc.v:138175$7003_Y - connect \$106 $and$libresoc.v:138176$7004_Y - connect \$108 $and$libresoc.v:138177$7005_Y - connect \$10 $and$libresoc.v:138178$7006_Y - connect \$110 $and$libresoc.v:138179$7007_Y - connect \$112 $and$libresoc.v:138180$7008_Y - connect \$114 $and$libresoc.v:138181$7009_Y - connect \$116 $and$libresoc.v:138182$7010_Y - connect \$118 $and$libresoc.v:138183$7011_Y - connect \$120 $and$libresoc.v:138184$7012_Y - connect \$12 $not$libresoc.v:138185$7013_Y - connect \$14 $and$libresoc.v:138186$7014_Y - connect \$16 $not$libresoc.v:138187$7015_Y - connect \$18 $and$libresoc.v:138188$7016_Y - connect \$20 $and$libresoc.v:138189$7017_Y - connect \$24 $not$libresoc.v:138190$7018_Y - connect \$26 $and$libresoc.v:138191$7019_Y - connect \$23 $reduce_or$libresoc.v:138192$7020_Y - connect \$22 $not$libresoc.v:138193$7021_Y - connect \$2 $and$libresoc.v:138194$7022_Y - connect \$30 $and$libresoc.v:138195$7023_Y - connect \$32 $reduce_or$libresoc.v:138196$7024_Y - connect \$34 $reduce_or$libresoc.v:138197$7025_Y - connect \$36 $or$libresoc.v:138198$7026_Y - connect \$38 $not$libresoc.v:138199$7027_Y - connect \$40 $and$libresoc.v:138200$7028_Y - connect \$42 $and$libresoc.v:138201$7029_Y - connect \$44 $eq$libresoc.v:138202$7030_Y - connect \$46 $and$libresoc.v:138203$7031_Y - connect \$48 $eq$libresoc.v:138204$7032_Y - connect \$50 $and$libresoc.v:138205$7033_Y - connect \$52 $and$libresoc.v:138206$7034_Y - connect \$54 $and$libresoc.v:138207$7035_Y - connect \$56 $or$libresoc.v:138208$7036_Y - connect \$58 $or$libresoc.v:138209$7037_Y - connect \$5 $not$libresoc.v:138210$7038_Y - connect \$60 $or$libresoc.v:138211$7039_Y - connect \$62 $or$libresoc.v:138212$7040_Y - connect \$64 $and$libresoc.v:138213$7041_Y - connect \$66 $and$libresoc.v:138214$7042_Y - connect \$68 $or$libresoc.v:138215$7043_Y - connect \$70 $and$libresoc.v:138216$7044_Y - connect \$72 $and$libresoc.v:138217$7045_Y - connect \$74 $and$libresoc.v:138218$7046_Y - connect \$76 $and$libresoc.v:138219$7047_Y - connect \$78 $ternary$libresoc.v:138220$7048_Y - connect \$7 $or$libresoc.v:138221$7049_Y - connect \$80 $ternary$libresoc.v:138222$7050_Y - connect \$82 $ternary$libresoc.v:138223$7051_Y - connect \$84 $ternary$libresoc.v:138224$7052_Y - connect \$86 $ternary$libresoc.v:138225$7053_Y - connect \$88 $and$libresoc.v:138226$7054_Y - connect \$4 $reduce_and$libresoc.v:138227$7055_Y - connect \$90 $and$libresoc.v:138228$7056_Y - connect \$92 $and$libresoc.v:138229$7057_Y - connect \$94 $not$libresoc.v:138230$7058_Y - connect \$96 $and$libresoc.v:138231$7059_Y - connect \$98 $not$libresoc.v:138232$7060_Y + assign $1\prev_wr_go$next[3:0]$7524 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7524 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7523 + end + connect \$100 $and$libresoc.v:140651$7311_Y + connect \$102 $and$libresoc.v:140652$7312_Y + connect \$104 $and$libresoc.v:140653$7313_Y + connect \$106 $and$libresoc.v:140654$7314_Y + connect \$108 $and$libresoc.v:140655$7315_Y + connect \$10 $and$libresoc.v:140656$7316_Y + connect \$110 $and$libresoc.v:140657$7317_Y + connect \$112 $and$libresoc.v:140658$7318_Y + connect \$114 $and$libresoc.v:140659$7319_Y + connect \$116 $and$libresoc.v:140660$7320_Y + connect \$118 $and$libresoc.v:140661$7321_Y + connect \$120 $and$libresoc.v:140662$7322_Y + connect \$12 $not$libresoc.v:140663$7323_Y + connect \$14 $and$libresoc.v:140664$7324_Y + connect \$16 $not$libresoc.v:140665$7325_Y + connect \$18 $and$libresoc.v:140666$7326_Y + connect \$20 $and$libresoc.v:140667$7327_Y + connect \$24 $not$libresoc.v:140668$7328_Y + connect \$26 $and$libresoc.v:140669$7329_Y + connect \$23 $reduce_or$libresoc.v:140670$7330_Y + connect \$22 $not$libresoc.v:140671$7331_Y + connect \$2 $and$libresoc.v:140672$7332_Y + connect \$30 $and$libresoc.v:140673$7333_Y + connect \$32 $reduce_or$libresoc.v:140674$7334_Y + connect \$34 $reduce_or$libresoc.v:140675$7335_Y + connect \$36 $or$libresoc.v:140676$7336_Y + connect \$38 $not$libresoc.v:140677$7337_Y + connect \$40 $and$libresoc.v:140678$7338_Y + connect \$42 $and$libresoc.v:140679$7339_Y + connect \$44 $eq$libresoc.v:140680$7340_Y + connect \$46 $and$libresoc.v:140681$7341_Y + connect \$48 $eq$libresoc.v:140682$7342_Y + connect \$50 $and$libresoc.v:140683$7343_Y + connect \$52 $and$libresoc.v:140684$7344_Y + connect \$54 $and$libresoc.v:140685$7345_Y + connect \$56 $or$libresoc.v:140686$7346_Y + connect \$58 $or$libresoc.v:140687$7347_Y + connect \$5 $not$libresoc.v:140688$7348_Y + connect \$60 $or$libresoc.v:140689$7349_Y + connect \$62 $or$libresoc.v:140690$7350_Y + connect \$64 $and$libresoc.v:140691$7351_Y + connect \$66 $and$libresoc.v:140692$7352_Y + connect \$68 $or$libresoc.v:140693$7353_Y + connect \$70 $and$libresoc.v:140694$7354_Y + connect \$72 $and$libresoc.v:140695$7355_Y + connect \$74 $and$libresoc.v:140696$7356_Y + connect \$76 $and$libresoc.v:140697$7357_Y + connect \$78 $ternary$libresoc.v:140698$7358_Y + connect \$7 $or$libresoc.v:140699$7359_Y + connect \$80 $ternary$libresoc.v:140700$7360_Y + connect \$82 $ternary$libresoc.v:140701$7361_Y + connect \$84 $ternary$libresoc.v:140702$7362_Y + connect \$86 $ternary$libresoc.v:140703$7363_Y + connect \$88 $and$libresoc.v:140704$7364_Y + connect \$4 $reduce_and$libresoc.v:140705$7365_Y + connect \$90 $and$libresoc.v:140706$7366_Y + connect \$92 $and$libresoc.v:140707$7367_Y + connect \$94 $not$libresoc.v:140708$7368_Y + connect \$96 $and$libresoc.v:140709$7369_Y + connect \$98 $not$libresoc.v:140710$7370_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -290612,51 +297003,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:138740.1-139067.10" +attribute \src "libresoc.v:141218.1-141545.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:139034.18-139034.116" - wire $and$libresoc.v:139034$7255_Y - attribute \src "libresoc.v:139036.18-139036.116" - wire $and$libresoc.v:139036$7257_Y - attribute \src "libresoc.v:139037.18-139037.117" - wire $and$libresoc.v:139037$7258_Y - attribute \src "libresoc.v:139038.18-139038.117" - wire $and$libresoc.v:139038$7259_Y - attribute \src "libresoc.v:139041.18-139041.95" - wire width 65 $extend$libresoc.v:139041$7262_Y - attribute \src "libresoc.v:139042.18-139042.91" - wire width 65 $extend$libresoc.v:139042$7264_Y - attribute \src "libresoc.v:139044.18-139044.95" - wire width 65 $extend$libresoc.v:139044$7267_Y - attribute \src "libresoc.v:139045.18-139045.91" - wire width 65 $extend$libresoc.v:139045$7269_Y - attribute \src "libresoc.v:139041.18-139041.95" - wire width 65 $neg$libresoc.v:139041$7263_Y - attribute \src "libresoc.v:139044.18-139044.95" - wire width 65 $neg$libresoc.v:139044$7268_Y - attribute \src "libresoc.v:139042.18-139042.91" - wire width 65 $pos$libresoc.v:139042$7265_Y - attribute \src "libresoc.v:139045.18-139045.91" - wire width 65 $pos$libresoc.v:139045$7270_Y - attribute \src "libresoc.v:139033.18-139033.125" - wire $ternary$libresoc.v:139033$7254_Y - attribute \src "libresoc.v:139035.18-139035.125" - wire $ternary$libresoc.v:139035$7256_Y - attribute \src "libresoc.v:139043.18-139043.112" - wire width 65 $ternary$libresoc.v:139043$7266_Y - attribute \src "libresoc.v:139046.18-139046.112" - wire width 65 $ternary$libresoc.v:139046$7271_Y - attribute \src "libresoc.v:139047.18-139047.116" - wire width 32 $ternary$libresoc.v:139047$7272_Y - attribute \src "libresoc.v:139048.18-139048.116" - wire width 32 $ternary$libresoc.v:139048$7273_Y - attribute \src "libresoc.v:139039.18-139039.106" - wire $xor$libresoc.v:139039$7260_Y - attribute \src "libresoc.v:139040.18-139040.110" - wire $xor$libresoc.v:139040$7261_Y + attribute \src "libresoc.v:141512.18-141512.116" + wire $and$libresoc.v:141512$7565_Y + attribute \src "libresoc.v:141514.18-141514.116" + wire $and$libresoc.v:141514$7567_Y + attribute \src "libresoc.v:141515.18-141515.117" + wire $and$libresoc.v:141515$7568_Y + attribute \src "libresoc.v:141516.18-141516.117" + wire $and$libresoc.v:141516$7569_Y + attribute \src "libresoc.v:141519.18-141519.95" + wire width 65 $extend$libresoc.v:141519$7572_Y + attribute \src "libresoc.v:141520.18-141520.91" + wire width 65 $extend$libresoc.v:141520$7574_Y + attribute \src "libresoc.v:141522.18-141522.95" + wire width 65 $extend$libresoc.v:141522$7577_Y + attribute \src "libresoc.v:141523.18-141523.91" + wire width 65 $extend$libresoc.v:141523$7579_Y + attribute \src "libresoc.v:141519.18-141519.95" + wire width 65 $neg$libresoc.v:141519$7573_Y + attribute \src "libresoc.v:141522.18-141522.95" + wire width 65 $neg$libresoc.v:141522$7578_Y + attribute \src "libresoc.v:141520.18-141520.91" + wire width 65 $pos$libresoc.v:141520$7575_Y + attribute \src "libresoc.v:141523.18-141523.91" + wire width 65 $pos$libresoc.v:141523$7580_Y + attribute \src "libresoc.v:141511.18-141511.125" + wire $ternary$libresoc.v:141511$7564_Y + attribute \src "libresoc.v:141513.18-141513.125" + wire $ternary$libresoc.v:141513$7566_Y + attribute \src "libresoc.v:141521.18-141521.112" + wire width 65 $ternary$libresoc.v:141521$7576_Y + attribute \src "libresoc.v:141524.18-141524.112" + wire width 65 $ternary$libresoc.v:141524$7581_Y + attribute \src "libresoc.v:141525.18-141525.116" + wire width 32 $ternary$libresoc.v:141525$7582_Y + attribute \src "libresoc.v:141526.18-141526.116" + wire width 32 $ternary$libresoc.v:141526$7583_Y + attribute \src "libresoc.v:141517.18-141517.106" + wire $xor$libresoc.v:141517$7570_Y + attribute \src "libresoc.v:141518.18-141518.110" + wire $xor$libresoc.v:141518$7571_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -290950,7 +297341,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:139034$7255 + cell $and $and$libresoc.v:141512$7565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290958,10 +297349,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:139034$7255_Y + connect \Y $and$libresoc.v:141512$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:139036$7257 + cell $and $and$libresoc.v:141514$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290969,10 +297360,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:139036$7257_Y + connect \Y $and$libresoc.v:141514$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:139037$7258 + cell $and $and$libresoc.v:141515$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290980,10 +297371,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:139037$7258_Y + connect \Y $and$libresoc.v:141515$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:139038$7259 + cell $and $and$libresoc.v:141516$7569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -290991,122 +297382,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:139038$7259_Y + connect \Y $and$libresoc.v:141516$7569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:139041$7262 + cell $pos $extend$libresoc.v:141519$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:139041$7262_Y + connect \Y $extend$libresoc.v:141519$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139042$7264 + cell $pos $extend$libresoc.v:141520$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:139042$7264_Y + connect \Y $extend$libresoc.v:141520$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:139044$7267 + cell $pos $extend$libresoc.v:141522$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:139044$7267_Y + connect \Y $extend$libresoc.v:141522$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139045$7269 + cell $pos $extend$libresoc.v:141523$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:139045$7269_Y + connect \Y $extend$libresoc.v:141523$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:139041$7263 + cell $neg $neg$libresoc.v:141519$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139041$7262_Y - connect \Y $neg$libresoc.v:139041$7263_Y + connect \A $extend$libresoc.v:141519$7572_Y + connect \Y $neg$libresoc.v:141519$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:139044$7268 + cell $neg $neg$libresoc.v:141522$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139044$7267_Y - connect \Y $neg$libresoc.v:139044$7268_Y + connect \A $extend$libresoc.v:141522$7577_Y + connect \Y $neg$libresoc.v:141522$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139042$7265 + cell $pos $pos$libresoc.v:141520$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139042$7264_Y - connect \Y $pos$libresoc.v:139042$7265_Y + connect \A $extend$libresoc.v:141520$7574_Y + connect \Y $pos$libresoc.v:141520$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139045$7270 + cell $pos $pos$libresoc.v:141523$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139045$7269_Y - connect \Y $pos$libresoc.v:139045$7270_Y + connect \A $extend$libresoc.v:141523$7579_Y + connect \Y $pos$libresoc.v:141523$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:139033$7254 + cell $mux $ternary$libresoc.v:141511$7564 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:139033$7254_Y + connect \Y $ternary$libresoc.v:141511$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:139035$7256 + cell $mux $ternary$libresoc.v:141513$7566 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:139035$7256_Y + connect \Y $ternary$libresoc.v:141513$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:139043$7266 + cell $mux $ternary$libresoc.v:141521$7576 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:139043$7266_Y + connect \Y $ternary$libresoc.v:141521$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:139046$7271 + cell $mux $ternary$libresoc.v:141524$7581 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:139046$7271_Y + connect \Y $ternary$libresoc.v:141524$7581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:139047$7272 + cell $mux $ternary$libresoc.v:141525$7582 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:139047$7272_Y + connect \Y $ternary$libresoc.v:141525$7582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:139048$7273 + cell $mux $ternary$libresoc.v:141526$7583 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:139048$7273_Y + connect \Y $ternary$libresoc.v:141526$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:139039$7260 + cell $xor $xor$libresoc.v:141517$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -291114,10 +297505,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:139039$7260_Y + connect \Y $xor$libresoc.v:141517$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:139040$7261 + cell $xor $xor$libresoc.v:141518$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -291125,24 +297516,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:139040$7261_Y - end - connect \$17 $ternary$libresoc.v:139033$7254_Y - connect \$19 $and$libresoc.v:139034$7255_Y - connect \$21 $ternary$libresoc.v:139035$7256_Y - connect \$23 $and$libresoc.v:139036$7257_Y - connect \$25 $and$libresoc.v:139037$7258_Y - connect \$27 $and$libresoc.v:139038$7259_Y - connect \$29 $xor$libresoc.v:139039$7260_Y - connect \$31 $xor$libresoc.v:139040$7261_Y - connect \$34 $neg$libresoc.v:139041$7263_Y - connect \$36 $pos$libresoc.v:139042$7265_Y - connect \$38 $ternary$libresoc.v:139043$7266_Y - connect \$41 $neg$libresoc.v:139044$7268_Y - connect \$43 $pos$libresoc.v:139045$7270_Y - connect \$45 $ternary$libresoc.v:139046$7271_Y - connect \$47 $ternary$libresoc.v:139047$7272_Y - connect \$49 $ternary$libresoc.v:139048$7273_Y + connect \Y $xor$libresoc.v:141518$7571_Y + end + connect \$17 $ternary$libresoc.v:141511$7564_Y + connect \$19 $and$libresoc.v:141512$7565_Y + connect \$21 $ternary$libresoc.v:141513$7566_Y + connect \$23 $and$libresoc.v:141514$7567_Y + connect \$25 $and$libresoc.v:141515$7568_Y + connect \$27 $and$libresoc.v:141516$7569_Y + connect \$29 $xor$libresoc.v:141517$7570_Y + connect \$31 $xor$libresoc.v:141518$7571_Y + connect \$34 $neg$libresoc.v:141519$7573_Y + connect \$36 $pos$libresoc.v:141520$7575_Y + connect \$38 $ternary$libresoc.v:141521$7576_Y + connect \$41 $neg$libresoc.v:141522$7578_Y + connect \$43 $pos$libresoc.v:141523$7580_Y + connect \$45 $ternary$libresoc.v:141524$7581_Y + connect \$47 $ternary$libresoc.v:141525$7582_Y + connect \$49 $ternary$libresoc.v:141526$7583_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -291162,17 +297553,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:139071.1-139328.10" +attribute \src "libresoc.v:141549.1-141806.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:139321.18-139321.98" - wire width 129 $extend$libresoc.v:139321$7275_Y - attribute \src "libresoc.v:139320.18-139320.99" - wire width 128 $mul$libresoc.v:139320$7274_Y - attribute \src "libresoc.v:139321.18-139321.98" - wire width 129 $pos$libresoc.v:139321$7276_Y + attribute \src "libresoc.v:141799.18-141799.98" + wire width 129 $extend$libresoc.v:141799$7585_Y + attribute \src "libresoc.v:141798.18-141798.99" + wire width 128 $mul$libresoc.v:141798$7584_Y + attribute \src "libresoc.v:141799.18-141799.98" + wire width 129 $pos$libresoc.v:141799$7586_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -291422,15 +297813,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:139321$7275 + cell $pos $extend$libresoc.v:141799$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:139321$7275_Y + connect \Y $extend$libresoc.v:141799$7585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:139320$7274 + cell $mul $mul$libresoc.v:141798$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -291438,18 +297829,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:139320$7274_Y + connect \Y $mul$libresoc.v:141798$7584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:139321$7276 + cell $pos $pos$libresoc.v:141799$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:139321$7275_Y - connect \Y $pos$libresoc.v:139321$7276_Y + connect \A $extend$libresoc.v:141799$7585_Y + connect \Y $pos$libresoc.v:141799$7586_Y end - connect \$18 $mul$libresoc.v:139320$7274_Y - connect \$17 $pos$libresoc.v:139321$7276_Y + connect \$18 $mul$libresoc.v:141798$7584_Y + connect \$17 $pos$libresoc.v:141799$7586_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -291457,65 +297848,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:139332.1-139711.10" +attribute \src "libresoc.v:141810.1-142189.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:139333.7-139333.20" + attribute \src "libresoc.v:141811.7-141811.20" wire $0\initial[0:0] - attribute \src "libresoc.v:139664.3-139682.6" + attribute \src "libresoc.v:142142.3-142160.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:139626.3-139644.6" - wire width 64 $0\o$14[63:0]$7293 - attribute \src "libresoc.v:139645.3-139663.6" + attribute \src "libresoc.v:142104.3-142122.6" + wire width 64 $0\o$14[63:0]$7603 + attribute \src "libresoc.v:142123.3-142141.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:139683.3-139693.6" + attribute \src "libresoc.v:142161.3-142171.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:139694.3-139704.6" + attribute \src "libresoc.v:142172.3-142182.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:139664.3-139682.6" + attribute \src "libresoc.v:142142.3-142160.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:139626.3-139644.6" - wire width 64 $1\o$14[63:0]$7294 - attribute \src "libresoc.v:139645.3-139663.6" + attribute \src "libresoc.v:142104.3-142122.6" + wire width 64 $1\o$14[63:0]$7604 + attribute \src "libresoc.v:142123.3-142141.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:139683.3-139693.6" + attribute \src "libresoc.v:142161.3-142171.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:139694.3-139704.6" + attribute \src "libresoc.v:142172.3-142182.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:139664.3-139682.6" + attribute \src "libresoc.v:142142.3-142160.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:139620.18-139620.104" - wire $and$libresoc.v:139620$7285_Y - attribute \src "libresoc.v:139624.18-139624.104" - wire $and$libresoc.v:139624$7289_Y - attribute \src "libresoc.v:139614.18-139614.95" - wire width 130 $extend$libresoc.v:139614$7277_Y - attribute \src "libresoc.v:139615.18-139615.90" - wire width 130 $extend$libresoc.v:139615$7279_Y - attribute \src "libresoc.v:139625.18-139625.95" - wire width 2 $extend$libresoc.v:139625$7290_Y - attribute \src "libresoc.v:139614.18-139614.95" - wire width 130 $neg$libresoc.v:139614$7278_Y - attribute \src "libresoc.v:139619.18-139619.98" - wire $not$libresoc.v:139619$7284_Y - attribute \src "libresoc.v:139623.18-139623.98" - wire $not$libresoc.v:139623$7288_Y - attribute \src "libresoc.v:139615.18-139615.90" - wire width 130 $pos$libresoc.v:139615$7280_Y - attribute \src "libresoc.v:139625.18-139625.95" - wire width 2 $pos$libresoc.v:139625$7291_Y - attribute \src "libresoc.v:139618.18-139618.106" - wire $reduce_and$libresoc.v:139618$7283_Y - attribute \src "libresoc.v:139622.18-139622.107" - wire $reduce_and$libresoc.v:139622$7287_Y - attribute \src "libresoc.v:139617.18-139617.106" - wire $reduce_or$libresoc.v:139617$7282_Y - attribute \src "libresoc.v:139621.18-139621.107" - wire $reduce_or$libresoc.v:139621$7286_Y - attribute \src "libresoc.v:139616.18-139616.114" - wire width 130 $ternary$libresoc.v:139616$7281_Y + attribute \src "libresoc.v:142098.18-142098.104" + wire $and$libresoc.v:142098$7595_Y + attribute \src "libresoc.v:142102.18-142102.104" + wire $and$libresoc.v:142102$7599_Y + attribute \src "libresoc.v:142092.18-142092.95" + wire width 130 $extend$libresoc.v:142092$7587_Y + attribute \src "libresoc.v:142093.18-142093.90" + wire width 130 $extend$libresoc.v:142093$7589_Y + attribute \src "libresoc.v:142103.18-142103.95" + wire width 2 $extend$libresoc.v:142103$7600_Y + attribute \src "libresoc.v:142092.18-142092.95" + wire width 130 $neg$libresoc.v:142092$7588_Y + attribute \src "libresoc.v:142097.18-142097.98" + wire $not$libresoc.v:142097$7594_Y + attribute \src "libresoc.v:142101.18-142101.98" + wire $not$libresoc.v:142101$7598_Y + attribute \src "libresoc.v:142093.18-142093.90" + wire width 130 $pos$libresoc.v:142093$7590_Y + attribute \src "libresoc.v:142103.18-142103.95" + wire width 2 $pos$libresoc.v:142103$7601_Y + attribute \src "libresoc.v:142096.18-142096.106" + wire $reduce_and$libresoc.v:142096$7593_Y + attribute \src "libresoc.v:142100.18-142100.107" + wire $reduce_and$libresoc.v:142100$7597_Y + attribute \src "libresoc.v:142095.18-142095.106" + wire $reduce_or$libresoc.v:142095$7592_Y + attribute \src "libresoc.v:142099.18-142099.107" + wire $reduce_or$libresoc.v:142099$7596_Y + attribute \src "libresoc.v:142094.18-142094.114" + wire width 130 $ternary$libresoc.v:142094$7591_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -291542,7 +297933,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:139333.7-139333.15" + attribute \src "libresoc.v:141811.7-141811.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -291780,22 +298171,22 @@ module \mul3 wire input 15 \neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:139620$7285 + cell $and $and$libresoc.v:142098$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -291803,10 +298194,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:139620$7285_Y + connect \Y $and$libresoc.v:142098$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:139624$7289 + cell $and $and$libresoc.v:142102$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -291814,128 +298205,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:139624$7289_Y + connect \Y $and$libresoc.v:142102$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:139614$7277 + cell $pos $extend$libresoc.v:142092$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:139614$7277_Y + connect \Y $extend$libresoc.v:142092$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139615$7279 + cell $pos $extend$libresoc.v:142093$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:139615$7279_Y + connect \Y $extend$libresoc.v:142093$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139625$7290 + cell $pos $extend$libresoc.v:142103$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:139625$7290_Y + connect \Y $extend$libresoc.v:142103$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:139614$7278 + cell $neg $neg$libresoc.v:142092$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:139614$7277_Y - connect \Y $neg$libresoc.v:139614$7278_Y + connect \A $extend$libresoc.v:142092$7587_Y + connect \Y $neg$libresoc.v:142092$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:139619$7284 + cell $not $not$libresoc.v:142097$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:139619$7284_Y + connect \Y $not$libresoc.v:142097$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:139623$7288 + cell $not $not$libresoc.v:142101$7598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:139623$7288_Y + connect \Y $not$libresoc.v:142101$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139615$7280 + cell $pos $pos$libresoc.v:142093$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:139615$7279_Y - connect \Y $pos$libresoc.v:139615$7280_Y + connect \A $extend$libresoc.v:142093$7589_Y + connect \Y $pos$libresoc.v:142093$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139625$7291 + cell $pos $pos$libresoc.v:142103$7601 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:139625$7290_Y - connect \Y $pos$libresoc.v:139625$7291_Y + connect \A $extend$libresoc.v:142103$7600_Y + connect \Y $pos$libresoc.v:142103$7601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:139618$7283 + cell $reduce_and $reduce_and$libresoc.v:142096$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:139618$7283_Y + connect \Y $reduce_and$libresoc.v:142096$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:139622$7287 + cell $reduce_and $reduce_and$libresoc.v:142100$7597 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:139622$7287_Y + connect \Y $reduce_and$libresoc.v:142100$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:139617$7282 + cell $reduce_or $reduce_or$libresoc.v:142095$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:139617$7282_Y + connect \Y $reduce_or$libresoc.v:142095$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:139621$7286 + cell $reduce_or $reduce_or$libresoc.v:142099$7596 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:139621$7286_Y + connect \Y $reduce_or$libresoc.v:142099$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:139616$7281 + cell $mux $ternary$libresoc.v:142094$7591 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:139616$7281_Y + connect \Y $ternary$libresoc.v:142094$7591_Y end - attribute \src "libresoc.v:139333.7-139333.20" - process $proc$libresoc.v:139333$7299 + attribute \src "libresoc.v:141811.7-141811.20" + process $proc$libresoc.v:141811$7609 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:139626.3-139644.6" - process $proc$libresoc.v:139626$7292 + attribute \src "libresoc.v:142104.3-142122.6" + process $proc$libresoc.v:142104$7602 assign { } { } assign { } { } - assign $0\o$14[63:0]$7293 $1\o$14[63:0]$7294 - attribute \src "libresoc.v:139627.5-139627.29" + assign $0\o$14[63:0]$7603 $1\o$14[63:0]$7604 + attribute \src "libresoc.v:142105.5-142105.29" switch \initial - attribute \src "libresoc.v:139627.9-139627.17" + attribute \src "libresoc.v:142105.9-142105.17" case 1'1 case end @@ -291944,29 +298335,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7294 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7604 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7294 \mul_o [127:64] + assign $1\o$14[63:0]$7604 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7294 \mul_o [63:0] + assign $1\o$14[63:0]$7604 \mul_o [63:0] case - assign $1\o$14[63:0]$7294 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7604 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7293 + update \o$14 $0\o$14[63:0]$7603 end - attribute \src "libresoc.v:139645.3-139663.6" - process $proc$libresoc.v:139645$7295 + attribute \src "libresoc.v:142123.3-142141.6" + process $proc$libresoc.v:142123$7605 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:139646.5-139646.29" + attribute \src "libresoc.v:142124.5-142124.29" switch \initial - attribute \src "libresoc.v:139646.9-139646.17" + attribute \src "libresoc.v:142124.9-142124.17" case 1'1 case end @@ -291990,14 +298381,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:139664.3-139682.6" - process $proc$libresoc.v:139664$7296 + attribute \src "libresoc.v:142142.3-142160.6" + process $proc$libresoc.v:142142$7606 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:139665.5-139665.29" + attribute \src "libresoc.v:142143.5-142143.29" switch \initial - attribute \src "libresoc.v:139665.9-139665.17" + attribute \src "libresoc.v:142143.9-142143.17" case 1'1 case end @@ -292024,14 +298415,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:139683.3-139693.6" - process $proc$libresoc.v:139683$7297 + attribute \src "libresoc.v:142161.3-142171.6" + process $proc$libresoc.v:142161$7607 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:139684.5-139684.29" + attribute \src "libresoc.v:142162.5-142162.29" switch \initial - attribute \src "libresoc.v:139684.9-139684.17" + attribute \src "libresoc.v:142162.9-142162.17" case 1'1 case end @@ -292047,14 +298438,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:139694.3-139704.6" - process $proc$libresoc.v:139694$7298 + attribute \src "libresoc.v:142172.3-142182.6" + process $proc$libresoc.v:142172$7608 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:139695.5-139695.29" + attribute \src "libresoc.v:142173.5-142173.29" switch \initial - attribute \src "libresoc.v:139695.9-139695.17" + attribute \src "libresoc.v:142173.9-142173.17" case 1'1 case end @@ -292070,18 +298461,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:139614$7278_Y - connect \$19 $pos$libresoc.v:139615$7280_Y - connect \$21 $ternary$libresoc.v:139616$7281_Y - connect \$23 $reduce_or$libresoc.v:139617$7282_Y - connect \$26 $reduce_and$libresoc.v:139618$7283_Y - connect \$25 $not$libresoc.v:139619$7284_Y - connect \$29 $and$libresoc.v:139620$7285_Y - connect \$31 $reduce_or$libresoc.v:139621$7286_Y - connect \$34 $reduce_and$libresoc.v:139622$7287_Y - connect \$33 $not$libresoc.v:139623$7288_Y - connect \$37 $and$libresoc.v:139624$7289_Y - connect \$39 $pos$libresoc.v:139625$7291_Y + connect \$17 $neg$libresoc.v:142092$7588_Y + connect \$19 $pos$libresoc.v:142093$7590_Y + connect \$21 $ternary$libresoc.v:142094$7591_Y + connect \$23 $reduce_or$libresoc.v:142095$7592_Y + connect \$26 $reduce_and$libresoc.v:142096$7593_Y + connect \$25 $not$libresoc.v:142097$7594_Y + connect \$29 $and$libresoc.v:142098$7595_Y + connect \$31 $reduce_or$libresoc.v:142099$7596_Y + connect \$34 $reduce_and$libresoc.v:142100$7597_Y + connect \$33 $not$libresoc.v:142101$7598_Y + connect \$37 $and$libresoc.v:142102$7599_Y + connect \$39 $pos$libresoc.v:142103$7601_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -292089,188 +298480,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:139715.1-140911.10" +attribute \src "libresoc.v:142193.1-143389.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:139716.7-139716.20" + attribute \src "libresoc.v:142194.7-142194.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 12 $0\mul_op__fn_unit$next[11:0]$7328 - attribute \src "libresoc.v:140653.3-140654.47" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 12 $0\mul_op__fn_unit$next[11:0]$7638 + attribute \src "libresoc.v:143131.3-143132.47" wire width 12 $0\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7329 - attribute \src "libresoc.v:140655.3-140656.61" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7639 + attribute \src "libresoc.v:143133.3-143134.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7330 - attribute \src "libresoc.v:140657.3-140658.57" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7640 + attribute \src "libresoc.v:143135.3-143136.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 32 $0\mul_op__insn$next[31:0]$7331 - attribute \src "libresoc.v:140673.3-140674.41" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 32 $0\mul_op__insn$next[31:0]$7641 + attribute \src "libresoc.v:143151.3-143152.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7332 - attribute \src "libresoc.v:140651.3-140652.51" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7642 + attribute \src "libresoc.v:143129.3-143130.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__is_32bit$next[0:0]$7333 - attribute \src "libresoc.v:140669.3-140670.49" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__is_32bit$next[0:0]$7643 + attribute \src "libresoc.v:143147.3-143148.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__is_signed$next[0:0]$7334 - attribute \src "libresoc.v:140671.3-140672.51" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__is_signed$next[0:0]$7644 + attribute \src "libresoc.v:143149.3-143150.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__oe__oe$next[0:0]$7335 - attribute \src "libresoc.v:140663.3-140664.45" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__oe__oe$next[0:0]$7645 + attribute \src "libresoc.v:143141.3-143142.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__oe__ok$next[0:0]$7336 - attribute \src "libresoc.v:140665.3-140666.45" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__oe__ok$next[0:0]$7646 + attribute \src "libresoc.v:143143.3-143144.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__rc__ok$next[0:0]$7337 - attribute \src "libresoc.v:140661.3-140662.45" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__rc__ok$next[0:0]$7647 + attribute \src "libresoc.v:143139.3-143140.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__rc__rc$next[0:0]$7338 - attribute \src "libresoc.v:140659.3-140660.45" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__rc__rc$next[0:0]$7648 + attribute \src "libresoc.v:143137.3-143138.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $0\mul_op__write_cr0$next[0:0]$7339 - attribute \src "libresoc.v:140667.3-140668.51" + attribute \src "libresoc.v:143266.3-143301.6" + wire $0\mul_op__write_cr0$next[0:0]$7649 + attribute \src "libresoc.v:143145.3-143146.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:140775.3-140787.6" - wire width 2 $0\muxid$next[1:0]$7325 - attribute \src "libresoc.v:140675.3-140676.27" + attribute \src "libresoc.v:143253.3-143265.6" + wire width 2 $0\muxid$next[1:0]$7635 + attribute \src "libresoc.v:143153.3-143154.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:140863.3-140875.6" - wire $0\neg_res$next[0:0]$7368 - attribute \src "libresoc.v:140876.3-140888.6" - wire $0\neg_res32$next[0:0]$7371 - attribute \src "libresoc.v:140641.3-140642.35" + attribute \src "libresoc.v:143341.3-143353.6" + wire $0\neg_res$next[0:0]$7678 + attribute \src "libresoc.v:143354.3-143366.6" + wire $0\neg_res32$next[0:0]$7681 + attribute \src "libresoc.v:143119.3-143120.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:140643.3-140644.31" + attribute \src "libresoc.v:143121.3-143122.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:140757.3-140774.6" - wire $0\r_busy$next[0:0]$7321 - attribute \src "libresoc.v:140677.3-140678.29" + attribute \src "libresoc.v:143235.3-143252.6" + wire $0\r_busy$next[0:0]$7631 + attribute \src "libresoc.v:143155.3-143156.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:140824.3-140836.6" - wire width 64 $0\ra$next[63:0]$7359 - attribute \src "libresoc.v:140649.3-140650.21" + attribute \src "libresoc.v:143302.3-143314.6" + wire width 64 $0\ra$next[63:0]$7669 + attribute \src "libresoc.v:143127.3-143128.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:140837.3-140849.6" - wire width 64 $0\rb$next[63:0]$7362 - attribute \src "libresoc.v:140647.3-140648.21" + attribute \src "libresoc.v:143315.3-143327.6" + wire width 64 $0\rb$next[63:0]$7672 + attribute \src "libresoc.v:143125.3-143126.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:140850.3-140862.6" - wire $0\xer_so$next[0:0]$7365 - attribute \src "libresoc.v:140645.3-140646.29" + attribute \src "libresoc.v:143328.3-143340.6" + wire $0\xer_so$next[0:0]$7675 + attribute \src "libresoc.v:143123.3-143124.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 12 $1\mul_op__fn_unit$next[11:0]$7340 - attribute \src "libresoc.v:140218.14-140218.39" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 12 $1\mul_op__fn_unit$next[11:0]$7650 + attribute \src "libresoc.v:142696.14-142696.39" wire width 12 $1\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7341 - attribute \src "libresoc.v:140253.14-140253.59" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7651 + attribute \src "libresoc.v:142731.14-142731.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7342 - attribute \src "libresoc.v:140262.7-140262.34" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7652 + attribute \src "libresoc.v:142740.7-142740.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 32 $1\mul_op__insn$next[31:0]$7343 - attribute \src "libresoc.v:140271.14-140271.34" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 32 $1\mul_op__insn$next[31:0]$7653 + attribute \src "libresoc.v:142749.14-142749.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7344 - attribute \src "libresoc.v:140354.13-140354.38" + attribute \src "libresoc.v:143266.3-143301.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7654 + attribute \src "libresoc.v:142832.13-142832.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__is_32bit$next[0:0]$7345 - attribute \src "libresoc.v:140511.7-140511.30" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__is_32bit$next[0:0]$7655 + attribute \src "libresoc.v:142989.7-142989.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__is_signed$next[0:0]$7346 - attribute \src "libresoc.v:140520.7-140520.31" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__is_signed$next[0:0]$7656 + attribute \src "libresoc.v:142998.7-142998.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__oe__oe$next[0:0]$7347 - attribute \src "libresoc.v:140529.7-140529.28" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__oe__oe$next[0:0]$7657 + attribute \src "libresoc.v:143007.7-143007.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__oe__ok$next[0:0]$7348 - attribute \src "libresoc.v:140538.7-140538.28" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__oe__ok$next[0:0]$7658 + attribute \src "libresoc.v:143016.7-143016.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__rc__ok$next[0:0]$7349 - attribute \src "libresoc.v:140547.7-140547.28" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__rc__ok$next[0:0]$7659 + attribute \src "libresoc.v:143025.7-143025.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__rc__rc$next[0:0]$7350 - attribute \src "libresoc.v:140556.7-140556.28" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__rc__rc$next[0:0]$7660 + attribute \src "libresoc.v:143034.7-143034.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire $1\mul_op__write_cr0$next[0:0]$7351 - attribute \src "libresoc.v:140565.7-140565.31" + attribute \src "libresoc.v:143266.3-143301.6" + wire $1\mul_op__write_cr0$next[0:0]$7661 + attribute \src "libresoc.v:143043.7-143043.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:140775.3-140787.6" - wire width 2 $1\muxid$next[1:0]$7326 - attribute \src "libresoc.v:140574.13-140574.25" + attribute \src "libresoc.v:143253.3-143265.6" + wire width 2 $1\muxid$next[1:0]$7636 + attribute \src "libresoc.v:143052.13-143052.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:140863.3-140875.6" - wire $1\neg_res$next[0:0]$7369 - attribute \src "libresoc.v:140876.3-140888.6" - wire $1\neg_res32$next[0:0]$7372 - attribute \src "libresoc.v:140596.7-140596.23" + attribute \src "libresoc.v:143341.3-143353.6" + wire $1\neg_res$next[0:0]$7679 + attribute \src "libresoc.v:143354.3-143366.6" + wire $1\neg_res32$next[0:0]$7682 + attribute \src "libresoc.v:143074.7-143074.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:140589.7-140589.21" + attribute \src "libresoc.v:143067.7-143067.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:140757.3-140774.6" - wire $1\r_busy$next[0:0]$7322 - attribute \src "libresoc.v:140610.7-140610.20" + attribute \src "libresoc.v:143235.3-143252.6" + wire $1\r_busy$next[0:0]$7632 + attribute \src "libresoc.v:143088.7-143088.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:140824.3-140836.6" - wire width 64 $1\ra$next[63:0]$7360 - attribute \src "libresoc.v:140615.14-140615.39" + attribute \src "libresoc.v:143302.3-143314.6" + wire width 64 $1\ra$next[63:0]$7670 + attribute \src "libresoc.v:143093.14-143093.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:140837.3-140849.6" - wire width 64 $1\rb$next[63:0]$7363 - attribute \src "libresoc.v:140624.14-140624.39" + attribute \src "libresoc.v:143315.3-143327.6" + wire width 64 $1\rb$next[63:0]$7673 + attribute \src "libresoc.v:143102.14-143102.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:140850.3-140862.6" - wire $1\xer_so$next[0:0]$7366 - attribute \src "libresoc.v:140633.7-140633.20" + attribute \src "libresoc.v:143328.3-143340.6" + wire $1\xer_so$next[0:0]$7676 + attribute \src "libresoc.v:143111.7-143111.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:140788.3-140823.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7352 - attribute \src "libresoc.v:140788.3-140823.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7353 - attribute \src "libresoc.v:140788.3-140823.6" - wire $2\mul_op__oe__oe$next[0:0]$7354 - attribute \src "libresoc.v:140788.3-140823.6" - wire $2\mul_op__oe__ok$next[0:0]$7355 - attribute \src "libresoc.v:140788.3-140823.6" - wire $2\mul_op__rc__ok$next[0:0]$7356 - attribute \src "libresoc.v:140788.3-140823.6" - wire $2\mul_op__rc__rc$next[0:0]$7357 - attribute \src "libresoc.v:140757.3-140774.6" - wire $2\r_busy$next[0:0]$7323 - attribute \src "libresoc.v:140640.18-140640.118" - wire $and$libresoc.v:140640$7300_Y + attribute \src "libresoc.v:143266.3-143301.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7662 + attribute \src "libresoc.v:143266.3-143301.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7663 + attribute \src "libresoc.v:143266.3-143301.6" + wire $2\mul_op__oe__oe$next[0:0]$7664 + attribute \src "libresoc.v:143266.3-143301.6" + wire $2\mul_op__oe__ok$next[0:0]$7665 + attribute \src "libresoc.v:143266.3-143301.6" + wire $2\mul_op__rc__ok$next[0:0]$7666 + attribute \src "libresoc.v:143266.3-143301.6" + wire $2\mul_op__rc__rc$next[0:0]$7667 + attribute \src "libresoc.v:143235.3-143252.6" + wire $2\r_busy$next[0:0]$7633 + attribute \src "libresoc.v:143118.18-143118.118" + wire $and$libresoc.v:143118$7610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:139716.7-139716.15" + attribute \src "libresoc.v:142194.7-142194.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -293172,7 +299563,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:140640$7300 + cell $and $and$libresoc.v:143118$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -293180,11 +299571,11 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:140640$7300_Y + connect \Y $and$libresoc.v:143118$7610_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140679.14-140712.4" - cell \input$92 \input + attribute \src "libresoc.v:143157.14-143190.4" + cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 connect \mul_op__imm_data__data \input_mul_op__imm_data__data @@ -293219,7 +299610,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:140713.8-140748.4" + attribute \src "libresoc.v:143191.8-143226.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -293257,319 +299648,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:140749.10-140752.4" - cell \n$91 \n + attribute \src "libresoc.v:143227.10-143230.4" + cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:140753.10-140756.4" - cell \p$90 \p + attribute \src "libresoc.v:143231.10-143234.4" + cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:139716.7-139716.20" - process $proc$libresoc.v:139716$7373 + attribute \src "libresoc.v:142194.7-142194.20" + process $proc$libresoc.v:142194$7683 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140218.14-140218.39" - process $proc$libresoc.v:140218$7374 + attribute \src "libresoc.v:142696.14-142696.39" + process $proc$libresoc.v:142696$7684 assign { } { } assign $1\mul_op__fn_unit[11:0] 12'000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] end - attribute \src "libresoc.v:140253.14-140253.59" - process $proc$libresoc.v:140253$7375 + attribute \src "libresoc.v:142731.14-142731.59" + process $proc$libresoc.v:142731$7685 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:140262.7-140262.34" - process $proc$libresoc.v:140262$7376 + attribute \src "libresoc.v:142740.7-142740.34" + process $proc$libresoc.v:142740$7686 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:140271.14-140271.34" - process $proc$libresoc.v:140271$7377 + attribute \src "libresoc.v:142749.14-142749.34" + process $proc$libresoc.v:142749$7687 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:140354.13-140354.38" - process $proc$libresoc.v:140354$7378 + attribute \src "libresoc.v:142832.13-142832.38" + process $proc$libresoc.v:142832$7688 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:140511.7-140511.30" - process $proc$libresoc.v:140511$7379 + attribute \src "libresoc.v:142989.7-142989.30" + process $proc$libresoc.v:142989$7689 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:140520.7-140520.31" - process $proc$libresoc.v:140520$7380 + attribute \src "libresoc.v:142998.7-142998.31" + process $proc$libresoc.v:142998$7690 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:140529.7-140529.28" - process $proc$libresoc.v:140529$7381 + attribute \src "libresoc.v:143007.7-143007.28" + process $proc$libresoc.v:143007$7691 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:140538.7-140538.28" - process $proc$libresoc.v:140538$7382 + attribute \src "libresoc.v:143016.7-143016.28" + process $proc$libresoc.v:143016$7692 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:140547.7-140547.28" - process $proc$libresoc.v:140547$7383 + attribute \src "libresoc.v:143025.7-143025.28" + process $proc$libresoc.v:143025$7693 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:140556.7-140556.28" - process $proc$libresoc.v:140556$7384 + attribute \src "libresoc.v:143034.7-143034.28" + process $proc$libresoc.v:143034$7694 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:140565.7-140565.31" - process $proc$libresoc.v:140565$7385 + attribute \src "libresoc.v:143043.7-143043.31" + process $proc$libresoc.v:143043$7695 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:140574.13-140574.25" - process $proc$libresoc.v:140574$7386 + attribute \src "libresoc.v:143052.13-143052.25" + process $proc$libresoc.v:143052$7696 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:140589.7-140589.21" - process $proc$libresoc.v:140589$7387 + attribute \src "libresoc.v:143067.7-143067.21" + process $proc$libresoc.v:143067$7697 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:140596.7-140596.23" - process $proc$libresoc.v:140596$7388 + attribute \src "libresoc.v:143074.7-143074.23" + process $proc$libresoc.v:143074$7698 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:140610.7-140610.20" - process $proc$libresoc.v:140610$7389 + attribute \src "libresoc.v:143088.7-143088.20" + process $proc$libresoc.v:143088$7699 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:140615.14-140615.39" - process $proc$libresoc.v:140615$7390 + attribute \src "libresoc.v:143093.14-143093.39" + process $proc$libresoc.v:143093$7700 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:140624.14-140624.39" - process $proc$libresoc.v:140624$7391 + attribute \src "libresoc.v:143102.14-143102.39" + process $proc$libresoc.v:143102$7701 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:140633.7-140633.20" - process $proc$libresoc.v:140633$7392 + attribute \src "libresoc.v:143111.7-143111.20" + process $proc$libresoc.v:143111$7702 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:140641.3-140642.35" - process $proc$libresoc.v:140641$7301 + attribute \src "libresoc.v:143119.3-143120.35" + process $proc$libresoc.v:143119$7611 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:140643.3-140644.31" - process $proc$libresoc.v:140643$7302 + attribute \src "libresoc.v:143121.3-143122.31" + process $proc$libresoc.v:143121$7612 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:140645.3-140646.29" - process $proc$libresoc.v:140645$7303 + attribute \src "libresoc.v:143123.3-143124.29" + process $proc$libresoc.v:143123$7613 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:140647.3-140648.21" - process $proc$libresoc.v:140647$7304 + attribute \src "libresoc.v:143125.3-143126.21" + process $proc$libresoc.v:143125$7614 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:140649.3-140650.21" - process $proc$libresoc.v:140649$7305 + attribute \src "libresoc.v:143127.3-143128.21" + process $proc$libresoc.v:143127$7615 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:140651.3-140652.51" - process $proc$libresoc.v:140651$7306 + attribute \src "libresoc.v:143129.3-143130.51" + process $proc$libresoc.v:143129$7616 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:140653.3-140654.47" - process $proc$libresoc.v:140653$7307 + attribute \src "libresoc.v:143131.3-143132.47" + process $proc$libresoc.v:143131$7617 assign { } { } assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] end - attribute \src "libresoc.v:140655.3-140656.61" - process $proc$libresoc.v:140655$7308 + attribute \src "libresoc.v:143133.3-143134.61" + process $proc$libresoc.v:143133$7618 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:140657.3-140658.57" - process $proc$libresoc.v:140657$7309 + attribute \src "libresoc.v:143135.3-143136.57" + process $proc$libresoc.v:143135$7619 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:140659.3-140660.45" - process $proc$libresoc.v:140659$7310 + attribute \src "libresoc.v:143137.3-143138.45" + process $proc$libresoc.v:143137$7620 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:140661.3-140662.45" - process $proc$libresoc.v:140661$7311 + attribute \src "libresoc.v:143139.3-143140.45" + process $proc$libresoc.v:143139$7621 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:140663.3-140664.45" - process $proc$libresoc.v:140663$7312 + attribute \src "libresoc.v:143141.3-143142.45" + process $proc$libresoc.v:143141$7622 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:140665.3-140666.45" - process $proc$libresoc.v:140665$7313 + attribute \src "libresoc.v:143143.3-143144.45" + process $proc$libresoc.v:143143$7623 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:140667.3-140668.51" - process $proc$libresoc.v:140667$7314 + attribute \src "libresoc.v:143145.3-143146.51" + process $proc$libresoc.v:143145$7624 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:140669.3-140670.49" - process $proc$libresoc.v:140669$7315 + attribute \src "libresoc.v:143147.3-143148.49" + process $proc$libresoc.v:143147$7625 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:140671.3-140672.51" - process $proc$libresoc.v:140671$7316 + attribute \src "libresoc.v:143149.3-143150.51" + process $proc$libresoc.v:143149$7626 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:140673.3-140674.41" - process $proc$libresoc.v:140673$7317 + attribute \src "libresoc.v:143151.3-143152.41" + process $proc$libresoc.v:143151$7627 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:140675.3-140676.27" - process $proc$libresoc.v:140675$7318 + attribute \src "libresoc.v:143153.3-143154.27" + process $proc$libresoc.v:143153$7628 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:140677.3-140678.29" - process $proc$libresoc.v:140677$7319 + attribute \src "libresoc.v:143155.3-143156.29" + process $proc$libresoc.v:143155$7629 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:140757.3-140774.6" - process $proc$libresoc.v:140757$7320 + attribute \src "libresoc.v:143235.3-143252.6" + process $proc$libresoc.v:143235$7630 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7321 $2\r_busy$next[0:0]$7323 - attribute \src "libresoc.v:140758.5-140758.29" + assign $0\r_busy$next[0:0]$7631 $2\r_busy$next[0:0]$7633 + attribute \src "libresoc.v:143236.5-143236.29" switch \initial - attribute \src "libresoc.v:140758.9-140758.17" + attribute \src "libresoc.v:143236.9-143236.17" case 1'1 case end @@ -293578,34 +299969,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7322 1'1 + assign $1\r_busy$next[0:0]$7632 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7322 1'0 + assign $1\r_busy$next[0:0]$7632 1'0 case - assign $1\r_busy$next[0:0]$7322 \r_busy + assign $1\r_busy$next[0:0]$7632 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7323 1'0 + assign $2\r_busy$next[0:0]$7633 1'0 case - assign $2\r_busy$next[0:0]$7323 $1\r_busy$next[0:0]$7322 + assign $2\r_busy$next[0:0]$7633 $1\r_busy$next[0:0]$7632 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7321 + update \r_busy$next $0\r_busy$next[0:0]$7631 end - attribute \src "libresoc.v:140775.3-140787.6" - process $proc$libresoc.v:140775$7324 + attribute \src "libresoc.v:143253.3-143265.6" + process $proc$libresoc.v:143253$7634 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7325 $1\muxid$next[1:0]$7326 - attribute \src "libresoc.v:140776.5-140776.29" + assign $0\muxid$next[1:0]$7635 $1\muxid$next[1:0]$7636 + attribute \src "libresoc.v:143254.5-143254.29" switch \initial - attribute \src "libresoc.v:140776.9-140776.17" + attribute \src "libresoc.v:143254.9-143254.17" case 1'1 case end @@ -293614,19 +300005,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7326 \muxid$52 + assign $1\muxid$next[1:0]$7636 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7326 \muxid$52 + assign $1\muxid$next[1:0]$7636 \muxid$52 case - assign $1\muxid$next[1:0]$7326 \muxid + assign $1\muxid$next[1:0]$7636 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7325 + update \muxid$next $0\muxid$next[1:0]$7635 end - attribute \src "libresoc.v:140788.3-140823.6" - process $proc$libresoc.v:140788$7327 + attribute \src "libresoc.v:143266.3-143301.6" + process $proc$libresoc.v:143266$7637 assign { } { } assign { } { } assign { } { } @@ -293651,27 +300042,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[11:0]$7328 $1\mul_op__fn_unit$next[11:0]$7340 + assign $0\mul_op__fn_unit$next[11:0]$7638 $1\mul_op__fn_unit$next[11:0]$7650 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7331 $1\mul_op__insn$next[31:0]$7343 - assign $0\mul_op__insn_type$next[6:0]$7332 $1\mul_op__insn_type$next[6:0]$7344 - assign $0\mul_op__is_32bit$next[0:0]$7333 $1\mul_op__is_32bit$next[0:0]$7345 - assign $0\mul_op__is_signed$next[0:0]$7334 $1\mul_op__is_signed$next[0:0]$7346 + assign $0\mul_op__insn$next[31:0]$7641 $1\mul_op__insn$next[31:0]$7653 + assign $0\mul_op__insn_type$next[6:0]$7642 $1\mul_op__insn_type$next[6:0]$7654 + assign $0\mul_op__is_32bit$next[0:0]$7643 $1\mul_op__is_32bit$next[0:0]$7655 + assign $0\mul_op__is_signed$next[0:0]$7644 $1\mul_op__is_signed$next[0:0]$7656 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7339 $1\mul_op__write_cr0$next[0:0]$7351 - assign $0\mul_op__imm_data__data$next[63:0]$7329 $2\mul_op__imm_data__data$next[63:0]$7352 - assign $0\mul_op__imm_data__ok$next[0:0]$7330 $2\mul_op__imm_data__ok$next[0:0]$7353 - assign $0\mul_op__oe__oe$next[0:0]$7335 $2\mul_op__oe__oe$next[0:0]$7354 - assign $0\mul_op__oe__ok$next[0:0]$7336 $2\mul_op__oe__ok$next[0:0]$7355 - assign $0\mul_op__rc__ok$next[0:0]$7337 $2\mul_op__rc__ok$next[0:0]$7356 - assign $0\mul_op__rc__rc$next[0:0]$7338 $2\mul_op__rc__rc$next[0:0]$7357 - attribute \src "libresoc.v:140789.5-140789.29" + assign $0\mul_op__write_cr0$next[0:0]$7649 $1\mul_op__write_cr0$next[0:0]$7661 + assign $0\mul_op__imm_data__data$next[63:0]$7639 $2\mul_op__imm_data__data$next[63:0]$7662 + assign $0\mul_op__imm_data__ok$next[0:0]$7640 $2\mul_op__imm_data__ok$next[0:0]$7663 + assign $0\mul_op__oe__oe$next[0:0]$7645 $2\mul_op__oe__oe$next[0:0]$7664 + assign $0\mul_op__oe__ok$next[0:0]$7646 $2\mul_op__oe__ok$next[0:0]$7665 + assign $0\mul_op__rc__ok$next[0:0]$7647 $2\mul_op__rc__ok$next[0:0]$7666 + assign $0\mul_op__rc__rc$next[0:0]$7648 $2\mul_op__rc__rc$next[0:0]$7667 + attribute \src "libresoc.v:143267.5-143267.29" switch \initial - attribute \src "libresoc.v:140789.9-140789.17" + attribute \src "libresoc.v:143267.9-143267.17" case 1'1 case end @@ -293691,7 +300082,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7343 $1\mul_op__is_signed$next[0:0]$7346 $1\mul_op__is_32bit$next[0:0]$7345 $1\mul_op__write_cr0$next[0:0]$7351 $1\mul_op__oe__ok$next[0:0]$7348 $1\mul_op__oe__oe$next[0:0]$7347 $1\mul_op__rc__ok$next[0:0]$7349 $1\mul_op__rc__rc$next[0:0]$7350 $1\mul_op__imm_data__ok$next[0:0]$7342 $1\mul_op__imm_data__data$next[63:0]$7341 $1\mul_op__fn_unit$next[11:0]$7340 $1\mul_op__insn_type$next[6:0]$7344 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7653 $1\mul_op__is_signed$next[0:0]$7656 $1\mul_op__is_32bit$next[0:0]$7655 $1\mul_op__write_cr0$next[0:0]$7661 $1\mul_op__oe__ok$next[0:0]$7658 $1\mul_op__oe__oe$next[0:0]$7657 $1\mul_op__rc__ok$next[0:0]$7659 $1\mul_op__rc__rc$next[0:0]$7660 $1\mul_op__imm_data__ok$next[0:0]$7652 $1\mul_op__imm_data__data$next[63:0]$7651 $1\mul_op__fn_unit$next[11:0]$7650 $1\mul_op__insn_type$next[6:0]$7654 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -293706,20 +300097,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7343 $1\mul_op__is_signed$next[0:0]$7346 $1\mul_op__is_32bit$next[0:0]$7345 $1\mul_op__write_cr0$next[0:0]$7351 $1\mul_op__oe__ok$next[0:0]$7348 $1\mul_op__oe__oe$next[0:0]$7347 $1\mul_op__rc__ok$next[0:0]$7349 $1\mul_op__rc__rc$next[0:0]$7350 $1\mul_op__imm_data__ok$next[0:0]$7342 $1\mul_op__imm_data__data$next[63:0]$7341 $1\mul_op__fn_unit$next[11:0]$7340 $1\mul_op__insn_type$next[6:0]$7344 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7653 $1\mul_op__is_signed$next[0:0]$7656 $1\mul_op__is_32bit$next[0:0]$7655 $1\mul_op__write_cr0$next[0:0]$7661 $1\mul_op__oe__ok$next[0:0]$7658 $1\mul_op__oe__oe$next[0:0]$7657 $1\mul_op__rc__ok$next[0:0]$7659 $1\mul_op__rc__rc$next[0:0]$7660 $1\mul_op__imm_data__ok$next[0:0]$7652 $1\mul_op__imm_data__data$next[63:0]$7651 $1\mul_op__fn_unit$next[11:0]$7650 $1\mul_op__insn_type$next[6:0]$7654 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[11:0]$7340 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7341 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7342 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7343 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7344 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7345 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7346 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7347 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7348 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7349 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7350 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7351 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[11:0]$7650 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7651 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7652 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7653 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7654 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7655 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7656 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7657 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7658 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7659 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7660 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7661 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -293731,42 +300122,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7352 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7353 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7357 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7356 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7354 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7355 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7662 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7663 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7667 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7666 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7664 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7665 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7352 $1\mul_op__imm_data__data$next[63:0]$7341 - assign $2\mul_op__imm_data__ok$next[0:0]$7353 $1\mul_op__imm_data__ok$next[0:0]$7342 - assign $2\mul_op__oe__oe$next[0:0]$7354 $1\mul_op__oe__oe$next[0:0]$7347 - assign $2\mul_op__oe__ok$next[0:0]$7355 $1\mul_op__oe__ok$next[0:0]$7348 - assign $2\mul_op__rc__ok$next[0:0]$7356 $1\mul_op__rc__ok$next[0:0]$7349 - assign $2\mul_op__rc__rc$next[0:0]$7357 $1\mul_op__rc__rc$next[0:0]$7350 + assign $2\mul_op__imm_data__data$next[63:0]$7662 $1\mul_op__imm_data__data$next[63:0]$7651 + assign $2\mul_op__imm_data__ok$next[0:0]$7663 $1\mul_op__imm_data__ok$next[0:0]$7652 + assign $2\mul_op__oe__oe$next[0:0]$7664 $1\mul_op__oe__oe$next[0:0]$7657 + assign $2\mul_op__oe__ok$next[0:0]$7665 $1\mul_op__oe__ok$next[0:0]$7658 + assign $2\mul_op__rc__ok$next[0:0]$7666 $1\mul_op__rc__ok$next[0:0]$7659 + assign $2\mul_op__rc__rc$next[0:0]$7667 $1\mul_op__rc__rc$next[0:0]$7660 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7328 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7329 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7330 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7331 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7332 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7333 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7334 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7335 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7336 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7337 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7338 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7339 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7638 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7639 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7640 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7641 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7642 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7643 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7644 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7645 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7646 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7647 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7648 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7649 end - attribute \src "libresoc.v:140824.3-140836.6" - process $proc$libresoc.v:140824$7358 + attribute \src "libresoc.v:143302.3-143314.6" + process $proc$libresoc.v:143302$7668 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7359 $1\ra$next[63:0]$7360 - attribute \src "libresoc.v:140825.5-140825.29" + assign $0\ra$next[63:0]$7669 $1\ra$next[63:0]$7670 + attribute \src "libresoc.v:143303.5-143303.29" switch \initial - attribute \src "libresoc.v:140825.9-140825.17" + attribute \src "libresoc.v:143303.9-143303.17" case 1'1 case end @@ -293775,25 +300166,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$7360 \ra$65 + assign $1\ra$next[63:0]$7670 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$7360 \ra$65 + assign $1\ra$next[63:0]$7670 \ra$65 case - assign $1\ra$next[63:0]$7360 \ra + assign $1\ra$next[63:0]$7670 \ra end sync always - update \ra$next $0\ra$next[63:0]$7359 + update \ra$next $0\ra$next[63:0]$7669 end - attribute \src "libresoc.v:140837.3-140849.6" - process $proc$libresoc.v:140837$7361 + attribute \src "libresoc.v:143315.3-143327.6" + process $proc$libresoc.v:143315$7671 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7362 $1\rb$next[63:0]$7363 - attribute \src "libresoc.v:140838.5-140838.29" + assign $0\rb$next[63:0]$7672 $1\rb$next[63:0]$7673 + attribute \src "libresoc.v:143316.5-143316.29" switch \initial - attribute \src "libresoc.v:140838.9-140838.17" + attribute \src "libresoc.v:143316.9-143316.17" case 1'1 case end @@ -293802,25 +300193,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$7363 \rb$66 + assign $1\rb$next[63:0]$7673 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$7363 \rb$66 + assign $1\rb$next[63:0]$7673 \rb$66 case - assign $1\rb$next[63:0]$7363 \rb + assign $1\rb$next[63:0]$7673 \rb end sync always - update \rb$next $0\rb$next[63:0]$7362 + update \rb$next $0\rb$next[63:0]$7672 end - attribute \src "libresoc.v:140850.3-140862.6" - process $proc$libresoc.v:140850$7364 + attribute \src "libresoc.v:143328.3-143340.6" + process $proc$libresoc.v:143328$7674 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$7365 $1\xer_so$next[0:0]$7366 - attribute \src "libresoc.v:140851.5-140851.29" + assign $0\xer_so$next[0:0]$7675 $1\xer_so$next[0:0]$7676 + attribute \src "libresoc.v:143329.5-143329.29" switch \initial - attribute \src "libresoc.v:140851.9-140851.17" + attribute \src "libresoc.v:143329.9-143329.17" case 1'1 case end @@ -293829,25 +300220,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$7366 \xer_so$67 + assign $1\xer_so$next[0:0]$7676 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$7366 \xer_so$67 + assign $1\xer_so$next[0:0]$7676 \xer_so$67 case - assign $1\xer_so$next[0:0]$7366 \xer_so + assign $1\xer_so$next[0:0]$7676 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$7365 + update \xer_so$next $0\xer_so$next[0:0]$7675 end - attribute \src "libresoc.v:140863.3-140875.6" - process $proc$libresoc.v:140863$7367 + attribute \src "libresoc.v:143341.3-143353.6" + process $proc$libresoc.v:143341$7677 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$7368 $1\neg_res$next[0:0]$7369 - attribute \src "libresoc.v:140864.5-140864.29" + assign $0\neg_res$next[0:0]$7678 $1\neg_res$next[0:0]$7679 + attribute \src "libresoc.v:143342.5-143342.29" switch \initial - attribute \src "libresoc.v:140864.9-140864.17" + attribute \src "libresoc.v:143342.9-143342.17" case 1'1 case end @@ -293856,25 +300247,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$7369 \neg_res$68 + assign $1\neg_res$next[0:0]$7679 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$7369 \neg_res$68 + assign $1\neg_res$next[0:0]$7679 \neg_res$68 case - assign $1\neg_res$next[0:0]$7369 \neg_res + assign $1\neg_res$next[0:0]$7679 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$7368 + update \neg_res$next $0\neg_res$next[0:0]$7678 end - attribute \src "libresoc.v:140876.3-140888.6" - process $proc$libresoc.v:140876$7370 + attribute \src "libresoc.v:143354.3-143366.6" + process $proc$libresoc.v:143354$7680 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$7371 $1\neg_res32$next[0:0]$7372 - attribute \src "libresoc.v:140877.5-140877.29" + assign $0\neg_res32$next[0:0]$7681 $1\neg_res32$next[0:0]$7682 + attribute \src "libresoc.v:143355.5-143355.29" switch \initial - attribute \src "libresoc.v:140877.9-140877.17" + attribute \src "libresoc.v:143355.9-143355.17" case 1'1 case end @@ -293883,18 +300274,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$7372 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7682 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$7372 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7682 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$7372 \neg_res32 + assign $1\neg_res32$next[0:0]$7682 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7371 + update \neg_res32$next $0\neg_res32$next[0:0]$7681 end - connect \$50 $and$libresoc.v:140640$7300_Y + connect \$50 $and$libresoc.v:143118$7610_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -293918,180 +300309,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:140915.1-141820.10" +attribute \src "libresoc.v:143393.1-144298.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:140916.7-140916.20" + attribute \src "libresoc.v:143394.7-143394.20" wire $0\initial[0:0] - attribute \src "libresoc.v:141714.3-141749.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7436 - attribute \src "libresoc.v:141612.3-141613.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7404 - attribute \src "libresoc.v:141197.14-141197.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7480 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7437 - attribute \src "libresoc.v:141614.3-141615.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7406 - attribute \src "libresoc.v:141221.14-141221.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7482 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7438 - attribute \src "libresoc.v:141616.3-141617.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7408 - attribute \src "libresoc.v:141230.7-141230.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7484 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7439 - attribute \src "libresoc.v:141632.3-141633.49" - wire width 32 $0\mul_op__insn$13[31:0]$7424 - attribute \src "libresoc.v:141237.14-141237.39" - wire width 32 $0\mul_op__insn$13[31:0]$7486 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7440 - attribute \src "libresoc.v:141610.3-141611.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7402 - attribute \src "libresoc.v:141394.13-141394.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7488 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7441 - attribute \src "libresoc.v:141628.3-141629.57" - wire $0\mul_op__is_32bit$11[0:0]$7420 - attribute \src "libresoc.v:141477.7-141477.35" - wire $0\mul_op__is_32bit$11[0:0]$7490 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__is_signed$12$next[0:0]$7442 - attribute \src "libresoc.v:141630.3-141631.59" - wire $0\mul_op__is_signed$12[0:0]$7422 - attribute \src "libresoc.v:141486.7-141486.36" - wire $0\mul_op__is_signed$12[0:0]$7492 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7443 - attribute \src "libresoc.v:141622.3-141623.51" - wire $0\mul_op__oe__oe$8[0:0]$7414 - attribute \src "libresoc.v:141497.7-141497.32" - wire $0\mul_op__oe__oe$8[0:0]$7494 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7444 - attribute \src "libresoc.v:141624.3-141625.51" - wire $0\mul_op__oe__ok$9[0:0]$7416 - attribute \src "libresoc.v:141506.7-141506.32" - wire $0\mul_op__oe__ok$9[0:0]$7496 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7445 - attribute \src "libresoc.v:141620.3-141621.51" - wire $0\mul_op__rc__ok$7[0:0]$7412 - attribute \src "libresoc.v:141515.7-141515.32" - wire $0\mul_op__rc__ok$7[0:0]$7498 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7446 - attribute \src "libresoc.v:141618.3-141619.51" - wire $0\mul_op__rc__rc$6[0:0]$7410 - attribute \src "libresoc.v:141524.7-141524.32" - wire $0\mul_op__rc__rc$6[0:0]$7500 - attribute \src "libresoc.v:141714.3-141749.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7447 - attribute \src "libresoc.v:141626.3-141627.59" - wire $0\mul_op__write_cr0$10[0:0]$7418 - attribute \src "libresoc.v:141531.7-141531.36" - wire $0\mul_op__write_cr0$10[0:0]$7502 - attribute \src "libresoc.v:141701.3-141713.6" - wire width 2 $0\muxid$1$next[1:0]$7433 - attribute \src "libresoc.v:141634.3-141635.33" - wire width 2 $0\muxid$1[1:0]$7426 - attribute \src "libresoc.v:141540.13-141540.29" - wire width 2 $0\muxid$1[1:0]$7504 - attribute \src "libresoc.v:141776.3-141788.6" - wire $0\neg_res$15$next[0:0]$7473 - attribute \src "libresoc.v:141604.3-141605.39" - wire $0\neg_res$15[0:0]$7397 - attribute \src "libresoc.v:141555.7-141555.26" - wire $0\neg_res$15[0:0]$7506 - attribute \src "libresoc.v:141789.3-141801.6" - wire $0\neg_res32$16$next[0:0]$7476 - attribute \src "libresoc.v:141602.3-141603.43" - wire $0\neg_res32$16[0:0]$7395 - attribute \src "libresoc.v:141564.7-141564.28" - wire $0\neg_res32$16[0:0]$7508 - attribute \src "libresoc.v:141750.3-141762.6" - wire width 129 $0\o$next[128:0]$7467 - attribute \src "libresoc.v:141608.3-141609.19" + attribute \src "libresoc.v:144192.3-144227.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7746 + attribute \src "libresoc.v:144090.3-144091.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7714 + attribute \src "libresoc.v:143675.14-143675.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7790 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7747 + attribute \src "libresoc.v:144092.3-144093.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7716 + attribute \src "libresoc.v:143699.14-143699.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7792 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7748 + attribute \src "libresoc.v:144094.3-144095.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7718 + attribute \src "libresoc.v:143708.7-143708.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7794 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7749 + attribute \src "libresoc.v:144110.3-144111.49" + wire width 32 $0\mul_op__insn$13[31:0]$7734 + attribute \src "libresoc.v:143715.14-143715.39" + wire width 32 $0\mul_op__insn$13[31:0]$7796 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7750 + attribute \src "libresoc.v:144088.3-144089.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7712 + attribute \src "libresoc.v:143872.13-143872.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7798 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7751 + attribute \src "libresoc.v:144106.3-144107.57" + wire $0\mul_op__is_32bit$11[0:0]$7730 + attribute \src "libresoc.v:143955.7-143955.35" + wire $0\mul_op__is_32bit$11[0:0]$7800 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__is_signed$12$next[0:0]$7752 + attribute \src "libresoc.v:144108.3-144109.59" + wire $0\mul_op__is_signed$12[0:0]$7732 + attribute \src "libresoc.v:143964.7-143964.36" + wire $0\mul_op__is_signed$12[0:0]$7802 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7753 + attribute \src "libresoc.v:144100.3-144101.51" + wire $0\mul_op__oe__oe$8[0:0]$7724 + attribute \src "libresoc.v:143975.7-143975.32" + wire $0\mul_op__oe__oe$8[0:0]$7804 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7754 + attribute \src "libresoc.v:144102.3-144103.51" + wire $0\mul_op__oe__ok$9[0:0]$7726 + attribute \src "libresoc.v:143984.7-143984.32" + wire $0\mul_op__oe__ok$9[0:0]$7806 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7755 + attribute \src "libresoc.v:144098.3-144099.51" + wire $0\mul_op__rc__ok$7[0:0]$7722 + attribute \src "libresoc.v:143993.7-143993.32" + wire $0\mul_op__rc__ok$7[0:0]$7808 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7756 + attribute \src "libresoc.v:144096.3-144097.51" + wire $0\mul_op__rc__rc$6[0:0]$7720 + attribute \src "libresoc.v:144002.7-144002.32" + wire $0\mul_op__rc__rc$6[0:0]$7810 + attribute \src "libresoc.v:144192.3-144227.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7757 + attribute \src "libresoc.v:144104.3-144105.59" + wire $0\mul_op__write_cr0$10[0:0]$7728 + attribute \src "libresoc.v:144009.7-144009.36" + wire $0\mul_op__write_cr0$10[0:0]$7812 + attribute \src "libresoc.v:144179.3-144191.6" + wire width 2 $0\muxid$1$next[1:0]$7743 + attribute \src "libresoc.v:144112.3-144113.33" + wire width 2 $0\muxid$1[1:0]$7736 + attribute \src "libresoc.v:144018.13-144018.29" + wire width 2 $0\muxid$1[1:0]$7814 + attribute \src "libresoc.v:144254.3-144266.6" + wire $0\neg_res$15$next[0:0]$7783 + attribute \src "libresoc.v:144082.3-144083.39" + wire $0\neg_res$15[0:0]$7707 + attribute \src "libresoc.v:144033.7-144033.26" + wire $0\neg_res$15[0:0]$7816 + attribute \src "libresoc.v:144267.3-144279.6" + wire $0\neg_res32$16$next[0:0]$7786 + attribute \src "libresoc.v:144080.3-144081.43" + wire $0\neg_res32$16[0:0]$7705 + attribute \src "libresoc.v:144042.7-144042.28" + wire $0\neg_res32$16[0:0]$7818 + attribute \src "libresoc.v:144228.3-144240.6" + wire width 129 $0\o$next[128:0]$7777 + attribute \src "libresoc.v:144086.3-144087.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:141683.3-141700.6" - wire $0\r_busy$next[0:0]$7429 - attribute \src "libresoc.v:141636.3-141637.29" + attribute \src "libresoc.v:144161.3-144178.6" + wire $0\r_busy$next[0:0]$7739 + attribute \src "libresoc.v:144114.3-144115.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:141763.3-141775.6" - wire $0\xer_so$14$next[0:0]$7470 - attribute \src "libresoc.v:141606.3-141607.37" - wire $0\xer_so$14[0:0]$7399 - attribute \src "libresoc.v:141596.7-141596.25" - wire $0\xer_so$14[0:0]$7512 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7448 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7449 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7450 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7451 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7452 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7453 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__is_signed$12$next[0:0]$7454 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7455 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7456 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7457 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7458 - attribute \src "libresoc.v:141714.3-141749.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7459 - attribute \src "libresoc.v:141701.3-141713.6" - wire width 2 $1\muxid$1$next[1:0]$7434 - attribute \src "libresoc.v:141776.3-141788.6" - wire $1\neg_res$15$next[0:0]$7474 - attribute \src "libresoc.v:141789.3-141801.6" - wire $1\neg_res32$16$next[0:0]$7477 - attribute \src "libresoc.v:141750.3-141762.6" - wire width 129 $1\o$next[128:0]$7468 - attribute \src "libresoc.v:141571.15-141571.57" + attribute \src "libresoc.v:144241.3-144253.6" + wire $0\xer_so$14$next[0:0]$7780 + attribute \src "libresoc.v:144084.3-144085.37" + wire $0\xer_so$14[0:0]$7709 + attribute \src "libresoc.v:144074.7-144074.25" + wire $0\xer_so$14[0:0]$7822 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7758 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7759 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7760 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7761 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7762 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7763 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__is_signed$12$next[0:0]$7764 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7765 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7766 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7767 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7768 + attribute \src "libresoc.v:144192.3-144227.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7769 + attribute \src "libresoc.v:144179.3-144191.6" + wire width 2 $1\muxid$1$next[1:0]$7744 + attribute \src "libresoc.v:144254.3-144266.6" + wire $1\neg_res$15$next[0:0]$7784 + attribute \src "libresoc.v:144267.3-144279.6" + wire $1\neg_res32$16$next[0:0]$7787 + attribute \src "libresoc.v:144228.3-144240.6" + wire width 129 $1\o$next[128:0]$7778 + attribute \src "libresoc.v:144049.15-144049.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:141683.3-141700.6" - wire $1\r_busy$next[0:0]$7430 - attribute \src "libresoc.v:141585.7-141585.20" + attribute \src "libresoc.v:144161.3-144178.6" + wire $1\r_busy$next[0:0]$7740 + attribute \src "libresoc.v:144063.7-144063.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:141763.3-141775.6" - wire $1\xer_so$14$next[0:0]$7471 - attribute \src "libresoc.v:141714.3-141749.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7460 - attribute \src "libresoc.v:141714.3-141749.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7461 - attribute \src "libresoc.v:141714.3-141749.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7462 - attribute \src "libresoc.v:141714.3-141749.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7463 - attribute \src "libresoc.v:141714.3-141749.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7464 - attribute \src "libresoc.v:141714.3-141749.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7465 - attribute \src "libresoc.v:141683.3-141700.6" - wire $2\r_busy$next[0:0]$7431 - attribute \src "libresoc.v:141601.18-141601.118" - wire $and$libresoc.v:141601$7393_Y + attribute \src "libresoc.v:144241.3-144253.6" + wire $1\xer_so$14$next[0:0]$7781 + attribute \src "libresoc.v:144192.3-144227.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7770 + attribute \src "libresoc.v:144192.3-144227.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7771 + attribute \src "libresoc.v:144192.3-144227.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7772 + attribute \src "libresoc.v:144192.3-144227.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7773 + attribute \src "libresoc.v:144192.3-144227.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7774 + attribute \src "libresoc.v:144192.3-144227.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7775 + attribute \src "libresoc.v:144161.3-144178.6" + wire $2\r_busy$next[0:0]$7741 + attribute \src "libresoc.v:144079.18-144079.118" + wire $and$libresoc.v:144079$7703_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:140916.7-140916.15" + attribute \src "libresoc.v:143394.7-143394.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -294755,7 +301146,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:141601$7393 + cell $and $and$libresoc.v:144079$7703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -294763,10 +301154,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:141601$7393_Y + connect \Y $and$libresoc.v:144079$7703_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141638.8-141674.4" + attribute \src "libresoc.v:144116.8-144152.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -294805,304 +301196,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:141675.10-141678.4" - cell \n$94 \n + attribute \src "libresoc.v:144153.10-144156.4" + cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:141679.10-141682.4" - cell \p$93 \p + attribute \src "libresoc.v:144157.10-144160.4" + cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:140916.7-140916.20" - process $proc$libresoc.v:140916$7478 + attribute \src "libresoc.v:143394.7-143394.20" + process $proc$libresoc.v:143394$7788 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141197.14-141197.43" - process $proc$libresoc.v:141197$7479 + attribute \src "libresoc.v:143675.14-143675.43" + process $proc$libresoc.v:143675$7789 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7480 12'000000000000 + assign $0\mul_op__fn_unit$3[11:0]$7790 12'000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7480 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7790 end - attribute \src "libresoc.v:141221.14-141221.63" - process $proc$libresoc.v:141221$7481 + attribute \src "libresoc.v:143699.14-143699.63" + process $proc$libresoc.v:143699$7791 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7482 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$7792 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7482 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7792 end - attribute \src "libresoc.v:141230.7-141230.38" - process $proc$libresoc.v:141230$7483 + attribute \src "libresoc.v:143708.7-143708.38" + process $proc$libresoc.v:143708$7793 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7484 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$7794 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7484 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7794 end - attribute \src "libresoc.v:141237.14-141237.39" - process $proc$libresoc.v:141237$7485 + attribute \src "libresoc.v:143715.14-143715.39" + process $proc$libresoc.v:143715$7795 assign { } { } - assign $0\mul_op__insn$13[31:0]$7486 0 + assign $0\mul_op__insn$13[31:0]$7796 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7486 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7796 end - attribute \src "libresoc.v:141394.13-141394.42" - process $proc$libresoc.v:141394$7487 + attribute \src "libresoc.v:143872.13-143872.42" + process $proc$libresoc.v:143872$7797 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7488 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$7798 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7488 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7798 end - attribute \src "libresoc.v:141477.7-141477.35" - process $proc$libresoc.v:141477$7489 + attribute \src "libresoc.v:143955.7-143955.35" + process $proc$libresoc.v:143955$7799 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7490 1'0 + assign $0\mul_op__is_32bit$11[0:0]$7800 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7490 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7800 end - attribute \src "libresoc.v:141486.7-141486.36" - process $proc$libresoc.v:141486$7491 + attribute \src "libresoc.v:143964.7-143964.36" + process $proc$libresoc.v:143964$7801 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7492 1'0 + assign $0\mul_op__is_signed$12[0:0]$7802 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7492 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7802 end - attribute \src "libresoc.v:141497.7-141497.32" - process $proc$libresoc.v:141497$7493 + attribute \src "libresoc.v:143975.7-143975.32" + process $proc$libresoc.v:143975$7803 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7494 1'0 + assign $0\mul_op__oe__oe$8[0:0]$7804 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7494 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7804 end - attribute \src "libresoc.v:141506.7-141506.32" - process $proc$libresoc.v:141506$7495 + attribute \src "libresoc.v:143984.7-143984.32" + process $proc$libresoc.v:143984$7805 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7496 1'0 + assign $0\mul_op__oe__ok$9[0:0]$7806 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7496 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7806 end - attribute \src "libresoc.v:141515.7-141515.32" - process $proc$libresoc.v:141515$7497 + attribute \src "libresoc.v:143993.7-143993.32" + process $proc$libresoc.v:143993$7807 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7498 1'0 + assign $0\mul_op__rc__ok$7[0:0]$7808 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7498 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7808 end - attribute \src "libresoc.v:141524.7-141524.32" - process $proc$libresoc.v:141524$7499 + attribute \src "libresoc.v:144002.7-144002.32" + process $proc$libresoc.v:144002$7809 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7500 1'0 + assign $0\mul_op__rc__rc$6[0:0]$7810 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7500 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7810 end - attribute \src "libresoc.v:141531.7-141531.36" - process $proc$libresoc.v:141531$7501 + attribute \src "libresoc.v:144009.7-144009.36" + process $proc$libresoc.v:144009$7811 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7502 1'0 + assign $0\mul_op__write_cr0$10[0:0]$7812 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7502 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7812 end - attribute \src "libresoc.v:141540.13-141540.29" - process $proc$libresoc.v:141540$7503 + attribute \src "libresoc.v:144018.13-144018.29" + process $proc$libresoc.v:144018$7813 assign { } { } - assign $0\muxid$1[1:0]$7504 2'00 + assign $0\muxid$1[1:0]$7814 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7504 + update \muxid$1 $0\muxid$1[1:0]$7814 end - attribute \src "libresoc.v:141555.7-141555.26" - process $proc$libresoc.v:141555$7505 + attribute \src "libresoc.v:144033.7-144033.26" + process $proc$libresoc.v:144033$7815 assign { } { } - assign $0\neg_res$15[0:0]$7506 1'0 + assign $0\neg_res$15[0:0]$7816 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$7506 + update \neg_res$15 $0\neg_res$15[0:0]$7816 end - attribute \src "libresoc.v:141564.7-141564.28" - process $proc$libresoc.v:141564$7507 + attribute \src "libresoc.v:144042.7-144042.28" + process $proc$libresoc.v:144042$7817 assign { } { } - assign $0\neg_res32$16[0:0]$7508 1'0 + assign $0\neg_res32$16[0:0]$7818 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$7508 + update \neg_res32$16 $0\neg_res32$16[0:0]$7818 end - attribute \src "libresoc.v:141571.15-141571.57" - process $proc$libresoc.v:141571$7509 + attribute \src "libresoc.v:144049.15-144049.57" + process $proc$libresoc.v:144049$7819 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:141585.7-141585.20" - process $proc$libresoc.v:141585$7510 + attribute \src "libresoc.v:144063.7-144063.20" + process $proc$libresoc.v:144063$7820 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:141596.7-141596.25" - process $proc$libresoc.v:141596$7511 + attribute \src "libresoc.v:144074.7-144074.25" + process $proc$libresoc.v:144074$7821 assign { } { } - assign $0\xer_so$14[0:0]$7512 1'0 + assign $0\xer_so$14[0:0]$7822 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$7512 + update \xer_so$14 $0\xer_so$14[0:0]$7822 end - attribute \src "libresoc.v:141602.3-141603.43" - process $proc$libresoc.v:141602$7394 + attribute \src "libresoc.v:144080.3-144081.43" + process $proc$libresoc.v:144080$7704 assign { } { } - assign $0\neg_res32$16[0:0]$7395 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$7705 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7395 + update \neg_res32$16 $0\neg_res32$16[0:0]$7705 end - attribute \src "libresoc.v:141604.3-141605.39" - process $proc$libresoc.v:141604$7396 + attribute \src "libresoc.v:144082.3-144083.39" + process $proc$libresoc.v:144082$7706 assign { } { } - assign $0\neg_res$15[0:0]$7397 \neg_res$15$next + assign $0\neg_res$15[0:0]$7707 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7397 + update \neg_res$15 $0\neg_res$15[0:0]$7707 end - attribute \src "libresoc.v:141606.3-141607.37" - process $proc$libresoc.v:141606$7398 + attribute \src "libresoc.v:144084.3-144085.37" + process $proc$libresoc.v:144084$7708 assign { } { } - assign $0\xer_so$14[0:0]$7399 \xer_so$14$next + assign $0\xer_so$14[0:0]$7709 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7399 + update \xer_so$14 $0\xer_so$14[0:0]$7709 end - attribute \src "libresoc.v:141608.3-141609.19" - process $proc$libresoc.v:141608$7400 + attribute \src "libresoc.v:144086.3-144087.19" + process $proc$libresoc.v:144086$7710 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:141610.3-141611.57" - process $proc$libresoc.v:141610$7401 + attribute \src "libresoc.v:144088.3-144089.57" + process $proc$libresoc.v:144088$7711 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7402 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$7712 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7402 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7712 end - attribute \src "libresoc.v:141612.3-141613.53" - process $proc$libresoc.v:141612$7403 + attribute \src "libresoc.v:144090.3-144091.53" + process $proc$libresoc.v:144090$7713 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7404 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[11:0]$7714 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7404 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7714 end - attribute \src "libresoc.v:141614.3-141615.67" - process $proc$libresoc.v:141614$7405 + attribute \src "libresoc.v:144092.3-144093.67" + process $proc$libresoc.v:144092$7715 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7406 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$7716 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7406 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7716 end - attribute \src "libresoc.v:141616.3-141617.63" - process $proc$libresoc.v:141616$7407 + attribute \src "libresoc.v:144094.3-144095.63" + process $proc$libresoc.v:144094$7717 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7408 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$7718 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7408 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7718 end - attribute \src "libresoc.v:141618.3-141619.51" - process $proc$libresoc.v:141618$7409 + attribute \src "libresoc.v:144096.3-144097.51" + process $proc$libresoc.v:144096$7719 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7410 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$7720 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7410 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7720 end - attribute \src "libresoc.v:141620.3-141621.51" - process $proc$libresoc.v:141620$7411 + attribute \src "libresoc.v:144098.3-144099.51" + process $proc$libresoc.v:144098$7721 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7412 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$7722 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7412 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7722 end - attribute \src "libresoc.v:141622.3-141623.51" - process $proc$libresoc.v:141622$7413 + attribute \src "libresoc.v:144100.3-144101.51" + process $proc$libresoc.v:144100$7723 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7414 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$7724 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7414 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7724 end - attribute \src "libresoc.v:141624.3-141625.51" - process $proc$libresoc.v:141624$7415 + attribute \src "libresoc.v:144102.3-144103.51" + process $proc$libresoc.v:144102$7725 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7416 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$7726 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7416 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7726 end - attribute \src "libresoc.v:141626.3-141627.59" - process $proc$libresoc.v:141626$7417 + attribute \src "libresoc.v:144104.3-144105.59" + process $proc$libresoc.v:144104$7727 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7418 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$7728 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7418 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7728 end - attribute \src "libresoc.v:141628.3-141629.57" - process $proc$libresoc.v:141628$7419 + attribute \src "libresoc.v:144106.3-144107.57" + process $proc$libresoc.v:144106$7729 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7420 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$7730 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7420 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7730 end - attribute \src "libresoc.v:141630.3-141631.59" - process $proc$libresoc.v:141630$7421 + attribute \src "libresoc.v:144108.3-144109.59" + process $proc$libresoc.v:144108$7731 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7422 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$7732 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7422 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7732 end - attribute \src "libresoc.v:141632.3-141633.49" - process $proc$libresoc.v:141632$7423 + attribute \src "libresoc.v:144110.3-144111.49" + process $proc$libresoc.v:144110$7733 assign { } { } - assign $0\mul_op__insn$13[31:0]$7424 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$7734 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7424 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7734 end - attribute \src "libresoc.v:141634.3-141635.33" - process $proc$libresoc.v:141634$7425 + attribute \src "libresoc.v:144112.3-144113.33" + process $proc$libresoc.v:144112$7735 assign { } { } - assign $0\muxid$1[1:0]$7426 \muxid$1$next + assign $0\muxid$1[1:0]$7736 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7426 + update \muxid$1 $0\muxid$1[1:0]$7736 end - attribute \src "libresoc.v:141636.3-141637.29" - process $proc$libresoc.v:141636$7427 + attribute \src "libresoc.v:144114.3-144115.29" + process $proc$libresoc.v:144114$7737 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:141683.3-141700.6" - process $proc$libresoc.v:141683$7428 + attribute \src "libresoc.v:144161.3-144178.6" + process $proc$libresoc.v:144161$7738 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7429 $2\r_busy$next[0:0]$7431 - attribute \src "libresoc.v:141684.5-141684.29" + assign $0\r_busy$next[0:0]$7739 $2\r_busy$next[0:0]$7741 + attribute \src "libresoc.v:144162.5-144162.29" switch \initial - attribute \src "libresoc.v:141684.9-141684.17" + attribute \src "libresoc.v:144162.9-144162.17" case 1'1 case end @@ -295111,34 +301502,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7430 1'1 + assign $1\r_busy$next[0:0]$7740 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7430 1'0 + assign $1\r_busy$next[0:0]$7740 1'0 case - assign $1\r_busy$next[0:0]$7430 \r_busy + assign $1\r_busy$next[0:0]$7740 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7431 1'0 + assign $2\r_busy$next[0:0]$7741 1'0 case - assign $2\r_busy$next[0:0]$7431 $1\r_busy$next[0:0]$7430 + assign $2\r_busy$next[0:0]$7741 $1\r_busy$next[0:0]$7740 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7429 + update \r_busy$next $0\r_busy$next[0:0]$7739 end - attribute \src "libresoc.v:141701.3-141713.6" - process $proc$libresoc.v:141701$7432 + attribute \src "libresoc.v:144179.3-144191.6" + process $proc$libresoc.v:144179$7742 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7433 $1\muxid$1$next[1:0]$7434 - attribute \src "libresoc.v:141702.5-141702.29" + assign $0\muxid$1$next[1:0]$7743 $1\muxid$1$next[1:0]$7744 + attribute \src "libresoc.v:144180.5-144180.29" switch \initial - attribute \src "libresoc.v:141702.9-141702.17" + attribute \src "libresoc.v:144180.9-144180.17" case 1'1 case end @@ -295147,19 +301538,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7434 \muxid$36 + assign $1\muxid$1$next[1:0]$7744 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7434 \muxid$36 + assign $1\muxid$1$next[1:0]$7744 \muxid$36 case - assign $1\muxid$1$next[1:0]$7434 \muxid$1 + assign $1\muxid$1$next[1:0]$7744 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7433 + update \muxid$1$next $0\muxid$1$next[1:0]$7743 end - attribute \src "libresoc.v:141714.3-141749.6" - process $proc$libresoc.v:141714$7435 + attribute \src "libresoc.v:144192.3-144227.6" + process $proc$libresoc.v:144192$7745 assign { } { } assign { } { } assign { } { } @@ -295184,27 +301575,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7436 $1\mul_op__fn_unit$3$next[11:0]$7448 + assign $0\mul_op__fn_unit$3$next[11:0]$7746 $1\mul_op__fn_unit$3$next[11:0]$7758 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7439 $1\mul_op__insn$13$next[31:0]$7451 - assign $0\mul_op__insn_type$2$next[6:0]$7440 $1\mul_op__insn_type$2$next[6:0]$7452 - assign $0\mul_op__is_32bit$11$next[0:0]$7441 $1\mul_op__is_32bit$11$next[0:0]$7453 - assign $0\mul_op__is_signed$12$next[0:0]$7442 $1\mul_op__is_signed$12$next[0:0]$7454 + assign $0\mul_op__insn$13$next[31:0]$7749 $1\mul_op__insn$13$next[31:0]$7761 + assign $0\mul_op__insn_type$2$next[6:0]$7750 $1\mul_op__insn_type$2$next[6:0]$7762 + assign $0\mul_op__is_32bit$11$next[0:0]$7751 $1\mul_op__is_32bit$11$next[0:0]$7763 + assign $0\mul_op__is_signed$12$next[0:0]$7752 $1\mul_op__is_signed$12$next[0:0]$7764 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7447 $1\mul_op__write_cr0$10$next[0:0]$7459 - assign $0\mul_op__imm_data__data$4$next[63:0]$7437 $2\mul_op__imm_data__data$4$next[63:0]$7460 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7438 $2\mul_op__imm_data__ok$5$next[0:0]$7461 - assign $0\mul_op__oe__oe$8$next[0:0]$7443 $2\mul_op__oe__oe$8$next[0:0]$7462 - assign $0\mul_op__oe__ok$9$next[0:0]$7444 $2\mul_op__oe__ok$9$next[0:0]$7463 - assign $0\mul_op__rc__ok$7$next[0:0]$7445 $2\mul_op__rc__ok$7$next[0:0]$7464 - assign $0\mul_op__rc__rc$6$next[0:0]$7446 $2\mul_op__rc__rc$6$next[0:0]$7465 - attribute \src "libresoc.v:141715.5-141715.29" + assign $0\mul_op__write_cr0$10$next[0:0]$7757 $1\mul_op__write_cr0$10$next[0:0]$7769 + assign $0\mul_op__imm_data__data$4$next[63:0]$7747 $2\mul_op__imm_data__data$4$next[63:0]$7770 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7748 $2\mul_op__imm_data__ok$5$next[0:0]$7771 + assign $0\mul_op__oe__oe$8$next[0:0]$7753 $2\mul_op__oe__oe$8$next[0:0]$7772 + assign $0\mul_op__oe__ok$9$next[0:0]$7754 $2\mul_op__oe__ok$9$next[0:0]$7773 + assign $0\mul_op__rc__ok$7$next[0:0]$7755 $2\mul_op__rc__ok$7$next[0:0]$7774 + assign $0\mul_op__rc__rc$6$next[0:0]$7756 $2\mul_op__rc__rc$6$next[0:0]$7775 + attribute \src "libresoc.v:144193.5-144193.29" switch \initial - attribute \src "libresoc.v:141715.9-141715.17" + attribute \src "libresoc.v:144193.9-144193.17" case 1'1 case end @@ -295224,7 +301615,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7451 $1\mul_op__is_signed$12$next[0:0]$7454 $1\mul_op__is_32bit$11$next[0:0]$7453 $1\mul_op__write_cr0$10$next[0:0]$7459 $1\mul_op__oe__ok$9$next[0:0]$7456 $1\mul_op__oe__oe$8$next[0:0]$7455 $1\mul_op__rc__ok$7$next[0:0]$7457 $1\mul_op__rc__rc$6$next[0:0]$7458 $1\mul_op__imm_data__ok$5$next[0:0]$7450 $1\mul_op__imm_data__data$4$next[63:0]$7449 $1\mul_op__fn_unit$3$next[11:0]$7448 $1\mul_op__insn_type$2$next[6:0]$7452 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$7761 $1\mul_op__is_signed$12$next[0:0]$7764 $1\mul_op__is_32bit$11$next[0:0]$7763 $1\mul_op__write_cr0$10$next[0:0]$7769 $1\mul_op__oe__ok$9$next[0:0]$7766 $1\mul_op__oe__oe$8$next[0:0]$7765 $1\mul_op__rc__ok$7$next[0:0]$7767 $1\mul_op__rc__rc$6$next[0:0]$7768 $1\mul_op__imm_data__ok$5$next[0:0]$7760 $1\mul_op__imm_data__data$4$next[63:0]$7759 $1\mul_op__fn_unit$3$next[11:0]$7758 $1\mul_op__insn_type$2$next[6:0]$7762 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -295239,20 +301630,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7451 $1\mul_op__is_signed$12$next[0:0]$7454 $1\mul_op__is_32bit$11$next[0:0]$7453 $1\mul_op__write_cr0$10$next[0:0]$7459 $1\mul_op__oe__ok$9$next[0:0]$7456 $1\mul_op__oe__oe$8$next[0:0]$7455 $1\mul_op__rc__ok$7$next[0:0]$7457 $1\mul_op__rc__rc$6$next[0:0]$7458 $1\mul_op__imm_data__ok$5$next[0:0]$7450 $1\mul_op__imm_data__data$4$next[63:0]$7449 $1\mul_op__fn_unit$3$next[11:0]$7448 $1\mul_op__insn_type$2$next[6:0]$7452 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$7761 $1\mul_op__is_signed$12$next[0:0]$7764 $1\mul_op__is_32bit$11$next[0:0]$7763 $1\mul_op__write_cr0$10$next[0:0]$7769 $1\mul_op__oe__ok$9$next[0:0]$7766 $1\mul_op__oe__oe$8$next[0:0]$7765 $1\mul_op__rc__ok$7$next[0:0]$7767 $1\mul_op__rc__rc$6$next[0:0]$7768 $1\mul_op__imm_data__ok$5$next[0:0]$7760 $1\mul_op__imm_data__data$4$next[63:0]$7759 $1\mul_op__fn_unit$3$next[11:0]$7758 $1\mul_op__insn_type$2$next[6:0]$7762 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[11:0]$7448 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7449 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7450 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7451 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7452 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7453 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7454 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7455 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7456 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7457 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7458 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7459 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[11:0]$7758 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7759 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7760 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7761 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7762 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7763 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7764 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7765 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7766 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7767 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7768 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7769 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -295264,42 +301655,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7461 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7465 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7464 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7462 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7463 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$7770 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7771 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7775 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7774 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7772 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7773 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$7460 $1\mul_op__imm_data__data$4$next[63:0]$7449 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7461 $1\mul_op__imm_data__ok$5$next[0:0]$7450 - assign $2\mul_op__oe__oe$8$next[0:0]$7462 $1\mul_op__oe__oe$8$next[0:0]$7455 - assign $2\mul_op__oe__ok$9$next[0:0]$7463 $1\mul_op__oe__ok$9$next[0:0]$7456 - assign $2\mul_op__rc__ok$7$next[0:0]$7464 $1\mul_op__rc__ok$7$next[0:0]$7457 - assign $2\mul_op__rc__rc$6$next[0:0]$7465 $1\mul_op__rc__rc$6$next[0:0]$7458 + assign $2\mul_op__imm_data__data$4$next[63:0]$7770 $1\mul_op__imm_data__data$4$next[63:0]$7759 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7771 $1\mul_op__imm_data__ok$5$next[0:0]$7760 + assign $2\mul_op__oe__oe$8$next[0:0]$7772 $1\mul_op__oe__oe$8$next[0:0]$7765 + assign $2\mul_op__oe__ok$9$next[0:0]$7773 $1\mul_op__oe__ok$9$next[0:0]$7766 + assign $2\mul_op__rc__ok$7$next[0:0]$7774 $1\mul_op__rc__ok$7$next[0:0]$7767 + assign $2\mul_op__rc__rc$6$next[0:0]$7775 $1\mul_op__rc__rc$6$next[0:0]$7768 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7436 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7437 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7438 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7439 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7440 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7441 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7442 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7443 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7444 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7445 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7446 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7447 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7746 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7747 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7748 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7749 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7750 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7751 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7752 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7753 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7754 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7755 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7756 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7757 end - attribute \src "libresoc.v:141750.3-141762.6" - process $proc$libresoc.v:141750$7466 + attribute \src "libresoc.v:144228.3-144240.6" + process $proc$libresoc.v:144228$7776 assign { } { } assign { } { } - assign $0\o$next[128:0]$7467 $1\o$next[128:0]$7468 - attribute \src "libresoc.v:141751.5-141751.29" + assign $0\o$next[128:0]$7777 $1\o$next[128:0]$7778 + attribute \src "libresoc.v:144229.5-144229.29" switch \initial - attribute \src "libresoc.v:141751.9-141751.17" + attribute \src "libresoc.v:144229.9-144229.17" case 1'1 case end @@ -295308,25 +301699,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$7468 \o$49 + assign $1\o$next[128:0]$7778 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$7468 \o$49 + assign $1\o$next[128:0]$7778 \o$49 case - assign $1\o$next[128:0]$7468 \o + assign $1\o$next[128:0]$7778 \o end sync always - update \o$next $0\o$next[128:0]$7467 + update \o$next $0\o$next[128:0]$7777 end - attribute \src "libresoc.v:141763.3-141775.6" - process $proc$libresoc.v:141763$7469 + attribute \src "libresoc.v:144241.3-144253.6" + process $proc$libresoc.v:144241$7779 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$7470 $1\xer_so$14$next[0:0]$7471 - attribute \src "libresoc.v:141764.5-141764.29" + assign $0\xer_so$14$next[0:0]$7780 $1\xer_so$14$next[0:0]$7781 + attribute \src "libresoc.v:144242.5-144242.29" switch \initial - attribute \src "libresoc.v:141764.9-141764.17" + attribute \src "libresoc.v:144242.9-144242.17" case 1'1 case end @@ -295335,25 +301726,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$7471 \xer_so$50 + assign $1\xer_so$14$next[0:0]$7781 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$7471 \xer_so$50 + assign $1\xer_so$14$next[0:0]$7781 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$7471 \xer_so$14 + assign $1\xer_so$14$next[0:0]$7781 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$7470 + update \xer_so$14$next $0\xer_so$14$next[0:0]$7780 end - attribute \src "libresoc.v:141776.3-141788.6" - process $proc$libresoc.v:141776$7472 + attribute \src "libresoc.v:144254.3-144266.6" + process $proc$libresoc.v:144254$7782 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$7473 $1\neg_res$15$next[0:0]$7474 - attribute \src "libresoc.v:141777.5-141777.29" + assign $0\neg_res$15$next[0:0]$7783 $1\neg_res$15$next[0:0]$7784 + attribute \src "libresoc.v:144255.5-144255.29" switch \initial - attribute \src "libresoc.v:141777.9-141777.17" + attribute \src "libresoc.v:144255.9-144255.17" case 1'1 case end @@ -295362,25 +301753,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$7474 \neg_res$51 + assign $1\neg_res$15$next[0:0]$7784 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$7474 \neg_res$51 + assign $1\neg_res$15$next[0:0]$7784 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$7474 \neg_res$15 + assign $1\neg_res$15$next[0:0]$7784 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$7473 + update \neg_res$15$next $0\neg_res$15$next[0:0]$7783 end - attribute \src "libresoc.v:141789.3-141801.6" - process $proc$libresoc.v:141789$7475 + attribute \src "libresoc.v:144267.3-144279.6" + process $proc$libresoc.v:144267$7785 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$7476 $1\neg_res32$16$next[0:0]$7477 - attribute \src "libresoc.v:141790.5-141790.29" + assign $0\neg_res32$16$next[0:0]$7786 $1\neg_res32$16$next[0:0]$7787 + attribute \src "libresoc.v:144268.5-144268.29" switch \initial - attribute \src "libresoc.v:141790.9-141790.17" + attribute \src "libresoc.v:144268.9-144268.17" case 1'1 case end @@ -295389,18 +301780,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$7477 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7476 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7786 end - connect \$34 $and$libresoc.v:141601$7393_Y + connect \$34 $and$libresoc.v:144079$7703_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -295420,238 +301811,238 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:141824.1-143099.10" +attribute \src "libresoc.v:144302.1-145577.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:143017.3-143035.6" - wire width 4 $0\cr_a$next[3:0]$7596 - attribute \src "libresoc.v:142809.3-142810.25" + attribute \src "libresoc.v:145495.3-145513.6" + wire width 4 $0\cr_a$next[3:0]$7906 + attribute \src "libresoc.v:145287.3-145288.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:143017.3-143035.6" - wire $0\cr_a_ok$next[0:0]$7597 - attribute \src "libresoc.v:142811.3-142812.31" + attribute \src "libresoc.v:145495.3-145513.6" + wire $0\cr_a_ok$next[0:0]$7907 + attribute \src "libresoc.v:145289.3-145290.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:141825.7-141825.20" + attribute \src "libresoc.v:144303.7-144303.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142962.3-142997.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7559 - attribute \src "libresoc.v:142819.3-142820.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7527 - attribute \src "libresoc.v:142126.14-142126.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7617 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7560 - attribute \src "libresoc.v:142821.3-142822.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7529 - attribute \src "libresoc.v:142148.14-142148.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7619 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7561 - attribute \src "libresoc.v:142823.3-142824.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7531 - attribute \src "libresoc.v:142157.7-142157.38" - wire $0\mul_op__imm_data__ok$5[0:0]$7621 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$7562 - attribute \src "libresoc.v:142839.3-142840.49" - wire width 32 $0\mul_op__insn$13[31:0]$7547 - attribute \src "libresoc.v:142166.14-142166.39" - wire width 32 $0\mul_op__insn$13[31:0]$7623 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7563 - attribute \src "libresoc.v:142817.3-142818.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7525 - attribute \src "libresoc.v:142323.13-142323.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7625 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7564 - attribute \src "libresoc.v:142835.3-142836.57" - wire $0\mul_op__is_32bit$11[0:0]$7543 - attribute \src "libresoc.v:142406.7-142406.35" - wire $0\mul_op__is_32bit$11[0:0]$7627 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__is_signed$12$next[0:0]$7565 - attribute \src "libresoc.v:142837.3-142838.59" - wire $0\mul_op__is_signed$12[0:0]$7545 - attribute \src "libresoc.v:142415.7-142415.36" - wire $0\mul_op__is_signed$12[0:0]$7629 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7566 - attribute \src "libresoc.v:142829.3-142830.51" - wire $0\mul_op__oe__oe$8[0:0]$7537 - attribute \src "libresoc.v:142426.7-142426.32" - wire $0\mul_op__oe__oe$8[0:0]$7631 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7567 - attribute \src "libresoc.v:142831.3-142832.51" - wire $0\mul_op__oe__ok$9[0:0]$7539 - attribute \src "libresoc.v:142435.7-142435.32" - wire $0\mul_op__oe__ok$9[0:0]$7633 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7568 - attribute \src "libresoc.v:142827.3-142828.51" - wire $0\mul_op__rc__ok$7[0:0]$7535 - attribute \src "libresoc.v:142444.7-142444.32" - wire $0\mul_op__rc__ok$7[0:0]$7635 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7569 - attribute \src "libresoc.v:142825.3-142826.51" - wire $0\mul_op__rc__rc$6[0:0]$7533 - attribute \src "libresoc.v:142451.7-142451.32" - wire $0\mul_op__rc__rc$6[0:0]$7637 - attribute \src "libresoc.v:142962.3-142997.6" - wire $0\mul_op__write_cr0$10$next[0:0]$7570 - attribute \src "libresoc.v:142833.3-142834.59" - wire $0\mul_op__write_cr0$10[0:0]$7541 - attribute \src "libresoc.v:142460.7-142460.36" - wire $0\mul_op__write_cr0$10[0:0]$7639 - attribute \src "libresoc.v:142949.3-142961.6" - wire width 2 $0\muxid$1$next[1:0]$7556 - attribute \src "libresoc.v:142841.3-142842.33" - wire width 2 $0\muxid$1[1:0]$7549 - attribute \src "libresoc.v:142469.13-142469.29" - wire width 2 $0\muxid$1[1:0]$7641 - attribute \src "libresoc.v:142998.3-143016.6" - wire width 64 $0\o$14$next[63:0]$7591 - attribute \src "libresoc.v:142813.3-142814.27" - wire width 64 $0\o$14[63:0]$7522 - attribute \src "libresoc.v:142490.14-142490.43" - wire width 64 $0\o$14[63:0]$7643 - attribute \src "libresoc.v:142998.3-143016.6" - wire $0\o_ok$next[0:0]$7590 - attribute \src "libresoc.v:142815.3-142816.25" + attribute \src "libresoc.v:145440.3-145475.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7869 + attribute \src "libresoc.v:145297.3-145298.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7837 + attribute \src "libresoc.v:144604.14-144604.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7927 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7870 + attribute \src "libresoc.v:145299.3-145300.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7839 + attribute \src "libresoc.v:144626.14-144626.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7929 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7871 + attribute \src "libresoc.v:145301.3-145302.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7841 + attribute \src "libresoc.v:144635.7-144635.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7931 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7872 + attribute \src "libresoc.v:145317.3-145318.49" + wire width 32 $0\mul_op__insn$13[31:0]$7857 + attribute \src "libresoc.v:144644.14-144644.39" + wire width 32 $0\mul_op__insn$13[31:0]$7933 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7873 + attribute \src "libresoc.v:145295.3-145296.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7835 + attribute \src "libresoc.v:144801.13-144801.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7935 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7874 + attribute \src "libresoc.v:145313.3-145314.57" + wire $0\mul_op__is_32bit$11[0:0]$7853 + attribute \src "libresoc.v:144884.7-144884.35" + wire $0\mul_op__is_32bit$11[0:0]$7937 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__is_signed$12$next[0:0]$7875 + attribute \src "libresoc.v:145315.3-145316.59" + wire $0\mul_op__is_signed$12[0:0]$7855 + attribute \src "libresoc.v:144893.7-144893.36" + wire $0\mul_op__is_signed$12[0:0]$7939 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7876 + attribute \src "libresoc.v:145307.3-145308.51" + wire $0\mul_op__oe__oe$8[0:0]$7847 + attribute \src "libresoc.v:144904.7-144904.32" + wire $0\mul_op__oe__oe$8[0:0]$7941 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7877 + attribute \src "libresoc.v:145309.3-145310.51" + wire $0\mul_op__oe__ok$9[0:0]$7849 + attribute \src "libresoc.v:144913.7-144913.32" + wire $0\mul_op__oe__ok$9[0:0]$7943 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7878 + attribute \src "libresoc.v:145305.3-145306.51" + wire $0\mul_op__rc__ok$7[0:0]$7845 + attribute \src "libresoc.v:144922.7-144922.32" + wire $0\mul_op__rc__ok$7[0:0]$7945 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7879 + attribute \src "libresoc.v:145303.3-145304.51" + wire $0\mul_op__rc__rc$6[0:0]$7843 + attribute \src "libresoc.v:144929.7-144929.32" + wire $0\mul_op__rc__rc$6[0:0]$7947 + attribute \src "libresoc.v:145440.3-145475.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7880 + attribute \src "libresoc.v:145311.3-145312.59" + wire $0\mul_op__write_cr0$10[0:0]$7851 + attribute \src "libresoc.v:144938.7-144938.36" + wire $0\mul_op__write_cr0$10[0:0]$7949 + attribute \src "libresoc.v:145427.3-145439.6" + wire width 2 $0\muxid$1$next[1:0]$7866 + attribute \src "libresoc.v:145319.3-145320.33" + wire width 2 $0\muxid$1[1:0]$7859 + attribute \src "libresoc.v:144947.13-144947.29" + wire width 2 $0\muxid$1[1:0]$7951 + attribute \src "libresoc.v:145476.3-145494.6" + wire width 64 $0\o$14$next[63:0]$7901 + attribute \src "libresoc.v:145291.3-145292.27" + wire width 64 $0\o$14[63:0]$7832 + attribute \src "libresoc.v:144968.14-144968.43" + wire width 64 $0\o$14[63:0]$7953 + attribute \src "libresoc.v:145476.3-145494.6" + wire $0\o_ok$next[0:0]$7900 + attribute \src "libresoc.v:145293.3-145294.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:142931.3-142948.6" - wire $0\r_busy$next[0:0]$7552 - attribute \src "libresoc.v:142843.3-142844.29" + attribute \src "libresoc.v:145409.3-145426.6" + wire $0\r_busy$next[0:0]$7862 + attribute \src "libresoc.v:145321.3-145322.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:143036.3-143054.6" - wire width 2 $0\xer_ov$next[1:0]$7602 - attribute \src "libresoc.v:142805.3-142806.29" + attribute \src "libresoc.v:145514.3-145532.6" + wire width 2 $0\xer_ov$next[1:0]$7912 + attribute \src "libresoc.v:145283.3-145284.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:143036.3-143054.6" - wire $0\xer_ov_ok$next[0:0]$7603 - attribute \src "libresoc.v:142807.3-142808.35" + attribute \src "libresoc.v:145514.3-145532.6" + wire $0\xer_ov_ok$next[0:0]$7913 + attribute \src "libresoc.v:145285.3-145286.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:143055.3-143073.6" - wire $0\xer_so$15$next[0:0]$7609 - attribute \src "libresoc.v:142801.3-142802.37" - wire $0\xer_so$15[0:0]$7515 - attribute \src "libresoc.v:142786.7-142786.25" - wire $0\xer_so$15[0:0]$7649 - attribute \src "libresoc.v:143055.3-143073.6" - wire $0\xer_so_ok$next[0:0]$7608 - attribute \src "libresoc.v:142803.3-142804.35" + attribute \src "libresoc.v:145533.3-145551.6" + wire $0\xer_so$15$next[0:0]$7919 + attribute \src "libresoc.v:145279.3-145280.37" + wire $0\xer_so$15[0:0]$7825 + attribute \src "libresoc.v:145264.7-145264.25" + wire $0\xer_so$15[0:0]$7959 + attribute \src "libresoc.v:145533.3-145551.6" + wire $0\xer_so_ok$next[0:0]$7918 + attribute \src "libresoc.v:145281.3-145282.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:143017.3-143035.6" - wire width 4 $1\cr_a$next[3:0]$7598 - attribute \src "libresoc.v:141834.13-141834.24" + attribute \src "libresoc.v:145495.3-145513.6" + wire width 4 $1\cr_a$next[3:0]$7908 + attribute \src "libresoc.v:144312.13-144312.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:143017.3-143035.6" - wire $1\cr_a_ok$next[0:0]$7599 - attribute \src "libresoc.v:141843.7-141843.21" + attribute \src "libresoc.v:145495.3-145513.6" + wire $1\cr_a_ok$next[0:0]$7909 + attribute \src "libresoc.v:144321.7-144321.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:142962.3-142997.6" - wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7571 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7572 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$7573 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$7574 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$7575 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__is_32bit$11$next[0:0]$7576 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__is_signed$12$next[0:0]$7577 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__oe__oe$8$next[0:0]$7578 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__oe__ok$9$next[0:0]$7579 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__rc__ok$7$next[0:0]$7580 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__rc__rc$6$next[0:0]$7581 - attribute \src "libresoc.v:142962.3-142997.6" - wire $1\mul_op__write_cr0$10$next[0:0]$7582 - attribute \src "libresoc.v:142949.3-142961.6" - wire width 2 $1\muxid$1$next[1:0]$7557 - attribute \src "libresoc.v:142998.3-143016.6" - wire width 64 $1\o$14$next[63:0]$7593 - attribute \src "libresoc.v:142998.3-143016.6" - wire $1\o_ok$next[0:0]$7592 - attribute \src "libresoc.v:142497.7-142497.18" + attribute \src "libresoc.v:145440.3-145475.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7881 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7882 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7883 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7884 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7885 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7886 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__is_signed$12$next[0:0]$7887 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7888 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7889 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7890 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7891 + attribute \src "libresoc.v:145440.3-145475.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7892 + attribute \src "libresoc.v:145427.3-145439.6" + wire width 2 $1\muxid$1$next[1:0]$7867 + attribute \src "libresoc.v:145476.3-145494.6" + wire width 64 $1\o$14$next[63:0]$7903 + attribute \src "libresoc.v:145476.3-145494.6" + wire $1\o_ok$next[0:0]$7902 + attribute \src "libresoc.v:144975.7-144975.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:142931.3-142948.6" - wire $1\r_busy$next[0:0]$7553 - attribute \src "libresoc.v:142763.7-142763.20" + attribute \src "libresoc.v:145409.3-145426.6" + wire $1\r_busy$next[0:0]$7863 + attribute \src "libresoc.v:145241.7-145241.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:143036.3-143054.6" - wire width 2 $1\xer_ov$next[1:0]$7604 - attribute \src "libresoc.v:142768.13-142768.26" + attribute \src "libresoc.v:145514.3-145532.6" + wire width 2 $1\xer_ov$next[1:0]$7914 + attribute \src "libresoc.v:145246.13-145246.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:143036.3-143054.6" - wire $1\xer_ov_ok$next[0:0]$7605 - attribute \src "libresoc.v:142775.7-142775.23" + attribute \src "libresoc.v:145514.3-145532.6" + wire $1\xer_ov_ok$next[0:0]$7915 + attribute \src "libresoc.v:145253.7-145253.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:143055.3-143073.6" - wire $1\xer_so$15$next[0:0]$7611 - attribute \src "libresoc.v:143055.3-143073.6" - wire $1\xer_so_ok$next[0:0]$7610 - attribute \src "libresoc.v:142793.7-142793.23" + attribute \src "libresoc.v:145533.3-145551.6" + wire $1\xer_so$15$next[0:0]$7921 + attribute \src "libresoc.v:145533.3-145551.6" + wire $1\xer_so_ok$next[0:0]$7920 + attribute \src "libresoc.v:145271.7-145271.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:143017.3-143035.6" - wire $2\cr_a_ok$next[0:0]$7600 - attribute \src "libresoc.v:142962.3-142997.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7583 - attribute \src "libresoc.v:142962.3-142997.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7584 - attribute \src "libresoc.v:142962.3-142997.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7585 - attribute \src "libresoc.v:142962.3-142997.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7586 - attribute \src "libresoc.v:142962.3-142997.6" - wire $2\mul_op__rc__ok$7$next[0:0]$7587 - attribute \src "libresoc.v:142962.3-142997.6" - wire $2\mul_op__rc__rc$6$next[0:0]$7588 - attribute \src "libresoc.v:142998.3-143016.6" - wire $2\o_ok$next[0:0]$7594 - attribute \src "libresoc.v:142931.3-142948.6" - wire $2\r_busy$next[0:0]$7554 - attribute \src "libresoc.v:143036.3-143054.6" - wire $2\xer_ov_ok$next[0:0]$7606 - attribute \src "libresoc.v:143055.3-143073.6" - wire $2\xer_so_ok$next[0:0]$7612 - attribute \src "libresoc.v:142800.18-142800.118" - wire $and$libresoc.v:142800$7513_Y + attribute \src "libresoc.v:145495.3-145513.6" + wire $2\cr_a_ok$next[0:0]$7910 + attribute \src "libresoc.v:145440.3-145475.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7893 + attribute \src "libresoc.v:145440.3-145475.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7894 + attribute \src "libresoc.v:145440.3-145475.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7895 + attribute \src "libresoc.v:145440.3-145475.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7896 + attribute \src "libresoc.v:145440.3-145475.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7897 + attribute \src "libresoc.v:145440.3-145475.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7898 + attribute \src "libresoc.v:145476.3-145494.6" + wire $2\o_ok$next[0:0]$7904 + attribute \src "libresoc.v:145409.3-145426.6" + wire $2\r_busy$next[0:0]$7864 + attribute \src "libresoc.v:145514.3-145532.6" + wire $2\xer_ov_ok$next[0:0]$7916 + attribute \src "libresoc.v:145533.3-145551.6" + wire $2\xer_so_ok$next[0:0]$7922 + attribute \src "libresoc.v:145278.18-145278.118" + wire $and$libresoc.v:145278$7823_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:141825.7-141825.15" + attribute \src "libresoc.v:144303.7-144303.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -295883,19 +302274,19 @@ module \mul_pipe3 wire \mul3_neg_res attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 \mul3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \mul3_o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \mul3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \mul3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_xer_so$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \mul3_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -296276,23 +302667,23 @@ module \mul_pipe3 wire \neg_res32$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 129 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 36 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 37 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -296520,25 +302911,25 @@ module \mul_pipe3 wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \output_muxid$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o @@ -296552,38 +302943,38 @@ module \mul_pipe3 wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 40 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 41 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:142800$7513 + cell $and $and$libresoc.v:145278$7823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -296591,10 +302982,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:142800$7513_Y + connect \Y $and$libresoc.v:145278$7823_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:142845.8-142881.4" + attribute \src "libresoc.v:145323.8-145359.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -296633,14 +303024,14 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:142882.10-142885.4" - cell \n$96 \n + attribute \src "libresoc.v:145360.10-145363.4" + cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:142886.15-142926.4" - cell \output$97 \output + attribute \src "libresoc.v:145364.16-145404.4" + cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 connect \cr_a_ok \output_cr_a_ok @@ -296682,358 +303073,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:142927.10-142930.4" - cell \p$95 \p + attribute \src "libresoc.v:145405.10-145408.4" + cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:141825.7-141825.20" - process $proc$libresoc.v:141825$7613 + attribute \src "libresoc.v:144303.7-144303.20" + process $proc$libresoc.v:144303$7923 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141834.13-141834.24" - process $proc$libresoc.v:141834$7614 + attribute \src "libresoc.v:144312.13-144312.24" + process $proc$libresoc.v:144312$7924 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:141843.7-141843.21" - process $proc$libresoc.v:141843$7615 + attribute \src "libresoc.v:144321.7-144321.21" + process $proc$libresoc.v:144321$7925 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:142126.14-142126.43" - process $proc$libresoc.v:142126$7616 + attribute \src "libresoc.v:144604.14-144604.43" + process $proc$libresoc.v:144604$7926 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7617 12'000000000000 + assign $0\mul_op__fn_unit$3[11:0]$7927 12'000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7617 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7927 end - attribute \src "libresoc.v:142148.14-142148.63" - process $proc$libresoc.v:142148$7618 + attribute \src "libresoc.v:144626.14-144626.63" + process $proc$libresoc.v:144626$7928 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7619 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$7929 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7619 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7929 end - attribute \src "libresoc.v:142157.7-142157.38" - process $proc$libresoc.v:142157$7620 + attribute \src "libresoc.v:144635.7-144635.38" + process $proc$libresoc.v:144635$7930 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7621 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$7931 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7621 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7931 end - attribute \src "libresoc.v:142166.14-142166.39" - process $proc$libresoc.v:142166$7622 + attribute \src "libresoc.v:144644.14-144644.39" + process $proc$libresoc.v:144644$7932 assign { } { } - assign $0\mul_op__insn$13[31:0]$7623 0 + assign $0\mul_op__insn$13[31:0]$7933 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7623 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7933 end - attribute \src "libresoc.v:142323.13-142323.42" - process $proc$libresoc.v:142323$7624 + attribute \src "libresoc.v:144801.13-144801.42" + process $proc$libresoc.v:144801$7934 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7625 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$7935 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7625 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7935 end - attribute \src "libresoc.v:142406.7-142406.35" - process $proc$libresoc.v:142406$7626 + attribute \src "libresoc.v:144884.7-144884.35" + process $proc$libresoc.v:144884$7936 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7627 1'0 + assign $0\mul_op__is_32bit$11[0:0]$7937 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7627 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7937 end - attribute \src "libresoc.v:142415.7-142415.36" - process $proc$libresoc.v:142415$7628 + attribute \src "libresoc.v:144893.7-144893.36" + process $proc$libresoc.v:144893$7938 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7629 1'0 + assign $0\mul_op__is_signed$12[0:0]$7939 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7629 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7939 end - attribute \src "libresoc.v:142426.7-142426.32" - process $proc$libresoc.v:142426$7630 + attribute \src "libresoc.v:144904.7-144904.32" + process $proc$libresoc.v:144904$7940 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7631 1'0 + assign $0\mul_op__oe__oe$8[0:0]$7941 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7631 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7941 end - attribute \src "libresoc.v:142435.7-142435.32" - process $proc$libresoc.v:142435$7632 + attribute \src "libresoc.v:144913.7-144913.32" + process $proc$libresoc.v:144913$7942 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7633 1'0 + assign $0\mul_op__oe__ok$9[0:0]$7943 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7633 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7943 end - attribute \src "libresoc.v:142444.7-142444.32" - process $proc$libresoc.v:142444$7634 + attribute \src "libresoc.v:144922.7-144922.32" + process $proc$libresoc.v:144922$7944 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7635 1'0 + assign $0\mul_op__rc__ok$7[0:0]$7945 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7635 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7945 end - attribute \src "libresoc.v:142451.7-142451.32" - process $proc$libresoc.v:142451$7636 + attribute \src "libresoc.v:144929.7-144929.32" + process $proc$libresoc.v:144929$7946 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7637 1'0 + assign $0\mul_op__rc__rc$6[0:0]$7947 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7637 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7947 end - attribute \src "libresoc.v:142460.7-142460.36" - process $proc$libresoc.v:142460$7638 + attribute \src "libresoc.v:144938.7-144938.36" + process $proc$libresoc.v:144938$7948 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7639 1'0 + assign $0\mul_op__write_cr0$10[0:0]$7949 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7639 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7949 end - attribute \src "libresoc.v:142469.13-142469.29" - process $proc$libresoc.v:142469$7640 + attribute \src "libresoc.v:144947.13-144947.29" + process $proc$libresoc.v:144947$7950 assign { } { } - assign $0\muxid$1[1:0]$7641 2'00 + assign $0\muxid$1[1:0]$7951 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7641 + update \muxid$1 $0\muxid$1[1:0]$7951 end - attribute \src "libresoc.v:142490.14-142490.43" - process $proc$libresoc.v:142490$7642 + attribute \src "libresoc.v:144968.14-144968.43" + process $proc$libresoc.v:144968$7952 assign { } { } - assign $0\o$14[63:0]$7643 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$7953 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$7643 + update \o$14 $0\o$14[63:0]$7953 end - attribute \src "libresoc.v:142497.7-142497.18" - process $proc$libresoc.v:142497$7644 + attribute \src "libresoc.v:144975.7-144975.18" + process $proc$libresoc.v:144975$7954 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:142763.7-142763.20" - process $proc$libresoc.v:142763$7645 + attribute \src "libresoc.v:145241.7-145241.20" + process $proc$libresoc.v:145241$7955 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:142768.13-142768.26" - process $proc$libresoc.v:142768$7646 + attribute \src "libresoc.v:145246.13-145246.26" + process $proc$libresoc.v:145246$7956 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:142775.7-142775.23" - process $proc$libresoc.v:142775$7647 + attribute \src "libresoc.v:145253.7-145253.23" + process $proc$libresoc.v:145253$7957 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:142786.7-142786.25" - process $proc$libresoc.v:142786$7648 + attribute \src "libresoc.v:145264.7-145264.25" + process $proc$libresoc.v:145264$7958 assign { } { } - assign $0\xer_so$15[0:0]$7649 1'0 + assign $0\xer_so$15[0:0]$7959 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$7649 + update \xer_so$15 $0\xer_so$15[0:0]$7959 end - attribute \src "libresoc.v:142793.7-142793.23" - process $proc$libresoc.v:142793$7650 + attribute \src "libresoc.v:145271.7-145271.23" + process $proc$libresoc.v:145271$7960 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:142801.3-142802.37" - process $proc$libresoc.v:142801$7514 + attribute \src "libresoc.v:145279.3-145280.37" + process $proc$libresoc.v:145279$7824 assign { } { } - assign $0\xer_so$15[0:0]$7515 \xer_so$15$next + assign $0\xer_so$15[0:0]$7825 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$7515 + update \xer_so$15 $0\xer_so$15[0:0]$7825 end - attribute \src "libresoc.v:142803.3-142804.35" - process $proc$libresoc.v:142803$7516 + attribute \src "libresoc.v:145281.3-145282.35" + process $proc$libresoc.v:145281$7826 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:142805.3-142806.29" - process $proc$libresoc.v:142805$7517 + attribute \src "libresoc.v:145283.3-145284.29" + process $proc$libresoc.v:145283$7827 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:142807.3-142808.35" - process $proc$libresoc.v:142807$7518 + attribute \src "libresoc.v:145285.3-145286.35" + process $proc$libresoc.v:145285$7828 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:142809.3-142810.25" - process $proc$libresoc.v:142809$7519 + attribute \src "libresoc.v:145287.3-145288.25" + process $proc$libresoc.v:145287$7829 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:142811.3-142812.31" - process $proc$libresoc.v:142811$7520 + attribute \src "libresoc.v:145289.3-145290.31" + process $proc$libresoc.v:145289$7830 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:142813.3-142814.27" - process $proc$libresoc.v:142813$7521 + attribute \src "libresoc.v:145291.3-145292.27" + process $proc$libresoc.v:145291$7831 assign { } { } - assign $0\o$14[63:0]$7522 \o$14$next + assign $0\o$14[63:0]$7832 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$7522 + update \o$14 $0\o$14[63:0]$7832 end - attribute \src "libresoc.v:142815.3-142816.25" - process $proc$libresoc.v:142815$7523 + attribute \src "libresoc.v:145293.3-145294.25" + process $proc$libresoc.v:145293$7833 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:142817.3-142818.57" - process $proc$libresoc.v:142817$7524 + attribute \src "libresoc.v:145295.3-145296.57" + process $proc$libresoc.v:145295$7834 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7525 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$7835 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7525 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7835 end - attribute \src "libresoc.v:142819.3-142820.53" - process $proc$libresoc.v:142819$7526 + attribute \src "libresoc.v:145297.3-145298.53" + process $proc$libresoc.v:145297$7836 assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7527 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[11:0]$7837 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7527 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7837 end - attribute \src "libresoc.v:142821.3-142822.67" - process $proc$libresoc.v:142821$7528 + attribute \src "libresoc.v:145299.3-145300.67" + process $proc$libresoc.v:145299$7838 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7529 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$7839 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7529 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7839 end - attribute \src "libresoc.v:142823.3-142824.63" - process $proc$libresoc.v:142823$7530 + attribute \src "libresoc.v:145301.3-145302.63" + process $proc$libresoc.v:145301$7840 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7531 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$7841 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7531 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7841 end - attribute \src "libresoc.v:142825.3-142826.51" - process $proc$libresoc.v:142825$7532 + attribute \src "libresoc.v:145303.3-145304.51" + process $proc$libresoc.v:145303$7842 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7533 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$7843 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7533 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7843 end - attribute \src "libresoc.v:142827.3-142828.51" - process $proc$libresoc.v:142827$7534 + attribute \src "libresoc.v:145305.3-145306.51" + process $proc$libresoc.v:145305$7844 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7535 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$7845 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7535 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7845 end - attribute \src "libresoc.v:142829.3-142830.51" - process $proc$libresoc.v:142829$7536 + attribute \src "libresoc.v:145307.3-145308.51" + process $proc$libresoc.v:145307$7846 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7537 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$7847 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7537 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7847 end - attribute \src "libresoc.v:142831.3-142832.51" - process $proc$libresoc.v:142831$7538 + attribute \src "libresoc.v:145309.3-145310.51" + process $proc$libresoc.v:145309$7848 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7539 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$7849 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7539 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7849 end - attribute \src "libresoc.v:142833.3-142834.59" - process $proc$libresoc.v:142833$7540 + attribute \src "libresoc.v:145311.3-145312.59" + process $proc$libresoc.v:145311$7850 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7541 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$7851 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7541 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7851 end - attribute \src "libresoc.v:142835.3-142836.57" - process $proc$libresoc.v:142835$7542 + attribute \src "libresoc.v:145313.3-145314.57" + process $proc$libresoc.v:145313$7852 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7543 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$7853 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7543 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7853 end - attribute \src "libresoc.v:142837.3-142838.59" - process $proc$libresoc.v:142837$7544 + attribute \src "libresoc.v:145315.3-145316.59" + process $proc$libresoc.v:145315$7854 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7545 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$7855 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7545 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7855 end - attribute \src "libresoc.v:142839.3-142840.49" - process $proc$libresoc.v:142839$7546 + attribute \src "libresoc.v:145317.3-145318.49" + process $proc$libresoc.v:145317$7856 assign { } { } - assign $0\mul_op__insn$13[31:0]$7547 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$7857 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7547 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7857 end - attribute \src "libresoc.v:142841.3-142842.33" - process $proc$libresoc.v:142841$7548 + attribute \src "libresoc.v:145319.3-145320.33" + process $proc$libresoc.v:145319$7858 assign { } { } - assign $0\muxid$1[1:0]$7549 \muxid$1$next + assign $0\muxid$1[1:0]$7859 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7549 + update \muxid$1 $0\muxid$1[1:0]$7859 end - attribute \src "libresoc.v:142843.3-142844.29" - process $proc$libresoc.v:142843$7550 + attribute \src "libresoc.v:145321.3-145322.29" + process $proc$libresoc.v:145321$7860 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:142931.3-142948.6" - process $proc$libresoc.v:142931$7551 + attribute \src "libresoc.v:145409.3-145426.6" + process $proc$libresoc.v:145409$7861 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7552 $2\r_busy$next[0:0]$7554 - attribute \src "libresoc.v:142932.5-142932.29" + assign $0\r_busy$next[0:0]$7862 $2\r_busy$next[0:0]$7864 + attribute \src "libresoc.v:145410.5-145410.29" switch \initial - attribute \src "libresoc.v:142932.9-142932.17" + attribute \src "libresoc.v:145410.9-145410.17" case 1'1 case end @@ -297042,34 +303433,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7553 1'1 + assign $1\r_busy$next[0:0]$7863 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7553 1'0 + assign $1\r_busy$next[0:0]$7863 1'0 case - assign $1\r_busy$next[0:0]$7553 \r_busy + assign $1\r_busy$next[0:0]$7863 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7554 1'0 + assign $2\r_busy$next[0:0]$7864 1'0 case - assign $2\r_busy$next[0:0]$7554 $1\r_busy$next[0:0]$7553 + assign $2\r_busy$next[0:0]$7864 $1\r_busy$next[0:0]$7863 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7552 + update \r_busy$next $0\r_busy$next[0:0]$7862 end - attribute \src "libresoc.v:142949.3-142961.6" - process $proc$libresoc.v:142949$7555 + attribute \src "libresoc.v:145427.3-145439.6" + process $proc$libresoc.v:145427$7865 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7556 $1\muxid$1$next[1:0]$7557 - attribute \src "libresoc.v:142950.5-142950.29" + assign $0\muxid$1$next[1:0]$7866 $1\muxid$1$next[1:0]$7867 + attribute \src "libresoc.v:145428.5-145428.29" switch \initial - attribute \src "libresoc.v:142950.9-142950.17" + attribute \src "libresoc.v:145428.9-145428.17" case 1'1 case end @@ -297078,19 +303469,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7557 \muxid$58 + assign $1\muxid$1$next[1:0]$7867 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7557 \muxid$58 + assign $1\muxid$1$next[1:0]$7867 \muxid$58 case - assign $1\muxid$1$next[1:0]$7557 \muxid$1 + assign $1\muxid$1$next[1:0]$7867 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7556 + update \muxid$1$next $0\muxid$1$next[1:0]$7866 end - attribute \src "libresoc.v:142962.3-142997.6" - process $proc$libresoc.v:142962$7558 + attribute \src "libresoc.v:145440.3-145475.6" + process $proc$libresoc.v:145440$7868 assign { } { } assign { } { } assign { } { } @@ -297115,27 +303506,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7559 $1\mul_op__fn_unit$3$next[11:0]$7571 + assign $0\mul_op__fn_unit$3$next[11:0]$7869 $1\mul_op__fn_unit$3$next[11:0]$7881 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7562 $1\mul_op__insn$13$next[31:0]$7574 - assign $0\mul_op__insn_type$2$next[6:0]$7563 $1\mul_op__insn_type$2$next[6:0]$7575 - assign $0\mul_op__is_32bit$11$next[0:0]$7564 $1\mul_op__is_32bit$11$next[0:0]$7576 - assign $0\mul_op__is_signed$12$next[0:0]$7565 $1\mul_op__is_signed$12$next[0:0]$7577 + assign $0\mul_op__insn$13$next[31:0]$7872 $1\mul_op__insn$13$next[31:0]$7884 + assign $0\mul_op__insn_type$2$next[6:0]$7873 $1\mul_op__insn_type$2$next[6:0]$7885 + assign $0\mul_op__is_32bit$11$next[0:0]$7874 $1\mul_op__is_32bit$11$next[0:0]$7886 + assign $0\mul_op__is_signed$12$next[0:0]$7875 $1\mul_op__is_signed$12$next[0:0]$7887 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7570 $1\mul_op__write_cr0$10$next[0:0]$7582 - assign $0\mul_op__imm_data__data$4$next[63:0]$7560 $2\mul_op__imm_data__data$4$next[63:0]$7583 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7561 $2\mul_op__imm_data__ok$5$next[0:0]$7584 - assign $0\mul_op__oe__oe$8$next[0:0]$7566 $2\mul_op__oe__oe$8$next[0:0]$7585 - assign $0\mul_op__oe__ok$9$next[0:0]$7567 $2\mul_op__oe__ok$9$next[0:0]$7586 - assign $0\mul_op__rc__ok$7$next[0:0]$7568 $2\mul_op__rc__ok$7$next[0:0]$7587 - assign $0\mul_op__rc__rc$6$next[0:0]$7569 $2\mul_op__rc__rc$6$next[0:0]$7588 - attribute \src "libresoc.v:142963.5-142963.29" + assign $0\mul_op__write_cr0$10$next[0:0]$7880 $1\mul_op__write_cr0$10$next[0:0]$7892 + assign $0\mul_op__imm_data__data$4$next[63:0]$7870 $2\mul_op__imm_data__data$4$next[63:0]$7893 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7871 $2\mul_op__imm_data__ok$5$next[0:0]$7894 + assign $0\mul_op__oe__oe$8$next[0:0]$7876 $2\mul_op__oe__oe$8$next[0:0]$7895 + assign $0\mul_op__oe__ok$9$next[0:0]$7877 $2\mul_op__oe__ok$9$next[0:0]$7896 + assign $0\mul_op__rc__ok$7$next[0:0]$7878 $2\mul_op__rc__ok$7$next[0:0]$7897 + assign $0\mul_op__rc__rc$6$next[0:0]$7879 $2\mul_op__rc__rc$6$next[0:0]$7898 + attribute \src "libresoc.v:145441.5-145441.29" switch \initial - attribute \src "libresoc.v:142963.9-142963.17" + attribute \src "libresoc.v:145441.9-145441.17" case 1'1 case end @@ -297155,7 +303546,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7574 $1\mul_op__is_signed$12$next[0:0]$7577 $1\mul_op__is_32bit$11$next[0:0]$7576 $1\mul_op__write_cr0$10$next[0:0]$7582 $1\mul_op__oe__ok$9$next[0:0]$7579 $1\mul_op__oe__oe$8$next[0:0]$7578 $1\mul_op__rc__ok$7$next[0:0]$7580 $1\mul_op__rc__rc$6$next[0:0]$7581 $1\mul_op__imm_data__ok$5$next[0:0]$7573 $1\mul_op__imm_data__data$4$next[63:0]$7572 $1\mul_op__fn_unit$3$next[11:0]$7571 $1\mul_op__insn_type$2$next[6:0]$7575 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$7884 $1\mul_op__is_signed$12$next[0:0]$7887 $1\mul_op__is_32bit$11$next[0:0]$7886 $1\mul_op__write_cr0$10$next[0:0]$7892 $1\mul_op__oe__ok$9$next[0:0]$7889 $1\mul_op__oe__oe$8$next[0:0]$7888 $1\mul_op__rc__ok$7$next[0:0]$7890 $1\mul_op__rc__rc$6$next[0:0]$7891 $1\mul_op__imm_data__ok$5$next[0:0]$7883 $1\mul_op__imm_data__data$4$next[63:0]$7882 $1\mul_op__fn_unit$3$next[11:0]$7881 $1\mul_op__insn_type$2$next[6:0]$7885 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -297170,20 +303561,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7574 $1\mul_op__is_signed$12$next[0:0]$7577 $1\mul_op__is_32bit$11$next[0:0]$7576 $1\mul_op__write_cr0$10$next[0:0]$7582 $1\mul_op__oe__ok$9$next[0:0]$7579 $1\mul_op__oe__oe$8$next[0:0]$7578 $1\mul_op__rc__ok$7$next[0:0]$7580 $1\mul_op__rc__rc$6$next[0:0]$7581 $1\mul_op__imm_data__ok$5$next[0:0]$7573 $1\mul_op__imm_data__data$4$next[63:0]$7572 $1\mul_op__fn_unit$3$next[11:0]$7571 $1\mul_op__insn_type$2$next[6:0]$7575 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$7884 $1\mul_op__is_signed$12$next[0:0]$7887 $1\mul_op__is_32bit$11$next[0:0]$7886 $1\mul_op__write_cr0$10$next[0:0]$7892 $1\mul_op__oe__ok$9$next[0:0]$7889 $1\mul_op__oe__oe$8$next[0:0]$7888 $1\mul_op__rc__ok$7$next[0:0]$7890 $1\mul_op__rc__rc$6$next[0:0]$7891 $1\mul_op__imm_data__ok$5$next[0:0]$7883 $1\mul_op__imm_data__data$4$next[63:0]$7882 $1\mul_op__fn_unit$3$next[11:0]$7881 $1\mul_op__insn_type$2$next[6:0]$7885 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[11:0]$7571 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7572 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7573 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7574 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7575 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7576 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7577 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7578 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7579 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7580 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7581 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7582 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[11:0]$7881 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7882 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7883 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7884 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7885 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7886 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7887 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7888 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7889 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7890 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7891 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7892 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -297195,46 +303586,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7583 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7584 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7588 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7587 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7585 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7586 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$7893 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7894 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7898 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7897 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7895 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7896 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$7583 $1\mul_op__imm_data__data$4$next[63:0]$7572 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7584 $1\mul_op__imm_data__ok$5$next[0:0]$7573 - assign $2\mul_op__oe__oe$8$next[0:0]$7585 $1\mul_op__oe__oe$8$next[0:0]$7578 - assign $2\mul_op__oe__ok$9$next[0:0]$7586 $1\mul_op__oe__ok$9$next[0:0]$7579 - assign $2\mul_op__rc__ok$7$next[0:0]$7587 $1\mul_op__rc__ok$7$next[0:0]$7580 - assign $2\mul_op__rc__rc$6$next[0:0]$7588 $1\mul_op__rc__rc$6$next[0:0]$7581 + assign $2\mul_op__imm_data__data$4$next[63:0]$7893 $1\mul_op__imm_data__data$4$next[63:0]$7882 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7894 $1\mul_op__imm_data__ok$5$next[0:0]$7883 + assign $2\mul_op__oe__oe$8$next[0:0]$7895 $1\mul_op__oe__oe$8$next[0:0]$7888 + assign $2\mul_op__oe__ok$9$next[0:0]$7896 $1\mul_op__oe__ok$9$next[0:0]$7889 + assign $2\mul_op__rc__ok$7$next[0:0]$7897 $1\mul_op__rc__ok$7$next[0:0]$7890 + assign $2\mul_op__rc__rc$6$next[0:0]$7898 $1\mul_op__rc__rc$6$next[0:0]$7891 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7559 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7560 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7561 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7562 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7563 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7564 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7565 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7566 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7567 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7568 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7569 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7570 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7869 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7870 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7871 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7872 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7873 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7874 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7875 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7876 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7877 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7878 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7879 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7880 end - attribute \src "libresoc.v:142998.3-143016.6" - process $proc$libresoc.v:142998$7589 + attribute \src "libresoc.v:145476.3-145494.6" + process $proc$libresoc.v:145476$7899 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$7591 $1\o$14$next[63:0]$7593 - assign $0\o_ok$next[0:0]$7590 $2\o_ok$next[0:0]$7594 - attribute \src "libresoc.v:142999.5-142999.29" + assign $0\o$14$next[63:0]$7901 $1\o$14$next[63:0]$7903 + assign $0\o_ok$next[0:0]$7900 $2\o_ok$next[0:0]$7904 + attribute \src "libresoc.v:145477.5-145477.29" switch \initial - attribute \src "libresoc.v:142999.9-142999.17" + attribute \src "libresoc.v:145477.9-145477.17" case 1'1 case end @@ -297244,41 +303635,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$7592 $1\o$14$next[63:0]$7593 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$7902 $1\o$14$next[63:0]$7903 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$7592 $1\o$14$next[63:0]$7593 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$7902 $1\o$14$next[63:0]$7903 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$7592 \o_ok - assign $1\o$14$next[63:0]$7593 \o$14 + assign $1\o_ok$next[0:0]$7902 \o_ok + assign $1\o$14$next[63:0]$7903 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$7594 1'0 + assign $2\o_ok$next[0:0]$7904 1'0 case - assign $2\o_ok$next[0:0]$7594 $1\o_ok$next[0:0]$7592 + assign $2\o_ok$next[0:0]$7904 $1\o_ok$next[0:0]$7902 end sync always - update \o_ok$next $0\o_ok$next[0:0]$7590 - update \o$14$next $0\o$14$next[63:0]$7591 + update \o_ok$next $0\o_ok$next[0:0]$7900 + update \o$14$next $0\o$14$next[63:0]$7901 end - attribute \src "libresoc.v:143017.3-143035.6" - process $proc$libresoc.v:143017$7595 + attribute \src "libresoc.v:145495.3-145513.6" + process $proc$libresoc.v:145495$7905 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$7596 $1\cr_a$next[3:0]$7598 + assign $0\cr_a$next[3:0]$7906 $1\cr_a$next[3:0]$7908 assign { } { } - assign $0\cr_a_ok$next[0:0]$7597 $2\cr_a_ok$next[0:0]$7600 - attribute \src "libresoc.v:143018.5-143018.29" + assign $0\cr_a_ok$next[0:0]$7907 $2\cr_a_ok$next[0:0]$7910 + attribute \src "libresoc.v:145496.5-145496.29" switch \initial - attribute \src "libresoc.v:143018.9-143018.17" + attribute \src "libresoc.v:145496.9-145496.17" case 1'1 case end @@ -297288,41 +303679,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$7599 $1\cr_a$next[3:0]$7598 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$7909 $1\cr_a$next[3:0]$7908 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$7599 $1\cr_a$next[3:0]$7598 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$7909 $1\cr_a$next[3:0]$7908 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$7598 \cr_a - assign $1\cr_a_ok$next[0:0]$7599 \cr_a_ok + assign $1\cr_a$next[3:0]$7908 \cr_a + assign $1\cr_a_ok$next[0:0]$7909 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$7600 1'0 + assign $2\cr_a_ok$next[0:0]$7910 1'0 case - assign $2\cr_a_ok$next[0:0]$7600 $1\cr_a_ok$next[0:0]$7599 + assign $2\cr_a_ok$next[0:0]$7910 $1\cr_a_ok$next[0:0]$7909 end sync always - update \cr_a$next $0\cr_a$next[3:0]$7596 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7597 + update \cr_a$next $0\cr_a$next[3:0]$7906 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7907 end - attribute \src "libresoc.v:143036.3-143054.6" - process $proc$libresoc.v:143036$7601 + attribute \src "libresoc.v:145514.3-145532.6" + process $proc$libresoc.v:145514$7911 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$7602 $1\xer_ov$next[1:0]$7604 + assign $0\xer_ov$next[1:0]$7912 $1\xer_ov$next[1:0]$7914 assign { } { } - assign $0\xer_ov_ok$next[0:0]$7603 $2\xer_ov_ok$next[0:0]$7606 - attribute \src "libresoc.v:143037.5-143037.29" + assign $0\xer_ov_ok$next[0:0]$7913 $2\xer_ov_ok$next[0:0]$7916 + attribute \src "libresoc.v:145515.5-145515.29" switch \initial - attribute \src "libresoc.v:143037.9-143037.17" + attribute \src "libresoc.v:145515.9-145515.17" case 1'1 case end @@ -297332,41 +303723,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7605 $1\xer_ov$next[1:0]$7604 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$7915 $1\xer_ov$next[1:0]$7914 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7605 $1\xer_ov$next[1:0]$7604 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$7915 $1\xer_ov$next[1:0]$7914 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$7604 \xer_ov - assign $1\xer_ov_ok$next[0:0]$7605 \xer_ov_ok + assign $1\xer_ov$next[1:0]$7914 \xer_ov + assign $1\xer_ov_ok$next[0:0]$7915 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$7606 1'0 + assign $2\xer_ov_ok$next[0:0]$7916 1'0 case - assign $2\xer_ov_ok$next[0:0]$7606 $1\xer_ov_ok$next[0:0]$7605 + assign $2\xer_ov_ok$next[0:0]$7916 $1\xer_ov_ok$next[0:0]$7915 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$7602 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7603 + update \xer_ov$next $0\xer_ov$next[1:0]$7912 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7913 end - attribute \src "libresoc.v:143055.3-143073.6" - process $proc$libresoc.v:143055$7607 + attribute \src "libresoc.v:145533.3-145551.6" + process $proc$libresoc.v:145533$7917 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$7609 $1\xer_so$15$next[0:0]$7611 - assign $0\xer_so_ok$next[0:0]$7608 $2\xer_so_ok$next[0:0]$7612 - attribute \src "libresoc.v:143056.5-143056.29" + assign $0\xer_so$15$next[0:0]$7919 $1\xer_so$15$next[0:0]$7921 + assign $0\xer_so_ok$next[0:0]$7918 $2\xer_so_ok$next[0:0]$7922 + attribute \src "libresoc.v:145534.5-145534.29" switch \initial - attribute \src "libresoc.v:143056.9-143056.17" + attribute \src "libresoc.v:145534.9-145534.17" case 1'1 case end @@ -297376,30 +303767,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$7610 $1\xer_so$15$next[0:0]$7611 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$7920 $1\xer_so$15$next[0:0]$7921 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$7610 $1\xer_so$15$next[0:0]$7611 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$7920 $1\xer_so$15$next[0:0]$7921 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$7610 \xer_so_ok - assign $1\xer_so$15$next[0:0]$7611 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$7920 \xer_so_ok + assign $1\xer_so$15$next[0:0]$7921 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$7612 1'0 + assign $2\xer_so_ok$next[0:0]$7922 1'0 case - assign $2\xer_so_ok$next[0:0]$7612 $1\xer_so_ok$next[0:0]$7610 + assign $2\xer_so_ok$next[0:0]$7922 $1\xer_so_ok$next[0:0]$7920 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7608 - update \xer_so$15$next $0\xer_so$15$next[0:0]$7609 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7918 + update \xer_so$15$next $0\xer_so$15$next[0:0]$7919 end - connect \$56 $and$libresoc.v:142800$7513_Y + connect \$56 $and$libresoc.v:145278$7823_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -297426,13 +303817,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:143103.1-143114.10" +attribute \src "libresoc.v:145581.1-145592.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:143112.17-143112.111" - wire $and$libresoc.v:143112$7651_Y + attribute \src "libresoc.v:145590.17-145590.111" + wire $and$libresoc.v:145590$7961_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297442,7 +303833,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143112$7651 + cell $and $and$libresoc.v:145590$7961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297450,18 +303841,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143112$7651_Y + connect \Y $and$libresoc.v:145590$7961_Y end - connect \$1 $and$libresoc.v:143112$7651_Y + connect \$1 $and$libresoc.v:145590$7961_Y connect \trigger \$1 end -attribute \src "libresoc.v:143118.1-143129.10" +attribute \src "libresoc.v:145596.1-145607.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" -module \n$106 - attribute \src "libresoc.v:143127.17-143127.111" - wire $and$libresoc.v:143127$7652_Y +module \n$109 + attribute \src "libresoc.v:145605.17-145605.111" + wire $and$libresoc.v:145605$7962_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297471,7 +303862,7 @@ module \n$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143127$7652 + cell $and $and$libresoc.v:145605$7962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297479,18 +303870,18 @@ module \n$106 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143127$7652_Y + connect \Y $and$libresoc.v:145605$7962_Y end - connect \$1 $and$libresoc.v:143127$7652_Y + connect \$1 $and$libresoc.v:145605$7962_Y connect \trigger \$1 end -attribute \src "libresoc.v:143133.1-143144.10" +attribute \src "libresoc.v:145611.1-145622.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" -module \n$109 - attribute \src "libresoc.v:143142.17-143142.111" - wire $and$libresoc.v:143142$7653_Y +module \n$112 + attribute \src "libresoc.v:145620.17-145620.111" + wire $and$libresoc.v:145620$7963_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297500,7 +303891,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143142$7653 + cell $and $and$libresoc.v:145620$7963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297508,18 +303899,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143142$7653_Y + connect \Y $and$libresoc.v:145620$7963_Y end - connect \$1 $and$libresoc.v:143142$7653_Y + connect \$1 $and$libresoc.v:145620$7963_Y connect \trigger \$1 end -attribute \src "libresoc.v:143148.1-143159.10" +attribute \src "libresoc.v:145626.1-145637.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" -module \n$114 - attribute \src "libresoc.v:143157.17-143157.111" - wire $and$libresoc.v:143157$7654_Y +module \n$117 + attribute \src "libresoc.v:145635.17-145635.111" + wire $and$libresoc.v:145635$7964_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297529,7 +303920,7 @@ module \n$114 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143157$7654 + cell $and $and$libresoc.v:145635$7964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297537,18 +303928,18 @@ module \n$114 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143157$7654_Y + connect \Y $and$libresoc.v:145635$7964_Y end - connect \$1 $and$libresoc.v:143157$7654_Y + connect \$1 $and$libresoc.v:145635$7964_Y connect \trigger \$1 end -attribute \src "libresoc.v:143163.1-143174.10" +attribute \src "libresoc.v:145641.1-145652.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:143172.17-143172.111" - wire $and$libresoc.v:143172$7655_Y + attribute \src "libresoc.v:145650.17-145650.111" + wire $and$libresoc.v:145650$7965_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297558,7 +303949,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143172$7655 + cell $and $and$libresoc.v:145650$7965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297566,18 +303957,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143172$7655_Y + connect \Y $and$libresoc.v:145650$7965_Y end - connect \$1 $and$libresoc.v:143172$7655_Y + connect \$1 $and$libresoc.v:145650$7965_Y connect \trigger \$1 end -attribute \src "libresoc.v:143178.1-143189.10" +attribute \src "libresoc.v:145656.1-145667.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:143187.17-143187.111" - wire $and$libresoc.v:143187$7656_Y + attribute \src "libresoc.v:145665.17-145665.111" + wire $and$libresoc.v:145665$7966_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297587,7 +303978,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143187$7656 + cell $and $and$libresoc.v:145665$7966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297595,18 +303986,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143187$7656_Y + connect \Y $and$libresoc.v:145665$7966_Y end - connect \$1 $and$libresoc.v:143187$7656_Y + connect \$1 $and$libresoc.v:145665$7966_Y connect \trigger \$1 end -attribute \src "libresoc.v:143193.1-143204.10" +attribute \src "libresoc.v:145671.1-145682.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:143202.17-143202.111" - wire $and$libresoc.v:143202$7657_Y + attribute \src "libresoc.v:145680.17-145680.111" + wire $and$libresoc.v:145680$7967_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297616,7 +304007,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143202$7657 + cell $and $and$libresoc.v:145680$7967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297624,18 +304015,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143202$7657_Y + connect \Y $and$libresoc.v:145680$7967_Y end - connect \$1 $and$libresoc.v:143202$7657_Y + connect \$1 $and$libresoc.v:145680$7967_Y connect \trigger \$1 end -attribute \src "libresoc.v:143208.1-143219.10" +attribute \src "libresoc.v:145686.1-145697.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:143217.17-143217.111" - wire $and$libresoc.v:143217$7658_Y + attribute \src "libresoc.v:145695.17-145695.111" + wire $and$libresoc.v:145695$7968_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297645,7 +304036,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143217$7658 + cell $and $and$libresoc.v:145695$7968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297653,18 +304044,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143217$7658_Y + connect \Y $and$libresoc.v:145695$7968_Y end - connect \$1 $and$libresoc.v:143217$7658_Y + connect \$1 $and$libresoc.v:145695$7968_Y connect \trigger \$1 end -attribute \src "libresoc.v:143223.1-143234.10" +attribute \src "libresoc.v:145701.1-145712.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:143232.17-143232.111" - wire $and$libresoc.v:143232$7659_Y + attribute \src "libresoc.v:145710.17-145710.111" + wire $and$libresoc.v:145710$7969_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297674,7 +304065,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143232$7659 + cell $and $and$libresoc.v:145710$7969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297682,18 +304073,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143232$7659_Y + connect \Y $and$libresoc.v:145710$7969_Y end - connect \$1 $and$libresoc.v:143232$7659_Y + connect \$1 $and$libresoc.v:145710$7969_Y connect \trigger \$1 end -attribute \src "libresoc.v:143238.1-143249.10" +attribute \src "libresoc.v:145716.1-145727.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" -module \n$4 - attribute \src "libresoc.v:143247.17-143247.111" - wire $and$libresoc.v:143247$7660_Y +module \n$37 + attribute \src "libresoc.v:145725.17-145725.111" + wire $and$libresoc.v:145725$7970_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297703,7 +304094,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143247$7660 + cell $and $and$libresoc.v:145725$7970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297711,18 +304102,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143247$7660_Y + connect \Y $and$libresoc.v:145725$7970_Y end - connect \$1 $and$libresoc.v:143247$7660_Y + connect \$1 $and$libresoc.v:145725$7970_Y connect \trigger \$1 end -attribute \src "libresoc.v:143253.1-143264.10" +attribute \src "libresoc.v:145731.1-145742.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" -module \n$44 - attribute \src "libresoc.v:143262.17-143262.111" - wire $and$libresoc.v:143262$7661_Y +module \n$4 + attribute \src "libresoc.v:145740.17-145740.111" + wire $and$libresoc.v:145740$7971_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297732,7 +304123,7 @@ module \n$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143262$7661 + cell $and $and$libresoc.v:145740$7971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297740,18 +304131,18 @@ module \n$44 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143262$7661_Y + connect \Y $and$libresoc.v:145740$7971_Y end - connect \$1 $and$libresoc.v:143262$7661_Y + connect \$1 $and$libresoc.v:145740$7971_Y connect \trigger \$1 end -attribute \src "libresoc.v:143268.1-143279.10" +attribute \src "libresoc.v:145746.1-145757.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" -module \n$46 - attribute \src "libresoc.v:143277.17-143277.111" - wire $and$libresoc.v:143277$7662_Y +module \n$47 + attribute \src "libresoc.v:145755.17-145755.111" + wire $and$libresoc.v:145755$7972_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297761,7 +304152,7 @@ module \n$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143277$7662 + cell $and $and$libresoc.v:145755$7972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297769,18 +304160,18 @@ module \n$46 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143277$7662_Y + connect \Y $and$libresoc.v:145755$7972_Y end - connect \$1 $and$libresoc.v:143277$7662_Y + connect \$1 $and$libresoc.v:145755$7972_Y connect \trigger \$1 end -attribute \src "libresoc.v:143283.1-143294.10" +attribute \src "libresoc.v:145761.1-145772.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" -module \n$50 - attribute \src "libresoc.v:143292.17-143292.111" - wire $and$libresoc.v:143292$7663_Y +module \n$49 + attribute \src "libresoc.v:145770.17-145770.111" + wire $and$libresoc.v:145770$7973_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297790,7 +304181,7 @@ module \n$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143292$7663 + cell $and $and$libresoc.v:145770$7973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297798,18 +304189,18 @@ module \n$50 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143292$7663_Y + connect \Y $and$libresoc.v:145770$7973_Y end - connect \$1 $and$libresoc.v:143292$7663_Y + connect \$1 $and$libresoc.v:145770$7973_Y connect \trigger \$1 end -attribute \src "libresoc.v:143298.1-143309.10" +attribute \src "libresoc.v:145776.1-145787.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" -module \n$6 - attribute \src "libresoc.v:143307.17-143307.111" - wire $and$libresoc.v:143307$7664_Y +module \n$53 + attribute \src "libresoc.v:145785.17-145785.111" + wire $and$libresoc.v:145785$7974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297819,7 +304210,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143307$7664 + cell $and $and$libresoc.v:145785$7974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297827,18 +304218,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143307$7664_Y + connect \Y $and$libresoc.v:145785$7974_Y end - connect \$1 $and$libresoc.v:143307$7664_Y + connect \$1 $and$libresoc.v:145785$7974_Y connect \trigger \$1 end -attribute \src "libresoc.v:143313.1-143324.10" +attribute \src "libresoc.v:145791.1-145802.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" -module \n$60 - attribute \src "libresoc.v:143322.17-143322.111" - wire $and$libresoc.v:143322$7665_Y +module \n$6 + attribute \src "libresoc.v:145800.17-145800.111" + wire $and$libresoc.v:145800$7975_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297848,7 +304239,7 @@ module \n$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143322$7665 + cell $and $and$libresoc.v:145800$7975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297856,18 +304247,18 @@ module \n$60 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143322$7665_Y + connect \Y $and$libresoc.v:145800$7975_Y end - connect \$1 $and$libresoc.v:143322$7665_Y + connect \$1 $and$libresoc.v:145800$7975_Y connect \trigger \$1 end -attribute \src "libresoc.v:143328.1-143339.10" +attribute \src "libresoc.v:145806.1-145817.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:143337.17-143337.111" - wire $and$libresoc.v:143337$7666_Y + attribute \src "libresoc.v:145815.17-145815.111" + wire $and$libresoc.v:145815$7976_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297877,7 +304268,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143337$7666 + cell $and $and$libresoc.v:145815$7976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297885,18 +304276,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143337$7666_Y + connect \Y $and$libresoc.v:145815$7976_Y end - connect \$1 $and$libresoc.v:143337$7666_Y + connect \$1 $and$libresoc.v:145815$7976_Y connect \trigger \$1 end -attribute \src "libresoc.v:143343.1-143354.10" +attribute \src "libresoc.v:145821.1-145832.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" -module \n$72 - attribute \src "libresoc.v:143352.17-143352.111" - wire $and$libresoc.v:143352$7667_Y +module \n$66 + attribute \src "libresoc.v:145830.17-145830.111" + wire $and$libresoc.v:145830$7977_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297906,7 +304297,7 @@ module \n$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143352$7667 + cell $and $and$libresoc.v:145830$7977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297914,18 +304305,18 @@ module \n$72 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143352$7667_Y + connect \Y $and$libresoc.v:145830$7977_Y end - connect \$1 $and$libresoc.v:143352$7667_Y + connect \$1 $and$libresoc.v:145830$7977_Y connect \trigger \$1 end -attribute \src "libresoc.v:143358.1-143369.10" +attribute \src "libresoc.v:145836.1-145847.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" -module \n$74 - attribute \src "libresoc.v:143367.17-143367.111" - wire $and$libresoc.v:143367$7668_Y +module \n$75 + attribute \src "libresoc.v:145845.17-145845.111" + wire $and$libresoc.v:145845$7978_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297935,7 +304326,7 @@ module \n$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143367$7668 + cell $and $and$libresoc.v:145845$7978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297943,18 +304334,18 @@ module \n$74 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143367$7668_Y + connect \Y $and$libresoc.v:145845$7978_Y end - connect \$1 $and$libresoc.v:143367$7668_Y + connect \$1 $and$libresoc.v:145845$7978_Y connect \trigger \$1 end -attribute \src "libresoc.v:143373.1-143384.10" +attribute \src "libresoc.v:145851.1-145862.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:143382.17-143382.111" - wire $and$libresoc.v:143382$7669_Y + attribute \src "libresoc.v:145860.17-145860.111" + wire $and$libresoc.v:145860$7979_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297964,7 +304355,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143382$7669 + cell $and $and$libresoc.v:145860$7979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -297972,18 +304363,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143382$7669_Y + connect \Y $and$libresoc.v:145860$7979_Y end - connect \$1 $and$libresoc.v:143382$7669_Y + connect \$1 $and$libresoc.v:145860$7979_Y connect \trigger \$1 end -attribute \src "libresoc.v:143388.1-143399.10" +attribute \src "libresoc.v:145866.1-145877.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" -module \n$79 - attribute \src "libresoc.v:143397.17-143397.111" - wire $and$libresoc.v:143397$7670_Y +module \n$8 + attribute \src "libresoc.v:145875.17-145875.111" + wire $and$libresoc.v:145875$7980_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -297993,7 +304384,7 @@ module \n$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143397$7670 + cell $and $and$libresoc.v:145875$7980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298001,18 +304392,18 @@ module \n$79 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143397$7670_Y + connect \Y $and$libresoc.v:145875$7980_Y end - connect \$1 $and$libresoc.v:143397$7670_Y + connect \$1 $and$libresoc.v:145875$7980_Y connect \trigger \$1 end -attribute \src "libresoc.v:143403.1-143414.10" +attribute \src "libresoc.v:145881.1-145892.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" -module \n$8 - attribute \src "libresoc.v:143412.17-143412.111" - wire $and$libresoc.v:143412$7671_Y +module \n$80 + attribute \src "libresoc.v:145890.17-145890.111" + wire $and$libresoc.v:145890$7981_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -298022,7 +304413,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143412$7671 + cell $and $and$libresoc.v:145890$7981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298030,18 +304421,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143412$7671_Y + connect \Y $and$libresoc.v:145890$7981_Y end - connect \$1 $and$libresoc.v:143412$7671_Y + connect \$1 $and$libresoc.v:145890$7981_Y connect \trigger \$1 end -attribute \src "libresoc.v:143418.1-143429.10" +attribute \src "libresoc.v:145896.1-145907.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" -module \n$89 - attribute \src "libresoc.v:143427.17-143427.111" - wire $and$libresoc.v:143427$7672_Y +module \n$82 + attribute \src "libresoc.v:145905.17-145905.111" + wire $and$libresoc.v:145905$7982_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -298051,7 +304442,7 @@ module \n$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143427$7672 + cell $and $and$libresoc.v:145905$7982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298059,18 +304450,18 @@ module \n$89 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143427$7672_Y + connect \Y $and$libresoc.v:145905$7982_Y end - connect \$1 $and$libresoc.v:143427$7672_Y + connect \$1 $and$libresoc.v:145905$7982_Y connect \trigger \$1 end -attribute \src "libresoc.v:143433.1-143444.10" +attribute \src "libresoc.v:145911.1-145922.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" -module \n$91 - attribute \src "libresoc.v:143442.17-143442.111" - wire $and$libresoc.v:143442$7673_Y +module \n$92 + attribute \src "libresoc.v:145920.17-145920.111" + wire $and$libresoc.v:145920$7983_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -298080,7 +304471,7 @@ module \n$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143442$7673 + cell $and $and$libresoc.v:145920$7983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298088,18 +304479,18 @@ module \n$91 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143442$7673_Y + connect \Y $and$libresoc.v:145920$7983_Y end - connect \$1 $and$libresoc.v:143442$7673_Y + connect \$1 $and$libresoc.v:145920$7983_Y connect \trigger \$1 end -attribute \src "libresoc.v:143448.1-143459.10" +attribute \src "libresoc.v:145926.1-145937.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:143457.17-143457.111" - wire $and$libresoc.v:143457$7674_Y + attribute \src "libresoc.v:145935.17-145935.111" + wire $and$libresoc.v:145935$7984_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -298109,7 +304500,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143457$7674 + cell $and $and$libresoc.v:145935$7984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298117,18 +304508,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143457$7674_Y + connect \Y $and$libresoc.v:145935$7984_Y end - connect \$1 $and$libresoc.v:143457$7674_Y + connect \$1 $and$libresoc.v:145935$7984_Y connect \trigger \$1 end -attribute \src "libresoc.v:143463.1-143474.10" +attribute \src "libresoc.v:145941.1-145952.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" -module \n$96 - attribute \src "libresoc.v:143472.17-143472.111" - wire $and$libresoc.v:143472$7675_Y +module \n$97 + attribute \src "libresoc.v:145950.17-145950.111" + wire $and$libresoc.v:145950$7985_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -298138,7 +304529,7 @@ module \n$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:143472$7675 + cell $and $and$libresoc.v:145950$7985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298146,246 +304537,71 @@ module \n$96 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:143472$7675_Y + connect \Y $and$libresoc.v:145950$7985_Y end - connect \$1 $and$libresoc.v:143472$7675_Y + connect \$1 $and$libresoc.v:145950$7985_Y connect \trigger \$1 end -attribute \src "libresoc.v:143478.1-143536.10" +attribute \src "libresoc.v:145956.1-145967.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" -module \opc_l - attribute \src "libresoc.v:143479.7-143479.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:143524.3-143532.6" - wire $0\q_int$next[0:0]$7686 - attribute \src "libresoc.v:143522.3-143523.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:143524.3-143532.6" - wire $1\q_int$next[0:0]$7687 - attribute \src "libresoc.v:143501.7-143501.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:143514.17-143514.96" - wire $and$libresoc.v:143514$7676_Y - attribute \src "libresoc.v:143519.17-143519.96" - wire $and$libresoc.v:143519$7681_Y - attribute \src "libresoc.v:143516.18-143516.93" - wire $not$libresoc.v:143516$7678_Y - attribute \src "libresoc.v:143518.17-143518.92" - wire $not$libresoc.v:143518$7680_Y - attribute \src "libresoc.v:143521.17-143521.92" - wire $not$libresoc.v:143521$7683_Y - attribute \src "libresoc.v:143515.18-143515.98" - wire $or$libresoc.v:143515$7677_Y - attribute \src "libresoc.v:143517.18-143517.99" - wire $or$libresoc.v:143517$7679_Y - attribute \src "libresoc.v:143520.17-143520.97" - wire $or$libresoc.v:143520$7682_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +module \n$99 + attribute \src "libresoc.v:145965.17-145965.111" + wire $and$libresoc.v:145965$7986_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "libresoc.v:143479.7-143479.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143514$7676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:143514$7676_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143519$7681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:143519$7681_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143516$7678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:143516$7678_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143518$7680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:143518$7680_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143521$7683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:143521$7683_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143515$7677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:143515$7677_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143517$7679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:143517$7679_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143520$7682 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$libresoc.v:145965$7986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:143520$7682_Y - end - attribute \src "libresoc.v:143479.7-143479.20" - process $proc$libresoc.v:143479$7688 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:143501.7-143501.19" - process $proc$libresoc.v:143501$7689 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:143522.3-143523.27" - process $proc$libresoc.v:143522$7684 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:143524.3-143532.6" - process $proc$libresoc.v:143524$7685 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$7686 $1\q_int$next[0:0]$7687 - attribute \src "libresoc.v:143525.5-143525.29" - switch \initial - attribute \src "libresoc.v:143525.9-143525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7687 1'0 - case - assign $1\q_int$next[0:0]$7687 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$7686 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:145965$7986_Y end - connect \$9 $and$libresoc.v:143514$7676_Y - connect \$11 $or$libresoc.v:143515$7677_Y - connect \$13 $not$libresoc.v:143516$7678_Y - connect \$15 $or$libresoc.v:143517$7679_Y - connect \$1 $not$libresoc.v:143518$7680_Y - connect \$3 $and$libresoc.v:143519$7681_Y - connect \$5 $or$libresoc.v:143520$7682_Y - connect \$7 $not$libresoc.v:143521$7683_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 + connect \$1 $and$libresoc.v:145965$7986_Y + connect \trigger \$1 end -attribute \src "libresoc.v:143540.1-143598.10" +attribute \src "libresoc.v:145971.1-146029.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" -module \opc_l$11 - attribute \src "libresoc.v:143541.7-143541.20" +module \opc_l + attribute \src "libresoc.v:145972.7-145972.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143586.3-143594.6" - wire $0\q_int$next[0:0]$7700 - attribute \src "libresoc.v:143584.3-143585.27" + attribute \src "libresoc.v:146017.3-146025.6" + wire $0\q_int$next[0:0]$7997 + attribute \src "libresoc.v:146015.3-146016.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143586.3-143594.6" - wire $1\q_int$next[0:0]$7701 - attribute \src "libresoc.v:143563.7-143563.19" + attribute \src "libresoc.v:146017.3-146025.6" + wire $1\q_int$next[0:0]$7998 + attribute \src "libresoc.v:145994.7-145994.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143576.17-143576.96" - wire $and$libresoc.v:143576$7690_Y - attribute \src "libresoc.v:143581.17-143581.96" - wire $and$libresoc.v:143581$7695_Y - attribute \src "libresoc.v:143578.18-143578.93" - wire $not$libresoc.v:143578$7692_Y - attribute \src "libresoc.v:143580.17-143580.92" - wire $not$libresoc.v:143580$7694_Y - attribute \src "libresoc.v:143583.17-143583.92" - wire $not$libresoc.v:143583$7697_Y - attribute \src "libresoc.v:143577.18-143577.98" - wire $or$libresoc.v:143577$7691_Y - attribute \src "libresoc.v:143579.18-143579.99" - wire $or$libresoc.v:143579$7693_Y - attribute \src "libresoc.v:143582.17-143582.97" - wire $or$libresoc.v:143582$7696_Y + attribute \src "libresoc.v:146007.17-146007.96" + wire $and$libresoc.v:146007$7987_Y + attribute \src "libresoc.v:146012.17-146012.96" + wire $and$libresoc.v:146012$7992_Y + attribute \src "libresoc.v:146009.18-146009.93" + wire $not$libresoc.v:146009$7989_Y + attribute \src "libresoc.v:146011.17-146011.92" + wire $not$libresoc.v:146011$7991_Y + attribute \src "libresoc.v:146014.17-146014.92" + wire $not$libresoc.v:146014$7994_Y + attribute \src "libresoc.v:146008.18-146008.98" + wire $or$libresoc.v:146008$7988_Y + attribute \src "libresoc.v:146010.18-146010.99" + wire $or$libresoc.v:146010$7990_Y + attribute \src "libresoc.v:146013.17-146013.97" + wire $or$libresoc.v:146013$7993_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -298402,11 +304618,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143541.7-143541.15" + attribute \src "libresoc.v:145972.7-145972.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -298423,7 +304639,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143576$7690 + cell $and $and$libresoc.v:146007$7987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298431,10 +304647,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143576$7690_Y + connect \Y $and$libresoc.v:146007$7987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143581$7695 + cell $and $and$libresoc.v:146012$7992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298442,34 +304658,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143581$7695_Y + connect \Y $and$libresoc.v:146012$7992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143578$7692 + cell $not $not$libresoc.v:146009$7989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143578$7692_Y + connect \Y $not$libresoc.v:146009$7989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143580$7694 + cell $not $not$libresoc.v:146011$7991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143580$7694_Y + connect \Y $not$libresoc.v:146011$7991_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143583$7697 + cell $not $not$libresoc.v:146014$7994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143583$7697_Y + connect \Y $not$libresoc.v:146014$7994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143577$7691 + cell $or $or$libresoc.v:146008$7988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298477,10 +304693,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143577$7691_Y + connect \Y $or$libresoc.v:146008$7988_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143579$7693 + cell $or $or$libresoc.v:146010$7990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298488,10 +304704,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143579$7693_Y + connect \Y $or$libresoc.v:146010$7990_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143582$7696 + cell $or $or$libresoc.v:146013$7993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298499,39 +304715,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143582$7696_Y + connect \Y $or$libresoc.v:146013$7993_Y end - attribute \src "libresoc.v:143541.7-143541.20" - process $proc$libresoc.v:143541$7702 + attribute \src "libresoc.v:145972.7-145972.20" + process $proc$libresoc.v:145972$7999 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143563.7-143563.19" - process $proc$libresoc.v:143563$7703 + attribute \src "libresoc.v:145994.7-145994.19" + process $proc$libresoc.v:145994$8000 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143584.3-143585.27" - process $proc$libresoc.v:143584$7698 + attribute \src "libresoc.v:146015.3-146016.27" + process $proc$libresoc.v:146015$7995 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143586.3-143594.6" - process $proc$libresoc.v:143586$7699 + attribute \src "libresoc.v:146017.3-146025.6" + process $proc$libresoc.v:146017$7996 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7700 $1\q_int$next[0:0]$7701 - attribute \src "libresoc.v:143587.5-143587.29" + assign $0\q_int$next[0:0]$7997 $1\q_int$next[0:0]$7998 + attribute \src "libresoc.v:146018.5-146018.29" switch \initial - attribute \src "libresoc.v:143587.9-143587.17" + attribute \src "libresoc.v:146018.9-146018.17" case 1'1 case end @@ -298540,56 +304756,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7701 1'0 + assign $1\q_int$next[0:0]$7998 1'0 case - assign $1\q_int$next[0:0]$7701 \$5 + assign $1\q_int$next[0:0]$7998 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7700 + update \q_int$next $0\q_int$next[0:0]$7997 end - connect \$9 $and$libresoc.v:143576$7690_Y - connect \$11 $or$libresoc.v:143577$7691_Y - connect \$13 $not$libresoc.v:143578$7692_Y - connect \$15 $or$libresoc.v:143579$7693_Y - connect \$1 $not$libresoc.v:143580$7694_Y - connect \$3 $and$libresoc.v:143581$7695_Y - connect \$5 $or$libresoc.v:143582$7696_Y - connect \$7 $not$libresoc.v:143583$7697_Y + connect \$9 $and$libresoc.v:146007$7987_Y + connect \$11 $or$libresoc.v:146008$7988_Y + connect \$13 $not$libresoc.v:146009$7989_Y + connect \$15 $or$libresoc.v:146010$7990_Y + connect \$1 $not$libresoc.v:146011$7991_Y + connect \$3 $and$libresoc.v:146012$7992_Y + connect \$5 $or$libresoc.v:146013$7993_Y + connect \$7 $not$libresoc.v:146014$7994_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143602.1-143660.10" +attribute \src "libresoc.v:146033.1-146091.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" -module \opc_l$117 - attribute \src "libresoc.v:143603.7-143603.20" +module \opc_l$102 + attribute \src "libresoc.v:146034.7-146034.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143648.3-143656.6" - wire $0\q_int$next[0:0]$7714 - attribute \src "libresoc.v:143646.3-143647.27" + attribute \src "libresoc.v:146079.3-146087.6" + wire $0\q_int$next[0:0]$8011 + attribute \src "libresoc.v:146077.3-146078.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143648.3-143656.6" - wire $1\q_int$next[0:0]$7715 - attribute \src "libresoc.v:143625.7-143625.19" + attribute \src "libresoc.v:146079.3-146087.6" + wire $1\q_int$next[0:0]$8012 + attribute \src "libresoc.v:146056.7-146056.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143638.17-143638.96" - wire $and$libresoc.v:143638$7704_Y - attribute \src "libresoc.v:143643.17-143643.96" - wire $and$libresoc.v:143643$7709_Y - attribute \src "libresoc.v:143640.18-143640.93" - wire $not$libresoc.v:143640$7706_Y - attribute \src "libresoc.v:143642.17-143642.92" - wire $not$libresoc.v:143642$7708_Y - attribute \src "libresoc.v:143645.17-143645.92" - wire $not$libresoc.v:143645$7711_Y - attribute \src "libresoc.v:143639.18-143639.98" - wire $or$libresoc.v:143639$7705_Y - attribute \src "libresoc.v:143641.18-143641.99" - wire $or$libresoc.v:143641$7707_Y - attribute \src "libresoc.v:143644.17-143644.97" - wire $or$libresoc.v:143644$7710_Y + attribute \src "libresoc.v:146069.17-146069.96" + wire $and$libresoc.v:146069$8001_Y + attribute \src "libresoc.v:146074.17-146074.96" + wire $and$libresoc.v:146074$8006_Y + attribute \src "libresoc.v:146071.18-146071.93" + wire $not$libresoc.v:146071$8003_Y + attribute \src "libresoc.v:146073.17-146073.92" + wire $not$libresoc.v:146073$8005_Y + attribute \src "libresoc.v:146076.17-146076.92" + wire $not$libresoc.v:146076$8008_Y + attribute \src "libresoc.v:146070.18-146070.98" + wire $or$libresoc.v:146070$8002_Y + attribute \src "libresoc.v:146072.18-146072.99" + wire $or$libresoc.v:146072$8004_Y + attribute \src "libresoc.v:146075.17-146075.97" + wire $or$libresoc.v:146075$8007_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -298606,11 +304822,11 @@ module \opc_l$117 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143603.7-143603.15" + attribute \src "libresoc.v:146034.7-146034.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -298627,7 +304843,7 @@ module \opc_l$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143638$7704 + cell $and $and$libresoc.v:146069$8001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298635,10 +304851,10 @@ module \opc_l$117 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143638$7704_Y + connect \Y $and$libresoc.v:146069$8001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143643$7709 + cell $and $and$libresoc.v:146074$8006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298646,34 +304862,34 @@ module \opc_l$117 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143643$7709_Y + connect \Y $and$libresoc.v:146074$8006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143640$7706 + cell $not $not$libresoc.v:146071$8003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143640$7706_Y + connect \Y $not$libresoc.v:146071$8003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143642$7708 + cell $not $not$libresoc.v:146073$8005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143642$7708_Y + connect \Y $not$libresoc.v:146073$8005_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143645$7711 + cell $not $not$libresoc.v:146076$8008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143645$7711_Y + connect \Y $not$libresoc.v:146076$8008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143639$7705 + cell $or $or$libresoc.v:146070$8002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298681,10 +304897,10 @@ module \opc_l$117 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143639$7705_Y + connect \Y $or$libresoc.v:146070$8002_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143641$7707 + cell $or $or$libresoc.v:146072$8004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298692,10 +304908,10 @@ module \opc_l$117 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143641$7707_Y + connect \Y $or$libresoc.v:146072$8004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143644$7710 + cell $or $or$libresoc.v:146075$8007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298703,39 +304919,39 @@ module \opc_l$117 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143644$7710_Y + connect \Y $or$libresoc.v:146075$8007_Y end - attribute \src "libresoc.v:143603.7-143603.20" - process $proc$libresoc.v:143603$7716 + attribute \src "libresoc.v:146034.7-146034.20" + process $proc$libresoc.v:146034$8013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143625.7-143625.19" - process $proc$libresoc.v:143625$7717 + attribute \src "libresoc.v:146056.7-146056.19" + process $proc$libresoc.v:146056$8014 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143646.3-143647.27" - process $proc$libresoc.v:143646$7712 + attribute \src "libresoc.v:146077.3-146078.27" + process $proc$libresoc.v:146077$8009 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143648.3-143656.6" - process $proc$libresoc.v:143648$7713 + attribute \src "libresoc.v:146079.3-146087.6" + process $proc$libresoc.v:146079$8010 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7714 $1\q_int$next[0:0]$7715 - attribute \src "libresoc.v:143649.5-143649.29" + assign $0\q_int$next[0:0]$8011 $1\q_int$next[0:0]$8012 + attribute \src "libresoc.v:146080.5-146080.29" switch \initial - attribute \src "libresoc.v:143649.9-143649.17" + attribute \src "libresoc.v:146080.9-146080.17" case 1'1 case end @@ -298744,56 +304960,56 @@ module \opc_l$117 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7715 1'0 + assign $1\q_int$next[0:0]$8012 1'0 case - assign $1\q_int$next[0:0]$7715 \$5 + assign $1\q_int$next[0:0]$8012 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7714 + update \q_int$next $0\q_int$next[0:0]$8011 end - connect \$9 $and$libresoc.v:143638$7704_Y - connect \$11 $or$libresoc.v:143639$7705_Y - connect \$13 $not$libresoc.v:143640$7706_Y - connect \$15 $or$libresoc.v:143641$7707_Y - connect \$1 $not$libresoc.v:143642$7708_Y - connect \$3 $and$libresoc.v:143643$7709_Y - connect \$5 $or$libresoc.v:143644$7710_Y - connect \$7 $not$libresoc.v:143645$7711_Y + connect \$9 $and$libresoc.v:146069$8001_Y + connect \$11 $or$libresoc.v:146070$8002_Y + connect \$13 $not$libresoc.v:146071$8003_Y + connect \$15 $or$libresoc.v:146072$8004_Y + connect \$1 $not$libresoc.v:146073$8005_Y + connect \$3 $and$libresoc.v:146074$8006_Y + connect \$5 $or$libresoc.v:146075$8007_Y + connect \$7 $not$libresoc.v:146076$8008_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143664.1-143722.10" +attribute \src "libresoc.v:146095.1-146153.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" -module \opc_l$123 - attribute \src "libresoc.v:143665.7-143665.20" +module \opc_l$11 + attribute \src "libresoc.v:146096.7-146096.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143710.3-143718.6" - wire $0\q_int$next[0:0]$7728 - attribute \src "libresoc.v:143708.3-143709.27" + attribute \src "libresoc.v:146141.3-146149.6" + wire $0\q_int$next[0:0]$8025 + attribute \src "libresoc.v:146139.3-146140.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143710.3-143718.6" - wire $1\q_int$next[0:0]$7729 - attribute \src "libresoc.v:143687.7-143687.19" + attribute \src "libresoc.v:146141.3-146149.6" + wire $1\q_int$next[0:0]$8026 + attribute \src "libresoc.v:146118.7-146118.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143700.17-143700.96" - wire $and$libresoc.v:143700$7718_Y - attribute \src "libresoc.v:143705.17-143705.96" - wire $and$libresoc.v:143705$7723_Y - attribute \src "libresoc.v:143702.18-143702.93" - wire $not$libresoc.v:143702$7720_Y - attribute \src "libresoc.v:143704.17-143704.92" - wire $not$libresoc.v:143704$7722_Y - attribute \src "libresoc.v:143707.17-143707.92" - wire $not$libresoc.v:143707$7725_Y - attribute \src "libresoc.v:143701.18-143701.98" - wire $or$libresoc.v:143701$7719_Y - attribute \src "libresoc.v:143703.18-143703.99" - wire $or$libresoc.v:143703$7721_Y - attribute \src "libresoc.v:143706.17-143706.97" - wire $or$libresoc.v:143706$7724_Y + attribute \src "libresoc.v:146131.17-146131.96" + wire $and$libresoc.v:146131$8015_Y + attribute \src "libresoc.v:146136.17-146136.96" + wire $and$libresoc.v:146136$8020_Y + attribute \src "libresoc.v:146133.18-146133.93" + wire $not$libresoc.v:146133$8017_Y + attribute \src "libresoc.v:146135.17-146135.92" + wire $not$libresoc.v:146135$8019_Y + attribute \src "libresoc.v:146138.17-146138.92" + wire $not$libresoc.v:146138$8022_Y + attribute \src "libresoc.v:146132.18-146132.98" + wire $or$libresoc.v:146132$8016_Y + attribute \src "libresoc.v:146134.18-146134.99" + wire $or$libresoc.v:146134$8018_Y + attribute \src "libresoc.v:146137.17-146137.97" + wire $or$libresoc.v:146137$8021_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -298810,11 +305026,11 @@ module \opc_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143665.7-143665.15" + attribute \src "libresoc.v:146096.7-146096.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -298831,7 +305047,7 @@ module \opc_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143700$7718 + cell $and $and$libresoc.v:146131$8015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298839,10 +305055,10 @@ module \opc_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143700$7718_Y + connect \Y $and$libresoc.v:146131$8015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143705$7723 + cell $and $and$libresoc.v:146136$8020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298850,34 +305066,34 @@ module \opc_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143705$7723_Y + connect \Y $and$libresoc.v:146136$8020_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143702$7720 + cell $not $not$libresoc.v:146133$8017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143702$7720_Y + connect \Y $not$libresoc.v:146133$8017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143704$7722 + cell $not $not$libresoc.v:146135$8019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143704$7722_Y + connect \Y $not$libresoc.v:146135$8019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143707$7725 + cell $not $not$libresoc.v:146138$8022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143707$7725_Y + connect \Y $not$libresoc.v:146138$8022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143701$7719 + cell $or $or$libresoc.v:146132$8016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298885,10 +305101,10 @@ module \opc_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143701$7719_Y + connect \Y $or$libresoc.v:146132$8016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143703$7721 + cell $or $or$libresoc.v:146134$8018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298896,10 +305112,10 @@ module \opc_l$123 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143703$7721_Y + connect \Y $or$libresoc.v:146134$8018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143706$7724 + cell $or $or$libresoc.v:146137$8021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -298907,39 +305123,39 @@ module \opc_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143706$7724_Y + connect \Y $or$libresoc.v:146137$8021_Y end - attribute \src "libresoc.v:143665.7-143665.20" - process $proc$libresoc.v:143665$7730 + attribute \src "libresoc.v:146096.7-146096.20" + process $proc$libresoc.v:146096$8027 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143687.7-143687.19" - process $proc$libresoc.v:143687$7731 + attribute \src "libresoc.v:146118.7-146118.19" + process $proc$libresoc.v:146118$8028 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143708.3-143709.27" - process $proc$libresoc.v:143708$7726 + attribute \src "libresoc.v:146139.3-146140.27" + process $proc$libresoc.v:146139$8023 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143710.3-143718.6" - process $proc$libresoc.v:143710$7727 + attribute \src "libresoc.v:146141.3-146149.6" + process $proc$libresoc.v:146141$8024 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7728 $1\q_int$next[0:0]$7729 - attribute \src "libresoc.v:143711.5-143711.29" + assign $0\q_int$next[0:0]$8025 $1\q_int$next[0:0]$8026 + attribute \src "libresoc.v:146142.5-146142.29" switch \initial - attribute \src "libresoc.v:143711.9-143711.17" + attribute \src "libresoc.v:146142.9-146142.17" case 1'1 case end @@ -298948,56 +305164,56 @@ module \opc_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7729 1'0 + assign $1\q_int$next[0:0]$8026 1'0 case - assign $1\q_int$next[0:0]$7729 \$5 + assign $1\q_int$next[0:0]$8026 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7728 + update \q_int$next $0\q_int$next[0:0]$8025 end - connect \$9 $and$libresoc.v:143700$7718_Y - connect \$11 $or$libresoc.v:143701$7719_Y - connect \$13 $not$libresoc.v:143702$7720_Y - connect \$15 $or$libresoc.v:143703$7721_Y - connect \$1 $not$libresoc.v:143704$7722_Y - connect \$3 $and$libresoc.v:143705$7723_Y - connect \$5 $or$libresoc.v:143706$7724_Y - connect \$7 $not$libresoc.v:143707$7725_Y + connect \$9 $and$libresoc.v:146131$8015_Y + connect \$11 $or$libresoc.v:146132$8016_Y + connect \$13 $not$libresoc.v:146133$8017_Y + connect \$15 $or$libresoc.v:146134$8018_Y + connect \$1 $not$libresoc.v:146135$8019_Y + connect \$3 $and$libresoc.v:146136$8020_Y + connect \$5 $or$libresoc.v:146137$8021_Y + connect \$7 $not$libresoc.v:146138$8022_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143726.1-143784.10" +attribute \src "libresoc.v:146157.1-146215.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" -module \opc_l$24 - attribute \src "libresoc.v:143727.7-143727.20" +module \opc_l$120 + attribute \src "libresoc.v:146158.7-146158.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143772.3-143780.6" - wire $0\q_int$next[0:0]$7742 - attribute \src "libresoc.v:143770.3-143771.27" + attribute \src "libresoc.v:146203.3-146211.6" + wire $0\q_int$next[0:0]$8039 + attribute \src "libresoc.v:146201.3-146202.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143772.3-143780.6" - wire $1\q_int$next[0:0]$7743 - attribute \src "libresoc.v:143749.7-143749.19" + attribute \src "libresoc.v:146203.3-146211.6" + wire $1\q_int$next[0:0]$8040 + attribute \src "libresoc.v:146180.7-146180.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143762.17-143762.96" - wire $and$libresoc.v:143762$7732_Y - attribute \src "libresoc.v:143767.17-143767.96" - wire $and$libresoc.v:143767$7737_Y - attribute \src "libresoc.v:143764.18-143764.93" - wire $not$libresoc.v:143764$7734_Y - attribute \src "libresoc.v:143766.17-143766.92" - wire $not$libresoc.v:143766$7736_Y - attribute \src "libresoc.v:143769.17-143769.92" - wire $not$libresoc.v:143769$7739_Y - attribute \src "libresoc.v:143763.18-143763.98" - wire $or$libresoc.v:143763$7733_Y - attribute \src "libresoc.v:143765.18-143765.99" - wire $or$libresoc.v:143765$7735_Y - attribute \src "libresoc.v:143768.17-143768.97" - wire $or$libresoc.v:143768$7738_Y + attribute \src "libresoc.v:146193.17-146193.96" + wire $and$libresoc.v:146193$8029_Y + attribute \src "libresoc.v:146198.17-146198.96" + wire $and$libresoc.v:146198$8034_Y + attribute \src "libresoc.v:146195.18-146195.93" + wire $not$libresoc.v:146195$8031_Y + attribute \src "libresoc.v:146197.17-146197.92" + wire $not$libresoc.v:146197$8033_Y + attribute \src "libresoc.v:146200.17-146200.92" + wire $not$libresoc.v:146200$8036_Y + attribute \src "libresoc.v:146194.18-146194.98" + wire $or$libresoc.v:146194$8030_Y + attribute \src "libresoc.v:146196.18-146196.99" + wire $or$libresoc.v:146196$8032_Y + attribute \src "libresoc.v:146199.17-146199.97" + wire $or$libresoc.v:146199$8035_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -299014,11 +305230,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143727.7-143727.15" + attribute \src "libresoc.v:146158.7-146158.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -299035,7 +305251,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143762$7732 + cell $and $and$libresoc.v:146193$8029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299043,10 +305259,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143762$7732_Y + connect \Y $and$libresoc.v:146193$8029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143767$7737 + cell $and $and$libresoc.v:146198$8034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299054,34 +305270,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143767$7737_Y + connect \Y $and$libresoc.v:146198$8034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143764$7734 + cell $not $not$libresoc.v:146195$8031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143764$7734_Y + connect \Y $not$libresoc.v:146195$8031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143766$7736 + cell $not $not$libresoc.v:146197$8033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143766$7736_Y + connect \Y $not$libresoc.v:146197$8033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143769$7739 + cell $not $not$libresoc.v:146200$8036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143769$7739_Y + connect \Y $not$libresoc.v:146200$8036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143763$7733 + cell $or $or$libresoc.v:146194$8030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299089,10 +305305,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143763$7733_Y + connect \Y $or$libresoc.v:146194$8030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143765$7735 + cell $or $or$libresoc.v:146196$8032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299100,10 +305316,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143765$7735_Y + connect \Y $or$libresoc.v:146196$8032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143768$7738 + cell $or $or$libresoc.v:146199$8035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299111,39 +305327,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143768$7738_Y + connect \Y $or$libresoc.v:146199$8035_Y end - attribute \src "libresoc.v:143727.7-143727.20" - process $proc$libresoc.v:143727$7744 + attribute \src "libresoc.v:146158.7-146158.20" + process $proc$libresoc.v:146158$8041 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143749.7-143749.19" - process $proc$libresoc.v:143749$7745 + attribute \src "libresoc.v:146180.7-146180.19" + process $proc$libresoc.v:146180$8042 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143770.3-143771.27" - process $proc$libresoc.v:143770$7740 + attribute \src "libresoc.v:146201.3-146202.27" + process $proc$libresoc.v:146201$8037 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143772.3-143780.6" - process $proc$libresoc.v:143772$7741 + attribute \src "libresoc.v:146203.3-146211.6" + process $proc$libresoc.v:146203$8038 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7742 $1\q_int$next[0:0]$7743 - attribute \src "libresoc.v:143773.5-143773.29" + assign $0\q_int$next[0:0]$8039 $1\q_int$next[0:0]$8040 + attribute \src "libresoc.v:146204.5-146204.29" switch \initial - attribute \src "libresoc.v:143773.9-143773.17" + attribute \src "libresoc.v:146204.9-146204.17" case 1'1 case end @@ -299152,56 +305368,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7743 1'0 + assign $1\q_int$next[0:0]$8040 1'0 case - assign $1\q_int$next[0:0]$7743 \$5 + assign $1\q_int$next[0:0]$8040 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7742 + update \q_int$next $0\q_int$next[0:0]$8039 end - connect \$9 $and$libresoc.v:143762$7732_Y - connect \$11 $or$libresoc.v:143763$7733_Y - connect \$13 $not$libresoc.v:143764$7734_Y - connect \$15 $or$libresoc.v:143765$7735_Y - connect \$1 $not$libresoc.v:143766$7736_Y - connect \$3 $and$libresoc.v:143767$7737_Y - connect \$5 $or$libresoc.v:143768$7738_Y - connect \$7 $not$libresoc.v:143769$7739_Y + connect \$9 $and$libresoc.v:146193$8029_Y + connect \$11 $or$libresoc.v:146194$8030_Y + connect \$13 $not$libresoc.v:146195$8031_Y + connect \$15 $or$libresoc.v:146196$8032_Y + connect \$1 $not$libresoc.v:146197$8033_Y + connect \$3 $and$libresoc.v:146198$8034_Y + connect \$5 $or$libresoc.v:146199$8035_Y + connect \$7 $not$libresoc.v:146200$8036_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143788.1-143846.10" +attribute \src "libresoc.v:146219.1-146277.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" -module \opc_l$37 - attribute \src "libresoc.v:143789.7-143789.20" +module \opc_l$126 + attribute \src "libresoc.v:146220.7-146220.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143834.3-143842.6" - wire $0\q_int$next[0:0]$7756 - attribute \src "libresoc.v:143832.3-143833.27" + attribute \src "libresoc.v:146265.3-146273.6" + wire $0\q_int$next[0:0]$8053 + attribute \src "libresoc.v:146263.3-146264.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143834.3-143842.6" - wire $1\q_int$next[0:0]$7757 - attribute \src "libresoc.v:143811.7-143811.19" + attribute \src "libresoc.v:146265.3-146273.6" + wire $1\q_int$next[0:0]$8054 + attribute \src "libresoc.v:146242.7-146242.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143824.17-143824.96" - wire $and$libresoc.v:143824$7746_Y - attribute \src "libresoc.v:143829.17-143829.96" - wire $and$libresoc.v:143829$7751_Y - attribute \src "libresoc.v:143826.18-143826.93" - wire $not$libresoc.v:143826$7748_Y - attribute \src "libresoc.v:143828.17-143828.92" - wire $not$libresoc.v:143828$7750_Y - attribute \src "libresoc.v:143831.17-143831.92" - wire $not$libresoc.v:143831$7753_Y - attribute \src "libresoc.v:143825.18-143825.98" - wire $or$libresoc.v:143825$7747_Y - attribute \src "libresoc.v:143827.18-143827.99" - wire $or$libresoc.v:143827$7749_Y - attribute \src "libresoc.v:143830.17-143830.97" - wire $or$libresoc.v:143830$7752_Y + attribute \src "libresoc.v:146255.17-146255.96" + wire $and$libresoc.v:146255$8043_Y + attribute \src "libresoc.v:146260.17-146260.96" + wire $and$libresoc.v:146260$8048_Y + attribute \src "libresoc.v:146257.18-146257.93" + wire $not$libresoc.v:146257$8045_Y + attribute \src "libresoc.v:146259.17-146259.92" + wire $not$libresoc.v:146259$8047_Y + attribute \src "libresoc.v:146262.17-146262.92" + wire $not$libresoc.v:146262$8050_Y + attribute \src "libresoc.v:146256.18-146256.98" + wire $or$libresoc.v:146256$8044_Y + attribute \src "libresoc.v:146258.18-146258.99" + wire $or$libresoc.v:146258$8046_Y + attribute \src "libresoc.v:146261.17-146261.97" + wire $or$libresoc.v:146261$8049_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -299218,11 +305434,11 @@ module \opc_l$37 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143789.7-143789.15" + attribute \src "libresoc.v:146220.7-146220.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -299239,7 +305455,7 @@ module \opc_l$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143824$7746 + cell $and $and$libresoc.v:146255$8043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299247,10 +305463,10 @@ module \opc_l$37 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143824$7746_Y + connect \Y $and$libresoc.v:146255$8043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143829$7751 + cell $and $and$libresoc.v:146260$8048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299258,34 +305474,34 @@ module \opc_l$37 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143829$7751_Y + connect \Y $and$libresoc.v:146260$8048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143826$7748 + cell $not $not$libresoc.v:146257$8045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143826$7748_Y + connect \Y $not$libresoc.v:146257$8045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143828$7750 + cell $not $not$libresoc.v:146259$8047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143828$7750_Y + connect \Y $not$libresoc.v:146259$8047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143831$7753 + cell $not $not$libresoc.v:146262$8050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143831$7753_Y + connect \Y $not$libresoc.v:146262$8050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143825$7747 + cell $or $or$libresoc.v:146256$8044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299293,10 +305509,10 @@ module \opc_l$37 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143825$7747_Y + connect \Y $or$libresoc.v:146256$8044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143827$7749 + cell $or $or$libresoc.v:146258$8046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299304,10 +305520,10 @@ module \opc_l$37 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143827$7749_Y + connect \Y $or$libresoc.v:146258$8046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143830$7752 + cell $or $or$libresoc.v:146261$8049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299315,39 +305531,39 @@ module \opc_l$37 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143830$7752_Y + connect \Y $or$libresoc.v:146261$8049_Y end - attribute \src "libresoc.v:143789.7-143789.20" - process $proc$libresoc.v:143789$7758 + attribute \src "libresoc.v:146220.7-146220.20" + process $proc$libresoc.v:146220$8055 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143811.7-143811.19" - process $proc$libresoc.v:143811$7759 + attribute \src "libresoc.v:146242.7-146242.19" + process $proc$libresoc.v:146242$8056 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143832.3-143833.27" - process $proc$libresoc.v:143832$7754 + attribute \src "libresoc.v:146263.3-146264.27" + process $proc$libresoc.v:146263$8051 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143834.3-143842.6" - process $proc$libresoc.v:143834$7755 + attribute \src "libresoc.v:146265.3-146273.6" + process $proc$libresoc.v:146265$8052 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7756 $1\q_int$next[0:0]$7757 - attribute \src "libresoc.v:143835.5-143835.29" + assign $0\q_int$next[0:0]$8053 $1\q_int$next[0:0]$8054 + attribute \src "libresoc.v:146266.5-146266.29" switch \initial - attribute \src "libresoc.v:143835.9-143835.17" + attribute \src "libresoc.v:146266.9-146266.17" case 1'1 case end @@ -299356,56 +305572,56 @@ module \opc_l$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7757 1'0 + assign $1\q_int$next[0:0]$8054 1'0 case - assign $1\q_int$next[0:0]$7757 \$5 + assign $1\q_int$next[0:0]$8054 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7756 + update \q_int$next $0\q_int$next[0:0]$8053 end - connect \$9 $and$libresoc.v:143824$7746_Y - connect \$11 $or$libresoc.v:143825$7747_Y - connect \$13 $not$libresoc.v:143826$7748_Y - connect \$15 $or$libresoc.v:143827$7749_Y - connect \$1 $not$libresoc.v:143828$7750_Y - connect \$3 $and$libresoc.v:143829$7751_Y - connect \$5 $or$libresoc.v:143830$7752_Y - connect \$7 $not$libresoc.v:143831$7753_Y + connect \$9 $and$libresoc.v:146255$8043_Y + connect \$11 $or$libresoc.v:146256$8044_Y + connect \$13 $not$libresoc.v:146257$8045_Y + connect \$15 $or$libresoc.v:146258$8046_Y + connect \$1 $not$libresoc.v:146259$8047_Y + connect \$3 $and$libresoc.v:146260$8048_Y + connect \$5 $or$libresoc.v:146261$8049_Y + connect \$7 $not$libresoc.v:146262$8050_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143850.1-143908.10" +attribute \src "libresoc.v:146281.1-146339.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" -module \opc_l$53 - attribute \src "libresoc.v:143851.7-143851.20" +module \opc_l$24 + attribute \src "libresoc.v:146282.7-146282.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143896.3-143904.6" - wire $0\q_int$next[0:0]$7770 - attribute \src "libresoc.v:143894.3-143895.27" + attribute \src "libresoc.v:146327.3-146335.6" + wire $0\q_int$next[0:0]$8067 + attribute \src "libresoc.v:146325.3-146326.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143896.3-143904.6" - wire $1\q_int$next[0:0]$7771 - attribute \src "libresoc.v:143873.7-143873.19" + attribute \src "libresoc.v:146327.3-146335.6" + wire $1\q_int$next[0:0]$8068 + attribute \src "libresoc.v:146304.7-146304.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143886.17-143886.96" - wire $and$libresoc.v:143886$7760_Y - attribute \src "libresoc.v:143891.17-143891.96" - wire $and$libresoc.v:143891$7765_Y - attribute \src "libresoc.v:143888.18-143888.93" - wire $not$libresoc.v:143888$7762_Y - attribute \src "libresoc.v:143890.17-143890.92" - wire $not$libresoc.v:143890$7764_Y - attribute \src "libresoc.v:143893.17-143893.92" - wire $not$libresoc.v:143893$7767_Y - attribute \src "libresoc.v:143887.18-143887.98" - wire $or$libresoc.v:143887$7761_Y - attribute \src "libresoc.v:143889.18-143889.99" - wire $or$libresoc.v:143889$7763_Y - attribute \src "libresoc.v:143892.17-143892.97" - wire $or$libresoc.v:143892$7766_Y + attribute \src "libresoc.v:146317.17-146317.96" + wire $and$libresoc.v:146317$8057_Y + attribute \src "libresoc.v:146322.17-146322.96" + wire $and$libresoc.v:146322$8062_Y + attribute \src "libresoc.v:146319.18-146319.93" + wire $not$libresoc.v:146319$8059_Y + attribute \src "libresoc.v:146321.17-146321.92" + wire $not$libresoc.v:146321$8061_Y + attribute \src "libresoc.v:146324.17-146324.92" + wire $not$libresoc.v:146324$8064_Y + attribute \src "libresoc.v:146318.18-146318.98" + wire $or$libresoc.v:146318$8058_Y + attribute \src "libresoc.v:146320.18-146320.99" + wire $or$libresoc.v:146320$8060_Y + attribute \src "libresoc.v:146323.17-146323.97" + wire $or$libresoc.v:146323$8063_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -299422,11 +305638,11 @@ module \opc_l$53 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143851.7-143851.15" + attribute \src "libresoc.v:146282.7-146282.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -299443,7 +305659,7 @@ module \opc_l$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143886$7760 + cell $and $and$libresoc.v:146317$8057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299451,10 +305667,10 @@ module \opc_l$53 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143886$7760_Y + connect \Y $and$libresoc.v:146317$8057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143891$7765 + cell $and $and$libresoc.v:146322$8062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299462,34 +305678,34 @@ module \opc_l$53 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143891$7765_Y + connect \Y $and$libresoc.v:146322$8062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143888$7762 + cell $not $not$libresoc.v:146319$8059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143888$7762_Y + connect \Y $not$libresoc.v:146319$8059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143890$7764 + cell $not $not$libresoc.v:146321$8061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143890$7764_Y + connect \Y $not$libresoc.v:146321$8061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143893$7767 + cell $not $not$libresoc.v:146324$8064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143893$7767_Y + connect \Y $not$libresoc.v:146324$8064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143887$7761 + cell $or $or$libresoc.v:146318$8058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299497,10 +305713,10 @@ module \opc_l$53 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143887$7761_Y + connect \Y $or$libresoc.v:146318$8058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143889$7763 + cell $or $or$libresoc.v:146320$8060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299508,10 +305724,10 @@ module \opc_l$53 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143889$7763_Y + connect \Y $or$libresoc.v:146320$8060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143892$7766 + cell $or $or$libresoc.v:146323$8063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299519,39 +305735,39 @@ module \opc_l$53 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143892$7766_Y + connect \Y $or$libresoc.v:146323$8063_Y end - attribute \src "libresoc.v:143851.7-143851.20" - process $proc$libresoc.v:143851$7772 + attribute \src "libresoc.v:146282.7-146282.20" + process $proc$libresoc.v:146282$8069 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143873.7-143873.19" - process $proc$libresoc.v:143873$7773 + attribute \src "libresoc.v:146304.7-146304.19" + process $proc$libresoc.v:146304$8070 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143894.3-143895.27" - process $proc$libresoc.v:143894$7768 + attribute \src "libresoc.v:146325.3-146326.27" + process $proc$libresoc.v:146325$8065 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143896.3-143904.6" - process $proc$libresoc.v:143896$7769 + attribute \src "libresoc.v:146327.3-146335.6" + process $proc$libresoc.v:146327$8066 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7770 $1\q_int$next[0:0]$7771 - attribute \src "libresoc.v:143897.5-143897.29" + assign $0\q_int$next[0:0]$8067 $1\q_int$next[0:0]$8068 + attribute \src "libresoc.v:146328.5-146328.29" switch \initial - attribute \src "libresoc.v:143897.9-143897.17" + attribute \src "libresoc.v:146328.9-146328.17" case 1'1 case end @@ -299560,56 +305776,56 @@ module \opc_l$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7771 1'0 + assign $1\q_int$next[0:0]$8068 1'0 case - assign $1\q_int$next[0:0]$7771 \$5 + assign $1\q_int$next[0:0]$8068 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7770 + update \q_int$next $0\q_int$next[0:0]$8067 end - connect \$9 $and$libresoc.v:143886$7760_Y - connect \$11 $or$libresoc.v:143887$7761_Y - connect \$13 $not$libresoc.v:143888$7762_Y - connect \$15 $or$libresoc.v:143889$7763_Y - connect \$1 $not$libresoc.v:143890$7764_Y - connect \$3 $and$libresoc.v:143891$7765_Y - connect \$5 $or$libresoc.v:143892$7766_Y - connect \$7 $not$libresoc.v:143893$7767_Y + connect \$9 $and$libresoc.v:146317$8057_Y + connect \$11 $or$libresoc.v:146318$8058_Y + connect \$13 $not$libresoc.v:146319$8059_Y + connect \$15 $or$libresoc.v:146320$8060_Y + connect \$1 $not$libresoc.v:146321$8061_Y + connect \$3 $and$libresoc.v:146322$8062_Y + connect \$5 $or$libresoc.v:146323$8063_Y + connect \$7 $not$libresoc.v:146324$8064_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143912.1-143970.10" +attribute \src "libresoc.v:146343.1-146401.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" -module \opc_l$65 - attribute \src "libresoc.v:143913.7-143913.20" +module \opc_l$40 + attribute \src "libresoc.v:146344.7-146344.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143958.3-143966.6" - wire $0\q_int$next[0:0]$7784 - attribute \src "libresoc.v:143956.3-143957.27" + attribute \src "libresoc.v:146389.3-146397.6" + wire $0\q_int$next[0:0]$8081 + attribute \src "libresoc.v:146387.3-146388.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:143958.3-143966.6" - wire $1\q_int$next[0:0]$7785 - attribute \src "libresoc.v:143935.7-143935.19" + attribute \src "libresoc.v:146389.3-146397.6" + wire $1\q_int$next[0:0]$8082 + attribute \src "libresoc.v:146366.7-146366.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:143948.17-143948.96" - wire $and$libresoc.v:143948$7774_Y - attribute \src "libresoc.v:143953.17-143953.96" - wire $and$libresoc.v:143953$7779_Y - attribute \src "libresoc.v:143950.18-143950.93" - wire $not$libresoc.v:143950$7776_Y - attribute \src "libresoc.v:143952.17-143952.92" - wire $not$libresoc.v:143952$7778_Y - attribute \src "libresoc.v:143955.17-143955.92" - wire $not$libresoc.v:143955$7781_Y - attribute \src "libresoc.v:143949.18-143949.98" - wire $or$libresoc.v:143949$7775_Y - attribute \src "libresoc.v:143951.18-143951.99" - wire $or$libresoc.v:143951$7777_Y - attribute \src "libresoc.v:143954.17-143954.97" - wire $or$libresoc.v:143954$7780_Y + attribute \src "libresoc.v:146379.17-146379.96" + wire $and$libresoc.v:146379$8071_Y + attribute \src "libresoc.v:146384.17-146384.96" + wire $and$libresoc.v:146384$8076_Y + attribute \src "libresoc.v:146381.18-146381.93" + wire $not$libresoc.v:146381$8073_Y + attribute \src "libresoc.v:146383.17-146383.92" + wire $not$libresoc.v:146383$8075_Y + attribute \src "libresoc.v:146386.17-146386.92" + wire $not$libresoc.v:146386$8078_Y + attribute \src "libresoc.v:146380.18-146380.98" + wire $or$libresoc.v:146380$8072_Y + attribute \src "libresoc.v:146382.18-146382.99" + wire $or$libresoc.v:146382$8074_Y + attribute \src "libresoc.v:146385.17-146385.97" + wire $or$libresoc.v:146385$8077_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -299626,11 +305842,11 @@ module \opc_l$65 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143913.7-143913.15" + attribute \src "libresoc.v:146344.7-146344.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -299647,7 +305863,7 @@ module \opc_l$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:143948$7774 + cell $and $and$libresoc.v:146379$8071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299655,10 +305871,10 @@ module \opc_l$65 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:143948$7774_Y + connect \Y $and$libresoc.v:146379$8071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:143953$7779 + cell $and $and$libresoc.v:146384$8076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299666,34 +305882,34 @@ module \opc_l$65 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:143953$7779_Y + connect \Y $and$libresoc.v:146384$8076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:143950$7776 + cell $not $not$libresoc.v:146381$8073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:143950$7776_Y + connect \Y $not$libresoc.v:146381$8073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:143952$7778 + cell $not $not$libresoc.v:146383$8075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143952$7778_Y + connect \Y $not$libresoc.v:146383$8075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:143955$7781 + cell $not $not$libresoc.v:146386$8078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:143955$7781_Y + connect \Y $not$libresoc.v:146386$8078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:143949$7775 + cell $or $or$libresoc.v:146380$8072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299701,10 +305917,10 @@ module \opc_l$65 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:143949$7775_Y + connect \Y $or$libresoc.v:146380$8072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:143951$7777 + cell $or $or$libresoc.v:146382$8074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299712,10 +305928,10 @@ module \opc_l$65 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:143951$7777_Y + connect \Y $or$libresoc.v:146382$8074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:143954$7780 + cell $or $or$libresoc.v:146385$8077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299723,39 +305939,39 @@ module \opc_l$65 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:143954$7780_Y + connect \Y $or$libresoc.v:146385$8077_Y end - attribute \src "libresoc.v:143913.7-143913.20" - process $proc$libresoc.v:143913$7786 + attribute \src "libresoc.v:146344.7-146344.20" + process $proc$libresoc.v:146344$8083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143935.7-143935.19" - process $proc$libresoc.v:143935$7787 + attribute \src "libresoc.v:146366.7-146366.19" + process $proc$libresoc.v:146366$8084 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:143956.3-143957.27" - process $proc$libresoc.v:143956$7782 + attribute \src "libresoc.v:146387.3-146388.27" + process $proc$libresoc.v:146387$8079 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:143958.3-143966.6" - process $proc$libresoc.v:143958$7783 + attribute \src "libresoc.v:146389.3-146397.6" + process $proc$libresoc.v:146389$8080 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7784 $1\q_int$next[0:0]$7785 - attribute \src "libresoc.v:143959.5-143959.29" + assign $0\q_int$next[0:0]$8081 $1\q_int$next[0:0]$8082 + attribute \src "libresoc.v:146390.5-146390.29" switch \initial - attribute \src "libresoc.v:143959.9-143959.17" + attribute \src "libresoc.v:146390.9-146390.17" case 1'1 case end @@ -299764,56 +305980,56 @@ module \opc_l$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7785 1'0 + assign $1\q_int$next[0:0]$8082 1'0 case - assign $1\q_int$next[0:0]$7785 \$5 + assign $1\q_int$next[0:0]$8082 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7784 + update \q_int$next $0\q_int$next[0:0]$8081 end - connect \$9 $and$libresoc.v:143948$7774_Y - connect \$11 $or$libresoc.v:143949$7775_Y - connect \$13 $not$libresoc.v:143950$7776_Y - connect \$15 $or$libresoc.v:143951$7777_Y - connect \$1 $not$libresoc.v:143952$7778_Y - connect \$3 $and$libresoc.v:143953$7779_Y - connect \$5 $or$libresoc.v:143954$7780_Y - connect \$7 $not$libresoc.v:143955$7781_Y + connect \$9 $and$libresoc.v:146379$8071_Y + connect \$11 $or$libresoc.v:146380$8072_Y + connect \$13 $not$libresoc.v:146381$8073_Y + connect \$15 $or$libresoc.v:146382$8074_Y + connect \$1 $not$libresoc.v:146383$8075_Y + connect \$3 $and$libresoc.v:146384$8076_Y + connect \$5 $or$libresoc.v:146385$8077_Y + connect \$7 $not$libresoc.v:146386$8078_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:143974.1-144032.10" +attribute \src "libresoc.v:146405.1-146463.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" -module \opc_l$82 - attribute \src "libresoc.v:143975.7-143975.20" +module \opc_l$56 + attribute \src "libresoc.v:146406.7-146406.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144020.3-144028.6" - wire $0\q_int$next[0:0]$7798 - attribute \src "libresoc.v:144018.3-144019.27" + attribute \src "libresoc.v:146451.3-146459.6" + wire $0\q_int$next[0:0]$8095 + attribute \src "libresoc.v:146449.3-146450.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:144020.3-144028.6" - wire $1\q_int$next[0:0]$7799 - attribute \src "libresoc.v:143997.7-143997.19" + attribute \src "libresoc.v:146451.3-146459.6" + wire $1\q_int$next[0:0]$8096 + attribute \src "libresoc.v:146428.7-146428.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:144010.17-144010.96" - wire $and$libresoc.v:144010$7788_Y - attribute \src "libresoc.v:144015.17-144015.96" - wire $and$libresoc.v:144015$7793_Y - attribute \src "libresoc.v:144012.18-144012.93" - wire $not$libresoc.v:144012$7790_Y - attribute \src "libresoc.v:144014.17-144014.92" - wire $not$libresoc.v:144014$7792_Y - attribute \src "libresoc.v:144017.17-144017.92" - wire $not$libresoc.v:144017$7795_Y - attribute \src "libresoc.v:144011.18-144011.98" - wire $or$libresoc.v:144011$7789_Y - attribute \src "libresoc.v:144013.18-144013.99" - wire $or$libresoc.v:144013$7791_Y - attribute \src "libresoc.v:144016.17-144016.97" - wire $or$libresoc.v:144016$7794_Y + attribute \src "libresoc.v:146441.17-146441.96" + wire $and$libresoc.v:146441$8085_Y + attribute \src "libresoc.v:146446.17-146446.96" + wire $and$libresoc.v:146446$8090_Y + attribute \src "libresoc.v:146443.18-146443.93" + wire $not$libresoc.v:146443$8087_Y + attribute \src "libresoc.v:146445.17-146445.92" + wire $not$libresoc.v:146445$8089_Y + attribute \src "libresoc.v:146448.17-146448.92" + wire $not$libresoc.v:146448$8092_Y + attribute \src "libresoc.v:146442.18-146442.98" + wire $or$libresoc.v:146442$8086_Y + attribute \src "libresoc.v:146444.18-146444.99" + wire $or$libresoc.v:146444$8088_Y + attribute \src "libresoc.v:146447.17-146447.97" + wire $or$libresoc.v:146447$8091_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -299830,11 +306046,11 @@ module \opc_l$82 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:143975.7-143975.15" + attribute \src "libresoc.v:146406.7-146406.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -299851,7 +306067,7 @@ module \opc_l$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:144010$7788 + cell $and $and$libresoc.v:146441$8085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299859,10 +306075,10 @@ module \opc_l$82 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:144010$7788_Y + connect \Y $and$libresoc.v:146441$8085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:144015$7793 + cell $and $and$libresoc.v:146446$8090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299870,34 +306086,34 @@ module \opc_l$82 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:144015$7793_Y + connect \Y $and$libresoc.v:146446$8090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:144012$7790 + cell $not $not$libresoc.v:146443$8087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:144012$7790_Y + connect \Y $not$libresoc.v:146443$8087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:144014$7792 + cell $not $not$libresoc.v:146445$8089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:144014$7792_Y + connect \Y $not$libresoc.v:146445$8089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:144017$7795 + cell $not $not$libresoc.v:146448$8092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:144017$7795_Y + connect \Y $not$libresoc.v:146448$8092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:144011$7789 + cell $or $or$libresoc.v:146442$8086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299905,10 +306121,10 @@ module \opc_l$82 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:144011$7789_Y + connect \Y $or$libresoc.v:146442$8086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:144013$7791 + cell $or $or$libresoc.v:146444$8088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299916,10 +306132,10 @@ module \opc_l$82 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:144013$7791_Y + connect \Y $or$libresoc.v:146444$8088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:144016$7794 + cell $or $or$libresoc.v:146447$8091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -299927,39 +306143,39 @@ module \opc_l$82 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:144016$7794_Y + connect \Y $or$libresoc.v:146447$8091_Y end - attribute \src "libresoc.v:143975.7-143975.20" - process $proc$libresoc.v:143975$7800 + attribute \src "libresoc.v:146406.7-146406.20" + process $proc$libresoc.v:146406$8097 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143997.7-143997.19" - process $proc$libresoc.v:143997$7801 + attribute \src "libresoc.v:146428.7-146428.19" + process $proc$libresoc.v:146428$8098 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:144018.3-144019.27" - process $proc$libresoc.v:144018$7796 + attribute \src "libresoc.v:146449.3-146450.27" + process $proc$libresoc.v:146449$8093 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:144020.3-144028.6" - process $proc$libresoc.v:144020$7797 + attribute \src "libresoc.v:146451.3-146459.6" + process $proc$libresoc.v:146451$8094 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7798 $1\q_int$next[0:0]$7799 - attribute \src "libresoc.v:144021.5-144021.29" + assign $0\q_int$next[0:0]$8095 $1\q_int$next[0:0]$8096 + attribute \src "libresoc.v:146452.5-146452.29" switch \initial - attribute \src "libresoc.v:144021.9-144021.17" + attribute \src "libresoc.v:146452.9-146452.17" case 1'1 case end @@ -299968,56 +306184,56 @@ module \opc_l$82 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7799 1'0 + assign $1\q_int$next[0:0]$8096 1'0 case - assign $1\q_int$next[0:0]$7799 \$5 + assign $1\q_int$next[0:0]$8096 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7798 + update \q_int$next $0\q_int$next[0:0]$8095 end - connect \$9 $and$libresoc.v:144010$7788_Y - connect \$11 $or$libresoc.v:144011$7789_Y - connect \$13 $not$libresoc.v:144012$7790_Y - connect \$15 $or$libresoc.v:144013$7791_Y - connect \$1 $not$libresoc.v:144014$7792_Y - connect \$3 $and$libresoc.v:144015$7793_Y - connect \$5 $or$libresoc.v:144016$7794_Y - connect \$7 $not$libresoc.v:144017$7795_Y + connect \$9 $and$libresoc.v:146441$8085_Y + connect \$11 $or$libresoc.v:146442$8086_Y + connect \$13 $not$libresoc.v:146443$8087_Y + connect \$15 $or$libresoc.v:146444$8088_Y + connect \$1 $not$libresoc.v:146445$8089_Y + connect \$3 $and$libresoc.v:146446$8090_Y + connect \$5 $or$libresoc.v:146447$8091_Y + connect \$7 $not$libresoc.v:146448$8092_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:144036.1-144094.10" +attribute \src "libresoc.v:146467.1-146525.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" -module \opc_l$99 - attribute \src "libresoc.v:144037.7-144037.20" +module \opc_l$68 + attribute \src "libresoc.v:146468.7-146468.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144082.3-144090.6" - wire $0\q_int$next[0:0]$7812 - attribute \src "libresoc.v:144080.3-144081.27" + attribute \src "libresoc.v:146513.3-146521.6" + wire $0\q_int$next[0:0]$8109 + attribute \src "libresoc.v:146511.3-146512.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:144082.3-144090.6" - wire $1\q_int$next[0:0]$7813 - attribute \src "libresoc.v:144059.7-144059.19" + attribute \src "libresoc.v:146513.3-146521.6" + wire $1\q_int$next[0:0]$8110 + attribute \src "libresoc.v:146490.7-146490.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:144072.17-144072.96" - wire $and$libresoc.v:144072$7802_Y - attribute \src "libresoc.v:144077.17-144077.96" - wire $and$libresoc.v:144077$7807_Y - attribute \src "libresoc.v:144074.18-144074.93" - wire $not$libresoc.v:144074$7804_Y - attribute \src "libresoc.v:144076.17-144076.92" - wire $not$libresoc.v:144076$7806_Y - attribute \src "libresoc.v:144079.17-144079.92" - wire $not$libresoc.v:144079$7809_Y - attribute \src "libresoc.v:144073.18-144073.98" - wire $or$libresoc.v:144073$7803_Y - attribute \src "libresoc.v:144075.18-144075.99" - wire $or$libresoc.v:144075$7805_Y - attribute \src "libresoc.v:144078.17-144078.97" - wire $or$libresoc.v:144078$7808_Y + attribute \src "libresoc.v:146503.17-146503.96" + wire $and$libresoc.v:146503$8099_Y + attribute \src "libresoc.v:146508.17-146508.96" + wire $and$libresoc.v:146508$8104_Y + attribute \src "libresoc.v:146505.18-146505.93" + wire $not$libresoc.v:146505$8101_Y + attribute \src "libresoc.v:146507.17-146507.92" + wire $not$libresoc.v:146507$8103_Y + attribute \src "libresoc.v:146510.17-146510.92" + wire $not$libresoc.v:146510$8106_Y + attribute \src "libresoc.v:146504.18-146504.98" + wire $or$libresoc.v:146504$8100_Y + attribute \src "libresoc.v:146506.18-146506.99" + wire $or$libresoc.v:146506$8102_Y + attribute \src "libresoc.v:146509.17-146509.97" + wire $or$libresoc.v:146509$8105_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -300034,11 +306250,11 @@ module \opc_l$99 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:144037.7-144037.15" + attribute \src "libresoc.v:146468.7-146468.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -300055,7 +306271,7 @@ module \opc_l$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:144072$7802 + cell $and $and$libresoc.v:146503$8099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300063,10 +306279,10 @@ module \opc_l$99 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:144072$7802_Y + connect \Y $and$libresoc.v:146503$8099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:144077$7807 + cell $and $and$libresoc.v:146508$8104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300074,34 +306290,34 @@ module \opc_l$99 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:144077$7807_Y + connect \Y $and$libresoc.v:146508$8104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:144074$7804 + cell $not $not$libresoc.v:146505$8101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:144074$7804_Y + connect \Y $not$libresoc.v:146505$8101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:144076$7806 + cell $not $not$libresoc.v:146507$8103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:144076$7806_Y + connect \Y $not$libresoc.v:146507$8103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:144079$7809 + cell $not $not$libresoc.v:146510$8106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:144079$7809_Y + connect \Y $not$libresoc.v:146510$8106_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:144073$7803 + cell $or $or$libresoc.v:146504$8100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300109,10 +306325,10 @@ module \opc_l$99 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:144073$7803_Y + connect \Y $or$libresoc.v:146504$8100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:144075$7805 + cell $or $or$libresoc.v:146506$8102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300120,10 +306336,10 @@ module \opc_l$99 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:144075$7805_Y + connect \Y $or$libresoc.v:146506$8102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:144078$7808 + cell $or $or$libresoc.v:146509$8105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300131,39 +306347,39 @@ module \opc_l$99 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:144078$7808_Y + connect \Y $or$libresoc.v:146509$8105_Y end - attribute \src "libresoc.v:144037.7-144037.20" - process $proc$libresoc.v:144037$7814 + attribute \src "libresoc.v:146468.7-146468.20" + process $proc$libresoc.v:146468$8111 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144059.7-144059.19" - process $proc$libresoc.v:144059$7815 + attribute \src "libresoc.v:146490.7-146490.19" + process $proc$libresoc.v:146490$8112 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:144080.3-144081.27" - process $proc$libresoc.v:144080$7810 + attribute \src "libresoc.v:146511.3-146512.27" + process $proc$libresoc.v:146511$8107 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:144082.3-144090.6" - process $proc$libresoc.v:144082$7811 + attribute \src "libresoc.v:146513.3-146521.6" + process $proc$libresoc.v:146513$8108 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7812 $1\q_int$next[0:0]$7813 - attribute \src "libresoc.v:144083.5-144083.29" + assign $0\q_int$next[0:0]$8109 $1\q_int$next[0:0]$8110 + attribute \src "libresoc.v:146514.5-146514.29" switch \initial - attribute \src "libresoc.v:144083.9-144083.17" + attribute \src "libresoc.v:146514.9-146514.17" case 1'1 case end @@ -300172,97 +306388,301 @@ module \opc_l$99 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7813 1'0 + assign $1\q_int$next[0:0]$8110 1'0 case - assign $1\q_int$next[0:0]$7813 \$5 + assign $1\q_int$next[0:0]$8110 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7812 + update \q_int$next $0\q_int$next[0:0]$8109 end - connect \$9 $and$libresoc.v:144072$7802_Y - connect \$11 $or$libresoc.v:144073$7803_Y - connect \$13 $not$libresoc.v:144074$7804_Y - connect \$15 $or$libresoc.v:144075$7805_Y - connect \$1 $not$libresoc.v:144076$7806_Y - connect \$3 $and$libresoc.v:144077$7807_Y - connect \$5 $or$libresoc.v:144078$7808_Y - connect \$7 $not$libresoc.v:144079$7809_Y + connect \$9 $and$libresoc.v:146503$8099_Y + connect \$11 $or$libresoc.v:146504$8100_Y + connect \$13 $not$libresoc.v:146505$8101_Y + connect \$15 $or$libresoc.v:146506$8102_Y + connect \$1 $not$libresoc.v:146507$8103_Y + connect \$3 $and$libresoc.v:146508$8104_Y + connect \$5 $or$libresoc.v:146509$8105_Y + connect \$7 $not$libresoc.v:146510$8106_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:144098.1-144550.10" +attribute \src "libresoc.v:146529.1-146587.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" +attribute \generator "nMigen" +module \opc_l$85 + attribute \src "libresoc.v:146530.7-146530.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146575.3-146583.6" + wire $0\q_int$next[0:0]$8123 + attribute \src "libresoc.v:146573.3-146574.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:146575.3-146583.6" + wire $1\q_int$next[0:0]$8124 + attribute \src "libresoc.v:146552.7-146552.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:146565.17-146565.96" + wire $and$libresoc.v:146565$8113_Y + attribute \src "libresoc.v:146570.17-146570.96" + wire $and$libresoc.v:146570$8118_Y + attribute \src "libresoc.v:146567.18-146567.93" + wire $not$libresoc.v:146567$8115_Y + attribute \src "libresoc.v:146569.17-146569.92" + wire $not$libresoc.v:146569$8117_Y + attribute \src "libresoc.v:146572.17-146572.92" + wire $not$libresoc.v:146572$8120_Y + attribute \src "libresoc.v:146566.18-146566.98" + wire $or$libresoc.v:146566$8114_Y + attribute \src "libresoc.v:146568.18-146568.99" + wire $or$libresoc.v:146568$8116_Y + attribute \src "libresoc.v:146571.17-146571.97" + wire $or$libresoc.v:146571$8119_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "libresoc.v:146530.7-146530.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:146565$8113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:146565$8113_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:146570$8118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:146570$8118_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:146567$8115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:146567$8115_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:146569$8117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146569$8117_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:146572$8120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:146572$8120_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:146566$8114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:146566$8114_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:146568$8116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:146568$8116_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:146571$8119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:146571$8119_Y + end + attribute \src "libresoc.v:146530.7-146530.20" + process $proc$libresoc.v:146530$8125 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146552.7-146552.19" + process $proc$libresoc.v:146552$8126 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:146573.3-146574.27" + process $proc$libresoc.v:146573$8121 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:146575.3-146583.6" + process $proc$libresoc.v:146575$8122 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8123 $1\q_int$next[0:0]$8124 + attribute \src "libresoc.v:146576.5-146576.29" + switch \initial + attribute \src "libresoc.v:146576.9-146576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8124 1'0 + case + assign $1\q_int$next[0:0]$8124 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8123 + end + connect \$9 $and$libresoc.v:146565$8113_Y + connect \$11 $or$libresoc.v:146566$8114_Y + connect \$13 $not$libresoc.v:146567$8115_Y + connect \$15 $or$libresoc.v:146568$8116_Y + connect \$1 $not$libresoc.v:146569$8117_Y + connect \$3 $and$libresoc.v:146570$8118_Y + connect \$5 $or$libresoc.v:146571$8119_Y + connect \$7 $not$libresoc.v:146572$8120_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:146591.1-147043.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:144469.3-144480.6" + attribute \src "libresoc.v:146962.3-146973.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:144099.7-144099.20" + attribute \src "libresoc.v:146592.7-146592.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144481.3-144492.6" - wire width 65 $0\o$28[64:0]$7834 - attribute \src "libresoc.v:144457.3-144468.6" + attribute \src "libresoc.v:146974.3-146985.6" + wire width 65 $0\o$28[64:0]$8145 + attribute \src "libresoc.v:146950.3-146961.6" wire $0\so[0:0] - attribute \src "libresoc.v:144513.3-144522.6" - wire width 2 $0\xer_ov$24[1:0]$7841 - attribute \src "libresoc.v:144523.3-144532.6" + attribute \src "libresoc.v:147006.3-147015.6" + wire width 2 $0\xer_ov$24[1:0]$8152 + attribute \src "libresoc.v:147016.3-147025.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:144493.3-144502.6" - wire $0\xer_so$25[0:0]$7837 - attribute \src "libresoc.v:144503.3-144512.6" + attribute \src "libresoc.v:146986.3-146995.6" + wire $0\xer_so$25[0:0]$8148 + attribute \src "libresoc.v:146996.3-147005.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:144469.3-144480.6" + attribute \src "libresoc.v:146962.3-146973.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:144481.3-144492.6" - wire width 65 $1\o$28[64:0]$7835 - attribute \src "libresoc.v:144457.3-144468.6" + attribute \src "libresoc.v:146974.3-146985.6" + wire width 65 $1\o$28[64:0]$8146 + attribute \src "libresoc.v:146950.3-146961.6" wire $1\so[0:0] - attribute \src "libresoc.v:144513.3-144522.6" - wire width 2 $1\xer_ov$24[1:0]$7842 - attribute \src "libresoc.v:144523.3-144532.6" + attribute \src "libresoc.v:147006.3-147015.6" + wire width 2 $1\xer_ov$24[1:0]$8153 + attribute \src "libresoc.v:147016.3-147025.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:144493.3-144502.6" - wire $1\xer_so$25[0:0]$7838 - attribute \src "libresoc.v:144503.3-144512.6" + attribute \src "libresoc.v:146986.3-146995.6" + wire $1\xer_so$25[0:0]$8149 + attribute \src "libresoc.v:146996.3-147005.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:144444.18-144444.128" - wire $and$libresoc.v:144444$7816_Y - attribute \src "libresoc.v:144452.18-144452.112" - wire $and$libresoc.v:144452$7826_Y - attribute \src "libresoc.v:144455.18-144455.125" - wire $and$libresoc.v:144455$7829_Y - attribute \src "libresoc.v:144448.18-144448.123" - wire $eq$libresoc.v:144448$7822_Y - attribute \src "libresoc.v:144449.18-144449.123" - wire $eq$libresoc.v:144449$7823_Y - attribute \src "libresoc.v:144446.18-144446.103" - wire width 65 $extend$libresoc.v:144446$7818_Y - attribute \src "libresoc.v:144447.18-144447.101" - wire width 65 $extend$libresoc.v:144447$7820_Y - attribute \src "libresoc.v:144445.18-144445.100" - wire width 64 $not$libresoc.v:144445$7817_Y - attribute \src "libresoc.v:144451.18-144451.107" - wire $not$libresoc.v:144451$7825_Y - attribute \src "libresoc.v:144454.18-144454.107" - wire $not$libresoc.v:144454$7828_Y - attribute \src "libresoc.v:144453.18-144453.115" - wire $or$libresoc.v:144453$7827_Y - attribute \src "libresoc.v:144456.18-144456.112" - wire $or$libresoc.v:144456$7830_Y - attribute \src "libresoc.v:144446.18-144446.103" - wire width 65 $pos$libresoc.v:144446$7819_Y - attribute \src "libresoc.v:144447.18-144447.101" - wire width 65 $pos$libresoc.v:144447$7821_Y - attribute \src "libresoc.v:144450.18-144450.105" - wire $reduce_or$libresoc.v:144450$7824_Y + attribute \src "libresoc.v:146937.18-146937.128" + wire $and$libresoc.v:146937$8127_Y + attribute \src "libresoc.v:146945.18-146945.112" + wire $and$libresoc.v:146945$8137_Y + attribute \src "libresoc.v:146948.18-146948.125" + wire $and$libresoc.v:146948$8140_Y + attribute \src "libresoc.v:146941.18-146941.123" + wire $eq$libresoc.v:146941$8133_Y + attribute \src "libresoc.v:146942.18-146942.123" + wire $eq$libresoc.v:146942$8134_Y + attribute \src "libresoc.v:146939.18-146939.103" + wire width 65 $extend$libresoc.v:146939$8129_Y + attribute \src "libresoc.v:146940.18-146940.101" + wire width 65 $extend$libresoc.v:146940$8131_Y + attribute \src "libresoc.v:146938.18-146938.100" + wire width 64 $not$libresoc.v:146938$8128_Y + attribute \src "libresoc.v:146944.18-146944.107" + wire $not$libresoc.v:146944$8136_Y + attribute \src "libresoc.v:146947.18-146947.107" + wire $not$libresoc.v:146947$8139_Y + attribute \src "libresoc.v:146946.18-146946.115" + wire $or$libresoc.v:146946$8138_Y + attribute \src "libresoc.v:146949.18-146949.112" + wire $or$libresoc.v:146949$8141_Y + attribute \src "libresoc.v:146939.18-146939.103" + wire width 65 $pos$libresoc.v:146939$8130_Y + attribute \src "libresoc.v:146940.18-146940.101" + wire width 65 $pos$libresoc.v:146940$8132_Y + attribute \src "libresoc.v:146943.18-146943.105" + wire $reduce_or$libresoc.v:146943$8135_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$35 @@ -300538,13 +306958,13 @@ module \output wire output 35 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:144099.7-144099.15" + attribute \src "libresoc.v:146592.7-146592.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -300562,15 +306982,15 @@ module \output wire width 2 input 54 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 25 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 44 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe @@ -300580,26 +307000,26 @@ module \output wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:144444$7816 + cell $and $and$libresoc.v:146937$8127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300607,10 +307027,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:144444$7816_Y + connect \Y $and$libresoc.v:146937$8127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:144452$7826 + cell $and $and$libresoc.v:146945$8137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300618,10 +307038,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:144452$7826_Y + connect \Y $and$libresoc.v:146945$8137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:144455$7829 + cell $and $and$libresoc.v:146948$8140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300629,10 +307049,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:144455$7829_Y + connect \Y $and$libresoc.v:146948$8140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:144448$7822 + cell $eq $eq$libresoc.v:146941$8133 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -300640,10 +307060,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144448$7822_Y + connect \Y $eq$libresoc.v:146941$8133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:144449$7823 + cell $eq $eq$libresoc.v:146942$8134 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -300651,50 +307071,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:144449$7823_Y + connect \Y $eq$libresoc.v:146942$8134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:144446$7818 + cell $pos $extend$libresoc.v:146939$8129 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:144446$7818_Y + connect \Y $extend$libresoc.v:146939$8129_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$libresoc.v:144447$7820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:146940$8131 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:144447$7820_Y + connect \Y $extend$libresoc.v:146940$8131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:144445$7817 + cell $not $not$libresoc.v:146938$8128 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:144445$7817_Y + connect \Y $not$libresoc.v:146938$8128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:144451$7825 + cell $not $not$libresoc.v:146944$8136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:144451$7825_Y + connect \Y $not$libresoc.v:146944$8136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:144454$7828 + cell $not $not$libresoc.v:146947$8139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:144454$7828_Y + connect \Y $not$libresoc.v:146947$8139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:144453$7827 + cell $or $or$libresoc.v:146946$8138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300702,10 +307122,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:144453$7827_Y + connect \Y $or$libresoc.v:146946$8138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:144456$7830 + cell $or $or$libresoc.v:146949$8141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -300713,47 +307133,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:144456$7830_Y + connect \Y $or$libresoc.v:146949$8141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:144446$7819 + cell $pos $pos$libresoc.v:146939$8130 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:144446$7818_Y - connect \Y $pos$libresoc.v:144446$7819_Y + connect \A $extend$libresoc.v:146939$8129_Y + connect \Y $pos$libresoc.v:146939$8130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$libresoc.v:144447$7821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:146940$8132 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:144447$7820_Y - connect \Y $pos$libresoc.v:144447$7821_Y + connect \A $extend$libresoc.v:146940$8131_Y + connect \Y $pos$libresoc.v:146940$8132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:144450$7824 + cell $reduce_or $reduce_or$libresoc.v:146943$8135 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:144450$7824_Y + connect \Y $reduce_or$libresoc.v:146943$8135_Y end - attribute \src "libresoc.v:144099.7-144099.20" - process $proc$libresoc.v:144099$7844 + attribute \src "libresoc.v:146592.7-146592.20" + process $proc$libresoc.v:146592$8155 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144457.3-144468.6" - process $proc$libresoc.v:144457$7831 + attribute \src "libresoc.v:146950.3-146961.6" + process $proc$libresoc.v:146950$8142 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:144458.5-144458.29" + attribute \src "libresoc.v:146951.5-146951.29" switch \initial - attribute \src "libresoc.v:144458.9-144458.17" + attribute \src "libresoc.v:146951.9-146951.17" case 1'1 case end @@ -300771,13 +307191,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:144469.3-144480.6" - process $proc$libresoc.v:144469$7832 + attribute \src "libresoc.v:146962.3-146973.6" + process $proc$libresoc.v:146962$8143 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:144470.5-144470.29" + attribute \src "libresoc.v:146963.5-146963.29" switch \initial - attribute \src "libresoc.v:144470.9-144470.17" + attribute \src "libresoc.v:146963.9-146963.17" case 1'1 case end @@ -300795,13 +307215,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:144481.3-144492.6" - process $proc$libresoc.v:144481$7833 + attribute \src "libresoc.v:146974.3-146985.6" + process $proc$libresoc.v:146974$8144 assign { } { } - assign $0\o$28[64:0]$7834 $1\o$28[64:0]$7835 - attribute \src "libresoc.v:144482.5-144482.29" + assign $0\o$28[64:0]$8145 $1\o$28[64:0]$8146 + attribute \src "libresoc.v:146975.5-146975.29" switch \initial - attribute \src "libresoc.v:144482.9-144482.17" + attribute \src "libresoc.v:146975.9-146975.17" case 1'1 case end @@ -300810,23 +307230,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$7835 \$29 + assign $1\o$28[64:0]$8146 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$7835 \$33 + assign $1\o$28[64:0]$8146 \$33 end sync always - update \o$28 $0\o$28[64:0]$7834 + update \o$28 $0\o$28[64:0]$8145 end - attribute \src "libresoc.v:144493.3-144502.6" - process $proc$libresoc.v:144493$7836 + attribute \src "libresoc.v:146986.3-146995.6" + process $proc$libresoc.v:146986$8147 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$7837 $1\xer_so$25[0:0]$7838 - attribute \src "libresoc.v:144494.5-144494.29" + assign $0\xer_so$25[0:0]$8148 $1\xer_so$25[0:0]$8149 + attribute \src "libresoc.v:146987.5-146987.29" switch \initial - attribute \src "libresoc.v:144494.9-144494.17" + attribute \src "libresoc.v:146987.9-146987.17" case 1'1 case end @@ -300835,21 +307255,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$7838 \$52 + assign $1\xer_so$25[0:0]$8149 \$52 case - assign $1\xer_so$25[0:0]$7838 1'0 + assign $1\xer_so$25[0:0]$8149 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$7837 + update \xer_so$25 $0\xer_so$25[0:0]$8148 end - attribute \src "libresoc.v:144503.3-144512.6" - process $proc$libresoc.v:144503$7839 + attribute \src "libresoc.v:146996.3-147005.6" + process $proc$libresoc.v:146996$8150 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:144504.5-144504.29" + attribute \src "libresoc.v:146997.5-146997.29" switch \initial - attribute \src "libresoc.v:144504.9-144504.17" + attribute \src "libresoc.v:146997.9-146997.17" case 1'1 case end @@ -300865,14 +307285,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:144513.3-144522.6" - process $proc$libresoc.v:144513$7840 + attribute \src "libresoc.v:147006.3-147015.6" + process $proc$libresoc.v:147006$8151 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$7841 $1\xer_ov$24[1:0]$7842 - attribute \src "libresoc.v:144514.5-144514.29" + assign $0\xer_ov$24[1:0]$8152 $1\xer_ov$24[1:0]$8153 + attribute \src "libresoc.v:147007.5-147007.29" switch \initial - attribute \src "libresoc.v:144514.9-144514.17" + attribute \src "libresoc.v:147007.9-147007.17" case 1'1 case end @@ -300881,21 +307301,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$7842 \xer_ov + assign $1\xer_ov$24[1:0]$8153 \xer_ov case - assign $1\xer_ov$24[1:0]$7842 2'00 + assign $1\xer_ov$24[1:0]$8153 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$7841 + update \xer_ov$24 $0\xer_ov$24[1:0]$8152 end - attribute \src "libresoc.v:144523.3-144532.6" - process $proc$libresoc.v:144523$7843 + attribute \src "libresoc.v:147016.3-147025.6" + process $proc$libresoc.v:147016$8154 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:144524.5-144524.29" + attribute \src "libresoc.v:147017.5-147017.29" switch \initial - attribute \src "libresoc.v:144524.9-144524.17" + attribute \src "libresoc.v:147017.9-147017.17" case 1'1 case end @@ -300911,19 +307331,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:144444$7816_Y - connect \$30 $not$libresoc.v:144445$7817_Y - connect \$29 $pos$libresoc.v:144446$7819_Y - connect \$33 $pos$libresoc.v:144447$7821_Y - connect \$35 $eq$libresoc.v:144448$7822_Y - connect \$37 $eq$libresoc.v:144449$7823_Y - connect \$39 $reduce_or$libresoc.v:144450$7824_Y - connect \$41 $not$libresoc.v:144451$7825_Y - connect \$43 $and$libresoc.v:144452$7826_Y - connect \$45 $or$libresoc.v:144453$7827_Y - connect \$47 $not$libresoc.v:144454$7828_Y - connect \$50 $and$libresoc.v:144455$7829_Y - connect \$52 $or$libresoc.v:144456$7830_Y + connect \$26 $and$libresoc.v:146937$8127_Y + connect \$30 $not$libresoc.v:146938$8128_Y + connect \$29 $pos$libresoc.v:146939$8130_Y + connect \$33 $pos$libresoc.v:146940$8132_Y + connect \$35 $eq$libresoc.v:146941$8133_Y + connect \$37 $eq$libresoc.v:146942$8134_Y + connect \$39 $reduce_or$libresoc.v:146943$8135_Y + connect \$41 $not$libresoc.v:146944$8136_Y + connect \$43 $and$libresoc.v:146945$8137_Y + connect \$45 $or$libresoc.v:146946$8138_Y + connect \$47 $not$libresoc.v:146947$8139_Y + connect \$50 $and$libresoc.v:146948$8140_Y + connect \$52 $or$libresoc.v:146949$8141_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -300942,60 +307362,92 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:144554.1-144898.10" +attribute \src "libresoc.v:147047.1-147442.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" -module \output$115 - attribute \src "libresoc.v:144870.3-144881.6" +module \output$100 + attribute \src "libresoc.v:147374.3-147385.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:144555.7-144555.20" + attribute \src "libresoc.v:147048.7-147048.20" wire $0\initial[0:0] - attribute \src "libresoc.v:144870.3-144881.6" + attribute \src "libresoc.v:147362.3-147373.6" + wire $0\so[0:0] + attribute \src "libresoc.v:147406.3-147415.6" + wire width 2 $0\xer_ov$17[1:0]$8175 + attribute \src "libresoc.v:147416.3-147425.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:147386.3-147395.6" + wire $0\xer_so$18[0:0]$8171 + attribute \src "libresoc.v:147396.3-147405.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:147374.3-147385.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:144867.18-144867.112" - wire $and$libresoc.v:144867$7851_Y - attribute \src "libresoc.v:144863.18-144863.122" - wire $eq$libresoc.v:144863$7847_Y - attribute \src "libresoc.v:144864.18-144864.122" - wire $eq$libresoc.v:144864$7848_Y - attribute \src "libresoc.v:144862.18-144862.101" - wire width 65 $extend$libresoc.v:144862$7845_Y - attribute \src "libresoc.v:144866.18-144866.107" - wire $not$libresoc.v:144866$7850_Y - attribute \src "libresoc.v:144869.18-144869.107" - wire $not$libresoc.v:144869$7853_Y - attribute \src "libresoc.v:144868.18-144868.115" - wire $or$libresoc.v:144868$7852_Y - attribute \src "libresoc.v:144862.18-144862.101" - wire width 65 $pos$libresoc.v:144862$7846_Y - attribute \src "libresoc.v:144865.18-144865.105" - wire $reduce_or$libresoc.v:144865$7849_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 \$23 + attribute \src "libresoc.v:147362.3-147373.6" + wire $1\so[0:0] + attribute \src "libresoc.v:147406.3-147415.6" + wire width 2 $1\xer_ov$17[1:0]$8176 + attribute \src "libresoc.v:147416.3-147425.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:147386.3-147395.6" + wire $1\xer_so$18[0:0]$8172 + attribute \src "libresoc.v:147396.3-147405.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:147351.18-147351.128" + wire $and$libresoc.v:147351$8156_Y + attribute \src "libresoc.v:147357.18-147357.112" + wire $and$libresoc.v:147357$8163_Y + attribute \src "libresoc.v:147360.18-147360.125" + wire $and$libresoc.v:147360$8166_Y + attribute \src "libresoc.v:147353.18-147353.123" + wire $eq$libresoc.v:147353$8159_Y + attribute \src "libresoc.v:147354.18-147354.123" + wire $eq$libresoc.v:147354$8160_Y + attribute \src "libresoc.v:147352.18-147352.101" + wire width 65 $extend$libresoc.v:147352$8157_Y + attribute \src "libresoc.v:147356.18-147356.107" + wire $not$libresoc.v:147356$8162_Y + attribute \src "libresoc.v:147359.18-147359.107" + wire $not$libresoc.v:147359$8165_Y + attribute \src "libresoc.v:147358.18-147358.115" + wire $or$libresoc.v:147358$8164_Y + attribute \src "libresoc.v:147361.18-147361.112" + wire $or$libresoc.v:147361$8167_Y + attribute \src "libresoc.v:147352.18-147352.101" + wire width 65 $pos$libresoc.v:147352$8158_Y + attribute \src "libresoc.v:147355.18-147355.105" + wire $reduce_or$libresoc.v:147355$8161_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$25 + wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$27 + wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$29 + wire \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$31 + wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$33 + wire \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$35 + wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$37 + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 19 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 41 \cr_a$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 42 \cr_a_ok - attribute \src "libresoc.v:144555.7-144555.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \cr_a_ok + attribute \src "libresoc.v:147048.7-147048.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -301009,20 +307461,6 @@ module \output$115 wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 45 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 39 \o$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 40 \o_ok$19 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -301037,7 +307475,7 @@ module \output$115 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit + wire width 12 input 2 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -301052,35 +307490,665 @@ module \output$115 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok + wire width 12 output 20 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 input 3 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 output 21 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \sr_op__input_carry$11 + wire input 4 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__input_cr + wire output 22 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \sr_op__input_cr$13 + wire width 32 input 12 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 38 \sr_op__insn$17 + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:147351$8156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:147351$8156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:147357$8163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:147357$8163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:147360$8166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:147360$8166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:147353$8159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:147353$8159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:147354$8160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:147354$8160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:147352$8157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:147352$8157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:147356$8162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:147356$8162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:147359$8165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:147359$8165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:147358$8164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:147358$8164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:147361$8167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:147361$8167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:147352$8158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:147352$8157_Y + connect \Y $pos$libresoc.v:147352$8158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:147355$8161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:147355$8161_Y + end + attribute \src "libresoc.v:147048.7-147048.20" + process $proc$libresoc.v:147048$8178 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147362.3-147373.6" + process $proc$libresoc.v:147362$8168 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:147363.5-147363.29" + switch \initial + attribute \src "libresoc.v:147363.9-147363.17" + case 1'1 + case + end + attribute \src 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switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:147406.3-147415.6" + process $proc$libresoc.v:147406$8174 + assign { } { } + assign { } { } + assign $0\xer_ov$17[1:0]$8175 $1\xer_ov$17[1:0]$8176 + attribute \src "libresoc.v:147407.5-147407.29" + switch \initial + attribute \src "libresoc.v:147407.9-147407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$8176 \xer_ov + case + assign $1\xer_ov$17[1:0]$8176 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$8175 + end + attribute \src "libresoc.v:147416.3-147425.6" + process $proc$libresoc.v:147416$8177 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:147417.5-147417.29" + switch \initial + attribute \src "libresoc.v:147417.9-147417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$19 $and$libresoc.v:147351$8156_Y + connect \$22 $pos$libresoc.v:147352$8158_Y + connect \$24 $eq$libresoc.v:147353$8159_Y + connect \$26 $eq$libresoc.v:147354$8160_Y + connect \$28 $reduce_or$libresoc.v:147355$8161_Y + connect \$30 $not$libresoc.v:147356$8162_Y + connect \$32 $and$libresoc.v:147357$8163_Y + connect \$34 $or$libresoc.v:147358$8164_Y + connect \$36 $not$libresoc.v:147359$8165_Y + connect \$39 $and$libresoc.v:147360$8166_Y + connect \$41 $or$libresoc.v:147361$8167_Y + connect \oe$38 \$39 + connect { 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\enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -301232,66 +308300,70 @@ module \output$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \sr_op__insn_type$2 + wire width 7 output 24 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__is_32bit + wire output 33 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__is_32bit$15 + wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_signed + wire output 38 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__is_signed$16 + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__oe__oe$8 + wire output 30 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__ok$9 + wire output 31 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__output_carry + wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__output_carry$12 + wire output 35 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__output_cr + wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_cr$14 + wire output 37 \sr_op__output_cr$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 6 \sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__ok$7 + wire output 29 \sr_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 5 \sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__rc__rc$6 + wire output 28 \sr_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire input 9 \sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__write_cr0$10 + wire output 32 \sr_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 21 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 43 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 44 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 45 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:144867$7851 + cell $and $and$libresoc.v:147763$8185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \B \$31 - connect \Y $and$libresoc.v:144867$7851_Y + connect \B \$32 + connect \Y $and$libresoc.v:147763$8185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:144863$7847 + cell $eq $eq$libresoc.v:147759$8181 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -301299,10 +308371,10 @@ module \output$115 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:144863$7847_Y + connect \Y $eq$libresoc.v:147759$8181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:144864$7848 + cell $eq $eq$libresoc.v:147760$8182 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -301310,34 +308382,34 @@ module \output$115 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:144864$7848_Y + connect \Y $eq$libresoc.v:147760$8182_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$libresoc.v:144862$7845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:147758$8179 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:144862$7845_Y + connect \Y $extend$libresoc.v:147758$8179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:144866$7850 + cell $not $not$libresoc.v:147762$8184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:144866$7850_Y + connect \Y $not$libresoc.v:147762$8184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:144869$7853 + cell $not $not$libresoc.v:147765$8187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:144869$7853_Y + connect \Y $not$libresoc.v:147765$8187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:144868$7852 + cell $or $or$libresoc.v:147764$8186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301345,44 +308417,44 @@ module \output$115 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:144868$7852_Y + connect \Y $or$libresoc.v:147764$8186_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$libresoc.v:144862$7846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:147758$8180 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:144862$7845_Y - connect \Y $pos$libresoc.v:144862$7846_Y + connect \A $extend$libresoc.v:147758$8179_Y + connect \Y $pos$libresoc.v:147758$8180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:144865$7849 + cell $reduce_or $reduce_or$libresoc.v:147761$8183 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:144865$7849_Y + connect \Y $reduce_or$libresoc.v:147761$8183_Y end - attribute \src "libresoc.v:144555.7-144555.20" - process $proc$libresoc.v:144555$7855 + attribute \src "libresoc.v:147447.7-147447.20" + process $proc$libresoc.v:147447$8189 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144870.3-144881.6" - process $proc$libresoc.v:144870$7854 + attribute \src "libresoc.v:147766.3-147777.6" + process $proc$libresoc.v:147766$8188 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:144871.5-144871.29" + attribute \src "libresoc.v:147767.5-147767.29" switch \initial - attribute \src "libresoc.v:144871.9-144871.17" + attribute \src "libresoc.v:147767.9-147767.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$35 + switch \$36 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -301390,80 +308462,80 @@ module \output$115 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$37 \xer_so } + assign $1\cr0[3:0] { \is_negative \is_positive \$38 \xer_so } end sync always update \cr0 $0\cr0[3:0] end - connect \$23 $pos$libresoc.v:144862$7846_Y - connect \$25 $eq$libresoc.v:144863$7847_Y - connect \$27 $eq$libresoc.v:144864$7848_Y - connect \$29 $reduce_or$libresoc.v:144865$7849_Y - connect \$31 $not$libresoc.v:144866$7850_Y - connect \$33 $and$libresoc.v:144867$7851_Y - connect \$35 $or$libresoc.v:144868$7852_Y - connect \$37 $not$libresoc.v:144869$7853_Y - connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \$24 $pos$libresoc.v:147758$8180_Y + connect \$26 $eq$libresoc.v:147759$8181_Y + connect \$28 $eq$libresoc.v:147760$8182_Y + connect \$30 $reduce_or$libresoc.v:147761$8183_Y + connect \$32 $not$libresoc.v:147762$8184_Y + connect \$34 $and$libresoc.v:147763$8185_Y + connect \$36 $or$libresoc.v:147764$8186_Y + connect \$38 $not$libresoc.v:147765$8187_Y + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 - connect \cr_a$20 \cr0 - connect \o_ok$19 \o_ok - connect \o$18 \o$22 [63:0] - connect \is_positive \$33 + connect \cr_a$21 \cr0 + connect \o_ok$20 \o_ok + connect \o$19 \o$23 [63:0] + connect \is_positive \$34 connect \is_negative \msb_test - connect \is_nzero \$29 + connect \is_nzero \$30 connect \msb_test \target [63] - connect \is_cmpeqb \$27 - connect \is_cmp \$25 + connect \is_cmpeqb \$28 + connect \is_cmp \$26 connect \xer_ca_ok \sr_op__output_carry - connect \xer_ca$21 \xer_ca - connect \target \o$22 [63:0] - connect \o$22 \$23 + connect \xer_ca$22 \xer_ca + connect \target \o$23 [63:0] + connect \o$23 \$24 end -attribute \src "libresoc.v:144902.1-145263.10" +attribute \src "libresoc.v:147798.1-148159.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" -module \output$51 - attribute \src "libresoc.v:145238.3-145249.6" +module \output$54 + attribute \src "libresoc.v:148134.3-148145.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:144903.7-144903.20" + attribute \src "libresoc.v:147799.7-147799.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145226.3-145237.6" - wire width 65 $0\o$23[64:0]$7869 - attribute \src "libresoc.v:145238.3-145249.6" + attribute \src "libresoc.v:148122.3-148133.6" + wire width 65 $0\o$23[64:0]$8203 + attribute \src "libresoc.v:148134.3-148145.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:145226.3-145237.6" - wire width 65 $1\o$23[64:0]$7870 - attribute \src "libresoc.v:145223.18-145223.112" - wire $and$libresoc.v:145223$7865_Y - attribute \src "libresoc.v:145219.18-145219.127" - wire $eq$libresoc.v:145219$7861_Y - attribute \src "libresoc.v:145220.18-145220.127" - wire $eq$libresoc.v:145220$7862_Y - attribute \src "libresoc.v:145217.18-145217.103" - wire width 65 $extend$libresoc.v:145217$7857_Y - attribute \src "libresoc.v:145218.18-145218.101" - wire width 65 $extend$libresoc.v:145218$7859_Y - attribute \src "libresoc.v:145216.18-145216.100" - wire width 64 $not$libresoc.v:145216$7856_Y - attribute \src "libresoc.v:145222.18-145222.107" - wire $not$libresoc.v:145222$7864_Y - attribute \src "libresoc.v:145225.18-145225.107" - wire $not$libresoc.v:145225$7867_Y - attribute \src "libresoc.v:145224.18-145224.115" - wire $or$libresoc.v:145224$7866_Y - attribute \src "libresoc.v:145217.18-145217.103" - wire width 65 $pos$libresoc.v:145217$7858_Y - attribute \src "libresoc.v:145218.18-145218.101" - wire width 65 $pos$libresoc.v:145218$7860_Y - attribute \src "libresoc.v:145221.18-145221.105" - wire $reduce_or$libresoc.v:145221$7863_Y + attribute \src "libresoc.v:148122.3-148133.6" + wire width 65 $1\o$23[64:0]$8204 + attribute \src "libresoc.v:148119.18-148119.112" + wire $and$libresoc.v:148119$8199_Y + attribute \src "libresoc.v:148115.18-148115.127" + wire $eq$libresoc.v:148115$8195_Y + attribute \src "libresoc.v:148116.18-148116.127" + wire $eq$libresoc.v:148116$8196_Y + attribute \src "libresoc.v:148113.18-148113.103" + wire width 65 $extend$libresoc.v:148113$8191_Y + attribute \src "libresoc.v:148114.18-148114.101" + wire width 65 $extend$libresoc.v:148114$8193_Y + attribute \src "libresoc.v:148112.18-148112.100" + wire width 64 $not$libresoc.v:148112$8190_Y + attribute \src "libresoc.v:148118.18-148118.107" + wire $not$libresoc.v:148118$8198_Y + attribute \src "libresoc.v:148121.18-148121.107" + wire $not$libresoc.v:148121$8201_Y + attribute \src "libresoc.v:148120.18-148120.115" + wire $or$libresoc.v:148120$8200_Y + attribute \src "libresoc.v:148113.18-148113.103" + wire width 65 $pos$libresoc.v:148113$8192_Y + attribute \src "libresoc.v:148114.18-148114.101" + wire width 65 $pos$libresoc.v:148114$8194_Y + attribute \src "libresoc.v:148117.18-148117.105" + wire $reduce_or$libresoc.v:148117$8197_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$30 @@ -301481,13 +308553,13 @@ module \output$51 wire \$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 44 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:144903.7-144903.15" + attribute \src "libresoc.v:147799.7-147799.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -301759,22 +308831,22 @@ module \output$51 wire width 2 input 46 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 42 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:145223$7865 + cell $and $and$libresoc.v:148119$8199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301782,10 +308854,10 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:145223$7865_Y + connect \Y $and$libresoc.v:148119$8199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:145219$7861 + cell $eq $eq$libresoc.v:148115$8195 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -301793,10 +308865,10 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:145219$7861_Y + connect \Y $eq$libresoc.v:148115$8195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:145220$7862 + cell $eq $eq$libresoc.v:148116$8196 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -301804,50 +308876,50 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:145220$7862_Y + connect \Y $eq$libresoc.v:148116$8196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:145217$7857 + cell $pos $extend$libresoc.v:148113$8191 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:145217$7857_Y + connect \Y $extend$libresoc.v:148113$8191_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$libresoc.v:145218$7859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:148114$8193 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:145218$7859_Y + connect \Y $extend$libresoc.v:148114$8193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:145216$7856 + cell $not $not$libresoc.v:148112$8190 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:145216$7856_Y + connect \Y $not$libresoc.v:148112$8190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:145222$7864 + cell $not $not$libresoc.v:148118$8198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:145222$7864_Y + connect \Y $not$libresoc.v:148118$8198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:145225$7867 + cell $not $not$libresoc.v:148121$8201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:145225$7867_Y + connect \Y $not$libresoc.v:148121$8201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:145224$7866 + cell $or $or$libresoc.v:148120$8200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -301855,47 +308927,47 @@ module \output$51 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:145224$7866_Y + connect \Y $or$libresoc.v:148120$8200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:145217$7858 + cell $pos $pos$libresoc.v:148113$8192 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:145217$7857_Y - connect \Y $pos$libresoc.v:145217$7858_Y + connect \A $extend$libresoc.v:148113$8191_Y + connect \Y $pos$libresoc.v:148113$8192_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$libresoc.v:145218$7860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:148114$8194 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:145218$7859_Y - connect \Y $pos$libresoc.v:145218$7860_Y + connect \A $extend$libresoc.v:148114$8193_Y + connect \Y $pos$libresoc.v:148114$8194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:145221$7863 + cell $reduce_or $reduce_or$libresoc.v:148117$8197 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:145221$7863_Y + connect \Y $reduce_or$libresoc.v:148117$8197_Y end - attribute \src "libresoc.v:144903.7-144903.20" - process $proc$libresoc.v:144903$7872 + attribute \src "libresoc.v:147799.7-147799.20" + process $proc$libresoc.v:147799$8206 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145226.3-145237.6" - process $proc$libresoc.v:145226$7868 + attribute \src "libresoc.v:148122.3-148133.6" + process $proc$libresoc.v:148122$8202 assign { } { } - assign $0\o$23[64:0]$7869 $1\o$23[64:0]$7870 - attribute \src "libresoc.v:145227.5-145227.29" + assign $0\o$23[64:0]$8203 $1\o$23[64:0]$8204 + attribute \src "libresoc.v:148123.5-148123.29" switch \initial - attribute \src "libresoc.v:145227.9-145227.17" + attribute \src "libresoc.v:148123.9-148123.17" case 1'1 case end @@ -301904,22 +308976,22 @@ module \output$51 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$7870 \$24 + assign $1\o$23[64:0]$8204 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$7870 \$28 + assign $1\o$23[64:0]$8204 \$28 end sync always - update \o$23 $0\o$23[64:0]$7869 + update \o$23 $0\o$23[64:0]$8203 end - attribute \src "libresoc.v:145238.3-145249.6" - process $proc$libresoc.v:145238$7871 + attribute \src "libresoc.v:148134.3-148145.6" + process $proc$libresoc.v:148134$8205 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:145239.5-145239.29" + attribute \src "libresoc.v:148135.5-148135.29" switch \initial - attribute \src "libresoc.v:145239.9-145239.17" + attribute \src "libresoc.v:148135.9-148135.17" case 1'1 case end @@ -301937,16 +309009,16 @@ module \output$51 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:145216$7856_Y - connect \$24 $pos$libresoc.v:145217$7858_Y - connect \$28 $pos$libresoc.v:145218$7860_Y - connect \$30 $eq$libresoc.v:145219$7861_Y - connect \$32 $eq$libresoc.v:145220$7862_Y - connect \$34 $reduce_or$libresoc.v:145221$7863_Y - connect \$36 $not$libresoc.v:145222$7864_Y - connect \$38 $and$libresoc.v:145223$7865_Y - connect \$40 $or$libresoc.v:145224$7866_Y - connect \$42 $not$libresoc.v:145225$7867_Y + connect \$25 $not$libresoc.v:148112$8190_Y + connect \$24 $pos$libresoc.v:148113$8192_Y + connect \$28 $pos$libresoc.v:148114$8194_Y + connect \$30 $eq$libresoc.v:148115$8195_Y + connect \$32 $eq$libresoc.v:148116$8196_Y + connect \$34 $reduce_or$libresoc.v:148117$8197_Y + connect \$36 $not$libresoc.v:148118$8198_Y + connect \$38 $and$libresoc.v:148119$8199_Y + connect \$40 $or$libresoc.v:148120$8200_Y + connect \$42 $not$libresoc.v:148121$8201_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -301961,78 +309033,78 @@ module \output$51 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:145267.1-145711.10" +attribute \src "libresoc.v:148163.1-148607.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" -module \output$80 - attribute \src "libresoc.v:145632.3-145643.6" +module \output$83 + attribute \src "libresoc.v:148528.3-148539.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:145268.7-145268.20" + attribute \src "libresoc.v:148164.7-148164.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145644.3-145655.6" - wire width 65 $0\o$27[64:0]$7891 - attribute \src "libresoc.v:145620.3-145631.6" + attribute \src "libresoc.v:148540.3-148551.6" + wire width 65 $0\o$27[64:0]$8225 + attribute \src "libresoc.v:148516.3-148527.6" wire $0\so[0:0] - attribute \src "libresoc.v:145676.3-145685.6" - wire width 2 $0\xer_ov$23[1:0]$7898 - attribute \src "libresoc.v:145686.3-145695.6" + attribute \src "libresoc.v:148572.3-148581.6" + wire width 2 $0\xer_ov$23[1:0]$8232 + attribute \src "libresoc.v:148582.3-148591.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:145656.3-145665.6" - wire $0\xer_so$24[0:0]$7894 - attribute \src "libresoc.v:145666.3-145675.6" + attribute \src "libresoc.v:148552.3-148561.6" + wire $0\xer_so$24[0:0]$8228 + attribute \src "libresoc.v:148562.3-148571.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:145632.3-145643.6" + attribute \src "libresoc.v:148528.3-148539.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:145644.3-145655.6" - wire width 65 $1\o$27[64:0]$7892 - attribute \src "libresoc.v:145620.3-145631.6" + attribute \src "libresoc.v:148540.3-148551.6" + wire width 65 $1\o$27[64:0]$8226 + attribute \src "libresoc.v:148516.3-148527.6" wire $1\so[0:0] - attribute \src "libresoc.v:145676.3-145685.6" - wire width 2 $1\xer_ov$23[1:0]$7899 - attribute \src "libresoc.v:145686.3-145695.6" + attribute \src "libresoc.v:148572.3-148581.6" + wire width 2 $1\xer_ov$23[1:0]$8233 + attribute \src "libresoc.v:148582.3-148591.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:145656.3-145665.6" - wire $1\xer_so$24[0:0]$7895 - attribute \src "libresoc.v:145666.3-145675.6" + attribute \src "libresoc.v:148552.3-148561.6" + wire $1\xer_so$24[0:0]$8229 + attribute \src "libresoc.v:148562.3-148571.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145607.18-145607.136" - wire $and$libresoc.v:145607$7873_Y - attribute \src "libresoc.v:145615.18-145615.112" - wire $and$libresoc.v:145615$7883_Y - attribute \src "libresoc.v:145618.18-145618.133" - wire $and$libresoc.v:145618$7886_Y - attribute \src "libresoc.v:145611.18-145611.127" - wire $eq$libresoc.v:145611$7879_Y - attribute \src "libresoc.v:145612.18-145612.127" - wire $eq$libresoc.v:145612$7880_Y - attribute \src "libresoc.v:145609.18-145609.103" - wire width 65 $extend$libresoc.v:145609$7875_Y - attribute \src "libresoc.v:145610.18-145610.101" - wire width 65 $extend$libresoc.v:145610$7877_Y - attribute \src "libresoc.v:145608.18-145608.100" - wire width 64 $not$libresoc.v:145608$7874_Y - attribute \src "libresoc.v:145614.18-145614.107" - wire $not$libresoc.v:145614$7882_Y - attribute \src "libresoc.v:145617.18-145617.107" - wire $not$libresoc.v:145617$7885_Y - attribute \src "libresoc.v:145616.18-145616.115" - wire $or$libresoc.v:145616$7884_Y - attribute \src "libresoc.v:145619.18-145619.112" - wire $or$libresoc.v:145619$7887_Y - attribute \src "libresoc.v:145609.18-145609.103" - wire width 65 $pos$libresoc.v:145609$7876_Y - attribute \src "libresoc.v:145610.18-145610.101" - wire width 65 $pos$libresoc.v:145610$7878_Y - attribute \src "libresoc.v:145613.18-145613.105" - wire $reduce_or$libresoc.v:145613$7881_Y + attribute \src "libresoc.v:148503.18-148503.136" + wire $and$libresoc.v:148503$8207_Y + attribute \src "libresoc.v:148511.18-148511.112" + wire $and$libresoc.v:148511$8217_Y + attribute \src "libresoc.v:148514.18-148514.133" + wire $and$libresoc.v:148514$8220_Y + attribute \src "libresoc.v:148507.18-148507.127" + wire $eq$libresoc.v:148507$8213_Y + attribute \src "libresoc.v:148508.18-148508.127" + wire $eq$libresoc.v:148508$8214_Y + attribute \src "libresoc.v:148505.18-148505.103" + wire width 65 $extend$libresoc.v:148505$8209_Y + attribute \src "libresoc.v:148506.18-148506.101" + wire width 65 $extend$libresoc.v:148506$8211_Y + attribute \src "libresoc.v:148504.18-148504.100" + wire width 64 $not$libresoc.v:148504$8208_Y + attribute \src "libresoc.v:148510.18-148510.107" + wire $not$libresoc.v:148510$8216_Y + attribute \src "libresoc.v:148513.18-148513.107" + wire $not$libresoc.v:148513$8219_Y + attribute \src "libresoc.v:148512.18-148512.115" + wire $or$libresoc.v:148512$8218_Y + attribute \src "libresoc.v:148515.18-148515.112" + wire $or$libresoc.v:148515$8221_Y + attribute \src "libresoc.v:148505.18-148505.103" + wire width 65 $pos$libresoc.v:148505$8210_Y + attribute \src "libresoc.v:148506.18-148506.101" + wire width 65 $pos$libresoc.v:148506$8212_Y + attribute \src "libresoc.v:148509.18-148509.105" + wire $reduce_or$libresoc.v:148509$8215_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 64 \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire \$34 @@ -302054,13 +309126,13 @@ module \output$80 wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 45 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:145268.7-145268.15" + attribute \src "libresoc.v:148164.7-148164.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -302332,15 +309404,15 @@ module \output$80 wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 43 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" wire \oe @@ -302350,20 +309422,20 @@ module \output$80 wire \so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:145607$7873 + cell $and $and$libresoc.v:148503$8207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302371,10 +309443,10 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:145607$7873_Y + connect \Y $and$libresoc.v:148503$8207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:145615$7883 + cell $and $and$libresoc.v:148511$8217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302382,10 +309454,10 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:145615$7883_Y + connect \Y $and$libresoc.v:148511$8217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:145618$7886 + cell $and $and$libresoc.v:148514$8220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302393,10 +309465,10 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:145618$7886_Y + connect \Y $and$libresoc.v:148514$8220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:145611$7879 + cell $eq $eq$libresoc.v:148507$8213 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -302404,10 +309476,10 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:145611$7879_Y + connect \Y $eq$libresoc.v:148507$8213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:145612$7880 + cell $eq $eq$libresoc.v:148508$8214 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -302415,50 +309487,50 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:145612$7880_Y + connect \Y $eq$libresoc.v:148508$8214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:145609$7875 + cell $pos $extend$libresoc.v:148505$8209 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:145609$7875_Y + connect \Y $extend$libresoc.v:148505$8209_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $extend$libresoc.v:145610$7877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:148506$8211 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:145610$7877_Y + connect \Y $extend$libresoc.v:148506$8211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:145608$7874 + cell $not $not$libresoc.v:148504$8208 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:145608$7874_Y + connect \Y $not$libresoc.v:148504$8208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:145614$7882 + cell $not $not$libresoc.v:148510$8216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:145614$7882_Y + connect \Y $not$libresoc.v:148510$8216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:145617$7885 + cell $not $not$libresoc.v:148513$8219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:145617$7885_Y + connect \Y $not$libresoc.v:148513$8219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:145616$7884 + cell $or $or$libresoc.v:148512$8218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302466,10 +309538,10 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:145616$7884_Y + connect \Y $or$libresoc.v:148512$8218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:145619$7887 + cell $or $or$libresoc.v:148515$8221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302477,47 +309549,47 @@ module \output$80 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:145619$7887_Y + connect \Y $or$libresoc.v:148515$8221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:145609$7876 + cell $pos $pos$libresoc.v:148505$8210 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:145609$7875_Y - connect \Y $pos$libresoc.v:145609$7876_Y + connect \A $extend$libresoc.v:148505$8209_Y + connect \Y $pos$libresoc.v:148505$8210_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$libresoc.v:145610$7878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:148506$8212 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:145610$7877_Y - connect \Y $pos$libresoc.v:145610$7878_Y + connect \A $extend$libresoc.v:148506$8211_Y + connect \Y $pos$libresoc.v:148506$8212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:145613$7881 + cell $reduce_or $reduce_or$libresoc.v:148509$8215 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:145613$7881_Y + connect \Y $reduce_or$libresoc.v:148509$8215_Y end - attribute \src "libresoc.v:145268.7-145268.20" - process $proc$libresoc.v:145268$7901 + attribute \src "libresoc.v:148164.7-148164.20" + process $proc$libresoc.v:148164$8235 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145620.3-145631.6" - process $proc$libresoc.v:145620$7888 + attribute \src "libresoc.v:148516.3-148527.6" + process $proc$libresoc.v:148516$8222 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:145621.5-145621.29" + attribute \src "libresoc.v:148517.5-148517.29" switch \initial - attribute \src "libresoc.v:145621.9-145621.17" + attribute \src "libresoc.v:148517.9-148517.17" case 1'1 case end @@ -302535,13 +309607,13 @@ module \output$80 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:145632.3-145643.6" - process $proc$libresoc.v:145632$7889 + attribute \src "libresoc.v:148528.3-148539.6" + process $proc$libresoc.v:148528$8223 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:145633.5-145633.29" + attribute \src "libresoc.v:148529.5-148529.29" switch \initial - attribute \src "libresoc.v:145633.9-145633.17" + attribute \src "libresoc.v:148529.9-148529.17" case 1'1 case end @@ -302559,13 +309631,13 @@ module \output$80 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:145644.3-145655.6" - process $proc$libresoc.v:145644$7890 + attribute \src "libresoc.v:148540.3-148551.6" + process $proc$libresoc.v:148540$8224 assign { } { } - assign $0\o$27[64:0]$7891 $1\o$27[64:0]$7892 - attribute \src "libresoc.v:145645.5-145645.29" + assign $0\o$27[64:0]$8225 $1\o$27[64:0]$8226 + attribute \src "libresoc.v:148541.5-148541.29" switch \initial - attribute \src "libresoc.v:145645.9-145645.17" + attribute \src "libresoc.v:148541.9-148541.17" case 1'1 case end @@ -302574,23 +309646,23 @@ module \output$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$7892 \$28 + assign $1\o$27[64:0]$8226 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$7892 \$32 + assign $1\o$27[64:0]$8226 \$32 end sync always - update \o$27 $0\o$27[64:0]$7891 + update \o$27 $0\o$27[64:0]$8225 end - attribute \src "libresoc.v:145656.3-145665.6" - process $proc$libresoc.v:145656$7893 + attribute \src "libresoc.v:148552.3-148561.6" + process $proc$libresoc.v:148552$8227 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$7894 $1\xer_so$24[0:0]$7895 - attribute \src "libresoc.v:145657.5-145657.29" + assign $0\xer_so$24[0:0]$8228 $1\xer_so$24[0:0]$8229 + attribute \src "libresoc.v:148553.5-148553.29" switch \initial - attribute \src "libresoc.v:145657.9-145657.17" + attribute \src "libresoc.v:148553.9-148553.17" case 1'1 case end @@ -302599,21 +309671,21 @@ module \output$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$7895 \$51 + assign $1\xer_so$24[0:0]$8229 \$51 case - assign $1\xer_so$24[0:0]$7895 1'0 + assign $1\xer_so$24[0:0]$8229 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$7894 + update \xer_so$24 $0\xer_so$24[0:0]$8228 end - attribute \src "libresoc.v:145666.3-145675.6" - process $proc$libresoc.v:145666$7896 + attribute \src "libresoc.v:148562.3-148571.6" + process $proc$libresoc.v:148562$8230 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145667.5-145667.29" + attribute \src "libresoc.v:148563.5-148563.29" switch \initial - attribute \src "libresoc.v:145667.9-145667.17" + attribute \src "libresoc.v:148563.9-148563.17" case 1'1 case end @@ -302629,14 +309701,14 @@ module \output$80 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145676.3-145685.6" - process $proc$libresoc.v:145676$7897 + attribute \src "libresoc.v:148572.3-148581.6" + process $proc$libresoc.v:148572$8231 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$7898 $1\xer_ov$23[1:0]$7899 - attribute \src "libresoc.v:145677.5-145677.29" + assign $0\xer_ov$23[1:0]$8232 $1\xer_ov$23[1:0]$8233 + attribute \src "libresoc.v:148573.5-148573.29" switch \initial - attribute \src "libresoc.v:145677.9-145677.17" + attribute \src "libresoc.v:148573.9-148573.17" case 1'1 case end @@ -302645,21 +309717,21 @@ module \output$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$7899 \xer_ov + assign $1\xer_ov$23[1:0]$8233 \xer_ov case - assign $1\xer_ov$23[1:0]$7899 2'00 + assign $1\xer_ov$23[1:0]$8233 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$7898 + update \xer_ov$23 $0\xer_ov$23[1:0]$8232 end - attribute \src "libresoc.v:145686.3-145695.6" - process $proc$libresoc.v:145686$7900 + attribute \src "libresoc.v:148582.3-148591.6" + process $proc$libresoc.v:148582$8234 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:145687.5-145687.29" + attribute \src "libresoc.v:148583.5-148583.29" switch \initial - attribute \src "libresoc.v:145687.9-145687.17" + attribute \src "libresoc.v:148583.9-148583.17" case 1'1 case end @@ -302675,19 +309747,19 @@ module \output$80 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:145607$7873_Y - connect \$29 $not$libresoc.v:145608$7874_Y - connect \$28 $pos$libresoc.v:145609$7876_Y - connect \$32 $pos$libresoc.v:145610$7878_Y - connect \$34 $eq$libresoc.v:145611$7879_Y - connect \$36 $eq$libresoc.v:145612$7880_Y - connect \$38 $reduce_or$libresoc.v:145613$7881_Y - connect \$40 $not$libresoc.v:145614$7882_Y - connect \$42 $and$libresoc.v:145615$7883_Y - connect \$44 $or$libresoc.v:145616$7884_Y - connect \$46 $not$libresoc.v:145617$7885_Y - connect \$49 $and$libresoc.v:145618$7886_Y - connect \$51 $or$libresoc.v:145619$7887_Y + connect \$25 $and$libresoc.v:148503$8207_Y + connect \$29 $not$libresoc.v:148504$8208_Y + connect \$28 $pos$libresoc.v:148505$8210_Y + connect \$32 $pos$libresoc.v:148506$8212_Y + connect \$34 $eq$libresoc.v:148507$8213_Y + connect \$36 $eq$libresoc.v:148508$8214_Y + connect \$38 $reduce_or$libresoc.v:148509$8215_Y + connect \$40 $not$libresoc.v:148510$8216_Y + connect \$42 $and$libresoc.v:148511$8217_Y + connect \$44 $or$libresoc.v:148512$8218_Y + connect \$46 $not$libresoc.v:148513$8219_Y + connect \$49 $and$libresoc.v:148514$8220_Y + connect \$51 $or$libresoc.v:148515$8221_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -302704,741 +309776,93 @@ module \output$80 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:145715.1-146110.10" +attribute \src "libresoc.v:148611.1-149087.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" -attribute \generator "nMigen" -module \output$97 - attribute \src "libresoc.v:146042.3-146053.6" - wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:145716.7-145716.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146030.3-146041.6" - wire $0\so[0:0] - attribute \src "libresoc.v:146074.3-146083.6" - wire width 2 $0\xer_ov$17[1:0]$7921 - attribute \src "libresoc.v:146084.3-146093.6" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:146054.3-146063.6" - wire $0\xer_so$18[0:0]$7917 - attribute \src "libresoc.v:146064.3-146073.6" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:146042.3-146053.6" - wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:146030.3-146041.6" - wire $1\so[0:0] - attribute \src "libresoc.v:146074.3-146083.6" - wire width 2 $1\xer_ov$17[1:0]$7922 - attribute \src "libresoc.v:146084.3-146093.6" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146054.3-146063.6" - wire $1\xer_so$18[0:0]$7918 - attribute \src "libresoc.v:146064.3-146073.6" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:146019.18-146019.128" - wire $and$libresoc.v:146019$7902_Y - attribute \src "libresoc.v:146025.18-146025.112" - wire $and$libresoc.v:146025$7909_Y - attribute \src "libresoc.v:146028.18-146028.125" - wire $and$libresoc.v:146028$7912_Y - attribute \src "libresoc.v:146021.18-146021.123" - wire $eq$libresoc.v:146021$7905_Y - attribute \src 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wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 15 \cr_a - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:146028$7912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:146028$7912_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:146021$7905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:146021$7905_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:146022$7906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001100 - connect \Y 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\A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:146026$7910_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:146029$7913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$libresoc.v:146029$7913_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $pos$libresoc.v:146020$7904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146020$7903_Y - connect \Y $pos$libresoc.v:146020$7904_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:146023$7907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 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\initial - attribute \src "libresoc.v:146075.9-146075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$38 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov$17[1:0]$7922 \xer_ov - case - assign $1\xer_ov$17[1:0]$7922 2'00 - end - sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$7921 - end - attribute \src "libresoc.v:146084.3-146093.6" - process $proc$libresoc.v:146084$7923 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:146085.5-146085.29" - switch \initial - attribute \src "libresoc.v:146085.9-146085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$38 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end 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\src "libresoc.v:146501.3-146572.6" + attribute \src "libresoc.v:148968.3-149039.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:146501.3-146572.6" + attribute \src "libresoc.v:148968.3-149039.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:146501.3-146572.6" + attribute \src "libresoc.v:148968.3-149039.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:146458.18-146458.122" - wire $and$libresoc.v:146458$7938_Y - attribute \src "libresoc.v:146450.18-146450.109" - wire width 65 $extend$libresoc.v:146450$7926_Y - attribute \src "libresoc.v:146451.18-146451.100" - wire width 65 $extend$libresoc.v:146451$7928_Y - attribute \src "libresoc.v:146453.18-146453.113" - wire width 65 $extend$libresoc.v:146453$7931_Y - attribute \src "libresoc.v:146454.18-146454.104" - wire width 65 $extend$libresoc.v:146454$7933_Y - attribute \src "libresoc.v:146461.18-146461.114" - wire width 64 $extend$libresoc.v:146461$7941_Y - attribute \src "libresoc.v:146462.18-146462.114" - wire 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"libresoc.v:148960.18-148960.128" + wire $ne$libresoc.v:148960$8250_Y + attribute \src "libresoc.v:148951.18-148951.109" + wire width 65 $neg$libresoc.v:148951$8238_Y + attribute \src "libresoc.v:148954.18-148954.113" + wire width 65 $neg$libresoc.v:148954$8243_Y + attribute \src "libresoc.v:148957.18-148957.116" + wire $not$libresoc.v:148957$8247_Y + attribute \src "libresoc.v:148962.18-148962.99" + wire $not$libresoc.v:148962$8252_Y + attribute \src "libresoc.v:148952.18-148952.100" + wire width 65 $pos$libresoc.v:148952$8240_Y + attribute \src "libresoc.v:148955.18-148955.104" + wire width 65 $pos$libresoc.v:148955$8245_Y + attribute \src "libresoc.v:148961.18-148961.118" + wire width 64 $pos$libresoc.v:148961$8251_Y + attribute \src "libresoc.v:148963.18-148963.114" + wire width 64 $pos$libresoc.v:148963$8254_Y + attribute \src "libresoc.v:148964.18-148964.114" + wire width 64 $pos$libresoc.v:148964$8256_Y + attribute \src "libresoc.v:148965.18-148965.114" + wire width 64 $pos$libresoc.v:148965$8258_Y + attribute \src "libresoc.v:148966.18-148966.114" + wire width 64 $pos$libresoc.v:148966$8260_Y + attribute \src "libresoc.v:148967.18-148967.115" + wire width 64 $pos$libresoc.v:148967$8262_Y + attribute \src "libresoc.v:148953.18-148953.121" + wire width 65 $ternary$libresoc.v:148953$8241_Y + attribute \src "libresoc.v:148956.18-148956.122" + wire width 65 $ternary$libresoc.v:148956$8246_Y + attribute \src "libresoc.v:148950.18-148950.120" + wire $xor$libresoc.v:148950$8236_Y + attribute \src "libresoc.v:148958.18-148958.127" + wire $xor$libresoc.v:148958$8248_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -303463,19 +309887,19 @@ module \output_stage wire \$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 64 \$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - wire width 64 \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" wire width 64 \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" wire width 64 \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" wire width 64 \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" wire width 64 \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" wire width 64 \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 24 \div_by_zero @@ -303487,7 +309911,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:146115.7-146115.15" + attribute \src "libresoc.v:148612.7-148612.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -303747,9 +310171,9 @@ module \output_stage wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 27 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" wire \ov @@ -303765,16 +310189,20 @@ module \output_stage wire width 64 \remainder_64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" wire \remainder_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 32 \remainder_s32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + wire width 64 \remainder_s32_as_s64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:146458$7938 + cell $and $and$libresoc.v:148959$8249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303782,82 +310210,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:146458$7938_Y + connect \Y $and$libresoc.v:148959$8249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:146450$7926 + cell $pos $extend$libresoc.v:148951$8237 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:146450$7926_Y + connect \Y $extend$libresoc.v:148951$8237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:146451$7928 + cell $pos $extend$libresoc.v:148952$8239 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:146451$7928_Y + connect \Y $extend$libresoc.v:148952$8239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:146453$7931 + cell $pos $extend$libresoc.v:148954$8242 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:146453$7931_Y + connect \Y $extend$libresoc.v:148954$8242_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:146454$7933 + cell $pos $extend$libresoc.v:148955$8244 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:146454$7933_Y + connect \Y $extend$libresoc.v:148955$8244_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $extend$libresoc.v:146461$7941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $extend$libresoc.v:148963$8253 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:146461$7941_Y + connect \Y $extend$libresoc.v:148963$8253_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $extend$libresoc.v:146462$7943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $extend$libresoc.v:148964$8255 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:146462$7943_Y + connect \Y $extend$libresoc.v:148964$8255_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $extend$libresoc.v:146463$7945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $extend$libresoc.v:148965$8257 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:146463$7945_Y + connect \Y $extend$libresoc.v:148965$8257_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $extend$libresoc.v:146464$7947 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $extend$libresoc.v:148966$8259 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:146464$7947_Y + connect \Y $extend$libresoc.v:148966$8259_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $extend$libresoc.v:146466$7950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $extend$libresoc.v:148967$8261 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:146466$7950_Y + connect \Y $extend$libresoc.v:148967$8261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:146459$7939 + cell $ne $ne$libresoc.v:148960$8250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303865,122 +310293,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:146459$7939_Y + connect \Y $ne$libresoc.v:148960$8250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:146450$7927 + cell $neg $neg$libresoc.v:148951$8238 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146450$7926_Y - connect \Y $neg$libresoc.v:146450$7927_Y + connect \A $extend$libresoc.v:148951$8237_Y + connect \Y $neg$libresoc.v:148951$8238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:146453$7932 + cell $neg $neg$libresoc.v:148954$8243 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146453$7931_Y - connect \Y $neg$libresoc.v:146453$7932_Y + connect \A $extend$libresoc.v:148954$8242_Y + connect \Y $neg$libresoc.v:148954$8243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:146456$7936 + cell $not $not$libresoc.v:148957$8247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:146456$7936_Y + connect \Y $not$libresoc.v:148957$8247_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - cell $not $not$libresoc.v:146460$7940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $not $not$libresoc.v:148962$8252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:146460$7940_Y + connect \Y $not$libresoc.v:148962$8252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:146451$7929 + cell $pos $pos$libresoc.v:148952$8240 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146451$7928_Y - connect \Y $pos$libresoc.v:146451$7929_Y + connect \A $extend$libresoc.v:148952$8239_Y + connect \Y $pos$libresoc.v:148952$8240_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:146454$7934 + cell $pos $pos$libresoc.v:148955$8245 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:146454$7933_Y - connect \Y $pos$libresoc.v:146454$7934_Y + connect \A $extend$libresoc.v:148955$8244_Y + connect \Y $pos$libresoc.v:148955$8245_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $pos$libresoc.v:146461$7942 - parameter \A_SIGNED 0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + cell $pos $pos$libresoc.v:148961$8251 + parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146461$7941_Y - connect \Y $pos$libresoc.v:146461$7942_Y + connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } + connect \Y $pos$libresoc.v:148961$8251_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $pos$libresoc.v:146462$7944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $pos$libresoc.v:148963$8254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146462$7943_Y - connect \Y $pos$libresoc.v:146462$7944_Y + connect \A $extend$libresoc.v:148963$8253_Y + connect \Y $pos$libresoc.v:148963$8254_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $pos$libresoc.v:146463$7946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $pos$libresoc.v:148964$8256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146463$7945_Y - connect \Y $pos$libresoc.v:146463$7946_Y + connect \A $extend$libresoc.v:148964$8255_Y + connect \Y $pos$libresoc.v:148964$8256_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $pos$libresoc.v:146464$7948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $pos$libresoc.v:148965$8258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146464$7947_Y - connect \Y $pos$libresoc.v:146464$7948_Y + connect \A $extend$libresoc.v:148965$8257_Y + connect \Y $pos$libresoc.v:148965$8258_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - cell $pos $pos$libresoc.v:146465$7949 - parameter \A_SIGNED 1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $pos$libresoc.v:148966$8260 + parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A { \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31:0] } - connect \Y $pos$libresoc.v:146465$7949_Y + connect \A $extend$libresoc.v:148966$8259_Y + connect \Y $pos$libresoc.v:148966$8260_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $pos$libresoc.v:146466$7951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $pos$libresoc.v:148967$8262 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:146466$7950_Y - connect \Y $pos$libresoc.v:146466$7951_Y + connect \A $extend$libresoc.v:148967$8261_Y + connect \Y $pos$libresoc.v:148967$8262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:146452$7930 + cell $mux $ternary$libresoc.v:148953$8241 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:146452$7930_Y + connect \Y $ternary$libresoc.v:148953$8241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:146455$7935 + cell $mux $ternary$libresoc.v:148956$8246 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:146455$7935_Y + connect \Y $ternary$libresoc.v:148956$8246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:146449$7925 + cell $xor $xor$libresoc.v:148950$8236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303988,10 +310416,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:146449$7925_Y + connect \Y $xor$libresoc.v:148950$8236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:146457$7937 + cell $xor $xor$libresoc.v:148958$8248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303999,107 +310427,55 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:146457$7937_Y + connect \Y $xor$libresoc.v:148958$8248_Y end - attribute \src "libresoc.v:146115.7-146115.20" - process $proc$libresoc.v:146115$7954 + attribute \src "libresoc.v:148612.7-148612.20" + process $proc$libresoc.v:148612$8265 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146467.3-146500.6" - process $proc$libresoc.v:146467$7952 - assign { } { } - assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:146468.5-146468.29" - switch \initial - attribute \src "libresoc.v:146468.9-146468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed \$36 \div_by_zero } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\ov[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign { } { } - assign $1\ov[0:0] $2\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ov[0:0] 1'1 - case - assign $2\ov[0:0] \dive_abs_ov64 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign { } { } - assign $1\ov[0:0] $3\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ov[0:0] 1'1 - case - assign $3\ov[0:0] \dive_abs_ov32 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ov[0:0] \dive_abs_ov32 - end - sync always - update \ov $0\ov[0:0] - end - attribute \src "libresoc.v:146501.3-146572.6" - process $proc$libresoc.v:146501$7953 + attribute \src "libresoc.v:148968.3-149039.6" + process $proc$libresoc.v:148968$8263 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:146502.5-146502.29" + attribute \src "libresoc.v:148969.5-148969.29" switch \initial - attribute \src "libresoc.v:146502.9-146502.17" + attribute \src "libresoc.v:148969.9-148969.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - switch \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + switch \$46 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" case 7'0011110 assign { } { } assign $2\o[63:0] $3\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\o[63:0] \$46 + assign $4\o[63:0] \$48 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\o[63:0] \$48 + assign $4\o[63:0] \$50 end attribute \src "libresoc.v:0.0-0.0" case @@ -304110,22 +310486,22 @@ module \output_stage case 7'0011101 assign { } { } assign $2\o[63:0] $5\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\o[63:0] $6\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\o[63:0] \$50 + assign $6\o[63:0] \$52 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $6\o[63:0] \$52 + assign $6\o[63:0] \$54 end attribute \src "libresoc.v:0.0-0.0" case @@ -304136,18 +310512,18 @@ module \output_stage case 7'0101111 assign { } { } assign $2\o[63:0] $7\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" switch \logical_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\o[63:0] $8\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" switch \logical_op__is_signed attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\o[63:0] \$54 + assign $8\o[63:0] \remainder_s32_as_s64 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -304167,28 +310543,82 @@ module \output_stage sync always update \o $0\o[63:0] end - connect \$21 $xor$libresoc.v:146449$7925_Y - connect \$23 $neg$libresoc.v:146450$7927_Y - connect \$25 $pos$libresoc.v:146451$7929_Y - connect \$27 $ternary$libresoc.v:146452$7930_Y - connect \$30 $neg$libresoc.v:146453$7932_Y - connect \$32 $pos$libresoc.v:146454$7934_Y - connect \$34 $ternary$libresoc.v:146455$7935_Y - connect \$36 $not$libresoc.v:146456$7936_Y - connect \$38 $xor$libresoc.v:146457$7937_Y - connect \$40 $and$libresoc.v:146458$7938_Y - connect \$42 $ne$libresoc.v:146459$7939_Y - connect \$44 $not$libresoc.v:146460$7940_Y - connect \$46 $pos$libresoc.v:146461$7942_Y - connect \$48 $pos$libresoc.v:146462$7944_Y - connect \$50 $pos$libresoc.v:146463$7946_Y - connect \$52 $pos$libresoc.v:146464$7948_Y - connect \$54 $pos$libresoc.v:146465$7949_Y - connect \$56 $pos$libresoc.v:146466$7951_Y + attribute \src "libresoc.v:149040.3-149073.6" + process $proc$libresoc.v:149040$8264 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:149041.5-149041.29" + switch \initial + attribute \src "libresoc.v:149041.9-149041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + connect \$21 $xor$libresoc.v:148950$8236_Y + connect \$23 $neg$libresoc.v:148951$8238_Y + connect \$25 $pos$libresoc.v:148952$8240_Y + connect \$27 $ternary$libresoc.v:148953$8241_Y + connect \$30 $neg$libresoc.v:148954$8243_Y + connect \$32 $pos$libresoc.v:148955$8245_Y + connect \$34 $ternary$libresoc.v:148956$8246_Y + connect \$36 $not$libresoc.v:148957$8247_Y + connect \$38 $xor$libresoc.v:148958$8248_Y + connect \$40 $and$libresoc.v:148959$8249_Y + connect \$42 $ne$libresoc.v:148960$8250_Y + connect \$44 $pos$libresoc.v:148961$8251_Y + connect \$46 $not$libresoc.v:148962$8252_Y + connect \$48 $pos$libresoc.v:148963$8254_Y + connect \$50 $pos$libresoc.v:148964$8256_Y + connect \$52 $pos$libresoc.v:148965$8258_Y + connect \$54 $pos$libresoc.v:148966$8260_Y + connect \$56 $pos$libresoc.v:148967$8262_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so + connect \remainder_s32_as_s64 \$44 + connect \remainder_s32 \remainder_64 [31:0] connect \o_ok 1'1 connect \xer_ov { \ov \ov } connect \xer_ov_ok 1'1 @@ -304197,13 +310627,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:146588.1-146599.10" +attribute \src "libresoc.v:149091.1-149102.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:146597.17-146597.111" - wire $and$libresoc.v:146597$7955_Y + attribute \src "libresoc.v:149100.17-149100.111" + wire $and$libresoc.v:149100$8266_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304213,7 +310643,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146597$7955 + cell $and $and$libresoc.v:149100$8266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304221,18 +310651,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146597$7955_Y + connect \Y $and$libresoc.v:149100$8266_Y end - connect \$1 $and$libresoc.v:146597$7955_Y + connect \$1 $and$libresoc.v:149100$8266_Y connect \trigger \$1 end -attribute \src "libresoc.v:146603.1-146614.10" +attribute \src "libresoc.v:149106.1-149117.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:146612.17-146612.111" - wire $and$libresoc.v:146612$7956_Y + attribute \src "libresoc.v:149115.17-149115.111" + wire $and$libresoc.v:149115$8267_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304242,7 +310672,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146612$7956 + cell $and $and$libresoc.v:149115$8267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304250,18 +310680,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146612$7956_Y + connect \Y $and$libresoc.v:149115$8267_Y end - connect \$1 $and$libresoc.v:146612$7956_Y + connect \$1 $and$libresoc.v:149115$8267_Y connect \trigger \$1 end -attribute \src "libresoc.v:146618.1-146629.10" +attribute \src "libresoc.v:149121.1-149132.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" -module \p$105 - attribute \src "libresoc.v:146627.17-146627.111" - wire $and$libresoc.v:146627$7957_Y +module \p$108 + attribute \src "libresoc.v:149130.17-149130.111" + wire $and$libresoc.v:149130$8268_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304271,7 +310701,7 @@ module \p$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146627$7957 + cell $and $and$libresoc.v:149130$8268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304279,18 +310709,18 @@ module \p$105 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146627$7957_Y + connect \Y $and$libresoc.v:149130$8268_Y end - connect \$1 $and$libresoc.v:146627$7957_Y + connect \$1 $and$libresoc.v:149130$8268_Y connect \trigger \$1 end -attribute \src "libresoc.v:146633.1-146644.10" +attribute \src "libresoc.v:149136.1-149147.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" -module \p$108 - attribute \src "libresoc.v:146642.17-146642.111" - wire $and$libresoc.v:146642$7958_Y +module \p$111 + attribute \src "libresoc.v:149145.17-149145.111" + wire $and$libresoc.v:149145$8269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304300,7 +310730,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146642$7958 + cell $and $and$libresoc.v:149145$8269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304308,18 +310738,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146642$7958_Y + connect \Y $and$libresoc.v:149145$8269_Y end - connect \$1 $and$libresoc.v:146642$7958_Y + connect \$1 $and$libresoc.v:149145$8269_Y connect \trigger \$1 end -attribute \src "libresoc.v:146648.1-146659.10" +attribute \src "libresoc.v:149151.1-149162.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" -module \p$113 - attribute \src "libresoc.v:146657.17-146657.111" - wire $and$libresoc.v:146657$7959_Y +module \p$116 + attribute \src "libresoc.v:149160.17-149160.111" + wire $and$libresoc.v:149160$8270_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304329,7 +310759,7 @@ module \p$113 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146657$7959 + cell $and $and$libresoc.v:149160$8270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304337,18 +310767,18 @@ module \p$113 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146657$7959_Y + connect \Y $and$libresoc.v:149160$8270_Y end - connect \$1 $and$libresoc.v:146657$7959_Y + connect \$1 $and$libresoc.v:149160$8270_Y connect \trigger \$1 end -attribute \src "libresoc.v:146663.1-146674.10" +attribute \src "libresoc.v:149166.1-149177.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:146672.17-146672.111" - wire $and$libresoc.v:146672$7960_Y + attribute \src "libresoc.v:149175.17-149175.111" + wire $and$libresoc.v:149175$8271_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304358,7 +310788,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146672$7960 + cell $and $and$libresoc.v:149175$8271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304366,18 +310796,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146672$7960_Y + connect \Y $and$libresoc.v:149175$8271_Y end - connect \$1 $and$libresoc.v:146672$7960_Y + connect \$1 $and$libresoc.v:149175$8271_Y connect \trigger \$1 end -attribute \src "libresoc.v:146678.1-146689.10" +attribute \src "libresoc.v:149181.1-149192.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:146687.17-146687.111" - wire $and$libresoc.v:146687$7961_Y + attribute \src "libresoc.v:149190.17-149190.111" + wire $and$libresoc.v:149190$8272_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304387,7 +310817,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146687$7961 + cell $and $and$libresoc.v:149190$8272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304395,18 +310825,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146687$7961_Y + connect \Y $and$libresoc.v:149190$8272_Y end - connect \$1 $and$libresoc.v:146687$7961_Y + connect \$1 $and$libresoc.v:149190$8272_Y connect \trigger \$1 end -attribute \src "libresoc.v:146693.1-146704.10" +attribute \src "libresoc.v:149196.1-149207.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:146702.17-146702.111" - wire $and$libresoc.v:146702$7962_Y + attribute \src "libresoc.v:149205.17-149205.111" + wire $and$libresoc.v:149205$8273_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304416,7 +310846,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146702$7962 + cell $and $and$libresoc.v:149205$8273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304424,18 +310854,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146702$7962_Y + connect \Y $and$libresoc.v:149205$8273_Y end - connect \$1 $and$libresoc.v:146702$7962_Y + connect \$1 $and$libresoc.v:149205$8273_Y connect \trigger \$1 end -attribute \src "libresoc.v:146708.1-146719.10" +attribute \src "libresoc.v:149211.1-149222.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:146717.17-146717.111" - wire $and$libresoc.v:146717$7963_Y + attribute \src "libresoc.v:149220.17-149220.111" + wire $and$libresoc.v:149220$8274_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304445,7 +310875,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146717$7963 + cell $and $and$libresoc.v:149220$8274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304453,18 +310883,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146717$7963_Y + connect \Y $and$libresoc.v:149220$8274_Y end - connect \$1 $and$libresoc.v:146717$7963_Y + connect \$1 $and$libresoc.v:149220$8274_Y connect \trigger \$1 end -attribute \src "libresoc.v:146723.1-146734.10" +attribute \src "libresoc.v:149226.1-149237.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:146732.17-146732.111" - wire $and$libresoc.v:146732$7964_Y + attribute \src "libresoc.v:149235.17-149235.111" + wire $and$libresoc.v:149235$8275_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304474,7 +310904,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146732$7964 + cell $and $and$libresoc.v:149235$8275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304482,18 +310912,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146732$7964_Y + connect \Y $and$libresoc.v:149235$8275_Y end - connect \$1 $and$libresoc.v:146732$7964_Y + connect \$1 $and$libresoc.v:149235$8275_Y connect \trigger \$1 end -attribute \src "libresoc.v:146738.1-146749.10" +attribute \src "libresoc.v:149241.1-149252.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" -module \p$43 - attribute \src "libresoc.v:146747.17-146747.111" - wire $and$libresoc.v:146747$7965_Y +module \p$36 + attribute \src "libresoc.v:149250.17-149250.111" + wire $and$libresoc.v:149250$8276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304503,7 +310933,7 @@ module \p$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146747$7965 + cell $and $and$libresoc.v:149250$8276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304511,18 +310941,18 @@ module \p$43 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146747$7965_Y + connect \Y $and$libresoc.v:149250$8276_Y end - connect \$1 $and$libresoc.v:146747$7965_Y + connect \$1 $and$libresoc.v:149250$8276_Y connect \trigger \$1 end -attribute \src "libresoc.v:146753.1-146764.10" +attribute \src "libresoc.v:149256.1-149267.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" -module \p$45 - attribute \src "libresoc.v:146762.17-146762.111" - wire $and$libresoc.v:146762$7966_Y +module \p$46 + attribute \src "libresoc.v:149265.17-149265.111" + wire $and$libresoc.v:149265$8277_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304532,7 +310962,7 @@ module \p$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146762$7966 + cell $and $and$libresoc.v:149265$8277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304540,18 +310970,18 @@ module \p$45 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146762$7966_Y + connect \Y $and$libresoc.v:149265$8277_Y end - connect \$1 $and$libresoc.v:146762$7966_Y + connect \$1 $and$libresoc.v:149265$8277_Y connect \trigger \$1 end -attribute \src "libresoc.v:146768.1-146779.10" +attribute \src "libresoc.v:149271.1-149282.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" -module \p$49 - attribute \src "libresoc.v:146777.17-146777.111" - wire $and$libresoc.v:146777$7967_Y +module \p$48 + attribute \src "libresoc.v:149280.17-149280.111" + wire $and$libresoc.v:149280$8278_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304561,7 +310991,7 @@ module \p$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146777$7967 + cell $and $and$libresoc.v:149280$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304569,18 +310999,18 @@ module \p$49 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146777$7967_Y + connect \Y $and$libresoc.v:149280$8278_Y end - connect \$1 $and$libresoc.v:146777$7967_Y + connect \$1 $and$libresoc.v:149280$8278_Y connect \trigger \$1 end -attribute \src "libresoc.v:146783.1-146794.10" +attribute \src "libresoc.v:149286.1-149297.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:146792.17-146792.111" - wire $and$libresoc.v:146792$7968_Y + attribute \src "libresoc.v:149295.17-149295.111" + wire $and$libresoc.v:149295$8279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304590,7 +311020,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146792$7968 + cell $and $and$libresoc.v:149295$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304598,18 +311028,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146792$7968_Y + connect \Y $and$libresoc.v:149295$8279_Y end - connect \$1 $and$libresoc.v:146792$7968_Y + connect \$1 $and$libresoc.v:149295$8279_Y connect \trigger \$1 end -attribute \src "libresoc.v:146798.1-146809.10" +attribute \src "libresoc.v:149301.1-149312.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" -module \p$59 - attribute \src "libresoc.v:146807.17-146807.111" - wire $and$libresoc.v:146807$7969_Y +module \p$52 + attribute \src "libresoc.v:149310.17-149310.111" + wire $and$libresoc.v:149310$8280_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304619,7 +311049,7 @@ module \p$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146807$7969 + cell $and $and$libresoc.v:149310$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304627,18 +311057,18 @@ module \p$59 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146807$7969_Y + connect \Y $and$libresoc.v:149310$8280_Y end - connect \$1 $and$libresoc.v:146807$7969_Y + connect \$1 $and$libresoc.v:149310$8280_Y connect \trigger \$1 end -attribute \src "libresoc.v:146813.1-146824.10" +attribute \src "libresoc.v:149316.1-149327.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:146822.17-146822.111" - wire $and$libresoc.v:146822$7970_Y + attribute \src "libresoc.v:149325.17-149325.111" + wire $and$libresoc.v:149325$8281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304648,7 +311078,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146822$7970 + cell $and $and$libresoc.v:149325$8281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304656,18 +311086,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146822$7970_Y + connect \Y $and$libresoc.v:149325$8281_Y end - connect \$1 $and$libresoc.v:146822$7970_Y + connect \$1 $and$libresoc.v:149325$8281_Y connect \trigger \$1 end -attribute \src "libresoc.v:146828.1-146839.10" +attribute \src "libresoc.v:149331.1-149342.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" -module \p$7 - attribute \src "libresoc.v:146837.17-146837.111" - wire $and$libresoc.v:146837$7971_Y +module \p$65 + attribute \src "libresoc.v:149340.17-149340.111" + wire $and$libresoc.v:149340$8282_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304677,7 +311107,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146837$7971 + cell $and $and$libresoc.v:149340$8282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304685,18 +311115,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146837$7971_Y + connect \Y $and$libresoc.v:149340$8282_Y end - connect \$1 $and$libresoc.v:146837$7971_Y + connect \$1 $and$libresoc.v:149340$8282_Y connect \trigger \$1 end -attribute \src "libresoc.v:146843.1-146854.10" +attribute \src "libresoc.v:149346.1-149357.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" -module \p$71 - attribute \src "libresoc.v:146852.17-146852.111" - wire $and$libresoc.v:146852$7972_Y +module \p$7 + attribute \src "libresoc.v:149355.17-149355.111" + wire $and$libresoc.v:149355$8283_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304706,7 +311136,7 @@ module \p$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146852$7972 + cell $and $and$libresoc.v:149355$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304714,18 +311144,18 @@ module \p$71 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146852$7972_Y + connect \Y $and$libresoc.v:149355$8283_Y end - connect \$1 $and$libresoc.v:146852$7972_Y + connect \$1 $and$libresoc.v:149355$8283_Y connect \trigger \$1 end -attribute \src "libresoc.v:146858.1-146869.10" +attribute \src "libresoc.v:149361.1-149372.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" -module \p$73 - attribute \src "libresoc.v:146867.17-146867.111" - wire $and$libresoc.v:146867$7973_Y +module \p$74 + attribute \src "libresoc.v:149370.17-149370.111" + wire $and$libresoc.v:149370$8284_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304735,7 +311165,7 @@ module \p$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146867$7973 + cell $and $and$libresoc.v:149370$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304743,18 +311173,18 @@ module \p$73 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146867$7973_Y + connect \Y $and$libresoc.v:149370$8284_Y end - connect \$1 $and$libresoc.v:146867$7973_Y + connect \$1 $and$libresoc.v:149370$8284_Y connect \trigger \$1 end -attribute \src "libresoc.v:146873.1-146884.10" +attribute \src "libresoc.v:149376.1-149387.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:146882.17-146882.111" - wire $and$libresoc.v:146882$7974_Y + attribute \src "libresoc.v:149385.17-149385.111" + wire $and$libresoc.v:149385$8285_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304764,7 +311194,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146882$7974 + cell $and $and$libresoc.v:149385$8285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304772,18 +311202,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146882$7974_Y + connect \Y $and$libresoc.v:149385$8285_Y end - connect \$1 $and$libresoc.v:146882$7974_Y + connect \$1 $and$libresoc.v:149385$8285_Y connect \trigger \$1 end -attribute \src "libresoc.v:146888.1-146899.10" +attribute \src "libresoc.v:149391.1-149402.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" -module \p$78 - attribute \src "libresoc.v:146897.17-146897.111" - wire $and$libresoc.v:146897$7975_Y +module \p$79 + attribute \src "libresoc.v:149400.17-149400.111" + wire $and$libresoc.v:149400$8286_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304793,7 +311223,7 @@ module \p$78 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146897$7975 + cell $and $and$libresoc.v:149400$8286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304801,18 +311231,18 @@ module \p$78 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146897$7975_Y + connect \Y $and$libresoc.v:149400$8286_Y end - connect \$1 $and$libresoc.v:146897$7975_Y + connect \$1 $and$libresoc.v:149400$8286_Y connect \trigger \$1 end -attribute \src "libresoc.v:146903.1-146914.10" +attribute \src "libresoc.v:149406.1-149417.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" -module \p$88 - attribute \src "libresoc.v:146912.17-146912.111" - wire $and$libresoc.v:146912$7976_Y +module \p$81 + attribute \src "libresoc.v:149415.17-149415.111" + wire $and$libresoc.v:149415$8287_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304822,7 +311252,7 @@ module \p$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146912$7976 + cell $and $and$libresoc.v:149415$8287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304830,18 +311260,18 @@ module \p$88 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146912$7976_Y + connect \Y $and$libresoc.v:149415$8287_Y end - connect \$1 $and$libresoc.v:146912$7976_Y + connect \$1 $and$libresoc.v:149415$8287_Y connect \trigger \$1 end -attribute \src "libresoc.v:146918.1-146929.10" +attribute \src "libresoc.v:149421.1-149432.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" -module \p$90 - attribute \src "libresoc.v:146927.17-146927.111" - wire $and$libresoc.v:146927$7977_Y +module \p$91 + attribute \src "libresoc.v:149430.17-149430.111" + wire $and$libresoc.v:149430$8288_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304851,7 +311281,7 @@ module \p$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146927$7977 + cell $and $and$libresoc.v:149430$8288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304859,18 +311289,47 @@ module \p$90 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146927$7977_Y + connect \Y $and$libresoc.v:149430$8288_Y end - connect \$1 $and$libresoc.v:146927$7977_Y + connect \$1 $and$libresoc.v:149430$8288_Y connect \trigger \$1 end -attribute \src "libresoc.v:146933.1-146944.10" +attribute \src "libresoc.v:149436.1-149447.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:146942.17-146942.111" - wire $and$libresoc.v:146942$7978_Y + attribute \src "libresoc.v:149445.17-149445.111" + wire $and$libresoc.v:149445$8289_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$libresoc.v:149445$8289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:149445$8289_Y + end + connect \$1 $and$libresoc.v:149445$8289_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:149451.1-149462.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" +attribute \generator "nMigen" +module \p$96 + attribute \src "libresoc.v:149460.17-149460.111" + wire $and$libresoc.v:149460$8290_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304880,7 +311339,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146942$7978 + cell $and $and$libresoc.v:149460$8290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304888,18 +311347,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146942$7978_Y + connect \Y $and$libresoc.v:149460$8290_Y end - connect \$1 $and$libresoc.v:146942$7978_Y + connect \$1 $and$libresoc.v:149460$8290_Y connect \trigger \$1 end -attribute \src "libresoc.v:146948.1-146959.10" +attribute \src "libresoc.v:149466.1-149477.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" -module \p$95 - attribute \src "libresoc.v:146957.17-146957.111" - wire $and$libresoc.v:146957$7979_Y +module \p$98 + attribute \src "libresoc.v:149475.17-149475.111" + wire $and$libresoc.v:149475$8291_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -304909,7 +311368,7 @@ module \p$95 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:146957$7979 + cell $and $and$libresoc.v:149475$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304917,36 +311376,36 @@ module \p$95 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:146957$7979_Y + connect \Y $and$libresoc.v:149475$8291_Y end - connect \$1 $and$libresoc.v:146957$7979_Y + connect \$1 $and$libresoc.v:149475$8291_Y connect \trigger \$1 end -attribute \src "libresoc.v:146963.1-146986.10" +attribute \src "libresoc.v:149481.1-149504.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:146964.7-146964.20" + attribute \src "libresoc.v:149482.7-149482.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146975.3-146984.6" + attribute \src "libresoc.v:149493.3-149502.6" wire $0\o[0:0] - attribute \src "libresoc.v:146975.3-146984.6" + attribute \src "libresoc.v:149493.3-149502.6" wire $1\o[0:0] - attribute \src "libresoc.v:146974.17-146974.95" - wire $eq$libresoc.v:146974$7980_Y + attribute \src "libresoc.v:149492.17-149492.95" + wire $eq$libresoc.v:149492$8292_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:146964.7-146964.15" + attribute \src "libresoc.v:149482.7-149482.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:146974$7980 + cell $eq $eq$libresoc.v:149492$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -304954,24 +311413,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:146974$7980_Y + connect \Y $eq$libresoc.v:149492$8292_Y end - attribute \src "libresoc.v:146964.7-146964.20" - process $proc$libresoc.v:146964$7982 + attribute \src "libresoc.v:149482.7-149482.20" + process $proc$libresoc.v:149482$8294 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146975.3-146984.6" - process $proc$libresoc.v:146975$7981 + attribute \src "libresoc.v:149493.3-149502.6" + process $proc$libresoc.v:149493$8293 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:146976.5-146976.29" + attribute \src "libresoc.v:149494.5-149494.29" switch \initial - attribute \src "libresoc.v:146976.9-146976.17" + attribute \src "libresoc.v:149494.9-149494.17" case 1'1 case end @@ -304987,299 +311446,299 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:146974$7980_Y + connect \$1 $eq$libresoc.v:149492$8292_Y connect \n \$1 end -attribute \src "libresoc.v:146990.1-147804.10" +attribute \src "libresoc.v:149508.1-150322.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:147767.3-147782.6" + attribute \src "libresoc.v:150285.3-150300.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8072 - attribute \src "libresoc.v:147289.3-147290.57" + attribute \src "libresoc.v:150249.3-150284.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8384 + attribute \src "libresoc.v:149807.3-149808.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:147381.3-147389.6" - wire $0\busy_delay$next[0:0]$8040 - attribute \src "libresoc.v:147287.3-147288.37" + attribute \src "libresoc.v:149899.3-149907.6" + wire $0\busy_delay$next[0:0]$8352 + attribute \src "libresoc.v:149805.3-149806.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:147715.3-147730.6" + attribute \src "libresoc.v:150233.3-150248.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:147705.3-147714.6" + attribute \src "libresoc.v:150223.3-150232.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:147695.3-147704.6" + attribute \src "libresoc.v:150213.3-150222.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:147676.3-147685.6" + attribute \src "libresoc.v:150194.3-150203.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $0\fsm_state$next[1:0]$8058 - attribute \src "libresoc.v:147279.3-147280.35" + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $0\fsm_state$next[1:0]$8370 + attribute \src "libresoc.v:149797.3-149798.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:146991.7-146991.20" + attribute \src "libresoc.v:149509.7-149509.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147577.3-147586.6" + attribute \src "libresoc.v:150095.3-150104.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:147285.3-147286.35" + attribute \src "libresoc.v:149803.3-149804.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150028.3-150058.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147567.3-147576.6" + attribute \src "libresoc.v:150085.3-150094.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:147587.3-147596.6" + attribute \src "libresoc.v:150105.3-150114.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:147416.3-147431.6" + attribute \src "libresoc.v:149934.3-149949.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:147400.3-147415.6" + attribute \src "libresoc.v:149918.3-149933.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:147686.3-147694.6" - wire $0\lsui_active_dly$next[0:0]$8066 - attribute \src "libresoc.v:147277.3-147278.47" + attribute \src "libresoc.v:150204.3-150212.6" + wire $0\lsui_active_dly$next[0:0]$8378 + attribute \src "libresoc.v:149795.3-149796.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:147617.3-147636.6" + attribute \src "libresoc.v:150135.3-150154.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:147281.3-147282.36" + attribute \src "libresoc.v:149799.3-149800.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:147557.3-147566.6" + attribute \src "libresoc.v:150075.3-150084.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:147541.3-147556.6" + attribute \src "libresoc.v:150059.3-150074.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:147390.3-147399.6" + attribute \src "libresoc.v:149908.3-149917.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:147371.3-147380.6" + attribute \src "libresoc.v:149889.3-149898.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:147356.3-147370.6" - wire $0\st_done_s_st_done$next[0:0]$8035 - attribute \src "libresoc.v:147291.3-147292.51" + attribute \src "libresoc.v:149874.3-149888.6" + wire $0\st_done_s_st_done$next[0:0]$8347 + attribute \src "libresoc.v:149809.3-149810.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:147597.3-147606.6" + attribute \src "libresoc.v:150115.3-150124.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:147283.3-147284.35" + attribute \src "libresoc.v:149801.3-149802.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:147432.3-147457.6" + attribute \src "libresoc.v:149950.3-149975.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147484.3-147509.6" + attribute \src "libresoc.v:150002.3-150027.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:147458.3-147483.6" + attribute \src "libresoc.v:149976.3-150001.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:147607.3-147616.6" + attribute \src "libresoc.v:150125.3-150134.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:147767.3-147782.6" + attribute \src "libresoc.v:150285.3-150300.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8073 - attribute \src "libresoc.v:147085.7-147085.34" + attribute \src "libresoc.v:150249.3-150284.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8385 + attribute \src "libresoc.v:149603.7-149603.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:147381.3-147389.6" - wire $1\busy_delay$next[0:0]$8041 - attribute \src "libresoc.v:147089.7-147089.24" + attribute \src "libresoc.v:149899.3-149907.6" + wire $1\busy_delay$next[0:0]$8353 + attribute \src "libresoc.v:149607.7-149607.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:147715.3-147730.6" + attribute \src "libresoc.v:150233.3-150248.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:147705.3-147714.6" + attribute \src "libresoc.v:150223.3-150232.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:147695.3-147704.6" + attribute \src "libresoc.v:150213.3-150222.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:147676.3-147685.6" + attribute \src "libresoc.v:150194.3-150203.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $1\fsm_state$next[1:0]$8059 - attribute \src "libresoc.v:147111.13-147111.29" + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $1\fsm_state$next[1:0]$8371 + attribute \src "libresoc.v:149629.13-149629.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:147577.3-147586.6" + attribute \src "libresoc.v:150095.3-150104.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:147125.7-147125.21" + attribute \src "libresoc.v:149643.7-149643.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150028.3-150058.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147567.3-147576.6" + attribute \src "libresoc.v:150085.3-150094.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:147587.3-147596.6" + attribute \src "libresoc.v:150105.3-150114.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:147416.3-147431.6" + attribute \src "libresoc.v:149934.3-149949.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:147400.3-147415.6" + attribute \src "libresoc.v:149918.3-149933.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:147686.3-147694.6" - wire $1\lsui_active_dly$next[0:0]$8067 - attribute \src "libresoc.v:147168.7-147168.29" + attribute \src "libresoc.v:150204.3-150212.6" + wire $1\lsui_active_dly$next[0:0]$8379 + attribute \src "libresoc.v:149686.7-149686.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:147617.3-147636.6" + attribute \src "libresoc.v:150135.3-150154.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:147180.7-147180.25" + attribute \src "libresoc.v:149698.7-149698.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:147557.3-147566.6" + attribute \src "libresoc.v:150075.3-150084.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:147541.3-147556.6" + attribute \src "libresoc.v:150059.3-150074.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:147390.3-147399.6" + attribute \src "libresoc.v:149908.3-149917.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:147371.3-147380.6" + attribute \src "libresoc.v:149889.3-149898.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:147356.3-147370.6" - wire $1\st_done_s_st_done$next[0:0]$8036 - attribute \src "libresoc.v:147200.7-147200.31" + attribute \src "libresoc.v:149874.3-149888.6" + wire $1\st_done_s_st_done$next[0:0]$8348 + attribute \src "libresoc.v:149718.7-149718.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:147597.3-147606.6" + attribute \src "libresoc.v:150115.3-150124.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:147208.7-147208.21" + attribute \src "libresoc.v:149726.7-149726.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:147432.3-147457.6" + attribute \src "libresoc.v:149950.3-149975.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147484.3-147509.6" + attribute \src "libresoc.v:150002.3-150027.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:147458.3-147483.6" + attribute \src "libresoc.v:149976.3-150001.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:147607.3-147616.6" + attribute \src "libresoc.v:150125.3-150134.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:147767.3-147782.6" + attribute \src "libresoc.v:150285.3-150300.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8074 - attribute \src "libresoc.v:147715.3-147730.6" + attribute \src "libresoc.v:150249.3-150284.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8386 + attribute \src "libresoc.v:150233.3-150248.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $2\fsm_state$next[1:0]$8060 - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $2\fsm_state$next[1:0]$8372 + attribute \src "libresoc.v:150028.3-150058.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147416.3-147431.6" + attribute \src "libresoc.v:149934.3-149949.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:147400.3-147415.6" + attribute \src "libresoc.v:149918.3-149933.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:147617.3-147636.6" + attribute \src "libresoc.v:150135.3-150154.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:147541.3-147556.6" + attribute \src "libresoc.v:150059.3-150074.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:147356.3-147370.6" - wire $2\st_done_s_st_done$next[0:0]$8037 - attribute \src "libresoc.v:147432.3-147457.6" + attribute \src "libresoc.v:149874.3-149888.6" + wire $2\st_done_s_st_done$next[0:0]$8349 + attribute \src "libresoc.v:149950.3-149975.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147484.3-147509.6" + attribute \src "libresoc.v:150002.3-150027.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:147458.3-147483.6" + attribute \src "libresoc.v:149976.3-150001.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8075 - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $3\fsm_state$next[1:0]$8061 - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150249.3-150284.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8387 + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $3\fsm_state$next[1:0]$8373 + attribute \src "libresoc.v:150028.3-150058.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147432.3-147457.6" + attribute \src "libresoc.v:149950.3-149975.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147484.3-147509.6" + attribute \src "libresoc.v:150002.3-150027.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:147458.3-147483.6" + attribute \src "libresoc.v:149976.3-150001.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8076 - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $4\fsm_state$next[1:0]$8062 - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150249.3-150284.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8388 + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $4\fsm_state$next[1:0]$8374 + attribute \src "libresoc.v:150028.3-150058.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147432.3-147457.6" + attribute \src "libresoc.v:149950.3-149975.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147484.3-147509.6" + attribute \src "libresoc.v:150002.3-150027.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:147458.3-147483.6" + attribute \src "libresoc.v:149976.3-150001.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8077 - attribute \src "libresoc.v:147637.3-147675.6" - wire width 2 $5\fsm_state$next[1:0]$8063 - attribute \src "libresoc.v:147510.3-147540.6" + attribute \src "libresoc.v:150249.3-150284.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8389 + attribute \src "libresoc.v:150155.3-150193.6" + wire width 2 $5\fsm_state$next[1:0]$8375 + attribute \src "libresoc.v:150028.3-150058.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147731.3-147766.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8078 - attribute \src "libresoc.v:147237.18-147237.115" - wire $and$libresoc.v:147237$7984_Y - attribute \src "libresoc.v:147239.18-147239.95" - wire $and$libresoc.v:147239$7986_Y - attribute \src "libresoc.v:147241.17-147241.138" - wire $and$libresoc.v:147241$7988_Y - attribute \src "libresoc.v:147242.18-147242.95" - wire $and$libresoc.v:147242$7989_Y - attribute \src "libresoc.v:147245.18-147245.136" - wire $and$libresoc.v:147245$7994_Y - attribute \src "libresoc.v:147246.18-147246.136" - wire $and$libresoc.v:147246$7995_Y - attribute \src "libresoc.v:147247.18-147247.136" - wire $and$libresoc.v:147247$7996_Y - attribute \src "libresoc.v:147248.18-147248.136" - wire $and$libresoc.v:147248$7997_Y - attribute \src "libresoc.v:147249.18-147249.136" - wire $and$libresoc.v:147249$7998_Y - attribute \src "libresoc.v:147254.18-147254.119" - wire width 176 $and$libresoc.v:147254$8003_Y - attribute \src "libresoc.v:147257.18-147257.136" - wire $and$libresoc.v:147257$8006_Y - attribute \src "libresoc.v:147258.18-147258.136" - wire $and$libresoc.v:147258$8007_Y - attribute \src "libresoc.v:147260.18-147260.139" - wire $and$libresoc.v:147260$8009_Y - attribute \src "libresoc.v:147264.18-147264.139" - wire $and$libresoc.v:147264$8013_Y - attribute \src "libresoc.v:147266.18-147266.114" - wire $and$libresoc.v:147266$8015_Y - attribute \src "libresoc.v:147268.18-147268.114" - wire $and$libresoc.v:147268$8017_Y - attribute \src "libresoc.v:147272.18-147272.103" - wire $and$libresoc.v:147272$8021_Y - attribute \src "libresoc.v:147273.17-147273.135" - wire $and$libresoc.v:147273$8022_Y - attribute \src "libresoc.v:147276.18-147276.103" - wire $and$libresoc.v:147276$8025_Y - attribute \src "libresoc.v:147243.18-147243.109" - wire width 4 $extend$libresoc.v:147243$7990_Y - attribute \src "libresoc.v:147244.18-147244.109" - wire width 4 $extend$libresoc.v:147244$7992_Y - attribute \src "libresoc.v:147255.18-147255.112" - wire width 8 $mul$libresoc.v:147255$8004_Y - attribute \src "libresoc.v:147261.18-147261.112" - wire width 8 $mul$libresoc.v:147261$8010_Y - attribute \src "libresoc.v:147236.17-147236.103" - wire $not$libresoc.v:147236$7983_Y - attribute \src "libresoc.v:147238.18-147238.94" - wire $not$libresoc.v:147238$7985_Y - attribute \src "libresoc.v:147240.18-147240.94" - wire $not$libresoc.v:147240$7987_Y - attribute \src "libresoc.v:147250.18-147250.102" - wire $not$libresoc.v:147250$7999_Y - attribute \src "libresoc.v:147253.18-147253.97" - wire $not$libresoc.v:147253$8002_Y - attribute \src "libresoc.v:147259.18-147259.102" - wire $not$libresoc.v:147259$8008_Y - attribute \src "libresoc.v:147262.17-147262.103" - wire $not$libresoc.v:147262$8011_Y - attribute \src "libresoc.v:147269.18-147269.101" - wire $not$libresoc.v:147269$8018_Y - attribute \src "libresoc.v:147270.18-147270.111" - wire $not$libresoc.v:147270$8019_Y - attribute \src "libresoc.v:147271.18-147271.110" - wire $not$libresoc.v:147271$8020_Y - attribute \src "libresoc.v:147274.18-147274.102" - wire $not$libresoc.v:147274$8023_Y - attribute \src "libresoc.v:147275.18-147275.102" - wire $not$libresoc.v:147275$8024_Y - attribute \src "libresoc.v:147251.18-147251.111" - wire $or$libresoc.v:147251$8000_Y - attribute \src "libresoc.v:147252.17-147252.130" - wire $or$libresoc.v:147252$8001_Y - attribute \src "libresoc.v:147265.18-147265.130" - wire $or$libresoc.v:147265$8014_Y - attribute \src "libresoc.v:147267.18-147267.130" - wire $or$libresoc.v:147267$8016_Y - attribute \src "libresoc.v:147243.18-147243.109" - wire width 4 $pos$libresoc.v:147243$7991_Y - attribute \src "libresoc.v:147244.18-147244.109" - wire width 4 $pos$libresoc.v:147244$7993_Y - attribute \src "libresoc.v:147263.18-147263.121" - wire width 319 $sshl$libresoc.v:147263$8012_Y - attribute \src "libresoc.v:147256.18-147256.106" - wire width 176 $sshr$libresoc.v:147256$8005_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "libresoc.v:150249.3-150284.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8390 + attribute \src "libresoc.v:149755.18-149755.115" + wire $and$libresoc.v:149755$8296_Y + attribute \src "libresoc.v:149757.18-149757.95" + wire $and$libresoc.v:149757$8298_Y + attribute \src "libresoc.v:149759.17-149759.138" + wire $and$libresoc.v:149759$8300_Y + attribute \src "libresoc.v:149760.18-149760.95" + wire $and$libresoc.v:149760$8301_Y + attribute \src "libresoc.v:149763.18-149763.136" + wire $and$libresoc.v:149763$8306_Y + attribute \src "libresoc.v:149764.18-149764.136" + wire $and$libresoc.v:149764$8307_Y + attribute \src "libresoc.v:149765.18-149765.136" + wire $and$libresoc.v:149765$8308_Y + attribute \src "libresoc.v:149766.18-149766.136" + wire $and$libresoc.v:149766$8309_Y + attribute \src "libresoc.v:149767.18-149767.136" + wire $and$libresoc.v:149767$8310_Y + attribute \src "libresoc.v:149772.18-149772.119" + wire width 176 $and$libresoc.v:149772$8315_Y + attribute \src "libresoc.v:149775.18-149775.136" + wire $and$libresoc.v:149775$8318_Y + attribute \src "libresoc.v:149776.18-149776.136" + wire $and$libresoc.v:149776$8319_Y + attribute \src "libresoc.v:149778.18-149778.139" + wire $and$libresoc.v:149778$8321_Y + attribute \src "libresoc.v:149782.18-149782.139" + wire $and$libresoc.v:149782$8325_Y + attribute \src "libresoc.v:149784.18-149784.114" + wire $and$libresoc.v:149784$8327_Y + attribute \src "libresoc.v:149786.18-149786.114" + wire $and$libresoc.v:149786$8329_Y + attribute \src "libresoc.v:149790.18-149790.103" + wire $and$libresoc.v:149790$8333_Y + attribute \src "libresoc.v:149791.17-149791.135" + wire $and$libresoc.v:149791$8334_Y + attribute \src "libresoc.v:149794.18-149794.103" + wire $and$libresoc.v:149794$8337_Y + attribute \src "libresoc.v:149761.18-149761.109" + wire width 4 $extend$libresoc.v:149761$8302_Y + attribute \src "libresoc.v:149762.18-149762.109" + wire width 4 $extend$libresoc.v:149762$8304_Y + attribute \src "libresoc.v:149773.18-149773.112" + wire width 8 $mul$libresoc.v:149773$8316_Y + attribute \src "libresoc.v:149779.18-149779.112" + wire width 8 $mul$libresoc.v:149779$8322_Y + attribute \src "libresoc.v:149754.17-149754.103" + wire $not$libresoc.v:149754$8295_Y + attribute \src "libresoc.v:149756.18-149756.94" + wire $not$libresoc.v:149756$8297_Y + attribute \src "libresoc.v:149758.18-149758.94" + wire $not$libresoc.v:149758$8299_Y + attribute \src "libresoc.v:149768.18-149768.102" + wire $not$libresoc.v:149768$8311_Y + attribute \src "libresoc.v:149771.18-149771.97" + wire $not$libresoc.v:149771$8314_Y + attribute \src "libresoc.v:149777.18-149777.102" + wire $not$libresoc.v:149777$8320_Y + attribute \src "libresoc.v:149780.17-149780.103" + wire $not$libresoc.v:149780$8323_Y + attribute \src "libresoc.v:149787.18-149787.101" + wire $not$libresoc.v:149787$8330_Y + attribute \src "libresoc.v:149788.18-149788.111" + wire $not$libresoc.v:149788$8331_Y + attribute \src "libresoc.v:149789.18-149789.110" + wire $not$libresoc.v:149789$8332_Y + attribute \src "libresoc.v:149792.18-149792.102" + wire $not$libresoc.v:149792$8335_Y + attribute \src "libresoc.v:149793.18-149793.102" + wire $not$libresoc.v:149793$8336_Y + attribute \src "libresoc.v:149769.18-149769.111" + wire $or$libresoc.v:149769$8312_Y + attribute \src "libresoc.v:149770.17-149770.130" + wire $or$libresoc.v:149770$8313_Y + attribute \src "libresoc.v:149783.18-149783.130" + wire $or$libresoc.v:149783$8326_Y + attribute \src "libresoc.v:149785.18-149785.130" + wire $or$libresoc.v:149785$8328_Y + attribute \src "libresoc.v:149761.18-149761.109" + wire width 4 $pos$libresoc.v:149761$8303_Y + attribute \src "libresoc.v:149762.18-149762.109" + wire width 4 $pos$libresoc.v:149762$8305_Y + attribute \src "libresoc.v:149781.18-149781.121" + wire width 319 $sshl$libresoc.v:149781$8324_Y + attribute \src "libresoc.v:149774.18-149774.106" + wire width 176 $sshr$libresoc.v:149774$8317_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" wire \$13 @@ -305293,17 +311752,17 @@ module \pimem wire width 4 \$21 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 4 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" wire \$35 @@ -305311,31 +311770,31 @@ module \pimem wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 176 \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" wire width 176 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 8 \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" wire width 176 \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 319 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 8 \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" wire width 319 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$63 @@ -305345,7 +311804,7 @@ module \pimem wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" wire \$71 @@ -305361,7 +311820,7 @@ module \pimem wire \$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" wire \$9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \adrok_l_q_addr_acked @@ -305373,11 +311832,11 @@ module \pimem wire \adrok_l_s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \adrok_l_s_addr_acked$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" wire \busy_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" wire \busy_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" wire \busy_edge attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \busy_l_q_busy @@ -305385,9 +311844,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \cyc_l_q_cyc @@ -305399,7 +311858,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:146991.7-146991.15" + attribute \src "libresoc.v:149509.7-149509.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \ld_active_q_ld_active @@ -305407,9 +311866,9 @@ module \pimem wire \ld_active_r_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" wire \lds attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire \lds_dly @@ -305417,11 +311876,9 @@ module \pimem wire \lds_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \lds_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire input 18 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 7 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" wire output 10 \ldst_port0_addr_ok_o @@ -305429,17 +311886,19 @@ module \pimem wire output 4 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 18 \ldst_port0_exc_$signal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" wire input 2 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" wire input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 14 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" wire width 4 \lenexp_addr_i @@ -305459,13 +311918,13 @@ module \pimem wire \lsui_active_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" wire \lsui_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" wire width 64 input 11 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" wire output 21 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" wire \reset_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \reset_l_q_reset @@ -305487,9 +311946,9 @@ module \pimem wire \st_done_s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \st_done_s_st_done$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" wire width 64 \stdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" wire \sts attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire \sts_dly @@ -305503,22 +311962,22 @@ module \pimem wire \valid_l_r_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" wire width 48 output 9 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" wire input 17 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" wire output 19 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" wire width 8 output 8 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" wire width 64 output 16 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" wire output 20 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - cell $and $and$libresoc.v:147237$7984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $and$libresoc.v:149755$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305526,10 +311985,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:147237$7984_Y + connect \Y $and$libresoc.v:149755$8296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:147239$7986 + cell $and $and$libresoc.v:149757$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305537,10 +311996,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:147239$7986_Y + connect \Y $and$libresoc.v:149757$8298_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - cell $and $and$libresoc.v:147241$7988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149759$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305548,10 +312007,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:147241$7988_Y + connect \Y $and$libresoc.v:149759$8300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:147242$7989 + cell $and $and$libresoc.v:149760$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305559,10 +312018,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:147242$7989_Y + connect \Y $and$libresoc.v:149760$8301_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$libresoc.v:147245$7994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149763$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305570,10 +312029,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:147245$7994_Y + connect \Y $and$libresoc.v:149763$8306_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$libresoc.v:147246$7995 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149764$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305581,10 +312040,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:147246$7995_Y + connect \Y $and$libresoc.v:149764$8307_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$libresoc.v:147247$7996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149765$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305592,10 +312051,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:147247$7996_Y + connect \Y $and$libresoc.v:149765$8308_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$libresoc.v:147248$7997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149766$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305603,10 +312062,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:147248$7997_Y + connect \Y $and$libresoc.v:149766$8309_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $and $and$libresoc.v:147249$7998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149767$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305614,10 +312073,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:147249$7998_Y + connect \Y $and$libresoc.v:149767$8310_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" - cell $and $and$libresoc.v:147254$8003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" + cell $and $and$libresoc.v:149772$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -305625,10 +312084,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:147254$8003_Y + connect \Y $and$libresoc.v:149772$8315_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $and $and$libresoc.v:147257$8006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149775$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305636,10 +312095,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:147257$8006_Y + connect \Y $and$libresoc.v:149775$8318_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $and $and$libresoc.v:147258$8007 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + cell $and $and$libresoc.v:149776$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305647,10 +312106,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:147258$8007_Y + connect \Y $and$libresoc.v:149776$8319_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - cell $and $and$libresoc.v:147260$8009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149778$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305658,10 +312117,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:147260$8009_Y + connect \Y $and$libresoc.v:149778$8321_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" - cell $and $and$libresoc.v:147264$8013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:149782$8325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305669,10 +312128,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:147264$8013_Y + connect \Y $and$libresoc.v:149782$8325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:147266$8015 + cell $and $and$libresoc.v:149784$8327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305680,10 +312139,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:147266$8015_Y + connect \Y $and$libresoc.v:149784$8327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:147268$8017 + cell $and $and$libresoc.v:149786$8329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305691,10 +312150,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:147268$8017_Y + connect \Y $and$libresoc.v:149786$8329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:147272$8021 + cell $and $and$libresoc.v:149790$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305702,10 +312161,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:147272$8021_Y + connect \Y $and$libresoc.v:149790$8333_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - cell $and $and$libresoc.v:147273$8022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:149791$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305713,10 +312172,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:147273$8022_Y + connect \Y $and$libresoc.v:149791$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:147276$8025 + cell $and $and$libresoc.v:149794$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305724,26 +312183,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:147276$8025_Y + connect \Y $and$libresoc.v:149794$8337_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147243$7990 + cell $pos $extend$libresoc.v:149761$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:147243$7990_Y + connect \Y $extend$libresoc.v:149761$8302_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:147244$7992 + cell $pos $extend$libresoc.v:149762$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:147244$7992_Y + connect \Y $extend$libresoc.v:149762$8304_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - cell $mul $mul$libresoc.v:147255$8004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $mul $mul$libresoc.v:149773$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305751,10 +312210,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:147255$8004_Y + connect \Y $mul$libresoc.v:149773$8316_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" - cell $mul $mul$libresoc.v:147261$8010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $mul $mul$libresoc.v:149779$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305762,106 +312221,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:147261$8010_Y + connect \Y $mul$libresoc.v:149779$8322_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - cell $not $not$libresoc.v:147236$7983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $not $not$libresoc.v:149754$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:147236$7983_Y + connect \Y $not$libresoc.v:149754$8295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:147238$7985 + cell $not $not$libresoc.v:149756$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:147238$7985_Y + connect \Y $not$libresoc.v:149756$8297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:147240$7987 + cell $not $not$libresoc.v:149758$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:147240$7987_Y + connect \Y $not$libresoc.v:149758$8299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:147250$7999 + cell $not $not$libresoc.v:149768$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:147250$7999_Y + connect \Y $not$libresoc.v:149768$8311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:147253$8002 + cell $not $not$libresoc.v:149771$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:147253$8002_Y + connect \Y $not$libresoc.v:149771$8314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:147259$8008 + cell $not $not$libresoc.v:149777$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:147259$8008_Y + connect \Y $not$libresoc.v:149777$8320_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" - cell $not $not$libresoc.v:147262$8011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + cell $not $not$libresoc.v:149780$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:147262$8011_Y + connect \Y $not$libresoc.v:149780$8323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:147269$8018 + cell $not $not$libresoc.v:149787$8330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:147269$8018_Y + connect \Y $not$libresoc.v:149787$8330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:147270$8019 + cell $not $not$libresoc.v:149788$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:147270$8019_Y + connect \Y $not$libresoc.v:149788$8331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:147271$8020 + cell $not $not$libresoc.v:149789$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:147271$8020_Y + connect \Y $not$libresoc.v:149789$8332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:147274$8023 + cell $not $not$libresoc.v:149792$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:147274$8023_Y + connect \Y $not$libresoc.v:149792$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:147275$8024 + cell $not $not$libresoc.v:149793$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:147275$8024_Y + connect \Y $not$libresoc.v:149793$8336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:147251$8000 + cell $or $or$libresoc.v:149769$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305869,10 +312328,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:147251$8000_Y + connect \Y $or$libresoc.v:149769$8312_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" - cell $or $or$libresoc.v:147252$8001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + cell $or $or$libresoc.v:149770$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305880,10 +312339,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:147252$8001_Y + connect \Y $or$libresoc.v:149770$8313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:147265$8014 + cell $or $or$libresoc.v:149783$8326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305891,10 +312350,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:147265$8014_Y + connect \Y $or$libresoc.v:149783$8326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:147267$8016 + cell $or $or$libresoc.v:149785$8328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305902,26 +312361,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:147267$8016_Y + connect \Y $or$libresoc.v:149785$8328_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147243$7991 + cell $pos $pos$libresoc.v:149761$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:147243$7990_Y - connect \Y $pos$libresoc.v:147243$7991_Y + connect \A $extend$libresoc.v:149761$8302_Y + connect \Y $pos$libresoc.v:149761$8303_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:147244$7993 + cell $pos $pos$libresoc.v:149762$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:147244$7992_Y - connect \Y $pos$libresoc.v:147244$7993_Y + connect \A $extend$libresoc.v:149762$8304_Y + connect \Y $pos$libresoc.v:149762$8305_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" - cell $sshl $sshl$libresoc.v:147263$8012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $sshl $sshl$libresoc.v:149781$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -305929,10 +312388,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:147263$8012_Y + connect \Y $sshl$libresoc.v:149781$8324_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - cell $sshr $sshr$libresoc.v:147256$8005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $sshr $sshr$libresoc.v:149774$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -305940,10 +312399,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:147256$8005_Y + connect \Y $sshr$libresoc.v:149774$8317_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:147293.11-147300.4" + attribute \src "libresoc.v:149811.11-149818.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -305953,7 +312412,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:147301.10-147307.4" + attribute \src "libresoc.v:149819.10-149825.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -305962,7 +312421,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:147308.9-147314.4" + attribute \src "libresoc.v:149826.9-149832.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -305971,7 +312430,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:147315.13-147321.4" + attribute \src "libresoc.v:149833.13-149839.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -305980,7 +312439,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:147322.10-147327.4" + attribute \src "libresoc.v:149840.10-149845.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -305988,7 +312447,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:147328.11-147334.4" + attribute \src "libresoc.v:149846.11-149852.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -305997,7 +312456,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:147335.13-147341.4" + attribute \src "libresoc.v:149853.13-149859.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -306006,7 +312465,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:147342.11-147348.4" + attribute \src "libresoc.v:149860.11-149866.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -306015,7 +312474,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:147349.11-147355.4" + attribute \src "libresoc.v:149867.11-149873.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -306023,179 +312482,179 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:146991.7-146991.20" - process $proc$libresoc.v:146991$8080 + attribute \src "libresoc.v:149509.7-149509.20" + process $proc$libresoc.v:149509$8392 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147085.7-147085.34" - process $proc$libresoc.v:147085$8081 + attribute \src "libresoc.v:149603.7-149603.34" + process $proc$libresoc.v:149603$8393 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:147089.7-147089.24" - process $proc$libresoc.v:147089$8082 + attribute \src "libresoc.v:149607.7-149607.24" + process $proc$libresoc.v:149607$8394 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:147111.13-147111.29" - process $proc$libresoc.v:147111$8083 + attribute \src "libresoc.v:149629.13-149629.29" + process $proc$libresoc.v:149629$8395 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:147125.7-147125.21" - process $proc$libresoc.v:147125$8084 + attribute \src "libresoc.v:149643.7-149643.21" + process $proc$libresoc.v:149643$8396 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:147168.7-147168.29" - process $proc$libresoc.v:147168$8085 + attribute \src "libresoc.v:149686.7-149686.29" + process $proc$libresoc.v:149686$8397 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:147180.7-147180.25" - process $proc$libresoc.v:147180$8086 + attribute \src "libresoc.v:149698.7-149698.25" + process $proc$libresoc.v:149698$8398 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:147200.7-147200.31" - process $proc$libresoc.v:147200$8087 + attribute \src "libresoc.v:149718.7-149718.31" + process $proc$libresoc.v:149718$8399 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:147208.7-147208.21" - process $proc$libresoc.v:147208$8088 + attribute \src "libresoc.v:149726.7-149726.21" + process $proc$libresoc.v:149726$8400 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:147277.3-147278.47" - process $proc$libresoc.v:147277$8026 + attribute \src "libresoc.v:149795.3-149796.47" + process $proc$libresoc.v:149795$8338 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:147279.3-147280.35" - process $proc$libresoc.v:147279$8027 + attribute \src "libresoc.v:149797.3-149798.35" + process $proc$libresoc.v:149797$8339 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:147281.3-147282.36" - process $proc$libresoc.v:147281$8028 + attribute \src "libresoc.v:149799.3-149800.36" + process $proc$libresoc.v:149799$8340 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:147283.3-147284.35" - process $proc$libresoc.v:147283$8029 + attribute \src "libresoc.v:149801.3-149802.35" + process $proc$libresoc.v:149801$8341 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:147285.3-147286.35" - process $proc$libresoc.v:147285$8030 + attribute \src "libresoc.v:149803.3-149804.35" + process $proc$libresoc.v:149803$8342 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:147287.3-147288.37" - process $proc$libresoc.v:147287$8031 + attribute \src "libresoc.v:149805.3-149806.37" + process $proc$libresoc.v:149805$8343 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:147289.3-147290.57" - process $proc$libresoc.v:147289$8032 + attribute \src "libresoc.v:149807.3-149808.57" + process $proc$libresoc.v:149807$8344 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:147291.3-147292.51" - process $proc$libresoc.v:147291$8033 + attribute \src "libresoc.v:149809.3-149810.51" + process $proc$libresoc.v:149809$8345 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:147356.3-147370.6" - process $proc$libresoc.v:147356$8034 + attribute \src "libresoc.v:149874.3-149888.6" + process $proc$libresoc.v:149874$8346 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8035 $2\st_done_s_st_done$next[0:0]$8037 - attribute \src "libresoc.v:147357.5-147357.29" + assign $0\st_done_s_st_done$next[0:0]$8347 $2\st_done_s_st_done$next[0:0]$8349 + attribute \src "libresoc.v:149875.5-149875.29" switch \initial - attribute \src "libresoc.v:147357.9-147357.17" + attribute \src "libresoc.v:149875.9-149875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8036 1'1 + assign $1\st_done_s_st_done$next[0:0]$8348 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8036 1'0 + assign $1\st_done_s_st_done$next[0:0]$8348 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8037 1'0 + assign $2\st_done_s_st_done$next[0:0]$8349 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8037 $1\st_done_s_st_done$next[0:0]$8036 + assign $2\st_done_s_st_done$next[0:0]$8349 $1\st_done_s_st_done$next[0:0]$8348 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8035 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8347 end - attribute \src "libresoc.v:147371.3-147380.6" - process $proc$libresoc.v:147371$8038 + attribute \src "libresoc.v:149889.3-149898.6" + process $proc$libresoc.v:149889$8350 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:147372.5-147372.29" + attribute \src "libresoc.v:149890.5-149890.29" switch \initial - attribute \src "libresoc.v:147372.9-147372.17" + attribute \src "libresoc.v:149890.9-149890.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306207,14 +312666,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:147381.3-147389.6" - process $proc$libresoc.v:147381$8039 + attribute \src "libresoc.v:149899.3-149907.6" + process $proc$libresoc.v:149899$8351 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8040 $1\busy_delay$next[0:0]$8041 - attribute \src "libresoc.v:147382.5-147382.29" + assign $0\busy_delay$next[0:0]$8352 $1\busy_delay$next[0:0]$8353 + attribute \src "libresoc.v:149900.5-149900.29" switch \initial - attribute \src "libresoc.v:147382.9-147382.17" + attribute \src "libresoc.v:149900.9-149900.17" case 1'1 case end @@ -306223,25 +312682,25 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8041 1'0 + assign $1\busy_delay$next[0:0]$8353 1'0 case - assign $1\busy_delay$next[0:0]$8041 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8353 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8040 + update \busy_delay$next $0\busy_delay$next[0:0]$8352 end - attribute \src "libresoc.v:147390.3-147399.6" - process $proc$libresoc.v:147390$8042 + attribute \src "libresoc.v:149908.3-149917.6" + process $proc$libresoc.v:149908$8354 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:147391.5-147391.29" + attribute \src "libresoc.v:149909.5-149909.29" switch \initial - attribute \src "libresoc.v:147391.9-147391.17" + attribute \src "libresoc.v:149909.9-149909.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306253,19 +312712,19 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:147400.3-147415.6" - process $proc$libresoc.v:147400$8043 + attribute \src "libresoc.v:149918.3-149933.6" + process $proc$libresoc.v:149918$8355 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:147401.5-147401.29" + attribute \src "libresoc.v:149919.5-149919.29" switch \initial - attribute \src "libresoc.v:147401.9-147401.17" + attribute \src "libresoc.v:149919.9-149919.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306274,7 +312733,7 @@ module \pimem case assign $1\lenexp_len_i[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306286,19 +312745,19 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:147416.3-147431.6" - process $proc$libresoc.v:147416$8044 + attribute \src "libresoc.v:149934.3-149949.6" + process $proc$libresoc.v:149934$8356 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:147417.5-147417.29" + attribute \src "libresoc.v:149935.5-149935.29" switch \initial - attribute \src "libresoc.v:147417.9-147417.17" + attribute \src "libresoc.v:149935.9-149935.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306307,7 +312766,7 @@ module \pimem case assign $1\lenexp_addr_i[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306319,25 +312778,25 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:147432.3-147457.6" - process $proc$libresoc.v:147432$8045 + attribute \src "libresoc.v:149950.3-149975.6" + process $proc$libresoc.v:149950$8357 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:147433.5-147433.29" + attribute \src "libresoc.v:149951.5-149951.29" switch \initial - attribute \src "libresoc.v:147433.9-147433.17" + attribute \src "libresoc.v:149951.9-149951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306349,13 +312808,13 @@ module \pimem case assign $1\valid_l_s_valid[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306370,25 +312829,25 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:147458.3-147483.6" - process $proc$libresoc.v:147458$8046 + attribute \src "libresoc.v:149976.3-150001.6" + process $proc$libresoc.v:149976$8358 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:147459.5-147459.29" + attribute \src "libresoc.v:149977.5-149977.29" switch \initial - attribute \src "libresoc.v:147459.9-147459.17" + attribute \src "libresoc.v:149977.9-149977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306400,13 +312859,13 @@ module \pimem case assign $1\x_mask_i[7:0] 8'00000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306421,25 +312880,25 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:147484.3-147509.6" - process $proc$libresoc.v:147484$8047 + attribute \src "libresoc.v:150002.3-150027.6" + process $proc$libresoc.v:150002$8359 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:147485.5-147485.29" + attribute \src "libresoc.v:150003.5-150003.29" switch \initial - attribute \src "libresoc.v:147485.9-147485.17" + attribute \src "libresoc.v:150003.9-150003.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306451,13 +312910,13 @@ module \pimem case assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306472,25 +312931,25 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:147510.3-147540.6" - process $proc$libresoc.v:147510$8048 + attribute \src "libresoc.v:150028.3-150058.6" + process $proc$libresoc.v:150028$8360 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:147511.5-147511.29" + attribute \src "libresoc.v:150029.5-150029.29" switch \initial - attribute \src "libresoc.v:147511.9-147511.17" + attribute \src "libresoc.v:150029.9-150029.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$31 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306502,19 +312961,19 @@ module \pimem case assign $1\ldst_port0_addr_ok_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306532,19 +312991,19 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:147541.3-147556.6" - process $proc$libresoc.v:147541$8049 + attribute \src "libresoc.v:150059.3-150074.6" + process $proc$libresoc.v:150059$8361 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:147542.5-147542.29" + attribute \src "libresoc.v:150060.5-150060.29" switch \initial - attribute \src "libresoc.v:147542.9-147542.17" + attribute \src "libresoc.v:150060.9-150060.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306553,7 +313012,7 @@ module \pimem case assign $1\reset_l_s_reset[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" switch \st_done_q_st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306565,18 +313024,18 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:147557.3-147566.6" - process $proc$libresoc.v:147557$8050 + attribute \src "libresoc.v:150075.3-150084.6" + process $proc$libresoc.v:150075$8362 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:147558.5-147558.29" + attribute \src "libresoc.v:150076.5-150076.29" switch \initial - attribute \src "libresoc.v:147558.9-147558.17" + attribute \src "libresoc.v:150076.9-150076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306588,18 +313047,18 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:147567.3-147576.6" - process $proc$libresoc.v:147567$8051 + attribute \src "libresoc.v:150085.3-150094.6" + process $proc$libresoc.v:150085$8363 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:147568.5-147568.29" + attribute \src "libresoc.v:150086.5-150086.29" switch \initial - attribute \src "libresoc.v:147568.9-147568.17" + attribute \src "libresoc.v:150086.9-150086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306611,18 +313070,18 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:147577.3-147586.6" - process $proc$libresoc.v:147577$8052 + attribute \src "libresoc.v:150095.3-150104.6" + process $proc$libresoc.v:150095$8364 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:147578.5-147578.29" + attribute \src "libresoc.v:150096.5-150096.29" switch \initial - attribute \src "libresoc.v:147578.9-147578.17" + attribute \src "libresoc.v:150096.9-150096.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306634,18 +313093,18 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:147587.3-147596.6" - process $proc$libresoc.v:147587$8053 + attribute \src "libresoc.v:150105.3-150114.6" + process $proc$libresoc.v:150105$8365 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:147588.5-147588.29" + attribute \src "libresoc.v:150106.5-150106.29" switch \initial - attribute \src "libresoc.v:147588.9-147588.17" + attribute \src "libresoc.v:150106.9-150106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" switch \$50 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306657,18 +313116,18 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:147597.3-147606.6" - process $proc$libresoc.v:147597$8054 + attribute \src "libresoc.v:150115.3-150124.6" + process $proc$libresoc.v:150115$8366 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:147598.5-147598.29" + attribute \src "libresoc.v:150116.5-150116.29" switch \initial - attribute \src "libresoc.v:147598.9-147598.17" + attribute \src "libresoc.v:150116.9-150116.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306680,18 +313139,18 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:147607.3-147616.6" - process $proc$libresoc.v:147607$8055 + attribute \src "libresoc.v:150125.3-150134.6" + process $proc$libresoc.v:150125$8367 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:147608.5-147608.29" + attribute \src "libresoc.v:150126.5-150126.29" switch \initial - attribute \src "libresoc.v:147608.9-147608.17" + attribute \src "libresoc.v:150126.9-150126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306703,14 +313162,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:147617.3-147636.6" - process $proc$libresoc.v:147617$8056 + attribute \src "libresoc.v:150135.3-150154.6" + process $proc$libresoc.v:150135$8368 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:147618.5-147618.29" + attribute \src "libresoc.v:150136.5-150136.29" switch \initial - attribute \src "libresoc.v:147618.9-147618.17" + attribute \src "libresoc.v:150136.9-150136.17" case 1'1 case end @@ -306739,15 +313198,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:147637.3-147675.6" - process $proc$libresoc.v:147637$8057 + attribute \src "libresoc.v:150155.3-150193.6" + process $proc$libresoc.v:150155$8369 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8058 $5\fsm_state$next[1:0]$8063 - attribute \src "libresoc.v:147638.5-147638.29" + assign $0\fsm_state$next[1:0]$8370 $5\fsm_state$next[1:0]$8375 + attribute \src "libresoc.v:150156.5-150156.29" switch \initial - attribute \src "libresoc.v:147638.9-147638.17" + attribute \src "libresoc.v:150156.9-150156.17" case 1'1 case end @@ -306756,69 +313215,69 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8059 $2\fsm_state$next[1:0]$8060 + assign $1\fsm_state$next[1:0]$8371 $2\fsm_state$next[1:0]$8372 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8060 2'01 + assign $2\fsm_state$next[1:0]$8372 2'01 case - assign $2\fsm_state$next[1:0]$8060 \fsm_state + assign $2\fsm_state$next[1:0]$8372 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8059 $3\fsm_state$next[1:0]$8061 + assign $1\fsm_state$next[1:0]$8371 $3\fsm_state$next[1:0]$8373 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8061 2'10 + assign $3\fsm_state$next[1:0]$8373 2'10 case - assign $3\fsm_state$next[1:0]$8061 \fsm_state + assign $3\fsm_state$next[1:0]$8373 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8059 $4\fsm_state$next[1:0]$8062 + assign $1\fsm_state$next[1:0]$8371 $4\fsm_state$next[1:0]$8374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8062 2'00 + assign $4\fsm_state$next[1:0]$8374 2'00 case - assign $4\fsm_state$next[1:0]$8062 \fsm_state + assign $4\fsm_state$next[1:0]$8374 \fsm_state end case - assign $1\fsm_state$next[1:0]$8059 \fsm_state + assign $1\fsm_state$next[1:0]$8371 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8063 2'00 + assign $5\fsm_state$next[1:0]$8375 2'00 case - assign $5\fsm_state$next[1:0]$8063 $1\fsm_state$next[1:0]$8059 + assign $5\fsm_state$next[1:0]$8375 $1\fsm_state$next[1:0]$8371 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8058 + update \fsm_state$next $0\fsm_state$next[1:0]$8370 end - attribute \src "libresoc.v:147676.3-147685.6" - process $proc$libresoc.v:147676$8064 + attribute \src "libresoc.v:150194.3-150203.6" + process $proc$libresoc.v:150194$8376 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:147677.5-147677.29" + attribute \src "libresoc.v:150195.5-150195.29" switch \initial - attribute \src "libresoc.v:147677.9-147677.17" + attribute \src "libresoc.v:150195.9-150195.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:288" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" switch \reset_l_s_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306830,14 +313289,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:147686.3-147694.6" - process $proc$libresoc.v:147686$8065 + attribute \src "libresoc.v:150204.3-150212.6" + process $proc$libresoc.v:150204$8377 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8066 $1\lsui_active_dly$next[0:0]$8067 - attribute \src "libresoc.v:147687.5-147687.29" + assign $0\lsui_active_dly$next[0:0]$8378 $1\lsui_active_dly$next[0:0]$8379 + attribute \src "libresoc.v:150205.5-150205.29" switch \initial - attribute \src "libresoc.v:147687.9-147687.17" + attribute \src "libresoc.v:150205.9-150205.17" case 1'1 case end @@ -306846,25 +313305,25 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8067 1'0 + assign $1\lsui_active_dly$next[0:0]$8379 1'0 case - assign $1\lsui_active_dly$next[0:0]$8067 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8379 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8066 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8378 end - attribute \src "libresoc.v:147695.3-147704.6" - process $proc$libresoc.v:147695$8068 + attribute \src "libresoc.v:150213.3-150222.6" + process $proc$libresoc.v:150213$8380 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:147696.5-147696.29" + attribute \src "libresoc.v:150214.5-150214.29" switch \initial - attribute \src "libresoc.v:147696.9-147696.17" + attribute \src "libresoc.v:150214.9-150214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306876,18 +313335,18 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:147705.3-147714.6" - process $proc$libresoc.v:147705$8069 + attribute \src "libresoc.v:150223.3-150232.6" + process $proc$libresoc.v:150223$8381 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:147706.5-147706.29" + attribute \src "libresoc.v:150224.5-150224.29" switch \initial - attribute \src "libresoc.v:147706.9-147706.17" + attribute \src "libresoc.v:150224.9-150224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306899,20 +313358,20 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:147715.3-147730.6" - process $proc$libresoc.v:147715$8070 + attribute \src "libresoc.v:150233.3-150248.6" + process $proc$libresoc.v:150233$8382 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:147716.5-147716.29" + attribute \src "libresoc.v:150234.5-150234.29" switch \initial - attribute \src "libresoc.v:147716.9-147716.17" + attribute \src "libresoc.v:150234.9-150234.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:283" - switch \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -306920,7 +313379,7 @@ module \pimem case assign $1\busy_l_r_busy[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -306932,89 +313391,89 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:147731.3-147766.6" - process $proc$libresoc.v:147731$8071 + attribute \src "libresoc.v:150249.3-150284.6" + process $proc$libresoc.v:150249$8383 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8072 $6\adrok_l_s_addr_acked$next[0:0]$8078 - attribute \src "libresoc.v:147732.5-147732.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8384 $6\adrok_l_s_addr_acked$next[0:0]$8390 + attribute \src "libresoc.v:150250.5-150250.29" switch \initial - attribute \src "libresoc.v:147732.9-147732.17" + attribute \src "libresoc.v:150250.9-150250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8073 $2\adrok_l_s_addr_acked$next[0:0]$8074 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + assign $1\adrok_l_s_addr_acked$next[0:0]$8385 $2\adrok_l_s_addr_acked$next[0:0]$8386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8074 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8386 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8074 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8386 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8073 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8385 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8075 $4\adrok_l_s_addr_acked$next[0:0]$8076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + assign $3\adrok_l_s_addr_acked$next[0:0]$8387 $4\adrok_l_s_addr_acked$next[0:0]$8388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8076 $5\adrok_l_s_addr_acked$next[0:0]$8077 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + assign $4\adrok_l_s_addr_acked$next[0:0]$8388 $5\adrok_l_s_addr_acked$next[0:0]$8389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8077 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8389 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8077 $1\adrok_l_s_addr_acked$next[0:0]$8073 + assign $5\adrok_l_s_addr_acked$next[0:0]$8389 $1\adrok_l_s_addr_acked$next[0:0]$8385 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8076 $1\adrok_l_s_addr_acked$next[0:0]$8073 + assign $4\adrok_l_s_addr_acked$next[0:0]$8388 $1\adrok_l_s_addr_acked$next[0:0]$8385 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8075 $1\adrok_l_s_addr_acked$next[0:0]$8073 + assign $3\adrok_l_s_addr_acked$next[0:0]$8387 $1\adrok_l_s_addr_acked$next[0:0]$8385 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8078 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8390 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8078 $3\adrok_l_s_addr_acked$next[0:0]$8075 + assign $6\adrok_l_s_addr_acked$next[0:0]$8390 $3\adrok_l_s_addr_acked$next[0:0]$8387 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8072 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8384 end - attribute \src "libresoc.v:147767.3-147782.6" - process $proc$libresoc.v:147767$8079 + attribute \src "libresoc.v:150285.3-150300.6" + process $proc$libresoc.v:150285$8391 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:147768.5-147768.29" + attribute \src "libresoc.v:150286.5-150286.29" switch \initial - attribute \src "libresoc.v:147768.9-147768.17" + attribute \src "libresoc.v:150286.9-150286.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" switch \reset_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -307023,7 +313482,7 @@ module \pimem case assign $1\adrok_l_r_addr_acked[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -307035,47 +313494,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:147236$7983_Y - connect \$11 $and$libresoc.v:147237$7984_Y - connect \$13 $not$libresoc.v:147238$7985_Y - connect \$15 $and$libresoc.v:147239$7986_Y - connect \$17 $not$libresoc.v:147240$7987_Y - connect \$1 $and$libresoc.v:147241$7988_Y - connect \$19 $and$libresoc.v:147242$7989_Y - connect \$21 $pos$libresoc.v:147243$7991_Y - connect \$23 $pos$libresoc.v:147244$7993_Y - connect \$25 $and$libresoc.v:147245$7994_Y - connect \$27 $and$libresoc.v:147246$7995_Y - connect \$29 $and$libresoc.v:147247$7996_Y - connect \$31 $and$libresoc.v:147248$7997_Y - connect \$33 $and$libresoc.v:147249$7998_Y - connect \$35 $not$libresoc.v:147250$7999_Y - connect \$38 $or$libresoc.v:147251$8000_Y - connect \$3 $or$libresoc.v:147252$8001_Y - connect \$37 $not$libresoc.v:147253$8002_Y - connect \$42 $and$libresoc.v:147254$8003_Y - connect \$44 $mul$libresoc.v:147255$8004_Y - connect \$46 $sshr$libresoc.v:147256$8005_Y - connect \$48 $and$libresoc.v:147257$8006_Y - connect \$50 $and$libresoc.v:147258$8007_Y - connect \$52 $not$libresoc.v:147259$8008_Y - connect \$54 $and$libresoc.v:147260$8009_Y - connect \$57 $mul$libresoc.v:147261$8010_Y - connect \$5 $not$libresoc.v:147262$8011_Y - connect \$59 $sshl$libresoc.v:147263$8012_Y - connect \$61 $and$libresoc.v:147264$8013_Y - connect \$63 $or$libresoc.v:147265$8014_Y - connect \$65 $and$libresoc.v:147266$8015_Y - connect \$67 $or$libresoc.v:147267$8016_Y - connect \$69 $and$libresoc.v:147268$8017_Y - connect \$71 $not$libresoc.v:147269$8018_Y - connect \$73 $not$libresoc.v:147270$8019_Y - connect \$75 $not$libresoc.v:147271$8020_Y - connect \$77 $and$libresoc.v:147272$8021_Y - connect \$7 $and$libresoc.v:147273$8022_Y - connect \$79 $not$libresoc.v:147274$8023_Y - connect \$81 $not$libresoc.v:147275$8024_Y - connect \$83 $and$libresoc.v:147276$8025_Y + connect \$9 $not$libresoc.v:149754$8295_Y + connect \$11 $and$libresoc.v:149755$8296_Y + connect \$13 $not$libresoc.v:149756$8297_Y + connect \$15 $and$libresoc.v:149757$8298_Y + connect \$17 $not$libresoc.v:149758$8299_Y + connect \$1 $and$libresoc.v:149759$8300_Y + connect \$19 $and$libresoc.v:149760$8301_Y + connect \$21 $pos$libresoc.v:149761$8303_Y + connect \$23 $pos$libresoc.v:149762$8305_Y + connect \$25 $and$libresoc.v:149763$8306_Y + connect \$27 $and$libresoc.v:149764$8307_Y + connect \$29 $and$libresoc.v:149765$8308_Y + connect \$31 $and$libresoc.v:149766$8309_Y + connect \$33 $and$libresoc.v:149767$8310_Y + connect \$35 $not$libresoc.v:149768$8311_Y + connect \$38 $or$libresoc.v:149769$8312_Y + connect \$3 $or$libresoc.v:149770$8313_Y + connect \$37 $not$libresoc.v:149771$8314_Y + connect \$42 $and$libresoc.v:149772$8315_Y + connect \$44 $mul$libresoc.v:149773$8316_Y + connect \$46 $sshr$libresoc.v:149774$8317_Y + connect \$48 $and$libresoc.v:149775$8318_Y + connect \$50 $and$libresoc.v:149776$8319_Y + connect \$52 $not$libresoc.v:149777$8320_Y + connect \$54 $and$libresoc.v:149778$8321_Y + connect \$57 $mul$libresoc.v:149779$8322_Y + connect \$5 $not$libresoc.v:149780$8323_Y + connect \$59 $sshl$libresoc.v:149781$8324_Y + connect \$61 $and$libresoc.v:149782$8325_Y + connect \$63 $or$libresoc.v:149783$8326_Y + connect \$65 $and$libresoc.v:149784$8327_Y + connect \$67 $or$libresoc.v:149785$8328_Y + connect \$69 $and$libresoc.v:149786$8329_Y + connect \$71 $not$libresoc.v:149787$8330_Y + connect \$73 $not$libresoc.v:149788$8331_Y + connect \$75 $not$libresoc.v:149789$8332_Y + connect \$77 $and$libresoc.v:149790$8333_Y + connect \$7 $and$libresoc.v:149791$8334_Y + connect \$79 $not$libresoc.v:149792$8335_Y + connect \$81 $not$libresoc.v:149793$8336_Y + connect \$83 $and$libresoc.v:149794$8337_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -307098,130 +313557,130 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:147808.1-148573.10" +attribute \src "libresoc.v:150326.1-151091.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:148536.3-148554.6" - wire width 4 $0\cr_a$6$next[3:0]$8135 - attribute \src "libresoc.v:148400.3-148401.31" - wire width 4 $0\cr_a$6[3:0]$8091 - attribute \src "libresoc.v:147822.13-147822.28" - wire width 4 $0\cr_a$6[3:0]$8141 - attribute \src "libresoc.v:148536.3-148554.6" - wire $0\cr_a_ok$next[0:0]$8134 - attribute \src "libresoc.v:148402.3-148403.31" + attribute \src "libresoc.v:151054.3-151072.6" + wire width 4 $0\cr_a$6$next[3:0]$8447 + attribute \src "libresoc.v:150918.3-150919.31" + wire width 4 $0\cr_a$6[3:0]$8403 + attribute \src "libresoc.v:150340.13-150340.28" + wire width 4 $0\cr_a$6[3:0]$8453 + attribute \src "libresoc.v:151054.3-151072.6" + wire $0\cr_a_ok$next[0:0]$8446 + attribute \src "libresoc.v:150920.3-150921.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:148483.3-148497.6" - wire width 12 $0\cr_op__fn_unit$3$next[11:0]$8115 - attribute \src "libresoc.v:148414.3-148415.51" - wire width 12 $0\cr_op__fn_unit$3[11:0]$8101 - attribute \src "libresoc.v:147881.14-147881.42" - wire width 12 $0\cr_op__fn_unit$3[11:0]$8144 - attribute \src "libresoc.v:148483.3-148497.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8116 - attribute \src "libresoc.v:148416.3-148417.45" - wire width 32 $0\cr_op__insn$4[31:0]$8103 - attribute \src "libresoc.v:147890.14-147890.37" - wire width 32 $0\cr_op__insn$4[31:0]$8146 - attribute \src "libresoc.v:148483.3-148497.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8117 - attribute \src "libresoc.v:148412.3-148413.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8099 - attribute \src "libresoc.v:148121.13-148121.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8148 - attribute \src "libresoc.v:148517.3-148535.6" - wire width 32 $0\full_cr$5$next[31:0]$8128 - attribute \src "libresoc.v:148404.3-148405.37" - wire width 32 $0\full_cr$5[31:0]$8094 - attribute \src "libresoc.v:148130.14-148130.33" - wire width 32 $0\full_cr$5[31:0]$8150 - attribute \src "libresoc.v:148517.3-148535.6" - wire $0\full_cr_ok$next[0:0]$8129 - attribute \src "libresoc.v:148406.3-148407.37" + attribute \src "libresoc.v:151001.3-151015.6" + wire width 12 $0\cr_op__fn_unit$3$next[11:0]$8427 + attribute \src "libresoc.v:150932.3-150933.51" + wire width 12 $0\cr_op__fn_unit$3[11:0]$8413 + attribute \src "libresoc.v:150399.14-150399.42" + wire width 12 $0\cr_op__fn_unit$3[11:0]$8456 + attribute \src "libresoc.v:151001.3-151015.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8428 + attribute \src "libresoc.v:150934.3-150935.45" + wire width 32 $0\cr_op__insn$4[31:0]$8415 + attribute \src "libresoc.v:150408.14-150408.37" + wire width 32 $0\cr_op__insn$4[31:0]$8458 + attribute \src "libresoc.v:151001.3-151015.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8429 + attribute \src "libresoc.v:150930.3-150931.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8411 + attribute \src "libresoc.v:150639.13-150639.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8460 + attribute \src "libresoc.v:151035.3-151053.6" + wire width 32 $0\full_cr$5$next[31:0]$8440 + attribute \src "libresoc.v:150922.3-150923.37" + wire width 32 $0\full_cr$5[31:0]$8406 + attribute \src "libresoc.v:150648.14-150648.33" + wire width 32 $0\full_cr$5[31:0]$8462 + attribute \src "libresoc.v:151035.3-151053.6" + wire $0\full_cr_ok$next[0:0]$8441 + attribute \src "libresoc.v:150924.3-150925.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:147809.7-147809.20" + attribute \src "libresoc.v:150327.7-150327.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148470.3-148482.6" - wire width 2 $0\muxid$1$next[1:0]$8112 - attribute \src "libresoc.v:148418.3-148419.33" - wire width 2 $0\muxid$1[1:0]$8105 - attribute \src "libresoc.v:148358.13-148358.29" - wire width 2 $0\muxid$1[1:0]$8153 - attribute \src "libresoc.v:148498.3-148516.6" - wire width 64 $0\o$next[63:0]$8122 - attribute \src "libresoc.v:148408.3-148409.19" + attribute \src "libresoc.v:150988.3-151000.6" + wire width 2 $0\muxid$1$next[1:0]$8424 + attribute \src "libresoc.v:150936.3-150937.33" + wire width 2 $0\muxid$1[1:0]$8417 + attribute \src "libresoc.v:150876.13-150876.29" + wire width 2 $0\muxid$1[1:0]$8465 + attribute \src "libresoc.v:151016.3-151034.6" + wire width 64 $0\o$next[63:0]$8434 + attribute \src "libresoc.v:150926.3-150927.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:148498.3-148516.6" - wire $0\o_ok$next[0:0]$8123 - attribute \src "libresoc.v:148410.3-148411.25" + attribute \src "libresoc.v:151016.3-151034.6" + wire $0\o_ok$next[0:0]$8435 + attribute \src "libresoc.v:150928.3-150929.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148452.3-148469.6" - wire $0\r_busy$next[0:0]$8108 - attribute \src "libresoc.v:148420.3-148421.29" + attribute \src "libresoc.v:150970.3-150987.6" + wire $0\r_busy$next[0:0]$8420 + attribute \src "libresoc.v:150938.3-150939.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:148536.3-148554.6" - wire width 4 $1\cr_a$6$next[3:0]$8137 - attribute \src "libresoc.v:148536.3-148554.6" - wire $1\cr_a_ok$next[0:0]$8136 - attribute \src "libresoc.v:147827.7-147827.21" + attribute \src "libresoc.v:151054.3-151072.6" + wire width 4 $1\cr_a$6$next[3:0]$8449 + attribute \src "libresoc.v:151054.3-151072.6" + wire $1\cr_a_ok$next[0:0]$8448 + attribute \src "libresoc.v:150345.7-150345.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148483.3-148497.6" - wire width 12 $1\cr_op__fn_unit$3$next[11:0]$8118 - attribute \src "libresoc.v:148483.3-148497.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8119 - attribute \src "libresoc.v:148483.3-148497.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8120 - attribute \src "libresoc.v:148517.3-148535.6" - wire width 32 $1\full_cr$5$next[31:0]$8130 - attribute \src "libresoc.v:148517.3-148535.6" - wire $1\full_cr_ok$next[0:0]$8131 - attribute \src "libresoc.v:148135.7-148135.24" + attribute \src "libresoc.v:151001.3-151015.6" + wire width 12 $1\cr_op__fn_unit$3$next[11:0]$8430 + attribute \src "libresoc.v:151001.3-151015.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8431 + attribute \src "libresoc.v:151001.3-151015.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8432 + attribute \src "libresoc.v:151035.3-151053.6" + wire width 32 $1\full_cr$5$next[31:0]$8442 + attribute \src "libresoc.v:151035.3-151053.6" + wire $1\full_cr_ok$next[0:0]$8443 + attribute \src "libresoc.v:150653.7-150653.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:148470.3-148482.6" - wire width 2 $1\muxid$1$next[1:0]$8113 - attribute \src "libresoc.v:148498.3-148516.6" - wire width 64 $1\o$next[63:0]$8124 - attribute \src "libresoc.v:148371.14-148371.38" + attribute \src "libresoc.v:150988.3-151000.6" + wire width 2 $1\muxid$1$next[1:0]$8425 + attribute \src "libresoc.v:151016.3-151034.6" + wire width 64 $1\o$next[63:0]$8436 + attribute \src "libresoc.v:150889.14-150889.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:148498.3-148516.6" - wire $1\o_ok$next[0:0]$8125 - attribute \src "libresoc.v:148378.7-148378.18" + attribute \src "libresoc.v:151016.3-151034.6" + wire $1\o_ok$next[0:0]$8437 + attribute \src "libresoc.v:150896.7-150896.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148452.3-148469.6" - wire $1\r_busy$next[0:0]$8109 - attribute \src "libresoc.v:148392.7-148392.20" + attribute \src "libresoc.v:150970.3-150987.6" + wire $1\r_busy$next[0:0]$8421 + attribute \src "libresoc.v:150910.7-150910.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:148536.3-148554.6" - wire $2\cr_a_ok$next[0:0]$8138 - attribute \src "libresoc.v:148517.3-148535.6" - wire $2\full_cr_ok$next[0:0]$8132 - attribute \src "libresoc.v:148498.3-148516.6" - wire $2\o_ok$next[0:0]$8126 - attribute \src "libresoc.v:148452.3-148469.6" - wire $2\r_busy$next[0:0]$8110 - attribute \src "libresoc.v:148399.18-148399.118" - wire $and$libresoc.v:148399$8089_Y + attribute \src "libresoc.v:151054.3-151072.6" + wire $2\cr_a_ok$next[0:0]$8450 + attribute \src "libresoc.v:151035.3-151053.6" + wire $2\full_cr_ok$next[0:0]$8444 + attribute \src "libresoc.v:151016.3-151034.6" + wire $2\o_ok$next[0:0]$8438 + attribute \src "libresoc.v:150970.3-150987.6" + wire $2\r_busy$next[0:0]$8422 + attribute \src "libresoc.v:150917.18-150917.118" + wire $and$libresoc.v:150917$8401_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 24 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 12 \cr_b @@ -307514,25 +313973,25 @@ module \pipe wire width 7 \cr_op__insn_type$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 input 10 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \full_cr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 output 22 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \full_cr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:147809.7-147809.15" + attribute \src "libresoc.v:150327.7-150327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \main_cr_a$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_b @@ -307726,17 +314185,17 @@ module \pipe wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_full_cr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_ra @@ -307756,17 +314215,17 @@ module \pipe wire input 15 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o @@ -307785,7 +314244,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:148399$8089 + cell $and $and$libresoc.v:150917$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307793,10 +314252,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:148399$8089_Y + connect \Y $and$libresoc.v:150917$8401_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:148422.12-148443.4" + attribute \src "libresoc.v:150940.12-150961.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -307820,199 +314279,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:148444.9-148447.4" + attribute \src "libresoc.v:150962.9-150965.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:148448.9-148451.4" + attribute \src "libresoc.v:150966.9-150969.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:147809.7-147809.20" - process $proc$libresoc.v:147809$8139 + attribute \src "libresoc.v:150327.7-150327.20" + process $proc$libresoc.v:150327$8451 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147822.13-147822.28" - process $proc$libresoc.v:147822$8140 + attribute \src "libresoc.v:150340.13-150340.28" + process $proc$libresoc.v:150340$8452 assign { } { } - assign $0\cr_a$6[3:0]$8141 4'0000 + assign $0\cr_a$6[3:0]$8453 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8141 + update \cr_a$6 $0\cr_a$6[3:0]$8453 end - attribute \src "libresoc.v:147827.7-147827.21" - process $proc$libresoc.v:147827$8142 + attribute \src "libresoc.v:150345.7-150345.21" + process $proc$libresoc.v:150345$8454 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:147881.14-147881.42" - process $proc$libresoc.v:147881$8143 + attribute \src "libresoc.v:150399.14-150399.42" + process $proc$libresoc.v:150399$8455 assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8144 12'000000000000 + assign $0\cr_op__fn_unit$3[11:0]$8456 12'000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8144 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8456 end - attribute \src "libresoc.v:147890.14-147890.37" - process $proc$libresoc.v:147890$8145 + attribute \src "libresoc.v:150408.14-150408.37" + process $proc$libresoc.v:150408$8457 assign { } { } - assign $0\cr_op__insn$4[31:0]$8146 0 + assign $0\cr_op__insn$4[31:0]$8458 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8146 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8458 end - attribute \src "libresoc.v:148121.13-148121.41" - process $proc$libresoc.v:148121$8147 + attribute \src "libresoc.v:150639.13-150639.41" + process $proc$libresoc.v:150639$8459 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8148 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8460 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8148 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8460 end - attribute \src "libresoc.v:148130.14-148130.33" - process $proc$libresoc.v:148130$8149 + attribute \src "libresoc.v:150648.14-150648.33" + process $proc$libresoc.v:150648$8461 assign { } { } - assign $0\full_cr$5[31:0]$8150 0 + assign $0\full_cr$5[31:0]$8462 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8150 + update \full_cr$5 $0\full_cr$5[31:0]$8462 end - attribute \src "libresoc.v:148135.7-148135.24" - process $proc$libresoc.v:148135$8151 + attribute \src "libresoc.v:150653.7-150653.24" + process $proc$libresoc.v:150653$8463 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:148358.13-148358.29" - process $proc$libresoc.v:148358$8152 + attribute \src "libresoc.v:150876.13-150876.29" + process $proc$libresoc.v:150876$8464 assign { } { } - assign $0\muxid$1[1:0]$8153 2'00 + assign $0\muxid$1[1:0]$8465 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8153 + update \muxid$1 $0\muxid$1[1:0]$8465 end - attribute \src "libresoc.v:148371.14-148371.38" - process $proc$libresoc.v:148371$8154 + attribute \src "libresoc.v:150889.14-150889.38" + process $proc$libresoc.v:150889$8466 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:148378.7-148378.18" - process $proc$libresoc.v:148378$8155 + attribute \src "libresoc.v:150896.7-150896.18" + process $proc$libresoc.v:150896$8467 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:148392.7-148392.20" - process $proc$libresoc.v:148392$8156 + attribute \src "libresoc.v:150910.7-150910.20" + process $proc$libresoc.v:150910$8468 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:148400.3-148401.31" - process $proc$libresoc.v:148400$8090 + attribute \src "libresoc.v:150918.3-150919.31" + process $proc$libresoc.v:150918$8402 assign { } { } - assign $0\cr_a$6[3:0]$8091 \cr_a$6$next + assign $0\cr_a$6[3:0]$8403 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8091 + update \cr_a$6 $0\cr_a$6[3:0]$8403 end - attribute \src "libresoc.v:148402.3-148403.31" - process $proc$libresoc.v:148402$8092 + attribute \src "libresoc.v:150920.3-150921.31" + process $proc$libresoc.v:150920$8404 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:148404.3-148405.37" - process $proc$libresoc.v:148404$8093 + attribute \src "libresoc.v:150922.3-150923.37" + process $proc$libresoc.v:150922$8405 assign { } { } - assign $0\full_cr$5[31:0]$8094 \full_cr$5$next + assign $0\full_cr$5[31:0]$8406 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8094 + update \full_cr$5 $0\full_cr$5[31:0]$8406 end - attribute \src "libresoc.v:148406.3-148407.37" - process $proc$libresoc.v:148406$8095 + attribute \src "libresoc.v:150924.3-150925.37" + process $proc$libresoc.v:150924$8407 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:148408.3-148409.19" - process $proc$libresoc.v:148408$8096 + attribute \src "libresoc.v:150926.3-150927.19" + process $proc$libresoc.v:150926$8408 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:148410.3-148411.25" - process $proc$libresoc.v:148410$8097 + attribute \src "libresoc.v:150928.3-150929.25" + process $proc$libresoc.v:150928$8409 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148412.3-148413.55" - process $proc$libresoc.v:148412$8098 + attribute \src "libresoc.v:150930.3-150931.55" + process $proc$libresoc.v:150930$8410 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8099 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8411 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8099 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8411 end - attribute \src "libresoc.v:148414.3-148415.51" - process $proc$libresoc.v:148414$8100 + attribute \src "libresoc.v:150932.3-150933.51" + process $proc$libresoc.v:150932$8412 assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8101 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[11:0]$8413 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8101 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8413 end - attribute \src "libresoc.v:148416.3-148417.45" - process $proc$libresoc.v:148416$8102 + attribute \src "libresoc.v:150934.3-150935.45" + process $proc$libresoc.v:150934$8414 assign { } { } - assign $0\cr_op__insn$4[31:0]$8103 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8415 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8103 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8415 end - attribute \src "libresoc.v:148418.3-148419.33" - process $proc$libresoc.v:148418$8104 + attribute \src "libresoc.v:150936.3-150937.33" + process $proc$libresoc.v:150936$8416 assign { } { } - assign $0\muxid$1[1:0]$8105 \muxid$1$next + assign $0\muxid$1[1:0]$8417 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8105 + update \muxid$1 $0\muxid$1[1:0]$8417 end - attribute \src "libresoc.v:148420.3-148421.29" - process $proc$libresoc.v:148420$8106 + attribute \src "libresoc.v:150938.3-150939.29" + process $proc$libresoc.v:150938$8418 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:148452.3-148469.6" - process $proc$libresoc.v:148452$8107 + attribute \src "libresoc.v:150970.3-150987.6" + process $proc$libresoc.v:150970$8419 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8108 $2\r_busy$next[0:0]$8110 - attribute \src "libresoc.v:148453.5-148453.29" + assign $0\r_busy$next[0:0]$8420 $2\r_busy$next[0:0]$8422 + attribute \src "libresoc.v:150971.5-150971.29" switch \initial - attribute \src "libresoc.v:148453.9-148453.17" + attribute \src "libresoc.v:150971.9-150971.17" case 1'1 case end @@ -308021,34 +314480,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8109 1'1 + assign $1\r_busy$next[0:0]$8421 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8109 1'0 + assign $1\r_busy$next[0:0]$8421 1'0 case - assign $1\r_busy$next[0:0]$8109 \r_busy + assign $1\r_busy$next[0:0]$8421 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8110 1'0 + assign $2\r_busy$next[0:0]$8422 1'0 case - assign $2\r_busy$next[0:0]$8110 $1\r_busy$next[0:0]$8109 + assign $2\r_busy$next[0:0]$8422 $1\r_busy$next[0:0]$8421 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8108 + update \r_busy$next $0\r_busy$next[0:0]$8420 end - attribute \src "libresoc.v:148470.3-148482.6" - process $proc$libresoc.v:148470$8111 + attribute \src "libresoc.v:150988.3-151000.6" + process $proc$libresoc.v:150988$8423 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8112 $1\muxid$1$next[1:0]$8113 - attribute \src "libresoc.v:148471.5-148471.29" + assign $0\muxid$1$next[1:0]$8424 $1\muxid$1$next[1:0]$8425 + attribute \src "libresoc.v:150989.5-150989.29" switch \initial - attribute \src "libresoc.v:148471.9-148471.17" + attribute \src "libresoc.v:150989.9-150989.17" case 1'1 case end @@ -308057,31 +314516,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8113 \muxid$16 + assign $1\muxid$1$next[1:0]$8425 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8113 \muxid$16 + assign $1\muxid$1$next[1:0]$8425 \muxid$16 case - assign $1\muxid$1$next[1:0]$8113 \muxid$1 + assign $1\muxid$1$next[1:0]$8425 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8112 + update \muxid$1$next $0\muxid$1$next[1:0]$8424 end - attribute \src "libresoc.v:148483.3-148497.6" - process $proc$libresoc.v:148483$8114 + attribute \src "libresoc.v:151001.3-151015.6" + process $proc$libresoc.v:151001$8426 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[11:0]$8115 $1\cr_op__fn_unit$3$next[11:0]$8118 - assign $0\cr_op__insn$4$next[31:0]$8116 $1\cr_op__insn$4$next[31:0]$8119 - assign $0\cr_op__insn_type$2$next[6:0]$8117 $1\cr_op__insn_type$2$next[6:0]$8120 - attribute \src "libresoc.v:148484.5-148484.29" + assign $0\cr_op__fn_unit$3$next[11:0]$8427 $1\cr_op__fn_unit$3$next[11:0]$8430 + assign $0\cr_op__insn$4$next[31:0]$8428 $1\cr_op__insn$4$next[31:0]$8431 + assign $0\cr_op__insn_type$2$next[6:0]$8429 $1\cr_op__insn_type$2$next[6:0]$8432 + attribute \src "libresoc.v:151002.5-151002.29" switch \initial - attribute \src "libresoc.v:148484.9-148484.17" + attribute \src "libresoc.v:151002.9-151002.17" case 1'1 case end @@ -308092,35 +314551,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8119 $1\cr_op__fn_unit$3$next[11:0]$8118 $1\cr_op__insn_type$2$next[6:0]$8120 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8431 $1\cr_op__fn_unit$3$next[11:0]$8430 $1\cr_op__insn_type$2$next[6:0]$8432 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8119 $1\cr_op__fn_unit$3$next[11:0]$8118 $1\cr_op__insn_type$2$next[6:0]$8120 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8431 $1\cr_op__fn_unit$3$next[11:0]$8430 $1\cr_op__insn_type$2$next[6:0]$8432 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[11:0]$8118 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8119 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8120 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[11:0]$8430 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8431 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8432 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8115 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8116 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8117 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8427 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8428 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8429 end - attribute \src "libresoc.v:148498.3-148516.6" - process $proc$libresoc.v:148498$8121 + attribute \src "libresoc.v:151016.3-151034.6" + process $proc$libresoc.v:151016$8433 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8122 $1\o$next[63:0]$8124 + assign $0\o$next[63:0]$8434 $1\o$next[63:0]$8436 assign { } { } - assign $0\o_ok$next[0:0]$8123 $2\o_ok$next[0:0]$8126 - attribute \src "libresoc.v:148499.5-148499.29" + assign $0\o_ok$next[0:0]$8435 $2\o_ok$next[0:0]$8438 + attribute \src "libresoc.v:151017.5-151017.29" switch \initial - attribute \src "libresoc.v:148499.9-148499.17" + attribute \src "libresoc.v:151017.9-151017.17" case 1'1 case end @@ -308130,41 +314589,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8125 $1\o$next[63:0]$8124 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8437 $1\o$next[63:0]$8436 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8125 $1\o$next[63:0]$8124 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8437 $1\o$next[63:0]$8436 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8124 \o - assign $1\o_ok$next[0:0]$8125 \o_ok + assign $1\o$next[63:0]$8436 \o + assign $1\o_ok$next[0:0]$8437 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8126 1'0 + assign $2\o_ok$next[0:0]$8438 1'0 case - assign $2\o_ok$next[0:0]$8126 $1\o_ok$next[0:0]$8125 + assign $2\o_ok$next[0:0]$8438 $1\o_ok$next[0:0]$8437 end sync always - update \o$next $0\o$next[63:0]$8122 - update \o_ok$next $0\o_ok$next[0:0]$8123 + update \o$next $0\o$next[63:0]$8434 + update \o_ok$next $0\o_ok$next[0:0]$8435 end - attribute \src "libresoc.v:148517.3-148535.6" - process $proc$libresoc.v:148517$8127 + attribute \src "libresoc.v:151035.3-151053.6" + process $proc$libresoc.v:151035$8439 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8128 $1\full_cr$5$next[31:0]$8130 + assign $0\full_cr$5$next[31:0]$8440 $1\full_cr$5$next[31:0]$8442 assign { } { } - assign $0\full_cr_ok$next[0:0]$8129 $2\full_cr_ok$next[0:0]$8132 - attribute \src "libresoc.v:148518.5-148518.29" + assign $0\full_cr_ok$next[0:0]$8441 $2\full_cr_ok$next[0:0]$8444 + attribute \src "libresoc.v:151036.5-151036.29" switch \initial - attribute \src "libresoc.v:148518.9-148518.17" + attribute \src "libresoc.v:151036.9-151036.17" case 1'1 case end @@ -308174,41 +314633,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8131 $1\full_cr$5$next[31:0]$8130 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8443 $1\full_cr$5$next[31:0]$8442 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8131 $1\full_cr$5$next[31:0]$8130 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8443 $1\full_cr$5$next[31:0]$8442 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8130 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8131 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8442 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8443 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8132 1'0 + assign $2\full_cr_ok$next[0:0]$8444 1'0 case - assign $2\full_cr_ok$next[0:0]$8132 $1\full_cr_ok$next[0:0]$8131 + assign $2\full_cr_ok$next[0:0]$8444 $1\full_cr_ok$next[0:0]$8443 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8128 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8129 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8440 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8441 end - attribute \src "libresoc.v:148536.3-148554.6" - process $proc$libresoc.v:148536$8133 + attribute \src "libresoc.v:151054.3-151072.6" + process $proc$libresoc.v:151054$8445 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8135 $1\cr_a$6$next[3:0]$8137 - assign $0\cr_a_ok$next[0:0]$8134 $2\cr_a_ok$next[0:0]$8138 - attribute \src "libresoc.v:148537.5-148537.29" + assign $0\cr_a$6$next[3:0]$8447 $1\cr_a$6$next[3:0]$8449 + assign $0\cr_a_ok$next[0:0]$8446 $2\cr_a_ok$next[0:0]$8450 + attribute \src "libresoc.v:151055.5-151055.29" switch \initial - attribute \src "libresoc.v:148537.9-148537.17" + attribute \src "libresoc.v:151055.9-151055.17" case 1'1 case end @@ -308218,30 +314677,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8136 $1\cr_a$6$next[3:0]$8137 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8448 $1\cr_a$6$next[3:0]$8449 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8136 $1\cr_a$6$next[3:0]$8137 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8448 $1\cr_a$6$next[3:0]$8449 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8136 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8137 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8448 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8449 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8138 1'0 + assign $2\cr_a_ok$next[0:0]$8450 1'0 case - assign $2\cr_a_ok$next[0:0]$8138 $1\cr_a_ok$next[0:0]$8136 + assign $2\cr_a_ok$next[0:0]$8450 $1\cr_a_ok$next[0:0]$8448 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8134 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8135 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8446 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8447 end - connect \$14 $and$libresoc.v:148399$8089_Y + connect \$14 $and$libresoc.v:150917$8401_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -308261,155 +314720,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:148577.1-149422.10" +attribute \src "libresoc.v:151095.1-151940.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8193 - attribute \src "libresoc.v:149234.3-149235.43" - wire width 64 $0\br_op__cia$2[63:0]$8167 - attribute \src "libresoc.v:148585.14-148585.51" - wire width 64 $0\br_op__cia$2[63:0]$8231 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 12 $0\br_op__fn_unit$4$next[11:0]$8194 - attribute \src "libresoc.v:149238.3-149239.51" - wire width 12 $0\br_op__fn_unit$4[11:0]$8171 - attribute \src "libresoc.v:148635.14-148635.42" - wire width 12 $0\br_op__fn_unit$4[11:0]$8233 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8195 - attribute \src "libresoc.v:149242.3-149243.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8175 - attribute \src "libresoc.v:148644.14-148644.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8235 - attribute \src "libresoc.v:149322.3-149349.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8196 - attribute \src "libresoc.v:149244.3-149245.61" - wire $0\br_op__imm_data__ok$7[0:0]$8177 - attribute \src "libresoc.v:148653.7-148653.37" - wire $0\br_op__imm_data__ok$7[0:0]$8237 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8197 - attribute \src "libresoc.v:149240.3-149241.45" - wire width 32 $0\br_op__insn$5[31:0]$8173 - attribute \src "libresoc.v:148662.14-148662.37" - wire width 32 $0\br_op__insn$5[31:0]$8239 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8198 - attribute \src "libresoc.v:149236.3-149237.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8169 - attribute \src "libresoc.v:148893.13-148893.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8241 - attribute \src "libresoc.v:149322.3-149349.6" - wire $0\br_op__is_32bit$9$next[0:0]$8199 - attribute \src "libresoc.v:149248.3-149249.53" - wire $0\br_op__is_32bit$9[0:0]$8181 - attribute \src "libresoc.v:148902.7-148902.33" - wire $0\br_op__is_32bit$9[0:0]$8243 - attribute \src "libresoc.v:149322.3-149349.6" - wire $0\br_op__lk$8$next[0:0]$8200 - attribute \src "libresoc.v:149246.3-149247.41" - wire $0\br_op__lk$8[0:0]$8179 - attribute \src "libresoc.v:148911.7-148911.27" - wire $0\br_op__lk$8[0:0]$8245 - attribute \src "libresoc.v:149350.3-149368.6" - wire width 64 $0\fast1$10$next[63:0]$8212 - attribute \src "libresoc.v:149230.3-149231.35" - wire width 64 $0\fast1$10[63:0]$8164 - attribute \src "libresoc.v:148924.14-148924.47" - wire width 64 $0\fast1$10[63:0]$8247 - attribute \src "libresoc.v:149350.3-149368.6" - wire $0\fast1_ok$next[0:0]$8213 - attribute \src "libresoc.v:149232.3-149233.33" + attribute \src "libresoc.v:151840.3-151867.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8505 + attribute \src "libresoc.v:151752.3-151753.43" + wire width 64 $0\br_op__cia$2[63:0]$8479 + attribute \src "libresoc.v:151103.14-151103.51" + wire width 64 $0\br_op__cia$2[63:0]$8543 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 12 $0\br_op__fn_unit$4$next[11:0]$8506 + attribute \src "libresoc.v:151756.3-151757.51" + wire width 12 $0\br_op__fn_unit$4[11:0]$8483 + attribute \src "libresoc.v:151153.14-151153.42" + wire width 12 $0\br_op__fn_unit$4[11:0]$8545 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8507 + attribute \src "libresoc.v:151760.3-151761.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8487 + attribute \src "libresoc.v:151162.14-151162.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8547 + attribute \src "libresoc.v:151840.3-151867.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8508 + attribute \src "libresoc.v:151762.3-151763.61" + wire $0\br_op__imm_data__ok$7[0:0]$8489 + attribute \src "libresoc.v:151171.7-151171.37" + wire $0\br_op__imm_data__ok$7[0:0]$8549 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8509 + attribute \src "libresoc.v:151758.3-151759.45" + wire width 32 $0\br_op__insn$5[31:0]$8485 + attribute \src "libresoc.v:151180.14-151180.37" + wire width 32 $0\br_op__insn$5[31:0]$8551 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8510 + attribute \src "libresoc.v:151754.3-151755.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8481 + attribute \src "libresoc.v:151411.13-151411.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8553 + attribute \src "libresoc.v:151840.3-151867.6" + wire $0\br_op__is_32bit$9$next[0:0]$8511 + attribute \src "libresoc.v:151766.3-151767.53" + wire $0\br_op__is_32bit$9[0:0]$8493 + attribute \src "libresoc.v:151420.7-151420.33" + wire $0\br_op__is_32bit$9[0:0]$8555 + attribute \src "libresoc.v:151840.3-151867.6" + wire $0\br_op__lk$8$next[0:0]$8512 + attribute \src "libresoc.v:151764.3-151765.41" + wire $0\br_op__lk$8[0:0]$8491 + attribute \src "libresoc.v:151429.7-151429.27" + wire $0\br_op__lk$8[0:0]$8557 + attribute \src "libresoc.v:151868.3-151886.6" + wire width 64 $0\fast1$10$next[63:0]$8524 + attribute \src "libresoc.v:151748.3-151749.35" + wire width 64 $0\fast1$10[63:0]$8476 + attribute \src "libresoc.v:151442.14-151442.47" + wire width 64 $0\fast1$10[63:0]$8559 + attribute \src "libresoc.v:151868.3-151886.6" + wire $0\fast1_ok$next[0:0]$8525 + attribute \src "libresoc.v:151750.3-151751.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:149369.3-149387.6" - wire width 64 $0\fast2$11$next[63:0]$8218 - attribute \src "libresoc.v:149226.3-149227.35" - wire width 64 $0\fast2$11[63:0]$8161 - attribute \src "libresoc.v:148940.14-148940.47" - wire width 64 $0\fast2$11[63:0]$8250 - attribute \src "libresoc.v:149369.3-149387.6" - wire $0\fast2_ok$next[0:0]$8219 - attribute \src "libresoc.v:149228.3-149229.33" + attribute \src "libresoc.v:151887.3-151905.6" + wire width 64 $0\fast2$11$next[63:0]$8530 + attribute \src "libresoc.v:151744.3-151745.35" + wire width 64 $0\fast2$11[63:0]$8473 + attribute \src "libresoc.v:151458.14-151458.47" + wire width 64 $0\fast2$11[63:0]$8562 + attribute \src "libresoc.v:151887.3-151905.6" + wire $0\fast2_ok$next[0:0]$8531 + attribute \src "libresoc.v:151746.3-151747.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:148578.7-148578.20" + attribute \src "libresoc.v:151096.7-151096.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149309.3-149321.6" - wire width 2 $0\muxid$1$next[1:0]$8190 - attribute \src "libresoc.v:149250.3-149251.33" - wire width 2 $0\muxid$1[1:0]$8183 - attribute \src "libresoc.v:149184.13-149184.29" - wire width 2 $0\muxid$1[1:0]$8253 - attribute \src "libresoc.v:149388.3-149406.6" - wire width 64 $0\nia$next[63:0]$8224 - attribute \src "libresoc.v:149222.3-149223.23" + attribute \src "libresoc.v:151827.3-151839.6" + wire width 2 $0\muxid$1$next[1:0]$8502 + attribute \src "libresoc.v:151768.3-151769.33" + wire width 2 $0\muxid$1[1:0]$8495 + attribute \src "libresoc.v:151702.13-151702.29" + wire width 2 $0\muxid$1[1:0]$8565 + attribute \src "libresoc.v:151906.3-151924.6" + wire width 64 $0\nia$next[63:0]$8536 + attribute \src "libresoc.v:151740.3-151741.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:149388.3-149406.6" - wire $0\nia_ok$next[0:0]$8225 - attribute \src "libresoc.v:149224.3-149225.29" + attribute \src "libresoc.v:151906.3-151924.6" + wire $0\nia_ok$next[0:0]$8537 + attribute \src "libresoc.v:151742.3-151743.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:149291.3-149308.6" - wire $0\r_busy$next[0:0]$8186 - attribute \src "libresoc.v:149252.3-149253.29" + attribute \src "libresoc.v:151809.3-151826.6" + wire $0\r_busy$next[0:0]$8498 + attribute \src "libresoc.v:151770.3-151771.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:149322.3-149349.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8201 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 12 $1\br_op__fn_unit$4$next[11:0]$8202 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8203 - attribute \src "libresoc.v:149322.3-149349.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8204 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8205 - attribute \src "libresoc.v:149322.3-149349.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8206 - attribute \src "libresoc.v:149322.3-149349.6" - wire $1\br_op__is_32bit$9$next[0:0]$8207 - attribute \src "libresoc.v:149322.3-149349.6" - wire $1\br_op__lk$8$next[0:0]$8208 - attribute \src "libresoc.v:149350.3-149368.6" - wire width 64 $1\fast1$10$next[63:0]$8214 - attribute \src "libresoc.v:149350.3-149368.6" - wire $1\fast1_ok$next[0:0]$8215 - attribute \src "libresoc.v:148931.7-148931.22" + attribute \src "libresoc.v:151840.3-151867.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8513 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 12 $1\br_op__fn_unit$4$next[11:0]$8514 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8515 + attribute \src "libresoc.v:151840.3-151867.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8516 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8517 + attribute \src "libresoc.v:151840.3-151867.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8518 + attribute \src "libresoc.v:151840.3-151867.6" + wire $1\br_op__is_32bit$9$next[0:0]$8519 + attribute \src "libresoc.v:151840.3-151867.6" + wire $1\br_op__lk$8$next[0:0]$8520 + attribute \src "libresoc.v:151868.3-151886.6" + wire width 64 $1\fast1$10$next[63:0]$8526 + attribute \src "libresoc.v:151868.3-151886.6" + wire $1\fast1_ok$next[0:0]$8527 + attribute \src "libresoc.v:151449.7-151449.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:149369.3-149387.6" - wire width 64 $1\fast2$11$next[63:0]$8220 - attribute \src "libresoc.v:149369.3-149387.6" - wire $1\fast2_ok$next[0:0]$8221 - attribute \src "libresoc.v:148947.7-148947.22" + attribute \src "libresoc.v:151887.3-151905.6" + wire width 64 $1\fast2$11$next[63:0]$8532 + attribute \src "libresoc.v:151887.3-151905.6" + wire $1\fast2_ok$next[0:0]$8533 + attribute \src "libresoc.v:151465.7-151465.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:149309.3-149321.6" - wire width 2 $1\muxid$1$next[1:0]$8191 - attribute \src "libresoc.v:149388.3-149406.6" - wire width 64 $1\nia$next[63:0]$8226 - attribute \src "libresoc.v:149197.14-149197.40" + attribute \src "libresoc.v:151827.3-151839.6" + wire width 2 $1\muxid$1$next[1:0]$8503 + attribute \src "libresoc.v:151906.3-151924.6" + wire width 64 $1\nia$next[63:0]$8538 + attribute \src "libresoc.v:151715.14-151715.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:149388.3-149406.6" - wire $1\nia_ok$next[0:0]$8227 - attribute \src "libresoc.v:149204.7-149204.20" + attribute \src "libresoc.v:151906.3-151924.6" + wire $1\nia_ok$next[0:0]$8539 + attribute \src "libresoc.v:151722.7-151722.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:149291.3-149308.6" - wire $1\r_busy$next[0:0]$8187 - attribute \src "libresoc.v:149218.7-149218.20" + attribute \src "libresoc.v:151809.3-151826.6" + wire $1\r_busy$next[0:0]$8499 + attribute \src "libresoc.v:151736.7-151736.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:149322.3-149349.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8209 - attribute \src "libresoc.v:149322.3-149349.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8210 - attribute \src "libresoc.v:149350.3-149368.6" - wire $2\fast1_ok$next[0:0]$8216 - attribute \src "libresoc.v:149369.3-149387.6" - wire $2\fast2_ok$next[0:0]$8222 - attribute \src "libresoc.v:149388.3-149406.6" - wire $2\nia_ok$next[0:0]$8228 - attribute \src "libresoc.v:149291.3-149308.6" - wire $2\r_busy$next[0:0]$8188 - attribute \src "libresoc.v:149221.18-149221.118" - wire $and$libresoc.v:149221$8157_Y + attribute \src "libresoc.v:151840.3-151867.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8521 + attribute \src "libresoc.v:151840.3-151867.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8522 + attribute \src "libresoc.v:151868.3-151886.6" + wire $2\fast1_ok$next[0:0]$8528 + attribute \src "libresoc.v:151887.3-151905.6" + wire $2\fast2_ok$next[0:0]$8534 + attribute \src "libresoc.v:151906.3-151924.6" + wire $2\nia_ok$next[0:0]$8540 + attribute \src "libresoc.v:151809.3-151826.6" + wire $2\r_busy$next[0:0]$8500 + attribute \src "libresoc.v:151739.18-151739.118" + wire $and$libresoc.v:151739$8469_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -308737,41 +315196,41 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 13 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 27 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 29 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \fast2$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:148578.7-148578.15" + attribute \src "libresoc.v:151096.7-151096.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -308983,23 +315442,23 @@ module \pipe$19 wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \main_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 4 \muxid @@ -309015,17 +315474,17 @@ module \pipe$19 wire input 17 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 31 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \nia_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o @@ -309040,7 +315499,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:149221$8157 + cell $and $and$libresoc.v:151739$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -309048,10 +315507,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:149221$8157_Y + connect \Y $and$libresoc.v:151739$8469_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:149254.13-149282.4" + attribute \src "libresoc.v:151772.13-151800.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -309082,274 +315541,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:149283.10-149286.4" + attribute \src "libresoc.v:151801.10-151804.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:149287.10-149290.4" + attribute \src "libresoc.v:151805.10-151808.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:148578.7-148578.20" - process $proc$libresoc.v:148578$8229 + attribute \src "libresoc.v:151096.7-151096.20" + process $proc$libresoc.v:151096$8541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148585.14-148585.51" - process $proc$libresoc.v:148585$8230 + attribute \src "libresoc.v:151103.14-151103.51" + process $proc$libresoc.v:151103$8542 assign { } { } - assign $0\br_op__cia$2[63:0]$8231 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8543 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8231 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8543 end - attribute \src "libresoc.v:148635.14-148635.42" - process $proc$libresoc.v:148635$8232 + attribute \src "libresoc.v:151153.14-151153.42" + process $proc$libresoc.v:151153$8544 assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8233 12'000000000000 + assign $0\br_op__fn_unit$4[11:0]$8545 12'000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8233 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8545 end - attribute \src "libresoc.v:148644.14-148644.62" - process $proc$libresoc.v:148644$8234 + attribute \src "libresoc.v:151162.14-151162.62" + process $proc$libresoc.v:151162$8546 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8235 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8547 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8235 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8547 end - attribute \src "libresoc.v:148653.7-148653.37" - process $proc$libresoc.v:148653$8236 + attribute \src "libresoc.v:151171.7-151171.37" + process $proc$libresoc.v:151171$8548 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8237 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8549 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8237 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8549 end - attribute \src "libresoc.v:148662.14-148662.37" - process $proc$libresoc.v:148662$8238 + attribute \src "libresoc.v:151180.14-151180.37" + process $proc$libresoc.v:151180$8550 assign { } { } - assign $0\br_op__insn$5[31:0]$8239 0 + assign $0\br_op__insn$5[31:0]$8551 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8239 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8551 end - attribute \src "libresoc.v:148893.13-148893.41" - process $proc$libresoc.v:148893$8240 + attribute \src "libresoc.v:151411.13-151411.41" + process $proc$libresoc.v:151411$8552 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8241 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8553 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8241 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8553 end - attribute \src "libresoc.v:148902.7-148902.33" - process $proc$libresoc.v:148902$8242 + attribute \src "libresoc.v:151420.7-151420.33" + process $proc$libresoc.v:151420$8554 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8243 1'0 + assign $0\br_op__is_32bit$9[0:0]$8555 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8243 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8555 end - attribute \src "libresoc.v:148911.7-148911.27" - process $proc$libresoc.v:148911$8244 + attribute \src "libresoc.v:151429.7-151429.27" + process $proc$libresoc.v:151429$8556 assign { } { } - assign $0\br_op__lk$8[0:0]$8245 1'0 + assign $0\br_op__lk$8[0:0]$8557 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8245 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8557 end - attribute \src "libresoc.v:148924.14-148924.47" - process $proc$libresoc.v:148924$8246 + attribute \src "libresoc.v:151442.14-151442.47" + process $proc$libresoc.v:151442$8558 assign { } { } - assign $0\fast1$10[63:0]$8247 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8559 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8247 + update \fast1$10 $0\fast1$10[63:0]$8559 end - attribute \src "libresoc.v:148931.7-148931.22" - process $proc$libresoc.v:148931$8248 + attribute \src "libresoc.v:151449.7-151449.22" + process $proc$libresoc.v:151449$8560 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:148940.14-148940.47" - process $proc$libresoc.v:148940$8249 + attribute \src "libresoc.v:151458.14-151458.47" + process $proc$libresoc.v:151458$8561 assign { } { } - assign $0\fast2$11[63:0]$8250 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8562 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8250 + update \fast2$11 $0\fast2$11[63:0]$8562 end - attribute \src "libresoc.v:148947.7-148947.22" - process $proc$libresoc.v:148947$8251 + attribute \src "libresoc.v:151465.7-151465.22" + process $proc$libresoc.v:151465$8563 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:149184.13-149184.29" - process $proc$libresoc.v:149184$8252 + attribute \src "libresoc.v:151702.13-151702.29" + process $proc$libresoc.v:151702$8564 assign { } { } - assign $0\muxid$1[1:0]$8253 2'00 + assign $0\muxid$1[1:0]$8565 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8253 + update \muxid$1 $0\muxid$1[1:0]$8565 end - attribute \src "libresoc.v:149197.14-149197.40" - process $proc$libresoc.v:149197$8254 + attribute \src "libresoc.v:151715.14-151715.40" + process $proc$libresoc.v:151715$8566 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:149204.7-149204.20" - process $proc$libresoc.v:149204$8255 + attribute \src "libresoc.v:151722.7-151722.20" + process $proc$libresoc.v:151722$8567 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:149218.7-149218.20" - process $proc$libresoc.v:149218$8256 + attribute \src "libresoc.v:151736.7-151736.20" + process $proc$libresoc.v:151736$8568 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:149222.3-149223.23" - process $proc$libresoc.v:149222$8158 + attribute \src "libresoc.v:151740.3-151741.23" + process $proc$libresoc.v:151740$8470 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:149224.3-149225.29" - process $proc$libresoc.v:149224$8159 + attribute \src "libresoc.v:151742.3-151743.29" + process $proc$libresoc.v:151742$8471 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:149226.3-149227.35" - process $proc$libresoc.v:149226$8160 + attribute \src "libresoc.v:151744.3-151745.35" + process $proc$libresoc.v:151744$8472 assign { } { } - assign $0\fast2$11[63:0]$8161 \fast2$11$next + assign $0\fast2$11[63:0]$8473 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8161 + update \fast2$11 $0\fast2$11[63:0]$8473 end - attribute \src "libresoc.v:149228.3-149229.33" - process $proc$libresoc.v:149228$8162 + attribute \src "libresoc.v:151746.3-151747.33" + process $proc$libresoc.v:151746$8474 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:149230.3-149231.35" - process $proc$libresoc.v:149230$8163 + attribute \src "libresoc.v:151748.3-151749.35" + process $proc$libresoc.v:151748$8475 assign { } { } - assign $0\fast1$10[63:0]$8164 \fast1$10$next + assign $0\fast1$10[63:0]$8476 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8164 + update \fast1$10 $0\fast1$10[63:0]$8476 end - attribute \src "libresoc.v:149232.3-149233.33" - process $proc$libresoc.v:149232$8165 + attribute \src "libresoc.v:151750.3-151751.33" + process $proc$libresoc.v:151750$8477 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:149234.3-149235.43" - process $proc$libresoc.v:149234$8166 + attribute \src "libresoc.v:151752.3-151753.43" + process $proc$libresoc.v:151752$8478 assign { } { } - assign $0\br_op__cia$2[63:0]$8167 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8479 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8167 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8479 end - attribute \src "libresoc.v:149236.3-149237.55" - process $proc$libresoc.v:149236$8168 + attribute \src "libresoc.v:151754.3-151755.55" + process $proc$libresoc.v:151754$8480 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8169 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8481 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8169 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8481 end - attribute \src "libresoc.v:149238.3-149239.51" - process $proc$libresoc.v:149238$8170 + attribute \src "libresoc.v:151756.3-151757.51" + process $proc$libresoc.v:151756$8482 assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8171 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[11:0]$8483 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8171 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8483 end - attribute \src "libresoc.v:149240.3-149241.45" - process $proc$libresoc.v:149240$8172 + attribute \src "libresoc.v:151758.3-151759.45" + process $proc$libresoc.v:151758$8484 assign { } { } - assign $0\br_op__insn$5[31:0]$8173 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8485 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8173 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8485 end - attribute \src "libresoc.v:149242.3-149243.65" - process $proc$libresoc.v:149242$8174 + attribute \src "libresoc.v:151760.3-151761.65" + process $proc$libresoc.v:151760$8486 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8175 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8487 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8175 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8487 end - attribute \src "libresoc.v:149244.3-149245.61" - process $proc$libresoc.v:149244$8176 + attribute \src "libresoc.v:151762.3-151763.61" + process $proc$libresoc.v:151762$8488 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8177 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8489 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8177 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8489 end - attribute \src "libresoc.v:149246.3-149247.41" - process $proc$libresoc.v:149246$8178 + attribute \src "libresoc.v:151764.3-151765.41" + process $proc$libresoc.v:151764$8490 assign { } { } - assign $0\br_op__lk$8[0:0]$8179 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8491 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8179 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8491 end - attribute \src "libresoc.v:149248.3-149249.53" - process $proc$libresoc.v:149248$8180 + attribute \src "libresoc.v:151766.3-151767.53" + process $proc$libresoc.v:151766$8492 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8181 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8493 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8181 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8493 end - attribute \src "libresoc.v:149250.3-149251.33" - process $proc$libresoc.v:149250$8182 + attribute \src "libresoc.v:151768.3-151769.33" + process $proc$libresoc.v:151768$8494 assign { } { } - assign $0\muxid$1[1:0]$8183 \muxid$1$next + assign $0\muxid$1[1:0]$8495 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8183 + update \muxid$1 $0\muxid$1[1:0]$8495 end - attribute \src "libresoc.v:149252.3-149253.29" - process $proc$libresoc.v:149252$8184 + attribute \src "libresoc.v:151770.3-151771.29" + process $proc$libresoc.v:151770$8496 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:149291.3-149308.6" - process $proc$libresoc.v:149291$8185 + attribute \src "libresoc.v:151809.3-151826.6" + process $proc$libresoc.v:151809$8497 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8186 $2\r_busy$next[0:0]$8188 - attribute \src "libresoc.v:149292.5-149292.29" + assign $0\r_busy$next[0:0]$8498 $2\r_busy$next[0:0]$8500 + attribute \src "libresoc.v:151810.5-151810.29" switch \initial - attribute \src "libresoc.v:149292.9-149292.17" + attribute \src "libresoc.v:151810.9-151810.17" case 1'1 case end @@ -309358,34 +315817,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8187 1'1 + assign $1\r_busy$next[0:0]$8499 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8187 1'0 + assign $1\r_busy$next[0:0]$8499 1'0 case - assign $1\r_busy$next[0:0]$8187 \r_busy + assign $1\r_busy$next[0:0]$8499 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8188 1'0 + assign $2\r_busy$next[0:0]$8500 1'0 case - assign $2\r_busy$next[0:0]$8188 $1\r_busy$next[0:0]$8187 + assign $2\r_busy$next[0:0]$8500 $1\r_busy$next[0:0]$8499 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8186 + update \r_busy$next $0\r_busy$next[0:0]$8498 end - attribute \src "libresoc.v:149309.3-149321.6" - process $proc$libresoc.v:149309$8189 + attribute \src "libresoc.v:151827.3-151839.6" + process $proc$libresoc.v:151827$8501 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8190 $1\muxid$1$next[1:0]$8191 - attribute \src "libresoc.v:149310.5-149310.29" + assign $0\muxid$1$next[1:0]$8502 $1\muxid$1$next[1:0]$8503 + attribute \src "libresoc.v:151828.5-151828.29" switch \initial - attribute \src "libresoc.v:149310.9-149310.17" + attribute \src "libresoc.v:151828.9-151828.17" case 1'1 case end @@ -309394,19 +315853,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8191 \muxid$26 + assign $1\muxid$1$next[1:0]$8503 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8191 \muxid$26 + assign $1\muxid$1$next[1:0]$8503 \muxid$26 case - assign $1\muxid$1$next[1:0]$8191 \muxid$1 + assign $1\muxid$1$next[1:0]$8503 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8190 + update \muxid$1$next $0\muxid$1$next[1:0]$8502 end - attribute \src "libresoc.v:149322.3-149349.6" - process $proc$libresoc.v:149322$8192 + attribute \src "libresoc.v:151840.3-151867.6" + process $proc$libresoc.v:151840$8504 assign { } { } assign { } { } assign { } { } @@ -309423,19 +315882,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8193 $1\br_op__cia$2$next[63:0]$8201 - assign $0\br_op__fn_unit$4$next[11:0]$8194 $1\br_op__fn_unit$4$next[11:0]$8202 + assign $0\br_op__cia$2$next[63:0]$8505 $1\br_op__cia$2$next[63:0]$8513 + assign $0\br_op__fn_unit$4$next[11:0]$8506 $1\br_op__fn_unit$4$next[11:0]$8514 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8197 $1\br_op__insn$5$next[31:0]$8205 - assign $0\br_op__insn_type$3$next[6:0]$8198 $1\br_op__insn_type$3$next[6:0]$8206 - assign $0\br_op__is_32bit$9$next[0:0]$8199 $1\br_op__is_32bit$9$next[0:0]$8207 - assign $0\br_op__lk$8$next[0:0]$8200 $1\br_op__lk$8$next[0:0]$8208 - assign $0\br_op__imm_data__data$6$next[63:0]$8195 $2\br_op__imm_data__data$6$next[63:0]$8209 - assign $0\br_op__imm_data__ok$7$next[0:0]$8196 $2\br_op__imm_data__ok$7$next[0:0]$8210 - attribute \src "libresoc.v:149323.5-149323.29" + assign $0\br_op__insn$5$next[31:0]$8509 $1\br_op__insn$5$next[31:0]$8517 + assign $0\br_op__insn_type$3$next[6:0]$8510 $1\br_op__insn_type$3$next[6:0]$8518 + assign $0\br_op__is_32bit$9$next[0:0]$8511 $1\br_op__is_32bit$9$next[0:0]$8519 + assign $0\br_op__lk$8$next[0:0]$8512 $1\br_op__lk$8$next[0:0]$8520 + assign $0\br_op__imm_data__data$6$next[63:0]$8507 $2\br_op__imm_data__data$6$next[63:0]$8521 + assign $0\br_op__imm_data__ok$7$next[0:0]$8508 $2\br_op__imm_data__ok$7$next[0:0]$8522 + attribute \src "libresoc.v:151841.5-151841.29" switch \initial - attribute \src "libresoc.v:149323.9-149323.17" + attribute \src "libresoc.v:151841.9-151841.17" case 1'1 case end @@ -309451,7 +315910,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8207 $1\br_op__lk$8$next[0:0]$8208 $1\br_op__imm_data__ok$7$next[0:0]$8204 $1\br_op__imm_data__data$6$next[63:0]$8203 $1\br_op__insn$5$next[31:0]$8205 $1\br_op__fn_unit$4$next[11:0]$8202 $1\br_op__insn_type$3$next[6:0]$8206 $1\br_op__cia$2$next[63:0]$8201 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8519 $1\br_op__lk$8$next[0:0]$8520 $1\br_op__imm_data__ok$7$next[0:0]$8516 $1\br_op__imm_data__data$6$next[63:0]$8515 $1\br_op__insn$5$next[31:0]$8517 $1\br_op__fn_unit$4$next[11:0]$8514 $1\br_op__insn_type$3$next[6:0]$8518 $1\br_op__cia$2$next[63:0]$8513 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -309462,16 +315921,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8207 $1\br_op__lk$8$next[0:0]$8208 $1\br_op__imm_data__ok$7$next[0:0]$8204 $1\br_op__imm_data__data$6$next[63:0]$8203 $1\br_op__insn$5$next[31:0]$8205 $1\br_op__fn_unit$4$next[11:0]$8202 $1\br_op__insn_type$3$next[6:0]$8206 $1\br_op__cia$2$next[63:0]$8201 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8519 $1\br_op__lk$8$next[0:0]$8520 $1\br_op__imm_data__ok$7$next[0:0]$8516 $1\br_op__imm_data__data$6$next[63:0]$8515 $1\br_op__insn$5$next[31:0]$8517 $1\br_op__fn_unit$4$next[11:0]$8514 $1\br_op__insn_type$3$next[6:0]$8518 $1\br_op__cia$2$next[63:0]$8513 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8201 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[11:0]$8202 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8203 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8204 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8205 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8206 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8207 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8208 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8513 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[11:0]$8514 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8515 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8516 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8517 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8518 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8519 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8520 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -309479,34 +315938,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8209 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8210 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8521 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8522 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8209 $1\br_op__imm_data__data$6$next[63:0]$8203 - assign $2\br_op__imm_data__ok$7$next[0:0]$8210 $1\br_op__imm_data__ok$7$next[0:0]$8204 + assign $2\br_op__imm_data__data$6$next[63:0]$8521 $1\br_op__imm_data__data$6$next[63:0]$8515 + assign $2\br_op__imm_data__ok$7$next[0:0]$8522 $1\br_op__imm_data__ok$7$next[0:0]$8516 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8193 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8194 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8195 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8196 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8197 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8198 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8199 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8200 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8505 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8506 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8507 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8508 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8509 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8510 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8511 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8512 end - attribute \src "libresoc.v:149350.3-149368.6" - process $proc$libresoc.v:149350$8211 + attribute \src "libresoc.v:151868.3-151886.6" + process $proc$libresoc.v:151868$8523 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8212 $1\fast1$10$next[63:0]$8214 + assign $0\fast1$10$next[63:0]$8524 $1\fast1$10$next[63:0]$8526 assign { } { } - assign $0\fast1_ok$next[0:0]$8213 $2\fast1_ok$next[0:0]$8216 - attribute \src "libresoc.v:149351.5-149351.29" + assign $0\fast1_ok$next[0:0]$8525 $2\fast1_ok$next[0:0]$8528 + attribute \src "libresoc.v:151869.5-151869.29" switch \initial - attribute \src "libresoc.v:149351.9-149351.17" + attribute \src "libresoc.v:151869.9-151869.17" case 1'1 case end @@ -309516,41 +315975,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8215 $1\fast1$10$next[63:0]$8214 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8527 $1\fast1$10$next[63:0]$8526 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8215 $1\fast1$10$next[63:0]$8214 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8527 $1\fast1$10$next[63:0]$8526 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8214 \fast1$10 - assign $1\fast1_ok$next[0:0]$8215 \fast1_ok + assign $1\fast1$10$next[63:0]$8526 \fast1$10 + assign $1\fast1_ok$next[0:0]$8527 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8216 1'0 + assign $2\fast1_ok$next[0:0]$8528 1'0 case - assign $2\fast1_ok$next[0:0]$8216 $1\fast1_ok$next[0:0]$8215 + assign $2\fast1_ok$next[0:0]$8528 $1\fast1_ok$next[0:0]$8527 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8212 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8213 + update \fast1$10$next $0\fast1$10$next[63:0]$8524 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8525 end - attribute \src "libresoc.v:149369.3-149387.6" - process $proc$libresoc.v:149369$8217 + attribute \src "libresoc.v:151887.3-151905.6" + process $proc$libresoc.v:151887$8529 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8218 $1\fast2$11$next[63:0]$8220 + assign $0\fast2$11$next[63:0]$8530 $1\fast2$11$next[63:0]$8532 assign { } { } - assign $0\fast2_ok$next[0:0]$8219 $2\fast2_ok$next[0:0]$8222 - attribute \src "libresoc.v:149370.5-149370.29" + assign $0\fast2_ok$next[0:0]$8531 $2\fast2_ok$next[0:0]$8534 + attribute \src "libresoc.v:151888.5-151888.29" switch \initial - attribute \src "libresoc.v:149370.9-149370.17" + attribute \src "libresoc.v:151888.9-151888.17" case 1'1 case end @@ -309560,41 +316019,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8221 $1\fast2$11$next[63:0]$8220 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8533 $1\fast2$11$next[63:0]$8532 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8221 $1\fast2$11$next[63:0]$8220 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8533 $1\fast2$11$next[63:0]$8532 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8220 \fast2$11 - assign $1\fast2_ok$next[0:0]$8221 \fast2_ok + assign $1\fast2$11$next[63:0]$8532 \fast2$11 + assign $1\fast2_ok$next[0:0]$8533 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8222 1'0 + assign $2\fast2_ok$next[0:0]$8534 1'0 case - assign $2\fast2_ok$next[0:0]$8222 $1\fast2_ok$next[0:0]$8221 + assign $2\fast2_ok$next[0:0]$8534 $1\fast2_ok$next[0:0]$8533 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8218 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8219 + update \fast2$11$next $0\fast2$11$next[63:0]$8530 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8531 end - attribute \src "libresoc.v:149388.3-149406.6" - process $proc$libresoc.v:149388$8223 + attribute \src "libresoc.v:151906.3-151924.6" + process $proc$libresoc.v:151906$8535 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8224 $1\nia$next[63:0]$8226 + assign $0\nia$next[63:0]$8536 $1\nia$next[63:0]$8538 assign { } { } - assign $0\nia_ok$next[0:0]$8225 $2\nia_ok$next[0:0]$8228 - attribute \src "libresoc.v:149389.5-149389.29" + assign $0\nia_ok$next[0:0]$8537 $2\nia_ok$next[0:0]$8540 + attribute \src "libresoc.v:151907.5-151907.29" switch \initial - attribute \src "libresoc.v:149389.9-149389.17" + attribute \src "libresoc.v:151907.9-151907.17" case 1'1 case end @@ -309604,30 +316063,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8227 $1\nia$next[63:0]$8226 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8539 $1\nia$next[63:0]$8538 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8227 $1\nia$next[63:0]$8226 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8539 $1\nia$next[63:0]$8538 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8226 \nia - assign $1\nia_ok$next[0:0]$8227 \nia_ok + assign $1\nia$next[63:0]$8538 \nia + assign $1\nia_ok$next[0:0]$8539 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8228 1'0 + assign $2\nia_ok$next[0:0]$8540 1'0 case - assign $2\nia_ok$next[0:0]$8228 $1\nia_ok$next[0:0]$8227 + assign $2\nia_ok$next[0:0]$8540 $1\nia_ok$next[0:0]$8539 end sync always - update \nia$next $0\nia$next[63:0]$8224 - update \nia_ok$next $0\nia_ok$next[0:0]$8225 + update \nia$next $0\nia$next[63:0]$8536 + update \nia_ok$next $0\nia_ok$next[0:0]$8537 end - connect \$24 $and$libresoc.v:149221$8157_Y + connect \$24 $and$libresoc.v:151739$8469_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -309644,259 +316103,271 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:149426.1-150357.10" +attribute \src "libresoc.v:151944.1-152859.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" -module \pipe$32 - attribute \src "libresoc.v:150263.3-150281.6" - wire width 64 $0\fast1$10$next[63:0]$8320 - attribute \src "libresoc.v:150123.3-150124.35" - wire width 64 $0\fast1$10[63:0]$8266 - attribute \src "libresoc.v:149438.14-149438.47" - wire width 64 $0\fast1$10[63:0]$8345 - attribute \src "libresoc.v:150263.3-150281.6" - wire $0\fast1_ok$next[0:0]$8321 - attribute \src "libresoc.v:150125.3-150126.33" +module \pipe$64 + attribute \src "libresoc.v:152762.3-152780.6" + wire width 64 $0\fast1$7$next[63:0]$8628 + attribute \src "libresoc.v:152615.3-152616.33" + wire width 64 $0\fast1$7[63:0]$8580 + attribute \src "libresoc.v:151958.14-151958.46" + wire width 64 $0\fast1$7[63:0]$8652 + attribute \src "libresoc.v:152762.3-152780.6" + wire $0\fast1_ok$next[0:0]$8627 + attribute \src "libresoc.v:152617.3-152618.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:150282.3-150300.6" - wire width 64 $0\fast2$11$next[63:0]$8326 - attribute \src "libresoc.v:150119.3-150120.35" - wire width 64 $0\fast2$11[63:0]$8263 - attribute \src "libresoc.v:149454.14-149454.47" - wire width 64 $0\fast2$11[63:0]$8348 - attribute \src "libresoc.v:150282.3-150300.6" - wire $0\fast2_ok$next[0:0]$8327 - attribute \src "libresoc.v:150121.3-150122.33" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149427.7-149427.20" + attribute \src "libresoc.v:151945.7-151945.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150320.3-150338.6" - wire width 64 $0\msr$next[63:0]$8338 - attribute \src "libresoc.v:150111.3-150112.23" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:150320.3-150338.6" - wire $0\msr_ok$next[0:0]$8339 - attribute \src "libresoc.v:150113.3-150114.29" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:150211.3-150223.6" - wire width 2 $0\muxid$1$next[1:0]$8294 - attribute \src "libresoc.v:150147.3-150148.33" - wire width 2 $0\muxid$1[1:0]$8287 - attribute \src "libresoc.v:149722.13-149722.29" - wire width 2 $0\muxid$1[1:0]$8353 - attribute \src "libresoc.v:150301.3-150319.6" - wire width 64 $0\nia$next[63:0]$8332 - attribute \src "libresoc.v:150115.3-150116.23" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:150301.3-150319.6" - wire $0\nia_ok$next[0:0]$8333 - attribute \src "libresoc.v:150117.3-150118.29" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:150244.3-150262.6" - wire width 64 $0\o$next[63:0]$8314 - attribute \src "libresoc.v:150127.3-150128.19" + attribute \src "libresoc.v:152695.3-152707.6" + wire width 2 $0\muxid$1$next[1:0]$8603 + attribute \src "libresoc.v:152635.3-152636.33" + wire width 2 $0\muxid$1[1:0]$8596 + attribute \src "libresoc.v:151972.13-151972.29" + wire width 2 $0\muxid$1[1:0]$8655 + attribute \src "libresoc.v:152724.3-152742.6" + wire width 64 $0\o$next[63:0]$8615 + attribute \src "libresoc.v:152623.3-152624.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150244.3-150262.6" - wire $0\o_ok$next[0:0]$8315 - attribute \src "libresoc.v:150129.3-150130.25" + attribute \src "libresoc.v:152724.3-152742.6" + wire $0\o_ok$next[0:0]$8616 + attribute \src "libresoc.v:152625.3-152626.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:150193.3-150210.6" - wire $0\r_busy$next[0:0]$8290 - attribute \src "libresoc.v:150149.3-150150.29" + attribute \src "libresoc.v:152677.3-152694.6" + wire $0\r_busy$next[0:0]$8599 + attribute \src "libresoc.v:152637.3-152638.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:150224.3-150243.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$8297 - attribute \src "libresoc.v:150139.3-150140.47" - wire width 64 $0\trap_op__cia$6[63:0]$8279 - attribute \src "libresoc.v:149783.14-149783.53" - wire width 64 $0\trap_op__cia$6[63:0]$8360 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 12 $0\trap_op__fn_unit$3$next[11:0]$8298 - attribute \src "libresoc.v:150133.3-150134.55" - wire width 12 $0\trap_op__fn_unit$3[11:0]$8273 - attribute \src "libresoc.v:149831.14-149831.44" - wire width 12 $0\trap_op__fn_unit$3[11:0]$8362 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$8299 - attribute \src "libresoc.v:150135.3-150136.49" - wire width 32 $0\trap_op__insn$4[31:0]$8275 - attribute \src "libresoc.v:149840.14-149840.39" - wire width 32 $0\trap_op__insn$4[31:0]$8364 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$8300 - attribute \src "libresoc.v:150131.3-150132.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$8271 - attribute \src "libresoc.v:149995.13-149995.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$8366 - attribute \src "libresoc.v:150224.3-150243.6" - wire $0\trap_op__is_32bit$7$next[0:0]$8301 - attribute \src "libresoc.v:150141.3-150142.57" - wire $0\trap_op__is_32bit$7[0:0]$8281 - attribute \src "libresoc.v:150080.7-150080.35" - wire $0\trap_op__is_32bit$7[0:0]$8368 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$8302 - attribute \src "libresoc.v:150137.3-150138.47" - wire width 64 $0\trap_op__msr$5[63:0]$8277 - attribute \src "libresoc.v:150089.14-150089.53" - wire width 64 $0\trap_op__msr$5[63:0]$8370 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$8303 - attribute \src "libresoc.v:150145.3-150146.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$8285 - attribute \src "libresoc.v:150098.14-150098.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$8372 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 7 $0\trap_op__traptype$8$next[6:0]$8304 - attribute \src "libresoc.v:150143.3-150144.57" - wire width 7 $0\trap_op__traptype$8[6:0]$8283 - attribute \src "libresoc.v:150107.13-150107.42" - wire width 7 $0\trap_op__traptype$8[6:0]$8374 - attribute \src "libresoc.v:150263.3-150281.6" - wire width 64 $1\fast1$10$next[63:0]$8322 - attribute \src "libresoc.v:150263.3-150281.6" - wire $1\fast1_ok$next[0:0]$8323 - attribute \src "libresoc.v:149445.7-149445.22" + attribute \src "libresoc.v:152743.3-152761.6" + wire width 64 $0\spr1$6$next[63:0]$8621 + attribute \src "libresoc.v:152619.3-152620.31" + wire width 64 $0\spr1$6[63:0]$8583 + attribute \src "libresoc.v:152017.14-152017.45" + wire width 64 $0\spr1$6[63:0]$8660 + attribute \src "libresoc.v:152743.3-152761.6" + wire $0\spr1_ok$next[0:0]$8622 + attribute \src "libresoc.v:152621.3-152622.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:152708.3-152723.6" + wire width 12 $0\spr_op__fn_unit$3$next[11:0]$8606 + attribute \src "libresoc.v:152629.3-152630.53" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8590 + attribute \src "libresoc.v:152302.14-152302.43" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8663 + attribute \src "libresoc.v:152708.3-152723.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8607 + attribute \src "libresoc.v:152631.3-152632.47" + wire width 32 $0\spr_op__insn$4[31:0]$8592 + attribute \src "libresoc.v:152311.14-152311.38" + wire width 32 $0\spr_op__insn$4[31:0]$8665 + attribute \src "libresoc.v:152708.3-152723.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8608 + attribute \src "libresoc.v:152627.3-152628.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8588 + attribute \src "libresoc.v:152466.13-152466.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8667 + attribute \src "libresoc.v:152708.3-152723.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8609 + attribute \src "libresoc.v:152633.3-152634.55" + wire $0\spr_op__is_32bit$5[0:0]$8594 + attribute \src "libresoc.v:152551.7-152551.34" + wire $0\spr_op__is_32bit$5[0:0]$8669 + attribute \src "libresoc.v:152819.3-152837.6" + wire width 2 $0\xer_ca$10$next[1:0]$8645 + attribute \src "libresoc.v:152603.3-152604.37" + wire width 2 $0\xer_ca$10[1:0]$8571 + attribute \src "libresoc.v:152558.13-152558.31" + wire width 2 $0\xer_ca$10[1:0]$8671 + attribute \src "libresoc.v:152819.3-152837.6" + wire $0\xer_ca_ok$next[0:0]$8646 + attribute \src "libresoc.v:152605.3-152606.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:152800.3-152818.6" + wire width 2 $0\xer_ov$9$next[1:0]$8640 + attribute \src "libresoc.v:152607.3-152608.35" + wire width 2 $0\xer_ov$9[1:0]$8574 + attribute \src "libresoc.v:152576.13-152576.30" + wire width 2 $0\xer_ov$9[1:0]$8674 + attribute \src "libresoc.v:152800.3-152818.6" + wire $0\xer_ov_ok$next[0:0]$8639 + attribute \src "libresoc.v:152609.3-152610.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:152781.3-152799.6" + wire $0\xer_so$8$next[0:0]$8634 + attribute \src "libresoc.v:152611.3-152612.35" + wire $0\xer_so$8[0:0]$8577 + attribute \src "libresoc.v:152592.7-152592.24" + wire $0\xer_so$8[0:0]$8677 + attribute \src "libresoc.v:152781.3-152799.6" + wire $0\xer_so_ok$next[0:0]$8633 + attribute \src "libresoc.v:152613.3-152614.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:152762.3-152780.6" + wire width 64 $1\fast1$7$next[63:0]$8630 + attribute \src "libresoc.v:152762.3-152780.6" + wire $1\fast1_ok$next[0:0]$8629 + attribute \src "libresoc.v:151963.7-151963.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:150282.3-150300.6" - wire width 64 $1\fast2$11$next[63:0]$8328 - attribute \src "libresoc.v:150282.3-150300.6" - wire $1\fast2_ok$next[0:0]$8329 - attribute \src "libresoc.v:149461.7-149461.22" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:150320.3-150338.6" - wire width 64 $1\msr$next[63:0]$8340 - attribute \src "libresoc.v:149706.14-149706.40" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:150320.3-150338.6" - wire $1\msr_ok$next[0:0]$8341 - attribute \src "libresoc.v:149713.7-149713.20" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:150211.3-150223.6" - wire width 2 $1\muxid$1$next[1:0]$8295 - attribute \src "libresoc.v:150301.3-150319.6" - wire width 64 $1\nia$next[63:0]$8334 - attribute \src "libresoc.v:149735.14-149735.40" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:150301.3-150319.6" - wire $1\nia_ok$next[0:0]$8335 - attribute \src "libresoc.v:149742.7-149742.20" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:150244.3-150262.6" - wire width 64 $1\o$next[63:0]$8316 - attribute \src "libresoc.v:149749.14-149749.38" + attribute \src "libresoc.v:152695.3-152707.6" + wire width 2 $1\muxid$1$next[1:0]$8604 + attribute \src "libresoc.v:152724.3-152742.6" + wire width 64 $1\o$next[63:0]$8617 + attribute \src "libresoc.v:151985.14-151985.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150244.3-150262.6" - wire $1\o_ok$next[0:0]$8317 - attribute \src "libresoc.v:149756.7-149756.18" + attribute \src "libresoc.v:152724.3-152742.6" + wire $1\o_ok$next[0:0]$8618 + attribute \src "libresoc.v:151992.7-151992.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:150193.3-150210.6" - wire $1\r_busy$next[0:0]$8291 - attribute \src "libresoc.v:149770.7-149770.20" + attribute \src "libresoc.v:152677.3-152694.6" + wire $1\r_busy$next[0:0]$8600 + attribute \src "libresoc.v:152006.7-152006.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:150224.3-150243.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$8305 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 12 $1\trap_op__fn_unit$3$next[11:0]$8306 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$8307 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$8308 - attribute \src "libresoc.v:150224.3-150243.6" - wire $1\trap_op__is_32bit$7$next[0:0]$8309 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$8310 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$8311 - attribute \src "libresoc.v:150224.3-150243.6" - wire width 7 $1\trap_op__traptype$8$next[6:0]$8312 - attribute \src "libresoc.v:150263.3-150281.6" - wire $2\fast1_ok$next[0:0]$8324 - attribute \src "libresoc.v:150282.3-150300.6" - wire $2\fast2_ok$next[0:0]$8330 - attribute \src "libresoc.v:150320.3-150338.6" - wire $2\msr_ok$next[0:0]$8342 - attribute \src "libresoc.v:150301.3-150319.6" - wire $2\nia_ok$next[0:0]$8336 - attribute \src "libresoc.v:150244.3-150262.6" - wire $2\o_ok$next[0:0]$8318 - attribute \src "libresoc.v:150193.3-150210.6" - wire $2\r_busy$next[0:0]$8292 - attribute \src "libresoc.v:150110.18-150110.118" - wire $and$libresoc.v:150110$8257_Y + attribute \src "libresoc.v:152743.3-152761.6" + wire width 64 $1\spr1$6$next[63:0]$8623 + attribute \src "libresoc.v:152743.3-152761.6" + wire $1\spr1_ok$next[0:0]$8624 + attribute \src "libresoc.v:152022.7-152022.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:152708.3-152723.6" + wire width 12 $1\spr_op__fn_unit$3$next[11:0]$8610 + attribute \src "libresoc.v:152708.3-152723.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8611 + attribute \src "libresoc.v:152708.3-152723.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8612 + attribute \src "libresoc.v:152708.3-152723.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8613 + attribute \src "libresoc.v:152819.3-152837.6" + wire width 2 $1\xer_ca$10$next[1:0]$8647 + attribute \src "libresoc.v:152819.3-152837.6" + wire $1\xer_ca_ok$next[0:0]$8648 + attribute \src "libresoc.v:152565.7-152565.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:152800.3-152818.6" + wire width 2 $1\xer_ov$9$next[1:0]$8642 + attribute \src "libresoc.v:152800.3-152818.6" + wire $1\xer_ov_ok$next[0:0]$8641 + attribute \src "libresoc.v:152581.7-152581.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:152781.3-152799.6" + wire $1\xer_so$8$next[0:0]$8636 + attribute \src "libresoc.v:152781.3-152799.6" + wire $1\xer_so_ok$next[0:0]$8635 + attribute \src "libresoc.v:152597.7-152597.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:152762.3-152780.6" + wire $2\fast1_ok$next[0:0]$8631 + attribute \src "libresoc.v:152724.3-152742.6" + wire $2\o_ok$next[0:0]$8619 + attribute \src "libresoc.v:152677.3-152694.6" + wire $2\r_busy$next[0:0]$8601 + attribute \src "libresoc.v:152743.3-152761.6" + wire $2\spr1_ok$next[0:0]$8625 + attribute \src "libresoc.v:152819.3-152837.6" + wire $2\xer_ca_ok$next[0:0]$8649 + attribute \src "libresoc.v:152800.3-152818.6" + wire $2\xer_ov_ok$next[0:0]$8643 + attribute \src "libresoc.v:152781.3-152799.6" + wire $2\xer_so_ok$next[0:0]$8637 + attribute \src "libresoc.v:152602.18-152602.118" + wire $and$libresoc.v:152602$8569_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast2_ok$next - attribute \src "libresoc.v:149427.7-149427.15" + attribute \src "libresoc.v:151945.7-151945.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast1_ok + wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_msr_ok + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid + wire width 2 \spr_main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$17 + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -309911,7 +316382,7 @@ module \pipe$32 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit + wire width 12 \spr_main_spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -309926,11 +316397,11 @@ module \pipe$32 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_trap_op__fn_unit$14 + wire width 12 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn + wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$15 + wire width 32 \spr_main_spr_op__insn$14 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -310006,7 +316477,7 @@ module \pipe$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type + wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -310082,97 +316553,29 @@ module \pipe$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr$20 + wire width 7 \spr_main_spr_op__insn_type$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__traptype + wire \spr_main_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__traptype$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 36 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \msr$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 37 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \msr_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \msr_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 19 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 18 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 17 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 34 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 35 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \nia_ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 28 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next + wire \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra + wire width 2 \spr_main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \spr_main_xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \trap_op__cia$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$6$next + wire width 2 \spr_main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \spr_main_xer_ov$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \spr_main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -310187,7 +316590,7 @@ module \pipe$32 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \trap_op__fn_unit + wire width 12 input 6 \spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -310202,7 +316605,7 @@ module \pipe$32 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$28 + wire width 12 \spr_op__fn_unit$26 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -310217,17 +316620,17 @@ module \pipe$32 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 21 \trap_op__fn_unit$3 + wire width 12 output 19 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \trap_op__fn_unit$3$next + wire width 12 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \trap_op__insn + wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$29 + wire width 32 \spr_op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \trap_op__insn$4 + wire width 32 output 20 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$4$next + wire width 32 \spr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -310303,7 +316706,7 @@ module \pipe$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \trap_op__insn_type + wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -310379,9 +316782,9 @@ module \pipe$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \trap_op__insn_type$2 + wire width 7 output 18 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$2$next + wire width 7 \spr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -310457,415 +316860,399 @@ module \pipe$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \trap_op__is_32bit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \trap_op__msr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 12 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 27 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$9$next + wire width 7 \spr_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 11 \trap_op__traptype + wire input 8 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$33 + wire \spr_op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \trap_op__traptype$8 + wire output 21 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$8$next + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:150110$8257 + cell $and $and$libresoc.v:152602$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 + connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:150110$8257_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:150151.13-150184.4" - cell \main$35 \main - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__cia$6 \main_trap_op__cia$17 - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__insn$4 \main_trap_op__insn$15 - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__msr$5 \main_trap_op__msr$16 - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__traptype$8 \main_trap_op__traptype$19 + connect \Y $and$libresoc.v:152602$8569_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150185.10-150188.4" - cell \n$34 \n + attribute \src "libresoc.v:152639.10-152642.4" + cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:150189.10-150192.4" - cell \p$33 \p + attribute \src "libresoc.v:152643.10-152646.4" + cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:149427.7-149427.20" - process $proc$libresoc.v:149427$8343 + attribute \module_not_derived 1 + attribute \src "libresoc.v:152647.12-152676.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:151945.7-151945.20" + process $proc$libresoc.v:151945$8650 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149438.14-149438.47" - process $proc$libresoc.v:149438$8344 + attribute \src "libresoc.v:151958.14-151958.46" + process $proc$libresoc.v:151958$8651 assign { } { } - assign $0\fast1$10[63:0]$8345 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8652 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8345 + update \fast1$7 $0\fast1$7[63:0]$8652 end - attribute \src "libresoc.v:149445.7-149445.22" - process $proc$libresoc.v:149445$8346 + attribute \src "libresoc.v:151963.7-151963.22" + process $proc$libresoc.v:151963$8653 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:149454.14-149454.47" - process $proc$libresoc.v:149454$8347 + attribute \src "libresoc.v:151972.13-151972.29" + process $proc$libresoc.v:151972$8654 assign { } { } - assign $0\fast2$11[63:0]$8348 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\muxid$1[1:0]$8655 2'00 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8348 + update \muxid$1 $0\muxid$1[1:0]$8655 end - attribute \src "libresoc.v:149461.7-149461.22" - process $proc$libresoc.v:149461$8349 + attribute \src "libresoc.v:151985.14-151985.38" + process $proc$libresoc.v:151985$8656 assign { } { } - assign $1\fast2_ok[0:0] 1'0 - sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] - end - attribute \src "libresoc.v:149706.14-149706.40" - process $proc$libresoc.v:149706$8350 - assign { } { } - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr $1\msr[63:0] - end - attribute \src "libresoc.v:149713.7-149713.20" - process $proc$libresoc.v:149713$8351 - assign { } { } - assign $1\msr_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \msr_ok $1\msr_ok[0:0] + update \o $1\o[63:0] end - attribute \src "libresoc.v:149722.13-149722.29" - process $proc$libresoc.v:149722$8352 + attribute \src "libresoc.v:151992.7-151992.18" + process $proc$libresoc.v:151992$8657 assign { } { } - assign $0\muxid$1[1:0]$8353 2'00 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8353 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:149735.14-149735.40" - process $proc$libresoc.v:149735$8354 + attribute \src "libresoc.v:152006.7-152006.20" + process $proc$libresoc.v:152006$8658 assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \nia $1\nia[63:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:149742.7-149742.20" - process $proc$libresoc.v:149742$8355 + attribute \src "libresoc.v:152017.14-152017.45" + process $proc$libresoc.v:152017$8659 assign { } { } - assign $1\nia_ok[0:0] 1'0 + assign $0\spr1$6[63:0]$8660 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \nia_ok $1\nia_ok[0:0] + update \spr1$6 $0\spr1$6[63:0]$8660 end - attribute \src "libresoc.v:149749.14-149749.38" - process $proc$libresoc.v:149749$8356 + attribute \src "libresoc.v:152022.7-152022.21" + process $proc$libresoc.v:152022$8661 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1_ok[0:0] 1'0 sync always sync init - update \o $1\o[63:0] + update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:149756.7-149756.18" - process $proc$libresoc.v:149756$8357 + attribute \src "libresoc.v:152302.14-152302.43" + process $proc$libresoc.v:152302$8662 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\spr_op__fn_unit$3[11:0]$8663 12'000000000000 sync always sync init - update \o_ok $1\o_ok[0:0] + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8663 end - attribute \src "libresoc.v:149770.7-149770.20" - process $proc$libresoc.v:149770$8358 + attribute \src "libresoc.v:152311.14-152311.38" + process $proc$libresoc.v:152311$8664 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\spr_op__insn$4[31:0]$8665 0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8665 end - attribute \src "libresoc.v:149783.14-149783.53" - process $proc$libresoc.v:149783$8359 + attribute \src "libresoc.v:152466.13-152466.42" + process $proc$libresoc.v:152466$8666 assign { } { } - assign $0\trap_op__cia$6[63:0]$8360 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr_op__insn_type$2[6:0]$8667 7'0000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$8360 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8667 end - attribute \src "libresoc.v:149831.14-149831.44" - process $proc$libresoc.v:149831$8361 + attribute \src "libresoc.v:152551.7-152551.34" + process $proc$libresoc.v:152551$8668 assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$8362 12'000000000000 + assign $0\spr_op__is_32bit$5[0:0]$8669 1'0 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$8362 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8669 end - attribute \src "libresoc.v:149840.14-149840.39" - process $proc$libresoc.v:149840$8363 + attribute \src "libresoc.v:152558.13-152558.31" + process $proc$libresoc.v:152558$8670 assign { } { } - assign $0\trap_op__insn$4[31:0]$8364 0 + assign $0\xer_ca$10[1:0]$8671 2'00 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$8364 + update \xer_ca$10 $0\xer_ca$10[1:0]$8671 end - attribute \src "libresoc.v:149995.13-149995.43" - process $proc$libresoc.v:149995$8365 + attribute \src "libresoc.v:152565.7-152565.23" + process $proc$libresoc.v:152565$8672 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$8366 7'0000000 + assign $1\xer_ca_ok[0:0] 1'0 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$8366 + update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:150080.7-150080.35" - process $proc$libresoc.v:150080$8367 + attribute \src "libresoc.v:152576.13-152576.30" + process $proc$libresoc.v:152576$8673 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$8368 1'0 + assign $0\xer_ov$9[1:0]$8674 2'00 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$8368 + update \xer_ov$9 $0\xer_ov$9[1:0]$8674 end - attribute \src "libresoc.v:150089.14-150089.53" - process $proc$libresoc.v:150089$8369 + attribute \src "libresoc.v:152581.7-152581.23" + process $proc$libresoc.v:152581$8675 assign { } { } - assign $0\trap_op__msr$5[63:0]$8370 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\xer_ov_ok[0:0] 1'0 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$8370 + update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:150098.14-150098.46" - process $proc$libresoc.v:150098$8371 + attribute \src "libresoc.v:152592.7-152592.24" + process $proc$libresoc.v:152592$8676 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$8372 13'0000000000000 + assign $0\xer_so$8[0:0]$8677 1'0 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$8372 + update \xer_so$8 $0\xer_so$8[0:0]$8677 end - attribute \src "libresoc.v:150107.13-150107.42" - process $proc$libresoc.v:150107$8373 + attribute \src "libresoc.v:152597.7-152597.23" + process $proc$libresoc.v:152597$8678 assign { } { } - assign $0\trap_op__traptype$8[6:0]$8374 7'0000000 + assign $1\xer_so_ok[0:0] 1'0 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$8374 + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:150111.3-150112.23" - process $proc$libresoc.v:150111$8258 + attribute \src "libresoc.v:152603.3-152604.37" + process $proc$libresoc.v:152603$8570 assign { } { } - assign $0\msr[63:0] \msr$next + assign $0\xer_ca$10[1:0]$8571 \xer_ca$10$next sync posedge \coresync_clk - update \msr $0\msr[63:0] + update \xer_ca$10 $0\xer_ca$10[1:0]$8571 end - attribute \src "libresoc.v:150113.3-150114.29" - process $proc$libresoc.v:150113$8259 + attribute \src "libresoc.v:152605.3-152606.35" + process $proc$libresoc.v:152605$8572 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:150115.3-150116.23" - process $proc$libresoc.v:150115$8260 + attribute \src "libresoc.v:152607.3-152608.35" + process $proc$libresoc.v:152607$8573 assign { } { } - assign $0\nia[63:0] \nia$next + assign $0\xer_ov$9[1:0]$8574 \xer_ov$9$next sync posedge \coresync_clk - update \nia $0\nia[63:0] + update \xer_ov$9 $0\xer_ov$9[1:0]$8574 end - attribute \src "libresoc.v:150117.3-150118.29" - process $proc$libresoc.v:150117$8261 + attribute \src "libresoc.v:152609.3-152610.35" + process $proc$libresoc.v:152609$8575 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:150119.3-150120.35" - process $proc$libresoc.v:150119$8262 + attribute \src "libresoc.v:152611.3-152612.35" + process $proc$libresoc.v:152611$8576 assign { } { } - assign $0\fast2$11[63:0]$8263 \fast2$11$next + assign $0\xer_so$8[0:0]$8577 \xer_so$8$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8263 + update \xer_so$8 $0\xer_so$8[0:0]$8577 end - attribute \src "libresoc.v:150121.3-150122.33" - process $proc$libresoc.v:150121$8264 + attribute \src "libresoc.v:152613.3-152614.35" + process $proc$libresoc.v:152613$8578 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:150123.3-150124.35" - process $proc$libresoc.v:150123$8265 + attribute \src "libresoc.v:152615.3-152616.33" + process $proc$libresoc.v:152615$8579 assign { } { } - assign $0\fast1$10[63:0]$8266 \fast1$10$next + assign $0\fast1$7[63:0]$8580 \fast1$7$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8266 + update \fast1$7 $0\fast1$7[63:0]$8580 end - attribute \src "libresoc.v:150125.3-150126.33" - process $proc$libresoc.v:150125$8267 + attribute \src "libresoc.v:152617.3-152618.33" + process $proc$libresoc.v:152617$8581 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:150127.3-150128.19" - process $proc$libresoc.v:150127$8268 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:150129.3-150130.25" - process $proc$libresoc.v:150129$8269 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:150131.3-150132.59" - process $proc$libresoc.v:150131$8270 + attribute \src "libresoc.v:152619.3-152620.31" + process $proc$libresoc.v:152619$8582 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$8271 \trap_op__insn_type$2$next + assign $0\spr1$6[63:0]$8583 \spr1$6$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$8271 + update \spr1$6 $0\spr1$6[63:0]$8583 end - attribute \src "libresoc.v:150133.3-150134.55" - process $proc$libresoc.v:150133$8272 + attribute \src "libresoc.v:152621.3-152622.31" + process $proc$libresoc.v:152621$8584 assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$8273 \trap_op__fn_unit$3$next + assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$8273 + update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:150135.3-150136.49" - process $proc$libresoc.v:150135$8274 + attribute \src "libresoc.v:152623.3-152624.19" + process $proc$libresoc.v:152623$8585 assign { } { } - assign $0\trap_op__insn$4[31:0]$8275 \trap_op__insn$4$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$8275 + update \o $0\o[63:0] end - attribute \src "libresoc.v:150137.3-150138.47" - process $proc$libresoc.v:150137$8276 + attribute \src "libresoc.v:152625.3-152626.25" + process $proc$libresoc.v:152625$8586 assign { } { } - assign $0\trap_op__msr$5[63:0]$8277 \trap_op__msr$5$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$8277 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:150139.3-150140.47" - process $proc$libresoc.v:150139$8278 + attribute \src "libresoc.v:152627.3-152628.57" + process $proc$libresoc.v:152627$8587 assign { } { } - assign $0\trap_op__cia$6[63:0]$8279 \trap_op__cia$6$next + assign $0\spr_op__insn_type$2[6:0]$8588 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$8279 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8588 end - attribute \src "libresoc.v:150141.3-150142.57" - process $proc$libresoc.v:150141$8280 + attribute \src "libresoc.v:152629.3-152630.53" + process $proc$libresoc.v:152629$8589 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$8281 \trap_op__is_32bit$7$next + assign $0\spr_op__fn_unit$3[11:0]$8590 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$8281 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8590 end - attribute \src "libresoc.v:150143.3-150144.57" - process $proc$libresoc.v:150143$8282 + attribute \src "libresoc.v:152631.3-152632.47" + process $proc$libresoc.v:152631$8591 assign { } { } - assign $0\trap_op__traptype$8[6:0]$8283 \trap_op__traptype$8$next + assign $0\spr_op__insn$4[31:0]$8592 \spr_op__insn$4$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$8283 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8592 end - attribute \src "libresoc.v:150145.3-150146.57" - process $proc$libresoc.v:150145$8284 + attribute \src "libresoc.v:152633.3-152634.55" + process $proc$libresoc.v:152633$8593 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$8285 \trap_op__trapaddr$9$next + assign $0\spr_op__is_32bit$5[0:0]$8594 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$8285 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8594 end - attribute \src "libresoc.v:150147.3-150148.33" - process $proc$libresoc.v:150147$8286 + attribute \src "libresoc.v:152635.3-152636.33" + process $proc$libresoc.v:152635$8595 assign { } { } - assign $0\muxid$1[1:0]$8287 \muxid$1$next + assign $0\muxid$1[1:0]$8596 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8287 + update \muxid$1 $0\muxid$1[1:0]$8596 end - attribute \src "libresoc.v:150149.3-150150.29" - process $proc$libresoc.v:150149$8288 + attribute \src "libresoc.v:152637.3-152638.29" + process $proc$libresoc.v:152637$8597 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:150193.3-150210.6" - process $proc$libresoc.v:150193$8289 + attribute \src "libresoc.v:152677.3-152694.6" + process $proc$libresoc.v:152677$8598 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8290 $2\r_busy$next[0:0]$8292 - attribute \src "libresoc.v:150194.5-150194.29" + assign $0\r_busy$next[0:0]$8599 $2\r_busy$next[0:0]$8601 + attribute \src "libresoc.v:152678.5-152678.29" switch \initial - attribute \src "libresoc.v:150194.9-150194.17" + attribute \src "libresoc.v:152678.9-152678.17" case 1'1 case end @@ -310874,34 +317261,34 @@ module \pipe$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8291 1'1 + assign $1\r_busy$next[0:0]$8600 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8291 1'0 + assign $1\r_busy$next[0:0]$8600 1'0 case - assign $1\r_busy$next[0:0]$8291 \r_busy + assign $1\r_busy$next[0:0]$8600 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8292 1'0 + assign $2\r_busy$next[0:0]$8601 1'0 case - assign $2\r_busy$next[0:0]$8292 $1\r_busy$next[0:0]$8291 + assign $2\r_busy$next[0:0]$8601 $1\r_busy$next[0:0]$8600 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8290 + update \r_busy$next $0\r_busy$next[0:0]$8599 end - attribute \src "libresoc.v:150211.3-150223.6" - process $proc$libresoc.v:150211$8293 + attribute \src "libresoc.v:152695.3-152707.6" + process $proc$libresoc.v:152695$8602 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8294 $1\muxid$1$next[1:0]$8295 - attribute \src "libresoc.v:150212.5-150212.29" + assign $0\muxid$1$next[1:0]$8603 $1\muxid$1$next[1:0]$8604 + attribute \src "libresoc.v:152696.5-152696.29" switch \initial - attribute \src "libresoc.v:150212.9-150212.17" + attribute \src "libresoc.v:152696.9-152696.17" case 1'1 case end @@ -310910,23 +317297,19 @@ module \pipe$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8295 \muxid$26 + assign $1\muxid$1$next[1:0]$8604 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8295 \muxid$26 + assign $1\muxid$1$next[1:0]$8604 \muxid$24 case - assign $1\muxid$1$next[1:0]$8295 \muxid$1 + assign $1\muxid$1$next[1:0]$8604 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8294 + update \muxid$1$next $0\muxid$1$next[1:0]$8603 end - attribute \src "libresoc.v:150224.3-150243.6" - process $proc$libresoc.v:150224$8296 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:152708.3-152723.6" + process $proc$libresoc.v:152708$8605 assign { } { } assign { } { } assign { } { } @@ -310935,21 +317318,13 @@ module \pipe$32 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trap_op__cia$6$next[63:0]$8297 $1\trap_op__cia$6$next[63:0]$8305 - assign $0\trap_op__fn_unit$3$next[11:0]$8298 $1\trap_op__fn_unit$3$next[11:0]$8306 - assign $0\trap_op__insn$4$next[31:0]$8299 $1\trap_op__insn$4$next[31:0]$8307 - assign $0\trap_op__insn_type$2$next[6:0]$8300 $1\trap_op__insn_type$2$next[6:0]$8308 - assign $0\trap_op__is_32bit$7$next[0:0]$8301 $1\trap_op__is_32bit$7$next[0:0]$8309 - assign $0\trap_op__msr$5$next[63:0]$8302 $1\trap_op__msr$5$next[63:0]$8310 - assign $0\trap_op__trapaddr$9$next[12:0]$8303 $1\trap_op__trapaddr$9$next[12:0]$8311 - assign $0\trap_op__traptype$8$next[6:0]$8304 $1\trap_op__traptype$8$next[6:0]$8312 - attribute \src "libresoc.v:150225.5-150225.29" + assign $0\spr_op__fn_unit$3$next[11:0]$8606 $1\spr_op__fn_unit$3$next[11:0]$8610 + assign $0\spr_op__insn$4$next[31:0]$8607 $1\spr_op__insn$4$next[31:0]$8611 + assign $0\spr_op__insn_type$2$next[6:0]$8608 $1\spr_op__insn_type$2$next[6:0]$8612 + assign $0\spr_op__is_32bit$5$next[0:0]$8609 $1\spr_op__is_32bit$5$next[0:0]$8613 + attribute \src "libresoc.v:152709.5-152709.29" switch \initial - attribute \src "libresoc.v:150225.9-150225.17" + attribute \src "libresoc.v:152709.9-152709.17" case 1'1 case end @@ -310961,54 +317336,82 @@ module \pipe$32 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\trap_op__trapaddr$9$next[12:0]$8311 $1\trap_op__traptype$8$next[6:0]$8312 $1\trap_op__is_32bit$7$next[0:0]$8309 $1\trap_op__cia$6$next[63:0]$8305 $1\trap_op__msr$5$next[63:0]$8310 $1\trap_op__insn$4$next[31:0]$8307 $1\trap_op__fn_unit$3$next[11:0]$8306 $1\trap_op__insn_type$2$next[6:0]$8308 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8613 $1\spr_op__insn$4$next[31:0]$8611 $1\spr_op__fn_unit$3$next[11:0]$8610 $1\spr_op__insn_type$2$next[6:0]$8612 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8613 $1\spr_op__insn$4$next[31:0]$8611 $1\spr_op__fn_unit$3$next[11:0]$8610 $1\spr_op__insn_type$2$next[6:0]$8612 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[11:0]$8610 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8611 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8612 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8613 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8606 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8607 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8608 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8609 + end + attribute \src "libresoc.v:152724.3-152742.6" + process $proc$libresoc.v:152724$8614 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8615 $1\o$next[63:0]$8617 + assign { } { } + assign $0\o_ok$next[0:0]$8616 $2\o_ok$next[0:0]$8619 + attribute \src "libresoc.v:152725.5-152725.29" + switch \initial + attribute \src "libresoc.v:152725.9-152725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\o_ok$next[0:0]$8618 $1\o$next[63:0]$8617 } { \o_ok$30 \o$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } + assign { $1\o_ok$next[0:0]$8618 $1\o$next[63:0]$8617 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8617 \o + assign $1\o_ok$next[0:0]$8618 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $1\trap_op__trapaddr$9$next[12:0]$8311 $1\trap_op__traptype$8$next[6:0]$8312 $1\trap_op__is_32bit$7$next[0:0]$8309 $1\trap_op__cia$6$next[63:0]$8305 $1\trap_op__msr$5$next[63:0]$8310 $1\trap_op__insn$4$next[31:0]$8307 $1\trap_op__fn_unit$3$next[11:0]$8306 $1\trap_op__insn_type$2$next[6:0]$8308 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + assign $2\o_ok$next[0:0]$8619 1'0 case - assign $1\trap_op__cia$6$next[63:0]$8305 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[11:0]$8306 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$8307 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$8308 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$8309 \trap_op__is_32bit$7 - assign $1\trap_op__msr$5$next[63:0]$8310 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$8311 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[6:0]$8312 \trap_op__traptype$8 + assign $2\o_ok$next[0:0]$8619 $1\o_ok$next[0:0]$8618 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$8297 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$8298 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$8299 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$8300 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$8301 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$8302 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$8303 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[6:0]$8304 + update \o$next $0\o$next[63:0]$8615 + update \o_ok$next $0\o_ok$next[0:0]$8616 end - attribute \src "libresoc.v:150244.3-150262.6" - process $proc$libresoc.v:150244$8313 + attribute \src "libresoc.v:152743.3-152761.6" + process $proc$libresoc.v:152743$8620 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8314 $1\o$next[63:0]$8316 + assign $0\spr1$6$next[63:0]$8621 $1\spr1$6$next[63:0]$8623 assign { } { } - assign $0\o_ok$next[0:0]$8315 $2\o_ok$next[0:0]$8318 - attribute \src "libresoc.v:150245.5-150245.29" + assign $0\spr1_ok$next[0:0]$8622 $2\spr1_ok$next[0:0]$8625 + attribute \src "libresoc.v:152744.5-152744.29" switch \initial - attribute \src "libresoc.v:150245.9-150245.17" + attribute \src "libresoc.v:152744.9-152744.17" case 1'1 case end @@ -311018,41 +317421,41 @@ module \pipe$32 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8317 $1\o$next[63:0]$8316 } { \o_ok$36 \o$35 } + assign { $1\spr1_ok$next[0:0]$8624 $1\spr1$6$next[63:0]$8623 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8317 $1\o$next[63:0]$8316 } { \o_ok$36 \o$35 } + assign { $1\spr1_ok$next[0:0]$8624 $1\spr1$6$next[63:0]$8623 } { \spr1_ok$32 \spr1$31 } case - assign $1\o$next[63:0]$8316 \o - assign $1\o_ok$next[0:0]$8317 \o_ok + assign $1\spr1$6$next[63:0]$8623 \spr1$6 + assign $1\spr1_ok$next[0:0]$8624 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8318 1'0 + assign $2\spr1_ok$next[0:0]$8625 1'0 case - assign $2\o_ok$next[0:0]$8318 $1\o_ok$next[0:0]$8317 + assign $2\spr1_ok$next[0:0]$8625 $1\spr1_ok$next[0:0]$8624 end sync always - update \o$next $0\o$next[63:0]$8314 - update \o_ok$next $0\o_ok$next[0:0]$8315 + update \spr1$6$next $0\spr1$6$next[63:0]$8621 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8622 end - attribute \src "libresoc.v:150263.3-150281.6" - process $proc$libresoc.v:150263$8319 + attribute \src "libresoc.v:152762.3-152780.6" + process $proc$libresoc.v:152762$8626 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8320 $1\fast1$10$next[63:0]$8322 assign { } { } - assign $0\fast1_ok$next[0:0]$8321 $2\fast1_ok$next[0:0]$8324 - attribute \src "libresoc.v:150264.5-150264.29" + assign $0\fast1$7$next[63:0]$8628 $1\fast1$7$next[63:0]$8630 + assign $0\fast1_ok$next[0:0]$8627 $2\fast1_ok$next[0:0]$8631 + attribute \src "libresoc.v:152763.5-152763.29" switch \initial - attribute \src "libresoc.v:150264.9-150264.17" + attribute \src "libresoc.v:152763.9-152763.17" case 1'1 case end @@ -311062,41 +317465,41 @@ module \pipe$32 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8323 $1\fast1$10$next[63:0]$8322 } { \fast1_ok$38 \fast1$37 } + assign { $1\fast1_ok$next[0:0]$8629 $1\fast1$7$next[63:0]$8630 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8323 $1\fast1$10$next[63:0]$8322 } { \fast1_ok$38 \fast1$37 } + assign { $1\fast1_ok$next[0:0]$8629 $1\fast1$7$next[63:0]$8630 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1$10$next[63:0]$8322 \fast1$10 - assign $1\fast1_ok$next[0:0]$8323 \fast1_ok + assign $1\fast1_ok$next[0:0]$8629 \fast1_ok + assign $1\fast1$7$next[63:0]$8630 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8324 1'0 + assign $2\fast1_ok$next[0:0]$8631 1'0 case - assign $2\fast1_ok$next[0:0]$8324 $1\fast1_ok$next[0:0]$8323 + assign $2\fast1_ok$next[0:0]$8631 $1\fast1_ok$next[0:0]$8629 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8320 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8321 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8627 + update \fast1$7$next $0\fast1$7$next[63:0]$8628 end - attribute \src "libresoc.v:150282.3-150300.6" - process $proc$libresoc.v:150282$8325 + attribute \src "libresoc.v:152781.3-152799.6" + process $proc$libresoc.v:152781$8632 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8326 $1\fast2$11$next[63:0]$8328 assign { } { } - assign $0\fast2_ok$next[0:0]$8327 $2\fast2_ok$next[0:0]$8330 - attribute \src "libresoc.v:150283.5-150283.29" + assign $0\xer_so$8$next[0:0]$8634 $1\xer_so$8$next[0:0]$8636 + assign $0\xer_so_ok$next[0:0]$8633 $2\xer_so_ok$next[0:0]$8637 + attribute \src "libresoc.v:152782.5-152782.29" switch \initial - attribute \src "libresoc.v:150283.9-150283.17" + attribute \src "libresoc.v:152782.9-152782.17" case 1'1 case end @@ -311106,41 +317509,41 @@ module \pipe$32 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8329 $1\fast2$11$next[63:0]$8328 } { \fast2_ok$40 \fast2$39 } + assign { $1\xer_so_ok$next[0:0]$8635 $1\xer_so$8$next[0:0]$8636 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8329 $1\fast2$11$next[63:0]$8328 } { \fast2_ok$40 \fast2$39 } + assign { $1\xer_so_ok$next[0:0]$8635 $1\xer_so$8$next[0:0]$8636 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\fast2$11$next[63:0]$8328 \fast2$11 - assign $1\fast2_ok$next[0:0]$8329 \fast2_ok + assign $1\xer_so_ok$next[0:0]$8635 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8636 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8330 1'0 + assign $2\xer_so_ok$next[0:0]$8637 1'0 case - assign $2\fast2_ok$next[0:0]$8330 $1\fast2_ok$next[0:0]$8329 + assign $2\xer_so_ok$next[0:0]$8637 $1\xer_so_ok$next[0:0]$8635 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8326 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8327 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8633 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8634 end - attribute \src "libresoc.v:150301.3-150319.6" - process $proc$libresoc.v:150301$8331 + attribute \src "libresoc.v:152800.3-152818.6" + process $proc$libresoc.v:152800$8638 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8332 $1\nia$next[63:0]$8334 assign { } { } - assign $0\nia_ok$next[0:0]$8333 $2\nia_ok$next[0:0]$8336 - attribute \src "libresoc.v:150302.5-150302.29" + assign $0\xer_ov$9$next[1:0]$8640 $1\xer_ov$9$next[1:0]$8642 + assign $0\xer_ov_ok$next[0:0]$8639 $2\xer_ov_ok$next[0:0]$8643 + attribute \src "libresoc.v:152801.5-152801.29" switch \initial - attribute \src "libresoc.v:150302.9-150302.17" + attribute \src "libresoc.v:152801.9-152801.17" case 1'1 case end @@ -311150,41 +317553,41 @@ module \pipe$32 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8335 $1\nia$next[63:0]$8334 } { \nia_ok$42 \nia$41 } + assign { $1\xer_ov_ok$next[0:0]$8641 $1\xer_ov$9$next[1:0]$8642 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8335 $1\nia$next[63:0]$8334 } { \nia_ok$42 \nia$41 } + assign { $1\xer_ov_ok$next[0:0]$8641 $1\xer_ov$9$next[1:0]$8642 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\nia$next[63:0]$8334 \nia - assign $1\nia_ok$next[0:0]$8335 \nia_ok + assign $1\xer_ov_ok$next[0:0]$8641 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8642 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8336 1'0 + assign $2\xer_ov_ok$next[0:0]$8643 1'0 case - assign $2\nia_ok$next[0:0]$8336 $1\nia_ok$next[0:0]$8335 + assign $2\xer_ov_ok$next[0:0]$8643 $1\xer_ov_ok$next[0:0]$8641 end sync always - update \nia$next $0\nia$next[63:0]$8332 - update \nia_ok$next $0\nia_ok$next[0:0]$8333 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8639 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8640 end - attribute \src "libresoc.v:150320.3-150338.6" - process $proc$libresoc.v:150320$8337 + attribute \src "libresoc.v:152819.3-152837.6" + process $proc$libresoc.v:152819$8644 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$8338 $1\msr$next[63:0]$8340 + assign $0\xer_ca$10$next[1:0]$8645 $1\xer_ca$10$next[1:0]$8647 assign { } { } - assign $0\msr_ok$next[0:0]$8339 $2\msr_ok$next[0:0]$8342 - attribute \src "libresoc.v:150321.5-150321.29" + assign $0\xer_ca_ok$next[0:0]$8646 $2\xer_ca_ok$next[0:0]$8649 + attribute \src "libresoc.v:152820.5-152820.29" switch \initial - attribute \src "libresoc.v:150321.9-150321.17" + attribute \src "libresoc.v:152820.9-152820.17" case 1'1 case end @@ -311194,314 +317597,335 @@ module \pipe$32 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$8341 $1\msr$next[63:0]$8340 } { \msr_ok$44 \msr$43 } + assign { $1\xer_ca_ok$next[0:0]$8648 $1\xer_ca$10$next[1:0]$8647 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$8341 $1\msr$next[63:0]$8340 } { \msr_ok$44 \msr$43 } + assign { $1\xer_ca_ok$next[0:0]$8648 $1\xer_ca$10$next[1:0]$8647 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\msr$next[63:0]$8340 \msr - assign $1\msr_ok$next[0:0]$8341 \msr_ok + assign $1\xer_ca$10$next[1:0]$8647 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8648 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$8342 1'0 + assign $2\xer_ca_ok$next[0:0]$8649 1'0 case - assign $2\msr_ok$next[0:0]$8342 $1\msr_ok$next[0:0]$8341 + assign $2\xer_ca_ok$next[0:0]$8649 $1\xer_ca_ok$next[0:0]$8648 end sync always - update \msr$next $0\msr$next[63:0]$8338 - update \msr_ok$next $0\msr_ok$next[0:0]$8339 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8645 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8646 end - connect \$24 $and$libresoc.v:150110$8257_Y + connect \$22 $and$libresoc.v:152602$8569_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } - connect { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } - connect { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } - connect { \o_ok$36 \o$35 } { \main_o_ok \main_o } - connect { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect \main_rb \rb - connect \main_ra \ra - connect { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \main_muxid \muxid + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:150361.1-151276.10" +attribute \src "libresoc.v:152863.1-154334.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" -module \pipe$61 - attribute \src "libresoc.v:151179.3-151197.6" - wire width 64 $0\fast1$7$next[63:0]$8434 - attribute \src "libresoc.v:151032.3-151033.33" - wire width 64 $0\fast1$7[63:0]$8386 - attribute \src "libresoc.v:150375.14-150375.46" - wire width 64 $0\fast1$7[63:0]$8458 - attribute \src "libresoc.v:151179.3-151197.6" - wire $0\fast1_ok$next[0:0]$8433 - attribute \src "libresoc.v:151034.3-151035.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:150362.7-150362.20" +module \pipe1 + attribute \src "libresoc.v:154248.3-154289.6" + wire width 4 $0\alu_op__data_len$next[3:0]$8742 + attribute \src "libresoc.v:154024.3-154025.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 12 $0\alu_op__fn_unit$next[11:0]$8743 + attribute \src "libresoc.v:153994.3-153995.47" + wire width 12 $0\alu_op__fn_unit[11:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$8744 + attribute \src "libresoc.v:153996.3-153997.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__imm_data__ok$next[0:0]$8745 + attribute \src "libresoc.v:153998.3-153999.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$8746 + attribute \src "libresoc.v:154016.3-154017.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 32 $0\alu_op__insn$next[31:0]$8747 + attribute \src "libresoc.v:154026.3-154027.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$8748 + attribute \src "libresoc.v:153992.3-153993.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__invert_in$next[0:0]$8749 + attribute \src "libresoc.v:154008.3-154009.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__invert_out$next[0:0]$8750 + attribute \src "libresoc.v:154012.3-154013.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__is_32bit$next[0:0]$8751 + attribute \src "libresoc.v:154020.3-154021.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__is_signed$next[0:0]$8752 + attribute \src "libresoc.v:154022.3-154023.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__oe__oe$next[0:0]$8753 + attribute \src "libresoc.v:154004.3-154005.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__oe__ok$next[0:0]$8754 + attribute \src "libresoc.v:154006.3-154007.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__output_carry$next[0:0]$8755 + attribute \src "libresoc.v:154018.3-154019.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__rc__ok$next[0:0]$8756 + attribute \src "libresoc.v:154002.3-154003.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__rc__rc$next[0:0]$8757 + attribute \src "libresoc.v:154000.3-154001.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__write_cr0$next[0:0]$8758 + attribute \src "libresoc.v:154014.3-154015.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $0\alu_op__zero_a$next[0:0]$8759 + attribute \src "libresoc.v:154010.3-154011.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:154141.3-154159.6" + wire width 4 $0\cr_a$next[3:0]$8711 + attribute \src "libresoc.v:153984.3-153985.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:154141.3-154159.6" + wire $0\cr_a_ok$next[0:0]$8712 + attribute \src "libresoc.v:153986.3-153987.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:152864.7-152864.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151112.3-151124.6" - wire width 2 $0\muxid$1$next[1:0]$8409 - attribute \src "libresoc.v:151052.3-151053.33" - wire width 2 $0\muxid$1[1:0]$8402 - attribute \src "libresoc.v:150389.13-150389.29" - wire width 2 $0\muxid$1[1:0]$8461 - attribute \src "libresoc.v:151141.3-151159.6" - wire width 64 $0\o$next[63:0]$8421 - attribute \src "libresoc.v:151040.3-151041.19" + attribute \src "libresoc.v:154235.3-154247.6" + wire width 2 $0\muxid$next[1:0]$8739 + attribute \src "libresoc.v:154028.3-154029.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:154290.3-154308.6" + wire width 64 $0\o$next[63:0]$8785 + attribute \src "libresoc.v:153988.3-153989.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151141.3-151159.6" - wire $0\o_ok$next[0:0]$8422 - attribute \src "libresoc.v:151042.3-151043.25" + attribute \src "libresoc.v:154290.3-154308.6" + wire $0\o_ok$next[0:0]$8786 + attribute \src "libresoc.v:153990.3-153991.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151094.3-151111.6" - wire $0\r_busy$next[0:0]$8405 - attribute \src "libresoc.v:151054.3-151055.29" + attribute \src "libresoc.v:154217.3-154234.6" + wire $0\r_busy$next[0:0]$8735 + attribute \src "libresoc.v:154030.3-154031.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:151160.3-151178.6" - wire width 64 $0\spr1$6$next[63:0]$8427 - attribute \src "libresoc.v:151036.3-151037.31" - wire width 64 $0\spr1$6[63:0]$8389 - attribute \src "libresoc.v:150434.14-150434.45" - wire width 64 $0\spr1$6[63:0]$8466 - attribute \src "libresoc.v:151160.3-151178.6" - wire $0\spr1_ok$next[0:0]$8428 - attribute \src "libresoc.v:151038.3-151039.31" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:151125.3-151140.6" - wire width 12 $0\spr_op__fn_unit$3$next[11:0]$8412 - attribute \src "libresoc.v:151046.3-151047.53" - wire width 12 $0\spr_op__fn_unit$3[11:0]$8396 - attribute \src "libresoc.v:150719.14-150719.43" - wire width 12 $0\spr_op__fn_unit$3[11:0]$8469 - attribute \src "libresoc.v:151125.3-151140.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8413 - attribute \src "libresoc.v:151048.3-151049.47" - wire width 32 $0\spr_op__insn$4[31:0]$8398 - attribute \src "libresoc.v:150728.14-150728.38" - wire width 32 $0\spr_op__insn$4[31:0]$8471 - attribute \src "libresoc.v:151125.3-151140.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8414 - attribute \src "libresoc.v:151044.3-151045.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8394 - attribute \src "libresoc.v:150883.13-150883.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8473 - attribute \src "libresoc.v:151125.3-151140.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8415 - attribute \src "libresoc.v:151050.3-151051.55" - wire $0\spr_op__is_32bit$5[0:0]$8400 - attribute \src "libresoc.v:150968.7-150968.34" - wire $0\spr_op__is_32bit$5[0:0]$8475 - attribute \src "libresoc.v:151236.3-151254.6" - wire width 2 $0\xer_ca$10$next[1:0]$8451 - attribute \src "libresoc.v:151020.3-151021.37" - wire width 2 $0\xer_ca$10[1:0]$8377 - attribute \src "libresoc.v:150975.13-150975.31" - wire width 2 $0\xer_ca$10[1:0]$8477 - attribute \src "libresoc.v:151236.3-151254.6" - wire $0\xer_ca_ok$next[0:0]$8452 - attribute \src "libresoc.v:151022.3-151023.35" + attribute \src "libresoc.v:154160.3-154178.6" + wire width 2 $0\xer_ca$next[1:0]$8718 + attribute \src "libresoc.v:153980.3-153981.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:154160.3-154178.6" + wire $0\xer_ca_ok$next[0:0]$8717 + attribute \src "libresoc.v:153982.3-153983.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:151217.3-151235.6" - wire width 2 $0\xer_ov$9$next[1:0]$8446 - attribute \src "libresoc.v:151024.3-151025.35" - wire width 2 $0\xer_ov$9[1:0]$8380 - attribute \src "libresoc.v:150993.13-150993.30" - wire width 2 $0\xer_ov$9[1:0]$8480 - attribute \src "libresoc.v:151217.3-151235.6" - wire $0\xer_ov_ok$next[0:0]$8445 - attribute \src "libresoc.v:151026.3-151027.35" + attribute \src "libresoc.v:154179.3-154197.6" + wire width 2 $0\xer_ov$next[1:0]$8723 + attribute \src "libresoc.v:153976.3-153977.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:154179.3-154197.6" + wire $0\xer_ov_ok$next[0:0]$8724 + attribute \src "libresoc.v:153978.3-153979.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:151198.3-151216.6" - wire $0\xer_so$8$next[0:0]$8440 - attribute \src "libresoc.v:151028.3-151029.35" - wire $0\xer_so$8[0:0]$8383 - attribute \src "libresoc.v:151009.7-151009.24" - wire $0\xer_so$8[0:0]$8483 - attribute \src "libresoc.v:151198.3-151216.6" - wire $0\xer_so_ok$next[0:0]$8439 - attribute \src "libresoc.v:151030.3-151031.35" + attribute \src "libresoc.v:154198.3-154216.6" + wire $0\xer_so$next[0:0]$8729 + attribute \src "libresoc.v:153972.3-153973.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:154198.3-154216.6" + wire $0\xer_so_ok$next[0:0]$8730 + attribute \src "libresoc.v:153974.3-153975.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:151179.3-151197.6" - wire width 64 $1\fast1$7$next[63:0]$8436 - attribute \src "libresoc.v:151179.3-151197.6" - wire $1\fast1_ok$next[0:0]$8435 - attribute \src "libresoc.v:150380.7-150380.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:151112.3-151124.6" - wire width 2 $1\muxid$1$next[1:0]$8410 - attribute \src "libresoc.v:151141.3-151159.6" - wire width 64 $1\o$next[63:0]$8423 - attribute \src "libresoc.v:150402.14-150402.38" + attribute \src "libresoc.v:154248.3-154289.6" + wire width 4 $1\alu_op__data_len$next[3:0]$8760 + attribute \src "libresoc.v:152869.13-152869.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 12 $1\alu_op__fn_unit$next[11:0]$8761 + attribute \src "libresoc.v:152891.14-152891.39" + wire width 12 $1\alu_op__fn_unit[11:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$8762 + attribute \src "libresoc.v:152926.14-152926.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__imm_data__ok$next[0:0]$8763 + attribute \src "libresoc.v:152935.7-152935.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$8764 + attribute \src "libresoc.v:152948.13-152948.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 32 $1\alu_op__insn$next[31:0]$8765 + attribute \src "libresoc.v:152965.14-152965.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$8766 + attribute \src "libresoc.v:153048.13-153048.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__invert_in$next[0:0]$8767 + attribute \src "libresoc.v:153205.7-153205.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__invert_out$next[0:0]$8768 + attribute \src "libresoc.v:153214.7-153214.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__is_32bit$next[0:0]$8769 + attribute \src "libresoc.v:153223.7-153223.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__is_signed$next[0:0]$8770 + attribute \src "libresoc.v:153232.7-153232.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__oe__oe$next[0:0]$8771 + attribute \src "libresoc.v:153241.7-153241.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__oe__ok$next[0:0]$8772 + attribute \src "libresoc.v:153250.7-153250.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__output_carry$next[0:0]$8773 + attribute \src "libresoc.v:153259.7-153259.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__rc__ok$next[0:0]$8774 + attribute \src "libresoc.v:153268.7-153268.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__rc__rc$next[0:0]$8775 + attribute \src "libresoc.v:153277.7-153277.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__write_cr0$next[0:0]$8776 + attribute \src "libresoc.v:153286.7-153286.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:154248.3-154289.6" + wire $1\alu_op__zero_a$next[0:0]$8777 + attribute \src "libresoc.v:153295.7-153295.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:154141.3-154159.6" + wire width 4 $1\cr_a$next[3:0]$8713 + attribute \src "libresoc.v:153308.13-153308.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:154141.3-154159.6" + wire $1\cr_a_ok$next[0:0]$8714 + attribute \src "libresoc.v:153315.7-153315.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:154235.3-154247.6" + wire width 2 $1\muxid$next[1:0]$8740 + attribute \src "libresoc.v:153880.13-153880.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:154290.3-154308.6" + wire width 64 $1\o$next[63:0]$8787 + attribute \src "libresoc.v:153895.14-153895.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151141.3-151159.6" - wire $1\o_ok$next[0:0]$8424 - attribute \src "libresoc.v:150409.7-150409.18" + attribute \src "libresoc.v:154290.3-154308.6" + wire $1\o_ok$next[0:0]$8788 + attribute \src "libresoc.v:153902.7-153902.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151094.3-151111.6" - wire $1\r_busy$next[0:0]$8406 - attribute \src "libresoc.v:150423.7-150423.20" + attribute \src "libresoc.v:154217.3-154234.6" + wire $1\r_busy$next[0:0]$8736 + attribute \src "libresoc.v:153916.7-153916.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:151160.3-151178.6" - wire width 64 $1\spr1$6$next[63:0]$8429 - attribute \src "libresoc.v:151160.3-151178.6" - wire $1\spr1_ok$next[0:0]$8430 - attribute \src "libresoc.v:150439.7-150439.21" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:151125.3-151140.6" - wire width 12 $1\spr_op__fn_unit$3$next[11:0]$8416 - attribute \src "libresoc.v:151125.3-151140.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8417 - attribute \src "libresoc.v:151125.3-151140.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8418 - attribute \src "libresoc.v:151125.3-151140.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8419 - attribute \src "libresoc.v:151236.3-151254.6" - wire width 2 $1\xer_ca$10$next[1:0]$8453 - attribute \src "libresoc.v:151236.3-151254.6" - wire $1\xer_ca_ok$next[0:0]$8454 - attribute \src "libresoc.v:150982.7-150982.23" + attribute \src "libresoc.v:154160.3-154178.6" + wire width 2 $1\xer_ca$next[1:0]$8720 + attribute \src "libresoc.v:153925.13-153925.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:154160.3-154178.6" + wire $1\xer_ca_ok$next[0:0]$8719 + attribute \src "libresoc.v:153934.7-153934.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:151217.3-151235.6" - wire width 2 $1\xer_ov$9$next[1:0]$8448 - attribute \src "libresoc.v:151217.3-151235.6" - wire $1\xer_ov_ok$next[0:0]$8447 - attribute \src "libresoc.v:150998.7-150998.23" + attribute \src "libresoc.v:154179.3-154197.6" + wire width 2 $1\xer_ov$next[1:0]$8725 + attribute \src "libresoc.v:153941.13-153941.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:154179.3-154197.6" + wire $1\xer_ov_ok$next[0:0]$8726 + attribute \src "libresoc.v:153948.7-153948.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:151198.3-151216.6" - wire $1\xer_so$8$next[0:0]$8442 - attribute \src "libresoc.v:151198.3-151216.6" - wire $1\xer_so_ok$next[0:0]$8441 - attribute \src "libresoc.v:151014.7-151014.23" + attribute \src "libresoc.v:154198.3-154216.6" + wire $1\xer_so$next[0:0]$8731 + attribute \src "libresoc.v:153955.7-153955.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:154198.3-154216.6" + wire $1\xer_so_ok$next[0:0]$8732 + attribute \src "libresoc.v:153964.7-153964.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:151179.3-151197.6" - wire $2\fast1_ok$next[0:0]$8437 - attribute \src "libresoc.v:151141.3-151159.6" - wire $2\o_ok$next[0:0]$8425 - attribute \src "libresoc.v:151094.3-151111.6" - wire $2\r_busy$next[0:0]$8407 - attribute \src "libresoc.v:151160.3-151178.6" - wire $2\spr1_ok$next[0:0]$8431 - attribute \src "libresoc.v:151236.3-151254.6" - wire $2\xer_ca_ok$next[0:0]$8455 - attribute \src "libresoc.v:151217.3-151235.6" - wire $2\xer_ov_ok$next[0:0]$8449 - attribute \src "libresoc.v:151198.3-151216.6" - wire $2\xer_so_ok$next[0:0]$8443 - attribute \src "libresoc.v:151019.18-151019.118" - wire $and$libresoc.v:151019$8375_Y + attribute \src "libresoc.v:154248.3-154289.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$8778 + attribute \src "libresoc.v:154248.3-154289.6" + wire $2\alu_op__imm_data__ok$next[0:0]$8779 + attribute \src "libresoc.v:154248.3-154289.6" + wire $2\alu_op__oe__oe$next[0:0]$8780 + attribute \src "libresoc.v:154248.3-154289.6" + wire $2\alu_op__oe__ok$next[0:0]$8781 + attribute \src "libresoc.v:154248.3-154289.6" + wire $2\alu_op__rc__ok$next[0:0]$8782 + attribute \src "libresoc.v:154248.3-154289.6" + wire $2\alu_op__rc__rc$next[0:0]$8783 + attribute \src "libresoc.v:154141.3-154159.6" + wire $2\cr_a_ok$next[0:0]$8715 + attribute \src "libresoc.v:154290.3-154308.6" + wire $2\o_ok$next[0:0]$8789 + attribute \src "libresoc.v:154217.3-154234.6" + wire $2\r_busy$next[0:0]$8737 + attribute \src "libresoc.v:154160.3-154178.6" + wire $2\xer_ca_ok$next[0:0]$8721 + attribute \src "libresoc.v:154179.3-154197.6" + wire $2\xer_ov_ok$next[0:0]$8727 + attribute \src "libresoc.v:154198.3-154216.6" + wire $2\xer_so_ok$next[0:0]$8733 + attribute \src "libresoc.v:153971.18-153971.118" + wire $and$libresoc.v:153971$8679_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \fast1_ok$next - attribute \src "libresoc.v:150362.7-150362.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 17 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 16 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 15 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr1_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_fast1$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_spr1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_spr1_ok + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -311516,7 +317940,7 @@ module \pipe$61 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_main_spr_op__fn_unit + wire width 12 output 6 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -311531,11 +317955,68 @@ module \pipe$61 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_main_spr_op__fn_unit$13 + wire width 12 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn + wire width 12 \alu_op__fn_unit$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn$14 + wire width 12 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -311611,7 +318092,7 @@ module \pipe$61 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type + wire width 7 output 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -311687,29 +318168,2465 @@ module \pipe$61 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type$12 + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:152864.7-152864.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$libresoc.v:153971$8679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$libresoc.v:153971$8679_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154032.11-154079.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154080.8-154132.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154133.9-154136.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154137.9-154140.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:152864.7-152864.20" + process $proc$libresoc.v:152864$8790 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:152869.13-152869.36" + process $proc$libresoc.v:152869$8791 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:152891.14-152891.39" + process $proc$libresoc.v:152891$8792 + assign { } { } + assign $1\alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:152926.14-152926.59" + process $proc$libresoc.v:152926$8793 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:152935.7-152935.34" + process $proc$libresoc.v:152935$8794 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:152948.13-152948.39" + process $proc$libresoc.v:152948$8795 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:152965.14-152965.34" + process $proc$libresoc.v:152965$8796 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "libresoc.v:153048.13-153048.38" + process $proc$libresoc.v:153048$8797 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:153205.7-153205.31" + process $proc$libresoc.v:153205$8798 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:153214.7-153214.32" + process $proc$libresoc.v:153214$8799 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:153223.7-153223.30" + process $proc$libresoc.v:153223$8800 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:153232.7-153232.31" + process $proc$libresoc.v:153232$8801 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:153241.7-153241.28" + process $proc$libresoc.v:153241$8802 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:153250.7-153250.28" + process $proc$libresoc.v:153250$8803 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:153259.7-153259.34" + process $proc$libresoc.v:153259$8804 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:153268.7-153268.28" + process $proc$libresoc.v:153268$8805 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:153277.7-153277.28" + process $proc$libresoc.v:153277$8806 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:153286.7-153286.31" + process $proc$libresoc.v:153286$8807 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:153295.7-153295.28" + process $proc$libresoc.v:153295$8808 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:153308.13-153308.24" + process $proc$libresoc.v:153308$8809 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:153315.7-153315.21" + process $proc$libresoc.v:153315$8810 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153880.13-153880.25" + process $proc$libresoc.v:153880$8811 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:153895.14-153895.38" + process $proc$libresoc.v:153895$8812 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:153902.7-153902.18" + process $proc$libresoc.v:153902$8813 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:153916.7-153916.20" + process $proc$libresoc.v:153916$8814 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:153925.13-153925.26" + process $proc$libresoc.v:153925$8815 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:153934.7-153934.23" + process $proc$libresoc.v:153934$8816 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153941.13-153941.26" + process $proc$libresoc.v:153941$8817 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:153948.7-153948.23" + process $proc$libresoc.v:153948$8818 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:153955.7-153955.20" + process $proc$libresoc.v:153955$8819 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:153964.7-153964.23" + process $proc$libresoc.v:153964$8820 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153972.3-153973.29" + process $proc$libresoc.v:153972$8680 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:153974.3-153975.35" + process $proc$libresoc.v:153974$8681 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:153976.3-153977.29" + process $proc$libresoc.v:153976$8682 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:153978.3-153979.35" + process $proc$libresoc.v:153978$8683 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:153980.3-153981.29" + process $proc$libresoc.v:153980$8684 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:153982.3-153983.35" + process $proc$libresoc.v:153982$8685 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:153984.3-153985.25" + process $proc$libresoc.v:153984$8686 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:153986.3-153987.31" + process $proc$libresoc.v:153986$8687 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:153988.3-153989.19" + process $proc$libresoc.v:153988$8688 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:153990.3-153991.25" + process $proc$libresoc.v:153990$8689 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:153992.3-153993.51" + process $proc$libresoc.v:153992$8690 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:153994.3-153995.47" + process $proc$libresoc.v:153994$8691 + assign { } { } + assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] + end + attribute \src "libresoc.v:153996.3-153997.61" + process $proc$libresoc.v:153996$8692 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:153998.3-153999.57" + process $proc$libresoc.v:153998$8693 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154000.3-154001.45" + process $proc$libresoc.v:154000$8694 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:154002.3-154003.45" + process $proc$libresoc.v:154002$8695 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:154004.3-154005.45" + process $proc$libresoc.v:154004$8696 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:154006.3-154007.45" + process $proc$libresoc.v:154006$8697 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:154008.3-154009.51" + process $proc$libresoc.v:154008$8698 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:154010.3-154011.45" + process $proc$libresoc.v:154010$8699 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:154012.3-154013.53" + process $proc$libresoc.v:154012$8700 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:154014.3-154015.51" + process $proc$libresoc.v:154014$8701 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:154016.3-154017.55" + process $proc$libresoc.v:154016$8702 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:154018.3-154019.57" + process $proc$libresoc.v:154018$8703 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:154020.3-154021.49" + process $proc$libresoc.v:154020$8704 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:154022.3-154023.51" + process $proc$libresoc.v:154022$8705 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:154024.3-154025.49" + process $proc$libresoc.v:154024$8706 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:154026.3-154027.41" + process $proc$libresoc.v:154026$8707 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:154028.3-154029.27" + process $proc$libresoc.v:154028$8708 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:154030.3-154031.29" + process $proc$libresoc.v:154030$8709 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:154141.3-154159.6" + process $proc$libresoc.v:154141$8710 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8711 $1\cr_a$next[3:0]$8713 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8712 $2\cr_a_ok$next[0:0]$8715 + attribute \src "libresoc.v:154142.5-154142.29" + switch \initial + attribute \src "libresoc.v:154142.9-154142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8714 $1\cr_a$next[3:0]$8713 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8714 $1\cr_a$next[3:0]$8713 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$8713 \cr_a + assign $1\cr_a_ok$next[0:0]$8714 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8715 1'0 + case + assign $2\cr_a_ok$next[0:0]$8715 $1\cr_a_ok$next[0:0]$8714 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8711 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8712 + end + attribute \src "libresoc.v:154160.3-154178.6" + process $proc$libresoc.v:154160$8716 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8718 $1\xer_ca$next[1:0]$8720 + assign $0\xer_ca_ok$next[0:0]$8717 $2\xer_ca_ok$next[0:0]$8721 + attribute \src "libresoc.v:154161.5-154161.29" + switch \initial + attribute \src "libresoc.v:154161.9-154161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8719 $1\xer_ca$next[1:0]$8720 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8719 $1\xer_ca$next[1:0]$8720 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$8719 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8720 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8721 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8721 $1\xer_ca_ok$next[0:0]$8719 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8717 + update \xer_ca$next $0\xer_ca$next[1:0]$8718 + end + attribute \src "libresoc.v:154179.3-154197.6" + process $proc$libresoc.v:154179$8722 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8723 $1\xer_ov$next[1:0]$8725 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8724 $2\xer_ov_ok$next[0:0]$8727 + attribute \src "libresoc.v:154180.5-154180.29" + switch \initial + attribute \src "libresoc.v:154180.9-154180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8726 $1\xer_ov$next[1:0]$8725 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8726 $1\xer_ov$next[1:0]$8725 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$8725 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8726 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8727 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8727 $1\xer_ov_ok$next[0:0]$8726 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8723 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8724 + end + attribute \src "libresoc.v:154198.3-154216.6" + process $proc$libresoc.v:154198$8728 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8729 $1\xer_so$next[0:0]$8731 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8730 $2\xer_so_ok$next[0:0]$8733 + attribute \src "libresoc.v:154199.5-154199.29" + switch \initial + attribute \src "libresoc.v:154199.9-154199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8732 $1\xer_so$next[0:0]$8731 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8732 $1\xer_so$next[0:0]$8731 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$8731 \xer_so + assign $1\xer_so_ok$next[0:0]$8732 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8733 1'0 + case + assign $2\xer_so_ok$next[0:0]$8733 $1\xer_so_ok$next[0:0]$8732 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8729 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8730 + end + attribute \src "libresoc.v:154217.3-154234.6" + process $proc$libresoc.v:154217$8734 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8735 $2\r_busy$next[0:0]$8737 + attribute \src "libresoc.v:154218.5-154218.29" + switch \initial + attribute \src "libresoc.v:154218.9-154218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8736 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8736 1'0 + case + assign $1\r_busy$next[0:0]$8736 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8737 1'0 + case + assign $2\r_busy$next[0:0]$8737 $1\r_busy$next[0:0]$8736 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8735 + end + attribute \src "libresoc.v:154235.3-154247.6" + process $proc$libresoc.v:154235$8738 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8739 $1\muxid$next[1:0]$8740 + attribute \src "libresoc.v:154236.5-154236.29" + switch \initial + attribute \src "libresoc.v:154236.9-154236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8740 \muxid$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8740 \muxid$69 + case + assign $1\muxid$next[1:0]$8740 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8739 + end + attribute \src "libresoc.v:154248.3-154289.6" + process $proc$libresoc.v:154248$8741 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$8742 $1\alu_op__data_len$next[3:0]$8760 + assign $0\alu_op__fn_unit$next[11:0]$8743 $1\alu_op__fn_unit$next[11:0]$8761 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$8746 $1\alu_op__input_carry$next[1:0]$8764 + assign $0\alu_op__insn$next[31:0]$8747 $1\alu_op__insn$next[31:0]$8765 + assign $0\alu_op__insn_type$next[6:0]$8748 $1\alu_op__insn_type$next[6:0]$8766 + assign $0\alu_op__invert_in$next[0:0]$8749 $1\alu_op__invert_in$next[0:0]$8767 + assign $0\alu_op__invert_out$next[0:0]$8750 $1\alu_op__invert_out$next[0:0]$8768 + assign $0\alu_op__is_32bit$next[0:0]$8751 $1\alu_op__is_32bit$next[0:0]$8769 + assign $0\alu_op__is_signed$next[0:0]$8752 $1\alu_op__is_signed$next[0:0]$8770 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$8755 $1\alu_op__output_carry$next[0:0]$8773 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$8758 $1\alu_op__write_cr0$next[0:0]$8776 + assign $0\alu_op__zero_a$next[0:0]$8759 $1\alu_op__zero_a$next[0:0]$8777 + assign $0\alu_op__imm_data__data$next[63:0]$8744 $2\alu_op__imm_data__data$next[63:0]$8778 + assign $0\alu_op__imm_data__ok$next[0:0]$8745 $2\alu_op__imm_data__ok$next[0:0]$8779 + assign $0\alu_op__oe__oe$next[0:0]$8753 $2\alu_op__oe__oe$next[0:0]$8780 + assign $0\alu_op__oe__ok$next[0:0]$8754 $2\alu_op__oe__ok$next[0:0]$8781 + assign $0\alu_op__rc__ok$next[0:0]$8756 $2\alu_op__rc__ok$next[0:0]$8782 + assign $0\alu_op__rc__rc$next[0:0]$8757 $2\alu_op__rc__rc$next[0:0]$8783 + attribute \src "libresoc.v:154249.5-154249.29" + switch \initial + attribute \src "libresoc.v:154249.9-154249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8765 $1\alu_op__data_len$next[3:0]$8760 $1\alu_op__is_signed$next[0:0]$8770 $1\alu_op__is_32bit$next[0:0]$8769 $1\alu_op__output_carry$next[0:0]$8773 $1\alu_op__input_carry$next[1:0]$8764 $1\alu_op__write_cr0$next[0:0]$8776 $1\alu_op__invert_out$next[0:0]$8768 $1\alu_op__zero_a$next[0:0]$8777 $1\alu_op__invert_in$next[0:0]$8767 $1\alu_op__oe__ok$next[0:0]$8772 $1\alu_op__oe__oe$next[0:0]$8771 $1\alu_op__rc__ok$next[0:0]$8774 $1\alu_op__rc__rc$next[0:0]$8775 $1\alu_op__imm_data__ok$next[0:0]$8763 $1\alu_op__imm_data__data$next[63:0]$8762 $1\alu_op__fn_unit$next[11:0]$8761 $1\alu_op__insn_type$next[6:0]$8766 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8765 $1\alu_op__data_len$next[3:0]$8760 $1\alu_op__is_signed$next[0:0]$8770 $1\alu_op__is_32bit$next[0:0]$8769 $1\alu_op__output_carry$next[0:0]$8773 $1\alu_op__input_carry$next[1:0]$8764 $1\alu_op__write_cr0$next[0:0]$8776 $1\alu_op__invert_out$next[0:0]$8768 $1\alu_op__zero_a$next[0:0]$8777 $1\alu_op__invert_in$next[0:0]$8767 $1\alu_op__oe__ok$next[0:0]$8772 $1\alu_op__oe__oe$next[0:0]$8771 $1\alu_op__rc__ok$next[0:0]$8774 $1\alu_op__rc__rc$next[0:0]$8775 $1\alu_op__imm_data__ok$next[0:0]$8763 $1\alu_op__imm_data__data$next[63:0]$8762 $1\alu_op__fn_unit$next[11:0]$8761 $1\alu_op__insn_type$next[6:0]$8766 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$8760 \alu_op__data_len + assign $1\alu_op__fn_unit$next[11:0]$8761 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$8762 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$8763 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$8764 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$8765 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$8766 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$8767 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$8768 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$8769 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$8770 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$8771 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$8772 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$8773 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$8774 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$8775 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$8776 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$8777 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$8778 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$8779 1'0 + assign $2\alu_op__rc__rc$next[0:0]$8783 1'0 + assign $2\alu_op__rc__ok$next[0:0]$8782 1'0 + assign $2\alu_op__oe__oe$next[0:0]$8780 1'0 + assign $2\alu_op__oe__ok$next[0:0]$8781 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$8778 $1\alu_op__imm_data__data$next[63:0]$8762 + assign $2\alu_op__imm_data__ok$next[0:0]$8779 $1\alu_op__imm_data__ok$next[0:0]$8763 + assign $2\alu_op__oe__oe$next[0:0]$8780 $1\alu_op__oe__oe$next[0:0]$8771 + assign $2\alu_op__oe__ok$next[0:0]$8781 $1\alu_op__oe__ok$next[0:0]$8772 + assign $2\alu_op__rc__ok$next[0:0]$8782 $1\alu_op__rc__ok$next[0:0]$8774 + assign $2\alu_op__rc__rc$next[0:0]$8783 $1\alu_op__rc__rc$next[0:0]$8775 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8742 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8743 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8744 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8745 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8746 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8747 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8748 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8749 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8750 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8751 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8752 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8753 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8754 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8755 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8756 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8757 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8758 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8759 + end + attribute \src "libresoc.v:154290.3-154308.6" + process $proc$libresoc.v:154290$8784 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8785 $1\o$next[63:0]$8787 + assign { } { } + assign $0\o_ok$next[0:0]$8786 $2\o_ok$next[0:0]$8789 + attribute \src "libresoc.v:154291.5-154291.29" + switch \initial + attribute \src "libresoc.v:154291.9-154291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8788 $1\o$next[63:0]$8787 } { \o_ok$89 \o$88 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8788 $1\o$next[63:0]$8787 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$8787 \o + assign $1\o_ok$next[0:0]$8788 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8789 1'0 + case + assign $2\o_ok$next[0:0]$8789 $1\o_ok$next[0:0]$8788 + end + sync always + update \o$next $0\o$next[63:0]$8785 + update \o_ok$next $0\o_ok$next[0:0]$8786 + end + connect \$67 $and$libresoc.v:153971$8679_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:154338.1-155753.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$110 + attribute \src "libresoc.v:155686.3-155704.6" + wire width 4 $0\cr_a$next[3:0]$8910 + attribute \src "libresoc.v:155428.3-155429.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:155686.3-155704.6" + wire $0\cr_a_ok$next[0:0]$8911 + attribute \src "libresoc.v:155430.3-155431.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:154339.7-154339.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155613.3-155625.6" + wire width 2 $0\muxid$next[1:0]$8860 + attribute \src "libresoc.v:155470.3-155471.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:155667.3-155685.6" + wire width 64 $0\o$next[63:0]$8904 + attribute \src "libresoc.v:155432.3-155433.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:155667.3-155685.6" + wire $0\o_ok$next[0:0]$8905 + attribute \src "libresoc.v:155434.3-155435.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:155595.3-155612.6" + wire $0\r_busy$next[0:0]$8856 + attribute \src "libresoc.v:155472.3-155473.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 12 $0\sr_op__fn_unit$next[11:0]$8863 + attribute \src "libresoc.v:155438.3-155439.45" + wire width 12 $0\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$8864 + attribute \src "libresoc.v:155440.3-155441.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $0\sr_op__imm_data__ok$next[0:0]$8865 + attribute \src "libresoc.v:155442.3-155443.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$8866 + attribute \src "libresoc.v:155456.3-155457.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $0\sr_op__input_cr$next[0:0]$8867 + attribute \src "libresoc.v:155460.3-155461.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 32 $0\sr_op__insn$next[31:0]$8868 + attribute \src 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$1\muxid$next[1:0]$8861 + attribute \src "libresoc.v:154910.13-154910.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:155667.3-155685.6" + wire width 64 $1\o$next[63:0]$8906 + attribute \src "libresoc.v:154925.14-154925.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:155667.3-155685.6" + wire $1\o_ok$next[0:0]$8907 + attribute \src "libresoc.v:154932.7-154932.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:155595.3-155612.6" + wire $1\r_busy$next[0:0]$8857 + attribute \src "libresoc.v:154946.7-154946.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 12 $1\sr_op__fn_unit$next[11:0]$8880 + attribute \src "libresoc.v:154970.14-154970.38" + wire width 12 $1\sr_op__fn_unit[11:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$8881 + attribute \src "libresoc.v:155005.14-155005.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:155626.3-155666.6" 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wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__is_32bit$next[0:0]$8888 + attribute \src "libresoc.v:155302.7-155302.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__is_signed$next[0:0]$8889 + attribute \src "libresoc.v:155311.7-155311.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__oe__oe$next[0:0]$8890 + attribute \src "libresoc.v:155320.7-155320.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__oe__ok$next[0:0]$8891 + attribute \src "libresoc.v:155329.7-155329.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__output_carry$next[0:0]$8892 + attribute \src "libresoc.v:155338.7-155338.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:155626.3-155666.6" + wire $1\sr_op__output_cr$next[0:0]$8893 + attribute \src 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64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire 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"OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_xer_ca_ok + wire width 2 \input_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ov$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_xer_ov_ok + wire width 2 \input_xer_ca$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \spr_main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \spr_main_xer_so_ok + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -311724,7 +320641,7 @@ module \pipe$61 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \spr_op__fn_unit + wire width 12 \main_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -311739,7 +320656,277 @@ module \pipe$61 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$26 + wire width 12 \main_sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -311754,17 +320941,91 @@ module \pipe$61 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 19 \spr_op__fn_unit$3 + wire width 12 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$3$next + wire width 12 input 34 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \spr_op__insn + wire width 12 \sr_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$27 + wire width 12 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \spr_op__insn$4 + wire width 64 output 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$4$next + wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 43 \sr_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -311840,7 +321101,7 @@ module \pipe$61 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \spr_op__insn_type + wire width 7 output 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -311916,9 +321177,7 @@ module \pipe$61 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 18 \spr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$2$next + wire width 7 input 33 \sr_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -311994,399 +321253,669 @@ module \pipe$61 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$25 + wire width 7 \sr_op__insn_type$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \spr_op__is_32bit + wire width 7 \sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$28 + wire output 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \spr_op__is_32bit$5 + wire input 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$5$next + wire \sr_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 14 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next + wire width 2 input 54 \xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$next + wire width 2 \xer_ca$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 12 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 29 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 53 \xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:151019$8375 + cell $and $and$libresoc.v:155419$8821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 + connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:151019$8375_Y + connect \Y $and$libresoc.v:155419$8821_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:151056.10-151059.4" - cell \n$63 \n + attribute \src "libresoc.v:155474.15-155521.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155522.14-155567.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155568.11-155571.4" + cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:151060.10-151063.4" - cell \p$62 \p + attribute \src "libresoc.v:155572.11-155575.4" + cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151064.12-151093.4" - cell \spr_main \spr_main - connect \fast1 \spr_main_fast1 - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \muxid \spr_main_muxid - connect \muxid$1 \spr_main_muxid$11 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \xer_ca \spr_main_xer_ca - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - connect \xer_ov \spr_main_xer_ov - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_so \spr_main_xer_so - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - end - attribute \src "libresoc.v:150362.7-150362.20" - process $proc$libresoc.v:150362$8456 + attribute \src "libresoc.v:154339.7-154339.20" + process $proc$libresoc.v:154339$8921 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150375.14-150375.46" - process $proc$libresoc.v:150375$8457 + attribute \src "libresoc.v:154348.13-154348.24" + process $proc$libresoc.v:154348$8922 assign { } { } - assign $0\fast1$7[63:0]$8458 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cr_a[3:0] 4'0000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8458 + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:150380.7-150380.22" - process $proc$libresoc.v:150380$8459 + attribute \src "libresoc.v:154357.7-154357.21" + process $proc$libresoc.v:154357$8923 assign { } { } - assign $1\fast1_ok[0:0] 1'0 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \fast1_ok $1\fast1_ok[0:0] + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:150389.13-150389.29" - process $proc$libresoc.v:150389$8460 + attribute \src "libresoc.v:154910.13-154910.25" + process $proc$libresoc.v:154910$8924 assign { } { } - assign $0\muxid$1[1:0]$8461 2'00 + assign $1\muxid[1:0] 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8461 + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:150402.14-150402.38" - process $proc$libresoc.v:150402$8462 + attribute \src "libresoc.v:154925.14-154925.38" + process $proc$libresoc.v:154925$8925 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:150409.7-150409.18" - process $proc$libresoc.v:150409$8463 + attribute \src "libresoc.v:154932.7-154932.18" + process $proc$libresoc.v:154932$8926 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:150423.7-150423.20" - process $proc$libresoc.v:150423$8464 + attribute \src "libresoc.v:154946.7-154946.20" + process $proc$libresoc.v:154946$8927 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:150434.14-150434.45" - process $proc$libresoc.v:150434$8465 + attribute \src "libresoc.v:154970.14-154970.38" + process $proc$libresoc.v:154970$8928 assign { } { } - assign $0\spr1$6[63:0]$8466 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sr_op__fn_unit[11:0] 12'000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8466 + update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] end - attribute \src "libresoc.v:150439.7-150439.21" - process $proc$libresoc.v:150439$8467 + attribute \src "libresoc.v:155005.14-155005.58" + process $proc$libresoc.v:155005$8929 assign { } { } - assign $1\spr1_ok[0:0] 1'0 + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1_ok $1\spr1_ok[0:0] + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:155014.7-155014.33" + process $proc$libresoc.v:155014$8930 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:155027.13-155027.38" + process $proc$libresoc.v:155027$8931 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:155044.7-155044.29" + process $proc$libresoc.v:155044$8932 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:155053.14-155053.33" + process $proc$libresoc.v:155053$8933 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "libresoc.v:155136.13-155136.37" + process $proc$libresoc.v:155136$8934 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:155293.7-155293.30" + process $proc$libresoc.v:155293$8935 + assign { } { } + assign $1\sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \sr_op__invert_in $1\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:155302.7-155302.29" + process $proc$libresoc.v:155302$8936 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:155311.7-155311.30" + process $proc$libresoc.v:155311$8937 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:155320.7-155320.27" + process $proc$libresoc.v:155320$8938 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:155329.7-155329.27" + process $proc$libresoc.v:155329$8939 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:155338.7-155338.33" + process $proc$libresoc.v:155338$8940 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:150719.14-150719.43" - process $proc$libresoc.v:150719$8468 + attribute \src "libresoc.v:155347.7-155347.30" + process $proc$libresoc.v:155347$8941 assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8469 12'000000000000 + assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8469 + update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:150728.14-150728.38" - process $proc$libresoc.v:150728$8470 + attribute \src "libresoc.v:155356.7-155356.27" + process $proc$libresoc.v:155356$8942 assign { } { } - assign $0\spr_op__insn$4[31:0]$8471 0 + assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8471 + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:150883.13-150883.42" - process $proc$libresoc.v:150883$8472 + attribute \src "libresoc.v:155365.7-155365.27" + process $proc$libresoc.v:155365$8943 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8473 7'0000000 + assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8473 + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:150968.7-150968.34" - process $proc$libresoc.v:150968$8474 + attribute \src "libresoc.v:155374.7-155374.30" + process $proc$libresoc.v:155374$8944 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8475 1'0 + assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8475 + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:150975.13-150975.31" - process $proc$libresoc.v:150975$8476 + attribute \src "libresoc.v:155383.13-155383.26" + process $proc$libresoc.v:155383$8945 assign { } { } - assign $0\xer_ca$10[1:0]$8477 2'00 + assign $1\xer_ca[1:0] 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8477 + update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:150982.7-150982.23" - process $proc$libresoc.v:150982$8478 + attribute \src "libresoc.v:155394.7-155394.23" + process $proc$libresoc.v:155394$8946 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:150993.13-150993.30" - process $proc$libresoc.v:150993$8479 + attribute \src "libresoc.v:155403.7-155403.20" + process $proc$libresoc.v:155403$8947 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:155412.7-155412.23" + process $proc$libresoc.v:155412$8948 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:155420.3-155421.29" + process $proc$libresoc.v:155420$8822 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:155422.3-155423.35" + process $proc$libresoc.v:155422$8823 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:155424.3-155425.29" + process $proc$libresoc.v:155424$8824 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:155426.3-155427.35" + process $proc$libresoc.v:155426$8825 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:155428.3-155429.25" + process $proc$libresoc.v:155428$8826 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:155430.3-155431.31" + process $proc$libresoc.v:155430$8827 assign { } { } - assign $0\xer_ov$9[1:0]$8480 2'00 - sync always - sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8480 + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:150998.7-150998.23" - process $proc$libresoc.v:150998$8481 + attribute \src "libresoc.v:155432.3-155433.19" + process $proc$libresoc.v:155432$8828 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] end - attribute \src "libresoc.v:151009.7-151009.24" - process $proc$libresoc.v:151009$8482 + attribute \src "libresoc.v:155434.3-155435.25" + process $proc$libresoc.v:155434$8829 assign { } { } - assign $0\xer_so$8[0:0]$8483 1'0 - sync always - sync init - update \xer_so$8 $0\xer_so$8[0:0]$8483 + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:151014.7-151014.23" - process $proc$libresoc.v:151014$8484 + attribute \src "libresoc.v:155436.3-155437.49" + process $proc$libresoc.v:155436$8830 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:151020.3-151021.37" - process $proc$libresoc.v:151020$8376 + attribute \src "libresoc.v:155438.3-155439.45" + process $proc$libresoc.v:155438$8831 assign { } { } - assign $0\xer_ca$10[1:0]$8377 \xer_ca$10$next + assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8377 + update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] end - attribute \src "libresoc.v:151022.3-151023.35" - process $proc$libresoc.v:151022$8378 + attribute \src "libresoc.v:155440.3-155441.59" + process $proc$libresoc.v:155440$8832 assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:151024.3-151025.35" - process $proc$libresoc.v:151024$8379 + attribute \src "libresoc.v:155442.3-155443.55" + process $proc$libresoc.v:155442$8833 assign { } { } - assign $0\xer_ov$9[1:0]$8380 \xer_ov$9$next + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8380 + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:151026.3-151027.35" - process $proc$libresoc.v:151026$8381 + attribute \src "libresoc.v:155444.3-155445.43" + process $proc$libresoc.v:155444$8834 assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:151028.3-151029.35" - process $proc$libresoc.v:151028$8382 + attribute \src "libresoc.v:155446.3-155447.43" + process $proc$libresoc.v:155446$8835 assign { } { } - assign $0\xer_so$8[0:0]$8383 \xer_so$8$next + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8383 + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:151030.3-151031.35" - process $proc$libresoc.v:151030$8384 + attribute \src "libresoc.v:155448.3-155449.43" + process $proc$libresoc.v:155448$8836 assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:151032.3-151033.33" - process $proc$libresoc.v:151032$8385 + attribute \src "libresoc.v:155450.3-155451.43" + process $proc$libresoc.v:155450$8837 assign { } { } - assign $0\fast1$7[63:0]$8386 \fast1$7$next + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8386 + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:151034.3-151035.33" - process $proc$libresoc.v:151034$8387 + attribute \src "libresoc.v:155452.3-155453.49" + process $proc$libresoc.v:155452$8838 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:151036.3-151037.31" - process $proc$libresoc.v:151036$8388 + attribute \src "libresoc.v:155454.3-155455.49" + process $proc$libresoc.v:155454$8839 assign { } { } - assign $0\spr1$6[63:0]$8389 \spr1$6$next + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8389 + update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:151038.3-151039.31" - process $proc$libresoc.v:151038$8390 + attribute \src "libresoc.v:155456.3-155457.53" + process $proc$libresoc.v:155456$8840 assign { } { } - assign $0\spr1_ok[0:0] \spr1_ok$next + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk - update \spr1_ok $0\spr1_ok[0:0] + update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:151040.3-151041.19" - process $proc$libresoc.v:151040$8391 + attribute \src "libresoc.v:155458.3-155459.55" + process $proc$libresoc.v:155458$8841 assign { } { } - assign $0\o[63:0] \o$next + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:151042.3-151043.25" - process $proc$libresoc.v:151042$8392 + attribute \src "libresoc.v:155460.3-155461.47" + process $proc$libresoc.v:155460$8842 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:151044.3-151045.57" - process $proc$libresoc.v:151044$8393 + attribute \src "libresoc.v:155462.3-155463.49" + process $proc$libresoc.v:155462$8843 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8394 \spr_op__insn_type$2$next + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8394 + update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:151046.3-151047.53" - process $proc$libresoc.v:151046$8395 + attribute \src "libresoc.v:155464.3-155465.47" + process $proc$libresoc.v:155464$8844 assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8396 \spr_op__fn_unit$3$next + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8396 + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:151048.3-151049.47" - process $proc$libresoc.v:151048$8397 + attribute \src "libresoc.v:155466.3-155467.49" + process $proc$libresoc.v:155466$8845 assign { } { } - assign $0\spr_op__insn$4[31:0]$8398 \spr_op__insn$4$next + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8398 + update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:151050.3-151051.55" - process $proc$libresoc.v:151050$8399 + attribute \src "libresoc.v:155468.3-155469.39" + process $proc$libresoc.v:155468$8846 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8400 \spr_op__is_32bit$5$next + assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8400 + update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:151052.3-151053.33" - process $proc$libresoc.v:151052$8401 + attribute \src "libresoc.v:155470.3-155471.27" + process $proc$libresoc.v:155470$8847 assign { } { } - assign $0\muxid$1[1:0]$8402 \muxid$1$next + assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8402 + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:151054.3-151055.29" - process $proc$libresoc.v:151054$8403 + attribute \src "libresoc.v:155472.3-155473.29" + process $proc$libresoc.v:155472$8848 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:151094.3-151111.6" - process $proc$libresoc.v:151094$8404 + attribute \src "libresoc.v:155576.3-155594.6" + process $proc$libresoc.v:155576$8849 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8405 $2\r_busy$next[0:0]$8407 - attribute \src "libresoc.v:151095.5-151095.29" + assign $0\xer_ca$next[1:0]$8851 $1\xer_ca$next[1:0]$8853 + assign $0\xer_ca_ok$next[0:0]$8850 $2\xer_ca_ok$next[0:0]$8854 + attribute \src "libresoc.v:155577.5-155577.29" switch \initial - attribute \src "libresoc.v:151095.9-151095.17" + attribute \src "libresoc.v:155577.9-155577.17" case 1'1 case end @@ -312395,34 +321924,39 @@ module \pipe$61 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8406 1'1 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8852 $1\xer_ca$next[1:0]$8853 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8406 1'0 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8852 $1\xer_ca$next[1:0]$8853 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\r_busy$next[0:0]$8406 \r_busy + assign $1\xer_ca_ok$next[0:0]$8852 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8853 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8407 1'0 + assign $2\xer_ca_ok$next[0:0]$8854 1'0 case - assign $2\r_busy$next[0:0]$8407 $1\r_busy$next[0:0]$8406 + assign $2\xer_ca_ok$next[0:0]$8854 $1\xer_ca_ok$next[0:0]$8852 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8405 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8850 + update \xer_ca$next $0\xer_ca$next[1:0]$8851 end - attribute \src "libresoc.v:151112.3-151124.6" - process $proc$libresoc.v:151112$8408 + attribute \src "libresoc.v:155595.3-155612.6" + process $proc$libresoc.v:155595$8855 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8409 $1\muxid$1$next[1:0]$8410 - attribute \src "libresoc.v:151113.5-151113.29" + assign { } { } + assign $0\r_busy$next[0:0]$8856 $2\r_busy$next[0:0]$8858 + attribute \src "libresoc.v:155596.5-155596.29" switch \initial - attribute \src "libresoc.v:151113.9-151113.17" + attribute \src "libresoc.v:155596.9-155596.17" case 1'1 case end @@ -312431,34 +321965,34 @@ module \pipe$61 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8410 \muxid$24 + assign $1\r_busy$next[0:0]$8857 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8410 \muxid$24 + assign $1\r_busy$next[0:0]$8857 1'0 + case + assign $1\r_busy$next[0:0]$8857 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8858 1'0 case - assign $1\muxid$1$next[1:0]$8410 \muxid$1 + assign $2\r_busy$next[0:0]$8858 $1\r_busy$next[0:0]$8857 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8409 + update \r_busy$next $0\r_busy$next[0:0]$8856 end - attribute \src "libresoc.v:151125.3-151140.6" - process $proc$libresoc.v:151125$8411 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:155613.3-155625.6" + process $proc$libresoc.v:155613$8859 assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[11:0]$8412 $1\spr_op__fn_unit$3$next[11:0]$8416 - assign $0\spr_op__insn$4$next[31:0]$8413 $1\spr_op__insn$4$next[31:0]$8417 - assign $0\spr_op__insn_type$2$next[6:0]$8414 $1\spr_op__insn_type$2$next[6:0]$8418 - assign $0\spr_op__is_32bit$5$next[0:0]$8415 $1\spr_op__is_32bit$5$next[0:0]$8419 - attribute \src "libresoc.v:151126.5-151126.29" + assign $0\muxid$next[1:0]$8860 $1\muxid$next[1:0]$8861 + attribute \src "libresoc.v:155614.5-155614.29" switch \initial - attribute \src "libresoc.v:151126.9-151126.17" + attribute \src "libresoc.v:155614.9-155614.17" case 1'1 case end @@ -312467,129 +322001,79 @@ module \pipe$61 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8419 $1\spr_op__insn$4$next[31:0]$8417 $1\spr_op__fn_unit$3$next[11:0]$8416 $1\spr_op__insn_type$2$next[6:0]$8418 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$next[1:0]$8861 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8419 $1\spr_op__insn$4$next[31:0]$8417 $1\spr_op__fn_unit$3$next[11:0]$8416 $1\spr_op__insn_type$2$next[6:0]$8418 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$next[1:0]$8861 \muxid$67 case - assign $1\spr_op__fn_unit$3$next[11:0]$8416 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8417 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8418 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8419 \spr_op__is_32bit$5 + assign $1\muxid$next[1:0]$8861 \muxid end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8412 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8413 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8414 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8415 + update \muxid$next $0\muxid$next[1:0]$8860 end - attribute \src "libresoc.v:151141.3-151159.6" - process $proc$libresoc.v:151141$8420 + attribute \src "libresoc.v:155626.3-155666.6" + process $proc$libresoc.v:155626$8862 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8421 $1\o$next[63:0]$8423 assign { } { } - assign $0\o_ok$next[0:0]$8422 $2\o_ok$next[0:0]$8425 - attribute \src "libresoc.v:151142.5-151142.29" - switch \initial - attribute \src "libresoc.v:151142.9-151142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8424 $1\o$next[63:0]$8423 } { \o_ok$30 \o$29 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8424 $1\o$next[63:0]$8423 } { \o_ok$30 \o$29 } - case - assign $1\o$next[63:0]$8423 \o - assign $1\o_ok$next[0:0]$8424 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8425 1'0 - case - assign $2\o_ok$next[0:0]$8425 $1\o_ok$next[0:0]$8424 - end - sync always - update \o$next $0\o$next[63:0]$8421 - update \o_ok$next $0\o_ok$next[0:0]$8422 - end - attribute \src "libresoc.v:151160.3-151178.6" - process $proc$libresoc.v:151160$8426 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8427 $1\spr1$6$next[63:0]$8429 assign { } { } - assign $0\spr1_ok$next[0:0]$8428 $2\spr1_ok$next[0:0]$8431 - attribute \src "libresoc.v:151161.5-151161.29" - switch \initial - attribute \src "libresoc.v:151161.9-151161.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8430 $1\spr1$6$next[63:0]$8429 } { \spr1_ok$32 \spr1$31 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8430 $1\spr1$6$next[63:0]$8429 } { \spr1_ok$32 \spr1$31 } - case - assign $1\spr1$6$next[63:0]$8429 \spr1$6 - assign $1\spr1_ok$next[0:0]$8430 \spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\spr1_ok$next[0:0]$8431 1'0 - case - assign $2\spr1_ok$next[0:0]$8431 $1\spr1_ok$next[0:0]$8430 - end - sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8427 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8428 - end - attribute \src "libresoc.v:151179.3-151197.6" - process $proc$libresoc.v:151179$8432 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8434 $1\fast1$7$next[63:0]$8436 - assign $0\fast1_ok$next[0:0]$8433 $2\fast1_ok$next[0:0]$8437 - attribute \src "libresoc.v:151180.5-151180.29" + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[11:0]$8863 $1\sr_op__fn_unit$next[11:0]$8880 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$8866 $1\sr_op__input_carry$next[1:0]$8883 + assign $0\sr_op__input_cr$next[0:0]$8867 $1\sr_op__input_cr$next[0:0]$8884 + assign $0\sr_op__insn$next[31:0]$8868 $1\sr_op__insn$next[31:0]$8885 + assign $0\sr_op__insn_type$next[6:0]$8869 $1\sr_op__insn_type$next[6:0]$8886 + assign $0\sr_op__invert_in$next[0:0]$8870 $1\sr_op__invert_in$next[0:0]$8887 + assign $0\sr_op__is_32bit$next[0:0]$8871 $1\sr_op__is_32bit$next[0:0]$8888 + assign $0\sr_op__is_signed$next[0:0]$8872 $1\sr_op__is_signed$next[0:0]$8889 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$8875 $1\sr_op__output_carry$next[0:0]$8892 + assign $0\sr_op__output_cr$next[0:0]$8876 $1\sr_op__output_cr$next[0:0]$8893 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$8879 $1\sr_op__write_cr0$next[0:0]$8896 + assign $0\sr_op__imm_data__data$next[63:0]$8864 $2\sr_op__imm_data__data$next[63:0]$8897 + assign $0\sr_op__imm_data__ok$next[0:0]$8865 $2\sr_op__imm_data__ok$next[0:0]$8898 + assign $0\sr_op__oe__oe$next[0:0]$8873 $2\sr_op__oe__oe$next[0:0]$8899 + assign $0\sr_op__oe__ok$next[0:0]$8874 $2\sr_op__oe__ok$next[0:0]$8900 + assign $0\sr_op__rc__ok$next[0:0]$8877 $2\sr_op__rc__ok$next[0:0]$8901 + assign $0\sr_op__rc__rc$next[0:0]$8878 $2\sr_op__rc__rc$next[0:0]$8902 + attribute \src "libresoc.v:155627.5-155627.29" switch \initial - attribute \src "libresoc.v:151180.9-151180.17" + attribute \src "libresoc.v:155627.9-155627.17" case 1'1 case end @@ -312599,41 +322083,116 @@ module \pipe$61 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8435 $1\fast1$7$next[63:0]$8436 } { \fast1_ok$34 \fast1$33 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8885 $1\sr_op__is_signed$next[0:0]$8889 $1\sr_op__is_32bit$next[0:0]$8888 $1\sr_op__output_cr$next[0:0]$8893 $1\sr_op__input_cr$next[0:0]$8884 $1\sr_op__output_carry$next[0:0]$8892 $1\sr_op__input_carry$next[1:0]$8883 $1\sr_op__invert_in$next[0:0]$8887 $1\sr_op__write_cr0$next[0:0]$8896 $1\sr_op__oe__ok$next[0:0]$8891 $1\sr_op__oe__oe$next[0:0]$8890 $1\sr_op__rc__ok$next[0:0]$8894 $1\sr_op__rc__rc$next[0:0]$8895 $1\sr_op__imm_data__ok$next[0:0]$8882 $1\sr_op__imm_data__data$next[63:0]$8881 $1\sr_op__fn_unit$next[11:0]$8880 $1\sr_op__insn_type$next[6:0]$8886 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8435 $1\fast1$7$next[63:0]$8436 } { \fast1_ok$34 \fast1$33 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8885 $1\sr_op__is_signed$next[0:0]$8889 $1\sr_op__is_32bit$next[0:0]$8888 $1\sr_op__output_cr$next[0:0]$8893 $1\sr_op__input_cr$next[0:0]$8884 $1\sr_op__output_carry$next[0:0]$8892 $1\sr_op__input_carry$next[1:0]$8883 $1\sr_op__invert_in$next[0:0]$8887 $1\sr_op__write_cr0$next[0:0]$8896 $1\sr_op__oe__ok$next[0:0]$8891 $1\sr_op__oe__oe$next[0:0]$8890 $1\sr_op__rc__ok$next[0:0]$8894 $1\sr_op__rc__rc$next[0:0]$8895 $1\sr_op__imm_data__ok$next[0:0]$8882 $1\sr_op__imm_data__data$next[63:0]$8881 $1\sr_op__fn_unit$next[11:0]$8880 $1\sr_op__insn_type$next[6:0]$8886 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\fast1_ok$next[0:0]$8435 \fast1_ok - assign $1\fast1$7$next[63:0]$8436 \fast1$7 + assign $1\sr_op__fn_unit$next[11:0]$8880 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$8881 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$8882 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$8883 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$8884 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$8885 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$8886 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$8887 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$8888 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$8889 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$8890 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$8891 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$8892 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$8893 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$8894 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$8895 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$8896 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8437 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$8898 1'0 + assign $2\sr_op__rc__rc$next[0:0]$8902 1'0 + assign $2\sr_op__rc__ok$next[0:0]$8901 1'0 + assign $2\sr_op__oe__oe$next[0:0]$8899 1'0 + assign $2\sr_op__oe__ok$next[0:0]$8900 1'0 case - assign $2\fast1_ok$next[0:0]$8437 $1\fast1_ok$next[0:0]$8435 + assign $2\sr_op__imm_data__data$next[63:0]$8897 $1\sr_op__imm_data__data$next[63:0]$8881 + assign $2\sr_op__imm_data__ok$next[0:0]$8898 $1\sr_op__imm_data__ok$next[0:0]$8882 + assign $2\sr_op__oe__oe$next[0:0]$8899 $1\sr_op__oe__oe$next[0:0]$8890 + assign $2\sr_op__oe__ok$next[0:0]$8900 $1\sr_op__oe__ok$next[0:0]$8891 + assign $2\sr_op__rc__ok$next[0:0]$8901 $1\sr_op__rc__ok$next[0:0]$8894 + assign $2\sr_op__rc__rc$next[0:0]$8902 $1\sr_op__rc__rc$next[0:0]$8895 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8433 - update \fast1$7$next $0\fast1$7$next[63:0]$8434 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8863 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8864 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8865 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8866 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8867 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8868 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8869 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$8870 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8871 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8872 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8873 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8874 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8875 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8876 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8877 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8878 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8879 end - attribute \src "libresoc.v:151198.3-151216.6" - process $proc$libresoc.v:151198$8438 + attribute \src "libresoc.v:155667.3-155685.6" + process $proc$libresoc.v:155667$8903 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$next[63:0]$8904 $1\o$next[63:0]$8906 assign { } { } - assign $0\xer_so$8$next[0:0]$8440 $1\xer_so$8$next[0:0]$8442 - assign $0\xer_so_ok$next[0:0]$8439 $2\xer_so_ok$next[0:0]$8443 - attribute \src "libresoc.v:151199.5-151199.29" + assign $0\o_ok$next[0:0]$8905 $2\o_ok$next[0:0]$8908 + attribute \src "libresoc.v:155668.5-155668.29" switch \initial - attribute \src "libresoc.v:151199.9-151199.17" + attribute \src "libresoc.v:155668.9-155668.17" case 1'1 case end @@ -312643,41 +322202,41 @@ module \pipe$61 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8441 $1\xer_so$8$next[0:0]$8442 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8907 $1\o$next[63:0]$8906 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8441 $1\xer_so$8$next[0:0]$8442 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8907 $1\o$next[63:0]$8906 } { \o_ok$86 \o$85 } case - assign $1\xer_so_ok$next[0:0]$8441 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8442 \xer_so$8 + assign $1\o$next[63:0]$8906 \o + assign $1\o_ok$next[0:0]$8907 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8443 1'0 + assign $2\o_ok$next[0:0]$8908 1'0 case - assign $2\xer_so_ok$next[0:0]$8443 $1\xer_so_ok$next[0:0]$8441 + assign $2\o_ok$next[0:0]$8908 $1\o_ok$next[0:0]$8907 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8439 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8440 + update \o$next $0\o$next[63:0]$8904 + update \o_ok$next $0\o_ok$next[0:0]$8905 end - attribute \src "libresoc.v:151217.3-151235.6" - process $proc$libresoc.v:151217$8444 + attribute \src "libresoc.v:155686.3-155704.6" + process $proc$libresoc.v:155686$8909 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\cr_a$next[3:0]$8910 $1\cr_a$next[3:0]$8912 assign { } { } - assign $0\xer_ov$9$next[1:0]$8446 $1\xer_ov$9$next[1:0]$8448 - assign $0\xer_ov_ok$next[0:0]$8445 $2\xer_ov_ok$next[0:0]$8449 - attribute \src "libresoc.v:151218.5-151218.29" + assign $0\cr_a_ok$next[0:0]$8911 $2\cr_a_ok$next[0:0]$8914 + attribute \src "libresoc.v:155687.5-155687.29" switch \initial - attribute \src "libresoc.v:151218.9-151218.17" + attribute \src "libresoc.v:155687.9-155687.17" case 1'1 case end @@ -312687,41 +322246,41 @@ module \pipe$61 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8447 $1\xer_ov$9$next[1:0]$8448 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\cr_a_ok$next[0:0]$8913 $1\cr_a$next[3:0]$8912 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8447 $1\xer_ov$9$next[1:0]$8448 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\cr_a_ok$next[0:0]$8913 $1\cr_a$next[3:0]$8912 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\xer_ov_ok$next[0:0]$8447 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8448 \xer_ov$9 + assign $1\cr_a$next[3:0]$8912 \cr_a + assign $1\cr_a_ok$next[0:0]$8913 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8449 1'0 + assign $2\cr_a_ok$next[0:0]$8914 1'0 case - assign $2\xer_ov_ok$next[0:0]$8449 $1\xer_ov_ok$next[0:0]$8447 + assign $2\cr_a_ok$next[0:0]$8914 $1\cr_a_ok$next[0:0]$8913 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8445 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8446 + update \cr_a$next $0\cr_a$next[3:0]$8910 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8911 end - attribute \src "libresoc.v:151236.3-151254.6" - process $proc$libresoc.v:151236$8450 + attribute \src "libresoc.v:155705.3-155723.6" + process $proc$libresoc.v:155705$8915 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8451 $1\xer_ca$10$next[1:0]$8453 + assign $0\xer_so$next[0:0]$8916 $1\xer_so$next[0:0]$8918 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8452 $2\xer_ca_ok$next[0:0]$8455 - attribute \src "libresoc.v:151237.5-151237.29" + assign $0\xer_so_ok$next[0:0]$8917 $2\xer_so_ok$next[0:0]$8920 + attribute \src "libresoc.v:155706.5-155706.29" switch \initial - attribute \src "libresoc.v:151237.9-151237.17" + attribute \src "libresoc.v:155706.9-155706.17" case 1'1 case end @@ -312731,350 +322290,221 @@ module \pipe$61 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8454 $1\xer_ca$10$next[1:0]$8453 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_so_ok$next[0:0]$8919 $1\xer_so$next[0:0]$8918 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8454 $1\xer_ca$10$next[1:0]$8453 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_so_ok$next[0:0]$8919 $1\xer_so$next[0:0]$8918 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_ca$10$next[1:0]$8453 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8454 \xer_ca_ok + assign $1\xer_so$next[0:0]$8918 \xer_so + assign $1\xer_so_ok$next[0:0]$8919 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8455 1'0 + assign $2\xer_so_ok$next[0:0]$8920 1'0 case - assign $2\xer_ca_ok$next[0:0]$8455 $1\xer_ca_ok$next[0:0]$8454 + assign $2\xer_so_ok$next[0:0]$8920 $1\xer_so_ok$next[0:0]$8919 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8451 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8452 + update \xer_so$next $0\xer_so$next[0:0]$8916 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8917 end - connect \$22 $and$libresoc.v:151019$8375_Y + connect \$65 $and$libresoc.v:155419$8821_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - connect \muxid$24 \spr_main_muxid$11 - connect \p_valid_i_p_ready_o \$22 + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$21 \p_valid_i - connect \spr_main_xer_ca \xer_ca - connect \spr_main_xer_ov \xer_ov - connect \spr_main_xer_so \xer_so - connect \spr_main_fast1 \fast1 - connect \spr_main_spr1 \spr1 - connect \spr_main_ra \ra - connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \spr_main_muxid \muxid + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:151280.1-152751.10" +attribute \src "libresoc.v:155757.1-156590.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" -module \pipe1 - attribute \src "libresoc.v:152665.3-152706.6" - wire width 4 $0\alu_op__data_len$next[3:0]$8548 - attribute \src "libresoc.v:152441.3-152442.49" - wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 12 $0\alu_op__fn_unit$next[11:0]$8549 - attribute \src "libresoc.v:152411.3-152412.47" - wire width 12 $0\alu_op__fn_unit[11:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$8550 - attribute \src "libresoc.v:152413.3-152414.61" - wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__imm_data__ok$next[0:0]$8551 - attribute \src "libresoc.v:152415.3-152416.57" - wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$8552 - attribute \src "libresoc.v:152433.3-152434.55" - wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 32 $0\alu_op__insn$next[31:0]$8553 - attribute \src "libresoc.v:152443.3-152444.41" - wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$8554 - attribute \src "libresoc.v:152409.3-152410.51" - wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__invert_in$next[0:0]$8555 - attribute \src "libresoc.v:152425.3-152426.51" - wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__invert_out$next[0:0]$8556 - attribute \src "libresoc.v:152429.3-152430.53" - wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__is_32bit$next[0:0]$8557 - attribute \src "libresoc.v:152437.3-152438.49" - wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__is_signed$next[0:0]$8558 - attribute \src "libresoc.v:152439.3-152440.51" - wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__oe__oe$next[0:0]$8559 - attribute \src "libresoc.v:152421.3-152422.45" - wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__oe__ok$next[0:0]$8560 - attribute \src "libresoc.v:152423.3-152424.45" - wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__output_carry$next[0:0]$8561 - attribute \src "libresoc.v:152435.3-152436.57" - wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__rc__ok$next[0:0]$8562 - attribute \src "libresoc.v:152419.3-152420.45" - wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__rc__rc$next[0:0]$8563 - attribute \src "libresoc.v:152417.3-152418.45" - wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__write_cr0$next[0:0]$8564 - attribute \src "libresoc.v:152431.3-152432.51" - wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $0\alu_op__zero_a$next[0:0]$8565 - attribute \src "libresoc.v:152427.3-152428.45" - wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:152558.3-152576.6" - wire width 4 $0\cr_a$next[3:0]$8517 - attribute \src "libresoc.v:152401.3-152402.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:152558.3-152576.6" - wire $0\cr_a_ok$next[0:0]$8518 - attribute \src "libresoc.v:152403.3-152404.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:151281.7-151281.20" +module \pipe1$32 + attribute \src "libresoc.v:156547.3-156559.6" + wire width 64 $0\fast1$next[63:0]$8998 + attribute \src "libresoc.v:156401.3-156402.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:156560.3-156572.6" + wire width 64 $0\fast2$next[63:0]$9001 + attribute \src "libresoc.v:156429.3-156430.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:155758.7-155758.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152652.3-152664.6" - wire width 2 $0\muxid$next[1:0]$8545 - attribute \src "libresoc.v:152445.3-152446.27" + attribute \src "libresoc.v:156487.3-156499.6" + wire width 2 $0\muxid$next[1:0]$8970 + attribute \src "libresoc.v:156425.3-156426.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:152707.3-152725.6" - wire width 64 $0\o$next[63:0]$8591 - attribute \src "libresoc.v:152405.3-152406.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:152707.3-152725.6" - wire $0\o_ok$next[0:0]$8592 - attribute \src "libresoc.v:152407.3-152408.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:152634.3-152651.6" - wire $0\r_busy$next[0:0]$8541 - attribute \src "libresoc.v:152447.3-152448.29" + attribute \src "libresoc.v:156469.3-156486.6" + wire $0\r_busy$next[0:0]$8966 + attribute \src "libresoc.v:156427.3-156428.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:152577.3-152595.6" - wire width 2 $0\xer_ca$next[1:0]$8524 - attribute \src "libresoc.v:152397.3-152398.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:152577.3-152595.6" - wire $0\xer_ca_ok$next[0:0]$8523 - attribute \src "libresoc.v:152399.3-152400.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:152596.3-152614.6" - wire width 2 $0\xer_ov$next[1:0]$8529 - attribute \src "libresoc.v:152393.3-152394.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:152596.3-152614.6" - wire $0\xer_ov_ok$next[0:0]$8530 - attribute \src "libresoc.v:152395.3-152396.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:152615.3-152633.6" - wire $0\xer_so$next[0:0]$8535 - attribute \src "libresoc.v:152389.3-152390.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:152615.3-152633.6" - wire $0\xer_so_ok$next[0:0]$8536 - attribute \src "libresoc.v:152391.3-152392.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 4 $1\alu_op__data_len$next[3:0]$8566 - attribute \src "libresoc.v:151286.13-151286.36" - wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 12 $1\alu_op__fn_unit$next[11:0]$8567 - attribute \src "libresoc.v:151308.14-151308.39" - wire width 12 $1\alu_op__fn_unit[11:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$8568 - attribute \src "libresoc.v:151343.14-151343.59" - wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__imm_data__ok$next[0:0]$8569 - attribute \src "libresoc.v:151352.7-151352.34" - wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$8570 - attribute \src "libresoc.v:151365.13-151365.39" - wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 32 $1\alu_op__insn$next[31:0]$8571 - attribute \src "libresoc.v:151382.14-151382.34" - wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$8572 - attribute \src "libresoc.v:151465.13-151465.38" - wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__invert_in$next[0:0]$8573 - attribute \src "libresoc.v:151622.7-151622.31" - wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__invert_out$next[0:0]$8574 - attribute \src "libresoc.v:151631.7-151631.32" - wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__is_32bit$next[0:0]$8575 - attribute \src "libresoc.v:151640.7-151640.30" - wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__is_signed$next[0:0]$8576 - attribute \src "libresoc.v:151649.7-151649.31" - wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__oe__oe$next[0:0]$8577 - attribute \src "libresoc.v:151658.7-151658.28" - wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__oe__ok$next[0:0]$8578 - attribute \src "libresoc.v:151667.7-151667.28" - wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__output_carry$next[0:0]$8579 - attribute \src "libresoc.v:151676.7-151676.34" - wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__rc__ok$next[0:0]$8580 - attribute \src "libresoc.v:151685.7-151685.28" - wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__rc__rc$next[0:0]$8581 - attribute \src "libresoc.v:151694.7-151694.28" - wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__write_cr0$next[0:0]$8582 - attribute \src "libresoc.v:151703.7-151703.31" - wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire $1\alu_op__zero_a$next[0:0]$8583 - attribute \src "libresoc.v:151712.7-151712.28" - wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:152558.3-152576.6" - wire width 4 $1\cr_a$next[3:0]$8519 - attribute \src "libresoc.v:151725.13-151725.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:152558.3-152576.6" - wire $1\cr_a_ok$next[0:0]$8520 - attribute \src "libresoc.v:151732.7-151732.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:152652.3-152664.6" - wire width 2 $1\muxid$next[1:0]$8546 - attribute \src "libresoc.v:152297.13-152297.25" + attribute \src "libresoc.v:156521.3-156533.6" + wire width 64 $0\ra$next[63:0]$8992 + attribute \src "libresoc.v:156405.3-156406.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:156534.3-156546.6" + wire width 64 $0\rb$next[63:0]$8995 + attribute \src "libresoc.v:156403.3-156404.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 64 $0\trap_op__cia$next[63:0]$8973 + attribute \src "libresoc.v:156415.3-156416.41" + wire width 64 $0\trap_op__cia[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 12 $0\trap_op__fn_unit$next[11:0]$8974 + attribute \src "libresoc.v:156409.3-156410.49" + wire width 12 $0\trap_op__fn_unit[11:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 32 $0\trap_op__insn$next[31:0]$8975 + attribute \src "libresoc.v:156411.3-156412.43" + wire width 32 $0\trap_op__insn[31:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$8976 + attribute \src "libresoc.v:156407.3-156408.53" + wire width 7 $0\trap_op__insn_type[6:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire $0\trap_op__is_32bit$next[0:0]$8977 + attribute \src "libresoc.v:156417.3-156418.51" + wire $0\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$8978 + attribute \src "libresoc.v:156423.3-156424.51" + wire width 8 $0\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 64 $0\trap_op__msr$next[63:0]$8979 + attribute \src "libresoc.v:156413.3-156414.41" + wire width 64 $0\trap_op__msr[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$8980 + attribute \src "libresoc.v:156421.3-156422.51" + wire width 13 $0\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 8 $0\trap_op__traptype$next[7:0]$8981 + attribute \src "libresoc.v:156419.3-156420.51" + wire width 8 $0\trap_op__traptype[7:0] + attribute \src "libresoc.v:156547.3-156559.6" + wire width 64 $1\fast1$next[63:0]$8999 + attribute \src "libresoc.v:155997.14-155997.42" + wire width 64 $1\fast1[63:0] + attribute \src "libresoc.v:156560.3-156572.6" + wire width 64 $1\fast2$next[63:0]$9002 + attribute \src "libresoc.v:156006.14-156006.42" + wire width 64 $1\fast2[63:0] + attribute \src "libresoc.v:156487.3-156499.6" + wire width 2 $1\muxid$next[1:0]$8971 + attribute \src "libresoc.v:156015.13-156015.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:152707.3-152725.6" - wire width 64 $1\o$next[63:0]$8593 - attribute \src "libresoc.v:152312.14-152312.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:152707.3-152725.6" - wire $1\o_ok$next[0:0]$8594 - attribute \src "libresoc.v:152319.7-152319.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:152634.3-152651.6" - wire $1\r_busy$next[0:0]$8542 - attribute \src "libresoc.v:152333.7-152333.20" + attribute \src "libresoc.v:156469.3-156486.6" + wire $1\r_busy$next[0:0]$8967 + attribute \src "libresoc.v:156037.7-156037.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:152577.3-152595.6" - wire width 2 $1\xer_ca$next[1:0]$8526 - attribute \src "libresoc.v:152342.13-152342.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:152577.3-152595.6" - wire $1\xer_ca_ok$next[0:0]$8525 - attribute \src "libresoc.v:152351.7-152351.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:152596.3-152614.6" - wire width 2 $1\xer_ov$next[1:0]$8531 - attribute \src "libresoc.v:152358.13-152358.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:152596.3-152614.6" - wire $1\xer_ov_ok$next[0:0]$8532 - attribute \src "libresoc.v:152365.7-152365.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:152615.3-152633.6" - wire $1\xer_so$next[0:0]$8537 - attribute \src "libresoc.v:152372.7-152372.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:152615.3-152633.6" - wire $1\xer_so_ok$next[0:0]$8538 - attribute \src "libresoc.v:152381.7-152381.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:152665.3-152706.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$8584 - attribute \src "libresoc.v:152665.3-152706.6" - wire $2\alu_op__imm_data__ok$next[0:0]$8585 - attribute \src "libresoc.v:152665.3-152706.6" - wire $2\alu_op__oe__oe$next[0:0]$8586 - attribute \src "libresoc.v:152665.3-152706.6" - wire $2\alu_op__oe__ok$next[0:0]$8587 - attribute \src "libresoc.v:152665.3-152706.6" - wire $2\alu_op__rc__ok$next[0:0]$8588 - attribute \src "libresoc.v:152665.3-152706.6" - wire $2\alu_op__rc__rc$next[0:0]$8589 - attribute \src "libresoc.v:152558.3-152576.6" - wire $2\cr_a_ok$next[0:0]$8521 - attribute \src "libresoc.v:152707.3-152725.6" - wire $2\o_ok$next[0:0]$8595 - attribute \src "libresoc.v:152634.3-152651.6" - wire $2\r_busy$next[0:0]$8543 - attribute \src "libresoc.v:152577.3-152595.6" - wire $2\xer_ca_ok$next[0:0]$8527 - attribute \src "libresoc.v:152596.3-152614.6" - wire $2\xer_ov_ok$next[0:0]$8533 - attribute \src "libresoc.v:152615.3-152633.6" - wire $2\xer_so_ok$next[0:0]$8539 - attribute \src "libresoc.v:152388.18-152388.118" - wire $and$libresoc.v:152388$8485_Y + attribute \src "libresoc.v:156521.3-156533.6" + wire width 64 $1\ra$next[63:0]$8993 + attribute \src "libresoc.v:156042.14-156042.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:156534.3-156546.6" + wire width 64 $1\rb$next[63:0]$8996 + attribute \src "libresoc.v:156051.14-156051.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 64 $1\trap_op__cia$next[63:0]$8982 + attribute \src "libresoc.v:156060.14-156060.49" + wire width 64 $1\trap_op__cia[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 12 $1\trap_op__fn_unit$next[11:0]$8983 + attribute \src "libresoc.v:156082.14-156082.40" + wire width 12 $1\trap_op__fn_unit[11:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 32 $1\trap_op__insn$next[31:0]$8984 + attribute \src "libresoc.v:156117.14-156117.35" + wire width 32 $1\trap_op__insn[31:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$8985 + attribute \src "libresoc.v:156200.13-156200.39" + wire width 7 $1\trap_op__insn_type[6:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire $1\trap_op__is_32bit$next[0:0]$8986 + attribute \src "libresoc.v:156357.7-156357.31" + wire $1\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$8987 + attribute \src "libresoc.v:156366.13-156366.38" + wire width 8 $1\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 64 $1\trap_op__msr$next[63:0]$8988 + attribute \src "libresoc.v:156375.14-156375.49" + wire width 64 $1\trap_op__msr[63:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$8989 + attribute \src "libresoc.v:156384.14-156384.42" + wire width 13 $1\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:156500.3-156520.6" + wire width 8 $1\trap_op__traptype$next[7:0]$8990 + attribute \src "libresoc.v:156393.13-156393.38" + wire width 8 $1\trap_op__traptype[7:0] + attribute \src "libresoc.v:156469.3-156486.6" + wire $2\r_busy$next[0:0]$8968 + attribute \src "libresoc.v:156400.18-156400.118" + wire $and$libresoc.v:156400$8949_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$86 + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \dummy_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \dummy_muxid$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" + wire width 64 \dummy_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \alu_op__fn_unit + wire width 64 \dummy_trap_op__cia$20 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -313089,7 +322519,7 @@ module \pipe1 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 37 \alu_op__fn_unit$3 + wire width 12 \dummy_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -313104,129 +322534,11 @@ module \pipe1 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 48 \alu_op__input_carry$14 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$87 + wire width 12 \dummy_trap_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 \dummy_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type + wire width 32 \dummy_trap_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313302,7 +322614,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 36 \alu_op__insn_type$2 + wire width 7 \dummy_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313378,119 +322690,95 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$next + wire width 7 \dummy_trap_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \alu_op__rc__rc + wire \dummy_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \alu_op__rc__rc$6 + wire \dummy_trap_op__is_32bit$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$74 + wire width 8 \dummy_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$next + wire width 8 \dummy_trap_op__ldst_exc$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \alu_op__write_cr0 + wire width 64 \dummy_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \alu_op__write_cr0$13 + wire width 64 \dummy_trap_op__msr$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$81 + wire width 13 \dummy_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$next + wire width 13 \dummy_trap_op__trapaddr$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \alu_op__zero_a + wire width 8 \dummy_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \alu_op__zero_a$11 + wire width 8 \dummy_trap_op__traptype$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$next + attribute \src "libresoc.v:155758.7-155758.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 19 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 18 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$79 + wire width 64 output 9 \trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "libresoc.v:151281.7-151281.15" - wire \initial + wire width 64 \trap_op__cia$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len + wire width 64 input 25 \trap_op__cia$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 + wire width 64 \trap_op__cia$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -313505,7 +322793,7 @@ module \pipe1 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit + wire width 12 output 6 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -313520,107 +322808,32 @@ module \pipe1 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok + wire width 12 input 22 \trap_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok$26 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 12 \trap_op__fn_unit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 12 \trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry$35 + wire width 32 output 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn + wire width 32 \trap_op__insn$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn$40 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 input 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type + wire width 32 \trap_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313696,129 +322909,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len$62 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_alu_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok$49 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn$63 + wire width 7 output 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313894,7 +322985,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type + wire width 7 input 21 \trap_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313970,763 +323061,346 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in + wire width 7 \trap_op__insn_type$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in$54 + wire width 7 \trap_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out + wire output 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out$56 + wire \trap_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit + wire input 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit$60 + wire \trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed + wire width 8 output 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed$61 + wire width 8 input 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe + wire width 8 \trap_op__ldst_exc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe$52 + wire width 8 \trap_op__ldst_exc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok + wire width 64 output 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok$53 + wire width 64 \trap_op__msr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry + wire width 64 input 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry$59 + wire width 64 \trap_op__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok + wire width 13 output 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok$51 + wire width 13 \trap_op__trapaddr$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc + wire width 13 input 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc$50 + wire width 13 \trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0 + wire width 8 output 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0$57 + wire width 8 \trap_op__traptype$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a + wire width 8 input 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_so$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 54 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next + wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:152388$8485 + cell $and $and$libresoc.v:156400$8949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 + connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:152388$8485_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152449.11-152496.4" - cell \input \input - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__insn \input_alu_op__insn - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \alu_op__insn_type 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\input_alu_op__rc__rc - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$22 - connect \ra \input_ra - connect \ra$20 \input_ra$41 - connect \rb \input_rb - connect \rb$21 \input_rb$42 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$44 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$43 + connect \Y $and$libresoc.v:156400$8949_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152497.8-152549.4" - cell \main \main - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__insn \main_alu_op__insn - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 - connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$45 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_ca \main_xer_ca - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so \main_xer_so - connect \xer_so$21 \main_xer_so$65 + attribute \module_not_derived 1 + attribute \src "libresoc.v:156431.9-156460.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:152550.9-152553.4" - cell \n$2 \n + attribute \src "libresoc.v:156461.10-156464.4" + cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:152554.9-152557.4" - cell \p$1 \p + attribute \src "libresoc.v:156465.10-156468.4" + cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:151281.7-151281.20" - process $proc$libresoc.v:151281$8596 + attribute \src "libresoc.v:155758.7-155758.20" + process $proc$libresoc.v:155758$9003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151286.13-151286.36" - process $proc$libresoc.v:151286$8597 - assign { } { } - assign $1\alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_op__data_len $1\alu_op__data_len[3:0] - end - attribute \src "libresoc.v:151308.14-151308.39" - process $proc$libresoc.v:151308$8598 - assign { } { } - assign $1\alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:151343.14-151343.59" - process $proc$libresoc.v:151343$8599 - assign { } { } - assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:151352.7-151352.34" - process $proc$libresoc.v:151352$8600 - assign { } { } - assign $1\alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:151365.13-151365.39" - process $proc$libresoc.v:151365$8601 - assign { } { } - assign $1\alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_op__input_carry $1\alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:151382.14-151382.34" - process $proc$libresoc.v:151382$8602 - assign { } { } - assign $1\alu_op__insn[31:0] 0 - sync always - sync init - update \alu_op__insn $1\alu_op__insn[31:0] - end - attribute \src "libresoc.v:151465.13-151465.38" - process $proc$libresoc.v:151465$8603 - assign { } { } - assign $1\alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_op__insn_type $1\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:151622.7-151622.31" - process $proc$libresoc.v:151622$8604 - assign { } { } - assign $1\alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_op__invert_in $1\alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:151631.7-151631.32" - process $proc$libresoc.v:151631$8605 - assign { } { } - assign $1\alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_op__invert_out $1\alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:151640.7-151640.30" - process $proc$libresoc.v:151640$8606 - assign { } { } - assign $1\alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:151649.7-151649.31" - process $proc$libresoc.v:151649$8607 - assign { } { } - assign $1\alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_op__is_signed $1\alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:151658.7-151658.28" - process $proc$libresoc.v:151658$8608 - assign { } { } - assign $1\alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:151667.7-151667.28" - process $proc$libresoc.v:151667$8609 - assign { } { } - assign $1\alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:151676.7-151676.34" - process $proc$libresoc.v:151676$8610 - assign { } { } - assign $1\alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_op__output_carry $1\alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:151685.7-151685.28" - process $proc$libresoc.v:151685$8611 - assign { } { } - assign $1\alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:151694.7-151694.28" - process $proc$libresoc.v:151694$8612 + attribute \src "libresoc.v:155997.14-155997.42" + process $proc$libresoc.v:155997$9004 assign { } { } - assign $1\alu_op__rc__rc[0:0] 1'0 + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:151703.7-151703.31" - process $proc$libresoc.v:151703$8613 + attribute \src "libresoc.v:156006.14-156006.42" + process $proc$libresoc.v:156006$9005 assign { } { } - assign $1\alu_op__write_cr0[0:0] 1'0 + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:151712.7-151712.28" - process $proc$libresoc.v:151712$8614 + attribute \src "libresoc.v:156015.13-156015.25" + process $proc$libresoc.v:156015$9006 assign { } { } - assign $1\alu_op__zero_a[0:0] 1'0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \alu_op__zero_a $1\alu_op__zero_a[0:0] + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:151725.13-151725.24" - process $proc$libresoc.v:151725$8615 + attribute \src "libresoc.v:156037.7-156037.20" + process $proc$libresoc.v:156037$9007 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \cr_a $1\cr_a[3:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:151732.7-151732.21" - process $proc$libresoc.v:151732$8616 + attribute \src "libresoc.v:156042.14-156042.39" + process $proc$libresoc.v:156042$9008 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \ra $1\ra[63:0] end - attribute \src "libresoc.v:152297.13-152297.25" - process $proc$libresoc.v:152297$8617 + attribute \src "libresoc.v:156051.14-156051.39" + process $proc$libresoc.v:156051$9009 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid $1\muxid[1:0] + update \rb $1\rb[63:0] end - attribute \src "libresoc.v:152312.14-152312.38" - process $proc$libresoc.v:152312$8618 + attribute \src "libresoc.v:156060.14-156060.49" + process $proc$libresoc.v:156060$9010 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o $1\o[63:0] + update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:152319.7-152319.18" - process $proc$libresoc.v:152319$8619 + attribute \src "libresoc.v:156082.14-156082.40" + process $proc$libresoc.v:156082$9011 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $1\trap_op__fn_unit[11:0] 12'000000000000 sync always sync init - update \o_ok $1\o_ok[0:0] + update \trap_op__fn_unit $1\trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:152333.7-152333.20" - process $proc$libresoc.v:152333$8620 + attribute \src "libresoc.v:156117.14-156117.35" + process $proc$libresoc.v:156117$9012 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\trap_op__insn[31:0] 0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:152342.13-152342.26" - process $proc$libresoc.v:152342$8621 + attribute \src "libresoc.v:156200.13-156200.39" + process $proc$libresoc.v:156200$9013 assign { } { } - assign $1\xer_ca[1:0] 2'00 + assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init - update \xer_ca $1\xer_ca[1:0] + update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:152351.7-152351.23" - process $proc$libresoc.v:152351$8622 + attribute \src "libresoc.v:156357.7-156357.31" + process $proc$libresoc.v:156357$9014 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:152358.13-152358.26" - process $proc$libresoc.v:152358$8623 + attribute \src "libresoc.v:156366.13-156366.38" + process $proc$libresoc.v:156366$9015 assign { } { } - assign $1\xer_ov[1:0] 2'00 + assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init - update \xer_ov $1\xer_ov[1:0] + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:152365.7-152365.23" - process $proc$libresoc.v:152365$8624 + attribute \src "libresoc.v:156375.14-156375.49" + process $proc$libresoc.v:156375$9016 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:152372.7-152372.20" - process $proc$libresoc.v:152372$8625 + attribute \src "libresoc.v:156384.14-156384.42" + process $proc$libresoc.v:156384$9017 assign { } { } - assign $1\xer_so[0:0] 1'0 + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init - update \xer_so $1\xer_so[0:0] + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:152381.7-152381.23" - process $proc$libresoc.v:152381$8626 + attribute \src "libresoc.v:156393.13-156393.38" + process $proc$libresoc.v:156393$9018 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:152389.3-152390.29" - process $proc$libresoc.v:152389$8486 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:152391.3-152392.35" - process $proc$libresoc.v:152391$8487 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:152393.3-152394.29" - process $proc$libresoc.v:152393$8488 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:152395.3-152396.35" - process $proc$libresoc.v:152395$8489 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:152397.3-152398.29" - process $proc$libresoc.v:152397$8490 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "libresoc.v:152399.3-152400.35" - process $proc$libresoc.v:152399$8491 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:152401.3-152402.25" - process $proc$libresoc.v:152401$8492 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:152403.3-152404.31" - process $proc$libresoc.v:152403$8493 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:152405.3-152406.19" - process $proc$libresoc.v:152405$8494 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:152407.3-152408.25" - process $proc$libresoc.v:152407$8495 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:152409.3-152410.51" - process $proc$libresoc.v:152409$8496 - assign { } { } - assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_op__insn_type $0\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:152411.3-152412.47" - process $proc$libresoc.v:152411$8497 - assign { } { } - assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:152413.3-152414.61" - process $proc$libresoc.v:152413$8498 - assign { } { } - assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:152415.3-152416.57" - process $proc$libresoc.v:152415$8499 - assign { } { } - assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:152417.3-152418.45" - process $proc$libresoc.v:152417$8500 - assign { } { } - assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next - sync posedge \coresync_clk - update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:152419.3-152420.45" - process $proc$libresoc.v:152419$8501 + attribute \src "libresoc.v:156401.3-156402.27" + process $proc$libresoc.v:156401$8950 assign { } { } - assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next - sync posedge \coresync_clk - update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:152421.3-152422.45" - process $proc$libresoc.v:152421$8502 - assign { } { } - assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk - update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:152423.3-152424.45" - process $proc$libresoc.v:152423$8503 + attribute \src "libresoc.v:156403.3-156404.21" + process $proc$libresoc.v:156403$8951 assign { } { } - assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + assign $0\rb[63:0] \rb$next sync posedge \coresync_clk - update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + update \rb $0\rb[63:0] end - attribute \src "libresoc.v:152425.3-152426.51" - process $proc$libresoc.v:152425$8504 + attribute \src "libresoc.v:156405.3-156406.21" + process $proc$libresoc.v:156405$8952 assign { } { } - assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + assign $0\ra[63:0] \ra$next sync posedge \coresync_clk - update \alu_op__invert_in $0\alu_op__invert_in[0:0] + update \ra $0\ra[63:0] end - attribute \src "libresoc.v:152427.3-152428.45" - process $proc$libresoc.v:152427$8505 + attribute \src "libresoc.v:156407.3-156408.53" + process $proc$libresoc.v:156407$8953 assign { } { } - assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk - update \alu_op__zero_a $0\alu_op__zero_a[0:0] + update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:152429.3-152430.53" - process $proc$libresoc.v:152429$8506 + attribute \src "libresoc.v:156409.3-156410.49" + process $proc$libresoc.v:156409$8954 assign { } { } - assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + assign $0\trap_op__fn_unit[11:0] \trap_op__fn_unit$next sync posedge \coresync_clk - update \alu_op__invert_out $0\alu_op__invert_out[0:0] + update \trap_op__fn_unit $0\trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:152431.3-152432.51" - process $proc$libresoc.v:152431$8507 + attribute \src "libresoc.v:156411.3-156412.43" + process $proc$libresoc.v:156411$8955 assign { } { } - assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk - update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:152433.3-152434.55" - process $proc$libresoc.v:152433$8508 + attribute \src "libresoc.v:156413.3-156414.41" + process $proc$libresoc.v:156413$8956 assign { } { } - assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk - update \alu_op__input_carry $0\alu_op__input_carry[1:0] + update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:152435.3-152436.57" - process $proc$libresoc.v:152435$8509 + attribute \src "libresoc.v:156415.3-156416.41" + process $proc$libresoc.v:156415$8957 assign { } { } - assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk - update \alu_op__output_carry $0\alu_op__output_carry[0:0] + update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:152437.3-152438.49" - process $proc$libresoc.v:152437$8510 + attribute \src "libresoc.v:156417.3-156418.51" + process $proc$libresoc.v:156417$8958 assign { } { } - assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk - update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:152439.3-152440.51" - process $proc$libresoc.v:152439$8511 + attribute \src "libresoc.v:156419.3-156420.51" + process $proc$libresoc.v:156419$8959 assign { } { } - assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk - update \alu_op__is_signed $0\alu_op__is_signed[0:0] + update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:152441.3-152442.49" - process $proc$libresoc.v:152441$8512 + attribute \src "libresoc.v:156421.3-156422.51" + process $proc$libresoc.v:156421$8960 assign { } { } - assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk - update \alu_op__data_len $0\alu_op__data_len[3:0] + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:152443.3-152444.41" - process $proc$libresoc.v:152443$8513 + attribute \src "libresoc.v:156423.3-156424.51" + process $proc$libresoc.v:156423$8961 assign { } { } - assign $0\alu_op__insn[31:0] \alu_op__insn$next + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk - update \alu_op__insn $0\alu_op__insn[31:0] + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:152445.3-152446.27" - process $proc$libresoc.v:152445$8514 + attribute \src "libresoc.v:156425.3-156426.27" + process $proc$libresoc.v:156425$8962 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:152447.3-152448.29" - process $proc$libresoc.v:152447$8515 + attribute \src "libresoc.v:156427.3-156428.29" + process $proc$libresoc.v:156427$8963 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:152558.3-152576.6" - process $proc$libresoc.v:152558$8516 - assign { } { } + attribute \src "libresoc.v:156429.3-156430.27" + process $proc$libresoc.v:156429$8964 assign { } { } + assign $0\fast2[63:0] \fast2$next + sync posedge \coresync_clk + update \fast2 $0\fast2[63:0] + end + attribute \src "libresoc.v:156469.3-156486.6" + process $proc$libresoc.v:156469$8965 assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8517 $1\cr_a$next[3:0]$8519 assign { } { } - assign $0\cr_a_ok$next[0:0]$8518 $2\cr_a_ok$next[0:0]$8521 - attribute \src "libresoc.v:152559.5-152559.29" + assign $0\r_busy$next[0:0]$8966 $2\r_busy$next[0:0]$8968 + attribute \src "libresoc.v:156470.5-156470.29" switch \initial - attribute \src "libresoc.v:152559.9-152559.17" + attribute \src "libresoc.v:156470.9-156470.17" case 1'1 case end @@ -314735,42 +323409,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8520 $1\cr_a$next[3:0]$8519 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8967 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8520 $1\cr_a$next[3:0]$8519 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8967 1'0 case - assign $1\cr_a$next[3:0]$8519 \cr_a - assign $1\cr_a_ok$next[0:0]$8520 \cr_a_ok + assign $1\r_busy$next[0:0]$8967 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8521 1'0 + assign $2\r_busy$next[0:0]$8968 1'0 case - assign $2\cr_a_ok$next[0:0]$8521 $1\cr_a_ok$next[0:0]$8520 + assign $2\r_busy$next[0:0]$8968 $1\r_busy$next[0:0]$8967 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8517 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8518 + update \r_busy$next $0\r_busy$next[0:0]$8966 end - attribute \src "libresoc.v:152577.3-152595.6" - process $proc$libresoc.v:152577$8522 - assign { } { } - assign { } { } + attribute \src "libresoc.v:156487.3-156499.6" + process $proc$libresoc.v:156487$8969 assign { } { } assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8524 $1\xer_ca$next[1:0]$8526 - assign $0\xer_ca_ok$next[0:0]$8523 $2\xer_ca_ok$next[0:0]$8527 - attribute \src "libresoc.v:152578.5-152578.29" + assign $0\muxid$next[1:0]$8970 $1\muxid$next[1:0]$8971 + attribute \src "libresoc.v:156488.5-156488.29" switch \initial - attribute \src "libresoc.v:152578.9-152578.17" + attribute \src "libresoc.v:156488.9-156488.17" case 1'1 case end @@ -314779,86 +323445,49 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8525 $1\xer_ca$next[1:0]$8526 } { \xer_ca_ok$93 \xer_ca$92 } + assign $1\muxid$next[1:0]$8971 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8525 $1\xer_ca$next[1:0]$8526 } { \xer_ca_ok$93 \xer_ca$92 } - case - assign $1\xer_ca_ok$next[0:0]$8525 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8526 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$8527 1'0 + assign $1\muxid$next[1:0]$8971 \muxid$32 case - assign $2\xer_ca_ok$next[0:0]$8527 $1\xer_ca_ok$next[0:0]$8525 + assign $1\muxid$next[1:0]$8971 \muxid end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8523 - update \xer_ca$next $0\xer_ca$next[1:0]$8524 + update \muxid$next $0\muxid$next[1:0]$8970 end - attribute \src "libresoc.v:152596.3-152614.6" - process $proc$libresoc.v:152596$8528 + attribute \src "libresoc.v:156500.3-156520.6" + process $proc$libresoc.v:156500$8972 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8529 $1\xer_ov$next[1:0]$8531 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8530 $2\xer_ov_ok$next[0:0]$8533 - attribute \src "libresoc.v:152597.5-152597.29" - switch \initial - attribute \src "libresoc.v:152597.9-152597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8532 $1\xer_ov$next[1:0]$8531 } { \xer_ov_ok$95 \xer_ov$94 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8532 $1\xer_ov$next[1:0]$8531 } { \xer_ov_ok$95 \xer_ov$94 } - case - assign $1\xer_ov$next[1:0]$8531 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8532 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$8533 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8533 $1\xer_ov_ok$next[0:0]$8532 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8529 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8530 - end - attribute \src "libresoc.v:152615.3-152633.6" - process $proc$libresoc.v:152615$8534 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8535 $1\xer_so$next[0:0]$8537 assign { } { } - assign $0\xer_so_ok$next[0:0]$8536 $2\xer_so_ok$next[0:0]$8539 - attribute \src "libresoc.v:152616.5-152616.29" + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$next[63:0]$8973 $1\trap_op__cia$next[63:0]$8982 + assign $0\trap_op__fn_unit$next[11:0]$8974 $1\trap_op__fn_unit$next[11:0]$8983 + assign $0\trap_op__insn$next[31:0]$8975 $1\trap_op__insn$next[31:0]$8984 + assign $0\trap_op__insn_type$next[6:0]$8976 $1\trap_op__insn_type$next[6:0]$8985 + assign $0\trap_op__is_32bit$next[0:0]$8977 $1\trap_op__is_32bit$next[0:0]$8986 + assign $0\trap_op__ldst_exc$next[7:0]$8978 $1\trap_op__ldst_exc$next[7:0]$8987 + assign $0\trap_op__msr$next[63:0]$8979 $1\trap_op__msr$next[63:0]$8988 + assign $0\trap_op__trapaddr$next[12:0]$8980 $1\trap_op__trapaddr$next[12:0]$8989 + assign $0\trap_op__traptype$next[7:0]$8981 $1\trap_op__traptype$next[7:0]$8990 + attribute \src "libresoc.v:156501.5-156501.29" switch \initial - attribute \src "libresoc.v:152616.9-152616.17" + attribute \src "libresoc.v:156501.9-156501.17" case 1'1 case end @@ -314868,38 +323497,56 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8538 $1\xer_so$next[0:0]$8537 } { \xer_so_ok$97 \xer_so$96 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$8987 $1\trap_op__trapaddr$next[12:0]$8989 $1\trap_op__traptype$next[7:0]$8990 $1\trap_op__is_32bit$next[0:0]$8986 $1\trap_op__cia$next[63:0]$8982 $1\trap_op__msr$next[63:0]$8988 $1\trap_op__insn$next[31:0]$8984 $1\trap_op__fn_unit$next[11:0]$8983 $1\trap_op__insn_type$next[6:0]$8985 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8538 $1\xer_so$next[0:0]$8537 } { \xer_so_ok$97 \xer_so$96 } - case - assign $1\xer_so$next[0:0]$8537 \xer_so - assign $1\xer_so_ok$next[0:0]$8538 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8539 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$8987 $1\trap_op__trapaddr$next[12:0]$8989 $1\trap_op__traptype$next[7:0]$8990 $1\trap_op__is_32bit$next[0:0]$8986 $1\trap_op__cia$next[63:0]$8982 $1\trap_op__msr$next[63:0]$8988 $1\trap_op__insn$next[31:0]$8984 $1\trap_op__fn_unit$next[11:0]$8983 $1\trap_op__insn_type$next[6:0]$8985 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $2\xer_so_ok$next[0:0]$8539 $1\xer_so_ok$next[0:0]$8538 + assign $1\trap_op__cia$next[63:0]$8982 \trap_op__cia + assign $1\trap_op__fn_unit$next[11:0]$8983 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$8984 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$8985 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$8986 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$8987 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$8988 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$8989 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$8990 \trap_op__traptype end sync always - update \xer_so$next $0\xer_so$next[0:0]$8535 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8536 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$8973 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[11:0]$8974 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$8975 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$8976 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$8977 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$8978 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$8979 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$8980 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$8981 end - attribute \src "libresoc.v:152634.3-152651.6" - process $proc$libresoc.v:152634$8540 + attribute \src "libresoc.v:156521.3-156533.6" + process $proc$libresoc.v:156521$8991 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8541 $2\r_busy$next[0:0]$8543 - attribute \src "libresoc.v:152635.5-152635.29" + assign $0\ra$next[63:0]$8992 $1\ra$next[63:0]$8993 + attribute \src "libresoc.v:156522.5-156522.29" switch \initial - attribute \src "libresoc.v:152635.9-152635.17" + attribute \src "libresoc.v:156522.9-156522.17" case 1'1 case end @@ -314908,34 +323555,25 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8542 1'1 + assign $1\ra$next[63:0]$8993 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8542 1'0 - case - assign $1\r_busy$next[0:0]$8542 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$8543 1'0 + assign $1\ra$next[63:0]$8993 \ra$42 case - assign $2\r_busy$next[0:0]$8543 $1\r_busy$next[0:0]$8542 + assign $1\ra$next[63:0]$8993 \ra end sync always - update \r_busy$next $0\r_busy$next[0:0]$8541 + update \ra$next $0\ra$next[63:0]$8992 end - attribute \src "libresoc.v:152652.3-152664.6" - process $proc$libresoc.v:152652$8544 + attribute \src "libresoc.v:156534.3-156546.6" + process $proc$libresoc.v:156534$8994 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8545 $1\muxid$next[1:0]$8546 - attribute \src "libresoc.v:152653.5-152653.29" + assign $0\rb$next[63:0]$8995 $1\rb$next[63:0]$8996 + attribute \src "libresoc.v:156535.5-156535.29" switch \initial - attribute \src "libresoc.v:152653.9-152653.17" + attribute \src "libresoc.v:156535.9-156535.17" case 1'1 case end @@ -314944,82 +323582,25 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8546 \muxid$69 + assign $1\rb$next[63:0]$8996 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8546 \muxid$69 + assign $1\rb$next[63:0]$8996 \rb$43 case - assign $1\muxid$next[1:0]$8546 \muxid + assign $1\rb$next[63:0]$8996 \rb end sync always - update \muxid$next $0\muxid$next[1:0]$8545 + update \rb$next $0\rb$next[63:0]$8995 end - attribute \src "libresoc.v:152665.3-152706.6" - process $proc$libresoc.v:152665$8547 - assign { } { } - assign { } { } + attribute \src "libresoc.v:156547.3-156559.6" + process $proc$libresoc.v:156547$8997 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$next[3:0]$8548 $1\alu_op__data_len$next[3:0]$8566 - assign $0\alu_op__fn_unit$next[11:0]$8549 $1\alu_op__fn_unit$next[11:0]$8567 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$next[1:0]$8552 $1\alu_op__input_carry$next[1:0]$8570 - assign $0\alu_op__insn$next[31:0]$8553 $1\alu_op__insn$next[31:0]$8571 - assign $0\alu_op__insn_type$next[6:0]$8554 $1\alu_op__insn_type$next[6:0]$8572 - assign $0\alu_op__invert_in$next[0:0]$8555 $1\alu_op__invert_in$next[0:0]$8573 - assign $0\alu_op__invert_out$next[0:0]$8556 $1\alu_op__invert_out$next[0:0]$8574 - assign $0\alu_op__is_32bit$next[0:0]$8557 $1\alu_op__is_32bit$next[0:0]$8575 - assign $0\alu_op__is_signed$next[0:0]$8558 $1\alu_op__is_signed$next[0:0]$8576 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$next[0:0]$8561 $1\alu_op__output_carry$next[0:0]$8579 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$8564 $1\alu_op__write_cr0$next[0:0]$8582 - assign $0\alu_op__zero_a$next[0:0]$8565 $1\alu_op__zero_a$next[0:0]$8583 - assign $0\alu_op__imm_data__data$next[63:0]$8550 $2\alu_op__imm_data__data$next[63:0]$8584 - assign $0\alu_op__imm_data__ok$next[0:0]$8551 $2\alu_op__imm_data__ok$next[0:0]$8585 - assign $0\alu_op__oe__oe$next[0:0]$8559 $2\alu_op__oe__oe$next[0:0]$8586 - assign $0\alu_op__oe__ok$next[0:0]$8560 $2\alu_op__oe__ok$next[0:0]$8587 - assign $0\alu_op__rc__ok$next[0:0]$8562 $2\alu_op__rc__ok$next[0:0]$8588 - assign $0\alu_op__rc__rc$next[0:0]$8563 $2\alu_op__rc__rc$next[0:0]$8589 - attribute \src "libresoc.v:152666.5-152666.29" + assign $0\fast1$next[63:0]$8998 $1\fast1$next[63:0]$8999 + attribute \src "libresoc.v:156548.5-156548.29" switch \initial - attribute \src "libresoc.v:152666.9-152666.17" + attribute \src "libresoc.v:156548.9-156548.17" case 1'1 case end @@ -315028,121 +323609,25 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8571 $1\alu_op__data_len$next[3:0]$8566 $1\alu_op__is_signed$next[0:0]$8576 $1\alu_op__is_32bit$next[0:0]$8575 $1\alu_op__output_carry$next[0:0]$8579 $1\alu_op__input_carry$next[1:0]$8570 $1\alu_op__write_cr0$next[0:0]$8582 $1\alu_op__invert_out$next[0:0]$8574 $1\alu_op__zero_a$next[0:0]$8583 $1\alu_op__invert_in$next[0:0]$8573 $1\alu_op__oe__ok$next[0:0]$8578 $1\alu_op__oe__oe$next[0:0]$8577 $1\alu_op__rc__ok$next[0:0]$8580 $1\alu_op__rc__rc$next[0:0]$8581 $1\alu_op__imm_data__ok$next[0:0]$8569 $1\alu_op__imm_data__data$next[63:0]$8568 $1\alu_op__fn_unit$next[11:0]$8567 $1\alu_op__insn_type$next[6:0]$8572 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign $1\fast1$next[63:0]$8999 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$8571 $1\alu_op__data_len$next[3:0]$8566 $1\alu_op__is_signed$next[0:0]$8576 $1\alu_op__is_32bit$next[0:0]$8575 $1\alu_op__output_carry$next[0:0]$8579 $1\alu_op__input_carry$next[1:0]$8570 $1\alu_op__write_cr0$next[0:0]$8582 $1\alu_op__invert_out$next[0:0]$8574 $1\alu_op__zero_a$next[0:0]$8583 $1\alu_op__invert_in$next[0:0]$8573 $1\alu_op__oe__ok$next[0:0]$8578 $1\alu_op__oe__oe$next[0:0]$8577 $1\alu_op__rc__ok$next[0:0]$8580 $1\alu_op__rc__rc$next[0:0]$8581 $1\alu_op__imm_data__ok$next[0:0]$8569 $1\alu_op__imm_data__data$next[63:0]$8568 $1\alu_op__fn_unit$next[11:0]$8567 $1\alu_op__insn_type$next[6:0]$8572 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } - case - assign $1\alu_op__data_len$next[3:0]$8566 \alu_op__data_len - assign $1\alu_op__fn_unit$next[11:0]$8567 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$8568 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$8569 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$8570 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$8571 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$8572 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$8573 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$8574 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$8575 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$8576 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$8577 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$8578 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$8579 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$8580 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$8581 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$8582 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$8583 \alu_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$8584 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$8585 1'0 - assign $2\alu_op__rc__rc$next[0:0]$8589 1'0 - assign $2\alu_op__rc__ok$next[0:0]$8588 1'0 - assign $2\alu_op__oe__oe$next[0:0]$8586 1'0 - assign $2\alu_op__oe__ok$next[0:0]$8587 1'0 + assign $1\fast1$next[63:0]$8999 \fast1$44 case - assign $2\alu_op__imm_data__data$next[63:0]$8584 $1\alu_op__imm_data__data$next[63:0]$8568 - assign $2\alu_op__imm_data__ok$next[0:0]$8585 $1\alu_op__imm_data__ok$next[0:0]$8569 - assign $2\alu_op__oe__oe$next[0:0]$8586 $1\alu_op__oe__oe$next[0:0]$8577 - assign $2\alu_op__oe__ok$next[0:0]$8587 $1\alu_op__oe__ok$next[0:0]$8578 - assign $2\alu_op__rc__ok$next[0:0]$8588 $1\alu_op__rc__ok$next[0:0]$8580 - assign $2\alu_op__rc__rc$next[0:0]$8589 $1\alu_op__rc__rc$next[0:0]$8581 + assign $1\fast1$next[63:0]$8999 \fast1 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8548 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8549 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8550 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8551 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8552 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8553 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8554 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8555 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8556 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8557 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8558 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8559 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8560 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8561 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8562 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8563 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8564 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8565 + update \fast1$next $0\fast1$next[63:0]$8998 end - attribute \src "libresoc.v:152707.3-152725.6" - process $proc$libresoc.v:152707$8590 + attribute \src "libresoc.v:156560.3-156572.6" + process $proc$libresoc.v:156560$9000 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8591 $1\o$next[63:0]$8593 - assign { } { } - assign $0\o_ok$next[0:0]$8592 $2\o_ok$next[0:0]$8595 - attribute \src "libresoc.v:152708.5-152708.29" + assign $0\fast2$next[63:0]$9001 $1\fast2$next[63:0]$9002 + attribute \src "libresoc.v:156561.5-156561.29" switch \initial - attribute \src "libresoc.v:152708.9-152708.17" + attribute \src "libresoc.v:156561.9-156561.17" case 1'1 case end @@ -315151,336 +323636,319 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8594 $1\o$next[63:0]$8593 } { \o_ok$89 \o$88 } + assign $1\fast2$next[63:0]$9002 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8594 $1\o$next[63:0]$8593 } { \o_ok$89 \o$88 } - case - assign $1\o$next[63:0]$8593 \o - assign $1\o_ok$next[0:0]$8594 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8595 1'0 + assign $1\fast2$next[63:0]$9002 \fast2$45 case - assign $2\o_ok$next[0:0]$8595 $1\o_ok$next[0:0]$8594 + assign $1\fast2$next[63:0]$9002 \fast2 end sync always - update \o$next $0\o$next[63:0]$8591 - update \o_ok$next $0\o_ok$next[0:0]$8592 + update \fast2$next $0\fast2$next[63:0]$9001 end - connect \$67 $and$libresoc.v:152388$8485_Y - connect \xer_so_ok$98 1'0 + connect \$30 $and$libresoc.v:156400$8949_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } - connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } - connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - connect \muxid$69 \main_muxid$45 - connect \p_valid_i_p_ready_o \$67 + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$66 \p_valid_i - connect \main_xer_ca \input_xer_ca$44 - connect \main_xer_so \input_xer_so$43 - connect \main_rb \input_rb$42 - connect \main_ra \input_ra$41 - connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - connect \main_muxid \input_muxid$22 - connect \input_xer_ca \xer_ca$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:152755.1-154146.10" +attribute \src "libresoc.v:156594.1-157764.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" -module \pipe1$107 - attribute \src "libresoc.v:154060.3-154078.6" - wire width 4 $0\cr_a$next[3:0]$8707 - attribute \src "libresoc.v:153828.3-153829.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:154060.3-154078.6" - wire $0\cr_a_ok$next[0:0]$8708 - attribute \src "libresoc.v:153830.3-153831.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:152756.7-152756.20" +module \pipe2 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9087 + attribute \src "libresoc.v:157505.3-157506.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9073 + attribute \src "libresoc.v:156602.13-156602.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9161 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 12 $0\alu_op__fn_unit$3$next[11:0]$9088 + attribute \src "libresoc.v:157475.3-157476.53" + wire width 12 $0\alu_op__fn_unit$3[11:0]$9043 + attribute \src "libresoc.v:156637.14-156637.43" + wire width 12 $0\alu_op__fn_unit$3[11:0]$9163 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9089 + attribute \src "libresoc.v:157477.3-157478.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9045 + attribute \src "libresoc.v:156659.14-156659.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9165 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9090 + attribute \src "libresoc.v:157479.3-157480.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9047 + attribute \src "libresoc.v:156668.7-156668.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9167 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9091 + attribute \src "libresoc.v:157497.3-157498.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9065 + attribute \src "libresoc.v:156685.13-156685.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9169 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9092 + attribute \src "libresoc.v:157507.3-157508.49" + wire width 32 $0\alu_op__insn$19[31:0]$9075 + attribute \src "libresoc.v:156698.14-156698.39" + wire width 32 $0\alu_op__insn$19[31:0]$9171 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9093 + attribute \src "libresoc.v:157473.3-157474.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9041 + attribute \src "libresoc.v:156855.13-156855.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9173 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__invert_in$10$next[0:0]$9094 + attribute \src "libresoc.v:157489.3-157490.59" + wire $0\alu_op__invert_in$10[0:0]$9057 + attribute \src "libresoc.v:156938.7-156938.36" + wire $0\alu_op__invert_in$10[0:0]$9175 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__invert_out$12$next[0:0]$9095 + attribute \src "libresoc.v:157493.3-157494.61" + wire $0\alu_op__invert_out$12[0:0]$9061 + attribute \src "libresoc.v:156947.7-156947.37" + wire $0\alu_op__invert_out$12[0:0]$9177 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9096 + attribute \src "libresoc.v:157501.3-157502.57" + wire $0\alu_op__is_32bit$16[0:0]$9069 + attribute \src "libresoc.v:156956.7-156956.35" + wire $0\alu_op__is_32bit$16[0:0]$9179 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__is_signed$17$next[0:0]$9097 + attribute \src "libresoc.v:157503.3-157504.59" + wire $0\alu_op__is_signed$17[0:0]$9071 + attribute \src "libresoc.v:156965.7-156965.36" + wire $0\alu_op__is_signed$17[0:0]$9181 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9098 + attribute \src "libresoc.v:157485.3-157486.51" + wire $0\alu_op__oe__oe$8[0:0]$9053 + attribute \src "libresoc.v:156976.7-156976.32" + wire $0\alu_op__oe__oe$8[0:0]$9183 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9099 + attribute \src "libresoc.v:157487.3-157488.51" + wire $0\alu_op__oe__ok$9[0:0]$9055 + attribute \src "libresoc.v:156985.7-156985.32" + wire $0\alu_op__oe__ok$9[0:0]$9185 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__output_carry$15$next[0:0]$9100 + attribute \src "libresoc.v:157499.3-157500.65" + wire $0\alu_op__output_carry$15[0:0]$9067 + attribute \src "libresoc.v:156992.7-156992.39" + wire $0\alu_op__output_carry$15[0:0]$9187 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9101 + attribute \src "libresoc.v:157483.3-157484.51" + wire $0\alu_op__rc__ok$7[0:0]$9051 + attribute \src "libresoc.v:157003.7-157003.32" + wire $0\alu_op__rc__ok$7[0:0]$9189 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9102 + attribute \src "libresoc.v:157481.3-157482.51" + wire $0\alu_op__rc__rc$6[0:0]$9049 + attribute \src "libresoc.v:157010.7-157010.32" + wire $0\alu_op__rc__rc$6[0:0]$9191 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9103 + attribute \src "libresoc.v:157495.3-157496.59" + wire $0\alu_op__write_cr0$13[0:0]$9063 + attribute \src "libresoc.v:157019.7-157019.36" + wire $0\alu_op__write_cr0$13[0:0]$9193 + attribute \src "libresoc.v:157608.3-157649.6" + wire $0\alu_op__zero_a$11$next[0:0]$9104 + attribute \src "libresoc.v:157491.3-157492.53" + wire $0\alu_op__zero_a$11[0:0]$9059 + attribute \src "libresoc.v:157028.7-157028.33" + wire $0\alu_op__zero_a$11[0:0]$9195 + attribute \src "libresoc.v:157669.3-157687.6" + wire width 4 $0\cr_a$22$next[3:0]$9136 + attribute \src "libresoc.v:157465.3-157466.33" + wire width 4 $0\cr_a$22[3:0]$9033 + attribute \src "libresoc.v:157041.13-157041.29" + wire width 4 $0\cr_a$22[3:0]$9197 + attribute \src "libresoc.v:157669.3-157687.6" + wire $0\cr_a_ok$23$next[0:0]$9137 + attribute \src "libresoc.v:157467.3-157468.39" + wire $0\cr_a_ok$23[0:0]$9035 + attribute \src "libresoc.v:157050.7-157050.26" + wire $0\cr_a_ok$23[0:0]$9199 + attribute \src "libresoc.v:156595.7-156595.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153988.3-154000.6" - wire width 2 $0\muxid$next[1:0]$8659 - attribute \src "libresoc.v:153868.3-153869.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154041.3-154059.6" - wire width 64 $0\o$next[63:0]$8701 - attribute \src "libresoc.v:153832.3-153833.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:154041.3-154059.6" - wire $0\o_ok$next[0:0]$8702 - attribute \src "libresoc.v:153834.3-153835.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:153970.3-153987.6" - wire $0\r_busy$next[0:0]$8655 - attribute \src "libresoc.v:153870.3-153871.29" + attribute \src "libresoc.v:157595.3-157607.6" + wire width 2 $0\muxid$1$next[1:0]$9084 + attribute \src "libresoc.v:157509.3-157510.33" + wire width 2 $0\muxid$1[1:0]$9077 + attribute \src "libresoc.v:157061.13-157061.29" + wire width 2 $0\muxid$1[1:0]$9201 + attribute \src "libresoc.v:157650.3-157668.6" + wire width 64 $0\o$20$next[63:0]$9130 + attribute \src "libresoc.v:157469.3-157470.27" + wire width 64 $0\o$20[63:0]$9037 + attribute \src "libresoc.v:157076.14-157076.43" + wire width 64 $0\o$20[63:0]$9203 + attribute \src "libresoc.v:157650.3-157668.6" + wire $0\o_ok$21$next[0:0]$9131 + attribute \src "libresoc.v:157471.3-157472.33" + wire $0\o_ok$21[0:0]$9039 + attribute \src "libresoc.v:157085.7-157085.23" + wire $0\o_ok$21[0:0]$9205 + attribute \src "libresoc.v:157577.3-157594.6" + wire $0\r_busy$next[0:0]$9080 + attribute \src "libresoc.v:157511.3-157512.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 12 $0\sr_op__fn_unit$next[11:0]$8662 - attribute \src "libresoc.v:153838.3-153839.45" - wire width 12 $0\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$8663 - attribute \src "libresoc.v:153840.3-153841.59" - wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__imm_data__ok$next[0:0]$8664 - attribute \src "libresoc.v:153842.3-153843.55" - wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$8665 - attribute \src "libresoc.v:153854.3-153855.53" - wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__input_cr$next[0:0]$8666 - attribute \src "libresoc.v:153858.3-153859.47" - wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 32 $0\sr_op__insn$next[31:0]$8667 - attribute \src "libresoc.v:153866.3-153867.39" - wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$8668 - attribute \src "libresoc.v:153836.3-153837.49" - wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__is_32bit$next[0:0]$8669 - attribute \src "libresoc.v:153862.3-153863.47" - wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__is_signed$next[0:0]$8670 - attribute \src "libresoc.v:153864.3-153865.49" - wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__oe__oe$next[0:0]$8671 - attribute \src "libresoc.v:153848.3-153849.43" - wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__oe__ok$next[0:0]$8672 - attribute \src "libresoc.v:153850.3-153851.43" - wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__output_carry$next[0:0]$8673 - attribute \src "libresoc.v:153856.3-153857.55" - wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__output_cr$next[0:0]$8674 - attribute \src "libresoc.v:153860.3-153861.49" - wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__rc__ok$next[0:0]$8675 - attribute \src "libresoc.v:153846.3-153847.43" - wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__rc__rc$next[0:0]$8676 - attribute \src "libresoc.v:153844.3-153845.43" - wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $0\sr_op__write_cr0$next[0:0]$8677 - attribute \src "libresoc.v:153852.3-153853.49" - wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:154098.3-154116.6" - wire width 2 $0\xer_ca$next[1:0]$8720 - attribute \src "libresoc.v:153820.3-153821.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:154098.3-154116.6" - wire $0\xer_ca_ok$next[0:0]$8719 - attribute \src "libresoc.v:153822.3-153823.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:154079.3-154097.6" - wire $0\xer_so$next[0:0]$8713 - attribute \src "libresoc.v:153824.3-153825.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:154079.3-154097.6" - wire $0\xer_so_ok$next[0:0]$8714 - attribute \src "libresoc.v:153826.3-153827.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:154060.3-154078.6" - wire width 4 $1\cr_a$next[3:0]$8709 - attribute \src "libresoc.v:152765.13-152765.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:154060.3-154078.6" - wire $1\cr_a_ok$next[0:0]$8710 - attribute \src "libresoc.v:152774.7-152774.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:153988.3-154000.6" - wire width 2 $1\muxid$next[1:0]$8660 - attribute \src "libresoc.v:153319.13-153319.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:154041.3-154059.6" - wire width 64 $1\o$next[63:0]$8703 - attribute \src "libresoc.v:153334.14-153334.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:154041.3-154059.6" - wire $1\o_ok$next[0:0]$8704 - attribute \src "libresoc.v:153341.7-153341.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:153970.3-153987.6" - wire $1\r_busy$next[0:0]$8656 - attribute \src "libresoc.v:153355.7-153355.20" + attribute \src "libresoc.v:157688.3-157706.6" + wire width 2 $0\xer_ca$24$next[1:0]$9142 + attribute \src "libresoc.v:157461.3-157462.37" + wire width 2 $0\xer_ca$24[1:0]$9029 + attribute \src "libresoc.v:157396.13-157396.31" + wire width 2 $0\xer_ca$24[1:0]$9208 + attribute \src "libresoc.v:157688.3-157706.6" + wire $0\xer_ca_ok$25$next[0:0]$9143 + attribute \src "libresoc.v:157463.3-157464.43" + wire $0\xer_ca_ok$25[0:0]$9031 + attribute \src "libresoc.v:157405.7-157405.28" + wire $0\xer_ca_ok$25[0:0]$9210 + attribute \src "libresoc.v:157707.3-157725.6" + wire width 2 $0\xer_ov$26$next[1:0]$9148 + attribute \src "libresoc.v:157457.3-157458.37" + wire width 2 $0\xer_ov$26[1:0]$9025 + attribute \src "libresoc.v:157416.13-157416.31" + wire width 2 $0\xer_ov$26[1:0]$9212 + attribute \src "libresoc.v:157707.3-157725.6" + wire $0\xer_ov_ok$27$next[0:0]$9149 + attribute \src "libresoc.v:157459.3-157460.43" + wire $0\xer_ov_ok$27[0:0]$9027 + attribute \src "libresoc.v:157425.7-157425.28" + wire $0\xer_ov_ok$27[0:0]$9214 + attribute \src "libresoc.v:157726.3-157744.6" + wire $0\xer_so$28$next[0:0]$9154 + attribute \src "libresoc.v:157453.3-157454.37" + wire $0\xer_so$28[0:0]$9021 + attribute \src "libresoc.v:157436.7-157436.25" + wire $0\xer_so$28[0:0]$9216 + attribute \src "libresoc.v:157726.3-157744.6" + wire $0\xer_so_ok$29$next[0:0]$9155 + attribute \src "libresoc.v:157455.3-157456.43" + wire $0\xer_so_ok$29[0:0]$9023 + attribute \src "libresoc.v:157445.7-157445.28" + wire $0\xer_so_ok$29[0:0]$9218 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9105 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 12 $1\alu_op__fn_unit$3$next[11:0]$9106 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9107 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9108 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9109 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9110 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9111 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__invert_in$10$next[0:0]$9112 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__invert_out$12$next[0:0]$9113 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9114 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__is_signed$17$next[0:0]$9115 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9116 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9117 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__output_carry$15$next[0:0]$9118 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9119 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9120 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9121 + attribute \src "libresoc.v:157608.3-157649.6" + wire $1\alu_op__zero_a$11$next[0:0]$9122 + attribute \src "libresoc.v:157669.3-157687.6" + wire width 4 $1\cr_a$22$next[3:0]$9138 + attribute \src "libresoc.v:157669.3-157687.6" + wire $1\cr_a_ok$23$next[0:0]$9139 + attribute \src "libresoc.v:157595.3-157607.6" + wire width 2 $1\muxid$1$next[1:0]$9085 + attribute \src "libresoc.v:157650.3-157668.6" + wire width 64 $1\o$20$next[63:0]$9132 + attribute \src "libresoc.v:157650.3-157668.6" + wire $1\o_ok$21$next[0:0]$9133 + attribute \src "libresoc.v:157577.3-157594.6" + wire $1\r_busy$next[0:0]$9081 + attribute \src "libresoc.v:157389.7-157389.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 12 $1\sr_op__fn_unit$next[11:0]$8678 - attribute \src "libresoc.v:153379.14-153379.38" - wire width 12 $1\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$8679 - attribute \src "libresoc.v:153414.14-153414.58" - wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__imm_data__ok$next[0:0]$8680 - attribute \src "libresoc.v:153423.7-153423.33" - wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$8681 - attribute \src "libresoc.v:153436.13-153436.38" - wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__input_cr$next[0:0]$8682 - attribute \src "libresoc.v:153453.7-153453.29" - wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 32 $1\sr_op__insn$next[31:0]$8683 - attribute \src "libresoc.v:153462.14-153462.33" - wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$8684 - attribute \src "libresoc.v:153545.13-153545.37" - wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__is_32bit$next[0:0]$8685 - attribute \src "libresoc.v:153702.7-153702.29" - wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__is_signed$next[0:0]$8686 - attribute \src "libresoc.v:153711.7-153711.30" - wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__oe__oe$next[0:0]$8687 - attribute \src "libresoc.v:153720.7-153720.27" - wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__oe__ok$next[0:0]$8688 - attribute \src "libresoc.v:153729.7-153729.27" - wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__output_carry$next[0:0]$8689 - attribute \src "libresoc.v:153738.7-153738.33" - wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__output_cr$next[0:0]$8690 - attribute \src "libresoc.v:153747.7-153747.30" - wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__rc__ok$next[0:0]$8691 - attribute \src "libresoc.v:153756.7-153756.27" - wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__rc__rc$next[0:0]$8692 - attribute \src "libresoc.v:153765.7-153765.27" - wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:154001.3-154040.6" - wire $1\sr_op__write_cr0$next[0:0]$8693 - attribute \src "libresoc.v:153774.7-153774.30" - wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:154098.3-154116.6" - wire width 2 $1\xer_ca$next[1:0]$8722 - attribute \src "libresoc.v:153783.13-153783.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:154098.3-154116.6" - wire $1\xer_ca_ok$next[0:0]$8721 - attribute \src "libresoc.v:153794.7-153794.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:154079.3-154097.6" - wire $1\xer_so$next[0:0]$8715 - attribute \src "libresoc.v:153803.7-153803.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:154079.3-154097.6" - wire $1\xer_so_ok$next[0:0]$8716 - attribute \src "libresoc.v:153812.7-153812.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:154060.3-154078.6" - wire $2\cr_a_ok$next[0:0]$8711 - attribute \src "libresoc.v:154041.3-154059.6" - wire $2\o_ok$next[0:0]$8705 - attribute \src "libresoc.v:153970.3-153987.6" - wire $2\r_busy$next[0:0]$8657 - attribute \src "libresoc.v:154001.3-154040.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$8694 - attribute \src "libresoc.v:154001.3-154040.6" - wire $2\sr_op__imm_data__ok$next[0:0]$8695 - attribute \src "libresoc.v:154001.3-154040.6" - wire $2\sr_op__oe__oe$next[0:0]$8696 - attribute \src "libresoc.v:154001.3-154040.6" - wire $2\sr_op__oe__ok$next[0:0]$8697 - attribute \src "libresoc.v:154001.3-154040.6" - wire $2\sr_op__rc__ok$next[0:0]$8698 - attribute \src "libresoc.v:154001.3-154040.6" - wire $2\sr_op__rc__rc$next[0:0]$8699 - attribute \src "libresoc.v:154098.3-154116.6" - wire $2\xer_ca_ok$next[0:0]$8723 - attribute \src "libresoc.v:154079.3-154097.6" - wire $2\xer_so_ok$next[0:0]$8717 - attribute \src "libresoc.v:153819.18-153819.118" - wire $and$libresoc.v:153819$8627_Y + attribute \src "libresoc.v:157688.3-157706.6" + wire width 2 $1\xer_ca$24$next[1:0]$9144 + attribute \src "libresoc.v:157688.3-157706.6" + wire $1\xer_ca_ok$25$next[0:0]$9145 + attribute \src "libresoc.v:157707.3-157725.6" + wire width 2 $1\xer_ov$26$next[1:0]$9150 + attribute \src "libresoc.v:157707.3-157725.6" + wire $1\xer_ov_ok$27$next[0:0]$9151 + attribute \src "libresoc.v:157726.3-157744.6" + wire $1\xer_so$28$next[0:0]$9156 + attribute \src "libresoc.v:157726.3-157744.6" + wire $1\xer_so_ok$29$next[0:0]$9157 + attribute \src "libresoc.v:157608.3-157649.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9123 + attribute \src "libresoc.v:157608.3-157649.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9124 + attribute \src "libresoc.v:157608.3-157649.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9125 + attribute \src "libresoc.v:157608.3-157649.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9126 + attribute \src "libresoc.v:157608.3-157649.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9127 + attribute \src "libresoc.v:157608.3-157649.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9128 + attribute \src "libresoc.v:157669.3-157687.6" + wire $2\cr_a_ok$23$next[0:0]$9140 + attribute \src "libresoc.v:157650.3-157668.6" + wire $2\o_ok$21$next[0:0]$9134 + attribute \src "libresoc.v:157577.3-157594.6" + wire $2\r_busy$next[0:0]$9082 + attribute \src "libresoc.v:157688.3-157706.6" + wire $2\xer_ca_ok$25$next[0:0]$9146 + attribute \src "libresoc.v:157707.3-157725.6" + wire $2\xer_ov_ok$27$next[0:0]$9152 + attribute \src "libresoc.v:157726.3-157744.6" + wire $2\xer_so_ok$29$next[0:0]$9158 + attribute \src "libresoc.v:157452.18-157452.118" + wire $and$libresoc.v:157452$9019_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 23 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$next - attribute \src "libresoc.v:152756.7-152756.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$39 + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -315495,7 +323963,7 @@ module \pipe1$107 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_sr_op__fn_unit + wire width 12 input 6 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -315510,35 +323978,68 @@ module \pipe1$107 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_sr_op__fn_unit$22 + wire width 12 output 37 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data + wire width 12 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data$23 + wire width 12 \alu_op__fn_unit$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok$24 + wire \alu_op__imm_data__ok$66 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry + wire width 2 input 17 \alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$30 + wire width 2 output 48 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr$32 + wire width 2 \alu_op__input_carry$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn$36 + wire width 32 \alu_op__insn$80 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -315614,7 +324115,7 @@ module \pipe1$107 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type + wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -315690,123 +324191,9 @@ module \pipe1$107 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_sr_op__fn_unit$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok$46 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn + wire width 7 output 36 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn$58 + wire width 7 \alu_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -315882,184 +324269,153 @@ module \pipe1$107 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 7 \alu_op__insn_type$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type$43 + wire input 13 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit + wire output 44 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit$56 + wire \alu_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed + wire \alu_op__invert_in$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed$57 + wire input 15 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe + wire output 46 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe$49 + wire \alu_op__invert_out$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok + wire \alu_op__invert_out$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok$50 + wire input 19 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry + wire output 50 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry$53 + wire \alu_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr + wire \alu_op__is_32bit$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr$55 + wire input 20 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok + wire output 51 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok$48 + wire \alu_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc + wire \alu_op__is_signed$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc$47 + wire input 11 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0 + wire \alu_op__oe__oe$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \main_xer_so$59 + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:156595.7-156595.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid + wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 31 \muxid$1 + wire width 2 output 35 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$64 + wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next + wire width 2 \muxid$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i + wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 48 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 49 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \sr_op__fn_unit + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -316074,7 +324430,7 @@ module \pipe1$107 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 33 \sr_op__fn_unit$3 + wire width 12 \output_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -316089,137 +324445,31 @@ module \pipe1$107 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 34 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \sr_op__imm_data__ok + wire width 12 \output_alu_op__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 35 \sr_op__imm_data__ok$5 + wire width 64 \output_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$68 + wire width 64 \output_alu_op__imm_data__data$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \output_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \sr_op__input_carry + wire \output_alu_op__imm_data__ok$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 41 \sr_op__input_carry$11 + wire width 2 \output_alu_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 47 \sr_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$80 + wire width 2 \output_alu_op__input_carry$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 \output_alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \sr_op__insn_type + wire width 32 \output_alu_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -316295,7 +324545,7 @@ module \pipe1$107 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 32 \sr_op__insn_type$2 + wire width 7 \output_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -316367,643 +324617,705 @@ module \pipe1$107 attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \sr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \sr_op__oe__ok + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$72 + wire width 7 \output_alu_op__insn_type$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \sr_op__oe__ok$9 + wire \output_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$next + wire \output_alu_op__invert_in$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \sr_op__output_carry + wire \output_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \sr_op__output_carry$12 + wire \output_alu_op__invert_out$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$75 + wire \output_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$next + wire \output_alu_op__is_32bit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \sr_op__output_cr + wire \output_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \sr_op__output_cr$14 + wire \output_alu_op__is_signed$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$77 + wire \output_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$next + wire \output_alu_op__oe__oe$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \sr_op__rc__ok + wire \output_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \sr_op__rc__ok$7 + wire \output_alu_op__oe__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$70 + wire \output_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$next + wire \output_alu_op__output_carry$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \sr_op__rc__rc + wire \output_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \sr_op__rc__rc$6 + wire \output_alu_op__rc__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$69 + wire \output_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$next + wire \output_alu_op__rc__rc$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \sr_op__write_cr0 + wire \output_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \sr_op__write_cr0$10 + wire \output_alu_op__write_cr0$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$73 + wire \output_alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 52 \xer_ca$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 51 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$next + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:153819$8627 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\main_sr_op__imm_data__data$45 - connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$46 - connect \sr_op__input_carry \main_sr_op__input_carry - connect \sr_op__input_carry$11 \main_sr_op__input_carry$52 - connect \sr_op__input_cr \main_sr_op__input_cr - connect \sr_op__input_cr$13 \main_sr_op__input_cr$54 - connect \sr_op__insn \main_sr_op__insn - connect \sr_op__insn$17 \main_sr_op__insn$58 - connect \sr_op__insn_type \main_sr_op__insn_type - connect \sr_op__insn_type$2 \main_sr_op__insn_type$43 - connect \sr_op__is_32bit \main_sr_op__is_32bit - connect \sr_op__is_32bit$15 \main_sr_op__is_32bit$56 - connect \sr_op__is_signed \main_sr_op__is_signed - connect \sr_op__is_signed$16 \main_sr_op__is_signed$57 - connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$49 - connect \sr_op__oe__ok \main_sr_op__oe__ok - connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$50 - connect \sr_op__output_carry \main_sr_op__output_carry - connect \sr_op__output_carry$12 \main_sr_op__output_carry$53 - connect \sr_op__output_cr \main_sr_op__output_cr - connect \sr_op__output_cr$14 \main_sr_op__output_cr$55 - connect \sr_op__rc__ok \main_sr_op__rc__ok - connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$48 - connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$47 - connect \sr_op__write_cr0 \main_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$51 - connect \xer_ca \main_xer_ca - connect \xer_so \main_xer_so - connect \xer_so$18 \main_xer_so$59 + connect \Y $and$libresoc.v:157452$9019_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:153962.11-153965.4" - cell \n$109 \n + attribute \src "libresoc.v:157513.9-157516.4" + cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:153966.11-153969.4" - cell \p$108 \p + attribute \src "libresoc.v:157517.12-157572.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157573.9-157576.4" + cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:152756.7-152756.20" - process $proc$libresoc.v:152756$8724 + attribute \src "libresoc.v:156595.7-156595.20" + process $proc$libresoc.v:156595$9159 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:152765.13-152765.24" - process $proc$libresoc.v:152765$8725 + attribute \src "libresoc.v:156602.13-156602.41" + process $proc$libresoc.v:156602$9160 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $0\alu_op__data_len$18[3:0]$9161 4'0000 sync always sync init - update \cr_a $1\cr_a[3:0] + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9161 end - attribute \src "libresoc.v:152774.7-152774.21" - process $proc$libresoc.v:152774$8726 + attribute \src "libresoc.v:156637.14-156637.43" + process $proc$libresoc.v:156637$9162 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $0\alu_op__fn_unit$3[11:0]$9163 12'000000000000 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9163 end - attribute \src "libresoc.v:153319.13-153319.25" - process $proc$libresoc.v:153319$8727 + attribute \src "libresoc.v:156659.14-156659.63" + process $proc$libresoc.v:156659$9164 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $0\alu_op__imm_data__data$4[63:0]$9165 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid $1\muxid[1:0] + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9165 end - attribute \src "libresoc.v:153334.14-153334.38" - process $proc$libresoc.v:153334$8728 + attribute \src "libresoc.v:156668.7-156668.38" + process $proc$libresoc.v:156668$9166 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__ok$5[0:0]$9167 1'0 sync always sync init - update \o $1\o[63:0] + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9167 end - attribute \src "libresoc.v:153341.7-153341.18" - process $proc$libresoc.v:153341$8729 + attribute \src "libresoc.v:156685.13-156685.44" + process $proc$libresoc.v:156685$9168 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\alu_op__input_carry$14[1:0]$9169 2'00 sync always sync init - update \o_ok $1\o_ok[0:0] + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9169 end - attribute \src "libresoc.v:153355.7-153355.20" - process $proc$libresoc.v:153355$8730 + attribute \src "libresoc.v:156698.14-156698.39" + process $proc$libresoc.v:156698$9170 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\alu_op__insn$19[31:0]$9171 0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9171 end - attribute \src "libresoc.v:153379.14-153379.38" - process $proc$libresoc.v:153379$8731 + attribute \src "libresoc.v:156855.13-156855.42" + process $proc$libresoc.v:156855$9172 assign { } { } - assign $1\sr_op__fn_unit[11:0] 12'000000000000 + assign $0\alu_op__insn_type$2[6:0]$9173 7'0000000 sync always sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9173 end - attribute \src "libresoc.v:153414.14-153414.58" - process $proc$libresoc.v:153414$8732 + attribute \src "libresoc.v:156938.7-156938.36" + process $proc$libresoc.v:156938$9174 assign { } { } - assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__invert_in$10[0:0]$9175 1'0 sync always sync init - update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9175 end - attribute \src "libresoc.v:153423.7-153423.33" - process $proc$libresoc.v:153423$8733 + attribute \src "libresoc.v:156947.7-156947.37" + process $proc$libresoc.v:156947$9176 assign { } { } - assign $1\sr_op__imm_data__ok[0:0] 1'0 + assign $0\alu_op__invert_out$12[0:0]$9177 1'0 sync always sync init - update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9177 end - attribute \src "libresoc.v:153436.13-153436.38" - process $proc$libresoc.v:153436$8734 + attribute \src "libresoc.v:156956.7-156956.35" + process $proc$libresoc.v:156956$9178 assign { } { } - assign $1\sr_op__input_carry[1:0] 2'00 + assign $0\alu_op__is_32bit$16[0:0]$9179 1'0 sync always sync init - update \sr_op__input_carry $1\sr_op__input_carry[1:0] + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9179 end - attribute \src "libresoc.v:153453.7-153453.29" - process $proc$libresoc.v:153453$8735 + attribute \src "libresoc.v:156965.7-156965.36" + process $proc$libresoc.v:156965$9180 assign { } { } - assign $1\sr_op__input_cr[0:0] 1'0 + assign $0\alu_op__is_signed$17[0:0]$9181 1'0 sync always sync init - update \sr_op__input_cr $1\sr_op__input_cr[0:0] + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9181 end - attribute \src "libresoc.v:153462.14-153462.33" - process $proc$libresoc.v:153462$8736 + attribute \src "libresoc.v:156976.7-156976.32" + process $proc$libresoc.v:156976$9182 assign { } { } - assign $1\sr_op__insn[31:0] 0 + assign $0\alu_op__oe__oe$8[0:0]$9183 1'0 sync always sync init - update \sr_op__insn $1\sr_op__insn[31:0] + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9183 end - attribute \src "libresoc.v:153545.13-153545.37" - process $proc$libresoc.v:153545$8737 + attribute \src "libresoc.v:156985.7-156985.32" + process $proc$libresoc.v:156985$9184 assign { } { } - assign $1\sr_op__insn_type[6:0] 7'0000000 + assign $0\alu_op__oe__ok$9[0:0]$9185 1'0 sync always sync init - update \sr_op__insn_type $1\sr_op__insn_type[6:0] + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9185 end - attribute \src "libresoc.v:153702.7-153702.29" - process $proc$libresoc.v:153702$8738 + attribute \src "libresoc.v:156992.7-156992.39" + process $proc$libresoc.v:156992$9186 assign { } { } - assign $1\sr_op__is_32bit[0:0] 1'0 + assign $0\alu_op__output_carry$15[0:0]$9187 1'0 sync always sync init - update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9187 end - attribute \src "libresoc.v:153711.7-153711.30" - process $proc$libresoc.v:153711$8739 + attribute \src "libresoc.v:157003.7-157003.32" + process $proc$libresoc.v:157003$9188 assign { } { } - assign $1\sr_op__is_signed[0:0] 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9189 1'0 sync always sync init - update \sr_op__is_signed $1\sr_op__is_signed[0:0] + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9189 end - attribute \src "libresoc.v:153720.7-153720.27" - process $proc$libresoc.v:153720$8740 + attribute \src "libresoc.v:157010.7-157010.32" + process $proc$libresoc.v:157010$9190 assign { } { } - assign $1\sr_op__oe__oe[0:0] 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9191 1'0 sync always sync init - update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9191 end - attribute \src "libresoc.v:153729.7-153729.27" - process $proc$libresoc.v:153729$8741 + attribute \src "libresoc.v:157019.7-157019.36" + process $proc$libresoc.v:157019$9192 assign { } { } - assign $1\sr_op__oe__ok[0:0] 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9193 1'0 sync always sync init - update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9193 end - attribute \src "libresoc.v:153738.7-153738.33" - process $proc$libresoc.v:153738$8742 + attribute \src "libresoc.v:157028.7-157028.33" + process $proc$libresoc.v:157028$9194 assign { } { } - assign $1\sr_op__output_carry[0:0] 1'0 + assign $0\alu_op__zero_a$11[0:0]$9195 1'0 sync always sync init - update \sr_op__output_carry $1\sr_op__output_carry[0:0] + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9195 end - attribute \src "libresoc.v:153747.7-153747.30" - process $proc$libresoc.v:153747$8743 + attribute \src "libresoc.v:157041.13-157041.29" + process $proc$libresoc.v:157041$9196 assign { } { } - assign $1\sr_op__output_cr[0:0] 1'0 + assign $0\cr_a$22[3:0]$9197 4'0000 sync always sync init - update \sr_op__output_cr $1\sr_op__output_cr[0:0] + update \cr_a$22 $0\cr_a$22[3:0]$9197 end - attribute \src "libresoc.v:153756.7-153756.27" - process $proc$libresoc.v:153756$8744 + attribute \src "libresoc.v:157050.7-157050.26" + process $proc$libresoc.v:157050$9198 assign { } { } - assign $1\sr_op__rc__ok[0:0] 1'0 + assign $0\cr_a_ok$23[0:0]$9199 1'0 sync always sync init - update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9199 end - attribute \src "libresoc.v:153765.7-153765.27" - process $proc$libresoc.v:153765$8745 + attribute \src "libresoc.v:157061.13-157061.29" + process $proc$libresoc.v:157061$9200 assign { } { } - assign $1\sr_op__rc__rc[0:0] 1'0 + assign $0\muxid$1[1:0]$9201 2'00 sync always sync init - update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + update \muxid$1 $0\muxid$1[1:0]$9201 end - attribute \src "libresoc.v:153774.7-153774.30" - process $proc$libresoc.v:153774$8746 + attribute \src "libresoc.v:157076.14-157076.43" + process $proc$libresoc.v:157076$9202 assign { } { } - assign $1\sr_op__write_cr0[0:0] 1'0 + assign $0\o$20[63:0]$9203 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + update \o$20 $0\o$20[63:0]$9203 end - attribute \src "libresoc.v:153783.13-153783.26" - process $proc$libresoc.v:153783$8747 + attribute \src "libresoc.v:157085.7-157085.23" + process $proc$libresoc.v:157085$9204 assign { } { } - assign $1\xer_ca[1:0] 2'00 + assign $0\o_ok$21[0:0]$9205 1'0 sync always sync init - update \xer_ca $1\xer_ca[1:0] + update \o_ok$21 $0\o_ok$21[0:0]$9205 end - attribute \src "libresoc.v:153794.7-153794.23" - process $proc$libresoc.v:153794$8748 + attribute \src "libresoc.v:157389.7-157389.20" + process $proc$libresoc.v:157389$9206 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:153803.7-153803.20" - process $proc$libresoc.v:153803$8749 + attribute \src "libresoc.v:157396.13-157396.31" + process $proc$libresoc.v:157396$9207 assign { } { } - assign $1\xer_so[0:0] 1'0 + assign $0\xer_ca$24[1:0]$9208 2'00 sync always sync init - update \xer_so $1\xer_so[0:0] + update \xer_ca$24 $0\xer_ca$24[1:0]$9208 end - attribute \src "libresoc.v:153812.7-153812.23" - process $proc$libresoc.v:153812$8750 + attribute \src "libresoc.v:157405.7-157405.28" + process $proc$libresoc.v:157405$9209 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $0\xer_ca_ok$25[0:0]$9210 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9210 end - attribute \src "libresoc.v:153820.3-153821.29" - process $proc$libresoc.v:153820$8628 + attribute \src "libresoc.v:157416.13-157416.31" + process $proc$libresoc.v:157416$9211 assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next + assign $0\xer_ov$26[1:0]$9212 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9212 + end + attribute \src "libresoc.v:157425.7-157425.28" + process $proc$libresoc.v:157425$9213 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9214 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9214 + end + attribute \src "libresoc.v:157436.7-157436.25" + process $proc$libresoc.v:157436$9215 + assign { } { } + assign $0\xer_so$28[0:0]$9216 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9216 + end + attribute \src "libresoc.v:157445.7-157445.28" + process $proc$libresoc.v:157445$9217 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9218 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9218 + end + attribute \src "libresoc.v:157453.3-157454.37" + process $proc$libresoc.v:157453$9020 + assign { } { } + assign $0\xer_so$28[0:0]$9021 \xer_so$28$next sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] + update \xer_so$28 $0\xer_so$28[0:0]$9021 end - attribute \src "libresoc.v:153822.3-153823.35" - process $proc$libresoc.v:153822$8629 + attribute \src "libresoc.v:157455.3-157456.43" + process $proc$libresoc.v:157455$9022 assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + assign $0\xer_so_ok$29[0:0]$9023 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9023 end - attribute \src "libresoc.v:153824.3-153825.29" - process $proc$libresoc.v:153824$8630 + attribute \src "libresoc.v:157457.3-157458.37" + process $proc$libresoc.v:157457$9024 assign { } { } - assign $0\xer_so[0:0] \xer_so$next + assign $0\xer_ov$26[1:0]$9025 \xer_ov$26$next sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] + update \xer_ov$26 $0\xer_ov$26[1:0]$9025 end - attribute \src "libresoc.v:153826.3-153827.35" - process $proc$libresoc.v:153826$8631 + attribute \src "libresoc.v:157459.3-157460.43" + process $proc$libresoc.v:157459$9026 assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next + assign $0\xer_ov_ok$27[0:0]$9027 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9027 end - attribute \src "libresoc.v:153828.3-153829.25" - process $proc$libresoc.v:153828$8632 + attribute \src "libresoc.v:157461.3-157462.37" + process $proc$libresoc.v:157461$9028 assign { } { } - assign $0\cr_a[3:0] \cr_a$next + assign $0\xer_ca$24[1:0]$9029 \xer_ca$24$next sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + update \xer_ca$24 $0\xer_ca$24[1:0]$9029 end - attribute \src "libresoc.v:153830.3-153831.31" - process $proc$libresoc.v:153830$8633 + attribute \src "libresoc.v:157463.3-157464.43" + process $proc$libresoc.v:157463$9030 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next + assign $0\xer_ca_ok$25[0:0]$9031 \xer_ca_ok$25$next sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9031 end - attribute \src "libresoc.v:153832.3-153833.19" - process $proc$libresoc.v:153832$8634 + attribute \src "libresoc.v:157465.3-157466.33" + process $proc$libresoc.v:157465$9032 assign { } { } - assign $0\o[63:0] \o$next + assign $0\cr_a$22[3:0]$9033 \cr_a$22$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \cr_a$22 $0\cr_a$22[3:0]$9033 end - attribute \src "libresoc.v:153834.3-153835.25" - process $proc$libresoc.v:153834$8635 + attribute \src "libresoc.v:157467.3-157468.39" + process $proc$libresoc.v:157467$9034 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\cr_a_ok$23[0:0]$9035 \cr_a_ok$23$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9035 end - attribute \src "libresoc.v:153836.3-153837.49" - process $proc$libresoc.v:153836$8636 + attribute \src "libresoc.v:157469.3-157470.27" + process $proc$libresoc.v:157469$9036 assign { } { } - assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + assign $0\o$20[63:0]$9037 \o$20$next sync posedge \coresync_clk - update \sr_op__insn_type $0\sr_op__insn_type[6:0] + update \o$20 $0\o$20[63:0]$9037 end - attribute \src "libresoc.v:153838.3-153839.45" - process $proc$libresoc.v:153838$8637 + attribute \src "libresoc.v:157471.3-157472.33" + process $proc$libresoc.v:157471$9038 assign { } { } - assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next + assign $0\o_ok$21[0:0]$9039 \o_ok$21$next sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] + update \o_ok$21 $0\o_ok$21[0:0]$9039 end - attribute \src "libresoc.v:153840.3-153841.59" - process $proc$libresoc.v:153840$8638 + attribute \src "libresoc.v:157473.3-157474.57" + process $proc$libresoc.v:157473$9040 assign { } { } - assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + assign $0\alu_op__insn_type$2[6:0]$9041 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9041 end - attribute \src "libresoc.v:153842.3-153843.55" - process $proc$libresoc.v:153842$8639 + attribute \src "libresoc.v:157475.3-157476.53" + process $proc$libresoc.v:157475$9042 assign { } { } - assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + assign $0\alu_op__fn_unit$3[11:0]$9043 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9043 end - attribute \src "libresoc.v:153844.3-153845.43" - process $proc$libresoc.v:153844$8640 + attribute \src "libresoc.v:157477.3-157478.67" + process $proc$libresoc.v:157477$9044 assign { } { } - assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + assign $0\alu_op__imm_data__data$4[63:0]$9045 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9045 end - attribute \src "libresoc.v:153846.3-153847.43" - process $proc$libresoc.v:153846$8641 + attribute \src "libresoc.v:157479.3-157480.63" + process $proc$libresoc.v:157479$9046 assign { } { } - assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + assign $0\alu_op__imm_data__ok$5[0:0]$9047 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9047 end - attribute \src "libresoc.v:153848.3-153849.43" - process $proc$libresoc.v:153848$8642 + attribute \src "libresoc.v:157481.3-157482.51" + process $proc$libresoc.v:157481$9048 assign { } { } - assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + assign $0\alu_op__rc__rc$6[0:0]$9049 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9049 end - attribute \src "libresoc.v:153850.3-153851.43" - process $proc$libresoc.v:153850$8643 + attribute \src "libresoc.v:157483.3-157484.51" + process $proc$libresoc.v:157483$9050 assign { } { } - assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + assign $0\alu_op__rc__ok$7[0:0]$9051 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9051 end - attribute \src "libresoc.v:153852.3-153853.49" - process $proc$libresoc.v:153852$8644 + attribute \src "libresoc.v:157485.3-157486.51" + process $proc$libresoc.v:157485$9052 assign { } { } - assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + assign $0\alu_op__oe__oe$8[0:0]$9053 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9053 end - attribute \src "libresoc.v:153854.3-153855.53" - process $proc$libresoc.v:153854$8645 + attribute \src "libresoc.v:157487.3-157488.51" + process $proc$libresoc.v:157487$9054 assign { } { } - assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + assign $0\alu_op__oe__ok$9[0:0]$9055 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__input_carry $0\sr_op__input_carry[1:0] + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9055 end - attribute \src "libresoc.v:153856.3-153857.55" - process $proc$libresoc.v:153856$8646 + attribute \src "libresoc.v:157489.3-157490.59" + process $proc$libresoc.v:157489$9056 assign { } { } - assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + assign $0\alu_op__invert_in$10[0:0]$9057 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \sr_op__output_carry $0\sr_op__output_carry[0:0] + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9057 end - attribute \src "libresoc.v:153858.3-153859.47" - process $proc$libresoc.v:153858$8647 + attribute \src "libresoc.v:157491.3-157492.53" + process $proc$libresoc.v:157491$9058 assign { } { } - assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + assign $0\alu_op__zero_a$11[0:0]$9059 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \sr_op__input_cr $0\sr_op__input_cr[0:0] + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9059 end - attribute \src "libresoc.v:153860.3-153861.49" - process $proc$libresoc.v:153860$8648 + attribute \src "libresoc.v:157493.3-157494.61" + process $proc$libresoc.v:157493$9060 assign { } { } - assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + assign $0\alu_op__invert_out$12[0:0]$9061 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \sr_op__output_cr $0\sr_op__output_cr[0:0] + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9061 end - attribute \src "libresoc.v:153862.3-153863.47" - process $proc$libresoc.v:153862$8649 + attribute \src "libresoc.v:157495.3-157496.59" + process $proc$libresoc.v:157495$9062 assign { } { } - assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + assign $0\alu_op__write_cr0$13[0:0]$9063 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9063 end - attribute \src "libresoc.v:153864.3-153865.49" - process $proc$libresoc.v:153864$8650 + attribute \src "libresoc.v:157497.3-157498.63" + process $proc$libresoc.v:157497$9064 assign { } { } - assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + assign $0\alu_op__input_carry$14[1:0]$9065 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \sr_op__is_signed $0\sr_op__is_signed[0:0] + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9065 end - attribute \src "libresoc.v:153866.3-153867.39" - process $proc$libresoc.v:153866$8651 + attribute \src "libresoc.v:157499.3-157500.65" + process $proc$libresoc.v:157499$9066 assign { } { } - assign $0\sr_op__insn[31:0] \sr_op__insn$next + assign $0\alu_op__output_carry$15[0:0]$9067 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \sr_op__insn $0\sr_op__insn[31:0] + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9067 end - attribute \src "libresoc.v:153868.3-153869.27" - process $proc$libresoc.v:153868$8652 + attribute \src "libresoc.v:157501.3-157502.57" + process $proc$libresoc.v:157501$9068 assign { } { } - assign $0\muxid[1:0] \muxid$next + assign $0\alu_op__is_32bit$16[0:0]$9069 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \muxid $0\muxid[1:0] + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9069 end - attribute \src "libresoc.v:153870.3-153871.29" - process $proc$libresoc.v:153870$8653 + attribute \src "libresoc.v:157503.3-157504.59" + process $proc$libresoc.v:157503$9070 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9071 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9071 + end + attribute \src "libresoc.v:157505.3-157506.57" + process $proc$libresoc.v:157505$9072 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9073 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9073 + end + attribute \src "libresoc.v:157507.3-157508.49" + process $proc$libresoc.v:157507$9074 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9075 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9075 + end + attribute \src "libresoc.v:157509.3-157510.33" + process $proc$libresoc.v:157509$9076 + assign { } { } + assign $0\muxid$1[1:0]$9077 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9077 + end + attribute \src "libresoc.v:157511.3-157512.29" + process $proc$libresoc.v:157511$9078 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:153970.3-153987.6" - process $proc$libresoc.v:153970$8654 + attribute \src "libresoc.v:157577.3-157594.6" + process $proc$libresoc.v:157577$9079 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8655 $2\r_busy$next[0:0]$8657 - attribute \src "libresoc.v:153971.5-153971.29" + assign $0\r_busy$next[0:0]$9080 $2\r_busy$next[0:0]$9082 + attribute \src "libresoc.v:157578.5-157578.29" switch \initial - attribute \src "libresoc.v:153971.9-153971.17" + attribute \src "libresoc.v:157578.9-157578.17" case 1'1 case end @@ -317012,34 +325324,34 @@ module \pipe1$107 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8656 1'1 + assign $1\r_busy$next[0:0]$9081 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8656 1'0 + assign $1\r_busy$next[0:0]$9081 1'0 case - assign $1\r_busy$next[0:0]$8656 \r_busy + assign $1\r_busy$next[0:0]$9081 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8657 1'0 + assign $2\r_busy$next[0:0]$9082 1'0 case - assign $2\r_busy$next[0:0]$8657 $1\r_busy$next[0:0]$8656 + assign $2\r_busy$next[0:0]$9082 $1\r_busy$next[0:0]$9081 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8655 + update \r_busy$next $0\r_busy$next[0:0]$9080 end - attribute \src "libresoc.v:153988.3-154000.6" - process $proc$libresoc.v:153988$8658 + attribute \src "libresoc.v:157595.3-157607.6" + process $proc$libresoc.v:157595$9083 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8659 $1\muxid$next[1:0]$8660 - attribute \src "libresoc.v:153989.5-153989.29" + assign $0\muxid$1$next[1:0]$9084 $1\muxid$1$next[1:0]$9085 + attribute \src "libresoc.v:157596.5-157596.29" switch \initial - attribute \src "libresoc.v:153989.9-153989.17" + attribute \src "libresoc.v:157596.9-157596.17" case 1'1 case end @@ -317048,19 +325360,23 @@ module \pipe1$107 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$8660 \muxid$64 + assign $1\muxid$1$next[1:0]$9085 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$8660 \muxid$64 + assign $1\muxid$1$next[1:0]$9085 \muxid$62 case - assign $1\muxid$next[1:0]$8660 \muxid + assign $1\muxid$1$next[1:0]$9085 \muxid$1 end sync always - update \muxid$next $0\muxid$next[1:0]$8659 + update \muxid$1$next $0\muxid$1$next[1:0]$9084 end - attribute \src "libresoc.v:154001.3-154040.6" - process $proc$libresoc.v:154001$8661 + attribute \src "libresoc.v:157608.3-157649.6" + process $proc$libresoc.v:157608$9086 + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -317093,31 +325409,33 @@ module \pipe1$107 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[11:0]$8662 $1\sr_op__fn_unit$next[11:0]$8678 + assign $0\alu_op__data_len$18$next[3:0]$9087 $1\alu_op__data_len$18$next[3:0]$9105 + assign $0\alu_op__fn_unit$3$next[11:0]$9088 $1\alu_op__fn_unit$3$next[11:0]$9106 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$8665 $1\sr_op__input_carry$next[1:0]$8681 - assign $0\sr_op__input_cr$next[0:0]$8666 $1\sr_op__input_cr$next[0:0]$8682 - assign $0\sr_op__insn$next[31:0]$8667 $1\sr_op__insn$next[31:0]$8683 - assign $0\sr_op__insn_type$next[6:0]$8668 $1\sr_op__insn_type$next[6:0]$8684 - assign $0\sr_op__is_32bit$next[0:0]$8669 $1\sr_op__is_32bit$next[0:0]$8685 - assign $0\sr_op__is_signed$next[0:0]$8670 $1\sr_op__is_signed$next[0:0]$8686 + assign $0\alu_op__input_carry$14$next[1:0]$9091 $1\alu_op__input_carry$14$next[1:0]$9109 + assign $0\alu_op__insn$19$next[31:0]$9092 $1\alu_op__insn$19$next[31:0]$9110 + assign $0\alu_op__insn_type$2$next[6:0]$9093 $1\alu_op__insn_type$2$next[6:0]$9111 + assign $0\alu_op__invert_in$10$next[0:0]$9094 $1\alu_op__invert_in$10$next[0:0]$9112 + assign $0\alu_op__invert_out$12$next[0:0]$9095 $1\alu_op__invert_out$12$next[0:0]$9113 + assign $0\alu_op__is_32bit$16$next[0:0]$9096 $1\alu_op__is_32bit$16$next[0:0]$9114 + assign $0\alu_op__is_signed$17$next[0:0]$9097 $1\alu_op__is_signed$17$next[0:0]$9115 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$8673 $1\sr_op__output_carry$next[0:0]$8689 - assign $0\sr_op__output_cr$next[0:0]$8674 $1\sr_op__output_cr$next[0:0]$8690 + assign $0\alu_op__output_carry$15$next[0:0]$9100 $1\alu_op__output_carry$15$next[0:0]$9118 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$8677 $1\sr_op__write_cr0$next[0:0]$8693 - assign $0\sr_op__imm_data__data$next[63:0]$8663 $2\sr_op__imm_data__data$next[63:0]$8694 - assign $0\sr_op__imm_data__ok$next[0:0]$8664 $2\sr_op__imm_data__ok$next[0:0]$8695 - assign $0\sr_op__oe__oe$next[0:0]$8671 $2\sr_op__oe__oe$next[0:0]$8696 - assign $0\sr_op__oe__ok$next[0:0]$8672 $2\sr_op__oe__ok$next[0:0]$8697 - assign $0\sr_op__rc__ok$next[0:0]$8675 $2\sr_op__rc__ok$next[0:0]$8698 - assign $0\sr_op__rc__rc$next[0:0]$8676 $2\sr_op__rc__rc$next[0:0]$8699 - attribute \src "libresoc.v:154002.5-154002.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9103 $1\alu_op__write_cr0$13$next[0:0]$9121 + assign $0\alu_op__zero_a$11$next[0:0]$9104 $1\alu_op__zero_a$11$next[0:0]$9122 + assign $0\alu_op__imm_data__data$4$next[63:0]$9089 $2\alu_op__imm_data__data$4$next[63:0]$9123 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9090 $2\alu_op__imm_data__ok$5$next[0:0]$9124 + assign $0\alu_op__oe__oe$8$next[0:0]$9098 $2\alu_op__oe__oe$8$next[0:0]$9125 + assign $0\alu_op__oe__ok$9$next[0:0]$9099 $2\alu_op__oe__ok$9$next[0:0]$9126 + assign $0\alu_op__rc__ok$7$next[0:0]$9101 $2\alu_op__rc__ok$7$next[0:0]$9127 + assign $0\alu_op__rc__rc$6$next[0:0]$9102 $2\alu_op__rc__rc$6$next[0:0]$9128 + attribute \src "libresoc.v:157609.5-157609.29" switch \initial - attribute \src "libresoc.v:154002.9-154002.17" + attribute \src "libresoc.v:157609.9-157609.17" case 1'1 case end @@ -317141,7 +325459,9 @@ module \pipe1$107 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$8683 $1\sr_op__is_signed$next[0:0]$8686 $1\sr_op__is_32bit$next[0:0]$8685 $1\sr_op__output_cr$next[0:0]$8690 $1\sr_op__input_cr$next[0:0]$8682 $1\sr_op__output_carry$next[0:0]$8689 $1\sr_op__input_carry$next[1:0]$8681 $1\sr_op__write_cr0$next[0:0]$8693 $1\sr_op__oe__ok$next[0:0]$8688 $1\sr_op__oe__oe$next[0:0]$8687 $1\sr_op__rc__ok$next[0:0]$8691 $1\sr_op__rc__rc$next[0:0]$8692 $1\sr_op__imm_data__ok$next[0:0]$8680 $1\sr_op__imm_data__data$next[63:0]$8679 $1\sr_op__fn_unit$next[11:0]$8678 $1\sr_op__insn_type$next[6:0]$8684 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9110 $1\alu_op__data_len$18$next[3:0]$9105 $1\alu_op__is_signed$17$next[0:0]$9115 $1\alu_op__is_32bit$16$next[0:0]$9114 $1\alu_op__output_carry$15$next[0:0]$9118 $1\alu_op__input_carry$14$next[1:0]$9109 $1\alu_op__write_cr0$13$next[0:0]$9121 $1\alu_op__invert_out$12$next[0:0]$9113 $1\alu_op__zero_a$11$next[0:0]$9122 $1\alu_op__invert_in$10$next[0:0]$9112 $1\alu_op__oe__ok$9$next[0:0]$9117 $1\alu_op__oe__oe$8$next[0:0]$9116 $1\alu_op__rc__ok$7$next[0:0]$9119 $1\alu_op__rc__rc$6$next[0:0]$9120 $1\alu_op__imm_data__ok$5$next[0:0]$9108 $1\alu_op__imm_data__data$4$next[63:0]$9107 $1\alu_op__fn_unit$3$next[11:0]$9106 $1\alu_op__insn_type$2$next[6:0]$9111 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -317160,24 +325480,28 @@ module \pipe1$107 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$8683 $1\sr_op__is_signed$next[0:0]$8686 $1\sr_op__is_32bit$next[0:0]$8685 $1\sr_op__output_cr$next[0:0]$8690 $1\sr_op__input_cr$next[0:0]$8682 $1\sr_op__output_carry$next[0:0]$8689 $1\sr_op__input_carry$next[1:0]$8681 $1\sr_op__write_cr0$next[0:0]$8693 $1\sr_op__oe__ok$next[0:0]$8688 $1\sr_op__oe__oe$next[0:0]$8687 $1\sr_op__rc__ok$next[0:0]$8691 $1\sr_op__rc__rc$next[0:0]$8692 $1\sr_op__imm_data__ok$next[0:0]$8680 $1\sr_op__imm_data__data$next[63:0]$8679 $1\sr_op__fn_unit$next[11:0]$8678 $1\sr_op__insn_type$next[6:0]$8684 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9110 $1\alu_op__data_len$18$next[3:0]$9105 $1\alu_op__is_signed$17$next[0:0]$9115 $1\alu_op__is_32bit$16$next[0:0]$9114 $1\alu_op__output_carry$15$next[0:0]$9118 $1\alu_op__input_carry$14$next[1:0]$9109 $1\alu_op__write_cr0$13$next[0:0]$9121 $1\alu_op__invert_out$12$next[0:0]$9113 $1\alu_op__zero_a$11$next[0:0]$9122 $1\alu_op__invert_in$10$next[0:0]$9112 $1\alu_op__oe__ok$9$next[0:0]$9117 $1\alu_op__oe__oe$8$next[0:0]$9116 $1\alu_op__rc__ok$7$next[0:0]$9119 $1\alu_op__rc__rc$6$next[0:0]$9120 $1\alu_op__imm_data__ok$5$next[0:0]$9108 $1\alu_op__imm_data__data$4$next[63:0]$9107 $1\alu_op__fn_unit$3$next[11:0]$9106 $1\alu_op__insn_type$2$next[6:0]$9111 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\sr_op__fn_unit$next[11:0]$8678 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$8679 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$8680 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$8681 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$8682 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$8683 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$8684 \sr_op__insn_type - assign $1\sr_op__is_32bit$next[0:0]$8685 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$8686 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$8687 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$8688 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$8689 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$8690 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$8691 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$8692 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$8693 \sr_op__write_cr0 + assign $1\alu_op__data_len$18$next[3:0]$9105 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[11:0]$9106 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9107 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9108 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9109 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9110 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9111 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9112 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9113 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9114 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9115 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9116 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9117 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9118 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9119 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9120 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9121 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9122 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -317189,50 +325513,96 @@ module \pipe1$107 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$8694 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$8695 1'0 - assign $2\sr_op__rc__rc$next[0:0]$8699 1'0 - assign $2\sr_op__rc__ok$next[0:0]$8698 1'0 - assign $2\sr_op__oe__oe$next[0:0]$8696 1'0 - assign $2\sr_op__oe__ok$next[0:0]$8697 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9123 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9124 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9128 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9127 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9125 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9126 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$9123 $1\alu_op__imm_data__data$4$next[63:0]$9107 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9124 $1\alu_op__imm_data__ok$5$next[0:0]$9108 + assign $2\alu_op__oe__oe$8$next[0:0]$9125 $1\alu_op__oe__oe$8$next[0:0]$9116 + assign $2\alu_op__oe__ok$9$next[0:0]$9126 $1\alu_op__oe__ok$9$next[0:0]$9117 + assign $2\alu_op__rc__ok$7$next[0:0]$9127 $1\alu_op__rc__ok$7$next[0:0]$9119 + assign $2\alu_op__rc__rc$6$next[0:0]$9128 $1\alu_op__rc__rc$6$next[0:0]$9120 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9087 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$9088 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9089 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9090 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9091 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9092 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9093 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9094 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9095 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9096 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9097 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9098 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9099 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9100 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9101 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9102 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9103 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9104 + end + attribute \src "libresoc.v:157650.3-157668.6" + process $proc$libresoc.v:157650$9129 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$9130 $1\o$20$next[63:0]$9132 + assign { } { } + assign $0\o_ok$21$next[0:0]$9131 $2\o_ok$21$next[0:0]$9134 + attribute \src "libresoc.v:157651.5-157651.29" + switch \initial + attribute \src "libresoc.v:157651.9-157651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9133 $1\o$20$next[63:0]$9132 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9133 $1\o$20$next[63:0]$9132 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$9132 \o$20 + assign $1\o_ok$21$next[0:0]$9133 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$9134 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$8694 $1\sr_op__imm_data__data$next[63:0]$8679 - assign $2\sr_op__imm_data__ok$next[0:0]$8695 $1\sr_op__imm_data__ok$next[0:0]$8680 - assign $2\sr_op__oe__oe$next[0:0]$8696 $1\sr_op__oe__oe$next[0:0]$8687 - assign $2\sr_op__oe__ok$next[0:0]$8697 $1\sr_op__oe__ok$next[0:0]$8688 - assign $2\sr_op__rc__ok$next[0:0]$8698 $1\sr_op__rc__ok$next[0:0]$8691 - assign $2\sr_op__rc__rc$next[0:0]$8699 $1\sr_op__rc__rc$next[0:0]$8692 + assign $2\o_ok$21$next[0:0]$9134 $1\o_ok$21$next[0:0]$9133 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8662 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8663 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8664 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8665 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8666 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8667 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8668 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8669 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8670 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8671 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8672 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8673 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8674 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8675 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8676 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8677 + update \o$20$next $0\o$20$next[63:0]$9130 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9131 end - attribute \src "libresoc.v:154041.3-154059.6" - process $proc$libresoc.v:154041$8700 + attribute \src "libresoc.v:157669.3-157687.6" + process $proc$libresoc.v:157669$9135 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8701 $1\o$next[63:0]$8703 + assign $0\cr_a$22$next[3:0]$9136 $1\cr_a$22$next[3:0]$9138 assign { } { } - assign $0\o_ok$next[0:0]$8702 $2\o_ok$next[0:0]$8705 - attribute \src "libresoc.v:154042.5-154042.29" + assign $0\cr_a_ok$23$next[0:0]$9137 $2\cr_a_ok$23$next[0:0]$9140 + attribute \src "libresoc.v:157670.5-157670.29" switch \initial - attribute \src "libresoc.v:154042.9-154042.17" + attribute \src "libresoc.v:157670.9-157670.17" case 1'1 case end @@ -317242,41 +325612,41 @@ module \pipe1$107 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8704 $1\o$next[63:0]$8703 } { \o_ok$82 \o$81 } + assign { $1\cr_a_ok$23$next[0:0]$9139 $1\cr_a$22$next[3:0]$9138 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8704 $1\o$next[63:0]$8703 } { \o_ok$82 \o$81 } + assign { $1\cr_a_ok$23$next[0:0]$9139 $1\cr_a$22$next[3:0]$9138 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\o$next[63:0]$8703 \o - assign $1\o_ok$next[0:0]$8704 \o_ok + assign $1\cr_a$22$next[3:0]$9138 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9139 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8705 1'0 + assign $2\cr_a_ok$23$next[0:0]$9140 1'0 case - assign $2\o_ok$next[0:0]$8705 $1\o_ok$next[0:0]$8704 + assign $2\cr_a_ok$23$next[0:0]$9140 $1\cr_a_ok$23$next[0:0]$9139 end sync always - update \o$next $0\o$next[63:0]$8701 - update \o_ok$next $0\o_ok$next[0:0]$8702 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9136 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9137 end - attribute \src "libresoc.v:154060.3-154078.6" - process $proc$libresoc.v:154060$8706 + attribute \src "libresoc.v:157688.3-157706.6" + process $proc$libresoc.v:157688$9141 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8707 $1\cr_a$next[3:0]$8709 + assign $0\xer_ca$24$next[1:0]$9142 $1\xer_ca$24$next[1:0]$9144 assign { } { } - assign $0\cr_a_ok$next[0:0]$8708 $2\cr_a_ok$next[0:0]$8711 - attribute \src "libresoc.v:154061.5-154061.29" + assign $0\xer_ca_ok$25$next[0:0]$9143 $2\xer_ca_ok$25$next[0:0]$9146 + attribute \src "libresoc.v:157689.5-157689.29" switch \initial - attribute \src "libresoc.v:154061.9-154061.17" + attribute \src "libresoc.v:157689.9-157689.17" case 1'1 case end @@ -317286,41 +325656,41 @@ module \pipe1$107 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$next[3:0]$8709 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\xer_ca_ok$25$next[0:0]$9145 $1\xer_ca$24$next[1:0]$9144 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8710 $1\cr_a$next[3:0]$8709 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\xer_ca_ok$25$next[0:0]$9145 $1\xer_ca$24$next[1:0]$9144 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\cr_a$next[3:0]$8709 \cr_a - assign $1\cr_a_ok$next[0:0]$8710 \cr_a_ok + assign $1\xer_ca$24$next[1:0]$9144 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9145 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8711 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9146 1'0 case - assign $2\cr_a_ok$next[0:0]$8711 $1\cr_a_ok$next[0:0]$8710 + assign $2\xer_ca_ok$25$next[0:0]$9146 $1\xer_ca_ok$25$next[0:0]$9145 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8707 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8708 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9142 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9143 end - attribute \src "libresoc.v:154079.3-154097.6" - process $proc$libresoc.v:154079$8712 + attribute \src "libresoc.v:157707.3-157725.6" + process $proc$libresoc.v:157707$9147 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8713 $1\xer_so$next[0:0]$8715 + assign $0\xer_ov$26$next[1:0]$9148 $1\xer_ov$26$next[1:0]$9150 assign { } { } - assign $0\xer_so_ok$next[0:0]$8714 $2\xer_so_ok$next[0:0]$8717 - attribute \src "libresoc.v:154080.5-154080.29" + assign $0\xer_ov_ok$27$next[0:0]$9149 $2\xer_ov_ok$27$next[0:0]$9152 + attribute \src "libresoc.v:157708.5-157708.29" switch \initial - attribute \src "libresoc.v:154080.9-154080.17" + attribute \src "libresoc.v:157708.9-157708.17" case 1'1 case end @@ -317330,41 +325700,41 @@ module \pipe1$107 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8716 $1\xer_so$next[0:0]$8715 } { \xer_so_ok$88 \xer_so$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9151 $1\xer_ov$26$next[1:0]$9150 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8716 $1\xer_so$next[0:0]$8715 } { \xer_so_ok$88 \xer_so$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9151 $1\xer_ov$26$next[1:0]$9150 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_so$next[0:0]$8715 \xer_so - assign $1\xer_so_ok$next[0:0]$8716 \xer_so_ok + assign $1\xer_ov$26$next[1:0]$9150 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9151 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8717 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9152 1'0 case - assign $2\xer_so_ok$next[0:0]$8717 $1\xer_so_ok$next[0:0]$8716 + assign $2\xer_ov_ok$27$next[0:0]$9152 $1\xer_ov_ok$27$next[0:0]$9151 end sync always - update \xer_so$next $0\xer_so$next[0:0]$8713 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8714 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9148 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9149 end - attribute \src "libresoc.v:154098.3-154116.6" - process $proc$libresoc.v:154098$8718 + attribute \src "libresoc.v:157726.3-157744.6" + process $proc$libresoc.v:157726$9153 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_so$28$next[0:0]$9154 $1\xer_so$28$next[0:0]$9156 assign { } { } - assign $0\xer_ca$next[1:0]$8720 $1\xer_ca$next[1:0]$8722 - assign $0\xer_ca_ok$next[0:0]$8719 $2\xer_ca_ok$next[0:0]$8723 - attribute \src "libresoc.v:154099.5-154099.29" + assign $0\xer_so_ok$29$next[0:0]$9155 $2\xer_so_ok$29$next[0:0]$9158 + attribute \src "libresoc.v:157727.5-157727.29" switch \initial - attribute \src "libresoc.v:154099.9-154099.17" + attribute \src "libresoc.v:157727.9-157727.17" case 1'1 case end @@ -317374,358 +325744,353 @@ module \pipe1$107 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8721 $1\xer_ca$next[1:0]$8722 } { \xer_ca_ok$91 \xer_ca$90 } + assign { $1\xer_so_ok$29$next[0:0]$9157 $1\xer_so$28$next[0:0]$9156 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8721 $1\xer_ca$next[1:0]$8722 } { \xer_ca_ok$91 \xer_ca$90 } + assign { $1\xer_so_ok$29$next[0:0]$9157 $1\xer_so$28$next[0:0]$9156 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_ca_ok$next[0:0]$8721 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8722 \xer_ca + assign $1\xer_so$28$next[0:0]$9156 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9157 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8723 1'0 + assign $2\xer_so_ok$29$next[0:0]$9158 1'0 case - assign $2\xer_ca_ok$next[0:0]$8723 $1\xer_ca_ok$next[0:0]$8721 + assign $2\xer_so_ok$29$next[0:0]$9158 $1\xer_so_ok$29$next[0:0]$9157 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8719 - update \xer_ca$next $0\xer_ca$next[1:0]$8720 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9154 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9155 end - connect \$62 $and$libresoc.v:153819$8627_Y - connect \cr_a$85 4'0000 - connect \cr_a_ok$86 1'0 - connect \xer_so_ok$89 1'0 - connect \xer_ca_ok$92 1'0 + connect \$60 $and$libresoc.v:157452$9019_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$91 \xer_ca$90 } { 1'0 \main_xer_ca } - connect { \xer_so_ok$88 \xer_so$87 } { 1'0 \main_xer_so$59 } - connect { \cr_a_ok$84 \cr_a$83 } 5'00000 - connect { \o_ok$82 \o$81 } { \main_o_ok \main_o } - connect { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } { \main_sr_op__insn$58 \main_sr_op__is_signed$57 \main_sr_op__is_32bit$56 \main_sr_op__output_cr$55 \main_sr_op__input_cr$54 \main_sr_op__output_carry$53 \main_sr_op__input_carry$52 \main_sr_op__write_cr0$51 \main_sr_op__oe__ok$50 \main_sr_op__oe__oe$49 \main_sr_op__rc__ok$48 \main_sr_op__rc__rc$47 \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } - connect \muxid$64 \main_muxid$42 - connect \p_valid_i_p_ready_o \$62 + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$61 \p_valid_i - connect \xer_ca$60 \input_xer_ca$41 - connect \main_xer_so \input_xer_so$40 - connect \main_rc \input_rc$39 - connect \main_rb \input_rb$38 - connect \main_ra \input_ra$37 - connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$36 \input_sr_op__is_signed$35 \input_sr_op__is_32bit$34 \input_sr_op__output_cr$33 \input_sr_op__input_cr$32 \input_sr_op__output_carry$31 \input_sr_op__input_carry$30 \input_sr_op__write_cr0$29 \input_sr_op__oe__ok$28 \input_sr_op__oe__oe$27 \input_sr_op__rc__ok$26 \input_sr_op__rc__rc$25 \input_sr_op__imm_data__ok$24 \input_sr_op__imm_data__data$23 \input_sr_op__fn_unit$22 \input_sr_op__insn_type$21 } - connect \main_muxid \input_muxid$20 - connect \input_xer_ca \xer_ca$19 - connect \input_xer_so \xer_so$18 - connect \input_rc \rc - connect \input_rb \rb - connect \input_ra \ra - connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:154150.1-155320.10" +attribute \src "libresoc.v:157768.1-158822.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" -module \pipe2 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$8819 - attribute \src "libresoc.v:155061.3-155062.57" - wire width 4 $0\alu_op__data_len$18[3:0]$8805 - attribute \src "libresoc.v:154158.13-154158.41" - wire width 4 $0\alu_op__data_len$18[3:0]$8893 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 12 $0\alu_op__fn_unit$3$next[11:0]$8820 - attribute \src "libresoc.v:155031.3-155032.53" - wire width 12 $0\alu_op__fn_unit$3[11:0]$8775 - attribute \src "libresoc.v:154193.14-154193.43" - wire width 12 $0\alu_op__fn_unit$3[11:0]$8895 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$8821 - attribute \src "libresoc.v:155033.3-155034.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$8777 - attribute \src "libresoc.v:154215.14-154215.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$8897 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$8822 - attribute \src "libresoc.v:155035.3-155036.63" - wire $0\alu_op__imm_data__ok$5[0:0]$8779 - attribute \src "libresoc.v:154224.7-154224.38" - wire $0\alu_op__imm_data__ok$5[0:0]$8899 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$8823 - attribute \src "libresoc.v:155053.3-155054.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$8797 - attribute \src "libresoc.v:154241.13-154241.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$8901 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$8824 - attribute \src "libresoc.v:155063.3-155064.49" - wire width 32 $0\alu_op__insn$19[31:0]$8807 - attribute \src "libresoc.v:154254.14-154254.39" - wire width 32 $0\alu_op__insn$19[31:0]$8903 - attribute \src "libresoc.v:155164.3-155205.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$8825 - attribute \src "libresoc.v:155029.3-155030.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$8773 - attribute \src "libresoc.v:154411.13-154411.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$8905 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__invert_in$10$next[0:0]$8826 - attribute \src "libresoc.v:155045.3-155046.59" - wire $0\alu_op__invert_in$10[0:0]$8789 - attribute \src "libresoc.v:154494.7-154494.36" - wire $0\alu_op__invert_in$10[0:0]$8907 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__invert_out$12$next[0:0]$8827 - attribute \src "libresoc.v:155049.3-155050.61" - wire $0\alu_op__invert_out$12[0:0]$8793 - attribute \src "libresoc.v:154503.7-154503.37" - wire $0\alu_op__invert_out$12[0:0]$8909 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__is_32bit$16$next[0:0]$8828 - attribute \src "libresoc.v:155057.3-155058.57" - wire $0\alu_op__is_32bit$16[0:0]$8801 - attribute \src "libresoc.v:154512.7-154512.35" - wire $0\alu_op__is_32bit$16[0:0]$8911 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__is_signed$17$next[0:0]$8829 - attribute \src "libresoc.v:155059.3-155060.59" - wire $0\alu_op__is_signed$17[0:0]$8803 - attribute \src "libresoc.v:154521.7-154521.36" - wire $0\alu_op__is_signed$17[0:0]$8913 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__oe__oe$8$next[0:0]$8830 - attribute \src "libresoc.v:155041.3-155042.51" - wire $0\alu_op__oe__oe$8[0:0]$8785 - attribute \src "libresoc.v:154532.7-154532.32" - wire $0\alu_op__oe__oe$8[0:0]$8915 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__oe__ok$9$next[0:0]$8831 - attribute \src "libresoc.v:155043.3-155044.51" - wire $0\alu_op__oe__ok$9[0:0]$8787 - attribute \src "libresoc.v:154541.7-154541.32" - wire $0\alu_op__oe__ok$9[0:0]$8917 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__output_carry$15$next[0:0]$8832 - attribute \src "libresoc.v:155055.3-155056.65" - wire $0\alu_op__output_carry$15[0:0]$8799 - attribute \src "libresoc.v:154548.7-154548.39" - wire $0\alu_op__output_carry$15[0:0]$8919 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__rc__ok$7$next[0:0]$8833 - attribute \src "libresoc.v:155039.3-155040.51" - wire $0\alu_op__rc__ok$7[0:0]$8783 - attribute \src "libresoc.v:154559.7-154559.32" - wire $0\alu_op__rc__ok$7[0:0]$8921 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__rc__rc$6$next[0:0]$8834 - attribute \src "libresoc.v:155037.3-155038.51" - wire $0\alu_op__rc__rc$6[0:0]$8781 - attribute \src "libresoc.v:154566.7-154566.32" - wire $0\alu_op__rc__rc$6[0:0]$8923 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__write_cr0$13$next[0:0]$8835 - attribute \src "libresoc.v:155051.3-155052.59" - wire $0\alu_op__write_cr0$13[0:0]$8795 - attribute \src "libresoc.v:154575.7-154575.36" - wire $0\alu_op__write_cr0$13[0:0]$8925 - attribute \src "libresoc.v:155164.3-155205.6" - wire $0\alu_op__zero_a$11$next[0:0]$8836 - attribute \src "libresoc.v:155047.3-155048.53" - wire $0\alu_op__zero_a$11[0:0]$8791 - attribute \src "libresoc.v:154584.7-154584.33" - wire $0\alu_op__zero_a$11[0:0]$8927 - attribute \src "libresoc.v:155225.3-155243.6" - wire width 4 $0\cr_a$22$next[3:0]$8868 - attribute \src "libresoc.v:155021.3-155022.33" - wire width 4 $0\cr_a$22[3:0]$8765 - attribute \src "libresoc.v:154597.13-154597.29" - wire width 4 $0\cr_a$22[3:0]$8929 - attribute \src "libresoc.v:155225.3-155243.6" - wire $0\cr_a_ok$23$next[0:0]$8869 - attribute \src "libresoc.v:155023.3-155024.39" - wire $0\cr_a_ok$23[0:0]$8767 - attribute \src "libresoc.v:154606.7-154606.26" - wire $0\cr_a_ok$23[0:0]$8931 - attribute \src "libresoc.v:154151.7-154151.20" +module \pipe2$115 + attribute \src "libresoc.v:158768.3-158786.6" + wire width 4 $0\cr_a$21$next[3:0]$9324 + attribute \src "libresoc.v:158574.3-158575.33" + wire width 4 $0\cr_a$21[3:0]$9225 + attribute \src "libresoc.v:157780.13-157780.29" + wire width 4 $0\cr_a$21[3:0]$9337 + attribute \src "libresoc.v:158768.3-158786.6" + wire $0\cr_a_ok$22$next[0:0]$9325 + attribute \src "libresoc.v:158576.3-158577.39" + wire $0\cr_a_ok$22[0:0]$9227 + attribute \src "libresoc.v:157789.7-157789.26" + wire $0\cr_a_ok$22[0:0]$9339 + attribute \src "libresoc.v:157769.7-157769.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155151.3-155163.6" - wire width 2 $0\muxid$1$next[1:0]$8816 - attribute \src "libresoc.v:155065.3-155066.33" - wire width 2 $0\muxid$1[1:0]$8809 - attribute \src "libresoc.v:154617.13-154617.29" - wire width 2 $0\muxid$1[1:0]$8933 - attribute \src "libresoc.v:155206.3-155224.6" - wire width 64 $0\o$20$next[63:0]$8862 - attribute \src "libresoc.v:155025.3-155026.27" - wire width 64 $0\o$20[63:0]$8769 - attribute \src "libresoc.v:154632.14-154632.43" - wire width 64 $0\o$20[63:0]$8935 - attribute \src "libresoc.v:155206.3-155224.6" - wire $0\o_ok$21$next[0:0]$8863 - attribute \src "libresoc.v:155027.3-155028.33" - wire $0\o_ok$21[0:0]$8771 - attribute \src "libresoc.v:154641.7-154641.23" - wire $0\o_ok$21[0:0]$8937 - attribute \src "libresoc.v:155133.3-155150.6" - wire $0\r_busy$next[0:0]$8812 - attribute \src "libresoc.v:155067.3-155068.29" + attribute \src "libresoc.v:158695.3-158707.6" + wire width 2 $0\muxid$1$next[1:0]$9274 + attribute \src "libresoc.v:158616.3-158617.33" + wire width 2 $0\muxid$1[1:0]$9267 + attribute \src "libresoc.v:157800.13-157800.29" + wire width 2 $0\muxid$1[1:0]$9341 + attribute \src "libresoc.v:158749.3-158767.6" + wire width 64 $0\o$19$next[63:0]$9318 + attribute \src "libresoc.v:158578.3-158579.27" + wire width 64 $0\o$19[63:0]$9229 + attribute \src "libresoc.v:157815.14-157815.43" + wire width 64 $0\o$19[63:0]$9343 + attribute \src "libresoc.v:158749.3-158767.6" + wire $0\o_ok$20$next[0:0]$9319 + attribute \src "libresoc.v:158580.3-158581.33" + wire $0\o_ok$20[0:0]$9231 + attribute \src "libresoc.v:157824.7-157824.23" + wire $0\o_ok$20[0:0]$9345 + attribute \src "libresoc.v:158677.3-158694.6" + wire $0\r_busy$next[0:0]$9270 + attribute \src "libresoc.v:158618.3-158619.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155244.3-155262.6" - wire width 2 $0\xer_ca$24$next[1:0]$8874 - attribute \src "libresoc.v:155017.3-155018.37" - wire width 2 $0\xer_ca$24[1:0]$8761 - attribute \src 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+ wire $1\xer_ca_ok$24$next[0:0]$9333 + attribute \src "libresoc.v:158768.3-158786.6" + wire $2\cr_a_ok$22$next[0:0]$9328 + attribute \src "libresoc.v:158749.3-158767.6" + wire $2\o_ok$20$next[0:0]$9322 + attribute \src "libresoc.v:158677.3-158694.6" + wire $2\r_busy$next[0:0]$9272 + attribute \src "libresoc.v:158708.3-158748.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9311 + attribute \src "libresoc.v:158708.3-158748.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9312 + attribute \src "libresoc.v:158708.3-158748.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9313 + attribute \src "libresoc.v:158708.3-158748.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9314 + attribute \src "libresoc.v:158708.3-158748.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9315 + attribute \src "libresoc.v:158708.3-158748.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9316 + attribute \src "libresoc.v:158787.3-158805.6" + wire $2\xer_ca_ok$24$next[0:0]$9334 + attribute \src "libresoc.v:158569.18-158569.118" + wire $and$libresoc.v:158569$9219_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \alu_op__fn_unit + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 56 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "libresoc.v:157769.7-157769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 31 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 30 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -317740,9 +326105,7 @@ module \pipe2 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$3$next + wire width 12 \output_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -317757,51 +326120,35 @@ module \pipe2 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__imm_data__ok + wire width 12 \output_sr_op__fn_unit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__imm_data__ok$5 + wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$5$next + wire width 64 \output_sr_op__imm_data__data$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$66 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \output_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry + wire \output_sr_op__imm_data__ok$29 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 48 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next + wire width 2 \output_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 + wire width 2 \output_sr_op__input_carry$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn + wire \output_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 + wire \output_sr_op__input_cr$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next + wire width 32 \output_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 + wire width 32 \output_sr_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317877,7 +326224,7 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type + wire width 7 \output_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -317953,9 +326300,166 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \alu_op__insn_type$2 + wire width 7 \output_sr_op__insn_type$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next + wire \output_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 43 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -318031,207 +326535,7 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \cr_a_ok$84 - attribute \src "libresoc.v:154151.7-154151.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 54 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 55 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_alu_op__fn_unit$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn$48 + wire width 7 input 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -318307,7 +326611,9 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type + wire width 7 output 33 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -318383,701 +326689,577 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type$31 + wire width 7 \sr_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in + wire input 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in$39 + wire output 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out + wire \sr_op__invert_in$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out$41 + wire \sr_op__invert_in$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit + wire input 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit$45 + wire output 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed + wire \sr_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed$46 + wire \sr_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe + wire input 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe$37 + wire output 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok + wire \sr_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok$38 + wire \sr_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry + wire input 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry$44 + wire \sr_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok + wire output 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok$36 + wire \sr_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc + wire input 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc$35 + wire \sr_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0 + wire output 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0$42 + wire \sr_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a + wire input 16 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 58 \xer_ca$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 59 \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 60 \xer_ov$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 61 \xer_ov_ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$27$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ov_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 62 \xer_so$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$28$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 63 \xer_so_ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$90 + wire output 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 54 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \xer_ca_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:155008$8751 + cell $and $and$libresoc.v:158569$9219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$59 + connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:155008$8751_Y + connect \Y $and$libresoc.v:158569$9219_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155069.9-155072.4" - cell \n$4 \n + attribute \src "libresoc.v:158620.11-158623.4" + cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155073.12-155128.4" - cell \output \output - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__data_len$18 \output_alu_op__data_len$47 - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__data \output_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 - connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 - connect \alu_op__insn \output_alu_op__insn - connect \alu_op__insn$19 \output_alu_op__insn$48 - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 - connect \alu_op__invert_in \output_alu_op__invert_in - connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__ok \output_alu_op__oe__ok - connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 - connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + attribute \src "libresoc.v:158624.16-158672.4" + cell \output$118 \output connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$51 + connect \cr_a$21 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok connect \muxid \output_muxid - connect \muxid$1 \output_muxid$30 + connect \muxid$1 \output_muxid$25 connect \o \output_o - connect \o$20 \output_o$49 + connect \o$19 \output_o$43 connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$50 + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 connect \xer_ca \output_xer_ca - connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca$22 \output_xer_ca$46 connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov \output_xer_ov - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok connect \xer_so \output_xer_so - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:155129.9-155132.4" - cell \p$3 \p + attribute \src "libresoc.v:158673.11-158676.4" + cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154151.7-154151.20" - process $proc$libresoc.v:154151$8891 + attribute \src "libresoc.v:157769.7-157769.20" + process $proc$libresoc.v:157769$9335 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154158.13-154158.41" - process $proc$libresoc.v:154158$8892 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$8893 4'0000 - sync always - sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8893 - end - attribute \src "libresoc.v:154193.14-154193.43" - process $proc$libresoc.v:154193$8894 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$8895 12'000000000000 - sync always - sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8895 - end - attribute \src "libresoc.v:154215.14-154215.63" - process $proc$libresoc.v:154215$8896 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8897 - end - attribute \src "libresoc.v:154224.7-154224.38" - process $proc$libresoc.v:154224$8898 - assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$8899 1'0 - sync always - sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8899 - end - attribute \src "libresoc.v:154241.13-154241.44" - process $proc$libresoc.v:154241$8900 - assign { } { } - assign $0\alu_op__input_carry$14[1:0]$8901 2'00 - sync always - sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8901 - end - attribute \src "libresoc.v:154254.14-154254.39" - process $proc$libresoc.v:154254$8902 + attribute \src "libresoc.v:157780.13-157780.29" + process $proc$libresoc.v:157780$9336 assign { } { } - assign $0\alu_op__insn$19[31:0]$8903 0 + assign $0\cr_a$21[3:0]$9337 4'0000 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8903 + update \cr_a$21 $0\cr_a$21[3:0]$9337 end - attribute \src "libresoc.v:154411.13-154411.42" - process $proc$libresoc.v:154411$8904 + attribute \src "libresoc.v:157789.7-157789.26" + process $proc$libresoc.v:157789$9338 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$8905 7'0000000 + assign $0\cr_a_ok$22[0:0]$9339 1'0 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8905 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9339 end - attribute \src "libresoc.v:154494.7-154494.36" - process $proc$libresoc.v:154494$8906 + attribute \src "libresoc.v:157800.13-157800.29" + process $proc$libresoc.v:157800$9340 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$8907 1'0 + assign $0\muxid$1[1:0]$9341 2'00 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8907 + update \muxid$1 $0\muxid$1[1:0]$9341 end - attribute \src "libresoc.v:154503.7-154503.37" - process $proc$libresoc.v:154503$8908 + attribute \src "libresoc.v:157815.14-157815.43" + process $proc$libresoc.v:157815$9342 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$8909 1'0 + assign $0\o$19[63:0]$9343 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8909 + update \o$19 $0\o$19[63:0]$9343 end - attribute \src "libresoc.v:154512.7-154512.35" - process $proc$libresoc.v:154512$8910 + attribute \src "libresoc.v:157824.7-157824.23" + process $proc$libresoc.v:157824$9344 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$8911 1'0 + assign $0\o_ok$20[0:0]$9345 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8911 + update \o_ok$20 $0\o_ok$20[0:0]$9345 end - attribute \src "libresoc.v:154521.7-154521.36" - process $proc$libresoc.v:154521$8912 + attribute \src "libresoc.v:158114.7-158114.20" + process $proc$libresoc.v:158114$9346 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$8913 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8913 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154532.7-154532.32" - process $proc$libresoc.v:154532$8914 + attribute \src "libresoc.v:158147.14-158147.42" + process $proc$libresoc.v:158147$9347 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$8915 1'0 + assign $0\sr_op__fn_unit$3[11:0]$9348 12'000000000000 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8915 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9348 end - attribute \src "libresoc.v:154541.7-154541.32" - process $proc$libresoc.v:154541$8916 + attribute \src "libresoc.v:158169.14-158169.62" + process $proc$libresoc.v:158169$9349 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$8917 1'0 + assign $0\sr_op__imm_data__data$4[63:0]$9350 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8917 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9350 end - attribute \src "libresoc.v:154548.7-154548.39" - process $proc$libresoc.v:154548$8918 + attribute \src "libresoc.v:158178.7-158178.37" + process $proc$libresoc.v:158178$9351 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$8919 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9352 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8919 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9352 end - attribute \src "libresoc.v:154559.7-154559.32" - process $proc$libresoc.v:154559$8920 + attribute \src "libresoc.v:158195.13-158195.43" + process $proc$libresoc.v:158195$9353 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$8921 1'0 + assign $0\sr_op__input_carry$12[1:0]$9354 2'00 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8921 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9354 end - attribute \src "libresoc.v:154566.7-154566.32" - process $proc$libresoc.v:154566$8922 + attribute \src "libresoc.v:158208.7-158208.34" + process $proc$libresoc.v:158208$9355 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$8923 1'0 + assign $0\sr_op__input_cr$14[0:0]$9356 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8923 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9356 end - attribute \src "libresoc.v:154575.7-154575.36" - process $proc$libresoc.v:154575$8924 + attribute \src "libresoc.v:158217.14-158217.38" + process $proc$libresoc.v:158217$9357 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$8925 1'0 + assign $0\sr_op__insn$18[31:0]$9358 0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8925 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9358 end - attribute \src "libresoc.v:154584.7-154584.33" - process $proc$libresoc.v:154584$8926 + attribute \src "libresoc.v:158374.13-158374.41" + process $proc$libresoc.v:158374$9359 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$8927 1'0 + assign $0\sr_op__insn_type$2[6:0]$9360 7'0000000 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8927 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9360 end - attribute \src "libresoc.v:154597.13-154597.29" - process $proc$libresoc.v:154597$8928 + attribute \src "libresoc.v:158457.7-158457.35" + process $proc$libresoc.v:158457$9361 assign { } { } - assign $0\cr_a$22[3:0]$8929 4'0000 + assign $0\sr_op__invert_in$11[0:0]$9362 1'0 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$8929 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9362 end - attribute \src "libresoc.v:154606.7-154606.26" - process $proc$libresoc.v:154606$8930 + attribute \src "libresoc.v:158466.7-158466.34" + process $proc$libresoc.v:158466$9363 assign { } { } - assign $0\cr_a_ok$23[0:0]$8931 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9364 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8931 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9364 end - attribute \src "libresoc.v:154617.13-154617.29" - process $proc$libresoc.v:154617$8932 + attribute \src "libresoc.v:158475.7-158475.35" + process $proc$libresoc.v:158475$9365 assign { } { } - assign $0\muxid$1[1:0]$8933 2'00 + assign $0\sr_op__is_signed$17[0:0]$9366 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8933 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9366 end - attribute \src "libresoc.v:154632.14-154632.43" - process $proc$libresoc.v:154632$8934 + attribute \src "libresoc.v:158486.7-158486.31" + process $proc$libresoc.v:158486$9367 assign { } { } - assign $0\o$20[63:0]$8935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__oe__oe$8[0:0]$9368 1'0 sync always sync init - update \o$20 $0\o$20[63:0]$8935 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9368 end - attribute \src "libresoc.v:154641.7-154641.23" - process $proc$libresoc.v:154641$8936 + attribute \src "libresoc.v:158495.7-158495.31" + process $proc$libresoc.v:158495$9369 assign { } { } - assign $0\o_ok$21[0:0]$8937 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9370 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$8937 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9370 end - attribute \src "libresoc.v:154945.7-154945.20" - process $proc$libresoc.v:154945$8938 + attribute \src "libresoc.v:158502.7-158502.38" + process $proc$libresoc.v:158502$9371 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\sr_op__output_carry$13[0:0]$9372 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9372 end - attribute \src "libresoc.v:154952.13-154952.31" - process $proc$libresoc.v:154952$8939 + attribute \src "libresoc.v:158511.7-158511.35" + process $proc$libresoc.v:158511$9373 assign { } { } - assign $0\xer_ca$24[1:0]$8940 2'00 + assign $0\sr_op__output_cr$15[0:0]$9374 1'0 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$8940 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9374 end - attribute \src "libresoc.v:154961.7-154961.28" - process $proc$libresoc.v:154961$8941 + attribute \src "libresoc.v:158522.7-158522.31" + process $proc$libresoc.v:158522$9375 assign { } { } - assign $0\xer_ca_ok$25[0:0]$8942 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9376 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8942 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9376 end - attribute \src "libresoc.v:154972.13-154972.31" - process $proc$libresoc.v:154972$8943 + attribute \src "libresoc.v:158531.7-158531.31" + process $proc$libresoc.v:158531$9377 assign { } { } - assign $0\xer_ov$26[1:0]$8944 2'00 + assign $0\sr_op__rc__rc$6[0:0]$9378 1'0 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$8944 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9378 end - attribute \src "libresoc.v:154981.7-154981.28" - process $proc$libresoc.v:154981$8945 + attribute \src "libresoc.v:158538.7-158538.35" + process $proc$libresoc.v:158538$9379 assign { } { } - assign $0\xer_ov_ok$27[0:0]$8946 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9380 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8946 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9380 end - attribute \src "libresoc.v:154992.7-154992.25" - process $proc$libresoc.v:154992$8947 + attribute \src "libresoc.v:158547.13-158547.31" + process $proc$libresoc.v:158547$9381 assign { } { } - assign $0\xer_so$28[0:0]$8948 1'0 + assign $0\xer_ca$23[1:0]$9382 2'00 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$8948 + update \xer_ca$23 $0\xer_ca$23[1:0]$9382 end - attribute \src "libresoc.v:155001.7-155001.28" - process $proc$libresoc.v:155001$8949 + attribute \src "libresoc.v:158556.7-158556.28" + process $proc$libresoc.v:158556$9383 assign { } { } - assign $0\xer_so_ok$29[0:0]$8950 1'0 + assign $0\xer_ca_ok$24[0:0]$9384 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8950 - end - attribute \src "libresoc.v:155009.3-155010.37" - process $proc$libresoc.v:155009$8752 - assign { } { } - assign $0\xer_so$28[0:0]$8753 \xer_so$28$next - sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$8753 - end - attribute \src "libresoc.v:155011.3-155012.43" - process $proc$libresoc.v:155011$8754 - assign { } { } - assign $0\xer_so_ok$29[0:0]$8755 \xer_so_ok$29$next - sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8755 - end - attribute \src "libresoc.v:155013.3-155014.37" - process $proc$libresoc.v:155013$8756 - assign { } { } - assign $0\xer_ov$26[1:0]$8757 \xer_ov$26$next - sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$8757 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9384 end - attribute \src "libresoc.v:155015.3-155016.43" - process $proc$libresoc.v:155015$8758 + attribute \src "libresoc.v:158570.3-158571.37" + process $proc$libresoc.v:158570$9220 assign { } { } - assign $0\xer_ov_ok$27[0:0]$8759 \xer_ov_ok$27$next + assign $0\xer_ca$23[1:0]$9221 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8759 + update \xer_ca$23 $0\xer_ca$23[1:0]$9221 end - attribute \src "libresoc.v:155017.3-155018.37" - process $proc$libresoc.v:155017$8760 + attribute \src "libresoc.v:158572.3-158573.43" + process $proc$libresoc.v:158572$9222 assign { } { } - assign $0\xer_ca$24[1:0]$8761 \xer_ca$24$next + assign $0\xer_ca_ok$24[0:0]$9223 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$8761 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9223 end - attribute \src "libresoc.v:155019.3-155020.43" - process $proc$libresoc.v:155019$8762 + attribute \src "libresoc.v:158574.3-158575.33" + process $proc$libresoc.v:158574$9224 assign { } { } - assign $0\xer_ca_ok$25[0:0]$8763 \xer_ca_ok$25$next + assign $0\cr_a$21[3:0]$9225 \cr_a$21$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8763 + update \cr_a$21 $0\cr_a$21[3:0]$9225 end - attribute \src "libresoc.v:155021.3-155022.33" - process $proc$libresoc.v:155021$8764 + attribute \src "libresoc.v:158576.3-158577.39" + process $proc$libresoc.v:158576$9226 assign { } { } - assign $0\cr_a$22[3:0]$8765 \cr_a$22$next + assign $0\cr_a_ok$22[0:0]$9227 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$8765 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9227 end - attribute \src "libresoc.v:155023.3-155024.39" - process $proc$libresoc.v:155023$8766 + attribute \src "libresoc.v:158578.3-158579.27" + process $proc$libresoc.v:158578$9228 assign { } { } - assign $0\cr_a_ok$23[0:0]$8767 \cr_a_ok$23$next + assign $0\o$19[63:0]$9229 \o$19$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8767 + update \o$19 $0\o$19[63:0]$9229 end - attribute \src "libresoc.v:155025.3-155026.27" - process $proc$libresoc.v:155025$8768 + attribute \src "libresoc.v:158580.3-158581.33" + process $proc$libresoc.v:158580$9230 assign { } { } - assign $0\o$20[63:0]$8769 \o$20$next + assign $0\o_ok$20[0:0]$9231 \o_ok$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$8769 + update \o_ok$20 $0\o_ok$20[0:0]$9231 end - attribute \src "libresoc.v:155027.3-155028.33" - process $proc$libresoc.v:155027$8770 + attribute \src "libresoc.v:158582.3-158583.55" + process $proc$libresoc.v:158582$9232 assign { } { } - assign $0\o_ok$21[0:0]$8771 \o_ok$21$next + assign $0\sr_op__insn_type$2[6:0]$9233 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$8771 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9233 end - attribute \src "libresoc.v:155029.3-155030.57" - process $proc$libresoc.v:155029$8772 + attribute \src "libresoc.v:158584.3-158585.51" + process $proc$libresoc.v:158584$9234 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$8773 \alu_op__insn_type$2$next + assign $0\sr_op__fn_unit$3[11:0]$9235 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8773 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9235 end - attribute \src "libresoc.v:155031.3-155032.53" - process $proc$libresoc.v:155031$8774 + attribute \src "libresoc.v:158586.3-158587.65" + process $proc$libresoc.v:158586$9236 assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$8775 \alu_op__fn_unit$3$next + assign $0\sr_op__imm_data__data$4[63:0]$9237 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8775 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9237 end - attribute \src "libresoc.v:155033.3-155034.67" - process $proc$libresoc.v:155033$8776 + attribute \src "libresoc.v:158588.3-158589.61" + process $proc$libresoc.v:158588$9238 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$8777 \alu_op__imm_data__data$4$next + assign $0\sr_op__imm_data__ok$5[0:0]$9239 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8777 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9239 end - attribute \src "libresoc.v:155035.3-155036.63" - process $proc$libresoc.v:155035$8778 + attribute \src "libresoc.v:158590.3-158591.49" + process $proc$libresoc.v:158590$9240 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$8779 \alu_op__imm_data__ok$5$next + assign $0\sr_op__rc__rc$6[0:0]$9241 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8779 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9241 end - attribute \src "libresoc.v:155037.3-155038.51" - process $proc$libresoc.v:155037$8780 + attribute \src "libresoc.v:158592.3-158593.49" + process $proc$libresoc.v:158592$9242 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$8781 \alu_op__rc__rc$6$next + assign $0\sr_op__rc__ok$7[0:0]$9243 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8781 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9243 end - attribute \src "libresoc.v:155039.3-155040.51" - process $proc$libresoc.v:155039$8782 + attribute \src "libresoc.v:158594.3-158595.49" + process $proc$libresoc.v:158594$9244 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$8783 \alu_op__rc__ok$7$next + assign $0\sr_op__oe__oe$8[0:0]$9245 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8783 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9245 end - attribute \src "libresoc.v:155041.3-155042.51" - process $proc$libresoc.v:155041$8784 + attribute \src "libresoc.v:158596.3-158597.49" + process $proc$libresoc.v:158596$9246 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$8785 \alu_op__oe__oe$8$next + assign $0\sr_op__oe__ok$9[0:0]$9247 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8785 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9247 end - attribute \src "libresoc.v:155043.3-155044.51" - process $proc$libresoc.v:155043$8786 + attribute \src "libresoc.v:158598.3-158599.57" + process $proc$libresoc.v:158598$9248 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$8787 \alu_op__oe__ok$9$next + assign $0\sr_op__write_cr0$10[0:0]$9249 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8787 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9249 end - attribute \src "libresoc.v:155045.3-155046.59" - process $proc$libresoc.v:155045$8788 + attribute \src "libresoc.v:158600.3-158601.57" + process $proc$libresoc.v:158600$9250 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$8789 \alu_op__invert_in$10$next + assign $0\sr_op__invert_in$11[0:0]$9251 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8789 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9251 end - attribute \src "libresoc.v:155047.3-155048.53" - process $proc$libresoc.v:155047$8790 + attribute \src "libresoc.v:158602.3-158603.61" + process $proc$libresoc.v:158602$9252 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$8791 \alu_op__zero_a$11$next + assign $0\sr_op__input_carry$12[1:0]$9253 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8791 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9253 end - attribute \src "libresoc.v:155049.3-155050.61" - process $proc$libresoc.v:155049$8792 + attribute \src "libresoc.v:158604.3-158605.63" + process $proc$libresoc.v:158604$9254 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$8793 \alu_op__invert_out$12$next + assign $0\sr_op__output_carry$13[0:0]$9255 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8793 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9255 end - attribute \src "libresoc.v:155051.3-155052.59" - process $proc$libresoc.v:155051$8794 + attribute \src "libresoc.v:158606.3-158607.55" + process $proc$libresoc.v:158606$9256 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$8795 \alu_op__write_cr0$13$next + assign $0\sr_op__input_cr$14[0:0]$9257 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8795 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9257 end - attribute \src "libresoc.v:155053.3-155054.63" - process $proc$libresoc.v:155053$8796 + attribute \src "libresoc.v:158608.3-158609.57" + process $proc$libresoc.v:158608$9258 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$8797 \alu_op__input_carry$14$next + assign $0\sr_op__output_cr$15[0:0]$9259 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8797 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9259 end - attribute \src "libresoc.v:155055.3-155056.65" - process $proc$libresoc.v:155055$8798 + attribute \src "libresoc.v:158610.3-158611.55" + process $proc$libresoc.v:158610$9260 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$8799 \alu_op__output_carry$15$next + assign $0\sr_op__is_32bit$16[0:0]$9261 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8799 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9261 end - attribute \src "libresoc.v:155057.3-155058.57" - process $proc$libresoc.v:155057$8800 + attribute \src "libresoc.v:158612.3-158613.57" + process $proc$libresoc.v:158612$9262 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$8801 \alu_op__is_32bit$16$next + assign $0\sr_op__is_signed$17[0:0]$9263 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8801 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9263 end - attribute \src "libresoc.v:155059.3-155060.59" - process $proc$libresoc.v:155059$8802 + attribute \src "libresoc.v:158614.3-158615.47" + process $proc$libresoc.v:158614$9264 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$8803 \alu_op__is_signed$17$next + assign $0\sr_op__insn$18[31:0]$9265 \sr_op__insn$18$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8803 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9265 end - attribute \src "libresoc.v:155061.3-155062.57" - process $proc$libresoc.v:155061$8804 + attribute \src "libresoc.v:158616.3-158617.33" + process $proc$libresoc.v:158616$9266 assign { } { } - assign $0\alu_op__data_len$18[3:0]$8805 \alu_op__data_len$18$next + assign $0\muxid$1[1:0]$9267 \muxid$1$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8805 + update \muxid$1 $0\muxid$1[1:0]$9267 end - attribute \src "libresoc.v:155063.3-155064.49" - process $proc$libresoc.v:155063$8806 - assign { } { } - assign $0\alu_op__insn$19[31:0]$8807 \alu_op__insn$19$next - sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8807 - end - attribute \src "libresoc.v:155065.3-155066.33" - process $proc$libresoc.v:155065$8808 - assign { } { } - assign $0\muxid$1[1:0]$8809 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8809 - end - attribute \src "libresoc.v:155067.3-155068.29" - process $proc$libresoc.v:155067$8810 + attribute \src "libresoc.v:158618.3-158619.29" + process $proc$libresoc.v:158618$9268 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155133.3-155150.6" - process $proc$libresoc.v:155133$8811 + attribute \src "libresoc.v:158677.3-158694.6" + process $proc$libresoc.v:158677$9269 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8812 $2\r_busy$next[0:0]$8814 - attribute \src "libresoc.v:155134.5-155134.29" + assign $0\r_busy$next[0:0]$9270 $2\r_busy$next[0:0]$9272 + attribute \src "libresoc.v:158678.5-158678.29" switch \initial - attribute \src "libresoc.v:155134.9-155134.17" + attribute \src "libresoc.v:158678.9-158678.17" case 1'1 case end @@ -319086,34 +327268,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8813 1'1 + assign $1\r_busy$next[0:0]$9271 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8813 1'0 + assign $1\r_busy$next[0:0]$9271 1'0 case - assign $1\r_busy$next[0:0]$8813 \r_busy + assign $1\r_busy$next[0:0]$9271 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8814 1'0 + assign $2\r_busy$next[0:0]$9272 1'0 case - assign $2\r_busy$next[0:0]$8814 $1\r_busy$next[0:0]$8813 + assign $2\r_busy$next[0:0]$9272 $1\r_busy$next[0:0]$9271 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8812 + update \r_busy$next $0\r_busy$next[0:0]$9270 end - attribute \src "libresoc.v:155151.3-155163.6" - process $proc$libresoc.v:155151$8815 + attribute \src "libresoc.v:158695.3-158707.6" + process $proc$libresoc.v:158695$9273 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8816 $1\muxid$1$next[1:0]$8817 - attribute \src "libresoc.v:155152.5-155152.29" + assign $0\muxid$1$next[1:0]$9274 $1\muxid$1$next[1:0]$9275 + attribute \src "libresoc.v:158696.5-158696.29" switch \initial - attribute \src "libresoc.v:155152.9-155152.17" + attribute \src "libresoc.v:158696.9-158696.17" case 1'1 case end @@ -319122,21 +327304,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8817 \muxid$62 + assign $1\muxid$1$next[1:0]$9275 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8817 \muxid$62 + assign $1\muxid$1$next[1:0]$9275 \muxid$53 case - assign $1\muxid$1$next[1:0]$8817 \muxid$1 + assign $1\muxid$1$next[1:0]$9275 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8816 + update \muxid$1$next $0\muxid$1$next[1:0]$9274 end - attribute \src "libresoc.v:155164.3-155205.6" - process $proc$libresoc.v:155164$8818 - assign { } { } - assign { } { } + attribute \src "libresoc.v:158708.3-158748.6" + process $proc$libresoc.v:158708$9276 assign { } { } assign { } { } assign { } { } @@ -319171,33 +327351,32 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$8819 $1\alu_op__data_len$18$next[3:0]$8837 - assign $0\alu_op__fn_unit$3$next[11:0]$8820 $1\alu_op__fn_unit$3$next[11:0]$8838 + assign $0\sr_op__fn_unit$3$next[11:0]$9277 $1\sr_op__fn_unit$3$next[11:0]$9294 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$8823 $1\alu_op__input_carry$14$next[1:0]$8841 - assign $0\alu_op__insn$19$next[31:0]$8824 $1\alu_op__insn$19$next[31:0]$8842 - assign $0\alu_op__insn_type$2$next[6:0]$8825 $1\alu_op__insn_type$2$next[6:0]$8843 - assign $0\alu_op__invert_in$10$next[0:0]$8826 $1\alu_op__invert_in$10$next[0:0]$8844 - assign $0\alu_op__invert_out$12$next[0:0]$8827 $1\alu_op__invert_out$12$next[0:0]$8845 - assign $0\alu_op__is_32bit$16$next[0:0]$8828 $1\alu_op__is_32bit$16$next[0:0]$8846 - assign $0\alu_op__is_signed$17$next[0:0]$8829 $1\alu_op__is_signed$17$next[0:0]$8847 + assign $0\sr_op__input_carry$12$next[1:0]$9280 $1\sr_op__input_carry$12$next[1:0]$9297 + assign $0\sr_op__input_cr$14$next[0:0]$9281 $1\sr_op__input_cr$14$next[0:0]$9298 + assign $0\sr_op__insn$18$next[31:0]$9282 $1\sr_op__insn$18$next[31:0]$9299 + assign $0\sr_op__insn_type$2$next[6:0]$9283 $1\sr_op__insn_type$2$next[6:0]$9300 + assign $0\sr_op__invert_in$11$next[0:0]$9284 $1\sr_op__invert_in$11$next[0:0]$9301 + assign $0\sr_op__is_32bit$16$next[0:0]$9285 $1\sr_op__is_32bit$16$next[0:0]$9302 + assign $0\sr_op__is_signed$17$next[0:0]$9286 $1\sr_op__is_signed$17$next[0:0]$9303 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$8832 $1\alu_op__output_carry$15$next[0:0]$8850 + assign $0\sr_op__output_carry$13$next[0:0]$9289 $1\sr_op__output_carry$13$next[0:0]$9306 + assign $0\sr_op__output_cr$15$next[0:0]$9290 $1\sr_op__output_cr$15$next[0:0]$9307 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$8835 $1\alu_op__write_cr0$13$next[0:0]$8853 - assign $0\alu_op__zero_a$11$next[0:0]$8836 $1\alu_op__zero_a$11$next[0:0]$8854 - assign $0\alu_op__imm_data__data$4$next[63:0]$8821 $2\alu_op__imm_data__data$4$next[63:0]$8855 - assign $0\alu_op__imm_data__ok$5$next[0:0]$8822 $2\alu_op__imm_data__ok$5$next[0:0]$8856 - assign $0\alu_op__oe__oe$8$next[0:0]$8830 $2\alu_op__oe__oe$8$next[0:0]$8857 - assign $0\alu_op__oe__ok$9$next[0:0]$8831 $2\alu_op__oe__ok$9$next[0:0]$8858 - assign $0\alu_op__rc__ok$7$next[0:0]$8833 $2\alu_op__rc__ok$7$next[0:0]$8859 - assign $0\alu_op__rc__rc$6$next[0:0]$8834 $2\alu_op__rc__rc$6$next[0:0]$8860 - attribute \src "libresoc.v:155165.5-155165.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9293 $1\sr_op__write_cr0$10$next[0:0]$9310 + assign $0\sr_op__imm_data__data$4$next[63:0]$9278 $2\sr_op__imm_data__data$4$next[63:0]$9311 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9279 $2\sr_op__imm_data__ok$5$next[0:0]$9312 + assign $0\sr_op__oe__oe$8$next[0:0]$9287 $2\sr_op__oe__oe$8$next[0:0]$9313 + assign $0\sr_op__oe__ok$9$next[0:0]$9288 $2\sr_op__oe__ok$9$next[0:0]$9314 + assign $0\sr_op__rc__ok$7$next[0:0]$9291 $2\sr_op__rc__ok$7$next[0:0]$9315 + assign $0\sr_op__rc__rc$6$next[0:0]$9292 $2\sr_op__rc__rc$6$next[0:0]$9316 + attribute \src "libresoc.v:158709.5-158709.29" switch \initial - attribute \src "libresoc.v:155165.9-155165.17" + attribute \src "libresoc.v:158709.9-158709.17" case 1'1 case end @@ -319222,8 +327401,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$8842 $1\alu_op__data_len$18$next[3:0]$8837 $1\alu_op__is_signed$17$next[0:0]$8847 $1\alu_op__is_32bit$16$next[0:0]$8846 $1\alu_op__output_carry$15$next[0:0]$8850 $1\alu_op__input_carry$14$next[1:0]$8841 $1\alu_op__write_cr0$13$next[0:0]$8853 $1\alu_op__invert_out$12$next[0:0]$8845 $1\alu_op__zero_a$11$next[0:0]$8854 $1\alu_op__invert_in$10$next[0:0]$8844 $1\alu_op__oe__ok$9$next[0:0]$8849 $1\alu_op__oe__oe$8$next[0:0]$8848 $1\alu_op__rc__ok$7$next[0:0]$8851 $1\alu_op__rc__rc$6$next[0:0]$8852 $1\alu_op__imm_data__ok$5$next[0:0]$8840 $1\alu_op__imm_data__data$4$next[63:0]$8839 $1\alu_op__fn_unit$3$next[11:0]$8838 $1\alu_op__insn_type$2$next[6:0]$8843 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\sr_op__insn$18$next[31:0]$9299 $1\sr_op__is_signed$17$next[0:0]$9303 $1\sr_op__is_32bit$16$next[0:0]$9302 $1\sr_op__output_cr$15$next[0:0]$9307 $1\sr_op__input_cr$14$next[0:0]$9298 $1\sr_op__output_carry$13$next[0:0]$9306 $1\sr_op__input_carry$12$next[1:0]$9297 $1\sr_op__invert_in$11$next[0:0]$9301 $1\sr_op__write_cr0$10$next[0:0]$9310 $1\sr_op__oe__ok$9$next[0:0]$9305 $1\sr_op__oe__oe$8$next[0:0]$9304 $1\sr_op__rc__ok$7$next[0:0]$9308 $1\sr_op__rc__rc$6$next[0:0]$9309 $1\sr_op__imm_data__ok$5$next[0:0]$9296 $1\sr_op__imm_data__data$4$next[63:0]$9295 $1\sr_op__fn_unit$3$next[11:0]$9294 $1\sr_op__insn_type$2$next[6:0]$9300 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -319243,172 +327421,81 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$8842 $1\alu_op__data_len$18$next[3:0]$8837 $1\alu_op__is_signed$17$next[0:0]$8847 $1\alu_op__is_32bit$16$next[0:0]$8846 $1\alu_op__output_carry$15$next[0:0]$8850 $1\alu_op__input_carry$14$next[1:0]$8841 $1\alu_op__write_cr0$13$next[0:0]$8853 $1\alu_op__invert_out$12$next[0:0]$8845 $1\alu_op__zero_a$11$next[0:0]$8854 $1\alu_op__invert_in$10$next[0:0]$8844 $1\alu_op__oe__ok$9$next[0:0]$8849 $1\alu_op__oe__oe$8$next[0:0]$8848 $1\alu_op__rc__ok$7$next[0:0]$8851 $1\alu_op__rc__rc$6$next[0:0]$8852 $1\alu_op__imm_data__ok$5$next[0:0]$8840 $1\alu_op__imm_data__data$4$next[63:0]$8839 $1\alu_op__fn_unit$3$next[11:0]$8838 $1\alu_op__insn_type$2$next[6:0]$8843 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - case - assign $1\alu_op__data_len$18$next[3:0]$8837 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[11:0]$8838 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$8839 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$8840 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$8841 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$8842 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$8843 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$8844 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$8845 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$8846 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$8847 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$8848 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$8849 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$8850 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$8851 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$8852 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$8853 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$8854 \alu_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$8855 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$8856 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$8860 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$8859 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$8857 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$8858 1'0 - case - assign $2\alu_op__imm_data__data$4$next[63:0]$8855 $1\alu_op__imm_data__data$4$next[63:0]$8839 - assign $2\alu_op__imm_data__ok$5$next[0:0]$8856 $1\alu_op__imm_data__ok$5$next[0:0]$8840 - assign $2\alu_op__oe__oe$8$next[0:0]$8857 $1\alu_op__oe__oe$8$next[0:0]$8848 - assign $2\alu_op__oe__ok$9$next[0:0]$8858 $1\alu_op__oe__ok$9$next[0:0]$8849 - assign $2\alu_op__rc__ok$7$next[0:0]$8859 $1\alu_op__rc__ok$7$next[0:0]$8851 - assign $2\alu_op__rc__rc$6$next[0:0]$8860 $1\alu_op__rc__rc$6$next[0:0]$8852 - end - sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$8819 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$8820 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$8821 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$8822 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$8823 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$8824 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$8825 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$8826 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$8827 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$8828 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$8829 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$8830 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$8831 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$8832 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$8833 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$8834 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$8835 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$8836 - end - attribute \src "libresoc.v:155206.3-155224.6" - process $proc$libresoc.v:155206$8861 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$8862 $1\o$20$next[63:0]$8864 - assign { } { } - assign $0\o_ok$21$next[0:0]$8863 $2\o_ok$21$next[0:0]$8866 - attribute \src "libresoc.v:155207.5-155207.29" - switch \initial - attribute \src "libresoc.v:155207.9-155207.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$8865 $1\o$20$next[63:0]$8864 } { \o_ok$82 \o$81 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$8865 $1\o$20$next[63:0]$8864 } { \o_ok$82 \o$81 } + assign { $1\sr_op__insn$18$next[31:0]$9299 $1\sr_op__is_signed$17$next[0:0]$9303 $1\sr_op__is_32bit$16$next[0:0]$9302 $1\sr_op__output_cr$15$next[0:0]$9307 $1\sr_op__input_cr$14$next[0:0]$9298 $1\sr_op__output_carry$13$next[0:0]$9306 $1\sr_op__input_carry$12$next[1:0]$9297 $1\sr_op__invert_in$11$next[0:0]$9301 $1\sr_op__write_cr0$10$next[0:0]$9310 $1\sr_op__oe__ok$9$next[0:0]$9305 $1\sr_op__oe__oe$8$next[0:0]$9304 $1\sr_op__rc__ok$7$next[0:0]$9308 $1\sr_op__rc__rc$6$next[0:0]$9309 $1\sr_op__imm_data__ok$5$next[0:0]$9296 $1\sr_op__imm_data__data$4$next[63:0]$9295 $1\sr_op__fn_unit$3$next[11:0]$9294 $1\sr_op__insn_type$2$next[6:0]$9300 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\o$20$next[63:0]$8864 \o$20 - assign $1\o_ok$21$next[0:0]$8865 \o_ok$21 + assign $1\sr_op__fn_unit$3$next[11:0]$9294 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9295 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9296 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9297 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9298 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9299 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9300 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9301 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9302 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9303 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9304 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9305 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9306 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9307 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9308 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9309 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9310 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$8866 1'0 - case - assign $2\o_ok$21$next[0:0]$8866 $1\o_ok$21$next[0:0]$8865 - end - sync always - update \o$20$next $0\o$20$next[63:0]$8862 - update \o_ok$21$next $0\o_ok$21$next[0:0]$8863 - end - attribute \src "libresoc.v:155225.3-155243.6" - process $proc$libresoc.v:155225$8867 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$8868 $1\cr_a$22$next[3:0]$8870 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$8869 $2\cr_a_ok$23$next[0:0]$8872 - attribute \src "libresoc.v:155226.5-155226.29" - switch \initial - attribute \src "libresoc.v:155226.9-155226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$8871 $1\cr_a$22$next[3:0]$8870 } { \cr_a_ok$84 \cr_a$83 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$8871 $1\cr_a$22$next[3:0]$8870 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$22$next[3:0]$8870 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$8871 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$8872 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9311 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9312 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9316 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9315 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9313 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9314 1'0 case - assign $2\cr_a_ok$23$next[0:0]$8872 $1\cr_a_ok$23$next[0:0]$8871 + assign $2\sr_op__imm_data__data$4$next[63:0]$9311 $1\sr_op__imm_data__data$4$next[63:0]$9295 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9312 $1\sr_op__imm_data__ok$5$next[0:0]$9296 + assign $2\sr_op__oe__oe$8$next[0:0]$9313 $1\sr_op__oe__oe$8$next[0:0]$9304 + assign $2\sr_op__oe__ok$9$next[0:0]$9314 $1\sr_op__oe__ok$9$next[0:0]$9305 + assign $2\sr_op__rc__ok$7$next[0:0]$9315 $1\sr_op__rc__ok$7$next[0:0]$9308 + assign $2\sr_op__rc__rc$6$next[0:0]$9316 $1\sr_op__rc__rc$6$next[0:0]$9309 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$8868 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$8869 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9277 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9278 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9279 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9280 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9281 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9282 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9283 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9284 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9285 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9286 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9287 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9288 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9289 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9290 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9291 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9292 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9293 end - attribute \src "libresoc.v:155244.3-155262.6" - process $proc$libresoc.v:155244$8873 + attribute \src "libresoc.v:158749.3-158767.6" + process $proc$libresoc.v:158749$9317 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$8874 $1\xer_ca$24$next[1:0]$8876 + assign $0\o$19$next[63:0]$9318 $1\o$19$next[63:0]$9320 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$8875 $2\xer_ca_ok$25$next[0:0]$8878 - attribute \src "libresoc.v:155245.5-155245.29" + assign $0\o_ok$20$next[0:0]$9319 $2\o_ok$20$next[0:0]$9322 + attribute \src "libresoc.v:158750.5-158750.29" switch \initial - attribute \src "libresoc.v:155245.9-155245.17" + attribute \src "libresoc.v:158750.9-158750.17" case 1'1 case end @@ -319418,41 +327505,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$8877 $1\xer_ca$24$next[1:0]$8876 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$20$next[0:0]$9321 $1\o$19$next[63:0]$9320 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$8877 $1\xer_ca$24$next[1:0]$8876 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$20$next[0:0]$9321 $1\o$19$next[63:0]$9320 } { \o_ok$72 \o$71 } case - assign $1\xer_ca$24$next[1:0]$8876 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$8877 \xer_ca_ok$25 + assign $1\o$19$next[63:0]$9320 \o$19 + assign $1\o_ok$20$next[0:0]$9321 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$8878 1'0 + assign $2\o_ok$20$next[0:0]$9322 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$8878 $1\xer_ca_ok$25$next[0:0]$8877 + assign $2\o_ok$20$next[0:0]$9322 $1\o_ok$20$next[0:0]$9321 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$8874 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$8875 + update \o$19$next $0\o$19$next[63:0]$9318 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9319 end - attribute \src "libresoc.v:155263.3-155281.6" - process $proc$libresoc.v:155263$8879 + attribute \src "libresoc.v:158768.3-158786.6" + process $proc$libresoc.v:158768$9323 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$8880 $1\xer_ov$26$next[1:0]$8882 + assign $0\cr_a$21$next[3:0]$9324 $1\cr_a$21$next[3:0]$9326 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$8881 $2\xer_ov_ok$27$next[0:0]$8884 - attribute \src "libresoc.v:155264.5-155264.29" + assign $0\cr_a_ok$22$next[0:0]$9325 $2\cr_a_ok$22$next[0:0]$9328 + attribute \src "libresoc.v:158769.5-158769.29" switch \initial - attribute \src "libresoc.v:155264.9-155264.17" + attribute \src "libresoc.v:158769.9-158769.17" case 1'1 case end @@ -319462,41 +327549,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$8883 $1\xer_ov$26$next[1:0]$8882 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$22$next[0:0]$9327 $1\cr_a$21$next[3:0]$9326 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$8883 $1\xer_ov$26$next[1:0]$8882 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$22$next[0:0]$9327 $1\cr_a$21$next[3:0]$9326 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\xer_ov$26$next[1:0]$8882 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$8883 \xer_ov_ok$27 + assign $1\cr_a$21$next[3:0]$9326 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9327 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$8884 1'0 + assign $2\cr_a_ok$22$next[0:0]$9328 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$8884 $1\xer_ov_ok$27$next[0:0]$8883 + assign $2\cr_a_ok$22$next[0:0]$9328 $1\cr_a_ok$22$next[0:0]$9327 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$8880 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$8881 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9324 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9325 end - attribute \src "libresoc.v:155282.3-155300.6" - process $proc$libresoc.v:155282$8885 + attribute \src "libresoc.v:158787.3-158805.6" + process $proc$libresoc.v:158787$9329 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$8886 $1\xer_so$28$next[0:0]$8888 + assign $0\xer_ca$23$next[1:0]$9330 $1\xer_ca$23$next[1:0]$9332 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$8887 $2\xer_so_ok$29$next[0:0]$8890 - attribute \src "libresoc.v:155283.5-155283.29" + assign $0\xer_ca_ok$24$next[0:0]$9331 $2\xer_ca_ok$24$next[0:0]$9334 + attribute \src "libresoc.v:158788.5-158788.29" switch \initial - attribute \src "libresoc.v:155283.9-155283.17" + attribute \src "libresoc.v:158788.9-158788.17" case 1'1 case end @@ -319506,345 +327593,308 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$8889 $1\xer_so$28$next[0:0]$8888 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_ca_ok$24$next[0:0]$9333 $1\xer_ca$23$next[1:0]$9332 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$8889 $1\xer_so$28$next[0:0]$8888 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_ca_ok$24$next[0:0]$9333 $1\xer_ca$23$next[1:0]$9332 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_so$28$next[0:0]$8888 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$8889 \xer_so_ok$29 + assign $1\xer_ca$23$next[1:0]$9332 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9333 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$8890 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9334 1'0 case - assign $2\xer_so_ok$29$next[0:0]$8890 $1\xer_so_ok$29$next[0:0]$8889 + assign $2\xer_ca_ok$24$next[0:0]$9334 $1\xer_ca_ok$24$next[0:0]$9333 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$8886 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$8887 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9330 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9331 end - connect \$60 $and$libresoc.v:155008$8751_Y + connect \$51 $and$libresoc.v:158569$9219_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - connect \muxid$62 \output_muxid$30 - connect \p_valid_i_p_ready_o \$60 + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$59 \p_valid_i - connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:155324.1-156360.10" +attribute \src "libresoc.v:158826.1-159775.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" -module \pipe2$112 - attribute \src "libresoc.v:156306.3-156324.6" - wire width 4 $0\cr_a$20$next[3:0]$9052 - attribute \src "libresoc.v:156117.3-156118.33" - wire width 4 $0\cr_a$20[3:0]$8957 - attribute \src "libresoc.v:155336.13-155336.29" - wire width 4 $0\cr_a$20[3:0]$9065 - attribute \src "libresoc.v:156306.3-156324.6" - wire $0\cr_a_ok$21$next[0:0]$9053 - attribute \src "libresoc.v:156119.3-156120.39" - wire $0\cr_a_ok$21[0:0]$8959 - attribute \src "libresoc.v:155345.7-155345.26" - wire $0\cr_a_ok$21[0:0]$9067 - attribute \src "libresoc.v:155325.7-155325.20" +module \pipe2$35 + attribute \src "libresoc.v:159681.3-159699.6" + wire width 64 $0\fast1$11$next[63:0]$9453 + attribute \src "libresoc.v:159536.3-159537.35" + wire width 64 $0\fast1$11[63:0]$9394 + attribute \src "libresoc.v:158838.14-158838.47" + wire width 64 $0\fast1$11[63:0]$9477 + attribute \src "libresoc.v:159681.3-159699.6" + wire $0\fast1_ok$next[0:0]$9452 + attribute \src "libresoc.v:159538.3-159539.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:159700.3-159718.6" + wire width 64 $0\fast2$12$next[63:0]$9459 + attribute \src "libresoc.v:159532.3-159533.35" + wire width 64 $0\fast2$12[63:0]$9391 + attribute \src "libresoc.v:158854.14-158854.47" + wire width 64 $0\fast2$12[63:0]$9480 + attribute \src "libresoc.v:159700.3-159718.6" + wire $0\fast2_ok$next[0:0]$9458 + attribute \src "libresoc.v:159534.3-159535.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:158827.7-158827.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156234.3-156246.6" - wire width 2 $0\muxid$1$next[1:0]$9004 - attribute \src "libresoc.v:156157.3-156158.33" - wire width 2 $0\muxid$1[1:0]$8997 - attribute \src "libresoc.v:155356.13-155356.29" - wire width 2 $0\muxid$1[1:0]$9069 - attribute \src "libresoc.v:156287.3-156305.6" - wire width 64 $0\o$18$next[63:0]$9046 - attribute \src "libresoc.v:156121.3-156122.27" - wire width 64 $0\o$18[63:0]$8961 - attribute \src "libresoc.v:155371.14-155371.43" - wire width 64 $0\o$18[63:0]$9071 - attribute \src "libresoc.v:156287.3-156305.6" - wire $0\o_ok$19$next[0:0]$9047 - attribute \src "libresoc.v:156123.3-156124.33" - wire $0\o_ok$19[0:0]$8963 - attribute \src "libresoc.v:155380.7-155380.23" - wire $0\o_ok$19[0:0]$9073 - attribute \src "libresoc.v:156216.3-156233.6" - wire $0\r_busy$next[0:0]$9000 - attribute \src "libresoc.v:156159.3-156160.29" + attribute \src "libresoc.v:159738.3-159756.6" + wire width 64 $0\msr$next[63:0]$9470 + attribute \src "libresoc.v:159524.3-159525.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:159738.3-159756.6" + wire $0\msr_ok$next[0:0]$9471 + attribute \src "libresoc.v:159526.3-159527.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:159628.3-159640.6" + wire width 2 $0\muxid$1$next[1:0]$9424 + attribute \src "libresoc.v:159562.3-159563.33" + wire width 2 $0\muxid$1[1:0]$9417 + attribute \src "libresoc.v:159126.13-159126.29" + wire width 2 $0\muxid$1[1:0]$9485 + attribute \src "libresoc.v:159719.3-159737.6" + wire width 64 $0\nia$next[63:0]$9464 + attribute \src "libresoc.v:159528.3-159529.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:159719.3-159737.6" + wire $0\nia_ok$next[0:0]$9465 + attribute \src "libresoc.v:159530.3-159531.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:159662.3-159680.6" + wire width 64 $0\o$next[63:0]$9446 + attribute \src "libresoc.v:159540.3-159541.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:159662.3-159680.6" + wire $0\o_ok$next[0:0]$9447 + attribute \src "libresoc.v:159542.3-159543.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:159610.3-159627.6" + wire $0\r_busy$next[0:0]$9420 + attribute \src "libresoc.v:159564.3-159565.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156247.3-156286.6" - wire width 12 $0\sr_op__fn_unit$3$next[11:0]$9007 - attribute \src "libresoc.v:156127.3-156128.51" - wire width 12 $0\sr_op__fn_unit$3[11:0]$8967 - attribute \src "libresoc.v:155699.14-155699.42" - wire width 12 $0\sr_op__fn_unit$3[11:0]$9076 - attribute \src "libresoc.v:156247.3-156286.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9008 - attribute \src "libresoc.v:156129.3-156130.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$8969 - attribute \src "libresoc.v:155721.14-155721.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9078 - attribute \src "libresoc.v:156247.3-156286.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9009 - attribute \src "libresoc.v:156131.3-156132.61" - wire $0\sr_op__imm_data__ok$5[0:0]$8971 - attribute \src "libresoc.v:155730.7-155730.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9080 - attribute \src "libresoc.v:156247.3-156286.6" - wire width 2 $0\sr_op__input_carry$11$next[1:0]$9010 - attribute \src "libresoc.v:156143.3-156144.61" - wire width 2 $0\sr_op__input_carry$11[1:0]$8983 - attribute \src "libresoc.v:155747.13-155747.43" - wire width 2 $0\sr_op__input_carry$11[1:0]$9082 - attribute \src "libresoc.v:156247.3-156286.6" - wire $0\sr_op__input_cr$13$next[0:0]$9011 - attribute \src "libresoc.v:156147.3-156148.55" - wire $0\sr_op__input_cr$13[0:0]$8987 - attribute \src "libresoc.v:155760.7-155760.34" - wire $0\sr_op__input_cr$13[0:0]$9084 - attribute \src "libresoc.v:156247.3-156286.6" - wire width 32 $0\sr_op__insn$17$next[31:0]$9012 - attribute \src "libresoc.v:156155.3-156156.47" - wire width 32 $0\sr_op__insn$17[31:0]$8995 - attribute \src "libresoc.v:155769.14-155769.38" - wire width 32 $0\sr_op__insn$17[31:0]$9086 - attribute \src "libresoc.v:156247.3-156286.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9013 - attribute \src "libresoc.v:156125.3-156126.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$8965 - attribute \src "libresoc.v:155926.13-155926.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9088 - attribute \src "libresoc.v:156247.3-156286.6" - wire $0\sr_op__is_32bit$15$next[0:0]$9014 - attribute \src "libresoc.v:156151.3-156152.55" - wire $0\sr_op__is_32bit$15[0:0]$8991 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 34 \fast2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 35 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:158827.7-158827.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_msr_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 21 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 48 \o$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 22 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 49 \o_ok$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \o_ok$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid + wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_o_ok$42 + wire width 2 \main_muxid$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia$18 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -319859,7 +327909,7 @@ module \pipe2$112 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit + wire width 12 \main_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -319874,35 +327924,11 @@ module \pipe2$112 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr$36 + wire width 12 \main_trap_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn + wire width 32 \main_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$40 + wire width 32 \main_trap_op__insn$16 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -319978,7 +328004,7 @@ module \pipe2$112 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type + wire width 7 \main_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -320054,63 +328080,101 @@ module \pipe2$112 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok + wire width 7 \main_trap_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry + wire \main_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry$35 + wire \main_trap_op__is_32bit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr + wire width 8 \main_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr$37 + wire width 8 \main_trap_op__ldst_exc$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok + wire width 64 \main_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok$30 + wire width 64 \main_trap_op__msr$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc + wire width 13 \main_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc$29 + wire width 13 \main_trap_op__trapaddr$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0 + wire width 8 \main_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \output_xer_so + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$48 + wire \p_valid_i$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -320125,7 +328189,7 @@ module \pipe2$112 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \sr_op__fn_unit + wire width 12 input 6 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -320140,9 +328204,9 @@ module \pipe2$112 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 33 \sr_op__fn_unit$3 + wire width 12 output 22 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$3$next + wire width 12 \trap_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -320157,59 +328221,15 @@ module \pipe2$112 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 34 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$54 + wire width 12 \trap_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$55 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 14 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 41 \sr_op__input_carry$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$11$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 20 \sr_op__insn + wire width 32 input 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 47 \sr_op__insn$17 + wire width 32 \trap_op__insn$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$17$next + wire width 32 output 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$67 + wire width 32 \trap_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -320285,7 +328305,7 @@ module \pipe2$112 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \sr_op__insn_type + wire width 7 input 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -320361,9 +328381,9 @@ module \pipe2$112 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 32 \sr_op__insn_type$2 + wire width 7 output 21 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$2$next + wire width 7 \trap_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -320439,552 +328459,440 @@ module \pipe2$112 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$52 + wire width 7 \trap_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \sr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__output_carry + wire input 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \sr_op__output_carry$12 + wire \trap_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$12$next + wire output 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$62 + wire \trap_op__is_32bit$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__output_cr + wire width 8 input 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \sr_op__output_cr$14 + wire width 8 output 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$14$next + wire width 8 \trap_op__ldst_exc$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$64 + wire width 8 \trap_op__ldst_exc$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__rc__ok + wire width 64 input 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$57 + wire width 64 \trap_op__msr$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__rc__ok$7 + wire width 64 output 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$7$next + wire width 64 \trap_op__msr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__rc__rc + wire width 13 input 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$56 + wire width 13 \trap_op__trapaddr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__rc__rc$6 + wire width 13 output 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$6$next + wire width 13 \trap_op__trapaddr$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__write_cr0 + wire width 8 input 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \sr_op__write_cr0$10 + wire width 8 \trap_op__traptype$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$10$next + wire width 8 output 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 52 \xer_ca$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 53 \xer_ca_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_ca_ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 26 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \xer_so_ok$46 + wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:156112$8951 + cell $and $and$libresoc.v:159523$9385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$48 + connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:156112$8951_Y + connect \Y $and$libresoc.v:159523$9385_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156161.11-156164.4" - cell \n$114 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:159566.13-159601.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:156165.16-156211.4" - cell \output$115 \output - connect \cr_a \output_cr_a - connect \cr_a$20 \output_cr_a$43 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$24 - connect \o \output_o - connect \o$18 \output_o$41 - connect \o_ok \output_o_ok - connect \o_ok$19 \output_o_ok$42 - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$26 - connect \sr_op__imm_data__data \output_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$27 - connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$28 - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__input_carry$11 \output_sr_op__input_carry$34 - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__input_cr$13 \output_sr_op__input_cr$36 - connect \sr_op__insn \output_sr_op__insn - connect \sr_op__insn$17 \output_sr_op__insn$40 - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__insn_type$2 \output_sr_op__insn_type$25 - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_32bit$15 \output_sr_op__is_32bit$38 - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__is_signed$16 \output_sr_op__is_signed$39 - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$31 - connect \sr_op__oe__ok \output_sr_op__oe__ok - connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$32 - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__output_carry$12 \output_sr_op__output_carry$35 - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__output_cr$14 \output_sr_op__output_cr$37 - connect \sr_op__rc__ok \output_sr_op__rc__ok - connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$30 - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$29 - connect \sr_op__write_cr0 \output_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$33 - connect \xer_ca \output_xer_ca - connect \xer_ca$21 \output_xer_ca$44 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_so \output_xer_so + attribute \src "libresoc.v:159602.10-159605.4" + cell \n$37 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156212.11-156215.4" - cell \p$113 \p + attribute \src "libresoc.v:159606.10-159609.4" + cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155325.7-155325.20" - process $proc$libresoc.v:155325$9063 + attribute \src "libresoc.v:158827.7-158827.20" + process $proc$libresoc.v:158827$9475 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155336.13-155336.29" - process $proc$libresoc.v:155336$9064 - assign { } { } - assign $0\cr_a$20[3:0]$9065 4'0000 - sync always - sync init - update \cr_a$20 $0\cr_a$20[3:0]$9065 - end - attribute \src "libresoc.v:155345.7-155345.26" - process $proc$libresoc.v:155345$9066 - assign { } { } - assign $0\cr_a_ok$21[0:0]$9067 1'0 - sync always - sync init - update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$9067 - end - attribute \src "libresoc.v:155356.13-155356.29" - process $proc$libresoc.v:155356$9068 - assign { } { } - assign $0\muxid$1[1:0]$9069 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$9069 - end - attribute \src "libresoc.v:155371.14-155371.43" - process $proc$libresoc.v:155371$9070 + attribute \src "libresoc.v:158838.14-158838.47" + process $proc$libresoc.v:158838$9476 assign { } { } - assign $0\o$18[63:0]$9071 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9477 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$18 $0\o$18[63:0]$9071 + update \fast1$11 $0\fast1$11[63:0]$9477 end - attribute \src "libresoc.v:155380.7-155380.23" - process $proc$libresoc.v:155380$9072 + attribute \src "libresoc.v:158845.7-158845.22" + process $proc$libresoc.v:158845$9478 assign { } { } - assign $0\o_ok$19[0:0]$9073 1'0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \o_ok$19 $0\o_ok$19[0:0]$9073 + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:155666.7-155666.20" - process $proc$libresoc.v:155666$9074 + attribute \src "libresoc.v:158854.14-158854.47" + process $proc$libresoc.v:158854$9479 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\fast2$12[63:0]$9480 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \r_busy $1\r_busy[0:0] + update \fast2$12 $0\fast2$12[63:0]$9480 end - attribute \src "libresoc.v:155699.14-155699.42" - process $proc$libresoc.v:155699$9075 + attribute \src "libresoc.v:158861.7-158861.22" + process $proc$libresoc.v:158861$9481 assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$9076 12'000000000000 + assign $1\fast2_ok[0:0] 1'0 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9076 + update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:155721.14-155721.62" - process $proc$libresoc.v:155721$9077 + attribute \src "libresoc.v:159110.14-159110.40" + process $proc$libresoc.v:159110$9482 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9078 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9078 + update \msr $1\msr[63:0] end - attribute \src "libresoc.v:155730.7-155730.37" - process $proc$libresoc.v:155730$9079 + attribute \src "libresoc.v:159117.7-159117.20" + process $proc$libresoc.v:159117$9483 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9080 1'0 + assign $1\msr_ok[0:0] 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9080 + update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:155747.13-155747.43" - process $proc$libresoc.v:155747$9081 + attribute \src "libresoc.v:159126.13-159126.29" + process $proc$libresoc.v:159126$9484 assign { } { } - assign $0\sr_op__input_carry$11[1:0]$9082 2'00 + assign $0\muxid$1[1:0]$9485 2'00 sync always sync init - update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$9082 + update \muxid$1 $0\muxid$1[1:0]$9485 end - attribute \src "libresoc.v:155760.7-155760.34" - process $proc$libresoc.v:155760$9083 + attribute \src "libresoc.v:159139.14-159139.40" + process $proc$libresoc.v:159139$9486 assign { } { } - assign $0\sr_op__input_cr$13[0:0]$9084 1'0 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$9084 + update \nia $1\nia[63:0] end - attribute \src "libresoc.v:155769.14-155769.38" - process $proc$libresoc.v:155769$9085 + attribute \src "libresoc.v:159146.7-159146.20" + process $proc$libresoc.v:159146$9487 assign { } { } - assign $0\sr_op__insn$17[31:0]$9086 0 + assign $1\nia_ok[0:0] 1'0 sync always sync init - update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$9086 + update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:155926.13-155926.41" - process $proc$libresoc.v:155926$9087 + attribute \src "libresoc.v:159153.14-159153.38" + process $proc$libresoc.v:159153$9488 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9088 7'0000000 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9088 + update \o $1\o[63:0] end - attribute \src "libresoc.v:156009.7-156009.34" - process $proc$libresoc.v:156009$9089 + attribute \src "libresoc.v:159160.7-159160.18" + process $proc$libresoc.v:159160$9489 assign { } { } - assign $0\sr_op__is_32bit$15[0:0]$9090 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$9090 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:156018.7-156018.35" - process $proc$libresoc.v:156018$9091 + attribute \src "libresoc.v:159174.7-159174.20" + process $proc$libresoc.v:159174$9490 assign { } { } - assign $0\sr_op__is_signed$16[0:0]$9092 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$9092 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156029.7-156029.31" - process $proc$libresoc.v:156029$9093 + attribute \src "libresoc.v:159187.14-159187.53" + process $proc$libresoc.v:159187$9491 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9094 1'0 + assign $0\trap_op__cia$6[63:0]$9492 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9094 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9492 end - attribute \src "libresoc.v:156038.7-156038.31" - process $proc$libresoc.v:156038$9095 + attribute \src "libresoc.v:159220.14-159220.44" + process $proc$libresoc.v:159220$9493 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9096 1'0 + assign $0\trap_op__fn_unit$3[11:0]$9494 12'000000000000 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9096 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9494 end - attribute \src "libresoc.v:156045.7-156045.38" - process $proc$libresoc.v:156045$9097 + attribute \src "libresoc.v:159244.14-159244.39" + process $proc$libresoc.v:159244$9495 assign { } { } - assign $0\sr_op__output_carry$12[0:0]$9098 1'0 + assign $0\trap_op__insn$4[31:0]$9496 0 sync always sync init - update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$9098 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9496 end - attribute \src "libresoc.v:156054.7-156054.35" - process $proc$libresoc.v:156054$9099 + attribute \src "libresoc.v:159399.13-159399.43" + process $proc$libresoc.v:159399$9497 assign { } { } - assign $0\sr_op__output_cr$14[0:0]$9100 1'0 + assign $0\trap_op__insn_type$2[6:0]$9498 7'0000000 sync always sync init - update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$9100 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9498 end - attribute \src "libresoc.v:156065.7-156065.31" - process $proc$libresoc.v:156065$9101 + attribute \src "libresoc.v:159484.7-159484.35" + process $proc$libresoc.v:159484$9499 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9102 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9500 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9102 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9500 end - attribute \src "libresoc.v:156074.7-156074.31" - process $proc$libresoc.v:156074$9103 + attribute \src "libresoc.v:159491.13-159491.43" + process $proc$libresoc.v:159491$9501 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9104 1'0 + assign $0\trap_op__ldst_exc$10[7:0]$9502 8'00000000 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9104 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9502 end - attribute \src "libresoc.v:156081.7-156081.35" - process $proc$libresoc.v:156081$9105 + attribute \src "libresoc.v:159502.14-159502.53" + process $proc$libresoc.v:159502$9503 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9106 1'0 + assign $0\trap_op__msr$5[63:0]$9504 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9106 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9504 end - attribute \src "libresoc.v:156090.13-156090.31" - process $proc$libresoc.v:156090$9107 + attribute \src "libresoc.v:159511.14-159511.46" + process $proc$libresoc.v:159511$9505 assign { } { } - assign $0\xer_ca$22[1:0]$9108 2'00 + assign $0\trap_op__trapaddr$9[12:0]$9506 13'0000000000000 sync always sync init - update \xer_ca$22 $0\xer_ca$22[1:0]$9108 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9506 end - attribute \src "libresoc.v:156099.7-156099.28" - process $proc$libresoc.v:156099$9109 + attribute \src "libresoc.v:159520.13-159520.42" + process $proc$libresoc.v:159520$9507 assign { } { } - assign $0\xer_ca_ok$23[0:0]$9110 1'0 + assign $0\trap_op__traptype$8[7:0]$9508 8'00000000 sync always sync init - update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$9110 - end - attribute \src "libresoc.v:156113.3-156114.37" - process $proc$libresoc.v:156113$8952 - assign { } { } - assign $0\xer_ca$22[1:0]$8953 \xer_ca$22$next - sync posedge \coresync_clk - update \xer_ca$22 $0\xer_ca$22[1:0]$8953 - end - attribute \src "libresoc.v:156115.3-156116.43" - process $proc$libresoc.v:156115$8954 - assign { } { } - assign $0\xer_ca_ok$23[0:0]$8955 \xer_ca_ok$23$next - sync posedge \coresync_clk - update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8955 - end - attribute \src "libresoc.v:156117.3-156118.33" - process $proc$libresoc.v:156117$8956 - assign { } { } - assign $0\cr_a$20[3:0]$8957 \cr_a$20$next - sync posedge \coresync_clk - update \cr_a$20 $0\cr_a$20[3:0]$8957 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9508 end - attribute \src "libresoc.v:156119.3-156120.39" - process $proc$libresoc.v:156119$8958 + attribute \src "libresoc.v:159524.3-159525.23" + process $proc$libresoc.v:159524$9386 assign { } { } - assign $0\cr_a_ok$21[0:0]$8959 \cr_a_ok$21$next + assign $0\msr[63:0] \msr$next sync posedge \coresync_clk - update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8959 + update \msr $0\msr[63:0] end - attribute \src "libresoc.v:156121.3-156122.27" - process $proc$libresoc.v:156121$8960 + attribute \src "libresoc.v:159526.3-159527.29" + process $proc$libresoc.v:159526$9387 assign { } { } - assign $0\o$18[63:0]$8961 \o$18$next + assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk - update \o$18 $0\o$18[63:0]$8961 + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:156123.3-156124.33" - process $proc$libresoc.v:156123$8962 + attribute \src "libresoc.v:159528.3-159529.23" + process $proc$libresoc.v:159528$9388 assign { } { } - assign $0\o_ok$19[0:0]$8963 \o_ok$19$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \o_ok$19 $0\o_ok$19[0:0]$8963 + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:156125.3-156126.55" - process $proc$libresoc.v:156125$8964 + attribute \src "libresoc.v:159530.3-159531.29" + process $proc$libresoc.v:159530$9389 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$8965 \sr_op__insn_type$2$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8965 + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:156127.3-156128.51" - process $proc$libresoc.v:156127$8966 + attribute \src "libresoc.v:159532.3-159533.35" + process $proc$libresoc.v:159532$9390 assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$8967 \sr_op__fn_unit$3$next + assign $0\fast2$12[63:0]$9391 \fast2$12$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8967 + update \fast2$12 $0\fast2$12[63:0]$9391 end - attribute \src "libresoc.v:156129.3-156130.65" - process $proc$libresoc.v:156129$8968 + attribute \src "libresoc.v:159534.3-159535.33" + process $proc$libresoc.v:159534$9392 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$8969 \sr_op__imm_data__data$4$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8969 + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:156131.3-156132.61" - process $proc$libresoc.v:156131$8970 + attribute \src "libresoc.v:159536.3-159537.35" + process $proc$libresoc.v:159536$9393 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$8971 \sr_op__imm_data__ok$5$next + assign $0\fast1$11[63:0]$9394 \fast1$11$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8971 + update \fast1$11 $0\fast1$11[63:0]$9394 end - attribute \src "libresoc.v:156133.3-156134.49" - process $proc$libresoc.v:156133$8972 + attribute \src "libresoc.v:159538.3-159539.33" + process $proc$libresoc.v:159538$9395 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$8973 \sr_op__rc__rc$6$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8973 + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:156135.3-156136.49" - process $proc$libresoc.v:156135$8974 + attribute \src "libresoc.v:159540.3-159541.19" + process $proc$libresoc.v:159540$9396 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$8975 \sr_op__rc__ok$7$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8975 + update \o $0\o[63:0] end - attribute \src "libresoc.v:156137.3-156138.49" - process $proc$libresoc.v:156137$8976 + attribute \src "libresoc.v:159542.3-159543.25" + process $proc$libresoc.v:159542$9397 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$8977 \sr_op__oe__oe$8$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8977 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:156139.3-156140.49" - process $proc$libresoc.v:156139$8978 + attribute \src "libresoc.v:159544.3-159545.59" + process $proc$libresoc.v:159544$9398 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$8979 \sr_op__oe__ok$9$next + assign $0\trap_op__insn_type$2[6:0]$9399 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8979 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9399 end - attribute \src "libresoc.v:156141.3-156142.57" - process $proc$libresoc.v:156141$8980 + attribute \src "libresoc.v:159546.3-159547.55" + process $proc$libresoc.v:159546$9400 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$8981 \sr_op__write_cr0$10$next + assign $0\trap_op__fn_unit$3[11:0]$9401 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8981 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9401 end - attribute \src "libresoc.v:156143.3-156144.61" - process $proc$libresoc.v:156143$8982 + attribute \src "libresoc.v:159548.3-159549.49" + process $proc$libresoc.v:159548$9402 assign { } { } - assign $0\sr_op__input_carry$11[1:0]$8983 \sr_op__input_carry$11$next + assign $0\trap_op__insn$4[31:0]$9403 \trap_op__insn$4$next sync posedge \coresync_clk - update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8983 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9403 end - attribute \src "libresoc.v:156145.3-156146.63" - process $proc$libresoc.v:156145$8984 + attribute \src "libresoc.v:159550.3-159551.47" + process $proc$libresoc.v:159550$9404 assign { } { } - assign $0\sr_op__output_carry$12[0:0]$8985 \sr_op__output_carry$12$next + assign $0\trap_op__msr$5[63:0]$9405 \trap_op__msr$5$next sync posedge \coresync_clk - update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8985 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9405 end - attribute \src "libresoc.v:156147.3-156148.55" - process $proc$libresoc.v:156147$8986 + attribute \src "libresoc.v:159552.3-159553.47" + process $proc$libresoc.v:159552$9406 assign { } { } - assign $0\sr_op__input_cr$13[0:0]$8987 \sr_op__input_cr$13$next + assign $0\trap_op__cia$6[63:0]$9407 \trap_op__cia$6$next sync posedge \coresync_clk - update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8987 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9407 end - attribute \src "libresoc.v:156149.3-156150.57" - process $proc$libresoc.v:156149$8988 + attribute \src "libresoc.v:159554.3-159555.57" + process $proc$libresoc.v:159554$9408 assign { } { } - assign $0\sr_op__output_cr$14[0:0]$8989 \sr_op__output_cr$14$next + assign $0\trap_op__is_32bit$7[0:0]$9409 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8989 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9409 end - attribute \src "libresoc.v:156151.3-156152.55" - process $proc$libresoc.v:156151$8990 + attribute \src "libresoc.v:159556.3-159557.57" + process $proc$libresoc.v:159556$9410 assign { } { } - assign $0\sr_op__is_32bit$15[0:0]$8991 \sr_op__is_32bit$15$next + assign $0\trap_op__traptype$8[7:0]$9411 \trap_op__traptype$8$next sync posedge \coresync_clk - update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8991 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9411 end - attribute \src "libresoc.v:156153.3-156154.57" - process $proc$libresoc.v:156153$8992 + attribute \src "libresoc.v:159558.3-159559.57" + process $proc$libresoc.v:159558$9412 assign { } { } - assign $0\sr_op__is_signed$16[0:0]$8993 \sr_op__is_signed$16$next + assign $0\trap_op__trapaddr$9[12:0]$9413 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8993 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9413 end - attribute \src "libresoc.v:156155.3-156156.47" - process $proc$libresoc.v:156155$8994 + attribute \src "libresoc.v:159560.3-159561.59" + process $proc$libresoc.v:159560$9414 assign { } { } - assign $0\sr_op__insn$17[31:0]$8995 \sr_op__insn$17$next + assign $0\trap_op__ldst_exc$10[7:0]$9415 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8995 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9415 end - attribute \src "libresoc.v:156157.3-156158.33" - process $proc$libresoc.v:156157$8996 + attribute \src "libresoc.v:159562.3-159563.33" + process $proc$libresoc.v:159562$9416 assign { } { } - assign $0\muxid$1[1:0]$8997 \muxid$1$next + assign $0\muxid$1[1:0]$9417 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8997 + update \muxid$1 $0\muxid$1[1:0]$9417 end - attribute \src "libresoc.v:156159.3-156160.29" - process $proc$libresoc.v:156159$8998 + attribute \src "libresoc.v:159564.3-159565.29" + process $proc$libresoc.v:159564$9418 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156216.3-156233.6" - process $proc$libresoc.v:156216$8999 + attribute \src "libresoc.v:159610.3-159627.6" + process $proc$libresoc.v:159610$9419 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9000 $2\r_busy$next[0:0]$9002 - attribute \src "libresoc.v:156217.5-156217.29" + assign $0\r_busy$next[0:0]$9420 $2\r_busy$next[0:0]$9422 + attribute \src "libresoc.v:159611.5-159611.29" switch \initial - attribute \src "libresoc.v:156217.9-156217.17" + attribute \src "libresoc.v:159611.9-159611.17" case 1'1 case end @@ -320993,34 +328901,34 @@ module \pipe2$112 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9001 1'1 + assign $1\r_busy$next[0:0]$9421 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9001 1'0 + assign $1\r_busy$next[0:0]$9421 1'0 case - assign $1\r_busy$next[0:0]$9001 \r_busy + assign $1\r_busy$next[0:0]$9421 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9002 1'0 + assign $2\r_busy$next[0:0]$9422 1'0 case - assign $2\r_busy$next[0:0]$9002 $1\r_busy$next[0:0]$9001 + assign $2\r_busy$next[0:0]$9422 $1\r_busy$next[0:0]$9421 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9000 + update \r_busy$next $0\r_busy$next[0:0]$9420 end - attribute \src "libresoc.v:156234.3-156246.6" - process $proc$libresoc.v:156234$9003 + attribute \src "libresoc.v:159628.3-159640.6" + process $proc$libresoc.v:159628$9423 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9004 $1\muxid$1$next[1:0]$9005 - attribute \src "libresoc.v:156235.5-156235.29" + assign $0\muxid$1$next[1:0]$9424 $1\muxid$1$next[1:0]$9425 + attribute \src "libresoc.v:159629.5-159629.29" switch \initial - attribute \src "libresoc.v:156235.9-156235.17" + attribute \src "libresoc.v:159629.9-159629.17" case 1'1 case end @@ -321029,31 +328937,19 @@ module \pipe2$112 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9005 \muxid$51 + assign $1\muxid$1$next[1:0]$9425 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9005 \muxid$51 + assign $1\muxid$1$next[1:0]$9425 \muxid$28 case - assign $1\muxid$1$next[1:0]$9005 \muxid$1 + assign $1\muxid$1$next[1:0]$9425 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9004 + update \muxid$1$next $0\muxid$1$next[1:0]$9424 end - attribute \src "libresoc.v:156247.3-156286.6" - process $proc$libresoc.v:156247$9006 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:159641.3-159661.6" + process $proc$libresoc.v:159641$9426 assign { } { } assign { } { } assign { } { } @@ -321072,33 +328968,18 @@ module \pipe2$112 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$3$next[11:0]$9007 $1\sr_op__fn_unit$3$next[11:0]$9023 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$11$next[1:0]$9010 $1\sr_op__input_carry$11$next[1:0]$9026 - assign $0\sr_op__input_cr$13$next[0:0]$9011 $1\sr_op__input_cr$13$next[0:0]$9027 - assign $0\sr_op__insn$17$next[31:0]$9012 $1\sr_op__insn$17$next[31:0]$9028 - assign $0\sr_op__insn_type$2$next[6:0]$9013 $1\sr_op__insn_type$2$next[6:0]$9029 - assign $0\sr_op__is_32bit$15$next[0:0]$9014 $1\sr_op__is_32bit$15$next[0:0]$9030 - assign $0\sr_op__is_signed$16$next[0:0]$9015 $1\sr_op__is_signed$16$next[0:0]$9031 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$12$next[0:0]$9018 $1\sr_op__output_carry$12$next[0:0]$9034 - assign $0\sr_op__output_cr$14$next[0:0]$9019 $1\sr_op__output_cr$14$next[0:0]$9035 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9022 $1\sr_op__write_cr0$10$next[0:0]$9038 - assign $0\sr_op__imm_data__data$4$next[63:0]$9008 $2\sr_op__imm_data__data$4$next[63:0]$9039 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9009 $2\sr_op__imm_data__ok$5$next[0:0]$9040 - assign $0\sr_op__oe__oe$8$next[0:0]$9016 $2\sr_op__oe__oe$8$next[0:0]$9041 - assign $0\sr_op__oe__ok$9$next[0:0]$9017 $2\sr_op__oe__ok$9$next[0:0]$9042 - assign $0\sr_op__rc__ok$7$next[0:0]$9020 $2\sr_op__rc__ok$7$next[0:0]$9043 - assign $0\sr_op__rc__rc$6$next[0:0]$9021 $2\sr_op__rc__rc$6$next[0:0]$9044 - attribute \src "libresoc.v:156248.5-156248.29" + assign $0\trap_op__cia$6$next[63:0]$9427 $1\trap_op__cia$6$next[63:0]$9436 + assign $0\trap_op__fn_unit$3$next[11:0]$9428 $1\trap_op__fn_unit$3$next[11:0]$9437 + assign $0\trap_op__insn$4$next[31:0]$9429 $1\trap_op__insn$4$next[31:0]$9438 + assign $0\trap_op__insn_type$2$next[6:0]$9430 $1\trap_op__insn_type$2$next[6:0]$9439 + assign $0\trap_op__is_32bit$7$next[0:0]$9431 $1\trap_op__is_32bit$7$next[0:0]$9440 + assign $0\trap_op__ldst_exc$10$next[7:0]$9432 $1\trap_op__ldst_exc$10$next[7:0]$9441 + assign $0\trap_op__msr$5$next[63:0]$9433 $1\trap_op__msr$5$next[63:0]$9442 + assign $0\trap_op__trapaddr$9$next[12:0]$9434 $1\trap_op__trapaddr$9$next[12:0]$9443 + assign $0\trap_op__traptype$8$next[7:0]$9435 $1\trap_op__traptype$8$next[7:0]$9444 + attribute \src "libresoc.v:159642.5-159642.29" switch \initial - attribute \src "libresoc.v:156248.9-156248.17" + attribute \src "libresoc.v:159642.9-159642.17" case 1'1 case end @@ -321115,14 +328996,7 @@ module \pipe2$112 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$17$next[31:0]$9028 $1\sr_op__is_signed$16$next[0:0]$9031 $1\sr_op__is_32bit$15$next[0:0]$9030 $1\sr_op__output_cr$14$next[0:0]$9035 $1\sr_op__input_cr$13$next[0:0]$9027 $1\sr_op__output_carry$12$next[0:0]$9034 $1\sr_op__input_carry$11$next[1:0]$9026 $1\sr_op__write_cr0$10$next[0:0]$9038 $1\sr_op__oe__ok$9$next[0:0]$9033 $1\sr_op__oe__oe$8$next[0:0]$9032 $1\sr_op__rc__ok$7$next[0:0]$9036 $1\sr_op__rc__rc$6$next[0:0]$9037 $1\sr_op__imm_data__ok$5$next[0:0]$9025 $1\sr_op__imm_data__data$4$next[63:0]$9024 $1\sr_op__fn_unit$3$next[11:0]$9023 $1\sr_op__insn_type$2$next[6:0]$9029 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9441 $1\trap_op__trapaddr$9$next[12:0]$9443 $1\trap_op__traptype$8$next[7:0]$9444 $1\trap_op__is_32bit$7$next[0:0]$9440 $1\trap_op__cia$6$next[63:0]$9436 $1\trap_op__msr$5$next[63:0]$9442 $1\trap_op__insn$4$next[31:0]$9438 $1\trap_op__fn_unit$3$next[11:0]$9437 $1\trap_op__insn_type$2$next[6:0]$9439 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -321134,86 +329008,129 @@ module \pipe2$112 assign { } { } assign { } { } assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9441 $1\trap_op__trapaddr$9$next[12:0]$9443 $1\trap_op__traptype$8$next[7:0]$9444 $1\trap_op__is_32bit$7$next[0:0]$9440 $1\trap_op__cia$6$next[63:0]$9436 $1\trap_op__msr$5$next[63:0]$9442 $1\trap_op__insn$4$next[31:0]$9438 $1\trap_op__fn_unit$3$next[11:0]$9437 $1\trap_op__insn_type$2$next[6:0]$9439 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + case + assign $1\trap_op__cia$6$next[63:0]$9436 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[11:0]$9437 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9438 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9439 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9440 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9441 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9442 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9443 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9444 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9427 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$9428 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9429 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9430 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9431 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9432 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9433 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9434 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9435 + end + attribute \src "libresoc.v:159662.3-159680.6" + process $proc$libresoc.v:159662$9445 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9446 $1\o$next[63:0]$9448 + assign { } { } + assign $0\o_ok$next[0:0]$9447 $2\o_ok$next[0:0]$9450 + attribute \src "libresoc.v:159663.5-159663.29" + switch \initial + attribute \src "libresoc.v:159663.9-159663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\o_ok$next[0:0]$9449 $1\o$next[63:0]$9448 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$17$next[31:0]$9028 $1\sr_op__is_signed$16$next[0:0]$9031 $1\sr_op__is_32bit$15$next[0:0]$9030 $1\sr_op__output_cr$14$next[0:0]$9035 $1\sr_op__input_cr$13$next[0:0]$9027 $1\sr_op__output_carry$12$next[0:0]$9034 $1\sr_op__input_carry$11$next[1:0]$9026 $1\sr_op__write_cr0$10$next[0:0]$9038 $1\sr_op__oe__ok$9$next[0:0]$9033 $1\sr_op__oe__oe$8$next[0:0]$9032 $1\sr_op__rc__ok$7$next[0:0]$9036 $1\sr_op__rc__rc$6$next[0:0]$9037 $1\sr_op__imm_data__ok$5$next[0:0]$9025 $1\sr_op__imm_data__data$4$next[63:0]$9024 $1\sr_op__fn_unit$3$next[11:0]$9023 $1\sr_op__insn_type$2$next[6:0]$9029 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + assign { $1\o_ok$next[0:0]$9449 $1\o$next[63:0]$9448 } { \o_ok$39 \o$38 } case - assign $1\sr_op__fn_unit$3$next[11:0]$9023 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9024 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9025 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$11$next[1:0]$9026 \sr_op__input_carry$11 - assign $1\sr_op__input_cr$13$next[0:0]$9027 \sr_op__input_cr$13 - assign $1\sr_op__insn$17$next[31:0]$9028 \sr_op__insn$17 - assign $1\sr_op__insn_type$2$next[6:0]$9029 \sr_op__insn_type$2 - assign $1\sr_op__is_32bit$15$next[0:0]$9030 \sr_op__is_32bit$15 - assign $1\sr_op__is_signed$16$next[0:0]$9031 \sr_op__is_signed$16 - assign $1\sr_op__oe__oe$8$next[0:0]$9032 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9033 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$12$next[0:0]$9034 \sr_op__output_carry$12 - assign $1\sr_op__output_cr$14$next[0:0]$9035 \sr_op__output_cr$14 - assign $1\sr_op__rc__ok$7$next[0:0]$9036 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9037 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9038 \sr_op__write_cr0$10 + assign $1\o$next[63:0]$9448 \o + assign $1\o_ok$next[0:0]$9449 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $2\o_ok$next[0:0]$9450 1'0 + case + assign $2\o_ok$next[0:0]$9450 $1\o_ok$next[0:0]$9449 + end + sync always + update \o$next $0\o$next[63:0]$9446 + update \o_ok$next $0\o_ok$next[0:0]$9447 + end + attribute \src "libresoc.v:159681.3-159699.6" + process $proc$libresoc.v:159681$9451 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9453 $1\fast1$11$next[63:0]$9455 + assign $0\fast1_ok$next[0:0]$9452 $2\fast1_ok$next[0:0]$9456 + attribute \src "libresoc.v:159682.5-159682.29" + switch \initial + attribute \src "libresoc.v:159682.9-159682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } assign { } { } + assign { $1\fast1_ok$next[0:0]$9454 $1\fast1$11$next[63:0]$9455 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } + assign { $1\fast1_ok$next[0:0]$9454 $1\fast1$11$next[63:0]$9455 } { \fast1_ok$41 \fast1$40 } + case + assign $1\fast1_ok$next[0:0]$9454 \fast1_ok + assign $1\fast1$11$next[63:0]$9455 \fast1$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9039 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9040 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9044 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9043 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9041 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9042 1'0 + assign $2\fast1_ok$next[0:0]$9456 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9039 $1\sr_op__imm_data__data$4$next[63:0]$9024 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9040 $1\sr_op__imm_data__ok$5$next[0:0]$9025 - assign $2\sr_op__oe__oe$8$next[0:0]$9041 $1\sr_op__oe__oe$8$next[0:0]$9032 - assign $2\sr_op__oe__ok$9$next[0:0]$9042 $1\sr_op__oe__ok$9$next[0:0]$9033 - assign $2\sr_op__rc__ok$7$next[0:0]$9043 $1\sr_op__rc__ok$7$next[0:0]$9036 - assign $2\sr_op__rc__rc$6$next[0:0]$9044 $1\sr_op__rc__rc$6$next[0:0]$9037 + assign $2\fast1_ok$next[0:0]$9456 $1\fast1_ok$next[0:0]$9454 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9007 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9008 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9009 - update \sr_op__input_carry$11$next $0\sr_op__input_carry$11$next[1:0]$9010 - update \sr_op__input_cr$13$next $0\sr_op__input_cr$13$next[0:0]$9011 - update \sr_op__insn$17$next $0\sr_op__insn$17$next[31:0]$9012 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9013 - update \sr_op__is_32bit$15$next $0\sr_op__is_32bit$15$next[0:0]$9014 - update \sr_op__is_signed$16$next $0\sr_op__is_signed$16$next[0:0]$9015 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9016 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9017 - update \sr_op__output_carry$12$next $0\sr_op__output_carry$12$next[0:0]$9018 - update \sr_op__output_cr$14$next $0\sr_op__output_cr$14$next[0:0]$9019 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9020 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9021 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9022 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9452 + update \fast1$11$next $0\fast1$11$next[63:0]$9453 end - attribute \src "libresoc.v:156287.3-156305.6" - process $proc$libresoc.v:156287$9045 + attribute \src "libresoc.v:159700.3-159718.6" + process $proc$libresoc.v:159700$9457 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$18$next[63:0]$9046 $1\o$18$next[63:0]$9048 assign { } { } - assign $0\o_ok$19$next[0:0]$9047 $2\o_ok$19$next[0:0]$9050 - attribute \src "libresoc.v:156288.5-156288.29" + assign $0\fast2$12$next[63:0]$9459 $1\fast2$12$next[63:0]$9461 + assign $0\fast2_ok$next[0:0]$9458 $2\fast2_ok$next[0:0]$9462 + attribute \src "libresoc.v:159701.5-159701.29" switch \initial - attribute \src "libresoc.v:156288.9-156288.17" + attribute \src "libresoc.v:159701.9-159701.17" case 1'1 case end @@ -321223,41 +329140,41 @@ module \pipe2$112 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$19$next[0:0]$9049 $1\o$18$next[63:0]$9048 } { \o_ok$69 \o$68 } + assign { $1\fast2_ok$next[0:0]$9460 $1\fast2$12$next[63:0]$9461 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$19$next[0:0]$9049 $1\o$18$next[63:0]$9048 } { \o_ok$69 \o$68 } + assign { $1\fast2_ok$next[0:0]$9460 $1\fast2$12$next[63:0]$9461 } { \fast2_ok$43 \fast2$42 } case - assign $1\o$18$next[63:0]$9048 \o$18 - assign $1\o_ok$19$next[0:0]$9049 \o_ok$19 + assign $1\fast2_ok$next[0:0]$9460 \fast2_ok + assign $1\fast2$12$next[63:0]$9461 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$19$next[0:0]$9050 1'0 + assign $2\fast2_ok$next[0:0]$9462 1'0 case - assign $2\o_ok$19$next[0:0]$9050 $1\o_ok$19$next[0:0]$9049 + assign $2\fast2_ok$next[0:0]$9462 $1\fast2_ok$next[0:0]$9460 end sync always - update \o$18$next $0\o$18$next[63:0]$9046 - update \o_ok$19$next $0\o_ok$19$next[0:0]$9047 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9458 + update \fast2$12$next $0\fast2$12$next[63:0]$9459 end - attribute \src "libresoc.v:156306.3-156324.6" - process $proc$libresoc.v:156306$9051 + attribute \src "libresoc.v:159719.3-159737.6" + process $proc$libresoc.v:159719$9463 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$20$next[3:0]$9052 $1\cr_a$20$next[3:0]$9054 + assign $0\nia$next[63:0]$9464 $1\nia$next[63:0]$9466 assign { } { } - assign $0\cr_a_ok$21$next[0:0]$9053 $2\cr_a_ok$21$next[0:0]$9056 - attribute \src "libresoc.v:156307.5-156307.29" + assign $0\nia_ok$next[0:0]$9465 $2\nia_ok$next[0:0]$9468 + attribute \src "libresoc.v:159720.5-159720.29" switch \initial - attribute \src "libresoc.v:156307.9-156307.17" + attribute \src "libresoc.v:159720.9-159720.17" case 1'1 case end @@ -321267,41 +329184,41 @@ module \pipe2$112 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$21$next[0:0]$9055 $1\cr_a$20$next[3:0]$9054 } { \cr_a_ok$71 \cr_a$70 } + assign { $1\nia_ok$next[0:0]$9467 $1\nia$next[63:0]$9466 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$21$next[0:0]$9055 $1\cr_a$20$next[3:0]$9054 } { \cr_a_ok$71 \cr_a$70 } + assign { $1\nia_ok$next[0:0]$9467 $1\nia$next[63:0]$9466 } { \nia_ok$45 \nia$44 } case - assign $1\cr_a$20$next[3:0]$9054 \cr_a$20 - assign $1\cr_a_ok$21$next[0:0]$9055 \cr_a_ok$21 + assign $1\nia$next[63:0]$9466 \nia + assign $1\nia_ok$next[0:0]$9467 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$21$next[0:0]$9056 1'0 + assign $2\nia_ok$next[0:0]$9468 1'0 case - assign $2\cr_a_ok$21$next[0:0]$9056 $1\cr_a_ok$21$next[0:0]$9055 + assign $2\nia_ok$next[0:0]$9468 $1\nia_ok$next[0:0]$9467 end sync always - update \cr_a$20$next $0\cr_a$20$next[3:0]$9052 - update \cr_a_ok$21$next $0\cr_a_ok$21$next[0:0]$9053 + update \nia$next $0\nia$next[63:0]$9464 + update \nia_ok$next $0\nia_ok$next[0:0]$9465 end - attribute \src "libresoc.v:156325.3-156343.6" - process $proc$libresoc.v:156325$9057 + attribute \src "libresoc.v:159738.3-159756.6" + process $proc$libresoc.v:159738$9469 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$22$next[1:0]$9058 $1\xer_ca$22$next[1:0]$9060 + assign $0\msr$next[63:0]$9470 $1\msr$next[63:0]$9472 assign { } { } - assign $0\xer_ca_ok$23$next[0:0]$9059 $2\xer_ca_ok$23$next[0:0]$9062 - attribute \src "libresoc.v:156326.5-156326.29" + assign $0\msr_ok$next[0:0]$9471 $2\msr_ok$next[0:0]$9474 + attribute \src "libresoc.v:159739.5-159739.29" switch \initial - attribute \src "libresoc.v:156326.9-156326.17" + attribute \src "libresoc.v:159739.9-159739.17" case 1'1 case end @@ -321311,325 +329228,327 @@ module \pipe2$112 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$23$next[0:0]$9061 $1\xer_ca$22$next[1:0]$9060 } { \xer_ca_ok$73 \xer_ca$72 } + assign { $1\msr_ok$next[0:0]$9473 $1\msr$next[63:0]$9472 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$23$next[0:0]$9061 $1\xer_ca$22$next[1:0]$9060 } { \xer_ca_ok$73 \xer_ca$72 } + assign { $1\msr_ok$next[0:0]$9473 $1\msr$next[63:0]$9472 } { \msr_ok$47 \msr$46 } case - assign $1\xer_ca$22$next[1:0]$9060 \xer_ca$22 - assign $1\xer_ca_ok$23$next[0:0]$9061 \xer_ca_ok$23 + assign $1\msr$next[63:0]$9472 \msr + assign $1\msr_ok$next[0:0]$9473 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$23$next[0:0]$9062 1'0 + assign $2\msr_ok$next[0:0]$9474 1'0 case - assign $2\xer_ca_ok$23$next[0:0]$9062 $1\xer_ca_ok$23$next[0:0]$9061 + assign $2\msr_ok$next[0:0]$9474 $1\msr_ok$next[0:0]$9473 end sync always - update \xer_ca$22$next $0\xer_ca$22$next[1:0]$9058 - update \xer_ca_ok$23$next $0\xer_ca_ok$23$next[0:0]$9059 + update \msr$next $0\msr$next[63:0]$9470 + update \msr_ok$next $0\msr_ok$next[0:0]$9471 end - connect \$49 $and$libresoc.v:156112$8951_Y + connect \$26 $and$libresoc.v:159523$9385_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } - connect { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } - connect { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } - connect { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } - connect \muxid$51 \output_muxid$24 - connect \p_valid_i_p_ready_o \$49 + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$48 \p_valid_i - connect { \xer_ca_ok$47 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \xer_so_ok$46 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$45 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \output_muxid \muxid + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid end -attribute \src "libresoc.v:156364.1-157846.10" +attribute \src "libresoc.v:159779.1-161261.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:157684.3-157702.6" - wire width 4 $0\cr_a$next[3:0]$9167 - attribute \src "libresoc.v:157503.3-157504.25" + attribute \src "libresoc.v:161099.3-161117.6" + wire width 4 $0\cr_a$next[3:0]$9565 + attribute \src "libresoc.v:160918.3-160919.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:157684.3-157702.6" - wire $0\cr_a_ok$next[0:0]$9168 - attribute \src "libresoc.v:157505.3-157506.31" + attribute \src "libresoc.v:161099.3-161117.6" + wire $0\cr_a_ok$next[0:0]$9566 + attribute \src "libresoc.v:160920.3-160921.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:156365.7-156365.20" + attribute \src "libresoc.v:159780.7-159780.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157772.3-157813.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9192 - attribute \src "libresoc.v:157543.3-157544.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9154 - attribute \src "libresoc.v:156406.13-156406.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9238 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9193 - attribute \src "libresoc.v:157513.3-157514.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9124 - attribute \src "libresoc.v:156441.14-156441.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9240 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9194 - attribute \src "libresoc.v:157515.3-157516.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9126 - attribute \src "libresoc.v:156463.14-156463.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9242 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9195 - attribute \src "libresoc.v:157517.3-157518.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9128 - attribute \src "libresoc.v:156472.7-156472.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9244 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9196 - attribute \src "libresoc.v:157531.3-157532.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9142 - attribute \src "libresoc.v:156489.13-156489.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9246 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9197 - attribute \src "libresoc.v:157545.3-157546.57" - wire width 32 $0\logical_op__insn$19[31:0]$9156 - attribute \src "libresoc.v:156502.14-156502.43" - wire width 32 $0\logical_op__insn$19[31:0]$9248 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9198 - attribute \src "libresoc.v:157511.3-157512.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9122 - attribute \src "libresoc.v:156659.13-156659.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9250 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__invert_in$10$next[0:0]$9199 - attribute \src "libresoc.v:157527.3-157528.67" - wire $0\logical_op__invert_in$10[0:0]$9138 - attribute \src "libresoc.v:156742.7-156742.40" - wire $0\logical_op__invert_in$10[0:0]$9252 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__invert_out$13$next[0:0]$9200 - attribute \src "libresoc.v:157533.3-157534.69" - wire $0\logical_op__invert_out$13[0:0]$9144 - attribute \src "libresoc.v:156751.7-156751.41" - wire $0\logical_op__invert_out$13[0:0]$9254 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9201 - attribute \src "libresoc.v:157539.3-157540.65" - wire $0\logical_op__is_32bit$16[0:0]$9150 - attribute \src "libresoc.v:156760.7-156760.39" - wire $0\logical_op__is_32bit$16[0:0]$9256 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__is_signed$17$next[0:0]$9202 - attribute \src "libresoc.v:157541.3-157542.67" - wire $0\logical_op__is_signed$17[0:0]$9152 - attribute \src "libresoc.v:156769.7-156769.40" - wire $0\logical_op__is_signed$17[0:0]$9258 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9203 - attribute \src "libresoc.v:157523.3-157524.59" - wire $0\logical_op__oe__oe$8[0:0]$9134 - attribute \src "libresoc.v:156778.7-156778.36" - wire $0\logical_op__oe__oe$8[0:0]$9260 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9204 - attribute \src "libresoc.v:157525.3-157526.59" - wire $0\logical_op__oe__ok$9[0:0]$9136 - attribute \src "libresoc.v:156789.7-156789.36" - wire $0\logical_op__oe__ok$9[0:0]$9262 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__output_carry$15$next[0:0]$9205 - attribute \src "libresoc.v:157537.3-157538.73" - wire $0\logical_op__output_carry$15[0:0]$9148 - attribute \src "libresoc.v:156796.7-156796.43" - wire $0\logical_op__output_carry$15[0:0]$9264 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9206 - attribute \src "libresoc.v:157521.3-157522.59" - wire $0\logical_op__rc__ok$7[0:0]$9132 - attribute \src "libresoc.v:156805.7-156805.36" - wire $0\logical_op__rc__ok$7[0:0]$9266 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9207 - attribute \src "libresoc.v:157519.3-157520.59" - wire $0\logical_op__rc__rc$6[0:0]$9130 - attribute \src "libresoc.v:156814.7-156814.36" - wire $0\logical_op__rc__rc$6[0:0]$9268 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9208 - attribute \src "libresoc.v:157535.3-157536.67" - wire $0\logical_op__write_cr0$14[0:0]$9146 - attribute \src "libresoc.v:156823.7-156823.40" - wire $0\logical_op__write_cr0$14[0:0]$9270 - attribute \src "libresoc.v:157772.3-157813.6" - wire $0\logical_op__zero_a$11$next[0:0]$9209 - attribute \src "libresoc.v:157529.3-157530.61" - wire $0\logical_op__zero_a$11[0:0]$9140 - attribute \src "libresoc.v:156832.7-156832.37" - wire $0\logical_op__zero_a$11[0:0]$9272 - attribute \src "libresoc.v:157759.3-157771.6" - wire width 2 $0\muxid$1$next[1:0]$9189 - attribute \src "libresoc.v:157547.3-157548.33" - wire width 2 $0\muxid$1[1:0]$9158 - attribute \src "libresoc.v:156841.13-156841.29" - wire width 2 $0\muxid$1[1:0]$9274 - attribute \src "libresoc.v:157665.3-157683.6" - wire width 64 $0\o$next[63:0]$9161 - attribute \src "libresoc.v:157507.3-157508.19" + attribute \src "libresoc.v:161187.3-161228.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9590 + attribute \src "libresoc.v:160958.3-160959.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9552 + attribute \src "libresoc.v:159821.13-159821.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9636 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9591 + attribute \src "libresoc.v:160928.3-160929.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9522 + attribute \src "libresoc.v:159856.14-159856.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$9638 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9592 + attribute \src "libresoc.v:160930.3-160931.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9524 + attribute \src "libresoc.v:159878.14-159878.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9640 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9593 + attribute \src "libresoc.v:160932.3-160933.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9526 + attribute \src "libresoc.v:159887.7-159887.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9642 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9594 + attribute \src "libresoc.v:160946.3-160947.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9540 + attribute \src "libresoc.v:159904.13-159904.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9644 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9595 + attribute \src "libresoc.v:160960.3-160961.57" + wire width 32 $0\logical_op__insn$19[31:0]$9554 + attribute \src "libresoc.v:159917.14-159917.43" + wire width 32 $0\logical_op__insn$19[31:0]$9646 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9596 + attribute \src "libresoc.v:160926.3-160927.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9520 + attribute \src "libresoc.v:160074.13-160074.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9648 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__invert_in$10$next[0:0]$9597 + attribute \src "libresoc.v:160942.3-160943.67" + wire $0\logical_op__invert_in$10[0:0]$9536 + attribute \src "libresoc.v:160157.7-160157.40" + wire $0\logical_op__invert_in$10[0:0]$9650 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__invert_out$13$next[0:0]$9598 + attribute \src "libresoc.v:160948.3-160949.69" + wire $0\logical_op__invert_out$13[0:0]$9542 + attribute \src "libresoc.v:160166.7-160166.41" + wire $0\logical_op__invert_out$13[0:0]$9652 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9599 + attribute \src "libresoc.v:160954.3-160955.65" + wire $0\logical_op__is_32bit$16[0:0]$9548 + attribute \src "libresoc.v:160175.7-160175.39" + wire $0\logical_op__is_32bit$16[0:0]$9654 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__is_signed$17$next[0:0]$9600 + attribute \src "libresoc.v:160956.3-160957.67" + wire $0\logical_op__is_signed$17[0:0]$9550 + attribute \src "libresoc.v:160184.7-160184.40" + wire $0\logical_op__is_signed$17[0:0]$9656 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9601 + attribute \src "libresoc.v:160938.3-160939.59" + wire $0\logical_op__oe__oe$8[0:0]$9532 + attribute \src "libresoc.v:160193.7-160193.36" + wire $0\logical_op__oe__oe$8[0:0]$9658 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9602 + attribute \src "libresoc.v:160940.3-160941.59" + wire $0\logical_op__oe__ok$9[0:0]$9534 + attribute \src "libresoc.v:160204.7-160204.36" + wire $0\logical_op__oe__ok$9[0:0]$9660 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__output_carry$15$next[0:0]$9603 + attribute \src "libresoc.v:160952.3-160953.73" + wire $0\logical_op__output_carry$15[0:0]$9546 + attribute \src "libresoc.v:160211.7-160211.43" + wire $0\logical_op__output_carry$15[0:0]$9662 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9604 + attribute \src "libresoc.v:160936.3-160937.59" + wire $0\logical_op__rc__ok$7[0:0]$9530 + attribute \src "libresoc.v:160220.7-160220.36" + wire $0\logical_op__rc__ok$7[0:0]$9664 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9605 + attribute \src "libresoc.v:160934.3-160935.59" + wire $0\logical_op__rc__rc$6[0:0]$9528 + attribute \src "libresoc.v:160229.7-160229.36" + wire $0\logical_op__rc__rc$6[0:0]$9666 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9606 + attribute \src "libresoc.v:160950.3-160951.67" + wire $0\logical_op__write_cr0$14[0:0]$9544 + attribute \src "libresoc.v:160238.7-160238.40" + wire $0\logical_op__write_cr0$14[0:0]$9668 + attribute \src "libresoc.v:161187.3-161228.6" + wire $0\logical_op__zero_a$11$next[0:0]$9607 + attribute \src "libresoc.v:160944.3-160945.61" + wire $0\logical_op__zero_a$11[0:0]$9538 + attribute \src "libresoc.v:160247.7-160247.37" + wire $0\logical_op__zero_a$11[0:0]$9670 + attribute \src "libresoc.v:161174.3-161186.6" + wire width 2 $0\muxid$1$next[1:0]$9587 + attribute \src "libresoc.v:160962.3-160963.33" + wire width 2 $0\muxid$1[1:0]$9556 + attribute \src "libresoc.v:160256.13-160256.29" + wire width 2 $0\muxid$1[1:0]$9672 + attribute \src "libresoc.v:161080.3-161098.6" + wire width 64 $0\o$next[63:0]$9559 + attribute \src "libresoc.v:160922.3-160923.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:157665.3-157683.6" - wire $0\o_ok$next[0:0]$9162 - attribute \src "libresoc.v:157509.3-157510.25" + attribute \src "libresoc.v:161080.3-161098.6" + wire $0\o_ok$next[0:0]$9560 + attribute \src "libresoc.v:160924.3-160925.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:157741.3-157758.6" - wire $0\r_busy$next[0:0]$9185 - attribute \src "libresoc.v:157549.3-157550.29" + attribute \src "libresoc.v:161156.3-161173.6" + wire $0\r_busy$next[0:0]$9583 + attribute \src "libresoc.v:160964.3-160965.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:157703.3-157721.6" - wire width 2 $0\xer_ov$next[1:0]$9173 - attribute \src "libresoc.v:157499.3-157500.29" + attribute \src "libresoc.v:161118.3-161136.6" + wire width 2 $0\xer_ov$next[1:0]$9571 + attribute \src "libresoc.v:160914.3-160915.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:157703.3-157721.6" - wire $0\xer_ov_ok$next[0:0]$9174 - attribute \src "libresoc.v:157501.3-157502.35" + attribute \src "libresoc.v:161118.3-161136.6" + wire $0\xer_ov_ok$next[0:0]$9572 + attribute \src "libresoc.v:160916.3-160917.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:157722.3-157740.6" - wire $0\xer_so$20$next[0:0]$9180 - attribute \src "libresoc.v:157495.3-157496.37" - wire $0\xer_so$20[0:0]$9113 - attribute \src "libresoc.v:157480.7-157480.25" - wire $0\xer_so$20[0:0]$9281 - attribute \src "libresoc.v:157722.3-157740.6" - wire $0\xer_so_ok$next[0:0]$9179 - attribute \src "libresoc.v:157497.3-157498.35" + attribute \src "libresoc.v:161137.3-161155.6" + wire $0\xer_so$20$next[0:0]$9578 + attribute \src "libresoc.v:160910.3-160911.37" + wire $0\xer_so$20[0:0]$9511 + attribute \src "libresoc.v:160895.7-160895.25" + wire $0\xer_so$20[0:0]$9679 + attribute \src "libresoc.v:161137.3-161155.6" + wire $0\xer_so_ok$next[0:0]$9577 + attribute \src "libresoc.v:160912.3-160913.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:157684.3-157702.6" - wire width 4 $1\cr_a$next[3:0]$9169 - attribute \src "libresoc.v:156374.13-156374.24" + attribute \src "libresoc.v:161099.3-161117.6" + wire width 4 $1\cr_a$next[3:0]$9567 + attribute \src "libresoc.v:159789.13-159789.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:157684.3-157702.6" - wire $1\cr_a_ok$next[0:0]$9170 - attribute \src "libresoc.v:156383.7-156383.21" + attribute \src "libresoc.v:161099.3-161117.6" + wire $1\cr_a_ok$next[0:0]$9568 + attribute \src "libresoc.v:159798.7-159798.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:157772.3-157813.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9210 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9211 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9212 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9213 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9214 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9215 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9216 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__invert_in$10$next[0:0]$9217 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__invert_out$13$next[0:0]$9218 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9219 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__is_signed$17$next[0:0]$9220 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9221 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9222 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__output_carry$15$next[0:0]$9223 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9224 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9225 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9226 - attribute \src "libresoc.v:157772.3-157813.6" - wire $1\logical_op__zero_a$11$next[0:0]$9227 - attribute \src "libresoc.v:157759.3-157771.6" - wire width 2 $1\muxid$1$next[1:0]$9190 - attribute \src "libresoc.v:157665.3-157683.6" - wire width 64 $1\o$next[63:0]$9163 - attribute \src "libresoc.v:156854.14-156854.38" + attribute \src "libresoc.v:161187.3-161228.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9608 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9609 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9610 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9611 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9612 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9613 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9614 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__invert_in$10$next[0:0]$9615 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__invert_out$13$next[0:0]$9616 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9617 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__is_signed$17$next[0:0]$9618 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9619 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9620 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__output_carry$15$next[0:0]$9621 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9622 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9623 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9624 + attribute \src "libresoc.v:161187.3-161228.6" + wire $1\logical_op__zero_a$11$next[0:0]$9625 + attribute \src "libresoc.v:161174.3-161186.6" + wire width 2 $1\muxid$1$next[1:0]$9588 + attribute \src "libresoc.v:161080.3-161098.6" + wire width 64 $1\o$next[63:0]$9561 + attribute \src "libresoc.v:160269.14-160269.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:157665.3-157683.6" - wire $1\o_ok$next[0:0]$9164 - attribute \src "libresoc.v:156861.7-156861.18" + attribute \src "libresoc.v:161080.3-161098.6" + wire $1\o_ok$next[0:0]$9562 + attribute \src "libresoc.v:160276.7-160276.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:157741.3-157758.6" - wire $1\r_busy$next[0:0]$9186 - attribute \src "libresoc.v:157445.7-157445.20" + attribute \src "libresoc.v:161156.3-161173.6" + wire $1\r_busy$next[0:0]$9584 + attribute \src "libresoc.v:160860.7-160860.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:157703.3-157721.6" - wire width 2 $1\xer_ov$next[1:0]$9175 - attribute \src "libresoc.v:157460.13-157460.26" + attribute \src "libresoc.v:161118.3-161136.6" + wire width 2 $1\xer_ov$next[1:0]$9573 + attribute \src "libresoc.v:160875.13-160875.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:157703.3-157721.6" - wire $1\xer_ov_ok$next[0:0]$9176 - attribute \src "libresoc.v:157467.7-157467.23" + attribute \src "libresoc.v:161118.3-161136.6" + wire $1\xer_ov_ok$next[0:0]$9574 + attribute \src "libresoc.v:160882.7-160882.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:157722.3-157740.6" - wire $1\xer_so$20$next[0:0]$9182 - attribute \src "libresoc.v:157722.3-157740.6" - wire $1\xer_so_ok$next[0:0]$9181 - attribute \src "libresoc.v:157485.7-157485.23" + attribute \src "libresoc.v:161137.3-161155.6" + wire $1\xer_so$20$next[0:0]$9580 + attribute \src "libresoc.v:161137.3-161155.6" + wire $1\xer_so_ok$next[0:0]$9579 + attribute \src "libresoc.v:160900.7-160900.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:157684.3-157702.6" - wire $2\cr_a_ok$next[0:0]$9171 - attribute \src "libresoc.v:157772.3-157813.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9228 - attribute \src "libresoc.v:157772.3-157813.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9229 - attribute \src "libresoc.v:157772.3-157813.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9230 - attribute \src "libresoc.v:157772.3-157813.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9231 - attribute \src "libresoc.v:157772.3-157813.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9232 - attribute \src "libresoc.v:157772.3-157813.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9233 - attribute \src "libresoc.v:157665.3-157683.6" - wire $2\o_ok$next[0:0]$9165 - attribute \src "libresoc.v:157741.3-157758.6" - wire $2\r_busy$next[0:0]$9187 - attribute \src "libresoc.v:157703.3-157721.6" - wire $2\xer_ov_ok$next[0:0]$9177 - attribute \src "libresoc.v:157722.3-157740.6" - wire $2\xer_so_ok$next[0:0]$9183 - attribute \src "libresoc.v:157494.18-157494.118" - wire $and$libresoc.v:157494$9111_Y + attribute \src "libresoc.v:161099.3-161117.6" + wire $2\cr_a_ok$next[0:0]$9569 + attribute \src "libresoc.v:161187.3-161228.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9626 + attribute \src "libresoc.v:161187.3-161228.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9627 + attribute \src "libresoc.v:161187.3-161228.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9628 + attribute \src "libresoc.v:161187.3-161228.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9629 + attribute \src "libresoc.v:161187.3-161228.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9630 + attribute \src "libresoc.v:161187.3-161228.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9631 + attribute \src "libresoc.v:161080.3-161098.6" + wire $2\o_ok$next[0:0]$9563 + attribute \src "libresoc.v:161156.3-161173.6" + wire $2\r_busy$next[0:0]$9585 + attribute \src "libresoc.v:161118.3-161136.6" + wire $2\xer_ov_ok$next[0:0]$9575 + attribute \src "libresoc.v:161137.3-161155.6" + wire $2\xer_so_ok$next[0:0]$9581 + attribute \src "libresoc.v:160909.18-160909.118" + wire $and$libresoc.v:160909$9509_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 56 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 57 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -321641,7 +329560,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:156365.7-156365.15" + attribute \src "libresoc.v:159780.7-159780.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -322074,23 +329993,23 @@ module \pipe_end wire input 34 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \output_cr_a$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \output_logical_op__data_len @@ -322350,13 +330269,13 @@ module \pipe_end wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \output_muxid$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_o_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire \output_stage_div_by_zero @@ -322626,33 +330545,33 @@ module \pipe_end wire width 2 \output_stage_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_stage_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" wire width 64 \output_stage_quotient_root attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_stage_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \output_xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire output 3 \p_ready_o @@ -322678,40 +330597,40 @@ module \pipe_end wire width 64 \rb$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 61 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:157494$9111 + cell $and $and$libresoc.v:160909$9509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322719,17 +330638,17 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:157494$9111_Y + connect \Y $and$libresoc.v:160909$9509_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:157551.10-157554.4" - cell \n$79 \n + attribute \src "libresoc.v:160966.10-160969.4" + cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:157555.15-157607.4" - cell \output$80 \output + attribute \src "libresoc.v:160970.15-161022.4" + cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 connect \cr_a_ok \output_cr_a_ok @@ -322783,7 +330702,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:157608.16-157660.4" + attribute \src "libresoc.v:161023.16-161075.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -322838,451 +330757,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:157661.10-157664.4" - cell \p$78 \p + attribute \src "libresoc.v:161076.10-161079.4" + cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:156365.7-156365.20" - process $proc$libresoc.v:156365$9234 + attribute \src "libresoc.v:159780.7-159780.20" + process $proc$libresoc.v:159780$9632 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156374.13-156374.24" - process $proc$libresoc.v:156374$9235 + attribute \src "libresoc.v:159789.13-159789.24" + process $proc$libresoc.v:159789$9633 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:156383.7-156383.21" - process $proc$libresoc.v:156383$9236 + attribute \src "libresoc.v:159798.7-159798.21" + process $proc$libresoc.v:159798$9634 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:156406.13-156406.45" - process $proc$libresoc.v:156406$9237 + attribute \src "libresoc.v:159821.13-159821.45" + process $proc$libresoc.v:159821$9635 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9238 4'0000 + assign $0\logical_op__data_len$18[3:0]$9636 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9238 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9636 end - attribute \src "libresoc.v:156441.14-156441.47" - process $proc$libresoc.v:156441$9239 + attribute \src "libresoc.v:159856.14-159856.47" + process $proc$libresoc.v:159856$9637 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9240 12'000000000000 + assign $0\logical_op__fn_unit$3[11:0]$9638 12'000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9240 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9638 end - attribute \src "libresoc.v:156463.14-156463.67" - process $proc$libresoc.v:156463$9241 + attribute \src "libresoc.v:159878.14-159878.67" + process $proc$libresoc.v:159878$9639 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9242 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9640 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9242 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9640 end - attribute \src "libresoc.v:156472.7-156472.42" - process $proc$libresoc.v:156472$9243 + attribute \src "libresoc.v:159887.7-159887.42" + process $proc$libresoc.v:159887$9641 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9244 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9642 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9244 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9642 end - attribute \src "libresoc.v:156489.13-156489.48" - process $proc$libresoc.v:156489$9245 + attribute \src "libresoc.v:159904.13-159904.48" + process $proc$libresoc.v:159904$9643 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9246 2'00 + assign $0\logical_op__input_carry$12[1:0]$9644 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9246 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9644 end - attribute \src "libresoc.v:156502.14-156502.43" - process $proc$libresoc.v:156502$9247 + attribute \src "libresoc.v:159917.14-159917.43" + process $proc$libresoc.v:159917$9645 assign { } { } - assign $0\logical_op__insn$19[31:0]$9248 0 + assign $0\logical_op__insn$19[31:0]$9646 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9248 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9646 end - attribute \src "libresoc.v:156659.13-156659.46" - process $proc$libresoc.v:156659$9249 + attribute \src "libresoc.v:160074.13-160074.46" + process $proc$libresoc.v:160074$9647 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9250 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9648 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9250 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9648 end - attribute \src "libresoc.v:156742.7-156742.40" - process $proc$libresoc.v:156742$9251 + attribute \src "libresoc.v:160157.7-160157.40" + process $proc$libresoc.v:160157$9649 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9252 1'0 + assign $0\logical_op__invert_in$10[0:0]$9650 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9252 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9650 end - attribute \src "libresoc.v:156751.7-156751.41" - process $proc$libresoc.v:156751$9253 + attribute \src "libresoc.v:160166.7-160166.41" + process $proc$libresoc.v:160166$9651 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9254 1'0 + assign $0\logical_op__invert_out$13[0:0]$9652 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9254 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9652 end - attribute \src "libresoc.v:156760.7-156760.39" - process $proc$libresoc.v:156760$9255 + attribute \src "libresoc.v:160175.7-160175.39" + process $proc$libresoc.v:160175$9653 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9256 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9654 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9256 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9654 end - attribute \src "libresoc.v:156769.7-156769.40" - process $proc$libresoc.v:156769$9257 + attribute \src "libresoc.v:160184.7-160184.40" + process $proc$libresoc.v:160184$9655 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9258 1'0 + assign $0\logical_op__is_signed$17[0:0]$9656 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9258 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9656 end - attribute \src "libresoc.v:156778.7-156778.36" - process $proc$libresoc.v:156778$9259 + attribute \src "libresoc.v:160193.7-160193.36" + process $proc$libresoc.v:160193$9657 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9260 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9658 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9260 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9658 end - attribute \src "libresoc.v:156789.7-156789.36" - process $proc$libresoc.v:156789$9261 + attribute \src "libresoc.v:160204.7-160204.36" + process $proc$libresoc.v:160204$9659 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9262 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9660 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9262 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9660 end - attribute \src "libresoc.v:156796.7-156796.43" - process $proc$libresoc.v:156796$9263 + attribute \src "libresoc.v:160211.7-160211.43" + process $proc$libresoc.v:160211$9661 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9264 1'0 + assign $0\logical_op__output_carry$15[0:0]$9662 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9264 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9662 end - attribute \src "libresoc.v:156805.7-156805.36" - process $proc$libresoc.v:156805$9265 + attribute \src "libresoc.v:160220.7-160220.36" + process $proc$libresoc.v:160220$9663 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9266 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9664 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9266 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9664 end - attribute \src "libresoc.v:156814.7-156814.36" - process $proc$libresoc.v:156814$9267 + attribute \src "libresoc.v:160229.7-160229.36" + process $proc$libresoc.v:160229$9665 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9268 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9666 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9268 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9666 end - attribute \src "libresoc.v:156823.7-156823.40" - process $proc$libresoc.v:156823$9269 + attribute \src "libresoc.v:160238.7-160238.40" + process $proc$libresoc.v:160238$9667 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9270 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9668 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9270 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9668 end - attribute \src "libresoc.v:156832.7-156832.37" - process $proc$libresoc.v:156832$9271 + attribute \src "libresoc.v:160247.7-160247.37" + process $proc$libresoc.v:160247$9669 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9272 1'0 + assign $0\logical_op__zero_a$11[0:0]$9670 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9272 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9670 end - attribute \src "libresoc.v:156841.13-156841.29" - process $proc$libresoc.v:156841$9273 + attribute \src "libresoc.v:160256.13-160256.29" + process $proc$libresoc.v:160256$9671 assign { } { } - assign $0\muxid$1[1:0]$9274 2'00 + assign $0\muxid$1[1:0]$9672 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9274 + update \muxid$1 $0\muxid$1[1:0]$9672 end - attribute \src "libresoc.v:156854.14-156854.38" - process $proc$libresoc.v:156854$9275 + attribute \src "libresoc.v:160269.14-160269.38" + process $proc$libresoc.v:160269$9673 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:156861.7-156861.18" - process $proc$libresoc.v:156861$9276 + attribute \src "libresoc.v:160276.7-160276.18" + process $proc$libresoc.v:160276$9674 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:157445.7-157445.20" - process $proc$libresoc.v:157445$9277 + attribute \src "libresoc.v:160860.7-160860.20" + process $proc$libresoc.v:160860$9675 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:157460.13-157460.26" - process $proc$libresoc.v:157460$9278 + attribute \src "libresoc.v:160875.13-160875.26" + process $proc$libresoc.v:160875$9676 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:157467.7-157467.23" - process $proc$libresoc.v:157467$9279 + attribute \src "libresoc.v:160882.7-160882.23" + process $proc$libresoc.v:160882$9677 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:157480.7-157480.25" - process $proc$libresoc.v:157480$9280 + attribute \src "libresoc.v:160895.7-160895.25" + process $proc$libresoc.v:160895$9678 assign { } { } - assign $0\xer_so$20[0:0]$9281 1'0 + assign $0\xer_so$20[0:0]$9679 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$9281 + update \xer_so$20 $0\xer_so$20[0:0]$9679 end - attribute \src "libresoc.v:157485.7-157485.23" - process $proc$libresoc.v:157485$9282 + attribute \src "libresoc.v:160900.7-160900.23" + process $proc$libresoc.v:160900$9680 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:157495.3-157496.37" - process $proc$libresoc.v:157495$9112 + attribute \src "libresoc.v:160910.3-160911.37" + process $proc$libresoc.v:160910$9510 assign { } { } - assign $0\xer_so$20[0:0]$9113 \xer_so$20$next + assign $0\xer_so$20[0:0]$9511 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9113 + update \xer_so$20 $0\xer_so$20[0:0]$9511 end - attribute \src "libresoc.v:157497.3-157498.35" - process $proc$libresoc.v:157497$9114 + attribute \src "libresoc.v:160912.3-160913.35" + process $proc$libresoc.v:160912$9512 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:157499.3-157500.29" - process $proc$libresoc.v:157499$9115 + attribute \src "libresoc.v:160914.3-160915.29" + process $proc$libresoc.v:160914$9513 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:157501.3-157502.35" - process $proc$libresoc.v:157501$9116 + attribute \src "libresoc.v:160916.3-160917.35" + process $proc$libresoc.v:160916$9514 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:157503.3-157504.25" - process $proc$libresoc.v:157503$9117 + attribute \src "libresoc.v:160918.3-160919.25" + process $proc$libresoc.v:160918$9515 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:157505.3-157506.31" - process $proc$libresoc.v:157505$9118 + attribute \src "libresoc.v:160920.3-160921.31" + process $proc$libresoc.v:160920$9516 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:157507.3-157508.19" - process $proc$libresoc.v:157507$9119 + attribute \src "libresoc.v:160922.3-160923.19" + process $proc$libresoc.v:160922$9517 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:157509.3-157510.25" - process $proc$libresoc.v:157509$9120 + attribute \src "libresoc.v:160924.3-160925.25" + process $proc$libresoc.v:160924$9518 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:157511.3-157512.65" - process $proc$libresoc.v:157511$9121 + attribute \src "libresoc.v:160926.3-160927.65" + process $proc$libresoc.v:160926$9519 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9122 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9520 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9122 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9520 end - attribute \src "libresoc.v:157513.3-157514.61" - process $proc$libresoc.v:157513$9123 + attribute \src "libresoc.v:160928.3-160929.61" + process $proc$libresoc.v:160928$9521 assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9124 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[11:0]$9522 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9124 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9522 end - attribute \src "libresoc.v:157515.3-157516.75" - process $proc$libresoc.v:157515$9125 + attribute \src "libresoc.v:160930.3-160931.75" + process $proc$libresoc.v:160930$9523 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9126 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9524 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9126 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9524 end - attribute \src "libresoc.v:157517.3-157518.71" - process $proc$libresoc.v:157517$9127 + attribute \src "libresoc.v:160932.3-160933.71" + process $proc$libresoc.v:160932$9525 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9128 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9526 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9128 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9526 end - attribute \src "libresoc.v:157519.3-157520.59" - process $proc$libresoc.v:157519$9129 + attribute \src "libresoc.v:160934.3-160935.59" + process $proc$libresoc.v:160934$9527 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9130 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9528 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9130 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9528 end - attribute \src "libresoc.v:157521.3-157522.59" - process $proc$libresoc.v:157521$9131 + attribute \src "libresoc.v:160936.3-160937.59" + process $proc$libresoc.v:160936$9529 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9132 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9530 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9132 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9530 end - attribute \src "libresoc.v:157523.3-157524.59" - process $proc$libresoc.v:157523$9133 + attribute \src "libresoc.v:160938.3-160939.59" + process $proc$libresoc.v:160938$9531 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9134 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9532 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9134 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9532 end - attribute \src "libresoc.v:157525.3-157526.59" - process $proc$libresoc.v:157525$9135 + attribute \src "libresoc.v:160940.3-160941.59" + process $proc$libresoc.v:160940$9533 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9136 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9534 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9136 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9534 end - attribute \src "libresoc.v:157527.3-157528.67" - process $proc$libresoc.v:157527$9137 + attribute \src "libresoc.v:160942.3-160943.67" + process $proc$libresoc.v:160942$9535 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9138 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9536 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9138 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9536 end - attribute \src "libresoc.v:157529.3-157530.61" - process $proc$libresoc.v:157529$9139 + attribute \src "libresoc.v:160944.3-160945.61" + process $proc$libresoc.v:160944$9537 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9140 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9538 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9140 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9538 end - attribute \src "libresoc.v:157531.3-157532.71" - process $proc$libresoc.v:157531$9141 + attribute \src "libresoc.v:160946.3-160947.71" + process $proc$libresoc.v:160946$9539 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9142 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9540 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9142 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9540 end - attribute \src "libresoc.v:157533.3-157534.69" - process $proc$libresoc.v:157533$9143 + attribute \src "libresoc.v:160948.3-160949.69" + process $proc$libresoc.v:160948$9541 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9144 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9542 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9144 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9542 end - attribute \src "libresoc.v:157535.3-157536.67" - process $proc$libresoc.v:157535$9145 + attribute \src "libresoc.v:160950.3-160951.67" + process $proc$libresoc.v:160950$9543 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9146 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9544 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9146 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9544 end - attribute \src "libresoc.v:157537.3-157538.73" - process $proc$libresoc.v:157537$9147 + attribute \src "libresoc.v:160952.3-160953.73" + process $proc$libresoc.v:160952$9545 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9148 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9546 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9148 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9546 end - attribute \src "libresoc.v:157539.3-157540.65" - process $proc$libresoc.v:157539$9149 + attribute \src "libresoc.v:160954.3-160955.65" + process $proc$libresoc.v:160954$9547 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9150 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9548 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9150 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9548 end - attribute \src "libresoc.v:157541.3-157542.67" - process $proc$libresoc.v:157541$9151 + attribute \src "libresoc.v:160956.3-160957.67" + process $proc$libresoc.v:160956$9549 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9152 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9550 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9152 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9550 end - attribute \src "libresoc.v:157543.3-157544.65" - process $proc$libresoc.v:157543$9153 + attribute \src "libresoc.v:160958.3-160959.65" + process $proc$libresoc.v:160958$9551 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9154 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9552 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9154 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9552 end - attribute \src "libresoc.v:157545.3-157546.57" - process $proc$libresoc.v:157545$9155 + attribute \src "libresoc.v:160960.3-160961.57" + process $proc$libresoc.v:160960$9553 assign { } { } - assign $0\logical_op__insn$19[31:0]$9156 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9554 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9156 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9554 end - attribute \src "libresoc.v:157547.3-157548.33" - process $proc$libresoc.v:157547$9157 + attribute \src "libresoc.v:160962.3-160963.33" + process $proc$libresoc.v:160962$9555 assign { } { } - assign $0\muxid$1[1:0]$9158 \muxid$1$next + assign $0\muxid$1[1:0]$9556 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9158 + update \muxid$1 $0\muxid$1[1:0]$9556 end - attribute \src "libresoc.v:157549.3-157550.29" - process $proc$libresoc.v:157549$9159 + attribute \src "libresoc.v:160964.3-160965.29" + process $proc$libresoc.v:160964$9557 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:157665.3-157683.6" - process $proc$libresoc.v:157665$9160 + attribute \src "libresoc.v:161080.3-161098.6" + process $proc$libresoc.v:161080$9558 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9161 $1\o$next[63:0]$9163 + assign $0\o$next[63:0]$9559 $1\o$next[63:0]$9561 assign { } { } - assign $0\o_ok$next[0:0]$9162 $2\o_ok$next[0:0]$9165 - attribute \src "libresoc.v:157666.5-157666.29" + assign $0\o_ok$next[0:0]$9560 $2\o_ok$next[0:0]$9563 + attribute \src "libresoc.v:161081.5-161081.29" switch \initial - attribute \src "libresoc.v:157666.9-157666.17" + attribute \src "libresoc.v:161081.9-161081.17" case 1'1 case end @@ -323292,41 +331211,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9164 $1\o$next[63:0]$9163 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9562 $1\o$next[63:0]$9561 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9164 $1\o$next[63:0]$9163 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9562 $1\o$next[63:0]$9561 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9163 \o - assign $1\o_ok$next[0:0]$9164 \o_ok + assign $1\o$next[63:0]$9561 \o + assign $1\o_ok$next[0:0]$9562 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9165 1'0 + assign $2\o_ok$next[0:0]$9563 1'0 case - assign $2\o_ok$next[0:0]$9165 $1\o_ok$next[0:0]$9164 + assign $2\o_ok$next[0:0]$9563 $1\o_ok$next[0:0]$9562 end sync always - update \o$next $0\o$next[63:0]$9161 - update \o_ok$next $0\o_ok$next[0:0]$9162 + update \o$next $0\o$next[63:0]$9559 + update \o_ok$next $0\o_ok$next[0:0]$9560 end - attribute \src "libresoc.v:157684.3-157702.6" - process $proc$libresoc.v:157684$9166 + attribute \src "libresoc.v:161099.3-161117.6" + process $proc$libresoc.v:161099$9564 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9167 $1\cr_a$next[3:0]$9169 + assign $0\cr_a$next[3:0]$9565 $1\cr_a$next[3:0]$9567 assign { } { } - assign $0\cr_a_ok$next[0:0]$9168 $2\cr_a_ok$next[0:0]$9171 - attribute \src "libresoc.v:157685.5-157685.29" + assign $0\cr_a_ok$next[0:0]$9566 $2\cr_a_ok$next[0:0]$9569 + attribute \src "libresoc.v:161100.5-161100.29" switch \initial - attribute \src "libresoc.v:157685.9-157685.17" + attribute \src "libresoc.v:161100.9-161100.17" case 1'1 case end @@ -323336,41 +331255,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9170 $1\cr_a$next[3:0]$9169 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9568 $1\cr_a$next[3:0]$9567 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9170 $1\cr_a$next[3:0]$9169 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9568 $1\cr_a$next[3:0]$9567 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9169 \cr_a - assign $1\cr_a_ok$next[0:0]$9170 \cr_a_ok + assign $1\cr_a$next[3:0]$9567 \cr_a + assign $1\cr_a_ok$next[0:0]$9568 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9171 1'0 + assign $2\cr_a_ok$next[0:0]$9569 1'0 case - assign $2\cr_a_ok$next[0:0]$9171 $1\cr_a_ok$next[0:0]$9170 + assign $2\cr_a_ok$next[0:0]$9569 $1\cr_a_ok$next[0:0]$9568 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9167 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9168 + update \cr_a$next $0\cr_a$next[3:0]$9565 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9566 end - attribute \src "libresoc.v:157703.3-157721.6" - process $proc$libresoc.v:157703$9172 + attribute \src "libresoc.v:161118.3-161136.6" + process $proc$libresoc.v:161118$9570 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9173 $1\xer_ov$next[1:0]$9175 + assign $0\xer_ov$next[1:0]$9571 $1\xer_ov$next[1:0]$9573 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9174 $2\xer_ov_ok$next[0:0]$9177 - attribute \src "libresoc.v:157704.5-157704.29" + assign $0\xer_ov_ok$next[0:0]$9572 $2\xer_ov_ok$next[0:0]$9575 + attribute \src "libresoc.v:161119.5-161119.29" switch \initial - attribute \src "libresoc.v:157704.9-157704.17" + attribute \src "libresoc.v:161119.9-161119.17" case 1'1 case end @@ -323380,41 +331299,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9176 $1\xer_ov$next[1:0]$9175 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9574 $1\xer_ov$next[1:0]$9573 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9176 $1\xer_ov$next[1:0]$9175 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9574 $1\xer_ov$next[1:0]$9573 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9175 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9176 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9573 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9574 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9177 1'0 + assign $2\xer_ov_ok$next[0:0]$9575 1'0 case - assign $2\xer_ov_ok$next[0:0]$9177 $1\xer_ov_ok$next[0:0]$9176 + assign $2\xer_ov_ok$next[0:0]$9575 $1\xer_ov_ok$next[0:0]$9574 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9173 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9174 + update \xer_ov$next $0\xer_ov$next[1:0]$9571 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9572 end - attribute \src "libresoc.v:157722.3-157740.6" - process $proc$libresoc.v:157722$9178 + attribute \src "libresoc.v:161137.3-161155.6" + process $proc$libresoc.v:161137$9576 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9180 $1\xer_so$20$next[0:0]$9182 - assign $0\xer_so_ok$next[0:0]$9179 $2\xer_so_ok$next[0:0]$9183 - attribute \src "libresoc.v:157723.5-157723.29" + assign $0\xer_so$20$next[0:0]$9578 $1\xer_so$20$next[0:0]$9580 + assign $0\xer_so_ok$next[0:0]$9577 $2\xer_so_ok$next[0:0]$9581 + attribute \src "libresoc.v:161138.5-161138.29" switch \initial - attribute \src "libresoc.v:157723.9-157723.17" + attribute \src "libresoc.v:161138.9-161138.17" case 1'1 case end @@ -323424,38 +331343,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$20$next[0:0]$9182 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9579 $1\xer_so$20$next[0:0]$9580 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9181 $1\xer_so$20$next[0:0]$9182 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9579 $1\xer_so$20$next[0:0]$9580 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9181 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9182 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9579 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9580 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9183 1'0 + assign $2\xer_so_ok$next[0:0]$9581 1'0 case - assign $2\xer_so_ok$next[0:0]$9183 $1\xer_so_ok$next[0:0]$9181 + assign $2\xer_so_ok$next[0:0]$9581 $1\xer_so_ok$next[0:0]$9579 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9179 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9180 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9577 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9578 end - attribute \src "libresoc.v:157741.3-157758.6" - process $proc$libresoc.v:157741$9184 + attribute \src "libresoc.v:161156.3-161173.6" + process $proc$libresoc.v:161156$9582 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9185 $2\r_busy$next[0:0]$9187 - attribute \src "libresoc.v:157742.5-157742.29" + assign $0\r_busy$next[0:0]$9583 $2\r_busy$next[0:0]$9585 + attribute \src "libresoc.v:161157.5-161157.29" switch \initial - attribute \src "libresoc.v:157742.9-157742.17" + attribute \src "libresoc.v:161157.9-161157.17" case 1'1 case end @@ -323464,34 +331383,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9186 1'1 + assign $1\r_busy$next[0:0]$9584 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9186 1'0 + assign $1\r_busy$next[0:0]$9584 1'0 case - assign $1\r_busy$next[0:0]$9186 \r_busy + assign $1\r_busy$next[0:0]$9584 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9187 1'0 + assign $2\r_busy$next[0:0]$9585 1'0 case - assign $2\r_busy$next[0:0]$9187 $1\r_busy$next[0:0]$9186 + assign $2\r_busy$next[0:0]$9585 $1\r_busy$next[0:0]$9584 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9185 + update \r_busy$next $0\r_busy$next[0:0]$9583 end - attribute \src "libresoc.v:157759.3-157771.6" - process $proc$libresoc.v:157759$9188 + attribute \src "libresoc.v:161174.3-161186.6" + process $proc$libresoc.v:161174$9586 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9189 $1\muxid$1$next[1:0]$9190 - attribute \src "libresoc.v:157760.5-157760.29" + assign $0\muxid$1$next[1:0]$9587 $1\muxid$1$next[1:0]$9588 + attribute \src "libresoc.v:161175.5-161175.29" switch \initial - attribute \src "libresoc.v:157760.9-157760.17" + attribute \src "libresoc.v:161175.9-161175.17" case 1'1 case end @@ -323500,19 +331419,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9190 \muxid$76 + assign $1\muxid$1$next[1:0]$9588 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9190 \muxid$76 + assign $1\muxid$1$next[1:0]$9588 \muxid$76 case - assign $1\muxid$1$next[1:0]$9190 \muxid$1 + assign $1\muxid$1$next[1:0]$9588 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9189 + update \muxid$1$next $0\muxid$1$next[1:0]$9587 end - attribute \src "libresoc.v:157772.3-157813.6" - process $proc$libresoc.v:157772$9191 + attribute \src "libresoc.v:161187.3-161228.6" + process $proc$libresoc.v:161187$9589 assign { } { } assign { } { } assign { } { } @@ -323549,33 +331468,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9192 $1\logical_op__data_len$18$next[3:0]$9210 - assign $0\logical_op__fn_unit$3$next[11:0]$9193 $1\logical_op__fn_unit$3$next[11:0]$9211 + assign $0\logical_op__data_len$18$next[3:0]$9590 $1\logical_op__data_len$18$next[3:0]$9608 + assign $0\logical_op__fn_unit$3$next[11:0]$9591 $1\logical_op__fn_unit$3$next[11:0]$9609 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9196 $1\logical_op__input_carry$12$next[1:0]$9214 - assign $0\logical_op__insn$19$next[31:0]$9197 $1\logical_op__insn$19$next[31:0]$9215 - assign $0\logical_op__insn_type$2$next[6:0]$9198 $1\logical_op__insn_type$2$next[6:0]$9216 - assign $0\logical_op__invert_in$10$next[0:0]$9199 $1\logical_op__invert_in$10$next[0:0]$9217 - assign $0\logical_op__invert_out$13$next[0:0]$9200 $1\logical_op__invert_out$13$next[0:0]$9218 - assign $0\logical_op__is_32bit$16$next[0:0]$9201 $1\logical_op__is_32bit$16$next[0:0]$9219 - assign $0\logical_op__is_signed$17$next[0:0]$9202 $1\logical_op__is_signed$17$next[0:0]$9220 + assign $0\logical_op__input_carry$12$next[1:0]$9594 $1\logical_op__input_carry$12$next[1:0]$9612 + assign $0\logical_op__insn$19$next[31:0]$9595 $1\logical_op__insn$19$next[31:0]$9613 + assign $0\logical_op__insn_type$2$next[6:0]$9596 $1\logical_op__insn_type$2$next[6:0]$9614 + assign $0\logical_op__invert_in$10$next[0:0]$9597 $1\logical_op__invert_in$10$next[0:0]$9615 + assign $0\logical_op__invert_out$13$next[0:0]$9598 $1\logical_op__invert_out$13$next[0:0]$9616 + assign $0\logical_op__is_32bit$16$next[0:0]$9599 $1\logical_op__is_32bit$16$next[0:0]$9617 + assign $0\logical_op__is_signed$17$next[0:0]$9600 $1\logical_op__is_signed$17$next[0:0]$9618 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9205 $1\logical_op__output_carry$15$next[0:0]$9223 + assign $0\logical_op__output_carry$15$next[0:0]$9603 $1\logical_op__output_carry$15$next[0:0]$9621 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9208 $1\logical_op__write_cr0$14$next[0:0]$9226 - assign $0\logical_op__zero_a$11$next[0:0]$9209 $1\logical_op__zero_a$11$next[0:0]$9227 - assign $0\logical_op__imm_data__data$4$next[63:0]$9194 $2\logical_op__imm_data__data$4$next[63:0]$9228 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9195 $2\logical_op__imm_data__ok$5$next[0:0]$9229 - assign $0\logical_op__oe__oe$8$next[0:0]$9203 $2\logical_op__oe__oe$8$next[0:0]$9230 - assign $0\logical_op__oe__ok$9$next[0:0]$9204 $2\logical_op__oe__ok$9$next[0:0]$9231 - assign $0\logical_op__rc__ok$7$next[0:0]$9206 $2\logical_op__rc__ok$7$next[0:0]$9232 - assign $0\logical_op__rc__rc$6$next[0:0]$9207 $2\logical_op__rc__rc$6$next[0:0]$9233 - attribute \src "libresoc.v:157773.5-157773.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9606 $1\logical_op__write_cr0$14$next[0:0]$9624 + assign $0\logical_op__zero_a$11$next[0:0]$9607 $1\logical_op__zero_a$11$next[0:0]$9625 + assign $0\logical_op__imm_data__data$4$next[63:0]$9592 $2\logical_op__imm_data__data$4$next[63:0]$9626 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9593 $2\logical_op__imm_data__ok$5$next[0:0]$9627 + assign $0\logical_op__oe__oe$8$next[0:0]$9601 $2\logical_op__oe__oe$8$next[0:0]$9628 + assign $0\logical_op__oe__ok$9$next[0:0]$9602 $2\logical_op__oe__ok$9$next[0:0]$9629 + assign $0\logical_op__rc__ok$7$next[0:0]$9604 $2\logical_op__rc__ok$7$next[0:0]$9630 + assign $0\logical_op__rc__rc$6$next[0:0]$9605 $2\logical_op__rc__rc$6$next[0:0]$9631 + attribute \src "libresoc.v:161188.5-161188.29" switch \initial - attribute \src "libresoc.v:157773.9-157773.17" + attribute \src "libresoc.v:161188.9-161188.17" case 1'1 case end @@ -323601,7 +331520,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9215 $1\logical_op__data_len$18$next[3:0]$9210 $1\logical_op__is_signed$17$next[0:0]$9220 $1\logical_op__is_32bit$16$next[0:0]$9219 $1\logical_op__output_carry$15$next[0:0]$9223 $1\logical_op__write_cr0$14$next[0:0]$9226 $1\logical_op__invert_out$13$next[0:0]$9218 $1\logical_op__input_carry$12$next[1:0]$9214 $1\logical_op__zero_a$11$next[0:0]$9227 $1\logical_op__invert_in$10$next[0:0]$9217 $1\logical_op__oe__ok$9$next[0:0]$9222 $1\logical_op__oe__oe$8$next[0:0]$9221 $1\logical_op__rc__ok$7$next[0:0]$9224 $1\logical_op__rc__rc$6$next[0:0]$9225 $1\logical_op__imm_data__ok$5$next[0:0]$9213 $1\logical_op__imm_data__data$4$next[63:0]$9212 $1\logical_op__fn_unit$3$next[11:0]$9211 $1\logical_op__insn_type$2$next[6:0]$9216 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9613 $1\logical_op__data_len$18$next[3:0]$9608 $1\logical_op__is_signed$17$next[0:0]$9618 $1\logical_op__is_32bit$16$next[0:0]$9617 $1\logical_op__output_carry$15$next[0:0]$9621 $1\logical_op__write_cr0$14$next[0:0]$9624 $1\logical_op__invert_out$13$next[0:0]$9616 $1\logical_op__input_carry$12$next[1:0]$9612 $1\logical_op__zero_a$11$next[0:0]$9625 $1\logical_op__invert_in$10$next[0:0]$9615 $1\logical_op__oe__ok$9$next[0:0]$9620 $1\logical_op__oe__oe$8$next[0:0]$9619 $1\logical_op__rc__ok$7$next[0:0]$9622 $1\logical_op__rc__rc$6$next[0:0]$9623 $1\logical_op__imm_data__ok$5$next[0:0]$9611 $1\logical_op__imm_data__data$4$next[63:0]$9610 $1\logical_op__fn_unit$3$next[11:0]$9609 $1\logical_op__insn_type$2$next[6:0]$9614 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -323622,26 +331541,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9215 $1\logical_op__data_len$18$next[3:0]$9210 $1\logical_op__is_signed$17$next[0:0]$9220 $1\logical_op__is_32bit$16$next[0:0]$9219 $1\logical_op__output_carry$15$next[0:0]$9223 $1\logical_op__write_cr0$14$next[0:0]$9226 $1\logical_op__invert_out$13$next[0:0]$9218 $1\logical_op__input_carry$12$next[1:0]$9214 $1\logical_op__zero_a$11$next[0:0]$9227 $1\logical_op__invert_in$10$next[0:0]$9217 $1\logical_op__oe__ok$9$next[0:0]$9222 $1\logical_op__oe__oe$8$next[0:0]$9221 $1\logical_op__rc__ok$7$next[0:0]$9224 $1\logical_op__rc__rc$6$next[0:0]$9225 $1\logical_op__imm_data__ok$5$next[0:0]$9213 $1\logical_op__imm_data__data$4$next[63:0]$9212 $1\logical_op__fn_unit$3$next[11:0]$9211 $1\logical_op__insn_type$2$next[6:0]$9216 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9613 $1\logical_op__data_len$18$next[3:0]$9608 $1\logical_op__is_signed$17$next[0:0]$9618 $1\logical_op__is_32bit$16$next[0:0]$9617 $1\logical_op__output_carry$15$next[0:0]$9621 $1\logical_op__write_cr0$14$next[0:0]$9624 $1\logical_op__invert_out$13$next[0:0]$9616 $1\logical_op__input_carry$12$next[1:0]$9612 $1\logical_op__zero_a$11$next[0:0]$9625 $1\logical_op__invert_in$10$next[0:0]$9615 $1\logical_op__oe__ok$9$next[0:0]$9620 $1\logical_op__oe__oe$8$next[0:0]$9619 $1\logical_op__rc__ok$7$next[0:0]$9622 $1\logical_op__rc__rc$6$next[0:0]$9623 $1\logical_op__imm_data__ok$5$next[0:0]$9611 $1\logical_op__imm_data__data$4$next[63:0]$9610 $1\logical_op__fn_unit$3$next[11:0]$9609 $1\logical_op__insn_type$2$next[6:0]$9614 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9210 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$9211 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9212 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9213 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9214 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9215 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9216 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9217 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9218 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9219 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9220 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9221 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9222 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9223 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9224 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9225 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9226 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9227 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9608 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$9609 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9610 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9611 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9612 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9613 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9614 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9615 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9616 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9617 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9618 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9619 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9620 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9621 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9622 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9623 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9624 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9625 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -323653,41 +331572,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9228 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9229 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9233 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9232 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9230 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9231 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9626 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9627 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9631 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9630 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9628 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9629 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9228 $1\logical_op__imm_data__data$4$next[63:0]$9212 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9229 $1\logical_op__imm_data__ok$5$next[0:0]$9213 - assign $2\logical_op__oe__oe$8$next[0:0]$9230 $1\logical_op__oe__oe$8$next[0:0]$9221 - assign $2\logical_op__oe__ok$9$next[0:0]$9231 $1\logical_op__oe__ok$9$next[0:0]$9222 - assign $2\logical_op__rc__ok$7$next[0:0]$9232 $1\logical_op__rc__ok$7$next[0:0]$9224 - assign $2\logical_op__rc__rc$6$next[0:0]$9233 $1\logical_op__rc__rc$6$next[0:0]$9225 + assign $2\logical_op__imm_data__data$4$next[63:0]$9626 $1\logical_op__imm_data__data$4$next[63:0]$9610 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9627 $1\logical_op__imm_data__ok$5$next[0:0]$9611 + assign $2\logical_op__oe__oe$8$next[0:0]$9628 $1\logical_op__oe__oe$8$next[0:0]$9619 + assign $2\logical_op__oe__ok$9$next[0:0]$9629 $1\logical_op__oe__ok$9$next[0:0]$9620 + assign $2\logical_op__rc__ok$7$next[0:0]$9630 $1\logical_op__rc__ok$7$next[0:0]$9622 + assign $2\logical_op__rc__rc$6$next[0:0]$9631 $1\logical_op__rc__rc$6$next[0:0]$9623 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9192 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9193 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9194 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9195 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9196 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9197 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9198 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9199 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9200 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9201 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9202 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9203 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9204 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9205 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9206 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9207 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9208 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9209 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9590 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9591 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9592 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9593 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9594 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9595 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9596 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9597 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9598 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9599 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9600 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9601 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9602 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9603 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9604 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9605 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9606 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9607 end - connect \$74 $and$libresoc.v:157494$9111_Y + connect \$74 $and$libresoc.v:160909$9509_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -323721,396 +331640,396 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:157850.1-158828.10" +attribute \src "libresoc.v:161265.1-162243.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:158753.3-158767.6" - wire $0\div_by_zero$54$next[0:0]$9462 - attribute \src "libresoc.v:158427.3-158428.47" - wire $0\div_by_zero$54[0:0]$9297 - attribute \src "libresoc.v:157873.7-157873.30" - wire $0\div_by_zero$54[0:0]$9479 - attribute \src "libresoc.v:158549.3-158560.6" + attribute \src "libresoc.v:162168.3-162182.6" + wire $0\div_by_zero$54$next[0:0]$9860 + attribute \src "libresoc.v:161842.3-161843.47" + wire $0\div_by_zero$54[0:0]$9695 + attribute \src "libresoc.v:161288.7-161288.30" + wire $0\div_by_zero$54[0:0]$9877 + attribute \src "libresoc.v:161964.3-161975.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:158537.3-158548.6" + attribute \src "libresoc.v:161952.3-161963.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:158525.3-158536.6" + attribute \src "libresoc.v:161940.3-161951.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:158723.3-158737.6" - wire $0\dive_abs_ov32$52$next[0:0]$9454 - attribute \src "libresoc.v:158431.3-158432.51" - wire $0\dive_abs_ov32$52[0:0]$9301 - attribute \src "libresoc.v:157897.7-157897.32" - wire $0\dive_abs_ov32$52[0:0]$9481 - attribute \src "libresoc.v:158738.3-158752.6" - wire $0\dive_abs_ov64$53$next[0:0]$9458 - attribute \src "libresoc.v:158429.3-158430.51" - wire $0\dive_abs_ov64$53[0:0]$9299 - attribute \src "libresoc.v:157905.7-157905.32" - wire $0\dive_abs_ov64$53[0:0]$9483 - attribute \src "libresoc.v:158768.3-158782.6" - wire width 128 $0\dividend$68$next[127:0]$9466 - attribute \src "libresoc.v:158425.3-158426.41" - wire width 128 $0\dividend$68[127:0]$9295 - attribute \src "libresoc.v:157911.15-157911.68" - wire width 128 $0\dividend$68[127:0]$9485 - attribute \src "libresoc.v:158708.3-158722.6" - wire $0\dividend_neg$51$next[0:0]$9450 - attribute \src "libresoc.v:158433.3-158434.49" - wire $0\dividend_neg$51[0:0]$9303 - attribute \src "libresoc.v:157919.7-157919.31" - wire $0\dividend_neg$51[0:0]$9487 - attribute \src "libresoc.v:158693.3-158707.6" - wire $0\divisor_neg$50$next[0:0]$9446 - attribute \src "libresoc.v:158435.3-158436.47" - wire $0\divisor_neg$50[0:0]$9305 - attribute \src "libresoc.v:157927.7-157927.30" - wire $0\divisor_neg$50[0:0]$9489 - attribute \src "libresoc.v:158783.3-158797.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$9470 - attribute \src "libresoc.v:158423.3-158424.57" - wire width 64 $0\divisor_radicand$65[63:0]$9293 - attribute \src "libresoc.v:157933.14-157933.58" - wire width 64 $0\divisor_radicand$65[63:0]$9491 - attribute \src "libresoc.v:158561.3-158588.6" - wire $0\empty$next[0:0]$9363 - attribute \src "libresoc.v:158481.3-158482.27" + attribute \src "libresoc.v:162138.3-162152.6" + wire $0\dive_abs_ov32$52$next[0:0]$9852 + attribute \src "libresoc.v:161846.3-161847.51" + wire $0\dive_abs_ov32$52[0:0]$9699 + attribute \src "libresoc.v:161312.7-161312.32" + wire $0\dive_abs_ov32$52[0:0]$9879 + attribute \src "libresoc.v:162153.3-162167.6" + wire $0\dive_abs_ov64$53$next[0:0]$9856 + attribute \src "libresoc.v:161844.3-161845.51" + wire $0\dive_abs_ov64$53[0:0]$9697 + attribute \src "libresoc.v:161320.7-161320.32" + wire $0\dive_abs_ov64$53[0:0]$9881 + attribute \src "libresoc.v:162183.3-162197.6" + wire width 128 $0\dividend$68$next[127:0]$9864 + attribute \src "libresoc.v:161840.3-161841.41" + wire width 128 $0\dividend$68[127:0]$9693 + attribute \src "libresoc.v:161326.15-161326.68" + wire width 128 $0\dividend$68[127:0]$9883 + attribute \src "libresoc.v:162123.3-162137.6" + wire $0\dividend_neg$51$next[0:0]$9848 + attribute \src "libresoc.v:161848.3-161849.49" + wire $0\dividend_neg$51[0:0]$9701 + attribute \src "libresoc.v:161334.7-161334.31" + wire $0\dividend_neg$51[0:0]$9885 + attribute \src "libresoc.v:162108.3-162122.6" + wire $0\divisor_neg$50$next[0:0]$9844 + attribute \src "libresoc.v:161850.3-161851.47" + wire $0\divisor_neg$50[0:0]$9703 + attribute \src "libresoc.v:161342.7-161342.30" + wire $0\divisor_neg$50[0:0]$9887 + attribute \src "libresoc.v:162198.3-162212.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$9868 + attribute \src "libresoc.v:161838.3-161839.57" + wire width 64 $0\divisor_radicand$65[63:0]$9691 + attribute \src "libresoc.v:161348.14-161348.58" + wire width 64 $0\divisor_radicand$65[63:0]$9889 + attribute \src "libresoc.v:161976.3-162003.6" + wire $0\empty$next[0:0]$9761 + attribute \src "libresoc.v:161896.3-161897.27" wire $0\empty[0:0] - attribute \src "libresoc.v:157851.7-157851.20" + attribute \src "libresoc.v:161266.7-161266.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158604.3-158647.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$9373 - attribute \src "libresoc.v:158475.3-158476.65" - wire width 4 $0\logical_op__data_len$45[3:0]$9345 - attribute \src "libresoc.v:157945.13-157945.45" - wire width 4 $0\logical_op__data_len$45[3:0]$9494 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9374 - attribute \src "libresoc.v:158445.3-158446.63" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9315 - attribute \src "libresoc.v:157992.14-157992.48" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9496 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9375 - attribute \src "libresoc.v:158447.3-158448.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9317 - attribute \src "libresoc.v:157998.14-157998.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9498 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$9376 - attribute \src "libresoc.v:158449.3-158450.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9319 - attribute \src "libresoc.v:158006.7-158006.43" - wire $0\logical_op__imm_data__ok$32[0:0]$9500 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$9377 - attribute \src "libresoc.v:158463.3-158464.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$9333 - attribute \src "libresoc.v:158028.13-158028.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$9502 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$9378 - attribute \src "libresoc.v:158477.3-158478.57" - wire width 32 $0\logical_op__insn$46[31:0]$9347 - attribute \src "libresoc.v:158036.14-158036.43" - wire width 32 $0\logical_op__insn$46[31:0]$9504 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$9379 - attribute \src "libresoc.v:158443.3-158444.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9313 - attribute \src "libresoc.v:158266.13-158266.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$9506 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__invert_in$37$next[0:0]$9380 - attribute \src "libresoc.v:158459.3-158460.67" - wire $0\logical_op__invert_in$37[0:0]$9329 - attribute \src "libresoc.v:158274.7-158274.40" - wire $0\logical_op__invert_in$37[0:0]$9508 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__invert_out$40$next[0:0]$9381 - attribute \src "libresoc.v:158465.3-158466.69" - wire $0\logical_op__invert_out$40[0:0]$9335 - attribute \src "libresoc.v:158282.7-158282.41" - wire $0\logical_op__invert_out$40[0:0]$9510 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__is_32bit$43$next[0:0]$9382 - attribute \src "libresoc.v:158471.3-158472.65" - wire $0\logical_op__is_32bit$43[0:0]$9341 - attribute \src "libresoc.v:158290.7-158290.39" - wire $0\logical_op__is_32bit$43[0:0]$9512 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__is_signed$44$next[0:0]$9383 - attribute \src "libresoc.v:158473.3-158474.67" - wire $0\logical_op__is_signed$44[0:0]$9343 - attribute \src "libresoc.v:158298.7-158298.40" - wire $0\logical_op__is_signed$44[0:0]$9514 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__oe__oe$35$next[0:0]$9384 - attribute \src "libresoc.v:158455.3-158456.61" - wire $0\logical_op__oe__oe$35[0:0]$9325 - attribute \src "libresoc.v:158304.7-158304.37" - wire $0\logical_op__oe__oe$35[0:0]$9516 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__oe__ok$36$next[0:0]$9385 - attribute \src "libresoc.v:158457.3-158458.61" - wire $0\logical_op__oe__ok$36[0:0]$9327 - attribute \src "libresoc.v:158312.7-158312.37" - wire $0\logical_op__oe__ok$36[0:0]$9518 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__output_carry$42$next[0:0]$9386 - attribute \src "libresoc.v:158469.3-158470.73" - wire $0\logical_op__output_carry$42[0:0]$9339 - attribute \src "libresoc.v:158322.7-158322.43" - wire $0\logical_op__output_carry$42[0:0]$9520 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__rc__ok$34$next[0:0]$9387 - attribute \src "libresoc.v:158453.3-158454.61" - wire $0\logical_op__rc__ok$34[0:0]$9323 - attribute \src "libresoc.v:158328.7-158328.37" - wire $0\logical_op__rc__ok$34[0:0]$9522 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__rc__rc$33$next[0:0]$9388 - attribute \src "libresoc.v:158451.3-158452.61" - wire $0\logical_op__rc__rc$33[0:0]$9321 - attribute \src "libresoc.v:158336.7-158336.37" - wire $0\logical_op__rc__rc$33[0:0]$9524 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__write_cr0$41$next[0:0]$9389 - attribute \src "libresoc.v:158467.3-158468.67" - wire $0\logical_op__write_cr0$41[0:0]$9337 - attribute \src "libresoc.v:158346.7-158346.40" - wire $0\logical_op__write_cr0$41[0:0]$9526 - attribute \src "libresoc.v:158604.3-158647.6" - wire $0\logical_op__zero_a$38$next[0:0]$9390 - attribute \src "libresoc.v:158461.3-158462.61" - wire $0\logical_op__zero_a$38[0:0]$9331 - attribute \src "libresoc.v:158354.7-158354.37" - wire $0\logical_op__zero_a$38[0:0]$9528 - attribute \src "libresoc.v:158589.3-158603.6" - wire width 2 $0\muxid$28$next[1:0]$9369 - attribute \src "libresoc.v:158479.3-158480.35" - wire width 2 $0\muxid$28[1:0]$9349 - attribute \src "libresoc.v:158362.13-158362.30" - wire width 2 $0\muxid$28[1:0]$9530 - attribute \src "libresoc.v:158798.3-158812.6" - wire width 2 $0\operation$69$next[1:0]$9474 - attribute \src "libresoc.v:158421.3-158422.43" - wire width 2 $0\operation$69[1:0]$9291 - attribute \src "libresoc.v:158372.13-158372.34" - wire width 2 $0\operation$69[1:0]$9532 - attribute \src "libresoc.v:158648.3-158662.6" - wire width 64 $0\ra$47$next[63:0]$9434 - attribute \src "libresoc.v:158441.3-158442.29" - wire width 64 $0\ra$47[63:0]$9311 - attribute \src "libresoc.v:158386.14-158386.44" - wire width 64 $0\ra$47[63:0]$9534 - attribute \src "libresoc.v:158663.3-158677.6" - wire width 64 $0\rb$48$next[63:0]$9438 - attribute \src "libresoc.v:158439.3-158440.29" - wire width 64 $0\rb$48[63:0]$9309 - attribute \src "libresoc.v:158394.14-158394.44" - wire width 64 $0\rb$48[63:0]$9536 - attribute \src "libresoc.v:158516.3-158524.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9357 - attribute \src "libresoc.v:158483.3-158484.75" + attribute \src "libresoc.v:162019.3-162062.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$9771 + attribute \src "libresoc.v:161890.3-161891.65" + wire width 4 $0\logical_op__data_len$45[3:0]$9743 + attribute \src "libresoc.v:161360.13-161360.45" + wire width 4 $0\logical_op__data_len$45[3:0]$9892 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9772 + attribute \src "libresoc.v:161860.3-161861.63" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9713 + attribute \src "libresoc.v:161407.14-161407.48" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9894 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9773 + attribute \src "libresoc.v:161862.3-161863.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9715 + attribute \src "libresoc.v:161413.14-161413.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9896 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$9774 + attribute \src "libresoc.v:161864.3-161865.73" + wire $0\logical_op__imm_data__ok$32[0:0]$9717 + attribute \src "libresoc.v:161421.7-161421.43" + wire $0\logical_op__imm_data__ok$32[0:0]$9898 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$9775 + attribute \src "libresoc.v:161878.3-161879.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$9731 + attribute \src "libresoc.v:161443.13-161443.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$9900 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$9776 + attribute \src "libresoc.v:161892.3-161893.57" + wire width 32 $0\logical_op__insn$46[31:0]$9745 + attribute \src "libresoc.v:161451.14-161451.43" + wire width 32 $0\logical_op__insn$46[31:0]$9902 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$9777 + attribute \src "libresoc.v:161858.3-161859.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$9711 + attribute \src "libresoc.v:161681.13-161681.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$9904 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__invert_in$37$next[0:0]$9778 + attribute \src "libresoc.v:161874.3-161875.67" + wire $0\logical_op__invert_in$37[0:0]$9727 + attribute \src "libresoc.v:161689.7-161689.40" + wire $0\logical_op__invert_in$37[0:0]$9906 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__invert_out$40$next[0:0]$9779 + attribute \src "libresoc.v:161880.3-161881.69" + wire $0\logical_op__invert_out$40[0:0]$9733 + attribute \src "libresoc.v:161697.7-161697.41" + wire $0\logical_op__invert_out$40[0:0]$9908 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__is_32bit$43$next[0:0]$9780 + attribute \src "libresoc.v:161886.3-161887.65" + wire $0\logical_op__is_32bit$43[0:0]$9739 + attribute \src "libresoc.v:161705.7-161705.39" + wire $0\logical_op__is_32bit$43[0:0]$9910 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__is_signed$44$next[0:0]$9781 + attribute \src "libresoc.v:161888.3-161889.67" + wire $0\logical_op__is_signed$44[0:0]$9741 + attribute \src "libresoc.v:161713.7-161713.40" + wire $0\logical_op__is_signed$44[0:0]$9912 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__oe__oe$35$next[0:0]$9782 + attribute \src "libresoc.v:161870.3-161871.61" + wire $0\logical_op__oe__oe$35[0:0]$9723 + attribute \src "libresoc.v:161719.7-161719.37" + wire $0\logical_op__oe__oe$35[0:0]$9914 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__oe__ok$36$next[0:0]$9783 + attribute \src "libresoc.v:161872.3-161873.61" + wire $0\logical_op__oe__ok$36[0:0]$9725 + attribute \src "libresoc.v:161727.7-161727.37" + wire $0\logical_op__oe__ok$36[0:0]$9916 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__output_carry$42$next[0:0]$9784 + attribute \src "libresoc.v:161884.3-161885.73" + wire $0\logical_op__output_carry$42[0:0]$9737 + attribute \src "libresoc.v:161737.7-161737.43" + wire $0\logical_op__output_carry$42[0:0]$9918 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__rc__ok$34$next[0:0]$9785 + attribute \src "libresoc.v:161868.3-161869.61" + wire $0\logical_op__rc__ok$34[0:0]$9721 + attribute \src "libresoc.v:161743.7-161743.37" + wire $0\logical_op__rc__ok$34[0:0]$9920 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__rc__rc$33$next[0:0]$9786 + attribute \src "libresoc.v:161866.3-161867.61" + wire $0\logical_op__rc__rc$33[0:0]$9719 + attribute \src "libresoc.v:161751.7-161751.37" + wire $0\logical_op__rc__rc$33[0:0]$9922 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__write_cr0$41$next[0:0]$9787 + attribute \src "libresoc.v:161882.3-161883.67" + wire $0\logical_op__write_cr0$41[0:0]$9735 + attribute \src "libresoc.v:161761.7-161761.40" + wire $0\logical_op__write_cr0$41[0:0]$9924 + attribute \src "libresoc.v:162019.3-162062.6" + wire $0\logical_op__zero_a$38$next[0:0]$9788 + attribute \src "libresoc.v:161876.3-161877.61" + wire $0\logical_op__zero_a$38[0:0]$9729 + attribute \src "libresoc.v:161769.7-161769.37" + wire $0\logical_op__zero_a$38[0:0]$9926 + attribute \src "libresoc.v:162004.3-162018.6" + wire width 2 $0\muxid$28$next[1:0]$9767 + attribute \src "libresoc.v:161894.3-161895.35" + wire width 2 $0\muxid$28[1:0]$9747 + attribute \src "libresoc.v:161777.13-161777.30" + wire width 2 $0\muxid$28[1:0]$9928 + attribute \src "libresoc.v:162213.3-162227.6" + wire width 2 $0\operation$69$next[1:0]$9872 + attribute \src "libresoc.v:161836.3-161837.43" + wire width 2 $0\operation$69[1:0]$9689 + attribute \src "libresoc.v:161787.13-161787.34" + wire width 2 $0\operation$69[1:0]$9930 + attribute \src "libresoc.v:162063.3-162077.6" + wire width 64 $0\ra$47$next[63:0]$9832 + attribute \src "libresoc.v:161856.3-161857.29" + wire width 64 $0\ra$47[63:0]$9709 + attribute \src "libresoc.v:161801.14-161801.44" + wire width 64 $0\ra$47[63:0]$9932 + attribute \src "libresoc.v:162078.3-162092.6" + wire width 64 $0\rb$48$next[63:0]$9836 + attribute \src "libresoc.v:161854.3-161855.29" + wire width 64 $0\rb$48[63:0]$9707 + attribute \src "libresoc.v:161809.14-161809.44" + wire width 64 $0\rb$48[63:0]$9934 + attribute \src "libresoc.v:161931.3-161939.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9755 + attribute \src "libresoc.v:161898.3-161899.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:158507.3-158515.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$9354 - attribute \src "libresoc.v:158485.3-158486.65" + attribute \src "libresoc.v:161922.3-161930.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$9752 + attribute \src "libresoc.v:161900.3-161901.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:158678.3-158692.6" - wire $0\xer_so$49$next[0:0]$9442 - attribute \src "libresoc.v:158437.3-158438.37" - wire $0\xer_so$49[0:0]$9307 - attribute \src "libresoc.v:158412.7-158412.25" - wire $0\xer_so$49[0:0]$9540 - attribute \src "libresoc.v:158753.3-158767.6" - wire $1\div_by_zero$54$next[0:0]$9463 - attribute \src "libresoc.v:158549.3-158560.6" + attribute \src "libresoc.v:162093.3-162107.6" + wire $0\xer_so$49$next[0:0]$9840 + attribute \src "libresoc.v:161852.3-161853.37" + wire $0\xer_so$49[0:0]$9705 + attribute \src "libresoc.v:161827.7-161827.25" + wire $0\xer_so$49[0:0]$9938 + attribute \src "libresoc.v:162168.3-162182.6" + wire $1\div_by_zero$54$next[0:0]$9861 + attribute \src "libresoc.v:161964.3-161975.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:158537.3-158548.6" + attribute \src "libresoc.v:161952.3-161963.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:158525.3-158536.6" + attribute \src "libresoc.v:161940.3-161951.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:158723.3-158737.6" - wire $1\dive_abs_ov32$52$next[0:0]$9455 - attribute \src "libresoc.v:158738.3-158752.6" - wire $1\dive_abs_ov64$53$next[0:0]$9459 - attribute \src "libresoc.v:158768.3-158782.6" - wire width 128 $1\dividend$68$next[127:0]$9467 - attribute \src "libresoc.v:158708.3-158722.6" - wire $1\dividend_neg$51$next[0:0]$9451 - attribute \src "libresoc.v:158693.3-158707.6" - wire $1\divisor_neg$50$next[0:0]$9447 - attribute \src "libresoc.v:158783.3-158797.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$9471 - attribute \src "libresoc.v:158561.3-158588.6" - wire $1\empty$next[0:0]$9364 - attribute \src "libresoc.v:157937.7-157937.19" + attribute \src "libresoc.v:162138.3-162152.6" + wire $1\dive_abs_ov32$52$next[0:0]$9853 + attribute \src "libresoc.v:162153.3-162167.6" + wire $1\dive_abs_ov64$53$next[0:0]$9857 + attribute \src "libresoc.v:162183.3-162197.6" + wire width 128 $1\dividend$68$next[127:0]$9865 + attribute \src "libresoc.v:162123.3-162137.6" + wire $1\dividend_neg$51$next[0:0]$9849 + attribute \src "libresoc.v:162108.3-162122.6" + wire $1\divisor_neg$50$next[0:0]$9845 + attribute \src "libresoc.v:162198.3-162212.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$9869 + attribute \src "libresoc.v:161976.3-162003.6" + wire $1\empty$next[0:0]$9762 + attribute \src "libresoc.v:161352.7-161352.19" wire $1\empty[0:0] - attribute \src "libresoc.v:158604.3-158647.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$9391 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9392 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9393 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$9394 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$9395 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$9396 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$9397 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__invert_in$37$next[0:0]$9398 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__invert_out$40$next[0:0]$9399 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__is_32bit$43$next[0:0]$9400 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__is_signed$44$next[0:0]$9401 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__oe__oe$35$next[0:0]$9402 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__oe__ok$36$next[0:0]$9403 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__output_carry$42$next[0:0]$9404 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__rc__ok$34$next[0:0]$9405 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__rc__rc$33$next[0:0]$9406 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__write_cr0$41$next[0:0]$9407 - attribute \src "libresoc.v:158604.3-158647.6" - wire $1\logical_op__zero_a$38$next[0:0]$9408 - attribute \src "libresoc.v:158589.3-158603.6" - wire width 2 $1\muxid$28$next[1:0]$9370 - attribute \src "libresoc.v:158798.3-158812.6" - wire width 2 $1\operation$69$next[1:0]$9475 - attribute \src "libresoc.v:158648.3-158662.6" - wire width 64 $1\ra$47$next[63:0]$9435 - attribute \src "libresoc.v:158663.3-158677.6" - wire width 64 $1\rb$48$next[63:0]$9439 - attribute \src "libresoc.v:158516.3-158524.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9358 - attribute \src "libresoc.v:158400.15-158400.84" + attribute \src "libresoc.v:162019.3-162062.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$9789 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9790 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9791 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$9792 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$9793 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$9794 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$9795 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__invert_in$37$next[0:0]$9796 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__invert_out$40$next[0:0]$9797 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__is_32bit$43$next[0:0]$9798 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__is_signed$44$next[0:0]$9799 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__oe__oe$35$next[0:0]$9800 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__oe__ok$36$next[0:0]$9801 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__output_carry$42$next[0:0]$9802 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__rc__ok$34$next[0:0]$9803 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__rc__rc$33$next[0:0]$9804 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__write_cr0$41$next[0:0]$9805 + attribute \src "libresoc.v:162019.3-162062.6" + wire $1\logical_op__zero_a$38$next[0:0]$9806 + attribute \src "libresoc.v:162004.3-162018.6" + wire width 2 $1\muxid$28$next[1:0]$9768 + attribute \src "libresoc.v:162213.3-162227.6" + wire width 2 $1\operation$69$next[1:0]$9873 + attribute \src "libresoc.v:162063.3-162077.6" + wire width 64 $1\ra$47$next[63:0]$9833 + attribute \src "libresoc.v:162078.3-162092.6" + wire width 64 $1\rb$48$next[63:0]$9837 + attribute \src "libresoc.v:161931.3-161939.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9756 + attribute \src "libresoc.v:161815.15-161815.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:158507.3-158515.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$9355 - attribute \src "libresoc.v:158404.13-158404.45" + attribute \src "libresoc.v:161922.3-161930.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$9753 + attribute \src "libresoc.v:161819.13-161819.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:158678.3-158692.6" - wire $1\xer_so$49$next[0:0]$9443 - attribute \src "libresoc.v:158753.3-158767.6" - wire $2\div_by_zero$54$next[0:0]$9464 - attribute \src "libresoc.v:158723.3-158737.6" - wire $2\dive_abs_ov32$52$next[0:0]$9456 - attribute \src "libresoc.v:158738.3-158752.6" - wire $2\dive_abs_ov64$53$next[0:0]$9460 - attribute \src "libresoc.v:158768.3-158782.6" - wire width 128 $2\dividend$68$next[127:0]$9468 - attribute \src "libresoc.v:158708.3-158722.6" - wire $2\dividend_neg$51$next[0:0]$9452 - attribute \src "libresoc.v:158693.3-158707.6" - wire $2\divisor_neg$50$next[0:0]$9448 - attribute \src "libresoc.v:158783.3-158797.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$9472 - attribute \src "libresoc.v:158561.3-158588.6" - wire $2\empty$next[0:0]$9365 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$9409 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9410 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9411 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$9412 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$9413 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$9414 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$9415 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__invert_in$37$next[0:0]$9416 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__invert_out$40$next[0:0]$9417 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__is_32bit$43$next[0:0]$9418 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__is_signed$44$next[0:0]$9419 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__oe__oe$35$next[0:0]$9420 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__oe__ok$36$next[0:0]$9421 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__output_carry$42$next[0:0]$9422 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__rc__ok$34$next[0:0]$9423 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__rc__rc$33$next[0:0]$9424 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__write_cr0$41$next[0:0]$9425 - attribute \src "libresoc.v:158604.3-158647.6" - wire $2\logical_op__zero_a$38$next[0:0]$9426 - attribute \src "libresoc.v:158589.3-158603.6" - wire width 2 $2\muxid$28$next[1:0]$9371 - attribute \src "libresoc.v:158798.3-158812.6" - wire width 2 $2\operation$69$next[1:0]$9476 - attribute \src "libresoc.v:158648.3-158662.6" - wire width 64 $2\ra$47$next[63:0]$9436 - attribute \src "libresoc.v:158663.3-158677.6" - wire width 64 $2\rb$48$next[63:0]$9440 - attribute \src "libresoc.v:158678.3-158692.6" - wire $2\xer_so$49$next[0:0]$9444 - attribute \src "libresoc.v:158561.3-158588.6" - wire $3\empty$next[0:0]$9366 - attribute \src "libresoc.v:158604.3-158647.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9427 - attribute \src "libresoc.v:158604.3-158647.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$9428 - attribute \src "libresoc.v:158604.3-158647.6" - wire $3\logical_op__oe__oe$35$next[0:0]$9429 - attribute \src "libresoc.v:158604.3-158647.6" - wire $3\logical_op__oe__ok$36$next[0:0]$9430 - attribute \src "libresoc.v:158604.3-158647.6" - wire $3\logical_op__rc__ok$34$next[0:0]$9431 - attribute \src "libresoc.v:158604.3-158647.6" - wire $3\logical_op__rc__rc$33$next[0:0]$9432 - attribute \src "libresoc.v:158561.3-158588.6" - wire $4\empty$next[0:0]$9367 - attribute \src "libresoc.v:158419.18-158419.98" - wire $and$libresoc.v:158419$9288_Y - attribute \src "libresoc.v:158420.18-158420.107" - wire $and$libresoc.v:158420$9289_Y - attribute \src "libresoc.v:158418.18-158418.124" - wire $eq$libresoc.v:158418$9287_Y - attribute \src "libresoc.v:158416.18-158416.92" - wire width 192 $extend$libresoc.v:158416$9284_Y - attribute \src "libresoc.v:158417.18-158417.93" - wire $not$libresoc.v:158417$9286_Y - attribute \src "libresoc.v:158416.18-158416.92" - wire width 192 $pos$libresoc.v:158416$9285_Y - attribute \src "libresoc.v:158415.18-158415.138" - wire width 191 $sshl$libresoc.v:158415$9283_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + attribute \src "libresoc.v:162093.3-162107.6" + wire $1\xer_so$49$next[0:0]$9841 + attribute \src "libresoc.v:162168.3-162182.6" + wire $2\div_by_zero$54$next[0:0]$9862 + attribute \src "libresoc.v:162138.3-162152.6" + wire $2\dive_abs_ov32$52$next[0:0]$9854 + attribute \src "libresoc.v:162153.3-162167.6" + wire $2\dive_abs_ov64$53$next[0:0]$9858 + attribute \src "libresoc.v:162183.3-162197.6" + wire width 128 $2\dividend$68$next[127:0]$9866 + attribute \src "libresoc.v:162123.3-162137.6" + wire $2\dividend_neg$51$next[0:0]$9850 + attribute \src "libresoc.v:162108.3-162122.6" + wire $2\divisor_neg$50$next[0:0]$9846 + attribute \src "libresoc.v:162198.3-162212.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$9870 + attribute \src "libresoc.v:161976.3-162003.6" + wire $2\empty$next[0:0]$9763 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$9807 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9808 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9809 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$9810 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$9811 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$9812 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$9813 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__invert_in$37$next[0:0]$9814 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__invert_out$40$next[0:0]$9815 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__is_32bit$43$next[0:0]$9816 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__is_signed$44$next[0:0]$9817 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__oe__oe$35$next[0:0]$9818 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__oe__ok$36$next[0:0]$9819 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__output_carry$42$next[0:0]$9820 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__rc__ok$34$next[0:0]$9821 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__rc__rc$33$next[0:0]$9822 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__write_cr0$41$next[0:0]$9823 + attribute \src "libresoc.v:162019.3-162062.6" + wire $2\logical_op__zero_a$38$next[0:0]$9824 + attribute \src "libresoc.v:162004.3-162018.6" + wire width 2 $2\muxid$28$next[1:0]$9769 + attribute \src "libresoc.v:162213.3-162227.6" + wire width 2 $2\operation$69$next[1:0]$9874 + attribute \src "libresoc.v:162063.3-162077.6" + wire width 64 $2\ra$47$next[63:0]$9834 + attribute \src "libresoc.v:162078.3-162092.6" + wire width 64 $2\rb$48$next[63:0]$9838 + attribute \src "libresoc.v:162093.3-162107.6" + wire $2\xer_so$49$next[0:0]$9842 + attribute \src "libresoc.v:161976.3-162003.6" + wire $3\empty$next[0:0]$9764 + attribute \src "libresoc.v:162019.3-162062.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9825 + attribute \src "libresoc.v:162019.3-162062.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$9826 + attribute \src "libresoc.v:162019.3-162062.6" + wire $3\logical_op__oe__oe$35$next[0:0]$9827 + attribute \src "libresoc.v:162019.3-162062.6" + wire $3\logical_op__oe__ok$36$next[0:0]$9828 + attribute \src "libresoc.v:162019.3-162062.6" + wire $3\logical_op__rc__ok$34$next[0:0]$9829 + attribute \src "libresoc.v:162019.3-162062.6" + wire $3\logical_op__rc__rc$33$next[0:0]$9830 + attribute \src "libresoc.v:161976.3-162003.6" + wire $4\empty$next[0:0]$9765 + attribute \src "libresoc.v:161834.18-161834.98" + wire $and$libresoc.v:161834$9686_Y + attribute \src "libresoc.v:161835.18-161835.107" + wire $and$libresoc.v:161835$9687_Y + attribute \src "libresoc.v:161831.18-161831.92" + wire width 192 $extend$libresoc.v:161831$9682_Y + attribute \src "libresoc.v:161833.18-161833.119" + wire $ge$libresoc.v:161833$9685_Y + attribute \src "libresoc.v:161832.18-161832.93" + wire $not$libresoc.v:161832$9684_Y + attribute \src "libresoc.v:161831.18-161831.92" + wire width 192 $pos$libresoc.v:161831$9683_Y + attribute \src "libresoc.v:161830.18-161830.138" + wire width 191 $sshl$libresoc.v:161830$9681_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 191 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -324180,11 +332099,11 @@ module \pipe_middle_0 wire width 64 \divisor_radicand$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$65$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:157851.7-157851.15" + attribute \src "libresoc.v:161266.7-161266.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -324661,8 +332580,8 @@ module \pipe_middle_0 wire \xer_so$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - cell $and $and$libresoc.v:158419$9288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:161834$9686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324670,10 +332589,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:158419$9288_Y + connect \Y $and$libresoc.v:161834$9686_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" - cell $and $and$libresoc.v:158420$9289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:161835$9687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324681,45 +332600,45 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:158420$9289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" - cell $eq $eq$libresoc.v:158418$9287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \div_state_next_o_q_bits_known - connect \B 7'1000000 - connect \Y $eq$libresoc.v:158418$9287_Y + connect \Y $and$libresoc.v:161835$9687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $pos $extend$libresoc.v:158416$9284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:161831$9682 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:158416$9284_Y + connect \Y $extend$libresoc.v:161831$9682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:161833$9685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:161833$9685_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" - cell $not $not$libresoc.v:158417$9286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:161832$9684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:158417$9286_Y + connect \Y $not$libresoc.v:161832$9684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $pos $pos$libresoc.v:158416$9285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:161831$9683 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:158416$9284_Y - connect \Y $pos$libresoc.v:158416$9285_Y + connect \A $extend$libresoc.v:161831$9682_Y + connect \Y $pos$libresoc.v:161831$9683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" - cell $sshl $sshl$libresoc.v:158415$9283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:161830$9681 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -324727,17 +332646,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:158415$9283_Y + connect \Y $sshl$libresoc.v:161830$9681_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:158487.18-158491.4" + attribute \src "libresoc.v:161902.18-161906.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:158492.18-158498.4" + attribute \src "libresoc.v:161907.18-161913.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -324746,528 +332665,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:158499.10-158502.4" - cell \n$77 \n + attribute \src "libresoc.v:161914.10-161917.4" + cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:158503.10-158506.4" - cell \p$76 \p + attribute \src "libresoc.v:161918.10-161921.4" + cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:157851.7-157851.20" - process $proc$libresoc.v:157851$9477 + attribute \src "libresoc.v:161266.7-161266.20" + process $proc$libresoc.v:161266$9875 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157873.7-157873.30" - process $proc$libresoc.v:157873$9478 + attribute \src "libresoc.v:161288.7-161288.30" + process $proc$libresoc.v:161288$9876 assign { } { } - assign $0\div_by_zero$54[0:0]$9479 1'0 + assign $0\div_by_zero$54[0:0]$9877 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9479 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9877 end - attribute \src "libresoc.v:157897.7-157897.32" - process $proc$libresoc.v:157897$9480 + attribute \src "libresoc.v:161312.7-161312.32" + process $proc$libresoc.v:161312$9878 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9481 1'0 + assign $0\dive_abs_ov32$52[0:0]$9879 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9481 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9879 end - attribute \src "libresoc.v:157905.7-157905.32" - process $proc$libresoc.v:157905$9482 + attribute \src "libresoc.v:161320.7-161320.32" + process $proc$libresoc.v:161320$9880 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9483 1'0 + assign $0\dive_abs_ov64$53[0:0]$9881 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9483 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9881 end - attribute \src "libresoc.v:157911.15-157911.68" - process $proc$libresoc.v:157911$9484 + attribute \src "libresoc.v:161326.15-161326.68" + process $proc$libresoc.v:161326$9882 assign { } { } - assign $0\dividend$68[127:0]$9485 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$9883 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$9485 + update \dividend$68 $0\dividend$68[127:0]$9883 end - attribute \src "libresoc.v:157919.7-157919.31" - process $proc$libresoc.v:157919$9486 + attribute \src "libresoc.v:161334.7-161334.31" + process $proc$libresoc.v:161334$9884 assign { } { } - assign $0\dividend_neg$51[0:0]$9487 1'0 + assign $0\dividend_neg$51[0:0]$9885 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9487 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9885 end - attribute \src "libresoc.v:157927.7-157927.30" - process $proc$libresoc.v:157927$9488 + attribute \src "libresoc.v:161342.7-161342.30" + process $proc$libresoc.v:161342$9886 assign { } { } - assign $0\divisor_neg$50[0:0]$9489 1'0 + assign $0\divisor_neg$50[0:0]$9887 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9489 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9887 end - attribute \src "libresoc.v:157933.14-157933.58" - process $proc$libresoc.v:157933$9490 + attribute \src "libresoc.v:161348.14-161348.58" + process $proc$libresoc.v:161348$9888 assign { } { } - assign $0\divisor_radicand$65[63:0]$9491 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$9889 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9491 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9889 end - attribute \src "libresoc.v:157937.7-157937.19" - process $proc$libresoc.v:157937$9492 + attribute \src "libresoc.v:161352.7-161352.19" + process $proc$libresoc.v:161352$9890 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:157945.13-157945.45" - process $proc$libresoc.v:157945$9493 + attribute \src "libresoc.v:161360.13-161360.45" + process $proc$libresoc.v:161360$9891 assign { } { } - assign $0\logical_op__data_len$45[3:0]$9494 4'0000 + assign $0\logical_op__data_len$45[3:0]$9892 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9494 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9892 end - attribute \src "libresoc.v:157992.14-157992.48" - process $proc$libresoc.v:157992$9495 + attribute \src "libresoc.v:161407.14-161407.48" + process $proc$libresoc.v:161407$9893 assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9496 12'000000000000 + assign $0\logical_op__fn_unit$30[11:0]$9894 12'000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9496 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9894 end - attribute \src "libresoc.v:157998.14-157998.68" - process $proc$libresoc.v:157998$9497 + attribute \src "libresoc.v:161413.14-161413.68" + process $proc$libresoc.v:161413$9895 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9498 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$9896 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9498 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9896 end - attribute \src "libresoc.v:158006.7-158006.43" - process $proc$libresoc.v:158006$9499 + attribute \src "libresoc.v:161421.7-161421.43" + process $proc$libresoc.v:161421$9897 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9500 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$9898 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9500 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9898 end - attribute \src "libresoc.v:158028.13-158028.48" - process $proc$libresoc.v:158028$9501 + attribute \src "libresoc.v:161443.13-161443.48" + process $proc$libresoc.v:161443$9899 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9502 2'00 + assign $0\logical_op__input_carry$39[1:0]$9900 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9502 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9900 end - attribute \src "libresoc.v:158036.14-158036.43" - process $proc$libresoc.v:158036$9503 + attribute \src "libresoc.v:161451.14-161451.43" + process $proc$libresoc.v:161451$9901 assign { } { } - assign $0\logical_op__insn$46[31:0]$9504 0 + assign $0\logical_op__insn$46[31:0]$9902 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9504 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9902 end - attribute \src "libresoc.v:158266.13-158266.47" - process $proc$libresoc.v:158266$9505 + attribute \src "libresoc.v:161681.13-161681.47" + process $proc$libresoc.v:161681$9903 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9506 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$9904 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9506 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9904 end - attribute \src "libresoc.v:158274.7-158274.40" - process $proc$libresoc.v:158274$9507 + attribute \src "libresoc.v:161689.7-161689.40" + process $proc$libresoc.v:161689$9905 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9508 1'0 + assign $0\logical_op__invert_in$37[0:0]$9906 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9508 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9906 end - attribute \src "libresoc.v:158282.7-158282.41" - process $proc$libresoc.v:158282$9509 + attribute \src "libresoc.v:161697.7-161697.41" + process $proc$libresoc.v:161697$9907 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9510 1'0 + assign $0\logical_op__invert_out$40[0:0]$9908 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9510 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9908 end - attribute \src "libresoc.v:158290.7-158290.39" - process $proc$libresoc.v:158290$9511 + attribute \src "libresoc.v:161705.7-161705.39" + process $proc$libresoc.v:161705$9909 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9512 1'0 + assign $0\logical_op__is_32bit$43[0:0]$9910 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9512 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9910 end - attribute \src "libresoc.v:158298.7-158298.40" - process $proc$libresoc.v:158298$9513 + attribute \src "libresoc.v:161713.7-161713.40" + process $proc$libresoc.v:161713$9911 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9514 1'0 + assign $0\logical_op__is_signed$44[0:0]$9912 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9514 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9912 end - attribute \src "libresoc.v:158304.7-158304.37" - process $proc$libresoc.v:158304$9515 + attribute \src "libresoc.v:161719.7-161719.37" + process $proc$libresoc.v:161719$9913 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9516 1'0 + assign $0\logical_op__oe__oe$35[0:0]$9914 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9516 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9914 end - attribute \src "libresoc.v:158312.7-158312.37" - process $proc$libresoc.v:158312$9517 + attribute \src "libresoc.v:161727.7-161727.37" + process $proc$libresoc.v:161727$9915 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9518 1'0 + assign $0\logical_op__oe__ok$36[0:0]$9916 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9518 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9916 end - attribute \src "libresoc.v:158322.7-158322.43" - process $proc$libresoc.v:158322$9519 + attribute \src "libresoc.v:161737.7-161737.43" + process $proc$libresoc.v:161737$9917 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9520 1'0 + assign $0\logical_op__output_carry$42[0:0]$9918 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9520 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9918 end - attribute \src "libresoc.v:158328.7-158328.37" - process $proc$libresoc.v:158328$9521 + attribute \src "libresoc.v:161743.7-161743.37" + process $proc$libresoc.v:161743$9919 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9522 1'0 + assign $0\logical_op__rc__ok$34[0:0]$9920 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9522 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9920 end - attribute \src "libresoc.v:158336.7-158336.37" - process $proc$libresoc.v:158336$9523 + attribute \src "libresoc.v:161751.7-161751.37" + process $proc$libresoc.v:161751$9921 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9524 1'0 + assign $0\logical_op__rc__rc$33[0:0]$9922 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9524 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9922 end - attribute \src "libresoc.v:158346.7-158346.40" - process $proc$libresoc.v:158346$9525 + attribute \src "libresoc.v:161761.7-161761.40" + process $proc$libresoc.v:161761$9923 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9526 1'0 + assign $0\logical_op__write_cr0$41[0:0]$9924 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9526 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9924 end - attribute \src "libresoc.v:158354.7-158354.37" - process $proc$libresoc.v:158354$9527 + attribute \src "libresoc.v:161769.7-161769.37" + process $proc$libresoc.v:161769$9925 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9528 1'0 + assign $0\logical_op__zero_a$38[0:0]$9926 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9528 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9926 end - attribute \src "libresoc.v:158362.13-158362.30" - process $proc$libresoc.v:158362$9529 + attribute \src "libresoc.v:161777.13-161777.30" + process $proc$libresoc.v:161777$9927 assign { } { } - assign $0\muxid$28[1:0]$9530 2'00 + assign $0\muxid$28[1:0]$9928 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$9530 + update \muxid$28 $0\muxid$28[1:0]$9928 end - attribute \src "libresoc.v:158372.13-158372.34" - process $proc$libresoc.v:158372$9531 + attribute \src "libresoc.v:161787.13-161787.34" + process $proc$libresoc.v:161787$9929 assign { } { } - assign $0\operation$69[1:0]$9532 2'00 + assign $0\operation$69[1:0]$9930 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$9532 + update \operation$69 $0\operation$69[1:0]$9930 end - attribute \src "libresoc.v:158386.14-158386.44" - process $proc$libresoc.v:158386$9533 + attribute \src "libresoc.v:161801.14-161801.44" + process $proc$libresoc.v:161801$9931 assign { } { } - assign $0\ra$47[63:0]$9534 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$9932 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$9534 + update \ra$47 $0\ra$47[63:0]$9932 end - attribute \src "libresoc.v:158394.14-158394.44" - process $proc$libresoc.v:158394$9535 + attribute \src "libresoc.v:161809.14-161809.44" + process $proc$libresoc.v:161809$9933 assign { } { } - assign $0\rb$48[63:0]$9536 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$9934 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$9536 + update \rb$48 $0\rb$48[63:0]$9934 end - attribute \src "libresoc.v:158400.15-158400.84" - process $proc$libresoc.v:158400$9537 + attribute \src "libresoc.v:161815.15-161815.84" + process $proc$libresoc.v:161815$9935 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:158404.13-158404.45" - process $proc$libresoc.v:158404$9538 + attribute \src "libresoc.v:161819.13-161819.45" + process $proc$libresoc.v:161819$9936 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:158412.7-158412.25" - process $proc$libresoc.v:158412$9539 + attribute \src "libresoc.v:161827.7-161827.25" + process $proc$libresoc.v:161827$9937 assign { } { } - assign $0\xer_so$49[0:0]$9540 1'0 + assign $0\xer_so$49[0:0]$9938 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$9540 + update \xer_so$49 $0\xer_so$49[0:0]$9938 end - attribute \src "libresoc.v:158421.3-158422.43" - process $proc$libresoc.v:158421$9290 + attribute \src "libresoc.v:161836.3-161837.43" + process $proc$libresoc.v:161836$9688 assign { } { } - assign $0\operation$69[1:0]$9291 \operation$69$next + assign $0\operation$69[1:0]$9689 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9291 + update \operation$69 $0\operation$69[1:0]$9689 end - attribute \src "libresoc.v:158423.3-158424.57" - process $proc$libresoc.v:158423$9292 + attribute \src "libresoc.v:161838.3-161839.57" + process $proc$libresoc.v:161838$9690 assign { } { } - assign $0\divisor_radicand$65[63:0]$9293 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$9691 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9293 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9691 end - attribute \src "libresoc.v:158425.3-158426.41" - process $proc$libresoc.v:158425$9294 + attribute \src "libresoc.v:161840.3-161841.41" + process $proc$libresoc.v:161840$9692 assign { } { } - assign $0\dividend$68[127:0]$9295 \dividend$68$next + assign $0\dividend$68[127:0]$9693 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9295 + update \dividend$68 $0\dividend$68[127:0]$9693 end - attribute \src "libresoc.v:158427.3-158428.47" - process $proc$libresoc.v:158427$9296 + attribute \src "libresoc.v:161842.3-161843.47" + process $proc$libresoc.v:161842$9694 assign { } { } - assign $0\div_by_zero$54[0:0]$9297 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$9695 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9297 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9695 end - attribute \src "libresoc.v:158429.3-158430.51" - process $proc$libresoc.v:158429$9298 + attribute \src "libresoc.v:161844.3-161845.51" + process $proc$libresoc.v:161844$9696 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9299 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$9697 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9299 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9697 end - attribute \src "libresoc.v:158431.3-158432.51" - process $proc$libresoc.v:158431$9300 + attribute \src "libresoc.v:161846.3-161847.51" + process $proc$libresoc.v:161846$9698 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9301 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$9699 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9301 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9699 end - attribute \src "libresoc.v:158433.3-158434.49" - process $proc$libresoc.v:158433$9302 + attribute \src "libresoc.v:161848.3-161849.49" + process $proc$libresoc.v:161848$9700 assign { } { } - assign $0\dividend_neg$51[0:0]$9303 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$9701 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9303 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9701 end - attribute \src "libresoc.v:158435.3-158436.47" - process $proc$libresoc.v:158435$9304 + attribute \src "libresoc.v:161850.3-161851.47" + process $proc$libresoc.v:161850$9702 assign { } { } - assign $0\divisor_neg$50[0:0]$9305 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$9703 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9305 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9703 end - attribute \src "libresoc.v:158437.3-158438.37" - process $proc$libresoc.v:158437$9306 + attribute \src "libresoc.v:161852.3-161853.37" + process $proc$libresoc.v:161852$9704 assign { } { } - assign $0\xer_so$49[0:0]$9307 \xer_so$49$next + assign $0\xer_so$49[0:0]$9705 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9307 + update \xer_so$49 $0\xer_so$49[0:0]$9705 end - attribute \src "libresoc.v:158439.3-158440.29" - process $proc$libresoc.v:158439$9308 + attribute \src "libresoc.v:161854.3-161855.29" + process $proc$libresoc.v:161854$9706 assign { } { } - assign $0\rb$48[63:0]$9309 \rb$48$next + assign $0\rb$48[63:0]$9707 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9309 + update \rb$48 $0\rb$48[63:0]$9707 end - attribute \src "libresoc.v:158441.3-158442.29" - process $proc$libresoc.v:158441$9310 + attribute \src "libresoc.v:161856.3-161857.29" + process $proc$libresoc.v:161856$9708 assign { } { } - assign $0\ra$47[63:0]$9311 \ra$47$next + assign $0\ra$47[63:0]$9709 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9311 + update \ra$47 $0\ra$47[63:0]$9709 end - attribute \src "libresoc.v:158443.3-158444.67" - process $proc$libresoc.v:158443$9312 + attribute \src "libresoc.v:161858.3-161859.67" + process $proc$libresoc.v:161858$9710 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9313 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$9711 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9313 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9711 end - attribute \src "libresoc.v:158445.3-158446.63" - process $proc$libresoc.v:158445$9314 + attribute \src "libresoc.v:161860.3-161861.63" + process $proc$libresoc.v:161860$9712 assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9315 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[11:0]$9713 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9315 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9713 end - attribute \src "libresoc.v:158447.3-158448.77" - process $proc$libresoc.v:158447$9316 + attribute \src "libresoc.v:161862.3-161863.77" + process $proc$libresoc.v:161862$9714 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9317 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$9715 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9317 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9715 end - attribute \src "libresoc.v:158449.3-158450.73" - process $proc$libresoc.v:158449$9318 + attribute \src "libresoc.v:161864.3-161865.73" + process $proc$libresoc.v:161864$9716 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9319 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$9717 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9319 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9717 end - attribute \src "libresoc.v:158451.3-158452.61" - process $proc$libresoc.v:158451$9320 + attribute \src "libresoc.v:161866.3-161867.61" + process $proc$libresoc.v:161866$9718 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9321 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$9719 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9321 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9719 end - attribute \src "libresoc.v:158453.3-158454.61" - process $proc$libresoc.v:158453$9322 + attribute \src "libresoc.v:161868.3-161869.61" + process $proc$libresoc.v:161868$9720 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9323 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$9721 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9323 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9721 end - attribute \src "libresoc.v:158455.3-158456.61" - process $proc$libresoc.v:158455$9324 + attribute \src "libresoc.v:161870.3-161871.61" + process $proc$libresoc.v:161870$9722 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9325 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$9723 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9325 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9723 end - attribute \src "libresoc.v:158457.3-158458.61" - process $proc$libresoc.v:158457$9326 + attribute \src "libresoc.v:161872.3-161873.61" + process $proc$libresoc.v:161872$9724 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9327 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$9725 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9327 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9725 end - attribute \src "libresoc.v:158459.3-158460.67" - process $proc$libresoc.v:158459$9328 + attribute \src "libresoc.v:161874.3-161875.67" + process $proc$libresoc.v:161874$9726 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9329 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$9727 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9329 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9727 end - attribute \src "libresoc.v:158461.3-158462.61" - process $proc$libresoc.v:158461$9330 + attribute \src "libresoc.v:161876.3-161877.61" + process $proc$libresoc.v:161876$9728 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9331 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$9729 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9331 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9729 end - attribute \src "libresoc.v:158463.3-158464.71" - process $proc$libresoc.v:158463$9332 + attribute \src "libresoc.v:161878.3-161879.71" + process $proc$libresoc.v:161878$9730 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9333 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$9731 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9333 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9731 end - attribute \src "libresoc.v:158465.3-158466.69" - process $proc$libresoc.v:158465$9334 + attribute \src "libresoc.v:161880.3-161881.69" + process $proc$libresoc.v:161880$9732 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9335 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$9733 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9335 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9733 end - attribute \src "libresoc.v:158467.3-158468.67" - process $proc$libresoc.v:158467$9336 + attribute \src "libresoc.v:161882.3-161883.67" + process $proc$libresoc.v:161882$9734 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9337 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$9735 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9337 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9735 end - attribute \src "libresoc.v:158469.3-158470.73" - process $proc$libresoc.v:158469$9338 + attribute \src "libresoc.v:161884.3-161885.73" + process $proc$libresoc.v:161884$9736 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9339 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$9737 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9339 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9737 end - attribute \src "libresoc.v:158471.3-158472.65" - process $proc$libresoc.v:158471$9340 + attribute \src "libresoc.v:161886.3-161887.65" + process $proc$libresoc.v:161886$9738 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9341 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$9739 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9341 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9739 end - attribute \src "libresoc.v:158473.3-158474.67" - process $proc$libresoc.v:158473$9342 + attribute \src "libresoc.v:161888.3-161889.67" + process $proc$libresoc.v:161888$9740 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9343 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$9741 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9343 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9741 end - attribute \src "libresoc.v:158475.3-158476.65" - process $proc$libresoc.v:158475$9344 + attribute \src "libresoc.v:161890.3-161891.65" + process $proc$libresoc.v:161890$9742 assign { } { } - assign $0\logical_op__data_len$45[3:0]$9345 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$9743 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9345 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9743 end - attribute \src "libresoc.v:158477.3-158478.57" - process $proc$libresoc.v:158477$9346 + attribute \src "libresoc.v:161892.3-161893.57" + process $proc$libresoc.v:161892$9744 assign { } { } - assign $0\logical_op__insn$46[31:0]$9347 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$9745 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9347 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9745 end - attribute \src "libresoc.v:158479.3-158480.35" - process $proc$libresoc.v:158479$9348 + attribute \src "libresoc.v:161894.3-161895.35" + process $proc$libresoc.v:161894$9746 assign { } { } - assign $0\muxid$28[1:0]$9349 \muxid$28$next + assign $0\muxid$28[1:0]$9747 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$9349 + update \muxid$28 $0\muxid$28[1:0]$9747 end - attribute \src "libresoc.v:158481.3-158482.27" - process $proc$libresoc.v:158481$9350 + attribute \src "libresoc.v:161896.3-161897.27" + process $proc$libresoc.v:161896$9748 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:158483.3-158484.75" - process $proc$libresoc.v:158483$9351 + attribute \src "libresoc.v:161898.3-161899.75" + process $proc$libresoc.v:161898$9749 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:158485.3-158486.65" - process $proc$libresoc.v:158485$9352 + attribute \src "libresoc.v:161900.3-161901.65" + process $proc$libresoc.v:161900$9750 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:158507.3-158515.6" - process $proc$libresoc.v:158507$9353 + attribute \src "libresoc.v:161922.3-161930.6" + process $proc$libresoc.v:161922$9751 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$9354 $1\saved_state_q_bits_known$next[6:0]$9355 - attribute \src "libresoc.v:158508.5-158508.29" + assign $0\saved_state_q_bits_known$next[6:0]$9752 $1\saved_state_q_bits_known$next[6:0]$9753 + attribute \src "libresoc.v:161923.5-161923.29" switch \initial - attribute \src "libresoc.v:158508.9-158508.17" + attribute \src "libresoc.v:161923.9-161923.17" case 1'1 case end @@ -325276,21 +333195,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$9355 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$9753 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$9355 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$9753 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9354 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9752 end - attribute \src "libresoc.v:158516.3-158524.6" - process $proc$libresoc.v:158516$9356 + attribute \src "libresoc.v:161931.3-161939.6" + process $proc$libresoc.v:161931$9754 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$9357 $1\saved_state_dividend_quotient$next[127:0]$9358 - attribute \src "libresoc.v:158517.5-158517.29" + assign $0\saved_state_dividend_quotient$next[127:0]$9755 $1\saved_state_dividend_quotient$next[127:0]$9756 + attribute \src "libresoc.v:161932.5-161932.29" switch \initial - attribute \src "libresoc.v:158517.9-158517.17" + attribute \src "libresoc.v:161932.9-161932.17" case 1'1 case end @@ -325299,24 +333218,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$9358 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$9756 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$9358 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$9756 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9357 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9755 end - attribute \src "libresoc.v:158525.3-158536.6" - process $proc$libresoc.v:158525$9359 + attribute \src "libresoc.v:161940.3-161951.6" + process $proc$libresoc.v:161940$9757 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:158526.5-158526.29" + attribute \src "libresoc.v:161941.5-161941.29" switch \initial - attribute \src "libresoc.v:158526.9-158526.17" + attribute \src "libresoc.v:161941.9-161941.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -325330,17 +333249,17 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:158537.3-158548.6" - process $proc$libresoc.v:158537$9360 + attribute \src "libresoc.v:161952.3-161963.6" + process $proc$libresoc.v:161952$9758 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:158538.5-158538.29" + attribute \src "libresoc.v:161953.5-161953.29" switch \initial - attribute \src "libresoc.v:158538.9-158538.17" + attribute \src "libresoc.v:161953.9-161953.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -325354,17 +333273,17 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:158549.3-158560.6" - process $proc$libresoc.v:158549$9361 + attribute \src "libresoc.v:161964.3-161975.6" + process $proc$libresoc.v:161964$9759 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:158550.5-158550.29" + attribute \src "libresoc.v:161965.5-161965.29" switch \initial - attribute \src "libresoc.v:158550.9-158550.17" + attribute \src "libresoc.v:161965.9-161965.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -325378,45 +333297,45 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:158561.3-158588.6" - process $proc$libresoc.v:158561$9362 + attribute \src "libresoc.v:161976.3-162003.6" + process $proc$libresoc.v:161976$9760 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$9363 $4\empty$next[0:0]$9367 - attribute \src "libresoc.v:158562.5-158562.29" + assign $0\empty$next[0:0]$9761 $4\empty$next[0:0]$9765 + attribute \src "libresoc.v:161977.5-161977.29" switch \initial - attribute \src "libresoc.v:158562.9-158562.17" + attribute \src "libresoc.v:161977.9-161977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$9364 $2\empty$next[0:0]$9365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\empty$next[0:0]$9762 $2\empty$next[0:0]$9763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$9365 1'0 + assign $2\empty$next[0:0]$9763 1'0 case - assign $2\empty$next[0:0]$9365 \empty + assign $2\empty$next[0:0]$9763 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$9364 $3\empty$next[0:0]$9366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + assign $1\empty$next[0:0]$9762 $3\empty$next[0:0]$9764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$9366 1'1 + assign $3\empty$next[0:0]$9764 1'1 case - assign $3\empty$next[0:0]$9366 \empty + assign $3\empty$next[0:0]$9764 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -325424,47 +333343,47 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$9367 1'1 + assign $4\empty$next[0:0]$9765 1'1 case - assign $4\empty$next[0:0]$9367 $1\empty$next[0:0]$9364 + assign $4\empty$next[0:0]$9765 $1\empty$next[0:0]$9762 end sync always - update \empty$next $0\empty$next[0:0]$9363 + update \empty$next $0\empty$next[0:0]$9761 end - attribute \src "libresoc.v:158589.3-158603.6" - process $proc$libresoc.v:158589$9368 + attribute \src "libresoc.v:162004.3-162018.6" + process $proc$libresoc.v:162004$9766 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$9369 $1\muxid$28$next[1:0]$9370 - attribute \src "libresoc.v:158590.5-158590.29" + assign $0\muxid$28$next[1:0]$9767 $1\muxid$28$next[1:0]$9768 + attribute \src "libresoc.v:162005.5-162005.29" switch \initial - attribute \src "libresoc.v:158590.9-158590.17" + attribute \src "libresoc.v:162005.9-162005.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$9370 $2\muxid$28$next[1:0]$9371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\muxid$28$next[1:0]$9768 $2\muxid$28$next[1:0]$9769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$9371 \muxid + assign $2\muxid$28$next[1:0]$9769 \muxid case - assign $2\muxid$28$next[1:0]$9371 \muxid$28 + assign $2\muxid$28$next[1:0]$9769 \muxid$28 end case - assign $1\muxid$28$next[1:0]$9370 \muxid$28 + assign $1\muxid$28$next[1:0]$9768 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$9369 + update \muxid$28$next $0\muxid$28$next[1:0]$9767 end - attribute \src "libresoc.v:158604.3-158647.6" - process $proc$libresoc.v:158604$9372 + attribute \src "libresoc.v:162019.3-162062.6" + process $proc$libresoc.v:162019$9770 assign { } { } assign { } { } assign { } { } @@ -325501,37 +333420,37 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$9373 $1\logical_op__data_len$45$next[3:0]$9391 - assign $0\logical_op__fn_unit$30$next[11:0]$9374 $1\logical_op__fn_unit$30$next[11:0]$9392 + assign $0\logical_op__data_len$45$next[3:0]$9771 $1\logical_op__data_len$45$next[3:0]$9789 + assign $0\logical_op__fn_unit$30$next[11:0]$9772 $1\logical_op__fn_unit$30$next[11:0]$9790 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$9377 $1\logical_op__input_carry$39$next[1:0]$9395 - assign $0\logical_op__insn$46$next[31:0]$9378 $1\logical_op__insn$46$next[31:0]$9396 - assign $0\logical_op__insn_type$29$next[6:0]$9379 $1\logical_op__insn_type$29$next[6:0]$9397 - assign $0\logical_op__invert_in$37$next[0:0]$9380 $1\logical_op__invert_in$37$next[0:0]$9398 - assign $0\logical_op__invert_out$40$next[0:0]$9381 $1\logical_op__invert_out$40$next[0:0]$9399 - assign $0\logical_op__is_32bit$43$next[0:0]$9382 $1\logical_op__is_32bit$43$next[0:0]$9400 - assign $0\logical_op__is_signed$44$next[0:0]$9383 $1\logical_op__is_signed$44$next[0:0]$9401 + assign $0\logical_op__input_carry$39$next[1:0]$9775 $1\logical_op__input_carry$39$next[1:0]$9793 + assign $0\logical_op__insn$46$next[31:0]$9776 $1\logical_op__insn$46$next[31:0]$9794 + assign $0\logical_op__insn_type$29$next[6:0]$9777 $1\logical_op__insn_type$29$next[6:0]$9795 + assign $0\logical_op__invert_in$37$next[0:0]$9778 $1\logical_op__invert_in$37$next[0:0]$9796 + assign $0\logical_op__invert_out$40$next[0:0]$9779 $1\logical_op__invert_out$40$next[0:0]$9797 + assign $0\logical_op__is_32bit$43$next[0:0]$9780 $1\logical_op__is_32bit$43$next[0:0]$9798 + assign $0\logical_op__is_signed$44$next[0:0]$9781 $1\logical_op__is_signed$44$next[0:0]$9799 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$9386 $1\logical_op__output_carry$42$next[0:0]$9404 + assign $0\logical_op__output_carry$42$next[0:0]$9784 $1\logical_op__output_carry$42$next[0:0]$9802 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$9389 $1\logical_op__write_cr0$41$next[0:0]$9407 - assign $0\logical_op__zero_a$38$next[0:0]$9390 $1\logical_op__zero_a$38$next[0:0]$9408 - assign $0\logical_op__imm_data__data$31$next[63:0]$9375 $3\logical_op__imm_data__data$31$next[63:0]$9427 - assign $0\logical_op__imm_data__ok$32$next[0:0]$9376 $3\logical_op__imm_data__ok$32$next[0:0]$9428 - assign $0\logical_op__oe__oe$35$next[0:0]$9384 $3\logical_op__oe__oe$35$next[0:0]$9429 - assign $0\logical_op__oe__ok$36$next[0:0]$9385 $3\logical_op__oe__ok$36$next[0:0]$9430 - assign $0\logical_op__rc__ok$34$next[0:0]$9387 $3\logical_op__rc__ok$34$next[0:0]$9431 - assign $0\logical_op__rc__rc$33$next[0:0]$9388 $3\logical_op__rc__rc$33$next[0:0]$9432 - attribute \src "libresoc.v:158605.5-158605.29" + assign $0\logical_op__write_cr0$41$next[0:0]$9787 $1\logical_op__write_cr0$41$next[0:0]$9805 + assign $0\logical_op__zero_a$38$next[0:0]$9788 $1\logical_op__zero_a$38$next[0:0]$9806 + assign $0\logical_op__imm_data__data$31$next[63:0]$9773 $3\logical_op__imm_data__data$31$next[63:0]$9825 + assign $0\logical_op__imm_data__ok$32$next[0:0]$9774 $3\logical_op__imm_data__ok$32$next[0:0]$9826 + assign $0\logical_op__oe__oe$35$next[0:0]$9782 $3\logical_op__oe__oe$35$next[0:0]$9827 + assign $0\logical_op__oe__ok$36$next[0:0]$9783 $3\logical_op__oe__ok$36$next[0:0]$9828 + assign $0\logical_op__rc__ok$34$next[0:0]$9785 $3\logical_op__rc__ok$34$next[0:0]$9829 + assign $0\logical_op__rc__rc$33$next[0:0]$9786 $3\logical_op__rc__rc$33$next[0:0]$9830 + attribute \src "libresoc.v:162020.5-162020.29" switch \initial - attribute \src "libresoc.v:158605.9-158605.17" + attribute \src "libresoc.v:162020.9-162020.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -325553,25 +333472,25 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$9391 $2\logical_op__data_len$45$next[3:0]$9409 - assign $1\logical_op__fn_unit$30$next[11:0]$9392 $2\logical_op__fn_unit$30$next[11:0]$9410 - assign $1\logical_op__imm_data__data$31$next[63:0]$9393 $2\logical_op__imm_data__data$31$next[63:0]$9411 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9394 $2\logical_op__imm_data__ok$32$next[0:0]$9412 - assign $1\logical_op__input_carry$39$next[1:0]$9395 $2\logical_op__input_carry$39$next[1:0]$9413 - assign $1\logical_op__insn$46$next[31:0]$9396 $2\logical_op__insn$46$next[31:0]$9414 - assign $1\logical_op__insn_type$29$next[6:0]$9397 $2\logical_op__insn_type$29$next[6:0]$9415 - assign $1\logical_op__invert_in$37$next[0:0]$9398 $2\logical_op__invert_in$37$next[0:0]$9416 - assign $1\logical_op__invert_out$40$next[0:0]$9399 $2\logical_op__invert_out$40$next[0:0]$9417 - assign $1\logical_op__is_32bit$43$next[0:0]$9400 $2\logical_op__is_32bit$43$next[0:0]$9418 - assign $1\logical_op__is_signed$44$next[0:0]$9401 $2\logical_op__is_signed$44$next[0:0]$9419 - assign $1\logical_op__oe__oe$35$next[0:0]$9402 $2\logical_op__oe__oe$35$next[0:0]$9420 - assign $1\logical_op__oe__ok$36$next[0:0]$9403 $2\logical_op__oe__ok$36$next[0:0]$9421 - assign $1\logical_op__output_carry$42$next[0:0]$9404 $2\logical_op__output_carry$42$next[0:0]$9422 - assign $1\logical_op__rc__ok$34$next[0:0]$9405 $2\logical_op__rc__ok$34$next[0:0]$9423 - assign $1\logical_op__rc__rc$33$next[0:0]$9406 $2\logical_op__rc__rc$33$next[0:0]$9424 - assign $1\logical_op__write_cr0$41$next[0:0]$9407 $2\logical_op__write_cr0$41$next[0:0]$9425 - assign $1\logical_op__zero_a$38$next[0:0]$9408 $2\logical_op__zero_a$38$next[0:0]$9426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\logical_op__data_len$45$next[3:0]$9789 $2\logical_op__data_len$45$next[3:0]$9807 + assign $1\logical_op__fn_unit$30$next[11:0]$9790 $2\logical_op__fn_unit$30$next[11:0]$9808 + assign $1\logical_op__imm_data__data$31$next[63:0]$9791 $2\logical_op__imm_data__data$31$next[63:0]$9809 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9792 $2\logical_op__imm_data__ok$32$next[0:0]$9810 + assign $1\logical_op__input_carry$39$next[1:0]$9793 $2\logical_op__input_carry$39$next[1:0]$9811 + assign $1\logical_op__insn$46$next[31:0]$9794 $2\logical_op__insn$46$next[31:0]$9812 + assign $1\logical_op__insn_type$29$next[6:0]$9795 $2\logical_op__insn_type$29$next[6:0]$9813 + assign $1\logical_op__invert_in$37$next[0:0]$9796 $2\logical_op__invert_in$37$next[0:0]$9814 + assign $1\logical_op__invert_out$40$next[0:0]$9797 $2\logical_op__invert_out$40$next[0:0]$9815 + assign $1\logical_op__is_32bit$43$next[0:0]$9798 $2\logical_op__is_32bit$43$next[0:0]$9816 + assign $1\logical_op__is_signed$44$next[0:0]$9799 $2\logical_op__is_signed$44$next[0:0]$9817 + assign $1\logical_op__oe__oe$35$next[0:0]$9800 $2\logical_op__oe__oe$35$next[0:0]$9818 + assign $1\logical_op__oe__ok$36$next[0:0]$9801 $2\logical_op__oe__ok$36$next[0:0]$9819 + assign $1\logical_op__output_carry$42$next[0:0]$9802 $2\logical_op__output_carry$42$next[0:0]$9820 + assign $1\logical_op__rc__ok$34$next[0:0]$9803 $2\logical_op__rc__ok$34$next[0:0]$9821 + assign $1\logical_op__rc__rc$33$next[0:0]$9804 $2\logical_op__rc__rc$33$next[0:0]$9822 + assign $1\logical_op__write_cr0$41$next[0:0]$9805 $2\logical_op__write_cr0$41$next[0:0]$9823 + assign $1\logical_op__zero_a$38$next[0:0]$9806 $2\logical_op__zero_a$38$next[0:0]$9824 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -325593,46 +333512,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$9414 $2\logical_op__data_len$45$next[3:0]$9409 $2\logical_op__is_signed$44$next[0:0]$9419 $2\logical_op__is_32bit$43$next[0:0]$9418 $2\logical_op__output_carry$42$next[0:0]$9422 $2\logical_op__write_cr0$41$next[0:0]$9425 $2\logical_op__invert_out$40$next[0:0]$9417 $2\logical_op__input_carry$39$next[1:0]$9413 $2\logical_op__zero_a$38$next[0:0]$9426 $2\logical_op__invert_in$37$next[0:0]$9416 $2\logical_op__oe__ok$36$next[0:0]$9421 $2\logical_op__oe__oe$35$next[0:0]$9420 $2\logical_op__rc__ok$34$next[0:0]$9423 $2\logical_op__rc__rc$33$next[0:0]$9424 $2\logical_op__imm_data__ok$32$next[0:0]$9412 $2\logical_op__imm_data__data$31$next[63:0]$9411 $2\logical_op__fn_unit$30$next[11:0]$9410 $2\logical_op__insn_type$29$next[6:0]$9415 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$9812 $2\logical_op__data_len$45$next[3:0]$9807 $2\logical_op__is_signed$44$next[0:0]$9817 $2\logical_op__is_32bit$43$next[0:0]$9816 $2\logical_op__output_carry$42$next[0:0]$9820 $2\logical_op__write_cr0$41$next[0:0]$9823 $2\logical_op__invert_out$40$next[0:0]$9815 $2\logical_op__input_carry$39$next[1:0]$9811 $2\logical_op__zero_a$38$next[0:0]$9824 $2\logical_op__invert_in$37$next[0:0]$9814 $2\logical_op__oe__ok$36$next[0:0]$9819 $2\logical_op__oe__oe$35$next[0:0]$9818 $2\logical_op__rc__ok$34$next[0:0]$9821 $2\logical_op__rc__rc$33$next[0:0]$9822 $2\logical_op__imm_data__ok$32$next[0:0]$9810 $2\logical_op__imm_data__data$31$next[63:0]$9809 $2\logical_op__fn_unit$30$next[11:0]$9808 $2\logical_op__insn_type$29$next[6:0]$9813 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$9409 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[11:0]$9410 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$9411 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$9412 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$9413 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$9414 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$9415 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$9416 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$9417 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$9418 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$9419 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$9420 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$9421 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$9422 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$9423 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$9424 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$9425 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$9426 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$9807 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[11:0]$9808 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$9809 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$9810 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$9811 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$9812 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$9813 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$9814 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$9815 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$9816 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$9817 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$9818 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$9819 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$9820 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$9821 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$9822 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$9823 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$9824 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$9391 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[11:0]$9392 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$9393 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9394 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$9395 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$9396 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$9397 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$9398 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$9399 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$9400 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$9401 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$9402 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$9403 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$9404 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$9405 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$9406 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$9407 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$9408 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$9789 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[11:0]$9790 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$9791 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$9792 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$9793 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$9794 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$9795 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$9796 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$9797 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$9798 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$9799 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$9800 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$9801 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$9802 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$9803 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$9804 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$9805 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$9806 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -325644,398 +333563,398 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$9427 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9428 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$9432 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$9431 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$9429 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$9430 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$9825 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9826 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$9830 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$9829 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$9827 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$9828 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$9427 $1\logical_op__imm_data__data$31$next[63:0]$9393 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9428 $1\logical_op__imm_data__ok$32$next[0:0]$9394 - assign $3\logical_op__oe__oe$35$next[0:0]$9429 $1\logical_op__oe__oe$35$next[0:0]$9402 - assign $3\logical_op__oe__ok$36$next[0:0]$9430 $1\logical_op__oe__ok$36$next[0:0]$9403 - assign $3\logical_op__rc__ok$34$next[0:0]$9431 $1\logical_op__rc__ok$34$next[0:0]$9405 - assign $3\logical_op__rc__rc$33$next[0:0]$9432 $1\logical_op__rc__rc$33$next[0:0]$9406 + assign $3\logical_op__imm_data__data$31$next[63:0]$9825 $1\logical_op__imm_data__data$31$next[63:0]$9791 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9826 $1\logical_op__imm_data__ok$32$next[0:0]$9792 + assign $3\logical_op__oe__oe$35$next[0:0]$9827 $1\logical_op__oe__oe$35$next[0:0]$9800 + assign $3\logical_op__oe__ok$36$next[0:0]$9828 $1\logical_op__oe__ok$36$next[0:0]$9801 + assign $3\logical_op__rc__ok$34$next[0:0]$9829 $1\logical_op__rc__ok$34$next[0:0]$9803 + assign $3\logical_op__rc__rc$33$next[0:0]$9830 $1\logical_op__rc__rc$33$next[0:0]$9804 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9373 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9374 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9375 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9376 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9377 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9378 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9379 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9380 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9381 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9382 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9383 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9384 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9385 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9386 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9387 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9388 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9389 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9390 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9771 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9772 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9773 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9774 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9775 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9776 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9777 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9778 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9779 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9780 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9781 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9782 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9783 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9784 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9785 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9786 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9787 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9788 end - attribute \src "libresoc.v:158648.3-158662.6" - process $proc$libresoc.v:158648$9433 + attribute \src "libresoc.v:162063.3-162077.6" + process $proc$libresoc.v:162063$9831 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$9434 $1\ra$47$next[63:0]$9435 - attribute \src "libresoc.v:158649.5-158649.29" + assign $0\ra$47$next[63:0]$9832 $1\ra$47$next[63:0]$9833 + attribute \src "libresoc.v:162064.5-162064.29" switch \initial - attribute \src "libresoc.v:158649.9-158649.17" + attribute \src "libresoc.v:162064.9-162064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$9435 $2\ra$47$next[63:0]$9436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\ra$47$next[63:0]$9833 $2\ra$47$next[63:0]$9834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$9436 \ra + assign $2\ra$47$next[63:0]$9834 \ra case - assign $2\ra$47$next[63:0]$9436 \ra$47 + assign $2\ra$47$next[63:0]$9834 \ra$47 end case - assign $1\ra$47$next[63:0]$9435 \ra$47 + assign $1\ra$47$next[63:0]$9833 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$9434 + update \ra$47$next $0\ra$47$next[63:0]$9832 end - attribute \src "libresoc.v:158663.3-158677.6" - process $proc$libresoc.v:158663$9437 + attribute \src "libresoc.v:162078.3-162092.6" + process $proc$libresoc.v:162078$9835 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$9438 $1\rb$48$next[63:0]$9439 - attribute \src "libresoc.v:158664.5-158664.29" + assign $0\rb$48$next[63:0]$9836 $1\rb$48$next[63:0]$9837 + attribute \src "libresoc.v:162079.5-162079.29" switch \initial - attribute \src "libresoc.v:158664.9-158664.17" + attribute \src "libresoc.v:162079.9-162079.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$9439 $2\rb$48$next[63:0]$9440 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\rb$48$next[63:0]$9837 $2\rb$48$next[63:0]$9838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$9440 \rb + assign $2\rb$48$next[63:0]$9838 \rb case - assign $2\rb$48$next[63:0]$9440 \rb$48 + assign $2\rb$48$next[63:0]$9838 \rb$48 end case - assign $1\rb$48$next[63:0]$9439 \rb$48 + assign $1\rb$48$next[63:0]$9837 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$9438 + update \rb$48$next $0\rb$48$next[63:0]$9836 end - attribute \src "libresoc.v:158678.3-158692.6" - process $proc$libresoc.v:158678$9441 + attribute \src "libresoc.v:162093.3-162107.6" + process $proc$libresoc.v:162093$9839 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$9442 $1\xer_so$49$next[0:0]$9443 - attribute \src "libresoc.v:158679.5-158679.29" + assign $0\xer_so$49$next[0:0]$9840 $1\xer_so$49$next[0:0]$9841 + attribute \src "libresoc.v:162094.5-162094.29" switch \initial - attribute \src "libresoc.v:158679.9-158679.17" + attribute \src "libresoc.v:162094.9-162094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$9443 $2\xer_so$49$next[0:0]$9444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\xer_so$49$next[0:0]$9841 $2\xer_so$49$next[0:0]$9842 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$9444 \xer_so + assign $2\xer_so$49$next[0:0]$9842 \xer_so case - assign $2\xer_so$49$next[0:0]$9444 \xer_so$49 + assign $2\xer_so$49$next[0:0]$9842 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$9443 \xer_so$49 + assign $1\xer_so$49$next[0:0]$9841 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$9442 + update \xer_so$49$next $0\xer_so$49$next[0:0]$9840 end - attribute \src "libresoc.v:158693.3-158707.6" - process $proc$libresoc.v:158693$9445 + attribute \src "libresoc.v:162108.3-162122.6" + process $proc$libresoc.v:162108$9843 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$9446 $1\divisor_neg$50$next[0:0]$9447 - attribute \src "libresoc.v:158694.5-158694.29" + assign $0\divisor_neg$50$next[0:0]$9844 $1\divisor_neg$50$next[0:0]$9845 + attribute \src "libresoc.v:162109.5-162109.29" switch \initial - attribute \src "libresoc.v:158694.9-158694.17" + attribute \src "libresoc.v:162109.9-162109.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$9447 $2\divisor_neg$50$next[0:0]$9448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\divisor_neg$50$next[0:0]$9845 $2\divisor_neg$50$next[0:0]$9846 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$9448 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$9846 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$9448 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$9846 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$9447 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$9845 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9446 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9844 end - attribute \src "libresoc.v:158708.3-158722.6" - process $proc$libresoc.v:158708$9449 + attribute \src "libresoc.v:162123.3-162137.6" + process $proc$libresoc.v:162123$9847 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$9450 $1\dividend_neg$51$next[0:0]$9451 - attribute \src "libresoc.v:158709.5-158709.29" + assign $0\dividend_neg$51$next[0:0]$9848 $1\dividend_neg$51$next[0:0]$9849 + attribute \src "libresoc.v:162124.5-162124.29" switch \initial - attribute \src "libresoc.v:158709.9-158709.17" + attribute \src "libresoc.v:162124.9-162124.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$9451 $2\dividend_neg$51$next[0:0]$9452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\dividend_neg$51$next[0:0]$9849 $2\dividend_neg$51$next[0:0]$9850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$9452 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$9850 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$9452 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$9850 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$9451 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$9849 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9450 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9848 end - attribute \src "libresoc.v:158723.3-158737.6" - process $proc$libresoc.v:158723$9453 + attribute \src "libresoc.v:162138.3-162152.6" + process $proc$libresoc.v:162138$9851 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$9454 $1\dive_abs_ov32$52$next[0:0]$9455 - attribute \src "libresoc.v:158724.5-158724.29" + assign $0\dive_abs_ov32$52$next[0:0]$9852 $1\dive_abs_ov32$52$next[0:0]$9853 + attribute \src "libresoc.v:162139.5-162139.29" switch \initial - attribute \src "libresoc.v:158724.9-158724.17" + attribute \src "libresoc.v:162139.9-162139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$9455 $2\dive_abs_ov32$52$next[0:0]$9456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\dive_abs_ov32$52$next[0:0]$9853 $2\dive_abs_ov32$52$next[0:0]$9854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$9456 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$9854 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$9456 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$9854 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$9455 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$9853 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9454 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9852 end - attribute \src "libresoc.v:158738.3-158752.6" - process $proc$libresoc.v:158738$9457 + attribute \src "libresoc.v:162153.3-162167.6" + process $proc$libresoc.v:162153$9855 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$9458 $1\dive_abs_ov64$53$next[0:0]$9459 - attribute \src "libresoc.v:158739.5-158739.29" + assign $0\dive_abs_ov64$53$next[0:0]$9856 $1\dive_abs_ov64$53$next[0:0]$9857 + attribute \src "libresoc.v:162154.5-162154.29" switch \initial - attribute \src "libresoc.v:158739.9-158739.17" + attribute \src "libresoc.v:162154.9-162154.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$9459 $2\dive_abs_ov64$53$next[0:0]$9460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\dive_abs_ov64$53$next[0:0]$9857 $2\dive_abs_ov64$53$next[0:0]$9858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$9460 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$9858 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$9460 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$9858 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$9459 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$9857 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9458 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9856 end - attribute \src "libresoc.v:158753.3-158767.6" - process $proc$libresoc.v:158753$9461 + attribute \src "libresoc.v:162168.3-162182.6" + process $proc$libresoc.v:162168$9859 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$9462 $1\div_by_zero$54$next[0:0]$9463 - attribute \src "libresoc.v:158754.5-158754.29" + assign $0\div_by_zero$54$next[0:0]$9860 $1\div_by_zero$54$next[0:0]$9861 + attribute \src "libresoc.v:162169.5-162169.29" switch \initial - attribute \src "libresoc.v:158754.9-158754.17" + attribute \src "libresoc.v:162169.9-162169.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$9463 $2\div_by_zero$54$next[0:0]$9464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\div_by_zero$54$next[0:0]$9861 $2\div_by_zero$54$next[0:0]$9862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$9464 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$9862 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$9464 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$9862 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$9463 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$9861 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9462 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9860 end - attribute \src "libresoc.v:158768.3-158782.6" - process $proc$libresoc.v:158768$9465 + attribute \src "libresoc.v:162183.3-162197.6" + process $proc$libresoc.v:162183$9863 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$9466 $1\dividend$68$next[127:0]$9467 - attribute \src "libresoc.v:158769.5-158769.29" + assign $0\dividend$68$next[127:0]$9864 $1\dividend$68$next[127:0]$9865 + attribute \src "libresoc.v:162184.5-162184.29" switch \initial - attribute \src "libresoc.v:158769.9-158769.17" + attribute \src "libresoc.v:162184.9-162184.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$9467 $2\dividend$68$next[127:0]$9468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\dividend$68$next[127:0]$9865 $2\dividend$68$next[127:0]$9866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$9468 \dividend + assign $2\dividend$68$next[127:0]$9866 \dividend case - assign $2\dividend$68$next[127:0]$9468 \dividend$68 + assign $2\dividend$68$next[127:0]$9866 \dividend$68 end case - assign $1\dividend$68$next[127:0]$9467 \dividend$68 + assign $1\dividend$68$next[127:0]$9865 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$9466 + update \dividend$68$next $0\dividend$68$next[127:0]$9864 end - attribute \src "libresoc.v:158783.3-158797.6" - process $proc$libresoc.v:158783$9469 + attribute \src "libresoc.v:162198.3-162212.6" + process $proc$libresoc.v:162198$9867 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$9470 $1\divisor_radicand$65$next[63:0]$9471 - attribute \src "libresoc.v:158784.5-158784.29" + assign $0\divisor_radicand$65$next[63:0]$9868 $1\divisor_radicand$65$next[63:0]$9869 + attribute \src "libresoc.v:162199.5-162199.29" switch \initial - attribute \src "libresoc.v:158784.9-158784.17" + attribute \src "libresoc.v:162199.9-162199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$9471 $2\divisor_radicand$65$next[63:0]$9472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\divisor_radicand$65$next[63:0]$9869 $2\divisor_radicand$65$next[63:0]$9870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$9472 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$9870 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$9472 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$9870 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$9471 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$9869 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9470 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9868 end - attribute \src "libresoc.v:158798.3-158812.6" - process $proc$libresoc.v:158798$9473 + attribute \src "libresoc.v:162213.3-162227.6" + process $proc$libresoc.v:162213$9871 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$9474 $1\operation$69$next[1:0]$9475 - attribute \src "libresoc.v:158799.5-158799.29" + assign $0\operation$69$next[1:0]$9872 $1\operation$69$next[1:0]$9873 + attribute \src "libresoc.v:162214.5-162214.29" switch \initial - attribute \src "libresoc.v:158799.9-158799.17" + attribute \src "libresoc.v:162214.9-162214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" switch \empty attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$9475 $2\operation$69$next[1:0]$9476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + assign $1\operation$69$next[1:0]$9873 $2\operation$69$next[1:0]$9874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$9476 \operation + assign $2\operation$69$next[1:0]$9874 \operation case - assign $2\operation$69$next[1:0]$9476 \operation$69 + assign $2\operation$69$next[1:0]$9874 \operation$69 end case - assign $1\operation$69$next[1:0]$9475 \operation$69 + assign $1\operation$69$next[1:0]$9873 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$9474 + update \operation$69$next $0\operation$69$next[1:0]$9872 end - connect \$56 $sshl$libresoc.v:158415$9283_Y - connect \$55 $pos$libresoc.v:158416$9285_Y - connect \$59 $not$libresoc.v:158417$9286_Y - connect \$61 $eq$libresoc.v:158418$9287_Y - connect \$63 $and$libresoc.v:158419$9288_Y - connect \$66 $and$libresoc.v:158420$9289_Y + connect \$56 $sshl$libresoc.v:161830$9681_Y + connect \$55 $pos$libresoc.v:161831$9683_Y + connect \$59 $not$libresoc.v:161832$9684_Y + connect \$61 $ge$libresoc.v:161833$9685_Y + connect \$63 $and$libresoc.v:161834$9686_Y + connect \$66 $and$libresoc.v:161835$9687_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -326052,282 +333971,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:158832.1-160356.10" +attribute \src "libresoc.v:162247.1-163771.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:160162.3-160174.6" - wire $0\div_by_zero$next[0:0]$9586 - attribute \src "libresoc.v:159948.3-159949.39" + attribute \src "libresoc.v:163577.3-163589.6" + wire $0\div_by_zero$next[0:0]$9984 + attribute \src "libresoc.v:163363.3-163364.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:160136.3-160148.6" - wire $0\dive_abs_ov32$next[0:0]$9580 - attribute \src "libresoc.v:159952.3-159953.43" + attribute \src "libresoc.v:163551.3-163563.6" + wire $0\dive_abs_ov32$next[0:0]$9978 + attribute \src "libresoc.v:163367.3-163368.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:160149.3-160161.6" - wire $0\dive_abs_ov64$next[0:0]$9583 - attribute \src "libresoc.v:159950.3-159951.43" + attribute \src "libresoc.v:163564.3-163576.6" + wire $0\dive_abs_ov64$next[0:0]$9981 + attribute \src "libresoc.v:163365.3-163366.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:160175.3-160187.6" - wire width 128 $0\dividend$next[127:0]$9589 - attribute \src "libresoc.v:159946.3-159947.33" + attribute \src "libresoc.v:163590.3-163602.6" + wire width 128 $0\dividend$next[127:0]$9987 + attribute \src "libresoc.v:163361.3-163362.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:160123.3-160135.6" - wire $0\dividend_neg$next[0:0]$9577 - attribute \src "libresoc.v:159954.3-159955.41" + attribute \src "libresoc.v:163538.3-163550.6" + wire $0\dividend_neg$next[0:0]$9975 + attribute \src "libresoc.v:163369.3-163370.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:160110.3-160122.6" - wire $0\divisor_neg$next[0:0]$9574 - attribute \src "libresoc.v:159956.3-159957.39" + attribute \src "libresoc.v:163525.3-163537.6" + wire $0\divisor_neg$next[0:0]$9972 + attribute \src "libresoc.v:163371.3-163372.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:160188.3-160200.6" - wire width 64 $0\divisor_radicand$next[63:0]$9592 - attribute \src "libresoc.v:159944.3-159945.49" + attribute \src "libresoc.v:163603.3-163615.6" + wire width 64 $0\divisor_radicand$next[63:0]$9990 + attribute \src "libresoc.v:163359.3-163360.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:158833.7-158833.20" + attribute \src "libresoc.v:162248.7-162248.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 4 $0\logical_op__data_len$next[3:0]$9605 - attribute \src "libresoc.v:159996.3-159997.57" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10003 + attribute \src "libresoc.v:163411.3-163412.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$9606 - attribute \src "libresoc.v:159966.3-159967.55" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$10004 + attribute \src "libresoc.v:163381.3-163382.55" wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$9607 - attribute \src "libresoc.v:159968.3-159969.69" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10005 + attribute \src "libresoc.v:163383.3-163384.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__imm_data__ok$next[0:0]$9608 - attribute \src "libresoc.v:159970.3-159971.65" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10006 + attribute \src "libresoc.v:163385.3-163386.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$9609 - attribute \src "libresoc.v:159984.3-159985.63" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10007 + attribute \src "libresoc.v:163399.3-163400.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 32 $0\logical_op__insn$next[31:0]$9610 - attribute \src "libresoc.v:159998.3-159999.49" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 32 $0\logical_op__insn$next[31:0]$10008 + attribute \src "libresoc.v:163413.3-163414.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$9611 - attribute \src "libresoc.v:159964.3-159965.59" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10009 + attribute \src "libresoc.v:163379.3-163380.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__invert_in$next[0:0]$9612 - attribute \src "libresoc.v:159980.3-159981.59" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__invert_in$next[0:0]$10010 + attribute \src "libresoc.v:163395.3-163396.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__invert_out$next[0:0]$9613 - attribute \src "libresoc.v:159986.3-159987.61" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__invert_out$next[0:0]$10011 + attribute \src "libresoc.v:163401.3-163402.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__is_32bit$next[0:0]$9614 - attribute \src "libresoc.v:159992.3-159993.57" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__is_32bit$next[0:0]$10012 + attribute \src "libresoc.v:163407.3-163408.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__is_signed$next[0:0]$9615 - attribute \src "libresoc.v:159994.3-159995.59" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__is_signed$next[0:0]$10013 + attribute \src "libresoc.v:163409.3-163410.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__oe__oe$next[0:0]$9616 - attribute \src "libresoc.v:159976.3-159977.53" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__oe__oe$next[0:0]$10014 + attribute \src "libresoc.v:163391.3-163392.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__oe__ok$next[0:0]$9617 - attribute \src "libresoc.v:159978.3-159979.53" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__oe__ok$next[0:0]$10015 + attribute \src "libresoc.v:163393.3-163394.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__output_carry$next[0:0]$9618 - attribute \src "libresoc.v:159990.3-159991.65" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__output_carry$next[0:0]$10016 + attribute \src "libresoc.v:163405.3-163406.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__rc__ok$next[0:0]$9619 - attribute \src "libresoc.v:159974.3-159975.53" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__rc__ok$next[0:0]$10017 + attribute \src "libresoc.v:163389.3-163390.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__rc__rc$next[0:0]$9620 - attribute \src "libresoc.v:159972.3-159973.53" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__rc__rc$next[0:0]$10018 + attribute \src "libresoc.v:163387.3-163388.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__write_cr0$next[0:0]$9621 - attribute \src "libresoc.v:159988.3-159989.59" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__write_cr0$next[0:0]$10019 + attribute \src "libresoc.v:163403.3-163404.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $0\logical_op__zero_a$next[0:0]$9622 - attribute \src "libresoc.v:159982.3-159983.53" + attribute \src "libresoc.v:163660.3-163701.6" + wire $0\logical_op__zero_a$next[0:0]$10020 + attribute \src "libresoc.v:163397.3-163398.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:160232.3-160244.6" - wire width 2 $0\muxid$next[1:0]$9602 - attribute \src "libresoc.v:160000.3-160001.27" + attribute \src "libresoc.v:163647.3-163659.6" + wire width 2 $0\muxid$next[1:0]$10000 + attribute \src "libresoc.v:163415.3-163416.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:160201.3-160213.6" - wire width 2 $0\operation$next[1:0]$9595 - attribute \src "libresoc.v:159942.3-159943.35" + attribute \src "libresoc.v:163616.3-163628.6" + wire width 2 $0\operation$next[1:0]$9993 + attribute \src "libresoc.v:163357.3-163358.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:160214.3-160231.6" - wire $0\r_busy$next[0:0]$9598 - attribute \src "libresoc.v:160002.3-160003.29" + attribute \src "libresoc.v:163629.3-163646.6" + wire $0\r_busy$next[0:0]$9996 + attribute \src "libresoc.v:163417.3-163418.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:160287.3-160299.6" - wire width 64 $0\ra$next[63:0]$9648 - attribute \src "libresoc.v:159962.3-159963.21" + attribute \src "libresoc.v:163702.3-163714.6" + wire width 64 $0\ra$next[63:0]$10046 + attribute \src "libresoc.v:163377.3-163378.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:160300.3-160312.6" - wire width 64 $0\rb$next[63:0]$9651 - attribute \src "libresoc.v:159960.3-159961.21" + attribute \src "libresoc.v:163715.3-163727.6" + wire width 64 $0\rb$next[63:0]$10049 + attribute \src "libresoc.v:163375.3-163376.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:160313.3-160325.6" - wire $0\xer_so$next[0:0]$9654 - attribute \src "libresoc.v:159958.3-159959.29" + attribute \src "libresoc.v:163728.3-163740.6" + wire $0\xer_so$next[0:0]$10052 + attribute \src "libresoc.v:163373.3-163374.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:160162.3-160174.6" - wire $1\div_by_zero$next[0:0]$9587 - attribute \src "libresoc.v:158842.7-158842.25" + attribute \src "libresoc.v:163577.3-163589.6" + wire $1\div_by_zero$next[0:0]$9985 + attribute \src "libresoc.v:162257.7-162257.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:160136.3-160148.6" - wire $1\dive_abs_ov32$next[0:0]$9581 - attribute \src "libresoc.v:158849.7-158849.27" + attribute \src "libresoc.v:163551.3-163563.6" + wire $1\dive_abs_ov32$next[0:0]$9979 + attribute \src "libresoc.v:162264.7-162264.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:160149.3-160161.6" - wire $1\dive_abs_ov64$next[0:0]$9584 - attribute \src "libresoc.v:158856.7-158856.27" + attribute \src "libresoc.v:163564.3-163576.6" + wire $1\dive_abs_ov64$next[0:0]$9982 + attribute \src "libresoc.v:162271.7-162271.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:160175.3-160187.6" - wire width 128 $1\dividend$next[127:0]$9590 - attribute \src "libresoc.v:158863.15-158863.63" + attribute \src "libresoc.v:163590.3-163602.6" + wire width 128 $1\dividend$next[127:0]$9988 + attribute \src "libresoc.v:162278.15-162278.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:160123.3-160135.6" - wire $1\dividend_neg$next[0:0]$9578 - attribute \src "libresoc.v:158870.7-158870.26" + attribute \src "libresoc.v:163538.3-163550.6" + wire $1\dividend_neg$next[0:0]$9976 + attribute \src "libresoc.v:162285.7-162285.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:160110.3-160122.6" - wire $1\divisor_neg$next[0:0]$9575 - attribute \src "libresoc.v:158877.7-158877.25" + attribute \src "libresoc.v:163525.3-163537.6" + wire $1\divisor_neg$next[0:0]$9973 + attribute \src "libresoc.v:162292.7-162292.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:160188.3-160200.6" - wire width 64 $1\divisor_radicand$next[63:0]$9593 - attribute \src "libresoc.v:158884.14-158884.53" + attribute \src "libresoc.v:163603.3-163615.6" + wire width 64 $1\divisor_radicand$next[63:0]$9991 + attribute \src "libresoc.v:162299.14-162299.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 4 $1\logical_op__data_len$next[3:0]$9623 - attribute \src "libresoc.v:159161.13-159161.40" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10021 + attribute \src "libresoc.v:162576.13-162576.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$9624 - attribute \src "libresoc.v:159183.14-159183.43" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$10022 + attribute \src "libresoc.v:162598.14-162598.43" wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$9625 - attribute \src "libresoc.v:159218.14-159218.63" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10023 + attribute \src "libresoc.v:162633.14-162633.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__imm_data__ok$next[0:0]$9626 - attribute \src "libresoc.v:159227.7-159227.38" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10024 + attribute \src "libresoc.v:162642.7-162642.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$9627 - attribute \src "libresoc.v:159240.13-159240.43" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10025 + attribute \src "libresoc.v:162655.13-162655.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 32 $1\logical_op__insn$next[31:0]$9628 - attribute \src "libresoc.v:159257.14-159257.38" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 32 $1\logical_op__insn$next[31:0]$10026 + attribute \src "libresoc.v:162672.14-162672.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$9629 - attribute \src "libresoc.v:159340.13-159340.42" + attribute \src "libresoc.v:163660.3-163701.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10027 + attribute \src "libresoc.v:162755.13-162755.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__invert_in$next[0:0]$9630 - attribute \src "libresoc.v:159497.7-159497.35" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__invert_in$next[0:0]$10028 + attribute \src "libresoc.v:162912.7-162912.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__invert_out$next[0:0]$9631 - attribute \src "libresoc.v:159506.7-159506.36" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__invert_out$next[0:0]$10029 + attribute \src "libresoc.v:162921.7-162921.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__is_32bit$next[0:0]$9632 - attribute \src "libresoc.v:159515.7-159515.34" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__is_32bit$next[0:0]$10030 + attribute \src "libresoc.v:162930.7-162930.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__is_signed$next[0:0]$9633 - attribute \src "libresoc.v:159524.7-159524.35" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__is_signed$next[0:0]$10031 + attribute \src "libresoc.v:162939.7-162939.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__oe__oe$next[0:0]$9634 - attribute \src "libresoc.v:159533.7-159533.32" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__oe__oe$next[0:0]$10032 + attribute \src "libresoc.v:162948.7-162948.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__oe__ok$next[0:0]$9635 - attribute \src "libresoc.v:159542.7-159542.32" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__oe__ok$next[0:0]$10033 + attribute \src "libresoc.v:162957.7-162957.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__output_carry$next[0:0]$9636 - attribute \src "libresoc.v:159551.7-159551.38" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__output_carry$next[0:0]$10034 + attribute \src "libresoc.v:162966.7-162966.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__rc__ok$next[0:0]$9637 - attribute \src "libresoc.v:159560.7-159560.32" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__rc__ok$next[0:0]$10035 + attribute \src "libresoc.v:162975.7-162975.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__rc__rc$next[0:0]$9638 - attribute \src "libresoc.v:159569.7-159569.32" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__rc__rc$next[0:0]$10036 + attribute \src "libresoc.v:162984.7-162984.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__write_cr0$next[0:0]$9639 - attribute \src "libresoc.v:159578.7-159578.35" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__write_cr0$next[0:0]$10037 + attribute \src "libresoc.v:162993.7-162993.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire $1\logical_op__zero_a$next[0:0]$9640 - attribute \src "libresoc.v:159587.7-159587.32" + attribute \src "libresoc.v:163660.3-163701.6" + wire $1\logical_op__zero_a$next[0:0]$10038 + attribute \src "libresoc.v:163002.7-163002.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:160232.3-160244.6" - wire width 2 $1\muxid$next[1:0]$9603 - attribute \src "libresoc.v:159596.13-159596.25" + attribute \src "libresoc.v:163647.3-163659.6" + wire width 2 $1\muxid$next[1:0]$10001 + attribute \src "libresoc.v:163011.13-163011.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:160201.3-160213.6" - wire width 2 $1\operation$next[1:0]$9596 - attribute \src "libresoc.v:159611.13-159611.29" + attribute \src "libresoc.v:163616.3-163628.6" + wire width 2 $1\operation$next[1:0]$9994 + attribute \src "libresoc.v:163026.13-163026.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:160214.3-160231.6" - wire $1\r_busy$next[0:0]$9599 - attribute \src "libresoc.v:159625.7-159625.20" + attribute \src "libresoc.v:163629.3-163646.6" + wire $1\r_busy$next[0:0]$9997 + attribute \src "libresoc.v:163040.7-163040.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:160287.3-160299.6" - wire width 64 $1\ra$next[63:0]$9649 - attribute \src "libresoc.v:159630.14-159630.39" + attribute \src "libresoc.v:163702.3-163714.6" + wire width 64 $1\ra$next[63:0]$10047 + attribute \src "libresoc.v:163045.14-163045.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:160300.3-160312.6" - wire width 64 $1\rb$next[63:0]$9652 - attribute \src "libresoc.v:159641.14-159641.39" + attribute \src "libresoc.v:163715.3-163727.6" + wire width 64 $1\rb$next[63:0]$10050 + attribute \src "libresoc.v:163056.14-163056.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:160313.3-160325.6" - wire $1\xer_so$next[0:0]$9655 - attribute \src "libresoc.v:159934.7-159934.20" + attribute \src "libresoc.v:163728.3-163740.6" + wire $1\xer_so$next[0:0]$10053 + attribute \src "libresoc.v:163349.7-163349.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:160245.3-160286.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$9641 - attribute \src "libresoc.v:160245.3-160286.6" - wire $2\logical_op__imm_data__ok$next[0:0]$9642 - attribute \src "libresoc.v:160245.3-160286.6" - wire $2\logical_op__oe__oe$next[0:0]$9643 - attribute \src "libresoc.v:160245.3-160286.6" - wire $2\logical_op__oe__ok$next[0:0]$9644 - attribute \src "libresoc.v:160245.3-160286.6" - wire $2\logical_op__rc__ok$next[0:0]$9645 - attribute \src "libresoc.v:160245.3-160286.6" - wire $2\logical_op__rc__rc$next[0:0]$9646 - attribute \src "libresoc.v:160214.3-160231.6" - wire $2\r_busy$next[0:0]$9600 - attribute \src "libresoc.v:159941.18-159941.118" - wire $and$libresoc.v:159941$9541_Y + attribute \src "libresoc.v:163660.3-163701.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10039 + attribute \src "libresoc.v:163660.3-163701.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10040 + attribute \src "libresoc.v:163660.3-163701.6" + wire $2\logical_op__oe__oe$next[0:0]$10041 + attribute \src "libresoc.v:163660.3-163701.6" + wire $2\logical_op__oe__ok$next[0:0]$10042 + attribute \src "libresoc.v:163660.3-163701.6" + wire $2\logical_op__rc__ok$next[0:0]$10043 + attribute \src "libresoc.v:163660.3-163701.6" + wire $2\logical_op__rc__rc$next[0:0]$10044 + attribute \src "libresoc.v:163629.3-163646.6" + wire $2\r_busy$next[0:0]$9998 + attribute \src "libresoc.v:163356.18-163356.118" + wire $and$libresoc.v:163356$9939_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -326371,7 +334290,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:158833.7-158833.15" + attribute \src "libresoc.v:162248.7-162248.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -327403,7 +335322,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:159941$9541 + cell $and $and$libresoc.v:163356$9939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327411,11 +335330,11 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:159941$9541_Y + connect \Y $and$libresoc.v:163356$9939_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:160004.14-160049.4" - cell \input$75 \input + attribute \src "libresoc.v:163419.14-163464.4" + cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 connect \logical_op__fn_unit \input_logical_op__fn_unit @@ -327462,19 +335381,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:160050.10-160053.4" - cell \n$74 \n + attribute \src "libresoc.v:163465.10-163468.4" + cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:160054.10-160057.4" - cell \p$73 \p + attribute \src "libresoc.v:163469.10-163472.4" + cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:160058.15-160109.4" + attribute \src "libresoc.v:163473.15-163524.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -327527,487 +335446,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:158833.7-158833.20" - process $proc$libresoc.v:158833$9656 + attribute \src "libresoc.v:162248.7-162248.20" + process $proc$libresoc.v:162248$10054 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158842.7-158842.25" - process $proc$libresoc.v:158842$9657 + attribute \src "libresoc.v:162257.7-162257.25" + process $proc$libresoc.v:162257$10055 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:158849.7-158849.27" - process $proc$libresoc.v:158849$9658 + attribute \src "libresoc.v:162264.7-162264.27" + process $proc$libresoc.v:162264$10056 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:158856.7-158856.27" - process $proc$libresoc.v:158856$9659 + attribute \src "libresoc.v:162271.7-162271.27" + process $proc$libresoc.v:162271$10057 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:158863.15-158863.63" - process $proc$libresoc.v:158863$9660 + attribute \src "libresoc.v:162278.15-162278.63" + process $proc$libresoc.v:162278$10058 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:158870.7-158870.26" - process $proc$libresoc.v:158870$9661 + attribute \src "libresoc.v:162285.7-162285.26" + process $proc$libresoc.v:162285$10059 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:158877.7-158877.25" - process $proc$libresoc.v:158877$9662 + attribute \src "libresoc.v:162292.7-162292.25" + process $proc$libresoc.v:162292$10060 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:158884.14-158884.53" - process $proc$libresoc.v:158884$9663 + attribute \src "libresoc.v:162299.14-162299.53" + process $proc$libresoc.v:162299$10061 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:159161.13-159161.40" - process $proc$libresoc.v:159161$9664 + attribute \src "libresoc.v:162576.13-162576.40" + process $proc$libresoc.v:162576$10062 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:159183.14-159183.43" - process $proc$libresoc.v:159183$9665 + attribute \src "libresoc.v:162598.14-162598.43" + process $proc$libresoc.v:162598$10063 assign { } { } assign $1\logical_op__fn_unit[11:0] 12'000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:159218.14-159218.63" - process $proc$libresoc.v:159218$9666 + attribute \src "libresoc.v:162633.14-162633.63" + process $proc$libresoc.v:162633$10064 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:159227.7-159227.38" - process $proc$libresoc.v:159227$9667 + attribute \src "libresoc.v:162642.7-162642.38" + process $proc$libresoc.v:162642$10065 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:159240.13-159240.43" - process $proc$libresoc.v:159240$9668 + attribute \src "libresoc.v:162655.13-162655.43" + process $proc$libresoc.v:162655$10066 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:159257.14-159257.38" - process $proc$libresoc.v:159257$9669 + attribute \src "libresoc.v:162672.14-162672.38" + process $proc$libresoc.v:162672$10067 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:159340.13-159340.42" - process $proc$libresoc.v:159340$9670 + attribute \src "libresoc.v:162755.13-162755.42" + process $proc$libresoc.v:162755$10068 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:159497.7-159497.35" - process $proc$libresoc.v:159497$9671 + attribute \src "libresoc.v:162912.7-162912.35" + process $proc$libresoc.v:162912$10069 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:159506.7-159506.36" - process $proc$libresoc.v:159506$9672 + attribute \src "libresoc.v:162921.7-162921.36" + process $proc$libresoc.v:162921$10070 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:159515.7-159515.34" - process $proc$libresoc.v:159515$9673 + attribute \src "libresoc.v:162930.7-162930.34" + process $proc$libresoc.v:162930$10071 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:159524.7-159524.35" - process $proc$libresoc.v:159524$9674 + attribute \src "libresoc.v:162939.7-162939.35" + process $proc$libresoc.v:162939$10072 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:159533.7-159533.32" - process $proc$libresoc.v:159533$9675 + attribute \src "libresoc.v:162948.7-162948.32" + process $proc$libresoc.v:162948$10073 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:159542.7-159542.32" - process $proc$libresoc.v:159542$9676 + attribute \src "libresoc.v:162957.7-162957.32" + process $proc$libresoc.v:162957$10074 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:159551.7-159551.38" - process $proc$libresoc.v:159551$9677 + attribute \src "libresoc.v:162966.7-162966.38" + process $proc$libresoc.v:162966$10075 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:159560.7-159560.32" - process $proc$libresoc.v:159560$9678 + attribute \src "libresoc.v:162975.7-162975.32" + process $proc$libresoc.v:162975$10076 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:159569.7-159569.32" - process $proc$libresoc.v:159569$9679 + attribute \src "libresoc.v:162984.7-162984.32" + process $proc$libresoc.v:162984$10077 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:159578.7-159578.35" - process $proc$libresoc.v:159578$9680 + attribute \src "libresoc.v:162993.7-162993.35" + process $proc$libresoc.v:162993$10078 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:159587.7-159587.32" - process $proc$libresoc.v:159587$9681 + attribute \src "libresoc.v:163002.7-163002.32" + process $proc$libresoc.v:163002$10079 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:159596.13-159596.25" - process $proc$libresoc.v:159596$9682 + attribute \src "libresoc.v:163011.13-163011.25" + process $proc$libresoc.v:163011$10080 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:159611.13-159611.29" - process $proc$libresoc.v:159611$9683 + attribute \src "libresoc.v:163026.13-163026.29" + process $proc$libresoc.v:163026$10081 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:159625.7-159625.20" - process $proc$libresoc.v:159625$9684 + attribute \src "libresoc.v:163040.7-163040.20" + process $proc$libresoc.v:163040$10082 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:159630.14-159630.39" - process $proc$libresoc.v:159630$9685 + attribute \src "libresoc.v:163045.14-163045.39" + process $proc$libresoc.v:163045$10083 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:159641.14-159641.39" - process $proc$libresoc.v:159641$9686 + attribute \src "libresoc.v:163056.14-163056.39" + process $proc$libresoc.v:163056$10084 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:159934.7-159934.20" - process $proc$libresoc.v:159934$9687 + attribute \src "libresoc.v:163349.7-163349.20" + process $proc$libresoc.v:163349$10085 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:159942.3-159943.35" - process $proc$libresoc.v:159942$9542 + attribute \src "libresoc.v:163357.3-163358.35" + process $proc$libresoc.v:163357$9940 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:159944.3-159945.49" - process $proc$libresoc.v:159944$9543 + attribute \src "libresoc.v:163359.3-163360.49" + process $proc$libresoc.v:163359$9941 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:159946.3-159947.33" - process $proc$libresoc.v:159946$9544 + attribute \src "libresoc.v:163361.3-163362.33" + process $proc$libresoc.v:163361$9942 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:159948.3-159949.39" - process $proc$libresoc.v:159948$9545 + attribute \src "libresoc.v:163363.3-163364.39" + process $proc$libresoc.v:163363$9943 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:159950.3-159951.43" - process $proc$libresoc.v:159950$9546 + attribute \src "libresoc.v:163365.3-163366.43" + process $proc$libresoc.v:163365$9944 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:159952.3-159953.43" - process $proc$libresoc.v:159952$9547 + attribute \src "libresoc.v:163367.3-163368.43" + process $proc$libresoc.v:163367$9945 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:159954.3-159955.41" - process $proc$libresoc.v:159954$9548 + attribute \src "libresoc.v:163369.3-163370.41" + process $proc$libresoc.v:163369$9946 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:159956.3-159957.39" - process $proc$libresoc.v:159956$9549 + attribute \src "libresoc.v:163371.3-163372.39" + process $proc$libresoc.v:163371$9947 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:159958.3-159959.29" - process $proc$libresoc.v:159958$9550 + attribute \src "libresoc.v:163373.3-163374.29" + process $proc$libresoc.v:163373$9948 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:159960.3-159961.21" - process $proc$libresoc.v:159960$9551 + attribute \src "libresoc.v:163375.3-163376.21" + process $proc$libresoc.v:163375$9949 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:159962.3-159963.21" - process $proc$libresoc.v:159962$9552 + attribute \src "libresoc.v:163377.3-163378.21" + process $proc$libresoc.v:163377$9950 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:159964.3-159965.59" - process $proc$libresoc.v:159964$9553 + attribute \src "libresoc.v:163379.3-163380.59" + process $proc$libresoc.v:163379$9951 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:159966.3-159967.55" - process $proc$libresoc.v:159966$9554 + attribute \src "libresoc.v:163381.3-163382.55" + process $proc$libresoc.v:163381$9952 assign { } { } assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] end - attribute \src "libresoc.v:159968.3-159969.69" - process $proc$libresoc.v:159968$9555 + attribute \src "libresoc.v:163383.3-163384.69" + process $proc$libresoc.v:163383$9953 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:159970.3-159971.65" - process $proc$libresoc.v:159970$9556 + attribute \src "libresoc.v:163385.3-163386.65" + process $proc$libresoc.v:163385$9954 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:159972.3-159973.53" - process $proc$libresoc.v:159972$9557 + attribute \src "libresoc.v:163387.3-163388.53" + process $proc$libresoc.v:163387$9955 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:159974.3-159975.53" - process $proc$libresoc.v:159974$9558 + attribute \src "libresoc.v:163389.3-163390.53" + process $proc$libresoc.v:163389$9956 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:159976.3-159977.53" - process $proc$libresoc.v:159976$9559 + attribute \src "libresoc.v:163391.3-163392.53" + process $proc$libresoc.v:163391$9957 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:159978.3-159979.53" - process $proc$libresoc.v:159978$9560 + attribute \src "libresoc.v:163393.3-163394.53" + process $proc$libresoc.v:163393$9958 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:159980.3-159981.59" - process $proc$libresoc.v:159980$9561 + attribute \src "libresoc.v:163395.3-163396.59" + process $proc$libresoc.v:163395$9959 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:159982.3-159983.53" - process $proc$libresoc.v:159982$9562 + attribute \src "libresoc.v:163397.3-163398.53" + process $proc$libresoc.v:163397$9960 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:159984.3-159985.63" - process $proc$libresoc.v:159984$9563 + attribute \src "libresoc.v:163399.3-163400.63" + process $proc$libresoc.v:163399$9961 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:159986.3-159987.61" - process $proc$libresoc.v:159986$9564 + attribute \src "libresoc.v:163401.3-163402.61" + process $proc$libresoc.v:163401$9962 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:159988.3-159989.59" - process $proc$libresoc.v:159988$9565 + attribute \src "libresoc.v:163403.3-163404.59" + process $proc$libresoc.v:163403$9963 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:159990.3-159991.65" - process $proc$libresoc.v:159990$9566 + attribute \src "libresoc.v:163405.3-163406.65" + process $proc$libresoc.v:163405$9964 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:159992.3-159993.57" - process $proc$libresoc.v:159992$9567 + attribute \src "libresoc.v:163407.3-163408.57" + process $proc$libresoc.v:163407$9965 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:159994.3-159995.59" - process $proc$libresoc.v:159994$9568 + attribute \src "libresoc.v:163409.3-163410.59" + process $proc$libresoc.v:163409$9966 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:159996.3-159997.57" - process $proc$libresoc.v:159996$9569 + attribute \src "libresoc.v:163411.3-163412.57" + process $proc$libresoc.v:163411$9967 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:159998.3-159999.49" - process $proc$libresoc.v:159998$9570 + attribute \src "libresoc.v:163413.3-163414.49" + process $proc$libresoc.v:163413$9968 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:160000.3-160001.27" - process $proc$libresoc.v:160000$9571 + attribute \src "libresoc.v:163415.3-163416.27" + process $proc$libresoc.v:163415$9969 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:160002.3-160003.29" - process $proc$libresoc.v:160002$9572 + attribute \src "libresoc.v:163417.3-163418.29" + process $proc$libresoc.v:163417$9970 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160110.3-160122.6" - process $proc$libresoc.v:160110$9573 + attribute \src "libresoc.v:163525.3-163537.6" + process $proc$libresoc.v:163525$9971 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$9574 $1\divisor_neg$next[0:0]$9575 - attribute \src "libresoc.v:160111.5-160111.29" + assign $0\divisor_neg$next[0:0]$9972 $1\divisor_neg$next[0:0]$9973 + attribute \src "libresoc.v:163526.5-163526.29" switch \initial - attribute \src "libresoc.v:160111.9-160111.17" + attribute \src "libresoc.v:163526.9-163526.17" case 1'1 case end @@ -328016,25 +335935,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$9575 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$9973 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$9575 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$9973 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$9575 \divisor_neg + assign $1\divisor_neg$next[0:0]$9973 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$9574 + update \divisor_neg$next $0\divisor_neg$next[0:0]$9972 end - attribute \src "libresoc.v:160123.3-160135.6" - process $proc$libresoc.v:160123$9576 + attribute \src "libresoc.v:163538.3-163550.6" + process $proc$libresoc.v:163538$9974 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$9577 $1\dividend_neg$next[0:0]$9578 - attribute \src "libresoc.v:160124.5-160124.29" + assign $0\dividend_neg$next[0:0]$9975 $1\dividend_neg$next[0:0]$9976 + attribute \src "libresoc.v:163539.5-163539.29" switch \initial - attribute \src "libresoc.v:160124.9-160124.17" + attribute \src "libresoc.v:163539.9-163539.17" case 1'1 case end @@ -328043,25 +335962,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$9578 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$9976 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$9578 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$9976 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$9578 \dividend_neg + assign $1\dividend_neg$next[0:0]$9976 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$9577 + update \dividend_neg$next $0\dividend_neg$next[0:0]$9975 end - attribute \src "libresoc.v:160136.3-160148.6" - process $proc$libresoc.v:160136$9579 + attribute \src "libresoc.v:163551.3-163563.6" + process $proc$libresoc.v:163551$9977 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$9580 $1\dive_abs_ov32$next[0:0]$9581 - attribute \src "libresoc.v:160137.5-160137.29" + assign $0\dive_abs_ov32$next[0:0]$9978 $1\dive_abs_ov32$next[0:0]$9979 + attribute \src "libresoc.v:163552.5-163552.29" switch \initial - attribute \src "libresoc.v:160137.9-160137.17" + attribute \src "libresoc.v:163552.9-163552.17" case 1'1 case end @@ -328070,25 +335989,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$9581 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9580 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9978 end - attribute \src "libresoc.v:160149.3-160161.6" - process $proc$libresoc.v:160149$9582 + attribute \src "libresoc.v:163564.3-163576.6" + process $proc$libresoc.v:163564$9980 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$9583 $1\dive_abs_ov64$next[0:0]$9584 - attribute \src "libresoc.v:160150.5-160150.29" + assign $0\dive_abs_ov64$next[0:0]$9981 $1\dive_abs_ov64$next[0:0]$9982 + attribute \src "libresoc.v:163565.5-163565.29" switch \initial - attribute \src "libresoc.v:160150.9-160150.17" + attribute \src "libresoc.v:163565.9-163565.17" case 1'1 case end @@ -328097,25 +336016,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$9584 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9583 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9981 end - attribute \src "libresoc.v:160162.3-160174.6" - process $proc$libresoc.v:160162$9585 + attribute \src "libresoc.v:163577.3-163589.6" + process $proc$libresoc.v:163577$9983 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$9586 $1\div_by_zero$next[0:0]$9587 - attribute \src "libresoc.v:160163.5-160163.29" + assign $0\div_by_zero$next[0:0]$9984 $1\div_by_zero$next[0:0]$9985 + attribute \src "libresoc.v:163578.5-163578.29" switch \initial - attribute \src "libresoc.v:160163.9-160163.17" + attribute \src "libresoc.v:163578.9-163578.17" case 1'1 case end @@ -328124,25 +336043,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$9587 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$9985 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$9587 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$9985 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$9587 \div_by_zero + assign $1\div_by_zero$next[0:0]$9985 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$9586 + update \div_by_zero$next $0\div_by_zero$next[0:0]$9984 end - attribute \src "libresoc.v:160175.3-160187.6" - process $proc$libresoc.v:160175$9588 + attribute \src "libresoc.v:163590.3-163602.6" + process $proc$libresoc.v:163590$9986 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$9589 $1\dividend$next[127:0]$9590 - attribute \src "libresoc.v:160176.5-160176.29" + assign $0\dividend$next[127:0]$9987 $1\dividend$next[127:0]$9988 + attribute \src "libresoc.v:163591.5-163591.29" switch \initial - attribute \src "libresoc.v:160176.9-160176.17" + attribute \src "libresoc.v:163591.9-163591.17" case 1'1 case end @@ -328151,25 +336070,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$9590 \dividend$97 + assign $1\dividend$next[127:0]$9988 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$9590 \dividend$97 + assign $1\dividend$next[127:0]$9988 \dividend$97 case - assign $1\dividend$next[127:0]$9590 \dividend + assign $1\dividend$next[127:0]$9988 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$9589 + update \dividend$next $0\dividend$next[127:0]$9987 end - attribute \src "libresoc.v:160188.3-160200.6" - process $proc$libresoc.v:160188$9591 + attribute \src "libresoc.v:163603.3-163615.6" + process $proc$libresoc.v:163603$9989 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$9592 $1\divisor_radicand$next[63:0]$9593 - attribute \src "libresoc.v:160189.5-160189.29" + assign $0\divisor_radicand$next[63:0]$9990 $1\divisor_radicand$next[63:0]$9991 + attribute \src "libresoc.v:163604.5-163604.29" switch \initial - attribute \src "libresoc.v:160189.9-160189.17" + attribute \src "libresoc.v:163604.9-163604.17" case 1'1 case end @@ -328178,25 +336097,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$9593 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9592 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9990 end - attribute \src "libresoc.v:160201.3-160213.6" - process $proc$libresoc.v:160201$9594 + attribute \src "libresoc.v:163616.3-163628.6" + process $proc$libresoc.v:163616$9992 assign { } { } assign { } { } - assign $0\operation$next[1:0]$9595 $1\operation$next[1:0]$9596 - attribute \src "libresoc.v:160202.5-160202.29" + assign $0\operation$next[1:0]$9993 $1\operation$next[1:0]$9994 + attribute \src "libresoc.v:163617.5-163617.29" switch \initial - attribute \src "libresoc.v:160202.9-160202.17" + attribute \src "libresoc.v:163617.9-163617.17" case 1'1 case end @@ -328205,26 +336124,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$9596 \operation$99 + assign $1\operation$next[1:0]$9994 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$9596 \operation$99 + assign $1\operation$next[1:0]$9994 \operation$99 case - assign $1\operation$next[1:0]$9596 \operation + assign $1\operation$next[1:0]$9994 \operation end sync always - update \operation$next $0\operation$next[1:0]$9595 + update \operation$next $0\operation$next[1:0]$9993 end - attribute \src "libresoc.v:160214.3-160231.6" - process $proc$libresoc.v:160214$9597 + attribute \src "libresoc.v:163629.3-163646.6" + process $proc$libresoc.v:163629$9995 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9598 $2\r_busy$next[0:0]$9600 - attribute \src "libresoc.v:160215.5-160215.29" + assign $0\r_busy$next[0:0]$9996 $2\r_busy$next[0:0]$9998 + attribute \src "libresoc.v:163630.5-163630.29" switch \initial - attribute \src "libresoc.v:160215.9-160215.17" + attribute \src "libresoc.v:163630.9-163630.17" case 1'1 case end @@ -328233,34 +336152,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9599 1'1 + assign $1\r_busy$next[0:0]$9997 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9599 1'0 + assign $1\r_busy$next[0:0]$9997 1'0 case - assign $1\r_busy$next[0:0]$9599 \r_busy + assign $1\r_busy$next[0:0]$9997 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9600 1'0 + assign $2\r_busy$next[0:0]$9998 1'0 case - assign $2\r_busy$next[0:0]$9600 $1\r_busy$next[0:0]$9599 + assign $2\r_busy$next[0:0]$9998 $1\r_busy$next[0:0]$9997 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9598 + update \r_busy$next $0\r_busy$next[0:0]$9996 end - attribute \src "libresoc.v:160232.3-160244.6" - process $proc$libresoc.v:160232$9601 + attribute \src "libresoc.v:163647.3-163659.6" + process $proc$libresoc.v:163647$9999 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9602 $1\muxid$next[1:0]$9603 - attribute \src "libresoc.v:160233.5-160233.29" + assign $0\muxid$next[1:0]$10000 $1\muxid$next[1:0]$10001 + attribute \src "libresoc.v:163648.5-163648.29" switch \initial - attribute \src "libresoc.v:160233.9-160233.17" + attribute \src "libresoc.v:163648.9-163648.17" case 1'1 case end @@ -328269,19 +336188,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9603 \muxid$68 + assign $1\muxid$next[1:0]$10001 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9603 \muxid$68 + assign $1\muxid$next[1:0]$10001 \muxid$68 case - assign $1\muxid$next[1:0]$9603 \muxid + assign $1\muxid$next[1:0]$10001 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9602 + update \muxid$next $0\muxid$next[1:0]$10000 end - attribute \src "libresoc.v:160245.3-160286.6" - process $proc$libresoc.v:160245$9604 + attribute \src "libresoc.v:163660.3-163701.6" + process $proc$libresoc.v:163660$10002 assign { } { } assign { } { } assign { } { } @@ -328318,33 +336237,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$9605 $1\logical_op__data_len$next[3:0]$9623 - assign $0\logical_op__fn_unit$next[11:0]$9606 $1\logical_op__fn_unit$next[11:0]$9624 + assign $0\logical_op__data_len$next[3:0]$10003 $1\logical_op__data_len$next[3:0]$10021 + assign $0\logical_op__fn_unit$next[11:0]$10004 $1\logical_op__fn_unit$next[11:0]$10022 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$9609 $1\logical_op__input_carry$next[1:0]$9627 - assign $0\logical_op__insn$next[31:0]$9610 $1\logical_op__insn$next[31:0]$9628 - assign $0\logical_op__insn_type$next[6:0]$9611 $1\logical_op__insn_type$next[6:0]$9629 - assign $0\logical_op__invert_in$next[0:0]$9612 $1\logical_op__invert_in$next[0:0]$9630 - assign $0\logical_op__invert_out$next[0:0]$9613 $1\logical_op__invert_out$next[0:0]$9631 - assign $0\logical_op__is_32bit$next[0:0]$9614 $1\logical_op__is_32bit$next[0:0]$9632 - assign $0\logical_op__is_signed$next[0:0]$9615 $1\logical_op__is_signed$next[0:0]$9633 + assign $0\logical_op__input_carry$next[1:0]$10007 $1\logical_op__input_carry$next[1:0]$10025 + assign $0\logical_op__insn$next[31:0]$10008 $1\logical_op__insn$next[31:0]$10026 + assign $0\logical_op__insn_type$next[6:0]$10009 $1\logical_op__insn_type$next[6:0]$10027 + assign $0\logical_op__invert_in$next[0:0]$10010 $1\logical_op__invert_in$next[0:0]$10028 + assign $0\logical_op__invert_out$next[0:0]$10011 $1\logical_op__invert_out$next[0:0]$10029 + assign $0\logical_op__is_32bit$next[0:0]$10012 $1\logical_op__is_32bit$next[0:0]$10030 + assign $0\logical_op__is_signed$next[0:0]$10013 $1\logical_op__is_signed$next[0:0]$10031 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$9618 $1\logical_op__output_carry$next[0:0]$9636 + assign $0\logical_op__output_carry$next[0:0]$10016 $1\logical_op__output_carry$next[0:0]$10034 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$9621 $1\logical_op__write_cr0$next[0:0]$9639 - assign $0\logical_op__zero_a$next[0:0]$9622 $1\logical_op__zero_a$next[0:0]$9640 - assign $0\logical_op__imm_data__data$next[63:0]$9607 $2\logical_op__imm_data__data$next[63:0]$9641 - assign $0\logical_op__imm_data__ok$next[0:0]$9608 $2\logical_op__imm_data__ok$next[0:0]$9642 - assign $0\logical_op__oe__oe$next[0:0]$9616 $2\logical_op__oe__oe$next[0:0]$9643 - assign $0\logical_op__oe__ok$next[0:0]$9617 $2\logical_op__oe__ok$next[0:0]$9644 - assign $0\logical_op__rc__ok$next[0:0]$9619 $2\logical_op__rc__ok$next[0:0]$9645 - assign $0\logical_op__rc__rc$next[0:0]$9620 $2\logical_op__rc__rc$next[0:0]$9646 - attribute \src "libresoc.v:160246.5-160246.29" + assign $0\logical_op__write_cr0$next[0:0]$10019 $1\logical_op__write_cr0$next[0:0]$10037 + assign $0\logical_op__zero_a$next[0:0]$10020 $1\logical_op__zero_a$next[0:0]$10038 + assign $0\logical_op__imm_data__data$next[63:0]$10005 $2\logical_op__imm_data__data$next[63:0]$10039 + assign $0\logical_op__imm_data__ok$next[0:0]$10006 $2\logical_op__imm_data__ok$next[0:0]$10040 + assign $0\logical_op__oe__oe$next[0:0]$10014 $2\logical_op__oe__oe$next[0:0]$10041 + assign $0\logical_op__oe__ok$next[0:0]$10015 $2\logical_op__oe__ok$next[0:0]$10042 + assign $0\logical_op__rc__ok$next[0:0]$10017 $2\logical_op__rc__ok$next[0:0]$10043 + assign $0\logical_op__rc__rc$next[0:0]$10018 $2\logical_op__rc__rc$next[0:0]$10044 + attribute \src "libresoc.v:163661.5-163661.29" switch \initial - attribute \src "libresoc.v:160246.9-160246.17" + attribute \src "libresoc.v:163661.9-163661.17" case 1'1 case end @@ -328370,7 +336289,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$9628 $1\logical_op__data_len$next[3:0]$9623 $1\logical_op__is_signed$next[0:0]$9633 $1\logical_op__is_32bit$next[0:0]$9632 $1\logical_op__output_carry$next[0:0]$9636 $1\logical_op__write_cr0$next[0:0]$9639 $1\logical_op__invert_out$next[0:0]$9631 $1\logical_op__input_carry$next[1:0]$9627 $1\logical_op__zero_a$next[0:0]$9640 $1\logical_op__invert_in$next[0:0]$9630 $1\logical_op__oe__ok$next[0:0]$9635 $1\logical_op__oe__oe$next[0:0]$9634 $1\logical_op__rc__ok$next[0:0]$9637 $1\logical_op__rc__rc$next[0:0]$9638 $1\logical_op__imm_data__ok$next[0:0]$9626 $1\logical_op__imm_data__data$next[63:0]$9625 $1\logical_op__fn_unit$next[11:0]$9624 $1\logical_op__insn_type$next[6:0]$9629 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10026 $1\logical_op__data_len$next[3:0]$10021 $1\logical_op__is_signed$next[0:0]$10031 $1\logical_op__is_32bit$next[0:0]$10030 $1\logical_op__output_carry$next[0:0]$10034 $1\logical_op__write_cr0$next[0:0]$10037 $1\logical_op__invert_out$next[0:0]$10029 $1\logical_op__input_carry$next[1:0]$10025 $1\logical_op__zero_a$next[0:0]$10038 $1\logical_op__invert_in$next[0:0]$10028 $1\logical_op__oe__ok$next[0:0]$10033 $1\logical_op__oe__oe$next[0:0]$10032 $1\logical_op__rc__ok$next[0:0]$10035 $1\logical_op__rc__rc$next[0:0]$10036 $1\logical_op__imm_data__ok$next[0:0]$10024 $1\logical_op__imm_data__data$next[63:0]$10023 $1\logical_op__fn_unit$next[11:0]$10022 $1\logical_op__insn_type$next[6:0]$10027 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -328391,26 +336310,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$9628 $1\logical_op__data_len$next[3:0]$9623 $1\logical_op__is_signed$next[0:0]$9633 $1\logical_op__is_32bit$next[0:0]$9632 $1\logical_op__output_carry$next[0:0]$9636 $1\logical_op__write_cr0$next[0:0]$9639 $1\logical_op__invert_out$next[0:0]$9631 $1\logical_op__input_carry$next[1:0]$9627 $1\logical_op__zero_a$next[0:0]$9640 $1\logical_op__invert_in$next[0:0]$9630 $1\logical_op__oe__ok$next[0:0]$9635 $1\logical_op__oe__oe$next[0:0]$9634 $1\logical_op__rc__ok$next[0:0]$9637 $1\logical_op__rc__rc$next[0:0]$9638 $1\logical_op__imm_data__ok$next[0:0]$9626 $1\logical_op__imm_data__data$next[63:0]$9625 $1\logical_op__fn_unit$next[11:0]$9624 $1\logical_op__insn_type$next[6:0]$9629 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10026 $1\logical_op__data_len$next[3:0]$10021 $1\logical_op__is_signed$next[0:0]$10031 $1\logical_op__is_32bit$next[0:0]$10030 $1\logical_op__output_carry$next[0:0]$10034 $1\logical_op__write_cr0$next[0:0]$10037 $1\logical_op__invert_out$next[0:0]$10029 $1\logical_op__input_carry$next[1:0]$10025 $1\logical_op__zero_a$next[0:0]$10038 $1\logical_op__invert_in$next[0:0]$10028 $1\logical_op__oe__ok$next[0:0]$10033 $1\logical_op__oe__oe$next[0:0]$10032 $1\logical_op__rc__ok$next[0:0]$10035 $1\logical_op__rc__rc$next[0:0]$10036 $1\logical_op__imm_data__ok$next[0:0]$10024 $1\logical_op__imm_data__data$next[63:0]$10023 $1\logical_op__fn_unit$next[11:0]$10022 $1\logical_op__insn_type$next[6:0]$10027 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$9623 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$9624 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$9625 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$9626 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$9627 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$9628 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$9629 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$9630 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$9631 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$9632 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$9633 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$9634 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$9635 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$9636 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$9637 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$9638 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$9639 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$9640 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10021 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$10022 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10023 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10024 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10025 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10026 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10027 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10028 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10029 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10030 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10031 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10032 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10033 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10034 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10035 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10036 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10037 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10038 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -328422,48 +336341,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$9642 1'0 - assign $2\logical_op__rc__rc$next[0:0]$9646 1'0 - assign $2\logical_op__rc__ok$next[0:0]$9645 1'0 - assign $2\logical_op__oe__oe$next[0:0]$9643 1'0 - assign $2\logical_op__oe__ok$next[0:0]$9644 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10039 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10040 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10044 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10043 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10041 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10042 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$9641 $1\logical_op__imm_data__data$next[63:0]$9625 - assign $2\logical_op__imm_data__ok$next[0:0]$9642 $1\logical_op__imm_data__ok$next[0:0]$9626 - assign $2\logical_op__oe__oe$next[0:0]$9643 $1\logical_op__oe__oe$next[0:0]$9634 - assign $2\logical_op__oe__ok$next[0:0]$9644 $1\logical_op__oe__ok$next[0:0]$9635 - assign $2\logical_op__rc__ok$next[0:0]$9645 $1\logical_op__rc__ok$next[0:0]$9637 - assign $2\logical_op__rc__rc$next[0:0]$9646 $1\logical_op__rc__rc$next[0:0]$9638 + assign $2\logical_op__imm_data__data$next[63:0]$10039 $1\logical_op__imm_data__data$next[63:0]$10023 + assign $2\logical_op__imm_data__ok$next[0:0]$10040 $1\logical_op__imm_data__ok$next[0:0]$10024 + assign $2\logical_op__oe__oe$next[0:0]$10041 $1\logical_op__oe__oe$next[0:0]$10032 + assign $2\logical_op__oe__ok$next[0:0]$10042 $1\logical_op__oe__ok$next[0:0]$10033 + assign $2\logical_op__rc__ok$next[0:0]$10043 $1\logical_op__rc__ok$next[0:0]$10035 + assign $2\logical_op__rc__rc$next[0:0]$10044 $1\logical_op__rc__rc$next[0:0]$10036 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9605 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9606 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9607 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9608 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9609 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9610 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9611 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9612 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9613 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9614 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9615 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9616 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9617 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9618 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9619 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9620 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9621 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9622 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10003 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$10004 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10005 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10006 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10007 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10008 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10009 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10010 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10011 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10012 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10013 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10014 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10015 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10016 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10017 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10018 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10019 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10020 end - attribute \src "libresoc.v:160287.3-160299.6" - process $proc$libresoc.v:160287$9647 + attribute \src "libresoc.v:163702.3-163714.6" + process $proc$libresoc.v:163702$10045 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9648 $1\ra$next[63:0]$9649 - attribute \src "libresoc.v:160288.5-160288.29" + assign $0\ra$next[63:0]$10046 $1\ra$next[63:0]$10047 + attribute \src "libresoc.v:163703.5-163703.29" switch \initial - attribute \src "libresoc.v:160288.9-160288.17" + attribute \src "libresoc.v:163703.9-163703.17" case 1'1 case end @@ -328472,25 +336391,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9649 \ra$87 + assign $1\ra$next[63:0]$10047 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9649 \ra$87 + assign $1\ra$next[63:0]$10047 \ra$87 case - assign $1\ra$next[63:0]$9649 \ra + assign $1\ra$next[63:0]$10047 \ra end sync always - update \ra$next $0\ra$next[63:0]$9648 + update \ra$next $0\ra$next[63:0]$10046 end - attribute \src "libresoc.v:160300.3-160312.6" - process $proc$libresoc.v:160300$9650 + attribute \src "libresoc.v:163715.3-163727.6" + process $proc$libresoc.v:163715$10048 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9651 $1\rb$next[63:0]$9652 - attribute \src "libresoc.v:160301.5-160301.29" + assign $0\rb$next[63:0]$10049 $1\rb$next[63:0]$10050 + attribute \src "libresoc.v:163716.5-163716.29" switch \initial - attribute \src "libresoc.v:160301.9-160301.17" + attribute \src "libresoc.v:163716.9-163716.17" case 1'1 case end @@ -328499,25 +336418,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9652 \rb$89 + assign $1\rb$next[63:0]$10050 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9652 \rb$89 + assign $1\rb$next[63:0]$10050 \rb$89 case - assign $1\rb$next[63:0]$9652 \rb + assign $1\rb$next[63:0]$10050 \rb end sync always - update \rb$next $0\rb$next[63:0]$9651 + update \rb$next $0\rb$next[63:0]$10049 end - attribute \src "libresoc.v:160313.3-160325.6" - process $proc$libresoc.v:160313$9653 + attribute \src "libresoc.v:163728.3-163740.6" + process $proc$libresoc.v:163728$10051 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9654 $1\xer_so$next[0:0]$9655 - attribute \src "libresoc.v:160314.5-160314.29" + assign $0\xer_so$next[0:0]$10052 $1\xer_so$next[0:0]$10053 + attribute \src "libresoc.v:163729.5-163729.29" switch \initial - attribute \src "libresoc.v:160314.9-160314.17" + attribute \src "libresoc.v:163729.9-163729.17" case 1'1 case end @@ -328526,18 +336445,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$9655 \xer_so$91 + assign $1\xer_so$next[0:0]$10053 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$9655 \xer_so$91 + assign $1\xer_so$next[0:0]$10053 \xer_so$91 case - assign $1\xer_so$next[0:0]$9655 \xer_so + assign $1\xer_so$next[0:0]$10053 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$9654 + update \xer_so$next $0\xer_so$next[0:0]$10052 end - connect \$66 $and$libresoc.v:159941$9541_Y + connect \$66 $and$libresoc.v:163356$9939_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -328569,191 +336488,202 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:160360.1-161002.10" +attribute \src "libresoc.v:163775.1-163781.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:78" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:79" + wire output 2 \clk_pll_o + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:163785.1-164427.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:160361.7-160361.20" + attribute \src "libresoc.v:163786.7-163786.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160849.3-160875.6" + attribute \src "libresoc.v:164274.3-164300.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160849.3-160875.6" + attribute \src "libresoc.v:164274.3-164300.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160773.19-160773.132" - wire width 4 $add$libresoc.v:160773$9688_Y - attribute \src "libresoc.v:160774.19-160774.132" - wire width 4 $add$libresoc.v:160774$9689_Y - attribute \src "libresoc.v:160775.19-160775.132" - wire width 4 $add$libresoc.v:160775$9690_Y - attribute \src "libresoc.v:160776.19-160776.132" - wire width 4 $add$libresoc.v:160776$9691_Y - attribute \src "libresoc.v:160777.19-160777.134" - wire width 4 $add$libresoc.v:160777$9692_Y - attribute \src "libresoc.v:160778.19-160778.134" - wire width 4 $add$libresoc.v:160778$9693_Y - attribute \src "libresoc.v:160779.18-160779.125" - wire width 3 $add$libresoc.v:160779$9694_Y - attribute \src "libresoc.v:160780.19-160780.134" - wire width 4 $add$libresoc.v:160780$9695_Y - attribute \src "libresoc.v:160781.19-160781.134" - wire width 4 $add$libresoc.v:160781$9696_Y - attribute \src "libresoc.v:160782.19-160782.134" - wire width 4 $add$libresoc.v:160782$9697_Y - attribute \src "libresoc.v:160783.19-160783.134" - wire width 4 $add$libresoc.v:160783$9698_Y - attribute \src "libresoc.v:160784.19-160784.134" - wire width 4 $add$libresoc.v:160784$9699_Y - attribute \src "libresoc.v:160785.19-160785.134" - wire width 4 $add$libresoc.v:160785$9700_Y - attribute \src "libresoc.v:160786.19-160786.134" - wire width 4 $add$libresoc.v:160786$9701_Y - attribute \src "libresoc.v:160787.19-160787.134" - wire width 4 $add$libresoc.v:160787$9702_Y - attribute \src "libresoc.v:160788.19-160788.134" - wire width 4 $add$libresoc.v:160788$9703_Y - attribute \src "libresoc.v:160789.19-160789.132" - wire width 5 $add$libresoc.v:160789$9704_Y - attribute \src "libresoc.v:160790.18-160790.125" - wire width 3 $add$libresoc.v:160790$9705_Y - attribute \src "libresoc.v:160791.19-160791.132" - wire width 5 $add$libresoc.v:160791$9706_Y - attribute \src "libresoc.v:160792.19-160792.132" - wire width 5 $add$libresoc.v:160792$9707_Y - attribute \src "libresoc.v:160793.19-160793.132" - wire width 5 $add$libresoc.v:160793$9708_Y - attribute \src "libresoc.v:160794.19-160794.132" - wire width 5 $add$libresoc.v:160794$9709_Y - attribute \src "libresoc.v:160795.19-160795.134" - wire width 5 $add$libresoc.v:160795$9710_Y - attribute \src "libresoc.v:160796.19-160796.134" - wire width 5 $add$libresoc.v:160796$9711_Y - attribute \src "libresoc.v:160797.19-160797.134" - wire width 5 $add$libresoc.v:160797$9712_Y - attribute \src "libresoc.v:160798.19-160798.132" - wire width 6 $add$libresoc.v:160798$9713_Y - attribute \src "libresoc.v:160799.19-160799.132" - wire width 6 $add$libresoc.v:160799$9714_Y - attribute \src "libresoc.v:160800.19-160800.132" - wire width 6 $add$libresoc.v:160800$9715_Y - attribute \src "libresoc.v:160801.18-160801.127" - wire width 3 $add$libresoc.v:160801$9716_Y - attribute \src "libresoc.v:160802.19-160802.132" - wire width 6 $add$libresoc.v:160802$9717_Y - attribute \src "libresoc.v:160803.19-160803.132" - wire width 7 $add$libresoc.v:160803$9718_Y - attribute \src "libresoc.v:160804.19-160804.132" - wire width 7 $add$libresoc.v:160804$9719_Y - attribute \src "libresoc.v:160805.19-160805.132" - wire width 8 $add$libresoc.v:160805$9720_Y - attribute \src "libresoc.v:160816.18-160816.127" - wire width 3 $add$libresoc.v:160816$9739_Y - attribute \src "libresoc.v:160820.18-160820.127" - wire width 3 $add$libresoc.v:160820$9746_Y - attribute \src "libresoc.v:160821.18-160821.127" - wire width 3 $add$libresoc.v:160821$9747_Y - attribute \src "libresoc.v:160822.17-160822.124" - wire width 3 $add$libresoc.v:160822$9748_Y - attribute \src "libresoc.v:160823.18-160823.127" - wire width 3 $add$libresoc.v:160823$9749_Y - attribute \src "libresoc.v:160824.18-160824.127" - wire width 3 $add$libresoc.v:160824$9750_Y - attribute \src "libresoc.v:160825.18-160825.127" - wire width 3 $add$libresoc.v:160825$9751_Y - attribute \src "libresoc.v:160826.18-160826.127" - wire width 3 $add$libresoc.v:160826$9752_Y - attribute \src "libresoc.v:160827.18-160827.127" - wire width 3 $add$libresoc.v:160827$9753_Y - attribute \src "libresoc.v:160828.18-160828.127" - wire width 3 $add$libresoc.v:160828$9754_Y - attribute \src "libresoc.v:160829.18-160829.127" - wire width 3 $add$libresoc.v:160829$9755_Y - attribute \src "libresoc.v:160830.18-160830.127" - wire width 3 $add$libresoc.v:160830$9756_Y - attribute \src "libresoc.v:160831.18-160831.127" - wire width 3 $add$libresoc.v:160831$9757_Y - attribute \src "libresoc.v:160832.18-160832.127" - wire width 3 $add$libresoc.v:160832$9758_Y - attribute \src "libresoc.v:160833.17-160833.124" - wire width 3 $add$libresoc.v:160833$9759_Y - attribute \src "libresoc.v:160834.18-160834.127" - wire width 3 $add$libresoc.v:160834$9760_Y - attribute \src "libresoc.v:160835.18-160835.127" - wire width 3 $add$libresoc.v:160835$9761_Y - attribute \src "libresoc.v:160836.18-160836.127" - wire width 3 $add$libresoc.v:160836$9762_Y - attribute \src "libresoc.v:160837.18-160837.127" - wire width 3 $add$libresoc.v:160837$9763_Y - attribute \src "libresoc.v:160838.18-160838.127" - wire width 3 $add$libresoc.v:160838$9764_Y - attribute \src "libresoc.v:160839.18-160839.127" - wire width 3 $add$libresoc.v:160839$9765_Y - attribute \src "libresoc.v:160840.18-160840.127" - wire width 3 $add$libresoc.v:160840$9766_Y - attribute \src "libresoc.v:160841.18-160841.127" - wire width 3 $add$libresoc.v:160841$9767_Y - attribute \src "libresoc.v:160842.18-160842.127" - wire width 3 $add$libresoc.v:160842$9768_Y - attribute \src "libresoc.v:160843.18-160843.127" - wire width 3 $add$libresoc.v:160843$9769_Y - attribute \src "libresoc.v:160844.17-160844.124" - wire width 3 $add$libresoc.v:160844$9770_Y - attribute \src "libresoc.v:160845.18-160845.127" - wire width 3 $add$libresoc.v:160845$9771_Y - attribute \src "libresoc.v:160846.18-160846.127" - wire width 3 $add$libresoc.v:160846$9772_Y - attribute \src "libresoc.v:160847.18-160847.127" - wire width 3 $add$libresoc.v:160847$9773_Y - attribute \src "libresoc.v:160848.18-160848.131" - wire width 4 $add$libresoc.v:160848$9774_Y - attribute \src "libresoc.v:160806.19-160806.111" - wire $eq$libresoc.v:160806$9721_Y - attribute \src "libresoc.v:160807.19-160807.111" - wire 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wire width 8 $extend$libresoc.v:164236$10127_Y + attribute \src "libresoc.v:164237.19-164237.104" + wire width 8 $extend$libresoc.v:164237$10129_Y + attribute \src "libresoc.v:164238.19-164238.104" + wire width 8 $extend$libresoc.v:164238$10131_Y + attribute \src "libresoc.v:164239.19-164239.104" + wire width 8 $extend$libresoc.v:164239$10133_Y + attribute \src "libresoc.v:164240.19-164240.104" + wire width 8 $extend$libresoc.v:164240$10135_Y + attribute \src "libresoc.v:164242.19-164242.104" + wire width 32 $extend$libresoc.v:164242$10138_Y + attribute \src "libresoc.v:164243.19-164243.104" + wire width 32 $extend$libresoc.v:164243$10140_Y + attribute \src "libresoc.v:164244.19-164244.104" + wire width 64 $extend$libresoc.v:164244$10142_Y + attribute \src "libresoc.v:164233.19-164233.104" + wire width 8 $pos$libresoc.v:164233$10122_Y + attribute \src "libresoc.v:164234.19-164234.104" + wire width 8 $pos$libresoc.v:164234$10124_Y + attribute \src "libresoc.v:164235.19-164235.104" + wire width 8 $pos$libresoc.v:164235$10126_Y + attribute \src "libresoc.v:164236.19-164236.104" + wire width 8 $pos$libresoc.v:164236$10128_Y + attribute \src "libresoc.v:164237.19-164237.104" + wire width 8 $pos$libresoc.v:164237$10130_Y + attribute \src "libresoc.v:164238.19-164238.104" + wire width 8 $pos$libresoc.v:164238$10132_Y + attribute \src "libresoc.v:164239.19-164239.104" + wire width 8 $pos$libresoc.v:164239$10134_Y + attribute \src "libresoc.v:164240.19-164240.104" + wire width 8 $pos$libresoc.v:164240$10136_Y + attribute \src "libresoc.v:164242.19-164242.104" + wire width 32 $pos$libresoc.v:164242$10139_Y + attribute \src "libresoc.v:164243.19-164243.104" + wire width 32 $pos$libresoc.v:164243$10141_Y + attribute \src "libresoc.v:164244.19-164244.104" + wire width 64 $pos$libresoc.v:164244$10143_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -329036,7 +336966,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:160361.7-160361.15" + attribute \src "libresoc.v:163786.7-163786.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -329167,7 +337097,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160773$9688 + cell $add $add$libresoc.v:164198$10086 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329175,10 +337105,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:160773$9688_Y + connect \Y $add$libresoc.v:164198$10086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160774$9689 + cell $add $add$libresoc.v:164199$10087 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329186,10 +337116,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:160774$9689_Y + connect \Y $add$libresoc.v:164199$10087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160775$9690 + cell $add $add$libresoc.v:164200$10088 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329197,10 +337127,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:160775$9690_Y + connect \Y $add$libresoc.v:164200$10088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160776$9691 + cell $add $add$libresoc.v:164201$10089 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329208,10 +337138,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:160776$9691_Y + connect \Y $add$libresoc.v:164201$10089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160777$9692 + cell $add $add$libresoc.v:164202$10090 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329219,10 +337149,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:160777$9692_Y + connect \Y $add$libresoc.v:164202$10090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160778$9693 + cell $add $add$libresoc.v:164203$10091 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329230,10 +337160,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:160778$9693_Y + connect \Y $add$libresoc.v:164203$10091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160779$9694 + cell $add $add$libresoc.v:164204$10092 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329241,10 +337171,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:160779$9694_Y + connect \Y $add$libresoc.v:164204$10092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160780$9695 + cell $add $add$libresoc.v:164205$10093 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329252,10 +337182,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:160780$9695_Y + connect \Y $add$libresoc.v:164205$10093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160781$9696 + cell $add $add$libresoc.v:164206$10094 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329263,10 +337193,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:160781$9696_Y + connect \Y $add$libresoc.v:164206$10094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160782$9697 + cell $add $add$libresoc.v:164207$10095 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329274,10 +337204,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:160782$9697_Y + connect \Y $add$libresoc.v:164207$10095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160783$9698 + cell $add $add$libresoc.v:164208$10096 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329285,10 +337215,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:160783$9698_Y + connect \Y $add$libresoc.v:164208$10096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160784$9699 + cell $add $add$libresoc.v:164209$10097 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329296,10 +337226,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:160784$9699_Y + connect \Y $add$libresoc.v:164209$10097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160785$9700 + cell $add $add$libresoc.v:164210$10098 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329307,10 +337237,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:160785$9700_Y + connect \Y $add$libresoc.v:164210$10098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160786$9701 + cell $add $add$libresoc.v:164211$10099 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329318,10 +337248,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:160786$9701_Y + connect \Y $add$libresoc.v:164211$10099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160787$9702 + cell $add $add$libresoc.v:164212$10100 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329329,10 +337259,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:160787$9702_Y + connect \Y $add$libresoc.v:164212$10100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160788$9703 + cell $add $add$libresoc.v:164213$10101 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329340,10 +337270,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:160788$9703_Y + connect \Y $add$libresoc.v:164213$10101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160789$9704 + cell $add $add$libresoc.v:164214$10102 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329351,10 +337281,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:160789$9704_Y + connect \Y $add$libresoc.v:164214$10102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160790$9705 + cell $add $add$libresoc.v:164215$10103 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329362,10 +337292,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:160790$9705_Y + connect \Y $add$libresoc.v:164215$10103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160791$9706 + cell $add $add$libresoc.v:164216$10104 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329373,10 +337303,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:160791$9706_Y + connect \Y $add$libresoc.v:164216$10104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160792$9707 + cell $add $add$libresoc.v:164217$10105 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329384,10 +337314,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:160792$9707_Y + connect \Y $add$libresoc.v:164217$10105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160793$9708 + cell $add $add$libresoc.v:164218$10106 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329395,10 +337325,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:160793$9708_Y + connect \Y $add$libresoc.v:164218$10106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160794$9709 + cell $add $add$libresoc.v:164219$10107 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329406,10 +337336,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:160794$9709_Y + connect \Y $add$libresoc.v:164219$10107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160795$9710 + cell $add $add$libresoc.v:164220$10108 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329417,10 +337347,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:160795$9710_Y + connect \Y $add$libresoc.v:164220$10108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160796$9711 + cell $add $add$libresoc.v:164221$10109 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329428,10 +337358,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:160796$9711_Y + connect \Y $add$libresoc.v:164221$10109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160797$9712 + cell $add $add$libresoc.v:164222$10110 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -329439,10 +337369,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:160797$9712_Y + connect \Y $add$libresoc.v:164222$10110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160798$9713 + cell $add $add$libresoc.v:164223$10111 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -329450,10 +337380,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:160798$9713_Y + connect \Y $add$libresoc.v:164223$10111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160799$9714 + cell $add $add$libresoc.v:164224$10112 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -329461,10 +337391,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:160799$9714_Y + connect \Y $add$libresoc.v:164224$10112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160800$9715 + cell $add $add$libresoc.v:164225$10113 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -329472,10 +337402,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:160800$9715_Y + connect \Y $add$libresoc.v:164225$10113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160801$9716 + cell $add $add$libresoc.v:164226$10114 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329483,10 +337413,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:160801$9716_Y + connect \Y $add$libresoc.v:164226$10114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160802$9717 + cell $add $add$libresoc.v:164227$10115 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -329494,10 +337424,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:160802$9717_Y + connect \Y $add$libresoc.v:164227$10115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160803$9718 + cell $add $add$libresoc.v:164228$10116 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329505,10 +337435,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:160803$9718_Y + connect \Y $add$libresoc.v:164228$10116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160804$9719 + cell $add $add$libresoc.v:164229$10117 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329516,10 +337446,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:160804$9719_Y + connect \Y $add$libresoc.v:164229$10117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160805$9720 + cell $add $add$libresoc.v:164230$10118 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -329527,10 +337457,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:160805$9720_Y + connect \Y $add$libresoc.v:164230$10118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160816$9739 + cell $add $add$libresoc.v:164241$10137 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329538,10 +337468,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:160816$9739_Y + connect \Y $add$libresoc.v:164241$10137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160820$9746 + cell $add $add$libresoc.v:164245$10144 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329549,10 +337479,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:160820$9746_Y + connect \Y $add$libresoc.v:164245$10144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160821$9747 + cell $add $add$libresoc.v:164246$10145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329560,10 +337490,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:160821$9747_Y + connect \Y $add$libresoc.v:164246$10145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160822$9748 + cell $add $add$libresoc.v:164247$10146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329571,10 +337501,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:160822$9748_Y + connect \Y $add$libresoc.v:164247$10146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160823$9749 + cell $add $add$libresoc.v:164248$10147 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329582,10 +337512,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:160823$9749_Y + connect \Y $add$libresoc.v:164248$10147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160824$9750 + cell $add $add$libresoc.v:164249$10148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329593,10 +337523,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:160824$9750_Y + connect \Y $add$libresoc.v:164249$10148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160825$9751 + cell $add $add$libresoc.v:164250$10149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329604,10 +337534,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:160825$9751_Y + connect \Y $add$libresoc.v:164250$10149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160826$9752 + cell $add $add$libresoc.v:164251$10150 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329615,10 +337545,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:160826$9752_Y + connect \Y $add$libresoc.v:164251$10150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160827$9753 + cell $add $add$libresoc.v:164252$10151 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329626,10 +337556,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:160827$9753_Y + connect \Y $add$libresoc.v:164252$10151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160828$9754 + cell $add $add$libresoc.v:164253$10152 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329637,10 +337567,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:160828$9754_Y + connect \Y $add$libresoc.v:164253$10152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160829$9755 + cell $add $add$libresoc.v:164254$10153 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329648,10 +337578,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:160829$9755_Y + connect \Y $add$libresoc.v:164254$10153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160830$9756 + cell $add $add$libresoc.v:164255$10154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329659,10 +337589,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:160830$9756_Y + connect \Y $add$libresoc.v:164255$10154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160831$9757 + cell $add $add$libresoc.v:164256$10155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329670,10 +337600,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:160831$9757_Y + connect \Y $add$libresoc.v:164256$10155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160832$9758 + cell $add $add$libresoc.v:164257$10156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329681,10 +337611,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:160832$9758_Y + connect \Y $add$libresoc.v:164257$10156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160833$9759 + cell $add $add$libresoc.v:164258$10157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329692,10 +337622,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:160833$9759_Y + connect \Y $add$libresoc.v:164258$10157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160834$9760 + cell $add $add$libresoc.v:164259$10158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329703,10 +337633,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:160834$9760_Y + connect \Y $add$libresoc.v:164259$10158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160835$9761 + cell $add $add$libresoc.v:164260$10159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329714,10 +337644,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:160835$9761_Y + connect \Y $add$libresoc.v:164260$10159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160836$9762 + cell $add $add$libresoc.v:164261$10160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329725,10 +337655,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:160836$9762_Y + connect \Y $add$libresoc.v:164261$10160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160837$9763 + cell $add $add$libresoc.v:164262$10161 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329736,10 +337666,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:160837$9763_Y + connect \Y $add$libresoc.v:164262$10161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160838$9764 + cell $add $add$libresoc.v:164263$10162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329747,10 +337677,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:160838$9764_Y + connect \Y $add$libresoc.v:164263$10162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160839$9765 + cell $add $add$libresoc.v:164264$10163 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329758,10 +337688,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:160839$9765_Y + connect \Y $add$libresoc.v:164264$10163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160840$9766 + cell $add $add$libresoc.v:164265$10164 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329769,10 +337699,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:160840$9766_Y + connect \Y $add$libresoc.v:164265$10164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160841$9767 + cell $add $add$libresoc.v:164266$10165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329780,10 +337710,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:160841$9767_Y + connect \Y $add$libresoc.v:164266$10165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160842$9768 + cell $add $add$libresoc.v:164267$10166 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329791,10 +337721,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:160842$9768_Y + connect \Y $add$libresoc.v:164267$10166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160843$9769 + cell $add $add$libresoc.v:164268$10167 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329802,10 +337732,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:160843$9769_Y + connect \Y $add$libresoc.v:164268$10167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160844$9770 + cell $add $add$libresoc.v:164269$10168 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329813,10 +337743,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:160844$9770_Y + connect \Y $add$libresoc.v:164269$10168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160845$9771 + cell $add $add$libresoc.v:164270$10169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329824,10 +337754,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:160845$9771_Y + connect \Y $add$libresoc.v:164270$10169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160846$9772 + cell $add $add$libresoc.v:164271$10170 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329835,10 +337765,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:160846$9772_Y + connect \Y $add$libresoc.v:164271$10170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160847$9773 + cell $add $add$libresoc.v:164272$10171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -329846,10 +337776,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:160847$9773_Y + connect \Y $add$libresoc.v:164272$10171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:160848$9774 + cell $add $add$libresoc.v:164273$10172 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -329857,10 +337787,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:160848$9774_Y + connect \Y $add$libresoc.v:164273$10172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:160806$9721 + cell $eq $eq$libresoc.v:164231$10119 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -329868,10 +337798,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:160806$9721_Y + connect \Y $eq$libresoc.v:164231$10119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:160807$9722 + cell $eq $eq$libresoc.v:164232$10120 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -329879,199 +337809,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:160807$9722_Y + connect \Y $eq$libresoc.v:164232$10120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160808$9723 + cell $pos $extend$libresoc.v:164233$10121 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:160808$9723_Y + connect \Y $extend$libresoc.v:164233$10121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160809$9725 + cell $pos $extend$libresoc.v:164234$10123 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:160809$9725_Y + connect \Y $extend$libresoc.v:164234$10123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160810$9727 + cell $pos $extend$libresoc.v:164235$10125 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:160810$9727_Y + connect \Y $extend$libresoc.v:164235$10125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160811$9729 + cell $pos $extend$libresoc.v:164236$10127 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:160811$9729_Y + connect \Y $extend$libresoc.v:164236$10127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160812$9731 + cell $pos $extend$libresoc.v:164237$10129 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:160812$9731_Y + connect \Y $extend$libresoc.v:164237$10129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160813$9733 + cell $pos $extend$libresoc.v:164238$10131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:160813$9733_Y + connect \Y $extend$libresoc.v:164238$10131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160814$9735 + cell $pos $extend$libresoc.v:164239$10133 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:160814$9735_Y + connect \Y $extend$libresoc.v:164239$10133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160815$9737 + cell $pos $extend$libresoc.v:164240$10135 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:160815$9737_Y + connect \Y $extend$libresoc.v:164240$10135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160817$9740 + cell $pos $extend$libresoc.v:164242$10138 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:160817$9740_Y + connect \Y $extend$libresoc.v:164242$10138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160818$9742 + cell $pos $extend$libresoc.v:164243$10140 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:160818$9742_Y + connect \Y $extend$libresoc.v:164243$10140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:160819$9744 + cell $pos $extend$libresoc.v:164244$10142 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:160819$9744_Y + connect \Y $extend$libresoc.v:164244$10142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160808$9724 + cell $pos $pos$libresoc.v:164233$10122 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160808$9723_Y - connect \Y $pos$libresoc.v:160808$9724_Y + connect \A $extend$libresoc.v:164233$10121_Y + connect \Y $pos$libresoc.v:164233$10122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160809$9726 + cell $pos $pos$libresoc.v:164234$10124 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160809$9725_Y - connect \Y $pos$libresoc.v:160809$9726_Y + connect \A $extend$libresoc.v:164234$10123_Y + connect \Y $pos$libresoc.v:164234$10124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160810$9728 + cell $pos $pos$libresoc.v:164235$10126 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160810$9727_Y - connect \Y $pos$libresoc.v:160810$9728_Y + connect \A $extend$libresoc.v:164235$10125_Y + connect \Y $pos$libresoc.v:164235$10126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160811$9730 + cell $pos $pos$libresoc.v:164236$10128 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160811$9729_Y - connect \Y $pos$libresoc.v:160811$9730_Y + connect \A $extend$libresoc.v:164236$10127_Y + connect \Y $pos$libresoc.v:164236$10128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160812$9732 + cell $pos $pos$libresoc.v:164237$10130 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160812$9731_Y - connect \Y $pos$libresoc.v:160812$9732_Y + connect \A $extend$libresoc.v:164237$10129_Y + connect \Y $pos$libresoc.v:164237$10130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160813$9734 + cell $pos $pos$libresoc.v:164238$10132 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160813$9733_Y - connect \Y $pos$libresoc.v:160813$9734_Y + connect \A $extend$libresoc.v:164238$10131_Y + connect \Y $pos$libresoc.v:164238$10132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160814$9736 + cell $pos $pos$libresoc.v:164239$10134 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160814$9735_Y - connect \Y $pos$libresoc.v:160814$9736_Y + connect \A $extend$libresoc.v:164239$10133_Y + connect \Y $pos$libresoc.v:164239$10134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160815$9738 + cell $pos $pos$libresoc.v:164240$10136 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:160815$9737_Y - connect \Y $pos$libresoc.v:160815$9738_Y + connect \A $extend$libresoc.v:164240$10135_Y + connect \Y $pos$libresoc.v:164240$10136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160817$9741 + cell $pos $pos$libresoc.v:164242$10139 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:160817$9740_Y - connect \Y $pos$libresoc.v:160817$9741_Y + connect \A $extend$libresoc.v:164242$10138_Y + connect \Y $pos$libresoc.v:164242$10139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160818$9743 + cell $pos $pos$libresoc.v:164243$10141 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:160818$9742_Y - connect \Y $pos$libresoc.v:160818$9743_Y + connect \A $extend$libresoc.v:164243$10140_Y + connect \Y $pos$libresoc.v:164243$10141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:160819$9745 + cell $pos $pos$libresoc.v:164244$10143 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160819$9744_Y - connect \Y $pos$libresoc.v:160819$9745_Y + connect \A $extend$libresoc.v:164244$10142_Y + connect \Y $pos$libresoc.v:164244$10143_Y end - attribute \src "libresoc.v:160361.7-160361.20" - process $proc$libresoc.v:160361$9776 + attribute \src "libresoc.v:163786.7-163786.20" + process $proc$libresoc.v:163786$10174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160849.3-160875.6" - process $proc$libresoc.v:160849$9775 + attribute \src "libresoc.v:164274.3-164300.6" + process $proc$libresoc.v:164274$10173 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:160850.5-160850.29" + attribute \src "libresoc.v:164275.5-164275.29" switch \initial - attribute \src "libresoc.v:160850.9-160850.17" + attribute \src "libresoc.v:164275.9-164275.17" case 1'1 case end @@ -330101,82 +338031,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:160773$9688_Y - connect \$104 $add$libresoc.v:160774$9689_Y - connect \$107 $add$libresoc.v:160775$9690_Y - connect \$110 $add$libresoc.v:160776$9691_Y - connect \$113 $add$libresoc.v:160777$9692_Y - connect \$116 $add$libresoc.v:160778$9693_Y - connect \$11 $add$libresoc.v:160779$9694_Y - connect \$119 $add$libresoc.v:160780$9695_Y - connect \$122 $add$libresoc.v:160781$9696_Y - connect \$125 $add$libresoc.v:160782$9697_Y - connect \$128 $add$libresoc.v:160783$9698_Y - connect \$131 $add$libresoc.v:160784$9699_Y - connect \$134 $add$libresoc.v:160785$9700_Y - connect \$137 $add$libresoc.v:160786$9701_Y - connect \$140 $add$libresoc.v:160787$9702_Y - connect \$143 $add$libresoc.v:160788$9703_Y - connect \$146 $add$libresoc.v:160789$9704_Y - connect \$14 $add$libresoc.v:160790$9705_Y - connect \$149 $add$libresoc.v:160791$9706_Y - connect \$152 $add$libresoc.v:160792$9707_Y - connect \$155 $add$libresoc.v:160793$9708_Y - connect \$158 $add$libresoc.v:160794$9709_Y - connect \$161 $add$libresoc.v:160795$9710_Y - connect \$164 $add$libresoc.v:160796$9711_Y - connect \$167 $add$libresoc.v:160797$9712_Y - connect \$170 $add$libresoc.v:160798$9713_Y - connect \$173 $add$libresoc.v:160799$9714_Y - connect \$176 $add$libresoc.v:160800$9715_Y - connect \$17 $add$libresoc.v:160801$9716_Y - connect \$179 $add$libresoc.v:160802$9717_Y - connect \$182 $add$libresoc.v:160803$9718_Y - connect \$185 $add$libresoc.v:160804$9719_Y - connect \$188 $add$libresoc.v:160805$9720_Y - connect \$190 $eq$libresoc.v:160806$9721_Y - connect \$192 $eq$libresoc.v:160807$9722_Y - connect \$194 $pos$libresoc.v:160808$9724_Y - connect \$196 $pos$libresoc.v:160809$9726_Y - connect \$198 $pos$libresoc.v:160810$9728_Y - connect \$200 $pos$libresoc.v:160811$9730_Y - connect \$202 $pos$libresoc.v:160812$9732_Y - connect \$204 $pos$libresoc.v:160813$9734_Y - connect \$206 $pos$libresoc.v:160814$9736_Y - connect \$208 $pos$libresoc.v:160815$9738_Y - connect \$20 $add$libresoc.v:160816$9739_Y - connect \$210 $pos$libresoc.v:160817$9741_Y - connect \$212 $pos$libresoc.v:160818$9743_Y - connect \$214 $pos$libresoc.v:160819$9745_Y - connect \$23 $add$libresoc.v:160820$9746_Y - connect \$26 $add$libresoc.v:160821$9747_Y - connect \$2 $add$libresoc.v:160822$9748_Y - connect \$29 $add$libresoc.v:160823$9749_Y - connect \$32 $add$libresoc.v:160824$9750_Y - connect \$35 $add$libresoc.v:160825$9751_Y - connect \$38 $add$libresoc.v:160826$9752_Y - connect \$41 $add$libresoc.v:160827$9753_Y - connect \$44 $add$libresoc.v:160828$9754_Y - connect \$47 $add$libresoc.v:160829$9755_Y - connect \$50 $add$libresoc.v:160830$9756_Y - connect \$53 $add$libresoc.v:160831$9757_Y - connect \$56 $add$libresoc.v:160832$9758_Y - connect \$5 $add$libresoc.v:160833$9759_Y - connect \$59 $add$libresoc.v:160834$9760_Y - connect \$62 $add$libresoc.v:160835$9761_Y - connect \$65 $add$libresoc.v:160836$9762_Y - connect \$68 $add$libresoc.v:160837$9763_Y - connect \$71 $add$libresoc.v:160838$9764_Y - connect \$74 $add$libresoc.v:160839$9765_Y - connect \$77 $add$libresoc.v:160840$9766_Y - connect \$80 $add$libresoc.v:160841$9767_Y - connect \$83 $add$libresoc.v:160842$9768_Y - connect \$86 $add$libresoc.v:160843$9769_Y - connect \$8 $add$libresoc.v:160844$9770_Y - connect \$89 $add$libresoc.v:160845$9771_Y - connect \$92 $add$libresoc.v:160846$9772_Y - connect \$95 $add$libresoc.v:160847$9773_Y - connect \$98 $add$libresoc.v:160848$9774_Y + connect \$101 $add$libresoc.v:164198$10086_Y + connect \$104 $add$libresoc.v:164199$10087_Y + connect \$107 $add$libresoc.v:164200$10088_Y + connect \$110 $add$libresoc.v:164201$10089_Y + connect \$113 $add$libresoc.v:164202$10090_Y + connect \$116 $add$libresoc.v:164203$10091_Y + connect \$11 $add$libresoc.v:164204$10092_Y + connect \$119 $add$libresoc.v:164205$10093_Y + connect \$122 $add$libresoc.v:164206$10094_Y + connect \$125 $add$libresoc.v:164207$10095_Y + connect \$128 $add$libresoc.v:164208$10096_Y + connect \$131 $add$libresoc.v:164209$10097_Y + connect \$134 $add$libresoc.v:164210$10098_Y + connect \$137 $add$libresoc.v:164211$10099_Y + connect \$140 $add$libresoc.v:164212$10100_Y + connect \$143 $add$libresoc.v:164213$10101_Y + connect \$146 $add$libresoc.v:164214$10102_Y + connect \$14 $add$libresoc.v:164215$10103_Y + connect \$149 $add$libresoc.v:164216$10104_Y + connect \$152 $add$libresoc.v:164217$10105_Y + connect \$155 $add$libresoc.v:164218$10106_Y + connect \$158 $add$libresoc.v:164219$10107_Y + connect \$161 $add$libresoc.v:164220$10108_Y + connect \$164 $add$libresoc.v:164221$10109_Y + connect \$167 $add$libresoc.v:164222$10110_Y + connect \$170 $add$libresoc.v:164223$10111_Y + connect \$173 $add$libresoc.v:164224$10112_Y + connect \$176 $add$libresoc.v:164225$10113_Y + connect \$17 $add$libresoc.v:164226$10114_Y + connect \$179 $add$libresoc.v:164227$10115_Y + connect \$182 $add$libresoc.v:164228$10116_Y + connect \$185 $add$libresoc.v:164229$10117_Y + connect \$188 $add$libresoc.v:164230$10118_Y + connect \$190 $eq$libresoc.v:164231$10119_Y + connect \$192 $eq$libresoc.v:164232$10120_Y + connect \$194 $pos$libresoc.v:164233$10122_Y + connect \$196 $pos$libresoc.v:164234$10124_Y + connect \$198 $pos$libresoc.v:164235$10126_Y + connect \$200 $pos$libresoc.v:164236$10128_Y + connect \$202 $pos$libresoc.v:164237$10130_Y + connect \$204 $pos$libresoc.v:164238$10132_Y + connect \$206 $pos$libresoc.v:164239$10134_Y + connect \$208 $pos$libresoc.v:164240$10136_Y + connect \$20 $add$libresoc.v:164241$10137_Y + connect \$210 $pos$libresoc.v:164242$10139_Y + connect \$212 $pos$libresoc.v:164243$10141_Y + connect \$214 $pos$libresoc.v:164244$10143_Y + connect \$23 $add$libresoc.v:164245$10144_Y + connect \$26 $add$libresoc.v:164246$10145_Y + connect \$2 $add$libresoc.v:164247$10146_Y + connect \$29 $add$libresoc.v:164248$10147_Y + connect \$32 $add$libresoc.v:164249$10148_Y + connect \$35 $add$libresoc.v:164250$10149_Y + connect \$38 $add$libresoc.v:164251$10150_Y + connect \$41 $add$libresoc.v:164252$10151_Y + connect \$44 $add$libresoc.v:164253$10152_Y + connect \$47 $add$libresoc.v:164254$10153_Y + connect \$50 $add$libresoc.v:164255$10154_Y + connect \$53 $add$libresoc.v:164256$10155_Y + connect \$56 $add$libresoc.v:164257$10156_Y + connect \$5 $add$libresoc.v:164258$10157_Y + connect \$59 $add$libresoc.v:164259$10158_Y + connect \$62 $add$libresoc.v:164260$10159_Y + connect \$65 $add$libresoc.v:164261$10160_Y + connect \$68 $add$libresoc.v:164262$10161_Y + connect \$71 $add$libresoc.v:164263$10162_Y + connect \$74 $add$libresoc.v:164264$10163_Y + connect \$77 $add$libresoc.v:164265$10164_Y + connect \$80 $add$libresoc.v:164266$10165_Y + connect \$83 $add$libresoc.v:164267$10166_Y + connect \$86 $add$libresoc.v:164268$10167_Y + connect \$8 $add$libresoc.v:164269$10168_Y + connect \$89 $add$libresoc.v:164270$10169_Y + connect \$92 $add$libresoc.v:164271$10170_Y + connect \$95 $add$libresoc.v:164272$10171_Y + connect \$98 $add$libresoc.v:164273$10172_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -330304,43 +338234,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:161006.1-161090.10" +attribute \src "libresoc.v:164431.1-164515.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:161063.17-161063.91" - wire $not$libresoc.v:161063$9777_Y - attribute \src "libresoc.v:161065.18-161065.93" - wire $not$libresoc.v:161065$9779_Y - attribute \src "libresoc.v:161067.18-161067.93" - wire $not$libresoc.v:161067$9781_Y - attribute \src "libresoc.v:161068.17-161068.138" - wire width 8 $not$libresoc.v:161068$9782_Y - attribute \src "libresoc.v:161070.18-161070.93" - wire $not$libresoc.v:161070$9784_Y - attribute \src "libresoc.v:161072.18-161072.93" - wire $not$libresoc.v:161072$9786_Y - attribute \src "libresoc.v:161074.18-161074.93" - wire $not$libresoc.v:161074$9788_Y - attribute \src "libresoc.v:161077.17-161077.91" - wire $not$libresoc.v:161077$9791_Y - attribute \src "libresoc.v:161064.18-161064.116" - wire $reduce_or$libresoc.v:161064$9778_Y - attribute \src "libresoc.v:161066.18-161066.122" - wire $reduce_or$libresoc.v:161066$9780_Y - attribute \src "libresoc.v:161069.18-161069.128" - wire $reduce_or$libresoc.v:161069$9783_Y - attribute \src "libresoc.v:161071.18-161071.134" - wire $reduce_or$libresoc.v:161071$9785_Y - attribute \src "libresoc.v:161073.18-161073.140" - wire $reduce_or$libresoc.v:161073$9787_Y - attribute \src "libresoc.v:161075.18-161075.90" - wire $reduce_or$libresoc.v:161075$9789_Y - attribute \src "libresoc.v:161076.17-161076.103" - wire $reduce_or$libresoc.v:161076$9790_Y - attribute \src "libresoc.v:161078.17-161078.109" - wire $reduce_or$libresoc.v:161078$9792_Y + attribute \src "libresoc.v:164488.17-164488.91" + wire $not$libresoc.v:164488$10175_Y + attribute \src "libresoc.v:164490.18-164490.93" + wire $not$libresoc.v:164490$10177_Y + attribute \src "libresoc.v:164492.18-164492.93" + wire $not$libresoc.v:164492$10179_Y + attribute \src "libresoc.v:164493.17-164493.138" + wire width 8 $not$libresoc.v:164493$10180_Y + attribute \src "libresoc.v:164495.18-164495.93" + wire $not$libresoc.v:164495$10182_Y + attribute \src "libresoc.v:164497.18-164497.93" + wire $not$libresoc.v:164497$10184_Y + attribute \src "libresoc.v:164499.18-164499.93" + wire $not$libresoc.v:164499$10186_Y + attribute \src "libresoc.v:164502.17-164502.91" + wire $not$libresoc.v:164502$10189_Y + attribute \src "libresoc.v:164489.18-164489.116" + wire $reduce_or$libresoc.v:164489$10176_Y + attribute \src "libresoc.v:164491.18-164491.122" + wire $reduce_or$libresoc.v:164491$10178_Y + attribute \src "libresoc.v:164494.18-164494.128" + wire $reduce_or$libresoc.v:164494$10181_Y + attribute \src "libresoc.v:164496.18-164496.134" + wire $reduce_or$libresoc.v:164496$10183_Y + attribute \src "libresoc.v:164498.18-164498.140" + wire $reduce_or$libresoc.v:164498$10185_Y + attribute \src "libresoc.v:164500.18-164500.90" + wire $reduce_or$libresoc.v:164500$10187_Y + attribute \src "libresoc.v:164501.17-164501.103" + wire $reduce_or$libresoc.v:164501$10188_Y + attribute \src "libresoc.v:164503.17-164503.109" + wire $reduce_or$libresoc.v:164503$10190_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -330398,149 +338328,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161063$9777 + cell $not $not$libresoc.v:164488$10175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161063$9777_Y + connect \Y $not$libresoc.v:164488$10175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161065$9779 + cell $not $not$libresoc.v:164490$10177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161065$9779_Y + connect \Y $not$libresoc.v:164490$10177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161067$9781 + cell $not $not$libresoc.v:164492$10179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161067$9781_Y + connect \Y $not$libresoc.v:164492$10179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161068$9782 + cell $not $not$libresoc.v:164493$10180 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161068$9782_Y + connect \Y $not$libresoc.v:164493$10180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161070$9784 + cell $not $not$libresoc.v:164495$10182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161070$9784_Y + connect \Y $not$libresoc.v:164495$10182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161072$9786 + cell $not $not$libresoc.v:164497$10184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161072$9786_Y + connect \Y $not$libresoc.v:164497$10184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161074$9788 + cell $not $not$libresoc.v:164499$10186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161074$9788_Y + connect \Y $not$libresoc.v:164499$10186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161077$9791 + cell $not $not$libresoc.v:164502$10189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161077$9791_Y + connect \Y $not$libresoc.v:164502$10189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161064$9778 + cell $reduce_or $reduce_or$libresoc.v:164489$10176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161064$9778_Y + connect \Y $reduce_or$libresoc.v:164489$10176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161066$9780 + cell $reduce_or $reduce_or$libresoc.v:164491$10178 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161066$9780_Y + connect \Y $reduce_or$libresoc.v:164491$10178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161069$9783 + cell $reduce_or $reduce_or$libresoc.v:164494$10181 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161069$9783_Y + connect \Y $reduce_or$libresoc.v:164494$10181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161071$9785 + cell $reduce_or $reduce_or$libresoc.v:164496$10183 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161071$9785_Y + connect \Y $reduce_or$libresoc.v:164496$10183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161073$9787 + cell $reduce_or $reduce_or$libresoc.v:164498$10185 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161073$9787_Y + connect \Y $reduce_or$libresoc.v:164498$10185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161075$9789 + cell $reduce_or $reduce_or$libresoc.v:164500$10187 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161075$9789_Y + connect \Y $reduce_or$libresoc.v:164500$10187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161076$9790 + cell $reduce_or $reduce_or$libresoc.v:164501$10188 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161076$9790_Y + connect \Y $reduce_or$libresoc.v:164501$10188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161078$9792 + cell $reduce_or $reduce_or$libresoc.v:164503$10190 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161078$9792_Y - end - connect \$7 $not$libresoc.v:161063$9777_Y - connect \$12 $reduce_or$libresoc.v:161064$9778_Y - connect \$11 $not$libresoc.v:161065$9779_Y - connect \$16 $reduce_or$libresoc.v:161066$9780_Y - connect \$15 $not$libresoc.v:161067$9781_Y - connect \$1 $not$libresoc.v:161068$9782_Y - connect \$20 $reduce_or$libresoc.v:161069$9783_Y - connect \$19 $not$libresoc.v:161070$9784_Y - connect \$24 $reduce_or$libresoc.v:161071$9785_Y - connect \$23 $not$libresoc.v:161072$9786_Y - connect \$28 $reduce_or$libresoc.v:161073$9787_Y - connect \$27 $not$libresoc.v:161074$9788_Y - connect \$31 $reduce_or$libresoc.v:161075$9789_Y - connect \$4 $reduce_or$libresoc.v:161076$9790_Y - connect \$3 $not$libresoc.v:161077$9791_Y - connect \$8 $reduce_or$libresoc.v:161078$9792_Y + connect \Y $reduce_or$libresoc.v:164503$10190_Y + end + connect \$7 $not$libresoc.v:164488$10175_Y + connect \$12 $reduce_or$libresoc.v:164489$10176_Y + connect \$11 $not$libresoc.v:164490$10177_Y + connect \$16 $reduce_or$libresoc.v:164491$10178_Y + connect \$15 $not$libresoc.v:164492$10179_Y + connect \$1 $not$libresoc.v:164493$10180_Y + connect \$20 $reduce_or$libresoc.v:164494$10181_Y + connect \$19 $not$libresoc.v:164495$10182_Y + connect \$24 $reduce_or$libresoc.v:164496$10183_Y + connect \$23 $not$libresoc.v:164497$10184_Y + connect \$28 $reduce_or$libresoc.v:164498$10185_Y + connect \$27 $not$libresoc.v:164499$10186_Y + connect \$31 $reduce_or$libresoc.v:164500$10187_Y + connect \$4 $reduce_or$libresoc.v:164501$10188_Y + connect \$3 $not$libresoc.v:164502$10189_Y + connect \$8 $reduce_or$libresoc.v:164503$10190_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -330553,43 +338483,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161094.1-161178.10" +attribute \src "libresoc.v:164519.1-164603.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$136 - attribute \src "libresoc.v:161151.17-161151.91" - wire $not$libresoc.v:161151$9793_Y - attribute \src "libresoc.v:161153.18-161153.93" - wire $not$libresoc.v:161153$9795_Y - attribute \src "libresoc.v:161155.18-161155.93" - wire $not$libresoc.v:161155$9797_Y - attribute \src "libresoc.v:161156.17-161156.138" - wire width 8 $not$libresoc.v:161156$9798_Y - attribute \src "libresoc.v:161158.18-161158.93" - wire $not$libresoc.v:161158$9800_Y - attribute \src "libresoc.v:161160.18-161160.93" - wire $not$libresoc.v:161160$9802_Y - attribute \src "libresoc.v:161162.18-161162.93" - wire $not$libresoc.v:161162$9804_Y - attribute \src "libresoc.v:161165.17-161165.91" - wire $not$libresoc.v:161165$9807_Y - attribute \src "libresoc.v:161152.18-161152.116" - wire $reduce_or$libresoc.v:161152$9794_Y - attribute \src "libresoc.v:161154.18-161154.122" - wire $reduce_or$libresoc.v:161154$9796_Y - attribute \src "libresoc.v:161157.18-161157.128" - wire $reduce_or$libresoc.v:161157$9799_Y - attribute \src "libresoc.v:161159.18-161159.134" - wire $reduce_or$libresoc.v:161159$9801_Y - attribute \src "libresoc.v:161161.18-161161.140" - wire $reduce_or$libresoc.v:161161$9803_Y - attribute \src "libresoc.v:161163.18-161163.90" - wire $reduce_or$libresoc.v:161163$9805_Y - attribute \src "libresoc.v:161164.17-161164.103" - wire $reduce_or$libresoc.v:161164$9806_Y - attribute \src "libresoc.v:161166.17-161166.109" - wire $reduce_or$libresoc.v:161166$9808_Y +module \ppick$139 + attribute \src "libresoc.v:164576.17-164576.91" + wire $not$libresoc.v:164576$10191_Y + attribute \src "libresoc.v:164578.18-164578.93" + wire $not$libresoc.v:164578$10193_Y + attribute \src "libresoc.v:164580.18-164580.93" + wire $not$libresoc.v:164580$10195_Y + attribute \src "libresoc.v:164581.17-164581.138" + wire width 8 $not$libresoc.v:164581$10196_Y + attribute \src "libresoc.v:164583.18-164583.93" + wire $not$libresoc.v:164583$10198_Y + attribute \src "libresoc.v:164585.18-164585.93" + wire $not$libresoc.v:164585$10200_Y + attribute \src "libresoc.v:164587.18-164587.93" + wire $not$libresoc.v:164587$10202_Y + attribute \src "libresoc.v:164590.17-164590.91" + wire $not$libresoc.v:164590$10205_Y + attribute \src "libresoc.v:164577.18-164577.116" + wire $reduce_or$libresoc.v:164577$10192_Y + attribute \src "libresoc.v:164579.18-164579.122" + wire $reduce_or$libresoc.v:164579$10194_Y + attribute \src "libresoc.v:164582.18-164582.128" + wire $reduce_or$libresoc.v:164582$10197_Y + attribute \src "libresoc.v:164584.18-164584.134" + wire $reduce_or$libresoc.v:164584$10199_Y + attribute \src "libresoc.v:164586.18-164586.140" + wire $reduce_or$libresoc.v:164586$10201_Y + attribute \src "libresoc.v:164588.18-164588.90" + wire $reduce_or$libresoc.v:164588$10203_Y + attribute \src "libresoc.v:164589.17-164589.103" + wire $reduce_or$libresoc.v:164589$10204_Y + attribute \src "libresoc.v:164591.17-164591.109" + wire $reduce_or$libresoc.v:164591$10206_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -330647,149 +338577,149 @@ module \ppick$136 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161151$9793 + cell $not $not$libresoc.v:164576$10191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161151$9793_Y + connect \Y $not$libresoc.v:164576$10191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161153$9795 + cell $not $not$libresoc.v:164578$10193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161153$9795_Y + connect \Y $not$libresoc.v:164578$10193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161155$9797 + cell $not $not$libresoc.v:164580$10195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161155$9797_Y + connect \Y $not$libresoc.v:164580$10195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161156$9798 + cell $not $not$libresoc.v:164581$10196 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161156$9798_Y + connect \Y $not$libresoc.v:164581$10196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161158$9800 + cell $not $not$libresoc.v:164583$10198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161158$9800_Y + connect \Y $not$libresoc.v:164583$10198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161160$9802 + cell $not $not$libresoc.v:164585$10200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161160$9802_Y + connect \Y $not$libresoc.v:164585$10200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161162$9804 + cell $not $not$libresoc.v:164587$10202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161162$9804_Y + connect \Y $not$libresoc.v:164587$10202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161165$9807 + cell $not $not$libresoc.v:164590$10205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161165$9807_Y + connect \Y $not$libresoc.v:164590$10205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161152$9794 + cell $reduce_or $reduce_or$libresoc.v:164577$10192 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161152$9794_Y + connect \Y $reduce_or$libresoc.v:164577$10192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161154$9796 + cell $reduce_or $reduce_or$libresoc.v:164579$10194 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161154$9796_Y + connect \Y $reduce_or$libresoc.v:164579$10194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161157$9799 + cell $reduce_or $reduce_or$libresoc.v:164582$10197 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161157$9799_Y + connect \Y $reduce_or$libresoc.v:164582$10197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161159$9801 + cell $reduce_or $reduce_or$libresoc.v:164584$10199 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161159$9801_Y + connect \Y $reduce_or$libresoc.v:164584$10199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161161$9803 + cell $reduce_or $reduce_or$libresoc.v:164586$10201 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161161$9803_Y + connect \Y $reduce_or$libresoc.v:164586$10201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161163$9805 + cell $reduce_or $reduce_or$libresoc.v:164588$10203 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161163$9805_Y + connect \Y $reduce_or$libresoc.v:164588$10203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161164$9806 + cell $reduce_or $reduce_or$libresoc.v:164589$10204 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161164$9806_Y + connect \Y $reduce_or$libresoc.v:164589$10204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161166$9808 + cell $reduce_or $reduce_or$libresoc.v:164591$10206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161166$9808_Y - end - connect \$7 $not$libresoc.v:161151$9793_Y - connect \$12 $reduce_or$libresoc.v:161152$9794_Y - connect \$11 $not$libresoc.v:161153$9795_Y - connect \$16 $reduce_or$libresoc.v:161154$9796_Y - connect \$15 $not$libresoc.v:161155$9797_Y - connect \$1 $not$libresoc.v:161156$9798_Y - connect \$20 $reduce_or$libresoc.v:161157$9799_Y - connect \$19 $not$libresoc.v:161158$9800_Y - connect \$24 $reduce_or$libresoc.v:161159$9801_Y - connect \$23 $not$libresoc.v:161160$9802_Y - connect \$28 $reduce_or$libresoc.v:161161$9803_Y - connect \$27 $not$libresoc.v:161162$9804_Y - connect \$31 $reduce_or$libresoc.v:161163$9805_Y - connect \$4 $reduce_or$libresoc.v:161164$9806_Y - connect \$3 $not$libresoc.v:161165$9807_Y - connect \$8 $reduce_or$libresoc.v:161166$9808_Y + connect \Y $reduce_or$libresoc.v:164591$10206_Y + end + connect \$7 $not$libresoc.v:164576$10191_Y + connect \$12 $reduce_or$libresoc.v:164577$10192_Y + connect \$11 $not$libresoc.v:164578$10193_Y + connect \$16 $reduce_or$libresoc.v:164579$10194_Y + connect \$15 $not$libresoc.v:164580$10195_Y + connect \$1 $not$libresoc.v:164581$10196_Y + connect \$20 $reduce_or$libresoc.v:164582$10197_Y + connect \$19 $not$libresoc.v:164583$10198_Y + connect \$24 $reduce_or$libresoc.v:164584$10199_Y + connect \$23 $not$libresoc.v:164585$10200_Y + connect \$28 $reduce_or$libresoc.v:164586$10201_Y + connect \$27 $not$libresoc.v:164587$10202_Y + connect \$31 $reduce_or$libresoc.v:164588$10203_Y + connect \$4 $reduce_or$libresoc.v:164589$10204_Y + connect \$3 $not$libresoc.v:164590$10205_Y + connect \$8 $reduce_or$libresoc.v:164591$10206_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -330802,43 +338732,43 @@ module \ppick$136 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161182.1-161266.10" +attribute \src "libresoc.v:164607.1-164691.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$141 - attribute \src "libresoc.v:161239.17-161239.91" - wire $not$libresoc.v:161239$9809_Y - attribute \src "libresoc.v:161241.18-161241.93" - wire $not$libresoc.v:161241$9811_Y - attribute \src "libresoc.v:161243.18-161243.93" - wire $not$libresoc.v:161243$9813_Y - attribute \src "libresoc.v:161244.17-161244.138" - wire width 8 $not$libresoc.v:161244$9814_Y - attribute \src "libresoc.v:161246.18-161246.93" - wire $not$libresoc.v:161246$9816_Y - attribute \src "libresoc.v:161248.18-161248.93" - wire $not$libresoc.v:161248$9818_Y - attribute \src "libresoc.v:161250.18-161250.93" - wire $not$libresoc.v:161250$9820_Y - attribute \src "libresoc.v:161253.17-161253.91" - wire $not$libresoc.v:161253$9823_Y - attribute \src "libresoc.v:161240.18-161240.116" - wire $reduce_or$libresoc.v:161240$9810_Y - attribute \src "libresoc.v:161242.18-161242.122" - wire $reduce_or$libresoc.v:161242$9812_Y - attribute \src "libresoc.v:161245.18-161245.128" - wire $reduce_or$libresoc.v:161245$9815_Y - attribute \src "libresoc.v:161247.18-161247.134" - wire $reduce_or$libresoc.v:161247$9817_Y - attribute \src "libresoc.v:161249.18-161249.140" - wire $reduce_or$libresoc.v:161249$9819_Y - attribute \src "libresoc.v:161251.18-161251.90" - wire $reduce_or$libresoc.v:161251$9821_Y - attribute \src "libresoc.v:161252.17-161252.103" - wire $reduce_or$libresoc.v:161252$9822_Y - attribute \src "libresoc.v:161254.17-161254.109" - wire $reduce_or$libresoc.v:161254$9824_Y +module \ppick$144 + attribute \src "libresoc.v:164664.17-164664.91" + wire $not$libresoc.v:164664$10207_Y + attribute \src "libresoc.v:164666.18-164666.93" + wire $not$libresoc.v:164666$10209_Y + attribute \src "libresoc.v:164668.18-164668.93" + wire $not$libresoc.v:164668$10211_Y + attribute \src "libresoc.v:164669.17-164669.138" + wire width 8 $not$libresoc.v:164669$10212_Y + attribute \src "libresoc.v:164671.18-164671.93" + wire $not$libresoc.v:164671$10214_Y + attribute \src "libresoc.v:164673.18-164673.93" + wire $not$libresoc.v:164673$10216_Y + attribute \src "libresoc.v:164675.18-164675.93" + wire $not$libresoc.v:164675$10218_Y + attribute \src "libresoc.v:164678.17-164678.91" + wire $not$libresoc.v:164678$10221_Y + attribute \src "libresoc.v:164665.18-164665.116" + wire $reduce_or$libresoc.v:164665$10208_Y + attribute \src "libresoc.v:164667.18-164667.122" + wire $reduce_or$libresoc.v:164667$10210_Y + attribute \src "libresoc.v:164670.18-164670.128" + wire $reduce_or$libresoc.v:164670$10213_Y + attribute \src "libresoc.v:164672.18-164672.134" + wire $reduce_or$libresoc.v:164672$10215_Y + attribute \src "libresoc.v:164674.18-164674.140" + wire $reduce_or$libresoc.v:164674$10217_Y + attribute \src "libresoc.v:164676.18-164676.90" + wire $reduce_or$libresoc.v:164676$10219_Y + attribute \src "libresoc.v:164677.17-164677.103" + wire $reduce_or$libresoc.v:164677$10220_Y + attribute \src "libresoc.v:164679.17-164679.109" + wire $reduce_or$libresoc.v:164679$10222_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -330896,149 +338826,149 @@ module \ppick$141 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161239$9809 + cell $not $not$libresoc.v:164664$10207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161239$9809_Y + connect \Y $not$libresoc.v:164664$10207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161241$9811 + cell $not $not$libresoc.v:164666$10209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161241$9811_Y + connect \Y $not$libresoc.v:164666$10209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161243$9813 + cell $not $not$libresoc.v:164668$10211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161243$9813_Y + connect \Y $not$libresoc.v:164668$10211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161244$9814 + cell $not $not$libresoc.v:164669$10212 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161244$9814_Y + connect \Y $not$libresoc.v:164669$10212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161246$9816 + cell $not $not$libresoc.v:164671$10214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161246$9816_Y + connect \Y $not$libresoc.v:164671$10214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161248$9818 + cell $not $not$libresoc.v:164673$10216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161248$9818_Y + connect \Y $not$libresoc.v:164673$10216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161250$9820 + cell $not $not$libresoc.v:164675$10218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161250$9820_Y + connect \Y $not$libresoc.v:164675$10218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161253$9823 + cell $not $not$libresoc.v:164678$10221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161253$9823_Y + connect \Y $not$libresoc.v:164678$10221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161240$9810 + cell $reduce_or $reduce_or$libresoc.v:164665$10208 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161240$9810_Y + connect \Y $reduce_or$libresoc.v:164665$10208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161242$9812 + cell $reduce_or $reduce_or$libresoc.v:164667$10210 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161242$9812_Y + connect \Y $reduce_or$libresoc.v:164667$10210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161245$9815 + cell $reduce_or $reduce_or$libresoc.v:164670$10213 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161245$9815_Y + connect \Y $reduce_or$libresoc.v:164670$10213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161247$9817 + cell $reduce_or $reduce_or$libresoc.v:164672$10215 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161247$9817_Y + connect \Y $reduce_or$libresoc.v:164672$10215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161249$9819 + cell $reduce_or $reduce_or$libresoc.v:164674$10217 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161249$9819_Y + connect \Y $reduce_or$libresoc.v:164674$10217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161251$9821 + cell $reduce_or $reduce_or$libresoc.v:164676$10219 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161251$9821_Y + connect \Y $reduce_or$libresoc.v:164676$10219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161252$9822 + cell $reduce_or $reduce_or$libresoc.v:164677$10220 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161252$9822_Y + connect \Y $reduce_or$libresoc.v:164677$10220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161254$9824 + cell $reduce_or $reduce_or$libresoc.v:164679$10222 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161254$9824_Y - end - connect \$7 $not$libresoc.v:161239$9809_Y - connect \$12 $reduce_or$libresoc.v:161240$9810_Y - connect \$11 $not$libresoc.v:161241$9811_Y - connect \$16 $reduce_or$libresoc.v:161242$9812_Y - connect \$15 $not$libresoc.v:161243$9813_Y - connect \$1 $not$libresoc.v:161244$9814_Y - connect \$20 $reduce_or$libresoc.v:161245$9815_Y - connect \$19 $not$libresoc.v:161246$9816_Y - connect \$24 $reduce_or$libresoc.v:161247$9817_Y - connect \$23 $not$libresoc.v:161248$9818_Y - connect \$28 $reduce_or$libresoc.v:161249$9819_Y - connect \$27 $not$libresoc.v:161250$9820_Y - connect \$31 $reduce_or$libresoc.v:161251$9821_Y - connect \$4 $reduce_or$libresoc.v:161252$9822_Y - connect \$3 $not$libresoc.v:161253$9823_Y - connect \$8 $reduce_or$libresoc.v:161254$9824_Y + connect \Y $reduce_or$libresoc.v:164679$10222_Y + end + connect \$7 $not$libresoc.v:164664$10207_Y + connect \$12 $reduce_or$libresoc.v:164665$10208_Y + connect \$11 $not$libresoc.v:164666$10209_Y + connect \$16 $reduce_or$libresoc.v:164667$10210_Y + connect \$15 $not$libresoc.v:164668$10211_Y + connect \$1 $not$libresoc.v:164669$10212_Y + connect \$20 $reduce_or$libresoc.v:164670$10213_Y + connect \$19 $not$libresoc.v:164671$10214_Y + connect \$24 $reduce_or$libresoc.v:164672$10215_Y + connect \$23 $not$libresoc.v:164673$10216_Y + connect \$28 $reduce_or$libresoc.v:164674$10217_Y + connect \$27 $not$libresoc.v:164675$10218_Y + connect \$31 $reduce_or$libresoc.v:164676$10219_Y + connect \$4 $reduce_or$libresoc.v:164677$10220_Y + connect \$3 $not$libresoc.v:164678$10221_Y + connect \$8 $reduce_or$libresoc.v:164679$10222_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -331051,43 +338981,43 @@ module \ppick$141 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161270.1-161354.10" +attribute \src "libresoc.v:164695.1-164779.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$143 - attribute \src "libresoc.v:161327.17-161327.91" - wire $not$libresoc.v:161327$9825_Y - attribute \src "libresoc.v:161329.18-161329.93" - wire $not$libresoc.v:161329$9827_Y - attribute \src "libresoc.v:161331.18-161331.93" - wire $not$libresoc.v:161331$9829_Y - attribute \src "libresoc.v:161332.17-161332.138" - wire width 8 $not$libresoc.v:161332$9830_Y - attribute \src "libresoc.v:161334.18-161334.93" - wire $not$libresoc.v:161334$9832_Y - attribute \src "libresoc.v:161336.18-161336.93" - wire $not$libresoc.v:161336$9834_Y - attribute \src "libresoc.v:161338.18-161338.93" - wire $not$libresoc.v:161338$9836_Y - attribute \src "libresoc.v:161341.17-161341.91" - wire $not$libresoc.v:161341$9839_Y - attribute \src "libresoc.v:161328.18-161328.116" - wire $reduce_or$libresoc.v:161328$9826_Y - attribute \src "libresoc.v:161330.18-161330.122" - wire $reduce_or$libresoc.v:161330$9828_Y - attribute \src "libresoc.v:161333.18-161333.128" - wire $reduce_or$libresoc.v:161333$9831_Y - attribute \src "libresoc.v:161335.18-161335.134" - wire $reduce_or$libresoc.v:161335$9833_Y - attribute \src "libresoc.v:161337.18-161337.140" - wire $reduce_or$libresoc.v:161337$9835_Y - attribute \src "libresoc.v:161339.18-161339.90" - wire $reduce_or$libresoc.v:161339$9837_Y - attribute \src "libresoc.v:161340.17-161340.103" - wire $reduce_or$libresoc.v:161340$9838_Y - attribute \src "libresoc.v:161342.17-161342.109" - wire $reduce_or$libresoc.v:161342$9840_Y +module \ppick$146 + attribute \src "libresoc.v:164752.17-164752.91" + wire $not$libresoc.v:164752$10223_Y + attribute \src "libresoc.v:164754.18-164754.93" + wire $not$libresoc.v:164754$10225_Y + attribute \src "libresoc.v:164756.18-164756.93" + wire $not$libresoc.v:164756$10227_Y + attribute \src "libresoc.v:164757.17-164757.138" + wire width 8 $not$libresoc.v:164757$10228_Y + attribute \src "libresoc.v:164759.18-164759.93" + wire $not$libresoc.v:164759$10230_Y + attribute \src "libresoc.v:164761.18-164761.93" + wire $not$libresoc.v:164761$10232_Y + attribute \src "libresoc.v:164763.18-164763.93" + wire $not$libresoc.v:164763$10234_Y + attribute \src "libresoc.v:164766.17-164766.91" + wire $not$libresoc.v:164766$10237_Y + attribute \src "libresoc.v:164753.18-164753.116" + wire $reduce_or$libresoc.v:164753$10224_Y + attribute \src "libresoc.v:164755.18-164755.122" + wire $reduce_or$libresoc.v:164755$10226_Y + attribute \src "libresoc.v:164758.18-164758.128" + wire $reduce_or$libresoc.v:164758$10229_Y + attribute \src "libresoc.v:164760.18-164760.134" + wire $reduce_or$libresoc.v:164760$10231_Y + attribute \src "libresoc.v:164762.18-164762.140" + wire $reduce_or$libresoc.v:164762$10233_Y + attribute \src "libresoc.v:164764.18-164764.90" + wire $reduce_or$libresoc.v:164764$10235_Y + attribute \src "libresoc.v:164765.17-164765.103" + wire $reduce_or$libresoc.v:164765$10236_Y + attribute \src "libresoc.v:164767.17-164767.109" + wire $reduce_or$libresoc.v:164767$10238_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -331145,149 +339075,149 @@ module \ppick$143 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161327$9825 + cell $not $not$libresoc.v:164752$10223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161327$9825_Y + connect \Y $not$libresoc.v:164752$10223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161329$9827 + cell $not $not$libresoc.v:164754$10225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161329$9827_Y + connect \Y $not$libresoc.v:164754$10225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161331$9829 + cell $not $not$libresoc.v:164756$10227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161331$9829_Y + connect \Y $not$libresoc.v:164756$10227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161332$9830 + cell $not $not$libresoc.v:164757$10228 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161332$9830_Y + connect \Y $not$libresoc.v:164757$10228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161334$9832 + cell $not $not$libresoc.v:164759$10230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161334$9832_Y + connect \Y $not$libresoc.v:164759$10230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161336$9834 + cell $not $not$libresoc.v:164761$10232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161336$9834_Y + connect \Y $not$libresoc.v:164761$10232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161338$9836 + cell $not $not$libresoc.v:164763$10234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161338$9836_Y + connect \Y $not$libresoc.v:164763$10234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161341$9839 + cell $not $not$libresoc.v:164766$10237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161341$9839_Y + connect \Y $not$libresoc.v:164766$10237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161328$9826 + cell $reduce_or $reduce_or$libresoc.v:164753$10224 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161328$9826_Y + connect \Y $reduce_or$libresoc.v:164753$10224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161330$9828 + cell $reduce_or $reduce_or$libresoc.v:164755$10226 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161330$9828_Y + connect \Y $reduce_or$libresoc.v:164755$10226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161333$9831 + cell $reduce_or $reduce_or$libresoc.v:164758$10229 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161333$9831_Y + connect \Y $reduce_or$libresoc.v:164758$10229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161335$9833 + cell $reduce_or $reduce_or$libresoc.v:164760$10231 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161335$9833_Y + connect \Y $reduce_or$libresoc.v:164760$10231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161337$9835 + cell $reduce_or $reduce_or$libresoc.v:164762$10233 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161337$9835_Y + connect \Y $reduce_or$libresoc.v:164762$10233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161339$9837 + cell $reduce_or $reduce_or$libresoc.v:164764$10235 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161339$9837_Y + connect \Y $reduce_or$libresoc.v:164764$10235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161340$9838 + cell $reduce_or $reduce_or$libresoc.v:164765$10236 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161340$9838_Y + connect \Y $reduce_or$libresoc.v:164765$10236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161342$9840 + cell $reduce_or $reduce_or$libresoc.v:164767$10238 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161342$9840_Y - end - connect \$7 $not$libresoc.v:161327$9825_Y - connect \$12 $reduce_or$libresoc.v:161328$9826_Y - connect \$11 $not$libresoc.v:161329$9827_Y - connect \$16 $reduce_or$libresoc.v:161330$9828_Y - connect \$15 $not$libresoc.v:161331$9829_Y - connect \$1 $not$libresoc.v:161332$9830_Y - connect \$20 $reduce_or$libresoc.v:161333$9831_Y - connect \$19 $not$libresoc.v:161334$9832_Y - connect \$24 $reduce_or$libresoc.v:161335$9833_Y - connect \$23 $not$libresoc.v:161336$9834_Y - connect \$28 $reduce_or$libresoc.v:161337$9835_Y - connect \$27 $not$libresoc.v:161338$9836_Y - connect \$31 $reduce_or$libresoc.v:161339$9837_Y - connect \$4 $reduce_or$libresoc.v:161340$9838_Y - connect \$3 $not$libresoc.v:161341$9839_Y - connect \$8 $reduce_or$libresoc.v:161342$9840_Y + connect \Y $reduce_or$libresoc.v:164767$10238_Y + end + connect \$7 $not$libresoc.v:164752$10223_Y + connect \$12 $reduce_or$libresoc.v:164753$10224_Y + connect \$11 $not$libresoc.v:164754$10225_Y + connect \$16 $reduce_or$libresoc.v:164755$10226_Y + connect \$15 $not$libresoc.v:164756$10227_Y + connect \$1 $not$libresoc.v:164757$10228_Y + connect \$20 $reduce_or$libresoc.v:164758$10229_Y + connect \$19 $not$libresoc.v:164759$10230_Y + connect \$24 $reduce_or$libresoc.v:164760$10231_Y + connect \$23 $not$libresoc.v:164761$10232_Y + connect \$28 $reduce_or$libresoc.v:164762$10233_Y + connect \$27 $not$libresoc.v:164763$10234_Y + connect \$31 $reduce_or$libresoc.v:164764$10235_Y + connect \$4 $reduce_or$libresoc.v:164765$10236_Y + connect \$3 $not$libresoc.v:164766$10237_Y + connect \$8 $reduce_or$libresoc.v:164767$10238_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -331300,43 +339230,43 @@ module \ppick$143 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161358.1-161442.10" +attribute \src "libresoc.v:164783.1-164867.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$148 - attribute \src "libresoc.v:161415.17-161415.91" - wire $not$libresoc.v:161415$9841_Y - attribute \src "libresoc.v:161417.18-161417.93" - wire $not$libresoc.v:161417$9843_Y - attribute \src "libresoc.v:161419.18-161419.93" - wire $not$libresoc.v:161419$9845_Y - attribute \src "libresoc.v:161420.17-161420.138" - wire width 8 $not$libresoc.v:161420$9846_Y - attribute \src "libresoc.v:161422.18-161422.93" - wire $not$libresoc.v:161422$9848_Y - attribute \src "libresoc.v:161424.18-161424.93" - wire $not$libresoc.v:161424$9850_Y - attribute \src "libresoc.v:161426.18-161426.93" - wire $not$libresoc.v:161426$9852_Y - attribute \src "libresoc.v:161429.17-161429.91" - wire $not$libresoc.v:161429$9855_Y - attribute \src "libresoc.v:161416.18-161416.116" - wire $reduce_or$libresoc.v:161416$9842_Y - attribute \src "libresoc.v:161418.18-161418.122" - wire $reduce_or$libresoc.v:161418$9844_Y - attribute \src "libresoc.v:161421.18-161421.128" - wire $reduce_or$libresoc.v:161421$9847_Y - attribute \src "libresoc.v:161423.18-161423.134" - wire $reduce_or$libresoc.v:161423$9849_Y - attribute \src "libresoc.v:161425.18-161425.140" - wire $reduce_or$libresoc.v:161425$9851_Y - attribute \src "libresoc.v:161427.18-161427.90" - wire $reduce_or$libresoc.v:161427$9853_Y - attribute \src "libresoc.v:161428.17-161428.103" - wire $reduce_or$libresoc.v:161428$9854_Y - attribute \src "libresoc.v:161430.17-161430.109" - wire $reduce_or$libresoc.v:161430$9856_Y +module \ppick$151 + attribute \src "libresoc.v:164840.17-164840.91" + wire $not$libresoc.v:164840$10239_Y + attribute \src "libresoc.v:164842.18-164842.93" + wire $not$libresoc.v:164842$10241_Y + attribute \src "libresoc.v:164844.18-164844.93" + wire $not$libresoc.v:164844$10243_Y + attribute \src "libresoc.v:164845.17-164845.138" + wire width 8 $not$libresoc.v:164845$10244_Y + attribute \src "libresoc.v:164847.18-164847.93" + wire $not$libresoc.v:164847$10246_Y + attribute \src "libresoc.v:164849.18-164849.93" + wire $not$libresoc.v:164849$10248_Y + attribute \src "libresoc.v:164851.18-164851.93" + wire $not$libresoc.v:164851$10250_Y + attribute \src "libresoc.v:164854.17-164854.91" + wire $not$libresoc.v:164854$10253_Y + attribute \src "libresoc.v:164841.18-164841.116" + wire $reduce_or$libresoc.v:164841$10240_Y + attribute \src "libresoc.v:164843.18-164843.122" + wire $reduce_or$libresoc.v:164843$10242_Y + attribute \src "libresoc.v:164846.18-164846.128" + wire $reduce_or$libresoc.v:164846$10245_Y + attribute \src "libresoc.v:164848.18-164848.134" + wire $reduce_or$libresoc.v:164848$10247_Y + attribute \src "libresoc.v:164850.18-164850.140" + wire $reduce_or$libresoc.v:164850$10249_Y + attribute \src "libresoc.v:164852.18-164852.90" + wire $reduce_or$libresoc.v:164852$10251_Y + attribute \src "libresoc.v:164853.17-164853.103" + wire $reduce_or$libresoc.v:164853$10252_Y + attribute \src "libresoc.v:164855.17-164855.109" + wire $reduce_or$libresoc.v:164855$10254_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -331394,149 +339324,149 @@ module \ppick$148 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161415$9841 + cell $not $not$libresoc.v:164840$10239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161415$9841_Y + connect \Y $not$libresoc.v:164840$10239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161417$9843 + cell $not $not$libresoc.v:164842$10241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161417$9843_Y + connect \Y $not$libresoc.v:164842$10241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161419$9845 + cell $not $not$libresoc.v:164844$10243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161419$9845_Y + connect \Y $not$libresoc.v:164844$10243_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161420$9846 + cell $not $not$libresoc.v:164845$10244 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161420$9846_Y + connect \Y $not$libresoc.v:164845$10244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161422$9848 + cell $not $not$libresoc.v:164847$10246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161422$9848_Y + connect \Y $not$libresoc.v:164847$10246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161424$9850 + cell $not $not$libresoc.v:164849$10248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161424$9850_Y + connect \Y $not$libresoc.v:164849$10248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161426$9852 + cell $not $not$libresoc.v:164851$10250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161426$9852_Y + connect \Y $not$libresoc.v:164851$10250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161429$9855 + cell $not $not$libresoc.v:164854$10253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161429$9855_Y + connect \Y $not$libresoc.v:164854$10253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161416$9842 + cell $reduce_or $reduce_or$libresoc.v:164841$10240 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161416$9842_Y + connect \Y $reduce_or$libresoc.v:164841$10240_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161418$9844 + cell $reduce_or $reduce_or$libresoc.v:164843$10242 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161418$9844_Y + connect \Y $reduce_or$libresoc.v:164843$10242_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161421$9847 + cell $reduce_or $reduce_or$libresoc.v:164846$10245 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161421$9847_Y + connect \Y $reduce_or$libresoc.v:164846$10245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161423$9849 + cell $reduce_or $reduce_or$libresoc.v:164848$10247 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161423$9849_Y + connect \Y $reduce_or$libresoc.v:164848$10247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161425$9851 + cell $reduce_or $reduce_or$libresoc.v:164850$10249 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161425$9851_Y + connect \Y $reduce_or$libresoc.v:164850$10249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161427$9853 + cell $reduce_or $reduce_or$libresoc.v:164852$10251 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161427$9853_Y + connect \Y $reduce_or$libresoc.v:164852$10251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161428$9854 + cell $reduce_or $reduce_or$libresoc.v:164853$10252 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161428$9854_Y + connect \Y $reduce_or$libresoc.v:164853$10252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161430$9856 + cell $reduce_or $reduce_or$libresoc.v:164855$10254 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161430$9856_Y - end - connect \$7 $not$libresoc.v:161415$9841_Y - connect \$12 $reduce_or$libresoc.v:161416$9842_Y - connect \$11 $not$libresoc.v:161417$9843_Y - connect \$16 $reduce_or$libresoc.v:161418$9844_Y - connect \$15 $not$libresoc.v:161419$9845_Y - connect \$1 $not$libresoc.v:161420$9846_Y - connect \$20 $reduce_or$libresoc.v:161421$9847_Y - connect \$19 $not$libresoc.v:161422$9848_Y - connect \$24 $reduce_or$libresoc.v:161423$9849_Y - connect \$23 $not$libresoc.v:161424$9850_Y - connect \$28 $reduce_or$libresoc.v:161425$9851_Y - connect \$27 $not$libresoc.v:161426$9852_Y - connect \$31 $reduce_or$libresoc.v:161427$9853_Y - connect \$4 $reduce_or$libresoc.v:161428$9854_Y - connect \$3 $not$libresoc.v:161429$9855_Y - connect \$8 $reduce_or$libresoc.v:161430$9856_Y + connect \Y $reduce_or$libresoc.v:164855$10254_Y + end + connect \$7 $not$libresoc.v:164840$10239_Y + connect \$12 $reduce_or$libresoc.v:164841$10240_Y + connect \$11 $not$libresoc.v:164842$10241_Y + connect \$16 $reduce_or$libresoc.v:164843$10242_Y + connect \$15 $not$libresoc.v:164844$10243_Y + connect \$1 $not$libresoc.v:164845$10244_Y + connect \$20 $reduce_or$libresoc.v:164846$10245_Y + connect \$19 $not$libresoc.v:164847$10246_Y + connect \$24 $reduce_or$libresoc.v:164848$10247_Y + connect \$23 $not$libresoc.v:164849$10248_Y + connect \$28 $reduce_or$libresoc.v:164850$10249_Y + connect \$27 $not$libresoc.v:164851$10250_Y + connect \$31 $reduce_or$libresoc.v:164852$10251_Y + connect \$4 $reduce_or$libresoc.v:164853$10252_Y + connect \$3 $not$libresoc.v:164854$10253_Y + connect \$8 $reduce_or$libresoc.v:164855$10254_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -331549,43 +339479,43 @@ module \ppick$148 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161446.1-161530.10" +attribute \src "libresoc.v:164871.1-164955.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$150 - attribute \src "libresoc.v:161503.17-161503.91" - wire $not$libresoc.v:161503$9857_Y - attribute \src "libresoc.v:161505.18-161505.93" - wire $not$libresoc.v:161505$9859_Y - attribute \src "libresoc.v:161507.18-161507.93" - wire $not$libresoc.v:161507$9861_Y - attribute \src "libresoc.v:161508.17-161508.138" - wire width 8 $not$libresoc.v:161508$9862_Y - attribute \src "libresoc.v:161510.18-161510.93" - wire $not$libresoc.v:161510$9864_Y - attribute \src "libresoc.v:161512.18-161512.93" - wire $not$libresoc.v:161512$9866_Y - attribute \src "libresoc.v:161514.18-161514.93" - wire $not$libresoc.v:161514$9868_Y - attribute \src "libresoc.v:161517.17-161517.91" - wire $not$libresoc.v:161517$9871_Y - attribute \src "libresoc.v:161504.18-161504.116" - wire $reduce_or$libresoc.v:161504$9858_Y - attribute \src "libresoc.v:161506.18-161506.122" - wire $reduce_or$libresoc.v:161506$9860_Y - attribute \src "libresoc.v:161509.18-161509.128" - wire $reduce_or$libresoc.v:161509$9863_Y - attribute \src "libresoc.v:161511.18-161511.134" - wire $reduce_or$libresoc.v:161511$9865_Y - attribute \src "libresoc.v:161513.18-161513.140" - wire $reduce_or$libresoc.v:161513$9867_Y - attribute \src "libresoc.v:161515.18-161515.90" - wire $reduce_or$libresoc.v:161515$9869_Y - attribute \src "libresoc.v:161516.17-161516.103" - wire $reduce_or$libresoc.v:161516$9870_Y - attribute \src "libresoc.v:161518.17-161518.109" - wire $reduce_or$libresoc.v:161518$9872_Y +module \ppick$153 + attribute \src "libresoc.v:164928.17-164928.91" + wire $not$libresoc.v:164928$10255_Y + attribute \src "libresoc.v:164930.18-164930.93" + wire $not$libresoc.v:164930$10257_Y + attribute \src "libresoc.v:164932.18-164932.93" + wire $not$libresoc.v:164932$10259_Y + attribute \src "libresoc.v:164933.17-164933.138" + wire width 8 $not$libresoc.v:164933$10260_Y + attribute \src "libresoc.v:164935.18-164935.93" + wire $not$libresoc.v:164935$10262_Y + attribute \src "libresoc.v:164937.18-164937.93" + wire $not$libresoc.v:164937$10264_Y + attribute \src "libresoc.v:164939.18-164939.93" + wire $not$libresoc.v:164939$10266_Y + attribute \src "libresoc.v:164942.17-164942.91" + wire $not$libresoc.v:164942$10269_Y + attribute \src "libresoc.v:164929.18-164929.116" + wire $reduce_or$libresoc.v:164929$10256_Y + attribute \src "libresoc.v:164931.18-164931.122" + wire $reduce_or$libresoc.v:164931$10258_Y + attribute \src "libresoc.v:164934.18-164934.128" + wire $reduce_or$libresoc.v:164934$10261_Y + attribute \src "libresoc.v:164936.18-164936.134" + wire $reduce_or$libresoc.v:164936$10263_Y + attribute \src "libresoc.v:164938.18-164938.140" + wire $reduce_or$libresoc.v:164938$10265_Y + attribute \src "libresoc.v:164940.18-164940.90" + wire $reduce_or$libresoc.v:164940$10267_Y + attribute \src "libresoc.v:164941.17-164941.103" + wire $reduce_or$libresoc.v:164941$10268_Y + attribute \src "libresoc.v:164943.17-164943.109" + wire $reduce_or$libresoc.v:164943$10270_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -331643,149 +339573,149 @@ module \ppick$150 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161503$9857 + cell $not $not$libresoc.v:164928$10255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161503$9857_Y + connect \Y $not$libresoc.v:164928$10255_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161505$9859 + cell $not $not$libresoc.v:164930$10257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161505$9859_Y + connect \Y $not$libresoc.v:164930$10257_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161507$9861 + cell $not $not$libresoc.v:164932$10259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161507$9861_Y + connect \Y $not$libresoc.v:164932$10259_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161508$9862 + cell $not $not$libresoc.v:164933$10260 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161508$9862_Y + connect \Y $not$libresoc.v:164933$10260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161510$9864 + cell $not $not$libresoc.v:164935$10262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161510$9864_Y + connect \Y $not$libresoc.v:164935$10262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161512$9866 + cell $not $not$libresoc.v:164937$10264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161512$9866_Y + connect \Y $not$libresoc.v:164937$10264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161514$9868 + cell $not $not$libresoc.v:164939$10266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161514$9868_Y + connect \Y $not$libresoc.v:164939$10266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161517$9871 + cell $not $not$libresoc.v:164942$10269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161517$9871_Y + connect \Y $not$libresoc.v:164942$10269_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161504$9858 + cell $reduce_or $reduce_or$libresoc.v:164929$10256 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161504$9858_Y + connect \Y $reduce_or$libresoc.v:164929$10256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161506$9860 + cell $reduce_or $reduce_or$libresoc.v:164931$10258 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161506$9860_Y + connect \Y $reduce_or$libresoc.v:164931$10258_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161509$9863 + cell $reduce_or $reduce_or$libresoc.v:164934$10261 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161509$9863_Y + connect \Y $reduce_or$libresoc.v:164934$10261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161511$9865 + cell $reduce_or $reduce_or$libresoc.v:164936$10263 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161511$9865_Y + connect \Y $reduce_or$libresoc.v:164936$10263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161513$9867 + cell $reduce_or $reduce_or$libresoc.v:164938$10265 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161513$9867_Y + connect \Y $reduce_or$libresoc.v:164938$10265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161515$9869 + cell $reduce_or $reduce_or$libresoc.v:164940$10267 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161515$9869_Y + connect \Y $reduce_or$libresoc.v:164940$10267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161516$9870 + cell $reduce_or $reduce_or$libresoc.v:164941$10268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161516$9870_Y + connect \Y $reduce_or$libresoc.v:164941$10268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161518$9872 + cell $reduce_or $reduce_or$libresoc.v:164943$10270 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161518$9872_Y - end - connect \$7 $not$libresoc.v:161503$9857_Y - connect \$12 $reduce_or$libresoc.v:161504$9858_Y - connect \$11 $not$libresoc.v:161505$9859_Y - connect \$16 $reduce_or$libresoc.v:161506$9860_Y - connect \$15 $not$libresoc.v:161507$9861_Y - connect \$1 $not$libresoc.v:161508$9862_Y - connect \$20 $reduce_or$libresoc.v:161509$9863_Y - connect \$19 $not$libresoc.v:161510$9864_Y - connect \$24 $reduce_or$libresoc.v:161511$9865_Y - connect \$23 $not$libresoc.v:161512$9866_Y - connect \$28 $reduce_or$libresoc.v:161513$9867_Y - connect \$27 $not$libresoc.v:161514$9868_Y - connect \$31 $reduce_or$libresoc.v:161515$9869_Y - connect \$4 $reduce_or$libresoc.v:161516$9870_Y - connect \$3 $not$libresoc.v:161517$9871_Y - connect \$8 $reduce_or$libresoc.v:161518$9872_Y + connect \Y $reduce_or$libresoc.v:164943$10270_Y + end + connect \$7 $not$libresoc.v:164928$10255_Y + connect \$12 $reduce_or$libresoc.v:164929$10256_Y + connect \$11 $not$libresoc.v:164930$10257_Y + connect \$16 $reduce_or$libresoc.v:164931$10258_Y + connect \$15 $not$libresoc.v:164932$10259_Y + connect \$1 $not$libresoc.v:164933$10260_Y + connect \$20 $reduce_or$libresoc.v:164934$10261_Y + connect \$19 $not$libresoc.v:164935$10262_Y + connect \$24 $reduce_or$libresoc.v:164936$10263_Y + connect \$23 $not$libresoc.v:164937$10264_Y + connect \$28 $reduce_or$libresoc.v:164938$10265_Y + connect \$27 $not$libresoc.v:164939$10266_Y + connect \$31 $reduce_or$libresoc.v:164940$10267_Y + connect \$4 $reduce_or$libresoc.v:164941$10268_Y + connect \$3 $not$libresoc.v:164942$10269_Y + connect \$8 $reduce_or$libresoc.v:164943$10270_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -331798,43 +339728,43 @@ module \ppick$150 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161534.1-161618.10" +attribute \src "libresoc.v:164959.1-165043.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$156 - attribute \src "libresoc.v:161591.17-161591.91" - wire $not$libresoc.v:161591$9873_Y - attribute \src "libresoc.v:161593.18-161593.93" - wire $not$libresoc.v:161593$9875_Y - attribute \src "libresoc.v:161595.18-161595.93" - wire $not$libresoc.v:161595$9877_Y - attribute \src "libresoc.v:161596.17-161596.138" - wire width 8 $not$libresoc.v:161596$9878_Y - attribute \src "libresoc.v:161598.18-161598.93" - wire $not$libresoc.v:161598$9880_Y - attribute \src "libresoc.v:161600.18-161600.93" - wire $not$libresoc.v:161600$9882_Y - attribute \src "libresoc.v:161602.18-161602.93" - wire $not$libresoc.v:161602$9884_Y - attribute \src "libresoc.v:161605.17-161605.91" - wire $not$libresoc.v:161605$9887_Y - attribute \src "libresoc.v:161592.18-161592.116" - wire $reduce_or$libresoc.v:161592$9874_Y - attribute \src "libresoc.v:161594.18-161594.122" - wire $reduce_or$libresoc.v:161594$9876_Y - attribute \src "libresoc.v:161597.18-161597.128" - wire $reduce_or$libresoc.v:161597$9879_Y - attribute \src "libresoc.v:161599.18-161599.134" - wire $reduce_or$libresoc.v:161599$9881_Y - attribute \src "libresoc.v:161601.18-161601.140" - wire $reduce_or$libresoc.v:161601$9883_Y - attribute \src "libresoc.v:161603.18-161603.90" - wire $reduce_or$libresoc.v:161603$9885_Y - attribute \src "libresoc.v:161604.17-161604.103" - wire $reduce_or$libresoc.v:161604$9886_Y - attribute \src "libresoc.v:161606.17-161606.109" - wire $reduce_or$libresoc.v:161606$9888_Y +module \ppick$159 + attribute \src "libresoc.v:165016.17-165016.91" + wire $not$libresoc.v:165016$10271_Y + attribute \src "libresoc.v:165018.18-165018.93" + wire $not$libresoc.v:165018$10273_Y + attribute \src "libresoc.v:165020.18-165020.93" + wire $not$libresoc.v:165020$10275_Y + attribute \src "libresoc.v:165021.17-165021.138" + wire width 8 $not$libresoc.v:165021$10276_Y + attribute \src "libresoc.v:165023.18-165023.93" + wire $not$libresoc.v:165023$10278_Y + attribute \src "libresoc.v:165025.18-165025.93" + wire $not$libresoc.v:165025$10280_Y + attribute \src "libresoc.v:165027.18-165027.93" + wire $not$libresoc.v:165027$10282_Y + attribute \src "libresoc.v:165030.17-165030.91" + wire $not$libresoc.v:165030$10285_Y + attribute \src "libresoc.v:165017.18-165017.116" + wire $reduce_or$libresoc.v:165017$10272_Y + attribute \src "libresoc.v:165019.18-165019.122" + wire $reduce_or$libresoc.v:165019$10274_Y + attribute \src "libresoc.v:165022.18-165022.128" + wire $reduce_or$libresoc.v:165022$10277_Y + attribute \src "libresoc.v:165024.18-165024.134" + wire $reduce_or$libresoc.v:165024$10279_Y + attribute \src "libresoc.v:165026.18-165026.140" + wire $reduce_or$libresoc.v:165026$10281_Y + attribute \src "libresoc.v:165028.18-165028.90" + wire $reduce_or$libresoc.v:165028$10283_Y + attribute \src "libresoc.v:165029.17-165029.103" + wire $reduce_or$libresoc.v:165029$10284_Y + attribute \src "libresoc.v:165031.17-165031.109" + wire $reduce_or$libresoc.v:165031$10286_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -331892,149 +339822,149 @@ module \ppick$156 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161591$9873 + cell $not $not$libresoc.v:165016$10271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161591$9873_Y + connect \Y $not$libresoc.v:165016$10271_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161593$9875 + cell $not $not$libresoc.v:165018$10273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161593$9875_Y + connect \Y $not$libresoc.v:165018$10273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161595$9877 + cell $not $not$libresoc.v:165020$10275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161595$9877_Y + connect \Y $not$libresoc.v:165020$10275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161596$9878 + cell $not $not$libresoc.v:165021$10276 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161596$9878_Y + connect \Y $not$libresoc.v:165021$10276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161598$9880 + cell $not $not$libresoc.v:165023$10278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161598$9880_Y + connect \Y $not$libresoc.v:165023$10278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161600$9882 + cell $not $not$libresoc.v:165025$10280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161600$9882_Y + connect \Y $not$libresoc.v:165025$10280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161602$9884 + cell $not $not$libresoc.v:165027$10282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161602$9884_Y + connect \Y $not$libresoc.v:165027$10282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161605$9887 + cell $not $not$libresoc.v:165030$10285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161605$9887_Y + connect \Y $not$libresoc.v:165030$10285_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161592$9874 + cell $reduce_or $reduce_or$libresoc.v:165017$10272 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161592$9874_Y + connect \Y $reduce_or$libresoc.v:165017$10272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161594$9876 + cell $reduce_or $reduce_or$libresoc.v:165019$10274 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161594$9876_Y + connect \Y $reduce_or$libresoc.v:165019$10274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161597$9879 + cell $reduce_or $reduce_or$libresoc.v:165022$10277 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161597$9879_Y + connect \Y $reduce_or$libresoc.v:165022$10277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161599$9881 + cell $reduce_or $reduce_or$libresoc.v:165024$10279 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161599$9881_Y + connect \Y $reduce_or$libresoc.v:165024$10279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161601$9883 + cell $reduce_or $reduce_or$libresoc.v:165026$10281 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161601$9883_Y + connect \Y $reduce_or$libresoc.v:165026$10281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161603$9885 + cell $reduce_or $reduce_or$libresoc.v:165028$10283 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161603$9885_Y + connect \Y $reduce_or$libresoc.v:165028$10283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161604$9886 + cell $reduce_or $reduce_or$libresoc.v:165029$10284 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161604$9886_Y + connect \Y $reduce_or$libresoc.v:165029$10284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161606$9888 + cell $reduce_or $reduce_or$libresoc.v:165031$10286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161606$9888_Y - end - connect \$7 $not$libresoc.v:161591$9873_Y - connect \$12 $reduce_or$libresoc.v:161592$9874_Y - connect \$11 $not$libresoc.v:161593$9875_Y - connect \$16 $reduce_or$libresoc.v:161594$9876_Y - connect \$15 $not$libresoc.v:161595$9877_Y - connect \$1 $not$libresoc.v:161596$9878_Y - connect \$20 $reduce_or$libresoc.v:161597$9879_Y - connect \$19 $not$libresoc.v:161598$9880_Y - connect \$24 $reduce_or$libresoc.v:161599$9881_Y - connect \$23 $not$libresoc.v:161600$9882_Y - connect \$28 $reduce_or$libresoc.v:161601$9883_Y - connect \$27 $not$libresoc.v:161602$9884_Y - connect \$31 $reduce_or$libresoc.v:161603$9885_Y - connect \$4 $reduce_or$libresoc.v:161604$9886_Y - connect \$3 $not$libresoc.v:161605$9887_Y - connect \$8 $reduce_or$libresoc.v:161606$9888_Y + connect \Y $reduce_or$libresoc.v:165031$10286_Y + end + connect \$7 $not$libresoc.v:165016$10271_Y + connect \$12 $reduce_or$libresoc.v:165017$10272_Y + connect \$11 $not$libresoc.v:165018$10273_Y + connect \$16 $reduce_or$libresoc.v:165019$10274_Y + connect \$15 $not$libresoc.v:165020$10275_Y + connect \$1 $not$libresoc.v:165021$10276_Y + connect \$20 $reduce_or$libresoc.v:165022$10277_Y + connect \$19 $not$libresoc.v:165023$10278_Y + connect \$24 $reduce_or$libresoc.v:165024$10279_Y + connect \$23 $not$libresoc.v:165025$10280_Y + connect \$28 $reduce_or$libresoc.v:165026$10281_Y + connect \$27 $not$libresoc.v:165027$10282_Y + connect \$31 $reduce_or$libresoc.v:165028$10283_Y + connect \$4 $reduce_or$libresoc.v:165029$10284_Y + connect \$3 $not$libresoc.v:165030$10285_Y + connect \$8 $reduce_or$libresoc.v:165031$10286_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -332047,43 +339977,43 @@ module \ppick$156 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161622.1-161706.10" +attribute \src "libresoc.v:165047.1-165131.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$158 - attribute \src "libresoc.v:161679.17-161679.91" - wire $not$libresoc.v:161679$9889_Y - attribute \src "libresoc.v:161681.18-161681.93" - wire $not$libresoc.v:161681$9891_Y - attribute \src "libresoc.v:161683.18-161683.93" - wire $not$libresoc.v:161683$9893_Y - attribute \src "libresoc.v:161684.17-161684.138" - wire width 8 $not$libresoc.v:161684$9894_Y - attribute \src "libresoc.v:161686.18-161686.93" - wire $not$libresoc.v:161686$9896_Y - attribute \src "libresoc.v:161688.18-161688.93" - wire $not$libresoc.v:161688$9898_Y - attribute \src "libresoc.v:161690.18-161690.93" - wire $not$libresoc.v:161690$9900_Y - attribute \src "libresoc.v:161693.17-161693.91" - wire $not$libresoc.v:161693$9903_Y - attribute \src "libresoc.v:161680.18-161680.116" - wire $reduce_or$libresoc.v:161680$9890_Y - attribute \src "libresoc.v:161682.18-161682.122" - wire $reduce_or$libresoc.v:161682$9892_Y - attribute \src "libresoc.v:161685.18-161685.128" - wire $reduce_or$libresoc.v:161685$9895_Y - attribute \src "libresoc.v:161687.18-161687.134" - wire $reduce_or$libresoc.v:161687$9897_Y - attribute \src "libresoc.v:161689.18-161689.140" - wire $reduce_or$libresoc.v:161689$9899_Y - attribute \src "libresoc.v:161691.18-161691.90" - wire $reduce_or$libresoc.v:161691$9901_Y - attribute \src "libresoc.v:161692.17-161692.103" - wire $reduce_or$libresoc.v:161692$9902_Y - attribute \src "libresoc.v:161694.17-161694.109" - wire $reduce_or$libresoc.v:161694$9904_Y +module \ppick$161 + attribute \src "libresoc.v:165104.17-165104.91" + wire $not$libresoc.v:165104$10287_Y + attribute \src "libresoc.v:165106.18-165106.93" + wire $not$libresoc.v:165106$10289_Y + attribute \src "libresoc.v:165108.18-165108.93" + wire $not$libresoc.v:165108$10291_Y + attribute \src "libresoc.v:165109.17-165109.138" + wire width 8 $not$libresoc.v:165109$10292_Y + attribute \src "libresoc.v:165111.18-165111.93" + wire $not$libresoc.v:165111$10294_Y + attribute \src "libresoc.v:165113.18-165113.93" + wire $not$libresoc.v:165113$10296_Y + attribute \src "libresoc.v:165115.18-165115.93" + wire $not$libresoc.v:165115$10298_Y + attribute \src "libresoc.v:165118.17-165118.91" + wire $not$libresoc.v:165118$10301_Y + attribute \src "libresoc.v:165105.18-165105.116" + wire $reduce_or$libresoc.v:165105$10288_Y + attribute \src "libresoc.v:165107.18-165107.122" + wire $reduce_or$libresoc.v:165107$10290_Y + attribute \src "libresoc.v:165110.18-165110.128" + wire $reduce_or$libresoc.v:165110$10293_Y + attribute \src "libresoc.v:165112.18-165112.134" + wire $reduce_or$libresoc.v:165112$10295_Y + attribute \src "libresoc.v:165114.18-165114.140" + wire $reduce_or$libresoc.v:165114$10297_Y + attribute \src "libresoc.v:165116.18-165116.90" + wire $reduce_or$libresoc.v:165116$10299_Y + attribute \src "libresoc.v:165117.17-165117.103" + wire $reduce_or$libresoc.v:165117$10300_Y + attribute \src "libresoc.v:165119.17-165119.109" + wire $reduce_or$libresoc.v:165119$10302_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -332141,149 +340071,149 @@ module \ppick$158 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161679$9889 + cell $not $not$libresoc.v:165104$10287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161679$9889_Y + connect \Y $not$libresoc.v:165104$10287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161681$9891 + cell $not $not$libresoc.v:165106$10289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161681$9891_Y + connect \Y $not$libresoc.v:165106$10289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161683$9893 + cell $not $not$libresoc.v:165108$10291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161683$9893_Y + connect \Y $not$libresoc.v:165108$10291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161684$9894 + cell $not $not$libresoc.v:165109$10292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161684$9894_Y + connect \Y $not$libresoc.v:165109$10292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161686$9896 + cell $not $not$libresoc.v:165111$10294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161686$9896_Y + connect \Y $not$libresoc.v:165111$10294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161688$9898 + cell $not $not$libresoc.v:165113$10296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161688$9898_Y + connect \Y $not$libresoc.v:165113$10296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161690$9900 + cell $not $not$libresoc.v:165115$10298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161690$9900_Y + connect \Y $not$libresoc.v:165115$10298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161693$9903 + cell $not $not$libresoc.v:165118$10301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161693$9903_Y + connect \Y $not$libresoc.v:165118$10301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161680$9890 + cell $reduce_or $reduce_or$libresoc.v:165105$10288 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161680$9890_Y + connect \Y $reduce_or$libresoc.v:165105$10288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161682$9892 + cell $reduce_or $reduce_or$libresoc.v:165107$10290 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161682$9892_Y + connect \Y $reduce_or$libresoc.v:165107$10290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161685$9895 + cell $reduce_or $reduce_or$libresoc.v:165110$10293 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161685$9895_Y + connect \Y $reduce_or$libresoc.v:165110$10293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161687$9897 + cell $reduce_or $reduce_or$libresoc.v:165112$10295 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161687$9897_Y + connect \Y $reduce_or$libresoc.v:165112$10295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161689$9899 + cell $reduce_or $reduce_or$libresoc.v:165114$10297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161689$9899_Y + connect \Y $reduce_or$libresoc.v:165114$10297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161691$9901 + cell $reduce_or $reduce_or$libresoc.v:165116$10299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161691$9901_Y + connect \Y $reduce_or$libresoc.v:165116$10299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161692$9902 + cell $reduce_or $reduce_or$libresoc.v:165117$10300 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161692$9902_Y + connect \Y $reduce_or$libresoc.v:165117$10300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161694$9904 + cell $reduce_or $reduce_or$libresoc.v:165119$10302 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161694$9904_Y - end - connect \$7 $not$libresoc.v:161679$9889_Y - connect \$12 $reduce_or$libresoc.v:161680$9890_Y - connect \$11 $not$libresoc.v:161681$9891_Y - connect \$16 $reduce_or$libresoc.v:161682$9892_Y - connect \$15 $not$libresoc.v:161683$9893_Y - connect \$1 $not$libresoc.v:161684$9894_Y - connect \$20 $reduce_or$libresoc.v:161685$9895_Y - connect \$19 $not$libresoc.v:161686$9896_Y - connect \$24 $reduce_or$libresoc.v:161687$9897_Y - connect \$23 $not$libresoc.v:161688$9898_Y - connect \$28 $reduce_or$libresoc.v:161689$9899_Y - connect \$27 $not$libresoc.v:161690$9900_Y - connect \$31 $reduce_or$libresoc.v:161691$9901_Y - connect \$4 $reduce_or$libresoc.v:161692$9902_Y - connect \$3 $not$libresoc.v:161693$9903_Y - connect \$8 $reduce_or$libresoc.v:161694$9904_Y + connect \Y $reduce_or$libresoc.v:165119$10302_Y + end + connect \$7 $not$libresoc.v:165104$10287_Y + connect \$12 $reduce_or$libresoc.v:165105$10288_Y + connect \$11 $not$libresoc.v:165106$10289_Y + connect \$16 $reduce_or$libresoc.v:165107$10290_Y + connect \$15 $not$libresoc.v:165108$10291_Y + connect \$1 $not$libresoc.v:165109$10292_Y + connect \$20 $reduce_or$libresoc.v:165110$10293_Y + connect \$19 $not$libresoc.v:165111$10294_Y + connect \$24 $reduce_or$libresoc.v:165112$10295_Y + connect \$23 $not$libresoc.v:165113$10296_Y + connect \$28 $reduce_or$libresoc.v:165114$10297_Y + connect \$27 $not$libresoc.v:165115$10298_Y + connect \$31 $reduce_or$libresoc.v:165116$10299_Y + connect \$4 $reduce_or$libresoc.v:165117$10300_Y + connect \$3 $not$libresoc.v:165118$10301_Y + connect \$8 $reduce_or$libresoc.v:165119$10302_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -332296,43 +340226,43 @@ module \ppick$158 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161710.1-161794.10" +attribute \src "libresoc.v:165135.1-165219.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$165 - attribute \src "libresoc.v:161767.17-161767.91" - wire $not$libresoc.v:161767$9905_Y - attribute \src "libresoc.v:161769.18-161769.93" - wire $not$libresoc.v:161769$9907_Y - attribute \src "libresoc.v:161771.18-161771.93" - wire $not$libresoc.v:161771$9909_Y - attribute \src "libresoc.v:161772.17-161772.138" - wire width 8 $not$libresoc.v:161772$9910_Y - attribute \src "libresoc.v:161774.18-161774.93" - wire $not$libresoc.v:161774$9912_Y - attribute \src "libresoc.v:161776.18-161776.93" - wire $not$libresoc.v:161776$9914_Y - attribute \src "libresoc.v:161778.18-161778.93" - wire $not$libresoc.v:161778$9916_Y - attribute \src "libresoc.v:161781.17-161781.91" - wire $not$libresoc.v:161781$9919_Y - attribute \src "libresoc.v:161768.18-161768.116" - wire $reduce_or$libresoc.v:161768$9906_Y - attribute \src "libresoc.v:161770.18-161770.122" - wire $reduce_or$libresoc.v:161770$9908_Y - attribute \src "libresoc.v:161773.18-161773.128" - wire $reduce_or$libresoc.v:161773$9911_Y - attribute \src "libresoc.v:161775.18-161775.134" - wire $reduce_or$libresoc.v:161775$9913_Y - attribute \src "libresoc.v:161777.18-161777.140" - wire $reduce_or$libresoc.v:161777$9915_Y - attribute \src "libresoc.v:161779.18-161779.90" - wire $reduce_or$libresoc.v:161779$9917_Y - attribute \src "libresoc.v:161780.17-161780.103" - wire $reduce_or$libresoc.v:161780$9918_Y - attribute \src "libresoc.v:161782.17-161782.109" - wire $reduce_or$libresoc.v:161782$9920_Y +module \ppick$168 + attribute \src "libresoc.v:165192.17-165192.91" + wire $not$libresoc.v:165192$10303_Y + attribute \src "libresoc.v:165194.18-165194.93" + wire $not$libresoc.v:165194$10305_Y + attribute \src "libresoc.v:165196.18-165196.93" + wire $not$libresoc.v:165196$10307_Y + attribute \src "libresoc.v:165197.17-165197.138" + wire width 8 $not$libresoc.v:165197$10308_Y + attribute \src "libresoc.v:165199.18-165199.93" + wire $not$libresoc.v:165199$10310_Y + attribute \src "libresoc.v:165201.18-165201.93" + wire $not$libresoc.v:165201$10312_Y + attribute \src "libresoc.v:165203.18-165203.93" + wire $not$libresoc.v:165203$10314_Y + attribute \src "libresoc.v:165206.17-165206.91" + wire $not$libresoc.v:165206$10317_Y + attribute \src "libresoc.v:165193.18-165193.116" + wire $reduce_or$libresoc.v:165193$10304_Y + attribute \src "libresoc.v:165195.18-165195.122" + wire $reduce_or$libresoc.v:165195$10306_Y + attribute \src "libresoc.v:165198.18-165198.128" + wire $reduce_or$libresoc.v:165198$10309_Y + attribute \src "libresoc.v:165200.18-165200.134" + wire $reduce_or$libresoc.v:165200$10311_Y + attribute \src "libresoc.v:165202.18-165202.140" + wire $reduce_or$libresoc.v:165202$10313_Y + attribute \src "libresoc.v:165204.18-165204.90" + wire $reduce_or$libresoc.v:165204$10315_Y + attribute \src "libresoc.v:165205.17-165205.103" + wire $reduce_or$libresoc.v:165205$10316_Y + attribute \src "libresoc.v:165207.17-165207.109" + wire $reduce_or$libresoc.v:165207$10318_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -332390,149 +340320,149 @@ module \ppick$165 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161767$9905 + cell $not $not$libresoc.v:165192$10303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161767$9905_Y + connect \Y $not$libresoc.v:165192$10303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161769$9907 + cell $not $not$libresoc.v:165194$10305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161769$9907_Y + connect \Y $not$libresoc.v:165194$10305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161771$9909 + cell $not $not$libresoc.v:165196$10307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161771$9909_Y + connect \Y $not$libresoc.v:165196$10307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161772$9910 + cell $not $not$libresoc.v:165197$10308 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161772$9910_Y + connect \Y $not$libresoc.v:165197$10308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161774$9912 + cell $not $not$libresoc.v:165199$10310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161774$9912_Y + connect \Y $not$libresoc.v:165199$10310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161776$9914 + cell $not $not$libresoc.v:165201$10312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161776$9914_Y + connect \Y $not$libresoc.v:165201$10312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161778$9916 + cell $not $not$libresoc.v:165203$10314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161778$9916_Y + connect \Y $not$libresoc.v:165203$10314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161781$9919 + cell $not $not$libresoc.v:165206$10317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161781$9919_Y + connect \Y $not$libresoc.v:165206$10317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161768$9906 + cell $reduce_or $reduce_or$libresoc.v:165193$10304 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161768$9906_Y + connect \Y $reduce_or$libresoc.v:165193$10304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161770$9908 + cell $reduce_or $reduce_or$libresoc.v:165195$10306 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161770$9908_Y + connect \Y $reduce_or$libresoc.v:165195$10306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161773$9911 + cell $reduce_or $reduce_or$libresoc.v:165198$10309 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161773$9911_Y + connect \Y $reduce_or$libresoc.v:165198$10309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161775$9913 + cell $reduce_or $reduce_or$libresoc.v:165200$10311 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161775$9913_Y + connect \Y $reduce_or$libresoc.v:165200$10311_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161777$9915 + cell $reduce_or $reduce_or$libresoc.v:165202$10313 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161777$9915_Y + connect \Y $reduce_or$libresoc.v:165202$10313_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161779$9917 + cell $reduce_or $reduce_or$libresoc.v:165204$10315 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161779$9917_Y + connect \Y $reduce_or$libresoc.v:165204$10315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161780$9918 + cell $reduce_or $reduce_or$libresoc.v:165205$10316 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161780$9918_Y + connect \Y $reduce_or$libresoc.v:165205$10316_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161782$9920 + cell $reduce_or $reduce_or$libresoc.v:165207$10318 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161782$9920_Y - end - connect \$7 $not$libresoc.v:161767$9905_Y - connect \$12 $reduce_or$libresoc.v:161768$9906_Y - connect \$11 $not$libresoc.v:161769$9907_Y - connect \$16 $reduce_or$libresoc.v:161770$9908_Y - connect \$15 $not$libresoc.v:161771$9909_Y - connect \$1 $not$libresoc.v:161772$9910_Y - connect \$20 $reduce_or$libresoc.v:161773$9911_Y - connect \$19 $not$libresoc.v:161774$9912_Y - connect \$24 $reduce_or$libresoc.v:161775$9913_Y - connect \$23 $not$libresoc.v:161776$9914_Y - connect \$28 $reduce_or$libresoc.v:161777$9915_Y - connect \$27 $not$libresoc.v:161778$9916_Y - connect \$31 $reduce_or$libresoc.v:161779$9917_Y - connect \$4 $reduce_or$libresoc.v:161780$9918_Y - connect \$3 $not$libresoc.v:161781$9919_Y - connect \$8 $reduce_or$libresoc.v:161782$9920_Y + connect \Y $reduce_or$libresoc.v:165207$10318_Y + end + connect \$7 $not$libresoc.v:165192$10303_Y + connect \$12 $reduce_or$libresoc.v:165193$10304_Y + connect \$11 $not$libresoc.v:165194$10305_Y + connect \$16 $reduce_or$libresoc.v:165195$10306_Y + connect \$15 $not$libresoc.v:165196$10307_Y + connect \$1 $not$libresoc.v:165197$10308_Y + connect \$20 $reduce_or$libresoc.v:165198$10309_Y + connect \$19 $not$libresoc.v:165199$10310_Y + connect \$24 $reduce_or$libresoc.v:165200$10311_Y + connect \$23 $not$libresoc.v:165201$10312_Y + connect \$28 $reduce_or$libresoc.v:165202$10313_Y + connect \$27 $not$libresoc.v:165203$10314_Y + connect \$31 $reduce_or$libresoc.v:165204$10315_Y + connect \$4 $reduce_or$libresoc.v:165205$10316_Y + connect \$3 $not$libresoc.v:165206$10317_Y + connect \$8 $reduce_or$libresoc.v:165207$10318_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -332545,43 +340475,43 @@ module \ppick$165 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161798.1-161882.10" +attribute \src "libresoc.v:165223.1-165307.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$167 - attribute \src "libresoc.v:161855.17-161855.91" - wire $not$libresoc.v:161855$9921_Y - attribute \src "libresoc.v:161857.18-161857.93" - wire $not$libresoc.v:161857$9923_Y - attribute \src "libresoc.v:161859.18-161859.93" - wire $not$libresoc.v:161859$9925_Y - attribute \src "libresoc.v:161860.17-161860.138" - wire width 8 $not$libresoc.v:161860$9926_Y - attribute \src "libresoc.v:161862.18-161862.93" - wire $not$libresoc.v:161862$9928_Y - attribute \src "libresoc.v:161864.18-161864.93" - wire $not$libresoc.v:161864$9930_Y - attribute \src "libresoc.v:161866.18-161866.93" - wire $not$libresoc.v:161866$9932_Y - attribute \src "libresoc.v:161869.17-161869.91" - wire $not$libresoc.v:161869$9935_Y - attribute \src "libresoc.v:161856.18-161856.116" - wire $reduce_or$libresoc.v:161856$9922_Y - attribute \src "libresoc.v:161858.18-161858.122" - wire $reduce_or$libresoc.v:161858$9924_Y - attribute \src "libresoc.v:161861.18-161861.128" - wire $reduce_or$libresoc.v:161861$9927_Y - attribute \src "libresoc.v:161863.18-161863.134" - wire $reduce_or$libresoc.v:161863$9929_Y - attribute \src "libresoc.v:161865.18-161865.140" - wire $reduce_or$libresoc.v:161865$9931_Y - attribute \src "libresoc.v:161867.18-161867.90" - wire $reduce_or$libresoc.v:161867$9933_Y - attribute \src "libresoc.v:161868.17-161868.103" - wire $reduce_or$libresoc.v:161868$9934_Y - attribute \src "libresoc.v:161870.17-161870.109" - wire $reduce_or$libresoc.v:161870$9936_Y +module \ppick$170 + attribute \src "libresoc.v:165280.17-165280.91" + wire $not$libresoc.v:165280$10319_Y + attribute \src "libresoc.v:165282.18-165282.93" + wire $not$libresoc.v:165282$10321_Y + attribute \src "libresoc.v:165284.18-165284.93" + wire $not$libresoc.v:165284$10323_Y + attribute \src "libresoc.v:165285.17-165285.138" + wire width 8 $not$libresoc.v:165285$10324_Y + attribute \src "libresoc.v:165287.18-165287.93" + wire $not$libresoc.v:165287$10326_Y + attribute \src "libresoc.v:165289.18-165289.93" + wire $not$libresoc.v:165289$10328_Y + attribute \src "libresoc.v:165291.18-165291.93" + wire $not$libresoc.v:165291$10330_Y + attribute \src "libresoc.v:165294.17-165294.91" + wire $not$libresoc.v:165294$10333_Y + attribute \src "libresoc.v:165281.18-165281.116" + wire $reduce_or$libresoc.v:165281$10320_Y + attribute \src "libresoc.v:165283.18-165283.122" + wire $reduce_or$libresoc.v:165283$10322_Y + attribute \src "libresoc.v:165286.18-165286.128" + wire $reduce_or$libresoc.v:165286$10325_Y + attribute \src "libresoc.v:165288.18-165288.134" + wire $reduce_or$libresoc.v:165288$10327_Y + attribute \src "libresoc.v:165290.18-165290.140" + wire $reduce_or$libresoc.v:165290$10329_Y + attribute \src "libresoc.v:165292.18-165292.90" + wire $reduce_or$libresoc.v:165292$10331_Y + attribute \src "libresoc.v:165293.17-165293.103" + wire $reduce_or$libresoc.v:165293$10332_Y + attribute \src "libresoc.v:165295.17-165295.109" + wire $reduce_or$libresoc.v:165295$10334_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -332639,149 +340569,149 @@ module \ppick$167 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161855$9921 + cell $not $not$libresoc.v:165280$10319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161855$9921_Y + connect \Y $not$libresoc.v:165280$10319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161857$9923 + cell $not $not$libresoc.v:165282$10321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161857$9923_Y + connect \Y $not$libresoc.v:165282$10321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161859$9925 + cell $not $not$libresoc.v:165284$10323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161859$9925_Y + connect \Y $not$libresoc.v:165284$10323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161860$9926 + cell $not $not$libresoc.v:165285$10324 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161860$9926_Y + connect \Y $not$libresoc.v:165285$10324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161862$9928 + cell $not $not$libresoc.v:165287$10326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161862$9928_Y + connect \Y $not$libresoc.v:165287$10326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161864$9930 + cell $not $not$libresoc.v:165289$10328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161864$9930_Y + connect \Y $not$libresoc.v:165289$10328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161866$9932 + cell $not $not$libresoc.v:165291$10330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161866$9932_Y + connect \Y $not$libresoc.v:165291$10330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161869$9935 + cell $not $not$libresoc.v:165294$10333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161869$9935_Y + connect \Y $not$libresoc.v:165294$10333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161856$9922 + cell $reduce_or $reduce_or$libresoc.v:165281$10320 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161856$9922_Y + connect \Y $reduce_or$libresoc.v:165281$10320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161858$9924 + cell $reduce_or $reduce_or$libresoc.v:165283$10322 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161858$9924_Y + connect \Y $reduce_or$libresoc.v:165283$10322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161861$9927 + cell $reduce_or $reduce_or$libresoc.v:165286$10325 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161861$9927_Y + connect \Y $reduce_or$libresoc.v:165286$10325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161863$9929 + cell $reduce_or $reduce_or$libresoc.v:165288$10327 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161863$9929_Y + connect \Y $reduce_or$libresoc.v:165288$10327_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161865$9931 + cell $reduce_or $reduce_or$libresoc.v:165290$10329 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161865$9931_Y + connect \Y $reduce_or$libresoc.v:165290$10329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161867$9933 + cell $reduce_or $reduce_or$libresoc.v:165292$10331 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161867$9933_Y + connect \Y $reduce_or$libresoc.v:165292$10331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161868$9934 + cell $reduce_or $reduce_or$libresoc.v:165293$10332 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161868$9934_Y + connect \Y $reduce_or$libresoc.v:165293$10332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161870$9936 + cell $reduce_or $reduce_or$libresoc.v:165295$10334 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161870$9936_Y - end - connect \$7 $not$libresoc.v:161855$9921_Y - connect \$12 $reduce_or$libresoc.v:161856$9922_Y - connect \$11 $not$libresoc.v:161857$9923_Y - connect \$16 $reduce_or$libresoc.v:161858$9924_Y - connect \$15 $not$libresoc.v:161859$9925_Y - connect \$1 $not$libresoc.v:161860$9926_Y - connect \$20 $reduce_or$libresoc.v:161861$9927_Y - connect \$19 $not$libresoc.v:161862$9928_Y - connect \$24 $reduce_or$libresoc.v:161863$9929_Y - connect \$23 $not$libresoc.v:161864$9930_Y - connect \$28 $reduce_or$libresoc.v:161865$9931_Y - connect \$27 $not$libresoc.v:161866$9932_Y - connect \$31 $reduce_or$libresoc.v:161867$9933_Y - connect \$4 $reduce_or$libresoc.v:161868$9934_Y - connect \$3 $not$libresoc.v:161869$9935_Y - connect \$8 $reduce_or$libresoc.v:161870$9936_Y + connect \Y $reduce_or$libresoc.v:165295$10334_Y + end + connect \$7 $not$libresoc.v:165280$10319_Y + connect \$12 $reduce_or$libresoc.v:165281$10320_Y + connect \$11 $not$libresoc.v:165282$10321_Y + connect \$16 $reduce_or$libresoc.v:165283$10322_Y + connect \$15 $not$libresoc.v:165284$10323_Y + connect \$1 $not$libresoc.v:165285$10324_Y + connect \$20 $reduce_or$libresoc.v:165286$10325_Y + connect \$19 $not$libresoc.v:165287$10326_Y + connect \$24 $reduce_or$libresoc.v:165288$10327_Y + connect \$23 $not$libresoc.v:165289$10328_Y + connect \$28 $reduce_or$libresoc.v:165290$10329_Y + connect \$27 $not$libresoc.v:165291$10330_Y + connect \$31 $reduce_or$libresoc.v:165292$10331_Y + connect \$4 $reduce_or$libresoc.v:165293$10332_Y + connect \$3 $not$libresoc.v:165294$10333_Y + connect \$8 $reduce_or$libresoc.v:165295$10334_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -332794,43 +340724,43 @@ module \ppick$167 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161886.1-161970.10" +attribute \src "libresoc.v:165311.1-165395.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$172 - attribute \src "libresoc.v:161943.17-161943.91" - wire $not$libresoc.v:161943$9937_Y - attribute \src "libresoc.v:161945.18-161945.93" - wire $not$libresoc.v:161945$9939_Y - attribute \src "libresoc.v:161947.18-161947.93" - wire $not$libresoc.v:161947$9941_Y - attribute \src "libresoc.v:161948.17-161948.138" - wire width 8 $not$libresoc.v:161948$9942_Y - attribute \src "libresoc.v:161950.18-161950.93" - wire $not$libresoc.v:161950$9944_Y - attribute \src "libresoc.v:161952.18-161952.93" - wire $not$libresoc.v:161952$9946_Y - attribute \src "libresoc.v:161954.18-161954.93" - wire $not$libresoc.v:161954$9948_Y - attribute \src "libresoc.v:161957.17-161957.91" - wire $not$libresoc.v:161957$9951_Y - attribute \src "libresoc.v:161944.18-161944.116" - wire $reduce_or$libresoc.v:161944$9938_Y - attribute \src "libresoc.v:161946.18-161946.122" - wire $reduce_or$libresoc.v:161946$9940_Y - attribute \src "libresoc.v:161949.18-161949.128" - wire $reduce_or$libresoc.v:161949$9943_Y - attribute \src "libresoc.v:161951.18-161951.134" - wire $reduce_or$libresoc.v:161951$9945_Y - attribute \src "libresoc.v:161953.18-161953.140" - wire $reduce_or$libresoc.v:161953$9947_Y - attribute \src "libresoc.v:161955.18-161955.90" - wire $reduce_or$libresoc.v:161955$9949_Y - attribute \src "libresoc.v:161956.17-161956.103" - wire $reduce_or$libresoc.v:161956$9950_Y - attribute \src "libresoc.v:161958.17-161958.109" - wire $reduce_or$libresoc.v:161958$9952_Y +module \ppick$175 + attribute \src "libresoc.v:165368.17-165368.91" + wire $not$libresoc.v:165368$10335_Y + attribute \src "libresoc.v:165370.18-165370.93" + wire $not$libresoc.v:165370$10337_Y + attribute \src "libresoc.v:165372.18-165372.93" + wire $not$libresoc.v:165372$10339_Y + attribute \src "libresoc.v:165373.17-165373.138" + wire width 8 $not$libresoc.v:165373$10340_Y + attribute \src "libresoc.v:165375.18-165375.93" + wire $not$libresoc.v:165375$10342_Y + attribute \src "libresoc.v:165377.18-165377.93" + wire $not$libresoc.v:165377$10344_Y + attribute \src "libresoc.v:165379.18-165379.93" + wire $not$libresoc.v:165379$10346_Y + attribute \src "libresoc.v:165382.17-165382.91" + wire $not$libresoc.v:165382$10349_Y + attribute \src "libresoc.v:165369.18-165369.116" + wire $reduce_or$libresoc.v:165369$10336_Y + attribute \src "libresoc.v:165371.18-165371.122" + wire $reduce_or$libresoc.v:165371$10338_Y + attribute \src "libresoc.v:165374.18-165374.128" + wire $reduce_or$libresoc.v:165374$10341_Y + attribute \src "libresoc.v:165376.18-165376.134" + wire $reduce_or$libresoc.v:165376$10343_Y + attribute \src "libresoc.v:165378.18-165378.140" + wire $reduce_or$libresoc.v:165378$10345_Y + attribute \src "libresoc.v:165380.18-165380.90" + wire $reduce_or$libresoc.v:165380$10347_Y + attribute \src "libresoc.v:165381.17-165381.103" + wire $reduce_or$libresoc.v:165381$10348_Y + attribute \src "libresoc.v:165383.17-165383.109" + wire $reduce_or$libresoc.v:165383$10350_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -332888,149 +340818,149 @@ module \ppick$172 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161943$9937 + cell $not $not$libresoc.v:165368$10335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:161943$9937_Y + connect \Y $not$libresoc.v:165368$10335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161945$9939 + cell $not $not$libresoc.v:165370$10337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:161945$9939_Y + connect \Y $not$libresoc.v:165370$10337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161947$9941 + cell $not $not$libresoc.v:165372$10339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:161947$9941_Y + connect \Y $not$libresoc.v:165372$10339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:161948$9942 + cell $not $not$libresoc.v:165373$10340 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:161948$9942_Y + connect \Y $not$libresoc.v:165373$10340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161950$9944 + cell $not $not$libresoc.v:165375$10342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:161950$9944_Y + connect \Y $not$libresoc.v:165375$10342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161952$9946 + cell $not $not$libresoc.v:165377$10344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:161952$9946_Y + connect \Y $not$libresoc.v:165377$10344_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161954$9948 + cell $not $not$libresoc.v:165379$10346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:161954$9948_Y + connect \Y $not$libresoc.v:165379$10346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:161957$9951 + cell $not $not$libresoc.v:165382$10349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:161957$9951_Y + connect \Y $not$libresoc.v:165382$10349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161944$9938 + cell $reduce_or $reduce_or$libresoc.v:165369$10336 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:161944$9938_Y + connect \Y $reduce_or$libresoc.v:165369$10336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161946$9940 + cell $reduce_or $reduce_or$libresoc.v:165371$10338 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:161946$9940_Y + connect \Y $reduce_or$libresoc.v:165371$10338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161949$9943 + cell $reduce_or $reduce_or$libresoc.v:165374$10341 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:161949$9943_Y + connect \Y $reduce_or$libresoc.v:165374$10341_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161951$9945 + cell $reduce_or $reduce_or$libresoc.v:165376$10343 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:161951$9945_Y + connect \Y $reduce_or$libresoc.v:165376$10343_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161953$9947 + cell $reduce_or $reduce_or$libresoc.v:165378$10345 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:161953$9947_Y + connect \Y $reduce_or$libresoc.v:165378$10345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:161955$9949 + cell $reduce_or $reduce_or$libresoc.v:165380$10347 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:161955$9949_Y + connect \Y $reduce_or$libresoc.v:165380$10347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161956$9950 + cell $reduce_or $reduce_or$libresoc.v:165381$10348 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:161956$9950_Y + connect \Y $reduce_or$libresoc.v:165381$10348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:161958$9952 + cell $reduce_or $reduce_or$libresoc.v:165383$10350 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:161958$9952_Y - end - connect \$7 $not$libresoc.v:161943$9937_Y - connect \$12 $reduce_or$libresoc.v:161944$9938_Y - connect \$11 $not$libresoc.v:161945$9939_Y - connect \$16 $reduce_or$libresoc.v:161946$9940_Y - connect \$15 $not$libresoc.v:161947$9941_Y - connect \$1 $not$libresoc.v:161948$9942_Y - connect \$20 $reduce_or$libresoc.v:161949$9943_Y - connect \$19 $not$libresoc.v:161950$9944_Y - connect \$24 $reduce_or$libresoc.v:161951$9945_Y - connect \$23 $not$libresoc.v:161952$9946_Y - connect \$28 $reduce_or$libresoc.v:161953$9947_Y - connect \$27 $not$libresoc.v:161954$9948_Y - connect \$31 $reduce_or$libresoc.v:161955$9949_Y - connect \$4 $reduce_or$libresoc.v:161956$9950_Y - connect \$3 $not$libresoc.v:161957$9951_Y - connect \$8 $reduce_or$libresoc.v:161958$9952_Y + connect \Y $reduce_or$libresoc.v:165383$10350_Y + end + connect \$7 $not$libresoc.v:165368$10335_Y + connect \$12 $reduce_or$libresoc.v:165369$10336_Y + connect \$11 $not$libresoc.v:165370$10337_Y + connect \$16 $reduce_or$libresoc.v:165371$10338_Y + connect \$15 $not$libresoc.v:165372$10339_Y + connect \$1 $not$libresoc.v:165373$10340_Y + connect \$20 $reduce_or$libresoc.v:165374$10341_Y + connect \$19 $not$libresoc.v:165375$10342_Y + connect \$24 $reduce_or$libresoc.v:165376$10343_Y + connect \$23 $not$libresoc.v:165377$10344_Y + connect \$28 $reduce_or$libresoc.v:165378$10345_Y + connect \$27 $not$libresoc.v:165379$10346_Y + connect \$31 $reduce_or$libresoc.v:165380$10347_Y + connect \$4 $reduce_or$libresoc.v:165381$10348_Y + connect \$3 $not$libresoc.v:165382$10349_Y + connect \$8 $reduce_or$libresoc.v:165383$10350_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -333043,43 +340973,43 @@ module \ppick$172 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:161974.1-162058.10" +attribute \src "libresoc.v:165399.1-165483.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$174 - attribute \src "libresoc.v:162031.17-162031.91" - wire $not$libresoc.v:162031$9953_Y - attribute \src "libresoc.v:162033.18-162033.93" - wire $not$libresoc.v:162033$9955_Y - attribute \src "libresoc.v:162035.18-162035.93" - wire $not$libresoc.v:162035$9957_Y - attribute \src "libresoc.v:162036.17-162036.138" - wire width 8 $not$libresoc.v:162036$9958_Y - attribute \src "libresoc.v:162038.18-162038.93" - wire $not$libresoc.v:162038$9960_Y - attribute \src "libresoc.v:162040.18-162040.93" - wire $not$libresoc.v:162040$9962_Y - attribute \src "libresoc.v:162042.18-162042.93" - wire $not$libresoc.v:162042$9964_Y - attribute \src "libresoc.v:162045.17-162045.91" - wire $not$libresoc.v:162045$9967_Y - attribute \src "libresoc.v:162032.18-162032.116" - wire $reduce_or$libresoc.v:162032$9954_Y - attribute \src "libresoc.v:162034.18-162034.122" - wire $reduce_or$libresoc.v:162034$9956_Y - attribute \src "libresoc.v:162037.18-162037.128" - wire $reduce_or$libresoc.v:162037$9959_Y - attribute \src "libresoc.v:162039.18-162039.134" - wire $reduce_or$libresoc.v:162039$9961_Y - attribute \src "libresoc.v:162041.18-162041.140" - wire $reduce_or$libresoc.v:162041$9963_Y - attribute \src "libresoc.v:162043.18-162043.90" - wire $reduce_or$libresoc.v:162043$9965_Y - attribute \src "libresoc.v:162044.17-162044.103" - wire $reduce_or$libresoc.v:162044$9966_Y - attribute \src "libresoc.v:162046.17-162046.109" - wire $reduce_or$libresoc.v:162046$9968_Y +module \ppick$177 + attribute \src "libresoc.v:165456.17-165456.91" + wire $not$libresoc.v:165456$10351_Y + attribute \src "libresoc.v:165458.18-165458.93" + wire $not$libresoc.v:165458$10353_Y + attribute \src "libresoc.v:165460.18-165460.93" + wire $not$libresoc.v:165460$10355_Y + attribute \src "libresoc.v:165461.17-165461.138" + wire width 8 $not$libresoc.v:165461$10356_Y + attribute \src "libresoc.v:165463.18-165463.93" + wire $not$libresoc.v:165463$10358_Y + attribute \src "libresoc.v:165465.18-165465.93" + wire $not$libresoc.v:165465$10360_Y + attribute \src "libresoc.v:165467.18-165467.93" + wire $not$libresoc.v:165467$10362_Y + attribute \src "libresoc.v:165470.17-165470.91" + wire $not$libresoc.v:165470$10365_Y + attribute \src "libresoc.v:165457.18-165457.116" + wire $reduce_or$libresoc.v:165457$10352_Y + attribute \src "libresoc.v:165459.18-165459.122" + wire $reduce_or$libresoc.v:165459$10354_Y + attribute \src "libresoc.v:165462.18-165462.128" + wire $reduce_or$libresoc.v:165462$10357_Y + attribute \src "libresoc.v:165464.18-165464.134" + wire $reduce_or$libresoc.v:165464$10359_Y + attribute \src "libresoc.v:165466.18-165466.140" + wire $reduce_or$libresoc.v:165466$10361_Y + attribute \src "libresoc.v:165468.18-165468.90" + wire $reduce_or$libresoc.v:165468$10363_Y + attribute \src "libresoc.v:165469.17-165469.103" + wire $reduce_or$libresoc.v:165469$10364_Y + attribute \src "libresoc.v:165471.17-165471.109" + wire $reduce_or$libresoc.v:165471$10366_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -333137,149 +341067,149 @@ module \ppick$174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162031$9953 + cell $not $not$libresoc.v:165456$10351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162031$9953_Y + connect \Y $not$libresoc.v:165456$10351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162033$9955 + cell $not $not$libresoc.v:165458$10353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162033$9955_Y + connect \Y $not$libresoc.v:165458$10353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162035$9957 + cell $not $not$libresoc.v:165460$10355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162035$9957_Y + connect \Y $not$libresoc.v:165460$10355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162036$9958 + cell $not $not$libresoc.v:165461$10356 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162036$9958_Y + connect \Y $not$libresoc.v:165461$10356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162038$9960 + cell $not $not$libresoc.v:165463$10358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162038$9960_Y + connect \Y $not$libresoc.v:165463$10358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162040$9962 + cell $not $not$libresoc.v:165465$10360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162040$9962_Y + connect \Y $not$libresoc.v:165465$10360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162042$9964 + cell $not $not$libresoc.v:165467$10362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162042$9964_Y + connect \Y $not$libresoc.v:165467$10362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162045$9967 + cell $not $not$libresoc.v:165470$10365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162045$9967_Y + connect \Y $not$libresoc.v:165470$10365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162032$9954 + cell $reduce_or $reduce_or$libresoc.v:165457$10352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162032$9954_Y + connect \Y $reduce_or$libresoc.v:165457$10352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162034$9956 + cell $reduce_or $reduce_or$libresoc.v:165459$10354 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162034$9956_Y + connect \Y $reduce_or$libresoc.v:165459$10354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162037$9959 + cell $reduce_or $reduce_or$libresoc.v:165462$10357 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162037$9959_Y + connect \Y $reduce_or$libresoc.v:165462$10357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162039$9961 + cell $reduce_or $reduce_or$libresoc.v:165464$10359 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162039$9961_Y + connect \Y $reduce_or$libresoc.v:165464$10359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162041$9963 + cell $reduce_or $reduce_or$libresoc.v:165466$10361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162041$9963_Y + connect \Y $reduce_or$libresoc.v:165466$10361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162043$9965 + cell $reduce_or $reduce_or$libresoc.v:165468$10363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162043$9965_Y + connect \Y $reduce_or$libresoc.v:165468$10363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162044$9966 + cell $reduce_or $reduce_or$libresoc.v:165469$10364 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162044$9966_Y + connect \Y $reduce_or$libresoc.v:165469$10364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162046$9968 + cell $reduce_or $reduce_or$libresoc.v:165471$10366 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162046$9968_Y - end - connect \$7 $not$libresoc.v:162031$9953_Y - connect \$12 $reduce_or$libresoc.v:162032$9954_Y - connect \$11 $not$libresoc.v:162033$9955_Y - connect \$16 $reduce_or$libresoc.v:162034$9956_Y - connect \$15 $not$libresoc.v:162035$9957_Y - connect \$1 $not$libresoc.v:162036$9958_Y - connect \$20 $reduce_or$libresoc.v:162037$9959_Y - connect \$19 $not$libresoc.v:162038$9960_Y - connect \$24 $reduce_or$libresoc.v:162039$9961_Y - connect \$23 $not$libresoc.v:162040$9962_Y - connect \$28 $reduce_or$libresoc.v:162041$9963_Y - connect \$27 $not$libresoc.v:162042$9964_Y - connect \$31 $reduce_or$libresoc.v:162043$9965_Y - connect \$4 $reduce_or$libresoc.v:162044$9966_Y - connect \$3 $not$libresoc.v:162045$9967_Y - connect \$8 $reduce_or$libresoc.v:162046$9968_Y + connect \Y $reduce_or$libresoc.v:165471$10366_Y + end + connect \$7 $not$libresoc.v:165456$10351_Y + connect \$12 $reduce_or$libresoc.v:165457$10352_Y + connect \$11 $not$libresoc.v:165458$10353_Y + connect \$16 $reduce_or$libresoc.v:165459$10354_Y + connect \$15 $not$libresoc.v:165460$10355_Y + connect \$1 $not$libresoc.v:165461$10356_Y + connect \$20 $reduce_or$libresoc.v:165462$10357_Y + connect \$19 $not$libresoc.v:165463$10358_Y + connect \$24 $reduce_or$libresoc.v:165464$10359_Y + connect \$23 $not$libresoc.v:165465$10360_Y + connect \$28 $reduce_or$libresoc.v:165466$10361_Y + connect \$27 $not$libresoc.v:165467$10362_Y + connect \$31 $reduce_or$libresoc.v:165468$10363_Y + connect \$4 $reduce_or$libresoc.v:165469$10364_Y + connect \$3 $not$libresoc.v:165470$10365_Y + connect \$8 $reduce_or$libresoc.v:165471$10366_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -333292,43 +341222,43 @@ module \ppick$174 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162062.1-162146.10" +attribute \src "libresoc.v:165487.1-165571.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$181 - attribute \src "libresoc.v:162119.17-162119.91" - wire $not$libresoc.v:162119$9969_Y - attribute \src "libresoc.v:162121.18-162121.93" - wire $not$libresoc.v:162121$9971_Y - attribute \src "libresoc.v:162123.18-162123.93" - wire $not$libresoc.v:162123$9973_Y - attribute \src "libresoc.v:162124.17-162124.138" - wire width 8 $not$libresoc.v:162124$9974_Y - attribute \src "libresoc.v:162126.18-162126.93" - wire $not$libresoc.v:162126$9976_Y - attribute \src "libresoc.v:162128.18-162128.93" - wire $not$libresoc.v:162128$9978_Y - attribute \src "libresoc.v:162130.18-162130.93" - wire $not$libresoc.v:162130$9980_Y - attribute \src "libresoc.v:162133.17-162133.91" - wire $not$libresoc.v:162133$9983_Y - attribute \src "libresoc.v:162120.18-162120.116" - wire $reduce_or$libresoc.v:162120$9970_Y - attribute \src "libresoc.v:162122.18-162122.122" - wire $reduce_or$libresoc.v:162122$9972_Y - attribute \src "libresoc.v:162125.18-162125.128" - wire $reduce_or$libresoc.v:162125$9975_Y - attribute \src "libresoc.v:162127.18-162127.134" - wire $reduce_or$libresoc.v:162127$9977_Y - attribute \src "libresoc.v:162129.18-162129.140" - wire $reduce_or$libresoc.v:162129$9979_Y - attribute \src "libresoc.v:162131.18-162131.90" - wire $reduce_or$libresoc.v:162131$9981_Y - attribute \src "libresoc.v:162132.17-162132.103" - wire $reduce_or$libresoc.v:162132$9982_Y - attribute \src "libresoc.v:162134.17-162134.109" - wire $reduce_or$libresoc.v:162134$9984_Y +module \ppick$184 + attribute \src "libresoc.v:165544.17-165544.91" + wire $not$libresoc.v:165544$10367_Y + attribute \src "libresoc.v:165546.18-165546.93" + wire $not$libresoc.v:165546$10369_Y + attribute \src "libresoc.v:165548.18-165548.93" + wire $not$libresoc.v:165548$10371_Y + attribute \src "libresoc.v:165549.17-165549.138" + wire width 8 $not$libresoc.v:165549$10372_Y + attribute \src "libresoc.v:165551.18-165551.93" + wire $not$libresoc.v:165551$10374_Y + attribute \src "libresoc.v:165553.18-165553.93" + wire $not$libresoc.v:165553$10376_Y + attribute \src "libresoc.v:165555.18-165555.93" + wire $not$libresoc.v:165555$10378_Y + attribute \src "libresoc.v:165558.17-165558.91" + wire $not$libresoc.v:165558$10381_Y + attribute \src "libresoc.v:165545.18-165545.116" + wire $reduce_or$libresoc.v:165545$10368_Y + attribute \src "libresoc.v:165547.18-165547.122" + wire $reduce_or$libresoc.v:165547$10370_Y + attribute \src "libresoc.v:165550.18-165550.128" + wire $reduce_or$libresoc.v:165550$10373_Y + attribute \src "libresoc.v:165552.18-165552.134" + wire $reduce_or$libresoc.v:165552$10375_Y + attribute \src "libresoc.v:165554.18-165554.140" + wire $reduce_or$libresoc.v:165554$10377_Y + attribute \src "libresoc.v:165556.18-165556.90" + wire $reduce_or$libresoc.v:165556$10379_Y + attribute \src "libresoc.v:165557.17-165557.103" + wire $reduce_or$libresoc.v:165557$10380_Y + attribute \src "libresoc.v:165559.17-165559.109" + wire $reduce_or$libresoc.v:165559$10382_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -333386,149 +341316,149 @@ module \ppick$181 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162119$9969 + cell $not $not$libresoc.v:165544$10367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162119$9969_Y + connect \Y $not$libresoc.v:165544$10367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162121$9971 + cell $not $not$libresoc.v:165546$10369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162121$9971_Y + connect \Y $not$libresoc.v:165546$10369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162123$9973 + cell $not $not$libresoc.v:165548$10371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162123$9973_Y + connect \Y $not$libresoc.v:165548$10371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162124$9974 + cell $not $not$libresoc.v:165549$10372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162124$9974_Y + connect \Y $not$libresoc.v:165549$10372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162126$9976 + cell $not $not$libresoc.v:165551$10374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162126$9976_Y + connect \Y $not$libresoc.v:165551$10374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162128$9978 + cell $not $not$libresoc.v:165553$10376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162128$9978_Y + connect \Y $not$libresoc.v:165553$10376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162130$9980 + cell $not $not$libresoc.v:165555$10378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162130$9980_Y + connect \Y $not$libresoc.v:165555$10378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162133$9983 + cell $not $not$libresoc.v:165558$10381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162133$9983_Y + connect \Y $not$libresoc.v:165558$10381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162120$9970 + cell $reduce_or $reduce_or$libresoc.v:165545$10368 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162120$9970_Y + connect \Y $reduce_or$libresoc.v:165545$10368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162122$9972 + cell $reduce_or $reduce_or$libresoc.v:165547$10370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162122$9972_Y + connect \Y $reduce_or$libresoc.v:165547$10370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162125$9975 + cell $reduce_or $reduce_or$libresoc.v:165550$10373 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162125$9975_Y + connect \Y $reduce_or$libresoc.v:165550$10373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162127$9977 + cell $reduce_or $reduce_or$libresoc.v:165552$10375 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162127$9977_Y + connect \Y $reduce_or$libresoc.v:165552$10375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162129$9979 + cell $reduce_or $reduce_or$libresoc.v:165554$10377 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162129$9979_Y + connect \Y $reduce_or$libresoc.v:165554$10377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162131$9981 + cell $reduce_or $reduce_or$libresoc.v:165556$10379 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162131$9981_Y + connect \Y $reduce_or$libresoc.v:165556$10379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162132$9982 + cell $reduce_or $reduce_or$libresoc.v:165557$10380 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162132$9982_Y + connect \Y $reduce_or$libresoc.v:165557$10380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162134$9984 + cell $reduce_or $reduce_or$libresoc.v:165559$10382 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162134$9984_Y - end - connect \$7 $not$libresoc.v:162119$9969_Y - connect \$12 $reduce_or$libresoc.v:162120$9970_Y - connect \$11 $not$libresoc.v:162121$9971_Y - connect \$16 $reduce_or$libresoc.v:162122$9972_Y - connect \$15 $not$libresoc.v:162123$9973_Y - connect \$1 $not$libresoc.v:162124$9974_Y - connect \$20 $reduce_or$libresoc.v:162125$9975_Y - connect \$19 $not$libresoc.v:162126$9976_Y - connect \$24 $reduce_or$libresoc.v:162127$9977_Y - connect \$23 $not$libresoc.v:162128$9978_Y - connect \$28 $reduce_or$libresoc.v:162129$9979_Y - connect \$27 $not$libresoc.v:162130$9980_Y - connect \$31 $reduce_or$libresoc.v:162131$9981_Y - connect \$4 $reduce_or$libresoc.v:162132$9982_Y - connect \$3 $not$libresoc.v:162133$9983_Y - connect \$8 $reduce_or$libresoc.v:162134$9984_Y + connect \Y $reduce_or$libresoc.v:165559$10382_Y + end + connect \$7 $not$libresoc.v:165544$10367_Y + connect \$12 $reduce_or$libresoc.v:165545$10368_Y + connect \$11 $not$libresoc.v:165546$10369_Y + connect \$16 $reduce_or$libresoc.v:165547$10370_Y + connect \$15 $not$libresoc.v:165548$10371_Y + connect \$1 $not$libresoc.v:165549$10372_Y + connect \$20 $reduce_or$libresoc.v:165550$10373_Y + connect \$19 $not$libresoc.v:165551$10374_Y + connect \$24 $reduce_or$libresoc.v:165552$10375_Y + connect \$23 $not$libresoc.v:165553$10376_Y + connect \$28 $reduce_or$libresoc.v:165554$10377_Y + connect \$27 $not$libresoc.v:165555$10378_Y + connect \$31 $reduce_or$libresoc.v:165556$10379_Y + connect \$4 $reduce_or$libresoc.v:165557$10380_Y + connect \$3 $not$libresoc.v:165558$10381_Y + connect \$8 $reduce_or$libresoc.v:165559$10382_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -333541,43 +341471,43 @@ module \ppick$181 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162150.1-162234.10" +attribute \src "libresoc.v:165575.1-165659.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$183 - attribute \src "libresoc.v:162207.17-162207.91" - wire $not$libresoc.v:162207$9985_Y - attribute \src "libresoc.v:162209.18-162209.93" - wire $not$libresoc.v:162209$9987_Y - attribute \src "libresoc.v:162211.18-162211.93" - wire $not$libresoc.v:162211$9989_Y - attribute \src "libresoc.v:162212.17-162212.138" - wire width 8 $not$libresoc.v:162212$9990_Y - attribute \src "libresoc.v:162214.18-162214.93" - wire $not$libresoc.v:162214$9992_Y - attribute \src "libresoc.v:162216.18-162216.93" - wire $not$libresoc.v:162216$9994_Y - attribute \src "libresoc.v:162218.18-162218.93" - wire $not$libresoc.v:162218$9996_Y - attribute \src "libresoc.v:162221.17-162221.91" - wire $not$libresoc.v:162221$9999_Y - attribute \src "libresoc.v:162208.18-162208.116" - wire $reduce_or$libresoc.v:162208$9986_Y - attribute \src "libresoc.v:162210.18-162210.122" - wire $reduce_or$libresoc.v:162210$9988_Y - attribute \src "libresoc.v:162213.18-162213.128" - wire $reduce_or$libresoc.v:162213$9991_Y - attribute \src "libresoc.v:162215.18-162215.134" - wire $reduce_or$libresoc.v:162215$9993_Y - attribute \src "libresoc.v:162217.18-162217.140" - wire $reduce_or$libresoc.v:162217$9995_Y - attribute \src "libresoc.v:162219.18-162219.90" - wire $reduce_or$libresoc.v:162219$9997_Y - attribute \src "libresoc.v:162220.17-162220.103" - wire $reduce_or$libresoc.v:162220$9998_Y - attribute \src "libresoc.v:162222.17-162222.109" - wire $reduce_or$libresoc.v:162222$10000_Y +module \ppick$186 + attribute \src "libresoc.v:165632.17-165632.91" + wire $not$libresoc.v:165632$10383_Y + attribute \src "libresoc.v:165634.18-165634.93" + wire $not$libresoc.v:165634$10385_Y + attribute \src "libresoc.v:165636.18-165636.93" + wire $not$libresoc.v:165636$10387_Y + attribute \src "libresoc.v:165637.17-165637.138" + wire width 8 $not$libresoc.v:165637$10388_Y + attribute \src "libresoc.v:165639.18-165639.93" + wire $not$libresoc.v:165639$10390_Y + attribute \src "libresoc.v:165641.18-165641.93" + wire $not$libresoc.v:165641$10392_Y + attribute \src "libresoc.v:165643.18-165643.93" + wire $not$libresoc.v:165643$10394_Y + attribute \src "libresoc.v:165646.17-165646.91" + wire $not$libresoc.v:165646$10397_Y + attribute \src "libresoc.v:165633.18-165633.116" + wire $reduce_or$libresoc.v:165633$10384_Y + attribute \src "libresoc.v:165635.18-165635.122" + wire $reduce_or$libresoc.v:165635$10386_Y + attribute \src "libresoc.v:165638.18-165638.128" + wire $reduce_or$libresoc.v:165638$10389_Y + attribute \src "libresoc.v:165640.18-165640.134" + wire $reduce_or$libresoc.v:165640$10391_Y + attribute \src "libresoc.v:165642.18-165642.140" + wire $reduce_or$libresoc.v:165642$10393_Y + attribute \src "libresoc.v:165644.18-165644.90" + wire $reduce_or$libresoc.v:165644$10395_Y + attribute \src "libresoc.v:165645.17-165645.103" + wire $reduce_or$libresoc.v:165645$10396_Y + attribute \src "libresoc.v:165647.17-165647.109" + wire $reduce_or$libresoc.v:165647$10398_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -333635,149 +341565,149 @@ module \ppick$183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162207$9985 + cell $not $not$libresoc.v:165632$10383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162207$9985_Y + connect \Y $not$libresoc.v:165632$10383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162209$9987 + cell $not $not$libresoc.v:165634$10385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162209$9987_Y + connect \Y $not$libresoc.v:165634$10385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162211$9989 + cell $not $not$libresoc.v:165636$10387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162211$9989_Y + connect \Y $not$libresoc.v:165636$10387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162212$9990 + cell $not $not$libresoc.v:165637$10388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162212$9990_Y + connect \Y $not$libresoc.v:165637$10388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162214$9992 + cell $not $not$libresoc.v:165639$10390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162214$9992_Y + connect \Y $not$libresoc.v:165639$10390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162216$9994 + cell $not $not$libresoc.v:165641$10392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162216$9994_Y + connect \Y $not$libresoc.v:165641$10392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162218$9996 + cell $not $not$libresoc.v:165643$10394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162218$9996_Y + connect \Y $not$libresoc.v:165643$10394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162221$9999 + cell $not $not$libresoc.v:165646$10397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162221$9999_Y + connect \Y $not$libresoc.v:165646$10397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162208$9986 + cell $reduce_or $reduce_or$libresoc.v:165633$10384 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162208$9986_Y + connect \Y $reduce_or$libresoc.v:165633$10384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162210$9988 + cell $reduce_or $reduce_or$libresoc.v:165635$10386 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162210$9988_Y + connect \Y $reduce_or$libresoc.v:165635$10386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162213$9991 + cell $reduce_or $reduce_or$libresoc.v:165638$10389 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162213$9991_Y + connect \Y $reduce_or$libresoc.v:165638$10389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162215$9993 + cell $reduce_or $reduce_or$libresoc.v:165640$10391 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162215$9993_Y + connect \Y $reduce_or$libresoc.v:165640$10391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162217$9995 + cell $reduce_or $reduce_or$libresoc.v:165642$10393 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162217$9995_Y + connect \Y $reduce_or$libresoc.v:165642$10393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162219$9997 + cell $reduce_or $reduce_or$libresoc.v:165644$10395 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162219$9997_Y + connect \Y $reduce_or$libresoc.v:165644$10395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162220$9998 + cell $reduce_or $reduce_or$libresoc.v:165645$10396 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162220$9998_Y + connect \Y $reduce_or$libresoc.v:165645$10396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162222$10000 + cell $reduce_or $reduce_or$libresoc.v:165647$10398 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162222$10000_Y - end - connect \$7 $not$libresoc.v:162207$9985_Y - connect \$12 $reduce_or$libresoc.v:162208$9986_Y - connect \$11 $not$libresoc.v:162209$9987_Y - connect \$16 $reduce_or$libresoc.v:162210$9988_Y - connect \$15 $not$libresoc.v:162211$9989_Y - connect \$1 $not$libresoc.v:162212$9990_Y - connect \$20 $reduce_or$libresoc.v:162213$9991_Y - connect \$19 $not$libresoc.v:162214$9992_Y - connect \$24 $reduce_or$libresoc.v:162215$9993_Y - connect \$23 $not$libresoc.v:162216$9994_Y - connect \$28 $reduce_or$libresoc.v:162217$9995_Y - connect \$27 $not$libresoc.v:162218$9996_Y - connect \$31 $reduce_or$libresoc.v:162219$9997_Y - connect \$4 $reduce_or$libresoc.v:162220$9998_Y - connect \$3 $not$libresoc.v:162221$9999_Y - connect \$8 $reduce_or$libresoc.v:162222$10000_Y + connect \Y $reduce_or$libresoc.v:165647$10398_Y + end + connect \$7 $not$libresoc.v:165632$10383_Y + connect \$12 $reduce_or$libresoc.v:165633$10384_Y + connect \$11 $not$libresoc.v:165634$10385_Y + connect \$16 $reduce_or$libresoc.v:165635$10386_Y + connect \$15 $not$libresoc.v:165636$10387_Y + connect \$1 $not$libresoc.v:165637$10388_Y + connect \$20 $reduce_or$libresoc.v:165638$10389_Y + connect \$19 $not$libresoc.v:165639$10390_Y + connect \$24 $reduce_or$libresoc.v:165640$10391_Y + connect \$23 $not$libresoc.v:165641$10392_Y + connect \$28 $reduce_or$libresoc.v:165642$10393_Y + connect \$27 $not$libresoc.v:165643$10394_Y + connect \$31 $reduce_or$libresoc.v:165644$10395_Y + connect \$4 $reduce_or$libresoc.v:165645$10396_Y + connect \$3 $not$libresoc.v:165646$10397_Y + connect \$8 $reduce_or$libresoc.v:165647$10398_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -333790,43 +341720,43 @@ module \ppick$183 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162238.1-162322.10" +attribute \src "libresoc.v:165663.1-165747.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$189 - attribute \src "libresoc.v:162295.17-162295.91" - wire $not$libresoc.v:162295$10001_Y - attribute \src "libresoc.v:162297.18-162297.93" - wire $not$libresoc.v:162297$10003_Y - attribute \src "libresoc.v:162299.18-162299.93" - wire $not$libresoc.v:162299$10005_Y - attribute \src "libresoc.v:162300.17-162300.138" - wire width 8 $not$libresoc.v:162300$10006_Y - attribute \src "libresoc.v:162302.18-162302.93" - wire $not$libresoc.v:162302$10008_Y - attribute \src "libresoc.v:162304.18-162304.93" - wire $not$libresoc.v:162304$10010_Y - attribute \src "libresoc.v:162306.18-162306.93" - wire $not$libresoc.v:162306$10012_Y - attribute \src "libresoc.v:162309.17-162309.91" - wire $not$libresoc.v:162309$10015_Y - attribute \src "libresoc.v:162296.18-162296.116" - wire $reduce_or$libresoc.v:162296$10002_Y - attribute \src "libresoc.v:162298.18-162298.122" - wire $reduce_or$libresoc.v:162298$10004_Y - attribute \src "libresoc.v:162301.18-162301.128" - wire $reduce_or$libresoc.v:162301$10007_Y - attribute \src "libresoc.v:162303.18-162303.134" - wire $reduce_or$libresoc.v:162303$10009_Y - attribute \src "libresoc.v:162305.18-162305.140" - wire $reduce_or$libresoc.v:162305$10011_Y - attribute \src "libresoc.v:162307.18-162307.90" - wire $reduce_or$libresoc.v:162307$10013_Y - attribute \src "libresoc.v:162308.17-162308.103" - wire $reduce_or$libresoc.v:162308$10014_Y - attribute \src "libresoc.v:162310.17-162310.109" - wire $reduce_or$libresoc.v:162310$10016_Y +module \ppick$192 + attribute \src "libresoc.v:165720.17-165720.91" + wire $not$libresoc.v:165720$10399_Y + attribute \src "libresoc.v:165722.18-165722.93" + wire $not$libresoc.v:165722$10401_Y + attribute \src "libresoc.v:165724.18-165724.93" + wire $not$libresoc.v:165724$10403_Y + attribute \src "libresoc.v:165725.17-165725.138" + wire width 8 $not$libresoc.v:165725$10404_Y + attribute \src "libresoc.v:165727.18-165727.93" + wire $not$libresoc.v:165727$10406_Y + attribute \src "libresoc.v:165729.18-165729.93" + wire $not$libresoc.v:165729$10408_Y + attribute \src "libresoc.v:165731.18-165731.93" + wire $not$libresoc.v:165731$10410_Y + attribute \src "libresoc.v:165734.17-165734.91" + wire $not$libresoc.v:165734$10413_Y + attribute \src "libresoc.v:165721.18-165721.116" + wire $reduce_or$libresoc.v:165721$10400_Y + attribute \src "libresoc.v:165723.18-165723.122" + wire $reduce_or$libresoc.v:165723$10402_Y + attribute \src "libresoc.v:165726.18-165726.128" + wire $reduce_or$libresoc.v:165726$10405_Y + attribute \src "libresoc.v:165728.18-165728.134" + wire $reduce_or$libresoc.v:165728$10407_Y + attribute \src "libresoc.v:165730.18-165730.140" + wire $reduce_or$libresoc.v:165730$10409_Y + attribute \src "libresoc.v:165732.18-165732.90" + wire $reduce_or$libresoc.v:165732$10411_Y + attribute \src "libresoc.v:165733.17-165733.103" + wire $reduce_or$libresoc.v:165733$10412_Y + attribute \src "libresoc.v:165735.17-165735.109" + wire $reduce_or$libresoc.v:165735$10414_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -333884,149 +341814,149 @@ module \ppick$189 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162295$10001 + cell $not $not$libresoc.v:165720$10399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162295$10001_Y + connect \Y $not$libresoc.v:165720$10399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162297$10003 + cell $not $not$libresoc.v:165722$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162297$10003_Y + connect \Y $not$libresoc.v:165722$10401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162299$10005 + cell $not $not$libresoc.v:165724$10403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162299$10005_Y + connect \Y $not$libresoc.v:165724$10403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162300$10006 + cell $not $not$libresoc.v:165725$10404 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162300$10006_Y + connect \Y $not$libresoc.v:165725$10404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162302$10008 + cell $not $not$libresoc.v:165727$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162302$10008_Y + connect \Y $not$libresoc.v:165727$10406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162304$10010 + cell $not $not$libresoc.v:165729$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162304$10010_Y + connect \Y $not$libresoc.v:165729$10408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162306$10012 + cell $not $not$libresoc.v:165731$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162306$10012_Y + connect \Y $not$libresoc.v:165731$10410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162309$10015 + cell $not $not$libresoc.v:165734$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162309$10015_Y + connect \Y $not$libresoc.v:165734$10413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162296$10002 + cell $reduce_or $reduce_or$libresoc.v:165721$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162296$10002_Y + connect \Y $reduce_or$libresoc.v:165721$10400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162298$10004 + cell $reduce_or $reduce_or$libresoc.v:165723$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162298$10004_Y + connect \Y $reduce_or$libresoc.v:165723$10402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162301$10007 + cell $reduce_or $reduce_or$libresoc.v:165726$10405 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162301$10007_Y + connect \Y $reduce_or$libresoc.v:165726$10405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162303$10009 + cell $reduce_or $reduce_or$libresoc.v:165728$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162303$10009_Y + connect \Y $reduce_or$libresoc.v:165728$10407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162305$10011 + cell $reduce_or $reduce_or$libresoc.v:165730$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162305$10011_Y + connect \Y $reduce_or$libresoc.v:165730$10409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162307$10013 + cell $reduce_or $reduce_or$libresoc.v:165732$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162307$10013_Y + connect \Y $reduce_or$libresoc.v:165732$10411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162308$10014 + cell $reduce_or $reduce_or$libresoc.v:165733$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162308$10014_Y + connect \Y $reduce_or$libresoc.v:165733$10412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162310$10016 + cell $reduce_or $reduce_or$libresoc.v:165735$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162310$10016_Y - end - connect \$7 $not$libresoc.v:162295$10001_Y - connect \$12 $reduce_or$libresoc.v:162296$10002_Y - connect \$11 $not$libresoc.v:162297$10003_Y - connect \$16 $reduce_or$libresoc.v:162298$10004_Y - connect \$15 $not$libresoc.v:162299$10005_Y - connect \$1 $not$libresoc.v:162300$10006_Y - connect \$20 $reduce_or$libresoc.v:162301$10007_Y - connect \$19 $not$libresoc.v:162302$10008_Y - connect \$24 $reduce_or$libresoc.v:162303$10009_Y - connect \$23 $not$libresoc.v:162304$10010_Y - connect \$28 $reduce_or$libresoc.v:162305$10011_Y - connect \$27 $not$libresoc.v:162306$10012_Y - connect \$31 $reduce_or$libresoc.v:162307$10013_Y - connect \$4 $reduce_or$libresoc.v:162308$10014_Y - connect \$3 $not$libresoc.v:162309$10015_Y - connect \$8 $reduce_or$libresoc.v:162310$10016_Y + connect \Y $reduce_or$libresoc.v:165735$10414_Y + end + connect \$7 $not$libresoc.v:165720$10399_Y + connect \$12 $reduce_or$libresoc.v:165721$10400_Y + connect \$11 $not$libresoc.v:165722$10401_Y + connect \$16 $reduce_or$libresoc.v:165723$10402_Y + connect \$15 $not$libresoc.v:165724$10403_Y + connect \$1 $not$libresoc.v:165725$10404_Y + connect \$20 $reduce_or$libresoc.v:165726$10405_Y + connect \$19 $not$libresoc.v:165727$10406_Y + connect \$24 $reduce_or$libresoc.v:165728$10407_Y + connect \$23 $not$libresoc.v:165729$10408_Y + connect \$28 $reduce_or$libresoc.v:165730$10409_Y + connect \$27 $not$libresoc.v:165731$10410_Y + connect \$31 $reduce_or$libresoc.v:165732$10411_Y + connect \$4 $reduce_or$libresoc.v:165733$10412_Y + connect \$3 $not$libresoc.v:165734$10413_Y + connect \$8 $reduce_or$libresoc.v:165735$10414_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -334039,43 +341969,43 @@ module \ppick$189 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162326.1-162410.10" +attribute \src "libresoc.v:165751.1-165835.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$191 - attribute \src "libresoc.v:162383.17-162383.91" - wire $not$libresoc.v:162383$10017_Y - attribute \src "libresoc.v:162385.18-162385.93" - wire $not$libresoc.v:162385$10019_Y - attribute \src "libresoc.v:162387.18-162387.93" - wire $not$libresoc.v:162387$10021_Y - attribute \src "libresoc.v:162388.17-162388.138" - wire width 8 $not$libresoc.v:162388$10022_Y - attribute \src "libresoc.v:162390.18-162390.93" - wire $not$libresoc.v:162390$10024_Y - attribute \src "libresoc.v:162392.18-162392.93" - wire $not$libresoc.v:162392$10026_Y - attribute \src "libresoc.v:162394.18-162394.93" - wire $not$libresoc.v:162394$10028_Y - attribute \src "libresoc.v:162397.17-162397.91" - wire $not$libresoc.v:162397$10031_Y - attribute \src "libresoc.v:162384.18-162384.116" - wire $reduce_or$libresoc.v:162384$10018_Y - attribute \src "libresoc.v:162386.18-162386.122" - wire $reduce_or$libresoc.v:162386$10020_Y - attribute \src "libresoc.v:162389.18-162389.128" - wire $reduce_or$libresoc.v:162389$10023_Y - attribute \src "libresoc.v:162391.18-162391.134" - wire $reduce_or$libresoc.v:162391$10025_Y - attribute \src "libresoc.v:162393.18-162393.140" - wire $reduce_or$libresoc.v:162393$10027_Y - attribute \src "libresoc.v:162395.18-162395.90" - wire $reduce_or$libresoc.v:162395$10029_Y - attribute \src "libresoc.v:162396.17-162396.103" - wire $reduce_or$libresoc.v:162396$10030_Y - attribute \src "libresoc.v:162398.17-162398.109" - wire $reduce_or$libresoc.v:162398$10032_Y +module \ppick$194 + attribute \src "libresoc.v:165808.17-165808.91" + wire $not$libresoc.v:165808$10415_Y + attribute \src "libresoc.v:165810.18-165810.93" + wire $not$libresoc.v:165810$10417_Y + attribute \src "libresoc.v:165812.18-165812.93" + wire $not$libresoc.v:165812$10419_Y + attribute \src "libresoc.v:165813.17-165813.138" + wire width 8 $not$libresoc.v:165813$10420_Y + attribute \src "libresoc.v:165815.18-165815.93" + wire $not$libresoc.v:165815$10422_Y + attribute \src "libresoc.v:165817.18-165817.93" + wire $not$libresoc.v:165817$10424_Y + attribute \src "libresoc.v:165819.18-165819.93" + wire $not$libresoc.v:165819$10426_Y + attribute \src "libresoc.v:165822.17-165822.91" + wire $not$libresoc.v:165822$10429_Y + attribute \src "libresoc.v:165809.18-165809.116" + wire $reduce_or$libresoc.v:165809$10416_Y + attribute \src "libresoc.v:165811.18-165811.122" + wire $reduce_or$libresoc.v:165811$10418_Y + attribute \src "libresoc.v:165814.18-165814.128" + wire $reduce_or$libresoc.v:165814$10421_Y + attribute \src "libresoc.v:165816.18-165816.134" + wire $reduce_or$libresoc.v:165816$10423_Y + attribute \src "libresoc.v:165818.18-165818.140" + wire $reduce_or$libresoc.v:165818$10425_Y + attribute \src "libresoc.v:165820.18-165820.90" + wire $reduce_or$libresoc.v:165820$10427_Y + attribute \src "libresoc.v:165821.17-165821.103" + wire $reduce_or$libresoc.v:165821$10428_Y + attribute \src "libresoc.v:165823.17-165823.109" + wire $reduce_or$libresoc.v:165823$10430_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -334133,149 +342063,149 @@ module \ppick$191 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162383$10017 + cell $not $not$libresoc.v:165808$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162383$10017_Y + connect \Y $not$libresoc.v:165808$10415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162385$10019 + cell $not $not$libresoc.v:165810$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162385$10019_Y + connect \Y $not$libresoc.v:165810$10417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162387$10021 + cell $not $not$libresoc.v:165812$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162387$10021_Y + connect \Y $not$libresoc.v:165812$10419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162388$10022 + cell $not $not$libresoc.v:165813$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162388$10022_Y + connect \Y $not$libresoc.v:165813$10420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162390$10024 + cell $not $not$libresoc.v:165815$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162390$10024_Y + connect \Y $not$libresoc.v:165815$10422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162392$10026 + cell $not $not$libresoc.v:165817$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162392$10026_Y + connect \Y $not$libresoc.v:165817$10424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162394$10028 + cell $not $not$libresoc.v:165819$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162394$10028_Y + connect \Y $not$libresoc.v:165819$10426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162397$10031 + cell $not $not$libresoc.v:165822$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162397$10031_Y + connect \Y $not$libresoc.v:165822$10429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162384$10018 + cell $reduce_or $reduce_or$libresoc.v:165809$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162384$10018_Y + connect \Y $reduce_or$libresoc.v:165809$10416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162386$10020 + cell $reduce_or $reduce_or$libresoc.v:165811$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162386$10020_Y + connect \Y $reduce_or$libresoc.v:165811$10418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162389$10023 + cell $reduce_or $reduce_or$libresoc.v:165814$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162389$10023_Y + connect \Y $reduce_or$libresoc.v:165814$10421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162391$10025 + cell $reduce_or $reduce_or$libresoc.v:165816$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162391$10025_Y + connect \Y $reduce_or$libresoc.v:165816$10423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162393$10027 + cell $reduce_or $reduce_or$libresoc.v:165818$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162393$10027_Y + connect \Y $reduce_or$libresoc.v:165818$10425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162395$10029 + cell $reduce_or $reduce_or$libresoc.v:165820$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162395$10029_Y + connect \Y $reduce_or$libresoc.v:165820$10427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162396$10030 + cell $reduce_or $reduce_or$libresoc.v:165821$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162396$10030_Y + connect \Y $reduce_or$libresoc.v:165821$10428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162398$10032 + cell $reduce_or $reduce_or$libresoc.v:165823$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162398$10032_Y - end - connect \$7 $not$libresoc.v:162383$10017_Y - connect \$12 $reduce_or$libresoc.v:162384$10018_Y - connect \$11 $not$libresoc.v:162385$10019_Y - connect \$16 $reduce_or$libresoc.v:162386$10020_Y - connect \$15 $not$libresoc.v:162387$10021_Y - connect \$1 $not$libresoc.v:162388$10022_Y - connect \$20 $reduce_or$libresoc.v:162389$10023_Y - connect \$19 $not$libresoc.v:162390$10024_Y - connect \$24 $reduce_or$libresoc.v:162391$10025_Y - connect \$23 $not$libresoc.v:162392$10026_Y - connect \$28 $reduce_or$libresoc.v:162393$10027_Y - connect \$27 $not$libresoc.v:162394$10028_Y - connect \$31 $reduce_or$libresoc.v:162395$10029_Y - connect \$4 $reduce_or$libresoc.v:162396$10030_Y - connect \$3 $not$libresoc.v:162397$10031_Y - connect \$8 $reduce_or$libresoc.v:162398$10032_Y + connect \Y $reduce_or$libresoc.v:165823$10430_Y + end + connect \$7 $not$libresoc.v:165808$10415_Y + connect \$12 $reduce_or$libresoc.v:165809$10416_Y + connect \$11 $not$libresoc.v:165810$10417_Y + connect \$16 $reduce_or$libresoc.v:165811$10418_Y + connect \$15 $not$libresoc.v:165812$10419_Y + connect \$1 $not$libresoc.v:165813$10420_Y + connect \$20 $reduce_or$libresoc.v:165814$10421_Y + connect \$19 $not$libresoc.v:165815$10422_Y + connect \$24 $reduce_or$libresoc.v:165816$10423_Y + connect \$23 $not$libresoc.v:165817$10424_Y + connect \$28 $reduce_or$libresoc.v:165818$10425_Y + connect \$27 $not$libresoc.v:165819$10426_Y + connect \$31 $reduce_or$libresoc.v:165820$10427_Y + connect \$4 $reduce_or$libresoc.v:165821$10428_Y + connect \$3 $not$libresoc.v:165822$10429_Y + connect \$8 $reduce_or$libresoc.v:165823$10430_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -334288,43 +342218,43 @@ module \ppick$191 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162414.1-162498.10" +attribute \src "libresoc.v:165839.1-165923.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$197 - attribute \src "libresoc.v:162471.17-162471.91" - wire $not$libresoc.v:162471$10033_Y - attribute \src "libresoc.v:162473.18-162473.93" - wire $not$libresoc.v:162473$10035_Y - attribute \src "libresoc.v:162475.18-162475.93" - wire $not$libresoc.v:162475$10037_Y - attribute \src "libresoc.v:162476.17-162476.138" - wire width 8 $not$libresoc.v:162476$10038_Y - attribute \src "libresoc.v:162478.18-162478.93" - wire $not$libresoc.v:162478$10040_Y - attribute \src "libresoc.v:162480.18-162480.93" - wire $not$libresoc.v:162480$10042_Y - attribute \src "libresoc.v:162482.18-162482.93" - wire $not$libresoc.v:162482$10044_Y - attribute \src "libresoc.v:162485.17-162485.91" - wire $not$libresoc.v:162485$10047_Y - attribute \src "libresoc.v:162472.18-162472.116" - wire $reduce_or$libresoc.v:162472$10034_Y - attribute \src "libresoc.v:162474.18-162474.122" - wire $reduce_or$libresoc.v:162474$10036_Y - attribute \src "libresoc.v:162477.18-162477.128" - wire $reduce_or$libresoc.v:162477$10039_Y - attribute \src "libresoc.v:162479.18-162479.134" - wire $reduce_or$libresoc.v:162479$10041_Y - attribute \src "libresoc.v:162481.18-162481.140" - wire $reduce_or$libresoc.v:162481$10043_Y - attribute \src "libresoc.v:162483.18-162483.90" - wire $reduce_or$libresoc.v:162483$10045_Y - attribute \src "libresoc.v:162484.17-162484.103" - wire $reduce_or$libresoc.v:162484$10046_Y - attribute \src "libresoc.v:162486.17-162486.109" - wire $reduce_or$libresoc.v:162486$10048_Y +module \ppick$200 + attribute \src "libresoc.v:165896.17-165896.91" + wire $not$libresoc.v:165896$10431_Y + attribute \src "libresoc.v:165898.18-165898.93" + wire $not$libresoc.v:165898$10433_Y + attribute \src "libresoc.v:165900.18-165900.93" + wire $not$libresoc.v:165900$10435_Y + attribute \src "libresoc.v:165901.17-165901.138" + wire width 8 $not$libresoc.v:165901$10436_Y + attribute \src "libresoc.v:165903.18-165903.93" + wire $not$libresoc.v:165903$10438_Y + attribute \src "libresoc.v:165905.18-165905.93" + wire $not$libresoc.v:165905$10440_Y + attribute \src "libresoc.v:165907.18-165907.93" + wire $not$libresoc.v:165907$10442_Y + attribute \src "libresoc.v:165910.17-165910.91" + wire $not$libresoc.v:165910$10445_Y + attribute \src "libresoc.v:165897.18-165897.116" + wire $reduce_or$libresoc.v:165897$10432_Y + attribute \src "libresoc.v:165899.18-165899.122" + wire $reduce_or$libresoc.v:165899$10434_Y + attribute \src "libresoc.v:165902.18-165902.128" + wire $reduce_or$libresoc.v:165902$10437_Y + attribute \src "libresoc.v:165904.18-165904.134" + wire $reduce_or$libresoc.v:165904$10439_Y + attribute \src "libresoc.v:165906.18-165906.140" + wire $reduce_or$libresoc.v:165906$10441_Y + attribute \src "libresoc.v:165908.18-165908.90" + wire $reduce_or$libresoc.v:165908$10443_Y + attribute \src "libresoc.v:165909.17-165909.103" + wire $reduce_or$libresoc.v:165909$10444_Y + attribute \src "libresoc.v:165911.17-165911.109" + wire $reduce_or$libresoc.v:165911$10446_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -334382,149 +342312,149 @@ module \ppick$197 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162471$10033 + cell $not $not$libresoc.v:165896$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162471$10033_Y + connect \Y $not$libresoc.v:165896$10431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162473$10035 + cell $not $not$libresoc.v:165898$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162473$10035_Y + connect \Y $not$libresoc.v:165898$10433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162475$10037 + cell $not $not$libresoc.v:165900$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162475$10037_Y + connect \Y $not$libresoc.v:165900$10435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162476$10038 + cell $not $not$libresoc.v:165901$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162476$10038_Y + connect \Y $not$libresoc.v:165901$10436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162478$10040 + cell $not $not$libresoc.v:165903$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162478$10040_Y + connect \Y $not$libresoc.v:165903$10438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162480$10042 + cell $not $not$libresoc.v:165905$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162480$10042_Y + connect \Y $not$libresoc.v:165905$10440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162482$10044 + cell $not $not$libresoc.v:165907$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162482$10044_Y + connect \Y $not$libresoc.v:165907$10442_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162485$10047 + cell $not $not$libresoc.v:165910$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162485$10047_Y + connect \Y $not$libresoc.v:165910$10445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162472$10034 + cell $reduce_or $reduce_or$libresoc.v:165897$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162472$10034_Y + connect \Y $reduce_or$libresoc.v:165897$10432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162474$10036 + cell $reduce_or $reduce_or$libresoc.v:165899$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162474$10036_Y + connect \Y $reduce_or$libresoc.v:165899$10434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162477$10039 + cell $reduce_or $reduce_or$libresoc.v:165902$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162477$10039_Y + connect \Y $reduce_or$libresoc.v:165902$10437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162479$10041 + cell $reduce_or $reduce_or$libresoc.v:165904$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162479$10041_Y + connect \Y $reduce_or$libresoc.v:165904$10439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162481$10043 + cell $reduce_or $reduce_or$libresoc.v:165906$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162481$10043_Y + connect \Y $reduce_or$libresoc.v:165906$10441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162483$10045 + cell $reduce_or $reduce_or$libresoc.v:165908$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162483$10045_Y + connect \Y $reduce_or$libresoc.v:165908$10443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162484$10046 + cell $reduce_or $reduce_or$libresoc.v:165909$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162484$10046_Y + connect \Y $reduce_or$libresoc.v:165909$10444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162486$10048 + cell $reduce_or $reduce_or$libresoc.v:165911$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162486$10048_Y - end - connect \$7 $not$libresoc.v:162471$10033_Y - connect \$12 $reduce_or$libresoc.v:162472$10034_Y - connect \$11 $not$libresoc.v:162473$10035_Y - connect \$16 $reduce_or$libresoc.v:162474$10036_Y - connect \$15 $not$libresoc.v:162475$10037_Y - connect \$1 $not$libresoc.v:162476$10038_Y - connect \$20 $reduce_or$libresoc.v:162477$10039_Y - connect \$19 $not$libresoc.v:162478$10040_Y - connect \$24 $reduce_or$libresoc.v:162479$10041_Y - connect \$23 $not$libresoc.v:162480$10042_Y - connect \$28 $reduce_or$libresoc.v:162481$10043_Y - connect \$27 $not$libresoc.v:162482$10044_Y - connect \$31 $reduce_or$libresoc.v:162483$10045_Y - connect \$4 $reduce_or$libresoc.v:162484$10046_Y - connect \$3 $not$libresoc.v:162485$10047_Y - connect \$8 $reduce_or$libresoc.v:162486$10048_Y + connect \Y $reduce_or$libresoc.v:165911$10446_Y + end + connect \$7 $not$libresoc.v:165896$10431_Y + connect \$12 $reduce_or$libresoc.v:165897$10432_Y + connect \$11 $not$libresoc.v:165898$10433_Y + connect \$16 $reduce_or$libresoc.v:165899$10434_Y + connect \$15 $not$libresoc.v:165900$10435_Y + connect \$1 $not$libresoc.v:165901$10436_Y + connect \$20 $reduce_or$libresoc.v:165902$10437_Y + connect \$19 $not$libresoc.v:165903$10438_Y + connect \$24 $reduce_or$libresoc.v:165904$10439_Y + connect \$23 $not$libresoc.v:165905$10440_Y + connect \$28 $reduce_or$libresoc.v:165906$10441_Y + connect \$27 $not$libresoc.v:165907$10442_Y + connect \$31 $reduce_or$libresoc.v:165908$10443_Y + connect \$4 $reduce_or$libresoc.v:165909$10444_Y + connect \$3 $not$libresoc.v:165910$10445_Y + connect \$8 $reduce_or$libresoc.v:165911$10446_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -334537,43 +342467,43 @@ module \ppick$197 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162502.1-162586.10" +attribute \src "libresoc.v:165927.1-166011.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$199 - attribute \src "libresoc.v:162559.17-162559.91" - wire $not$libresoc.v:162559$10049_Y - attribute \src "libresoc.v:162561.18-162561.93" - wire $not$libresoc.v:162561$10051_Y - attribute \src "libresoc.v:162563.18-162563.93" - wire $not$libresoc.v:162563$10053_Y - attribute \src "libresoc.v:162564.17-162564.138" - wire width 8 $not$libresoc.v:162564$10054_Y - attribute \src "libresoc.v:162566.18-162566.93" - wire $not$libresoc.v:162566$10056_Y - attribute \src "libresoc.v:162568.18-162568.93" - wire $not$libresoc.v:162568$10058_Y - attribute \src "libresoc.v:162570.18-162570.93" - wire $not$libresoc.v:162570$10060_Y - attribute \src "libresoc.v:162573.17-162573.91" - wire $not$libresoc.v:162573$10063_Y - attribute \src "libresoc.v:162560.18-162560.116" - wire $reduce_or$libresoc.v:162560$10050_Y - attribute \src "libresoc.v:162562.18-162562.122" - wire $reduce_or$libresoc.v:162562$10052_Y - attribute \src "libresoc.v:162565.18-162565.128" - wire $reduce_or$libresoc.v:162565$10055_Y - attribute \src "libresoc.v:162567.18-162567.134" - wire $reduce_or$libresoc.v:162567$10057_Y - attribute \src "libresoc.v:162569.18-162569.140" - wire $reduce_or$libresoc.v:162569$10059_Y - attribute \src "libresoc.v:162571.18-162571.90" - wire $reduce_or$libresoc.v:162571$10061_Y - attribute \src "libresoc.v:162572.17-162572.103" - wire $reduce_or$libresoc.v:162572$10062_Y - attribute \src "libresoc.v:162574.17-162574.109" - wire $reduce_or$libresoc.v:162574$10064_Y +module \ppick$202 + attribute \src "libresoc.v:165984.17-165984.91" + wire $not$libresoc.v:165984$10447_Y + attribute \src "libresoc.v:165986.18-165986.93" + wire $not$libresoc.v:165986$10449_Y + attribute \src "libresoc.v:165988.18-165988.93" + wire $not$libresoc.v:165988$10451_Y + attribute \src "libresoc.v:165989.17-165989.138" + wire width 8 $not$libresoc.v:165989$10452_Y + attribute \src "libresoc.v:165991.18-165991.93" + wire $not$libresoc.v:165991$10454_Y + attribute \src "libresoc.v:165993.18-165993.93" + wire $not$libresoc.v:165993$10456_Y + attribute \src "libresoc.v:165995.18-165995.93" + wire $not$libresoc.v:165995$10458_Y + attribute \src "libresoc.v:165998.17-165998.91" + wire $not$libresoc.v:165998$10461_Y + attribute \src "libresoc.v:165985.18-165985.116" + wire $reduce_or$libresoc.v:165985$10448_Y + attribute \src "libresoc.v:165987.18-165987.122" + wire $reduce_or$libresoc.v:165987$10450_Y + attribute \src "libresoc.v:165990.18-165990.128" + wire $reduce_or$libresoc.v:165990$10453_Y + attribute \src "libresoc.v:165992.18-165992.134" + wire $reduce_or$libresoc.v:165992$10455_Y + attribute \src "libresoc.v:165994.18-165994.140" + wire $reduce_or$libresoc.v:165994$10457_Y + attribute \src "libresoc.v:165996.18-165996.90" + wire $reduce_or$libresoc.v:165996$10459_Y + attribute \src "libresoc.v:165997.17-165997.103" + wire $reduce_or$libresoc.v:165997$10460_Y + attribute \src "libresoc.v:165999.17-165999.109" + wire $reduce_or$libresoc.v:165999$10462_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -334631,149 +342561,149 @@ module \ppick$199 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162559$10049 + cell $not $not$libresoc.v:165984$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162559$10049_Y + connect \Y $not$libresoc.v:165984$10447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162561$10051 + cell $not $not$libresoc.v:165986$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162561$10051_Y + connect \Y $not$libresoc.v:165986$10449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162563$10053 + cell $not $not$libresoc.v:165988$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162563$10053_Y + connect \Y $not$libresoc.v:165988$10451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162564$10054 + cell $not $not$libresoc.v:165989$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162564$10054_Y + connect \Y $not$libresoc.v:165989$10452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162566$10056 + cell $not $not$libresoc.v:165991$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162566$10056_Y + connect \Y $not$libresoc.v:165991$10454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162568$10058 + cell $not $not$libresoc.v:165993$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162568$10058_Y + connect \Y $not$libresoc.v:165993$10456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162570$10060 + cell $not $not$libresoc.v:165995$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162570$10060_Y + connect \Y $not$libresoc.v:165995$10458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162573$10063 + cell $not $not$libresoc.v:165998$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162573$10063_Y + connect \Y $not$libresoc.v:165998$10461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162560$10050 + cell $reduce_or $reduce_or$libresoc.v:165985$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162560$10050_Y + connect \Y $reduce_or$libresoc.v:165985$10448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162562$10052 + cell $reduce_or $reduce_or$libresoc.v:165987$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162562$10052_Y + connect \Y $reduce_or$libresoc.v:165987$10450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162565$10055 + cell $reduce_or $reduce_or$libresoc.v:165990$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162565$10055_Y + connect \Y $reduce_or$libresoc.v:165990$10453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162567$10057 + cell $reduce_or $reduce_or$libresoc.v:165992$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162567$10057_Y + connect \Y $reduce_or$libresoc.v:165992$10455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162569$10059 + cell $reduce_or $reduce_or$libresoc.v:165994$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162569$10059_Y + connect \Y $reduce_or$libresoc.v:165994$10457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162571$10061 + cell $reduce_or $reduce_or$libresoc.v:165996$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162571$10061_Y + connect \Y $reduce_or$libresoc.v:165996$10459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162572$10062 + cell $reduce_or $reduce_or$libresoc.v:165997$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162572$10062_Y + connect \Y $reduce_or$libresoc.v:165997$10460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162574$10064 + cell $reduce_or $reduce_or$libresoc.v:165999$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162574$10064_Y - end - connect \$7 $not$libresoc.v:162559$10049_Y - connect \$12 $reduce_or$libresoc.v:162560$10050_Y - connect \$11 $not$libresoc.v:162561$10051_Y - connect \$16 $reduce_or$libresoc.v:162562$10052_Y - connect \$15 $not$libresoc.v:162563$10053_Y - connect \$1 $not$libresoc.v:162564$10054_Y - connect \$20 $reduce_or$libresoc.v:162565$10055_Y - connect \$19 $not$libresoc.v:162566$10056_Y - connect \$24 $reduce_or$libresoc.v:162567$10057_Y - connect \$23 $not$libresoc.v:162568$10058_Y - connect \$28 $reduce_or$libresoc.v:162569$10059_Y - connect \$27 $not$libresoc.v:162570$10060_Y - connect \$31 $reduce_or$libresoc.v:162571$10061_Y - connect \$4 $reduce_or$libresoc.v:162572$10062_Y - connect \$3 $not$libresoc.v:162573$10063_Y - connect \$8 $reduce_or$libresoc.v:162574$10064_Y + connect \Y $reduce_or$libresoc.v:165999$10462_Y + end + connect \$7 $not$libresoc.v:165984$10447_Y + connect \$12 $reduce_or$libresoc.v:165985$10448_Y + connect \$11 $not$libresoc.v:165986$10449_Y + connect \$16 $reduce_or$libresoc.v:165987$10450_Y + connect \$15 $not$libresoc.v:165988$10451_Y + connect \$1 $not$libresoc.v:165989$10452_Y + connect \$20 $reduce_or$libresoc.v:165990$10453_Y + connect \$19 $not$libresoc.v:165991$10454_Y + connect \$24 $reduce_or$libresoc.v:165992$10455_Y + connect \$23 $not$libresoc.v:165993$10456_Y + connect \$28 $reduce_or$libresoc.v:165994$10457_Y + connect \$27 $not$libresoc.v:165995$10458_Y + connect \$31 $reduce_or$libresoc.v:165996$10459_Y + connect \$4 $reduce_or$libresoc.v:165997$10460_Y + connect \$3 $not$libresoc.v:165998$10461_Y + connect \$8 $reduce_or$libresoc.v:165999$10462_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -334786,43 +342716,43 @@ module \ppick$199 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162590.1-162674.10" +attribute \src "libresoc.v:166015.1-166099.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$206 - attribute \src "libresoc.v:162647.17-162647.91" - wire $not$libresoc.v:162647$10065_Y - attribute \src "libresoc.v:162649.18-162649.93" - wire $not$libresoc.v:162649$10067_Y - attribute \src "libresoc.v:162651.18-162651.93" - wire $not$libresoc.v:162651$10069_Y - attribute \src "libresoc.v:162652.17-162652.138" - wire width 8 $not$libresoc.v:162652$10070_Y - attribute \src "libresoc.v:162654.18-162654.93" - wire $not$libresoc.v:162654$10072_Y - attribute \src "libresoc.v:162656.18-162656.93" - wire $not$libresoc.v:162656$10074_Y - attribute \src "libresoc.v:162658.18-162658.93" - wire $not$libresoc.v:162658$10076_Y - attribute \src "libresoc.v:162661.17-162661.91" - wire $not$libresoc.v:162661$10079_Y - attribute \src "libresoc.v:162648.18-162648.116" - wire $reduce_or$libresoc.v:162648$10066_Y - attribute \src "libresoc.v:162650.18-162650.122" - wire $reduce_or$libresoc.v:162650$10068_Y - attribute \src "libresoc.v:162653.18-162653.128" - wire $reduce_or$libresoc.v:162653$10071_Y - attribute \src "libresoc.v:162655.18-162655.134" - wire $reduce_or$libresoc.v:162655$10073_Y - attribute \src "libresoc.v:162657.18-162657.140" - wire $reduce_or$libresoc.v:162657$10075_Y - attribute \src "libresoc.v:162659.18-162659.90" - wire $reduce_or$libresoc.v:162659$10077_Y - attribute \src "libresoc.v:162660.17-162660.103" - wire $reduce_or$libresoc.v:162660$10078_Y - attribute \src "libresoc.v:162662.17-162662.109" - wire $reduce_or$libresoc.v:162662$10080_Y +module \ppick$209 + attribute \src "libresoc.v:166072.17-166072.91" + wire $not$libresoc.v:166072$10463_Y + attribute \src "libresoc.v:166074.18-166074.93" + wire $not$libresoc.v:166074$10465_Y + attribute \src "libresoc.v:166076.18-166076.93" + wire $not$libresoc.v:166076$10467_Y + attribute \src "libresoc.v:166077.17-166077.138" + wire width 8 $not$libresoc.v:166077$10468_Y + attribute \src "libresoc.v:166079.18-166079.93" + wire $not$libresoc.v:166079$10470_Y + attribute \src "libresoc.v:166081.18-166081.93" + wire $not$libresoc.v:166081$10472_Y + attribute \src "libresoc.v:166083.18-166083.93" + wire $not$libresoc.v:166083$10474_Y + attribute \src "libresoc.v:166086.17-166086.91" + wire $not$libresoc.v:166086$10477_Y + attribute \src "libresoc.v:166073.18-166073.116" + wire $reduce_or$libresoc.v:166073$10464_Y + attribute \src "libresoc.v:166075.18-166075.122" + wire $reduce_or$libresoc.v:166075$10466_Y + attribute \src "libresoc.v:166078.18-166078.128" + wire $reduce_or$libresoc.v:166078$10469_Y + attribute \src "libresoc.v:166080.18-166080.134" + wire $reduce_or$libresoc.v:166080$10471_Y + attribute \src "libresoc.v:166082.18-166082.140" + wire $reduce_or$libresoc.v:166082$10473_Y + attribute \src "libresoc.v:166084.18-166084.90" + wire $reduce_or$libresoc.v:166084$10475_Y + attribute \src "libresoc.v:166085.17-166085.103" + wire $reduce_or$libresoc.v:166085$10476_Y + attribute \src "libresoc.v:166087.17-166087.109" + wire $reduce_or$libresoc.v:166087$10478_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -334880,149 +342810,149 @@ module \ppick$206 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162647$10065 + cell $not $not$libresoc.v:166072$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162647$10065_Y + connect \Y $not$libresoc.v:166072$10463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162649$10067 + cell $not $not$libresoc.v:166074$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162649$10067_Y + connect \Y $not$libresoc.v:166074$10465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162651$10069 + cell $not $not$libresoc.v:166076$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162651$10069_Y + connect \Y $not$libresoc.v:166076$10467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162652$10070 + cell $not $not$libresoc.v:166077$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162652$10070_Y + connect \Y $not$libresoc.v:166077$10468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162654$10072 + cell $not $not$libresoc.v:166079$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162654$10072_Y + connect \Y $not$libresoc.v:166079$10470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162656$10074 + cell $not $not$libresoc.v:166081$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162656$10074_Y + connect \Y $not$libresoc.v:166081$10472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162658$10076 + cell $not $not$libresoc.v:166083$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162658$10076_Y + connect \Y $not$libresoc.v:166083$10474_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162661$10079 + cell $not $not$libresoc.v:166086$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162661$10079_Y + connect \Y $not$libresoc.v:166086$10477_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162648$10066 + cell $reduce_or $reduce_or$libresoc.v:166073$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162648$10066_Y + connect \Y $reduce_or$libresoc.v:166073$10464_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162650$10068 + cell $reduce_or $reduce_or$libresoc.v:166075$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162650$10068_Y + connect \Y $reduce_or$libresoc.v:166075$10466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162653$10071 + cell $reduce_or $reduce_or$libresoc.v:166078$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162653$10071_Y + connect \Y $reduce_or$libresoc.v:166078$10469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162655$10073 + cell $reduce_or $reduce_or$libresoc.v:166080$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162655$10073_Y + connect \Y $reduce_or$libresoc.v:166080$10471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162657$10075 + cell $reduce_or $reduce_or$libresoc.v:166082$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162657$10075_Y + connect \Y $reduce_or$libresoc.v:166082$10473_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162659$10077 + cell $reduce_or $reduce_or$libresoc.v:166084$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162659$10077_Y + connect \Y $reduce_or$libresoc.v:166084$10475_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162660$10078 + cell $reduce_or $reduce_or$libresoc.v:166085$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162660$10078_Y + connect \Y $reduce_or$libresoc.v:166085$10476_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162662$10080 + cell $reduce_or $reduce_or$libresoc.v:166087$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162662$10080_Y - end - connect \$7 $not$libresoc.v:162647$10065_Y - connect \$12 $reduce_or$libresoc.v:162648$10066_Y - connect \$11 $not$libresoc.v:162649$10067_Y - connect \$16 $reduce_or$libresoc.v:162650$10068_Y - connect \$15 $not$libresoc.v:162651$10069_Y - connect \$1 $not$libresoc.v:162652$10070_Y - connect \$20 $reduce_or$libresoc.v:162653$10071_Y - connect \$19 $not$libresoc.v:162654$10072_Y - connect \$24 $reduce_or$libresoc.v:162655$10073_Y - connect \$23 $not$libresoc.v:162656$10074_Y - connect \$28 $reduce_or$libresoc.v:162657$10075_Y - connect \$27 $not$libresoc.v:162658$10076_Y - connect \$31 $reduce_or$libresoc.v:162659$10077_Y - connect \$4 $reduce_or$libresoc.v:162660$10078_Y - connect \$3 $not$libresoc.v:162661$10079_Y - connect \$8 $reduce_or$libresoc.v:162662$10080_Y + connect \Y $reduce_or$libresoc.v:166087$10478_Y + end + connect \$7 $not$libresoc.v:166072$10463_Y + connect \$12 $reduce_or$libresoc.v:166073$10464_Y + connect \$11 $not$libresoc.v:166074$10465_Y + connect \$16 $reduce_or$libresoc.v:166075$10466_Y + connect \$15 $not$libresoc.v:166076$10467_Y + connect \$1 $not$libresoc.v:166077$10468_Y + connect \$20 $reduce_or$libresoc.v:166078$10469_Y + connect \$19 $not$libresoc.v:166079$10470_Y + connect \$24 $reduce_or$libresoc.v:166080$10471_Y + connect \$23 $not$libresoc.v:166081$10472_Y + connect \$28 $reduce_or$libresoc.v:166082$10473_Y + connect \$27 $not$libresoc.v:166083$10474_Y + connect \$31 $reduce_or$libresoc.v:166084$10475_Y + connect \$4 $reduce_or$libresoc.v:166085$10476_Y + connect \$3 $not$libresoc.v:166086$10477_Y + connect \$8 $reduce_or$libresoc.v:166087$10478_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -335035,43 +342965,43 @@ module \ppick$206 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162678.1-162762.10" +attribute \src "libresoc.v:166103.1-166187.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$208 - attribute \src "libresoc.v:162735.17-162735.91" - wire $not$libresoc.v:162735$10081_Y - attribute \src "libresoc.v:162737.18-162737.93" - wire $not$libresoc.v:162737$10083_Y - attribute \src "libresoc.v:162739.18-162739.93" - wire $not$libresoc.v:162739$10085_Y - attribute \src "libresoc.v:162740.17-162740.138" - wire width 8 $not$libresoc.v:162740$10086_Y - attribute \src "libresoc.v:162742.18-162742.93" - wire $not$libresoc.v:162742$10088_Y - attribute \src "libresoc.v:162744.18-162744.93" - wire $not$libresoc.v:162744$10090_Y - attribute \src "libresoc.v:162746.18-162746.93" - wire $not$libresoc.v:162746$10092_Y - attribute \src "libresoc.v:162749.17-162749.91" - wire $not$libresoc.v:162749$10095_Y - attribute \src "libresoc.v:162736.18-162736.116" - wire $reduce_or$libresoc.v:162736$10082_Y - attribute \src "libresoc.v:162738.18-162738.122" - wire $reduce_or$libresoc.v:162738$10084_Y - attribute \src "libresoc.v:162741.18-162741.128" - wire $reduce_or$libresoc.v:162741$10087_Y - attribute \src "libresoc.v:162743.18-162743.134" - wire $reduce_or$libresoc.v:162743$10089_Y - attribute \src "libresoc.v:162745.18-162745.140" - wire $reduce_or$libresoc.v:162745$10091_Y - attribute \src "libresoc.v:162747.18-162747.90" - wire $reduce_or$libresoc.v:162747$10093_Y - attribute \src "libresoc.v:162748.17-162748.103" - wire $reduce_or$libresoc.v:162748$10094_Y - attribute \src "libresoc.v:162750.17-162750.109" - wire $reduce_or$libresoc.v:162750$10096_Y +module \ppick$211 + attribute \src "libresoc.v:166160.17-166160.91" + wire $not$libresoc.v:166160$10479_Y + attribute \src "libresoc.v:166162.18-166162.93" + wire $not$libresoc.v:166162$10481_Y + attribute \src "libresoc.v:166164.18-166164.93" + wire $not$libresoc.v:166164$10483_Y + attribute \src "libresoc.v:166165.17-166165.138" + wire width 8 $not$libresoc.v:166165$10484_Y + attribute \src "libresoc.v:166167.18-166167.93" + wire $not$libresoc.v:166167$10486_Y + attribute \src "libresoc.v:166169.18-166169.93" + wire $not$libresoc.v:166169$10488_Y + attribute \src "libresoc.v:166171.18-166171.93" + wire $not$libresoc.v:166171$10490_Y + attribute \src "libresoc.v:166174.17-166174.91" + wire $not$libresoc.v:166174$10493_Y + attribute \src "libresoc.v:166161.18-166161.116" + wire $reduce_or$libresoc.v:166161$10480_Y + attribute \src "libresoc.v:166163.18-166163.122" + wire $reduce_or$libresoc.v:166163$10482_Y + attribute \src "libresoc.v:166166.18-166166.128" + wire $reduce_or$libresoc.v:166166$10485_Y + attribute \src "libresoc.v:166168.18-166168.134" + wire $reduce_or$libresoc.v:166168$10487_Y + attribute \src "libresoc.v:166170.18-166170.140" + wire $reduce_or$libresoc.v:166170$10489_Y + attribute \src "libresoc.v:166172.18-166172.90" + wire $reduce_or$libresoc.v:166172$10491_Y + attribute \src "libresoc.v:166173.17-166173.103" + wire $reduce_or$libresoc.v:166173$10492_Y + attribute \src "libresoc.v:166175.17-166175.109" + wire $reduce_or$libresoc.v:166175$10494_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -335129,149 +343059,149 @@ module \ppick$208 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162735$10081 + cell $not $not$libresoc.v:166160$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162735$10081_Y + connect \Y $not$libresoc.v:166160$10479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162737$10083 + cell $not $not$libresoc.v:166162$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:162737$10083_Y + connect \Y $not$libresoc.v:166162$10481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162739$10085 + cell $not $not$libresoc.v:166164$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:162739$10085_Y + connect \Y $not$libresoc.v:166164$10483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162740$10086 + cell $not $not$libresoc.v:166165$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:162740$10086_Y + connect \Y $not$libresoc.v:166165$10484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162742$10088 + cell $not $not$libresoc.v:166167$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:162742$10088_Y + connect \Y $not$libresoc.v:166167$10486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162744$10090 + cell $not $not$libresoc.v:166169$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:162744$10090_Y + connect \Y $not$libresoc.v:166169$10488_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162746$10092 + cell $not $not$libresoc.v:166171$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:162746$10092_Y + connect \Y $not$libresoc.v:166171$10490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162749$10095 + cell $not $not$libresoc.v:166174$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162749$10095_Y + connect \Y $not$libresoc.v:166174$10493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162736$10082 + cell $reduce_or $reduce_or$libresoc.v:166161$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:162736$10082_Y + connect \Y $reduce_or$libresoc.v:166161$10480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162738$10084 + cell $reduce_or $reduce_or$libresoc.v:166163$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:162738$10084_Y + connect \Y $reduce_or$libresoc.v:166163$10482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162741$10087 + cell $reduce_or $reduce_or$libresoc.v:166166$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:162741$10087_Y + connect \Y $reduce_or$libresoc.v:166166$10485_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162743$10089 + cell $reduce_or $reduce_or$libresoc.v:166168$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:162743$10089_Y + connect \Y $reduce_or$libresoc.v:166168$10487_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162745$10091 + cell $reduce_or $reduce_or$libresoc.v:166170$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:162745$10091_Y + connect \Y $reduce_or$libresoc.v:166170$10489_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162747$10093 + cell $reduce_or $reduce_or$libresoc.v:166172$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162747$10093_Y + connect \Y $reduce_or$libresoc.v:166172$10491_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162748$10094 + cell $reduce_or $reduce_or$libresoc.v:166173$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:162748$10094_Y + connect \Y $reduce_or$libresoc.v:166173$10492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162750$10096 + cell $reduce_or $reduce_or$libresoc.v:166175$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:162750$10096_Y - end - connect \$7 $not$libresoc.v:162735$10081_Y - connect \$12 $reduce_or$libresoc.v:162736$10082_Y - connect \$11 $not$libresoc.v:162737$10083_Y - connect \$16 $reduce_or$libresoc.v:162738$10084_Y - connect \$15 $not$libresoc.v:162739$10085_Y - connect \$1 $not$libresoc.v:162740$10086_Y - connect \$20 $reduce_or$libresoc.v:162741$10087_Y - connect \$19 $not$libresoc.v:162742$10088_Y - connect \$24 $reduce_or$libresoc.v:162743$10089_Y - connect \$23 $not$libresoc.v:162744$10090_Y - connect \$28 $reduce_or$libresoc.v:162745$10091_Y - connect \$27 $not$libresoc.v:162746$10092_Y - connect \$31 $reduce_or$libresoc.v:162747$10093_Y - connect \$4 $reduce_or$libresoc.v:162748$10094_Y - connect \$3 $not$libresoc.v:162749$10095_Y - connect \$8 $reduce_or$libresoc.v:162750$10096_Y + connect \Y $reduce_or$libresoc.v:166175$10494_Y + end + connect \$7 $not$libresoc.v:166160$10479_Y + connect \$12 $reduce_or$libresoc.v:166161$10480_Y + connect \$11 $not$libresoc.v:166162$10481_Y + connect \$16 $reduce_or$libresoc.v:166163$10482_Y + connect \$15 $not$libresoc.v:166164$10483_Y + connect \$1 $not$libresoc.v:166165$10484_Y + connect \$20 $reduce_or$libresoc.v:166166$10485_Y + connect \$19 $not$libresoc.v:166167$10486_Y + connect \$24 $reduce_or$libresoc.v:166168$10487_Y + connect \$23 $not$libresoc.v:166169$10488_Y + connect \$28 $reduce_or$libresoc.v:166170$10489_Y + connect \$27 $not$libresoc.v:166171$10490_Y + connect \$31 $reduce_or$libresoc.v:166172$10491_Y + connect \$4 $reduce_or$libresoc.v:166173$10492_Y + connect \$3 $not$libresoc.v:166174$10493_Y + connect \$8 $reduce_or$libresoc.v:166175$10494_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -335284,19 +343214,19 @@ module \ppick$208 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:162766.1-162796.10" +attribute \src "libresoc.v:166191.1-166221.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:162787.17-162787.89" - wire width 2 $not$libresoc.v:162787$10097_Y - attribute \src "libresoc.v:162789.17-162789.91" - wire $not$libresoc.v:162789$10099_Y - attribute \src "libresoc.v:162788.17-162788.103" - wire $reduce_or$libresoc.v:162788$10098_Y - attribute \src "libresoc.v:162790.17-162790.89" - wire $reduce_or$libresoc.v:162790$10100_Y + attribute \src "libresoc.v:166212.17-166212.89" + wire width 2 $not$libresoc.v:166212$10495_Y + attribute \src "libresoc.v:166214.17-166214.91" + wire $not$libresoc.v:166214$10497_Y + attribute \src "libresoc.v:166213.17-166213.103" + wire $reduce_or$libresoc.v:166213$10496_Y + attribute \src "libresoc.v:166215.17-166215.89" + wire $reduce_or$libresoc.v:166215$10498_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -335318,56 +343248,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162787$10097 + cell $not $not$libresoc.v:166212$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:162787$10097_Y + connect \Y $not$libresoc.v:166212$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162789$10099 + cell $not $not$libresoc.v:166214$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162789$10099_Y + connect \Y $not$libresoc.v:166214$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162788$10098 + cell $reduce_or $reduce_or$libresoc.v:166213$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:162788$10098_Y + connect \Y $reduce_or$libresoc.v:166213$10496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162790$10100 + cell $reduce_or $reduce_or$libresoc.v:166215$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162790$10100_Y + connect \Y $reduce_or$libresoc.v:166215$10498_Y end - connect \$1 $not$libresoc.v:162787$10097_Y - connect \$4 $reduce_or$libresoc.v:162788$10098_Y - connect \$3 $not$libresoc.v:162789$10099_Y - connect \$7 $reduce_or$libresoc.v:162790$10100_Y + connect \$1 $not$libresoc.v:166212$10495_Y + connect \$4 $reduce_or$libresoc.v:166213$10496_Y + connect \$3 $not$libresoc.v:166214$10497_Y + connect \$7 $reduce_or$libresoc.v:166215$10498_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:162800.1-162821.10" +attribute \src "libresoc.v:166225.1-166246.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:162815.17-162815.89" - wire $not$libresoc.v:162815$10101_Y - attribute \src "libresoc.v:162816.17-162816.89" - wire $reduce_or$libresoc.v:162816$10102_Y + attribute \src "libresoc.v:166240.17-166240.89" + wire $not$libresoc.v:166240$10499_Y + attribute \src "libresoc.v:166241.17-166241.89" + wire $reduce_or$libresoc.v:166241$10500_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -335383,37 +343313,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162815$10101 + cell $not $not$libresoc.v:166240$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:162815$10101_Y + connect \Y $not$libresoc.v:166240$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162816$10102 + cell $reduce_or $reduce_or$libresoc.v:166241$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162816$10102_Y + connect \Y $reduce_or$libresoc.v:166241$10500_Y end - connect \$1 $not$libresoc.v:162815$10101_Y - connect \$3 $reduce_or$libresoc.v:162816$10102_Y + connect \$1 $not$libresoc.v:166240$10499_Y + connect \$3 $reduce_or$libresoc.v:166241$10500_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:162825.1-162846.10" +attribute \src "libresoc.v:166250.1-166271.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:162840.17-162840.89" - wire $not$libresoc.v:162840$10103_Y - attribute \src "libresoc.v:162841.17-162841.89" - wire $reduce_or$libresoc.v:162841$10104_Y + attribute \src "libresoc.v:166265.17-166265.89" + wire $not$libresoc.v:166265$10501_Y + attribute \src "libresoc.v:166266.17-166266.89" + wire $reduce_or$libresoc.v:166266$10502_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -335429,37 +343359,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162840$10103 + cell $not $not$libresoc.v:166265$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:162840$10103_Y + connect \Y $not$libresoc.v:166265$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162841$10104 + cell $reduce_or $reduce_or$libresoc.v:166266$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162841$10104_Y + connect \Y $reduce_or$libresoc.v:166266$10502_Y end - connect \$1 $not$libresoc.v:162840$10103_Y - connect \$3 $reduce_or$libresoc.v:162841$10104_Y + connect \$1 $not$libresoc.v:166265$10501_Y + connect \$3 $reduce_or$libresoc.v:166266$10502_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:162850.1-162871.10" +attribute \src "libresoc.v:166275.1-166296.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:162865.17-162865.89" - wire $not$libresoc.v:162865$10105_Y - attribute \src "libresoc.v:162866.17-162866.89" - wire $reduce_or$libresoc.v:162866$10106_Y + attribute \src "libresoc.v:166290.17-166290.89" + wire $not$libresoc.v:166290$10503_Y + attribute \src "libresoc.v:166291.17-166291.89" + wire $reduce_or$libresoc.v:166291$10504_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -335475,45 +343405,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162865$10105 + cell $not $not$libresoc.v:166290$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:162865$10105_Y + connect \Y $not$libresoc.v:166290$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162866$10106 + cell $reduce_or $reduce_or$libresoc.v:166291$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162866$10106_Y + connect \Y $reduce_or$libresoc.v:166291$10504_Y end - connect \$1 $not$libresoc.v:162865$10105_Y - connect \$3 $reduce_or$libresoc.v:162866$10106_Y + connect \$1 $not$libresoc.v:166290$10503_Y + connect \$3 $reduce_or$libresoc.v:166291$10504_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:162875.1-162914.10" +attribute \src "libresoc.v:166300.1-166339.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:162902.17-162902.91" - wire $not$libresoc.v:162902$10107_Y - attribute \src "libresoc.v:162904.17-162904.89" - wire width 3 $not$libresoc.v:162904$10109_Y - attribute \src "libresoc.v:162906.17-162906.91" - wire $not$libresoc.v:162906$10111_Y - attribute \src "libresoc.v:162903.18-162903.90" - wire $reduce_or$libresoc.v:162903$10108_Y - attribute \src "libresoc.v:162905.17-162905.103" - wire $reduce_or$libresoc.v:162905$10110_Y - attribute \src "libresoc.v:162907.17-162907.105" - wire $reduce_or$libresoc.v:162907$10112_Y + attribute \src "libresoc.v:166327.17-166327.91" + wire $not$libresoc.v:166327$10505_Y + attribute \src "libresoc.v:166329.17-166329.89" + wire width 3 $not$libresoc.v:166329$10507_Y + attribute \src "libresoc.v:166331.17-166331.91" + wire $not$libresoc.v:166331$10509_Y + attribute \src "libresoc.v:166328.18-166328.90" + wire $reduce_or$libresoc.v:166328$10506_Y + attribute \src "libresoc.v:166330.17-166330.103" + wire $reduce_or$libresoc.v:166330$10508_Y + attribute \src "libresoc.v:166332.17-166332.105" + wire $reduce_or$libresoc.v:166332$10510_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -335541,59 +343471,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162902$10107 + cell $not $not$libresoc.v:166327$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:162902$10107_Y + connect \Y $not$libresoc.v:166327$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162904$10109 + cell $not $not$libresoc.v:166329$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:162904$10109_Y + connect \Y $not$libresoc.v:166329$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162906$10111 + cell $not $not$libresoc.v:166331$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162906$10111_Y + connect \Y $not$libresoc.v:166331$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162903$10108 + cell $reduce_or $reduce_or$libresoc.v:166328$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162903$10108_Y + connect \Y $reduce_or$libresoc.v:166328$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162905$10110 + cell $reduce_or $reduce_or$libresoc.v:166330$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:162905$10110_Y + connect \Y $reduce_or$libresoc.v:166330$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162907$10112 + cell $reduce_or $reduce_or$libresoc.v:166332$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:162907$10112_Y - end - connect \$7 $not$libresoc.v:162902$10107_Y - connect \$11 $reduce_or$libresoc.v:162903$10108_Y - connect \$1 $not$libresoc.v:162904$10109_Y - connect \$4 $reduce_or$libresoc.v:162905$10110_Y - connect \$3 $not$libresoc.v:162906$10111_Y - connect \$8 $reduce_or$libresoc.v:162907$10112_Y + connect \Y $reduce_or$libresoc.v:166332$10510_Y + end + connect \$7 $not$libresoc.v:166327$10505_Y + connect \$11 $reduce_or$libresoc.v:166328$10506_Y + connect \$1 $not$libresoc.v:166329$10507_Y + connect \$4 $reduce_or$libresoc.v:166330$10508_Y + connect \$3 $not$libresoc.v:166331$10509_Y + connect \$8 $reduce_or$libresoc.v:166332$10510_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -335601,19 +343531,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:162918.1-162948.10" +attribute \src "libresoc.v:166343.1-166373.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:162939.17-162939.89" - wire width 2 $not$libresoc.v:162939$10113_Y - attribute \src "libresoc.v:162941.17-162941.91" - wire $not$libresoc.v:162941$10115_Y - attribute \src "libresoc.v:162940.17-162940.103" - wire $reduce_or$libresoc.v:162940$10114_Y - attribute \src "libresoc.v:162942.17-162942.89" - wire $reduce_or$libresoc.v:162942$10116_Y + attribute \src "libresoc.v:166364.17-166364.89" + wire width 2 $not$libresoc.v:166364$10511_Y + attribute \src "libresoc.v:166366.17-166366.91" + wire $not$libresoc.v:166366$10513_Y + attribute \src "libresoc.v:166365.17-166365.103" + wire $reduce_or$libresoc.v:166365$10512_Y + attribute \src "libresoc.v:166367.17-166367.89" + wire $reduce_or$libresoc.v:166367$10514_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -335635,88 +343565,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:162939$10113 + cell $not $not$libresoc.v:166364$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:162939$10113_Y + connect \Y $not$libresoc.v:166364$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:162941$10115 + cell $not $not$libresoc.v:166366$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:162941$10115_Y + connect \Y $not$libresoc.v:166366$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:162940$10114 + cell $reduce_or $reduce_or$libresoc.v:166365$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:162940$10114_Y + connect \Y $reduce_or$libresoc.v:166365$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:162942$10116 + cell $reduce_or $reduce_or$libresoc.v:166367$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:162942$10116_Y + connect \Y $reduce_or$libresoc.v:166367$10514_Y end - connect \$1 $not$libresoc.v:162939$10113_Y - connect \$4 $reduce_or$libresoc.v:162940$10114_Y - connect \$3 $not$libresoc.v:162941$10115_Y - connect \$7 $reduce_or$libresoc.v:162942$10116_Y + connect \$1 $not$libresoc.v:166364$10511_Y + connect \$4 $reduce_or$libresoc.v:166365$10512_Y + connect \$3 $not$libresoc.v:166366$10513_Y + connect \$7 $reduce_or$libresoc.v:166367$10514_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:162952.1-163045.10" +attribute \src "libresoc.v:166377.1-166470.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:163015.17-163015.91" - wire $not$libresoc.v:163015$10117_Y - attribute \src "libresoc.v:163017.18-163017.93" - wire $not$libresoc.v:163017$10119_Y - attribute \src "libresoc.v:163019.18-163019.93" - wire $not$libresoc.v:163019$10121_Y - attribute \src "libresoc.v:163020.17-163020.89" - wire width 9 $not$libresoc.v:163020$10122_Y - attribute \src "libresoc.v:163022.18-163022.93" - wire $not$libresoc.v:163022$10124_Y - attribute \src "libresoc.v:163024.18-163024.93" - wire $not$libresoc.v:163024$10126_Y - attribute \src "libresoc.v:163026.18-163026.93" - wire $not$libresoc.v:163026$10128_Y - attribute \src "libresoc.v:163028.18-163028.93" - wire $not$libresoc.v:163028$10130_Y - attribute \src "libresoc.v:163031.17-163031.91" - wire $not$libresoc.v:163031$10133_Y - attribute \src "libresoc.v:163016.18-163016.106" - wire $reduce_or$libresoc.v:163016$10118_Y - attribute \src "libresoc.v:163018.18-163018.106" - wire $reduce_or$libresoc.v:163018$10120_Y - attribute \src "libresoc.v:163021.18-163021.106" - wire $reduce_or$libresoc.v:163021$10123_Y - attribute \src "libresoc.v:163023.18-163023.106" - wire $reduce_or$libresoc.v:163023$10125_Y - attribute \src "libresoc.v:163025.18-163025.106" - wire $reduce_or$libresoc.v:163025$10127_Y - attribute \src "libresoc.v:163027.18-163027.106" - wire $reduce_or$libresoc.v:163027$10129_Y - attribute \src "libresoc.v:163029.18-163029.90" - wire $reduce_or$libresoc.v:163029$10131_Y - attribute \src "libresoc.v:163030.17-163030.103" - wire $reduce_or$libresoc.v:163030$10132_Y - attribute \src "libresoc.v:163032.17-163032.105" - wire $reduce_or$libresoc.v:163032$10134_Y + attribute \src "libresoc.v:166440.17-166440.91" + wire $not$libresoc.v:166440$10515_Y + attribute \src "libresoc.v:166442.18-166442.93" + wire $not$libresoc.v:166442$10517_Y + attribute \src "libresoc.v:166444.18-166444.93" + wire $not$libresoc.v:166444$10519_Y + attribute \src "libresoc.v:166445.17-166445.89" + wire width 9 $not$libresoc.v:166445$10520_Y + attribute \src "libresoc.v:166447.18-166447.93" + wire $not$libresoc.v:166447$10522_Y + attribute \src "libresoc.v:166449.18-166449.93" + wire $not$libresoc.v:166449$10524_Y + attribute \src "libresoc.v:166451.18-166451.93" + wire $not$libresoc.v:166451$10526_Y + attribute \src "libresoc.v:166453.18-166453.93" + wire $not$libresoc.v:166453$10528_Y + attribute \src "libresoc.v:166456.17-166456.91" + wire $not$libresoc.v:166456$10531_Y + attribute \src "libresoc.v:166441.18-166441.106" + wire $reduce_or$libresoc.v:166441$10516_Y + attribute \src "libresoc.v:166443.18-166443.106" + wire $reduce_or$libresoc.v:166443$10518_Y + attribute \src "libresoc.v:166446.18-166446.106" + wire $reduce_or$libresoc.v:166446$10521_Y + attribute \src "libresoc.v:166448.18-166448.106" + wire $reduce_or$libresoc.v:166448$10523_Y + attribute \src "libresoc.v:166450.18-166450.106" + wire $reduce_or$libresoc.v:166450$10525_Y + attribute \src "libresoc.v:166452.18-166452.106" + wire $reduce_or$libresoc.v:166452$10527_Y + attribute \src "libresoc.v:166454.18-166454.90" + wire $reduce_or$libresoc.v:166454$10529_Y + attribute \src "libresoc.v:166455.17-166455.103" + wire $reduce_or$libresoc.v:166455$10530_Y + attribute \src "libresoc.v:166457.17-166457.105" + wire $reduce_or$libresoc.v:166457$10532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -335780,167 +343710,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163015$10117 + cell $not $not$libresoc.v:166440$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:163015$10117_Y + connect \Y $not$libresoc.v:166440$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163017$10119 + cell $not $not$libresoc.v:166442$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:163017$10119_Y + connect \Y $not$libresoc.v:166442$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163019$10121 + cell $not $not$libresoc.v:166444$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:163019$10121_Y + connect \Y $not$libresoc.v:166444$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163020$10122 + cell $not $not$libresoc.v:166445$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:163020$10122_Y + connect \Y $not$libresoc.v:166445$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163022$10124 + cell $not $not$libresoc.v:166447$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:163022$10124_Y + connect \Y $not$libresoc.v:166447$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163024$10126 + cell $not $not$libresoc.v:166449$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:163024$10126_Y + connect \Y $not$libresoc.v:166449$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163026$10128 + cell $not $not$libresoc.v:166451$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:163026$10128_Y + connect \Y $not$libresoc.v:166451$10526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163028$10130 + cell $not $not$libresoc.v:166453$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:163028$10130_Y + connect \Y $not$libresoc.v:166453$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163031$10133 + cell $not $not$libresoc.v:166456$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:163031$10133_Y + connect \Y $not$libresoc.v:166456$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163016$10118 + cell $reduce_or $reduce_or$libresoc.v:166441$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:163016$10118_Y + connect \Y $reduce_or$libresoc.v:166441$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163018$10120 + cell $reduce_or $reduce_or$libresoc.v:166443$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:163018$10120_Y + connect \Y $reduce_or$libresoc.v:166443$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163021$10123 + cell $reduce_or $reduce_or$libresoc.v:166446$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:163021$10123_Y + connect \Y $reduce_or$libresoc.v:166446$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163023$10125 + cell $reduce_or $reduce_or$libresoc.v:166448$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:163023$10125_Y + connect \Y $reduce_or$libresoc.v:166448$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163025$10127 + cell $reduce_or $reduce_or$libresoc.v:166450$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:163025$10127_Y + connect \Y $reduce_or$libresoc.v:166450$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163027$10129 + cell $reduce_or $reduce_or$libresoc.v:166452$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:163027$10129_Y + connect \Y $reduce_or$libresoc.v:166452$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163029$10131 + cell $reduce_or $reduce_or$libresoc.v:166454$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163029$10131_Y + connect \Y $reduce_or$libresoc.v:166454$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163030$10132 + cell $reduce_or $reduce_or$libresoc.v:166455$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:163030$10132_Y + connect \Y $reduce_or$libresoc.v:166455$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163032$10134 + cell $reduce_or $reduce_or$libresoc.v:166457$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:163032$10134_Y - end - connect \$7 $not$libresoc.v:163015$10117_Y - connect \$12 $reduce_or$libresoc.v:163016$10118_Y - connect \$11 $not$libresoc.v:163017$10119_Y - connect \$16 $reduce_or$libresoc.v:163018$10120_Y - connect \$15 $not$libresoc.v:163019$10121_Y - connect \$1 $not$libresoc.v:163020$10122_Y - connect \$20 $reduce_or$libresoc.v:163021$10123_Y - connect \$19 $not$libresoc.v:163022$10124_Y - connect \$24 $reduce_or$libresoc.v:163023$10125_Y - connect \$23 $not$libresoc.v:163024$10126_Y - connect \$28 $reduce_or$libresoc.v:163025$10127_Y - connect \$27 $not$libresoc.v:163026$10128_Y - connect \$32 $reduce_or$libresoc.v:163027$10129_Y - connect \$31 $not$libresoc.v:163028$10130_Y - connect \$35 $reduce_or$libresoc.v:163029$10131_Y - connect \$4 $reduce_or$libresoc.v:163030$10132_Y - connect \$3 $not$libresoc.v:163031$10133_Y - connect \$8 $reduce_or$libresoc.v:163032$10134_Y + connect \Y $reduce_or$libresoc.v:166457$10532_Y + end + connect \$7 $not$libresoc.v:166440$10515_Y + connect \$12 $reduce_or$libresoc.v:166441$10516_Y + connect \$11 $not$libresoc.v:166442$10517_Y + connect \$16 $reduce_or$libresoc.v:166443$10518_Y + connect \$15 $not$libresoc.v:166444$10519_Y + connect \$1 $not$libresoc.v:166445$10520_Y + connect \$20 $reduce_or$libresoc.v:166446$10521_Y + connect \$19 $not$libresoc.v:166447$10522_Y + connect \$24 $reduce_or$libresoc.v:166448$10523_Y + connect \$23 $not$libresoc.v:166449$10524_Y + connect \$28 $reduce_or$libresoc.v:166450$10525_Y + connect \$27 $not$libresoc.v:166451$10526_Y + connect \$32 $reduce_or$libresoc.v:166452$10527_Y + connect \$31 $not$libresoc.v:166453$10528_Y + connect \$35 $reduce_or$libresoc.v:166454$10529_Y + connect \$4 $reduce_or$libresoc.v:166455$10530_Y + connect \$3 $not$libresoc.v:166456$10531_Y + connect \$8 $reduce_or$libresoc.v:166457$10532_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -335954,43 +343884,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:163049.1-163133.10" +attribute \src "libresoc.v:166474.1-166558.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:163106.17-163106.91" - wire $not$libresoc.v:163106$10135_Y - attribute \src "libresoc.v:163108.18-163108.93" - wire $not$libresoc.v:163108$10137_Y - attribute \src "libresoc.v:163110.18-163110.93" - wire $not$libresoc.v:163110$10139_Y - attribute \src "libresoc.v:163111.17-163111.89" - wire width 8 $not$libresoc.v:163111$10140_Y - attribute \src "libresoc.v:163113.18-163113.93" - wire $not$libresoc.v:163113$10142_Y - attribute \src "libresoc.v:163115.18-163115.93" - wire $not$libresoc.v:163115$10144_Y - attribute \src "libresoc.v:163117.18-163117.93" - wire $not$libresoc.v:163117$10146_Y - attribute \src "libresoc.v:163120.17-163120.91" - wire $not$libresoc.v:163120$10149_Y - attribute \src "libresoc.v:163107.18-163107.106" - wire $reduce_or$libresoc.v:163107$10136_Y - attribute \src "libresoc.v:163109.18-163109.106" - wire $reduce_or$libresoc.v:163109$10138_Y - attribute \src "libresoc.v:163112.18-163112.106" - wire $reduce_or$libresoc.v:163112$10141_Y - attribute \src "libresoc.v:163114.18-163114.106" - wire $reduce_or$libresoc.v:163114$10143_Y - attribute \src "libresoc.v:163116.18-163116.106" - wire $reduce_or$libresoc.v:163116$10145_Y - attribute \src "libresoc.v:163118.18-163118.90" - wire $reduce_or$libresoc.v:163118$10147_Y - attribute \src "libresoc.v:163119.17-163119.103" - wire $reduce_or$libresoc.v:163119$10148_Y - attribute \src "libresoc.v:163121.17-163121.105" - wire $reduce_or$libresoc.v:163121$10150_Y + attribute \src "libresoc.v:166531.17-166531.91" + wire $not$libresoc.v:166531$10533_Y + attribute \src "libresoc.v:166533.18-166533.93" + wire $not$libresoc.v:166533$10535_Y + attribute \src "libresoc.v:166535.18-166535.93" + wire $not$libresoc.v:166535$10537_Y + attribute \src "libresoc.v:166536.17-166536.89" + wire width 8 $not$libresoc.v:166536$10538_Y + attribute \src "libresoc.v:166538.18-166538.93" + wire $not$libresoc.v:166538$10540_Y + attribute \src "libresoc.v:166540.18-166540.93" + wire $not$libresoc.v:166540$10542_Y + attribute \src "libresoc.v:166542.18-166542.93" + wire $not$libresoc.v:166542$10544_Y + attribute \src "libresoc.v:166545.17-166545.91" + wire $not$libresoc.v:166545$10547_Y + attribute \src "libresoc.v:166532.18-166532.106" + wire $reduce_or$libresoc.v:166532$10534_Y + attribute \src "libresoc.v:166534.18-166534.106" + wire $reduce_or$libresoc.v:166534$10536_Y + attribute \src "libresoc.v:166537.18-166537.106" + wire $reduce_or$libresoc.v:166537$10539_Y + attribute \src "libresoc.v:166539.18-166539.106" + wire $reduce_or$libresoc.v:166539$10541_Y + attribute \src "libresoc.v:166541.18-166541.106" + wire $reduce_or$libresoc.v:166541$10543_Y + attribute \src "libresoc.v:166543.18-166543.90" + wire $reduce_or$libresoc.v:166543$10545_Y + attribute \src "libresoc.v:166544.17-166544.103" + wire $reduce_or$libresoc.v:166544$10546_Y + attribute \src "libresoc.v:166546.17-166546.105" + wire $reduce_or$libresoc.v:166546$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -336048,149 +343978,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163106$10135 + cell $not $not$libresoc.v:166531$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:163106$10135_Y + connect \Y $not$libresoc.v:166531$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163108$10137 + cell $not $not$libresoc.v:166533$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:163108$10137_Y + connect \Y $not$libresoc.v:166533$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163110$10139 + cell $not $not$libresoc.v:166535$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:163110$10139_Y + connect \Y $not$libresoc.v:166535$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163111$10140 + cell $not $not$libresoc.v:166536$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:163111$10140_Y + connect \Y $not$libresoc.v:166536$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163113$10142 + cell $not $not$libresoc.v:166538$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:163113$10142_Y + connect \Y $not$libresoc.v:166538$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163115$10144 + cell $not $not$libresoc.v:166540$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:163115$10144_Y + connect \Y $not$libresoc.v:166540$10542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163117$10146 + cell $not $not$libresoc.v:166542$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:163117$10146_Y + connect \Y $not$libresoc.v:166542$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163120$10149 + cell $not $not$libresoc.v:166545$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:163120$10149_Y + connect \Y $not$libresoc.v:166545$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163107$10136 + cell $reduce_or $reduce_or$libresoc.v:166532$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:163107$10136_Y + connect \Y $reduce_or$libresoc.v:166532$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163109$10138 + cell $reduce_or $reduce_or$libresoc.v:166534$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:163109$10138_Y + connect \Y $reduce_or$libresoc.v:166534$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163112$10141 + cell $reduce_or $reduce_or$libresoc.v:166537$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:163112$10141_Y + connect \Y $reduce_or$libresoc.v:166537$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163114$10143 + cell $reduce_or $reduce_or$libresoc.v:166539$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:163114$10143_Y + connect \Y $reduce_or$libresoc.v:166539$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163116$10145 + cell $reduce_or $reduce_or$libresoc.v:166541$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:163116$10145_Y + connect \Y $reduce_or$libresoc.v:166541$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163118$10147 + cell $reduce_or $reduce_or$libresoc.v:166543$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163118$10147_Y + connect \Y $reduce_or$libresoc.v:166543$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163119$10148 + cell $reduce_or $reduce_or$libresoc.v:166544$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:163119$10148_Y + connect \Y $reduce_or$libresoc.v:166544$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163121$10150 + cell $reduce_or $reduce_or$libresoc.v:166546$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:163121$10150_Y - end - connect \$7 $not$libresoc.v:163106$10135_Y - connect \$12 $reduce_or$libresoc.v:163107$10136_Y - connect \$11 $not$libresoc.v:163108$10137_Y - connect \$16 $reduce_or$libresoc.v:163109$10138_Y - connect \$15 $not$libresoc.v:163110$10139_Y - connect \$1 $not$libresoc.v:163111$10140_Y - connect \$20 $reduce_or$libresoc.v:163112$10141_Y - connect \$19 $not$libresoc.v:163113$10142_Y - connect \$24 $reduce_or$libresoc.v:163114$10143_Y - connect \$23 $not$libresoc.v:163115$10144_Y - connect \$28 $reduce_or$libresoc.v:163116$10145_Y - connect \$27 $not$libresoc.v:163117$10146_Y - connect \$31 $reduce_or$libresoc.v:163118$10147_Y - connect \$4 $reduce_or$libresoc.v:163119$10148_Y - connect \$3 $not$libresoc.v:163120$10149_Y - connect \$8 $reduce_or$libresoc.v:163121$10150_Y + connect \Y $reduce_or$libresoc.v:166546$10548_Y + end + connect \$7 $not$libresoc.v:166531$10533_Y + connect \$12 $reduce_or$libresoc.v:166532$10534_Y + connect \$11 $not$libresoc.v:166533$10535_Y + connect \$16 $reduce_or$libresoc.v:166534$10536_Y + connect \$15 $not$libresoc.v:166535$10537_Y + connect \$1 $not$libresoc.v:166536$10538_Y + connect \$20 $reduce_or$libresoc.v:166537$10539_Y + connect \$19 $not$libresoc.v:166538$10540_Y + connect \$24 $reduce_or$libresoc.v:166539$10541_Y + connect \$23 $not$libresoc.v:166540$10542_Y + connect \$28 $reduce_or$libresoc.v:166541$10543_Y + connect \$27 $not$libresoc.v:166542$10544_Y + connect \$31 $reduce_or$libresoc.v:166543$10545_Y + connect \$4 $reduce_or$libresoc.v:166544$10546_Y + connect \$3 $not$libresoc.v:166545$10547_Y + connect \$8 $reduce_or$libresoc.v:166546$10548_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -336203,19 +344133,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:163137.1-163167.10" +attribute \src "libresoc.v:166562.1-166592.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:163158.17-163158.89" - wire width 2 $not$libresoc.v:163158$10151_Y - attribute \src "libresoc.v:163160.17-163160.91" - wire $not$libresoc.v:163160$10153_Y - attribute \src "libresoc.v:163159.17-163159.103" - wire $reduce_or$libresoc.v:163159$10152_Y - attribute \src "libresoc.v:163161.17-163161.89" - wire $reduce_or$libresoc.v:163161$10154_Y + attribute \src "libresoc.v:166583.17-166583.89" + wire width 2 $not$libresoc.v:166583$10549_Y + attribute \src "libresoc.v:166585.17-166585.91" + wire $not$libresoc.v:166585$10551_Y + attribute \src "libresoc.v:166584.17-166584.103" + wire $reduce_or$libresoc.v:166584$10550_Y + attribute \src "libresoc.v:166586.17-166586.89" + wire $reduce_or$libresoc.v:166586$10552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -336237,56 +344167,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163158$10151 + cell $not $not$libresoc.v:166583$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:163158$10151_Y + connect \Y $not$libresoc.v:166583$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163160$10153 + cell $not $not$libresoc.v:166585$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:163160$10153_Y + connect \Y $not$libresoc.v:166585$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163159$10152 + cell $reduce_or $reduce_or$libresoc.v:166584$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:163159$10152_Y + connect \Y $reduce_or$libresoc.v:166584$10550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163161$10154 + cell $reduce_or $reduce_or$libresoc.v:166586$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163161$10154_Y + connect \Y $reduce_or$libresoc.v:166586$10552_Y end - connect \$1 $not$libresoc.v:163158$10151_Y - connect \$4 $reduce_or$libresoc.v:163159$10152_Y - connect \$3 $not$libresoc.v:163160$10153_Y - connect \$7 $reduce_or$libresoc.v:163161$10154_Y + connect \$1 $not$libresoc.v:166583$10549_Y + connect \$4 $reduce_or$libresoc.v:166584$10550_Y + connect \$3 $not$libresoc.v:166585$10551_Y + connect \$7 $reduce_or$libresoc.v:166586$10552_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:163171.1-163192.10" +attribute \src "libresoc.v:166596.1-166617.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:163186.17-163186.89" - wire $not$libresoc.v:163186$10155_Y - attribute \src "libresoc.v:163187.17-163187.89" - wire $reduce_or$libresoc.v:163187$10156_Y + attribute \src "libresoc.v:166611.17-166611.89" + wire $not$libresoc.v:166611$10553_Y + attribute \src "libresoc.v:166612.17-166612.89" + wire $reduce_or$libresoc.v:166612$10554_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -336302,45 +344232,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163186$10155 + cell $not $not$libresoc.v:166611$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:163186$10155_Y + connect \Y $not$libresoc.v:166611$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163187$10156 + cell $reduce_or $reduce_or$libresoc.v:166612$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163187$10156_Y + connect \Y $reduce_or$libresoc.v:166612$10554_Y end - connect \$1 $not$libresoc.v:163186$10155_Y - connect \$3 $reduce_or$libresoc.v:163187$10156_Y + connect \$1 $not$libresoc.v:166611$10553_Y + connect \$3 $reduce_or$libresoc.v:166612$10554_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:163196.1-163235.10" +attribute \src "libresoc.v:166621.1-166660.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:163223.17-163223.91" - wire $not$libresoc.v:163223$10157_Y - attribute \src "libresoc.v:163225.17-163225.89" - wire width 3 $not$libresoc.v:163225$10159_Y - attribute \src "libresoc.v:163227.17-163227.91" - wire $not$libresoc.v:163227$10161_Y - attribute \src "libresoc.v:163224.18-163224.90" - wire $reduce_or$libresoc.v:163224$10158_Y - attribute \src "libresoc.v:163226.17-163226.103" - wire $reduce_or$libresoc.v:163226$10160_Y - attribute \src "libresoc.v:163228.17-163228.105" - wire $reduce_or$libresoc.v:163228$10162_Y + attribute \src "libresoc.v:166648.17-166648.91" + wire $not$libresoc.v:166648$10555_Y + attribute \src "libresoc.v:166650.17-166650.89" + wire width 3 $not$libresoc.v:166650$10557_Y + attribute \src "libresoc.v:166652.17-166652.91" + wire $not$libresoc.v:166652$10559_Y + attribute \src "libresoc.v:166649.18-166649.90" + wire $reduce_or$libresoc.v:166649$10556_Y + attribute \src "libresoc.v:166651.17-166651.103" + wire $reduce_or$libresoc.v:166651$10558_Y + attribute \src "libresoc.v:166653.17-166653.105" + wire $reduce_or$libresoc.v:166653$10560_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -336368,59 +344298,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163223$10157 + cell $not $not$libresoc.v:166648$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:163223$10157_Y + connect \Y $not$libresoc.v:166648$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163225$10159 + cell $not $not$libresoc.v:166650$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:163225$10159_Y + connect \Y $not$libresoc.v:166650$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163227$10161 + cell $not $not$libresoc.v:166652$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:163227$10161_Y + connect \Y $not$libresoc.v:166652$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163224$10158 + cell $reduce_or $reduce_or$libresoc.v:166649$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163224$10158_Y + connect \Y $reduce_or$libresoc.v:166649$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163226$10160 + cell $reduce_or $reduce_or$libresoc.v:166651$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:163226$10160_Y + connect \Y $reduce_or$libresoc.v:166651$10558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163228$10162 + cell $reduce_or $reduce_or$libresoc.v:166653$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:163228$10162_Y - end - connect \$7 $not$libresoc.v:163223$10157_Y - connect \$11 $reduce_or$libresoc.v:163224$10158_Y - connect \$1 $not$libresoc.v:163225$10159_Y - connect \$4 $reduce_or$libresoc.v:163226$10160_Y - connect \$3 $not$libresoc.v:163227$10161_Y - connect \$8 $reduce_or$libresoc.v:163228$10162_Y + connect \Y $reduce_or$libresoc.v:166653$10560_Y + end + connect \$7 $not$libresoc.v:166648$10555_Y + connect \$11 $reduce_or$libresoc.v:166649$10556_Y + connect \$1 $not$libresoc.v:166650$10557_Y + connect \$4 $reduce_or$libresoc.v:166651$10558_Y + connect \$3 $not$libresoc.v:166652$10559_Y + connect \$8 $reduce_or$libresoc.v:166653$10560_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -336428,15 +344358,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:163239.1-163260.10" +attribute \src "libresoc.v:166664.1-166685.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:163254.17-163254.89" - wire $not$libresoc.v:163254$10163_Y - attribute \src "libresoc.v:163255.17-163255.89" - wire $reduce_or$libresoc.v:163255$10164_Y + attribute \src "libresoc.v:166679.17-166679.89" + wire $not$libresoc.v:166679$10561_Y + attribute \src "libresoc.v:166680.17-166680.89" + wire $reduce_or$libresoc.v:166680$10562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -336452,57 +344382,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163254$10163 + cell $not $not$libresoc.v:166679$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:163254$10163_Y + connect \Y $not$libresoc.v:166679$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163255$10164 + cell $reduce_or $reduce_or$libresoc.v:166680$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163255$10164_Y + connect \Y $reduce_or$libresoc.v:166680$10562_Y end - connect \$1 $not$libresoc.v:163254$10163_Y - connect \$3 $reduce_or$libresoc.v:163255$10164_Y + connect \$1 $not$libresoc.v:166679$10561_Y + connect \$3 $reduce_or$libresoc.v:166680$10562_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:163264.1-163330.10" +attribute \src "libresoc.v:166689.1-166755.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:163309.17-163309.91" - wire $not$libresoc.v:163309$10165_Y - attribute \src "libresoc.v:163311.18-163311.93" - wire $not$libresoc.v:163311$10167_Y - attribute \src "libresoc.v:163313.18-163313.93" - wire $not$libresoc.v:163313$10169_Y - attribute \src "libresoc.v:163314.17-163314.89" - wire width 6 $not$libresoc.v:163314$10170_Y - attribute \src "libresoc.v:163316.18-163316.93" - wire $not$libresoc.v:163316$10172_Y - attribute \src "libresoc.v:163319.17-163319.91" - wire $not$libresoc.v:163319$10175_Y - attribute \src "libresoc.v:163310.18-163310.106" - wire $reduce_or$libresoc.v:163310$10166_Y - attribute \src "libresoc.v:163312.18-163312.106" - wire $reduce_or$libresoc.v:163312$10168_Y - attribute \src "libresoc.v:163315.18-163315.106" - wire $reduce_or$libresoc.v:163315$10171_Y - attribute \src "libresoc.v:163317.18-163317.90" - wire $reduce_or$libresoc.v:163317$10173_Y - attribute \src "libresoc.v:163318.17-163318.103" - wire $reduce_or$libresoc.v:163318$10174_Y - attribute \src "libresoc.v:163320.17-163320.105" - wire $reduce_or$libresoc.v:163320$10176_Y + attribute \src "libresoc.v:166734.17-166734.91" + wire $not$libresoc.v:166734$10563_Y + attribute \src "libresoc.v:166736.18-166736.93" + wire $not$libresoc.v:166736$10565_Y + attribute \src "libresoc.v:166738.18-166738.93" + wire $not$libresoc.v:166738$10567_Y + attribute \src "libresoc.v:166739.17-166739.89" + wire width 6 $not$libresoc.v:166739$10568_Y + attribute \src "libresoc.v:166741.18-166741.93" + wire $not$libresoc.v:166741$10570_Y + attribute \src "libresoc.v:166744.17-166744.91" + wire $not$libresoc.v:166744$10573_Y + attribute \src "libresoc.v:166735.18-166735.106" + wire $reduce_or$libresoc.v:166735$10564_Y + attribute \src "libresoc.v:166737.18-166737.106" + wire $reduce_or$libresoc.v:166737$10566_Y + attribute \src "libresoc.v:166740.18-166740.106" + wire $reduce_or$libresoc.v:166740$10569_Y + attribute \src "libresoc.v:166742.18-166742.90" + wire $reduce_or$libresoc.v:166742$10571_Y + attribute \src "libresoc.v:166743.17-166743.103" + wire $reduce_or$libresoc.v:166743$10572_Y + attribute \src "libresoc.v:166745.17-166745.105" + wire $reduce_or$libresoc.v:166745$10574_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -336548,113 +344478,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163309$10165 + cell $not $not$libresoc.v:166734$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:163309$10165_Y + connect \Y $not$libresoc.v:166734$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163311$10167 + cell $not $not$libresoc.v:166736$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:163311$10167_Y + connect \Y $not$libresoc.v:166736$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163313$10169 + cell $not $not$libresoc.v:166738$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:163313$10169_Y + connect \Y $not$libresoc.v:166738$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:163314$10170 + cell $not $not$libresoc.v:166739$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:163314$10170_Y + connect \Y $not$libresoc.v:166739$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163316$10172 + cell $not $not$libresoc.v:166741$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:163316$10172_Y + connect \Y $not$libresoc.v:166741$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:163319$10175 + cell $not $not$libresoc.v:166744$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:163319$10175_Y + connect \Y $not$libresoc.v:166744$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163310$10166 + cell $reduce_or $reduce_or$libresoc.v:166735$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:163310$10166_Y + connect \Y $reduce_or$libresoc.v:166735$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163312$10168 + cell $reduce_or $reduce_or$libresoc.v:166737$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:163312$10168_Y + connect \Y $reduce_or$libresoc.v:166737$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163315$10171 + cell $reduce_or $reduce_or$libresoc.v:166740$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:163315$10171_Y + connect \Y $reduce_or$libresoc.v:166740$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:163317$10173 + cell $reduce_or $reduce_or$libresoc.v:166742$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:163317$10173_Y + connect \Y $reduce_or$libresoc.v:166742$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163318$10174 + cell $reduce_or $reduce_or$libresoc.v:166743$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:163318$10174_Y + connect \Y $reduce_or$libresoc.v:166743$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:163320$10176 + cell $reduce_or $reduce_or$libresoc.v:166745$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:163320$10176_Y - end - connect \$7 $not$libresoc.v:163309$10165_Y - connect \$12 $reduce_or$libresoc.v:163310$10166_Y - connect \$11 $not$libresoc.v:163311$10167_Y - connect \$16 $reduce_or$libresoc.v:163312$10168_Y - connect \$15 $not$libresoc.v:163313$10169_Y - connect \$1 $not$libresoc.v:163314$10170_Y - connect \$20 $reduce_or$libresoc.v:163315$10171_Y - connect \$19 $not$libresoc.v:163316$10172_Y - connect \$23 $reduce_or$libresoc.v:163317$10173_Y - connect \$4 $reduce_or$libresoc.v:163318$10174_Y - connect \$3 $not$libresoc.v:163319$10175_Y - connect \$8 $reduce_or$libresoc.v:163320$10176_Y + connect \Y $reduce_or$libresoc.v:166745$10574_Y + end + connect \$7 $not$libresoc.v:166734$10563_Y + connect \$12 $reduce_or$libresoc.v:166735$10564_Y + connect \$11 $not$libresoc.v:166736$10565_Y + connect \$16 $reduce_or$libresoc.v:166737$10566_Y + connect \$15 $not$libresoc.v:166738$10567_Y + connect \$1 $not$libresoc.v:166739$10568_Y + connect \$20 $reduce_or$libresoc.v:166740$10569_Y + connect \$19 $not$libresoc.v:166741$10570_Y + connect \$23 $reduce_or$libresoc.v:166742$10571_Y + connect \$4 $reduce_or$libresoc.v:166743$10572_Y + connect \$3 $not$libresoc.v:166744$10573_Y + connect \$8 $reduce_or$libresoc.v:166745$10574_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -336665,177 +344595,177 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:163334.1-163805.10" +attribute \src "libresoc.v:166759.1-167230.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:163335.7-163335.20" + attribute \src "libresoc.v:166760.7-166760.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $0\r0__data_o$next[3:0]$10232 - attribute \src "libresoc.v:163420.3-163421.37" + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $0\r0__data_o$next[3:0]$10630 + attribute \src "libresoc.v:166845.3-166846.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $0\r20__data_o$next[3:0]$10246 - attribute \src "libresoc.v:163418.3-163419.39" + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $0\r20__data_o$next[3:0]$10644 + attribute \src "libresoc.v:166843.3-166844.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:163498.3-163524.6" - wire width 4 $0\reg$next[3:0]$10198 - attribute \src "libresoc.v:163416.3-163417.25" + attribute \src "libresoc.v:166923.3-166949.6" + wire width 4 $0\reg$next[3:0]$10596 + attribute \src "libresoc.v:166841.3-166842.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $0\src10__data_o$next[3:0]$10189 - attribute \src "libresoc.v:163426.3-163427.43" + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $0\src10__data_o$next[3:0]$10587 + attribute \src "libresoc.v:166851.3-166852.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $0\src20__data_o$next[3:0]$10204 - attribute \src "libresoc.v:163424.3-163425.43" + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $0\src20__data_o$next[3:0]$10602 + attribute \src "libresoc.v:166849.3-166850.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $0\src30__data_o$next[3:0]$10218 - attribute \src "libresoc.v:163422.3-163423.43" + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $0\src30__data_o$next[3:0]$10616 + attribute \src "libresoc.v:166847.3-166848.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:163705.3-163734.6" - wire $0\wr_detect$10[0:0]$10240 - attribute \src "libresoc.v:163775.3-163804.6" - wire $0\wr_detect$13[0:0]$10254 - attribute \src "libresoc.v:163565.3-163594.6" - wire $0\wr_detect$4[0:0]$10212 - attribute \src "libresoc.v:163635.3-163664.6" - wire $0\wr_detect$7[0:0]$10226 - attribute \src "libresoc.v:163468.3-163497.6" + attribute \src "libresoc.v:167130.3-167159.6" + wire $0\wr_detect$10[0:0]$10638 + attribute \src "libresoc.v:167200.3-167229.6" + wire $0\wr_detect$13[0:0]$10652 + attribute \src "libresoc.v:166990.3-167019.6" + wire $0\wr_detect$4[0:0]$10610 + attribute \src "libresoc.v:167060.3-167089.6" + wire $0\wr_detect$7[0:0]$10624 + attribute \src "libresoc.v:166893.3-166922.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $1\r0__data_o$next[3:0]$10233 - attribute \src "libresoc.v:163360.13-163360.30" + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $1\r0__data_o$next[3:0]$10631 + attribute \src "libresoc.v:166785.13-166785.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $1\r20__data_o$next[3:0]$10247 - attribute \src "libresoc.v:163367.13-163367.31" + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $1\r20__data_o$next[3:0]$10645 + attribute \src "libresoc.v:166792.13-166792.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:163498.3-163524.6" - wire width 4 $1\reg$next[3:0]$10199 - attribute \src "libresoc.v:163373.13-163373.25" + attribute \src "libresoc.v:166923.3-166949.6" + wire width 4 $1\reg$next[3:0]$10597 + attribute \src "libresoc.v:166798.13-166798.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $1\src10__data_o$next[3:0]$10190 - attribute \src "libresoc.v:163378.13-163378.33" + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $1\src10__data_o$next[3:0]$10588 + attribute \src "libresoc.v:166803.13-166803.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $1\src20__data_o$next[3:0]$10205 - attribute \src "libresoc.v:163385.13-163385.33" + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $1\src20__data_o$next[3:0]$10603 + attribute \src "libresoc.v:166810.13-166810.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $1\src30__data_o$next[3:0]$10219 - attribute \src "libresoc.v:163392.13-163392.33" + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $1\src30__data_o$next[3:0]$10617 + attribute \src "libresoc.v:166817.13-166817.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:163705.3-163734.6" - wire $1\wr_detect$10[0:0]$10241 - attribute \src "libresoc.v:163775.3-163804.6" - wire $1\wr_detect$13[0:0]$10255 - attribute \src "libresoc.v:163565.3-163594.6" - wire $1\wr_detect$4[0:0]$10213 - attribute \src "libresoc.v:163635.3-163664.6" - wire $1\wr_detect$7[0:0]$10227 - attribute \src "libresoc.v:163468.3-163497.6" + attribute \src "libresoc.v:167130.3-167159.6" + wire $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:167200.3-167229.6" + wire $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:166990.3-167019.6" + wire $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:167060.3-167089.6" + wire $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:166893.3-166922.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $2\r0__data_o$next[3:0]$10234 - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $2\r20__data_o$next[3:0]$10248 - attribute \src "libresoc.v:163498.3-163524.6" - wire width 4 $2\reg$next[3:0]$10200 - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $2\src10__data_o$next[3:0]$10191 - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $2\src20__data_o$next[3:0]$10206 - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $2\src30__data_o$next[3:0]$10220 - attribute \src "libresoc.v:163705.3-163734.6" - wire $2\wr_detect$10[0:0]$10242 - attribute \src "libresoc.v:163775.3-163804.6" - wire $2\wr_detect$13[0:0]$10256 - attribute \src "libresoc.v:163565.3-163594.6" - wire $2\wr_detect$4[0:0]$10214 - attribute \src "libresoc.v:163635.3-163664.6" - wire $2\wr_detect$7[0:0]$10228 - attribute \src "libresoc.v:163468.3-163497.6" + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $2\r0__data_o$next[3:0]$10632 + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $2\r20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:166923.3-166949.6" + wire width 4 $2\reg$next[3:0]$10598 + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $2\src10__data_o$next[3:0]$10589 + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $2\src20__data_o$next[3:0]$10604 + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $2\src30__data_o$next[3:0]$10618 + attribute \src "libresoc.v:167130.3-167159.6" + wire $2\wr_detect$10[0:0]$10640 + attribute \src "libresoc.v:167200.3-167229.6" + wire $2\wr_detect$13[0:0]$10654 + attribute \src "libresoc.v:166990.3-167019.6" + wire $2\wr_detect$4[0:0]$10612 + attribute \src "libresoc.v:167060.3-167089.6" + wire $2\wr_detect$7[0:0]$10626 + attribute \src "libresoc.v:166893.3-166922.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $3\r0__data_o$next[3:0]$10235 - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $3\r20__data_o$next[3:0]$10249 - attribute \src "libresoc.v:163498.3-163524.6" - wire width 4 $3\reg$next[3:0]$10201 - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $3\src10__data_o$next[3:0]$10192 - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $3\src20__data_o$next[3:0]$10207 - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $3\src30__data_o$next[3:0]$10221 - attribute \src "libresoc.v:163705.3-163734.6" - wire $3\wr_detect$10[0:0]$10243 - attribute \src "libresoc.v:163775.3-163804.6" - wire $3\wr_detect$13[0:0]$10257 - attribute \src "libresoc.v:163565.3-163594.6" - wire $3\wr_detect$4[0:0]$10215 - attribute \src "libresoc.v:163635.3-163664.6" - wire $3\wr_detect$7[0:0]$10229 - attribute \src "libresoc.v:163468.3-163497.6" + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $3\r0__data_o$next[3:0]$10633 + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $3\r20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:166923.3-166949.6" + wire width 4 $3\reg$next[3:0]$10599 + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $3\src10__data_o$next[3:0]$10590 + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $3\src20__data_o$next[3:0]$10605 + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $3\src30__data_o$next[3:0]$10619 + attribute \src "libresoc.v:167130.3-167159.6" + wire $3\wr_detect$10[0:0]$10641 + attribute \src "libresoc.v:167200.3-167229.6" + wire $3\wr_detect$13[0:0]$10655 + attribute \src "libresoc.v:166990.3-167019.6" + wire $3\wr_detect$4[0:0]$10613 + attribute \src "libresoc.v:167060.3-167089.6" + wire $3\wr_detect$7[0:0]$10627 + attribute \src "libresoc.v:166893.3-166922.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $4\r0__data_o$next[3:0]$10236 - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $4\r20__data_o$next[3:0]$10250 - attribute \src "libresoc.v:163498.3-163524.6" - wire width 4 $4\reg$next[3:0]$10202 - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $4\src10__data_o$next[3:0]$10193 - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $4\src20__data_o$next[3:0]$10208 - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $4\src30__data_o$next[3:0]$10222 - attribute \src "libresoc.v:163705.3-163734.6" - wire $4\wr_detect$10[0:0]$10244 - attribute \src "libresoc.v:163775.3-163804.6" - wire $4\wr_detect$13[0:0]$10258 - attribute \src "libresoc.v:163565.3-163594.6" - wire $4\wr_detect$4[0:0]$10216 - attribute \src "libresoc.v:163635.3-163664.6" - wire $4\wr_detect$7[0:0]$10230 - attribute \src "libresoc.v:163468.3-163497.6" + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $4\r0__data_o$next[3:0]$10634 + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $4\r20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:166923.3-166949.6" + wire width 4 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $4\src10__data_o$next[3:0]$10591 + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $4\src20__data_o$next[3:0]$10606 + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $4\src30__data_o$next[3:0]$10620 + attribute \src "libresoc.v:167130.3-167159.6" + wire $4\wr_detect$10[0:0]$10642 + attribute \src "libresoc.v:167200.3-167229.6" + wire $4\wr_detect$13[0:0]$10656 + attribute \src "libresoc.v:166990.3-167019.6" + wire $4\wr_detect$4[0:0]$10614 + attribute \src "libresoc.v:167060.3-167089.6" + wire $4\wr_detect$7[0:0]$10628 + attribute \src "libresoc.v:166893.3-166922.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $5\r0__data_o$next[3:0]$10237 - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $5\r20__data_o$next[3:0]$10251 - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $5\src10__data_o$next[3:0]$10194 - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $5\src20__data_o$next[3:0]$10209 - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $5\src30__data_o$next[3:0]$10223 - attribute \src "libresoc.v:163665.3-163704.6" - wire width 4 $6\r0__data_o$next[3:0]$10238 - attribute \src "libresoc.v:163735.3-163774.6" - wire width 4 $6\r20__data_o$next[3:0]$10252 - attribute \src "libresoc.v:163428.3-163467.6" - wire width 4 $6\src10__data_o$next[3:0]$10195 - attribute \src "libresoc.v:163525.3-163564.6" - wire width 4 $6\src20__data_o$next[3:0]$10210 - attribute \src "libresoc.v:163595.3-163634.6" - wire width 4 $6\src30__data_o$next[3:0]$10224 - attribute \src "libresoc.v:163411.17-163411.104" - wire $not$libresoc.v:163411$10177_Y - attribute \src "libresoc.v:163412.18-163412.105" - wire $not$libresoc.v:163412$10178_Y - attribute \src "libresoc.v:163413.17-163413.100" - wire $not$libresoc.v:163413$10179_Y - attribute \src "libresoc.v:163414.17-163414.103" - wire $not$libresoc.v:163414$10180_Y - attribute \src "libresoc.v:163415.17-163415.103" - wire $not$libresoc.v:163415$10181_Y + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $5\r0__data_o$next[3:0]$10635 + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $5\r20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $5\src10__data_o$next[3:0]$10592 + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $5\src20__data_o$next[3:0]$10607 + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $5\src30__data_o$next[3:0]$10621 + attribute \src "libresoc.v:167090.3-167129.6" + wire width 4 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:167160.3-167199.6" + wire width 4 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:166853.3-166892.6" + wire width 4 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:166950.3-166989.6" + wire width 4 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:167020.3-167059.6" + wire width 4 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:166836.17-166836.104" + wire $not$libresoc.v:166836$10575_Y + attribute \src "libresoc.v:166837.18-166837.105" + wire $not$libresoc.v:166837$10576_Y + attribute \src "libresoc.v:166838.17-166838.100" + wire $not$libresoc.v:166838$10577_Y + attribute \src "libresoc.v:166839.17-166839.103" + wire $not$libresoc.v:166839$10578_Y + attribute \src "libresoc.v:166840.17-166840.103" + wire $not$libresoc.v:166840$10579_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -336846,9 +344776,9 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest10__data_i @@ -336858,7 +344788,7 @@ module \reg_0 wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest20__wen - attribute \src "libresoc.v:163335.7-163335.15" + attribute \src "libresoc.v:166760.7-166760.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 12 \r0__data_o @@ -336909,152 +344839,152 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163411$10177 + cell $not $not$libresoc.v:166836$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:163411$10177_Y + connect \Y $not$libresoc.v:166836$10575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163412$10178 + cell $not $not$libresoc.v:166837$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:163412$10178_Y + connect \Y $not$libresoc.v:166837$10576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163413$10179 + cell $not $not$libresoc.v:166838$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:163413$10179_Y + connect \Y $not$libresoc.v:166838$10577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163414$10180 + cell $not $not$libresoc.v:166839$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:163414$10180_Y + connect \Y $not$libresoc.v:166839$10578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163415$10181 + cell $not $not$libresoc.v:166840$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:163415$10181_Y + connect \Y $not$libresoc.v:166840$10579_Y end - attribute \src "libresoc.v:163335.7-163335.20" - process $proc$libresoc.v:163335$10259 + attribute \src "libresoc.v:166760.7-166760.20" + process $proc$libresoc.v:166760$10657 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163360.13-163360.30" - process $proc$libresoc.v:163360$10260 + attribute \src "libresoc.v:166785.13-166785.30" + process $proc$libresoc.v:166785$10658 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:163367.13-163367.31" - process $proc$libresoc.v:163367$10261 + attribute \src "libresoc.v:166792.13-166792.31" + process $proc$libresoc.v:166792$10659 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:163373.13-163373.25" - process $proc$libresoc.v:163373$10262 + attribute \src "libresoc.v:166798.13-166798.25" + process $proc$libresoc.v:166798$10660 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:163378.13-163378.33" - process $proc$libresoc.v:163378$10263 + attribute \src "libresoc.v:166803.13-166803.33" + process $proc$libresoc.v:166803$10661 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:163385.13-163385.33" - process $proc$libresoc.v:163385$10264 + attribute \src "libresoc.v:166810.13-166810.33" + process $proc$libresoc.v:166810$10662 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:163392.13-163392.33" - process $proc$libresoc.v:163392$10265 + attribute \src "libresoc.v:166817.13-166817.33" + process $proc$libresoc.v:166817$10663 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:163416.3-163417.25" - process $proc$libresoc.v:163416$10182 + attribute \src "libresoc.v:166841.3-166842.25" + process $proc$libresoc.v:166841$10580 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:163418.3-163419.39" - process $proc$libresoc.v:163418$10183 + attribute \src "libresoc.v:166843.3-166844.39" + process $proc$libresoc.v:166843$10581 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:163420.3-163421.37" - process $proc$libresoc.v:163420$10184 + attribute \src "libresoc.v:166845.3-166846.37" + process $proc$libresoc.v:166845$10582 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:163422.3-163423.43" - process $proc$libresoc.v:163422$10185 + attribute \src "libresoc.v:166847.3-166848.43" + process $proc$libresoc.v:166847$10583 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:163424.3-163425.43" - process $proc$libresoc.v:163424$10186 + attribute \src "libresoc.v:166849.3-166850.43" + process $proc$libresoc.v:166849$10584 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:163426.3-163427.43" - process $proc$libresoc.v:163426$10187 + attribute \src "libresoc.v:166851.3-166852.43" + process $proc$libresoc.v:166851$10585 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:163428.3-163467.6" - process $proc$libresoc.v:163428$10188 + attribute \src "libresoc.v:166853.3-166892.6" + process $proc$libresoc.v:166853$10586 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10189 $6\src10__data_o$next[3:0]$10195 - attribute \src "libresoc.v:163429.5-163429.29" + assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 + attribute \src "libresoc.v:166854.5-166854.29" switch \initial - attribute \src "libresoc.v:163429.9-163429.17" + attribute \src "libresoc.v:166854.9-166854.17" case 1'1 case end @@ -337066,66 +344996,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10190 $5\src10__data_o$next[3:0]$10194 + assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10191 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10191 4'0000 + assign $2\src10__data_o$next[3:0]$10589 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10192 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10192 $2\src10__data_o$next[3:0]$10191 + assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10193 \w0__data_i + assign $4\src10__data_o$next[3:0]$10591 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10193 $3\src10__data_o$next[3:0]$10192 + assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10194 \reg + assign $5\src10__data_o$next[3:0]$10592 \reg case - assign $5\src10__data_o$next[3:0]$10194 $4\src10__data_o$next[3:0]$10193 + assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 end case - assign $1\src10__data_o$next[3:0]$10190 4'0000 + assign $1\src10__data_o$next[3:0]$10588 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10195 4'0000 + assign $6\src10__data_o$next[3:0]$10593 4'0000 case - assign $6\src10__data_o$next[3:0]$10195 $1\src10__data_o$next[3:0]$10190 + assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10189 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 end - attribute \src "libresoc.v:163468.3-163497.6" - process $proc$libresoc.v:163468$10196 + attribute \src "libresoc.v:166893.3-166922.6" + process $proc$libresoc.v:166893$10594 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:163469.5-163469.29" + attribute \src "libresoc.v:166894.5-166894.29" switch \initial - attribute \src "libresoc.v:163469.9-163469.17" + attribute \src "libresoc.v:166894.9-166894.17" case 1'1 case end @@ -337171,17 +345101,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:163498.3-163524.6" - process $proc$libresoc.v:163498$10197 + attribute \src "libresoc.v:166923.3-166949.6" + process $proc$libresoc.v:166923$10595 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10198 $4\reg$next[3:0]$10202 - attribute \src "libresoc.v:163499.5-163499.29" + assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 + attribute \src "libresoc.v:166924.5-166924.29" switch \initial - attribute \src "libresoc.v:163499.9-163499.17" + attribute \src "libresoc.v:166924.9-166924.17" case 1'1 case end @@ -337190,49 +345120,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10199 \dest10__data_i + assign $1\reg$next[3:0]$10597 \dest10__data_i case - assign $1\reg$next[3:0]$10199 \reg + assign $1\reg$next[3:0]$10597 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10200 \dest20__data_i + assign $2\reg$next[3:0]$10598 \dest20__data_i case - assign $2\reg$next[3:0]$10200 $1\reg$next[3:0]$10199 + assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10201 \w0__data_i + assign $3\reg$next[3:0]$10599 \w0__data_i case - assign $3\reg$next[3:0]$10201 $2\reg$next[3:0]$10200 + assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10202 4'0000 + assign $4\reg$next[3:0]$10600 4'0000 case - assign $4\reg$next[3:0]$10202 $3\reg$next[3:0]$10201 + assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 end sync always - update \reg$next $0\reg$next[3:0]$10198 + update \reg$next $0\reg$next[3:0]$10596 end - attribute \src "libresoc.v:163525.3-163564.6" - process $proc$libresoc.v:163525$10203 + attribute \src "libresoc.v:166950.3-166989.6" + process $proc$libresoc.v:166950$10601 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10204 $6\src20__data_o$next[3:0]$10210 - attribute \src "libresoc.v:163526.5-163526.29" + assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 + attribute \src "libresoc.v:166951.5-166951.29" switch \initial - attribute \src "libresoc.v:163526.9-163526.17" + attribute \src "libresoc.v:166951.9-166951.17" case 1'1 case end @@ -337244,66 +345174,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10205 $5\src20__data_o$next[3:0]$10209 + assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10206 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10206 4'0000 + assign $2\src20__data_o$next[3:0]$10604 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10207 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10207 $2\src20__data_o$next[3:0]$10206 + assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10208 \w0__data_i + assign $4\src20__data_o$next[3:0]$10606 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10208 $3\src20__data_o$next[3:0]$10207 + assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10209 \reg + assign $5\src20__data_o$next[3:0]$10607 \reg case - assign $5\src20__data_o$next[3:0]$10209 $4\src20__data_o$next[3:0]$10208 + assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 end case - assign $1\src20__data_o$next[3:0]$10205 4'0000 + assign $1\src20__data_o$next[3:0]$10603 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10210 4'0000 + assign $6\src20__data_o$next[3:0]$10608 4'0000 case - assign $6\src20__data_o$next[3:0]$10210 $1\src20__data_o$next[3:0]$10205 + assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10204 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 end - attribute \src "libresoc.v:163565.3-163594.6" - process $proc$libresoc.v:163565$10211 + attribute \src "libresoc.v:166990.3-167019.6" + process $proc$libresoc.v:166990$10609 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10212 $1\wr_detect$4[0:0]$10213 - attribute \src "libresoc.v:163566.5-163566.29" + assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 + attribute \src "libresoc.v:166991.5-166991.29" switch \initial - attribute \src "libresoc.v:163566.9-163566.17" + attribute \src "libresoc.v:166991.9-166991.17" case 1'1 case end @@ -337315,49 +345245,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10213 $4\wr_detect$4[0:0]$10216 + assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10214 1'1 + assign $2\wr_detect$4[0:0]$10612 1'1 case - assign $2\wr_detect$4[0:0]$10214 1'0 + assign $2\wr_detect$4[0:0]$10612 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10215 1'1 + assign $3\wr_detect$4[0:0]$10613 1'1 case - assign $3\wr_detect$4[0:0]$10215 $2\wr_detect$4[0:0]$10214 + assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10216 1'1 + assign $4\wr_detect$4[0:0]$10614 1'1 case - assign $4\wr_detect$4[0:0]$10216 $3\wr_detect$4[0:0]$10215 + assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 end case - assign $1\wr_detect$4[0:0]$10213 1'0 + assign $1\wr_detect$4[0:0]$10611 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10212 + update \wr_detect$4 $0\wr_detect$4[0:0]$10610 end - attribute \src "libresoc.v:163595.3-163634.6" - process $proc$libresoc.v:163595$10217 + attribute \src "libresoc.v:167020.3-167059.6" + process $proc$libresoc.v:167020$10615 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10218 $6\src30__data_o$next[3:0]$10224 - attribute \src "libresoc.v:163596.5-163596.29" + assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 + attribute \src "libresoc.v:167021.5-167021.29" switch \initial - attribute \src "libresoc.v:163596.9-163596.17" + attribute \src "libresoc.v:167021.9-167021.17" case 1'1 case end @@ -337369,66 +345299,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10219 $5\src30__data_o$next[3:0]$10223 + assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10220 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10220 4'0000 + assign $2\src30__data_o$next[3:0]$10618 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10221 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10221 $2\src30__data_o$next[3:0]$10220 + assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10222 \w0__data_i + assign $4\src30__data_o$next[3:0]$10620 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10222 $3\src30__data_o$next[3:0]$10221 + assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10223 \reg + assign $5\src30__data_o$next[3:0]$10621 \reg case - assign $5\src30__data_o$next[3:0]$10223 $4\src30__data_o$next[3:0]$10222 + assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 end case - assign $1\src30__data_o$next[3:0]$10219 4'0000 + assign $1\src30__data_o$next[3:0]$10617 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10224 4'0000 + assign $6\src30__data_o$next[3:0]$10622 4'0000 case - assign $6\src30__data_o$next[3:0]$10224 $1\src30__data_o$next[3:0]$10219 + assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10218 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 end - attribute \src "libresoc.v:163635.3-163664.6" - process $proc$libresoc.v:163635$10225 + attribute \src "libresoc.v:167060.3-167089.6" + process $proc$libresoc.v:167060$10623 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10226 $1\wr_detect$7[0:0]$10227 - attribute \src "libresoc.v:163636.5-163636.29" + assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 + attribute \src "libresoc.v:167061.5-167061.29" switch \initial - attribute \src "libresoc.v:163636.9-163636.17" + attribute \src "libresoc.v:167061.9-167061.17" case 1'1 case end @@ -337440,49 +345370,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10227 $4\wr_detect$7[0:0]$10230 + assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10228 1'1 + assign $2\wr_detect$7[0:0]$10626 1'1 case - assign $2\wr_detect$7[0:0]$10228 1'0 + assign $2\wr_detect$7[0:0]$10626 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10229 1'1 + assign $3\wr_detect$7[0:0]$10627 1'1 case - assign $3\wr_detect$7[0:0]$10229 $2\wr_detect$7[0:0]$10228 + assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10230 1'1 + assign $4\wr_detect$7[0:0]$10628 1'1 case - assign $4\wr_detect$7[0:0]$10230 $3\wr_detect$7[0:0]$10229 + assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 end case - assign $1\wr_detect$7[0:0]$10227 1'0 + assign $1\wr_detect$7[0:0]$10625 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10226 + update \wr_detect$7 $0\wr_detect$7[0:0]$10624 end - attribute \src "libresoc.v:163665.3-163704.6" - process $proc$libresoc.v:163665$10231 + attribute \src "libresoc.v:167090.3-167129.6" + process $proc$libresoc.v:167090$10629 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10232 $6\r0__data_o$next[3:0]$10238 - attribute \src "libresoc.v:163666.5-163666.29" + assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 + attribute \src "libresoc.v:167091.5-167091.29" switch \initial - attribute \src "libresoc.v:163666.9-163666.17" + attribute \src "libresoc.v:167091.9-167091.17" case 1'1 case end @@ -337494,66 +345424,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10233 $5\r0__data_o$next[3:0]$10237 + assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10234 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10234 4'0000 + assign $2\r0__data_o$next[3:0]$10632 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10235 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10235 $2\r0__data_o$next[3:0]$10234 + assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10236 \w0__data_i + assign $4\r0__data_o$next[3:0]$10634 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10236 $3\r0__data_o$next[3:0]$10235 + assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10237 \reg + assign $5\r0__data_o$next[3:0]$10635 \reg case - assign $5\r0__data_o$next[3:0]$10237 $4\r0__data_o$next[3:0]$10236 + assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 end case - assign $1\r0__data_o$next[3:0]$10233 4'0000 + assign $1\r0__data_o$next[3:0]$10631 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10238 4'0000 + assign $6\r0__data_o$next[3:0]$10636 4'0000 case - assign $6\r0__data_o$next[3:0]$10238 $1\r0__data_o$next[3:0]$10233 + assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10232 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 end - attribute \src "libresoc.v:163705.3-163734.6" - process $proc$libresoc.v:163705$10239 + attribute \src "libresoc.v:167130.3-167159.6" + process $proc$libresoc.v:167130$10637 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10240 $1\wr_detect$10[0:0]$10241 - attribute \src "libresoc.v:163706.5-163706.29" + assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 + attribute \src "libresoc.v:167131.5-167131.29" switch \initial - attribute \src "libresoc.v:163706.9-163706.17" + attribute \src "libresoc.v:167131.9-167131.17" case 1'1 case end @@ -337565,49 +345495,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10241 $4\wr_detect$10[0:0]$10244 + assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10242 1'1 + assign $2\wr_detect$10[0:0]$10640 1'1 case - assign $2\wr_detect$10[0:0]$10242 1'0 + assign $2\wr_detect$10[0:0]$10640 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10243 1'1 + assign $3\wr_detect$10[0:0]$10641 1'1 case - assign $3\wr_detect$10[0:0]$10243 $2\wr_detect$10[0:0]$10242 + assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10244 1'1 + assign $4\wr_detect$10[0:0]$10642 1'1 case - assign $4\wr_detect$10[0:0]$10244 $3\wr_detect$10[0:0]$10243 + assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 end case - assign $1\wr_detect$10[0:0]$10241 1'0 + assign $1\wr_detect$10[0:0]$10639 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10240 + update \wr_detect$10 $0\wr_detect$10[0:0]$10638 end - attribute \src "libresoc.v:163735.3-163774.6" - process $proc$libresoc.v:163735$10245 + attribute \src "libresoc.v:167160.3-167199.6" + process $proc$libresoc.v:167160$10643 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10246 $6\r20__data_o$next[3:0]$10252 - attribute \src "libresoc.v:163736.5-163736.29" + assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 + attribute \src "libresoc.v:167161.5-167161.29" switch \initial - attribute \src "libresoc.v:163736.9-163736.17" + attribute \src "libresoc.v:167161.9-167161.17" case 1'1 case end @@ -337619,66 +345549,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10247 $5\r20__data_o$next[3:0]$10251 + assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10248 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10248 4'0000 + assign $2\r20__data_o$next[3:0]$10646 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10249 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10249 $2\r20__data_o$next[3:0]$10248 + assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10250 \w0__data_i + assign $4\r20__data_o$next[3:0]$10648 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10250 $3\r20__data_o$next[3:0]$10249 + assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10251 \reg + assign $5\r20__data_o$next[3:0]$10649 \reg case - assign $5\r20__data_o$next[3:0]$10251 $4\r20__data_o$next[3:0]$10250 + assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 end case - assign $1\r20__data_o$next[3:0]$10247 4'0000 + assign $1\r20__data_o$next[3:0]$10645 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10252 4'0000 + assign $6\r20__data_o$next[3:0]$10650 4'0000 case - assign $6\r20__data_o$next[3:0]$10252 $1\r20__data_o$next[3:0]$10247 + assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10246 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 end - attribute \src "libresoc.v:163775.3-163804.6" - process $proc$libresoc.v:163775$10253 + attribute \src "libresoc.v:167200.3-167229.6" + process $proc$libresoc.v:167200$10651 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10254 $1\wr_detect$13[0:0]$10255 - attribute \src "libresoc.v:163776.5-163776.29" + assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 + attribute \src "libresoc.v:167201.5-167201.29" switch \initial - attribute \src "libresoc.v:163776.9-163776.17" + attribute \src "libresoc.v:167201.9-167201.17" case 1'1 case end @@ -337690,205 +345620,205 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10255 $4\wr_detect$13[0:0]$10258 + assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10256 1'1 + assign $2\wr_detect$13[0:0]$10654 1'1 case - assign $2\wr_detect$13[0:0]$10256 1'0 + assign $2\wr_detect$13[0:0]$10654 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10257 1'1 + assign $3\wr_detect$13[0:0]$10655 1'1 case - assign $3\wr_detect$13[0:0]$10257 $2\wr_detect$13[0:0]$10256 + assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10258 1'1 + assign $4\wr_detect$13[0:0]$10656 1'1 case - assign $4\wr_detect$13[0:0]$10258 $3\wr_detect$13[0:0]$10257 + assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 end case - assign $1\wr_detect$13[0:0]$10255 1'0 + assign $1\wr_detect$13[0:0]$10653 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10254 + update \wr_detect$13 $0\wr_detect$13[0:0]$10652 end - connect \$9 $not$libresoc.v:163411$10177_Y - connect \$12 $not$libresoc.v:163412$10178_Y - connect \$1 $not$libresoc.v:163413$10179_Y - connect \$3 $not$libresoc.v:163414$10180_Y - connect \$6 $not$libresoc.v:163415$10181_Y + connect \$9 $not$libresoc.v:166836$10575_Y + connect \$12 $not$libresoc.v:166837$10576_Y + connect \$1 $not$libresoc.v:166838$10577_Y + connect \$3 $not$libresoc.v:166839$10578_Y + connect \$6 $not$libresoc.v:166840$10579_Y end -attribute \src "libresoc.v:163809.1-164254.10" +attribute \src "libresoc.v:167234.1-167679.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" -module \reg_0$129 - attribute \src "libresoc.v:163810.7-163810.20" +module \reg_0$132 + attribute \src "libresoc.v:167235.7-167235.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $0\r0__data_o$next[1:0]$10318 - attribute \src "libresoc.v:163885.3-163886.37" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $0\r0__data_o$next[1:0]$10716 + attribute \src "libresoc.v:167310.3-167311.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $0\reg$next[1:0]$10334 - attribute \src "libresoc.v:163883.3-163884.25" + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $0\reg$next[1:0]$10732 + attribute \src "libresoc.v:167308.3-167309.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $0\src10__data_o$next[1:0]$10276 - attribute \src "libresoc.v:163891.3-163892.43" + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $0\src10__data_o$next[1:0]$10674 + attribute \src "libresoc.v:167316.3-167317.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $0\src20__data_o$next[1:0]$10286 - attribute \src "libresoc.v:163889.3-163890.43" + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $0\src20__data_o$next[1:0]$10684 + attribute \src "libresoc.v:167314.3-167315.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $0\src30__data_o$next[1:0]$10302 - attribute \src "libresoc.v:163887.3-163888.43" + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $0\src30__data_o$next[1:0]$10700 + attribute \src "libresoc.v:167312.3-167313.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:164185.3-164220.6" - wire $0\wr_detect$10[0:0]$10327 - attribute \src "libresoc.v:164021.3-164056.6" - wire $0\wr_detect$4[0:0]$10295 - attribute \src "libresoc.v:164103.3-164138.6" - wire $0\wr_detect$7[0:0]$10311 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167610.3-167645.6" + wire $0\wr_detect$10[0:0]$10725 + attribute \src "libresoc.v:167446.3-167481.6" + wire $0\wr_detect$4[0:0]$10693 + attribute \src "libresoc.v:167528.3-167563.6" + wire $0\wr_detect$7[0:0]$10709 + attribute \src "libresoc.v:167364.3-167399.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $1\r0__data_o$next[1:0]$10319 - attribute \src "libresoc.v:163837.13-163837.30" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $1\r0__data_o$next[1:0]$10717 + attribute \src "libresoc.v:167262.13-167262.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $1\reg$next[1:0]$10335 - attribute \src "libresoc.v:163843.13-163843.25" + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $1\reg$next[1:0]$10733 + attribute \src "libresoc.v:167268.13-167268.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $1\src10__data_o$next[1:0]$10277 - attribute \src "libresoc.v:163848.13-163848.33" + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $1\src10__data_o$next[1:0]$10675 + attribute \src "libresoc.v:167273.13-167273.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $1\src20__data_o$next[1:0]$10287 - attribute \src "libresoc.v:163855.13-163855.33" + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $1\src20__data_o$next[1:0]$10685 + attribute \src "libresoc.v:167280.13-167280.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $1\src30__data_o$next[1:0]$10303 - attribute \src "libresoc.v:163862.13-163862.33" + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $1\src30__data_o$next[1:0]$10701 + attribute \src "libresoc.v:167287.13-167287.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:164185.3-164220.6" - wire $1\wr_detect$10[0:0]$10328 - attribute \src "libresoc.v:164021.3-164056.6" - wire $1\wr_detect$4[0:0]$10296 - attribute \src "libresoc.v:164103.3-164138.6" - wire $1\wr_detect$7[0:0]$10312 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167610.3-167645.6" + wire $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:167446.3-167481.6" + wire $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:167528.3-167563.6" + wire $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:167364.3-167399.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $2\r0__data_o$next[1:0]$10320 - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $2\reg$next[1:0]$10336 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $2\src10__data_o$next[1:0]$10278 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $2\src20__data_o$next[1:0]$10288 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $2\src30__data_o$next[1:0]$10304 - attribute \src "libresoc.v:164185.3-164220.6" - wire $2\wr_detect$10[0:0]$10329 - attribute \src "libresoc.v:164021.3-164056.6" - wire $2\wr_detect$4[0:0]$10297 - attribute \src "libresoc.v:164103.3-164138.6" - wire $2\wr_detect$7[0:0]$10313 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $2\r0__data_o$next[1:0]$10718 + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $2\reg$next[1:0]$10734 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $2\src10__data_o$next[1:0]$10676 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $2\src20__data_o$next[1:0]$10686 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $2\src30__data_o$next[1:0]$10702 + attribute \src "libresoc.v:167610.3-167645.6" + wire $2\wr_detect$10[0:0]$10727 + attribute \src "libresoc.v:167446.3-167481.6" + wire $2\wr_detect$4[0:0]$10695 + attribute \src "libresoc.v:167528.3-167563.6" + wire $2\wr_detect$7[0:0]$10711 + attribute \src "libresoc.v:167364.3-167399.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $3\r0__data_o$next[1:0]$10321 - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $3\reg$next[1:0]$10337 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $3\src10__data_o$next[1:0]$10279 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $3\src20__data_o$next[1:0]$10289 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $3\src30__data_o$next[1:0]$10305 - attribute \src "libresoc.v:164185.3-164220.6" - wire $3\wr_detect$10[0:0]$10330 - attribute \src "libresoc.v:164021.3-164056.6" - wire $3\wr_detect$4[0:0]$10298 - attribute \src "libresoc.v:164103.3-164138.6" - wire $3\wr_detect$7[0:0]$10314 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $3\r0__data_o$next[1:0]$10719 + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $3\reg$next[1:0]$10735 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $3\src10__data_o$next[1:0]$10677 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $3\src20__data_o$next[1:0]$10687 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $3\src30__data_o$next[1:0]$10703 + attribute \src "libresoc.v:167610.3-167645.6" + wire $3\wr_detect$10[0:0]$10728 + attribute \src "libresoc.v:167446.3-167481.6" + wire $3\wr_detect$4[0:0]$10696 + attribute \src "libresoc.v:167528.3-167563.6" + wire $3\wr_detect$7[0:0]$10712 + attribute \src "libresoc.v:167364.3-167399.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $4\r0__data_o$next[1:0]$10322 - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $4\reg$next[1:0]$10338 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $4\src10__data_o$next[1:0]$10280 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $4\src20__data_o$next[1:0]$10290 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $4\src30__data_o$next[1:0]$10306 - attribute \src "libresoc.v:164185.3-164220.6" - wire $4\wr_detect$10[0:0]$10331 - attribute \src "libresoc.v:164021.3-164056.6" - wire $4\wr_detect$4[0:0]$10299 - attribute \src "libresoc.v:164103.3-164138.6" - wire $4\wr_detect$7[0:0]$10315 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $4\r0__data_o$next[1:0]$10720 + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $4\reg$next[1:0]$10736 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $4\src10__data_o$next[1:0]$10678 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $4\src20__data_o$next[1:0]$10688 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $4\src30__data_o$next[1:0]$10704 + attribute \src "libresoc.v:167610.3-167645.6" + wire $4\wr_detect$10[0:0]$10729 + attribute \src "libresoc.v:167446.3-167481.6" + wire $4\wr_detect$4[0:0]$10697 + attribute \src "libresoc.v:167528.3-167563.6" + wire $4\wr_detect$7[0:0]$10713 + attribute \src "libresoc.v:167364.3-167399.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $5\r0__data_o$next[1:0]$10323 - attribute \src "libresoc.v:164221.3-164253.6" - wire width 2 $5\reg$next[1:0]$10339 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $5\src10__data_o$next[1:0]$10281 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $5\src20__data_o$next[1:0]$10291 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $5\src30__data_o$next[1:0]$10307 - attribute \src "libresoc.v:164185.3-164220.6" - wire $5\wr_detect$10[0:0]$10332 - attribute \src "libresoc.v:164021.3-164056.6" - wire $5\wr_detect$4[0:0]$10300 - attribute \src "libresoc.v:164103.3-164138.6" - wire $5\wr_detect$7[0:0]$10316 - attribute \src "libresoc.v:163939.3-163974.6" + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $5\r0__data_o$next[1:0]$10721 + attribute \src "libresoc.v:167646.3-167678.6" + wire width 2 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $5\src10__data_o$next[1:0]$10679 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $5\src20__data_o$next[1:0]$10689 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $5\src30__data_o$next[1:0]$10705 + attribute \src "libresoc.v:167610.3-167645.6" + wire $5\wr_detect$10[0:0]$10730 + attribute \src "libresoc.v:167446.3-167481.6" + wire $5\wr_detect$4[0:0]$10698 + attribute \src "libresoc.v:167528.3-167563.6" + wire $5\wr_detect$7[0:0]$10714 + attribute \src "libresoc.v:167364.3-167399.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $6\r0__data_o$next[1:0]$10324 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $6\src10__data_o$next[1:0]$10282 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $6\src20__data_o$next[1:0]$10292 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $6\src30__data_o$next[1:0]$10308 - attribute \src "libresoc.v:164139.3-164184.6" - wire width 2 $7\r0__data_o$next[1:0]$10325 - attribute \src "libresoc.v:163893.3-163938.6" - wire width 2 $7\src10__data_o$next[1:0]$10283 - attribute \src "libresoc.v:163975.3-164020.6" - wire width 2 $7\src20__data_o$next[1:0]$10293 - attribute \src "libresoc.v:164057.3-164102.6" - wire width 2 $7\src30__data_o$next[1:0]$10309 - attribute \src "libresoc.v:163879.17-163879.104" - wire $not$libresoc.v:163879$10266_Y - attribute \src "libresoc.v:163880.17-163880.100" - wire $not$libresoc.v:163880$10267_Y - attribute \src "libresoc.v:163881.17-163881.103" - wire $not$libresoc.v:163881$10268_Y - attribute \src "libresoc.v:163882.17-163882.103" - wire $not$libresoc.v:163882$10269_Y + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $6\r0__data_o$next[1:0]$10722 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $6\src10__data_o$next[1:0]$10680 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $6\src20__data_o$next[1:0]$10690 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $6\src30__data_o$next[1:0]$10706 + attribute \src "libresoc.v:167564.3-167609.6" + wire width 2 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:167318.3-167363.6" + wire width 2 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:167400.3-167445.6" + wire width 2 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:167482.3-167527.6" + wire width 2 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:167304.17-167304.104" + wire $not$libresoc.v:167304$10664_Y + attribute \src "libresoc.v:167305.17-167305.100" + wire $not$libresoc.v:167305$10665_Y + attribute \src "libresoc.v:167306.17-167306.103" + wire $not$libresoc.v:167306$10666_Y + attribute \src "libresoc.v:167307.17-167307.103" + wire $not$libresoc.v:167307$10667_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -337897,9 +345827,9 @@ module \reg_0$129 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 input 9 \dest10__data_i @@ -337913,7 +345843,7 @@ module \reg_0$129 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 12 \dest30__wen - attribute \src "libresoc.v:163810.7-163810.15" + attribute \src "libresoc.v:167235.7-167235.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 output 14 \r0__data_o @@ -337956,129 +345886,129 @@ module \reg_0$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163879$10266 + cell $not $not$libresoc.v:167304$10664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:163879$10266_Y + connect \Y $not$libresoc.v:167304$10664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163880$10267 + cell $not $not$libresoc.v:167305$10665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:163880$10267_Y + connect \Y $not$libresoc.v:167305$10665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163881$10268 + cell $not $not$libresoc.v:167306$10666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:163881$10268_Y + connect \Y $not$libresoc.v:167306$10666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:163882$10269 + cell $not $not$libresoc.v:167307$10667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:163882$10269_Y + connect \Y $not$libresoc.v:167307$10667_Y end - attribute \src "libresoc.v:163810.7-163810.20" - process $proc$libresoc.v:163810$10340 + attribute \src "libresoc.v:167235.7-167235.20" + process $proc$libresoc.v:167235$10738 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163837.13-163837.30" - process $proc$libresoc.v:163837$10341 + attribute \src "libresoc.v:167262.13-167262.30" + process $proc$libresoc.v:167262$10739 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:163843.13-163843.25" - process $proc$libresoc.v:163843$10342 + attribute \src "libresoc.v:167268.13-167268.25" + process $proc$libresoc.v:167268$10740 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:163848.13-163848.33" - process $proc$libresoc.v:163848$10343 + attribute \src "libresoc.v:167273.13-167273.33" + process $proc$libresoc.v:167273$10741 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:163855.13-163855.33" - process $proc$libresoc.v:163855$10344 + attribute \src "libresoc.v:167280.13-167280.33" + process $proc$libresoc.v:167280$10742 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:163862.13-163862.33" - process $proc$libresoc.v:163862$10345 + attribute \src "libresoc.v:167287.13-167287.33" + process $proc$libresoc.v:167287$10743 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:163883.3-163884.25" - process $proc$libresoc.v:163883$10270 + attribute \src "libresoc.v:167308.3-167309.25" + process $proc$libresoc.v:167308$10668 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:163885.3-163886.37" - process $proc$libresoc.v:163885$10271 + attribute \src "libresoc.v:167310.3-167311.37" + process $proc$libresoc.v:167310$10669 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:163887.3-163888.43" - process $proc$libresoc.v:163887$10272 + attribute \src "libresoc.v:167312.3-167313.43" + process $proc$libresoc.v:167312$10670 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:163889.3-163890.43" - process $proc$libresoc.v:163889$10273 + attribute \src "libresoc.v:167314.3-167315.43" + process $proc$libresoc.v:167314$10671 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:163891.3-163892.43" - process $proc$libresoc.v:163891$10274 + attribute \src "libresoc.v:167316.3-167317.43" + process $proc$libresoc.v:167316$10672 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:163893.3-163938.6" - process $proc$libresoc.v:163893$10275 + attribute \src "libresoc.v:167318.3-167363.6" + process $proc$libresoc.v:167318$10673 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10276 $7\src10__data_o$next[1:0]$10283 - attribute \src "libresoc.v:163894.5-163894.29" + assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 + attribute \src "libresoc.v:167319.5-167319.29" switch \initial - attribute \src "libresoc.v:163894.9-163894.17" + attribute \src "libresoc.v:167319.9-167319.17" case 1'1 case end @@ -338091,75 +346021,75 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10277 $6\src10__data_o$next[1:0]$10282 + assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10278 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10278 2'00 + assign $2\src10__data_o$next[1:0]$10676 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10279 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10279 $2\src10__data_o$next[1:0]$10278 + assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10280 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10280 $3\src10__data_o$next[1:0]$10279 + assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10281 \w0__data_i + assign $5\src10__data_o$next[1:0]$10679 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10281 $4\src10__data_o$next[1:0]$10280 + assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10282 \reg + assign $6\src10__data_o$next[1:0]$10680 \reg case - assign $6\src10__data_o$next[1:0]$10282 $5\src10__data_o$next[1:0]$10281 + assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 end case - assign $1\src10__data_o$next[1:0]$10277 2'00 + assign $1\src10__data_o$next[1:0]$10675 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10283 2'00 + assign $7\src10__data_o$next[1:0]$10681 2'00 case - assign $7\src10__data_o$next[1:0]$10283 $1\src10__data_o$next[1:0]$10277 + assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10276 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 end - attribute \src "libresoc.v:163939.3-163974.6" - process $proc$libresoc.v:163939$10284 + attribute \src "libresoc.v:167364.3-167399.6" + process $proc$libresoc.v:167364$10682 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:163940.5-163940.29" + attribute \src "libresoc.v:167365.5-167365.29" switch \initial - attribute \src "libresoc.v:163940.9-163940.17" + attribute \src "libresoc.v:167365.9-167365.17" case 1'1 case end @@ -338215,15 +346145,15 @@ module \reg_0$129 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:163975.3-164020.6" - process $proc$libresoc.v:163975$10285 + attribute \src "libresoc.v:167400.3-167445.6" + process $proc$libresoc.v:167400$10683 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10286 $7\src20__data_o$next[1:0]$10293 - attribute \src "libresoc.v:163976.5-163976.29" + assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 + attribute \src "libresoc.v:167401.5-167401.29" switch \initial - attribute \src "libresoc.v:163976.9-163976.17" + attribute \src "libresoc.v:167401.9-167401.17" case 1'1 case end @@ -338236,75 +346166,75 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10287 $6\src20__data_o$next[1:0]$10292 + assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10288 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10288 2'00 + assign $2\src20__data_o$next[1:0]$10686 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10289 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10289 $2\src20__data_o$next[1:0]$10288 + assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10290 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10290 $3\src20__data_o$next[1:0]$10289 + assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10291 \w0__data_i + assign $5\src20__data_o$next[1:0]$10689 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10291 $4\src20__data_o$next[1:0]$10290 + assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10292 \reg + assign $6\src20__data_o$next[1:0]$10690 \reg case - assign $6\src20__data_o$next[1:0]$10292 $5\src20__data_o$next[1:0]$10291 + assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 end case - assign $1\src20__data_o$next[1:0]$10287 2'00 + assign $1\src20__data_o$next[1:0]$10685 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10293 2'00 + assign $7\src20__data_o$next[1:0]$10691 2'00 case - assign $7\src20__data_o$next[1:0]$10293 $1\src20__data_o$next[1:0]$10287 + assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10286 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 end - attribute \src "libresoc.v:164021.3-164056.6" - process $proc$libresoc.v:164021$10294 + attribute \src "libresoc.v:167446.3-167481.6" + process $proc$libresoc.v:167446$10692 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10295 $1\wr_detect$4[0:0]$10296 - attribute \src "libresoc.v:164022.5-164022.29" + assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 + attribute \src "libresoc.v:167447.5-167447.29" switch \initial - attribute \src "libresoc.v:164022.9-164022.17" + attribute \src "libresoc.v:167447.9-167447.17" case 1'1 case end @@ -338317,58 +346247,58 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10296 $5\wr_detect$4[0:0]$10300 + assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10297 1'1 + assign $2\wr_detect$4[0:0]$10695 1'1 case - assign $2\wr_detect$4[0:0]$10297 1'0 + assign $2\wr_detect$4[0:0]$10695 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10298 1'1 + assign $3\wr_detect$4[0:0]$10696 1'1 case - assign $3\wr_detect$4[0:0]$10298 $2\wr_detect$4[0:0]$10297 + assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10299 1'1 + assign $4\wr_detect$4[0:0]$10697 1'1 case - assign $4\wr_detect$4[0:0]$10299 $3\wr_detect$4[0:0]$10298 + assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10300 1'1 + assign $5\wr_detect$4[0:0]$10698 1'1 case - assign $5\wr_detect$4[0:0]$10300 $4\wr_detect$4[0:0]$10299 + assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 end case - assign $1\wr_detect$4[0:0]$10296 1'0 + assign $1\wr_detect$4[0:0]$10694 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10295 + update \wr_detect$4 $0\wr_detect$4[0:0]$10693 end - attribute \src "libresoc.v:164057.3-164102.6" - process $proc$libresoc.v:164057$10301 + attribute \src "libresoc.v:167482.3-167527.6" + process $proc$libresoc.v:167482$10699 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10302 $7\src30__data_o$next[1:0]$10309 - attribute \src "libresoc.v:164058.5-164058.29" + assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 + attribute \src "libresoc.v:167483.5-167483.29" switch \initial - attribute \src "libresoc.v:164058.9-164058.17" + attribute \src "libresoc.v:167483.9-167483.17" case 1'1 case end @@ -338381,75 +346311,75 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10303 $6\src30__data_o$next[1:0]$10308 + assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10304 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10304 2'00 + assign $2\src30__data_o$next[1:0]$10702 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10305 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10305 $2\src30__data_o$next[1:0]$10304 + assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10306 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10306 $3\src30__data_o$next[1:0]$10305 + assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10307 \w0__data_i + assign $5\src30__data_o$next[1:0]$10705 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10307 $4\src30__data_o$next[1:0]$10306 + assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10308 \reg + assign $6\src30__data_o$next[1:0]$10706 \reg case - assign $6\src30__data_o$next[1:0]$10308 $5\src30__data_o$next[1:0]$10307 + assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 end case - assign $1\src30__data_o$next[1:0]$10303 2'00 + assign $1\src30__data_o$next[1:0]$10701 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10309 2'00 + assign $7\src30__data_o$next[1:0]$10707 2'00 case - assign $7\src30__data_o$next[1:0]$10309 $1\src30__data_o$next[1:0]$10303 + assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10302 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 end - attribute \src "libresoc.v:164103.3-164138.6" - process $proc$libresoc.v:164103$10310 + attribute \src "libresoc.v:167528.3-167563.6" + process $proc$libresoc.v:167528$10708 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10311 $1\wr_detect$7[0:0]$10312 - attribute \src "libresoc.v:164104.5-164104.29" + assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 + attribute \src "libresoc.v:167529.5-167529.29" switch \initial - attribute \src "libresoc.v:164104.9-164104.17" + attribute \src "libresoc.v:167529.9-167529.17" case 1'1 case end @@ -338462,58 +346392,58 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10312 $5\wr_detect$7[0:0]$10316 + assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10313 1'1 + assign $2\wr_detect$7[0:0]$10711 1'1 case - assign $2\wr_detect$7[0:0]$10313 1'0 + assign $2\wr_detect$7[0:0]$10711 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10314 1'1 + assign $3\wr_detect$7[0:0]$10712 1'1 case - assign $3\wr_detect$7[0:0]$10314 $2\wr_detect$7[0:0]$10313 + assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10315 1'1 + assign $4\wr_detect$7[0:0]$10713 1'1 case - assign $4\wr_detect$7[0:0]$10315 $3\wr_detect$7[0:0]$10314 + assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10316 1'1 + assign $5\wr_detect$7[0:0]$10714 1'1 case - assign $5\wr_detect$7[0:0]$10316 $4\wr_detect$7[0:0]$10315 + assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 end case - assign $1\wr_detect$7[0:0]$10312 1'0 + assign $1\wr_detect$7[0:0]$10710 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10311 + update \wr_detect$7 $0\wr_detect$7[0:0]$10709 end - attribute \src "libresoc.v:164139.3-164184.6" - process $proc$libresoc.v:164139$10317 + attribute \src "libresoc.v:167564.3-167609.6" + process $proc$libresoc.v:167564$10715 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10318 $7\r0__data_o$next[1:0]$10325 - attribute \src "libresoc.v:164140.5-164140.29" + assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 + attribute \src "libresoc.v:167565.5-167565.29" switch \initial - attribute \src "libresoc.v:164140.9-164140.17" + attribute \src "libresoc.v:167565.9-167565.17" case 1'1 case end @@ -338526,75 +346456,75 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10319 $6\r0__data_o$next[1:0]$10324 + assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10320 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10320 2'00 + assign $2\r0__data_o$next[1:0]$10718 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10321 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10321 $2\r0__data_o$next[1:0]$10320 + assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10322 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10322 $3\r0__data_o$next[1:0]$10321 + assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10323 \w0__data_i + assign $5\r0__data_o$next[1:0]$10721 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10323 $4\r0__data_o$next[1:0]$10322 + assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10324 \reg + assign $6\r0__data_o$next[1:0]$10722 \reg case - assign $6\r0__data_o$next[1:0]$10324 $5\r0__data_o$next[1:0]$10323 + assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 end case - assign $1\r0__data_o$next[1:0]$10319 2'00 + assign $1\r0__data_o$next[1:0]$10717 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10325 2'00 + assign $7\r0__data_o$next[1:0]$10723 2'00 case - assign $7\r0__data_o$next[1:0]$10325 $1\r0__data_o$next[1:0]$10319 + assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10318 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 end - attribute \src "libresoc.v:164185.3-164220.6" - process $proc$libresoc.v:164185$10326 + attribute \src "libresoc.v:167610.3-167645.6" + process $proc$libresoc.v:167610$10724 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10327 $1\wr_detect$10[0:0]$10328 - attribute \src "libresoc.v:164186.5-164186.29" + assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 + attribute \src "libresoc.v:167611.5-167611.29" switch \initial - attribute \src "libresoc.v:164186.9-164186.17" + attribute \src "libresoc.v:167611.9-167611.17" case 1'1 case end @@ -338607,61 +346537,61 @@ module \reg_0$129 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10328 $5\wr_detect$10[0:0]$10332 + assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10329 1'1 + assign $2\wr_detect$10[0:0]$10727 1'1 case - assign $2\wr_detect$10[0:0]$10329 1'0 + assign $2\wr_detect$10[0:0]$10727 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10330 1'1 + assign $3\wr_detect$10[0:0]$10728 1'1 case - assign $3\wr_detect$10[0:0]$10330 $2\wr_detect$10[0:0]$10329 + assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10331 1'1 + assign $4\wr_detect$10[0:0]$10729 1'1 case - assign $4\wr_detect$10[0:0]$10331 $3\wr_detect$10[0:0]$10330 + assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10332 1'1 + assign $5\wr_detect$10[0:0]$10730 1'1 case - assign $5\wr_detect$10[0:0]$10332 $4\wr_detect$10[0:0]$10331 + assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 end case - assign $1\wr_detect$10[0:0]$10328 1'0 + assign $1\wr_detect$10[0:0]$10726 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10327 + update \wr_detect$10 $0\wr_detect$10[0:0]$10725 end - attribute \src "libresoc.v:164221.3-164253.6" - process $proc$libresoc.v:164221$10333 + attribute \src "libresoc.v:167646.3-167678.6" + process $proc$libresoc.v:167646$10731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10334 $5\reg$next[1:0]$10339 - attribute \src "libresoc.v:164222.5-164222.29" + assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 + attribute \src "libresoc.v:167647.5-167647.29" switch \initial - attribute \src "libresoc.v:164222.9-164222.17" + attribute \src "libresoc.v:167647.9-167647.17" case 1'1 case end @@ -338670,135 +346600,135 @@ module \reg_0$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10335 \dest10__data_i + assign $1\reg$next[1:0]$10733 \dest10__data_i case - assign $1\reg$next[1:0]$10335 \reg + assign $1\reg$next[1:0]$10733 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10336 \dest20__data_i + assign $2\reg$next[1:0]$10734 \dest20__data_i case - assign $2\reg$next[1:0]$10336 $1\reg$next[1:0]$10335 + assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10337 \dest30__data_i + assign $3\reg$next[1:0]$10735 \dest30__data_i case - assign $3\reg$next[1:0]$10337 $2\reg$next[1:0]$10336 + assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10338 \w0__data_i + assign $4\reg$next[1:0]$10736 \w0__data_i case - assign $4\reg$next[1:0]$10338 $3\reg$next[1:0]$10337 + assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10339 2'00 + assign $5\reg$next[1:0]$10737 2'00 case - assign $5\reg$next[1:0]$10339 $4\reg$next[1:0]$10338 + assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 end sync always - update \reg$next $0\reg$next[1:0]$10334 + update \reg$next $0\reg$next[1:0]$10732 end - connect \$9 $not$libresoc.v:163879$10266_Y - connect \$1 $not$libresoc.v:163880$10267_Y - connect \$3 $not$libresoc.v:163881$10268_Y - connect \$6 $not$libresoc.v:163882$10269_Y + connect \$9 $not$libresoc.v:167304$10664_Y + connect \$1 $not$libresoc.v:167305$10665_Y + connect \$3 $not$libresoc.v:167306$10666_Y + connect \$6 $not$libresoc.v:167307$10667_Y end -attribute \src "libresoc.v:164258.1-164477.10" +attribute \src "libresoc.v:167683.1-167902.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" -module \reg_0$132 - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $0\cia0__data_o$next[63:0]$10352 - attribute \src "libresoc.v:164308.3-164309.41" +module \reg_0$135 + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $0\cia0__data_o$next[63:0]$10750 + attribute \src "libresoc.v:167733.3-167734.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:164259.7-164259.20" + attribute \src "libresoc.v:167684.7-167684.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $0\msr0__data_o$next[63:0]$10361 - attribute \src "libresoc.v:164306.3-164307.41" + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $0\msr0__data_o$next[63:0]$10759 + attribute \src "libresoc.v:167731.3-167732.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:164450.3-164476.6" - wire width 64 $0\reg$next[63:0]$10375 - attribute \src "libresoc.v:164304.3-164305.25" + attribute \src "libresoc.v:167875.3-167901.6" + wire width 64 $0\reg$next[63:0]$10773 + attribute \src "libresoc.v:167729.3-167730.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:164420.3-164449.6" - wire $0\wr_detect$4[0:0]$10369 - attribute \src "libresoc.v:164350.3-164379.6" + attribute \src "libresoc.v:167845.3-167874.6" + wire $0\wr_detect$4[0:0]$10767 + attribute \src "libresoc.v:167775.3-167804.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $1\cia0__data_o$next[63:0]$10353 - attribute \src "libresoc.v:164266.14-164266.49" + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $1\cia0__data_o$next[63:0]$10751 + attribute \src "libresoc.v:167691.14-167691.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $1\msr0__data_o$next[63:0]$10362 - attribute \src "libresoc.v:164283.14-164283.49" + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $1\msr0__data_o$next[63:0]$10760 + attribute \src "libresoc.v:167708.14-167708.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:164450.3-164476.6" - wire width 64 $1\reg$next[63:0]$10376 - attribute \src "libresoc.v:164295.14-164295.42" + attribute \src "libresoc.v:167875.3-167901.6" + wire width 64 $1\reg$next[63:0]$10774 + attribute \src "libresoc.v:167720.14-167720.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:164420.3-164449.6" - wire $1\wr_detect$4[0:0]$10370 - attribute \src "libresoc.v:164350.3-164379.6" + attribute \src "libresoc.v:167845.3-167874.6" + wire $1\wr_detect$4[0:0]$10768 + attribute \src "libresoc.v:167775.3-167804.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $2\cia0__data_o$next[63:0]$10354 - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $2\msr0__data_o$next[63:0]$10363 - attribute \src "libresoc.v:164450.3-164476.6" - wire width 64 $2\reg$next[63:0]$10377 - attribute \src "libresoc.v:164420.3-164449.6" - wire $2\wr_detect$4[0:0]$10371 - attribute \src "libresoc.v:164350.3-164379.6" + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $2\cia0__data_o$next[63:0]$10752 + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $2\msr0__data_o$next[63:0]$10761 + attribute \src "libresoc.v:167875.3-167901.6" + wire width 64 $2\reg$next[63:0]$10775 + attribute \src "libresoc.v:167845.3-167874.6" + wire $2\wr_detect$4[0:0]$10769 + attribute \src "libresoc.v:167775.3-167804.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $3\cia0__data_o$next[63:0]$10355 - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $3\msr0__data_o$next[63:0]$10364 - attribute \src "libresoc.v:164450.3-164476.6" - wire width 64 $3\reg$next[63:0]$10378 - attribute \src "libresoc.v:164420.3-164449.6" - wire $3\wr_detect$4[0:0]$10372 - attribute \src "libresoc.v:164350.3-164379.6" + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $3\cia0__data_o$next[63:0]$10753 + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $3\msr0__data_o$next[63:0]$10762 + attribute \src "libresoc.v:167875.3-167901.6" + wire width 64 $3\reg$next[63:0]$10776 + attribute \src "libresoc.v:167845.3-167874.6" + wire $3\wr_detect$4[0:0]$10770 + attribute \src "libresoc.v:167775.3-167804.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $4\cia0__data_o$next[63:0]$10356 - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $4\msr0__data_o$next[63:0]$10365 - attribute \src "libresoc.v:164450.3-164476.6" - wire width 64 $4\reg$next[63:0]$10379 - attribute \src "libresoc.v:164420.3-164449.6" - wire $4\wr_detect$4[0:0]$10373 - attribute \src "libresoc.v:164350.3-164379.6" + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $4\cia0__data_o$next[63:0]$10754 + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $4\msr0__data_o$next[63:0]$10763 + attribute \src "libresoc.v:167875.3-167901.6" + wire width 64 $4\reg$next[63:0]$10777 + attribute \src "libresoc.v:167845.3-167874.6" + wire $4\wr_detect$4[0:0]$10771 + attribute \src "libresoc.v:167775.3-167804.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $5\cia0__data_o$next[63:0]$10357 - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $5\msr0__data_o$next[63:0]$10366 - attribute \src "libresoc.v:164310.3-164349.6" - wire width 64 $6\cia0__data_o$next[63:0]$10358 - attribute \src "libresoc.v:164380.3-164419.6" - wire width 64 $6\msr0__data_o$next[63:0]$10367 - attribute \src "libresoc.v:164302.17-164302.100" - wire $not$libresoc.v:164302$10346_Y - attribute \src "libresoc.v:164303.17-164303.103" - wire $not$libresoc.v:164303$10347_Y + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $5\cia0__data_o$next[63:0]$10755 + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $5\msr0__data_o$next[63:0]$10764 + attribute \src "libresoc.v:167735.3-167774.6" + wire width 64 $6\cia0__data_o$next[63:0]$10756 + attribute \src "libresoc.v:167805.3-167844.6" + wire width 64 $6\msr0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:167727.17-167727.100" + wire $not$libresoc.v:167727$10744_Y + attribute \src "libresoc.v:167728.17-167728.103" + wire $not$libresoc.v:167728$10745_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -338809,15 +346739,15 @@ module \reg_0$132 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \d_wr10__wen - attribute \src "libresoc.v:164259.7-164259.15" + attribute \src "libresoc.v:167684.7-167684.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 9 \msr0__data_i @@ -338842,83 +346772,83 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164302$10346 + cell $not $not$libresoc.v:167727$10744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:164302$10346_Y + connect \Y $not$libresoc.v:167727$10744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164303$10347 + cell $not $not$libresoc.v:167728$10745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:164303$10347_Y + connect \Y $not$libresoc.v:167728$10745_Y end - attribute \src "libresoc.v:164259.7-164259.20" - process $proc$libresoc.v:164259$10380 + attribute \src "libresoc.v:167684.7-167684.20" + process $proc$libresoc.v:167684$10778 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164266.14-164266.49" - process $proc$libresoc.v:164266$10381 + attribute \src "libresoc.v:167691.14-167691.49" + process $proc$libresoc.v:167691$10779 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:164283.14-164283.49" - process $proc$libresoc.v:164283$10382 + attribute \src "libresoc.v:167708.14-167708.49" + process $proc$libresoc.v:167708$10780 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:164295.14-164295.42" - process $proc$libresoc.v:164295$10383 + attribute \src "libresoc.v:167720.14-167720.42" + process $proc$libresoc.v:167720$10781 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:164304.3-164305.25" - process $proc$libresoc.v:164304$10348 + attribute \src "libresoc.v:167729.3-167730.25" + process $proc$libresoc.v:167729$10746 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:164306.3-164307.41" - process $proc$libresoc.v:164306$10349 + attribute \src "libresoc.v:167731.3-167732.41" + process $proc$libresoc.v:167731$10747 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:164308.3-164309.41" - process $proc$libresoc.v:164308$10350 + attribute \src "libresoc.v:167733.3-167734.41" + process $proc$libresoc.v:167733$10748 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:164310.3-164349.6" - process $proc$libresoc.v:164310$10351 + attribute \src "libresoc.v:167735.3-167774.6" + process $proc$libresoc.v:167735$10749 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10352 $6\cia0__data_o$next[63:0]$10358 - attribute \src "libresoc.v:164311.5-164311.29" + assign $0\cia0__data_o$next[63:0]$10750 $6\cia0__data_o$next[63:0]$10756 + attribute \src "libresoc.v:167736.5-167736.29" switch \initial - attribute \src "libresoc.v:164311.9-164311.17" + attribute \src "libresoc.v:167736.9-167736.17" case 1'1 case end @@ -338930,66 +346860,66 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10353 $5\cia0__data_o$next[63:0]$10357 + assign $1\cia0__data_o$next[63:0]$10751 $5\cia0__data_o$next[63:0]$10755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10354 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10752 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10354 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10752 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10355 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10753 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10355 $2\cia0__data_o$next[63:0]$10354 + assign $3\cia0__data_o$next[63:0]$10753 $2\cia0__data_o$next[63:0]$10752 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10356 \d_wr10__data_i + assign $4\cia0__data_o$next[63:0]$10754 \d_wr10__data_i case - assign $4\cia0__data_o$next[63:0]$10356 $3\cia0__data_o$next[63:0]$10355 + assign $4\cia0__data_o$next[63:0]$10754 $3\cia0__data_o$next[63:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10357 \reg + assign $5\cia0__data_o$next[63:0]$10755 \reg case - assign $5\cia0__data_o$next[63:0]$10357 $4\cia0__data_o$next[63:0]$10356 + assign $5\cia0__data_o$next[63:0]$10755 $4\cia0__data_o$next[63:0]$10754 end case - assign $1\cia0__data_o$next[63:0]$10353 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10751 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10358 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\cia0__data_o$next[63:0]$10756 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia0__data_o$next[63:0]$10358 $1\cia0__data_o$next[63:0]$10353 + assign $6\cia0__data_o$next[63:0]$10756 $1\cia0__data_o$next[63:0]$10751 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10352 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10750 end - attribute \src "libresoc.v:164350.3-164379.6" - process $proc$libresoc.v:164350$10359 + attribute \src "libresoc.v:167775.3-167804.6" + process $proc$libresoc.v:167775$10757 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:164351.5-164351.29" + attribute \src "libresoc.v:167776.5-167776.29" switch \initial - attribute \src "libresoc.v:164351.9-164351.17" + attribute \src "libresoc.v:167776.9-167776.17" case 1'1 case end @@ -339035,15 +346965,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:164380.3-164419.6" - process $proc$libresoc.v:164380$10360 + attribute \src "libresoc.v:167805.3-167844.6" + process $proc$libresoc.v:167805$10758 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10361 $6\msr0__data_o$next[63:0]$10367 - attribute \src "libresoc.v:164381.5-164381.29" + assign $0\msr0__data_o$next[63:0]$10759 $6\msr0__data_o$next[63:0]$10765 + attribute \src "libresoc.v:167806.5-167806.29" switch \initial - attribute \src "libresoc.v:164381.9-164381.17" + attribute \src "libresoc.v:167806.9-167806.17" case 1'1 case end @@ -339055,66 +346985,66 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10362 $5\msr0__data_o$next[63:0]$10366 + assign $1\msr0__data_o$next[63:0]$10760 $5\msr0__data_o$next[63:0]$10764 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10363 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10761 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10363 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10761 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10364 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10762 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10364 $2\msr0__data_o$next[63:0]$10363 + assign $3\msr0__data_o$next[63:0]$10762 $2\msr0__data_o$next[63:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10365 \d_wr10__data_i + assign $4\msr0__data_o$next[63:0]$10763 \d_wr10__data_i case - assign $4\msr0__data_o$next[63:0]$10365 $3\msr0__data_o$next[63:0]$10364 + assign $4\msr0__data_o$next[63:0]$10763 $3\msr0__data_o$next[63:0]$10762 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10366 \reg + assign $5\msr0__data_o$next[63:0]$10764 \reg case - assign $5\msr0__data_o$next[63:0]$10366 $4\msr0__data_o$next[63:0]$10365 + assign $5\msr0__data_o$next[63:0]$10764 $4\msr0__data_o$next[63:0]$10763 end case - assign $1\msr0__data_o$next[63:0]$10362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10760 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\msr0__data_o$next[63:0]$10765 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr0__data_o$next[63:0]$10367 $1\msr0__data_o$next[63:0]$10362 + assign $6\msr0__data_o$next[63:0]$10765 $1\msr0__data_o$next[63:0]$10760 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10361 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10759 end - attribute \src "libresoc.v:164420.3-164449.6" - process $proc$libresoc.v:164420$10368 + attribute \src "libresoc.v:167845.3-167874.6" + process $proc$libresoc.v:167845$10766 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10369 $1\wr_detect$4[0:0]$10370 - attribute \src "libresoc.v:164421.5-164421.29" + assign $0\wr_detect$4[0:0]$10767 $1\wr_detect$4[0:0]$10768 + attribute \src "libresoc.v:167846.5-167846.29" switch \initial - attribute \src "libresoc.v:164421.9-164421.17" + attribute \src "libresoc.v:167846.9-167846.17" case 1'1 case end @@ -339126,51 +347056,51 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10370 $4\wr_detect$4[0:0]$10373 + assign $1\wr_detect$4[0:0]$10768 $4\wr_detect$4[0:0]$10771 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10371 1'1 + assign $2\wr_detect$4[0:0]$10769 1'1 case - assign $2\wr_detect$4[0:0]$10371 1'0 + assign $2\wr_detect$4[0:0]$10769 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10372 1'1 + assign $3\wr_detect$4[0:0]$10770 1'1 case - assign $3\wr_detect$4[0:0]$10372 $2\wr_detect$4[0:0]$10371 + assign $3\wr_detect$4[0:0]$10770 $2\wr_detect$4[0:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10373 1'1 + assign $4\wr_detect$4[0:0]$10771 1'1 case - assign $4\wr_detect$4[0:0]$10373 $3\wr_detect$4[0:0]$10372 + assign $4\wr_detect$4[0:0]$10771 $3\wr_detect$4[0:0]$10770 end case - assign $1\wr_detect$4[0:0]$10370 1'0 + assign $1\wr_detect$4[0:0]$10768 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10369 + update \wr_detect$4 $0\wr_detect$4[0:0]$10767 end - attribute \src "libresoc.v:164450.3-164476.6" - process $proc$libresoc.v:164450$10374 + attribute \src "libresoc.v:167875.3-167901.6" + process $proc$libresoc.v:167875$10772 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10375 $4\reg$next[63:0]$10379 - attribute \src "libresoc.v:164451.5-164451.29" + assign $0\reg$next[63:0]$10773 $4\reg$next[63:0]$10777 + attribute \src "libresoc.v:167876.5-167876.29" switch \initial - attribute \src "libresoc.v:164451.9-164451.17" + attribute \src "libresoc.v:167876.9-167876.17" case 1'1 case end @@ -339179,214 +347109,214 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10376 \nia0__data_i + assign $1\reg$next[63:0]$10774 \nia0__data_i case - assign $1\reg$next[63:0]$10376 \reg + assign $1\reg$next[63:0]$10774 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10377 \msr0__data_i + assign $2\reg$next[63:0]$10775 \msr0__data_i case - assign $2\reg$next[63:0]$10377 $1\reg$next[63:0]$10376 + assign $2\reg$next[63:0]$10775 $1\reg$next[63:0]$10774 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10378 \d_wr10__data_i + assign $3\reg$next[63:0]$10776 \d_wr10__data_i case - assign $3\reg$next[63:0]$10378 $2\reg$next[63:0]$10377 + assign $3\reg$next[63:0]$10776 $2\reg$next[63:0]$10775 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10379 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\reg$next[63:0]$10777 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10379 $3\reg$next[63:0]$10378 + assign $4\reg$next[63:0]$10777 $3\reg$next[63:0]$10776 end sync always - update \reg$next $0\reg$next[63:0]$10375 + update \reg$next $0\reg$next[63:0]$10773 end - connect \$1 $not$libresoc.v:164302$10346_Y - connect \$3 $not$libresoc.v:164303$10347_Y + connect \$1 $not$libresoc.v:167727$10744_Y + connect \$3 $not$libresoc.v:167728$10745_Y end -attribute \src "libresoc.v:164481.1-164952.10" +attribute \src "libresoc.v:167906.1-168377.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:164482.7-164482.20" + attribute \src "libresoc.v:167907.7-167907.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $0\r1__data_o$next[3:0]$10439 - attribute \src "libresoc.v:164567.3-164568.37" + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $0\r1__data_o$next[3:0]$10837 + attribute \src "libresoc.v:167992.3-167993.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $0\r21__data_o$next[3:0]$10453 - attribute \src "libresoc.v:164565.3-164566.39" + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $0\r21__data_o$next[3:0]$10851 + attribute \src "libresoc.v:167990.3-167991.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:164645.3-164671.6" - wire width 4 $0\reg$next[3:0]$10405 - attribute \src "libresoc.v:164563.3-164564.25" + attribute \src "libresoc.v:168070.3-168096.6" + wire width 4 $0\reg$next[3:0]$10803 + attribute \src "libresoc.v:167988.3-167989.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $0\src11__data_o$next[3:0]$10396 - attribute \src "libresoc.v:164573.3-164574.43" + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $0\src11__data_o$next[3:0]$10794 + attribute \src "libresoc.v:167998.3-167999.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $0\src21__data_o$next[3:0]$10411 - attribute \src "libresoc.v:164571.3-164572.43" + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $0\src21__data_o$next[3:0]$10809 + attribute \src "libresoc.v:167996.3-167997.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $0\src31__data_o$next[3:0]$10425 - attribute \src "libresoc.v:164569.3-164570.43" + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $0\src31__data_o$next[3:0]$10823 + attribute \src "libresoc.v:167994.3-167995.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:164852.3-164881.6" - wire $0\wr_detect$10[0:0]$10447 - attribute \src "libresoc.v:164922.3-164951.6" - wire $0\wr_detect$13[0:0]$10461 - attribute \src "libresoc.v:164712.3-164741.6" - wire $0\wr_detect$4[0:0]$10419 - attribute \src "libresoc.v:164782.3-164811.6" - wire $0\wr_detect$7[0:0]$10433 - attribute \src "libresoc.v:164615.3-164644.6" + attribute \src "libresoc.v:168277.3-168306.6" + wire $0\wr_detect$10[0:0]$10845 + attribute \src "libresoc.v:168347.3-168376.6" + wire $0\wr_detect$13[0:0]$10859 + attribute \src "libresoc.v:168137.3-168166.6" + wire $0\wr_detect$4[0:0]$10817 + attribute \src "libresoc.v:168207.3-168236.6" + wire $0\wr_detect$7[0:0]$10831 + attribute \src "libresoc.v:168040.3-168069.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $1\r1__data_o$next[3:0]$10440 - attribute \src "libresoc.v:164507.13-164507.30" + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $1\r1__data_o$next[3:0]$10838 + attribute \src "libresoc.v:167932.13-167932.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $1\r21__data_o$next[3:0]$10454 - attribute \src "libresoc.v:164514.13-164514.31" + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $1\r21__data_o$next[3:0]$10852 + attribute \src "libresoc.v:167939.13-167939.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:164645.3-164671.6" - wire width 4 $1\reg$next[3:0]$10406 - attribute \src "libresoc.v:164520.13-164520.25" + attribute \src "libresoc.v:168070.3-168096.6" + wire width 4 $1\reg$next[3:0]$10804 + attribute \src "libresoc.v:167945.13-167945.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $1\src11__data_o$next[3:0]$10397 - attribute \src "libresoc.v:164525.13-164525.33" + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $1\src11__data_o$next[3:0]$10795 + attribute \src "libresoc.v:167950.13-167950.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $1\src21__data_o$next[3:0]$10412 - attribute \src "libresoc.v:164532.13-164532.33" + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $1\src21__data_o$next[3:0]$10810 + attribute \src "libresoc.v:167957.13-167957.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $1\src31__data_o$next[3:0]$10426 - attribute \src "libresoc.v:164539.13-164539.33" + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $1\src31__data_o$next[3:0]$10824 + attribute \src "libresoc.v:167964.13-167964.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:164852.3-164881.6" - wire $1\wr_detect$10[0:0]$10448 - attribute \src "libresoc.v:164922.3-164951.6" - wire $1\wr_detect$13[0:0]$10462 - attribute \src "libresoc.v:164712.3-164741.6" - wire $1\wr_detect$4[0:0]$10420 - attribute \src "libresoc.v:164782.3-164811.6" - wire $1\wr_detect$7[0:0]$10434 - attribute \src "libresoc.v:164615.3-164644.6" + attribute \src "libresoc.v:168277.3-168306.6" + wire $1\wr_detect$10[0:0]$10846 + attribute \src "libresoc.v:168347.3-168376.6" + wire $1\wr_detect$13[0:0]$10860 + attribute \src "libresoc.v:168137.3-168166.6" + wire $1\wr_detect$4[0:0]$10818 + attribute \src "libresoc.v:168207.3-168236.6" + wire $1\wr_detect$7[0:0]$10832 + attribute \src "libresoc.v:168040.3-168069.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $2\r1__data_o$next[3:0]$10441 - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $2\r21__data_o$next[3:0]$10455 - attribute \src "libresoc.v:164645.3-164671.6" - wire width 4 $2\reg$next[3:0]$10407 - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $2\src11__data_o$next[3:0]$10398 - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $2\src21__data_o$next[3:0]$10413 - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $2\src31__data_o$next[3:0]$10427 - attribute \src "libresoc.v:164852.3-164881.6" - wire $2\wr_detect$10[0:0]$10449 - attribute \src "libresoc.v:164922.3-164951.6" - wire $2\wr_detect$13[0:0]$10463 - attribute \src "libresoc.v:164712.3-164741.6" - wire $2\wr_detect$4[0:0]$10421 - attribute \src "libresoc.v:164782.3-164811.6" - wire $2\wr_detect$7[0:0]$10435 - attribute \src "libresoc.v:164615.3-164644.6" + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $2\r1__data_o$next[3:0]$10839 + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $2\r21__data_o$next[3:0]$10853 + attribute \src "libresoc.v:168070.3-168096.6" + wire width 4 $2\reg$next[3:0]$10805 + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $2\src11__data_o$next[3:0]$10796 + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $2\src21__data_o$next[3:0]$10811 + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $2\src31__data_o$next[3:0]$10825 + attribute \src "libresoc.v:168277.3-168306.6" + wire $2\wr_detect$10[0:0]$10847 + attribute \src "libresoc.v:168347.3-168376.6" + wire $2\wr_detect$13[0:0]$10861 + attribute \src "libresoc.v:168137.3-168166.6" + wire $2\wr_detect$4[0:0]$10819 + attribute \src "libresoc.v:168207.3-168236.6" + wire $2\wr_detect$7[0:0]$10833 + attribute \src "libresoc.v:168040.3-168069.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $3\r1__data_o$next[3:0]$10442 - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $3\r21__data_o$next[3:0]$10456 - attribute \src "libresoc.v:164645.3-164671.6" - wire width 4 $3\reg$next[3:0]$10408 - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $3\src11__data_o$next[3:0]$10399 - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $3\src21__data_o$next[3:0]$10414 - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $3\src31__data_o$next[3:0]$10428 - attribute \src "libresoc.v:164852.3-164881.6" - wire $3\wr_detect$10[0:0]$10450 - attribute \src "libresoc.v:164922.3-164951.6" - wire $3\wr_detect$13[0:0]$10464 - attribute \src "libresoc.v:164712.3-164741.6" - wire $3\wr_detect$4[0:0]$10422 - attribute \src "libresoc.v:164782.3-164811.6" - wire $3\wr_detect$7[0:0]$10436 - attribute \src "libresoc.v:164615.3-164644.6" + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $3\r1__data_o$next[3:0]$10840 + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $3\r21__data_o$next[3:0]$10854 + attribute \src "libresoc.v:168070.3-168096.6" + wire width 4 $3\reg$next[3:0]$10806 + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $3\src11__data_o$next[3:0]$10797 + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $3\src21__data_o$next[3:0]$10812 + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $3\src31__data_o$next[3:0]$10826 + attribute \src "libresoc.v:168277.3-168306.6" + wire $3\wr_detect$10[0:0]$10848 + attribute \src "libresoc.v:168347.3-168376.6" + wire $3\wr_detect$13[0:0]$10862 + attribute \src "libresoc.v:168137.3-168166.6" + wire $3\wr_detect$4[0:0]$10820 + attribute \src "libresoc.v:168207.3-168236.6" + wire $3\wr_detect$7[0:0]$10834 + attribute \src "libresoc.v:168040.3-168069.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $4\r1__data_o$next[3:0]$10443 - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $4\r21__data_o$next[3:0]$10457 - attribute \src "libresoc.v:164645.3-164671.6" - wire width 4 $4\reg$next[3:0]$10409 - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $4\src11__data_o$next[3:0]$10400 - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $4\src21__data_o$next[3:0]$10415 - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $4\src31__data_o$next[3:0]$10429 - attribute \src "libresoc.v:164852.3-164881.6" - wire $4\wr_detect$10[0:0]$10451 - attribute \src "libresoc.v:164922.3-164951.6" - wire $4\wr_detect$13[0:0]$10465 - attribute \src "libresoc.v:164712.3-164741.6" - wire $4\wr_detect$4[0:0]$10423 - attribute \src "libresoc.v:164782.3-164811.6" - wire $4\wr_detect$7[0:0]$10437 - attribute \src "libresoc.v:164615.3-164644.6" + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $4\r1__data_o$next[3:0]$10841 + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $4\r21__data_o$next[3:0]$10855 + attribute \src "libresoc.v:168070.3-168096.6" + wire width 4 $4\reg$next[3:0]$10807 + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $4\src11__data_o$next[3:0]$10798 + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $4\src21__data_o$next[3:0]$10813 + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $4\src31__data_o$next[3:0]$10827 + attribute \src "libresoc.v:168277.3-168306.6" + wire $4\wr_detect$10[0:0]$10849 + attribute \src "libresoc.v:168347.3-168376.6" + wire $4\wr_detect$13[0:0]$10863 + attribute \src "libresoc.v:168137.3-168166.6" + wire $4\wr_detect$4[0:0]$10821 + attribute \src "libresoc.v:168207.3-168236.6" + wire $4\wr_detect$7[0:0]$10835 + attribute \src "libresoc.v:168040.3-168069.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $5\r1__data_o$next[3:0]$10444 - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $5\r21__data_o$next[3:0]$10458 - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $5\src11__data_o$next[3:0]$10401 - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $5\src21__data_o$next[3:0]$10416 - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $5\src31__data_o$next[3:0]$10430 - attribute \src "libresoc.v:164812.3-164851.6" - wire width 4 $6\r1__data_o$next[3:0]$10445 - attribute \src "libresoc.v:164882.3-164921.6" - wire width 4 $6\r21__data_o$next[3:0]$10459 - attribute \src "libresoc.v:164575.3-164614.6" - wire width 4 $6\src11__data_o$next[3:0]$10402 - attribute \src "libresoc.v:164672.3-164711.6" - wire width 4 $6\src21__data_o$next[3:0]$10417 - attribute \src "libresoc.v:164742.3-164781.6" - wire width 4 $6\src31__data_o$next[3:0]$10431 - attribute \src "libresoc.v:164558.17-164558.104" - wire $not$libresoc.v:164558$10384_Y - attribute \src "libresoc.v:164559.18-164559.105" - wire $not$libresoc.v:164559$10385_Y - attribute \src "libresoc.v:164560.17-164560.100" - wire $not$libresoc.v:164560$10386_Y - attribute \src "libresoc.v:164561.17-164561.103" - wire $not$libresoc.v:164561$10387_Y - attribute \src "libresoc.v:164562.17-164562.103" - wire $not$libresoc.v:164562$10388_Y + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $5\r1__data_o$next[3:0]$10842 + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $5\r21__data_o$next[3:0]$10856 + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $5\src11__data_o$next[3:0]$10799 + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $5\src21__data_o$next[3:0]$10814 + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $5\src31__data_o$next[3:0]$10828 + attribute \src "libresoc.v:168237.3-168276.6" + wire width 4 $6\r1__data_o$next[3:0]$10843 + attribute \src "libresoc.v:168307.3-168346.6" + wire width 4 $6\r21__data_o$next[3:0]$10857 + attribute \src "libresoc.v:168000.3-168039.6" + wire width 4 $6\src11__data_o$next[3:0]$10800 + attribute \src "libresoc.v:168097.3-168136.6" + wire width 4 $6\src21__data_o$next[3:0]$10815 + attribute \src "libresoc.v:168167.3-168206.6" + wire width 4 $6\src31__data_o$next[3:0]$10829 + attribute \src "libresoc.v:167983.17-167983.104" + wire $not$libresoc.v:167983$10782_Y + attribute \src "libresoc.v:167984.18-167984.105" + wire $not$libresoc.v:167984$10783_Y + attribute \src "libresoc.v:167985.17-167985.100" + wire $not$libresoc.v:167985$10784_Y + attribute \src "libresoc.v:167986.17-167986.103" + wire $not$libresoc.v:167986$10785_Y + attribute \src "libresoc.v:167987.17-167987.103" + wire $not$libresoc.v:167987$10786_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -339397,9 +347327,9 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest11__data_i @@ -339409,7 +347339,7 @@ module \reg_1 wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest21__wen - attribute \src "libresoc.v:164482.7-164482.15" + attribute \src "libresoc.v:167907.7-167907.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 12 \r1__data_o @@ -339460,152 +347390,152 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164558$10384 + cell $not $not$libresoc.v:167983$10782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:164558$10384_Y + connect \Y $not$libresoc.v:167983$10782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164559$10385 + cell $not $not$libresoc.v:167984$10783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:164559$10385_Y + connect \Y $not$libresoc.v:167984$10783_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164560$10386 + cell $not $not$libresoc.v:167985$10784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:164560$10386_Y + connect \Y $not$libresoc.v:167985$10784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164561$10387 + cell $not $not$libresoc.v:167986$10785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:164561$10387_Y + connect \Y $not$libresoc.v:167986$10785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:164562$10388 + cell $not $not$libresoc.v:167987$10786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:164562$10388_Y + connect \Y $not$libresoc.v:167987$10786_Y end - attribute \src "libresoc.v:164482.7-164482.20" - process $proc$libresoc.v:164482$10466 + attribute \src "libresoc.v:167907.7-167907.20" + process $proc$libresoc.v:167907$10864 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164507.13-164507.30" - process $proc$libresoc.v:164507$10467 + attribute \src "libresoc.v:167932.13-167932.30" + process $proc$libresoc.v:167932$10865 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:164514.13-164514.31" - process $proc$libresoc.v:164514$10468 + attribute \src "libresoc.v:167939.13-167939.31" + process $proc$libresoc.v:167939$10866 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:164520.13-164520.25" - process $proc$libresoc.v:164520$10469 + attribute \src "libresoc.v:167945.13-167945.25" + process $proc$libresoc.v:167945$10867 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:164525.13-164525.33" - process $proc$libresoc.v:164525$10470 + attribute \src "libresoc.v:167950.13-167950.33" + process $proc$libresoc.v:167950$10868 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:164532.13-164532.33" - process $proc$libresoc.v:164532$10471 + attribute \src "libresoc.v:167957.13-167957.33" + process $proc$libresoc.v:167957$10869 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:164539.13-164539.33" - process $proc$libresoc.v:164539$10472 + attribute \src "libresoc.v:167964.13-167964.33" + process $proc$libresoc.v:167964$10870 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:164563.3-164564.25" - process $proc$libresoc.v:164563$10389 + attribute \src "libresoc.v:167988.3-167989.25" + process $proc$libresoc.v:167988$10787 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:164565.3-164566.39" - process $proc$libresoc.v:164565$10390 + attribute \src "libresoc.v:167990.3-167991.39" + process $proc$libresoc.v:167990$10788 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:164567.3-164568.37" - process $proc$libresoc.v:164567$10391 + attribute \src "libresoc.v:167992.3-167993.37" + process $proc$libresoc.v:167992$10789 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:164569.3-164570.43" - process $proc$libresoc.v:164569$10392 + attribute \src "libresoc.v:167994.3-167995.43" + process $proc$libresoc.v:167994$10790 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:164571.3-164572.43" - process $proc$libresoc.v:164571$10393 + attribute \src "libresoc.v:167996.3-167997.43" + process $proc$libresoc.v:167996$10791 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:164573.3-164574.43" - process $proc$libresoc.v:164573$10394 + attribute \src "libresoc.v:167998.3-167999.43" + process $proc$libresoc.v:167998$10792 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:164575.3-164614.6" - process $proc$libresoc.v:164575$10395 + attribute \src "libresoc.v:168000.3-168039.6" + process $proc$libresoc.v:168000$10793 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10396 $6\src11__data_o$next[3:0]$10402 - attribute \src "libresoc.v:164576.5-164576.29" + assign $0\src11__data_o$next[3:0]$10794 $6\src11__data_o$next[3:0]$10800 + attribute \src "libresoc.v:168001.5-168001.29" switch \initial - attribute \src "libresoc.v:164576.9-164576.17" + attribute \src "libresoc.v:168001.9-168001.17" case 1'1 case end @@ -339617,66 +347547,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10397 $5\src11__data_o$next[3:0]$10401 + assign $1\src11__data_o$next[3:0]$10795 $5\src11__data_o$next[3:0]$10799 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10398 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10796 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10398 4'0000 + assign $2\src11__data_o$next[3:0]$10796 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10399 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10797 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10399 $2\src11__data_o$next[3:0]$10398 + assign $3\src11__data_o$next[3:0]$10797 $2\src11__data_o$next[3:0]$10796 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10400 \w1__data_i + assign $4\src11__data_o$next[3:0]$10798 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10400 $3\src11__data_o$next[3:0]$10399 + assign $4\src11__data_o$next[3:0]$10798 $3\src11__data_o$next[3:0]$10797 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10401 \reg + assign $5\src11__data_o$next[3:0]$10799 \reg case - assign $5\src11__data_o$next[3:0]$10401 $4\src11__data_o$next[3:0]$10400 + assign $5\src11__data_o$next[3:0]$10799 $4\src11__data_o$next[3:0]$10798 end case - assign $1\src11__data_o$next[3:0]$10397 4'0000 + assign $1\src11__data_o$next[3:0]$10795 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10402 4'0000 + assign $6\src11__data_o$next[3:0]$10800 4'0000 case - assign $6\src11__data_o$next[3:0]$10402 $1\src11__data_o$next[3:0]$10397 + assign $6\src11__data_o$next[3:0]$10800 $1\src11__data_o$next[3:0]$10795 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10396 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10794 end - attribute \src "libresoc.v:164615.3-164644.6" - process $proc$libresoc.v:164615$10403 + attribute \src "libresoc.v:168040.3-168069.6" + process $proc$libresoc.v:168040$10801 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:164616.5-164616.29" + attribute \src "libresoc.v:168041.5-168041.29" switch \initial - attribute \src "libresoc.v:164616.9-164616.17" + attribute \src "libresoc.v:168041.9-168041.17" case 1'1 case end @@ -339722,17 +347652,17 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:164645.3-164671.6" - process $proc$libresoc.v:164645$10404 + attribute \src "libresoc.v:168070.3-168096.6" + process $proc$libresoc.v:168070$10802 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10405 $4\reg$next[3:0]$10409 - attribute \src "libresoc.v:164646.5-164646.29" + assign $0\reg$next[3:0]$10803 $4\reg$next[3:0]$10807 + attribute \src "libresoc.v:168071.5-168071.29" switch \initial - attribute \src "libresoc.v:164646.9-164646.17" + attribute \src "libresoc.v:168071.9-168071.17" case 1'1 case end @@ -339741,49 +347671,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10406 \dest11__data_i + assign $1\reg$next[3:0]$10804 \dest11__data_i case - assign $1\reg$next[3:0]$10406 \reg + assign $1\reg$next[3:0]$10804 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10407 \dest21__data_i + assign $2\reg$next[3:0]$10805 \dest21__data_i case - assign $2\reg$next[3:0]$10407 $1\reg$next[3:0]$10406 + assign $2\reg$next[3:0]$10805 $1\reg$next[3:0]$10804 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10408 \w1__data_i + assign $3\reg$next[3:0]$10806 \w1__data_i case - assign $3\reg$next[3:0]$10408 $2\reg$next[3:0]$10407 + assign $3\reg$next[3:0]$10806 $2\reg$next[3:0]$10805 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10409 4'0000 + assign $4\reg$next[3:0]$10807 4'0000 case - assign $4\reg$next[3:0]$10409 $3\reg$next[3:0]$10408 + assign $4\reg$next[3:0]$10807 $3\reg$next[3:0]$10806 end sync always - update \reg$next $0\reg$next[3:0]$10405 + update \reg$next $0\reg$next[3:0]$10803 end - attribute \src "libresoc.v:164672.3-164711.6" - process $proc$libresoc.v:164672$10410 + attribute \src "libresoc.v:168097.3-168136.6" + process $proc$libresoc.v:168097$10808 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10411 $6\src21__data_o$next[3:0]$10417 - attribute \src "libresoc.v:164673.5-164673.29" + assign $0\src21__data_o$next[3:0]$10809 $6\src21__data_o$next[3:0]$10815 + attribute \src "libresoc.v:168098.5-168098.29" switch \initial - attribute \src "libresoc.v:164673.9-164673.17" + attribute \src "libresoc.v:168098.9-168098.17" case 1'1 case end @@ -339795,66 +347725,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10412 $5\src21__data_o$next[3:0]$10416 + assign $1\src21__data_o$next[3:0]$10810 $5\src21__data_o$next[3:0]$10814 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10413 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10811 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10413 4'0000 + assign $2\src21__data_o$next[3:0]$10811 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10414 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10812 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10414 $2\src21__data_o$next[3:0]$10413 + assign $3\src21__data_o$next[3:0]$10812 $2\src21__data_o$next[3:0]$10811 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10415 \w1__data_i + assign $4\src21__data_o$next[3:0]$10813 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10415 $3\src21__data_o$next[3:0]$10414 + assign $4\src21__data_o$next[3:0]$10813 $3\src21__data_o$next[3:0]$10812 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10416 \reg + assign $5\src21__data_o$next[3:0]$10814 \reg case - assign $5\src21__data_o$next[3:0]$10416 $4\src21__data_o$next[3:0]$10415 + assign $5\src21__data_o$next[3:0]$10814 $4\src21__data_o$next[3:0]$10813 end case - assign $1\src21__data_o$next[3:0]$10412 4'0000 + assign $1\src21__data_o$next[3:0]$10810 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10417 4'0000 + assign $6\src21__data_o$next[3:0]$10815 4'0000 case - assign $6\src21__data_o$next[3:0]$10417 $1\src21__data_o$next[3:0]$10412 + assign $6\src21__data_o$next[3:0]$10815 $1\src21__data_o$next[3:0]$10810 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10411 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10809 end - attribute \src "libresoc.v:164712.3-164741.6" - process $proc$libresoc.v:164712$10418 + attribute \src "libresoc.v:168137.3-168166.6" + process $proc$libresoc.v:168137$10816 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10419 $1\wr_detect$4[0:0]$10420 - attribute \src "libresoc.v:164713.5-164713.29" + assign $0\wr_detect$4[0:0]$10817 $1\wr_detect$4[0:0]$10818 + attribute \src "libresoc.v:168138.5-168138.29" switch \initial - attribute \src "libresoc.v:164713.9-164713.17" + attribute \src "libresoc.v:168138.9-168138.17" case 1'1 case end @@ -339866,49 +347796,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10420 $4\wr_detect$4[0:0]$10423 + assign $1\wr_detect$4[0:0]$10818 $4\wr_detect$4[0:0]$10821 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10421 1'1 + assign $2\wr_detect$4[0:0]$10819 1'1 case - assign $2\wr_detect$4[0:0]$10421 1'0 + assign $2\wr_detect$4[0:0]$10819 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10422 1'1 + assign $3\wr_detect$4[0:0]$10820 1'1 case - assign $3\wr_detect$4[0:0]$10422 $2\wr_detect$4[0:0]$10421 + assign $3\wr_detect$4[0:0]$10820 $2\wr_detect$4[0:0]$10819 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10423 1'1 + assign $4\wr_detect$4[0:0]$10821 1'1 case - assign $4\wr_detect$4[0:0]$10423 $3\wr_detect$4[0:0]$10422 + assign $4\wr_detect$4[0:0]$10821 $3\wr_detect$4[0:0]$10820 end case - assign $1\wr_detect$4[0:0]$10420 1'0 + assign $1\wr_detect$4[0:0]$10818 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10419 + update \wr_detect$4 $0\wr_detect$4[0:0]$10817 end - attribute \src "libresoc.v:164742.3-164781.6" - process $proc$libresoc.v:164742$10424 + attribute \src "libresoc.v:168167.3-168206.6" + process $proc$libresoc.v:168167$10822 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10425 $6\src31__data_o$next[3:0]$10431 - attribute \src "libresoc.v:164743.5-164743.29" + assign $0\src31__data_o$next[3:0]$10823 $6\src31__data_o$next[3:0]$10829 + attribute \src "libresoc.v:168168.5-168168.29" switch \initial - attribute \src "libresoc.v:164743.9-164743.17" + attribute \src "libresoc.v:168168.9-168168.17" case 1'1 case end @@ -339920,66 +347850,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10426 $5\src31__data_o$next[3:0]$10430 + assign $1\src31__data_o$next[3:0]$10824 $5\src31__data_o$next[3:0]$10828 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10427 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10825 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10427 4'0000 + assign $2\src31__data_o$next[3:0]$10825 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10428 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10826 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10428 $2\src31__data_o$next[3:0]$10427 + assign $3\src31__data_o$next[3:0]$10826 $2\src31__data_o$next[3:0]$10825 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10429 \w1__data_i + assign $4\src31__data_o$next[3:0]$10827 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10429 $3\src31__data_o$next[3:0]$10428 + assign $4\src31__data_o$next[3:0]$10827 $3\src31__data_o$next[3:0]$10826 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10430 \reg + assign $5\src31__data_o$next[3:0]$10828 \reg case - assign $5\src31__data_o$next[3:0]$10430 $4\src31__data_o$next[3:0]$10429 + assign $5\src31__data_o$next[3:0]$10828 $4\src31__data_o$next[3:0]$10827 end case - assign $1\src31__data_o$next[3:0]$10426 4'0000 + assign $1\src31__data_o$next[3:0]$10824 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10431 4'0000 + assign $6\src31__data_o$next[3:0]$10829 4'0000 case - assign $6\src31__data_o$next[3:0]$10431 $1\src31__data_o$next[3:0]$10426 + assign $6\src31__data_o$next[3:0]$10829 $1\src31__data_o$next[3:0]$10824 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10425 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10823 end - attribute \src "libresoc.v:164782.3-164811.6" - process $proc$libresoc.v:164782$10432 + attribute \src "libresoc.v:168207.3-168236.6" + process $proc$libresoc.v:168207$10830 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10433 $1\wr_detect$7[0:0]$10434 - attribute \src "libresoc.v:164783.5-164783.29" + assign $0\wr_detect$7[0:0]$10831 $1\wr_detect$7[0:0]$10832 + attribute \src "libresoc.v:168208.5-168208.29" switch \initial - attribute \src "libresoc.v:164783.9-164783.17" + attribute \src "libresoc.v:168208.9-168208.17" case 1'1 case end @@ -339991,49 +347921,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10434 $4\wr_detect$7[0:0]$10437 + assign $1\wr_detect$7[0:0]$10832 $4\wr_detect$7[0:0]$10835 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10435 1'1 + assign $2\wr_detect$7[0:0]$10833 1'1 case - assign $2\wr_detect$7[0:0]$10435 1'0 + assign $2\wr_detect$7[0:0]$10833 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10436 1'1 + assign $3\wr_detect$7[0:0]$10834 1'1 case - assign $3\wr_detect$7[0:0]$10436 $2\wr_detect$7[0:0]$10435 + assign $3\wr_detect$7[0:0]$10834 $2\wr_detect$7[0:0]$10833 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10437 1'1 + assign $4\wr_detect$7[0:0]$10835 1'1 case - assign $4\wr_detect$7[0:0]$10437 $3\wr_detect$7[0:0]$10436 + assign $4\wr_detect$7[0:0]$10835 $3\wr_detect$7[0:0]$10834 end case - assign $1\wr_detect$7[0:0]$10434 1'0 + assign $1\wr_detect$7[0:0]$10832 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10433 + update \wr_detect$7 $0\wr_detect$7[0:0]$10831 end - attribute \src "libresoc.v:164812.3-164851.6" - process $proc$libresoc.v:164812$10438 + attribute \src "libresoc.v:168237.3-168276.6" + process $proc$libresoc.v:168237$10836 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10439 $6\r1__data_o$next[3:0]$10445 - attribute \src "libresoc.v:164813.5-164813.29" + assign $0\r1__data_o$next[3:0]$10837 $6\r1__data_o$next[3:0]$10843 + attribute \src "libresoc.v:168238.5-168238.29" switch \initial - attribute \src "libresoc.v:164813.9-164813.17" + attribute \src "libresoc.v:168238.9-168238.17" case 1'1 case end @@ -340045,66 +347975,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10440 $5\r1__data_o$next[3:0]$10444 + assign $1\r1__data_o$next[3:0]$10838 $5\r1__data_o$next[3:0]$10842 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10441 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10839 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10441 4'0000 + assign $2\r1__data_o$next[3:0]$10839 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10442 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10840 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10442 $2\r1__data_o$next[3:0]$10441 + assign $3\r1__data_o$next[3:0]$10840 $2\r1__data_o$next[3:0]$10839 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10443 \w1__data_i + assign $4\r1__data_o$next[3:0]$10841 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10443 $3\r1__data_o$next[3:0]$10442 + assign $4\r1__data_o$next[3:0]$10841 $3\r1__data_o$next[3:0]$10840 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10444 \reg + assign $5\r1__data_o$next[3:0]$10842 \reg case - assign $5\r1__data_o$next[3:0]$10444 $4\r1__data_o$next[3:0]$10443 + assign $5\r1__data_o$next[3:0]$10842 $4\r1__data_o$next[3:0]$10841 end case - assign $1\r1__data_o$next[3:0]$10440 4'0000 + assign $1\r1__data_o$next[3:0]$10838 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10445 4'0000 + assign $6\r1__data_o$next[3:0]$10843 4'0000 case - assign $6\r1__data_o$next[3:0]$10445 $1\r1__data_o$next[3:0]$10440 + assign $6\r1__data_o$next[3:0]$10843 $1\r1__data_o$next[3:0]$10838 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10439 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10837 end - attribute \src "libresoc.v:164852.3-164881.6" - process $proc$libresoc.v:164852$10446 + attribute \src "libresoc.v:168277.3-168306.6" + process $proc$libresoc.v:168277$10844 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10447 $1\wr_detect$10[0:0]$10448 - attribute \src "libresoc.v:164853.5-164853.29" + assign $0\wr_detect$10[0:0]$10845 $1\wr_detect$10[0:0]$10846 + attribute \src "libresoc.v:168278.5-168278.29" switch \initial - attribute \src "libresoc.v:164853.9-164853.17" + attribute \src "libresoc.v:168278.9-168278.17" case 1'1 case end @@ -340116,49 +348046,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10448 $4\wr_detect$10[0:0]$10451 + assign $1\wr_detect$10[0:0]$10846 $4\wr_detect$10[0:0]$10849 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10449 1'1 + assign $2\wr_detect$10[0:0]$10847 1'1 case - assign $2\wr_detect$10[0:0]$10449 1'0 + assign $2\wr_detect$10[0:0]$10847 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10450 1'1 + assign $3\wr_detect$10[0:0]$10848 1'1 case - assign $3\wr_detect$10[0:0]$10450 $2\wr_detect$10[0:0]$10449 + assign $3\wr_detect$10[0:0]$10848 $2\wr_detect$10[0:0]$10847 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10451 1'1 + assign $4\wr_detect$10[0:0]$10849 1'1 case - assign $4\wr_detect$10[0:0]$10451 $3\wr_detect$10[0:0]$10450 + assign $4\wr_detect$10[0:0]$10849 $3\wr_detect$10[0:0]$10848 end case - assign $1\wr_detect$10[0:0]$10448 1'0 + assign $1\wr_detect$10[0:0]$10846 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10447 + update \wr_detect$10 $0\wr_detect$10[0:0]$10845 end - attribute \src "libresoc.v:164882.3-164921.6" - process $proc$libresoc.v:164882$10452 + attribute \src "libresoc.v:168307.3-168346.6" + process $proc$libresoc.v:168307$10850 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10453 $6\r21__data_o$next[3:0]$10459 - attribute \src "libresoc.v:164883.5-164883.29" + assign $0\r21__data_o$next[3:0]$10851 $6\r21__data_o$next[3:0]$10857 + attribute \src "libresoc.v:168308.5-168308.29" switch \initial - attribute \src "libresoc.v:164883.9-164883.17" + attribute \src "libresoc.v:168308.9-168308.17" case 1'1 case end @@ -340170,66 +348100,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10454 $5\r21__data_o$next[3:0]$10458 + assign $1\r21__data_o$next[3:0]$10852 $5\r21__data_o$next[3:0]$10856 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10455 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10853 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10455 4'0000 + assign $2\r21__data_o$next[3:0]$10853 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10456 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10854 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10456 $2\r21__data_o$next[3:0]$10455 + assign $3\r21__data_o$next[3:0]$10854 $2\r21__data_o$next[3:0]$10853 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10457 \w1__data_i + assign $4\r21__data_o$next[3:0]$10855 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10457 $3\r21__data_o$next[3:0]$10456 + assign $4\r21__data_o$next[3:0]$10855 $3\r21__data_o$next[3:0]$10854 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10458 \reg + assign $5\r21__data_o$next[3:0]$10856 \reg case - assign $5\r21__data_o$next[3:0]$10458 $4\r21__data_o$next[3:0]$10457 + assign $5\r21__data_o$next[3:0]$10856 $4\r21__data_o$next[3:0]$10855 end case - assign $1\r21__data_o$next[3:0]$10454 4'0000 + assign $1\r21__data_o$next[3:0]$10852 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10459 4'0000 + assign $6\r21__data_o$next[3:0]$10857 4'0000 case - assign $6\r21__data_o$next[3:0]$10459 $1\r21__data_o$next[3:0]$10454 + assign $6\r21__data_o$next[3:0]$10857 $1\r21__data_o$next[3:0]$10852 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10453 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10851 end - attribute \src "libresoc.v:164922.3-164951.6" - process $proc$libresoc.v:164922$10460 + attribute \src "libresoc.v:168347.3-168376.6" + process $proc$libresoc.v:168347$10858 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10461 $1\wr_detect$13[0:0]$10462 - attribute \src "libresoc.v:164923.5-164923.29" + assign $0\wr_detect$13[0:0]$10859 $1\wr_detect$13[0:0]$10860 + attribute \src "libresoc.v:168348.5-168348.29" switch \initial - attribute \src "libresoc.v:164923.9-164923.17" + attribute \src "libresoc.v:168348.9-168348.17" case 1'1 case end @@ -340241,205 +348171,205 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10462 $4\wr_detect$13[0:0]$10465 + assign $1\wr_detect$13[0:0]$10860 $4\wr_detect$13[0:0]$10863 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10463 1'1 + assign $2\wr_detect$13[0:0]$10861 1'1 case - assign $2\wr_detect$13[0:0]$10463 1'0 + assign $2\wr_detect$13[0:0]$10861 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10464 1'1 + assign $3\wr_detect$13[0:0]$10862 1'1 case - assign $3\wr_detect$13[0:0]$10464 $2\wr_detect$13[0:0]$10463 + assign $3\wr_detect$13[0:0]$10862 $2\wr_detect$13[0:0]$10861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10465 1'1 + assign $4\wr_detect$13[0:0]$10863 1'1 case - assign $4\wr_detect$13[0:0]$10465 $3\wr_detect$13[0:0]$10464 + assign $4\wr_detect$13[0:0]$10863 $3\wr_detect$13[0:0]$10862 end case - assign $1\wr_detect$13[0:0]$10462 1'0 + assign $1\wr_detect$13[0:0]$10860 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10461 + update \wr_detect$13 $0\wr_detect$13[0:0]$10859 end - connect \$9 $not$libresoc.v:164558$10384_Y - connect \$12 $not$libresoc.v:164559$10385_Y - connect \$1 $not$libresoc.v:164560$10386_Y - connect \$3 $not$libresoc.v:164561$10387_Y - connect \$6 $not$libresoc.v:164562$10388_Y + connect \$9 $not$libresoc.v:167983$10782_Y + connect \$12 $not$libresoc.v:167984$10783_Y + connect \$1 $not$libresoc.v:167985$10784_Y + connect \$3 $not$libresoc.v:167986$10785_Y + connect \$6 $not$libresoc.v:167987$10786_Y end -attribute \src "libresoc.v:164956.1-165401.10" +attribute \src "libresoc.v:168381.1-168826.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" -module \reg_1$130 - attribute \src "libresoc.v:164957.7-164957.20" +module \reg_1$133 + attribute \src "libresoc.v:168382.7-168382.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $0\r1__data_o$next[1:0]$10525 - attribute \src "libresoc.v:165032.3-165033.37" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $0\r1__data_o$next[1:0]$10923 + attribute \src "libresoc.v:168457.3-168458.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $0\reg$next[1:0]$10541 - attribute \src "libresoc.v:165030.3-165031.25" + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $0\reg$next[1:0]$10939 + attribute \src "libresoc.v:168455.3-168456.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $0\src11__data_o$next[1:0]$10483 - attribute \src "libresoc.v:165038.3-165039.43" + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $0\src11__data_o$next[1:0]$10881 + attribute \src "libresoc.v:168463.3-168464.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $0\src21__data_o$next[1:0]$10493 - attribute \src "libresoc.v:165036.3-165037.43" + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $0\src21__data_o$next[1:0]$10891 + attribute \src "libresoc.v:168461.3-168462.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $0\src31__data_o$next[1:0]$10509 - attribute \src "libresoc.v:165034.3-165035.43" + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $0\src31__data_o$next[1:0]$10907 + attribute \src "libresoc.v:168459.3-168460.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:165332.3-165367.6" - wire $0\wr_detect$10[0:0]$10534 - attribute \src "libresoc.v:165168.3-165203.6" - wire $0\wr_detect$4[0:0]$10502 - attribute \src "libresoc.v:165250.3-165285.6" - wire $0\wr_detect$7[0:0]$10518 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168757.3-168792.6" + wire $0\wr_detect$10[0:0]$10932 + attribute \src "libresoc.v:168593.3-168628.6" + wire $0\wr_detect$4[0:0]$10900 + attribute \src "libresoc.v:168675.3-168710.6" + wire $0\wr_detect$7[0:0]$10916 + attribute \src "libresoc.v:168511.3-168546.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $1\r1__data_o$next[1:0]$10526 - attribute \src "libresoc.v:164984.13-164984.30" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $1\r1__data_o$next[1:0]$10924 + attribute \src "libresoc.v:168409.13-168409.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $1\reg$next[1:0]$10542 - attribute \src "libresoc.v:164990.13-164990.25" + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $1\reg$next[1:0]$10940 + attribute \src "libresoc.v:168415.13-168415.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $1\src11__data_o$next[1:0]$10484 - attribute \src "libresoc.v:164995.13-164995.33" + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $1\src11__data_o$next[1:0]$10882 + attribute \src "libresoc.v:168420.13-168420.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $1\src21__data_o$next[1:0]$10494 - attribute \src "libresoc.v:165002.13-165002.33" + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $1\src21__data_o$next[1:0]$10892 + attribute \src "libresoc.v:168427.13-168427.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $1\src31__data_o$next[1:0]$10510 - attribute \src "libresoc.v:165009.13-165009.33" + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $1\src31__data_o$next[1:0]$10908 + attribute \src "libresoc.v:168434.13-168434.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:165332.3-165367.6" - wire $1\wr_detect$10[0:0]$10535 - attribute \src "libresoc.v:165168.3-165203.6" - wire $1\wr_detect$4[0:0]$10503 - attribute \src "libresoc.v:165250.3-165285.6" - wire $1\wr_detect$7[0:0]$10519 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168757.3-168792.6" + wire $1\wr_detect$10[0:0]$10933 + attribute \src "libresoc.v:168593.3-168628.6" + wire $1\wr_detect$4[0:0]$10901 + attribute \src "libresoc.v:168675.3-168710.6" + wire $1\wr_detect$7[0:0]$10917 + attribute \src "libresoc.v:168511.3-168546.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $2\r1__data_o$next[1:0]$10527 - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $2\reg$next[1:0]$10543 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $2\src11__data_o$next[1:0]$10485 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $2\src21__data_o$next[1:0]$10495 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $2\src31__data_o$next[1:0]$10511 - attribute \src "libresoc.v:165332.3-165367.6" - wire $2\wr_detect$10[0:0]$10536 - attribute \src "libresoc.v:165168.3-165203.6" - wire $2\wr_detect$4[0:0]$10504 - attribute \src "libresoc.v:165250.3-165285.6" - wire $2\wr_detect$7[0:0]$10520 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $2\r1__data_o$next[1:0]$10925 + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $2\reg$next[1:0]$10941 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $2\src11__data_o$next[1:0]$10883 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $2\src21__data_o$next[1:0]$10893 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $2\src31__data_o$next[1:0]$10909 + attribute \src "libresoc.v:168757.3-168792.6" + wire $2\wr_detect$10[0:0]$10934 + attribute \src "libresoc.v:168593.3-168628.6" + wire $2\wr_detect$4[0:0]$10902 + attribute \src "libresoc.v:168675.3-168710.6" + wire $2\wr_detect$7[0:0]$10918 + attribute \src "libresoc.v:168511.3-168546.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $3\r1__data_o$next[1:0]$10528 - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $3\reg$next[1:0]$10544 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $3\src11__data_o$next[1:0]$10486 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $3\src21__data_o$next[1:0]$10496 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $3\src31__data_o$next[1:0]$10512 - attribute \src "libresoc.v:165332.3-165367.6" - wire $3\wr_detect$10[0:0]$10537 - attribute \src "libresoc.v:165168.3-165203.6" - wire $3\wr_detect$4[0:0]$10505 - attribute \src "libresoc.v:165250.3-165285.6" - wire $3\wr_detect$7[0:0]$10521 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $3\r1__data_o$next[1:0]$10926 + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $3\reg$next[1:0]$10942 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $3\src11__data_o$next[1:0]$10884 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $3\src21__data_o$next[1:0]$10894 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $3\src31__data_o$next[1:0]$10910 + attribute \src "libresoc.v:168757.3-168792.6" + wire $3\wr_detect$10[0:0]$10935 + attribute \src "libresoc.v:168593.3-168628.6" + wire $3\wr_detect$4[0:0]$10903 + attribute \src "libresoc.v:168675.3-168710.6" + wire $3\wr_detect$7[0:0]$10919 + attribute \src "libresoc.v:168511.3-168546.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $4\r1__data_o$next[1:0]$10529 - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $4\reg$next[1:0]$10545 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $4\src11__data_o$next[1:0]$10487 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $4\src21__data_o$next[1:0]$10497 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $4\src31__data_o$next[1:0]$10513 - attribute \src "libresoc.v:165332.3-165367.6" - wire $4\wr_detect$10[0:0]$10538 - attribute \src "libresoc.v:165168.3-165203.6" - wire $4\wr_detect$4[0:0]$10506 - attribute \src "libresoc.v:165250.3-165285.6" - wire $4\wr_detect$7[0:0]$10522 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $4\r1__data_o$next[1:0]$10927 + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $4\reg$next[1:0]$10943 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $4\src11__data_o$next[1:0]$10885 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $4\src21__data_o$next[1:0]$10895 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $4\src31__data_o$next[1:0]$10911 + attribute \src "libresoc.v:168757.3-168792.6" + wire $4\wr_detect$10[0:0]$10936 + attribute \src "libresoc.v:168593.3-168628.6" + wire $4\wr_detect$4[0:0]$10904 + attribute \src "libresoc.v:168675.3-168710.6" + wire $4\wr_detect$7[0:0]$10920 + attribute \src "libresoc.v:168511.3-168546.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $5\r1__data_o$next[1:0]$10530 - attribute \src "libresoc.v:165368.3-165400.6" - wire width 2 $5\reg$next[1:0]$10546 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $5\src11__data_o$next[1:0]$10488 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $5\src21__data_o$next[1:0]$10498 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $5\src31__data_o$next[1:0]$10514 - attribute \src "libresoc.v:165332.3-165367.6" - wire $5\wr_detect$10[0:0]$10539 - attribute \src "libresoc.v:165168.3-165203.6" - wire $5\wr_detect$4[0:0]$10507 - attribute \src "libresoc.v:165250.3-165285.6" - wire $5\wr_detect$7[0:0]$10523 - attribute \src "libresoc.v:165086.3-165121.6" + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $5\r1__data_o$next[1:0]$10928 + attribute \src "libresoc.v:168793.3-168825.6" + wire width 2 $5\reg$next[1:0]$10944 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $5\src11__data_o$next[1:0]$10886 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $5\src21__data_o$next[1:0]$10896 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $5\src31__data_o$next[1:0]$10912 + attribute \src "libresoc.v:168757.3-168792.6" + wire $5\wr_detect$10[0:0]$10937 + attribute \src "libresoc.v:168593.3-168628.6" + wire $5\wr_detect$4[0:0]$10905 + attribute \src "libresoc.v:168675.3-168710.6" + wire $5\wr_detect$7[0:0]$10921 + attribute \src "libresoc.v:168511.3-168546.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $6\r1__data_o$next[1:0]$10531 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $6\src11__data_o$next[1:0]$10489 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $6\src21__data_o$next[1:0]$10499 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $6\src31__data_o$next[1:0]$10515 - attribute \src "libresoc.v:165286.3-165331.6" - wire width 2 $7\r1__data_o$next[1:0]$10532 - attribute \src "libresoc.v:165040.3-165085.6" - wire width 2 $7\src11__data_o$next[1:0]$10490 - attribute \src "libresoc.v:165122.3-165167.6" - wire width 2 $7\src21__data_o$next[1:0]$10500 - attribute \src "libresoc.v:165204.3-165249.6" - wire width 2 $7\src31__data_o$next[1:0]$10516 - attribute \src "libresoc.v:165026.17-165026.104" - wire $not$libresoc.v:165026$10473_Y - attribute \src "libresoc.v:165027.17-165027.100" - wire $not$libresoc.v:165027$10474_Y - attribute \src "libresoc.v:165028.17-165028.103" - wire $not$libresoc.v:165028$10475_Y - attribute \src "libresoc.v:165029.17-165029.103" - wire $not$libresoc.v:165029$10476_Y + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $6\r1__data_o$next[1:0]$10929 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $6\src11__data_o$next[1:0]$10887 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $6\src21__data_o$next[1:0]$10897 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $6\src31__data_o$next[1:0]$10913 + attribute \src "libresoc.v:168711.3-168756.6" + wire width 2 $7\r1__data_o$next[1:0]$10930 + attribute \src "libresoc.v:168465.3-168510.6" + wire width 2 $7\src11__data_o$next[1:0]$10888 + attribute \src "libresoc.v:168547.3-168592.6" + wire width 2 $7\src21__data_o$next[1:0]$10898 + attribute \src "libresoc.v:168629.3-168674.6" + wire width 2 $7\src31__data_o$next[1:0]$10914 + attribute \src "libresoc.v:168451.17-168451.104" + wire $not$libresoc.v:168451$10871_Y + attribute \src "libresoc.v:168452.17-168452.100" + wire $not$libresoc.v:168452$10872_Y + attribute \src "libresoc.v:168453.17-168453.103" + wire $not$libresoc.v:168453$10873_Y + attribute \src "libresoc.v:168454.17-168454.103" + wire $not$libresoc.v:168454$10874_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -340448,9 +348378,9 @@ module \reg_1$130 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 input 9 \dest11__data_i @@ -340464,7 +348394,7 @@ module \reg_1$130 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 12 \dest31__wen - attribute \src "libresoc.v:164957.7-164957.15" + attribute \src "libresoc.v:168382.7-168382.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 output 14 \r1__data_o @@ -340507,129 +348437,129 @@ module \reg_1$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165026$10473 + cell $not $not$libresoc.v:168451$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:165026$10473_Y + connect \Y $not$libresoc.v:168451$10871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165027$10474 + cell $not $not$libresoc.v:168452$10872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:165027$10474_Y + connect \Y $not$libresoc.v:168452$10872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165028$10475 + cell $not $not$libresoc.v:168453$10873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:165028$10475_Y + connect \Y $not$libresoc.v:168453$10873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165029$10476 + cell $not $not$libresoc.v:168454$10874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:165029$10476_Y + connect \Y $not$libresoc.v:168454$10874_Y end - attribute \src "libresoc.v:164957.7-164957.20" - process $proc$libresoc.v:164957$10547 + attribute \src "libresoc.v:168382.7-168382.20" + process $proc$libresoc.v:168382$10945 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164984.13-164984.30" - process $proc$libresoc.v:164984$10548 + attribute \src "libresoc.v:168409.13-168409.30" + process $proc$libresoc.v:168409$10946 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:164990.13-164990.25" - process $proc$libresoc.v:164990$10549 + attribute \src "libresoc.v:168415.13-168415.25" + process $proc$libresoc.v:168415$10947 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:164995.13-164995.33" - process $proc$libresoc.v:164995$10550 + attribute \src "libresoc.v:168420.13-168420.33" + process $proc$libresoc.v:168420$10948 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:165002.13-165002.33" - process $proc$libresoc.v:165002$10551 + attribute \src "libresoc.v:168427.13-168427.33" + process $proc$libresoc.v:168427$10949 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:165009.13-165009.33" - process $proc$libresoc.v:165009$10552 + attribute \src "libresoc.v:168434.13-168434.33" + process $proc$libresoc.v:168434$10950 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:165030.3-165031.25" - process $proc$libresoc.v:165030$10477 + attribute \src "libresoc.v:168455.3-168456.25" + process $proc$libresoc.v:168455$10875 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:165032.3-165033.37" - process $proc$libresoc.v:165032$10478 + attribute \src "libresoc.v:168457.3-168458.37" + process $proc$libresoc.v:168457$10876 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:165034.3-165035.43" - process $proc$libresoc.v:165034$10479 + attribute \src "libresoc.v:168459.3-168460.43" + process $proc$libresoc.v:168459$10877 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:165036.3-165037.43" - process $proc$libresoc.v:165036$10480 + attribute \src "libresoc.v:168461.3-168462.43" + process $proc$libresoc.v:168461$10878 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:165038.3-165039.43" - process $proc$libresoc.v:165038$10481 + attribute \src "libresoc.v:168463.3-168464.43" + process $proc$libresoc.v:168463$10879 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:165040.3-165085.6" - process $proc$libresoc.v:165040$10482 + attribute \src "libresoc.v:168465.3-168510.6" + process $proc$libresoc.v:168465$10880 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10483 $7\src11__data_o$next[1:0]$10490 - attribute \src "libresoc.v:165041.5-165041.29" + assign $0\src11__data_o$next[1:0]$10881 $7\src11__data_o$next[1:0]$10888 + attribute \src "libresoc.v:168466.5-168466.29" switch \initial - attribute \src "libresoc.v:165041.9-165041.17" + attribute \src "libresoc.v:168466.9-168466.17" case 1'1 case end @@ -340642,75 +348572,75 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10484 $6\src11__data_o$next[1:0]$10489 + assign $1\src11__data_o$next[1:0]$10882 $6\src11__data_o$next[1:0]$10887 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10485 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10883 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10485 2'00 + assign $2\src11__data_o$next[1:0]$10883 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10486 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10884 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10486 $2\src11__data_o$next[1:0]$10485 + assign $3\src11__data_o$next[1:0]$10884 $2\src11__data_o$next[1:0]$10883 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10487 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10885 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10487 $3\src11__data_o$next[1:0]$10486 + assign $4\src11__data_o$next[1:0]$10885 $3\src11__data_o$next[1:0]$10884 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10488 \w1__data_i + assign $5\src11__data_o$next[1:0]$10886 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10488 $4\src11__data_o$next[1:0]$10487 + assign $5\src11__data_o$next[1:0]$10886 $4\src11__data_o$next[1:0]$10885 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10489 \reg + assign $6\src11__data_o$next[1:0]$10887 \reg case - assign $6\src11__data_o$next[1:0]$10489 $5\src11__data_o$next[1:0]$10488 + assign $6\src11__data_o$next[1:0]$10887 $5\src11__data_o$next[1:0]$10886 end case - assign $1\src11__data_o$next[1:0]$10484 2'00 + assign $1\src11__data_o$next[1:0]$10882 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10490 2'00 + assign $7\src11__data_o$next[1:0]$10888 2'00 case - assign $7\src11__data_o$next[1:0]$10490 $1\src11__data_o$next[1:0]$10484 + assign $7\src11__data_o$next[1:0]$10888 $1\src11__data_o$next[1:0]$10882 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10483 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10881 end - attribute \src "libresoc.v:165086.3-165121.6" - process $proc$libresoc.v:165086$10491 + attribute \src "libresoc.v:168511.3-168546.6" + process $proc$libresoc.v:168511$10889 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:165087.5-165087.29" + attribute \src "libresoc.v:168512.5-168512.29" switch \initial - attribute \src "libresoc.v:165087.9-165087.17" + attribute \src "libresoc.v:168512.9-168512.17" case 1'1 case end @@ -340766,15 +348696,15 @@ module \reg_1$130 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:165122.3-165167.6" - process $proc$libresoc.v:165122$10492 + attribute \src "libresoc.v:168547.3-168592.6" + process $proc$libresoc.v:168547$10890 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10493 $7\src21__data_o$next[1:0]$10500 - attribute \src "libresoc.v:165123.5-165123.29" + assign $0\src21__data_o$next[1:0]$10891 $7\src21__data_o$next[1:0]$10898 + attribute \src "libresoc.v:168548.5-168548.29" switch \initial - attribute \src "libresoc.v:165123.9-165123.17" + attribute \src "libresoc.v:168548.9-168548.17" case 1'1 case end @@ -340787,75 +348717,75 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10494 $6\src21__data_o$next[1:0]$10499 + assign $1\src21__data_o$next[1:0]$10892 $6\src21__data_o$next[1:0]$10897 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10495 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10893 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10495 2'00 + assign $2\src21__data_o$next[1:0]$10893 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10496 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10894 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10496 $2\src21__data_o$next[1:0]$10495 + assign $3\src21__data_o$next[1:0]$10894 $2\src21__data_o$next[1:0]$10893 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$10497 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10895 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$10497 $3\src21__data_o$next[1:0]$10496 + assign $4\src21__data_o$next[1:0]$10895 $3\src21__data_o$next[1:0]$10894 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$10498 \w1__data_i + assign $5\src21__data_o$next[1:0]$10896 \w1__data_i case - assign $5\src21__data_o$next[1:0]$10498 $4\src21__data_o$next[1:0]$10497 + assign $5\src21__data_o$next[1:0]$10896 $4\src21__data_o$next[1:0]$10895 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$10499 \reg + assign $6\src21__data_o$next[1:0]$10897 \reg case - assign $6\src21__data_o$next[1:0]$10499 $5\src21__data_o$next[1:0]$10498 + assign $6\src21__data_o$next[1:0]$10897 $5\src21__data_o$next[1:0]$10896 end case - assign $1\src21__data_o$next[1:0]$10494 2'00 + assign $1\src21__data_o$next[1:0]$10892 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$10500 2'00 + assign $7\src21__data_o$next[1:0]$10898 2'00 case - assign $7\src21__data_o$next[1:0]$10500 $1\src21__data_o$next[1:0]$10494 + assign $7\src21__data_o$next[1:0]$10898 $1\src21__data_o$next[1:0]$10892 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10493 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10891 end - attribute \src "libresoc.v:165168.3-165203.6" - process $proc$libresoc.v:165168$10501 + attribute \src "libresoc.v:168593.3-168628.6" + process $proc$libresoc.v:168593$10899 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10502 $1\wr_detect$4[0:0]$10503 - attribute \src "libresoc.v:165169.5-165169.29" + assign $0\wr_detect$4[0:0]$10900 $1\wr_detect$4[0:0]$10901 + attribute \src "libresoc.v:168594.5-168594.29" switch \initial - attribute \src "libresoc.v:165169.9-165169.17" + attribute \src "libresoc.v:168594.9-168594.17" case 1'1 case end @@ -340868,58 +348798,58 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10503 $5\wr_detect$4[0:0]$10507 + assign $1\wr_detect$4[0:0]$10901 $5\wr_detect$4[0:0]$10905 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10504 1'1 + assign $2\wr_detect$4[0:0]$10902 1'1 case - assign $2\wr_detect$4[0:0]$10504 1'0 + assign $2\wr_detect$4[0:0]$10902 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10505 1'1 + assign $3\wr_detect$4[0:0]$10903 1'1 case - assign $3\wr_detect$4[0:0]$10505 $2\wr_detect$4[0:0]$10504 + assign $3\wr_detect$4[0:0]$10903 $2\wr_detect$4[0:0]$10902 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10506 1'1 + assign $4\wr_detect$4[0:0]$10904 1'1 case - assign $4\wr_detect$4[0:0]$10506 $3\wr_detect$4[0:0]$10505 + assign $4\wr_detect$4[0:0]$10904 $3\wr_detect$4[0:0]$10903 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10507 1'1 + assign $5\wr_detect$4[0:0]$10905 1'1 case - assign $5\wr_detect$4[0:0]$10507 $4\wr_detect$4[0:0]$10506 + assign $5\wr_detect$4[0:0]$10905 $4\wr_detect$4[0:0]$10904 end case - assign $1\wr_detect$4[0:0]$10503 1'0 + assign $1\wr_detect$4[0:0]$10901 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10502 + update \wr_detect$4 $0\wr_detect$4[0:0]$10900 end - attribute \src "libresoc.v:165204.3-165249.6" - process $proc$libresoc.v:165204$10508 + attribute \src "libresoc.v:168629.3-168674.6" + process $proc$libresoc.v:168629$10906 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$10509 $7\src31__data_o$next[1:0]$10516 - attribute \src "libresoc.v:165205.5-165205.29" + assign $0\src31__data_o$next[1:0]$10907 $7\src31__data_o$next[1:0]$10914 + attribute \src "libresoc.v:168630.5-168630.29" switch \initial - attribute \src "libresoc.v:165205.9-165205.17" + attribute \src "libresoc.v:168630.9-168630.17" case 1'1 case end @@ -340932,75 +348862,75 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$10510 $6\src31__data_o$next[1:0]$10515 + assign $1\src31__data_o$next[1:0]$10908 $6\src31__data_o$next[1:0]$10913 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$10511 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10909 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$10511 2'00 + assign $2\src31__data_o$next[1:0]$10909 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$10512 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10910 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$10512 $2\src31__data_o$next[1:0]$10511 + assign $3\src31__data_o$next[1:0]$10910 $2\src31__data_o$next[1:0]$10909 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$10513 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10911 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$10513 $3\src31__data_o$next[1:0]$10512 + assign $4\src31__data_o$next[1:0]$10911 $3\src31__data_o$next[1:0]$10910 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$10514 \w1__data_i + assign $5\src31__data_o$next[1:0]$10912 \w1__data_i case - assign $5\src31__data_o$next[1:0]$10514 $4\src31__data_o$next[1:0]$10513 + assign $5\src31__data_o$next[1:0]$10912 $4\src31__data_o$next[1:0]$10911 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$10515 \reg + assign $6\src31__data_o$next[1:0]$10913 \reg case - assign $6\src31__data_o$next[1:0]$10515 $5\src31__data_o$next[1:0]$10514 + assign $6\src31__data_o$next[1:0]$10913 $5\src31__data_o$next[1:0]$10912 end case - assign $1\src31__data_o$next[1:0]$10510 2'00 + assign $1\src31__data_o$next[1:0]$10908 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$10516 2'00 + assign $7\src31__data_o$next[1:0]$10914 2'00 case - assign $7\src31__data_o$next[1:0]$10516 $1\src31__data_o$next[1:0]$10510 + assign $7\src31__data_o$next[1:0]$10914 $1\src31__data_o$next[1:0]$10908 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10509 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10907 end - attribute \src "libresoc.v:165250.3-165285.6" - process $proc$libresoc.v:165250$10517 + attribute \src "libresoc.v:168675.3-168710.6" + process $proc$libresoc.v:168675$10915 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10518 $1\wr_detect$7[0:0]$10519 - attribute \src "libresoc.v:165251.5-165251.29" + assign $0\wr_detect$7[0:0]$10916 $1\wr_detect$7[0:0]$10917 + attribute \src "libresoc.v:168676.5-168676.29" switch \initial - attribute \src "libresoc.v:165251.9-165251.17" + attribute \src "libresoc.v:168676.9-168676.17" case 1'1 case end @@ -341013,58 +348943,58 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10519 $5\wr_detect$7[0:0]$10523 + assign $1\wr_detect$7[0:0]$10917 $5\wr_detect$7[0:0]$10921 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10520 1'1 + assign $2\wr_detect$7[0:0]$10918 1'1 case - assign $2\wr_detect$7[0:0]$10520 1'0 + assign $2\wr_detect$7[0:0]$10918 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10521 1'1 + assign $3\wr_detect$7[0:0]$10919 1'1 case - assign $3\wr_detect$7[0:0]$10521 $2\wr_detect$7[0:0]$10520 + assign $3\wr_detect$7[0:0]$10919 $2\wr_detect$7[0:0]$10918 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10522 1'1 + assign $4\wr_detect$7[0:0]$10920 1'1 case - assign $4\wr_detect$7[0:0]$10522 $3\wr_detect$7[0:0]$10521 + assign $4\wr_detect$7[0:0]$10920 $3\wr_detect$7[0:0]$10919 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10523 1'1 + assign $5\wr_detect$7[0:0]$10921 1'1 case - assign $5\wr_detect$7[0:0]$10523 $4\wr_detect$7[0:0]$10522 + assign $5\wr_detect$7[0:0]$10921 $4\wr_detect$7[0:0]$10920 end case - assign $1\wr_detect$7[0:0]$10519 1'0 + assign $1\wr_detect$7[0:0]$10917 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10518 + update \wr_detect$7 $0\wr_detect$7[0:0]$10916 end - attribute \src "libresoc.v:165286.3-165331.6" - process $proc$libresoc.v:165286$10524 + attribute \src "libresoc.v:168711.3-168756.6" + process $proc$libresoc.v:168711$10922 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$10525 $7\r1__data_o$next[1:0]$10532 - attribute \src "libresoc.v:165287.5-165287.29" + assign $0\r1__data_o$next[1:0]$10923 $7\r1__data_o$next[1:0]$10930 + attribute \src "libresoc.v:168712.5-168712.29" switch \initial - attribute \src "libresoc.v:165287.9-165287.17" + attribute \src "libresoc.v:168712.9-168712.17" case 1'1 case end @@ -341077,75 +349007,75 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$10526 $6\r1__data_o$next[1:0]$10531 + assign $1\r1__data_o$next[1:0]$10924 $6\r1__data_o$next[1:0]$10929 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$10527 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10925 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$10527 2'00 + assign $2\r1__data_o$next[1:0]$10925 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$10528 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10926 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$10528 $2\r1__data_o$next[1:0]$10527 + assign $3\r1__data_o$next[1:0]$10926 $2\r1__data_o$next[1:0]$10925 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$10529 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10927 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$10529 $3\r1__data_o$next[1:0]$10528 + assign $4\r1__data_o$next[1:0]$10927 $3\r1__data_o$next[1:0]$10926 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$10530 \w1__data_i + assign $5\r1__data_o$next[1:0]$10928 \w1__data_i case - assign $5\r1__data_o$next[1:0]$10530 $4\r1__data_o$next[1:0]$10529 + assign $5\r1__data_o$next[1:0]$10928 $4\r1__data_o$next[1:0]$10927 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$10531 \reg + assign $6\r1__data_o$next[1:0]$10929 \reg case - assign $6\r1__data_o$next[1:0]$10531 $5\r1__data_o$next[1:0]$10530 + assign $6\r1__data_o$next[1:0]$10929 $5\r1__data_o$next[1:0]$10928 end case - assign $1\r1__data_o$next[1:0]$10526 2'00 + assign $1\r1__data_o$next[1:0]$10924 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$10532 2'00 + assign $7\r1__data_o$next[1:0]$10930 2'00 case - assign $7\r1__data_o$next[1:0]$10532 $1\r1__data_o$next[1:0]$10526 + assign $7\r1__data_o$next[1:0]$10930 $1\r1__data_o$next[1:0]$10924 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10525 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10923 end - attribute \src "libresoc.v:165332.3-165367.6" - process $proc$libresoc.v:165332$10533 + attribute \src "libresoc.v:168757.3-168792.6" + process $proc$libresoc.v:168757$10931 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10534 $1\wr_detect$10[0:0]$10535 - attribute \src "libresoc.v:165333.5-165333.29" + assign $0\wr_detect$10[0:0]$10932 $1\wr_detect$10[0:0]$10933 + attribute \src "libresoc.v:168758.5-168758.29" switch \initial - attribute \src "libresoc.v:165333.9-165333.17" + attribute \src "libresoc.v:168758.9-168758.17" case 1'1 case end @@ -341158,61 +349088,61 @@ module \reg_1$130 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10535 $5\wr_detect$10[0:0]$10539 + assign $1\wr_detect$10[0:0]$10933 $5\wr_detect$10[0:0]$10937 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10536 1'1 + assign $2\wr_detect$10[0:0]$10934 1'1 case - assign $2\wr_detect$10[0:0]$10536 1'0 + assign $2\wr_detect$10[0:0]$10934 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10537 1'1 + assign $3\wr_detect$10[0:0]$10935 1'1 case - assign $3\wr_detect$10[0:0]$10537 $2\wr_detect$10[0:0]$10536 + assign $3\wr_detect$10[0:0]$10935 $2\wr_detect$10[0:0]$10934 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10538 1'1 + assign $4\wr_detect$10[0:0]$10936 1'1 case - assign $4\wr_detect$10[0:0]$10538 $3\wr_detect$10[0:0]$10537 + assign $4\wr_detect$10[0:0]$10936 $3\wr_detect$10[0:0]$10935 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10539 1'1 + assign $5\wr_detect$10[0:0]$10937 1'1 case - assign $5\wr_detect$10[0:0]$10539 $4\wr_detect$10[0:0]$10538 + assign $5\wr_detect$10[0:0]$10937 $4\wr_detect$10[0:0]$10936 end case - assign $1\wr_detect$10[0:0]$10535 1'0 + assign $1\wr_detect$10[0:0]$10933 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10534 + update \wr_detect$10 $0\wr_detect$10[0:0]$10932 end - attribute \src "libresoc.v:165368.3-165400.6" - process $proc$libresoc.v:165368$10540 + attribute \src "libresoc.v:168793.3-168825.6" + process $proc$libresoc.v:168793$10938 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10541 $5\reg$next[1:0]$10546 - attribute \src "libresoc.v:165369.5-165369.29" + assign $0\reg$next[1:0]$10939 $5\reg$next[1:0]$10944 + attribute \src "libresoc.v:168794.5-168794.29" switch \initial - attribute \src "libresoc.v:165369.9-165369.17" + attribute \src "libresoc.v:168794.9-168794.17" case 1'1 case end @@ -341221,135 +349151,135 @@ module \reg_1$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10542 \dest11__data_i + assign $1\reg$next[1:0]$10940 \dest11__data_i case - assign $1\reg$next[1:0]$10542 \reg + assign $1\reg$next[1:0]$10940 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10543 \dest21__data_i + assign $2\reg$next[1:0]$10941 \dest21__data_i case - assign $2\reg$next[1:0]$10543 $1\reg$next[1:0]$10542 + assign $2\reg$next[1:0]$10941 $1\reg$next[1:0]$10940 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10544 \dest31__data_i + assign $3\reg$next[1:0]$10942 \dest31__data_i case - assign $3\reg$next[1:0]$10544 $2\reg$next[1:0]$10543 + assign $3\reg$next[1:0]$10942 $2\reg$next[1:0]$10941 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10545 \w1__data_i + assign $4\reg$next[1:0]$10943 \w1__data_i case - assign $4\reg$next[1:0]$10545 $3\reg$next[1:0]$10544 + assign $4\reg$next[1:0]$10943 $3\reg$next[1:0]$10942 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10546 2'00 + assign $5\reg$next[1:0]$10944 2'00 case - assign $5\reg$next[1:0]$10546 $4\reg$next[1:0]$10545 + assign $5\reg$next[1:0]$10944 $4\reg$next[1:0]$10943 end sync always - update \reg$next $0\reg$next[1:0]$10541 + update \reg$next $0\reg$next[1:0]$10939 end - connect \$9 $not$libresoc.v:165026$10473_Y - connect \$1 $not$libresoc.v:165027$10474_Y - connect \$3 $not$libresoc.v:165028$10475_Y - connect \$6 $not$libresoc.v:165029$10476_Y + connect \$9 $not$libresoc.v:168451$10871_Y + connect \$1 $not$libresoc.v:168452$10872_Y + connect \$3 $not$libresoc.v:168453$10873_Y + connect \$6 $not$libresoc.v:168454$10874_Y end -attribute \src "libresoc.v:165405.1-165624.10" +attribute \src "libresoc.v:168830.1-169049.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" -module \reg_1$133 - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $0\cia1__data_o$next[63:0]$10559 - attribute \src "libresoc.v:165455.3-165456.41" +module \reg_1$136 + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $0\cia1__data_o$next[63:0]$10957 + attribute \src "libresoc.v:168880.3-168881.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:165406.7-165406.20" + attribute \src "libresoc.v:168831.7-168831.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $0\msr1__data_o$next[63:0]$10568 - attribute \src "libresoc.v:165453.3-165454.41" + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $0\msr1__data_o$next[63:0]$10966 + attribute \src "libresoc.v:168878.3-168879.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:165597.3-165623.6" - wire width 64 $0\reg$next[63:0]$10582 - attribute \src "libresoc.v:165451.3-165452.25" + attribute \src "libresoc.v:169022.3-169048.6" + wire width 64 $0\reg$next[63:0]$10980 + attribute \src "libresoc.v:168876.3-168877.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:165567.3-165596.6" - wire $0\wr_detect$4[0:0]$10576 - attribute \src "libresoc.v:165497.3-165526.6" + attribute \src "libresoc.v:168992.3-169021.6" + wire $0\wr_detect$4[0:0]$10974 + attribute \src "libresoc.v:168922.3-168951.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $1\cia1__data_o$next[63:0]$10560 - attribute \src "libresoc.v:165413.14-165413.49" + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $1\cia1__data_o$next[63:0]$10958 + attribute \src "libresoc.v:168838.14-168838.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $1\msr1__data_o$next[63:0]$10569 - attribute \src "libresoc.v:165430.14-165430.49" + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $1\msr1__data_o$next[63:0]$10967 + attribute \src "libresoc.v:168855.14-168855.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:165597.3-165623.6" - wire width 64 $1\reg$next[63:0]$10583 - attribute \src "libresoc.v:165442.14-165442.42" + attribute \src "libresoc.v:169022.3-169048.6" + wire width 64 $1\reg$next[63:0]$10981 + attribute \src "libresoc.v:168867.14-168867.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:165567.3-165596.6" - wire $1\wr_detect$4[0:0]$10577 - attribute \src "libresoc.v:165497.3-165526.6" + attribute \src "libresoc.v:168992.3-169021.6" + wire $1\wr_detect$4[0:0]$10975 + attribute \src "libresoc.v:168922.3-168951.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $2\cia1__data_o$next[63:0]$10561 - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $2\msr1__data_o$next[63:0]$10570 - attribute \src "libresoc.v:165597.3-165623.6" - wire width 64 $2\reg$next[63:0]$10584 - attribute \src "libresoc.v:165567.3-165596.6" - wire $2\wr_detect$4[0:0]$10578 - attribute \src "libresoc.v:165497.3-165526.6" + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $2\cia1__data_o$next[63:0]$10959 + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $2\msr1__data_o$next[63:0]$10968 + attribute \src "libresoc.v:169022.3-169048.6" + wire width 64 $2\reg$next[63:0]$10982 + attribute \src "libresoc.v:168992.3-169021.6" + wire $2\wr_detect$4[0:0]$10976 + attribute \src "libresoc.v:168922.3-168951.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $3\cia1__data_o$next[63:0]$10562 - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $3\msr1__data_o$next[63:0]$10571 - attribute \src "libresoc.v:165597.3-165623.6" - wire width 64 $3\reg$next[63:0]$10585 - attribute \src "libresoc.v:165567.3-165596.6" - wire $3\wr_detect$4[0:0]$10579 - attribute \src "libresoc.v:165497.3-165526.6" + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $3\cia1__data_o$next[63:0]$10960 + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $3\msr1__data_o$next[63:0]$10969 + attribute \src "libresoc.v:169022.3-169048.6" + wire width 64 $3\reg$next[63:0]$10983 + attribute \src "libresoc.v:168992.3-169021.6" + wire $3\wr_detect$4[0:0]$10977 + attribute \src "libresoc.v:168922.3-168951.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $4\cia1__data_o$next[63:0]$10563 - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $4\msr1__data_o$next[63:0]$10572 - attribute \src "libresoc.v:165597.3-165623.6" - wire width 64 $4\reg$next[63:0]$10586 - attribute \src "libresoc.v:165567.3-165596.6" - wire $4\wr_detect$4[0:0]$10580 - attribute \src "libresoc.v:165497.3-165526.6" + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $4\cia1__data_o$next[63:0]$10961 + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $4\msr1__data_o$next[63:0]$10970 + attribute \src "libresoc.v:169022.3-169048.6" + wire width 64 $4\reg$next[63:0]$10984 + attribute \src "libresoc.v:168992.3-169021.6" + wire $4\wr_detect$4[0:0]$10978 + attribute \src "libresoc.v:168922.3-168951.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $5\cia1__data_o$next[63:0]$10564 - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $5\msr1__data_o$next[63:0]$10573 - attribute \src "libresoc.v:165457.3-165496.6" - wire width 64 $6\cia1__data_o$next[63:0]$10565 - attribute \src "libresoc.v:165527.3-165566.6" - wire width 64 $6\msr1__data_o$next[63:0]$10574 - attribute \src "libresoc.v:165449.17-165449.100" - wire $not$libresoc.v:165449$10553_Y - attribute \src "libresoc.v:165450.17-165450.103" - wire $not$libresoc.v:165450$10554_Y + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $5\cia1__data_o$next[63:0]$10962 + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $5\msr1__data_o$next[63:0]$10971 + attribute \src "libresoc.v:168882.3-168921.6" + wire width 64 $6\cia1__data_o$next[63:0]$10963 + attribute \src "libresoc.v:168952.3-168991.6" + wire width 64 $6\msr1__data_o$next[63:0]$10972 + attribute \src "libresoc.v:168874.17-168874.100" + wire $not$libresoc.v:168874$10951_Y + attribute \src "libresoc.v:168875.17-168875.103" + wire $not$libresoc.v:168875$10952_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -341360,15 +349290,15 @@ module \reg_1$133 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \d_wr11__wen - attribute \src "libresoc.v:165406.7-165406.15" + attribute \src "libresoc.v:168831.7-168831.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 9 \msr1__data_i @@ -341393,83 +349323,83 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165449$10553 + cell $not $not$libresoc.v:168874$10951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:165449$10553_Y + connect \Y $not$libresoc.v:168874$10951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165450$10554 + cell $not $not$libresoc.v:168875$10952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:165450$10554_Y + connect \Y $not$libresoc.v:168875$10952_Y end - attribute \src "libresoc.v:165406.7-165406.20" - process $proc$libresoc.v:165406$10587 + attribute \src "libresoc.v:168831.7-168831.20" + process $proc$libresoc.v:168831$10985 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165413.14-165413.49" - process $proc$libresoc.v:165413$10588 + attribute \src "libresoc.v:168838.14-168838.49" + process $proc$libresoc.v:168838$10986 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:165430.14-165430.49" - process $proc$libresoc.v:165430$10589 + attribute \src "libresoc.v:168855.14-168855.49" + process $proc$libresoc.v:168855$10987 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:165442.14-165442.42" - process $proc$libresoc.v:165442$10590 + attribute \src "libresoc.v:168867.14-168867.42" + process $proc$libresoc.v:168867$10988 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:165451.3-165452.25" - process $proc$libresoc.v:165451$10555 + attribute \src "libresoc.v:168876.3-168877.25" + process $proc$libresoc.v:168876$10953 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:165453.3-165454.41" - process $proc$libresoc.v:165453$10556 + attribute \src "libresoc.v:168878.3-168879.41" + process $proc$libresoc.v:168878$10954 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:165455.3-165456.41" - process $proc$libresoc.v:165455$10557 + attribute \src "libresoc.v:168880.3-168881.41" + process $proc$libresoc.v:168880$10955 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:165457.3-165496.6" - process $proc$libresoc.v:165457$10558 + attribute \src "libresoc.v:168882.3-168921.6" + process $proc$libresoc.v:168882$10956 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$10559 $6\cia1__data_o$next[63:0]$10565 - attribute \src "libresoc.v:165458.5-165458.29" + assign $0\cia1__data_o$next[63:0]$10957 $6\cia1__data_o$next[63:0]$10963 + attribute \src "libresoc.v:168883.5-168883.29" switch \initial - attribute \src "libresoc.v:165458.9-165458.17" + attribute \src "libresoc.v:168883.9-168883.17" case 1'1 case end @@ -341481,66 +349411,66 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$10560 $5\cia1__data_o$next[63:0]$10564 + assign $1\cia1__data_o$next[63:0]$10958 $5\cia1__data_o$next[63:0]$10962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$10561 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$10959 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$10561 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$10959 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$10562 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$10960 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$10562 $2\cia1__data_o$next[63:0]$10561 + assign $3\cia1__data_o$next[63:0]$10960 $2\cia1__data_o$next[63:0]$10959 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$10563 \d_wr11__data_i + assign $4\cia1__data_o$next[63:0]$10961 \d_wr11__data_i case - assign $4\cia1__data_o$next[63:0]$10563 $3\cia1__data_o$next[63:0]$10562 + assign $4\cia1__data_o$next[63:0]$10961 $3\cia1__data_o$next[63:0]$10960 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$10564 \reg + assign $5\cia1__data_o$next[63:0]$10962 \reg case - assign $5\cia1__data_o$next[63:0]$10564 $4\cia1__data_o$next[63:0]$10563 + assign $5\cia1__data_o$next[63:0]$10962 $4\cia1__data_o$next[63:0]$10961 end case - assign $1\cia1__data_o$next[63:0]$10560 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$10565 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia1__data_o$next[63:0]$10565 $1\cia1__data_o$next[63:0]$10560 + assign $6\cia1__data_o$next[63:0]$10963 $1\cia1__data_o$next[63:0]$10958 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10559 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10957 end - attribute \src "libresoc.v:165497.3-165526.6" - process $proc$libresoc.v:165497$10566 + attribute \src "libresoc.v:168922.3-168951.6" + process $proc$libresoc.v:168922$10964 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:165498.5-165498.29" + attribute \src "libresoc.v:168923.5-168923.29" switch \initial - attribute \src "libresoc.v:165498.9-165498.17" + attribute \src "libresoc.v:168923.9-168923.17" case 1'1 case end @@ -341586,15 +349516,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:165527.3-165566.6" - process $proc$libresoc.v:165527$10567 + attribute \src "libresoc.v:168952.3-168991.6" + process $proc$libresoc.v:168952$10965 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$10568 $6\msr1__data_o$next[63:0]$10574 - attribute \src "libresoc.v:165528.5-165528.29" + assign $0\msr1__data_o$next[63:0]$10966 $6\msr1__data_o$next[63:0]$10972 + attribute \src "libresoc.v:168953.5-168953.29" switch \initial - attribute \src "libresoc.v:165528.9-165528.17" + attribute \src "libresoc.v:168953.9-168953.17" case 1'1 case end @@ -341606,66 +349536,66 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$10569 $5\msr1__data_o$next[63:0]$10573 + assign $1\msr1__data_o$next[63:0]$10967 $5\msr1__data_o$next[63:0]$10971 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$10570 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$10968 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$10570 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$10968 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$10571 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$10969 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$10571 $2\msr1__data_o$next[63:0]$10570 + assign $3\msr1__data_o$next[63:0]$10969 $2\msr1__data_o$next[63:0]$10968 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$10572 \d_wr11__data_i + assign $4\msr1__data_o$next[63:0]$10970 \d_wr11__data_i case - assign $4\msr1__data_o$next[63:0]$10572 $3\msr1__data_o$next[63:0]$10571 + assign $4\msr1__data_o$next[63:0]$10970 $3\msr1__data_o$next[63:0]$10969 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$10573 \reg + assign $5\msr1__data_o$next[63:0]$10971 \reg case - assign $5\msr1__data_o$next[63:0]$10573 $4\msr1__data_o$next[63:0]$10572 + assign $5\msr1__data_o$next[63:0]$10971 $4\msr1__data_o$next[63:0]$10970 end case - assign $1\msr1__data_o$next[63:0]$10569 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$10967 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$10574 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\msr1__data_o$next[63:0]$10972 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr1__data_o$next[63:0]$10574 $1\msr1__data_o$next[63:0]$10569 + assign $6\msr1__data_o$next[63:0]$10972 $1\msr1__data_o$next[63:0]$10967 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10568 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10966 end - attribute \src "libresoc.v:165567.3-165596.6" - process $proc$libresoc.v:165567$10575 + attribute \src "libresoc.v:168992.3-169021.6" + process $proc$libresoc.v:168992$10973 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10576 $1\wr_detect$4[0:0]$10577 - attribute \src "libresoc.v:165568.5-165568.29" + assign $0\wr_detect$4[0:0]$10974 $1\wr_detect$4[0:0]$10975 + attribute \src "libresoc.v:168993.5-168993.29" switch \initial - attribute \src "libresoc.v:165568.9-165568.17" + attribute \src "libresoc.v:168993.9-168993.17" case 1'1 case end @@ -341677,51 +349607,51 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10577 $4\wr_detect$4[0:0]$10580 + assign $1\wr_detect$4[0:0]$10975 $4\wr_detect$4[0:0]$10978 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10578 1'1 + assign $2\wr_detect$4[0:0]$10976 1'1 case - assign $2\wr_detect$4[0:0]$10578 1'0 + assign $2\wr_detect$4[0:0]$10976 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10579 1'1 + assign $3\wr_detect$4[0:0]$10977 1'1 case - assign $3\wr_detect$4[0:0]$10579 $2\wr_detect$4[0:0]$10578 + assign $3\wr_detect$4[0:0]$10977 $2\wr_detect$4[0:0]$10976 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10580 1'1 + assign $4\wr_detect$4[0:0]$10978 1'1 case - assign $4\wr_detect$4[0:0]$10580 $3\wr_detect$4[0:0]$10579 + assign $4\wr_detect$4[0:0]$10978 $3\wr_detect$4[0:0]$10977 end case - assign $1\wr_detect$4[0:0]$10577 1'0 + assign $1\wr_detect$4[0:0]$10975 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10576 + update \wr_detect$4 $0\wr_detect$4[0:0]$10974 end - attribute \src "libresoc.v:165597.3-165623.6" - process $proc$libresoc.v:165597$10581 + attribute \src "libresoc.v:169022.3-169048.6" + process $proc$libresoc.v:169022$10979 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10582 $4\reg$next[63:0]$10586 - attribute \src "libresoc.v:165598.5-165598.29" + assign $0\reg$next[63:0]$10980 $4\reg$next[63:0]$10984 + attribute \src "libresoc.v:169023.5-169023.29" switch \initial - attribute \src "libresoc.v:165598.9-165598.17" + attribute \src "libresoc.v:169023.9-169023.17" case 1'1 case end @@ -341730,214 +349660,214 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10583 \nia1__data_i + assign $1\reg$next[63:0]$10981 \nia1__data_i case - assign $1\reg$next[63:0]$10583 \reg + assign $1\reg$next[63:0]$10981 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10584 \msr1__data_i + assign $2\reg$next[63:0]$10982 \msr1__data_i case - assign $2\reg$next[63:0]$10584 $1\reg$next[63:0]$10583 + assign $2\reg$next[63:0]$10982 $1\reg$next[63:0]$10981 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10585 \d_wr11__data_i + assign $3\reg$next[63:0]$10983 \d_wr11__data_i case - assign $3\reg$next[63:0]$10585 $2\reg$next[63:0]$10584 + assign $3\reg$next[63:0]$10983 $2\reg$next[63:0]$10982 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10586 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\reg$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10586 $3\reg$next[63:0]$10585 + assign $4\reg$next[63:0]$10984 $3\reg$next[63:0]$10983 end sync always - update \reg$next $0\reg$next[63:0]$10582 + update \reg$next $0\reg$next[63:0]$10980 end - connect \$1 $not$libresoc.v:165449$10553_Y - connect \$3 $not$libresoc.v:165450$10554_Y + connect \$1 $not$libresoc.v:168874$10951_Y + connect \$3 $not$libresoc.v:168875$10952_Y end -attribute \src "libresoc.v:165628.1-166099.10" +attribute \src "libresoc.v:169053.1-169524.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:165629.7-165629.20" + attribute \src "libresoc.v:169054.7-169054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $0\r22__data_o$next[3:0]$10660 - attribute \src "libresoc.v:165712.3-165713.39" + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $0\r22__data_o$next[3:0]$11058 + attribute \src "libresoc.v:169137.3-169138.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $0\r2__data_o$next[3:0]$10646 - attribute \src "libresoc.v:165714.3-165715.37" + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $0\r2__data_o$next[3:0]$11044 + attribute \src "libresoc.v:169139.3-169140.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:165792.3-165818.6" - wire width 4 $0\reg$next[3:0]$10612 - attribute \src "libresoc.v:165710.3-165711.25" + attribute \src "libresoc.v:169217.3-169243.6" + wire width 4 $0\reg$next[3:0]$11010 + attribute \src "libresoc.v:169135.3-169136.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $0\src12__data_o$next[3:0]$10603 - attribute \src "libresoc.v:165720.3-165721.43" + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $0\src12__data_o$next[3:0]$11001 + attribute \src "libresoc.v:169145.3-169146.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $0\src22__data_o$next[3:0]$10618 - attribute \src "libresoc.v:165718.3-165719.43" + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $0\src22__data_o$next[3:0]$11016 + attribute \src "libresoc.v:169143.3-169144.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $0\src32__data_o$next[3:0]$10632 - attribute \src "libresoc.v:165716.3-165717.43" + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $0\src32__data_o$next[3:0]$11030 + attribute \src "libresoc.v:169141.3-169142.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:165999.3-166028.6" - wire $0\wr_detect$10[0:0]$10654 - attribute \src "libresoc.v:166069.3-166098.6" - wire $0\wr_detect$13[0:0]$10668 - attribute \src "libresoc.v:165859.3-165888.6" - wire $0\wr_detect$4[0:0]$10626 - attribute \src "libresoc.v:165929.3-165958.6" - wire $0\wr_detect$7[0:0]$10640 - attribute \src "libresoc.v:165762.3-165791.6" + attribute \src "libresoc.v:169424.3-169453.6" + wire $0\wr_detect$10[0:0]$11052 + attribute \src "libresoc.v:169494.3-169523.6" + wire $0\wr_detect$13[0:0]$11066 + attribute \src "libresoc.v:169284.3-169313.6" + wire $0\wr_detect$4[0:0]$11024 + attribute \src "libresoc.v:169354.3-169383.6" + wire $0\wr_detect$7[0:0]$11038 + attribute \src "libresoc.v:169187.3-169216.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $1\r22__data_o$next[3:0]$10661 - attribute \src "libresoc.v:165654.13-165654.31" + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $1\r22__data_o$next[3:0]$11059 + attribute \src "libresoc.v:169079.13-169079.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $1\r2__data_o$next[3:0]$10647 - attribute \src "libresoc.v:165661.13-165661.30" + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $1\r2__data_o$next[3:0]$11045 + attribute \src "libresoc.v:169086.13-169086.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:165792.3-165818.6" - wire width 4 $1\reg$next[3:0]$10613 - attribute \src "libresoc.v:165667.13-165667.25" + attribute \src "libresoc.v:169217.3-169243.6" + wire width 4 $1\reg$next[3:0]$11011 + attribute \src "libresoc.v:169092.13-169092.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $1\src12__data_o$next[3:0]$10604 - attribute \src "libresoc.v:165672.13-165672.33" + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $1\src12__data_o$next[3:0]$11002 + attribute \src "libresoc.v:169097.13-169097.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $1\src22__data_o$next[3:0]$10619 - attribute \src "libresoc.v:165679.13-165679.33" + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $1\src22__data_o$next[3:0]$11017 + attribute \src "libresoc.v:169104.13-169104.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $1\src32__data_o$next[3:0]$10633 - attribute \src "libresoc.v:165686.13-165686.33" + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $1\src32__data_o$next[3:0]$11031 + attribute \src "libresoc.v:169111.13-169111.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:165999.3-166028.6" - wire $1\wr_detect$10[0:0]$10655 - attribute \src "libresoc.v:166069.3-166098.6" - wire $1\wr_detect$13[0:0]$10669 - attribute \src "libresoc.v:165859.3-165888.6" - wire $1\wr_detect$4[0:0]$10627 - attribute \src "libresoc.v:165929.3-165958.6" - wire $1\wr_detect$7[0:0]$10641 - attribute \src "libresoc.v:165762.3-165791.6" + attribute \src "libresoc.v:169424.3-169453.6" + wire $1\wr_detect$10[0:0]$11053 + attribute \src "libresoc.v:169494.3-169523.6" + wire $1\wr_detect$13[0:0]$11067 + attribute \src "libresoc.v:169284.3-169313.6" + wire $1\wr_detect$4[0:0]$11025 + attribute \src "libresoc.v:169354.3-169383.6" + wire $1\wr_detect$7[0:0]$11039 + attribute \src "libresoc.v:169187.3-169216.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $2\r22__data_o$next[3:0]$10662 - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $2\r2__data_o$next[3:0]$10648 - attribute \src "libresoc.v:165792.3-165818.6" - wire width 4 $2\reg$next[3:0]$10614 - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $2\src12__data_o$next[3:0]$10605 - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $2\src22__data_o$next[3:0]$10620 - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $2\src32__data_o$next[3:0]$10634 - attribute \src "libresoc.v:165999.3-166028.6" - wire $2\wr_detect$10[0:0]$10656 - attribute \src "libresoc.v:166069.3-166098.6" - wire $2\wr_detect$13[0:0]$10670 - attribute \src "libresoc.v:165859.3-165888.6" - wire $2\wr_detect$4[0:0]$10628 - attribute \src "libresoc.v:165929.3-165958.6" - wire $2\wr_detect$7[0:0]$10642 - attribute \src "libresoc.v:165762.3-165791.6" + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $2\r22__data_o$next[3:0]$11060 + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $2\r2__data_o$next[3:0]$11046 + attribute \src "libresoc.v:169217.3-169243.6" + wire width 4 $2\reg$next[3:0]$11012 + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $2\src12__data_o$next[3:0]$11003 + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $2\src22__data_o$next[3:0]$11018 + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $2\src32__data_o$next[3:0]$11032 + attribute \src "libresoc.v:169424.3-169453.6" + wire $2\wr_detect$10[0:0]$11054 + attribute \src "libresoc.v:169494.3-169523.6" + wire $2\wr_detect$13[0:0]$11068 + attribute \src "libresoc.v:169284.3-169313.6" + wire $2\wr_detect$4[0:0]$11026 + attribute \src "libresoc.v:169354.3-169383.6" + wire $2\wr_detect$7[0:0]$11040 + attribute \src "libresoc.v:169187.3-169216.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $3\r22__data_o$next[3:0]$10663 - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $3\r2__data_o$next[3:0]$10649 - attribute \src "libresoc.v:165792.3-165818.6" - wire width 4 $3\reg$next[3:0]$10615 - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $3\src12__data_o$next[3:0]$10606 - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $3\src22__data_o$next[3:0]$10621 - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $3\src32__data_o$next[3:0]$10635 - attribute \src "libresoc.v:165999.3-166028.6" - wire $3\wr_detect$10[0:0]$10657 - attribute \src "libresoc.v:166069.3-166098.6" - wire $3\wr_detect$13[0:0]$10671 - attribute \src "libresoc.v:165859.3-165888.6" - wire $3\wr_detect$4[0:0]$10629 - attribute \src "libresoc.v:165929.3-165958.6" - wire $3\wr_detect$7[0:0]$10643 - attribute \src "libresoc.v:165762.3-165791.6" + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $3\r22__data_o$next[3:0]$11061 + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $3\r2__data_o$next[3:0]$11047 + attribute \src "libresoc.v:169217.3-169243.6" + wire width 4 $3\reg$next[3:0]$11013 + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $3\src12__data_o$next[3:0]$11004 + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $3\src22__data_o$next[3:0]$11019 + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $3\src32__data_o$next[3:0]$11033 + attribute \src "libresoc.v:169424.3-169453.6" + wire $3\wr_detect$10[0:0]$11055 + attribute \src "libresoc.v:169494.3-169523.6" + wire $3\wr_detect$13[0:0]$11069 + attribute \src "libresoc.v:169284.3-169313.6" + wire $3\wr_detect$4[0:0]$11027 + attribute \src "libresoc.v:169354.3-169383.6" + wire $3\wr_detect$7[0:0]$11041 + attribute \src "libresoc.v:169187.3-169216.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $4\r22__data_o$next[3:0]$10664 - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $4\r2__data_o$next[3:0]$10650 - attribute \src "libresoc.v:165792.3-165818.6" - wire width 4 $4\reg$next[3:0]$10616 - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $4\src12__data_o$next[3:0]$10607 - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $4\src22__data_o$next[3:0]$10622 - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $4\src32__data_o$next[3:0]$10636 - attribute \src "libresoc.v:165999.3-166028.6" - wire $4\wr_detect$10[0:0]$10658 - attribute \src "libresoc.v:166069.3-166098.6" - wire $4\wr_detect$13[0:0]$10672 - attribute \src "libresoc.v:165859.3-165888.6" - wire $4\wr_detect$4[0:0]$10630 - attribute \src "libresoc.v:165929.3-165958.6" - wire $4\wr_detect$7[0:0]$10644 - attribute \src "libresoc.v:165762.3-165791.6" + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $4\r22__data_o$next[3:0]$11062 + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $4\r2__data_o$next[3:0]$11048 + attribute \src "libresoc.v:169217.3-169243.6" + wire width 4 $4\reg$next[3:0]$11014 + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $4\src12__data_o$next[3:0]$11005 + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $4\src22__data_o$next[3:0]$11020 + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $4\src32__data_o$next[3:0]$11034 + attribute \src "libresoc.v:169424.3-169453.6" + wire $4\wr_detect$10[0:0]$11056 + attribute \src "libresoc.v:169494.3-169523.6" + wire $4\wr_detect$13[0:0]$11070 + attribute \src "libresoc.v:169284.3-169313.6" + wire $4\wr_detect$4[0:0]$11028 + attribute \src "libresoc.v:169354.3-169383.6" + wire $4\wr_detect$7[0:0]$11042 + attribute \src "libresoc.v:169187.3-169216.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $5\r22__data_o$next[3:0]$10665 - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $5\r2__data_o$next[3:0]$10651 - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $5\src12__data_o$next[3:0]$10608 - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $5\src22__data_o$next[3:0]$10623 - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $5\src32__data_o$next[3:0]$10637 - attribute \src "libresoc.v:166029.3-166068.6" - wire width 4 $6\r22__data_o$next[3:0]$10666 - attribute \src "libresoc.v:165959.3-165998.6" - wire width 4 $6\r2__data_o$next[3:0]$10652 - attribute \src "libresoc.v:165722.3-165761.6" - wire width 4 $6\src12__data_o$next[3:0]$10609 - attribute \src "libresoc.v:165819.3-165858.6" - wire width 4 $6\src22__data_o$next[3:0]$10624 - attribute \src "libresoc.v:165889.3-165928.6" - wire width 4 $6\src32__data_o$next[3:0]$10638 - attribute \src "libresoc.v:165705.17-165705.104" - wire $not$libresoc.v:165705$10591_Y - attribute \src "libresoc.v:165706.18-165706.105" - wire $not$libresoc.v:165706$10592_Y - attribute \src "libresoc.v:165707.17-165707.100" - wire $not$libresoc.v:165707$10593_Y - attribute \src "libresoc.v:165708.17-165708.103" - wire $not$libresoc.v:165708$10594_Y - attribute \src "libresoc.v:165709.17-165709.103" - wire $not$libresoc.v:165709$10595_Y + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $5\r22__data_o$next[3:0]$11063 + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $5\r2__data_o$next[3:0]$11049 + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $5\src12__data_o$next[3:0]$11006 + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $5\src22__data_o$next[3:0]$11021 + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $5\src32__data_o$next[3:0]$11035 + attribute \src "libresoc.v:169454.3-169493.6" + wire width 4 $6\r22__data_o$next[3:0]$11064 + attribute \src "libresoc.v:169384.3-169423.6" + wire width 4 $6\r2__data_o$next[3:0]$11050 + attribute \src "libresoc.v:169147.3-169186.6" + wire width 4 $6\src12__data_o$next[3:0]$11007 + attribute \src "libresoc.v:169244.3-169283.6" + wire width 4 $6\src22__data_o$next[3:0]$11022 + attribute \src "libresoc.v:169314.3-169353.6" + wire width 4 $6\src32__data_o$next[3:0]$11036 + attribute \src "libresoc.v:169130.17-169130.104" + wire $not$libresoc.v:169130$10989_Y + attribute \src "libresoc.v:169131.18-169131.105" + wire $not$libresoc.v:169131$10990_Y + attribute \src "libresoc.v:169132.17-169132.100" + wire $not$libresoc.v:169132$10991_Y + attribute \src "libresoc.v:169133.17-169133.103" + wire $not$libresoc.v:169133$10992_Y + attribute \src "libresoc.v:169134.17-169134.103" + wire $not$libresoc.v:169134$10993_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -341948,9 +349878,9 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest12__data_i @@ -341960,7 +349890,7 @@ module \reg_2 wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest22__wen - attribute \src "libresoc.v:165629.7-165629.15" + attribute \src "libresoc.v:169054.7-169054.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r22__data_o @@ -342011,152 +349941,152 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165705$10591 + cell $not $not$libresoc.v:169130$10989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:165705$10591_Y + connect \Y $not$libresoc.v:169130$10989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165706$10592 + cell $not $not$libresoc.v:169131$10990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:165706$10592_Y + connect \Y $not$libresoc.v:169131$10990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165707$10593 + cell $not $not$libresoc.v:169132$10991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:165707$10593_Y + connect \Y $not$libresoc.v:169132$10991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165708$10594 + cell $not $not$libresoc.v:169133$10992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:165708$10594_Y + connect \Y $not$libresoc.v:169133$10992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:165709$10595 + cell $not $not$libresoc.v:169134$10993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:165709$10595_Y + connect \Y $not$libresoc.v:169134$10993_Y end - attribute \src "libresoc.v:165629.7-165629.20" - process $proc$libresoc.v:165629$10673 + attribute \src "libresoc.v:169054.7-169054.20" + process $proc$libresoc.v:169054$11071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165654.13-165654.31" - process $proc$libresoc.v:165654$10674 + attribute \src "libresoc.v:169079.13-169079.31" + process $proc$libresoc.v:169079$11072 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:165661.13-165661.30" - process $proc$libresoc.v:165661$10675 + attribute \src "libresoc.v:169086.13-169086.30" + process $proc$libresoc.v:169086$11073 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:165667.13-165667.25" - process $proc$libresoc.v:165667$10676 + attribute \src "libresoc.v:169092.13-169092.25" + process $proc$libresoc.v:169092$11074 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:165672.13-165672.33" - process $proc$libresoc.v:165672$10677 + attribute \src "libresoc.v:169097.13-169097.33" + process $proc$libresoc.v:169097$11075 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:165679.13-165679.33" - process $proc$libresoc.v:165679$10678 + attribute \src "libresoc.v:169104.13-169104.33" + process $proc$libresoc.v:169104$11076 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:165686.13-165686.33" - process $proc$libresoc.v:165686$10679 + attribute \src "libresoc.v:169111.13-169111.33" + process $proc$libresoc.v:169111$11077 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:165710.3-165711.25" - process $proc$libresoc.v:165710$10596 + attribute \src "libresoc.v:169135.3-169136.25" + process $proc$libresoc.v:169135$10994 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:165712.3-165713.39" - process $proc$libresoc.v:165712$10597 + attribute \src "libresoc.v:169137.3-169138.39" + process $proc$libresoc.v:169137$10995 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:165714.3-165715.37" - process $proc$libresoc.v:165714$10598 + attribute \src "libresoc.v:169139.3-169140.37" + process $proc$libresoc.v:169139$10996 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:165716.3-165717.43" - process $proc$libresoc.v:165716$10599 + attribute \src "libresoc.v:169141.3-169142.43" + process $proc$libresoc.v:169141$10997 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:165718.3-165719.43" - process $proc$libresoc.v:165718$10600 + attribute \src "libresoc.v:169143.3-169144.43" + process $proc$libresoc.v:169143$10998 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:165720.3-165721.43" - process $proc$libresoc.v:165720$10601 + attribute \src "libresoc.v:169145.3-169146.43" + process $proc$libresoc.v:169145$10999 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:165722.3-165761.6" - process $proc$libresoc.v:165722$10602 + attribute \src "libresoc.v:169147.3-169186.6" + process $proc$libresoc.v:169147$11000 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$10603 $6\src12__data_o$next[3:0]$10609 - attribute \src "libresoc.v:165723.5-165723.29" + assign $0\src12__data_o$next[3:0]$11001 $6\src12__data_o$next[3:0]$11007 + attribute \src "libresoc.v:169148.5-169148.29" switch \initial - attribute \src "libresoc.v:165723.9-165723.17" + attribute \src "libresoc.v:169148.9-169148.17" case 1'1 case end @@ -342168,66 +350098,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$10604 $5\src12__data_o$next[3:0]$10608 + assign $1\src12__data_o$next[3:0]$11002 $5\src12__data_o$next[3:0]$11006 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$10605 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11003 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$10605 4'0000 + assign $2\src12__data_o$next[3:0]$11003 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$10606 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11004 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$10606 $2\src12__data_o$next[3:0]$10605 + assign $3\src12__data_o$next[3:0]$11004 $2\src12__data_o$next[3:0]$11003 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$10607 \w2__data_i + assign $4\src12__data_o$next[3:0]$11005 \w2__data_i case - assign $4\src12__data_o$next[3:0]$10607 $3\src12__data_o$next[3:0]$10606 + assign $4\src12__data_o$next[3:0]$11005 $3\src12__data_o$next[3:0]$11004 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$10608 \reg + assign $5\src12__data_o$next[3:0]$11006 \reg case - assign $5\src12__data_o$next[3:0]$10608 $4\src12__data_o$next[3:0]$10607 + assign $5\src12__data_o$next[3:0]$11006 $4\src12__data_o$next[3:0]$11005 end case - assign $1\src12__data_o$next[3:0]$10604 4'0000 + assign $1\src12__data_o$next[3:0]$11002 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$10609 4'0000 + assign $6\src12__data_o$next[3:0]$11007 4'0000 case - assign $6\src12__data_o$next[3:0]$10609 $1\src12__data_o$next[3:0]$10604 + assign $6\src12__data_o$next[3:0]$11007 $1\src12__data_o$next[3:0]$11002 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$10603 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11001 end - attribute \src "libresoc.v:165762.3-165791.6" - process $proc$libresoc.v:165762$10610 + attribute \src "libresoc.v:169187.3-169216.6" + process $proc$libresoc.v:169187$11008 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:165763.5-165763.29" + attribute \src "libresoc.v:169188.5-169188.29" switch \initial - attribute \src "libresoc.v:165763.9-165763.17" + attribute \src "libresoc.v:169188.9-169188.17" case 1'1 case end @@ -342273,17 +350203,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:165792.3-165818.6" - process $proc$libresoc.v:165792$10611 + attribute \src "libresoc.v:169217.3-169243.6" + process $proc$libresoc.v:169217$11009 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10612 $4\reg$next[3:0]$10616 - attribute \src "libresoc.v:165793.5-165793.29" + assign $0\reg$next[3:0]$11010 $4\reg$next[3:0]$11014 + attribute \src "libresoc.v:169218.5-169218.29" switch \initial - attribute \src "libresoc.v:165793.9-165793.17" + attribute \src "libresoc.v:169218.9-169218.17" case 1'1 case end @@ -342292,49 +350222,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10613 \dest12__data_i + assign $1\reg$next[3:0]$11011 \dest12__data_i case - assign $1\reg$next[3:0]$10613 \reg + assign $1\reg$next[3:0]$11011 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10614 \dest22__data_i + assign $2\reg$next[3:0]$11012 \dest22__data_i case - assign $2\reg$next[3:0]$10614 $1\reg$next[3:0]$10613 + assign $2\reg$next[3:0]$11012 $1\reg$next[3:0]$11011 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10615 \w2__data_i + assign $3\reg$next[3:0]$11013 \w2__data_i case - assign $3\reg$next[3:0]$10615 $2\reg$next[3:0]$10614 + assign $3\reg$next[3:0]$11013 $2\reg$next[3:0]$11012 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10616 4'0000 + assign $4\reg$next[3:0]$11014 4'0000 case - assign $4\reg$next[3:0]$10616 $3\reg$next[3:0]$10615 + assign $4\reg$next[3:0]$11014 $3\reg$next[3:0]$11013 end sync always - update \reg$next $0\reg$next[3:0]$10612 + update \reg$next $0\reg$next[3:0]$11010 end - attribute \src "libresoc.v:165819.3-165858.6" - process $proc$libresoc.v:165819$10617 + attribute \src "libresoc.v:169244.3-169283.6" + process $proc$libresoc.v:169244$11015 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$10618 $6\src22__data_o$next[3:0]$10624 - attribute \src "libresoc.v:165820.5-165820.29" + assign $0\src22__data_o$next[3:0]$11016 $6\src22__data_o$next[3:0]$11022 + attribute \src "libresoc.v:169245.5-169245.29" switch \initial - attribute \src "libresoc.v:165820.9-165820.17" + attribute \src "libresoc.v:169245.9-169245.17" case 1'1 case end @@ -342346,66 +350276,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$10619 $5\src22__data_o$next[3:0]$10623 + assign $1\src22__data_o$next[3:0]$11017 $5\src22__data_o$next[3:0]$11021 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$10620 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11018 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$10620 4'0000 + assign $2\src22__data_o$next[3:0]$11018 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$10621 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11019 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$10621 $2\src22__data_o$next[3:0]$10620 + assign $3\src22__data_o$next[3:0]$11019 $2\src22__data_o$next[3:0]$11018 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$10622 \w2__data_i + assign $4\src22__data_o$next[3:0]$11020 \w2__data_i case - assign $4\src22__data_o$next[3:0]$10622 $3\src22__data_o$next[3:0]$10621 + assign $4\src22__data_o$next[3:0]$11020 $3\src22__data_o$next[3:0]$11019 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$10623 \reg + assign $5\src22__data_o$next[3:0]$11021 \reg case - assign $5\src22__data_o$next[3:0]$10623 $4\src22__data_o$next[3:0]$10622 + assign $5\src22__data_o$next[3:0]$11021 $4\src22__data_o$next[3:0]$11020 end case - assign $1\src22__data_o$next[3:0]$10619 4'0000 + assign $1\src22__data_o$next[3:0]$11017 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$10624 4'0000 + assign $6\src22__data_o$next[3:0]$11022 4'0000 case - assign $6\src22__data_o$next[3:0]$10624 $1\src22__data_o$next[3:0]$10619 + assign $6\src22__data_o$next[3:0]$11022 $1\src22__data_o$next[3:0]$11017 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$10618 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11016 end - attribute \src "libresoc.v:165859.3-165888.6" - process $proc$libresoc.v:165859$10625 + attribute \src "libresoc.v:169284.3-169313.6" + process $proc$libresoc.v:169284$11023 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10626 $1\wr_detect$4[0:0]$10627 - attribute \src "libresoc.v:165860.5-165860.29" + assign $0\wr_detect$4[0:0]$11024 $1\wr_detect$4[0:0]$11025 + attribute \src "libresoc.v:169285.5-169285.29" switch \initial - attribute \src "libresoc.v:165860.9-165860.17" + attribute \src "libresoc.v:169285.9-169285.17" case 1'1 case end @@ -342417,49 +350347,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10627 $4\wr_detect$4[0:0]$10630 + assign $1\wr_detect$4[0:0]$11025 $4\wr_detect$4[0:0]$11028 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10628 1'1 + assign $2\wr_detect$4[0:0]$11026 1'1 case - assign $2\wr_detect$4[0:0]$10628 1'0 + assign $2\wr_detect$4[0:0]$11026 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10629 1'1 + assign $3\wr_detect$4[0:0]$11027 1'1 case - assign $3\wr_detect$4[0:0]$10629 $2\wr_detect$4[0:0]$10628 + assign $3\wr_detect$4[0:0]$11027 $2\wr_detect$4[0:0]$11026 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10630 1'1 + assign $4\wr_detect$4[0:0]$11028 1'1 case - assign $4\wr_detect$4[0:0]$10630 $3\wr_detect$4[0:0]$10629 + assign $4\wr_detect$4[0:0]$11028 $3\wr_detect$4[0:0]$11027 end case - assign $1\wr_detect$4[0:0]$10627 1'0 + assign $1\wr_detect$4[0:0]$11025 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10626 + update \wr_detect$4 $0\wr_detect$4[0:0]$11024 end - attribute \src "libresoc.v:165889.3-165928.6" - process $proc$libresoc.v:165889$10631 + attribute \src "libresoc.v:169314.3-169353.6" + process $proc$libresoc.v:169314$11029 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$10632 $6\src32__data_o$next[3:0]$10638 - attribute \src "libresoc.v:165890.5-165890.29" + assign $0\src32__data_o$next[3:0]$11030 $6\src32__data_o$next[3:0]$11036 + attribute \src "libresoc.v:169315.5-169315.29" switch \initial - attribute \src "libresoc.v:165890.9-165890.17" + attribute \src "libresoc.v:169315.9-169315.17" case 1'1 case end @@ -342471,66 +350401,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$10633 $5\src32__data_o$next[3:0]$10637 + assign $1\src32__data_o$next[3:0]$11031 $5\src32__data_o$next[3:0]$11035 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$10634 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11032 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$10634 4'0000 + assign $2\src32__data_o$next[3:0]$11032 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$10635 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11033 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$10635 $2\src32__data_o$next[3:0]$10634 + assign $3\src32__data_o$next[3:0]$11033 $2\src32__data_o$next[3:0]$11032 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$10636 \w2__data_i + assign $4\src32__data_o$next[3:0]$11034 \w2__data_i case - assign $4\src32__data_o$next[3:0]$10636 $3\src32__data_o$next[3:0]$10635 + assign $4\src32__data_o$next[3:0]$11034 $3\src32__data_o$next[3:0]$11033 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$10637 \reg + assign $5\src32__data_o$next[3:0]$11035 \reg case - assign $5\src32__data_o$next[3:0]$10637 $4\src32__data_o$next[3:0]$10636 + assign $5\src32__data_o$next[3:0]$11035 $4\src32__data_o$next[3:0]$11034 end case - assign $1\src32__data_o$next[3:0]$10633 4'0000 + assign $1\src32__data_o$next[3:0]$11031 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$10638 4'0000 + assign $6\src32__data_o$next[3:0]$11036 4'0000 case - assign $6\src32__data_o$next[3:0]$10638 $1\src32__data_o$next[3:0]$10633 + assign $6\src32__data_o$next[3:0]$11036 $1\src32__data_o$next[3:0]$11031 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$10632 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11030 end - attribute \src "libresoc.v:165929.3-165958.6" - process $proc$libresoc.v:165929$10639 + attribute \src "libresoc.v:169354.3-169383.6" + process $proc$libresoc.v:169354$11037 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10640 $1\wr_detect$7[0:0]$10641 - attribute \src "libresoc.v:165930.5-165930.29" + assign $0\wr_detect$7[0:0]$11038 $1\wr_detect$7[0:0]$11039 + attribute \src "libresoc.v:169355.5-169355.29" switch \initial - attribute \src "libresoc.v:165930.9-165930.17" + attribute \src "libresoc.v:169355.9-169355.17" case 1'1 case end @@ -342542,49 +350472,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10641 $4\wr_detect$7[0:0]$10644 + assign $1\wr_detect$7[0:0]$11039 $4\wr_detect$7[0:0]$11042 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10642 1'1 + assign $2\wr_detect$7[0:0]$11040 1'1 case - assign $2\wr_detect$7[0:0]$10642 1'0 + assign $2\wr_detect$7[0:0]$11040 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10643 1'1 + assign $3\wr_detect$7[0:0]$11041 1'1 case - assign $3\wr_detect$7[0:0]$10643 $2\wr_detect$7[0:0]$10642 + assign $3\wr_detect$7[0:0]$11041 $2\wr_detect$7[0:0]$11040 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10644 1'1 + assign $4\wr_detect$7[0:0]$11042 1'1 case - assign $4\wr_detect$7[0:0]$10644 $3\wr_detect$7[0:0]$10643 + assign $4\wr_detect$7[0:0]$11042 $3\wr_detect$7[0:0]$11041 end case - assign $1\wr_detect$7[0:0]$10641 1'0 + assign $1\wr_detect$7[0:0]$11039 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10640 + update \wr_detect$7 $0\wr_detect$7[0:0]$11038 end - attribute \src "libresoc.v:165959.3-165998.6" - process $proc$libresoc.v:165959$10645 + attribute \src "libresoc.v:169384.3-169423.6" + process $proc$libresoc.v:169384$11043 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$10646 $6\r2__data_o$next[3:0]$10652 - attribute \src "libresoc.v:165960.5-165960.29" + assign $0\r2__data_o$next[3:0]$11044 $6\r2__data_o$next[3:0]$11050 + attribute \src "libresoc.v:169385.5-169385.29" switch \initial - attribute \src "libresoc.v:165960.9-165960.17" + attribute \src "libresoc.v:169385.9-169385.17" case 1'1 case end @@ -342596,66 +350526,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$10647 $5\r2__data_o$next[3:0]$10651 + assign $1\r2__data_o$next[3:0]$11045 $5\r2__data_o$next[3:0]$11049 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$10648 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11046 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$10648 4'0000 + assign $2\r2__data_o$next[3:0]$11046 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$10649 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11047 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$10649 $2\r2__data_o$next[3:0]$10648 + assign $3\r2__data_o$next[3:0]$11047 $2\r2__data_o$next[3:0]$11046 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$10650 \w2__data_i + assign $4\r2__data_o$next[3:0]$11048 \w2__data_i case - assign $4\r2__data_o$next[3:0]$10650 $3\r2__data_o$next[3:0]$10649 + assign $4\r2__data_o$next[3:0]$11048 $3\r2__data_o$next[3:0]$11047 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$10651 \reg + assign $5\r2__data_o$next[3:0]$11049 \reg case - assign $5\r2__data_o$next[3:0]$10651 $4\r2__data_o$next[3:0]$10650 + assign $5\r2__data_o$next[3:0]$11049 $4\r2__data_o$next[3:0]$11048 end case - assign $1\r2__data_o$next[3:0]$10647 4'0000 + assign $1\r2__data_o$next[3:0]$11045 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$10652 4'0000 + assign $6\r2__data_o$next[3:0]$11050 4'0000 case - assign $6\r2__data_o$next[3:0]$10652 $1\r2__data_o$next[3:0]$10647 + assign $6\r2__data_o$next[3:0]$11050 $1\r2__data_o$next[3:0]$11045 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$10646 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11044 end - attribute \src "libresoc.v:165999.3-166028.6" - process $proc$libresoc.v:165999$10653 + attribute \src "libresoc.v:169424.3-169453.6" + process $proc$libresoc.v:169424$11051 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10654 $1\wr_detect$10[0:0]$10655 - attribute \src "libresoc.v:166000.5-166000.29" + assign $0\wr_detect$10[0:0]$11052 $1\wr_detect$10[0:0]$11053 + attribute \src "libresoc.v:169425.5-169425.29" switch \initial - attribute \src "libresoc.v:166000.9-166000.17" + attribute \src "libresoc.v:169425.9-169425.17" case 1'1 case end @@ -342667,49 +350597,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10655 $4\wr_detect$10[0:0]$10658 + assign $1\wr_detect$10[0:0]$11053 $4\wr_detect$10[0:0]$11056 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10656 1'1 + assign $2\wr_detect$10[0:0]$11054 1'1 case - assign $2\wr_detect$10[0:0]$10656 1'0 + assign $2\wr_detect$10[0:0]$11054 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10657 1'1 + assign $3\wr_detect$10[0:0]$11055 1'1 case - assign $3\wr_detect$10[0:0]$10657 $2\wr_detect$10[0:0]$10656 + assign $3\wr_detect$10[0:0]$11055 $2\wr_detect$10[0:0]$11054 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10658 1'1 + assign $4\wr_detect$10[0:0]$11056 1'1 case - assign $4\wr_detect$10[0:0]$10658 $3\wr_detect$10[0:0]$10657 + assign $4\wr_detect$10[0:0]$11056 $3\wr_detect$10[0:0]$11055 end case - assign $1\wr_detect$10[0:0]$10655 1'0 + assign $1\wr_detect$10[0:0]$11053 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10654 + update \wr_detect$10 $0\wr_detect$10[0:0]$11052 end - attribute \src "libresoc.v:166029.3-166068.6" - process $proc$libresoc.v:166029$10659 + attribute \src "libresoc.v:169454.3-169493.6" + process $proc$libresoc.v:169454$11057 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$10660 $6\r22__data_o$next[3:0]$10666 - attribute \src "libresoc.v:166030.5-166030.29" + assign $0\r22__data_o$next[3:0]$11058 $6\r22__data_o$next[3:0]$11064 + attribute \src "libresoc.v:169455.5-169455.29" switch \initial - attribute \src "libresoc.v:166030.9-166030.17" + attribute \src "libresoc.v:169455.9-169455.17" case 1'1 case end @@ -342721,66 +350651,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$10661 $5\r22__data_o$next[3:0]$10665 + assign $1\r22__data_o$next[3:0]$11059 $5\r22__data_o$next[3:0]$11063 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$10662 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11060 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$10662 4'0000 + assign $2\r22__data_o$next[3:0]$11060 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$10663 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11061 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$10663 $2\r22__data_o$next[3:0]$10662 + assign $3\r22__data_o$next[3:0]$11061 $2\r22__data_o$next[3:0]$11060 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$10664 \w2__data_i + assign $4\r22__data_o$next[3:0]$11062 \w2__data_i case - assign $4\r22__data_o$next[3:0]$10664 $3\r22__data_o$next[3:0]$10663 + assign $4\r22__data_o$next[3:0]$11062 $3\r22__data_o$next[3:0]$11061 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$10665 \reg + assign $5\r22__data_o$next[3:0]$11063 \reg case - assign $5\r22__data_o$next[3:0]$10665 $4\r22__data_o$next[3:0]$10664 + assign $5\r22__data_o$next[3:0]$11063 $4\r22__data_o$next[3:0]$11062 end case - assign $1\r22__data_o$next[3:0]$10661 4'0000 + assign $1\r22__data_o$next[3:0]$11059 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$10666 4'0000 + assign $6\r22__data_o$next[3:0]$11064 4'0000 case - assign $6\r22__data_o$next[3:0]$10666 $1\r22__data_o$next[3:0]$10661 + assign $6\r22__data_o$next[3:0]$11064 $1\r22__data_o$next[3:0]$11059 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$10660 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11058 end - attribute \src "libresoc.v:166069.3-166098.6" - process $proc$libresoc.v:166069$10667 + attribute \src "libresoc.v:169494.3-169523.6" + process $proc$libresoc.v:169494$11065 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10668 $1\wr_detect$13[0:0]$10669 - attribute \src "libresoc.v:166070.5-166070.29" + assign $0\wr_detect$13[0:0]$11066 $1\wr_detect$13[0:0]$11067 + attribute \src "libresoc.v:169495.5-169495.29" switch \initial - attribute \src "libresoc.v:166070.9-166070.17" + attribute \src "libresoc.v:169495.9-169495.17" case 1'1 case end @@ -342792,205 +350722,205 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10669 $4\wr_detect$13[0:0]$10672 + assign $1\wr_detect$13[0:0]$11067 $4\wr_detect$13[0:0]$11070 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10670 1'1 + assign $2\wr_detect$13[0:0]$11068 1'1 case - assign $2\wr_detect$13[0:0]$10670 1'0 + assign $2\wr_detect$13[0:0]$11068 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10671 1'1 + assign $3\wr_detect$13[0:0]$11069 1'1 case - assign $3\wr_detect$13[0:0]$10671 $2\wr_detect$13[0:0]$10670 + assign $3\wr_detect$13[0:0]$11069 $2\wr_detect$13[0:0]$11068 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10672 1'1 + assign $4\wr_detect$13[0:0]$11070 1'1 case - assign $4\wr_detect$13[0:0]$10672 $3\wr_detect$13[0:0]$10671 + assign $4\wr_detect$13[0:0]$11070 $3\wr_detect$13[0:0]$11069 end case - assign $1\wr_detect$13[0:0]$10669 1'0 + assign $1\wr_detect$13[0:0]$11067 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10668 + update \wr_detect$13 $0\wr_detect$13[0:0]$11066 end - connect \$9 $not$libresoc.v:165705$10591_Y - connect \$12 $not$libresoc.v:165706$10592_Y - connect \$1 $not$libresoc.v:165707$10593_Y - connect \$3 $not$libresoc.v:165708$10594_Y - connect \$6 $not$libresoc.v:165709$10595_Y + connect \$9 $not$libresoc.v:169130$10989_Y + connect \$12 $not$libresoc.v:169131$10990_Y + connect \$1 $not$libresoc.v:169132$10991_Y + connect \$3 $not$libresoc.v:169133$10992_Y + connect \$6 $not$libresoc.v:169134$10993_Y end -attribute \src "libresoc.v:166103.1-166548.10" +attribute \src "libresoc.v:169528.1-169973.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" -module \reg_2$131 - attribute \src "libresoc.v:166104.7-166104.20" +module \reg_2$134 + attribute \src "libresoc.v:169529.7-169529.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $0\r2__data_o$next[1:0]$10732 - attribute \src "libresoc.v:166179.3-166180.37" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $0\r2__data_o$next[1:0]$11130 + attribute \src "libresoc.v:169604.3-169605.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $0\reg$next[1:0]$10748 - attribute \src "libresoc.v:166177.3-166178.25" + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $0\reg$next[1:0]$11146 + attribute \src "libresoc.v:169602.3-169603.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $0\src12__data_o$next[1:0]$10690 - attribute \src "libresoc.v:166185.3-166186.43" + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $0\src12__data_o$next[1:0]$11088 + attribute \src "libresoc.v:169610.3-169611.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $0\src22__data_o$next[1:0]$10700 - attribute \src "libresoc.v:166183.3-166184.43" + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $0\src22__data_o$next[1:0]$11098 + attribute \src "libresoc.v:169608.3-169609.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $0\src32__data_o$next[1:0]$10716 - attribute \src "libresoc.v:166181.3-166182.43" + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $0\src32__data_o$next[1:0]$11114 + attribute \src "libresoc.v:169606.3-169607.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:166479.3-166514.6" - wire $0\wr_detect$10[0:0]$10741 - attribute \src "libresoc.v:166315.3-166350.6" - wire $0\wr_detect$4[0:0]$10709 - attribute \src "libresoc.v:166397.3-166432.6" - wire $0\wr_detect$7[0:0]$10725 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169904.3-169939.6" + wire $0\wr_detect$10[0:0]$11139 + attribute \src "libresoc.v:169740.3-169775.6" + wire $0\wr_detect$4[0:0]$11107 + attribute \src "libresoc.v:169822.3-169857.6" + wire $0\wr_detect$7[0:0]$11123 + attribute \src "libresoc.v:169658.3-169693.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $1\r2__data_o$next[1:0]$10733 - attribute \src "libresoc.v:166131.13-166131.30" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $1\r2__data_o$next[1:0]$11131 + attribute \src "libresoc.v:169556.13-169556.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $1\reg$next[1:0]$10749 - attribute \src "libresoc.v:166137.13-166137.25" + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $1\reg$next[1:0]$11147 + attribute \src "libresoc.v:169562.13-169562.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $1\src12__data_o$next[1:0]$10691 - attribute \src "libresoc.v:166142.13-166142.33" + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $1\src12__data_o$next[1:0]$11089 + attribute \src "libresoc.v:169567.13-169567.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $1\src22__data_o$next[1:0]$10701 - attribute \src "libresoc.v:166149.13-166149.33" + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $1\src22__data_o$next[1:0]$11099 + attribute \src "libresoc.v:169574.13-169574.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $1\src32__data_o$next[1:0]$10717 - attribute \src "libresoc.v:166156.13-166156.33" + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $1\src32__data_o$next[1:0]$11115 + attribute \src "libresoc.v:169581.13-169581.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:166479.3-166514.6" - wire $1\wr_detect$10[0:0]$10742 - attribute \src "libresoc.v:166315.3-166350.6" - wire $1\wr_detect$4[0:0]$10710 - attribute \src "libresoc.v:166397.3-166432.6" - wire $1\wr_detect$7[0:0]$10726 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169904.3-169939.6" + wire $1\wr_detect$10[0:0]$11140 + attribute \src "libresoc.v:169740.3-169775.6" + wire $1\wr_detect$4[0:0]$11108 + attribute \src "libresoc.v:169822.3-169857.6" + wire $1\wr_detect$7[0:0]$11124 + attribute \src "libresoc.v:169658.3-169693.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $2\r2__data_o$next[1:0]$10734 - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $2\reg$next[1:0]$10750 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $2\src12__data_o$next[1:0]$10692 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $2\src22__data_o$next[1:0]$10702 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $2\src32__data_o$next[1:0]$10718 - attribute \src "libresoc.v:166479.3-166514.6" - wire $2\wr_detect$10[0:0]$10743 - attribute \src "libresoc.v:166315.3-166350.6" - wire $2\wr_detect$4[0:0]$10711 - attribute \src "libresoc.v:166397.3-166432.6" - wire $2\wr_detect$7[0:0]$10727 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $2\r2__data_o$next[1:0]$11132 + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $2\reg$next[1:0]$11148 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $2\src12__data_o$next[1:0]$11090 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $2\src22__data_o$next[1:0]$11100 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $2\src32__data_o$next[1:0]$11116 + attribute \src "libresoc.v:169904.3-169939.6" + wire $2\wr_detect$10[0:0]$11141 + attribute \src "libresoc.v:169740.3-169775.6" + wire $2\wr_detect$4[0:0]$11109 + attribute \src "libresoc.v:169822.3-169857.6" + wire $2\wr_detect$7[0:0]$11125 + attribute \src "libresoc.v:169658.3-169693.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $3\r2__data_o$next[1:0]$10735 - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $3\reg$next[1:0]$10751 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $3\src12__data_o$next[1:0]$10693 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $3\src22__data_o$next[1:0]$10703 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $3\src32__data_o$next[1:0]$10719 - attribute \src "libresoc.v:166479.3-166514.6" - wire $3\wr_detect$10[0:0]$10744 - attribute \src "libresoc.v:166315.3-166350.6" - wire $3\wr_detect$4[0:0]$10712 - attribute \src "libresoc.v:166397.3-166432.6" - wire $3\wr_detect$7[0:0]$10728 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $3\r2__data_o$next[1:0]$11133 + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $3\reg$next[1:0]$11149 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $3\src12__data_o$next[1:0]$11091 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $3\src22__data_o$next[1:0]$11101 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $3\src32__data_o$next[1:0]$11117 + attribute \src "libresoc.v:169904.3-169939.6" + wire $3\wr_detect$10[0:0]$11142 + attribute \src "libresoc.v:169740.3-169775.6" + wire $3\wr_detect$4[0:0]$11110 + attribute \src "libresoc.v:169822.3-169857.6" + wire $3\wr_detect$7[0:0]$11126 + attribute \src "libresoc.v:169658.3-169693.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $4\r2__data_o$next[1:0]$10736 - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $4\reg$next[1:0]$10752 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $4\src12__data_o$next[1:0]$10694 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $4\src22__data_o$next[1:0]$10704 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $4\src32__data_o$next[1:0]$10720 - attribute \src "libresoc.v:166479.3-166514.6" - wire $4\wr_detect$10[0:0]$10745 - attribute \src "libresoc.v:166315.3-166350.6" - wire $4\wr_detect$4[0:0]$10713 - attribute \src "libresoc.v:166397.3-166432.6" - wire $4\wr_detect$7[0:0]$10729 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $4\r2__data_o$next[1:0]$11134 + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $4\reg$next[1:0]$11150 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $4\src12__data_o$next[1:0]$11092 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $4\src22__data_o$next[1:0]$11102 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $4\src32__data_o$next[1:0]$11118 + attribute \src "libresoc.v:169904.3-169939.6" + wire $4\wr_detect$10[0:0]$11143 + attribute \src "libresoc.v:169740.3-169775.6" + wire $4\wr_detect$4[0:0]$11111 + attribute \src "libresoc.v:169822.3-169857.6" + wire $4\wr_detect$7[0:0]$11127 + attribute \src "libresoc.v:169658.3-169693.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $5\r2__data_o$next[1:0]$10737 - attribute \src "libresoc.v:166515.3-166547.6" - wire width 2 $5\reg$next[1:0]$10753 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $5\src12__data_o$next[1:0]$10695 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $5\src22__data_o$next[1:0]$10705 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $5\src32__data_o$next[1:0]$10721 - attribute \src "libresoc.v:166479.3-166514.6" - wire $5\wr_detect$10[0:0]$10746 - attribute \src "libresoc.v:166315.3-166350.6" - wire $5\wr_detect$4[0:0]$10714 - attribute \src "libresoc.v:166397.3-166432.6" - wire $5\wr_detect$7[0:0]$10730 - attribute \src "libresoc.v:166233.3-166268.6" + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $5\r2__data_o$next[1:0]$11135 + attribute \src "libresoc.v:169940.3-169972.6" + wire width 2 $5\reg$next[1:0]$11151 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $5\src12__data_o$next[1:0]$11093 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $5\src22__data_o$next[1:0]$11103 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $5\src32__data_o$next[1:0]$11119 + attribute \src "libresoc.v:169904.3-169939.6" + wire $5\wr_detect$10[0:0]$11144 + attribute \src "libresoc.v:169740.3-169775.6" + wire $5\wr_detect$4[0:0]$11112 + attribute \src "libresoc.v:169822.3-169857.6" + wire $5\wr_detect$7[0:0]$11128 + attribute \src "libresoc.v:169658.3-169693.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $6\r2__data_o$next[1:0]$10738 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $6\src12__data_o$next[1:0]$10696 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $6\src22__data_o$next[1:0]$10706 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $6\src32__data_o$next[1:0]$10722 - attribute \src "libresoc.v:166433.3-166478.6" - wire width 2 $7\r2__data_o$next[1:0]$10739 - attribute \src "libresoc.v:166187.3-166232.6" - wire width 2 $7\src12__data_o$next[1:0]$10697 - attribute \src "libresoc.v:166269.3-166314.6" - wire width 2 $7\src22__data_o$next[1:0]$10707 - attribute \src "libresoc.v:166351.3-166396.6" - wire width 2 $7\src32__data_o$next[1:0]$10723 - attribute \src "libresoc.v:166173.17-166173.104" - wire $not$libresoc.v:166173$10680_Y - attribute \src "libresoc.v:166174.17-166174.100" - wire $not$libresoc.v:166174$10681_Y - attribute \src "libresoc.v:166175.17-166175.103" - wire $not$libresoc.v:166175$10682_Y - attribute \src "libresoc.v:166176.17-166176.103" - wire $not$libresoc.v:166176$10683_Y + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $6\r2__data_o$next[1:0]$11136 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $6\src12__data_o$next[1:0]$11094 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $6\src22__data_o$next[1:0]$11104 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $6\src32__data_o$next[1:0]$11120 + attribute \src "libresoc.v:169858.3-169903.6" + wire width 2 $7\r2__data_o$next[1:0]$11137 + attribute \src "libresoc.v:169612.3-169657.6" + wire width 2 $7\src12__data_o$next[1:0]$11095 + attribute \src "libresoc.v:169694.3-169739.6" + wire width 2 $7\src22__data_o$next[1:0]$11105 + attribute \src "libresoc.v:169776.3-169821.6" + wire width 2 $7\src32__data_o$next[1:0]$11121 + attribute \src "libresoc.v:169598.17-169598.104" + wire $not$libresoc.v:169598$11078_Y + attribute \src "libresoc.v:169599.17-169599.100" + wire $not$libresoc.v:169599$11079_Y + attribute \src "libresoc.v:169600.17-169600.103" + wire $not$libresoc.v:169600$11080_Y + attribute \src "libresoc.v:169601.17-169601.103" + wire $not$libresoc.v:169601$11081_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -342999,9 +350929,9 @@ module \reg_2$131 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 input 9 \dest12__data_i @@ -343015,7 +350945,7 @@ module \reg_2$131 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 12 \dest32__wen - attribute \src "libresoc.v:166104.7-166104.15" + attribute \src "libresoc.v:169529.7-169529.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 output 14 \r2__data_o @@ -343058,129 +350988,129 @@ module \reg_2$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166173$10680 + cell $not $not$libresoc.v:169598$11078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:166173$10680_Y + connect \Y $not$libresoc.v:169598$11078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166174$10681 + cell $not $not$libresoc.v:169599$11079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:166174$10681_Y + connect \Y $not$libresoc.v:169599$11079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166175$10682 + cell $not $not$libresoc.v:169600$11080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:166175$10682_Y + connect \Y $not$libresoc.v:169600$11080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166176$10683 + cell $not $not$libresoc.v:169601$11081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:166176$10683_Y + connect \Y $not$libresoc.v:169601$11081_Y end - attribute \src "libresoc.v:166104.7-166104.20" - process $proc$libresoc.v:166104$10754 + attribute \src "libresoc.v:169529.7-169529.20" + process $proc$libresoc.v:169529$11152 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166131.13-166131.30" - process $proc$libresoc.v:166131$10755 + attribute \src "libresoc.v:169556.13-169556.30" + process $proc$libresoc.v:169556$11153 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:166137.13-166137.25" - process $proc$libresoc.v:166137$10756 + attribute \src "libresoc.v:169562.13-169562.25" + process $proc$libresoc.v:169562$11154 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:166142.13-166142.33" - process $proc$libresoc.v:166142$10757 + attribute \src "libresoc.v:169567.13-169567.33" + process $proc$libresoc.v:169567$11155 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:166149.13-166149.33" - process $proc$libresoc.v:166149$10758 + attribute \src "libresoc.v:169574.13-169574.33" + process $proc$libresoc.v:169574$11156 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:166156.13-166156.33" - process $proc$libresoc.v:166156$10759 + attribute \src "libresoc.v:169581.13-169581.33" + process $proc$libresoc.v:169581$11157 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:166177.3-166178.25" - process $proc$libresoc.v:166177$10684 + attribute \src "libresoc.v:169602.3-169603.25" + process $proc$libresoc.v:169602$11082 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:166179.3-166180.37" - process $proc$libresoc.v:166179$10685 + attribute \src "libresoc.v:169604.3-169605.37" + process $proc$libresoc.v:169604$11083 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:166181.3-166182.43" - process $proc$libresoc.v:166181$10686 + attribute \src "libresoc.v:169606.3-169607.43" + process $proc$libresoc.v:169606$11084 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:166183.3-166184.43" - process $proc$libresoc.v:166183$10687 + attribute \src "libresoc.v:169608.3-169609.43" + process $proc$libresoc.v:169608$11085 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:166185.3-166186.43" - process $proc$libresoc.v:166185$10688 + attribute \src "libresoc.v:169610.3-169611.43" + process $proc$libresoc.v:169610$11086 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:166187.3-166232.6" - process $proc$libresoc.v:166187$10689 + attribute \src "libresoc.v:169612.3-169657.6" + process $proc$libresoc.v:169612$11087 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$10690 $7\src12__data_o$next[1:0]$10697 - attribute \src "libresoc.v:166188.5-166188.29" + assign $0\src12__data_o$next[1:0]$11088 $7\src12__data_o$next[1:0]$11095 + attribute \src "libresoc.v:169613.5-169613.29" switch \initial - attribute \src "libresoc.v:166188.9-166188.17" + attribute \src "libresoc.v:169613.9-169613.17" case 1'1 case end @@ -343193,75 +351123,75 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$10691 $6\src12__data_o$next[1:0]$10696 + assign $1\src12__data_o$next[1:0]$11089 $6\src12__data_o$next[1:0]$11094 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$10692 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11090 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$10692 2'00 + assign $2\src12__data_o$next[1:0]$11090 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$10693 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11091 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$10693 $2\src12__data_o$next[1:0]$10692 + assign $3\src12__data_o$next[1:0]$11091 $2\src12__data_o$next[1:0]$11090 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$10694 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11092 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$10694 $3\src12__data_o$next[1:0]$10693 + assign $4\src12__data_o$next[1:0]$11092 $3\src12__data_o$next[1:0]$11091 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$10695 \w2__data_i + assign $5\src12__data_o$next[1:0]$11093 \w2__data_i case - assign $5\src12__data_o$next[1:0]$10695 $4\src12__data_o$next[1:0]$10694 + assign $5\src12__data_o$next[1:0]$11093 $4\src12__data_o$next[1:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$10696 \reg + assign $6\src12__data_o$next[1:0]$11094 \reg case - assign $6\src12__data_o$next[1:0]$10696 $5\src12__data_o$next[1:0]$10695 + assign $6\src12__data_o$next[1:0]$11094 $5\src12__data_o$next[1:0]$11093 end case - assign $1\src12__data_o$next[1:0]$10691 2'00 + assign $1\src12__data_o$next[1:0]$11089 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$10697 2'00 + assign $7\src12__data_o$next[1:0]$11095 2'00 case - assign $7\src12__data_o$next[1:0]$10697 $1\src12__data_o$next[1:0]$10691 + assign $7\src12__data_o$next[1:0]$11095 $1\src12__data_o$next[1:0]$11089 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$10690 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11088 end - attribute \src "libresoc.v:166233.3-166268.6" - process $proc$libresoc.v:166233$10698 + attribute \src "libresoc.v:169658.3-169693.6" + process $proc$libresoc.v:169658$11096 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:166234.5-166234.29" + attribute \src "libresoc.v:169659.5-169659.29" switch \initial - attribute \src "libresoc.v:166234.9-166234.17" + attribute \src "libresoc.v:169659.9-169659.17" case 1'1 case end @@ -343317,15 +351247,15 @@ module \reg_2$131 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:166269.3-166314.6" - process $proc$libresoc.v:166269$10699 + attribute \src "libresoc.v:169694.3-169739.6" + process $proc$libresoc.v:169694$11097 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$10700 $7\src22__data_o$next[1:0]$10707 - attribute \src "libresoc.v:166270.5-166270.29" + assign $0\src22__data_o$next[1:0]$11098 $7\src22__data_o$next[1:0]$11105 + attribute \src "libresoc.v:169695.5-169695.29" switch \initial - attribute \src "libresoc.v:166270.9-166270.17" + attribute \src "libresoc.v:169695.9-169695.17" case 1'1 case end @@ -343338,75 +351268,75 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$10701 $6\src22__data_o$next[1:0]$10706 + assign $1\src22__data_o$next[1:0]$11099 $6\src22__data_o$next[1:0]$11104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$10702 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11100 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$10702 2'00 + assign $2\src22__data_o$next[1:0]$11100 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$10703 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11101 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$10703 $2\src22__data_o$next[1:0]$10702 + assign $3\src22__data_o$next[1:0]$11101 $2\src22__data_o$next[1:0]$11100 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$10704 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11102 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$10704 $3\src22__data_o$next[1:0]$10703 + assign $4\src22__data_o$next[1:0]$11102 $3\src22__data_o$next[1:0]$11101 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$10705 \w2__data_i + assign $5\src22__data_o$next[1:0]$11103 \w2__data_i case - assign $5\src22__data_o$next[1:0]$10705 $4\src22__data_o$next[1:0]$10704 + assign $5\src22__data_o$next[1:0]$11103 $4\src22__data_o$next[1:0]$11102 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$10706 \reg + assign $6\src22__data_o$next[1:0]$11104 \reg case - assign $6\src22__data_o$next[1:0]$10706 $5\src22__data_o$next[1:0]$10705 + assign $6\src22__data_o$next[1:0]$11104 $5\src22__data_o$next[1:0]$11103 end case - assign $1\src22__data_o$next[1:0]$10701 2'00 + assign $1\src22__data_o$next[1:0]$11099 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$10707 2'00 + assign $7\src22__data_o$next[1:0]$11105 2'00 case - assign $7\src22__data_o$next[1:0]$10707 $1\src22__data_o$next[1:0]$10701 + assign $7\src22__data_o$next[1:0]$11105 $1\src22__data_o$next[1:0]$11099 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$10700 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11098 end - attribute \src "libresoc.v:166315.3-166350.6" - process $proc$libresoc.v:166315$10708 + attribute \src "libresoc.v:169740.3-169775.6" + process $proc$libresoc.v:169740$11106 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10709 $1\wr_detect$4[0:0]$10710 - attribute \src "libresoc.v:166316.5-166316.29" + assign $0\wr_detect$4[0:0]$11107 $1\wr_detect$4[0:0]$11108 + attribute \src "libresoc.v:169741.5-169741.29" switch \initial - attribute \src "libresoc.v:166316.9-166316.17" + attribute \src "libresoc.v:169741.9-169741.17" case 1'1 case end @@ -343419,58 +351349,58 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10710 $5\wr_detect$4[0:0]$10714 + assign $1\wr_detect$4[0:0]$11108 $5\wr_detect$4[0:0]$11112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10711 1'1 + assign $2\wr_detect$4[0:0]$11109 1'1 case - assign $2\wr_detect$4[0:0]$10711 1'0 + assign $2\wr_detect$4[0:0]$11109 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10712 1'1 + assign $3\wr_detect$4[0:0]$11110 1'1 case - assign $3\wr_detect$4[0:0]$10712 $2\wr_detect$4[0:0]$10711 + assign $3\wr_detect$4[0:0]$11110 $2\wr_detect$4[0:0]$11109 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10713 1'1 + assign $4\wr_detect$4[0:0]$11111 1'1 case - assign $4\wr_detect$4[0:0]$10713 $3\wr_detect$4[0:0]$10712 + assign $4\wr_detect$4[0:0]$11111 $3\wr_detect$4[0:0]$11110 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10714 1'1 + assign $5\wr_detect$4[0:0]$11112 1'1 case - assign $5\wr_detect$4[0:0]$10714 $4\wr_detect$4[0:0]$10713 + assign $5\wr_detect$4[0:0]$11112 $4\wr_detect$4[0:0]$11111 end case - assign $1\wr_detect$4[0:0]$10710 1'0 + assign $1\wr_detect$4[0:0]$11108 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10709 + update \wr_detect$4 $0\wr_detect$4[0:0]$11107 end - attribute \src "libresoc.v:166351.3-166396.6" - process $proc$libresoc.v:166351$10715 + attribute \src "libresoc.v:169776.3-169821.6" + process $proc$libresoc.v:169776$11113 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$10716 $7\src32__data_o$next[1:0]$10723 - attribute \src "libresoc.v:166352.5-166352.29" + assign $0\src32__data_o$next[1:0]$11114 $7\src32__data_o$next[1:0]$11121 + attribute \src "libresoc.v:169777.5-169777.29" switch \initial - attribute \src "libresoc.v:166352.9-166352.17" + attribute \src "libresoc.v:169777.9-169777.17" case 1'1 case end @@ -343483,75 +351413,75 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$10717 $6\src32__data_o$next[1:0]$10722 + assign $1\src32__data_o$next[1:0]$11115 $6\src32__data_o$next[1:0]$11120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$10718 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11116 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$10718 2'00 + assign $2\src32__data_o$next[1:0]$11116 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$10719 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11117 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$10719 $2\src32__data_o$next[1:0]$10718 + assign $3\src32__data_o$next[1:0]$11117 $2\src32__data_o$next[1:0]$11116 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$10720 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11118 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$10720 $3\src32__data_o$next[1:0]$10719 + assign $4\src32__data_o$next[1:0]$11118 $3\src32__data_o$next[1:0]$11117 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$10721 \w2__data_i + assign $5\src32__data_o$next[1:0]$11119 \w2__data_i case - assign $5\src32__data_o$next[1:0]$10721 $4\src32__data_o$next[1:0]$10720 + assign $5\src32__data_o$next[1:0]$11119 $4\src32__data_o$next[1:0]$11118 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$10722 \reg + assign $6\src32__data_o$next[1:0]$11120 \reg case - assign $6\src32__data_o$next[1:0]$10722 $5\src32__data_o$next[1:0]$10721 + assign $6\src32__data_o$next[1:0]$11120 $5\src32__data_o$next[1:0]$11119 end case - assign $1\src32__data_o$next[1:0]$10717 2'00 + assign $1\src32__data_o$next[1:0]$11115 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$10723 2'00 + assign $7\src32__data_o$next[1:0]$11121 2'00 case - assign $7\src32__data_o$next[1:0]$10723 $1\src32__data_o$next[1:0]$10717 + assign $7\src32__data_o$next[1:0]$11121 $1\src32__data_o$next[1:0]$11115 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$10716 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11114 end - attribute \src "libresoc.v:166397.3-166432.6" - process $proc$libresoc.v:166397$10724 + attribute \src "libresoc.v:169822.3-169857.6" + process $proc$libresoc.v:169822$11122 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10725 $1\wr_detect$7[0:0]$10726 - attribute \src "libresoc.v:166398.5-166398.29" + assign $0\wr_detect$7[0:0]$11123 $1\wr_detect$7[0:0]$11124 + attribute \src "libresoc.v:169823.5-169823.29" switch \initial - attribute \src "libresoc.v:166398.9-166398.17" + attribute \src "libresoc.v:169823.9-169823.17" case 1'1 case end @@ -343564,58 +351494,58 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10726 $5\wr_detect$7[0:0]$10730 + assign $1\wr_detect$7[0:0]$11124 $5\wr_detect$7[0:0]$11128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10727 1'1 + assign $2\wr_detect$7[0:0]$11125 1'1 case - assign $2\wr_detect$7[0:0]$10727 1'0 + assign $2\wr_detect$7[0:0]$11125 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10728 1'1 + assign $3\wr_detect$7[0:0]$11126 1'1 case - assign $3\wr_detect$7[0:0]$10728 $2\wr_detect$7[0:0]$10727 + assign $3\wr_detect$7[0:0]$11126 $2\wr_detect$7[0:0]$11125 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10729 1'1 + assign $4\wr_detect$7[0:0]$11127 1'1 case - assign $4\wr_detect$7[0:0]$10729 $3\wr_detect$7[0:0]$10728 + assign $4\wr_detect$7[0:0]$11127 $3\wr_detect$7[0:0]$11126 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10730 1'1 + assign $5\wr_detect$7[0:0]$11128 1'1 case - assign $5\wr_detect$7[0:0]$10730 $4\wr_detect$7[0:0]$10729 + assign $5\wr_detect$7[0:0]$11128 $4\wr_detect$7[0:0]$11127 end case - assign $1\wr_detect$7[0:0]$10726 1'0 + assign $1\wr_detect$7[0:0]$11124 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10725 + update \wr_detect$7 $0\wr_detect$7[0:0]$11123 end - attribute \src "libresoc.v:166433.3-166478.6" - process $proc$libresoc.v:166433$10731 + attribute \src "libresoc.v:169858.3-169903.6" + process $proc$libresoc.v:169858$11129 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$10732 $7\r2__data_o$next[1:0]$10739 - attribute \src "libresoc.v:166434.5-166434.29" + assign $0\r2__data_o$next[1:0]$11130 $7\r2__data_o$next[1:0]$11137 + attribute \src "libresoc.v:169859.5-169859.29" switch \initial - attribute \src "libresoc.v:166434.9-166434.17" + attribute \src "libresoc.v:169859.9-169859.17" case 1'1 case end @@ -343628,75 +351558,75 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$10733 $6\r2__data_o$next[1:0]$10738 + assign $1\r2__data_o$next[1:0]$11131 $6\r2__data_o$next[1:0]$11136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$10734 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11132 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$10734 2'00 + assign $2\r2__data_o$next[1:0]$11132 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$10735 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11133 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$10735 $2\r2__data_o$next[1:0]$10734 + assign $3\r2__data_o$next[1:0]$11133 $2\r2__data_o$next[1:0]$11132 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$10736 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11134 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$10736 $3\r2__data_o$next[1:0]$10735 + assign $4\r2__data_o$next[1:0]$11134 $3\r2__data_o$next[1:0]$11133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$10737 \w2__data_i + assign $5\r2__data_o$next[1:0]$11135 \w2__data_i case - assign $5\r2__data_o$next[1:0]$10737 $4\r2__data_o$next[1:0]$10736 + assign $5\r2__data_o$next[1:0]$11135 $4\r2__data_o$next[1:0]$11134 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$10738 \reg + assign $6\r2__data_o$next[1:0]$11136 \reg case - assign $6\r2__data_o$next[1:0]$10738 $5\r2__data_o$next[1:0]$10737 + assign $6\r2__data_o$next[1:0]$11136 $5\r2__data_o$next[1:0]$11135 end case - assign $1\r2__data_o$next[1:0]$10733 2'00 + assign $1\r2__data_o$next[1:0]$11131 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$10739 2'00 + assign $7\r2__data_o$next[1:0]$11137 2'00 case - assign $7\r2__data_o$next[1:0]$10739 $1\r2__data_o$next[1:0]$10733 + assign $7\r2__data_o$next[1:0]$11137 $1\r2__data_o$next[1:0]$11131 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$10732 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11130 end - attribute \src "libresoc.v:166479.3-166514.6" - process $proc$libresoc.v:166479$10740 + attribute \src "libresoc.v:169904.3-169939.6" + process $proc$libresoc.v:169904$11138 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10741 $1\wr_detect$10[0:0]$10742 - attribute \src "libresoc.v:166480.5-166480.29" + assign $0\wr_detect$10[0:0]$11139 $1\wr_detect$10[0:0]$11140 + attribute \src "libresoc.v:169905.5-169905.29" switch \initial - attribute \src "libresoc.v:166480.9-166480.17" + attribute \src "libresoc.v:169905.9-169905.17" case 1'1 case end @@ -343709,61 +351639,61 @@ module \reg_2$131 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10742 $5\wr_detect$10[0:0]$10746 + assign $1\wr_detect$10[0:0]$11140 $5\wr_detect$10[0:0]$11144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10743 1'1 + assign $2\wr_detect$10[0:0]$11141 1'1 case - assign $2\wr_detect$10[0:0]$10743 1'0 + assign $2\wr_detect$10[0:0]$11141 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10744 1'1 + assign $3\wr_detect$10[0:0]$11142 1'1 case - assign $3\wr_detect$10[0:0]$10744 $2\wr_detect$10[0:0]$10743 + assign $3\wr_detect$10[0:0]$11142 $2\wr_detect$10[0:0]$11141 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10745 1'1 + assign $4\wr_detect$10[0:0]$11143 1'1 case - assign $4\wr_detect$10[0:0]$10745 $3\wr_detect$10[0:0]$10744 + assign $4\wr_detect$10[0:0]$11143 $3\wr_detect$10[0:0]$11142 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10746 1'1 + assign $5\wr_detect$10[0:0]$11144 1'1 case - assign $5\wr_detect$10[0:0]$10746 $4\wr_detect$10[0:0]$10745 + assign $5\wr_detect$10[0:0]$11144 $4\wr_detect$10[0:0]$11143 end case - assign $1\wr_detect$10[0:0]$10742 1'0 + assign $1\wr_detect$10[0:0]$11140 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10741 + update \wr_detect$10 $0\wr_detect$10[0:0]$11139 end - attribute \src "libresoc.v:166515.3-166547.6" - process $proc$libresoc.v:166515$10747 + attribute \src "libresoc.v:169940.3-169972.6" + process $proc$libresoc.v:169940$11145 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10748 $5\reg$next[1:0]$10753 - attribute \src "libresoc.v:166516.5-166516.29" + assign $0\reg$next[1:0]$11146 $5\reg$next[1:0]$11151 + attribute \src "libresoc.v:169941.5-169941.29" switch \initial - attribute \src "libresoc.v:166516.9-166516.17" + attribute \src "libresoc.v:169941.9-169941.17" case 1'1 case end @@ -343772,135 +351702,135 @@ module \reg_2$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10749 \dest12__data_i + assign $1\reg$next[1:0]$11147 \dest12__data_i case - assign $1\reg$next[1:0]$10749 \reg + assign $1\reg$next[1:0]$11147 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10750 \dest22__data_i + assign $2\reg$next[1:0]$11148 \dest22__data_i case - assign $2\reg$next[1:0]$10750 $1\reg$next[1:0]$10749 + assign $2\reg$next[1:0]$11148 $1\reg$next[1:0]$11147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10751 \dest32__data_i + assign $3\reg$next[1:0]$11149 \dest32__data_i case - assign $3\reg$next[1:0]$10751 $2\reg$next[1:0]$10750 + assign $3\reg$next[1:0]$11149 $2\reg$next[1:0]$11148 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10752 \w2__data_i + assign $4\reg$next[1:0]$11150 \w2__data_i case - assign $4\reg$next[1:0]$10752 $3\reg$next[1:0]$10751 + assign $4\reg$next[1:0]$11150 $3\reg$next[1:0]$11149 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10753 2'00 + assign $5\reg$next[1:0]$11151 2'00 case - assign $5\reg$next[1:0]$10753 $4\reg$next[1:0]$10752 + assign $5\reg$next[1:0]$11151 $4\reg$next[1:0]$11150 end sync always - update \reg$next $0\reg$next[1:0]$10748 + update \reg$next $0\reg$next[1:0]$11146 end - connect \$9 $not$libresoc.v:166173$10680_Y - connect \$1 $not$libresoc.v:166174$10681_Y - connect \$3 $not$libresoc.v:166175$10682_Y - connect \$6 $not$libresoc.v:166176$10683_Y + connect \$9 $not$libresoc.v:169598$11078_Y + connect \$1 $not$libresoc.v:169599$11079_Y + connect \$3 $not$libresoc.v:169600$11080_Y + connect \$6 $not$libresoc.v:169601$11081_Y end -attribute \src "libresoc.v:166552.1-166771.10" +attribute \src "libresoc.v:169977.1-170196.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" -module \reg_2$134 - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $0\cia2__data_o$next[63:0]$10766 - attribute \src "libresoc.v:166602.3-166603.41" +module \reg_2$137 + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $0\cia2__data_o$next[63:0]$11164 + attribute \src "libresoc.v:170027.3-170028.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:166553.7-166553.20" + attribute \src "libresoc.v:169978.7-169978.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $0\msr2__data_o$next[63:0]$10775 - attribute \src "libresoc.v:166600.3-166601.41" + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $0\msr2__data_o$next[63:0]$11173 + attribute \src "libresoc.v:170025.3-170026.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:166744.3-166770.6" - wire width 64 $0\reg$next[63:0]$10789 - attribute \src "libresoc.v:166598.3-166599.25" + attribute \src "libresoc.v:170169.3-170195.6" + wire width 64 $0\reg$next[63:0]$11187 + attribute \src "libresoc.v:170023.3-170024.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:166714.3-166743.6" - wire $0\wr_detect$4[0:0]$10783 - attribute \src "libresoc.v:166644.3-166673.6" + attribute \src "libresoc.v:170139.3-170168.6" + wire $0\wr_detect$4[0:0]$11181 + attribute \src "libresoc.v:170069.3-170098.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $1\cia2__data_o$next[63:0]$10767 - attribute \src "libresoc.v:166560.14-166560.49" + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $1\cia2__data_o$next[63:0]$11165 + attribute \src "libresoc.v:169985.14-169985.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $1\msr2__data_o$next[63:0]$10776 - attribute \src "libresoc.v:166577.14-166577.49" + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $1\msr2__data_o$next[63:0]$11174 + attribute \src "libresoc.v:170002.14-170002.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:166744.3-166770.6" - wire width 64 $1\reg$next[63:0]$10790 - attribute \src "libresoc.v:166589.14-166589.42" + attribute \src "libresoc.v:170169.3-170195.6" + wire width 64 $1\reg$next[63:0]$11188 + attribute \src "libresoc.v:170014.14-170014.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:166714.3-166743.6" - wire $1\wr_detect$4[0:0]$10784 - attribute \src "libresoc.v:166644.3-166673.6" + attribute \src "libresoc.v:170139.3-170168.6" + wire $1\wr_detect$4[0:0]$11182 + attribute \src "libresoc.v:170069.3-170098.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $2\cia2__data_o$next[63:0]$10768 - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $2\msr2__data_o$next[63:0]$10777 - attribute \src "libresoc.v:166744.3-166770.6" - wire width 64 $2\reg$next[63:0]$10791 - attribute \src "libresoc.v:166714.3-166743.6" - wire $2\wr_detect$4[0:0]$10785 - attribute \src "libresoc.v:166644.3-166673.6" + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $2\cia2__data_o$next[63:0]$11166 + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $2\msr2__data_o$next[63:0]$11175 + attribute \src "libresoc.v:170169.3-170195.6" + wire width 64 $2\reg$next[63:0]$11189 + attribute \src "libresoc.v:170139.3-170168.6" + wire $2\wr_detect$4[0:0]$11183 + attribute \src "libresoc.v:170069.3-170098.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $3\cia2__data_o$next[63:0]$10769 - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $3\msr2__data_o$next[63:0]$10778 - attribute \src "libresoc.v:166744.3-166770.6" - wire width 64 $3\reg$next[63:0]$10792 - attribute \src "libresoc.v:166714.3-166743.6" - wire $3\wr_detect$4[0:0]$10786 - attribute \src "libresoc.v:166644.3-166673.6" + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $3\cia2__data_o$next[63:0]$11167 + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $3\msr2__data_o$next[63:0]$11176 + attribute \src "libresoc.v:170169.3-170195.6" + wire width 64 $3\reg$next[63:0]$11190 + attribute \src "libresoc.v:170139.3-170168.6" + wire $3\wr_detect$4[0:0]$11184 + attribute \src "libresoc.v:170069.3-170098.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $4\cia2__data_o$next[63:0]$10770 - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $4\msr2__data_o$next[63:0]$10779 - attribute \src "libresoc.v:166744.3-166770.6" - wire width 64 $4\reg$next[63:0]$10793 - attribute \src "libresoc.v:166714.3-166743.6" - wire $4\wr_detect$4[0:0]$10787 - attribute \src "libresoc.v:166644.3-166673.6" + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $4\cia2__data_o$next[63:0]$11168 + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $4\msr2__data_o$next[63:0]$11177 + attribute \src "libresoc.v:170169.3-170195.6" + wire width 64 $4\reg$next[63:0]$11191 + attribute \src "libresoc.v:170139.3-170168.6" + wire $4\wr_detect$4[0:0]$11185 + attribute \src "libresoc.v:170069.3-170098.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $5\cia2__data_o$next[63:0]$10771 - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $5\msr2__data_o$next[63:0]$10780 - attribute \src "libresoc.v:166604.3-166643.6" - wire width 64 $6\cia2__data_o$next[63:0]$10772 - attribute \src "libresoc.v:166674.3-166713.6" - wire width 64 $6\msr2__data_o$next[63:0]$10781 - attribute \src "libresoc.v:166596.17-166596.100" - wire $not$libresoc.v:166596$10760_Y - attribute \src "libresoc.v:166597.17-166597.103" - wire $not$libresoc.v:166597$10761_Y + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $5\cia2__data_o$next[63:0]$11169 + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $5\msr2__data_o$next[63:0]$11178 + attribute \src "libresoc.v:170029.3-170068.6" + wire width 64 $6\cia2__data_o$next[63:0]$11170 + attribute \src "libresoc.v:170099.3-170138.6" + wire width 64 $6\msr2__data_o$next[63:0]$11179 + attribute \src "libresoc.v:170021.17-170021.100" + wire $not$libresoc.v:170021$11158_Y + attribute \src "libresoc.v:170022.17-170022.103" + wire $not$libresoc.v:170022$11159_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -343911,15 +351841,15 @@ module \reg_2$134 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \d_wr12__wen - attribute \src "libresoc.v:166553.7-166553.15" + attribute \src "libresoc.v:169978.7-169978.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 9 \msr2__data_i @@ -343944,83 +351874,83 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166596$10760 + cell $not $not$libresoc.v:170021$11158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:166596$10760_Y + connect \Y $not$libresoc.v:170021$11158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166597$10761 + cell $not $not$libresoc.v:170022$11159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:166597$10761_Y + connect \Y $not$libresoc.v:170022$11159_Y end - attribute \src "libresoc.v:166553.7-166553.20" - process $proc$libresoc.v:166553$10794 + attribute \src "libresoc.v:169978.7-169978.20" + process $proc$libresoc.v:169978$11192 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166560.14-166560.49" - process $proc$libresoc.v:166560$10795 + attribute \src "libresoc.v:169985.14-169985.49" + process $proc$libresoc.v:169985$11193 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:166577.14-166577.49" - process $proc$libresoc.v:166577$10796 + attribute \src "libresoc.v:170002.14-170002.49" + process $proc$libresoc.v:170002$11194 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:166589.14-166589.42" - process $proc$libresoc.v:166589$10797 + attribute \src "libresoc.v:170014.14-170014.42" + process $proc$libresoc.v:170014$11195 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:166598.3-166599.25" - process $proc$libresoc.v:166598$10762 + attribute \src "libresoc.v:170023.3-170024.25" + process $proc$libresoc.v:170023$11160 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:166600.3-166601.41" - process $proc$libresoc.v:166600$10763 + attribute \src "libresoc.v:170025.3-170026.41" + process $proc$libresoc.v:170025$11161 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:166602.3-166603.41" - process $proc$libresoc.v:166602$10764 + attribute \src "libresoc.v:170027.3-170028.41" + process $proc$libresoc.v:170027$11162 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:166604.3-166643.6" - process $proc$libresoc.v:166604$10765 + attribute \src "libresoc.v:170029.3-170068.6" + process $proc$libresoc.v:170029$11163 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$10766 $6\cia2__data_o$next[63:0]$10772 - attribute \src "libresoc.v:166605.5-166605.29" + assign $0\cia2__data_o$next[63:0]$11164 $6\cia2__data_o$next[63:0]$11170 + attribute \src "libresoc.v:170030.5-170030.29" switch \initial - attribute \src "libresoc.v:166605.9-166605.17" + attribute \src "libresoc.v:170030.9-170030.17" case 1'1 case end @@ -344032,66 +351962,66 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$10767 $5\cia2__data_o$next[63:0]$10771 + assign $1\cia2__data_o$next[63:0]$11165 $5\cia2__data_o$next[63:0]$11169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$10768 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11166 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$10768 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11166 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$10769 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11167 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$10769 $2\cia2__data_o$next[63:0]$10768 + assign $3\cia2__data_o$next[63:0]$11167 $2\cia2__data_o$next[63:0]$11166 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$10770 \d_wr12__data_i + assign $4\cia2__data_o$next[63:0]$11168 \d_wr12__data_i case - assign $4\cia2__data_o$next[63:0]$10770 $3\cia2__data_o$next[63:0]$10769 + assign $4\cia2__data_o$next[63:0]$11168 $3\cia2__data_o$next[63:0]$11167 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$10771 \reg + assign $5\cia2__data_o$next[63:0]$11169 \reg case - assign $5\cia2__data_o$next[63:0]$10771 $4\cia2__data_o$next[63:0]$10770 + assign $5\cia2__data_o$next[63:0]$11169 $4\cia2__data_o$next[63:0]$11168 end case - assign $1\cia2__data_o$next[63:0]$10767 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11165 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$10772 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\cia2__data_o$next[63:0]$11170 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia2__data_o$next[63:0]$10772 $1\cia2__data_o$next[63:0]$10767 + assign $6\cia2__data_o$next[63:0]$11170 $1\cia2__data_o$next[63:0]$11165 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$10766 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11164 end - attribute \src "libresoc.v:166644.3-166673.6" - process $proc$libresoc.v:166644$10773 + attribute \src "libresoc.v:170069.3-170098.6" + process $proc$libresoc.v:170069$11171 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:166645.5-166645.29" + attribute \src "libresoc.v:170070.5-170070.29" switch \initial - attribute \src "libresoc.v:166645.9-166645.17" + attribute \src "libresoc.v:170070.9-170070.17" case 1'1 case end @@ -344137,15 +352067,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:166674.3-166713.6" - process $proc$libresoc.v:166674$10774 + attribute \src "libresoc.v:170099.3-170138.6" + process $proc$libresoc.v:170099$11172 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$10775 $6\msr2__data_o$next[63:0]$10781 - attribute \src "libresoc.v:166675.5-166675.29" + assign $0\msr2__data_o$next[63:0]$11173 $6\msr2__data_o$next[63:0]$11179 + attribute \src "libresoc.v:170100.5-170100.29" switch \initial - attribute \src "libresoc.v:166675.9-166675.17" + attribute \src "libresoc.v:170100.9-170100.17" case 1'1 case end @@ -344157,66 +352087,66 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$10776 $5\msr2__data_o$next[63:0]$10780 + assign $1\msr2__data_o$next[63:0]$11174 $5\msr2__data_o$next[63:0]$11178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$10777 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11175 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$10777 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11175 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$10778 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11176 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$10778 $2\msr2__data_o$next[63:0]$10777 + assign $3\msr2__data_o$next[63:0]$11176 $2\msr2__data_o$next[63:0]$11175 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$10779 \d_wr12__data_i + assign $4\msr2__data_o$next[63:0]$11177 \d_wr12__data_i case - assign $4\msr2__data_o$next[63:0]$10779 $3\msr2__data_o$next[63:0]$10778 + assign $4\msr2__data_o$next[63:0]$11177 $3\msr2__data_o$next[63:0]$11176 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$10780 \reg + assign $5\msr2__data_o$next[63:0]$11178 \reg case - assign $5\msr2__data_o$next[63:0]$10780 $4\msr2__data_o$next[63:0]$10779 + assign $5\msr2__data_o$next[63:0]$11178 $4\msr2__data_o$next[63:0]$11177 end case - assign $1\msr2__data_o$next[63:0]$10776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11174 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$10781 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\msr2__data_o$next[63:0]$11179 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr2__data_o$next[63:0]$10781 $1\msr2__data_o$next[63:0]$10776 + assign $6\msr2__data_o$next[63:0]$11179 $1\msr2__data_o$next[63:0]$11174 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$10775 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11173 end - attribute \src "libresoc.v:166714.3-166743.6" - process $proc$libresoc.v:166714$10782 + attribute \src "libresoc.v:170139.3-170168.6" + process $proc$libresoc.v:170139$11180 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10783 $1\wr_detect$4[0:0]$10784 - attribute \src "libresoc.v:166715.5-166715.29" + assign $0\wr_detect$4[0:0]$11181 $1\wr_detect$4[0:0]$11182 + attribute \src "libresoc.v:170140.5-170140.29" switch \initial - attribute \src "libresoc.v:166715.9-166715.17" + attribute \src "libresoc.v:170140.9-170140.17" case 1'1 case end @@ -344228,51 +352158,51 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10784 $4\wr_detect$4[0:0]$10787 + assign $1\wr_detect$4[0:0]$11182 $4\wr_detect$4[0:0]$11185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10785 1'1 + assign $2\wr_detect$4[0:0]$11183 1'1 case - assign $2\wr_detect$4[0:0]$10785 1'0 + assign $2\wr_detect$4[0:0]$11183 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10786 1'1 + assign $3\wr_detect$4[0:0]$11184 1'1 case - assign $3\wr_detect$4[0:0]$10786 $2\wr_detect$4[0:0]$10785 + assign $3\wr_detect$4[0:0]$11184 $2\wr_detect$4[0:0]$11183 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10787 1'1 + assign $4\wr_detect$4[0:0]$11185 1'1 case - assign $4\wr_detect$4[0:0]$10787 $3\wr_detect$4[0:0]$10786 + assign $4\wr_detect$4[0:0]$11185 $3\wr_detect$4[0:0]$11184 end case - assign $1\wr_detect$4[0:0]$10784 1'0 + assign $1\wr_detect$4[0:0]$11182 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10783 + update \wr_detect$4 $0\wr_detect$4[0:0]$11181 end - attribute \src "libresoc.v:166744.3-166770.6" - process $proc$libresoc.v:166744$10788 + attribute \src "libresoc.v:170169.3-170195.6" + process $proc$libresoc.v:170169$11186 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10789 $4\reg$next[63:0]$10793 - attribute \src "libresoc.v:166745.5-166745.29" + assign $0\reg$next[63:0]$11187 $4\reg$next[63:0]$11191 + attribute \src "libresoc.v:170170.5-170170.29" switch \initial - attribute \src "libresoc.v:166745.9-166745.17" + attribute \src "libresoc.v:170170.9-170170.17" case 1'1 case end @@ -344281,214 +352211,214 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10790 \nia2__data_i + assign $1\reg$next[63:0]$11188 \nia2__data_i case - assign $1\reg$next[63:0]$10790 \reg + assign $1\reg$next[63:0]$11188 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10791 \msr2__data_i + assign $2\reg$next[63:0]$11189 \msr2__data_i case - assign $2\reg$next[63:0]$10791 $1\reg$next[63:0]$10790 + assign $2\reg$next[63:0]$11189 $1\reg$next[63:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10792 \d_wr12__data_i + assign $3\reg$next[63:0]$11190 \d_wr12__data_i case - assign $3\reg$next[63:0]$10792 $2\reg$next[63:0]$10791 + assign $3\reg$next[63:0]$11190 $2\reg$next[63:0]$11189 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10793 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\reg$next[63:0]$11191 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10793 $3\reg$next[63:0]$10792 + assign $4\reg$next[63:0]$11191 $3\reg$next[63:0]$11190 end sync always - update \reg$next $0\reg$next[63:0]$10789 + update \reg$next $0\reg$next[63:0]$11187 end - connect \$1 $not$libresoc.v:166596$10760_Y - connect \$3 $not$libresoc.v:166597$10761_Y + connect \$1 $not$libresoc.v:170021$11158_Y + connect \$3 $not$libresoc.v:170022$11159_Y end -attribute \src "libresoc.v:166775.1-167246.10" +attribute \src "libresoc.v:170200.1-170671.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:166776.7-166776.20" + attribute \src "libresoc.v:170201.7-170201.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $0\r23__data_o$next[3:0]$10867 - attribute \src "libresoc.v:166859.3-166860.39" + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $0\r23__data_o$next[3:0]$11265 + attribute \src "libresoc.v:170284.3-170285.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $0\r3__data_o$next[3:0]$10853 - attribute \src "libresoc.v:166861.3-166862.37" + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $0\r3__data_o$next[3:0]$11251 + attribute \src "libresoc.v:170286.3-170287.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:166939.3-166965.6" - wire width 4 $0\reg$next[3:0]$10819 - attribute \src "libresoc.v:166857.3-166858.25" + attribute \src "libresoc.v:170364.3-170390.6" + wire width 4 $0\reg$next[3:0]$11217 + attribute \src "libresoc.v:170282.3-170283.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $0\src13__data_o$next[3:0]$10810 - attribute \src "libresoc.v:166867.3-166868.43" + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $0\src13__data_o$next[3:0]$11208 + attribute \src "libresoc.v:170292.3-170293.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $0\src23__data_o$next[3:0]$10825 - attribute \src "libresoc.v:166865.3-166866.43" + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $0\src23__data_o$next[3:0]$11223 + attribute \src "libresoc.v:170290.3-170291.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $0\src33__data_o$next[3:0]$10839 - attribute \src "libresoc.v:166863.3-166864.43" + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $0\src33__data_o$next[3:0]$11237 + attribute \src "libresoc.v:170288.3-170289.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:167146.3-167175.6" - wire $0\wr_detect$10[0:0]$10861 - attribute \src "libresoc.v:167216.3-167245.6" - wire $0\wr_detect$13[0:0]$10875 - attribute \src "libresoc.v:167006.3-167035.6" - wire $0\wr_detect$4[0:0]$10833 - attribute \src "libresoc.v:167076.3-167105.6" - wire $0\wr_detect$7[0:0]$10847 - attribute \src "libresoc.v:166909.3-166938.6" + attribute \src "libresoc.v:170571.3-170600.6" + wire $0\wr_detect$10[0:0]$11259 + attribute \src "libresoc.v:170641.3-170670.6" + wire $0\wr_detect$13[0:0]$11273 + attribute \src "libresoc.v:170431.3-170460.6" + wire $0\wr_detect$4[0:0]$11231 + attribute \src "libresoc.v:170501.3-170530.6" + wire $0\wr_detect$7[0:0]$11245 + attribute \src "libresoc.v:170334.3-170363.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $1\r23__data_o$next[3:0]$10868 - attribute \src "libresoc.v:166801.13-166801.31" + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $1\r23__data_o$next[3:0]$11266 + attribute \src "libresoc.v:170226.13-170226.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $1\r3__data_o$next[3:0]$10854 - attribute \src "libresoc.v:166808.13-166808.30" + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $1\r3__data_o$next[3:0]$11252 + attribute \src "libresoc.v:170233.13-170233.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:166939.3-166965.6" - wire width 4 $1\reg$next[3:0]$10820 - attribute \src "libresoc.v:166814.13-166814.25" + attribute \src "libresoc.v:170364.3-170390.6" + wire width 4 $1\reg$next[3:0]$11218 + attribute \src "libresoc.v:170239.13-170239.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $1\src13__data_o$next[3:0]$10811 - attribute \src "libresoc.v:166819.13-166819.33" + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $1\src13__data_o$next[3:0]$11209 + attribute \src "libresoc.v:170244.13-170244.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $1\src23__data_o$next[3:0]$10826 - attribute \src "libresoc.v:166826.13-166826.33" + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $1\src23__data_o$next[3:0]$11224 + attribute \src "libresoc.v:170251.13-170251.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $1\src33__data_o$next[3:0]$10840 - attribute \src "libresoc.v:166833.13-166833.33" + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $1\src33__data_o$next[3:0]$11238 + attribute \src "libresoc.v:170258.13-170258.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:167146.3-167175.6" - wire $1\wr_detect$10[0:0]$10862 - attribute \src "libresoc.v:167216.3-167245.6" - wire $1\wr_detect$13[0:0]$10876 - attribute \src "libresoc.v:167006.3-167035.6" - wire $1\wr_detect$4[0:0]$10834 - attribute \src "libresoc.v:167076.3-167105.6" - wire $1\wr_detect$7[0:0]$10848 - attribute \src "libresoc.v:166909.3-166938.6" + attribute \src "libresoc.v:170571.3-170600.6" + wire $1\wr_detect$10[0:0]$11260 + attribute \src "libresoc.v:170641.3-170670.6" + wire $1\wr_detect$13[0:0]$11274 + attribute \src "libresoc.v:170431.3-170460.6" + wire $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:170501.3-170530.6" + wire $1\wr_detect$7[0:0]$11246 + attribute \src "libresoc.v:170334.3-170363.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $2\r23__data_o$next[3:0]$10869 - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $2\r3__data_o$next[3:0]$10855 - attribute \src "libresoc.v:166939.3-166965.6" - wire width 4 $2\reg$next[3:0]$10821 - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $2\src13__data_o$next[3:0]$10812 - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $2\src23__data_o$next[3:0]$10827 - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $2\src33__data_o$next[3:0]$10841 - attribute \src "libresoc.v:167146.3-167175.6" - wire $2\wr_detect$10[0:0]$10863 - attribute \src "libresoc.v:167216.3-167245.6" - wire $2\wr_detect$13[0:0]$10877 - attribute \src "libresoc.v:167006.3-167035.6" - wire $2\wr_detect$4[0:0]$10835 - attribute \src "libresoc.v:167076.3-167105.6" - wire $2\wr_detect$7[0:0]$10849 - attribute \src "libresoc.v:166909.3-166938.6" + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $2\r23__data_o$next[3:0]$11267 + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $2\r3__data_o$next[3:0]$11253 + attribute \src "libresoc.v:170364.3-170390.6" + wire width 4 $2\reg$next[3:0]$11219 + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $2\src13__data_o$next[3:0]$11210 + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $2\src23__data_o$next[3:0]$11225 + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $2\src33__data_o$next[3:0]$11239 + attribute \src "libresoc.v:170571.3-170600.6" + wire $2\wr_detect$10[0:0]$11261 + attribute \src "libresoc.v:170641.3-170670.6" + wire $2\wr_detect$13[0:0]$11275 + attribute \src "libresoc.v:170431.3-170460.6" + wire $2\wr_detect$4[0:0]$11233 + attribute \src "libresoc.v:170501.3-170530.6" + wire $2\wr_detect$7[0:0]$11247 + attribute \src "libresoc.v:170334.3-170363.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $3\r23__data_o$next[3:0]$10870 - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $3\r3__data_o$next[3:0]$10856 - attribute \src "libresoc.v:166939.3-166965.6" - wire width 4 $3\reg$next[3:0]$10822 - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $3\src13__data_o$next[3:0]$10813 - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $3\src23__data_o$next[3:0]$10828 - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $3\src33__data_o$next[3:0]$10842 - attribute \src "libresoc.v:167146.3-167175.6" - wire $3\wr_detect$10[0:0]$10864 - attribute \src "libresoc.v:167216.3-167245.6" - wire $3\wr_detect$13[0:0]$10878 - attribute \src "libresoc.v:167006.3-167035.6" - wire $3\wr_detect$4[0:0]$10836 - attribute \src "libresoc.v:167076.3-167105.6" - wire $3\wr_detect$7[0:0]$10850 - attribute \src "libresoc.v:166909.3-166938.6" + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $3\r23__data_o$next[3:0]$11268 + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $3\r3__data_o$next[3:0]$11254 + attribute \src "libresoc.v:170364.3-170390.6" + wire width 4 $3\reg$next[3:0]$11220 + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $3\src13__data_o$next[3:0]$11211 + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $3\src23__data_o$next[3:0]$11226 + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $3\src33__data_o$next[3:0]$11240 + attribute \src "libresoc.v:170571.3-170600.6" + wire $3\wr_detect$10[0:0]$11262 + attribute \src "libresoc.v:170641.3-170670.6" + wire $3\wr_detect$13[0:0]$11276 + attribute \src "libresoc.v:170431.3-170460.6" + wire $3\wr_detect$4[0:0]$11234 + attribute \src "libresoc.v:170501.3-170530.6" + wire $3\wr_detect$7[0:0]$11248 + attribute \src "libresoc.v:170334.3-170363.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $4\r23__data_o$next[3:0]$10871 - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $4\r3__data_o$next[3:0]$10857 - attribute \src "libresoc.v:166939.3-166965.6" - wire width 4 $4\reg$next[3:0]$10823 - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $4\src13__data_o$next[3:0]$10814 - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $4\src23__data_o$next[3:0]$10829 - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $4\src33__data_o$next[3:0]$10843 - attribute \src "libresoc.v:167146.3-167175.6" - wire $4\wr_detect$10[0:0]$10865 - attribute \src "libresoc.v:167216.3-167245.6" - wire $4\wr_detect$13[0:0]$10879 - attribute \src "libresoc.v:167006.3-167035.6" - wire $4\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:167076.3-167105.6" - wire $4\wr_detect$7[0:0]$10851 - attribute \src "libresoc.v:166909.3-166938.6" + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $4\r23__data_o$next[3:0]$11269 + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $4\r3__data_o$next[3:0]$11255 + attribute \src "libresoc.v:170364.3-170390.6" + wire width 4 $4\reg$next[3:0]$11221 + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $4\src13__data_o$next[3:0]$11212 + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $4\src23__data_o$next[3:0]$11227 + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $4\src33__data_o$next[3:0]$11241 + attribute \src "libresoc.v:170571.3-170600.6" + wire $4\wr_detect$10[0:0]$11263 + attribute \src "libresoc.v:170641.3-170670.6" + wire $4\wr_detect$13[0:0]$11277 + attribute \src "libresoc.v:170431.3-170460.6" + wire $4\wr_detect$4[0:0]$11235 + attribute \src "libresoc.v:170501.3-170530.6" + wire $4\wr_detect$7[0:0]$11249 + attribute \src "libresoc.v:170334.3-170363.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $5\r23__data_o$next[3:0]$10872 - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $5\r3__data_o$next[3:0]$10858 - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $5\src13__data_o$next[3:0]$10815 - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $5\src23__data_o$next[3:0]$10830 - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $5\src33__data_o$next[3:0]$10844 - attribute \src "libresoc.v:167176.3-167215.6" - wire width 4 $6\r23__data_o$next[3:0]$10873 - attribute \src "libresoc.v:167106.3-167145.6" - wire width 4 $6\r3__data_o$next[3:0]$10859 - attribute \src "libresoc.v:166869.3-166908.6" - wire width 4 $6\src13__data_o$next[3:0]$10816 - attribute \src "libresoc.v:166966.3-167005.6" - wire width 4 $6\src23__data_o$next[3:0]$10831 - attribute \src "libresoc.v:167036.3-167075.6" - wire width 4 $6\src33__data_o$next[3:0]$10845 - attribute \src "libresoc.v:166852.17-166852.104" - wire $not$libresoc.v:166852$10798_Y - attribute \src "libresoc.v:166853.18-166853.105" - wire $not$libresoc.v:166853$10799_Y - attribute \src "libresoc.v:166854.17-166854.100" - wire $not$libresoc.v:166854$10800_Y - attribute \src "libresoc.v:166855.17-166855.103" - wire $not$libresoc.v:166855$10801_Y - attribute \src "libresoc.v:166856.17-166856.103" - wire $not$libresoc.v:166856$10802_Y + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $5\r23__data_o$next[3:0]$11270 + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $5\r3__data_o$next[3:0]$11256 + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $5\src13__data_o$next[3:0]$11213 + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $5\src23__data_o$next[3:0]$11228 + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $5\src33__data_o$next[3:0]$11242 + attribute \src "libresoc.v:170601.3-170640.6" + wire width 4 $6\r23__data_o$next[3:0]$11271 + attribute \src "libresoc.v:170531.3-170570.6" + wire width 4 $6\r3__data_o$next[3:0]$11257 + attribute \src "libresoc.v:170294.3-170333.6" + wire width 4 $6\src13__data_o$next[3:0]$11214 + attribute \src "libresoc.v:170391.3-170430.6" + wire width 4 $6\src23__data_o$next[3:0]$11229 + attribute \src "libresoc.v:170461.3-170500.6" + wire width 4 $6\src33__data_o$next[3:0]$11243 + attribute \src "libresoc.v:170277.17-170277.104" + wire $not$libresoc.v:170277$11196_Y + attribute \src "libresoc.v:170278.18-170278.105" + wire $not$libresoc.v:170278$11197_Y + attribute \src "libresoc.v:170279.17-170279.100" + wire $not$libresoc.v:170279$11198_Y + attribute \src "libresoc.v:170280.17-170280.103" + wire $not$libresoc.v:170280$11199_Y + attribute \src "libresoc.v:170281.17-170281.103" + wire $not$libresoc.v:170281$11200_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -344499,9 +352429,9 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest13__data_i @@ -344511,7 +352441,7 @@ module \reg_3 wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest23__wen - attribute \src "libresoc.v:166776.7-166776.15" + attribute \src "libresoc.v:170201.7-170201.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r23__data_o @@ -344562,152 +352492,152 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166852$10798 + cell $not $not$libresoc.v:170277$11196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:166852$10798_Y + connect \Y $not$libresoc.v:170277$11196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166853$10799 + cell $not $not$libresoc.v:170278$11197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:166853$10799_Y + connect \Y $not$libresoc.v:170278$11197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166854$10800 + cell $not $not$libresoc.v:170279$11198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:166854$10800_Y + connect \Y $not$libresoc.v:170279$11198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166855$10801 + cell $not $not$libresoc.v:170280$11199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:166855$10801_Y + connect \Y $not$libresoc.v:170280$11199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166856$10802 + cell $not $not$libresoc.v:170281$11200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:166856$10802_Y + connect \Y $not$libresoc.v:170281$11200_Y end - attribute \src "libresoc.v:166776.7-166776.20" - process $proc$libresoc.v:166776$10880 + attribute \src "libresoc.v:170201.7-170201.20" + process $proc$libresoc.v:170201$11278 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166801.13-166801.31" - process $proc$libresoc.v:166801$10881 + attribute \src "libresoc.v:170226.13-170226.31" + process $proc$libresoc.v:170226$11279 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:166808.13-166808.30" - process $proc$libresoc.v:166808$10882 + attribute \src "libresoc.v:170233.13-170233.30" + process $proc$libresoc.v:170233$11280 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:166814.13-166814.25" - process $proc$libresoc.v:166814$10883 + attribute \src "libresoc.v:170239.13-170239.25" + process $proc$libresoc.v:170239$11281 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:166819.13-166819.33" - process $proc$libresoc.v:166819$10884 + attribute \src "libresoc.v:170244.13-170244.33" + process $proc$libresoc.v:170244$11282 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:166826.13-166826.33" - process $proc$libresoc.v:166826$10885 + attribute \src "libresoc.v:170251.13-170251.33" + process $proc$libresoc.v:170251$11283 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:166833.13-166833.33" - process $proc$libresoc.v:166833$10886 + attribute \src "libresoc.v:170258.13-170258.33" + process $proc$libresoc.v:170258$11284 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:166857.3-166858.25" - process $proc$libresoc.v:166857$10803 + attribute \src "libresoc.v:170282.3-170283.25" + process $proc$libresoc.v:170282$11201 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:166859.3-166860.39" - process $proc$libresoc.v:166859$10804 + attribute \src "libresoc.v:170284.3-170285.39" + process $proc$libresoc.v:170284$11202 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:166861.3-166862.37" - process $proc$libresoc.v:166861$10805 + attribute \src "libresoc.v:170286.3-170287.37" + process $proc$libresoc.v:170286$11203 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:166863.3-166864.43" - process $proc$libresoc.v:166863$10806 + attribute \src "libresoc.v:170288.3-170289.43" + process $proc$libresoc.v:170288$11204 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:166865.3-166866.43" - process $proc$libresoc.v:166865$10807 + attribute \src "libresoc.v:170290.3-170291.43" + process $proc$libresoc.v:170290$11205 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:166867.3-166868.43" - process $proc$libresoc.v:166867$10808 + attribute \src "libresoc.v:170292.3-170293.43" + process $proc$libresoc.v:170292$11206 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:166869.3-166908.6" - process $proc$libresoc.v:166869$10809 + attribute \src "libresoc.v:170294.3-170333.6" + process $proc$libresoc.v:170294$11207 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$10810 $6\src13__data_o$next[3:0]$10816 - attribute \src "libresoc.v:166870.5-166870.29" + assign $0\src13__data_o$next[3:0]$11208 $6\src13__data_o$next[3:0]$11214 + attribute \src "libresoc.v:170295.5-170295.29" switch \initial - attribute \src "libresoc.v:166870.9-166870.17" + attribute \src "libresoc.v:170295.9-170295.17" case 1'1 case end @@ -344719,66 +352649,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$10811 $5\src13__data_o$next[3:0]$10815 + assign $1\src13__data_o$next[3:0]$11209 $5\src13__data_o$next[3:0]$11213 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$10812 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11210 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$10812 4'0000 + assign $2\src13__data_o$next[3:0]$11210 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$10813 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11211 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$10813 $2\src13__data_o$next[3:0]$10812 + assign $3\src13__data_o$next[3:0]$11211 $2\src13__data_o$next[3:0]$11210 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$10814 \w3__data_i + assign $4\src13__data_o$next[3:0]$11212 \w3__data_i case - assign $4\src13__data_o$next[3:0]$10814 $3\src13__data_o$next[3:0]$10813 + assign $4\src13__data_o$next[3:0]$11212 $3\src13__data_o$next[3:0]$11211 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$10815 \reg + assign $5\src13__data_o$next[3:0]$11213 \reg case - assign $5\src13__data_o$next[3:0]$10815 $4\src13__data_o$next[3:0]$10814 + assign $5\src13__data_o$next[3:0]$11213 $4\src13__data_o$next[3:0]$11212 end case - assign $1\src13__data_o$next[3:0]$10811 4'0000 + assign $1\src13__data_o$next[3:0]$11209 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$10816 4'0000 + assign $6\src13__data_o$next[3:0]$11214 4'0000 case - assign $6\src13__data_o$next[3:0]$10816 $1\src13__data_o$next[3:0]$10811 + assign $6\src13__data_o$next[3:0]$11214 $1\src13__data_o$next[3:0]$11209 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$10810 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11208 end - attribute \src "libresoc.v:166909.3-166938.6" - process $proc$libresoc.v:166909$10817 + attribute \src "libresoc.v:170334.3-170363.6" + process $proc$libresoc.v:170334$11215 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:166910.5-166910.29" + attribute \src "libresoc.v:170335.5-170335.29" switch \initial - attribute \src "libresoc.v:166910.9-166910.17" + attribute \src "libresoc.v:170335.9-170335.17" case 1'1 case end @@ -344824,17 +352754,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:166939.3-166965.6" - process $proc$libresoc.v:166939$10818 + attribute \src "libresoc.v:170364.3-170390.6" + process $proc$libresoc.v:170364$11216 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10819 $4\reg$next[3:0]$10823 - attribute \src "libresoc.v:166940.5-166940.29" + assign $0\reg$next[3:0]$11217 $4\reg$next[3:0]$11221 + attribute \src "libresoc.v:170365.5-170365.29" switch \initial - attribute \src "libresoc.v:166940.9-166940.17" + attribute \src "libresoc.v:170365.9-170365.17" case 1'1 case end @@ -344843,49 +352773,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10820 \dest13__data_i + assign $1\reg$next[3:0]$11218 \dest13__data_i case - assign $1\reg$next[3:0]$10820 \reg + assign $1\reg$next[3:0]$11218 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10821 \dest23__data_i + assign $2\reg$next[3:0]$11219 \dest23__data_i case - assign $2\reg$next[3:0]$10821 $1\reg$next[3:0]$10820 + assign $2\reg$next[3:0]$11219 $1\reg$next[3:0]$11218 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10822 \w3__data_i + assign $3\reg$next[3:0]$11220 \w3__data_i case - assign $3\reg$next[3:0]$10822 $2\reg$next[3:0]$10821 + assign $3\reg$next[3:0]$11220 $2\reg$next[3:0]$11219 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10823 4'0000 + assign $4\reg$next[3:0]$11221 4'0000 case - assign $4\reg$next[3:0]$10823 $3\reg$next[3:0]$10822 + assign $4\reg$next[3:0]$11221 $3\reg$next[3:0]$11220 end sync always - update \reg$next $0\reg$next[3:0]$10819 + update \reg$next $0\reg$next[3:0]$11217 end - attribute \src "libresoc.v:166966.3-167005.6" - process $proc$libresoc.v:166966$10824 + attribute \src "libresoc.v:170391.3-170430.6" + process $proc$libresoc.v:170391$11222 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$10825 $6\src23__data_o$next[3:0]$10831 - attribute \src "libresoc.v:166967.5-166967.29" + assign $0\src23__data_o$next[3:0]$11223 $6\src23__data_o$next[3:0]$11229 + attribute \src "libresoc.v:170392.5-170392.29" switch \initial - attribute \src "libresoc.v:166967.9-166967.17" + attribute \src "libresoc.v:170392.9-170392.17" case 1'1 case end @@ -344897,66 +352827,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$10826 $5\src23__data_o$next[3:0]$10830 + assign $1\src23__data_o$next[3:0]$11224 $5\src23__data_o$next[3:0]$11228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$10827 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11225 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$10827 4'0000 + assign $2\src23__data_o$next[3:0]$11225 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$10828 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11226 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$10828 $2\src23__data_o$next[3:0]$10827 + assign $3\src23__data_o$next[3:0]$11226 $2\src23__data_o$next[3:0]$11225 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$10829 \w3__data_i + assign $4\src23__data_o$next[3:0]$11227 \w3__data_i case - assign $4\src23__data_o$next[3:0]$10829 $3\src23__data_o$next[3:0]$10828 + assign $4\src23__data_o$next[3:0]$11227 $3\src23__data_o$next[3:0]$11226 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$10830 \reg + assign $5\src23__data_o$next[3:0]$11228 \reg case - assign $5\src23__data_o$next[3:0]$10830 $4\src23__data_o$next[3:0]$10829 + assign $5\src23__data_o$next[3:0]$11228 $4\src23__data_o$next[3:0]$11227 end case - assign $1\src23__data_o$next[3:0]$10826 4'0000 + assign $1\src23__data_o$next[3:0]$11224 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$10831 4'0000 + assign $6\src23__data_o$next[3:0]$11229 4'0000 case - assign $6\src23__data_o$next[3:0]$10831 $1\src23__data_o$next[3:0]$10826 + assign $6\src23__data_o$next[3:0]$11229 $1\src23__data_o$next[3:0]$11224 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$10825 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11223 end - attribute \src "libresoc.v:167006.3-167035.6" - process $proc$libresoc.v:167006$10832 + attribute \src "libresoc.v:170431.3-170460.6" + process $proc$libresoc.v:170431$11230 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10833 $1\wr_detect$4[0:0]$10834 - attribute \src "libresoc.v:167007.5-167007.29" + assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 + attribute \src "libresoc.v:170432.5-170432.29" switch \initial - attribute \src "libresoc.v:167007.9-167007.17" + attribute \src "libresoc.v:170432.9-170432.17" case 1'1 case end @@ -344968,49 +352898,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10834 $4\wr_detect$4[0:0]$10837 + assign $1\wr_detect$4[0:0]$11232 $4\wr_detect$4[0:0]$11235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10835 1'1 + assign $2\wr_detect$4[0:0]$11233 1'1 case - assign $2\wr_detect$4[0:0]$10835 1'0 + assign $2\wr_detect$4[0:0]$11233 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10836 1'1 + assign $3\wr_detect$4[0:0]$11234 1'1 case - assign $3\wr_detect$4[0:0]$10836 $2\wr_detect$4[0:0]$10835 + assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10837 1'1 + assign $4\wr_detect$4[0:0]$11235 1'1 case - assign $4\wr_detect$4[0:0]$10837 $3\wr_detect$4[0:0]$10836 + assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 end case - assign $1\wr_detect$4[0:0]$10834 1'0 + assign $1\wr_detect$4[0:0]$11232 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10833 + update \wr_detect$4 $0\wr_detect$4[0:0]$11231 end - attribute \src "libresoc.v:167036.3-167075.6" - process $proc$libresoc.v:167036$10838 + attribute \src "libresoc.v:170461.3-170500.6" + process $proc$libresoc.v:170461$11236 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$10839 $6\src33__data_o$next[3:0]$10845 - attribute \src "libresoc.v:167037.5-167037.29" + assign $0\src33__data_o$next[3:0]$11237 $6\src33__data_o$next[3:0]$11243 + attribute \src "libresoc.v:170462.5-170462.29" switch \initial - attribute \src "libresoc.v:167037.9-167037.17" + attribute \src "libresoc.v:170462.9-170462.17" case 1'1 case end @@ -345022,66 +352952,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$10840 $5\src33__data_o$next[3:0]$10844 + assign $1\src33__data_o$next[3:0]$11238 $5\src33__data_o$next[3:0]$11242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$10841 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11239 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$10841 4'0000 + assign $2\src33__data_o$next[3:0]$11239 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$10842 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11240 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$10842 $2\src33__data_o$next[3:0]$10841 + assign $3\src33__data_o$next[3:0]$11240 $2\src33__data_o$next[3:0]$11239 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$10843 \w3__data_i + assign $4\src33__data_o$next[3:0]$11241 \w3__data_i case - assign $4\src33__data_o$next[3:0]$10843 $3\src33__data_o$next[3:0]$10842 + assign $4\src33__data_o$next[3:0]$11241 $3\src33__data_o$next[3:0]$11240 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$10844 \reg + assign $5\src33__data_o$next[3:0]$11242 \reg case - assign $5\src33__data_o$next[3:0]$10844 $4\src33__data_o$next[3:0]$10843 + assign $5\src33__data_o$next[3:0]$11242 $4\src33__data_o$next[3:0]$11241 end case - assign $1\src33__data_o$next[3:0]$10840 4'0000 + assign $1\src33__data_o$next[3:0]$11238 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$10845 4'0000 + assign $6\src33__data_o$next[3:0]$11243 4'0000 case - assign $6\src33__data_o$next[3:0]$10845 $1\src33__data_o$next[3:0]$10840 + assign $6\src33__data_o$next[3:0]$11243 $1\src33__data_o$next[3:0]$11238 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$10839 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11237 end - attribute \src "libresoc.v:167076.3-167105.6" - process $proc$libresoc.v:167076$10846 + attribute \src "libresoc.v:170501.3-170530.6" + process $proc$libresoc.v:170501$11244 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10847 $1\wr_detect$7[0:0]$10848 - attribute \src "libresoc.v:167077.5-167077.29" + assign $0\wr_detect$7[0:0]$11245 $1\wr_detect$7[0:0]$11246 + attribute \src "libresoc.v:170502.5-170502.29" switch \initial - attribute \src "libresoc.v:167077.9-167077.17" + attribute \src "libresoc.v:170502.9-170502.17" case 1'1 case end @@ -345093,49 +353023,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10848 $4\wr_detect$7[0:0]$10851 + assign $1\wr_detect$7[0:0]$11246 $4\wr_detect$7[0:0]$11249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10849 1'1 + assign $2\wr_detect$7[0:0]$11247 1'1 case - assign $2\wr_detect$7[0:0]$10849 1'0 + assign $2\wr_detect$7[0:0]$11247 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10850 1'1 + assign $3\wr_detect$7[0:0]$11248 1'1 case - assign $3\wr_detect$7[0:0]$10850 $2\wr_detect$7[0:0]$10849 + assign $3\wr_detect$7[0:0]$11248 $2\wr_detect$7[0:0]$11247 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10851 1'1 + assign $4\wr_detect$7[0:0]$11249 1'1 case - assign $4\wr_detect$7[0:0]$10851 $3\wr_detect$7[0:0]$10850 + assign $4\wr_detect$7[0:0]$11249 $3\wr_detect$7[0:0]$11248 end case - assign $1\wr_detect$7[0:0]$10848 1'0 + assign $1\wr_detect$7[0:0]$11246 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10847 + update \wr_detect$7 $0\wr_detect$7[0:0]$11245 end - attribute \src "libresoc.v:167106.3-167145.6" - process $proc$libresoc.v:167106$10852 + attribute \src "libresoc.v:170531.3-170570.6" + process $proc$libresoc.v:170531$11250 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$10853 $6\r3__data_o$next[3:0]$10859 - attribute \src "libresoc.v:167107.5-167107.29" + assign $0\r3__data_o$next[3:0]$11251 $6\r3__data_o$next[3:0]$11257 + attribute \src "libresoc.v:170532.5-170532.29" switch \initial - attribute \src "libresoc.v:167107.9-167107.17" + attribute \src "libresoc.v:170532.9-170532.17" case 1'1 case end @@ -345147,66 +353077,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$10854 $5\r3__data_o$next[3:0]$10858 + assign $1\r3__data_o$next[3:0]$11252 $5\r3__data_o$next[3:0]$11256 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$10855 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11253 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$10855 4'0000 + assign $2\r3__data_o$next[3:0]$11253 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$10856 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11254 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$10856 $2\r3__data_o$next[3:0]$10855 + assign $3\r3__data_o$next[3:0]$11254 $2\r3__data_o$next[3:0]$11253 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$10857 \w3__data_i + assign $4\r3__data_o$next[3:0]$11255 \w3__data_i case - assign $4\r3__data_o$next[3:0]$10857 $3\r3__data_o$next[3:0]$10856 + assign $4\r3__data_o$next[3:0]$11255 $3\r3__data_o$next[3:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$10858 \reg + assign $5\r3__data_o$next[3:0]$11256 \reg case - assign $5\r3__data_o$next[3:0]$10858 $4\r3__data_o$next[3:0]$10857 + assign $5\r3__data_o$next[3:0]$11256 $4\r3__data_o$next[3:0]$11255 end case - assign $1\r3__data_o$next[3:0]$10854 4'0000 + assign $1\r3__data_o$next[3:0]$11252 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$10859 4'0000 + assign $6\r3__data_o$next[3:0]$11257 4'0000 case - assign $6\r3__data_o$next[3:0]$10859 $1\r3__data_o$next[3:0]$10854 + assign $6\r3__data_o$next[3:0]$11257 $1\r3__data_o$next[3:0]$11252 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$10853 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11251 end - attribute \src "libresoc.v:167146.3-167175.6" - process $proc$libresoc.v:167146$10860 + attribute \src "libresoc.v:170571.3-170600.6" + process $proc$libresoc.v:170571$11258 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10861 $1\wr_detect$10[0:0]$10862 - attribute \src "libresoc.v:167147.5-167147.29" + assign $0\wr_detect$10[0:0]$11259 $1\wr_detect$10[0:0]$11260 + attribute \src "libresoc.v:170572.5-170572.29" switch \initial - attribute \src "libresoc.v:167147.9-167147.17" + attribute \src "libresoc.v:170572.9-170572.17" case 1'1 case end @@ -345218,49 +353148,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10862 $4\wr_detect$10[0:0]$10865 + assign $1\wr_detect$10[0:0]$11260 $4\wr_detect$10[0:0]$11263 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10863 1'1 + assign $2\wr_detect$10[0:0]$11261 1'1 case - assign $2\wr_detect$10[0:0]$10863 1'0 + assign $2\wr_detect$10[0:0]$11261 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10864 1'1 + assign $3\wr_detect$10[0:0]$11262 1'1 case - assign $3\wr_detect$10[0:0]$10864 $2\wr_detect$10[0:0]$10863 + assign $3\wr_detect$10[0:0]$11262 $2\wr_detect$10[0:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10865 1'1 + assign $4\wr_detect$10[0:0]$11263 1'1 case - assign $4\wr_detect$10[0:0]$10865 $3\wr_detect$10[0:0]$10864 + assign $4\wr_detect$10[0:0]$11263 $3\wr_detect$10[0:0]$11262 end case - assign $1\wr_detect$10[0:0]$10862 1'0 + assign $1\wr_detect$10[0:0]$11260 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10861 + update \wr_detect$10 $0\wr_detect$10[0:0]$11259 end - attribute \src "libresoc.v:167176.3-167215.6" - process $proc$libresoc.v:167176$10866 + attribute \src "libresoc.v:170601.3-170640.6" + process $proc$libresoc.v:170601$11264 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$10867 $6\r23__data_o$next[3:0]$10873 - attribute \src "libresoc.v:167177.5-167177.29" + assign $0\r23__data_o$next[3:0]$11265 $6\r23__data_o$next[3:0]$11271 + attribute \src "libresoc.v:170602.5-170602.29" switch \initial - attribute \src "libresoc.v:167177.9-167177.17" + attribute \src "libresoc.v:170602.9-170602.17" case 1'1 case end @@ -345272,66 +353202,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$10868 $5\r23__data_o$next[3:0]$10872 + assign $1\r23__data_o$next[3:0]$11266 $5\r23__data_o$next[3:0]$11270 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$10869 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11267 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$10869 4'0000 + assign $2\r23__data_o$next[3:0]$11267 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$10870 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11268 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$10870 $2\r23__data_o$next[3:0]$10869 + assign $3\r23__data_o$next[3:0]$11268 $2\r23__data_o$next[3:0]$11267 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$10871 \w3__data_i + assign $4\r23__data_o$next[3:0]$11269 \w3__data_i case - assign $4\r23__data_o$next[3:0]$10871 $3\r23__data_o$next[3:0]$10870 + assign $4\r23__data_o$next[3:0]$11269 $3\r23__data_o$next[3:0]$11268 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$10872 \reg + assign $5\r23__data_o$next[3:0]$11270 \reg case - assign $5\r23__data_o$next[3:0]$10872 $4\r23__data_o$next[3:0]$10871 + assign $5\r23__data_o$next[3:0]$11270 $4\r23__data_o$next[3:0]$11269 end case - assign $1\r23__data_o$next[3:0]$10868 4'0000 + assign $1\r23__data_o$next[3:0]$11266 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$10873 4'0000 + assign $6\r23__data_o$next[3:0]$11271 4'0000 case - assign $6\r23__data_o$next[3:0]$10873 $1\r23__data_o$next[3:0]$10868 + assign $6\r23__data_o$next[3:0]$11271 $1\r23__data_o$next[3:0]$11266 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$10867 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11265 end - attribute \src "libresoc.v:167216.3-167245.6" - process $proc$libresoc.v:167216$10874 + attribute \src "libresoc.v:170641.3-170670.6" + process $proc$libresoc.v:170641$11272 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10875 $1\wr_detect$13[0:0]$10876 - attribute \src "libresoc.v:167217.5-167217.29" + assign $0\wr_detect$13[0:0]$11273 $1\wr_detect$13[0:0]$11274 + attribute \src "libresoc.v:170642.5-170642.29" switch \initial - attribute \src "libresoc.v:167217.9-167217.17" + attribute \src "libresoc.v:170642.9-170642.17" case 1'1 case end @@ -345343,127 +353273,127 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10876 $4\wr_detect$13[0:0]$10879 + assign $1\wr_detect$13[0:0]$11274 $4\wr_detect$13[0:0]$11277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10877 1'1 + assign $2\wr_detect$13[0:0]$11275 1'1 case - assign $2\wr_detect$13[0:0]$10877 1'0 + assign $2\wr_detect$13[0:0]$11275 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10878 1'1 + assign $3\wr_detect$13[0:0]$11276 1'1 case - assign $3\wr_detect$13[0:0]$10878 $2\wr_detect$13[0:0]$10877 + assign $3\wr_detect$13[0:0]$11276 $2\wr_detect$13[0:0]$11275 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10879 1'1 + assign $4\wr_detect$13[0:0]$11277 1'1 case - assign $4\wr_detect$13[0:0]$10879 $3\wr_detect$13[0:0]$10878 + assign $4\wr_detect$13[0:0]$11277 $3\wr_detect$13[0:0]$11276 end case - assign $1\wr_detect$13[0:0]$10876 1'0 + assign $1\wr_detect$13[0:0]$11274 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10875 + update \wr_detect$13 $0\wr_detect$13[0:0]$11273 end - connect \$9 $not$libresoc.v:166852$10798_Y - connect \$12 $not$libresoc.v:166853$10799_Y - connect \$1 $not$libresoc.v:166854$10800_Y - connect \$3 $not$libresoc.v:166855$10801_Y - connect \$6 $not$libresoc.v:166856$10802_Y + connect \$9 $not$libresoc.v:170277$11196_Y + connect \$12 $not$libresoc.v:170278$11197_Y + connect \$1 $not$libresoc.v:170279$11198_Y + connect \$3 $not$libresoc.v:170280$11199_Y + connect \$6 $not$libresoc.v:170281$11200_Y end -attribute \src "libresoc.v:167250.1-167469.10" +attribute \src "libresoc.v:170675.1-170894.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_3" attribute \generator "nMigen" -module \reg_3$135 - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $0\cia3__data_o$next[63:0]$10893 - attribute \src "libresoc.v:167300.3-167301.41" +module \reg_3$138 + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $0\cia3__data_o$next[63:0]$11291 + attribute \src "libresoc.v:170725.3-170726.41" wire width 64 $0\cia3__data_o[63:0] - attribute \src "libresoc.v:167251.7-167251.20" + attribute \src "libresoc.v:170676.7-170676.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $0\msr3__data_o$next[63:0]$10902 - attribute \src "libresoc.v:167298.3-167299.41" + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $0\msr3__data_o$next[63:0]$11300 + attribute \src "libresoc.v:170723.3-170724.41" wire width 64 $0\msr3__data_o[63:0] - attribute \src "libresoc.v:167442.3-167468.6" - wire width 64 $0\reg$next[63:0]$10916 - attribute \src "libresoc.v:167296.3-167297.25" + attribute \src "libresoc.v:170867.3-170893.6" + wire width 64 $0\reg$next[63:0]$11314 + attribute \src "libresoc.v:170721.3-170722.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:167412.3-167441.6" - wire $0\wr_detect$4[0:0]$10910 - attribute \src "libresoc.v:167342.3-167371.6" + attribute \src "libresoc.v:170837.3-170866.6" + wire $0\wr_detect$4[0:0]$11308 + attribute \src "libresoc.v:170767.3-170796.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $1\cia3__data_o$next[63:0]$10894 - attribute \src "libresoc.v:167258.14-167258.49" + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $1\cia3__data_o$next[63:0]$11292 + attribute \src "libresoc.v:170683.14-170683.49" wire width 64 $1\cia3__data_o[63:0] - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $1\msr3__data_o$next[63:0]$10903 - attribute \src "libresoc.v:167275.14-167275.49" + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $1\msr3__data_o$next[63:0]$11301 + attribute \src "libresoc.v:170700.14-170700.49" wire width 64 $1\msr3__data_o[63:0] - attribute \src "libresoc.v:167442.3-167468.6" - wire width 64 $1\reg$next[63:0]$10917 - attribute \src "libresoc.v:167287.14-167287.42" + attribute \src "libresoc.v:170867.3-170893.6" + wire width 64 $1\reg$next[63:0]$11315 + attribute \src "libresoc.v:170712.14-170712.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:167412.3-167441.6" - wire $1\wr_detect$4[0:0]$10911 - attribute \src "libresoc.v:167342.3-167371.6" + attribute \src "libresoc.v:170837.3-170866.6" + wire $1\wr_detect$4[0:0]$11309 + attribute \src "libresoc.v:170767.3-170796.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $2\cia3__data_o$next[63:0]$10895 - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $2\msr3__data_o$next[63:0]$10904 - attribute \src "libresoc.v:167442.3-167468.6" - wire width 64 $2\reg$next[63:0]$10918 - attribute \src "libresoc.v:167412.3-167441.6" - wire $2\wr_detect$4[0:0]$10912 - attribute \src "libresoc.v:167342.3-167371.6" + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $2\cia3__data_o$next[63:0]$11293 + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $2\msr3__data_o$next[63:0]$11302 + attribute \src "libresoc.v:170867.3-170893.6" + wire width 64 $2\reg$next[63:0]$11316 + attribute \src "libresoc.v:170837.3-170866.6" + wire $2\wr_detect$4[0:0]$11310 + attribute \src "libresoc.v:170767.3-170796.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $3\cia3__data_o$next[63:0]$10896 - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $3\msr3__data_o$next[63:0]$10905 - attribute \src "libresoc.v:167442.3-167468.6" - wire width 64 $3\reg$next[63:0]$10919 - attribute \src "libresoc.v:167412.3-167441.6" - wire $3\wr_detect$4[0:0]$10913 - attribute \src "libresoc.v:167342.3-167371.6" + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $3\cia3__data_o$next[63:0]$11294 + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $3\msr3__data_o$next[63:0]$11303 + attribute \src "libresoc.v:170867.3-170893.6" + wire width 64 $3\reg$next[63:0]$11317 + attribute \src "libresoc.v:170837.3-170866.6" + wire $3\wr_detect$4[0:0]$11311 + attribute \src "libresoc.v:170767.3-170796.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $4\cia3__data_o$next[63:0]$10897 - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $4\msr3__data_o$next[63:0]$10906 - attribute \src "libresoc.v:167442.3-167468.6" - wire width 64 $4\reg$next[63:0]$10920 - attribute \src "libresoc.v:167412.3-167441.6" - wire $4\wr_detect$4[0:0]$10914 - attribute \src "libresoc.v:167342.3-167371.6" + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $4\cia3__data_o$next[63:0]$11295 + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $4\msr3__data_o$next[63:0]$11304 + attribute \src "libresoc.v:170867.3-170893.6" + wire width 64 $4\reg$next[63:0]$11318 + attribute \src "libresoc.v:170837.3-170866.6" + wire $4\wr_detect$4[0:0]$11312 + attribute \src "libresoc.v:170767.3-170796.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $5\cia3__data_o$next[63:0]$10898 - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $5\msr3__data_o$next[63:0]$10907 - attribute \src "libresoc.v:167302.3-167341.6" - wire width 64 $6\cia3__data_o$next[63:0]$10899 - attribute \src "libresoc.v:167372.3-167411.6" - wire width 64 $6\msr3__data_o$next[63:0]$10908 - attribute \src "libresoc.v:167294.17-167294.100" - wire $not$libresoc.v:167294$10887_Y - attribute \src "libresoc.v:167295.17-167295.103" - wire $not$libresoc.v:167295$10888_Y + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $5\cia3__data_o$next[63:0]$11296 + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $5\msr3__data_o$next[63:0]$11305 + attribute \src "libresoc.v:170727.3-170766.6" + wire width 64 $6\cia3__data_o$next[63:0]$11297 + attribute \src "libresoc.v:170797.3-170836.6" + wire width 64 $6\msr3__data_o$next[63:0]$11306 + attribute \src "libresoc.v:170719.17-170719.100" + wire $not$libresoc.v:170719$11285_Y + attribute \src "libresoc.v:170720.17-170720.103" + wire $not$libresoc.v:170720$11286_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -345474,15 +353404,15 @@ module \reg_3$135 wire width 64 \cia3__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 2 \cia3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 11 \d_wr13__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \d_wr13__wen - attribute \src "libresoc.v:167251.7-167251.15" + attribute \src "libresoc.v:170676.7-170676.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 input 9 \msr3__data_i @@ -345507,83 +353437,83 @@ module \reg_3$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167294$10887 + cell $not $not$libresoc.v:170719$11285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:167294$10887_Y + connect \Y $not$libresoc.v:170719$11285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167295$10888 + cell $not $not$libresoc.v:170720$11286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167295$10888_Y + connect \Y $not$libresoc.v:170720$11286_Y end - attribute \src "libresoc.v:167251.7-167251.20" - process $proc$libresoc.v:167251$10921 + attribute \src "libresoc.v:170676.7-170676.20" + process $proc$libresoc.v:170676$11319 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167258.14-167258.49" - process $proc$libresoc.v:167258$10922 + attribute \src "libresoc.v:170683.14-170683.49" + process $proc$libresoc.v:170683$11320 assign { } { } assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia3__data_o $1\cia3__data_o[63:0] end - attribute \src "libresoc.v:167275.14-167275.49" - process $proc$libresoc.v:167275$10923 + attribute \src "libresoc.v:170700.14-170700.49" + process $proc$libresoc.v:170700$11321 assign { } { } assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr3__data_o $1\msr3__data_o[63:0] end - attribute \src "libresoc.v:167287.14-167287.42" - process $proc$libresoc.v:167287$10924 + attribute \src "libresoc.v:170712.14-170712.42" + process $proc$libresoc.v:170712$11322 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:167296.3-167297.25" - process $proc$libresoc.v:167296$10889 + attribute \src "libresoc.v:170721.3-170722.25" + process $proc$libresoc.v:170721$11287 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:167298.3-167299.41" - process $proc$libresoc.v:167298$10890 + attribute \src "libresoc.v:170723.3-170724.41" + process $proc$libresoc.v:170723$11288 assign { } { } assign $0\msr3__data_o[63:0] \msr3__data_o$next sync posedge \coresync_clk update \msr3__data_o $0\msr3__data_o[63:0] end - attribute \src "libresoc.v:167300.3-167301.41" - process $proc$libresoc.v:167300$10891 + attribute \src "libresoc.v:170725.3-170726.41" + process $proc$libresoc.v:170725$11289 assign { } { } assign $0\cia3__data_o[63:0] \cia3__data_o$next sync posedge \coresync_clk update \cia3__data_o $0\cia3__data_o[63:0] end - attribute \src "libresoc.v:167302.3-167341.6" - process $proc$libresoc.v:167302$10892 + attribute \src "libresoc.v:170727.3-170766.6" + process $proc$libresoc.v:170727$11290 assign { } { } assign { } { } assign { } { } - assign $0\cia3__data_o$next[63:0]$10893 $6\cia3__data_o$next[63:0]$10899 - attribute \src "libresoc.v:167303.5-167303.29" + assign $0\cia3__data_o$next[63:0]$11291 $6\cia3__data_o$next[63:0]$11297 + attribute \src "libresoc.v:170728.5-170728.29" switch \initial - attribute \src "libresoc.v:167303.9-167303.17" + attribute \src "libresoc.v:170728.9-170728.17" case 1'1 case end @@ -345595,66 +353525,66 @@ module \reg_3$135 assign { } { } assign { } { } assign { } { } - assign $1\cia3__data_o$next[63:0]$10894 $5\cia3__data_o$next[63:0]$10898 + assign $1\cia3__data_o$next[63:0]$11292 $5\cia3__data_o$next[63:0]$11296 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia3__data_o$next[63:0]$10895 \nia3__data_i + assign $2\cia3__data_o$next[63:0]$11293 \nia3__data_i case - assign $2\cia3__data_o$next[63:0]$10895 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia3__data_o$next[63:0]$11293 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia3__data_o$next[63:0]$10896 \msr3__data_i + assign $3\cia3__data_o$next[63:0]$11294 \msr3__data_i case - assign $3\cia3__data_o$next[63:0]$10896 $2\cia3__data_o$next[63:0]$10895 + assign $3\cia3__data_o$next[63:0]$11294 $2\cia3__data_o$next[63:0]$11293 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia3__data_o$next[63:0]$10897 \d_wr13__data_i + assign $4\cia3__data_o$next[63:0]$11295 \d_wr13__data_i case - assign $4\cia3__data_o$next[63:0]$10897 $3\cia3__data_o$next[63:0]$10896 + assign $4\cia3__data_o$next[63:0]$11295 $3\cia3__data_o$next[63:0]$11294 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia3__data_o$next[63:0]$10898 \reg + assign $5\cia3__data_o$next[63:0]$11296 \reg case - assign $5\cia3__data_o$next[63:0]$10898 $4\cia3__data_o$next[63:0]$10897 + assign $5\cia3__data_o$next[63:0]$11296 $4\cia3__data_o$next[63:0]$11295 end case - assign $1\cia3__data_o$next[63:0]$10894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia3__data_o$next[63:0]$11292 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia3__data_o$next[63:0]$10899 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\cia3__data_o$next[63:0]$11297 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\cia3__data_o$next[63:0]$10899 $1\cia3__data_o$next[63:0]$10894 + assign $6\cia3__data_o$next[63:0]$11297 $1\cia3__data_o$next[63:0]$11292 end sync always - update \cia3__data_o$next $0\cia3__data_o$next[63:0]$10893 + update \cia3__data_o$next $0\cia3__data_o$next[63:0]$11291 end - attribute \src "libresoc.v:167342.3-167371.6" - process $proc$libresoc.v:167342$10900 + attribute \src "libresoc.v:170767.3-170796.6" + process $proc$libresoc.v:170767$11298 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167343.5-167343.29" + attribute \src "libresoc.v:170768.5-170768.29" switch \initial - attribute \src "libresoc.v:167343.9-167343.17" + attribute \src "libresoc.v:170768.9-170768.17" case 1'1 case end @@ -345700,15 +353630,15 @@ module \reg_3$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:167372.3-167411.6" - process $proc$libresoc.v:167372$10901 + attribute \src "libresoc.v:170797.3-170836.6" + process $proc$libresoc.v:170797$11299 assign { } { } assign { } { } assign { } { } - assign $0\msr3__data_o$next[63:0]$10902 $6\msr3__data_o$next[63:0]$10908 - attribute \src "libresoc.v:167373.5-167373.29" + assign $0\msr3__data_o$next[63:0]$11300 $6\msr3__data_o$next[63:0]$11306 + attribute \src "libresoc.v:170798.5-170798.29" switch \initial - attribute \src "libresoc.v:167373.9-167373.17" + attribute \src "libresoc.v:170798.9-170798.17" case 1'1 case end @@ -345720,66 +353650,66 @@ module \reg_3$135 assign { } { } assign { } { } assign { } { } - assign $1\msr3__data_o$next[63:0]$10903 $5\msr3__data_o$next[63:0]$10907 + assign $1\msr3__data_o$next[63:0]$11301 $5\msr3__data_o$next[63:0]$11305 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr3__data_o$next[63:0]$10904 \nia3__data_i + assign $2\msr3__data_o$next[63:0]$11302 \nia3__data_i case - assign $2\msr3__data_o$next[63:0]$10904 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr3__data_o$next[63:0]$11302 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr3__data_o$next[63:0]$10905 \msr3__data_i + assign $3\msr3__data_o$next[63:0]$11303 \msr3__data_i case - assign $3\msr3__data_o$next[63:0]$10905 $2\msr3__data_o$next[63:0]$10904 + assign $3\msr3__data_o$next[63:0]$11303 $2\msr3__data_o$next[63:0]$11302 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr3__data_o$next[63:0]$10906 \d_wr13__data_i + assign $4\msr3__data_o$next[63:0]$11304 \d_wr13__data_i case - assign $4\msr3__data_o$next[63:0]$10906 $3\msr3__data_o$next[63:0]$10905 + assign $4\msr3__data_o$next[63:0]$11304 $3\msr3__data_o$next[63:0]$11303 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr3__data_o$next[63:0]$10907 \reg + assign $5\msr3__data_o$next[63:0]$11305 \reg case - assign $5\msr3__data_o$next[63:0]$10907 $4\msr3__data_o$next[63:0]$10906 + assign $5\msr3__data_o$next[63:0]$11305 $4\msr3__data_o$next[63:0]$11304 end case - assign $1\msr3__data_o$next[63:0]$10903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr3__data_o$next[63:0]$11301 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr3__data_o$next[63:0]$10908 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $6\msr3__data_o$next[63:0]$11306 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $6\msr3__data_o$next[63:0]$10908 $1\msr3__data_o$next[63:0]$10903 + assign $6\msr3__data_o$next[63:0]$11306 $1\msr3__data_o$next[63:0]$11301 end sync always - update \msr3__data_o$next $0\msr3__data_o$next[63:0]$10902 + update \msr3__data_o$next $0\msr3__data_o$next[63:0]$11300 end - attribute \src "libresoc.v:167412.3-167441.6" - process $proc$libresoc.v:167412$10909 + attribute \src "libresoc.v:170837.3-170866.6" + process $proc$libresoc.v:170837$11307 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10910 $1\wr_detect$4[0:0]$10911 - attribute \src "libresoc.v:167413.5-167413.29" + assign $0\wr_detect$4[0:0]$11308 $1\wr_detect$4[0:0]$11309 + attribute \src "libresoc.v:170838.5-170838.29" switch \initial - attribute \src "libresoc.v:167413.9-167413.17" + attribute \src "libresoc.v:170838.9-170838.17" case 1'1 case end @@ -345791,51 +353721,51 @@ module \reg_3$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10911 $4\wr_detect$4[0:0]$10914 + assign $1\wr_detect$4[0:0]$11309 $4\wr_detect$4[0:0]$11312 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10912 1'1 + assign $2\wr_detect$4[0:0]$11310 1'1 case - assign $2\wr_detect$4[0:0]$10912 1'0 + assign $2\wr_detect$4[0:0]$11310 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10913 1'1 + assign $3\wr_detect$4[0:0]$11311 1'1 case - assign $3\wr_detect$4[0:0]$10913 $2\wr_detect$4[0:0]$10912 + assign $3\wr_detect$4[0:0]$11311 $2\wr_detect$4[0:0]$11310 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10914 1'1 + assign $4\wr_detect$4[0:0]$11312 1'1 case - assign $4\wr_detect$4[0:0]$10914 $3\wr_detect$4[0:0]$10913 + assign $4\wr_detect$4[0:0]$11312 $3\wr_detect$4[0:0]$11311 end case - assign $1\wr_detect$4[0:0]$10911 1'0 + assign $1\wr_detect$4[0:0]$11309 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10910 + update \wr_detect$4 $0\wr_detect$4[0:0]$11308 end - attribute \src "libresoc.v:167442.3-167468.6" - process $proc$libresoc.v:167442$10915 + attribute \src "libresoc.v:170867.3-170893.6" + process $proc$libresoc.v:170867$11313 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10916 $4\reg$next[63:0]$10920 - attribute \src "libresoc.v:167443.5-167443.29" + assign $0\reg$next[63:0]$11314 $4\reg$next[63:0]$11318 + attribute \src "libresoc.v:170868.5-170868.29" switch \initial - attribute \src "libresoc.v:167443.9-167443.17" + attribute \src "libresoc.v:170868.9-170868.17" case 1'1 case end @@ -345844,214 +353774,214 @@ module \reg_3$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10917 \nia3__data_i + assign $1\reg$next[63:0]$11315 \nia3__data_i case - assign $1\reg$next[63:0]$10917 \reg + assign $1\reg$next[63:0]$11315 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10918 \msr3__data_i + assign $2\reg$next[63:0]$11316 \msr3__data_i case - assign $2\reg$next[63:0]$10918 $1\reg$next[63:0]$10917 + assign $2\reg$next[63:0]$11316 $1\reg$next[63:0]$11315 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10919 \d_wr13__data_i + assign $3\reg$next[63:0]$11317 \d_wr13__data_i case - assign $3\reg$next[63:0]$10919 $2\reg$next[63:0]$10918 + assign $3\reg$next[63:0]$11317 $2\reg$next[63:0]$11316 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\reg$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\reg$next[63:0]$10920 $3\reg$next[63:0]$10919 + assign $4\reg$next[63:0]$11318 $3\reg$next[63:0]$11317 end sync always - update \reg$next $0\reg$next[63:0]$10916 + update \reg$next $0\reg$next[63:0]$11314 end - connect \$1 $not$libresoc.v:167294$10887_Y - connect \$3 $not$libresoc.v:167295$10888_Y + connect \$1 $not$libresoc.v:170719$11285_Y + connect \$3 $not$libresoc.v:170720$11286_Y end -attribute \src "libresoc.v:167473.1-167944.10" +attribute \src "libresoc.v:170898.1-171369.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:167474.7-167474.20" + attribute \src "libresoc.v:170899.7-170899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $0\r24__data_o$next[3:0]$10994 - attribute \src "libresoc.v:167557.3-167558.39" + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $0\r24__data_o$next[3:0]$11392 + attribute \src "libresoc.v:170982.3-170983.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $0\r4__data_o$next[3:0]$10980 - attribute \src "libresoc.v:167559.3-167560.37" + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $0\r4__data_o$next[3:0]$11378 + attribute \src "libresoc.v:170984.3-170985.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:167637.3-167663.6" - wire width 4 $0\reg$next[3:0]$10946 - attribute \src "libresoc.v:167555.3-167556.25" + attribute \src "libresoc.v:171062.3-171088.6" + wire width 4 $0\reg$next[3:0]$11344 + attribute \src "libresoc.v:170980.3-170981.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $0\src14__data_o$next[3:0]$10937 - attribute \src "libresoc.v:167565.3-167566.43" + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $0\src14__data_o$next[3:0]$11335 + attribute \src "libresoc.v:170990.3-170991.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $0\src24__data_o$next[3:0]$10952 - attribute \src "libresoc.v:167563.3-167564.43" + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $0\src24__data_o$next[3:0]$11350 + attribute \src "libresoc.v:170988.3-170989.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $0\src34__data_o$next[3:0]$10966 - attribute \src "libresoc.v:167561.3-167562.43" + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $0\src34__data_o$next[3:0]$11364 + attribute \src "libresoc.v:170986.3-170987.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:167844.3-167873.6" - wire $0\wr_detect$10[0:0]$10988 - attribute \src "libresoc.v:167914.3-167943.6" - wire $0\wr_detect$13[0:0]$11002 - attribute \src "libresoc.v:167704.3-167733.6" - wire $0\wr_detect$4[0:0]$10960 - attribute \src "libresoc.v:167774.3-167803.6" - wire $0\wr_detect$7[0:0]$10974 - attribute \src "libresoc.v:167607.3-167636.6" + attribute \src "libresoc.v:171269.3-171298.6" + wire $0\wr_detect$10[0:0]$11386 + attribute \src "libresoc.v:171339.3-171368.6" + wire $0\wr_detect$13[0:0]$11400 + attribute \src "libresoc.v:171129.3-171158.6" + wire $0\wr_detect$4[0:0]$11358 + attribute \src "libresoc.v:171199.3-171228.6" + wire $0\wr_detect$7[0:0]$11372 + attribute \src "libresoc.v:171032.3-171061.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $1\r24__data_o$next[3:0]$10995 - attribute \src "libresoc.v:167499.13-167499.31" + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $1\r24__data_o$next[3:0]$11393 + attribute \src "libresoc.v:170924.13-170924.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $1\r4__data_o$next[3:0]$10981 - attribute \src "libresoc.v:167506.13-167506.30" + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $1\r4__data_o$next[3:0]$11379 + attribute \src "libresoc.v:170931.13-170931.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:167637.3-167663.6" - wire width 4 $1\reg$next[3:0]$10947 - attribute \src "libresoc.v:167512.13-167512.25" + attribute \src "libresoc.v:171062.3-171088.6" + wire width 4 $1\reg$next[3:0]$11345 + attribute \src "libresoc.v:170937.13-170937.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $1\src14__data_o$next[3:0]$10938 - attribute \src "libresoc.v:167517.13-167517.33" + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $1\src14__data_o$next[3:0]$11336 + attribute \src "libresoc.v:170942.13-170942.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $1\src24__data_o$next[3:0]$10953 - attribute \src "libresoc.v:167524.13-167524.33" + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $1\src24__data_o$next[3:0]$11351 + attribute \src "libresoc.v:170949.13-170949.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $1\src34__data_o$next[3:0]$10967 - attribute \src "libresoc.v:167531.13-167531.33" + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $1\src34__data_o$next[3:0]$11365 + attribute \src "libresoc.v:170956.13-170956.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:167844.3-167873.6" - wire $1\wr_detect$10[0:0]$10989 - attribute \src "libresoc.v:167914.3-167943.6" - wire $1\wr_detect$13[0:0]$11003 - attribute \src "libresoc.v:167704.3-167733.6" - wire $1\wr_detect$4[0:0]$10961 - attribute \src "libresoc.v:167774.3-167803.6" - wire $1\wr_detect$7[0:0]$10975 - attribute \src "libresoc.v:167607.3-167636.6" + attribute \src "libresoc.v:171269.3-171298.6" + wire $1\wr_detect$10[0:0]$11387 + attribute \src "libresoc.v:171339.3-171368.6" + wire $1\wr_detect$13[0:0]$11401 + attribute \src "libresoc.v:171129.3-171158.6" + wire $1\wr_detect$4[0:0]$11359 + attribute \src "libresoc.v:171199.3-171228.6" + wire $1\wr_detect$7[0:0]$11373 + attribute \src "libresoc.v:171032.3-171061.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $2\r24__data_o$next[3:0]$10996 - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $2\r4__data_o$next[3:0]$10982 - attribute \src "libresoc.v:167637.3-167663.6" - wire width 4 $2\reg$next[3:0]$10948 - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $2\src14__data_o$next[3:0]$10939 - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $2\src24__data_o$next[3:0]$10954 - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $2\src34__data_o$next[3:0]$10968 - attribute \src "libresoc.v:167844.3-167873.6" - wire $2\wr_detect$10[0:0]$10990 - attribute \src "libresoc.v:167914.3-167943.6" - wire $2\wr_detect$13[0:0]$11004 - attribute \src "libresoc.v:167704.3-167733.6" - wire $2\wr_detect$4[0:0]$10962 - attribute \src "libresoc.v:167774.3-167803.6" - wire $2\wr_detect$7[0:0]$10976 - attribute \src "libresoc.v:167607.3-167636.6" + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $2\r24__data_o$next[3:0]$11394 + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $2\r4__data_o$next[3:0]$11380 + attribute \src "libresoc.v:171062.3-171088.6" + wire width 4 $2\reg$next[3:0]$11346 + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $2\src14__data_o$next[3:0]$11337 + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $2\src24__data_o$next[3:0]$11352 + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $2\src34__data_o$next[3:0]$11366 + attribute \src "libresoc.v:171269.3-171298.6" + wire $2\wr_detect$10[0:0]$11388 + attribute \src "libresoc.v:171339.3-171368.6" + wire $2\wr_detect$13[0:0]$11402 + attribute \src "libresoc.v:171129.3-171158.6" + wire $2\wr_detect$4[0:0]$11360 + attribute \src "libresoc.v:171199.3-171228.6" + wire $2\wr_detect$7[0:0]$11374 + attribute \src "libresoc.v:171032.3-171061.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $3\r24__data_o$next[3:0]$10997 - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $3\r4__data_o$next[3:0]$10983 - attribute \src "libresoc.v:167637.3-167663.6" - wire width 4 $3\reg$next[3:0]$10949 - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $3\src14__data_o$next[3:0]$10940 - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $3\src24__data_o$next[3:0]$10955 - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $3\src34__data_o$next[3:0]$10969 - attribute \src "libresoc.v:167844.3-167873.6" - wire $3\wr_detect$10[0:0]$10991 - attribute \src "libresoc.v:167914.3-167943.6" - wire $3\wr_detect$13[0:0]$11005 - attribute \src "libresoc.v:167704.3-167733.6" - wire $3\wr_detect$4[0:0]$10963 - attribute \src "libresoc.v:167774.3-167803.6" - wire $3\wr_detect$7[0:0]$10977 - attribute \src "libresoc.v:167607.3-167636.6" + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $3\r24__data_o$next[3:0]$11395 + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $3\r4__data_o$next[3:0]$11381 + attribute \src "libresoc.v:171062.3-171088.6" + wire width 4 $3\reg$next[3:0]$11347 + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $3\src14__data_o$next[3:0]$11338 + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $3\src24__data_o$next[3:0]$11353 + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $3\src34__data_o$next[3:0]$11367 + attribute \src "libresoc.v:171269.3-171298.6" + wire $3\wr_detect$10[0:0]$11389 + attribute \src "libresoc.v:171339.3-171368.6" + wire $3\wr_detect$13[0:0]$11403 + attribute \src "libresoc.v:171129.3-171158.6" + wire $3\wr_detect$4[0:0]$11361 + attribute \src "libresoc.v:171199.3-171228.6" + wire $3\wr_detect$7[0:0]$11375 + attribute \src "libresoc.v:171032.3-171061.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $4\r24__data_o$next[3:0]$10998 - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $4\r4__data_o$next[3:0]$10984 - attribute \src "libresoc.v:167637.3-167663.6" - wire width 4 $4\reg$next[3:0]$10950 - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $4\src14__data_o$next[3:0]$10941 - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $4\src24__data_o$next[3:0]$10956 - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $4\src34__data_o$next[3:0]$10970 - attribute \src "libresoc.v:167844.3-167873.6" - wire $4\wr_detect$10[0:0]$10992 - attribute \src "libresoc.v:167914.3-167943.6" - wire $4\wr_detect$13[0:0]$11006 - attribute \src "libresoc.v:167704.3-167733.6" - wire $4\wr_detect$4[0:0]$10964 - attribute \src "libresoc.v:167774.3-167803.6" - wire $4\wr_detect$7[0:0]$10978 - attribute \src "libresoc.v:167607.3-167636.6" + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $4\r24__data_o$next[3:0]$11396 + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $4\r4__data_o$next[3:0]$11382 + attribute \src "libresoc.v:171062.3-171088.6" + wire width 4 $4\reg$next[3:0]$11348 + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $4\src14__data_o$next[3:0]$11339 + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $4\src24__data_o$next[3:0]$11354 + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $4\src34__data_o$next[3:0]$11368 + attribute \src "libresoc.v:171269.3-171298.6" + wire $4\wr_detect$10[0:0]$11390 + attribute \src "libresoc.v:171339.3-171368.6" + wire $4\wr_detect$13[0:0]$11404 + attribute \src "libresoc.v:171129.3-171158.6" + wire $4\wr_detect$4[0:0]$11362 + attribute \src "libresoc.v:171199.3-171228.6" + wire $4\wr_detect$7[0:0]$11376 + attribute \src "libresoc.v:171032.3-171061.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $5\r24__data_o$next[3:0]$10999 - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $5\r4__data_o$next[3:0]$10985 - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $5\src14__data_o$next[3:0]$10942 - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $5\src24__data_o$next[3:0]$10957 - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $5\src34__data_o$next[3:0]$10971 - attribute \src "libresoc.v:167874.3-167913.6" - wire width 4 $6\r24__data_o$next[3:0]$11000 - attribute \src "libresoc.v:167804.3-167843.6" - wire width 4 $6\r4__data_o$next[3:0]$10986 - attribute \src "libresoc.v:167567.3-167606.6" - wire width 4 $6\src14__data_o$next[3:0]$10943 - attribute \src "libresoc.v:167664.3-167703.6" - wire width 4 $6\src24__data_o$next[3:0]$10958 - attribute \src "libresoc.v:167734.3-167773.6" - wire width 4 $6\src34__data_o$next[3:0]$10972 - attribute \src "libresoc.v:167550.17-167550.104" - wire $not$libresoc.v:167550$10925_Y - attribute \src "libresoc.v:167551.18-167551.105" - wire $not$libresoc.v:167551$10926_Y - attribute \src "libresoc.v:167552.17-167552.100" - wire $not$libresoc.v:167552$10927_Y - attribute \src "libresoc.v:167553.17-167553.103" - wire $not$libresoc.v:167553$10928_Y - attribute \src "libresoc.v:167554.17-167554.103" - wire $not$libresoc.v:167554$10929_Y + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $5\r24__data_o$next[3:0]$11397 + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $5\r4__data_o$next[3:0]$11383 + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $5\src14__data_o$next[3:0]$11340 + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $5\src24__data_o$next[3:0]$11355 + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $5\src34__data_o$next[3:0]$11369 + attribute \src "libresoc.v:171299.3-171338.6" + wire width 4 $6\r24__data_o$next[3:0]$11398 + attribute \src "libresoc.v:171229.3-171268.6" + wire width 4 $6\r4__data_o$next[3:0]$11384 + attribute \src "libresoc.v:170992.3-171031.6" + wire width 4 $6\src14__data_o$next[3:0]$11341 + attribute \src "libresoc.v:171089.3-171128.6" + wire width 4 $6\src24__data_o$next[3:0]$11356 + attribute \src "libresoc.v:171159.3-171198.6" + wire width 4 $6\src34__data_o$next[3:0]$11370 + attribute \src "libresoc.v:170975.17-170975.104" + wire $not$libresoc.v:170975$11323_Y + attribute \src "libresoc.v:170976.18-170976.105" + wire $not$libresoc.v:170976$11324_Y + attribute \src "libresoc.v:170977.17-170977.100" + wire $not$libresoc.v:170977$11325_Y + attribute \src "libresoc.v:170978.17-170978.103" + wire $not$libresoc.v:170978$11326_Y + attribute \src "libresoc.v:170979.17-170979.103" + wire $not$libresoc.v:170979$11327_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -346062,9 +353992,9 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest14__data_i @@ -346074,7 +354004,7 @@ module \reg_4 wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest24__wen - attribute \src "libresoc.v:167474.7-167474.15" + attribute \src "libresoc.v:170899.7-170899.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r24__data_o @@ -346125,152 +354055,152 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167550$10925 + cell $not $not$libresoc.v:170975$11323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:167550$10925_Y + connect \Y $not$libresoc.v:170975$11323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167551$10926 + cell $not $not$libresoc.v:170976$11324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:167551$10926_Y + connect \Y $not$libresoc.v:170976$11324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167552$10927 + cell $not $not$libresoc.v:170977$11325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:167552$10927_Y + connect \Y $not$libresoc.v:170977$11325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167553$10928 + cell $not $not$libresoc.v:170978$11326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167553$10928_Y + connect \Y $not$libresoc.v:170978$11326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167554$10929 + cell $not $not$libresoc.v:170979$11327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:167554$10929_Y + connect \Y $not$libresoc.v:170979$11327_Y end - attribute \src "libresoc.v:167474.7-167474.20" - process $proc$libresoc.v:167474$11007 + attribute \src "libresoc.v:170899.7-170899.20" + process $proc$libresoc.v:170899$11405 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167499.13-167499.31" - process $proc$libresoc.v:167499$11008 + attribute \src "libresoc.v:170924.13-170924.31" + process $proc$libresoc.v:170924$11406 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:167506.13-167506.30" - process $proc$libresoc.v:167506$11009 + attribute \src "libresoc.v:170931.13-170931.30" + process $proc$libresoc.v:170931$11407 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:167512.13-167512.25" - process $proc$libresoc.v:167512$11010 + attribute \src "libresoc.v:170937.13-170937.25" + process $proc$libresoc.v:170937$11408 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:167517.13-167517.33" - process $proc$libresoc.v:167517$11011 + attribute \src "libresoc.v:170942.13-170942.33" + process $proc$libresoc.v:170942$11409 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:167524.13-167524.33" - process $proc$libresoc.v:167524$11012 + attribute \src "libresoc.v:170949.13-170949.33" + process $proc$libresoc.v:170949$11410 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:167531.13-167531.33" - process $proc$libresoc.v:167531$11013 + attribute \src "libresoc.v:170956.13-170956.33" + process $proc$libresoc.v:170956$11411 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:167555.3-167556.25" - process $proc$libresoc.v:167555$10930 + attribute \src "libresoc.v:170980.3-170981.25" + process $proc$libresoc.v:170980$11328 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:167557.3-167558.39" - process $proc$libresoc.v:167557$10931 + attribute \src "libresoc.v:170982.3-170983.39" + process $proc$libresoc.v:170982$11329 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:167559.3-167560.37" - process $proc$libresoc.v:167559$10932 + attribute \src "libresoc.v:170984.3-170985.37" + process $proc$libresoc.v:170984$11330 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:167561.3-167562.43" - process $proc$libresoc.v:167561$10933 + attribute \src "libresoc.v:170986.3-170987.43" + process $proc$libresoc.v:170986$11331 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:167563.3-167564.43" - process $proc$libresoc.v:167563$10934 + attribute \src "libresoc.v:170988.3-170989.43" + process $proc$libresoc.v:170988$11332 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:167565.3-167566.43" - process $proc$libresoc.v:167565$10935 + attribute \src "libresoc.v:170990.3-170991.43" + process $proc$libresoc.v:170990$11333 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:167567.3-167606.6" - process $proc$libresoc.v:167567$10936 + attribute \src "libresoc.v:170992.3-171031.6" + process $proc$libresoc.v:170992$11334 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$10937 $6\src14__data_o$next[3:0]$10943 - attribute \src "libresoc.v:167568.5-167568.29" + assign $0\src14__data_o$next[3:0]$11335 $6\src14__data_o$next[3:0]$11341 + attribute \src "libresoc.v:170993.5-170993.29" switch \initial - attribute \src "libresoc.v:167568.9-167568.17" + attribute \src "libresoc.v:170993.9-170993.17" case 1'1 case end @@ -346282,66 +354212,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$10938 $5\src14__data_o$next[3:0]$10942 + assign $1\src14__data_o$next[3:0]$11336 $5\src14__data_o$next[3:0]$11340 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$10939 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11337 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$10939 4'0000 + assign $2\src14__data_o$next[3:0]$11337 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$10940 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11338 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$10940 $2\src14__data_o$next[3:0]$10939 + assign $3\src14__data_o$next[3:0]$11338 $2\src14__data_o$next[3:0]$11337 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$10941 \w4__data_i + assign $4\src14__data_o$next[3:0]$11339 \w4__data_i case - assign $4\src14__data_o$next[3:0]$10941 $3\src14__data_o$next[3:0]$10940 + assign $4\src14__data_o$next[3:0]$11339 $3\src14__data_o$next[3:0]$11338 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$10942 \reg + assign $5\src14__data_o$next[3:0]$11340 \reg case - assign $5\src14__data_o$next[3:0]$10942 $4\src14__data_o$next[3:0]$10941 + assign $5\src14__data_o$next[3:0]$11340 $4\src14__data_o$next[3:0]$11339 end case - assign $1\src14__data_o$next[3:0]$10938 4'0000 + assign $1\src14__data_o$next[3:0]$11336 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$10943 4'0000 + assign $6\src14__data_o$next[3:0]$11341 4'0000 case - assign $6\src14__data_o$next[3:0]$10943 $1\src14__data_o$next[3:0]$10938 + assign $6\src14__data_o$next[3:0]$11341 $1\src14__data_o$next[3:0]$11336 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$10937 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11335 end - attribute \src "libresoc.v:167607.3-167636.6" - process $proc$libresoc.v:167607$10944 + attribute \src "libresoc.v:171032.3-171061.6" + process $proc$libresoc.v:171032$11342 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167608.5-167608.29" + attribute \src "libresoc.v:171033.5-171033.29" switch \initial - attribute \src "libresoc.v:167608.9-167608.17" + attribute \src "libresoc.v:171033.9-171033.17" case 1'1 case end @@ -346387,17 +354317,17 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:167637.3-167663.6" - process $proc$libresoc.v:167637$10945 + attribute \src "libresoc.v:171062.3-171088.6" + process $proc$libresoc.v:171062$11343 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10946 $4\reg$next[3:0]$10950 - attribute \src "libresoc.v:167638.5-167638.29" + assign $0\reg$next[3:0]$11344 $4\reg$next[3:0]$11348 + attribute \src "libresoc.v:171063.5-171063.29" switch \initial - attribute \src "libresoc.v:167638.9-167638.17" + attribute \src "libresoc.v:171063.9-171063.17" case 1'1 case end @@ -346406,49 +354336,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10947 \dest14__data_i + assign $1\reg$next[3:0]$11345 \dest14__data_i case - assign $1\reg$next[3:0]$10947 \reg + assign $1\reg$next[3:0]$11345 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10948 \dest24__data_i + assign $2\reg$next[3:0]$11346 \dest24__data_i case - assign $2\reg$next[3:0]$10948 $1\reg$next[3:0]$10947 + assign $2\reg$next[3:0]$11346 $1\reg$next[3:0]$11345 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10949 \w4__data_i + assign $3\reg$next[3:0]$11347 \w4__data_i case - assign $3\reg$next[3:0]$10949 $2\reg$next[3:0]$10948 + assign $3\reg$next[3:0]$11347 $2\reg$next[3:0]$11346 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10950 4'0000 + assign $4\reg$next[3:0]$11348 4'0000 case - assign $4\reg$next[3:0]$10950 $3\reg$next[3:0]$10949 + assign $4\reg$next[3:0]$11348 $3\reg$next[3:0]$11347 end sync always - update \reg$next $0\reg$next[3:0]$10946 + update \reg$next $0\reg$next[3:0]$11344 end - attribute \src "libresoc.v:167664.3-167703.6" - process $proc$libresoc.v:167664$10951 + attribute \src "libresoc.v:171089.3-171128.6" + process $proc$libresoc.v:171089$11349 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$10952 $6\src24__data_o$next[3:0]$10958 - attribute \src "libresoc.v:167665.5-167665.29" + assign $0\src24__data_o$next[3:0]$11350 $6\src24__data_o$next[3:0]$11356 + attribute \src "libresoc.v:171090.5-171090.29" switch \initial - attribute \src "libresoc.v:167665.9-167665.17" + attribute \src "libresoc.v:171090.9-171090.17" case 1'1 case end @@ -346460,66 +354390,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$10953 $5\src24__data_o$next[3:0]$10957 + assign $1\src24__data_o$next[3:0]$11351 $5\src24__data_o$next[3:0]$11355 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$10954 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11352 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$10954 4'0000 + assign $2\src24__data_o$next[3:0]$11352 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$10955 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11353 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$10955 $2\src24__data_o$next[3:0]$10954 + assign $3\src24__data_o$next[3:0]$11353 $2\src24__data_o$next[3:0]$11352 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$10956 \w4__data_i + assign $4\src24__data_o$next[3:0]$11354 \w4__data_i case - assign $4\src24__data_o$next[3:0]$10956 $3\src24__data_o$next[3:0]$10955 + assign $4\src24__data_o$next[3:0]$11354 $3\src24__data_o$next[3:0]$11353 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$10957 \reg + assign $5\src24__data_o$next[3:0]$11355 \reg case - assign $5\src24__data_o$next[3:0]$10957 $4\src24__data_o$next[3:0]$10956 + assign $5\src24__data_o$next[3:0]$11355 $4\src24__data_o$next[3:0]$11354 end case - assign $1\src24__data_o$next[3:0]$10953 4'0000 + assign $1\src24__data_o$next[3:0]$11351 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$10958 4'0000 + assign $6\src24__data_o$next[3:0]$11356 4'0000 case - assign $6\src24__data_o$next[3:0]$10958 $1\src24__data_o$next[3:0]$10953 + assign $6\src24__data_o$next[3:0]$11356 $1\src24__data_o$next[3:0]$11351 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$10952 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11350 end - attribute \src "libresoc.v:167704.3-167733.6" - process $proc$libresoc.v:167704$10959 + attribute \src "libresoc.v:171129.3-171158.6" + process $proc$libresoc.v:171129$11357 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10960 $1\wr_detect$4[0:0]$10961 - attribute \src "libresoc.v:167705.5-167705.29" + assign $0\wr_detect$4[0:0]$11358 $1\wr_detect$4[0:0]$11359 + attribute \src "libresoc.v:171130.5-171130.29" switch \initial - attribute \src "libresoc.v:167705.9-167705.17" + attribute \src "libresoc.v:171130.9-171130.17" case 1'1 case end @@ -346531,49 +354461,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10961 $4\wr_detect$4[0:0]$10964 + assign $1\wr_detect$4[0:0]$11359 $4\wr_detect$4[0:0]$11362 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10962 1'1 + assign $2\wr_detect$4[0:0]$11360 1'1 case - assign $2\wr_detect$4[0:0]$10962 1'0 + assign $2\wr_detect$4[0:0]$11360 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10963 1'1 + assign $3\wr_detect$4[0:0]$11361 1'1 case - assign $3\wr_detect$4[0:0]$10963 $2\wr_detect$4[0:0]$10962 + assign $3\wr_detect$4[0:0]$11361 $2\wr_detect$4[0:0]$11360 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10964 1'1 + assign $4\wr_detect$4[0:0]$11362 1'1 case - assign $4\wr_detect$4[0:0]$10964 $3\wr_detect$4[0:0]$10963 + assign $4\wr_detect$4[0:0]$11362 $3\wr_detect$4[0:0]$11361 end case - assign $1\wr_detect$4[0:0]$10961 1'0 + assign $1\wr_detect$4[0:0]$11359 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10960 + update \wr_detect$4 $0\wr_detect$4[0:0]$11358 end - attribute \src "libresoc.v:167734.3-167773.6" - process $proc$libresoc.v:167734$10965 + attribute \src "libresoc.v:171159.3-171198.6" + process $proc$libresoc.v:171159$11363 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$10966 $6\src34__data_o$next[3:0]$10972 - attribute \src "libresoc.v:167735.5-167735.29" + assign $0\src34__data_o$next[3:0]$11364 $6\src34__data_o$next[3:0]$11370 + attribute \src "libresoc.v:171160.5-171160.29" switch \initial - attribute \src "libresoc.v:167735.9-167735.17" + attribute \src "libresoc.v:171160.9-171160.17" case 1'1 case end @@ -346585,66 +354515,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$10967 $5\src34__data_o$next[3:0]$10971 + assign $1\src34__data_o$next[3:0]$11365 $5\src34__data_o$next[3:0]$11369 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$10968 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11366 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$10968 4'0000 + assign $2\src34__data_o$next[3:0]$11366 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$10969 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11367 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$10969 $2\src34__data_o$next[3:0]$10968 + assign $3\src34__data_o$next[3:0]$11367 $2\src34__data_o$next[3:0]$11366 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$10970 \w4__data_i + assign $4\src34__data_o$next[3:0]$11368 \w4__data_i case - assign $4\src34__data_o$next[3:0]$10970 $3\src34__data_o$next[3:0]$10969 + assign $4\src34__data_o$next[3:0]$11368 $3\src34__data_o$next[3:0]$11367 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$10971 \reg + assign $5\src34__data_o$next[3:0]$11369 \reg case - assign $5\src34__data_o$next[3:0]$10971 $4\src34__data_o$next[3:0]$10970 + assign $5\src34__data_o$next[3:0]$11369 $4\src34__data_o$next[3:0]$11368 end case - assign $1\src34__data_o$next[3:0]$10967 4'0000 + assign $1\src34__data_o$next[3:0]$11365 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$10972 4'0000 + assign $6\src34__data_o$next[3:0]$11370 4'0000 case - assign $6\src34__data_o$next[3:0]$10972 $1\src34__data_o$next[3:0]$10967 + assign $6\src34__data_o$next[3:0]$11370 $1\src34__data_o$next[3:0]$11365 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$10966 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11364 end - attribute \src "libresoc.v:167774.3-167803.6" - process $proc$libresoc.v:167774$10973 + attribute \src "libresoc.v:171199.3-171228.6" + process $proc$libresoc.v:171199$11371 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10974 $1\wr_detect$7[0:0]$10975 - attribute \src "libresoc.v:167775.5-167775.29" + assign $0\wr_detect$7[0:0]$11372 $1\wr_detect$7[0:0]$11373 + attribute \src "libresoc.v:171200.5-171200.29" switch \initial - attribute \src "libresoc.v:167775.9-167775.17" + attribute \src "libresoc.v:171200.9-171200.17" case 1'1 case end @@ -346656,49 +354586,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10975 $4\wr_detect$7[0:0]$10978 + assign $1\wr_detect$7[0:0]$11373 $4\wr_detect$7[0:0]$11376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10976 1'1 + assign $2\wr_detect$7[0:0]$11374 1'1 case - assign $2\wr_detect$7[0:0]$10976 1'0 + assign $2\wr_detect$7[0:0]$11374 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10977 1'1 + assign $3\wr_detect$7[0:0]$11375 1'1 case - assign $3\wr_detect$7[0:0]$10977 $2\wr_detect$7[0:0]$10976 + assign $3\wr_detect$7[0:0]$11375 $2\wr_detect$7[0:0]$11374 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10978 1'1 + assign $4\wr_detect$7[0:0]$11376 1'1 case - assign $4\wr_detect$7[0:0]$10978 $3\wr_detect$7[0:0]$10977 + assign $4\wr_detect$7[0:0]$11376 $3\wr_detect$7[0:0]$11375 end case - assign $1\wr_detect$7[0:0]$10975 1'0 + assign $1\wr_detect$7[0:0]$11373 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10974 + update \wr_detect$7 $0\wr_detect$7[0:0]$11372 end - attribute \src "libresoc.v:167804.3-167843.6" - process $proc$libresoc.v:167804$10979 + attribute \src "libresoc.v:171229.3-171268.6" + process $proc$libresoc.v:171229$11377 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$10980 $6\r4__data_o$next[3:0]$10986 - attribute \src "libresoc.v:167805.5-167805.29" + assign $0\r4__data_o$next[3:0]$11378 $6\r4__data_o$next[3:0]$11384 + attribute \src "libresoc.v:171230.5-171230.29" switch \initial - attribute \src "libresoc.v:167805.9-167805.17" + attribute \src "libresoc.v:171230.9-171230.17" case 1'1 case end @@ -346710,66 +354640,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$10981 $5\r4__data_o$next[3:0]$10985 + assign $1\r4__data_o$next[3:0]$11379 $5\r4__data_o$next[3:0]$11383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$10982 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11380 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$10982 4'0000 + assign $2\r4__data_o$next[3:0]$11380 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$10983 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11381 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$10983 $2\r4__data_o$next[3:0]$10982 + assign $3\r4__data_o$next[3:0]$11381 $2\r4__data_o$next[3:0]$11380 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$10984 \w4__data_i + assign $4\r4__data_o$next[3:0]$11382 \w4__data_i case - assign $4\r4__data_o$next[3:0]$10984 $3\r4__data_o$next[3:0]$10983 + assign $4\r4__data_o$next[3:0]$11382 $3\r4__data_o$next[3:0]$11381 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$10985 \reg + assign $5\r4__data_o$next[3:0]$11383 \reg case - assign $5\r4__data_o$next[3:0]$10985 $4\r4__data_o$next[3:0]$10984 + assign $5\r4__data_o$next[3:0]$11383 $4\r4__data_o$next[3:0]$11382 end case - assign $1\r4__data_o$next[3:0]$10981 4'0000 + assign $1\r4__data_o$next[3:0]$11379 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$10986 4'0000 + assign $6\r4__data_o$next[3:0]$11384 4'0000 case - assign $6\r4__data_o$next[3:0]$10986 $1\r4__data_o$next[3:0]$10981 + assign $6\r4__data_o$next[3:0]$11384 $1\r4__data_o$next[3:0]$11379 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$10980 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11378 end - attribute \src "libresoc.v:167844.3-167873.6" - process $proc$libresoc.v:167844$10987 + attribute \src "libresoc.v:171269.3-171298.6" + process $proc$libresoc.v:171269$11385 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10988 $1\wr_detect$10[0:0]$10989 - attribute \src "libresoc.v:167845.5-167845.29" + assign $0\wr_detect$10[0:0]$11386 $1\wr_detect$10[0:0]$11387 + attribute \src "libresoc.v:171270.5-171270.29" switch \initial - attribute \src "libresoc.v:167845.9-167845.17" + attribute \src "libresoc.v:171270.9-171270.17" case 1'1 case end @@ -346781,49 +354711,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10989 $4\wr_detect$10[0:0]$10992 + assign $1\wr_detect$10[0:0]$11387 $4\wr_detect$10[0:0]$11390 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10990 1'1 + assign $2\wr_detect$10[0:0]$11388 1'1 case - assign $2\wr_detect$10[0:0]$10990 1'0 + assign $2\wr_detect$10[0:0]$11388 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10991 1'1 + assign $3\wr_detect$10[0:0]$11389 1'1 case - assign $3\wr_detect$10[0:0]$10991 $2\wr_detect$10[0:0]$10990 + assign $3\wr_detect$10[0:0]$11389 $2\wr_detect$10[0:0]$11388 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10992 1'1 + assign $4\wr_detect$10[0:0]$11390 1'1 case - assign $4\wr_detect$10[0:0]$10992 $3\wr_detect$10[0:0]$10991 + assign $4\wr_detect$10[0:0]$11390 $3\wr_detect$10[0:0]$11389 end case - assign $1\wr_detect$10[0:0]$10989 1'0 + assign $1\wr_detect$10[0:0]$11387 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10988 + update \wr_detect$10 $0\wr_detect$10[0:0]$11386 end - attribute \src "libresoc.v:167874.3-167913.6" - process $proc$libresoc.v:167874$10993 + attribute \src "libresoc.v:171299.3-171338.6" + process $proc$libresoc.v:171299$11391 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$10994 $6\r24__data_o$next[3:0]$11000 - attribute \src "libresoc.v:167875.5-167875.29" + assign $0\r24__data_o$next[3:0]$11392 $6\r24__data_o$next[3:0]$11398 + attribute \src "libresoc.v:171300.5-171300.29" switch \initial - attribute \src "libresoc.v:167875.9-167875.17" + attribute \src "libresoc.v:171300.9-171300.17" case 1'1 case end @@ -346835,66 +354765,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$10995 $5\r24__data_o$next[3:0]$10999 + assign $1\r24__data_o$next[3:0]$11393 $5\r24__data_o$next[3:0]$11397 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$10996 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11394 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$10996 4'0000 + assign $2\r24__data_o$next[3:0]$11394 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$10997 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11395 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$10997 $2\r24__data_o$next[3:0]$10996 + assign $3\r24__data_o$next[3:0]$11395 $2\r24__data_o$next[3:0]$11394 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$10998 \w4__data_i + assign $4\r24__data_o$next[3:0]$11396 \w4__data_i case - assign $4\r24__data_o$next[3:0]$10998 $3\r24__data_o$next[3:0]$10997 + assign $4\r24__data_o$next[3:0]$11396 $3\r24__data_o$next[3:0]$11395 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$10999 \reg + assign $5\r24__data_o$next[3:0]$11397 \reg case - assign $5\r24__data_o$next[3:0]$10999 $4\r24__data_o$next[3:0]$10998 + assign $5\r24__data_o$next[3:0]$11397 $4\r24__data_o$next[3:0]$11396 end case - assign $1\r24__data_o$next[3:0]$10995 4'0000 + assign $1\r24__data_o$next[3:0]$11393 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11000 4'0000 + assign $6\r24__data_o$next[3:0]$11398 4'0000 case - assign $6\r24__data_o$next[3:0]$11000 $1\r24__data_o$next[3:0]$10995 + assign $6\r24__data_o$next[3:0]$11398 $1\r24__data_o$next[3:0]$11393 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$10994 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11392 end - attribute \src "libresoc.v:167914.3-167943.6" - process $proc$libresoc.v:167914$11001 + attribute \src "libresoc.v:171339.3-171368.6" + process $proc$libresoc.v:171339$11399 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11002 $1\wr_detect$13[0:0]$11003 - attribute \src "libresoc.v:167915.5-167915.29" + assign $0\wr_detect$13[0:0]$11400 $1\wr_detect$13[0:0]$11401 + attribute \src "libresoc.v:171340.5-171340.29" switch \initial - attribute \src "libresoc.v:167915.9-167915.17" + attribute \src "libresoc.v:171340.9-171340.17" case 1'1 case end @@ -346906,217 +354836,217 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11003 $4\wr_detect$13[0:0]$11006 + assign $1\wr_detect$13[0:0]$11401 $4\wr_detect$13[0:0]$11404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11004 1'1 + assign $2\wr_detect$13[0:0]$11402 1'1 case - assign $2\wr_detect$13[0:0]$11004 1'0 + assign $2\wr_detect$13[0:0]$11402 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11005 1'1 + assign $3\wr_detect$13[0:0]$11403 1'1 case - assign $3\wr_detect$13[0:0]$11005 $2\wr_detect$13[0:0]$11004 + assign $3\wr_detect$13[0:0]$11403 $2\wr_detect$13[0:0]$11402 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11006 1'1 + assign $4\wr_detect$13[0:0]$11404 1'1 case - assign $4\wr_detect$13[0:0]$11006 $3\wr_detect$13[0:0]$11005 + assign $4\wr_detect$13[0:0]$11404 $3\wr_detect$13[0:0]$11403 end case - assign $1\wr_detect$13[0:0]$11003 1'0 + assign $1\wr_detect$13[0:0]$11401 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11002 + update \wr_detect$13 $0\wr_detect$13[0:0]$11400 end - connect \$9 $not$libresoc.v:167550$10925_Y - connect \$12 $not$libresoc.v:167551$10926_Y - connect \$1 $not$libresoc.v:167552$10927_Y - connect \$3 $not$libresoc.v:167553$10928_Y - connect \$6 $not$libresoc.v:167554$10929_Y + connect \$9 $not$libresoc.v:170975$11323_Y + connect \$12 $not$libresoc.v:170976$11324_Y + connect \$1 $not$libresoc.v:170977$11325_Y + connect \$3 $not$libresoc.v:170978$11326_Y + connect \$6 $not$libresoc.v:170979$11327_Y end -attribute \src "libresoc.v:167948.1-168419.10" +attribute \src "libresoc.v:171373.1-171844.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:167949.7-167949.20" + attribute \src "libresoc.v:171374.7-171374.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $0\r25__data_o$next[3:0]$11083 - attribute \src "libresoc.v:168032.3-168033.39" + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $0\r25__data_o$next[3:0]$11481 + attribute \src "libresoc.v:171457.3-171458.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $0\r5__data_o$next[3:0]$11069 - attribute \src "libresoc.v:168034.3-168035.37" + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $0\r5__data_o$next[3:0]$11467 + attribute \src "libresoc.v:171459.3-171460.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:168112.3-168138.6" - wire width 4 $0\reg$next[3:0]$11035 - attribute \src "libresoc.v:168030.3-168031.25" + attribute \src "libresoc.v:171537.3-171563.6" + wire width 4 $0\reg$next[3:0]$11433 + attribute \src "libresoc.v:171455.3-171456.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $0\src15__data_o$next[3:0]$11026 - attribute \src "libresoc.v:168040.3-168041.43" + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $0\src15__data_o$next[3:0]$11424 + attribute \src "libresoc.v:171465.3-171466.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $0\src25__data_o$next[3:0]$11041 - attribute \src "libresoc.v:168038.3-168039.43" + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $0\src25__data_o$next[3:0]$11439 + attribute \src "libresoc.v:171463.3-171464.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $0\src35__data_o$next[3:0]$11055 - attribute \src "libresoc.v:168036.3-168037.43" + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $0\src35__data_o$next[3:0]$11453 + attribute \src "libresoc.v:171461.3-171462.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:168319.3-168348.6" - wire $0\wr_detect$10[0:0]$11077 - attribute \src "libresoc.v:168389.3-168418.6" - wire $0\wr_detect$13[0:0]$11091 - attribute \src "libresoc.v:168179.3-168208.6" - wire $0\wr_detect$4[0:0]$11049 - attribute \src "libresoc.v:168249.3-168278.6" - wire $0\wr_detect$7[0:0]$11063 - attribute \src "libresoc.v:168082.3-168111.6" + attribute \src "libresoc.v:171744.3-171773.6" + wire $0\wr_detect$10[0:0]$11475 + attribute \src "libresoc.v:171814.3-171843.6" + wire $0\wr_detect$13[0:0]$11489 + attribute \src "libresoc.v:171604.3-171633.6" + wire $0\wr_detect$4[0:0]$11447 + attribute \src "libresoc.v:171674.3-171703.6" + wire $0\wr_detect$7[0:0]$11461 + attribute \src "libresoc.v:171507.3-171536.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $1\r25__data_o$next[3:0]$11084 - attribute \src "libresoc.v:167974.13-167974.31" + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $1\r25__data_o$next[3:0]$11482 + attribute \src "libresoc.v:171399.13-171399.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $1\r5__data_o$next[3:0]$11070 - attribute \src "libresoc.v:167981.13-167981.30" + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $1\r5__data_o$next[3:0]$11468 + attribute \src "libresoc.v:171406.13-171406.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:168112.3-168138.6" - wire width 4 $1\reg$next[3:0]$11036 - attribute \src "libresoc.v:167987.13-167987.25" + attribute \src "libresoc.v:171537.3-171563.6" + wire width 4 $1\reg$next[3:0]$11434 + attribute \src "libresoc.v:171412.13-171412.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $1\src15__data_o$next[3:0]$11027 - attribute \src "libresoc.v:167992.13-167992.33" + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $1\src15__data_o$next[3:0]$11425 + attribute \src "libresoc.v:171417.13-171417.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $1\src25__data_o$next[3:0]$11042 - attribute \src "libresoc.v:167999.13-167999.33" + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $1\src25__data_o$next[3:0]$11440 + attribute \src "libresoc.v:171424.13-171424.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $1\src35__data_o$next[3:0]$11056 - attribute \src "libresoc.v:168006.13-168006.33" + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $1\src35__data_o$next[3:0]$11454 + attribute \src "libresoc.v:171431.13-171431.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:168319.3-168348.6" - wire $1\wr_detect$10[0:0]$11078 - attribute \src "libresoc.v:168389.3-168418.6" - wire $1\wr_detect$13[0:0]$11092 - attribute \src "libresoc.v:168179.3-168208.6" - wire $1\wr_detect$4[0:0]$11050 - attribute \src "libresoc.v:168249.3-168278.6" - wire $1\wr_detect$7[0:0]$11064 - attribute \src "libresoc.v:168082.3-168111.6" + attribute \src "libresoc.v:171744.3-171773.6" + wire $1\wr_detect$10[0:0]$11476 + attribute \src "libresoc.v:171814.3-171843.6" + wire $1\wr_detect$13[0:0]$11490 + attribute \src "libresoc.v:171604.3-171633.6" + wire $1\wr_detect$4[0:0]$11448 + attribute \src "libresoc.v:171674.3-171703.6" + wire $1\wr_detect$7[0:0]$11462 + attribute \src "libresoc.v:171507.3-171536.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $2\r25__data_o$next[3:0]$11085 - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $2\r5__data_o$next[3:0]$11071 - attribute \src "libresoc.v:168112.3-168138.6" - wire width 4 $2\reg$next[3:0]$11037 - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $2\src15__data_o$next[3:0]$11028 - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $2\src25__data_o$next[3:0]$11043 - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $2\src35__data_o$next[3:0]$11057 - attribute \src "libresoc.v:168319.3-168348.6" - wire $2\wr_detect$10[0:0]$11079 - attribute \src "libresoc.v:168389.3-168418.6" - wire $2\wr_detect$13[0:0]$11093 - attribute \src "libresoc.v:168179.3-168208.6" - wire $2\wr_detect$4[0:0]$11051 - attribute \src "libresoc.v:168249.3-168278.6" - wire $2\wr_detect$7[0:0]$11065 - attribute \src "libresoc.v:168082.3-168111.6" + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $2\r25__data_o$next[3:0]$11483 + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $2\r5__data_o$next[3:0]$11469 + attribute \src "libresoc.v:171537.3-171563.6" + wire width 4 $2\reg$next[3:0]$11435 + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $2\src15__data_o$next[3:0]$11426 + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $2\src25__data_o$next[3:0]$11441 + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $2\src35__data_o$next[3:0]$11455 + attribute \src "libresoc.v:171744.3-171773.6" + wire $2\wr_detect$10[0:0]$11477 + attribute \src "libresoc.v:171814.3-171843.6" + wire $2\wr_detect$13[0:0]$11491 + attribute \src "libresoc.v:171604.3-171633.6" + wire $2\wr_detect$4[0:0]$11449 + attribute \src "libresoc.v:171674.3-171703.6" + wire $2\wr_detect$7[0:0]$11463 + attribute \src "libresoc.v:171507.3-171536.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $3\r25__data_o$next[3:0]$11086 - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $3\r5__data_o$next[3:0]$11072 - attribute \src "libresoc.v:168112.3-168138.6" - wire width 4 $3\reg$next[3:0]$11038 - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $3\src15__data_o$next[3:0]$11029 - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $3\src25__data_o$next[3:0]$11044 - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $3\src35__data_o$next[3:0]$11058 - attribute \src "libresoc.v:168319.3-168348.6" - wire $3\wr_detect$10[0:0]$11080 - attribute \src "libresoc.v:168389.3-168418.6" - wire $3\wr_detect$13[0:0]$11094 - attribute \src "libresoc.v:168179.3-168208.6" - wire $3\wr_detect$4[0:0]$11052 - attribute \src "libresoc.v:168249.3-168278.6" - wire $3\wr_detect$7[0:0]$11066 - attribute \src "libresoc.v:168082.3-168111.6" + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $3\r25__data_o$next[3:0]$11484 + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $3\r5__data_o$next[3:0]$11470 + attribute \src "libresoc.v:171537.3-171563.6" + wire width 4 $3\reg$next[3:0]$11436 + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $3\src15__data_o$next[3:0]$11427 + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $3\src25__data_o$next[3:0]$11442 + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $3\src35__data_o$next[3:0]$11456 + attribute \src "libresoc.v:171744.3-171773.6" + wire $3\wr_detect$10[0:0]$11478 + attribute \src "libresoc.v:171814.3-171843.6" + wire $3\wr_detect$13[0:0]$11492 + attribute \src "libresoc.v:171604.3-171633.6" + wire $3\wr_detect$4[0:0]$11450 + attribute \src "libresoc.v:171674.3-171703.6" + wire $3\wr_detect$7[0:0]$11464 + attribute \src "libresoc.v:171507.3-171536.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $4\r25__data_o$next[3:0]$11087 - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $4\r5__data_o$next[3:0]$11073 - attribute \src "libresoc.v:168112.3-168138.6" - wire width 4 $4\reg$next[3:0]$11039 - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $4\src15__data_o$next[3:0]$11030 - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $4\src25__data_o$next[3:0]$11045 - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $4\src35__data_o$next[3:0]$11059 - attribute \src "libresoc.v:168319.3-168348.6" - wire $4\wr_detect$10[0:0]$11081 - attribute \src "libresoc.v:168389.3-168418.6" - wire $4\wr_detect$13[0:0]$11095 - attribute \src "libresoc.v:168179.3-168208.6" - wire $4\wr_detect$4[0:0]$11053 - attribute \src "libresoc.v:168249.3-168278.6" - wire $4\wr_detect$7[0:0]$11067 - attribute \src "libresoc.v:168082.3-168111.6" + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $4\r25__data_o$next[3:0]$11485 + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $4\r5__data_o$next[3:0]$11471 + attribute \src "libresoc.v:171537.3-171563.6" + wire width 4 $4\reg$next[3:0]$11437 + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $4\src15__data_o$next[3:0]$11428 + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $4\src25__data_o$next[3:0]$11443 + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $4\src35__data_o$next[3:0]$11457 + attribute \src "libresoc.v:171744.3-171773.6" + wire $4\wr_detect$10[0:0]$11479 + attribute \src "libresoc.v:171814.3-171843.6" + wire $4\wr_detect$13[0:0]$11493 + attribute \src "libresoc.v:171604.3-171633.6" + wire $4\wr_detect$4[0:0]$11451 + attribute \src "libresoc.v:171674.3-171703.6" + wire $4\wr_detect$7[0:0]$11465 + attribute \src "libresoc.v:171507.3-171536.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $5\r25__data_o$next[3:0]$11088 - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $5\r5__data_o$next[3:0]$11074 - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $5\src15__data_o$next[3:0]$11031 - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $5\src25__data_o$next[3:0]$11046 - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $5\src35__data_o$next[3:0]$11060 - attribute \src "libresoc.v:168349.3-168388.6" - wire width 4 $6\r25__data_o$next[3:0]$11089 - attribute \src "libresoc.v:168279.3-168318.6" - wire width 4 $6\r5__data_o$next[3:0]$11075 - attribute \src "libresoc.v:168042.3-168081.6" - wire width 4 $6\src15__data_o$next[3:0]$11032 - attribute \src "libresoc.v:168139.3-168178.6" - wire width 4 $6\src25__data_o$next[3:0]$11047 - attribute \src "libresoc.v:168209.3-168248.6" - wire width 4 $6\src35__data_o$next[3:0]$11061 - attribute \src "libresoc.v:168025.17-168025.104" - wire $not$libresoc.v:168025$11014_Y - attribute \src "libresoc.v:168026.18-168026.105" - wire $not$libresoc.v:168026$11015_Y - attribute \src "libresoc.v:168027.17-168027.100" - wire $not$libresoc.v:168027$11016_Y - attribute \src "libresoc.v:168028.17-168028.103" - wire $not$libresoc.v:168028$11017_Y - attribute \src "libresoc.v:168029.17-168029.103" - wire $not$libresoc.v:168029$11018_Y + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $5\r25__data_o$next[3:0]$11486 + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $5\r5__data_o$next[3:0]$11472 + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $5\src15__data_o$next[3:0]$11429 + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $5\src25__data_o$next[3:0]$11444 + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $5\src35__data_o$next[3:0]$11458 + attribute \src "libresoc.v:171774.3-171813.6" + wire width 4 $6\r25__data_o$next[3:0]$11487 + attribute \src "libresoc.v:171704.3-171743.6" + wire width 4 $6\r5__data_o$next[3:0]$11473 + attribute \src "libresoc.v:171467.3-171506.6" + wire width 4 $6\src15__data_o$next[3:0]$11430 + attribute \src "libresoc.v:171564.3-171603.6" + wire width 4 $6\src25__data_o$next[3:0]$11445 + attribute \src "libresoc.v:171634.3-171673.6" + wire width 4 $6\src35__data_o$next[3:0]$11459 + attribute \src "libresoc.v:171450.17-171450.104" + wire $not$libresoc.v:171450$11412_Y + attribute \src "libresoc.v:171451.18-171451.105" + wire $not$libresoc.v:171451$11413_Y + attribute \src "libresoc.v:171452.17-171452.100" + wire $not$libresoc.v:171452$11414_Y + attribute \src "libresoc.v:171453.17-171453.103" + wire $not$libresoc.v:171453$11415_Y + attribute \src "libresoc.v:171454.17-171454.103" + wire $not$libresoc.v:171454$11416_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -347127,9 +355057,9 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest15__data_i @@ -347139,7 +355069,7 @@ module \reg_5 wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest25__wen - attribute \src "libresoc.v:167949.7-167949.15" + attribute \src "libresoc.v:171374.7-171374.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r25__data_o @@ -347190,152 +355120,152 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168025$11014 + cell $not $not$libresoc.v:171450$11412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168025$11014_Y + connect \Y $not$libresoc.v:171450$11412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168026$11015 + cell $not $not$libresoc.v:171451$11413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:168026$11015_Y + connect \Y $not$libresoc.v:171451$11413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168027$11016 + cell $not $not$libresoc.v:171452$11414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168027$11016_Y + connect \Y $not$libresoc.v:171452$11414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168028$11017 + cell $not $not$libresoc.v:171453$11415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168028$11017_Y + connect \Y $not$libresoc.v:171453$11415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168029$11018 + cell $not $not$libresoc.v:171454$11416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168029$11018_Y + connect \Y $not$libresoc.v:171454$11416_Y end - attribute \src "libresoc.v:167949.7-167949.20" - process $proc$libresoc.v:167949$11096 + attribute \src "libresoc.v:171374.7-171374.20" + process $proc$libresoc.v:171374$11494 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167974.13-167974.31" - process $proc$libresoc.v:167974$11097 + attribute \src "libresoc.v:171399.13-171399.31" + process $proc$libresoc.v:171399$11495 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:167981.13-167981.30" - process $proc$libresoc.v:167981$11098 + attribute \src "libresoc.v:171406.13-171406.30" + process $proc$libresoc.v:171406$11496 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:167987.13-167987.25" - process $proc$libresoc.v:167987$11099 + attribute \src "libresoc.v:171412.13-171412.25" + process $proc$libresoc.v:171412$11497 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:167992.13-167992.33" - process $proc$libresoc.v:167992$11100 + attribute \src "libresoc.v:171417.13-171417.33" + process $proc$libresoc.v:171417$11498 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:167999.13-167999.33" - process $proc$libresoc.v:167999$11101 + attribute \src "libresoc.v:171424.13-171424.33" + process $proc$libresoc.v:171424$11499 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:168006.13-168006.33" - process $proc$libresoc.v:168006$11102 + attribute \src "libresoc.v:171431.13-171431.33" + process $proc$libresoc.v:171431$11500 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:168030.3-168031.25" - process $proc$libresoc.v:168030$11019 + attribute \src "libresoc.v:171455.3-171456.25" + process $proc$libresoc.v:171455$11417 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:168032.3-168033.39" - process $proc$libresoc.v:168032$11020 + attribute \src "libresoc.v:171457.3-171458.39" + process $proc$libresoc.v:171457$11418 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:168034.3-168035.37" - process $proc$libresoc.v:168034$11021 + attribute \src "libresoc.v:171459.3-171460.37" + process $proc$libresoc.v:171459$11419 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:168036.3-168037.43" - process $proc$libresoc.v:168036$11022 + attribute \src "libresoc.v:171461.3-171462.43" + process $proc$libresoc.v:171461$11420 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:168038.3-168039.43" - process $proc$libresoc.v:168038$11023 + attribute \src "libresoc.v:171463.3-171464.43" + process $proc$libresoc.v:171463$11421 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:168040.3-168041.43" - process $proc$libresoc.v:168040$11024 + attribute \src "libresoc.v:171465.3-171466.43" + process $proc$libresoc.v:171465$11422 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:168042.3-168081.6" - process $proc$libresoc.v:168042$11025 + attribute \src "libresoc.v:171467.3-171506.6" + process $proc$libresoc.v:171467$11423 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11026 $6\src15__data_o$next[3:0]$11032 - attribute \src "libresoc.v:168043.5-168043.29" + assign $0\src15__data_o$next[3:0]$11424 $6\src15__data_o$next[3:0]$11430 + attribute \src "libresoc.v:171468.5-171468.29" switch \initial - attribute \src "libresoc.v:168043.9-168043.17" + attribute \src "libresoc.v:171468.9-171468.17" case 1'1 case end @@ -347347,66 +355277,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11027 $5\src15__data_o$next[3:0]$11031 + assign $1\src15__data_o$next[3:0]$11425 $5\src15__data_o$next[3:0]$11429 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11028 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11426 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11028 4'0000 + assign $2\src15__data_o$next[3:0]$11426 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11029 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11427 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11029 $2\src15__data_o$next[3:0]$11028 + assign $3\src15__data_o$next[3:0]$11427 $2\src15__data_o$next[3:0]$11426 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11030 \w5__data_i + assign $4\src15__data_o$next[3:0]$11428 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11030 $3\src15__data_o$next[3:0]$11029 + assign $4\src15__data_o$next[3:0]$11428 $3\src15__data_o$next[3:0]$11427 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11031 \reg + assign $5\src15__data_o$next[3:0]$11429 \reg case - assign $5\src15__data_o$next[3:0]$11031 $4\src15__data_o$next[3:0]$11030 + assign $5\src15__data_o$next[3:0]$11429 $4\src15__data_o$next[3:0]$11428 end case - assign $1\src15__data_o$next[3:0]$11027 4'0000 + assign $1\src15__data_o$next[3:0]$11425 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11032 4'0000 + assign $6\src15__data_o$next[3:0]$11430 4'0000 case - assign $6\src15__data_o$next[3:0]$11032 $1\src15__data_o$next[3:0]$11027 + assign $6\src15__data_o$next[3:0]$11430 $1\src15__data_o$next[3:0]$11425 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11026 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11424 end - attribute \src "libresoc.v:168082.3-168111.6" - process $proc$libresoc.v:168082$11033 + attribute \src "libresoc.v:171507.3-171536.6" + process $proc$libresoc.v:171507$11431 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168083.5-168083.29" + attribute \src "libresoc.v:171508.5-171508.29" switch \initial - attribute \src "libresoc.v:168083.9-168083.17" + attribute \src "libresoc.v:171508.9-171508.17" case 1'1 case end @@ -347452,17 +355382,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:168112.3-168138.6" - process $proc$libresoc.v:168112$11034 + attribute \src "libresoc.v:171537.3-171563.6" + process $proc$libresoc.v:171537$11432 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11035 $4\reg$next[3:0]$11039 - attribute \src "libresoc.v:168113.5-168113.29" + assign $0\reg$next[3:0]$11433 $4\reg$next[3:0]$11437 + attribute \src "libresoc.v:171538.5-171538.29" switch \initial - attribute \src "libresoc.v:168113.9-168113.17" + attribute \src "libresoc.v:171538.9-171538.17" case 1'1 case end @@ -347471,49 +355401,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11036 \dest15__data_i + assign $1\reg$next[3:0]$11434 \dest15__data_i case - assign $1\reg$next[3:0]$11036 \reg + assign $1\reg$next[3:0]$11434 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11037 \dest25__data_i + assign $2\reg$next[3:0]$11435 \dest25__data_i case - assign $2\reg$next[3:0]$11037 $1\reg$next[3:0]$11036 + assign $2\reg$next[3:0]$11435 $1\reg$next[3:0]$11434 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11038 \w5__data_i + assign $3\reg$next[3:0]$11436 \w5__data_i case - assign $3\reg$next[3:0]$11038 $2\reg$next[3:0]$11037 + assign $3\reg$next[3:0]$11436 $2\reg$next[3:0]$11435 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11039 4'0000 + assign $4\reg$next[3:0]$11437 4'0000 case - assign $4\reg$next[3:0]$11039 $3\reg$next[3:0]$11038 + assign $4\reg$next[3:0]$11437 $3\reg$next[3:0]$11436 end sync always - update \reg$next $0\reg$next[3:0]$11035 + update \reg$next $0\reg$next[3:0]$11433 end - attribute \src "libresoc.v:168139.3-168178.6" - process $proc$libresoc.v:168139$11040 + attribute \src "libresoc.v:171564.3-171603.6" + process $proc$libresoc.v:171564$11438 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11041 $6\src25__data_o$next[3:0]$11047 - attribute \src "libresoc.v:168140.5-168140.29" + assign $0\src25__data_o$next[3:0]$11439 $6\src25__data_o$next[3:0]$11445 + attribute \src "libresoc.v:171565.5-171565.29" switch \initial - attribute \src "libresoc.v:168140.9-168140.17" + attribute \src "libresoc.v:171565.9-171565.17" case 1'1 case end @@ -347525,66 +355455,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11042 $5\src25__data_o$next[3:0]$11046 + assign $1\src25__data_o$next[3:0]$11440 $5\src25__data_o$next[3:0]$11444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11043 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11441 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11043 4'0000 + assign $2\src25__data_o$next[3:0]$11441 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11044 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11442 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11044 $2\src25__data_o$next[3:0]$11043 + assign $3\src25__data_o$next[3:0]$11442 $2\src25__data_o$next[3:0]$11441 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11045 \w5__data_i + assign $4\src25__data_o$next[3:0]$11443 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11045 $3\src25__data_o$next[3:0]$11044 + assign $4\src25__data_o$next[3:0]$11443 $3\src25__data_o$next[3:0]$11442 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11046 \reg + assign $5\src25__data_o$next[3:0]$11444 \reg case - assign $5\src25__data_o$next[3:0]$11046 $4\src25__data_o$next[3:0]$11045 + assign $5\src25__data_o$next[3:0]$11444 $4\src25__data_o$next[3:0]$11443 end case - assign $1\src25__data_o$next[3:0]$11042 4'0000 + assign $1\src25__data_o$next[3:0]$11440 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11047 4'0000 + assign $6\src25__data_o$next[3:0]$11445 4'0000 case - assign $6\src25__data_o$next[3:0]$11047 $1\src25__data_o$next[3:0]$11042 + assign $6\src25__data_o$next[3:0]$11445 $1\src25__data_o$next[3:0]$11440 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11041 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11439 end - attribute \src "libresoc.v:168179.3-168208.6" - process $proc$libresoc.v:168179$11048 + attribute \src "libresoc.v:171604.3-171633.6" + process $proc$libresoc.v:171604$11446 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11049 $1\wr_detect$4[0:0]$11050 - attribute \src "libresoc.v:168180.5-168180.29" + assign $0\wr_detect$4[0:0]$11447 $1\wr_detect$4[0:0]$11448 + attribute \src "libresoc.v:171605.5-171605.29" switch \initial - attribute \src "libresoc.v:168180.9-168180.17" + attribute \src "libresoc.v:171605.9-171605.17" case 1'1 case end @@ -347596,49 +355526,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11050 $4\wr_detect$4[0:0]$11053 + assign $1\wr_detect$4[0:0]$11448 $4\wr_detect$4[0:0]$11451 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11051 1'1 + assign $2\wr_detect$4[0:0]$11449 1'1 case - assign $2\wr_detect$4[0:0]$11051 1'0 + assign $2\wr_detect$4[0:0]$11449 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11052 1'1 + assign $3\wr_detect$4[0:0]$11450 1'1 case - assign $3\wr_detect$4[0:0]$11052 $2\wr_detect$4[0:0]$11051 + assign $3\wr_detect$4[0:0]$11450 $2\wr_detect$4[0:0]$11449 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11053 1'1 + assign $4\wr_detect$4[0:0]$11451 1'1 case - assign $4\wr_detect$4[0:0]$11053 $3\wr_detect$4[0:0]$11052 + assign $4\wr_detect$4[0:0]$11451 $3\wr_detect$4[0:0]$11450 end case - assign $1\wr_detect$4[0:0]$11050 1'0 + assign $1\wr_detect$4[0:0]$11448 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11049 + update \wr_detect$4 $0\wr_detect$4[0:0]$11447 end - attribute \src "libresoc.v:168209.3-168248.6" - process $proc$libresoc.v:168209$11054 + attribute \src "libresoc.v:171634.3-171673.6" + process $proc$libresoc.v:171634$11452 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11055 $6\src35__data_o$next[3:0]$11061 - attribute \src "libresoc.v:168210.5-168210.29" + assign $0\src35__data_o$next[3:0]$11453 $6\src35__data_o$next[3:0]$11459 + attribute \src "libresoc.v:171635.5-171635.29" switch \initial - attribute \src "libresoc.v:168210.9-168210.17" + attribute \src "libresoc.v:171635.9-171635.17" case 1'1 case end @@ -347650,66 +355580,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11056 $5\src35__data_o$next[3:0]$11060 + assign $1\src35__data_o$next[3:0]$11454 $5\src35__data_o$next[3:0]$11458 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11057 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11455 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11057 4'0000 + assign $2\src35__data_o$next[3:0]$11455 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11058 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11456 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11058 $2\src35__data_o$next[3:0]$11057 + assign $3\src35__data_o$next[3:0]$11456 $2\src35__data_o$next[3:0]$11455 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11059 \w5__data_i + assign $4\src35__data_o$next[3:0]$11457 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11059 $3\src35__data_o$next[3:0]$11058 + assign $4\src35__data_o$next[3:0]$11457 $3\src35__data_o$next[3:0]$11456 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11060 \reg + assign $5\src35__data_o$next[3:0]$11458 \reg case - assign $5\src35__data_o$next[3:0]$11060 $4\src35__data_o$next[3:0]$11059 + assign $5\src35__data_o$next[3:0]$11458 $4\src35__data_o$next[3:0]$11457 end case - assign $1\src35__data_o$next[3:0]$11056 4'0000 + assign $1\src35__data_o$next[3:0]$11454 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11061 4'0000 + assign $6\src35__data_o$next[3:0]$11459 4'0000 case - assign $6\src35__data_o$next[3:0]$11061 $1\src35__data_o$next[3:0]$11056 + assign $6\src35__data_o$next[3:0]$11459 $1\src35__data_o$next[3:0]$11454 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11055 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11453 end - attribute \src "libresoc.v:168249.3-168278.6" - process $proc$libresoc.v:168249$11062 + attribute \src "libresoc.v:171674.3-171703.6" + process $proc$libresoc.v:171674$11460 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11063 $1\wr_detect$7[0:0]$11064 - attribute \src "libresoc.v:168250.5-168250.29" + assign $0\wr_detect$7[0:0]$11461 $1\wr_detect$7[0:0]$11462 + attribute \src "libresoc.v:171675.5-171675.29" switch \initial - attribute \src "libresoc.v:168250.9-168250.17" + attribute \src "libresoc.v:171675.9-171675.17" case 1'1 case end @@ -347721,49 +355651,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11064 $4\wr_detect$7[0:0]$11067 + assign $1\wr_detect$7[0:0]$11462 $4\wr_detect$7[0:0]$11465 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11065 1'1 + assign $2\wr_detect$7[0:0]$11463 1'1 case - assign $2\wr_detect$7[0:0]$11065 1'0 + assign $2\wr_detect$7[0:0]$11463 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11066 1'1 + assign $3\wr_detect$7[0:0]$11464 1'1 case - assign $3\wr_detect$7[0:0]$11066 $2\wr_detect$7[0:0]$11065 + assign $3\wr_detect$7[0:0]$11464 $2\wr_detect$7[0:0]$11463 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11067 1'1 + assign $4\wr_detect$7[0:0]$11465 1'1 case - assign $4\wr_detect$7[0:0]$11067 $3\wr_detect$7[0:0]$11066 + assign $4\wr_detect$7[0:0]$11465 $3\wr_detect$7[0:0]$11464 end case - assign $1\wr_detect$7[0:0]$11064 1'0 + assign $1\wr_detect$7[0:0]$11462 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11063 + update \wr_detect$7 $0\wr_detect$7[0:0]$11461 end - attribute \src "libresoc.v:168279.3-168318.6" - process $proc$libresoc.v:168279$11068 + attribute \src "libresoc.v:171704.3-171743.6" + process $proc$libresoc.v:171704$11466 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11069 $6\r5__data_o$next[3:0]$11075 - attribute \src "libresoc.v:168280.5-168280.29" + assign $0\r5__data_o$next[3:0]$11467 $6\r5__data_o$next[3:0]$11473 + attribute \src "libresoc.v:171705.5-171705.29" switch \initial - attribute \src "libresoc.v:168280.9-168280.17" + attribute \src "libresoc.v:171705.9-171705.17" case 1'1 case end @@ -347775,66 +355705,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11070 $5\r5__data_o$next[3:0]$11074 + assign $1\r5__data_o$next[3:0]$11468 $5\r5__data_o$next[3:0]$11472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11071 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11469 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11071 4'0000 + assign $2\r5__data_o$next[3:0]$11469 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11072 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11470 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11072 $2\r5__data_o$next[3:0]$11071 + assign $3\r5__data_o$next[3:0]$11470 $2\r5__data_o$next[3:0]$11469 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11073 \w5__data_i + assign $4\r5__data_o$next[3:0]$11471 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11073 $3\r5__data_o$next[3:0]$11072 + assign $4\r5__data_o$next[3:0]$11471 $3\r5__data_o$next[3:0]$11470 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11074 \reg + assign $5\r5__data_o$next[3:0]$11472 \reg case - assign $5\r5__data_o$next[3:0]$11074 $4\r5__data_o$next[3:0]$11073 + assign $5\r5__data_o$next[3:0]$11472 $4\r5__data_o$next[3:0]$11471 end case - assign $1\r5__data_o$next[3:0]$11070 4'0000 + assign $1\r5__data_o$next[3:0]$11468 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11075 4'0000 + assign $6\r5__data_o$next[3:0]$11473 4'0000 case - assign $6\r5__data_o$next[3:0]$11075 $1\r5__data_o$next[3:0]$11070 + assign $6\r5__data_o$next[3:0]$11473 $1\r5__data_o$next[3:0]$11468 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11069 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11467 end - attribute \src "libresoc.v:168319.3-168348.6" - process $proc$libresoc.v:168319$11076 + attribute \src "libresoc.v:171744.3-171773.6" + process $proc$libresoc.v:171744$11474 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11077 $1\wr_detect$10[0:0]$11078 - attribute \src "libresoc.v:168320.5-168320.29" + assign $0\wr_detect$10[0:0]$11475 $1\wr_detect$10[0:0]$11476 + attribute \src "libresoc.v:171745.5-171745.29" switch \initial - attribute \src "libresoc.v:168320.9-168320.17" + attribute \src "libresoc.v:171745.9-171745.17" case 1'1 case end @@ -347846,49 +355776,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11078 $4\wr_detect$10[0:0]$11081 + assign $1\wr_detect$10[0:0]$11476 $4\wr_detect$10[0:0]$11479 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11079 1'1 + assign $2\wr_detect$10[0:0]$11477 1'1 case - assign $2\wr_detect$10[0:0]$11079 1'0 + assign $2\wr_detect$10[0:0]$11477 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11080 1'1 + assign $3\wr_detect$10[0:0]$11478 1'1 case - assign $3\wr_detect$10[0:0]$11080 $2\wr_detect$10[0:0]$11079 + assign $3\wr_detect$10[0:0]$11478 $2\wr_detect$10[0:0]$11477 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11081 1'1 + assign $4\wr_detect$10[0:0]$11479 1'1 case - assign $4\wr_detect$10[0:0]$11081 $3\wr_detect$10[0:0]$11080 + assign $4\wr_detect$10[0:0]$11479 $3\wr_detect$10[0:0]$11478 end case - assign $1\wr_detect$10[0:0]$11078 1'0 + assign $1\wr_detect$10[0:0]$11476 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11077 + update \wr_detect$10 $0\wr_detect$10[0:0]$11475 end - attribute \src "libresoc.v:168349.3-168388.6" - process $proc$libresoc.v:168349$11082 + attribute \src "libresoc.v:171774.3-171813.6" + process $proc$libresoc.v:171774$11480 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11083 $6\r25__data_o$next[3:0]$11089 - attribute \src "libresoc.v:168350.5-168350.29" + assign $0\r25__data_o$next[3:0]$11481 $6\r25__data_o$next[3:0]$11487 + attribute \src "libresoc.v:171775.5-171775.29" switch \initial - attribute \src "libresoc.v:168350.9-168350.17" + attribute \src "libresoc.v:171775.9-171775.17" case 1'1 case end @@ -347900,66 +355830,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11084 $5\r25__data_o$next[3:0]$11088 + assign $1\r25__data_o$next[3:0]$11482 $5\r25__data_o$next[3:0]$11486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11085 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11483 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11085 4'0000 + assign $2\r25__data_o$next[3:0]$11483 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11086 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11484 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11086 $2\r25__data_o$next[3:0]$11085 + assign $3\r25__data_o$next[3:0]$11484 $2\r25__data_o$next[3:0]$11483 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11087 \w5__data_i + assign $4\r25__data_o$next[3:0]$11485 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11087 $3\r25__data_o$next[3:0]$11086 + assign $4\r25__data_o$next[3:0]$11485 $3\r25__data_o$next[3:0]$11484 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11088 \reg + assign $5\r25__data_o$next[3:0]$11486 \reg case - assign $5\r25__data_o$next[3:0]$11088 $4\r25__data_o$next[3:0]$11087 + assign $5\r25__data_o$next[3:0]$11486 $4\r25__data_o$next[3:0]$11485 end case - assign $1\r25__data_o$next[3:0]$11084 4'0000 + assign $1\r25__data_o$next[3:0]$11482 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11089 4'0000 + assign $6\r25__data_o$next[3:0]$11487 4'0000 case - assign $6\r25__data_o$next[3:0]$11089 $1\r25__data_o$next[3:0]$11084 + assign $6\r25__data_o$next[3:0]$11487 $1\r25__data_o$next[3:0]$11482 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11083 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11481 end - attribute \src "libresoc.v:168389.3-168418.6" - process $proc$libresoc.v:168389$11090 + attribute \src "libresoc.v:171814.3-171843.6" + process $proc$libresoc.v:171814$11488 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11091 $1\wr_detect$13[0:0]$11092 - attribute \src "libresoc.v:168390.5-168390.29" + assign $0\wr_detect$13[0:0]$11489 $1\wr_detect$13[0:0]$11490 + attribute \src "libresoc.v:171815.5-171815.29" switch \initial - attribute \src "libresoc.v:168390.9-168390.17" + attribute \src "libresoc.v:171815.9-171815.17" case 1'1 case end @@ -347971,217 +355901,217 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11092 $4\wr_detect$13[0:0]$11095 + assign $1\wr_detect$13[0:0]$11490 $4\wr_detect$13[0:0]$11493 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11093 1'1 + assign $2\wr_detect$13[0:0]$11491 1'1 case - assign $2\wr_detect$13[0:0]$11093 1'0 + assign $2\wr_detect$13[0:0]$11491 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11094 1'1 + assign $3\wr_detect$13[0:0]$11492 1'1 case - assign $3\wr_detect$13[0:0]$11094 $2\wr_detect$13[0:0]$11093 + assign $3\wr_detect$13[0:0]$11492 $2\wr_detect$13[0:0]$11491 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11095 1'1 + assign $4\wr_detect$13[0:0]$11493 1'1 case - assign $4\wr_detect$13[0:0]$11095 $3\wr_detect$13[0:0]$11094 + assign $4\wr_detect$13[0:0]$11493 $3\wr_detect$13[0:0]$11492 end case - assign $1\wr_detect$13[0:0]$11092 1'0 + assign $1\wr_detect$13[0:0]$11490 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11091 + update \wr_detect$13 $0\wr_detect$13[0:0]$11489 end - connect \$9 $not$libresoc.v:168025$11014_Y - connect \$12 $not$libresoc.v:168026$11015_Y - connect \$1 $not$libresoc.v:168027$11016_Y - connect \$3 $not$libresoc.v:168028$11017_Y - connect \$6 $not$libresoc.v:168029$11018_Y + connect \$9 $not$libresoc.v:171450$11412_Y + connect \$12 $not$libresoc.v:171451$11413_Y + connect \$1 $not$libresoc.v:171452$11414_Y + connect \$3 $not$libresoc.v:171453$11415_Y + connect \$6 $not$libresoc.v:171454$11416_Y end -attribute \src "libresoc.v:168423.1-168894.10" +attribute \src "libresoc.v:171848.1-172319.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:168424.7-168424.20" + attribute \src "libresoc.v:171849.7-171849.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $0\r26__data_o$next[3:0]$11172 - attribute \src "libresoc.v:168507.3-168508.39" + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $0\r26__data_o$next[3:0]$11570 + attribute \src "libresoc.v:171932.3-171933.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $0\r6__data_o$next[3:0]$11158 - attribute \src "libresoc.v:168509.3-168510.37" + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $0\r6__data_o$next[3:0]$11556 + attribute \src "libresoc.v:171934.3-171935.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:168587.3-168613.6" - wire width 4 $0\reg$next[3:0]$11124 - attribute \src "libresoc.v:168505.3-168506.25" + attribute \src "libresoc.v:172012.3-172038.6" + wire width 4 $0\reg$next[3:0]$11522 + attribute \src "libresoc.v:171930.3-171931.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $0\src16__data_o$next[3:0]$11115 - attribute \src "libresoc.v:168515.3-168516.43" + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $0\src16__data_o$next[3:0]$11513 + attribute \src "libresoc.v:171940.3-171941.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $0\src26__data_o$next[3:0]$11130 - attribute \src "libresoc.v:168513.3-168514.43" + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $0\src26__data_o$next[3:0]$11528 + attribute \src "libresoc.v:171938.3-171939.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $0\src36__data_o$next[3:0]$11144 - attribute \src "libresoc.v:168511.3-168512.43" + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $0\src36__data_o$next[3:0]$11542 + attribute \src "libresoc.v:171936.3-171937.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:168794.3-168823.6" - wire $0\wr_detect$10[0:0]$11166 - attribute \src "libresoc.v:168864.3-168893.6" - wire $0\wr_detect$13[0:0]$11180 - attribute \src "libresoc.v:168654.3-168683.6" - wire $0\wr_detect$4[0:0]$11138 - attribute \src "libresoc.v:168724.3-168753.6" - wire $0\wr_detect$7[0:0]$11152 - attribute \src "libresoc.v:168557.3-168586.6" + attribute \src "libresoc.v:172219.3-172248.6" + wire $0\wr_detect$10[0:0]$11564 + attribute \src "libresoc.v:172289.3-172318.6" + wire $0\wr_detect$13[0:0]$11578 + attribute \src "libresoc.v:172079.3-172108.6" + wire $0\wr_detect$4[0:0]$11536 + attribute \src "libresoc.v:172149.3-172178.6" + wire $0\wr_detect$7[0:0]$11550 + attribute \src "libresoc.v:171982.3-172011.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $1\r26__data_o$next[3:0]$11173 - attribute \src "libresoc.v:168449.13-168449.31" + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $1\r26__data_o$next[3:0]$11571 + attribute \src "libresoc.v:171874.13-171874.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $1\r6__data_o$next[3:0]$11159 - attribute \src "libresoc.v:168456.13-168456.30" + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $1\r6__data_o$next[3:0]$11557 + attribute \src "libresoc.v:171881.13-171881.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:168587.3-168613.6" - wire width 4 $1\reg$next[3:0]$11125 - attribute \src "libresoc.v:168462.13-168462.25" + attribute \src "libresoc.v:172012.3-172038.6" + wire width 4 $1\reg$next[3:0]$11523 + attribute \src "libresoc.v:171887.13-171887.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $1\src16__data_o$next[3:0]$11116 - attribute \src "libresoc.v:168467.13-168467.33" + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $1\src16__data_o$next[3:0]$11514 + attribute \src "libresoc.v:171892.13-171892.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $1\src26__data_o$next[3:0]$11131 - attribute \src "libresoc.v:168474.13-168474.33" + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $1\src26__data_o$next[3:0]$11529 + attribute \src "libresoc.v:171899.13-171899.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $1\src36__data_o$next[3:0]$11145 - attribute \src "libresoc.v:168481.13-168481.33" + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $1\src36__data_o$next[3:0]$11543 + attribute \src "libresoc.v:171906.13-171906.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:168794.3-168823.6" - wire $1\wr_detect$10[0:0]$11167 - attribute \src "libresoc.v:168864.3-168893.6" - wire $1\wr_detect$13[0:0]$11181 - attribute \src "libresoc.v:168654.3-168683.6" - wire $1\wr_detect$4[0:0]$11139 - attribute \src "libresoc.v:168724.3-168753.6" - wire $1\wr_detect$7[0:0]$11153 - attribute \src "libresoc.v:168557.3-168586.6" + attribute \src "libresoc.v:172219.3-172248.6" + wire $1\wr_detect$10[0:0]$11565 + attribute \src "libresoc.v:172289.3-172318.6" + wire $1\wr_detect$13[0:0]$11579 + attribute \src "libresoc.v:172079.3-172108.6" + wire $1\wr_detect$4[0:0]$11537 + attribute \src "libresoc.v:172149.3-172178.6" + wire $1\wr_detect$7[0:0]$11551 + attribute \src "libresoc.v:171982.3-172011.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $2\r26__data_o$next[3:0]$11174 - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $2\r6__data_o$next[3:0]$11160 - attribute \src "libresoc.v:168587.3-168613.6" - wire width 4 $2\reg$next[3:0]$11126 - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $2\src16__data_o$next[3:0]$11117 - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $2\src26__data_o$next[3:0]$11132 - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $2\src36__data_o$next[3:0]$11146 - attribute \src "libresoc.v:168794.3-168823.6" - wire $2\wr_detect$10[0:0]$11168 - attribute \src "libresoc.v:168864.3-168893.6" - wire $2\wr_detect$13[0:0]$11182 - attribute \src "libresoc.v:168654.3-168683.6" - wire $2\wr_detect$4[0:0]$11140 - attribute \src "libresoc.v:168724.3-168753.6" - wire $2\wr_detect$7[0:0]$11154 - attribute \src "libresoc.v:168557.3-168586.6" + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $2\r26__data_o$next[3:0]$11572 + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $2\r6__data_o$next[3:0]$11558 + attribute \src "libresoc.v:172012.3-172038.6" + wire width 4 $2\reg$next[3:0]$11524 + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $2\src16__data_o$next[3:0]$11515 + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $2\src26__data_o$next[3:0]$11530 + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $2\src36__data_o$next[3:0]$11544 + attribute \src "libresoc.v:172219.3-172248.6" + wire $2\wr_detect$10[0:0]$11566 + attribute \src "libresoc.v:172289.3-172318.6" + wire $2\wr_detect$13[0:0]$11580 + attribute \src "libresoc.v:172079.3-172108.6" + wire $2\wr_detect$4[0:0]$11538 + attribute \src "libresoc.v:172149.3-172178.6" + wire $2\wr_detect$7[0:0]$11552 + attribute \src "libresoc.v:171982.3-172011.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $3\r26__data_o$next[3:0]$11175 - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $3\r6__data_o$next[3:0]$11161 - attribute \src "libresoc.v:168587.3-168613.6" - wire width 4 $3\reg$next[3:0]$11127 - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $3\src16__data_o$next[3:0]$11118 - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $3\src26__data_o$next[3:0]$11133 - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $3\src36__data_o$next[3:0]$11147 - attribute \src "libresoc.v:168794.3-168823.6" - wire $3\wr_detect$10[0:0]$11169 - attribute \src "libresoc.v:168864.3-168893.6" - wire $3\wr_detect$13[0:0]$11183 - attribute \src "libresoc.v:168654.3-168683.6" - wire $3\wr_detect$4[0:0]$11141 - attribute \src "libresoc.v:168724.3-168753.6" - wire $3\wr_detect$7[0:0]$11155 - attribute \src "libresoc.v:168557.3-168586.6" + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $3\r26__data_o$next[3:0]$11573 + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $3\r6__data_o$next[3:0]$11559 + attribute \src "libresoc.v:172012.3-172038.6" + wire width 4 $3\reg$next[3:0]$11525 + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $3\src16__data_o$next[3:0]$11516 + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $3\src26__data_o$next[3:0]$11531 + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $3\src36__data_o$next[3:0]$11545 + attribute \src "libresoc.v:172219.3-172248.6" + wire $3\wr_detect$10[0:0]$11567 + attribute \src "libresoc.v:172289.3-172318.6" + wire $3\wr_detect$13[0:0]$11581 + attribute \src "libresoc.v:172079.3-172108.6" + wire $3\wr_detect$4[0:0]$11539 + attribute \src "libresoc.v:172149.3-172178.6" + wire $3\wr_detect$7[0:0]$11553 + attribute \src "libresoc.v:171982.3-172011.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $4\r26__data_o$next[3:0]$11176 - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $4\r6__data_o$next[3:0]$11162 - attribute \src "libresoc.v:168587.3-168613.6" - wire width 4 $4\reg$next[3:0]$11128 - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $4\src16__data_o$next[3:0]$11119 - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $4\src26__data_o$next[3:0]$11134 - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $4\src36__data_o$next[3:0]$11148 - attribute \src "libresoc.v:168794.3-168823.6" - wire $4\wr_detect$10[0:0]$11170 - attribute \src "libresoc.v:168864.3-168893.6" - wire $4\wr_detect$13[0:0]$11184 - attribute \src "libresoc.v:168654.3-168683.6" - wire $4\wr_detect$4[0:0]$11142 - attribute \src "libresoc.v:168724.3-168753.6" - wire $4\wr_detect$7[0:0]$11156 - attribute \src "libresoc.v:168557.3-168586.6" + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $4\r26__data_o$next[3:0]$11574 + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $4\r6__data_o$next[3:0]$11560 + attribute \src "libresoc.v:172012.3-172038.6" + wire width 4 $4\reg$next[3:0]$11526 + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $4\src16__data_o$next[3:0]$11517 + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $4\src26__data_o$next[3:0]$11532 + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $4\src36__data_o$next[3:0]$11546 + attribute \src "libresoc.v:172219.3-172248.6" + wire $4\wr_detect$10[0:0]$11568 + attribute \src "libresoc.v:172289.3-172318.6" + wire $4\wr_detect$13[0:0]$11582 + attribute \src "libresoc.v:172079.3-172108.6" + wire $4\wr_detect$4[0:0]$11540 + attribute \src "libresoc.v:172149.3-172178.6" + wire $4\wr_detect$7[0:0]$11554 + attribute \src "libresoc.v:171982.3-172011.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $5\r26__data_o$next[3:0]$11177 - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $5\r6__data_o$next[3:0]$11163 - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $5\src16__data_o$next[3:0]$11120 - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $5\src26__data_o$next[3:0]$11135 - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $5\src36__data_o$next[3:0]$11149 - attribute \src "libresoc.v:168824.3-168863.6" - wire width 4 $6\r26__data_o$next[3:0]$11178 - attribute \src "libresoc.v:168754.3-168793.6" - wire width 4 $6\r6__data_o$next[3:0]$11164 - attribute \src "libresoc.v:168517.3-168556.6" - wire width 4 $6\src16__data_o$next[3:0]$11121 - attribute \src "libresoc.v:168614.3-168653.6" - wire width 4 $6\src26__data_o$next[3:0]$11136 - attribute \src "libresoc.v:168684.3-168723.6" - wire width 4 $6\src36__data_o$next[3:0]$11150 - attribute \src "libresoc.v:168500.17-168500.104" - wire $not$libresoc.v:168500$11103_Y - attribute \src "libresoc.v:168501.18-168501.105" - wire $not$libresoc.v:168501$11104_Y - attribute \src "libresoc.v:168502.17-168502.100" - wire $not$libresoc.v:168502$11105_Y - attribute \src "libresoc.v:168503.17-168503.103" - wire $not$libresoc.v:168503$11106_Y - attribute \src "libresoc.v:168504.17-168504.103" - wire $not$libresoc.v:168504$11107_Y + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $5\r26__data_o$next[3:0]$11575 + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $5\r6__data_o$next[3:0]$11561 + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $5\src16__data_o$next[3:0]$11518 + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $5\src26__data_o$next[3:0]$11533 + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $5\src36__data_o$next[3:0]$11547 + attribute \src "libresoc.v:172249.3-172288.6" + wire width 4 $6\r26__data_o$next[3:0]$11576 + attribute \src "libresoc.v:172179.3-172218.6" + wire width 4 $6\r6__data_o$next[3:0]$11562 + attribute \src "libresoc.v:171942.3-171981.6" + wire width 4 $6\src16__data_o$next[3:0]$11519 + attribute \src "libresoc.v:172039.3-172078.6" + wire width 4 $6\src26__data_o$next[3:0]$11534 + attribute \src "libresoc.v:172109.3-172148.6" + wire width 4 $6\src36__data_o$next[3:0]$11548 + attribute \src "libresoc.v:171925.17-171925.104" + wire $not$libresoc.v:171925$11501_Y + attribute \src "libresoc.v:171926.18-171926.105" + wire $not$libresoc.v:171926$11502_Y + attribute \src "libresoc.v:171927.17-171927.100" + wire $not$libresoc.v:171927$11503_Y + attribute \src "libresoc.v:171928.17-171928.103" + wire $not$libresoc.v:171928$11504_Y + attribute \src "libresoc.v:171929.17-171929.103" + wire $not$libresoc.v:171929$11505_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -348192,9 +356122,9 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest16__data_i @@ -348204,7 +356134,7 @@ module \reg_6 wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest26__wen - attribute \src "libresoc.v:168424.7-168424.15" + attribute \src "libresoc.v:171849.7-171849.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r26__data_o @@ -348255,152 +356185,152 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168500$11103 + cell $not $not$libresoc.v:171925$11501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168500$11103_Y + connect \Y $not$libresoc.v:171925$11501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168501$11104 + cell $not $not$libresoc.v:171926$11502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:168501$11104_Y + connect \Y $not$libresoc.v:171926$11502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168502$11105 + cell $not $not$libresoc.v:171927$11503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168502$11105_Y + connect \Y $not$libresoc.v:171927$11503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168503$11106 + cell $not $not$libresoc.v:171928$11504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168503$11106_Y + connect \Y $not$libresoc.v:171928$11504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168504$11107 + cell $not $not$libresoc.v:171929$11505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168504$11107_Y + connect \Y $not$libresoc.v:171929$11505_Y end - attribute \src "libresoc.v:168424.7-168424.20" - process $proc$libresoc.v:168424$11185 + attribute \src "libresoc.v:171849.7-171849.20" + process $proc$libresoc.v:171849$11583 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168449.13-168449.31" - process $proc$libresoc.v:168449$11186 + attribute \src "libresoc.v:171874.13-171874.31" + process $proc$libresoc.v:171874$11584 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:168456.13-168456.30" - process $proc$libresoc.v:168456$11187 + attribute \src "libresoc.v:171881.13-171881.30" + process $proc$libresoc.v:171881$11585 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:168462.13-168462.25" - process $proc$libresoc.v:168462$11188 + attribute \src "libresoc.v:171887.13-171887.25" + process $proc$libresoc.v:171887$11586 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:168467.13-168467.33" - process $proc$libresoc.v:168467$11189 + attribute \src "libresoc.v:171892.13-171892.33" + process $proc$libresoc.v:171892$11587 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:168474.13-168474.33" - process $proc$libresoc.v:168474$11190 + attribute \src "libresoc.v:171899.13-171899.33" + process $proc$libresoc.v:171899$11588 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:168481.13-168481.33" - process $proc$libresoc.v:168481$11191 + attribute \src "libresoc.v:171906.13-171906.33" + process $proc$libresoc.v:171906$11589 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:168505.3-168506.25" - process $proc$libresoc.v:168505$11108 + attribute \src "libresoc.v:171930.3-171931.25" + process $proc$libresoc.v:171930$11506 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:168507.3-168508.39" - process $proc$libresoc.v:168507$11109 + attribute \src "libresoc.v:171932.3-171933.39" + process $proc$libresoc.v:171932$11507 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:168509.3-168510.37" - process $proc$libresoc.v:168509$11110 + attribute \src "libresoc.v:171934.3-171935.37" + process $proc$libresoc.v:171934$11508 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:168511.3-168512.43" - process $proc$libresoc.v:168511$11111 + attribute \src "libresoc.v:171936.3-171937.43" + process $proc$libresoc.v:171936$11509 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:168513.3-168514.43" - process $proc$libresoc.v:168513$11112 + attribute \src "libresoc.v:171938.3-171939.43" + process $proc$libresoc.v:171938$11510 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:168515.3-168516.43" - process $proc$libresoc.v:168515$11113 + attribute \src "libresoc.v:171940.3-171941.43" + process $proc$libresoc.v:171940$11511 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:168517.3-168556.6" - process $proc$libresoc.v:168517$11114 + attribute \src "libresoc.v:171942.3-171981.6" + process $proc$libresoc.v:171942$11512 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11115 $6\src16__data_o$next[3:0]$11121 - attribute \src "libresoc.v:168518.5-168518.29" + assign $0\src16__data_o$next[3:0]$11513 $6\src16__data_o$next[3:0]$11519 + attribute \src "libresoc.v:171943.5-171943.29" switch \initial - attribute \src "libresoc.v:168518.9-168518.17" + attribute \src "libresoc.v:171943.9-171943.17" case 1'1 case end @@ -348412,66 +356342,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11116 $5\src16__data_o$next[3:0]$11120 + assign $1\src16__data_o$next[3:0]$11514 $5\src16__data_o$next[3:0]$11518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11117 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11515 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11117 4'0000 + assign $2\src16__data_o$next[3:0]$11515 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11118 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11516 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11118 $2\src16__data_o$next[3:0]$11117 + assign $3\src16__data_o$next[3:0]$11516 $2\src16__data_o$next[3:0]$11515 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11119 \w6__data_i + assign $4\src16__data_o$next[3:0]$11517 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11119 $3\src16__data_o$next[3:0]$11118 + assign $4\src16__data_o$next[3:0]$11517 $3\src16__data_o$next[3:0]$11516 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11120 \reg + assign $5\src16__data_o$next[3:0]$11518 \reg case - assign $5\src16__data_o$next[3:0]$11120 $4\src16__data_o$next[3:0]$11119 + assign $5\src16__data_o$next[3:0]$11518 $4\src16__data_o$next[3:0]$11517 end case - assign $1\src16__data_o$next[3:0]$11116 4'0000 + assign $1\src16__data_o$next[3:0]$11514 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11121 4'0000 + assign $6\src16__data_o$next[3:0]$11519 4'0000 case - assign $6\src16__data_o$next[3:0]$11121 $1\src16__data_o$next[3:0]$11116 + assign $6\src16__data_o$next[3:0]$11519 $1\src16__data_o$next[3:0]$11514 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11115 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11513 end - attribute \src "libresoc.v:168557.3-168586.6" - process $proc$libresoc.v:168557$11122 + attribute \src "libresoc.v:171982.3-172011.6" + process $proc$libresoc.v:171982$11520 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168558.5-168558.29" + attribute \src "libresoc.v:171983.5-171983.29" switch \initial - attribute \src "libresoc.v:168558.9-168558.17" + attribute \src "libresoc.v:171983.9-171983.17" case 1'1 case end @@ -348517,17 +356447,17 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:168587.3-168613.6" - process $proc$libresoc.v:168587$11123 + attribute \src "libresoc.v:172012.3-172038.6" + process $proc$libresoc.v:172012$11521 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11124 $4\reg$next[3:0]$11128 - attribute \src "libresoc.v:168588.5-168588.29" + assign $0\reg$next[3:0]$11522 $4\reg$next[3:0]$11526 + attribute \src "libresoc.v:172013.5-172013.29" switch \initial - attribute \src "libresoc.v:168588.9-168588.17" + attribute \src "libresoc.v:172013.9-172013.17" case 1'1 case end @@ -348536,49 +356466,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11125 \dest16__data_i + assign $1\reg$next[3:0]$11523 \dest16__data_i case - assign $1\reg$next[3:0]$11125 \reg + assign $1\reg$next[3:0]$11523 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11126 \dest26__data_i + assign $2\reg$next[3:0]$11524 \dest26__data_i case - assign $2\reg$next[3:0]$11126 $1\reg$next[3:0]$11125 + assign $2\reg$next[3:0]$11524 $1\reg$next[3:0]$11523 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11127 \w6__data_i + assign $3\reg$next[3:0]$11525 \w6__data_i case - assign $3\reg$next[3:0]$11127 $2\reg$next[3:0]$11126 + assign $3\reg$next[3:0]$11525 $2\reg$next[3:0]$11524 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11128 4'0000 + assign $4\reg$next[3:0]$11526 4'0000 case - assign $4\reg$next[3:0]$11128 $3\reg$next[3:0]$11127 + assign $4\reg$next[3:0]$11526 $3\reg$next[3:0]$11525 end sync always - update \reg$next $0\reg$next[3:0]$11124 + update \reg$next $0\reg$next[3:0]$11522 end - attribute \src "libresoc.v:168614.3-168653.6" - process $proc$libresoc.v:168614$11129 + attribute \src "libresoc.v:172039.3-172078.6" + process $proc$libresoc.v:172039$11527 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11130 $6\src26__data_o$next[3:0]$11136 - attribute \src "libresoc.v:168615.5-168615.29" + assign $0\src26__data_o$next[3:0]$11528 $6\src26__data_o$next[3:0]$11534 + attribute \src "libresoc.v:172040.5-172040.29" switch \initial - attribute \src "libresoc.v:168615.9-168615.17" + attribute \src "libresoc.v:172040.9-172040.17" case 1'1 case end @@ -348590,66 +356520,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11131 $5\src26__data_o$next[3:0]$11135 + assign $1\src26__data_o$next[3:0]$11529 $5\src26__data_o$next[3:0]$11533 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11132 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11530 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11132 4'0000 + assign $2\src26__data_o$next[3:0]$11530 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11133 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11531 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11133 $2\src26__data_o$next[3:0]$11132 + assign $3\src26__data_o$next[3:0]$11531 $2\src26__data_o$next[3:0]$11530 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11134 \w6__data_i + assign $4\src26__data_o$next[3:0]$11532 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11134 $3\src26__data_o$next[3:0]$11133 + assign $4\src26__data_o$next[3:0]$11532 $3\src26__data_o$next[3:0]$11531 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11135 \reg + assign $5\src26__data_o$next[3:0]$11533 \reg case - assign $5\src26__data_o$next[3:0]$11135 $4\src26__data_o$next[3:0]$11134 + assign $5\src26__data_o$next[3:0]$11533 $4\src26__data_o$next[3:0]$11532 end case - assign $1\src26__data_o$next[3:0]$11131 4'0000 + assign $1\src26__data_o$next[3:0]$11529 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11136 4'0000 + assign $6\src26__data_o$next[3:0]$11534 4'0000 case - assign $6\src26__data_o$next[3:0]$11136 $1\src26__data_o$next[3:0]$11131 + assign $6\src26__data_o$next[3:0]$11534 $1\src26__data_o$next[3:0]$11529 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11130 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11528 end - attribute \src "libresoc.v:168654.3-168683.6" - process $proc$libresoc.v:168654$11137 + attribute \src "libresoc.v:172079.3-172108.6" + process $proc$libresoc.v:172079$11535 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11138 $1\wr_detect$4[0:0]$11139 - attribute \src "libresoc.v:168655.5-168655.29" + assign $0\wr_detect$4[0:0]$11536 $1\wr_detect$4[0:0]$11537 + attribute \src "libresoc.v:172080.5-172080.29" switch \initial - attribute \src "libresoc.v:168655.9-168655.17" + attribute \src "libresoc.v:172080.9-172080.17" case 1'1 case end @@ -348661,49 +356591,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11139 $4\wr_detect$4[0:0]$11142 + assign $1\wr_detect$4[0:0]$11537 $4\wr_detect$4[0:0]$11540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11140 1'1 + assign $2\wr_detect$4[0:0]$11538 1'1 case - assign $2\wr_detect$4[0:0]$11140 1'0 + assign $2\wr_detect$4[0:0]$11538 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11141 1'1 + assign $3\wr_detect$4[0:0]$11539 1'1 case - assign $3\wr_detect$4[0:0]$11141 $2\wr_detect$4[0:0]$11140 + assign $3\wr_detect$4[0:0]$11539 $2\wr_detect$4[0:0]$11538 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11142 1'1 + assign $4\wr_detect$4[0:0]$11540 1'1 case - assign $4\wr_detect$4[0:0]$11142 $3\wr_detect$4[0:0]$11141 + assign $4\wr_detect$4[0:0]$11540 $3\wr_detect$4[0:0]$11539 end case - assign $1\wr_detect$4[0:0]$11139 1'0 + assign $1\wr_detect$4[0:0]$11537 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11138 + update \wr_detect$4 $0\wr_detect$4[0:0]$11536 end - attribute \src "libresoc.v:168684.3-168723.6" - process $proc$libresoc.v:168684$11143 + attribute \src "libresoc.v:172109.3-172148.6" + process $proc$libresoc.v:172109$11541 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11144 $6\src36__data_o$next[3:0]$11150 - attribute \src "libresoc.v:168685.5-168685.29" + assign $0\src36__data_o$next[3:0]$11542 $6\src36__data_o$next[3:0]$11548 + attribute \src "libresoc.v:172110.5-172110.29" switch \initial - attribute \src "libresoc.v:168685.9-168685.17" + attribute \src "libresoc.v:172110.9-172110.17" case 1'1 case end @@ -348715,66 +356645,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11145 $5\src36__data_o$next[3:0]$11149 + assign $1\src36__data_o$next[3:0]$11543 $5\src36__data_o$next[3:0]$11547 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11146 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11544 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11146 4'0000 + assign $2\src36__data_o$next[3:0]$11544 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11147 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11545 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11147 $2\src36__data_o$next[3:0]$11146 + assign $3\src36__data_o$next[3:0]$11545 $2\src36__data_o$next[3:0]$11544 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11148 \w6__data_i + assign $4\src36__data_o$next[3:0]$11546 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11148 $3\src36__data_o$next[3:0]$11147 + assign $4\src36__data_o$next[3:0]$11546 $3\src36__data_o$next[3:0]$11545 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11149 \reg + assign $5\src36__data_o$next[3:0]$11547 \reg case - assign $5\src36__data_o$next[3:0]$11149 $4\src36__data_o$next[3:0]$11148 + assign $5\src36__data_o$next[3:0]$11547 $4\src36__data_o$next[3:0]$11546 end case - assign $1\src36__data_o$next[3:0]$11145 4'0000 + assign $1\src36__data_o$next[3:0]$11543 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11150 4'0000 + assign $6\src36__data_o$next[3:0]$11548 4'0000 case - assign $6\src36__data_o$next[3:0]$11150 $1\src36__data_o$next[3:0]$11145 + assign $6\src36__data_o$next[3:0]$11548 $1\src36__data_o$next[3:0]$11543 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11144 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11542 end - attribute \src "libresoc.v:168724.3-168753.6" - process $proc$libresoc.v:168724$11151 + attribute \src "libresoc.v:172149.3-172178.6" + process $proc$libresoc.v:172149$11549 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11152 $1\wr_detect$7[0:0]$11153 - attribute \src "libresoc.v:168725.5-168725.29" + assign $0\wr_detect$7[0:0]$11550 $1\wr_detect$7[0:0]$11551 + attribute \src "libresoc.v:172150.5-172150.29" switch \initial - attribute \src "libresoc.v:168725.9-168725.17" + attribute \src "libresoc.v:172150.9-172150.17" case 1'1 case end @@ -348786,49 +356716,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11153 $4\wr_detect$7[0:0]$11156 + assign $1\wr_detect$7[0:0]$11551 $4\wr_detect$7[0:0]$11554 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11154 1'1 + assign $2\wr_detect$7[0:0]$11552 1'1 case - assign $2\wr_detect$7[0:0]$11154 1'0 + assign $2\wr_detect$7[0:0]$11552 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11155 1'1 + assign $3\wr_detect$7[0:0]$11553 1'1 case - assign $3\wr_detect$7[0:0]$11155 $2\wr_detect$7[0:0]$11154 + assign $3\wr_detect$7[0:0]$11553 $2\wr_detect$7[0:0]$11552 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11156 1'1 + assign $4\wr_detect$7[0:0]$11554 1'1 case - assign $4\wr_detect$7[0:0]$11156 $3\wr_detect$7[0:0]$11155 + assign $4\wr_detect$7[0:0]$11554 $3\wr_detect$7[0:0]$11553 end case - assign $1\wr_detect$7[0:0]$11153 1'0 + assign $1\wr_detect$7[0:0]$11551 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11152 + update \wr_detect$7 $0\wr_detect$7[0:0]$11550 end - attribute \src "libresoc.v:168754.3-168793.6" - process $proc$libresoc.v:168754$11157 + attribute \src "libresoc.v:172179.3-172218.6" + process $proc$libresoc.v:172179$11555 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11158 $6\r6__data_o$next[3:0]$11164 - attribute \src "libresoc.v:168755.5-168755.29" + assign $0\r6__data_o$next[3:0]$11556 $6\r6__data_o$next[3:0]$11562 + attribute \src "libresoc.v:172180.5-172180.29" switch \initial - attribute \src "libresoc.v:168755.9-168755.17" + attribute \src "libresoc.v:172180.9-172180.17" case 1'1 case end @@ -348840,66 +356770,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11159 $5\r6__data_o$next[3:0]$11163 + assign $1\r6__data_o$next[3:0]$11557 $5\r6__data_o$next[3:0]$11561 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11160 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11558 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11160 4'0000 + assign $2\r6__data_o$next[3:0]$11558 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11161 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11559 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11161 $2\r6__data_o$next[3:0]$11160 + assign $3\r6__data_o$next[3:0]$11559 $2\r6__data_o$next[3:0]$11558 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11162 \w6__data_i + assign $4\r6__data_o$next[3:0]$11560 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11162 $3\r6__data_o$next[3:0]$11161 + assign $4\r6__data_o$next[3:0]$11560 $3\r6__data_o$next[3:0]$11559 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11163 \reg + assign $5\r6__data_o$next[3:0]$11561 \reg case - assign $5\r6__data_o$next[3:0]$11163 $4\r6__data_o$next[3:0]$11162 + assign $5\r6__data_o$next[3:0]$11561 $4\r6__data_o$next[3:0]$11560 end case - assign $1\r6__data_o$next[3:0]$11159 4'0000 + assign $1\r6__data_o$next[3:0]$11557 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11164 4'0000 + assign $6\r6__data_o$next[3:0]$11562 4'0000 case - assign $6\r6__data_o$next[3:0]$11164 $1\r6__data_o$next[3:0]$11159 + assign $6\r6__data_o$next[3:0]$11562 $1\r6__data_o$next[3:0]$11557 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11158 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11556 end - attribute \src "libresoc.v:168794.3-168823.6" - process $proc$libresoc.v:168794$11165 + attribute \src "libresoc.v:172219.3-172248.6" + process $proc$libresoc.v:172219$11563 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11166 $1\wr_detect$10[0:0]$11167 - attribute \src "libresoc.v:168795.5-168795.29" + assign $0\wr_detect$10[0:0]$11564 $1\wr_detect$10[0:0]$11565 + attribute \src "libresoc.v:172220.5-172220.29" switch \initial - attribute \src "libresoc.v:168795.9-168795.17" + attribute \src "libresoc.v:172220.9-172220.17" case 1'1 case end @@ -348911,49 +356841,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11167 $4\wr_detect$10[0:0]$11170 + assign $1\wr_detect$10[0:0]$11565 $4\wr_detect$10[0:0]$11568 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11168 1'1 + assign $2\wr_detect$10[0:0]$11566 1'1 case - assign $2\wr_detect$10[0:0]$11168 1'0 + assign $2\wr_detect$10[0:0]$11566 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11169 1'1 + assign $3\wr_detect$10[0:0]$11567 1'1 case - assign $3\wr_detect$10[0:0]$11169 $2\wr_detect$10[0:0]$11168 + assign $3\wr_detect$10[0:0]$11567 $2\wr_detect$10[0:0]$11566 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11170 1'1 + assign $4\wr_detect$10[0:0]$11568 1'1 case - assign $4\wr_detect$10[0:0]$11170 $3\wr_detect$10[0:0]$11169 + assign $4\wr_detect$10[0:0]$11568 $3\wr_detect$10[0:0]$11567 end case - assign $1\wr_detect$10[0:0]$11167 1'0 + assign $1\wr_detect$10[0:0]$11565 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11166 + update \wr_detect$10 $0\wr_detect$10[0:0]$11564 end - attribute \src "libresoc.v:168824.3-168863.6" - process $proc$libresoc.v:168824$11171 + attribute \src "libresoc.v:172249.3-172288.6" + process $proc$libresoc.v:172249$11569 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11172 $6\r26__data_o$next[3:0]$11178 - attribute \src "libresoc.v:168825.5-168825.29" + assign $0\r26__data_o$next[3:0]$11570 $6\r26__data_o$next[3:0]$11576 + attribute \src "libresoc.v:172250.5-172250.29" switch \initial - attribute \src "libresoc.v:168825.9-168825.17" + attribute \src "libresoc.v:172250.9-172250.17" case 1'1 case end @@ -348965,66 +356895,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11173 $5\r26__data_o$next[3:0]$11177 + assign $1\r26__data_o$next[3:0]$11571 $5\r26__data_o$next[3:0]$11575 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11174 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11572 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11174 4'0000 + assign $2\r26__data_o$next[3:0]$11572 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11175 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11573 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11175 $2\r26__data_o$next[3:0]$11174 + assign $3\r26__data_o$next[3:0]$11573 $2\r26__data_o$next[3:0]$11572 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11176 \w6__data_i + assign $4\r26__data_o$next[3:0]$11574 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11176 $3\r26__data_o$next[3:0]$11175 + assign $4\r26__data_o$next[3:0]$11574 $3\r26__data_o$next[3:0]$11573 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11177 \reg + assign $5\r26__data_o$next[3:0]$11575 \reg case - assign $5\r26__data_o$next[3:0]$11177 $4\r26__data_o$next[3:0]$11176 + assign $5\r26__data_o$next[3:0]$11575 $4\r26__data_o$next[3:0]$11574 end case - assign $1\r26__data_o$next[3:0]$11173 4'0000 + assign $1\r26__data_o$next[3:0]$11571 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11178 4'0000 + assign $6\r26__data_o$next[3:0]$11576 4'0000 case - assign $6\r26__data_o$next[3:0]$11178 $1\r26__data_o$next[3:0]$11173 + assign $6\r26__data_o$next[3:0]$11576 $1\r26__data_o$next[3:0]$11571 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11172 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11570 end - attribute \src "libresoc.v:168864.3-168893.6" - process $proc$libresoc.v:168864$11179 + attribute \src "libresoc.v:172289.3-172318.6" + process $proc$libresoc.v:172289$11577 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11180 $1\wr_detect$13[0:0]$11181 - attribute \src "libresoc.v:168865.5-168865.29" + assign $0\wr_detect$13[0:0]$11578 $1\wr_detect$13[0:0]$11579 + attribute \src "libresoc.v:172290.5-172290.29" switch \initial - attribute \src "libresoc.v:168865.9-168865.17" + attribute \src "libresoc.v:172290.9-172290.17" case 1'1 case end @@ -349036,217 +356966,217 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11181 $4\wr_detect$13[0:0]$11184 + assign $1\wr_detect$13[0:0]$11579 $4\wr_detect$13[0:0]$11582 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11182 1'1 + assign $2\wr_detect$13[0:0]$11580 1'1 case - assign $2\wr_detect$13[0:0]$11182 1'0 + assign $2\wr_detect$13[0:0]$11580 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11183 1'1 + assign $3\wr_detect$13[0:0]$11581 1'1 case - assign $3\wr_detect$13[0:0]$11183 $2\wr_detect$13[0:0]$11182 + assign $3\wr_detect$13[0:0]$11581 $2\wr_detect$13[0:0]$11580 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11184 1'1 + assign $4\wr_detect$13[0:0]$11582 1'1 case - assign $4\wr_detect$13[0:0]$11184 $3\wr_detect$13[0:0]$11183 + assign $4\wr_detect$13[0:0]$11582 $3\wr_detect$13[0:0]$11581 end case - assign $1\wr_detect$13[0:0]$11181 1'0 + assign $1\wr_detect$13[0:0]$11579 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11180 + update \wr_detect$13 $0\wr_detect$13[0:0]$11578 end - connect \$9 $not$libresoc.v:168500$11103_Y - connect \$12 $not$libresoc.v:168501$11104_Y - connect \$1 $not$libresoc.v:168502$11105_Y - connect \$3 $not$libresoc.v:168503$11106_Y - connect \$6 $not$libresoc.v:168504$11107_Y + connect \$9 $not$libresoc.v:171925$11501_Y + connect \$12 $not$libresoc.v:171926$11502_Y + connect \$1 $not$libresoc.v:171927$11503_Y + connect \$3 $not$libresoc.v:171928$11504_Y + connect \$6 $not$libresoc.v:171929$11505_Y end -attribute \src "libresoc.v:168898.1-169369.10" +attribute \src "libresoc.v:172323.1-172794.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:168899.7-168899.20" + attribute \src "libresoc.v:172324.7-172324.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $0\r27__data_o$next[3:0]$11261 - attribute \src "libresoc.v:168982.3-168983.39" + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $0\r27__data_o$next[3:0]$11659 + attribute \src "libresoc.v:172407.3-172408.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $0\r7__data_o$next[3:0]$11247 - attribute \src "libresoc.v:168984.3-168985.37" + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $0\r7__data_o$next[3:0]$11645 + attribute \src "libresoc.v:172409.3-172410.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:169062.3-169088.6" - wire width 4 $0\reg$next[3:0]$11213 - attribute \src "libresoc.v:168980.3-168981.25" + attribute \src "libresoc.v:172487.3-172513.6" + wire width 4 $0\reg$next[3:0]$11611 + attribute \src "libresoc.v:172405.3-172406.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $0\src17__data_o$next[3:0]$11204 - attribute \src "libresoc.v:168990.3-168991.43" + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $0\src17__data_o$next[3:0]$11602 + attribute \src "libresoc.v:172415.3-172416.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $0\src27__data_o$next[3:0]$11219 - attribute \src "libresoc.v:168988.3-168989.43" + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $0\src27__data_o$next[3:0]$11617 + attribute \src "libresoc.v:172413.3-172414.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $0\src37__data_o$next[3:0]$11233 - attribute \src "libresoc.v:168986.3-168987.43" + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $0\src37__data_o$next[3:0]$11631 + attribute \src "libresoc.v:172411.3-172412.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:169269.3-169298.6" - wire $0\wr_detect$10[0:0]$11255 - attribute \src "libresoc.v:169339.3-169368.6" - wire $0\wr_detect$13[0:0]$11269 - attribute \src "libresoc.v:169129.3-169158.6" - wire $0\wr_detect$4[0:0]$11227 - attribute \src "libresoc.v:169199.3-169228.6" - wire $0\wr_detect$7[0:0]$11241 - attribute \src "libresoc.v:169032.3-169061.6" + attribute \src "libresoc.v:172694.3-172723.6" + wire $0\wr_detect$10[0:0]$11653 + attribute \src "libresoc.v:172764.3-172793.6" + wire $0\wr_detect$13[0:0]$11667 + attribute \src "libresoc.v:172554.3-172583.6" + wire $0\wr_detect$4[0:0]$11625 + attribute \src "libresoc.v:172624.3-172653.6" + wire $0\wr_detect$7[0:0]$11639 + attribute \src "libresoc.v:172457.3-172486.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $1\r27__data_o$next[3:0]$11262 - attribute \src "libresoc.v:168924.13-168924.31" + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $1\r27__data_o$next[3:0]$11660 + attribute \src "libresoc.v:172349.13-172349.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $1\r7__data_o$next[3:0]$11248 - attribute \src "libresoc.v:168931.13-168931.30" + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $1\r7__data_o$next[3:0]$11646 + attribute \src "libresoc.v:172356.13-172356.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:169062.3-169088.6" - wire width 4 $1\reg$next[3:0]$11214 - attribute \src "libresoc.v:168937.13-168937.25" + attribute \src "libresoc.v:172487.3-172513.6" + wire width 4 $1\reg$next[3:0]$11612 + attribute \src "libresoc.v:172362.13-172362.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $1\src17__data_o$next[3:0]$11205 - attribute \src "libresoc.v:168942.13-168942.33" + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $1\src17__data_o$next[3:0]$11603 + attribute \src "libresoc.v:172367.13-172367.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $1\src27__data_o$next[3:0]$11220 - attribute \src "libresoc.v:168949.13-168949.33" + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $1\src27__data_o$next[3:0]$11618 + attribute \src "libresoc.v:172374.13-172374.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $1\src37__data_o$next[3:0]$11234 - attribute \src "libresoc.v:168956.13-168956.33" + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $1\src37__data_o$next[3:0]$11632 + attribute \src "libresoc.v:172381.13-172381.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:169269.3-169298.6" - wire $1\wr_detect$10[0:0]$11256 - attribute \src "libresoc.v:169339.3-169368.6" - wire $1\wr_detect$13[0:0]$11270 - attribute \src "libresoc.v:169129.3-169158.6" - wire $1\wr_detect$4[0:0]$11228 - attribute \src "libresoc.v:169199.3-169228.6" - wire $1\wr_detect$7[0:0]$11242 - attribute \src "libresoc.v:169032.3-169061.6" + attribute \src "libresoc.v:172694.3-172723.6" + wire $1\wr_detect$10[0:0]$11654 + attribute \src "libresoc.v:172764.3-172793.6" + wire $1\wr_detect$13[0:0]$11668 + attribute \src "libresoc.v:172554.3-172583.6" + wire $1\wr_detect$4[0:0]$11626 + attribute \src "libresoc.v:172624.3-172653.6" + wire $1\wr_detect$7[0:0]$11640 + attribute \src "libresoc.v:172457.3-172486.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $2\r27__data_o$next[3:0]$11263 - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $2\r7__data_o$next[3:0]$11249 - attribute \src "libresoc.v:169062.3-169088.6" - wire width 4 $2\reg$next[3:0]$11215 - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $2\src17__data_o$next[3:0]$11206 - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $2\src27__data_o$next[3:0]$11221 - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $2\src37__data_o$next[3:0]$11235 - attribute \src "libresoc.v:169269.3-169298.6" - wire $2\wr_detect$10[0:0]$11257 - attribute \src "libresoc.v:169339.3-169368.6" - wire $2\wr_detect$13[0:0]$11271 - attribute \src "libresoc.v:169129.3-169158.6" - wire $2\wr_detect$4[0:0]$11229 - attribute \src "libresoc.v:169199.3-169228.6" - wire $2\wr_detect$7[0:0]$11243 - attribute \src "libresoc.v:169032.3-169061.6" + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $2\r27__data_o$next[3:0]$11661 + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $2\r7__data_o$next[3:0]$11647 + attribute \src "libresoc.v:172487.3-172513.6" + wire width 4 $2\reg$next[3:0]$11613 + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $2\src17__data_o$next[3:0]$11604 + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $2\src27__data_o$next[3:0]$11619 + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $2\src37__data_o$next[3:0]$11633 + attribute \src "libresoc.v:172694.3-172723.6" + wire $2\wr_detect$10[0:0]$11655 + attribute \src "libresoc.v:172764.3-172793.6" + wire $2\wr_detect$13[0:0]$11669 + attribute \src "libresoc.v:172554.3-172583.6" + wire $2\wr_detect$4[0:0]$11627 + attribute \src "libresoc.v:172624.3-172653.6" + wire $2\wr_detect$7[0:0]$11641 + attribute \src "libresoc.v:172457.3-172486.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $3\r27__data_o$next[3:0]$11264 - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $3\r7__data_o$next[3:0]$11250 - attribute \src "libresoc.v:169062.3-169088.6" - wire width 4 $3\reg$next[3:0]$11216 - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $3\src17__data_o$next[3:0]$11207 - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $3\src27__data_o$next[3:0]$11222 - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $3\src37__data_o$next[3:0]$11236 - attribute \src "libresoc.v:169269.3-169298.6" - wire $3\wr_detect$10[0:0]$11258 - attribute \src "libresoc.v:169339.3-169368.6" - wire $3\wr_detect$13[0:0]$11272 - attribute \src "libresoc.v:169129.3-169158.6" - wire $3\wr_detect$4[0:0]$11230 - attribute \src "libresoc.v:169199.3-169228.6" - wire $3\wr_detect$7[0:0]$11244 - attribute \src "libresoc.v:169032.3-169061.6" + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $3\r27__data_o$next[3:0]$11662 + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $3\r7__data_o$next[3:0]$11648 + attribute \src "libresoc.v:172487.3-172513.6" + wire width 4 $3\reg$next[3:0]$11614 + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $3\src17__data_o$next[3:0]$11605 + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $3\src27__data_o$next[3:0]$11620 + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $3\src37__data_o$next[3:0]$11634 + attribute \src "libresoc.v:172694.3-172723.6" + wire $3\wr_detect$10[0:0]$11656 + attribute \src "libresoc.v:172764.3-172793.6" + wire $3\wr_detect$13[0:0]$11670 + attribute \src "libresoc.v:172554.3-172583.6" + wire $3\wr_detect$4[0:0]$11628 + attribute \src "libresoc.v:172624.3-172653.6" + wire $3\wr_detect$7[0:0]$11642 + attribute \src "libresoc.v:172457.3-172486.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $4\r27__data_o$next[3:0]$11265 - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $4\r7__data_o$next[3:0]$11251 - attribute \src "libresoc.v:169062.3-169088.6" - wire width 4 $4\reg$next[3:0]$11217 - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $4\src17__data_o$next[3:0]$11208 - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $4\src27__data_o$next[3:0]$11223 - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $4\src37__data_o$next[3:0]$11237 - attribute \src "libresoc.v:169269.3-169298.6" - wire $4\wr_detect$10[0:0]$11259 - attribute \src "libresoc.v:169339.3-169368.6" - wire $4\wr_detect$13[0:0]$11273 - attribute \src "libresoc.v:169129.3-169158.6" - wire $4\wr_detect$4[0:0]$11231 - attribute \src "libresoc.v:169199.3-169228.6" - wire $4\wr_detect$7[0:0]$11245 - attribute \src "libresoc.v:169032.3-169061.6" + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $4\r27__data_o$next[3:0]$11663 + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $4\r7__data_o$next[3:0]$11649 + attribute \src "libresoc.v:172487.3-172513.6" + wire width 4 $4\reg$next[3:0]$11615 + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $4\src17__data_o$next[3:0]$11606 + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $4\src27__data_o$next[3:0]$11621 + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $4\src37__data_o$next[3:0]$11635 + attribute \src "libresoc.v:172694.3-172723.6" + wire $4\wr_detect$10[0:0]$11657 + attribute \src "libresoc.v:172764.3-172793.6" + wire $4\wr_detect$13[0:0]$11671 + attribute \src "libresoc.v:172554.3-172583.6" + wire $4\wr_detect$4[0:0]$11629 + attribute \src "libresoc.v:172624.3-172653.6" + wire $4\wr_detect$7[0:0]$11643 + attribute \src "libresoc.v:172457.3-172486.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $5\r27__data_o$next[3:0]$11266 - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $5\r7__data_o$next[3:0]$11252 - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $5\src17__data_o$next[3:0]$11209 - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $5\src27__data_o$next[3:0]$11224 - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $5\src37__data_o$next[3:0]$11238 - attribute \src "libresoc.v:169299.3-169338.6" - wire width 4 $6\r27__data_o$next[3:0]$11267 - attribute \src "libresoc.v:169229.3-169268.6" - wire width 4 $6\r7__data_o$next[3:0]$11253 - attribute \src "libresoc.v:168992.3-169031.6" - wire width 4 $6\src17__data_o$next[3:0]$11210 - attribute \src "libresoc.v:169089.3-169128.6" - wire width 4 $6\src27__data_o$next[3:0]$11225 - attribute \src "libresoc.v:169159.3-169198.6" - wire width 4 $6\src37__data_o$next[3:0]$11239 - attribute \src "libresoc.v:168975.17-168975.104" - wire $not$libresoc.v:168975$11192_Y - attribute \src "libresoc.v:168976.18-168976.105" - wire $not$libresoc.v:168976$11193_Y - attribute \src "libresoc.v:168977.17-168977.100" - wire $not$libresoc.v:168977$11194_Y - attribute \src "libresoc.v:168978.17-168978.103" - wire $not$libresoc.v:168978$11195_Y - attribute \src "libresoc.v:168979.17-168979.103" - wire $not$libresoc.v:168979$11196_Y + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $5\r27__data_o$next[3:0]$11664 + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $5\r7__data_o$next[3:0]$11650 + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $5\src17__data_o$next[3:0]$11607 + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $5\src27__data_o$next[3:0]$11622 + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $5\src37__data_o$next[3:0]$11636 + attribute \src "libresoc.v:172724.3-172763.6" + wire width 4 $6\r27__data_o$next[3:0]$11665 + attribute \src "libresoc.v:172654.3-172693.6" + wire width 4 $6\r7__data_o$next[3:0]$11651 + attribute \src "libresoc.v:172417.3-172456.6" + wire width 4 $6\src17__data_o$next[3:0]$11608 + attribute \src "libresoc.v:172514.3-172553.6" + wire width 4 $6\src27__data_o$next[3:0]$11623 + attribute \src "libresoc.v:172584.3-172623.6" + wire width 4 $6\src37__data_o$next[3:0]$11637 + attribute \src "libresoc.v:172400.17-172400.104" + wire $not$libresoc.v:172400$11590_Y + attribute \src "libresoc.v:172401.18-172401.105" + wire $not$libresoc.v:172401$11591_Y + attribute \src "libresoc.v:172402.17-172402.100" + wire $not$libresoc.v:172402$11592_Y + attribute \src "libresoc.v:172403.17-172403.103" + wire $not$libresoc.v:172403$11593_Y + attribute \src "libresoc.v:172404.17-172404.103" + wire $not$libresoc.v:172404$11594_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -349257,9 +357187,9 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 input 9 \dest17__data_i @@ -349269,7 +357199,7 @@ module \reg_7 wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire input 10 \dest27__wen - attribute \src "libresoc.v:168899.7-168899.15" + attribute \src "libresoc.v:172324.7-172324.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 output 14 \r27__data_o @@ -349320,152 +357250,152 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168975$11192 + cell $not $not$libresoc.v:172400$11590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168975$11192_Y + connect \Y $not$libresoc.v:172400$11590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168976$11193 + cell $not $not$libresoc.v:172401$11591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:168976$11193_Y + connect \Y $not$libresoc.v:172401$11591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168977$11194 + cell $not $not$libresoc.v:172402$11592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:168977$11194_Y + connect \Y $not$libresoc.v:172402$11592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168978$11195 + cell $not $not$libresoc.v:172403$11593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168978$11195_Y + connect \Y $not$libresoc.v:172403$11593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168979$11196 + cell $not $not$libresoc.v:172404$11594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168979$11196_Y + connect \Y $not$libresoc.v:172404$11594_Y end - attribute \src "libresoc.v:168899.7-168899.20" - process $proc$libresoc.v:168899$11274 + attribute \src "libresoc.v:172324.7-172324.20" + process $proc$libresoc.v:172324$11672 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168924.13-168924.31" - process $proc$libresoc.v:168924$11275 + attribute \src "libresoc.v:172349.13-172349.31" + process $proc$libresoc.v:172349$11673 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:168931.13-168931.30" - process $proc$libresoc.v:168931$11276 + attribute \src "libresoc.v:172356.13-172356.30" + process $proc$libresoc.v:172356$11674 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:168937.13-168937.25" - process $proc$libresoc.v:168937$11277 + attribute \src "libresoc.v:172362.13-172362.25" + process $proc$libresoc.v:172362$11675 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:168942.13-168942.33" - process $proc$libresoc.v:168942$11278 + attribute \src "libresoc.v:172367.13-172367.33" + process $proc$libresoc.v:172367$11676 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:168949.13-168949.33" - process $proc$libresoc.v:168949$11279 + attribute \src "libresoc.v:172374.13-172374.33" + process $proc$libresoc.v:172374$11677 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:168956.13-168956.33" - process $proc$libresoc.v:168956$11280 + attribute \src "libresoc.v:172381.13-172381.33" + process $proc$libresoc.v:172381$11678 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:168980.3-168981.25" - process $proc$libresoc.v:168980$11197 + attribute \src "libresoc.v:172405.3-172406.25" + process $proc$libresoc.v:172405$11595 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:168982.3-168983.39" - process $proc$libresoc.v:168982$11198 + attribute \src "libresoc.v:172407.3-172408.39" + process $proc$libresoc.v:172407$11596 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:168984.3-168985.37" - process $proc$libresoc.v:168984$11199 + attribute \src "libresoc.v:172409.3-172410.37" + process $proc$libresoc.v:172409$11597 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:168986.3-168987.43" - process $proc$libresoc.v:168986$11200 + attribute \src "libresoc.v:172411.3-172412.43" + process $proc$libresoc.v:172411$11598 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:168988.3-168989.43" - process $proc$libresoc.v:168988$11201 + attribute \src "libresoc.v:172413.3-172414.43" + process $proc$libresoc.v:172413$11599 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:168990.3-168991.43" - process $proc$libresoc.v:168990$11202 + attribute \src "libresoc.v:172415.3-172416.43" + process $proc$libresoc.v:172415$11600 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:168992.3-169031.6" - process $proc$libresoc.v:168992$11203 + attribute \src "libresoc.v:172417.3-172456.6" + process $proc$libresoc.v:172417$11601 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11204 $6\src17__data_o$next[3:0]$11210 - attribute \src "libresoc.v:168993.5-168993.29" + assign $0\src17__data_o$next[3:0]$11602 $6\src17__data_o$next[3:0]$11608 + attribute \src "libresoc.v:172418.5-172418.29" switch \initial - attribute \src "libresoc.v:168993.9-168993.17" + attribute \src "libresoc.v:172418.9-172418.17" case 1'1 case end @@ -349477,66 +357407,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11205 $5\src17__data_o$next[3:0]$11209 + assign $1\src17__data_o$next[3:0]$11603 $5\src17__data_o$next[3:0]$11607 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11206 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11604 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11206 4'0000 + assign $2\src17__data_o$next[3:0]$11604 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11207 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11605 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11207 $2\src17__data_o$next[3:0]$11206 + assign $3\src17__data_o$next[3:0]$11605 $2\src17__data_o$next[3:0]$11604 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11208 \w7__data_i + assign $4\src17__data_o$next[3:0]$11606 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11208 $3\src17__data_o$next[3:0]$11207 + assign $4\src17__data_o$next[3:0]$11606 $3\src17__data_o$next[3:0]$11605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11209 \reg + assign $5\src17__data_o$next[3:0]$11607 \reg case - assign $5\src17__data_o$next[3:0]$11209 $4\src17__data_o$next[3:0]$11208 + assign $5\src17__data_o$next[3:0]$11607 $4\src17__data_o$next[3:0]$11606 end case - assign $1\src17__data_o$next[3:0]$11205 4'0000 + assign $1\src17__data_o$next[3:0]$11603 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11210 4'0000 + assign $6\src17__data_o$next[3:0]$11608 4'0000 case - assign $6\src17__data_o$next[3:0]$11210 $1\src17__data_o$next[3:0]$11205 + assign $6\src17__data_o$next[3:0]$11608 $1\src17__data_o$next[3:0]$11603 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11204 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11602 end - attribute \src "libresoc.v:169032.3-169061.6" - process $proc$libresoc.v:169032$11211 + attribute \src "libresoc.v:172457.3-172486.6" + process $proc$libresoc.v:172457$11609 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169033.5-169033.29" + attribute \src "libresoc.v:172458.5-172458.29" switch \initial - attribute \src "libresoc.v:169033.9-169033.17" + attribute \src "libresoc.v:172458.9-172458.17" case 1'1 case end @@ -349582,17 +357512,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:169062.3-169088.6" - process $proc$libresoc.v:169062$11212 + attribute \src "libresoc.v:172487.3-172513.6" + process $proc$libresoc.v:172487$11610 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11213 $4\reg$next[3:0]$11217 - attribute \src "libresoc.v:169063.5-169063.29" + assign $0\reg$next[3:0]$11611 $4\reg$next[3:0]$11615 + attribute \src "libresoc.v:172488.5-172488.29" switch \initial - attribute \src "libresoc.v:169063.9-169063.17" + attribute \src "libresoc.v:172488.9-172488.17" case 1'1 case end @@ -349601,49 +357531,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11214 \dest17__data_i + assign $1\reg$next[3:0]$11612 \dest17__data_i case - assign $1\reg$next[3:0]$11214 \reg + assign $1\reg$next[3:0]$11612 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11215 \dest27__data_i + assign $2\reg$next[3:0]$11613 \dest27__data_i case - assign $2\reg$next[3:0]$11215 $1\reg$next[3:0]$11214 + assign $2\reg$next[3:0]$11613 $1\reg$next[3:0]$11612 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11216 \w7__data_i + assign $3\reg$next[3:0]$11614 \w7__data_i case - assign $3\reg$next[3:0]$11216 $2\reg$next[3:0]$11215 + assign $3\reg$next[3:0]$11614 $2\reg$next[3:0]$11613 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11217 4'0000 + assign $4\reg$next[3:0]$11615 4'0000 case - assign $4\reg$next[3:0]$11217 $3\reg$next[3:0]$11216 + assign $4\reg$next[3:0]$11615 $3\reg$next[3:0]$11614 end sync always - update \reg$next $0\reg$next[3:0]$11213 + update \reg$next $0\reg$next[3:0]$11611 end - attribute \src "libresoc.v:169089.3-169128.6" - process $proc$libresoc.v:169089$11218 + attribute \src "libresoc.v:172514.3-172553.6" + process $proc$libresoc.v:172514$11616 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11219 $6\src27__data_o$next[3:0]$11225 - attribute \src "libresoc.v:169090.5-169090.29" + assign $0\src27__data_o$next[3:0]$11617 $6\src27__data_o$next[3:0]$11623 + attribute \src "libresoc.v:172515.5-172515.29" switch \initial - attribute \src "libresoc.v:169090.9-169090.17" + attribute \src "libresoc.v:172515.9-172515.17" case 1'1 case end @@ -349655,66 +357585,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11220 $5\src27__data_o$next[3:0]$11224 + assign $1\src27__data_o$next[3:0]$11618 $5\src27__data_o$next[3:0]$11622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11221 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11619 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11221 4'0000 + assign $2\src27__data_o$next[3:0]$11619 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11222 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11620 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11222 $2\src27__data_o$next[3:0]$11221 + assign $3\src27__data_o$next[3:0]$11620 $2\src27__data_o$next[3:0]$11619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11223 \w7__data_i + assign $4\src27__data_o$next[3:0]$11621 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11223 $3\src27__data_o$next[3:0]$11222 + assign $4\src27__data_o$next[3:0]$11621 $3\src27__data_o$next[3:0]$11620 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11224 \reg + assign $5\src27__data_o$next[3:0]$11622 \reg case - assign $5\src27__data_o$next[3:0]$11224 $4\src27__data_o$next[3:0]$11223 + assign $5\src27__data_o$next[3:0]$11622 $4\src27__data_o$next[3:0]$11621 end case - assign $1\src27__data_o$next[3:0]$11220 4'0000 + assign $1\src27__data_o$next[3:0]$11618 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11225 4'0000 + assign $6\src27__data_o$next[3:0]$11623 4'0000 case - assign $6\src27__data_o$next[3:0]$11225 $1\src27__data_o$next[3:0]$11220 + assign $6\src27__data_o$next[3:0]$11623 $1\src27__data_o$next[3:0]$11618 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11219 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11617 end - attribute \src "libresoc.v:169129.3-169158.6" - process $proc$libresoc.v:169129$11226 + attribute \src "libresoc.v:172554.3-172583.6" + process $proc$libresoc.v:172554$11624 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11227 $1\wr_detect$4[0:0]$11228 - attribute \src "libresoc.v:169130.5-169130.29" + assign $0\wr_detect$4[0:0]$11625 $1\wr_detect$4[0:0]$11626 + attribute \src "libresoc.v:172555.5-172555.29" switch \initial - attribute \src "libresoc.v:169130.9-169130.17" + attribute \src "libresoc.v:172555.9-172555.17" case 1'1 case end @@ -349726,49 +357656,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11228 $4\wr_detect$4[0:0]$11231 + assign $1\wr_detect$4[0:0]$11626 $4\wr_detect$4[0:0]$11629 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11229 1'1 + assign $2\wr_detect$4[0:0]$11627 1'1 case - assign $2\wr_detect$4[0:0]$11229 1'0 + assign $2\wr_detect$4[0:0]$11627 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11230 1'1 + assign $3\wr_detect$4[0:0]$11628 1'1 case - assign $3\wr_detect$4[0:0]$11230 $2\wr_detect$4[0:0]$11229 + assign $3\wr_detect$4[0:0]$11628 $2\wr_detect$4[0:0]$11627 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11231 1'1 + assign $4\wr_detect$4[0:0]$11629 1'1 case - assign $4\wr_detect$4[0:0]$11231 $3\wr_detect$4[0:0]$11230 + assign $4\wr_detect$4[0:0]$11629 $3\wr_detect$4[0:0]$11628 end case - assign $1\wr_detect$4[0:0]$11228 1'0 + assign $1\wr_detect$4[0:0]$11626 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11227 + update \wr_detect$4 $0\wr_detect$4[0:0]$11625 end - attribute \src "libresoc.v:169159.3-169198.6" - process $proc$libresoc.v:169159$11232 + attribute \src "libresoc.v:172584.3-172623.6" + process $proc$libresoc.v:172584$11630 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11233 $6\src37__data_o$next[3:0]$11239 - attribute \src "libresoc.v:169160.5-169160.29" + assign $0\src37__data_o$next[3:0]$11631 $6\src37__data_o$next[3:0]$11637 + attribute \src "libresoc.v:172585.5-172585.29" switch \initial - attribute \src "libresoc.v:169160.9-169160.17" + attribute \src "libresoc.v:172585.9-172585.17" case 1'1 case end @@ -349780,66 +357710,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11234 $5\src37__data_o$next[3:0]$11238 + assign $1\src37__data_o$next[3:0]$11632 $5\src37__data_o$next[3:0]$11636 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11235 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11633 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11235 4'0000 + assign $2\src37__data_o$next[3:0]$11633 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11236 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11634 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11236 $2\src37__data_o$next[3:0]$11235 + assign $3\src37__data_o$next[3:0]$11634 $2\src37__data_o$next[3:0]$11633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11237 \w7__data_i + assign $4\src37__data_o$next[3:0]$11635 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11237 $3\src37__data_o$next[3:0]$11236 + assign $4\src37__data_o$next[3:0]$11635 $3\src37__data_o$next[3:0]$11634 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11238 \reg + assign $5\src37__data_o$next[3:0]$11636 \reg case - assign $5\src37__data_o$next[3:0]$11238 $4\src37__data_o$next[3:0]$11237 + assign $5\src37__data_o$next[3:0]$11636 $4\src37__data_o$next[3:0]$11635 end case - assign $1\src37__data_o$next[3:0]$11234 4'0000 + assign $1\src37__data_o$next[3:0]$11632 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11239 4'0000 + assign $6\src37__data_o$next[3:0]$11637 4'0000 case - assign $6\src37__data_o$next[3:0]$11239 $1\src37__data_o$next[3:0]$11234 + assign $6\src37__data_o$next[3:0]$11637 $1\src37__data_o$next[3:0]$11632 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11233 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11631 end - attribute \src "libresoc.v:169199.3-169228.6" - process $proc$libresoc.v:169199$11240 + attribute \src "libresoc.v:172624.3-172653.6" + process $proc$libresoc.v:172624$11638 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11241 $1\wr_detect$7[0:0]$11242 - attribute \src "libresoc.v:169200.5-169200.29" + assign $0\wr_detect$7[0:0]$11639 $1\wr_detect$7[0:0]$11640 + attribute \src "libresoc.v:172625.5-172625.29" switch \initial - attribute \src "libresoc.v:169200.9-169200.17" + attribute \src "libresoc.v:172625.9-172625.17" case 1'1 case end @@ -349851,49 +357781,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11242 $4\wr_detect$7[0:0]$11245 + assign $1\wr_detect$7[0:0]$11640 $4\wr_detect$7[0:0]$11643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11243 1'1 + assign $2\wr_detect$7[0:0]$11641 1'1 case - assign $2\wr_detect$7[0:0]$11243 1'0 + assign $2\wr_detect$7[0:0]$11641 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11244 1'1 + assign $3\wr_detect$7[0:0]$11642 1'1 case - assign $3\wr_detect$7[0:0]$11244 $2\wr_detect$7[0:0]$11243 + assign $3\wr_detect$7[0:0]$11642 $2\wr_detect$7[0:0]$11641 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11245 1'1 + assign $4\wr_detect$7[0:0]$11643 1'1 case - assign $4\wr_detect$7[0:0]$11245 $3\wr_detect$7[0:0]$11244 + assign $4\wr_detect$7[0:0]$11643 $3\wr_detect$7[0:0]$11642 end case - assign $1\wr_detect$7[0:0]$11242 1'0 + assign $1\wr_detect$7[0:0]$11640 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11241 + update \wr_detect$7 $0\wr_detect$7[0:0]$11639 end - attribute \src "libresoc.v:169229.3-169268.6" - process $proc$libresoc.v:169229$11246 + attribute \src "libresoc.v:172654.3-172693.6" + process $proc$libresoc.v:172654$11644 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11247 $6\r7__data_o$next[3:0]$11253 - attribute \src "libresoc.v:169230.5-169230.29" + assign $0\r7__data_o$next[3:0]$11645 $6\r7__data_o$next[3:0]$11651 + attribute \src "libresoc.v:172655.5-172655.29" switch \initial - attribute \src "libresoc.v:169230.9-169230.17" + attribute \src "libresoc.v:172655.9-172655.17" case 1'1 case end @@ -349905,66 +357835,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11248 $5\r7__data_o$next[3:0]$11252 + assign $1\r7__data_o$next[3:0]$11646 $5\r7__data_o$next[3:0]$11650 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11249 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11647 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11249 4'0000 + assign $2\r7__data_o$next[3:0]$11647 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11250 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11648 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11250 $2\r7__data_o$next[3:0]$11249 + assign $3\r7__data_o$next[3:0]$11648 $2\r7__data_o$next[3:0]$11647 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11251 \w7__data_i + assign $4\r7__data_o$next[3:0]$11649 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11251 $3\r7__data_o$next[3:0]$11250 + assign $4\r7__data_o$next[3:0]$11649 $3\r7__data_o$next[3:0]$11648 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11252 \reg + assign $5\r7__data_o$next[3:0]$11650 \reg case - assign $5\r7__data_o$next[3:0]$11252 $4\r7__data_o$next[3:0]$11251 + assign $5\r7__data_o$next[3:0]$11650 $4\r7__data_o$next[3:0]$11649 end case - assign $1\r7__data_o$next[3:0]$11248 4'0000 + assign $1\r7__data_o$next[3:0]$11646 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11253 4'0000 + assign $6\r7__data_o$next[3:0]$11651 4'0000 case - assign $6\r7__data_o$next[3:0]$11253 $1\r7__data_o$next[3:0]$11248 + assign $6\r7__data_o$next[3:0]$11651 $1\r7__data_o$next[3:0]$11646 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11247 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11645 end - attribute \src "libresoc.v:169269.3-169298.6" - process $proc$libresoc.v:169269$11254 + attribute \src "libresoc.v:172694.3-172723.6" + process $proc$libresoc.v:172694$11652 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11255 $1\wr_detect$10[0:0]$11256 - attribute \src "libresoc.v:169270.5-169270.29" + assign $0\wr_detect$10[0:0]$11653 $1\wr_detect$10[0:0]$11654 + attribute \src "libresoc.v:172695.5-172695.29" switch \initial - attribute \src "libresoc.v:169270.9-169270.17" + attribute \src "libresoc.v:172695.9-172695.17" case 1'1 case end @@ -349976,49 +357906,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11256 $4\wr_detect$10[0:0]$11259 + assign $1\wr_detect$10[0:0]$11654 $4\wr_detect$10[0:0]$11657 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11257 1'1 + assign $2\wr_detect$10[0:0]$11655 1'1 case - assign $2\wr_detect$10[0:0]$11257 1'0 + assign $2\wr_detect$10[0:0]$11655 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11258 1'1 + assign $3\wr_detect$10[0:0]$11656 1'1 case - assign $3\wr_detect$10[0:0]$11258 $2\wr_detect$10[0:0]$11257 + assign $3\wr_detect$10[0:0]$11656 $2\wr_detect$10[0:0]$11655 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11259 1'1 + assign $4\wr_detect$10[0:0]$11657 1'1 case - assign $4\wr_detect$10[0:0]$11259 $3\wr_detect$10[0:0]$11258 + assign $4\wr_detect$10[0:0]$11657 $3\wr_detect$10[0:0]$11656 end case - assign $1\wr_detect$10[0:0]$11256 1'0 + assign $1\wr_detect$10[0:0]$11654 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11255 + update \wr_detect$10 $0\wr_detect$10[0:0]$11653 end - attribute \src "libresoc.v:169299.3-169338.6" - process $proc$libresoc.v:169299$11260 + attribute \src "libresoc.v:172724.3-172763.6" + process $proc$libresoc.v:172724$11658 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11261 $6\r27__data_o$next[3:0]$11267 - attribute \src "libresoc.v:169300.5-169300.29" + assign $0\r27__data_o$next[3:0]$11659 $6\r27__data_o$next[3:0]$11665 + attribute \src "libresoc.v:172725.5-172725.29" switch \initial - attribute \src "libresoc.v:169300.9-169300.17" + attribute \src "libresoc.v:172725.9-172725.17" case 1'1 case end @@ -350030,66 +357960,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11262 $5\r27__data_o$next[3:0]$11266 + assign $1\r27__data_o$next[3:0]$11660 $5\r27__data_o$next[3:0]$11664 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11263 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11661 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11263 4'0000 + assign $2\r27__data_o$next[3:0]$11661 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11264 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11662 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11264 $2\r27__data_o$next[3:0]$11263 + assign $3\r27__data_o$next[3:0]$11662 $2\r27__data_o$next[3:0]$11661 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11265 \w7__data_i + assign $4\r27__data_o$next[3:0]$11663 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11265 $3\r27__data_o$next[3:0]$11264 + assign $4\r27__data_o$next[3:0]$11663 $3\r27__data_o$next[3:0]$11662 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11266 \reg + assign $5\r27__data_o$next[3:0]$11664 \reg case - assign $5\r27__data_o$next[3:0]$11266 $4\r27__data_o$next[3:0]$11265 + assign $5\r27__data_o$next[3:0]$11664 $4\r27__data_o$next[3:0]$11663 end case - assign $1\r27__data_o$next[3:0]$11262 4'0000 + assign $1\r27__data_o$next[3:0]$11660 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11267 4'0000 + assign $6\r27__data_o$next[3:0]$11665 4'0000 case - assign $6\r27__data_o$next[3:0]$11267 $1\r27__data_o$next[3:0]$11262 + assign $6\r27__data_o$next[3:0]$11665 $1\r27__data_o$next[3:0]$11660 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11261 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11659 end - attribute \src "libresoc.v:169339.3-169368.6" - process $proc$libresoc.v:169339$11268 + attribute \src "libresoc.v:172764.3-172793.6" + process $proc$libresoc.v:172764$11666 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11269 $1\wr_detect$13[0:0]$11270 - attribute \src "libresoc.v:169340.5-169340.29" + assign $0\wr_detect$13[0:0]$11667 $1\wr_detect$13[0:0]$11668 + attribute \src "libresoc.v:172765.5-172765.29" switch \initial - attribute \src "libresoc.v:169340.9-169340.17" + attribute \src "libresoc.v:172765.9-172765.17" case 1'1 case end @@ -350101,77 +358031,77 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11270 $4\wr_detect$13[0:0]$11273 + assign $1\wr_detect$13[0:0]$11668 $4\wr_detect$13[0:0]$11671 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11271 1'1 + assign $2\wr_detect$13[0:0]$11669 1'1 case - assign $2\wr_detect$13[0:0]$11271 1'0 + assign $2\wr_detect$13[0:0]$11669 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11272 1'1 + assign $3\wr_detect$13[0:0]$11670 1'1 case - assign $3\wr_detect$13[0:0]$11272 $2\wr_detect$13[0:0]$11271 + assign $3\wr_detect$13[0:0]$11670 $2\wr_detect$13[0:0]$11669 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11273 1'1 + assign $4\wr_detect$13[0:0]$11671 1'1 case - assign $4\wr_detect$13[0:0]$11273 $3\wr_detect$13[0:0]$11272 + assign $4\wr_detect$13[0:0]$11671 $3\wr_detect$13[0:0]$11670 end case - assign $1\wr_detect$13[0:0]$11270 1'0 + assign $1\wr_detect$13[0:0]$11668 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11269 + update \wr_detect$13 $0\wr_detect$13[0:0]$11667 end - connect \$9 $not$libresoc.v:168975$11192_Y - connect \$12 $not$libresoc.v:168976$11193_Y - connect \$1 $not$libresoc.v:168977$11194_Y - connect \$3 $not$libresoc.v:168978$11195_Y - connect \$6 $not$libresoc.v:168979$11196_Y + connect \$9 $not$libresoc.v:172400$11590_Y + connect \$12 $not$libresoc.v:172401$11591_Y + connect \$1 $not$libresoc.v:172402$11592_Y + connect \$3 $not$libresoc.v:172403$11593_Y + connect \$6 $not$libresoc.v:172404$11594_Y end -attribute \src "libresoc.v:169373.1-169431.10" +attribute \src "libresoc.v:172798.1-172856.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:169374.7-169374.20" + attribute \src "libresoc.v:172799.7-172799.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169419.3-169427.6" - wire width 5 $0\q_int$next[4:0]$11291 - attribute \src "libresoc.v:169417.3-169418.27" + attribute \src "libresoc.v:172844.3-172852.6" + wire width 5 $0\q_int$next[4:0]$11689 + attribute \src "libresoc.v:172842.3-172843.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:169419.3-169427.6" - wire width 5 $1\q_int$next[4:0]$11292 - attribute \src "libresoc.v:169396.13-169396.26" + attribute \src "libresoc.v:172844.3-172852.6" + wire width 5 $1\q_int$next[4:0]$11690 + attribute \src "libresoc.v:172821.13-172821.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:169409.17-169409.96" - wire width 5 $and$libresoc.v:169409$11281_Y - attribute \src "libresoc.v:169414.17-169414.96" - wire width 5 $and$libresoc.v:169414$11286_Y - attribute \src "libresoc.v:169411.18-169411.93" - wire width 5 $not$libresoc.v:169411$11283_Y - attribute \src "libresoc.v:169413.17-169413.92" - wire width 5 $not$libresoc.v:169413$11285_Y - attribute \src "libresoc.v:169416.17-169416.92" - wire width 5 $not$libresoc.v:169416$11288_Y - attribute \src "libresoc.v:169410.18-169410.98" - wire width 5 $or$libresoc.v:169410$11282_Y - attribute \src "libresoc.v:169412.18-169412.99" - wire width 5 $or$libresoc.v:169412$11284_Y - attribute \src "libresoc.v:169415.17-169415.97" - wire width 5 $or$libresoc.v:169415$11287_Y + attribute \src "libresoc.v:172834.17-172834.96" + wire width 5 $and$libresoc.v:172834$11679_Y + attribute \src "libresoc.v:172839.17-172839.96" + wire width 5 $and$libresoc.v:172839$11684_Y + attribute \src "libresoc.v:172836.18-172836.93" + wire width 5 $not$libresoc.v:172836$11681_Y + attribute \src "libresoc.v:172838.17-172838.92" + wire width 5 $not$libresoc.v:172838$11683_Y + attribute \src "libresoc.v:172841.17-172841.92" + wire width 5 $not$libresoc.v:172841$11686_Y + attribute \src "libresoc.v:172835.18-172835.98" + wire width 5 $or$libresoc.v:172835$11680_Y + attribute \src "libresoc.v:172837.18-172837.99" + wire width 5 $or$libresoc.v:172837$11682_Y + attribute \src "libresoc.v:172840.17-172840.97" + wire width 5 $or$libresoc.v:172840$11685_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -350188,11 +358118,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169374.7-169374.15" + attribute \src "libresoc.v:172799.7-172799.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int @@ -350209,7 +358139,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169409$11281 + cell $and $and$libresoc.v:172834$11679 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -350217,10 +358147,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169409$11281_Y + connect \Y $and$libresoc.v:172834$11679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169414$11286 + cell $and $and$libresoc.v:172839$11684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -350228,34 +358158,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169414$11286_Y + connect \Y $and$libresoc.v:172839$11684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169411$11283 + cell $not $not$libresoc.v:172836$11681 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:169411$11283_Y + connect \Y $not$libresoc.v:172836$11681_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169413$11285 + cell $not $not$libresoc.v:172838$11683 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:169413$11285_Y + connect \Y $not$libresoc.v:172838$11683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169416$11288 + cell $not $not$libresoc.v:172841$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:169416$11288_Y + connect \Y $not$libresoc.v:172841$11686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169410$11282 + cell $or $or$libresoc.v:172835$11680 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -350263,10 +358193,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169410$11282_Y + connect \Y $or$libresoc.v:172835$11680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169412$11284 + cell $or $or$libresoc.v:172837$11682 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -350274,10 +358204,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169412$11284_Y + connect \Y $or$libresoc.v:172837$11682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169415$11287 + cell $or $or$libresoc.v:172840$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -350285,39 +358215,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169415$11287_Y + connect \Y $or$libresoc.v:172840$11685_Y end - attribute \src "libresoc.v:169374.7-169374.20" - process $proc$libresoc.v:169374$11293 + attribute \src "libresoc.v:172799.7-172799.20" + process $proc$libresoc.v:172799$11691 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169396.13-169396.26" - process $proc$libresoc.v:169396$11294 + attribute \src "libresoc.v:172821.13-172821.26" + process $proc$libresoc.v:172821$11692 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:169417.3-169418.27" - process $proc$libresoc.v:169417$11289 + attribute \src "libresoc.v:172842.3-172843.27" + process $proc$libresoc.v:172842$11687 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:169419.3-169427.6" - process $proc$libresoc.v:169419$11290 + attribute \src "libresoc.v:172844.3-172852.6" + process $proc$libresoc.v:172844$11688 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11291 $1\q_int$next[4:0]$11292 - attribute \src "libresoc.v:169420.5-169420.29" + assign $0\q_int$next[4:0]$11689 $1\q_int$next[4:0]$11690 + attribute \src "libresoc.v:172845.5-172845.29" switch \initial - attribute \src "libresoc.v:169420.9-169420.17" + attribute \src "libresoc.v:172845.9-172845.17" case 1'1 case end @@ -350326,56 +358256,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11292 5'00000 + assign $1\q_int$next[4:0]$11690 5'00000 case - assign $1\q_int$next[4:0]$11292 \$5 + assign $1\q_int$next[4:0]$11690 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11291 + update \q_int$next $0\q_int$next[4:0]$11689 end - connect \$9 $and$libresoc.v:169409$11281_Y - connect \$11 $or$libresoc.v:169410$11282_Y - connect \$13 $not$libresoc.v:169411$11283_Y - connect \$15 $or$libresoc.v:169412$11284_Y - connect \$1 $not$libresoc.v:169413$11285_Y - connect \$3 $and$libresoc.v:169414$11286_Y - connect \$5 $or$libresoc.v:169415$11287_Y - connect \$7 $not$libresoc.v:169416$11288_Y + connect \$9 $and$libresoc.v:172834$11679_Y + connect \$11 $or$libresoc.v:172835$11680_Y + connect \$13 $not$libresoc.v:172836$11681_Y + connect \$15 $or$libresoc.v:172837$11682_Y + connect \$1 $not$libresoc.v:172838$11683_Y + connect \$3 $and$libresoc.v:172839$11684_Y + connect \$5 $or$libresoc.v:172840$11685_Y + connect \$7 $not$libresoc.v:172841$11686_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169435.1-169493.10" +attribute \src "libresoc.v:172860.1-172918.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" -module \req_l$100 - attribute \src "libresoc.v:169436.7-169436.20" +module \req_l$103 + attribute \src "libresoc.v:172861.7-172861.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169481.3-169489.6" - wire width 4 $0\q_int$next[3:0]$11305 - attribute \src "libresoc.v:169479.3-169480.27" + attribute \src "libresoc.v:172906.3-172914.6" + wire width 4 $0\q_int$next[3:0]$11703 + attribute \src "libresoc.v:172904.3-172905.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:169481.3-169489.6" - wire width 4 $1\q_int$next[3:0]$11306 - attribute \src "libresoc.v:169458.13-169458.25" + attribute \src "libresoc.v:172906.3-172914.6" + wire width 4 $1\q_int$next[3:0]$11704 + attribute \src "libresoc.v:172883.13-172883.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:169471.17-169471.96" - wire width 4 $and$libresoc.v:169471$11295_Y - attribute \src "libresoc.v:169476.17-169476.96" - wire width 4 $and$libresoc.v:169476$11300_Y - attribute \src "libresoc.v:169473.18-169473.93" - wire width 4 $not$libresoc.v:169473$11297_Y - attribute \src "libresoc.v:169475.17-169475.92" - wire width 4 $not$libresoc.v:169475$11299_Y - attribute \src "libresoc.v:169478.17-169478.92" - wire width 4 $not$libresoc.v:169478$11302_Y - attribute \src "libresoc.v:169472.18-169472.98" - wire width 4 $or$libresoc.v:169472$11296_Y - attribute \src "libresoc.v:169474.18-169474.99" - wire width 4 $or$libresoc.v:169474$11298_Y - attribute \src "libresoc.v:169477.17-169477.97" - wire width 4 $or$libresoc.v:169477$11301_Y + attribute \src "libresoc.v:172896.17-172896.96" + wire width 4 $and$libresoc.v:172896$11693_Y + attribute \src "libresoc.v:172901.17-172901.96" + wire width 4 $and$libresoc.v:172901$11698_Y + attribute \src "libresoc.v:172898.18-172898.93" + wire width 4 $not$libresoc.v:172898$11695_Y + attribute \src "libresoc.v:172900.17-172900.92" + wire width 4 $not$libresoc.v:172900$11697_Y + attribute \src "libresoc.v:172903.17-172903.92" + wire width 4 $not$libresoc.v:172903$11700_Y + attribute \src "libresoc.v:172897.18-172897.98" + wire width 4 $or$libresoc.v:172897$11694_Y + attribute \src "libresoc.v:172899.18-172899.99" + wire width 4 $or$libresoc.v:172899$11696_Y + attribute \src "libresoc.v:172902.17-172902.97" + wire width 4 $or$libresoc.v:172902$11699_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -350392,11 +358322,11 @@ module \req_l$100 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169436.7-169436.15" + attribute \src "libresoc.v:172861.7-172861.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int @@ -350413,7 +358343,7 @@ module \req_l$100 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169471$11295 + cell $and $and$libresoc.v:172896$11693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -350421,10 +358351,10 @@ module \req_l$100 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169471$11295_Y + connect \Y $and$libresoc.v:172896$11693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169476$11300 + cell $and $and$libresoc.v:172901$11698 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -350432,34 +358362,34 @@ module \req_l$100 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169476$11300_Y + connect \Y $and$libresoc.v:172901$11698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169473$11297 + cell $not $not$libresoc.v:172898$11695 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:169473$11297_Y + connect \Y $not$libresoc.v:172898$11695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169475$11299 + cell $not $not$libresoc.v:172900$11697 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:169475$11299_Y + connect \Y $not$libresoc.v:172900$11697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169478$11302 + cell $not $not$libresoc.v:172903$11700 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:169478$11302_Y + connect \Y $not$libresoc.v:172903$11700_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169472$11296 + cell $or $or$libresoc.v:172897$11694 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -350467,10 +358397,10 @@ module \req_l$100 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169472$11296_Y + connect \Y $or$libresoc.v:172897$11694_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169474$11298 + cell $or $or$libresoc.v:172899$11696 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -350478,10 +358408,10 @@ module \req_l$100 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169474$11298_Y + connect \Y $or$libresoc.v:172899$11696_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169477$11301 + cell $or $or$libresoc.v:172902$11699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -350489,39 +358419,39 @@ module \req_l$100 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169477$11301_Y + connect \Y $or$libresoc.v:172902$11699_Y end - attribute \src "libresoc.v:169436.7-169436.20" - process $proc$libresoc.v:169436$11307 + attribute \src "libresoc.v:172861.7-172861.20" + process $proc$libresoc.v:172861$11705 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169458.13-169458.25" - process $proc$libresoc.v:169458$11308 + attribute \src "libresoc.v:172883.13-172883.25" + process $proc$libresoc.v:172883$11706 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:169479.3-169480.27" - process $proc$libresoc.v:169479$11303 + attribute \src "libresoc.v:172904.3-172905.27" + process $proc$libresoc.v:172904$11701 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:169481.3-169489.6" - process $proc$libresoc.v:169481$11304 + attribute \src "libresoc.v:172906.3-172914.6" + process $proc$libresoc.v:172906$11702 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11305 $1\q_int$next[3:0]$11306 - attribute \src "libresoc.v:169482.5-169482.29" + assign $0\q_int$next[3:0]$11703 $1\q_int$next[3:0]$11704 + attribute \src "libresoc.v:172907.5-172907.29" switch \initial - attribute \src "libresoc.v:169482.9-169482.17" + attribute \src "libresoc.v:172907.9-172907.17" case 1'1 case end @@ -350530,56 +358460,56 @@ module \req_l$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11306 4'0000 + assign $1\q_int$next[3:0]$11704 4'0000 case - assign $1\q_int$next[3:0]$11306 \$5 + assign $1\q_int$next[3:0]$11704 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11305 + update \q_int$next $0\q_int$next[3:0]$11703 end - connect \$9 $and$libresoc.v:169471$11295_Y - connect \$11 $or$libresoc.v:169472$11296_Y - connect \$13 $not$libresoc.v:169473$11297_Y - connect \$15 $or$libresoc.v:169474$11298_Y - connect \$1 $not$libresoc.v:169475$11299_Y - connect \$3 $and$libresoc.v:169476$11300_Y - connect \$5 $or$libresoc.v:169477$11301_Y - connect \$7 $not$libresoc.v:169478$11302_Y + connect \$9 $and$libresoc.v:172896$11693_Y + connect \$11 $or$libresoc.v:172897$11694_Y + connect \$13 $not$libresoc.v:172898$11695_Y + connect \$15 $or$libresoc.v:172899$11696_Y + connect \$1 $not$libresoc.v:172900$11697_Y + connect \$3 $and$libresoc.v:172901$11698_Y + connect \$5 $or$libresoc.v:172902$11699_Y + connect \$7 $not$libresoc.v:172903$11700_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169497.1-169555.10" +attribute \src "libresoc.v:172922.1-172980.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" -module \req_l$118 - attribute \src "libresoc.v:169498.7-169498.20" +module \req_l$12 + attribute \src "libresoc.v:172923.7-172923.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169543.3-169551.6" - wire width 3 $0\q_int$next[2:0]$11319 - attribute \src "libresoc.v:169541.3-169542.27" + attribute \src "libresoc.v:172968.3-172976.6" + wire width 3 $0\q_int$next[2:0]$11717 + attribute \src "libresoc.v:172966.3-172967.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:169543.3-169551.6" - wire width 3 $1\q_int$next[2:0]$11320 - attribute \src "libresoc.v:169520.13-169520.25" + attribute \src "libresoc.v:172968.3-172976.6" + wire width 3 $1\q_int$next[2:0]$11718 + attribute \src "libresoc.v:172945.13-172945.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:169533.17-169533.96" - wire width 3 $and$libresoc.v:169533$11309_Y - attribute \src "libresoc.v:169538.17-169538.96" - wire width 3 $and$libresoc.v:169538$11314_Y - attribute \src "libresoc.v:169535.18-169535.93" - wire width 3 $not$libresoc.v:169535$11311_Y - attribute \src "libresoc.v:169537.17-169537.92" - wire width 3 $not$libresoc.v:169537$11313_Y - attribute \src "libresoc.v:169540.17-169540.92" - wire width 3 $not$libresoc.v:169540$11316_Y - attribute \src "libresoc.v:169534.18-169534.98" - wire width 3 $or$libresoc.v:169534$11310_Y - attribute \src "libresoc.v:169536.18-169536.99" - wire width 3 $or$libresoc.v:169536$11312_Y - attribute \src "libresoc.v:169539.17-169539.97" - wire width 3 $or$libresoc.v:169539$11315_Y + attribute \src "libresoc.v:172958.17-172958.96" + wire width 3 $and$libresoc.v:172958$11707_Y + attribute \src "libresoc.v:172963.17-172963.96" + wire width 3 $and$libresoc.v:172963$11712_Y + attribute \src "libresoc.v:172960.18-172960.93" + wire width 3 $not$libresoc.v:172960$11709_Y + attribute \src "libresoc.v:172962.17-172962.92" + wire width 3 $not$libresoc.v:172962$11711_Y + attribute \src "libresoc.v:172965.17-172965.92" + wire width 3 $not$libresoc.v:172965$11714_Y + attribute \src "libresoc.v:172959.18-172959.98" + wire width 3 $or$libresoc.v:172959$11708_Y + attribute \src "libresoc.v:172961.18-172961.99" + wire width 3 $or$libresoc.v:172961$11710_Y + attribute \src "libresoc.v:172964.17-172964.97" + wire width 3 $or$libresoc.v:172964$11713_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -350596,11 +358526,11 @@ module \req_l$118 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169498.7-169498.15" + attribute \src "libresoc.v:172923.7-172923.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -350617,7 +358547,7 @@ module \req_l$118 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169533$11309 + cell $and $and$libresoc.v:172958$11707 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350625,10 +358555,10 @@ module \req_l$118 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169533$11309_Y + connect \Y $and$libresoc.v:172958$11707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169538$11314 + cell $and $and$libresoc.v:172963$11712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350636,34 +358566,34 @@ module \req_l$118 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169538$11314_Y + connect \Y $and$libresoc.v:172963$11712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169535$11311 + cell $not $not$libresoc.v:172960$11709 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:169535$11311_Y + connect \Y $not$libresoc.v:172960$11709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169537$11313 + cell $not $not$libresoc.v:172962$11711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169537$11313_Y + connect \Y $not$libresoc.v:172962$11711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169540$11316 + cell $not $not$libresoc.v:172965$11714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169540$11316_Y + connect \Y $not$libresoc.v:172965$11714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169534$11310 + cell $or $or$libresoc.v:172959$11708 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350671,10 +358601,10 @@ module \req_l$118 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169534$11310_Y + connect \Y $or$libresoc.v:172959$11708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169536$11312 + cell $or $or$libresoc.v:172961$11710 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350682,10 +358612,10 @@ module \req_l$118 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169536$11312_Y + connect \Y $or$libresoc.v:172961$11710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169539$11315 + cell $or $or$libresoc.v:172964$11713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350693,39 +358623,39 @@ module \req_l$118 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169539$11315_Y + connect \Y $or$libresoc.v:172964$11713_Y end - attribute \src "libresoc.v:169498.7-169498.20" - process $proc$libresoc.v:169498$11321 + attribute \src "libresoc.v:172923.7-172923.20" + process $proc$libresoc.v:172923$11719 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169520.13-169520.25" - process $proc$libresoc.v:169520$11322 + attribute \src "libresoc.v:172945.13-172945.25" + process $proc$libresoc.v:172945$11720 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:169541.3-169542.27" - process $proc$libresoc.v:169541$11317 + attribute \src "libresoc.v:172966.3-172967.27" + process $proc$libresoc.v:172966$11715 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:169543.3-169551.6" - process $proc$libresoc.v:169543$11318 + attribute \src "libresoc.v:172968.3-172976.6" + process $proc$libresoc.v:172968$11716 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11319 $1\q_int$next[2:0]$11320 - attribute \src "libresoc.v:169544.5-169544.29" + assign $0\q_int$next[2:0]$11717 $1\q_int$next[2:0]$11718 + attribute \src "libresoc.v:172969.5-172969.29" switch \initial - attribute \src "libresoc.v:169544.9-169544.17" + attribute \src "libresoc.v:172969.9-172969.17" case 1'1 case end @@ -350734,56 +358664,56 @@ module \req_l$118 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11320 3'000 + assign $1\q_int$next[2:0]$11718 3'000 case - assign $1\q_int$next[2:0]$11320 \$5 + assign $1\q_int$next[2:0]$11718 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11319 + update \q_int$next $0\q_int$next[2:0]$11717 end - connect \$9 $and$libresoc.v:169533$11309_Y - connect \$11 $or$libresoc.v:169534$11310_Y - connect \$13 $not$libresoc.v:169535$11311_Y - connect \$15 $or$libresoc.v:169536$11312_Y - connect \$1 $not$libresoc.v:169537$11313_Y - connect \$3 $and$libresoc.v:169538$11314_Y - connect \$5 $or$libresoc.v:169539$11315_Y - connect \$7 $not$libresoc.v:169540$11316_Y + connect \$9 $and$libresoc.v:172958$11707_Y + connect \$11 $or$libresoc.v:172959$11708_Y + connect \$13 $not$libresoc.v:172960$11709_Y + connect \$15 $or$libresoc.v:172961$11710_Y + connect \$1 $not$libresoc.v:172962$11711_Y + connect \$3 $and$libresoc.v:172963$11712_Y + connect \$5 $or$libresoc.v:172964$11713_Y + connect \$7 $not$libresoc.v:172965$11714_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169559.1-169617.10" +attribute \src "libresoc.v:172984.1-173042.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" -module \req_l$12 - attribute \src "libresoc.v:169560.7-169560.20" +module \req_l$121 + attribute \src "libresoc.v:172985.7-172985.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169605.3-169613.6" - wire width 3 $0\q_int$next[2:0]$11333 - attribute \src "libresoc.v:169603.3-169604.27" + attribute \src "libresoc.v:173030.3-173038.6" + wire width 3 $0\q_int$next[2:0]$11731 + attribute \src "libresoc.v:173028.3-173029.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:169605.3-169613.6" - wire width 3 $1\q_int$next[2:0]$11334 - attribute \src "libresoc.v:169582.13-169582.25" + attribute \src "libresoc.v:173030.3-173038.6" + wire width 3 $1\q_int$next[2:0]$11732 + attribute \src "libresoc.v:173007.13-173007.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:169595.17-169595.96" - wire width 3 $and$libresoc.v:169595$11323_Y - attribute \src "libresoc.v:169600.17-169600.96" - wire width 3 $and$libresoc.v:169600$11328_Y - attribute \src "libresoc.v:169597.18-169597.93" - wire width 3 $not$libresoc.v:169597$11325_Y - attribute \src "libresoc.v:169599.17-169599.92" - wire width 3 $not$libresoc.v:169599$11327_Y - attribute \src "libresoc.v:169602.17-169602.92" - wire width 3 $not$libresoc.v:169602$11330_Y - attribute \src "libresoc.v:169596.18-169596.98" - wire width 3 $or$libresoc.v:169596$11324_Y - attribute \src "libresoc.v:169598.18-169598.99" - wire width 3 $or$libresoc.v:169598$11326_Y - attribute \src "libresoc.v:169601.17-169601.97" - wire width 3 $or$libresoc.v:169601$11329_Y + attribute \src "libresoc.v:173020.17-173020.96" + wire width 3 $and$libresoc.v:173020$11721_Y + attribute \src "libresoc.v:173025.17-173025.96" + wire width 3 $and$libresoc.v:173025$11726_Y + attribute \src "libresoc.v:173022.18-173022.93" + wire width 3 $not$libresoc.v:173022$11723_Y + attribute \src "libresoc.v:173024.17-173024.92" + wire width 3 $not$libresoc.v:173024$11725_Y + attribute \src "libresoc.v:173027.17-173027.92" + wire width 3 $not$libresoc.v:173027$11728_Y + attribute \src "libresoc.v:173021.18-173021.98" + wire width 3 $or$libresoc.v:173021$11722_Y + attribute \src "libresoc.v:173023.18-173023.99" + wire width 3 $or$libresoc.v:173023$11724_Y + attribute \src "libresoc.v:173026.17-173026.97" + wire width 3 $or$libresoc.v:173026$11727_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -350800,11 +358730,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169560.7-169560.15" + attribute \src "libresoc.v:172985.7-172985.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -350821,7 +358751,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169595$11323 + cell $and $and$libresoc.v:173020$11721 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350829,10 +358759,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169595$11323_Y + connect \Y $and$libresoc.v:173020$11721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169600$11328 + cell $and $and$libresoc.v:173025$11726 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350840,34 +358770,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169600$11328_Y + connect \Y $and$libresoc.v:173025$11726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169597$11325 + cell $not $not$libresoc.v:173022$11723 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:169597$11325_Y + connect \Y $not$libresoc.v:173022$11723_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169599$11327 + cell $not $not$libresoc.v:173024$11725 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169599$11327_Y + connect \Y $not$libresoc.v:173024$11725_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169602$11330 + cell $not $not$libresoc.v:173027$11728 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169602$11330_Y + connect \Y $not$libresoc.v:173027$11728_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169596$11324 + cell $or $or$libresoc.v:173021$11722 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350875,10 +358805,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169596$11324_Y + connect \Y $or$libresoc.v:173021$11722_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169598$11326 + cell $or $or$libresoc.v:173023$11724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350886,10 +358816,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169598$11326_Y + connect \Y $or$libresoc.v:173023$11724_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169601$11329 + cell $or $or$libresoc.v:173026$11727 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -350897,39 +358827,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169601$11329_Y + connect \Y $or$libresoc.v:173026$11727_Y end - attribute \src "libresoc.v:169560.7-169560.20" - process $proc$libresoc.v:169560$11335 + attribute \src "libresoc.v:172985.7-172985.20" + process $proc$libresoc.v:172985$11733 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169582.13-169582.25" - process $proc$libresoc.v:169582$11336 + attribute \src "libresoc.v:173007.13-173007.25" + process $proc$libresoc.v:173007$11734 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:169603.3-169604.27" - process $proc$libresoc.v:169603$11331 + attribute \src "libresoc.v:173028.3-173029.27" + process $proc$libresoc.v:173028$11729 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:169605.3-169613.6" - process $proc$libresoc.v:169605$11332 + attribute \src "libresoc.v:173030.3-173038.6" + process $proc$libresoc.v:173030$11730 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11333 $1\q_int$next[2:0]$11334 - attribute \src "libresoc.v:169606.5-169606.29" + assign $0\q_int$next[2:0]$11731 $1\q_int$next[2:0]$11732 + attribute \src "libresoc.v:173031.5-173031.29" switch \initial - attribute \src "libresoc.v:169606.9-169606.17" + attribute \src "libresoc.v:173031.9-173031.17" case 1'1 case end @@ -350938,56 +358868,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11334 3'000 + assign $1\q_int$next[2:0]$11732 3'000 case - assign $1\q_int$next[2:0]$11334 \$5 + assign $1\q_int$next[2:0]$11732 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11333 + update \q_int$next $0\q_int$next[2:0]$11731 end - connect \$9 $and$libresoc.v:169595$11323_Y - connect \$11 $or$libresoc.v:169596$11324_Y - connect \$13 $not$libresoc.v:169597$11325_Y - connect \$15 $or$libresoc.v:169598$11326_Y - connect \$1 $not$libresoc.v:169599$11327_Y - connect \$3 $and$libresoc.v:169600$11328_Y - connect \$5 $or$libresoc.v:169601$11329_Y - connect \$7 $not$libresoc.v:169602$11330_Y + connect \$9 $and$libresoc.v:173020$11721_Y + connect \$11 $or$libresoc.v:173021$11722_Y + connect \$13 $not$libresoc.v:173022$11723_Y + connect \$15 $or$libresoc.v:173023$11724_Y + connect \$1 $not$libresoc.v:173024$11725_Y + connect \$3 $and$libresoc.v:173025$11726_Y + connect \$5 $or$libresoc.v:173026$11727_Y + connect \$7 $not$libresoc.v:173027$11728_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169621.1-169679.10" +attribute \src "libresoc.v:173046.1-173104.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:169622.7-169622.20" + attribute \src "libresoc.v:173047.7-173047.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169667.3-169675.6" - wire width 3 $0\q_int$next[2:0]$11347 - attribute \src "libresoc.v:169665.3-169666.27" + attribute \src "libresoc.v:173092.3-173100.6" + wire width 3 $0\q_int$next[2:0]$11745 + attribute \src "libresoc.v:173090.3-173091.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:169667.3-169675.6" - wire width 3 $1\q_int$next[2:0]$11348 - attribute \src "libresoc.v:169644.13-169644.25" + attribute \src "libresoc.v:173092.3-173100.6" + wire width 3 $1\q_int$next[2:0]$11746 + attribute \src "libresoc.v:173069.13-173069.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:169657.17-169657.96" - wire width 3 $and$libresoc.v:169657$11337_Y - attribute \src "libresoc.v:169662.17-169662.96" - wire width 3 $and$libresoc.v:169662$11342_Y - attribute \src "libresoc.v:169659.18-169659.93" - wire width 3 $not$libresoc.v:169659$11339_Y - attribute \src "libresoc.v:169661.17-169661.92" - wire width 3 $not$libresoc.v:169661$11341_Y - attribute \src "libresoc.v:169664.17-169664.92" - wire width 3 $not$libresoc.v:169664$11344_Y - attribute \src "libresoc.v:169658.18-169658.98" - wire width 3 $or$libresoc.v:169658$11338_Y - attribute \src "libresoc.v:169660.18-169660.99" - wire width 3 $or$libresoc.v:169660$11340_Y - attribute \src "libresoc.v:169663.17-169663.97" - wire width 3 $or$libresoc.v:169663$11343_Y + attribute \src "libresoc.v:173082.17-173082.96" + wire width 3 $and$libresoc.v:173082$11735_Y + attribute \src "libresoc.v:173087.17-173087.96" + wire width 3 $and$libresoc.v:173087$11740_Y + attribute \src "libresoc.v:173084.18-173084.93" + wire width 3 $not$libresoc.v:173084$11737_Y + attribute \src "libresoc.v:173086.17-173086.92" + wire width 3 $not$libresoc.v:173086$11739_Y + attribute \src "libresoc.v:173089.17-173089.92" + wire width 3 $not$libresoc.v:173089$11742_Y + attribute \src "libresoc.v:173083.18-173083.98" + wire width 3 $or$libresoc.v:173083$11736_Y + attribute \src "libresoc.v:173085.18-173085.99" + wire width 3 $or$libresoc.v:173085$11738_Y + attribute \src "libresoc.v:173088.17-173088.97" + wire width 3 $or$libresoc.v:173088$11741_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -351004,11 +358934,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169622.7-169622.15" + attribute \src "libresoc.v:173047.7-173047.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -351025,7 +358955,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169657$11337 + cell $and $and$libresoc.v:173082$11735 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -351033,10 +358963,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169657$11337_Y + connect \Y $and$libresoc.v:173082$11735_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169662$11342 + cell $and $and$libresoc.v:173087$11740 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -351044,34 +358974,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169662$11342_Y + connect \Y $and$libresoc.v:173087$11740_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169659$11339 + cell $not $not$libresoc.v:173084$11737 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:169659$11339_Y + connect \Y $not$libresoc.v:173084$11737_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169661$11341 + cell $not $not$libresoc.v:173086$11739 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169661$11341_Y + connect \Y $not$libresoc.v:173086$11739_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169664$11344 + cell $not $not$libresoc.v:173089$11742 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:169664$11344_Y + connect \Y $not$libresoc.v:173089$11742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169658$11338 + cell $or $or$libresoc.v:173083$11736 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -351079,10 +359009,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169658$11338_Y + connect \Y $or$libresoc.v:173083$11736_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169660$11340 + cell $or $or$libresoc.v:173085$11738 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -351090,10 +359020,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169660$11340_Y + connect \Y $or$libresoc.v:173085$11738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169663$11343 + cell $or $or$libresoc.v:173088$11741 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -351101,39 +359031,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169663$11343_Y + connect \Y $or$libresoc.v:173088$11741_Y end - attribute \src "libresoc.v:169622.7-169622.20" - process $proc$libresoc.v:169622$11349 + attribute \src "libresoc.v:173047.7-173047.20" + process $proc$libresoc.v:173047$11747 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169644.13-169644.25" - process $proc$libresoc.v:169644$11350 + attribute \src "libresoc.v:173069.13-173069.25" + process $proc$libresoc.v:173069$11748 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:169665.3-169666.27" - process $proc$libresoc.v:169665$11345 + attribute \src "libresoc.v:173090.3-173091.27" + process $proc$libresoc.v:173090$11743 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:169667.3-169675.6" - process $proc$libresoc.v:169667$11346 + attribute \src "libresoc.v:173092.3-173100.6" + process $proc$libresoc.v:173092$11744 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11347 $1\q_int$next[2:0]$11348 - attribute \src "libresoc.v:169668.5-169668.29" + assign $0\q_int$next[2:0]$11745 $1\q_int$next[2:0]$11746 + attribute \src "libresoc.v:173093.5-173093.29" switch \initial - attribute \src "libresoc.v:169668.9-169668.17" + attribute \src "libresoc.v:173093.9-173093.17" case 1'1 case end @@ -351142,56 +359072,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11348 3'000 + assign $1\q_int$next[2:0]$11746 3'000 case - assign $1\q_int$next[2:0]$11348 \$5 + assign $1\q_int$next[2:0]$11746 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11347 + update \q_int$next $0\q_int$next[2:0]$11745 end - connect \$9 $and$libresoc.v:169657$11337_Y - connect \$11 $or$libresoc.v:169658$11338_Y - connect \$13 $not$libresoc.v:169659$11339_Y - connect \$15 $or$libresoc.v:169660$11340_Y - connect \$1 $not$libresoc.v:169661$11341_Y - connect \$3 $and$libresoc.v:169662$11342_Y - connect \$5 $or$libresoc.v:169663$11343_Y - connect \$7 $not$libresoc.v:169664$11344_Y + connect \$9 $and$libresoc.v:173082$11735_Y + connect \$11 $or$libresoc.v:173083$11736_Y + connect \$13 $not$libresoc.v:173084$11737_Y + connect \$15 $or$libresoc.v:173085$11738_Y + connect \$1 $not$libresoc.v:173086$11739_Y + connect \$3 $and$libresoc.v:173087$11740_Y + connect \$5 $or$libresoc.v:173088$11741_Y + connect \$7 $not$libresoc.v:173089$11742_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169683.1-169741.10" +attribute \src "libresoc.v:173108.1-173166.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" -module \req_l$38 - attribute \src "libresoc.v:169684.7-169684.20" +module \req_l$41 + attribute \src "libresoc.v:173109.7-173109.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169729.3-169737.6" - wire width 5 $0\q_int$next[4:0]$11361 - attribute \src "libresoc.v:169727.3-169728.27" + attribute \src "libresoc.v:173154.3-173162.6" + wire width 5 $0\q_int$next[4:0]$11759 + attribute \src "libresoc.v:173152.3-173153.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:169729.3-169737.6" - wire width 5 $1\q_int$next[4:0]$11362 - attribute \src "libresoc.v:169706.13-169706.26" + attribute \src "libresoc.v:173154.3-173162.6" + wire width 5 $1\q_int$next[4:0]$11760 + attribute \src "libresoc.v:173131.13-173131.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:169719.17-169719.96" - wire width 5 $and$libresoc.v:169719$11351_Y - attribute \src "libresoc.v:169724.17-169724.96" - wire width 5 $and$libresoc.v:169724$11356_Y - attribute \src "libresoc.v:169721.18-169721.93" - wire width 5 $not$libresoc.v:169721$11353_Y - attribute \src "libresoc.v:169723.17-169723.92" - wire width 5 $not$libresoc.v:169723$11355_Y - attribute \src "libresoc.v:169726.17-169726.92" - wire width 5 $not$libresoc.v:169726$11358_Y - attribute \src "libresoc.v:169720.18-169720.98" - wire width 5 $or$libresoc.v:169720$11352_Y - attribute \src "libresoc.v:169722.18-169722.99" - wire width 5 $or$libresoc.v:169722$11354_Y - attribute \src "libresoc.v:169725.17-169725.97" - wire width 5 $or$libresoc.v:169725$11357_Y + attribute \src "libresoc.v:173144.17-173144.96" + wire width 5 $and$libresoc.v:173144$11749_Y + attribute \src "libresoc.v:173149.17-173149.96" + wire width 5 $and$libresoc.v:173149$11754_Y + attribute \src "libresoc.v:173146.18-173146.93" + wire width 5 $not$libresoc.v:173146$11751_Y + attribute \src "libresoc.v:173148.17-173148.92" + wire width 5 $not$libresoc.v:173148$11753_Y + attribute \src "libresoc.v:173151.17-173151.92" + wire width 5 $not$libresoc.v:173151$11756_Y + attribute \src "libresoc.v:173145.18-173145.98" + wire width 5 $or$libresoc.v:173145$11750_Y + attribute \src "libresoc.v:173147.18-173147.99" + wire width 5 $or$libresoc.v:173147$11752_Y + attribute \src "libresoc.v:173150.17-173150.97" + wire width 5 $or$libresoc.v:173150$11755_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -351208,11 +359138,11 @@ module \req_l$38 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169684.7-169684.15" + attribute \src "libresoc.v:173109.7-173109.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int @@ -351229,7 +359159,7 @@ module \req_l$38 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169719$11351 + cell $and $and$libresoc.v:173144$11749 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -351237,10 +359167,10 @@ module \req_l$38 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169719$11351_Y + connect \Y $and$libresoc.v:173144$11749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169724$11356 + cell $and $and$libresoc.v:173149$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -351248,34 +359178,34 @@ module \req_l$38 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169724$11356_Y + connect \Y $and$libresoc.v:173149$11754_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169721$11353 + cell $not $not$libresoc.v:173146$11751 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:169721$11353_Y + connect \Y $not$libresoc.v:173146$11751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169723$11355 + cell $not $not$libresoc.v:173148$11753 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:169723$11355_Y + connect \Y $not$libresoc.v:173148$11753_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169726$11358 + cell $not $not$libresoc.v:173151$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:169726$11358_Y + connect \Y $not$libresoc.v:173151$11756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169720$11352 + cell $or $or$libresoc.v:173145$11750 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -351283,10 +359213,10 @@ module \req_l$38 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169720$11352_Y + connect \Y $or$libresoc.v:173145$11750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169722$11354 + cell $or $or$libresoc.v:173147$11752 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -351294,10 +359224,10 @@ module \req_l$38 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169722$11354_Y + connect \Y $or$libresoc.v:173147$11752_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169725$11357 + cell $or $or$libresoc.v:173150$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -351305,39 +359235,39 @@ module \req_l$38 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169725$11357_Y + connect \Y $or$libresoc.v:173150$11755_Y end - attribute \src "libresoc.v:169684.7-169684.20" - process $proc$libresoc.v:169684$11363 + attribute \src "libresoc.v:173109.7-173109.20" + process $proc$libresoc.v:173109$11761 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169706.13-169706.26" - process $proc$libresoc.v:169706$11364 + attribute \src "libresoc.v:173131.13-173131.26" + process $proc$libresoc.v:173131$11762 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:169727.3-169728.27" - process $proc$libresoc.v:169727$11359 + attribute \src "libresoc.v:173152.3-173153.27" + process $proc$libresoc.v:173152$11757 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:169729.3-169737.6" - process $proc$libresoc.v:169729$11360 + attribute \src "libresoc.v:173154.3-173162.6" + process $proc$libresoc.v:173154$11758 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11361 $1\q_int$next[4:0]$11362 - attribute \src "libresoc.v:169730.5-169730.29" + assign $0\q_int$next[4:0]$11759 $1\q_int$next[4:0]$11760 + attribute \src "libresoc.v:173155.5-173155.29" switch \initial - attribute \src "libresoc.v:169730.9-169730.17" + attribute \src "libresoc.v:173155.9-173155.17" case 1'1 case end @@ -351346,56 +359276,56 @@ module \req_l$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11362 5'00000 + assign $1\q_int$next[4:0]$11760 5'00000 case - assign $1\q_int$next[4:0]$11362 \$5 + assign $1\q_int$next[4:0]$11760 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11361 + update \q_int$next $0\q_int$next[4:0]$11759 end - connect \$9 $and$libresoc.v:169719$11351_Y - connect \$11 $or$libresoc.v:169720$11352_Y - connect \$13 $not$libresoc.v:169721$11353_Y - connect \$15 $or$libresoc.v:169722$11354_Y - connect \$1 $not$libresoc.v:169723$11355_Y - connect \$3 $and$libresoc.v:169724$11356_Y - connect \$5 $or$libresoc.v:169725$11357_Y - connect \$7 $not$libresoc.v:169726$11358_Y + connect \$9 $and$libresoc.v:173144$11749_Y + connect \$11 $or$libresoc.v:173145$11750_Y + connect \$13 $not$libresoc.v:173146$11751_Y + connect \$15 $or$libresoc.v:173147$11752_Y + connect \$1 $not$libresoc.v:173148$11753_Y + connect \$3 $and$libresoc.v:173149$11754_Y + connect \$5 $or$libresoc.v:173150$11755_Y + connect \$7 $not$libresoc.v:173151$11756_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169745.1-169803.10" +attribute \src "libresoc.v:173170.1-173228.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" -module \req_l$54 - attribute \src "libresoc.v:169746.7-169746.20" +module \req_l$57 + attribute \src "libresoc.v:173171.7-173171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169791.3-169799.6" - wire width 2 $0\q_int$next[1:0]$11375 - attribute \src "libresoc.v:169789.3-169790.27" + attribute \src "libresoc.v:173216.3-173224.6" + wire width 2 $0\q_int$next[1:0]$11773 + attribute \src "libresoc.v:173214.3-173215.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:169791.3-169799.6" - wire width 2 $1\q_int$next[1:0]$11376 - attribute \src "libresoc.v:169768.13-169768.25" + attribute \src "libresoc.v:173216.3-173224.6" + wire width 2 $1\q_int$next[1:0]$11774 + attribute \src "libresoc.v:173193.13-173193.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:169781.17-169781.96" - wire width 2 $and$libresoc.v:169781$11365_Y - attribute \src "libresoc.v:169786.17-169786.96" - wire width 2 $and$libresoc.v:169786$11370_Y - attribute \src "libresoc.v:169783.18-169783.93" - wire width 2 $not$libresoc.v:169783$11367_Y - attribute \src "libresoc.v:169785.17-169785.92" - wire width 2 $not$libresoc.v:169785$11369_Y - attribute \src "libresoc.v:169788.17-169788.92" - wire width 2 $not$libresoc.v:169788$11372_Y - attribute \src "libresoc.v:169782.18-169782.98" - wire width 2 $or$libresoc.v:169782$11366_Y - attribute \src "libresoc.v:169784.18-169784.99" - wire width 2 $or$libresoc.v:169784$11368_Y - attribute \src "libresoc.v:169787.17-169787.97" - wire width 2 $or$libresoc.v:169787$11371_Y + attribute \src "libresoc.v:173206.17-173206.96" + wire width 2 $and$libresoc.v:173206$11763_Y + attribute \src "libresoc.v:173211.17-173211.96" + wire width 2 $and$libresoc.v:173211$11768_Y + attribute \src "libresoc.v:173208.18-173208.93" + wire width 2 $not$libresoc.v:173208$11765_Y + attribute \src "libresoc.v:173210.17-173210.92" + wire width 2 $not$libresoc.v:173210$11767_Y + attribute \src "libresoc.v:173213.17-173213.92" + wire width 2 $not$libresoc.v:173213$11770_Y + attribute \src "libresoc.v:173207.18-173207.98" + wire width 2 $or$libresoc.v:173207$11764_Y + attribute \src "libresoc.v:173209.18-173209.99" + wire width 2 $or$libresoc.v:173209$11766_Y + attribute \src "libresoc.v:173212.17-173212.97" + wire width 2 $or$libresoc.v:173212$11769_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -351412,11 +359342,11 @@ module \req_l$54 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169746.7-169746.15" + attribute \src "libresoc.v:173171.7-173171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 2 \q_int @@ -351433,7 +359363,7 @@ module \req_l$54 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169781$11365 + cell $and $and$libresoc.v:173206$11763 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -351441,10 +359371,10 @@ module \req_l$54 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169781$11365_Y + connect \Y $and$libresoc.v:173206$11763_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169786$11370 + cell $and $and$libresoc.v:173211$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -351452,34 +359382,34 @@ module \req_l$54 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169786$11370_Y + connect \Y $and$libresoc.v:173211$11768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169783$11367 + cell $not $not$libresoc.v:173208$11765 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:169783$11367_Y + connect \Y $not$libresoc.v:173208$11765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169785$11369 + cell $not $not$libresoc.v:173210$11767 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:169785$11369_Y + connect \Y $not$libresoc.v:173210$11767_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169788$11372 + cell $not $not$libresoc.v:173213$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:169788$11372_Y + connect \Y $not$libresoc.v:173213$11770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169782$11366 + cell $or $or$libresoc.v:173207$11764 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -351487,10 +359417,10 @@ module \req_l$54 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169782$11366_Y + connect \Y $or$libresoc.v:173207$11764_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169784$11368 + cell $or $or$libresoc.v:173209$11766 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -351498,10 +359428,10 @@ module \req_l$54 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169784$11368_Y + connect \Y $or$libresoc.v:173209$11766_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169787$11371 + cell $or $or$libresoc.v:173212$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -351509,39 +359439,39 @@ module \req_l$54 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169787$11371_Y + connect \Y $or$libresoc.v:173212$11769_Y end - attribute \src "libresoc.v:169746.7-169746.20" - process $proc$libresoc.v:169746$11377 + attribute \src "libresoc.v:173171.7-173171.20" + process $proc$libresoc.v:173171$11775 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169768.13-169768.25" - process $proc$libresoc.v:169768$11378 + attribute \src "libresoc.v:173193.13-173193.25" + process $proc$libresoc.v:173193$11776 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:169789.3-169790.27" - process $proc$libresoc.v:169789$11373 + attribute \src "libresoc.v:173214.3-173215.27" + process $proc$libresoc.v:173214$11771 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:169791.3-169799.6" - process $proc$libresoc.v:169791$11374 + attribute \src "libresoc.v:173216.3-173224.6" + process $proc$libresoc.v:173216$11772 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11375 $1\q_int$next[1:0]$11376 - attribute \src "libresoc.v:169792.5-169792.29" + assign $0\q_int$next[1:0]$11773 $1\q_int$next[1:0]$11774 + attribute \src "libresoc.v:173217.5-173217.29" switch \initial - attribute \src "libresoc.v:169792.9-169792.17" + attribute \src "libresoc.v:173217.9-173217.17" case 1'1 case end @@ -351550,56 +359480,56 @@ module \req_l$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11376 2'00 + assign $1\q_int$next[1:0]$11774 2'00 case - assign $1\q_int$next[1:0]$11376 \$5 + assign $1\q_int$next[1:0]$11774 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11375 + update \q_int$next $0\q_int$next[1:0]$11773 end - connect \$9 $and$libresoc.v:169781$11365_Y - connect \$11 $or$libresoc.v:169782$11366_Y - connect \$13 $not$libresoc.v:169783$11367_Y - connect \$15 $or$libresoc.v:169784$11368_Y - connect \$1 $not$libresoc.v:169785$11369_Y - connect \$3 $and$libresoc.v:169786$11370_Y - connect \$5 $or$libresoc.v:169787$11371_Y - connect \$7 $not$libresoc.v:169788$11372_Y + connect \$9 $and$libresoc.v:173206$11763_Y + connect \$11 $or$libresoc.v:173207$11764_Y + connect \$13 $not$libresoc.v:173208$11765_Y + connect \$15 $or$libresoc.v:173209$11766_Y + connect \$1 $not$libresoc.v:173210$11767_Y + connect \$3 $and$libresoc.v:173211$11768_Y + connect \$5 $or$libresoc.v:173212$11769_Y + connect \$7 $not$libresoc.v:173213$11770_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169807.1-169865.10" +attribute \src "libresoc.v:173232.1-173290.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" -module \req_l$66 - attribute \src "libresoc.v:169808.7-169808.20" +module \req_l$69 + attribute \src "libresoc.v:173233.7-173233.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169853.3-169861.6" - wire width 6 $0\q_int$next[5:0]$11389 - attribute \src "libresoc.v:169851.3-169852.27" + attribute \src "libresoc.v:173278.3-173286.6" + wire width 6 $0\q_int$next[5:0]$11787 + attribute \src "libresoc.v:173276.3-173277.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:169853.3-169861.6" - wire width 6 $1\q_int$next[5:0]$11390 - attribute \src "libresoc.v:169830.13-169830.26" + attribute \src "libresoc.v:173278.3-173286.6" + wire width 6 $1\q_int$next[5:0]$11788 + attribute \src "libresoc.v:173255.13-173255.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:169843.17-169843.96" - wire width 6 $and$libresoc.v:169843$11379_Y - attribute \src "libresoc.v:169848.17-169848.96" - wire width 6 $and$libresoc.v:169848$11384_Y - attribute \src "libresoc.v:169845.18-169845.93" - wire width 6 $not$libresoc.v:169845$11381_Y - attribute \src "libresoc.v:169847.17-169847.92" - wire width 6 $not$libresoc.v:169847$11383_Y - attribute \src "libresoc.v:169850.17-169850.92" - wire width 6 $not$libresoc.v:169850$11386_Y - attribute \src "libresoc.v:169844.18-169844.98" - wire width 6 $or$libresoc.v:169844$11380_Y - attribute \src "libresoc.v:169846.18-169846.99" - wire width 6 $or$libresoc.v:169846$11382_Y - attribute \src "libresoc.v:169849.17-169849.97" - wire width 6 $or$libresoc.v:169849$11385_Y + attribute \src "libresoc.v:173268.17-173268.96" + wire width 6 $and$libresoc.v:173268$11777_Y + attribute \src "libresoc.v:173273.17-173273.96" + wire width 6 $and$libresoc.v:173273$11782_Y + attribute \src "libresoc.v:173270.18-173270.93" + wire width 6 $not$libresoc.v:173270$11779_Y + attribute \src "libresoc.v:173272.17-173272.92" + wire width 6 $not$libresoc.v:173272$11781_Y + attribute \src "libresoc.v:173275.17-173275.92" + wire width 6 $not$libresoc.v:173275$11784_Y + attribute \src "libresoc.v:173269.18-173269.98" + wire width 6 $or$libresoc.v:173269$11778_Y + attribute \src "libresoc.v:173271.18-173271.99" + wire width 6 $or$libresoc.v:173271$11780_Y + attribute \src "libresoc.v:173274.17-173274.97" + wire width 6 $or$libresoc.v:173274$11783_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -351616,11 +359546,11 @@ module \req_l$66 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169808.7-169808.15" + attribute \src "libresoc.v:173233.7-173233.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int @@ -351637,7 +359567,7 @@ module \req_l$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169843$11379 + cell $and $and$libresoc.v:173268$11777 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -351645,10 +359575,10 @@ module \req_l$66 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169843$11379_Y + connect \Y $and$libresoc.v:173268$11777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169848$11384 + cell $and $and$libresoc.v:173273$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -351656,34 +359586,34 @@ module \req_l$66 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169848$11384_Y + connect \Y $and$libresoc.v:173273$11782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169845$11381 + cell $not $not$libresoc.v:173270$11779 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:169845$11381_Y + connect \Y $not$libresoc.v:173270$11779_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169847$11383 + cell $not $not$libresoc.v:173272$11781 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:169847$11383_Y + connect \Y $not$libresoc.v:173272$11781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169850$11386 + cell $not $not$libresoc.v:173275$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:169850$11386_Y + connect \Y $not$libresoc.v:173275$11784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169844$11380 + cell $or $or$libresoc.v:173269$11778 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -351691,10 +359621,10 @@ module \req_l$66 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169844$11380_Y + connect \Y $or$libresoc.v:173269$11778_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169846$11382 + cell $or $or$libresoc.v:173271$11780 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -351702,10 +359632,10 @@ module \req_l$66 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169846$11382_Y + connect \Y $or$libresoc.v:173271$11780_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169849$11385 + cell $or $or$libresoc.v:173274$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -351713,39 +359643,39 @@ module \req_l$66 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169849$11385_Y + connect \Y $or$libresoc.v:173274$11783_Y end - attribute \src "libresoc.v:169808.7-169808.20" - process $proc$libresoc.v:169808$11391 + attribute \src "libresoc.v:173233.7-173233.20" + process $proc$libresoc.v:173233$11789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169830.13-169830.26" - process $proc$libresoc.v:169830$11392 + attribute \src "libresoc.v:173255.13-173255.26" + process $proc$libresoc.v:173255$11790 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:169851.3-169852.27" - process $proc$libresoc.v:169851$11387 + attribute \src "libresoc.v:173276.3-173277.27" + process $proc$libresoc.v:173276$11785 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:169853.3-169861.6" - process $proc$libresoc.v:169853$11388 + attribute \src "libresoc.v:173278.3-173286.6" + process $proc$libresoc.v:173278$11786 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11389 $1\q_int$next[5:0]$11390 - attribute \src "libresoc.v:169854.5-169854.29" + assign $0\q_int$next[5:0]$11787 $1\q_int$next[5:0]$11788 + attribute \src "libresoc.v:173279.5-173279.29" switch \initial - attribute \src "libresoc.v:169854.9-169854.17" + attribute \src "libresoc.v:173279.9-173279.17" case 1'1 case end @@ -351754,56 +359684,56 @@ module \req_l$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$11390 6'000000 + assign $1\q_int$next[5:0]$11788 6'000000 case - assign $1\q_int$next[5:0]$11390 \$5 + assign $1\q_int$next[5:0]$11788 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$11389 + update \q_int$next $0\q_int$next[5:0]$11787 end - connect \$9 $and$libresoc.v:169843$11379_Y - connect \$11 $or$libresoc.v:169844$11380_Y - connect \$13 $not$libresoc.v:169845$11381_Y - connect \$15 $or$libresoc.v:169846$11382_Y - connect \$1 $not$libresoc.v:169847$11383_Y - connect \$3 $and$libresoc.v:169848$11384_Y - connect \$5 $or$libresoc.v:169849$11385_Y - connect \$7 $not$libresoc.v:169850$11386_Y + connect \$9 $and$libresoc.v:173268$11777_Y + connect \$11 $or$libresoc.v:173269$11778_Y + connect \$13 $not$libresoc.v:173270$11779_Y + connect \$15 $or$libresoc.v:173271$11780_Y + connect \$1 $not$libresoc.v:173272$11781_Y + connect \$3 $and$libresoc.v:173273$11782_Y + connect \$5 $or$libresoc.v:173274$11783_Y + connect \$7 $not$libresoc.v:173275$11784_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169869.1-169927.10" +attribute \src "libresoc.v:173294.1-173352.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" -module \req_l$83 - attribute \src "libresoc.v:169870.7-169870.20" +module \req_l$86 + attribute \src "libresoc.v:173295.7-173295.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169915.3-169923.6" - wire width 4 $0\q_int$next[3:0]$11403 - attribute \src "libresoc.v:169913.3-169914.27" + attribute \src "libresoc.v:173340.3-173348.6" + wire width 4 $0\q_int$next[3:0]$11801 + attribute \src "libresoc.v:173338.3-173339.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:169915.3-169923.6" - wire width 4 $1\q_int$next[3:0]$11404 - attribute \src "libresoc.v:169892.13-169892.25" + attribute \src "libresoc.v:173340.3-173348.6" + wire width 4 $1\q_int$next[3:0]$11802 + attribute \src "libresoc.v:173317.13-173317.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:169905.17-169905.96" - wire width 4 $and$libresoc.v:169905$11393_Y - attribute \src "libresoc.v:169910.17-169910.96" - wire width 4 $and$libresoc.v:169910$11398_Y - attribute \src "libresoc.v:169907.18-169907.93" - wire width 4 $not$libresoc.v:169907$11395_Y - attribute \src "libresoc.v:169909.17-169909.92" - wire width 4 $not$libresoc.v:169909$11397_Y - attribute \src "libresoc.v:169912.17-169912.92" - wire width 4 $not$libresoc.v:169912$11400_Y - attribute \src "libresoc.v:169906.18-169906.98" - wire width 4 $or$libresoc.v:169906$11394_Y - attribute \src "libresoc.v:169908.18-169908.99" - wire width 4 $or$libresoc.v:169908$11396_Y - attribute \src "libresoc.v:169911.17-169911.97" - wire width 4 $or$libresoc.v:169911$11399_Y + attribute \src "libresoc.v:173330.17-173330.96" + wire width 4 $and$libresoc.v:173330$11791_Y + attribute \src "libresoc.v:173335.17-173335.96" + wire width 4 $and$libresoc.v:173335$11796_Y + attribute \src "libresoc.v:173332.18-173332.93" + wire width 4 $not$libresoc.v:173332$11793_Y + attribute \src "libresoc.v:173334.17-173334.92" + wire width 4 $not$libresoc.v:173334$11795_Y + attribute \src "libresoc.v:173337.17-173337.92" + wire width 4 $not$libresoc.v:173337$11798_Y + attribute \src "libresoc.v:173331.18-173331.98" + wire width 4 $or$libresoc.v:173331$11792_Y + attribute \src "libresoc.v:173333.18-173333.99" + wire width 4 $or$libresoc.v:173333$11794_Y + attribute \src "libresoc.v:173336.17-173336.97" + wire width 4 $or$libresoc.v:173336$11797_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -351820,11 +359750,11 @@ module \req_l$83 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169870.7-169870.15" + attribute \src "libresoc.v:173295.7-173295.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int @@ -351841,7 +359771,7 @@ module \req_l$83 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:169905$11393 + cell $and $and$libresoc.v:173330$11791 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -351849,10 +359779,10 @@ module \req_l$83 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:169905$11393_Y + connect \Y $and$libresoc.v:173330$11791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169910$11398 + cell $and $and$libresoc.v:173335$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -351860,34 +359790,34 @@ module \req_l$83 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169910$11398_Y + connect \Y $and$libresoc.v:173335$11796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169907$11395 + cell $not $not$libresoc.v:173332$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:169907$11395_Y + connect \Y $not$libresoc.v:173332$11793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169909$11397 + cell $not $not$libresoc.v:173334$11795 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:169909$11397_Y + connect \Y $not$libresoc.v:173334$11795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:169912$11400 + cell $not $not$libresoc.v:173337$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:169912$11400_Y + connect \Y $not$libresoc.v:173337$11798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:169906$11394 + cell $or $or$libresoc.v:173331$11792 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -351895,10 +359825,10 @@ module \req_l$83 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:169906$11394_Y + connect \Y $or$libresoc.v:173331$11792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169908$11396 + cell $or $or$libresoc.v:173333$11794 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -351906,10 +359836,10 @@ module \req_l$83 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:169908$11396_Y + connect \Y $or$libresoc.v:173333$11794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169911$11399 + cell $or $or$libresoc.v:173336$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -351917,39 +359847,39 @@ module \req_l$83 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:169911$11399_Y + connect \Y $or$libresoc.v:173336$11797_Y end - attribute \src "libresoc.v:169870.7-169870.20" - process $proc$libresoc.v:169870$11405 + attribute \src "libresoc.v:173295.7-173295.20" + process $proc$libresoc.v:173295$11803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169892.13-169892.25" - process $proc$libresoc.v:169892$11406 + attribute \src "libresoc.v:173317.13-173317.25" + process $proc$libresoc.v:173317$11804 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:169913.3-169914.27" - process $proc$libresoc.v:169913$11401 + attribute \src "libresoc.v:173338.3-173339.27" + process $proc$libresoc.v:173338$11799 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:169915.3-169923.6" - process $proc$libresoc.v:169915$11402 + attribute \src "libresoc.v:173340.3-173348.6" + process $proc$libresoc.v:173340$11800 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11403 $1\q_int$next[3:0]$11404 - attribute \src "libresoc.v:169916.5-169916.29" + assign $0\q_int$next[3:0]$11801 $1\q_int$next[3:0]$11802 + attribute \src "libresoc.v:173341.5-173341.29" switch \initial - attribute \src "libresoc.v:169916.9-169916.17" + attribute \src "libresoc.v:173341.9-173341.17" case 1'1 case end @@ -351958,50 +359888,50 @@ module \req_l$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11404 4'0000 + assign $1\q_int$next[3:0]$11802 4'0000 case - assign $1\q_int$next[3:0]$11404 \$5 + assign $1\q_int$next[3:0]$11802 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11403 + update \q_int$next $0\q_int$next[3:0]$11801 end - connect \$9 $and$libresoc.v:169905$11393_Y - connect \$11 $or$libresoc.v:169906$11394_Y - connect \$13 $not$libresoc.v:169907$11395_Y - connect \$15 $or$libresoc.v:169908$11396_Y - connect \$1 $not$libresoc.v:169909$11397_Y - connect \$3 $and$libresoc.v:169910$11398_Y - connect \$5 $or$libresoc.v:169911$11399_Y - connect \$7 $not$libresoc.v:169912$11400_Y + connect \$9 $and$libresoc.v:173330$11791_Y + connect \$11 $or$libresoc.v:173331$11792_Y + connect \$13 $not$libresoc.v:173332$11793_Y + connect \$15 $or$libresoc.v:173333$11794_Y + connect \$1 $not$libresoc.v:173334$11795_Y + connect \$3 $and$libresoc.v:173335$11796_Y + connect \$5 $or$libresoc.v:173336$11797_Y + connect \$7 $not$libresoc.v:173337$11798_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:169931.1-169980.10" +attribute \src "libresoc.v:173356.1-173405.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:169932.7-169932.20" + attribute \src "libresoc.v:173357.7-173357.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169968.3-169976.6" - wire $0\q_int$next[0:0]$11414 - attribute \src "libresoc.v:169966.3-169967.27" + attribute \src "libresoc.v:173393.3-173401.6" + wire $0\q_int$next[0:0]$11812 + attribute \src "libresoc.v:173391.3-173392.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:169968.3-169976.6" - wire $1\q_int$next[0:0]$11415 - attribute \src "libresoc.v:169948.7-169948.19" + attribute \src "libresoc.v:173393.3-173401.6" + wire $1\q_int$next[0:0]$11813 + attribute \src "libresoc.v:173373.7-173373.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:169963.17-169963.96" - wire $and$libresoc.v:169963$11409_Y - attribute \src "libresoc.v:169962.17-169962.94" - wire $not$libresoc.v:169962$11408_Y - attribute \src "libresoc.v:169965.17-169965.94" - wire $not$libresoc.v:169965$11411_Y - attribute \src "libresoc.v:169961.17-169961.100" - wire $or$libresoc.v:169961$11407_Y - attribute \src "libresoc.v:169964.17-169964.99" - wire $or$libresoc.v:169964$11410_Y + attribute \src "libresoc.v:173388.17-173388.96" + wire $and$libresoc.v:173388$11807_Y + attribute \src "libresoc.v:173387.17-173387.94" + wire $not$libresoc.v:173387$11806_Y + attribute \src "libresoc.v:173390.17-173390.94" + wire $not$libresoc.v:173390$11809_Y + attribute \src "libresoc.v:173386.17-173386.100" + wire $or$libresoc.v:173386$11805_Y + attribute \src "libresoc.v:173389.17-173389.99" + wire $or$libresoc.v:173389$11808_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" @@ -352012,11 +359942,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169932.7-169932.15" + attribute \src "libresoc.v:173357.7-173357.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -352033,7 +359963,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:169963$11409 + cell $and $and$libresoc.v:173388$11807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352041,26 +359971,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:169963$11409_Y + connect \Y $and$libresoc.v:173388$11807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:169962$11408 + cell $not $not$libresoc.v:173387$11806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:169962$11408_Y + connect \Y $not$libresoc.v:173387$11806_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:169965$11411 + cell $not $not$libresoc.v:173390$11809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:169965$11411_Y + connect \Y $not$libresoc.v:173390$11809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:169961$11407 + cell $or $or$libresoc.v:173386$11805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352068,10 +359998,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:169961$11407_Y + connect \Y $or$libresoc.v:173386$11805_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:169964$11410 + cell $or $or$libresoc.v:173389$11808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352079,39 +360009,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:169964$11410_Y + connect \Y $or$libresoc.v:173389$11808_Y end - attribute \src "libresoc.v:169932.7-169932.20" - process $proc$libresoc.v:169932$11416 + attribute \src "libresoc.v:173357.7-173357.20" + process $proc$libresoc.v:173357$11814 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169948.7-169948.19" - process $proc$libresoc.v:169948$11417 + attribute \src "libresoc.v:173373.7-173373.19" + process $proc$libresoc.v:173373$11815 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:169966.3-169967.27" - process $proc$libresoc.v:169966$11412 + attribute \src "libresoc.v:173391.3-173392.27" + process $proc$libresoc.v:173391$11810 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:169968.3-169976.6" - process $proc$libresoc.v:169968$11413 + attribute \src "libresoc.v:173393.3-173401.6" + process $proc$libresoc.v:173393$11811 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11414 $1\q_int$next[0:0]$11415 - attribute \src "libresoc.v:169969.5-169969.29" + assign $0\q_int$next[0:0]$11812 $1\q_int$next[0:0]$11813 + attribute \src "libresoc.v:173394.5-173394.29" switch \initial - attribute \src "libresoc.v:169969.9-169969.17" + attribute \src "libresoc.v:173394.9-173394.17" case 1'1 case end @@ -352120,47 +360050,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11415 1'0 + assign $1\q_int$next[0:0]$11813 1'0 case - assign $1\q_int$next[0:0]$11415 \$5 + assign $1\q_int$next[0:0]$11813 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11414 + update \q_int$next $0\q_int$next[0:0]$11812 end - connect \$9 $or$libresoc.v:169961$11407_Y - connect \$1 $not$libresoc.v:169962$11408_Y - connect \$3 $and$libresoc.v:169963$11409_Y - connect \$5 $or$libresoc.v:169964$11410_Y - connect \$7 $not$libresoc.v:169965$11411_Y + connect \$9 $or$libresoc.v:173386$11805_Y + connect \$1 $not$libresoc.v:173387$11806_Y + connect \$3 $and$libresoc.v:173388$11807_Y + connect \$5 $or$libresoc.v:173389$11808_Y + connect \$7 $not$libresoc.v:173390$11809_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:169984.1-170033.10" +attribute \src "libresoc.v:173409.1-173458.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" -module \reset_l$128 - attribute \src "libresoc.v:169985.7-169985.20" +module \reset_l$131 + attribute \src "libresoc.v:173410.7-173410.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170021.3-170029.6" - wire $0\q_int$next[0:0]$11425 - attribute \src "libresoc.v:170019.3-170020.27" + attribute \src "libresoc.v:173446.3-173454.6" + wire $0\q_int$next[0:0]$11823 + attribute \src "libresoc.v:173444.3-173445.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170021.3-170029.6" - wire $1\q_int$next[0:0]$11426 - attribute \src "libresoc.v:170001.7-170001.19" + attribute \src "libresoc.v:173446.3-173454.6" + wire $1\q_int$next[0:0]$11824 + attribute \src "libresoc.v:173426.7-173426.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170016.17-170016.96" - wire $and$libresoc.v:170016$11420_Y - attribute \src "libresoc.v:170015.17-170015.94" - wire $not$libresoc.v:170015$11419_Y - attribute \src "libresoc.v:170018.17-170018.94" - wire $not$libresoc.v:170018$11422_Y - attribute \src "libresoc.v:170014.17-170014.100" - wire $or$libresoc.v:170014$11418_Y - attribute \src "libresoc.v:170017.17-170017.99" - wire $or$libresoc.v:170017$11421_Y + attribute \src "libresoc.v:173441.17-173441.96" + wire $and$libresoc.v:173441$11818_Y + attribute \src "libresoc.v:173440.17-173440.94" + wire $not$libresoc.v:173440$11817_Y + attribute \src "libresoc.v:173443.17-173443.94" + wire $not$libresoc.v:173443$11820_Y + attribute \src "libresoc.v:173439.17-173439.100" + wire $or$libresoc.v:173439$11816_Y + attribute \src "libresoc.v:173442.17-173442.99" + wire $or$libresoc.v:173442$11819_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" @@ -352171,11 +360101,11 @@ module \reset_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:169985.7-169985.15" + attribute \src "libresoc.v:173410.7-173410.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -352192,7 +360122,7 @@ module \reset_l$128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170016$11420 + cell $and $and$libresoc.v:173441$11818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352200,26 +360130,26 @@ module \reset_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170016$11420_Y + connect \Y $and$libresoc.v:173441$11818_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170015$11419 + cell $not $not$libresoc.v:173440$11817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:170015$11419_Y + connect \Y $not$libresoc.v:173440$11817_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170018$11422 + cell $not $not$libresoc.v:173443$11820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:170018$11422_Y + connect \Y $not$libresoc.v:173443$11820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170014$11418 + cell $or $or$libresoc.v:173439$11816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352227,10 +360157,10 @@ module \reset_l$128 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:170014$11418_Y + connect \Y $or$libresoc.v:173439$11816_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170017$11421 + cell $or $or$libresoc.v:173442$11819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352238,39 +360168,39 @@ module \reset_l$128 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:170017$11421_Y + connect \Y $or$libresoc.v:173442$11819_Y end - attribute \src "libresoc.v:169985.7-169985.20" - process $proc$libresoc.v:169985$11427 + attribute \src "libresoc.v:173410.7-173410.20" + process $proc$libresoc.v:173410$11825 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170001.7-170001.19" - process $proc$libresoc.v:170001$11428 + attribute \src "libresoc.v:173426.7-173426.19" + process $proc$libresoc.v:173426$11826 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170019.3-170020.27" - process $proc$libresoc.v:170019$11423 + attribute \src "libresoc.v:173444.3-173445.27" + process $proc$libresoc.v:173444$11821 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170021.3-170029.6" - process $proc$libresoc.v:170021$11424 + attribute \src "libresoc.v:173446.3-173454.6" + process $proc$libresoc.v:173446$11822 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11425 $1\q_int$next[0:0]$11426 - attribute \src "libresoc.v:170022.5-170022.29" + assign $0\q_int$next[0:0]$11823 $1\q_int$next[0:0]$11824 + attribute \src "libresoc.v:173447.5-173447.29" switch \initial - attribute \src "libresoc.v:170022.9-170022.17" + attribute \src "libresoc.v:173447.9-173447.17" case 1'1 case end @@ -352279,287 +360209,287 @@ module \reset_l$128 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11426 1'0 + assign $1\q_int$next[0:0]$11824 1'0 case - assign $1\q_int$next[0:0]$11426 \$5 + assign $1\q_int$next[0:0]$11824 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11425 + update \q_int$next $0\q_int$next[0:0]$11823 end - connect \$9 $or$libresoc.v:170014$11418_Y - connect \$1 $not$libresoc.v:170015$11419_Y - connect \$3 $and$libresoc.v:170016$11420_Y - connect \$5 $or$libresoc.v:170017$11421_Y - connect \$7 $not$libresoc.v:170018$11422_Y + connect \$9 $or$libresoc.v:173439$11816_Y + connect \$1 $not$libresoc.v:173440$11817_Y + connect \$3 $and$libresoc.v:173441$11818_Y + connect \$5 $or$libresoc.v:173442$11819_Y + connect \$7 $not$libresoc.v:173443$11820_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:170037.1-170624.10" +attribute \src "libresoc.v:173462.1-174049.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:170038.7-170038.20" + attribute \src "libresoc.v:173463.7-173463.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $10\mask[9:9] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $11\mask[10:10] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $12\mask[11:11] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $13\mask[12:12] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $14\mask[13:13] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $15\mask[14:14] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $16\mask[15:15] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $17\mask[16:16] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $18\mask[17:17] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $19\mask[18:18] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $1\mask[0:0] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $20\mask[19:19] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $21\mask[20:20] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $22\mask[21:21] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $23\mask[22:22] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $24\mask[23:23] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $25\mask[24:24] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $26\mask[25:25] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $27\mask[26:26] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $28\mask[27:27] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $29\mask[28:28] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $2\mask[1:1] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $30\mask[29:29] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $31\mask[30:30] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $32\mask[31:31] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $33\mask[32:32] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $34\mask[33:33] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $35\mask[34:34] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $36\mask[35:35] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $37\mask[36:36] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $38\mask[37:37] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $39\mask[38:38] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $3\mask[2:2] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $40\mask[39:39] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $41\mask[40:40] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $42\mask[41:41] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $43\mask[42:42] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $44\mask[43:43] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $45\mask[44:44] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $46\mask[45:45] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $47\mask[46:46] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $48\mask[47:47] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $49\mask[48:48] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $4\mask[3:3] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $50\mask[49:49] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $51\mask[50:50] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $52\mask[51:51] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $53\mask[52:52] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $54\mask[53:53] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $55\mask[54:54] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $56\mask[55:55] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $57\mask[56:56] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $58\mask[57:57] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $59\mask[58:58] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $5\mask[4:4] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $60\mask[59:59] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $61\mask[60:60] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $62\mask[61:61] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $63\mask[62:62] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $64\mask[63:63] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $6\mask[5:5] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $7\mask[6:6] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $8\mask[7:7] - attribute \src "libresoc.v:170236.3-170623.6" + attribute \src "libresoc.v:173661.3-174048.6" wire $9\mask[8:8] - attribute \src "libresoc.v:170172.17-170172.96" - wire $gt$libresoc.v:170172$11429_Y - attribute \src "libresoc.v:170173.18-170173.98" - wire $gt$libresoc.v:170173$11430_Y - attribute \src "libresoc.v:170174.19-170174.99" - wire $gt$libresoc.v:170174$11431_Y - attribute \src "libresoc.v:170175.19-170175.99" - wire $gt$libresoc.v:170175$11432_Y - attribute \src "libresoc.v:170176.19-170176.99" - wire $gt$libresoc.v:170176$11433_Y - attribute \src "libresoc.v:170177.19-170177.99" - wire $gt$libresoc.v:170177$11434_Y - attribute \src "libresoc.v:170178.19-170178.99" - wire $gt$libresoc.v:170178$11435_Y - attribute \src "libresoc.v:170179.19-170179.99" - wire $gt$libresoc.v:170179$11436_Y - attribute \src "libresoc.v:170180.19-170180.99" - wire $gt$libresoc.v:170180$11437_Y - attribute \src "libresoc.v:170181.19-170181.99" - wire $gt$libresoc.v:170181$11438_Y - attribute \src "libresoc.v:170182.19-170182.99" - wire $gt$libresoc.v:170182$11439_Y - attribute \src "libresoc.v:170183.18-170183.97" - wire $gt$libresoc.v:170183$11440_Y - attribute \src "libresoc.v:170184.19-170184.99" - wire $gt$libresoc.v:170184$11441_Y - attribute \src "libresoc.v:170185.19-170185.99" - wire $gt$libresoc.v:170185$11442_Y - attribute \src "libresoc.v:170186.19-170186.99" - wire $gt$libresoc.v:170186$11443_Y - attribute \src "libresoc.v:170187.19-170187.99" - wire $gt$libresoc.v:170187$11444_Y - attribute \src "libresoc.v:170188.19-170188.99" - wire $gt$libresoc.v:170188$11445_Y - attribute \src "libresoc.v:170189.18-170189.97" - wire $gt$libresoc.v:170189$11446_Y - attribute \src "libresoc.v:170190.18-170190.97" - wire $gt$libresoc.v:170190$11447_Y - attribute \src "libresoc.v:170191.18-170191.97" - wire $gt$libresoc.v:170191$11448_Y - attribute \src "libresoc.v:170192.17-170192.96" - wire $gt$libresoc.v:170192$11449_Y - attribute \src "libresoc.v:170193.18-170193.97" - wire $gt$libresoc.v:170193$11450_Y - attribute \src "libresoc.v:170194.18-170194.97" - wire $gt$libresoc.v:170194$11451_Y - attribute \src "libresoc.v:170195.18-170195.97" - wire $gt$libresoc.v:170195$11452_Y - attribute \src "libresoc.v:170196.18-170196.97" - wire $gt$libresoc.v:170196$11453_Y - attribute \src "libresoc.v:170197.18-170197.97" - wire $gt$libresoc.v:170197$11454_Y - attribute \src "libresoc.v:170198.18-170198.97" - wire $gt$libresoc.v:170198$11455_Y - attribute \src "libresoc.v:170199.18-170199.97" - wire $gt$libresoc.v:170199$11456_Y - attribute \src "libresoc.v:170200.18-170200.98" - wire $gt$libresoc.v:170200$11457_Y - attribute \src "libresoc.v:170201.18-170201.98" - wire $gt$libresoc.v:170201$11458_Y - attribute \src "libresoc.v:170202.18-170202.98" - wire $gt$libresoc.v:170202$11459_Y - attribute \src "libresoc.v:170203.17-170203.96" - wire $gt$libresoc.v:170203$11460_Y - attribute \src "libresoc.v:170204.18-170204.98" - wire $gt$libresoc.v:170204$11461_Y - attribute \src "libresoc.v:170205.18-170205.98" - wire $gt$libresoc.v:170205$11462_Y - attribute \src "libresoc.v:170206.18-170206.98" - wire $gt$libresoc.v:170206$11463_Y - attribute \src "libresoc.v:170207.18-170207.98" - wire $gt$libresoc.v:170207$11464_Y - attribute \src "libresoc.v:170208.18-170208.98" - wire $gt$libresoc.v:170208$11465_Y - attribute \src "libresoc.v:170209.18-170209.98" - wire $gt$libresoc.v:170209$11466_Y - attribute \src "libresoc.v:170210.18-170210.98" - wire $gt$libresoc.v:170210$11467_Y - attribute \src "libresoc.v:170211.18-170211.98" - wire $gt$libresoc.v:170211$11468_Y - attribute \src "libresoc.v:170212.18-170212.98" - wire $gt$libresoc.v:170212$11469_Y - attribute \src "libresoc.v:170213.18-170213.98" - wire $gt$libresoc.v:170213$11470_Y - attribute \src "libresoc.v:170214.17-170214.96" - wire $gt$libresoc.v:170214$11471_Y - attribute \src "libresoc.v:170215.18-170215.98" - wire $gt$libresoc.v:170215$11472_Y - attribute \src "libresoc.v:170216.18-170216.98" - wire $gt$libresoc.v:170216$11473_Y - attribute \src "libresoc.v:170217.18-170217.98" - wire $gt$libresoc.v:170217$11474_Y - attribute \src "libresoc.v:170218.18-170218.98" - wire $gt$libresoc.v:170218$11475_Y - attribute \src "libresoc.v:170219.18-170219.98" - wire $gt$libresoc.v:170219$11476_Y - attribute \src "libresoc.v:170220.18-170220.98" - wire $gt$libresoc.v:170220$11477_Y - attribute \src "libresoc.v:170221.18-170221.98" - wire $gt$libresoc.v:170221$11478_Y - attribute \src "libresoc.v:170222.18-170222.98" - wire $gt$libresoc.v:170222$11479_Y - attribute \src "libresoc.v:170223.18-170223.98" - wire $gt$libresoc.v:170223$11480_Y - attribute \src "libresoc.v:170224.18-170224.98" - wire $gt$libresoc.v:170224$11481_Y - attribute \src "libresoc.v:170225.17-170225.96" - wire $gt$libresoc.v:170225$11482_Y - attribute \src "libresoc.v:170226.18-170226.98" - wire $gt$libresoc.v:170226$11483_Y - attribute \src "libresoc.v:170227.18-170227.98" - wire $gt$libresoc.v:170227$11484_Y - attribute \src "libresoc.v:170228.18-170228.98" - wire $gt$libresoc.v:170228$11485_Y - attribute \src "libresoc.v:170229.18-170229.98" - wire $gt$libresoc.v:170229$11486_Y - attribute \src "libresoc.v:170230.18-170230.98" - wire $gt$libresoc.v:170230$11487_Y - attribute \src "libresoc.v:170231.18-170231.98" - wire $gt$libresoc.v:170231$11488_Y - attribute \src "libresoc.v:170232.18-170232.98" - wire $gt$libresoc.v:170232$11489_Y - attribute \src "libresoc.v:170233.18-170233.98" - wire $gt$libresoc.v:170233$11490_Y - attribute \src "libresoc.v:170234.18-170234.98" - wire $gt$libresoc.v:170234$11491_Y - attribute \src "libresoc.v:170235.18-170235.98" - wire $gt$libresoc.v:170235$11492_Y + attribute \src "libresoc.v:173597.17-173597.96" + wire $gt$libresoc.v:173597$11827_Y + attribute \src "libresoc.v:173598.18-173598.98" + wire $gt$libresoc.v:173598$11828_Y + attribute \src "libresoc.v:173599.19-173599.99" + wire $gt$libresoc.v:173599$11829_Y + attribute \src "libresoc.v:173600.19-173600.99" + wire $gt$libresoc.v:173600$11830_Y + attribute \src "libresoc.v:173601.19-173601.99" + wire $gt$libresoc.v:173601$11831_Y + attribute \src "libresoc.v:173602.19-173602.99" + wire $gt$libresoc.v:173602$11832_Y + attribute \src "libresoc.v:173603.19-173603.99" + wire $gt$libresoc.v:173603$11833_Y + attribute \src "libresoc.v:173604.19-173604.99" + wire $gt$libresoc.v:173604$11834_Y + attribute \src "libresoc.v:173605.19-173605.99" + wire $gt$libresoc.v:173605$11835_Y + attribute \src "libresoc.v:173606.19-173606.99" + wire $gt$libresoc.v:173606$11836_Y + attribute \src "libresoc.v:173607.19-173607.99" + wire $gt$libresoc.v:173607$11837_Y + attribute \src "libresoc.v:173608.18-173608.97" + wire $gt$libresoc.v:173608$11838_Y + attribute \src "libresoc.v:173609.19-173609.99" + wire $gt$libresoc.v:173609$11839_Y + attribute \src "libresoc.v:173610.19-173610.99" + wire $gt$libresoc.v:173610$11840_Y + attribute \src "libresoc.v:173611.19-173611.99" + wire $gt$libresoc.v:173611$11841_Y + attribute \src "libresoc.v:173612.19-173612.99" + wire $gt$libresoc.v:173612$11842_Y + attribute \src "libresoc.v:173613.19-173613.99" + wire $gt$libresoc.v:173613$11843_Y + attribute \src "libresoc.v:173614.18-173614.97" + wire $gt$libresoc.v:173614$11844_Y + attribute \src "libresoc.v:173615.18-173615.97" + wire $gt$libresoc.v:173615$11845_Y + attribute \src "libresoc.v:173616.18-173616.97" + wire $gt$libresoc.v:173616$11846_Y + attribute \src "libresoc.v:173617.17-173617.96" + wire $gt$libresoc.v:173617$11847_Y + attribute \src "libresoc.v:173618.18-173618.97" + wire $gt$libresoc.v:173618$11848_Y + attribute \src "libresoc.v:173619.18-173619.97" + wire $gt$libresoc.v:173619$11849_Y + attribute \src "libresoc.v:173620.18-173620.97" + wire $gt$libresoc.v:173620$11850_Y + attribute \src "libresoc.v:173621.18-173621.97" + wire $gt$libresoc.v:173621$11851_Y + attribute \src "libresoc.v:173622.18-173622.97" + wire $gt$libresoc.v:173622$11852_Y + attribute \src "libresoc.v:173623.18-173623.97" + wire $gt$libresoc.v:173623$11853_Y + attribute \src "libresoc.v:173624.18-173624.97" + wire $gt$libresoc.v:173624$11854_Y + attribute \src "libresoc.v:173625.18-173625.98" + wire $gt$libresoc.v:173625$11855_Y + attribute \src "libresoc.v:173626.18-173626.98" + wire $gt$libresoc.v:173626$11856_Y + attribute \src "libresoc.v:173627.18-173627.98" + wire $gt$libresoc.v:173627$11857_Y + attribute \src "libresoc.v:173628.17-173628.96" + wire $gt$libresoc.v:173628$11858_Y + attribute \src "libresoc.v:173629.18-173629.98" + wire $gt$libresoc.v:173629$11859_Y + attribute \src "libresoc.v:173630.18-173630.98" + wire $gt$libresoc.v:173630$11860_Y + attribute \src "libresoc.v:173631.18-173631.98" + wire $gt$libresoc.v:173631$11861_Y + attribute \src "libresoc.v:173632.18-173632.98" + wire $gt$libresoc.v:173632$11862_Y + attribute \src "libresoc.v:173633.18-173633.98" + wire $gt$libresoc.v:173633$11863_Y + attribute \src "libresoc.v:173634.18-173634.98" + wire $gt$libresoc.v:173634$11864_Y + attribute \src "libresoc.v:173635.18-173635.98" + wire $gt$libresoc.v:173635$11865_Y + attribute \src "libresoc.v:173636.18-173636.98" + wire $gt$libresoc.v:173636$11866_Y + attribute \src "libresoc.v:173637.18-173637.98" + wire $gt$libresoc.v:173637$11867_Y + attribute \src "libresoc.v:173638.18-173638.98" + wire $gt$libresoc.v:173638$11868_Y + attribute \src "libresoc.v:173639.17-173639.96" + wire $gt$libresoc.v:173639$11869_Y + attribute \src "libresoc.v:173640.18-173640.98" + wire $gt$libresoc.v:173640$11870_Y + attribute \src "libresoc.v:173641.18-173641.98" + wire $gt$libresoc.v:173641$11871_Y + attribute \src "libresoc.v:173642.18-173642.98" + wire $gt$libresoc.v:173642$11872_Y + attribute \src "libresoc.v:173643.18-173643.98" + wire $gt$libresoc.v:173643$11873_Y + attribute \src "libresoc.v:173644.18-173644.98" + wire $gt$libresoc.v:173644$11874_Y + attribute \src "libresoc.v:173645.18-173645.98" + wire $gt$libresoc.v:173645$11875_Y + attribute \src "libresoc.v:173646.18-173646.98" + wire $gt$libresoc.v:173646$11876_Y + attribute \src "libresoc.v:173647.18-173647.98" + wire $gt$libresoc.v:173647$11877_Y + attribute \src "libresoc.v:173648.18-173648.98" + wire $gt$libresoc.v:173648$11878_Y + attribute \src "libresoc.v:173649.18-173649.98" + wire $gt$libresoc.v:173649$11879_Y + attribute \src "libresoc.v:173650.17-173650.96" + wire $gt$libresoc.v:173650$11880_Y + attribute \src "libresoc.v:173651.18-173651.98" + wire $gt$libresoc.v:173651$11881_Y + attribute \src "libresoc.v:173652.18-173652.98" + wire $gt$libresoc.v:173652$11882_Y + attribute \src "libresoc.v:173653.18-173653.98" + wire $gt$libresoc.v:173653$11883_Y + attribute \src "libresoc.v:173654.18-173654.98" + wire $gt$libresoc.v:173654$11884_Y + attribute \src "libresoc.v:173655.18-173655.98" + wire $gt$libresoc.v:173655$11885_Y + attribute \src "libresoc.v:173656.18-173656.98" + wire $gt$libresoc.v:173656$11886_Y + attribute \src "libresoc.v:173657.18-173657.98" + wire $gt$libresoc.v:173657$11887_Y + attribute \src "libresoc.v:173658.18-173658.98" + wire $gt$libresoc.v:173658$11888_Y + attribute \src "libresoc.v:173659.18-173659.98" + wire $gt$libresoc.v:173659$11889_Y + attribute \src "libresoc.v:173660.18-173660.98" + wire $gt$libresoc.v:173660$11890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" @@ -352688,14 +360618,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" wire \$99 - attribute \src "libresoc.v:170038.7-170038.15" + attribute \src "libresoc.v:173463.7-173463.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170172$11429 + cell $gt $gt$libresoc.v:173597$11827 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352703,10 +360633,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:170172$11429_Y + connect \Y $gt$libresoc.v:173597$11827_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170173$11430 + cell $gt $gt$libresoc.v:173598$11828 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352714,10 +360644,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:170173$11430_Y + connect \Y $gt$libresoc.v:173598$11828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170174$11431 + cell $gt $gt$libresoc.v:173599$11829 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352725,10 +360655,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:170174$11431_Y + connect \Y $gt$libresoc.v:173599$11829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170175$11432 + cell $gt $gt$libresoc.v:173600$11830 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352736,10 +360666,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:170175$11432_Y + connect \Y $gt$libresoc.v:173600$11830_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170176$11433 + cell $gt $gt$libresoc.v:173601$11831 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352747,10 +360677,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:170176$11433_Y + connect \Y $gt$libresoc.v:173601$11831_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170177$11434 + cell $gt $gt$libresoc.v:173602$11832 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352758,10 +360688,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:170177$11434_Y + connect \Y $gt$libresoc.v:173602$11832_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170178$11435 + cell $gt $gt$libresoc.v:173603$11833 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352769,10 +360699,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:170178$11435_Y + connect \Y $gt$libresoc.v:173603$11833_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170179$11436 + cell $gt $gt$libresoc.v:173604$11834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352780,10 +360710,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:170179$11436_Y + connect \Y $gt$libresoc.v:173604$11834_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170180$11437 + cell $gt $gt$libresoc.v:173605$11835 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352791,10 +360721,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:170180$11437_Y + connect \Y $gt$libresoc.v:173605$11835_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170181$11438 + cell $gt $gt$libresoc.v:173606$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352802,10 +360732,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:170181$11438_Y + connect \Y $gt$libresoc.v:173606$11836_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170182$11439 + cell $gt $gt$libresoc.v:173607$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352813,10 +360743,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:170182$11439_Y + connect \Y $gt$libresoc.v:173607$11837_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170183$11440 + cell $gt $gt$libresoc.v:173608$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352824,10 +360754,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:170183$11440_Y + connect \Y $gt$libresoc.v:173608$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170184$11441 + cell $gt $gt$libresoc.v:173609$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352835,10 +360765,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:170184$11441_Y + connect \Y $gt$libresoc.v:173609$11839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170185$11442 + cell $gt $gt$libresoc.v:173610$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352846,10 +360776,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:170185$11442_Y + connect \Y $gt$libresoc.v:173610$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170186$11443 + cell $gt $gt$libresoc.v:173611$11841 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352857,10 +360787,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:170186$11443_Y + connect \Y $gt$libresoc.v:173611$11841_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170187$11444 + cell $gt $gt$libresoc.v:173612$11842 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352868,10 +360798,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:170187$11444_Y + connect \Y $gt$libresoc.v:173612$11842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170188$11445 + cell $gt $gt$libresoc.v:173613$11843 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352879,10 +360809,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:170188$11445_Y + connect \Y $gt$libresoc.v:173613$11843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170189$11446 + cell $gt $gt$libresoc.v:173614$11844 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352890,10 +360820,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:170189$11446_Y + connect \Y $gt$libresoc.v:173614$11844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170190$11447 + cell $gt $gt$libresoc.v:173615$11845 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352901,10 +360831,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:170190$11447_Y + connect \Y $gt$libresoc.v:173615$11845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170191$11448 + cell $gt $gt$libresoc.v:173616$11846 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352912,10 +360842,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:170191$11448_Y + connect \Y $gt$libresoc.v:173616$11846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170192$11449 + cell $gt $gt$libresoc.v:173617$11847 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352923,10 +360853,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:170192$11449_Y + connect \Y $gt$libresoc.v:173617$11847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170193$11450 + cell $gt $gt$libresoc.v:173618$11848 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352934,10 +360864,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:170193$11450_Y + connect \Y $gt$libresoc.v:173618$11848_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170194$11451 + cell $gt $gt$libresoc.v:173619$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352945,10 +360875,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:170194$11451_Y + connect \Y $gt$libresoc.v:173619$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170195$11452 + cell $gt $gt$libresoc.v:173620$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352956,10 +360886,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:170195$11452_Y + connect \Y $gt$libresoc.v:173620$11850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170196$11453 + cell $gt $gt$libresoc.v:173621$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352967,10 +360897,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:170196$11453_Y + connect \Y $gt$libresoc.v:173621$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170197$11454 + cell $gt $gt$libresoc.v:173622$11852 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352978,10 +360908,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:170197$11454_Y + connect \Y $gt$libresoc.v:173622$11852_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170198$11455 + cell $gt $gt$libresoc.v:173623$11853 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352989,10 +360919,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:170198$11455_Y + connect \Y $gt$libresoc.v:173623$11853_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170199$11456 + cell $gt $gt$libresoc.v:173624$11854 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353000,10 +360930,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:170199$11456_Y + connect \Y $gt$libresoc.v:173624$11854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170200$11457 + cell $gt $gt$libresoc.v:173625$11855 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353011,10 +360941,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:170200$11457_Y + connect \Y $gt$libresoc.v:173625$11855_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170201$11458 + cell $gt $gt$libresoc.v:173626$11856 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353022,10 +360952,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:170201$11458_Y + connect \Y $gt$libresoc.v:173626$11856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170202$11459 + cell $gt $gt$libresoc.v:173627$11857 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353033,10 +360963,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:170202$11459_Y + connect \Y $gt$libresoc.v:173627$11857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170203$11460 + cell $gt $gt$libresoc.v:173628$11858 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353044,10 +360974,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:170203$11460_Y + connect \Y $gt$libresoc.v:173628$11858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170204$11461 + cell $gt $gt$libresoc.v:173629$11859 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353055,10 +360985,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:170204$11461_Y + connect \Y $gt$libresoc.v:173629$11859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170205$11462 + cell $gt $gt$libresoc.v:173630$11860 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353066,10 +360996,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:170205$11462_Y + connect \Y $gt$libresoc.v:173630$11860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170206$11463 + cell $gt $gt$libresoc.v:173631$11861 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353077,10 +361007,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:170206$11463_Y + connect \Y $gt$libresoc.v:173631$11861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170207$11464 + cell $gt $gt$libresoc.v:173632$11862 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353088,10 +361018,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:170207$11464_Y + connect \Y $gt$libresoc.v:173632$11862_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170208$11465 + cell $gt $gt$libresoc.v:173633$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353099,10 +361029,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:170208$11465_Y + connect \Y $gt$libresoc.v:173633$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170209$11466 + cell $gt $gt$libresoc.v:173634$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353110,10 +361040,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:170209$11466_Y + connect \Y $gt$libresoc.v:173634$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170210$11467 + cell $gt $gt$libresoc.v:173635$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353121,10 +361051,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:170210$11467_Y + connect \Y $gt$libresoc.v:173635$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170211$11468 + cell $gt $gt$libresoc.v:173636$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353132,10 +361062,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:170211$11468_Y + connect \Y $gt$libresoc.v:173636$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170212$11469 + cell $gt $gt$libresoc.v:173637$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353143,10 +361073,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:170212$11469_Y + connect \Y $gt$libresoc.v:173637$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170213$11470 + cell $gt $gt$libresoc.v:173638$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353154,10 +361084,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:170213$11470_Y + connect \Y $gt$libresoc.v:173638$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170214$11471 + cell $gt $gt$libresoc.v:173639$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353165,10 +361095,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:170214$11471_Y + connect \Y $gt$libresoc.v:173639$11869_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170215$11472 + cell $gt $gt$libresoc.v:173640$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353176,10 +361106,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:170215$11472_Y + connect \Y $gt$libresoc.v:173640$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170216$11473 + cell $gt $gt$libresoc.v:173641$11871 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353187,10 +361117,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:170216$11473_Y + connect \Y $gt$libresoc.v:173641$11871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170217$11474 + cell $gt $gt$libresoc.v:173642$11872 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353198,10 +361128,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:170217$11474_Y + connect \Y $gt$libresoc.v:173642$11872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170218$11475 + cell $gt $gt$libresoc.v:173643$11873 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353209,10 +361139,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:170218$11475_Y + connect \Y $gt$libresoc.v:173643$11873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170219$11476 + cell $gt $gt$libresoc.v:173644$11874 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353220,10 +361150,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:170219$11476_Y + connect \Y $gt$libresoc.v:173644$11874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170220$11477 + cell $gt $gt$libresoc.v:173645$11875 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353231,10 +361161,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:170220$11477_Y + connect \Y $gt$libresoc.v:173645$11875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170221$11478 + cell $gt $gt$libresoc.v:173646$11876 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353242,10 +361172,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:170221$11478_Y + connect \Y $gt$libresoc.v:173646$11876_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170222$11479 + cell $gt $gt$libresoc.v:173647$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353253,10 +361183,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:170222$11479_Y + connect \Y $gt$libresoc.v:173647$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170223$11480 + cell $gt $gt$libresoc.v:173648$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353264,10 +361194,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:170223$11480_Y + connect \Y $gt$libresoc.v:173648$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170224$11481 + cell $gt $gt$libresoc.v:173649$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353275,10 +361205,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:170224$11481_Y + connect \Y $gt$libresoc.v:173649$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170225$11482 + cell $gt $gt$libresoc.v:173650$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353286,10 +361216,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:170225$11482_Y + connect \Y $gt$libresoc.v:173650$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170226$11483 + cell $gt $gt$libresoc.v:173651$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353297,10 +361227,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:170226$11483_Y + connect \Y $gt$libresoc.v:173651$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170227$11484 + cell $gt $gt$libresoc.v:173652$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353308,10 +361238,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:170227$11484_Y + connect \Y $gt$libresoc.v:173652$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170228$11485 + cell $gt $gt$libresoc.v:173653$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353319,10 +361249,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:170228$11485_Y + connect \Y $gt$libresoc.v:173653$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170229$11486 + cell $gt $gt$libresoc.v:173654$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353330,10 +361260,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:170229$11486_Y + connect \Y $gt$libresoc.v:173654$11884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170230$11487 + cell $gt $gt$libresoc.v:173655$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353341,10 +361271,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:170230$11487_Y + connect \Y $gt$libresoc.v:173655$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170231$11488 + cell $gt $gt$libresoc.v:173656$11886 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353352,10 +361282,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:170231$11488_Y + connect \Y $gt$libresoc.v:173656$11886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170232$11489 + cell $gt $gt$libresoc.v:173657$11887 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353363,10 +361293,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:170232$11489_Y + connect \Y $gt$libresoc.v:173657$11887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170233$11490 + cell $gt $gt$libresoc.v:173658$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353374,10 +361304,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:170233$11490_Y + connect \Y $gt$libresoc.v:173658$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170234$11491 + cell $gt $gt$libresoc.v:173659$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353385,10 +361315,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:170234$11491_Y + connect \Y $gt$libresoc.v:173659$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:170235$11492 + cell $gt $gt$libresoc.v:173660$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -353396,18 +361326,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:170235$11492_Y + connect \Y $gt$libresoc.v:173660$11890_Y end - attribute \src "libresoc.v:170038.7-170038.20" - process $proc$libresoc.v:170038$11494 + attribute \src "libresoc.v:173463.7-173463.20" + process $proc$libresoc.v:173463$11892 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170236.3-170623.6" - process $proc$libresoc.v:170236$11493 + attribute \src "libresoc.v:173661.3-174048.6" + process $proc$libresoc.v:173661$11891 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -353474,9 +361404,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:170237.5-170237.29" + attribute \src "libresoc.v:173662.5-173662.29" switch \initial - attribute \src "libresoc.v:170237.9-170237.17" + attribute \src "libresoc.v:173662.9-173662.17" case 1'1 case end @@ -354059,102 +361989,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:170172$11429_Y - connect \$99 $gt$libresoc.v:170173$11430_Y - connect \$101 $gt$libresoc.v:170174$11431_Y - connect \$103 $gt$libresoc.v:170175$11432_Y - connect \$105 $gt$libresoc.v:170176$11433_Y - connect \$107 $gt$libresoc.v:170177$11434_Y - connect \$109 $gt$libresoc.v:170178$11435_Y - connect \$111 $gt$libresoc.v:170179$11436_Y - connect \$113 $gt$libresoc.v:170180$11437_Y - connect \$115 $gt$libresoc.v:170181$11438_Y - connect \$117 $gt$libresoc.v:170182$11439_Y - connect \$11 $gt$libresoc.v:170183$11440_Y - connect \$119 $gt$libresoc.v:170184$11441_Y - connect \$121 $gt$libresoc.v:170185$11442_Y - connect \$123 $gt$libresoc.v:170186$11443_Y - connect \$125 $gt$libresoc.v:170187$11444_Y - connect \$127 $gt$libresoc.v:170188$11445_Y - connect \$13 $gt$libresoc.v:170189$11446_Y - connect \$15 $gt$libresoc.v:170190$11447_Y - connect \$17 $gt$libresoc.v:170191$11448_Y - connect \$1 $gt$libresoc.v:170192$11449_Y - connect \$19 $gt$libresoc.v:170193$11450_Y - connect \$21 $gt$libresoc.v:170194$11451_Y - connect \$23 $gt$libresoc.v:170195$11452_Y - connect \$25 $gt$libresoc.v:170196$11453_Y - connect \$27 $gt$libresoc.v:170197$11454_Y - connect \$29 $gt$libresoc.v:170198$11455_Y - connect \$31 $gt$libresoc.v:170199$11456_Y - connect \$33 $gt$libresoc.v:170200$11457_Y - connect \$35 $gt$libresoc.v:170201$11458_Y - connect \$37 $gt$libresoc.v:170202$11459_Y - connect \$3 $gt$libresoc.v:170203$11460_Y - connect \$39 $gt$libresoc.v:170204$11461_Y - connect \$41 $gt$libresoc.v:170205$11462_Y - connect \$43 $gt$libresoc.v:170206$11463_Y - connect \$45 $gt$libresoc.v:170207$11464_Y - connect \$47 $gt$libresoc.v:170208$11465_Y - connect \$49 $gt$libresoc.v:170209$11466_Y - connect \$51 $gt$libresoc.v:170210$11467_Y - connect \$53 $gt$libresoc.v:170211$11468_Y - connect \$55 $gt$libresoc.v:170212$11469_Y - connect \$57 $gt$libresoc.v:170213$11470_Y - connect \$5 $gt$libresoc.v:170214$11471_Y - connect \$59 $gt$libresoc.v:170215$11472_Y - connect \$61 $gt$libresoc.v:170216$11473_Y - connect \$63 $gt$libresoc.v:170217$11474_Y - connect \$65 $gt$libresoc.v:170218$11475_Y - connect \$67 $gt$libresoc.v:170219$11476_Y - connect \$69 $gt$libresoc.v:170220$11477_Y - connect \$71 $gt$libresoc.v:170221$11478_Y - connect \$73 $gt$libresoc.v:170222$11479_Y - connect \$75 $gt$libresoc.v:170223$11480_Y - connect \$77 $gt$libresoc.v:170224$11481_Y - connect \$7 $gt$libresoc.v:170225$11482_Y - connect \$79 $gt$libresoc.v:170226$11483_Y - connect \$81 $gt$libresoc.v:170227$11484_Y - connect \$83 $gt$libresoc.v:170228$11485_Y - connect \$85 $gt$libresoc.v:170229$11486_Y - connect \$87 $gt$libresoc.v:170230$11487_Y - connect \$89 $gt$libresoc.v:170231$11488_Y - connect \$91 $gt$libresoc.v:170232$11489_Y - connect \$93 $gt$libresoc.v:170233$11490_Y - connect \$95 $gt$libresoc.v:170234$11491_Y - connect \$97 $gt$libresoc.v:170235$11492_Y + connect \$9 $gt$libresoc.v:173597$11827_Y + connect \$99 $gt$libresoc.v:173598$11828_Y + connect \$101 $gt$libresoc.v:173599$11829_Y + connect \$103 $gt$libresoc.v:173600$11830_Y + connect \$105 $gt$libresoc.v:173601$11831_Y + connect \$107 $gt$libresoc.v:173602$11832_Y + connect \$109 $gt$libresoc.v:173603$11833_Y + connect \$111 $gt$libresoc.v:173604$11834_Y + connect \$113 $gt$libresoc.v:173605$11835_Y + connect \$115 $gt$libresoc.v:173606$11836_Y + connect \$117 $gt$libresoc.v:173607$11837_Y + connect \$11 $gt$libresoc.v:173608$11838_Y + connect \$119 $gt$libresoc.v:173609$11839_Y + connect \$121 $gt$libresoc.v:173610$11840_Y + connect \$123 $gt$libresoc.v:173611$11841_Y + connect \$125 $gt$libresoc.v:173612$11842_Y + connect \$127 $gt$libresoc.v:173613$11843_Y + connect \$13 $gt$libresoc.v:173614$11844_Y + connect \$15 $gt$libresoc.v:173615$11845_Y + connect \$17 $gt$libresoc.v:173616$11846_Y + connect \$1 $gt$libresoc.v:173617$11847_Y + connect \$19 $gt$libresoc.v:173618$11848_Y + connect \$21 $gt$libresoc.v:173619$11849_Y + connect \$23 $gt$libresoc.v:173620$11850_Y + connect \$25 $gt$libresoc.v:173621$11851_Y + connect \$27 $gt$libresoc.v:173622$11852_Y + connect \$29 $gt$libresoc.v:173623$11853_Y + connect \$31 $gt$libresoc.v:173624$11854_Y + connect \$33 $gt$libresoc.v:173625$11855_Y + connect \$35 $gt$libresoc.v:173626$11856_Y + connect \$37 $gt$libresoc.v:173627$11857_Y + connect \$3 $gt$libresoc.v:173628$11858_Y + connect \$39 $gt$libresoc.v:173629$11859_Y + connect \$41 $gt$libresoc.v:173630$11860_Y + connect \$43 $gt$libresoc.v:173631$11861_Y + connect \$45 $gt$libresoc.v:173632$11862_Y + connect \$47 $gt$libresoc.v:173633$11863_Y + connect \$49 $gt$libresoc.v:173634$11864_Y + connect \$51 $gt$libresoc.v:173635$11865_Y + connect \$53 $gt$libresoc.v:173636$11866_Y + connect \$55 $gt$libresoc.v:173637$11867_Y + connect \$57 $gt$libresoc.v:173638$11868_Y + connect \$5 $gt$libresoc.v:173639$11869_Y + connect \$59 $gt$libresoc.v:173640$11870_Y + connect \$61 $gt$libresoc.v:173641$11871_Y + connect \$63 $gt$libresoc.v:173642$11872_Y + connect \$65 $gt$libresoc.v:173643$11873_Y + connect \$67 $gt$libresoc.v:173644$11874_Y + connect \$69 $gt$libresoc.v:173645$11875_Y + connect \$71 $gt$libresoc.v:173646$11876_Y + connect \$73 $gt$libresoc.v:173647$11877_Y + connect \$75 $gt$libresoc.v:173648$11878_Y + connect \$77 $gt$libresoc.v:173649$11879_Y + connect \$7 $gt$libresoc.v:173650$11880_Y + connect \$79 $gt$libresoc.v:173651$11881_Y + connect \$81 $gt$libresoc.v:173652$11882_Y + connect \$83 $gt$libresoc.v:173653$11883_Y + connect \$85 $gt$libresoc.v:173654$11884_Y + connect \$87 $gt$libresoc.v:173655$11885_Y + connect \$89 $gt$libresoc.v:173656$11886_Y + connect \$91 $gt$libresoc.v:173657$11887_Y + connect \$93 $gt$libresoc.v:173658$11888_Y + connect \$95 $gt$libresoc.v:173659$11889_Y + connect \$97 $gt$libresoc.v:173660$11890_Y end -attribute \src "libresoc.v:170628.1-170686.10" +attribute \src "libresoc.v:174053.1-174111.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:170629.7-170629.20" + attribute \src "libresoc.v:174054.7-174054.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170674.3-170682.6" - wire $0\q_int$next[0:0]$11505 - attribute \src "libresoc.v:170672.3-170673.27" + attribute \src "libresoc.v:174099.3-174107.6" + wire $0\q_int$next[0:0]$11903 + attribute \src "libresoc.v:174097.3-174098.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170674.3-170682.6" - wire $1\q_int$next[0:0]$11506 - attribute \src "libresoc.v:170651.7-170651.19" + attribute \src "libresoc.v:174099.3-174107.6" + wire $1\q_int$next[0:0]$11904 + attribute \src "libresoc.v:174076.7-174076.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170664.17-170664.96" - wire $and$libresoc.v:170664$11495_Y - attribute \src "libresoc.v:170669.17-170669.96" - wire $and$libresoc.v:170669$11500_Y - attribute \src "libresoc.v:170666.18-170666.94" - wire $not$libresoc.v:170666$11497_Y - attribute \src "libresoc.v:170668.17-170668.93" - wire $not$libresoc.v:170668$11499_Y - attribute \src "libresoc.v:170671.17-170671.93" - wire $not$libresoc.v:170671$11502_Y - attribute \src "libresoc.v:170665.18-170665.99" - wire $or$libresoc.v:170665$11496_Y - attribute \src "libresoc.v:170667.18-170667.100" - wire $or$libresoc.v:170667$11498_Y - attribute \src "libresoc.v:170670.17-170670.98" - wire $or$libresoc.v:170670$11501_Y + attribute \src "libresoc.v:174089.17-174089.96" + wire $and$libresoc.v:174089$11893_Y + attribute \src "libresoc.v:174094.17-174094.96" + wire $and$libresoc.v:174094$11898_Y + attribute \src "libresoc.v:174091.18-174091.94" + wire $not$libresoc.v:174091$11895_Y + attribute \src "libresoc.v:174093.17-174093.93" + wire $not$libresoc.v:174093$11897_Y + attribute \src "libresoc.v:174096.17-174096.93" + wire $not$libresoc.v:174096$11900_Y + attribute \src "libresoc.v:174090.18-174090.99" + wire $or$libresoc.v:174090$11894_Y + attribute \src "libresoc.v:174092.18-174092.100" + wire $or$libresoc.v:174092$11896_Y + attribute \src "libresoc.v:174095.17-174095.98" + wire $or$libresoc.v:174095$11899_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -354171,11 +362101,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170629.7-170629.15" + attribute \src "libresoc.v:174054.7-174054.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -354192,7 +362122,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170664$11495 + cell $and $and$libresoc.v:174089$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354200,10 +362130,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170664$11495_Y + connect \Y $and$libresoc.v:174089$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170669$11500 + cell $and $and$libresoc.v:174094$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354211,34 +362141,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170669$11500_Y + connect \Y $and$libresoc.v:174094$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170666$11497 + cell $not $not$libresoc.v:174091$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170666$11497_Y + connect \Y $not$libresoc.v:174091$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170668$11499 + cell $not $not$libresoc.v:174093$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170668$11499_Y + connect \Y $not$libresoc.v:174093$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170671$11502 + cell $not $not$libresoc.v:174096$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170671$11502_Y + connect \Y $not$libresoc.v:174096$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170665$11496 + cell $or $or$libresoc.v:174090$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354246,10 +362176,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170665$11496_Y + connect \Y $or$libresoc.v:174090$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170667$11498 + cell $or $or$libresoc.v:174092$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354257,10 +362187,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170667$11498_Y + connect \Y $or$libresoc.v:174092$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170670$11501 + cell $or $or$libresoc.v:174095$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354268,39 +362198,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170670$11501_Y + connect \Y $or$libresoc.v:174095$11899_Y end - attribute \src "libresoc.v:170629.7-170629.20" - process $proc$libresoc.v:170629$11507 + attribute \src "libresoc.v:174054.7-174054.20" + process $proc$libresoc.v:174054$11905 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170651.7-170651.19" - process $proc$libresoc.v:170651$11508 + attribute \src "libresoc.v:174076.7-174076.19" + process $proc$libresoc.v:174076$11906 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170672.3-170673.27" - process $proc$libresoc.v:170672$11503 + attribute \src "libresoc.v:174097.3-174098.27" + process $proc$libresoc.v:174097$11901 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170674.3-170682.6" - process $proc$libresoc.v:170674$11504 + attribute \src "libresoc.v:174099.3-174107.6" + process $proc$libresoc.v:174099$11902 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11505 $1\q_int$next[0:0]$11506 - attribute \src "libresoc.v:170675.5-170675.29" + assign $0\q_int$next[0:0]$11903 $1\q_int$next[0:0]$11904 + attribute \src "libresoc.v:174100.5-174100.29" switch \initial - attribute \src "libresoc.v:170675.9-170675.17" + attribute \src "libresoc.v:174100.9-174100.17" case 1'1 case end @@ -354309,56 +362239,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11506 1'0 + assign $1\q_int$next[0:0]$11904 1'0 case - assign $1\q_int$next[0:0]$11506 \$5 + assign $1\q_int$next[0:0]$11904 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11505 + update \q_int$next $0\q_int$next[0:0]$11903 end - connect \$9 $and$libresoc.v:170664$11495_Y - connect \$11 $or$libresoc.v:170665$11496_Y - connect \$13 $not$libresoc.v:170666$11497_Y - connect \$15 $or$libresoc.v:170667$11498_Y - connect \$1 $not$libresoc.v:170668$11499_Y - connect \$3 $and$libresoc.v:170669$11500_Y - connect \$5 $or$libresoc.v:170670$11501_Y - connect \$7 $not$libresoc.v:170671$11502_Y + connect \$9 $and$libresoc.v:174089$11893_Y + connect \$11 $or$libresoc.v:174090$11894_Y + connect \$13 $not$libresoc.v:174091$11895_Y + connect \$15 $or$libresoc.v:174092$11896_Y + connect \$1 $not$libresoc.v:174093$11897_Y + connect \$3 $and$libresoc.v:174094$11898_Y + connect \$5 $or$libresoc.v:174095$11899_Y + connect \$7 $not$libresoc.v:174096$11900_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:170690.1-170748.10" +attribute \src "libresoc.v:174115.1-174173.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" -module \rok_l$102 - attribute \src "libresoc.v:170691.7-170691.20" +module \rok_l$105 + attribute \src "libresoc.v:174116.7-174116.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170736.3-170744.6" - wire $0\q_int$next[0:0]$11519 - attribute \src "libresoc.v:170734.3-170735.27" + attribute \src "libresoc.v:174161.3-174169.6" + wire $0\q_int$next[0:0]$11917 + attribute \src "libresoc.v:174159.3-174160.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170736.3-170744.6" - wire $1\q_int$next[0:0]$11520 - attribute \src "libresoc.v:170713.7-170713.19" + attribute \src "libresoc.v:174161.3-174169.6" + wire $1\q_int$next[0:0]$11918 + attribute \src "libresoc.v:174138.7-174138.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170726.17-170726.96" - wire $and$libresoc.v:170726$11509_Y - attribute \src "libresoc.v:170731.17-170731.96" - wire $and$libresoc.v:170731$11514_Y - attribute \src "libresoc.v:170728.18-170728.94" - wire $not$libresoc.v:170728$11511_Y - attribute \src "libresoc.v:170730.17-170730.93" - wire $not$libresoc.v:170730$11513_Y - attribute \src "libresoc.v:170733.17-170733.93" - wire $not$libresoc.v:170733$11516_Y - attribute \src "libresoc.v:170727.18-170727.99" - wire $or$libresoc.v:170727$11510_Y - attribute \src "libresoc.v:170729.18-170729.100" - wire $or$libresoc.v:170729$11512_Y - attribute \src "libresoc.v:170732.17-170732.98" - wire $or$libresoc.v:170732$11515_Y + attribute \src "libresoc.v:174151.17-174151.96" + wire $and$libresoc.v:174151$11907_Y + attribute \src "libresoc.v:174156.17-174156.96" + wire $and$libresoc.v:174156$11912_Y + attribute \src "libresoc.v:174153.18-174153.94" + wire $not$libresoc.v:174153$11909_Y + attribute \src "libresoc.v:174155.17-174155.93" + wire $not$libresoc.v:174155$11911_Y + attribute \src "libresoc.v:174158.17-174158.93" + wire $not$libresoc.v:174158$11914_Y + attribute \src "libresoc.v:174152.18-174152.99" + wire $or$libresoc.v:174152$11908_Y + attribute \src "libresoc.v:174154.18-174154.100" + wire $or$libresoc.v:174154$11910_Y + attribute \src "libresoc.v:174157.17-174157.98" + wire $or$libresoc.v:174157$11913_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -354375,11 +362305,11 @@ module \rok_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170691.7-170691.15" + attribute \src "libresoc.v:174116.7-174116.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -354396,7 +362326,7 @@ module \rok_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170726$11509 + cell $and $and$libresoc.v:174151$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354404,10 +362334,10 @@ module \rok_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170726$11509_Y + connect \Y $and$libresoc.v:174151$11907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170731$11514 + cell $and $and$libresoc.v:174156$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354415,34 +362345,34 @@ module \rok_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170731$11514_Y + connect \Y $and$libresoc.v:174156$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170728$11511 + cell $not $not$libresoc.v:174153$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170728$11511_Y + connect \Y $not$libresoc.v:174153$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170730$11513 + cell $not $not$libresoc.v:174155$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170730$11513_Y + connect \Y $not$libresoc.v:174155$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170733$11516 + cell $not $not$libresoc.v:174158$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170733$11516_Y + connect \Y $not$libresoc.v:174158$11914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170727$11510 + cell $or $or$libresoc.v:174152$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354450,10 +362380,10 @@ module \rok_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170727$11510_Y + connect \Y $or$libresoc.v:174152$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170729$11512 + cell $or $or$libresoc.v:174154$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354461,10 +362391,10 @@ module \rok_l$102 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170729$11512_Y + connect \Y $or$libresoc.v:174154$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170732$11515 + cell $or $or$libresoc.v:174157$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354472,39 +362402,39 @@ module \rok_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170732$11515_Y + connect \Y $or$libresoc.v:174157$11913_Y end - attribute \src "libresoc.v:170691.7-170691.20" - process $proc$libresoc.v:170691$11521 + attribute \src "libresoc.v:174116.7-174116.20" + process $proc$libresoc.v:174116$11919 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170713.7-170713.19" - process $proc$libresoc.v:170713$11522 + attribute \src "libresoc.v:174138.7-174138.19" + process $proc$libresoc.v:174138$11920 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170734.3-170735.27" - process $proc$libresoc.v:170734$11517 + attribute \src "libresoc.v:174159.3-174160.27" + process $proc$libresoc.v:174159$11915 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170736.3-170744.6" - process $proc$libresoc.v:170736$11518 + attribute \src "libresoc.v:174161.3-174169.6" + process $proc$libresoc.v:174161$11916 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11519 $1\q_int$next[0:0]$11520 - attribute \src "libresoc.v:170737.5-170737.29" + assign $0\q_int$next[0:0]$11917 $1\q_int$next[0:0]$11918 + attribute \src "libresoc.v:174162.5-174162.29" switch \initial - attribute \src "libresoc.v:170737.9-170737.17" + attribute \src "libresoc.v:174162.9-174162.17" case 1'1 case end @@ -354513,56 +362443,56 @@ module \rok_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11520 1'0 + assign $1\q_int$next[0:0]$11918 1'0 case - assign $1\q_int$next[0:0]$11520 \$5 + assign $1\q_int$next[0:0]$11918 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11519 + update \q_int$next $0\q_int$next[0:0]$11917 end - connect \$9 $and$libresoc.v:170726$11509_Y - connect \$11 $or$libresoc.v:170727$11510_Y - connect \$13 $not$libresoc.v:170728$11511_Y - connect \$15 $or$libresoc.v:170729$11512_Y - connect \$1 $not$libresoc.v:170730$11513_Y - connect \$3 $and$libresoc.v:170731$11514_Y - connect \$5 $or$libresoc.v:170732$11515_Y - connect \$7 $not$libresoc.v:170733$11516_Y + connect \$9 $and$libresoc.v:174151$11907_Y + connect \$11 $or$libresoc.v:174152$11908_Y + connect \$13 $not$libresoc.v:174153$11909_Y + connect \$15 $or$libresoc.v:174154$11910_Y + connect \$1 $not$libresoc.v:174155$11911_Y + connect \$3 $and$libresoc.v:174156$11912_Y + connect \$5 $or$libresoc.v:174157$11913_Y + connect \$7 $not$libresoc.v:174158$11914_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:170752.1-170810.10" +attribute \src "libresoc.v:174177.1-174235.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" -module \rok_l$120 - attribute \src "libresoc.v:170753.7-170753.20" +module \rok_l$123 + attribute \src "libresoc.v:174178.7-174178.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170798.3-170806.6" - wire $0\q_int$next[0:0]$11533 - attribute \src "libresoc.v:170796.3-170797.27" + attribute \src "libresoc.v:174223.3-174231.6" + wire $0\q_int$next[0:0]$11931 + attribute \src "libresoc.v:174221.3-174222.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170798.3-170806.6" - wire $1\q_int$next[0:0]$11534 - attribute \src "libresoc.v:170775.7-170775.19" + attribute \src "libresoc.v:174223.3-174231.6" + wire $1\q_int$next[0:0]$11932 + attribute \src "libresoc.v:174200.7-174200.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170788.17-170788.96" - wire $and$libresoc.v:170788$11523_Y - attribute \src "libresoc.v:170793.17-170793.96" - wire $and$libresoc.v:170793$11528_Y - attribute \src "libresoc.v:170790.18-170790.94" - wire $not$libresoc.v:170790$11525_Y - attribute \src "libresoc.v:170792.17-170792.93" - wire $not$libresoc.v:170792$11527_Y - attribute \src "libresoc.v:170795.17-170795.93" - wire $not$libresoc.v:170795$11530_Y - attribute \src "libresoc.v:170789.18-170789.99" - wire $or$libresoc.v:170789$11524_Y - attribute \src "libresoc.v:170791.18-170791.100" - wire $or$libresoc.v:170791$11526_Y - attribute \src "libresoc.v:170794.17-170794.98" - wire $or$libresoc.v:170794$11529_Y + attribute \src "libresoc.v:174213.17-174213.96" + wire $and$libresoc.v:174213$11921_Y + attribute \src "libresoc.v:174218.17-174218.96" + wire $and$libresoc.v:174218$11926_Y + attribute \src "libresoc.v:174215.18-174215.94" + wire $not$libresoc.v:174215$11923_Y + attribute \src "libresoc.v:174217.17-174217.93" + wire $not$libresoc.v:174217$11925_Y + attribute \src "libresoc.v:174220.17-174220.93" + wire $not$libresoc.v:174220$11928_Y + attribute \src "libresoc.v:174214.18-174214.99" + wire $or$libresoc.v:174214$11922_Y + attribute \src "libresoc.v:174216.18-174216.100" + wire $or$libresoc.v:174216$11924_Y + attribute \src "libresoc.v:174219.17-174219.98" + wire $or$libresoc.v:174219$11927_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -354579,11 +362509,11 @@ module \rok_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170753.7-170753.15" + attribute \src "libresoc.v:174178.7-174178.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -354600,7 +362530,7 @@ module \rok_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170788$11523 + cell $and $and$libresoc.v:174213$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354608,10 +362538,10 @@ module \rok_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170788$11523_Y + connect \Y $and$libresoc.v:174213$11921_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170793$11528 + cell $and $and$libresoc.v:174218$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354619,34 +362549,34 @@ module \rok_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170793$11528_Y + connect \Y $and$libresoc.v:174218$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170790$11525 + cell $not $not$libresoc.v:174215$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170790$11525_Y + connect \Y $not$libresoc.v:174215$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170792$11527 + cell $not $not$libresoc.v:174217$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170792$11527_Y + connect \Y $not$libresoc.v:174217$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170795$11530 + cell $not $not$libresoc.v:174220$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170795$11530_Y + connect \Y $not$libresoc.v:174220$11928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170789$11524 + cell $or $or$libresoc.v:174214$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354654,10 +362584,10 @@ module \rok_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170789$11524_Y + connect \Y $or$libresoc.v:174214$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170791$11526 + cell $or $or$libresoc.v:174216$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354665,10 +362595,10 @@ module \rok_l$120 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170791$11526_Y + connect \Y $or$libresoc.v:174216$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170794$11529 + cell $or $or$libresoc.v:174219$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354676,39 +362606,39 @@ module \rok_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170794$11529_Y + connect \Y $or$libresoc.v:174219$11927_Y end - attribute \src "libresoc.v:170753.7-170753.20" - process $proc$libresoc.v:170753$11535 + attribute \src "libresoc.v:174178.7-174178.20" + process $proc$libresoc.v:174178$11933 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170775.7-170775.19" - process $proc$libresoc.v:170775$11536 + attribute \src "libresoc.v:174200.7-174200.19" + process $proc$libresoc.v:174200$11934 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170796.3-170797.27" - process $proc$libresoc.v:170796$11531 + attribute \src "libresoc.v:174221.3-174222.27" + process $proc$libresoc.v:174221$11929 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170798.3-170806.6" - process $proc$libresoc.v:170798$11532 + attribute \src "libresoc.v:174223.3-174231.6" + process $proc$libresoc.v:174223$11930 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11533 $1\q_int$next[0:0]$11534 - attribute \src "libresoc.v:170799.5-170799.29" + assign $0\q_int$next[0:0]$11931 $1\q_int$next[0:0]$11932 + attribute \src "libresoc.v:174224.5-174224.29" switch \initial - attribute \src "libresoc.v:170799.9-170799.17" + attribute \src "libresoc.v:174224.9-174224.17" case 1'1 case end @@ -354717,56 +362647,56 @@ module \rok_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11534 1'0 + assign $1\q_int$next[0:0]$11932 1'0 case - assign $1\q_int$next[0:0]$11534 \$5 + assign $1\q_int$next[0:0]$11932 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11533 + update \q_int$next $0\q_int$next[0:0]$11931 end - connect \$9 $and$libresoc.v:170788$11523_Y - connect \$11 $or$libresoc.v:170789$11524_Y - connect \$13 $not$libresoc.v:170790$11525_Y - connect \$15 $or$libresoc.v:170791$11526_Y - connect \$1 $not$libresoc.v:170792$11527_Y - connect \$3 $and$libresoc.v:170793$11528_Y - connect \$5 $or$libresoc.v:170794$11529_Y - connect \$7 $not$libresoc.v:170795$11530_Y + connect \$9 $and$libresoc.v:174213$11921_Y + connect \$11 $or$libresoc.v:174214$11922_Y + connect \$13 $not$libresoc.v:174215$11923_Y + connect \$15 $or$libresoc.v:174216$11924_Y + connect \$1 $not$libresoc.v:174217$11925_Y + connect \$3 $and$libresoc.v:174218$11926_Y + connect \$5 $or$libresoc.v:174219$11927_Y + connect \$7 $not$libresoc.v:174220$11928_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:170814.1-170872.10" +attribute \src "libresoc.v:174239.1-174297.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:170815.7-170815.20" + attribute \src "libresoc.v:174240.7-174240.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170860.3-170868.6" - wire $0\q_int$next[0:0]$11547 - attribute \src "libresoc.v:170858.3-170859.27" + attribute \src "libresoc.v:174285.3-174293.6" + wire $0\q_int$next[0:0]$11945 + attribute \src "libresoc.v:174283.3-174284.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170860.3-170868.6" - wire $1\q_int$next[0:0]$11548 - attribute \src "libresoc.v:170837.7-170837.19" + attribute \src "libresoc.v:174285.3-174293.6" + wire $1\q_int$next[0:0]$11946 + attribute \src "libresoc.v:174262.7-174262.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170850.17-170850.96" - wire $and$libresoc.v:170850$11537_Y - attribute \src "libresoc.v:170855.17-170855.96" - wire $and$libresoc.v:170855$11542_Y - attribute \src "libresoc.v:170852.18-170852.94" - wire $not$libresoc.v:170852$11539_Y - attribute \src "libresoc.v:170854.17-170854.93" - wire $not$libresoc.v:170854$11541_Y - attribute \src "libresoc.v:170857.17-170857.93" - wire $not$libresoc.v:170857$11544_Y - attribute \src "libresoc.v:170851.18-170851.99" - wire $or$libresoc.v:170851$11538_Y - attribute \src "libresoc.v:170853.18-170853.100" - wire $or$libresoc.v:170853$11540_Y - attribute \src "libresoc.v:170856.17-170856.98" - wire $or$libresoc.v:170856$11543_Y + attribute \src "libresoc.v:174275.17-174275.96" + wire $and$libresoc.v:174275$11935_Y + attribute \src "libresoc.v:174280.17-174280.96" + wire $and$libresoc.v:174280$11940_Y + attribute \src "libresoc.v:174277.18-174277.94" + wire $not$libresoc.v:174277$11937_Y + attribute \src "libresoc.v:174279.17-174279.93" + wire $not$libresoc.v:174279$11939_Y + attribute \src "libresoc.v:174282.17-174282.93" + wire $not$libresoc.v:174282$11942_Y + attribute \src "libresoc.v:174276.18-174276.99" + wire $or$libresoc.v:174276$11936_Y + attribute \src "libresoc.v:174278.18-174278.100" + wire $or$libresoc.v:174278$11938_Y + attribute \src "libresoc.v:174281.17-174281.98" + wire $or$libresoc.v:174281$11941_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -354783,11 +362713,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170815.7-170815.15" + attribute \src "libresoc.v:174240.7-174240.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -354804,7 +362734,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170850$11537 + cell $and $and$libresoc.v:174275$11935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354812,10 +362742,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170850$11537_Y + connect \Y $and$libresoc.v:174275$11935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170855$11542 + cell $and $and$libresoc.v:174280$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354823,34 +362753,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170855$11542_Y + connect \Y $and$libresoc.v:174280$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170852$11539 + cell $not $not$libresoc.v:174277$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170852$11539_Y + connect \Y $not$libresoc.v:174277$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170854$11541 + cell $not $not$libresoc.v:174279$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170854$11541_Y + connect \Y $not$libresoc.v:174279$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170857$11544 + cell $not $not$libresoc.v:174282$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170857$11544_Y + connect \Y $not$libresoc.v:174282$11942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170851$11538 + cell $or $or$libresoc.v:174276$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354858,10 +362788,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170851$11538_Y + connect \Y $or$libresoc.v:174276$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170853$11540 + cell $or $or$libresoc.v:174278$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354869,10 +362799,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170853$11540_Y + connect \Y $or$libresoc.v:174278$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170856$11543 + cell $or $or$libresoc.v:174281$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354880,39 +362810,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170856$11543_Y + connect \Y $or$libresoc.v:174281$11941_Y end - attribute \src "libresoc.v:170815.7-170815.20" - process $proc$libresoc.v:170815$11549 + attribute \src "libresoc.v:174240.7-174240.20" + process $proc$libresoc.v:174240$11947 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170837.7-170837.19" - process $proc$libresoc.v:170837$11550 + attribute \src "libresoc.v:174262.7-174262.19" + process $proc$libresoc.v:174262$11948 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170858.3-170859.27" - process $proc$libresoc.v:170858$11545 + attribute \src "libresoc.v:174283.3-174284.27" + process $proc$libresoc.v:174283$11943 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170860.3-170868.6" - process $proc$libresoc.v:170860$11546 + attribute \src "libresoc.v:174285.3-174293.6" + process $proc$libresoc.v:174285$11944 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11547 $1\q_int$next[0:0]$11548 - attribute \src "libresoc.v:170861.5-170861.29" + assign $0\q_int$next[0:0]$11945 $1\q_int$next[0:0]$11946 + attribute \src "libresoc.v:174286.5-174286.29" switch \initial - attribute \src "libresoc.v:170861.9-170861.17" + attribute \src "libresoc.v:174286.9-174286.17" case 1'1 case end @@ -354921,56 +362851,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11548 1'0 + assign $1\q_int$next[0:0]$11946 1'0 case - assign $1\q_int$next[0:0]$11548 \$5 + assign $1\q_int$next[0:0]$11946 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11547 + update \q_int$next $0\q_int$next[0:0]$11945 end - connect \$9 $and$libresoc.v:170850$11537_Y - connect \$11 $or$libresoc.v:170851$11538_Y - connect \$13 $not$libresoc.v:170852$11539_Y - connect \$15 $or$libresoc.v:170853$11540_Y - connect \$1 $not$libresoc.v:170854$11541_Y - connect \$3 $and$libresoc.v:170855$11542_Y - connect \$5 $or$libresoc.v:170856$11543_Y - connect \$7 $not$libresoc.v:170857$11544_Y + connect \$9 $and$libresoc.v:174275$11935_Y + connect \$11 $or$libresoc.v:174276$11936_Y + connect \$13 $not$libresoc.v:174277$11937_Y + connect \$15 $or$libresoc.v:174278$11938_Y + connect \$1 $not$libresoc.v:174279$11939_Y + connect \$3 $and$libresoc.v:174280$11940_Y + connect \$5 $or$libresoc.v:174281$11941_Y + connect \$7 $not$libresoc.v:174282$11942_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:170876.1-170934.10" +attribute \src "libresoc.v:174301.1-174359.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:170877.7-170877.20" + attribute \src "libresoc.v:174302.7-174302.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170922.3-170930.6" - wire $0\q_int$next[0:0]$11561 - attribute \src "libresoc.v:170920.3-170921.27" + attribute \src "libresoc.v:174347.3-174355.6" + wire $0\q_int$next[0:0]$11959 + attribute \src "libresoc.v:174345.3-174346.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170922.3-170930.6" - wire $1\q_int$next[0:0]$11562 - attribute \src "libresoc.v:170899.7-170899.19" + attribute \src "libresoc.v:174347.3-174355.6" + wire $1\q_int$next[0:0]$11960 + attribute \src "libresoc.v:174324.7-174324.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170912.17-170912.96" - wire $and$libresoc.v:170912$11551_Y - attribute \src "libresoc.v:170917.17-170917.96" - wire $and$libresoc.v:170917$11556_Y - attribute \src "libresoc.v:170914.18-170914.94" - wire $not$libresoc.v:170914$11553_Y - attribute \src "libresoc.v:170916.17-170916.93" - wire $not$libresoc.v:170916$11555_Y - attribute \src "libresoc.v:170919.17-170919.93" - wire $not$libresoc.v:170919$11558_Y - attribute \src "libresoc.v:170913.18-170913.99" - wire $or$libresoc.v:170913$11552_Y - attribute \src "libresoc.v:170915.18-170915.100" - wire $or$libresoc.v:170915$11554_Y - attribute \src "libresoc.v:170918.17-170918.98" - wire $or$libresoc.v:170918$11557_Y + attribute \src "libresoc.v:174337.17-174337.96" + wire $and$libresoc.v:174337$11949_Y + attribute \src "libresoc.v:174342.17-174342.96" + wire $and$libresoc.v:174342$11954_Y + attribute \src "libresoc.v:174339.18-174339.94" + wire $not$libresoc.v:174339$11951_Y + attribute \src "libresoc.v:174341.17-174341.93" + wire $not$libresoc.v:174341$11953_Y + attribute \src "libresoc.v:174344.17-174344.93" + wire $not$libresoc.v:174344$11956_Y + attribute \src "libresoc.v:174338.18-174338.99" + wire $or$libresoc.v:174338$11950_Y + attribute \src "libresoc.v:174340.18-174340.100" + wire $or$libresoc.v:174340$11952_Y + attribute \src "libresoc.v:174343.17-174343.98" + wire $or$libresoc.v:174343$11955_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -354987,11 +362917,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170877.7-170877.15" + attribute \src "libresoc.v:174302.7-174302.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -355008,7 +362938,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170912$11551 + cell $and $and$libresoc.v:174337$11949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355016,10 +362946,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170912$11551_Y + connect \Y $and$libresoc.v:174337$11949_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170917$11556 + cell $and $and$libresoc.v:174342$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355027,34 +362957,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170917$11556_Y + connect \Y $and$libresoc.v:174342$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170914$11553 + cell $not $not$libresoc.v:174339$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170914$11553_Y + connect \Y $not$libresoc.v:174339$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170916$11555 + cell $not $not$libresoc.v:174341$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170916$11555_Y + connect \Y $not$libresoc.v:174341$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170919$11558 + cell $not $not$libresoc.v:174344$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170919$11558_Y + connect \Y $not$libresoc.v:174344$11956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170913$11552 + cell $or $or$libresoc.v:174338$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355062,10 +362992,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170913$11552_Y + connect \Y $or$libresoc.v:174338$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170915$11554 + cell $or $or$libresoc.v:174340$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355073,10 +363003,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170915$11554_Y + connect \Y $or$libresoc.v:174340$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170918$11557 + cell $or $or$libresoc.v:174343$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355084,39 +363014,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170918$11557_Y + connect \Y $or$libresoc.v:174343$11955_Y end - attribute \src "libresoc.v:170877.7-170877.20" - process $proc$libresoc.v:170877$11563 + attribute \src "libresoc.v:174302.7-174302.20" + process $proc$libresoc.v:174302$11961 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170899.7-170899.19" - process $proc$libresoc.v:170899$11564 + attribute \src "libresoc.v:174324.7-174324.19" + process $proc$libresoc.v:174324$11962 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170920.3-170921.27" - process $proc$libresoc.v:170920$11559 + attribute \src "libresoc.v:174345.3-174346.27" + process $proc$libresoc.v:174345$11957 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170922.3-170930.6" - process $proc$libresoc.v:170922$11560 + attribute \src "libresoc.v:174347.3-174355.6" + process $proc$libresoc.v:174347$11958 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11561 $1\q_int$next[0:0]$11562 - attribute \src "libresoc.v:170923.5-170923.29" + assign $0\q_int$next[0:0]$11959 $1\q_int$next[0:0]$11960 + attribute \src "libresoc.v:174348.5-174348.29" switch \initial - attribute \src "libresoc.v:170923.9-170923.17" + attribute \src "libresoc.v:174348.9-174348.17" case 1'1 case end @@ -355125,56 +363055,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11562 1'0 + assign $1\q_int$next[0:0]$11960 1'0 case - assign $1\q_int$next[0:0]$11562 \$5 + assign $1\q_int$next[0:0]$11960 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11561 + update \q_int$next $0\q_int$next[0:0]$11959 end - connect \$9 $and$libresoc.v:170912$11551_Y - connect \$11 $or$libresoc.v:170913$11552_Y - connect \$13 $not$libresoc.v:170914$11553_Y - connect \$15 $or$libresoc.v:170915$11554_Y - connect \$1 $not$libresoc.v:170916$11555_Y - connect \$3 $and$libresoc.v:170917$11556_Y - connect \$5 $or$libresoc.v:170918$11557_Y - connect \$7 $not$libresoc.v:170919$11558_Y + connect \$9 $and$libresoc.v:174337$11949_Y + connect \$11 $or$libresoc.v:174338$11950_Y + connect \$13 $not$libresoc.v:174339$11951_Y + connect \$15 $or$libresoc.v:174340$11952_Y + connect \$1 $not$libresoc.v:174341$11953_Y + connect \$3 $and$libresoc.v:174342$11954_Y + connect \$5 $or$libresoc.v:174343$11955_Y + connect \$7 $not$libresoc.v:174344$11956_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:170938.1-170996.10" +attribute \src "libresoc.v:174363.1-174421.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" -module \rok_l$40 - attribute \src "libresoc.v:170939.7-170939.20" +module \rok_l$43 + attribute \src "libresoc.v:174364.7-174364.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170984.3-170992.6" - wire $0\q_int$next[0:0]$11575 - attribute \src "libresoc.v:170982.3-170983.27" + attribute \src "libresoc.v:174409.3-174417.6" + wire $0\q_int$next[0:0]$11973 + attribute \src "libresoc.v:174407.3-174408.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:170984.3-170992.6" - wire $1\q_int$next[0:0]$11576 - attribute \src "libresoc.v:170961.7-170961.19" + attribute \src "libresoc.v:174409.3-174417.6" + wire $1\q_int$next[0:0]$11974 + attribute \src "libresoc.v:174386.7-174386.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:170974.17-170974.96" - wire $and$libresoc.v:170974$11565_Y - attribute \src "libresoc.v:170979.17-170979.96" - wire $and$libresoc.v:170979$11570_Y - attribute \src "libresoc.v:170976.18-170976.94" - wire $not$libresoc.v:170976$11567_Y - attribute \src "libresoc.v:170978.17-170978.93" - wire $not$libresoc.v:170978$11569_Y - attribute \src "libresoc.v:170981.17-170981.93" - wire $not$libresoc.v:170981$11572_Y - attribute \src "libresoc.v:170975.18-170975.99" - wire $or$libresoc.v:170975$11566_Y - attribute \src "libresoc.v:170977.18-170977.100" - wire $or$libresoc.v:170977$11568_Y - attribute \src "libresoc.v:170980.17-170980.98" - wire $or$libresoc.v:170980$11571_Y + attribute \src "libresoc.v:174399.17-174399.96" + wire $and$libresoc.v:174399$11963_Y + attribute \src "libresoc.v:174404.17-174404.96" + wire $and$libresoc.v:174404$11968_Y + attribute \src "libresoc.v:174401.18-174401.94" + wire $not$libresoc.v:174401$11965_Y + attribute \src "libresoc.v:174403.17-174403.93" + wire $not$libresoc.v:174403$11967_Y + attribute \src "libresoc.v:174406.17-174406.93" + wire $not$libresoc.v:174406$11970_Y + attribute \src "libresoc.v:174400.18-174400.99" + wire $or$libresoc.v:174400$11964_Y + attribute \src "libresoc.v:174402.18-174402.100" + wire $or$libresoc.v:174402$11966_Y + attribute \src "libresoc.v:174405.17-174405.98" + wire $or$libresoc.v:174405$11969_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -355191,11 +363121,11 @@ module \rok_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:170939.7-170939.15" + attribute \src "libresoc.v:174364.7-174364.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -355212,7 +363142,7 @@ module \rok_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:170974$11565 + cell $and $and$libresoc.v:174399$11963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355220,10 +363150,10 @@ module \rok_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:170974$11565_Y + connect \Y $and$libresoc.v:174399$11963_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:170979$11570 + cell $and $and$libresoc.v:174404$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355231,34 +363161,34 @@ module \rok_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:170979$11570_Y + connect \Y $and$libresoc.v:174404$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:170976$11567 + cell $not $not$libresoc.v:174401$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:170976$11567_Y + connect \Y $not$libresoc.v:174401$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:170978$11569 + cell $not $not$libresoc.v:174403$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170978$11569_Y + connect \Y $not$libresoc.v:174403$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:170981$11572 + cell $not $not$libresoc.v:174406$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:170981$11572_Y + connect \Y $not$libresoc.v:174406$11970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:170975$11566 + cell $or $or$libresoc.v:174400$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355266,10 +363196,10 @@ module \rok_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:170975$11566_Y + connect \Y $or$libresoc.v:174400$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:170977$11568 + cell $or $or$libresoc.v:174402$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355277,10 +363207,10 @@ module \rok_l$40 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:170977$11568_Y + connect \Y $or$libresoc.v:174402$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:170980$11571 + cell $or $or$libresoc.v:174405$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355288,39 +363218,39 @@ module \rok_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:170980$11571_Y + connect \Y $or$libresoc.v:174405$11969_Y end - attribute \src "libresoc.v:170939.7-170939.20" - process $proc$libresoc.v:170939$11577 + attribute \src "libresoc.v:174364.7-174364.20" + process $proc$libresoc.v:174364$11975 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170961.7-170961.19" - process $proc$libresoc.v:170961$11578 + attribute \src "libresoc.v:174386.7-174386.19" + process $proc$libresoc.v:174386$11976 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:170982.3-170983.27" - process $proc$libresoc.v:170982$11573 + attribute \src "libresoc.v:174407.3-174408.27" + process $proc$libresoc.v:174407$11971 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:170984.3-170992.6" - process $proc$libresoc.v:170984$11574 + attribute \src "libresoc.v:174409.3-174417.6" + process $proc$libresoc.v:174409$11972 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11575 $1\q_int$next[0:0]$11576 - attribute \src "libresoc.v:170985.5-170985.29" + assign $0\q_int$next[0:0]$11973 $1\q_int$next[0:0]$11974 + attribute \src "libresoc.v:174410.5-174410.29" switch \initial - attribute \src "libresoc.v:170985.9-170985.17" + attribute \src "libresoc.v:174410.9-174410.17" case 1'1 case end @@ -355329,56 +363259,56 @@ module \rok_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11576 1'0 + assign $1\q_int$next[0:0]$11974 1'0 case - assign $1\q_int$next[0:0]$11576 \$5 + assign $1\q_int$next[0:0]$11974 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11575 + update \q_int$next $0\q_int$next[0:0]$11973 end - connect \$9 $and$libresoc.v:170974$11565_Y - connect \$11 $or$libresoc.v:170975$11566_Y - connect \$13 $not$libresoc.v:170976$11567_Y - connect \$15 $or$libresoc.v:170977$11568_Y - connect \$1 $not$libresoc.v:170978$11569_Y - connect \$3 $and$libresoc.v:170979$11570_Y - connect \$5 $or$libresoc.v:170980$11571_Y - connect \$7 $not$libresoc.v:170981$11572_Y + connect \$9 $and$libresoc.v:174399$11963_Y + connect \$11 $or$libresoc.v:174400$11964_Y + connect \$13 $not$libresoc.v:174401$11965_Y + connect \$15 $or$libresoc.v:174402$11966_Y + connect \$1 $not$libresoc.v:174403$11967_Y + connect \$3 $and$libresoc.v:174404$11968_Y + connect \$5 $or$libresoc.v:174405$11969_Y + connect \$7 $not$libresoc.v:174406$11970_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:171000.1-171058.10" +attribute \src "libresoc.v:174425.1-174483.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" -module \rok_l$56 - attribute \src "libresoc.v:171001.7-171001.20" +module \rok_l$59 + attribute \src "libresoc.v:174426.7-174426.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171046.3-171054.6" - wire $0\q_int$next[0:0]$11589 - attribute \src "libresoc.v:171044.3-171045.27" + attribute \src "libresoc.v:174471.3-174479.6" + wire $0\q_int$next[0:0]$11987 + attribute \src "libresoc.v:174469.3-174470.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171046.3-171054.6" - wire $1\q_int$next[0:0]$11590 - attribute \src "libresoc.v:171023.7-171023.19" + attribute \src "libresoc.v:174471.3-174479.6" + wire $1\q_int$next[0:0]$11988 + attribute \src "libresoc.v:174448.7-174448.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171036.17-171036.96" - wire $and$libresoc.v:171036$11579_Y - attribute \src "libresoc.v:171041.17-171041.96" - wire $and$libresoc.v:171041$11584_Y - attribute \src "libresoc.v:171038.18-171038.94" - wire $not$libresoc.v:171038$11581_Y - attribute \src "libresoc.v:171040.17-171040.93" - wire $not$libresoc.v:171040$11583_Y - attribute \src "libresoc.v:171043.17-171043.93" - wire $not$libresoc.v:171043$11586_Y - attribute \src "libresoc.v:171037.18-171037.99" - wire $or$libresoc.v:171037$11580_Y - attribute \src "libresoc.v:171039.18-171039.100" - wire $or$libresoc.v:171039$11582_Y - attribute \src "libresoc.v:171042.17-171042.98" - wire $or$libresoc.v:171042$11585_Y + attribute \src "libresoc.v:174461.17-174461.96" + wire $and$libresoc.v:174461$11977_Y + attribute \src "libresoc.v:174466.17-174466.96" + wire $and$libresoc.v:174466$11982_Y + attribute \src "libresoc.v:174463.18-174463.94" + wire $not$libresoc.v:174463$11979_Y + attribute \src "libresoc.v:174465.17-174465.93" + wire $not$libresoc.v:174465$11981_Y + attribute \src "libresoc.v:174468.17-174468.93" + wire $not$libresoc.v:174468$11984_Y + attribute \src "libresoc.v:174462.18-174462.99" + wire $or$libresoc.v:174462$11978_Y + attribute \src "libresoc.v:174464.18-174464.100" + wire $or$libresoc.v:174464$11980_Y + attribute \src "libresoc.v:174467.17-174467.98" + wire $or$libresoc.v:174467$11983_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -355395,11 +363325,11 @@ module \rok_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171001.7-171001.15" + attribute \src "libresoc.v:174426.7-174426.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -355416,7 +363346,7 @@ module \rok_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171036$11579 + cell $and $and$libresoc.v:174461$11977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355424,10 +363354,10 @@ module \rok_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171036$11579_Y + connect \Y $and$libresoc.v:174461$11977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171041$11584 + cell $and $and$libresoc.v:174466$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355435,34 +363365,34 @@ module \rok_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171041$11584_Y + connect \Y $and$libresoc.v:174466$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171038$11581 + cell $not $not$libresoc.v:174463$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:171038$11581_Y + connect \Y $not$libresoc.v:174463$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171040$11583 + cell $not $not$libresoc.v:174465$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171040$11583_Y + connect \Y $not$libresoc.v:174465$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171043$11586 + cell $not $not$libresoc.v:174468$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171043$11586_Y + connect \Y $not$libresoc.v:174468$11984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171037$11580 + cell $or $or$libresoc.v:174462$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355470,10 +363400,10 @@ module \rok_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:171037$11580_Y + connect \Y $or$libresoc.v:174462$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171039$11582 + cell $or $or$libresoc.v:174464$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355481,10 +363411,10 @@ module \rok_l$56 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:171039$11582_Y + connect \Y $or$libresoc.v:174464$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171042$11585 + cell $or $or$libresoc.v:174467$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355492,39 +363422,39 @@ module \rok_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:171042$11585_Y + connect \Y $or$libresoc.v:174467$11983_Y end - attribute \src "libresoc.v:171001.7-171001.20" - process $proc$libresoc.v:171001$11591 + attribute \src "libresoc.v:174426.7-174426.20" + process $proc$libresoc.v:174426$11989 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171023.7-171023.19" - process $proc$libresoc.v:171023$11592 + attribute \src "libresoc.v:174448.7-174448.19" + process $proc$libresoc.v:174448$11990 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171044.3-171045.27" - process $proc$libresoc.v:171044$11587 + attribute \src "libresoc.v:174469.3-174470.27" + process $proc$libresoc.v:174469$11985 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171046.3-171054.6" - process $proc$libresoc.v:171046$11588 + attribute \src "libresoc.v:174471.3-174479.6" + process $proc$libresoc.v:174471$11986 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11589 $1\q_int$next[0:0]$11590 - attribute \src "libresoc.v:171047.5-171047.29" + assign $0\q_int$next[0:0]$11987 $1\q_int$next[0:0]$11988 + attribute \src "libresoc.v:174472.5-174472.29" switch \initial - attribute \src "libresoc.v:171047.9-171047.17" + attribute \src "libresoc.v:174472.9-174472.17" case 1'1 case end @@ -355533,56 +363463,56 @@ module \rok_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11590 1'0 + assign $1\q_int$next[0:0]$11988 1'0 case - assign $1\q_int$next[0:0]$11590 \$5 + assign $1\q_int$next[0:0]$11988 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11589 + update \q_int$next $0\q_int$next[0:0]$11987 end - connect \$9 $and$libresoc.v:171036$11579_Y - connect \$11 $or$libresoc.v:171037$11580_Y - connect \$13 $not$libresoc.v:171038$11581_Y - connect \$15 $or$libresoc.v:171039$11582_Y - connect \$1 $not$libresoc.v:171040$11583_Y - connect \$3 $and$libresoc.v:171041$11584_Y - connect \$5 $or$libresoc.v:171042$11585_Y - connect \$7 $not$libresoc.v:171043$11586_Y + connect \$9 $and$libresoc.v:174461$11977_Y + connect \$11 $or$libresoc.v:174462$11978_Y + connect \$13 $not$libresoc.v:174463$11979_Y + connect \$15 $or$libresoc.v:174464$11980_Y + connect \$1 $not$libresoc.v:174465$11981_Y + connect \$3 $and$libresoc.v:174466$11982_Y + connect \$5 $or$libresoc.v:174467$11983_Y + connect \$7 $not$libresoc.v:174468$11984_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:171062.1-171120.10" +attribute \src "libresoc.v:174487.1-174545.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" -module \rok_l$68 - attribute \src "libresoc.v:171063.7-171063.20" +module \rok_l$71 + attribute \src "libresoc.v:174488.7-174488.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171108.3-171116.6" - wire $0\q_int$next[0:0]$11603 - attribute \src "libresoc.v:171106.3-171107.27" + attribute \src "libresoc.v:174533.3-174541.6" + wire $0\q_int$next[0:0]$12001 + attribute \src "libresoc.v:174531.3-174532.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171108.3-171116.6" - wire $1\q_int$next[0:0]$11604 - attribute \src "libresoc.v:171085.7-171085.19" + attribute \src "libresoc.v:174533.3-174541.6" + wire $1\q_int$next[0:0]$12002 + attribute \src "libresoc.v:174510.7-174510.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171098.17-171098.96" - wire $and$libresoc.v:171098$11593_Y - attribute \src "libresoc.v:171103.17-171103.96" - wire $and$libresoc.v:171103$11598_Y - attribute \src "libresoc.v:171100.18-171100.94" - wire $not$libresoc.v:171100$11595_Y - attribute \src "libresoc.v:171102.17-171102.93" - wire $not$libresoc.v:171102$11597_Y - attribute \src "libresoc.v:171105.17-171105.93" - wire $not$libresoc.v:171105$11600_Y - attribute \src "libresoc.v:171099.18-171099.99" - wire $or$libresoc.v:171099$11594_Y - attribute \src "libresoc.v:171101.18-171101.100" - wire $or$libresoc.v:171101$11596_Y - attribute \src "libresoc.v:171104.17-171104.98" - wire $or$libresoc.v:171104$11599_Y + attribute \src "libresoc.v:174523.17-174523.96" + wire $and$libresoc.v:174523$11991_Y + attribute \src "libresoc.v:174528.17-174528.96" + wire $and$libresoc.v:174528$11996_Y + attribute \src "libresoc.v:174525.18-174525.94" + wire $not$libresoc.v:174525$11993_Y + attribute \src "libresoc.v:174527.17-174527.93" + wire $not$libresoc.v:174527$11995_Y + attribute \src "libresoc.v:174530.17-174530.93" + wire $not$libresoc.v:174530$11998_Y + attribute \src "libresoc.v:174524.18-174524.99" + wire $or$libresoc.v:174524$11992_Y + attribute \src "libresoc.v:174526.18-174526.100" + wire $or$libresoc.v:174526$11994_Y + attribute \src "libresoc.v:174529.17-174529.98" + wire $or$libresoc.v:174529$11997_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -355599,11 +363529,11 @@ module \rok_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171063.7-171063.15" + attribute \src "libresoc.v:174488.7-174488.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -355620,7 +363550,7 @@ module \rok_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171098$11593 + cell $and $and$libresoc.v:174523$11991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355628,10 +363558,10 @@ module \rok_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171098$11593_Y + connect \Y $and$libresoc.v:174523$11991_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171103$11598 + cell $and $and$libresoc.v:174528$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355639,34 +363569,34 @@ module \rok_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171103$11598_Y + connect \Y $and$libresoc.v:174528$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171100$11595 + cell $not $not$libresoc.v:174525$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:171100$11595_Y + connect \Y $not$libresoc.v:174525$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171102$11597 + cell $not $not$libresoc.v:174527$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171102$11597_Y + connect \Y $not$libresoc.v:174527$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171105$11600 + cell $not $not$libresoc.v:174530$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171105$11600_Y + connect \Y $not$libresoc.v:174530$11998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171099$11594 + cell $or $or$libresoc.v:174524$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355674,10 +363604,10 @@ module \rok_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:171099$11594_Y + connect \Y $or$libresoc.v:174524$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171101$11596 + cell $or $or$libresoc.v:174526$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355685,10 +363615,10 @@ module \rok_l$68 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:171101$11596_Y + connect \Y $or$libresoc.v:174526$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171104$11599 + cell $or $or$libresoc.v:174529$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355696,39 +363626,39 @@ module \rok_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:171104$11599_Y + connect \Y $or$libresoc.v:174529$11997_Y end - attribute \src "libresoc.v:171063.7-171063.20" - process $proc$libresoc.v:171063$11605 + attribute \src "libresoc.v:174488.7-174488.20" + process $proc$libresoc.v:174488$12003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171085.7-171085.19" - process $proc$libresoc.v:171085$11606 + attribute \src "libresoc.v:174510.7-174510.19" + process $proc$libresoc.v:174510$12004 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171106.3-171107.27" - process $proc$libresoc.v:171106$11601 + attribute \src "libresoc.v:174531.3-174532.27" + process $proc$libresoc.v:174531$11999 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171108.3-171116.6" - process $proc$libresoc.v:171108$11602 + attribute \src "libresoc.v:174533.3-174541.6" + process $proc$libresoc.v:174533$12000 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11603 $1\q_int$next[0:0]$11604 - attribute \src "libresoc.v:171109.5-171109.29" + assign $0\q_int$next[0:0]$12001 $1\q_int$next[0:0]$12002 + attribute \src "libresoc.v:174534.5-174534.29" switch \initial - attribute \src "libresoc.v:171109.9-171109.17" + attribute \src "libresoc.v:174534.9-174534.17" case 1'1 case end @@ -355737,56 +363667,56 @@ module \rok_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11604 1'0 + assign $1\q_int$next[0:0]$12002 1'0 case - assign $1\q_int$next[0:0]$11604 \$5 + assign $1\q_int$next[0:0]$12002 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11603 + update \q_int$next $0\q_int$next[0:0]$12001 end - connect \$9 $and$libresoc.v:171098$11593_Y - connect \$11 $or$libresoc.v:171099$11594_Y - connect \$13 $not$libresoc.v:171100$11595_Y - connect \$15 $or$libresoc.v:171101$11596_Y - connect \$1 $not$libresoc.v:171102$11597_Y - connect \$3 $and$libresoc.v:171103$11598_Y - connect \$5 $or$libresoc.v:171104$11599_Y - connect \$7 $not$libresoc.v:171105$11600_Y + connect \$9 $and$libresoc.v:174523$11991_Y + connect \$11 $or$libresoc.v:174524$11992_Y + connect \$13 $not$libresoc.v:174525$11993_Y + connect \$15 $or$libresoc.v:174526$11994_Y + connect \$1 $not$libresoc.v:174527$11995_Y + connect \$3 $and$libresoc.v:174528$11996_Y + connect \$5 $or$libresoc.v:174529$11997_Y + connect \$7 $not$libresoc.v:174530$11998_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:171124.1-171182.10" +attribute \src "libresoc.v:174549.1-174607.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" -module \rok_l$85 - attribute \src "libresoc.v:171125.7-171125.20" +module \rok_l$88 + attribute \src "libresoc.v:174550.7-174550.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171170.3-171178.6" - wire $0\q_int$next[0:0]$11617 - attribute \src "libresoc.v:171168.3-171169.27" + attribute \src "libresoc.v:174595.3-174603.6" + wire $0\q_int$next[0:0]$12015 + attribute \src "libresoc.v:174593.3-174594.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171170.3-171178.6" - wire $1\q_int$next[0:0]$11618 - attribute \src "libresoc.v:171147.7-171147.19" + attribute \src "libresoc.v:174595.3-174603.6" + wire $1\q_int$next[0:0]$12016 + attribute \src "libresoc.v:174572.7-174572.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171160.17-171160.96" - wire $and$libresoc.v:171160$11607_Y - attribute \src "libresoc.v:171165.17-171165.96" - wire $and$libresoc.v:171165$11612_Y - attribute \src "libresoc.v:171162.18-171162.94" - wire $not$libresoc.v:171162$11609_Y - attribute \src "libresoc.v:171164.17-171164.93" - wire $not$libresoc.v:171164$11611_Y - attribute \src "libresoc.v:171167.17-171167.93" - wire $not$libresoc.v:171167$11614_Y - attribute \src "libresoc.v:171161.18-171161.99" - wire $or$libresoc.v:171161$11608_Y - attribute \src "libresoc.v:171163.18-171163.100" - wire $or$libresoc.v:171163$11610_Y - attribute \src "libresoc.v:171166.17-171166.98" - wire $or$libresoc.v:171166$11613_Y + attribute \src "libresoc.v:174585.17-174585.96" + wire $and$libresoc.v:174585$12005_Y + attribute \src "libresoc.v:174590.17-174590.96" + wire $and$libresoc.v:174590$12010_Y + attribute \src "libresoc.v:174587.18-174587.94" + wire $not$libresoc.v:174587$12007_Y + attribute \src "libresoc.v:174589.17-174589.93" + wire $not$libresoc.v:174589$12009_Y + attribute \src "libresoc.v:174592.17-174592.93" + wire $not$libresoc.v:174592$12012_Y + attribute \src "libresoc.v:174586.18-174586.99" + wire $or$libresoc.v:174586$12006_Y + attribute \src "libresoc.v:174588.18-174588.100" + wire $or$libresoc.v:174588$12008_Y + attribute \src "libresoc.v:174591.17-174591.98" + wire $or$libresoc.v:174591$12011_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -355803,11 +363733,11 @@ module \rok_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171125.7-171125.15" + attribute \src "libresoc.v:174550.7-174550.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -355824,7 +363754,7 @@ module \rok_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171160$11607 + cell $and $and$libresoc.v:174585$12005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355832,10 +363762,10 @@ module \rok_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171160$11607_Y + connect \Y $and$libresoc.v:174585$12005_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171165$11612 + cell $and $and$libresoc.v:174590$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355843,34 +363773,34 @@ module \rok_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171165$11612_Y + connect \Y $and$libresoc.v:174590$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171162$11609 + cell $not $not$libresoc.v:174587$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:171162$11609_Y + connect \Y $not$libresoc.v:174587$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171164$11611 + cell $not $not$libresoc.v:174589$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171164$11611_Y + connect \Y $not$libresoc.v:174589$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171167$11614 + cell $not $not$libresoc.v:174592$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:171167$11614_Y + connect \Y $not$libresoc.v:174592$12012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171161$11608 + cell $or $or$libresoc.v:174586$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355878,10 +363808,10 @@ module \rok_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:171161$11608_Y + connect \Y $or$libresoc.v:174586$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171163$11610 + cell $or $or$libresoc.v:174588$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355889,10 +363819,10 @@ module \rok_l$85 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:171163$11610_Y + connect \Y $or$libresoc.v:174588$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171166$11613 + cell $or $or$libresoc.v:174591$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355900,39 +363830,39 @@ module \rok_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:171166$11613_Y + connect \Y $or$libresoc.v:174591$12011_Y end - attribute \src "libresoc.v:171125.7-171125.20" - process $proc$libresoc.v:171125$11619 + attribute \src "libresoc.v:174550.7-174550.20" + process $proc$libresoc.v:174550$12017 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171147.7-171147.19" - process $proc$libresoc.v:171147$11620 + attribute \src "libresoc.v:174572.7-174572.19" + process $proc$libresoc.v:174572$12018 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171168.3-171169.27" - process $proc$libresoc.v:171168$11615 + attribute \src "libresoc.v:174593.3-174594.27" + process $proc$libresoc.v:174593$12013 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171170.3-171178.6" - process $proc$libresoc.v:171170$11616 + attribute \src "libresoc.v:174595.3-174603.6" + process $proc$libresoc.v:174595$12014 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11617 $1\q_int$next[0:0]$11618 - attribute \src "libresoc.v:171171.5-171171.29" + assign $0\q_int$next[0:0]$12015 $1\q_int$next[0:0]$12016 + attribute \src "libresoc.v:174596.5-174596.29" switch \initial - attribute \src "libresoc.v:171171.9-171171.17" + attribute \src "libresoc.v:174596.9-174596.17" case 1'1 case end @@ -355941,150 +363871,150 @@ module \rok_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11618 1'0 + assign $1\q_int$next[0:0]$12016 1'0 case - assign $1\q_int$next[0:0]$11618 \$5 + assign $1\q_int$next[0:0]$12016 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11617 + update \q_int$next $0\q_int$next[0:0]$12015 end - connect \$9 $and$libresoc.v:171160$11607_Y - connect \$11 $or$libresoc.v:171161$11608_Y - connect \$13 $not$libresoc.v:171162$11609_Y - connect \$15 $or$libresoc.v:171163$11610_Y - connect \$1 $not$libresoc.v:171164$11611_Y - connect \$3 $and$libresoc.v:171165$11612_Y - connect \$5 $or$libresoc.v:171166$11613_Y - connect \$7 $not$libresoc.v:171167$11614_Y + connect \$9 $and$libresoc.v:174585$12005_Y + connect \$11 $or$libresoc.v:174586$12006_Y + connect \$13 $not$libresoc.v:174587$12007_Y + connect \$15 $or$libresoc.v:174588$12008_Y + connect \$1 $not$libresoc.v:174589$12009_Y + connect \$3 $and$libresoc.v:174590$12010_Y + connect \$5 $or$libresoc.v:174591$12011_Y + connect \$7 $not$libresoc.v:174592$12012_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:171186.1-171537.10" +attribute \src "libresoc.v:174611.1-174962.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:171455.3-171464.6" + attribute \src "libresoc.v:174880.3-174889.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:171387.3-171401.6" + attribute \src "libresoc.v:174812.3-174826.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:171187.7-171187.20" + attribute \src "libresoc.v:174612.7-174612.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171477.3-171510.6" - wire width 7 $0\mb$8[6:0]$11668 - attribute \src "libresoc.v:171511.3-171525.6" - wire width 7 $0\me$13[6:0]$11673 - attribute \src "libresoc.v:171412.3-171423.6" + attribute \src "libresoc.v:174902.3-174935.6" + wire width 7 $0\mb$8[6:0]$12066 + attribute \src "libresoc.v:174936.3-174950.6" + wire width 7 $0\me$13[6:0]$12071 + attribute \src "libresoc.v:174837.3-174848.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:171424.3-171435.6" + attribute \src "libresoc.v:174849.3-174860.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:171436.3-171454.6" + attribute \src "libresoc.v:174861.3-174879.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:171402.3-171411.6" + attribute \src "libresoc.v:174827.3-174836.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:171465.3-171476.6" + attribute \src "libresoc.v:174890.3-174901.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:171455.3-171464.6" + attribute \src "libresoc.v:174880.3-174889.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:171387.3-171401.6" + attribute \src "libresoc.v:174812.3-174826.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:171477.3-171510.6" - wire width 7 $1\mb$8[6:0]$11669 - attribute \src "libresoc.v:171511.3-171525.6" - wire width 7 $1\me$13[6:0]$11674 - attribute \src "libresoc.v:171412.3-171423.6" + attribute \src "libresoc.v:174902.3-174935.6" + wire width 7 $1\mb$8[6:0]$12067 + attribute \src "libresoc.v:174936.3-174950.6" + wire width 7 $1\me$13[6:0]$12072 + attribute \src "libresoc.v:174837.3-174848.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:171424.3-171435.6" + attribute \src "libresoc.v:174849.3-174860.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:171436.3-171454.6" + attribute \src "libresoc.v:174861.3-174879.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:171402.3-171411.6" + attribute \src "libresoc.v:174827.3-174836.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:171465.3-171476.6" + attribute \src "libresoc.v:174890.3-174901.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:171477.3-171510.6" - wire width 2 $2\mb$8[6:5]$11670 - attribute \src "libresoc.v:171477.3-171510.6" - wire width 2 $3\mb$8[6:5]$11671 - attribute \src "libresoc.v:171338.18-171338.118" - wire $and$libresoc.v:171338$11624_Y - attribute \src "libresoc.v:171340.18-171340.114" - wire $and$libresoc.v:171340$11626_Y - attribute \src "libresoc.v:171349.18-171349.113" - wire $and$libresoc.v:171349$11635_Y - attribute \src "libresoc.v:171351.18-171351.114" - wire $and$libresoc.v:171351$11637_Y - attribute \src "libresoc.v:171353.18-171353.114" - wire $and$libresoc.v:171353$11639_Y - attribute \src "libresoc.v:171354.18-171354.103" - wire width 64 $and$libresoc.v:171354$11640_Y - attribute \src "libresoc.v:171355.18-171355.106" - wire width 64 $and$libresoc.v:171355$11641_Y - attribute \src "libresoc.v:171357.18-171357.103" - wire width 64 $and$libresoc.v:171357$11643_Y - attribute \src "libresoc.v:171359.18-171359.105" - wire width 64 $and$libresoc.v:171359$11645_Y - attribute \src "libresoc.v:171362.18-171362.106" - wire width 64 $and$libresoc.v:171362$11648_Y - attribute \src "libresoc.v:171365.18-171365.105" - wire width 64 $and$libresoc.v:171365$11651_Y - attribute \src "libresoc.v:171367.17-171367.109" - wire $and$libresoc.v:171367$11653_Y - attribute \src "libresoc.v:171368.18-171368.104" - wire width 64 $and$libresoc.v:171368$11654_Y - attribute \src "libresoc.v:171372.18-171372.105" - wire width 64 $and$libresoc.v:171372$11658_Y - attribute \src "libresoc.v:171336.17-171336.98" - wire width 7 $extend$libresoc.v:171336$11621_Y - attribute \src "libresoc.v:171352.18-171352.122" - wire $gt$libresoc.v:171352$11638_Y - attribute \src "libresoc.v:171342.18-171342.111" - wire $le$libresoc.v:171342$11628_Y - attribute \src "libresoc.v:171344.18-171344.111" - wire $le$libresoc.v:171344$11630_Y - attribute \src "libresoc.v:171345.17-171345.117" - wire width 7 $neg$libresoc.v:171345$11631_Y - attribute \src "libresoc.v:171337.18-171337.103" - wire $not$libresoc.v:171337$11623_Y - attribute \src "libresoc.v:171339.18-171339.108" - wire $not$libresoc.v:171339$11625_Y - attribute \src "libresoc.v:171341.18-171341.105" - wire width 6 $not$libresoc.v:171341$11627_Y - attribute \src "libresoc.v:171347.18-171347.112" - wire width 64 $not$libresoc.v:171347$11633_Y - attribute \src "libresoc.v:171348.18-171348.109" - wire $not$libresoc.v:171348$11634_Y - attribute \src "libresoc.v:171356.17-171356.105" - wire $not$libresoc.v:171356$11642_Y - attribute \src "libresoc.v:171358.18-171358.102" - wire width 64 $not$libresoc.v:171358$11644_Y - attribute \src "libresoc.v:171364.18-171364.102" - wire width 64 $not$libresoc.v:171364$11650_Y - attribute \src "libresoc.v:171369.18-171369.100" - wire width 64 $not$libresoc.v:171369$11655_Y - attribute \src "libresoc.v:171371.18-171371.100" - wire width 64 $not$libresoc.v:171371$11657_Y - attribute \src "libresoc.v:171350.18-171350.115" - wire $or$libresoc.v:171350$11636_Y - attribute \src "libresoc.v:171360.18-171360.108" - wire width 64 $or$libresoc.v:171360$11646_Y - attribute \src "libresoc.v:171361.18-171361.103" - wire width 64 $or$libresoc.v:171361$11647_Y - attribute \src "libresoc.v:171363.18-171363.103" - wire width 64 $or$libresoc.v:171363$11649_Y - attribute \src "libresoc.v:171366.18-171366.108" - wire width 64 $or$libresoc.v:171366$11652_Y - attribute \src "libresoc.v:171370.18-171370.106" - wire width 64 $or$libresoc.v:171370$11656_Y - attribute \src "libresoc.v:171336.17-171336.98" - wire width 7 $pos$libresoc.v:171336$11622_Y - attribute \src "libresoc.v:171373.18-171373.102" - wire $reduce_or$libresoc.v:171373$11659_Y - attribute \src "libresoc.v:171343.18-171343.109" - wire width 8 $sub$libresoc.v:171343$11629_Y - attribute \src "libresoc.v:171346.18-171346.110" - wire width 8 $sub$libresoc.v:171346$11632_Y + attribute \src "libresoc.v:174902.3-174935.6" + wire width 2 $2\mb$8[6:5]$12068 + attribute \src "libresoc.v:174902.3-174935.6" + wire width 2 $3\mb$8[6:5]$12069 + attribute \src "libresoc.v:174763.18-174763.118" + wire $and$libresoc.v:174763$12022_Y + attribute \src "libresoc.v:174765.18-174765.114" + wire $and$libresoc.v:174765$12024_Y + attribute \src "libresoc.v:174774.18-174774.113" + wire $and$libresoc.v:174774$12033_Y + attribute \src "libresoc.v:174776.18-174776.114" + wire $and$libresoc.v:174776$12035_Y + attribute \src "libresoc.v:174778.18-174778.114" + wire $and$libresoc.v:174778$12037_Y + attribute \src "libresoc.v:174779.18-174779.103" + wire width 64 $and$libresoc.v:174779$12038_Y + attribute \src "libresoc.v:174780.18-174780.106" + wire width 64 $and$libresoc.v:174780$12039_Y + attribute \src "libresoc.v:174782.18-174782.103" + wire width 64 $and$libresoc.v:174782$12041_Y + attribute \src "libresoc.v:174784.18-174784.105" + wire width 64 $and$libresoc.v:174784$12043_Y + attribute \src "libresoc.v:174787.18-174787.106" + wire width 64 $and$libresoc.v:174787$12046_Y + attribute \src "libresoc.v:174790.18-174790.105" + wire width 64 $and$libresoc.v:174790$12049_Y + attribute \src "libresoc.v:174792.17-174792.109" + wire $and$libresoc.v:174792$12051_Y + attribute \src "libresoc.v:174793.18-174793.104" + wire width 64 $and$libresoc.v:174793$12052_Y + attribute \src "libresoc.v:174797.18-174797.105" + wire width 64 $and$libresoc.v:174797$12056_Y + attribute \src "libresoc.v:174761.17-174761.98" + wire width 7 $extend$libresoc.v:174761$12019_Y + attribute \src "libresoc.v:174777.18-174777.122" + wire $gt$libresoc.v:174777$12036_Y + attribute \src "libresoc.v:174767.18-174767.111" + wire $le$libresoc.v:174767$12026_Y + attribute \src "libresoc.v:174769.18-174769.111" + wire $le$libresoc.v:174769$12028_Y + attribute \src "libresoc.v:174770.17-174770.117" + wire width 7 $neg$libresoc.v:174770$12029_Y + attribute \src "libresoc.v:174762.18-174762.103" + wire $not$libresoc.v:174762$12021_Y + attribute \src "libresoc.v:174764.18-174764.108" + wire $not$libresoc.v:174764$12023_Y + attribute \src "libresoc.v:174766.18-174766.105" + wire width 6 $not$libresoc.v:174766$12025_Y + attribute \src "libresoc.v:174772.18-174772.112" + wire width 64 $not$libresoc.v:174772$12031_Y + attribute \src "libresoc.v:174773.18-174773.109" + wire $not$libresoc.v:174773$12032_Y + attribute \src "libresoc.v:174781.17-174781.105" + wire $not$libresoc.v:174781$12040_Y + attribute \src "libresoc.v:174783.18-174783.102" + wire width 64 $not$libresoc.v:174783$12042_Y + attribute \src "libresoc.v:174789.18-174789.102" + wire width 64 $not$libresoc.v:174789$12048_Y + attribute \src "libresoc.v:174794.18-174794.100" + wire width 64 $not$libresoc.v:174794$12053_Y + attribute \src "libresoc.v:174796.18-174796.100" + wire width 64 $not$libresoc.v:174796$12055_Y + attribute \src "libresoc.v:174775.18-174775.115" + wire $or$libresoc.v:174775$12034_Y + attribute \src "libresoc.v:174785.18-174785.108" + wire width 64 $or$libresoc.v:174785$12044_Y + attribute \src "libresoc.v:174786.18-174786.103" + wire width 64 $or$libresoc.v:174786$12045_Y + attribute \src "libresoc.v:174788.18-174788.103" + wire width 64 $or$libresoc.v:174788$12047_Y + attribute \src "libresoc.v:174791.18-174791.108" + wire width 64 $or$libresoc.v:174791$12050_Y + attribute \src "libresoc.v:174795.18-174795.106" + wire width 64 $or$libresoc.v:174795$12054_Y + attribute \src "libresoc.v:174761.17-174761.98" + wire width 7 $pos$libresoc.v:174761$12020_Y + attribute \src "libresoc.v:174798.18-174798.102" + wire $reduce_or$libresoc.v:174798$12057_Y + attribute \src "libresoc.v:174768.18-174768.109" + wire width 8 $sub$libresoc.v:174768$12027_Y + attribute \src "libresoc.v:174771.18-174771.110" + wire width 8 $sub$libresoc.v:174771$12030_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -356177,7 +364107,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:171187.7-171187.15" + attribute \src "libresoc.v:174612.7-174612.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -356234,7 +364164,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:171338$11624 + cell $and $and$libresoc.v:174763$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356242,10 +364172,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:171338$11624_Y + connect \Y $and$libresoc.v:174763$12022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:171340$11626 + cell $and $and$libresoc.v:174765$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356253,10 +364183,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:171340$11626_Y + connect \Y $and$libresoc.v:174765$12024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:171349$11635 + cell $and $and$libresoc.v:174774$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356264,10 +364194,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:171349$11635_Y + connect \Y $and$libresoc.v:174774$12033_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:171351$11637 + cell $and $and$libresoc.v:174776$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356275,10 +364205,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:171351$11637_Y + connect \Y $and$libresoc.v:174776$12035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:171353$11639 + cell $and $and$libresoc.v:174778$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356286,10 +364216,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:171353$11639_Y + connect \Y $and$libresoc.v:174778$12037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:171354$11640 + cell $and $and$libresoc.v:174779$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356297,10 +364227,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:171354$11640_Y + connect \Y $and$libresoc.v:174779$12038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:171355$11641 + cell $and $and$libresoc.v:174780$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356308,10 +364238,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:171355$11641_Y + connect \Y $and$libresoc.v:174780$12039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:171357$11643 + cell $and $and$libresoc.v:174782$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356319,10 +364249,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:171357$11643_Y + connect \Y $and$libresoc.v:174782$12041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:171359$11645 + cell $and $and$libresoc.v:174784$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356330,10 +364260,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:171359$11645_Y + connect \Y $and$libresoc.v:174784$12043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:171362$11648 + cell $and $and$libresoc.v:174787$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356341,10 +364271,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:171362$11648_Y + connect \Y $and$libresoc.v:174787$12046_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:171365$11651 + cell $and $and$libresoc.v:174790$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356352,10 +364282,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:171365$11651_Y + connect \Y $and$libresoc.v:174790$12049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:171367$11653 + cell $and $and$libresoc.v:174792$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356363,10 +364293,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:171367$11653_Y + connect \Y $and$libresoc.v:174792$12051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:171368$11654 + cell $and $and$libresoc.v:174793$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356374,10 +364304,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:171368$11654_Y + connect \Y $and$libresoc.v:174793$12052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:171372$11658 + cell $and $and$libresoc.v:174797$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356385,18 +364315,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:171372$11658_Y + connect \Y $and$libresoc.v:174797$12056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:171336$11621 + cell $pos $extend$libresoc.v:174761$12019 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:171336$11621_Y + connect \Y $extend$libresoc.v:174761$12019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:171352$11638 + cell $gt $gt$libresoc.v:174777$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356404,10 +364334,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:171352$11638_Y + connect \Y $gt$libresoc.v:174777$12036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:171342$11628 + cell $le $le$libresoc.v:174767$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356415,10 +364345,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:171342$11628_Y + connect \Y $le$libresoc.v:174767$12026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:171344$11630 + cell $le $le$libresoc.v:174769$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356426,98 +364356,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:171344$11630_Y + connect \Y $le$libresoc.v:174769$12028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:171345$11631 + cell $neg $neg$libresoc.v:174770$12029 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:171345$11631_Y + connect \Y $neg$libresoc.v:174770$12029_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:171337$11623 + cell $not $not$libresoc.v:174762$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:171337$11623_Y + connect \Y $not$libresoc.v:174762$12021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:171339$11625 + cell $not $not$libresoc.v:174764$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:171339$11625_Y + connect \Y $not$libresoc.v:174764$12023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:171341$11627 + cell $not $not$libresoc.v:174766$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:171341$11627_Y + connect \Y $not$libresoc.v:174766$12025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:171347$11633 + cell $not $not$libresoc.v:174772$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:171347$11633_Y + connect \Y $not$libresoc.v:174772$12031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:171348$11634 + cell $not $not$libresoc.v:174773$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:171348$11634_Y + connect \Y $not$libresoc.v:174773$12032_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:171356$11642 + cell $not $not$libresoc.v:174781$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:171356$11642_Y + connect \Y $not$libresoc.v:174781$12040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:171358$11644 + cell $not $not$libresoc.v:174783$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:171358$11644_Y + connect \Y $not$libresoc.v:174783$12042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:171364$11650 + cell $not $not$libresoc.v:174789$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:171364$11650_Y + connect \Y $not$libresoc.v:174789$12048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:171369$11655 + cell $not $not$libresoc.v:174794$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:171369$11655_Y + connect \Y $not$libresoc.v:174794$12053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:171371$11657 + cell $not $not$libresoc.v:174796$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:171371$11657_Y + connect \Y $not$libresoc.v:174796$12055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:171350$11636 + cell $or $or$libresoc.v:174775$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -356525,10 +364455,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:171350$11636_Y + connect \Y $or$libresoc.v:174775$12034_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:171360$11646 + cell $or $or$libresoc.v:174785$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356536,10 +364466,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:171360$11646_Y + connect \Y $or$libresoc.v:174785$12044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:171361$11647 + cell $or $or$libresoc.v:174786$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356547,10 +364477,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:171361$11647_Y + connect \Y $or$libresoc.v:174786$12045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:171363$11649 + cell $or $or$libresoc.v:174788$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356558,10 +364488,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:171363$11649_Y + connect \Y $or$libresoc.v:174788$12047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:171366$11652 + cell $or $or$libresoc.v:174791$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356569,10 +364499,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:171366$11652_Y + connect \Y $or$libresoc.v:174791$12050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:171370$11656 + cell $or $or$libresoc.v:174795$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -356580,26 +364510,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:171370$11656_Y + connect \Y $or$libresoc.v:174795$12054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:171336$11622 + cell $pos $pos$libresoc.v:174761$12020 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:171336$11621_Y - connect \Y $pos$libresoc.v:171336$11622_Y + connect \A $extend$libresoc.v:174761$12019_Y + connect \Y $pos$libresoc.v:174761$12020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:171373$11659 + cell $reduce_or $reduce_or$libresoc.v:174798$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:171373$11659_Y + connect \Y $reduce_or$libresoc.v:174798$12057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:171343$11629 + cell $sub $sub$libresoc.v:174768$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356607,10 +364537,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:171343$11629_Y + connect \Y $sub$libresoc.v:174768$12027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:171346$11632 + cell $sub $sub$libresoc.v:174771$12030 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356618,42 +364548,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:171346$11632_Y + connect \Y $sub$libresoc.v:174771$12030_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171374.13-171377.4" + attribute \src "libresoc.v:174799.13-174802.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:171378.14-171381.4" + attribute \src "libresoc.v:174803.14-174806.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:171382.8-171386.4" + attribute \src "libresoc.v:174807.8-174811.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:171187.7-171187.20" - process $proc$libresoc.v:171187$11675 + attribute \src "libresoc.v:174612.7-174612.20" + process $proc$libresoc.v:174612$12073 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171387.3-171401.6" - process $proc$libresoc.v:171387$11660 + attribute \src "libresoc.v:174812.3-174826.6" + process $proc$libresoc.v:174812$12058 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:171388.5-171388.29" + attribute \src "libresoc.v:174813.5-174813.29" switch \initial - attribute \src "libresoc.v:171388.9-171388.17" + attribute \src "libresoc.v:174813.9-174813.17" case 1'1 case end @@ -356675,14 +364605,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:171402.3-171411.6" - process $proc$libresoc.v:171402$11661 + attribute \src "libresoc.v:174827.3-174836.6" + process $proc$libresoc.v:174827$12059 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:171403.5-171403.29" + attribute \src "libresoc.v:174828.5-174828.29" switch \initial - attribute \src "libresoc.v:171403.9-171403.17" + attribute \src "libresoc.v:174828.9-174828.17" case 1'1 case end @@ -356698,13 +364628,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:171412.3-171423.6" - process $proc$libresoc.v:171412$11662 + attribute \src "libresoc.v:174837.3-174848.6" + process $proc$libresoc.v:174837$12060 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:171413.5-171413.29" + attribute \src "libresoc.v:174838.5-174838.29" switch \initial - attribute \src "libresoc.v:171413.9-171413.17" + attribute \src "libresoc.v:174838.9-174838.17" case 1'1 case end @@ -356722,13 +364652,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:171424.3-171435.6" - process $proc$libresoc.v:171424$11663 + attribute \src "libresoc.v:174849.3-174860.6" + process $proc$libresoc.v:174849$12061 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:171425.5-171425.29" + attribute \src "libresoc.v:174850.5-174850.29" switch \initial - attribute \src "libresoc.v:171425.9-171425.17" + attribute \src "libresoc.v:174850.9-174850.17" case 1'1 case end @@ -356746,14 +364676,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:171436.3-171454.6" - process $proc$libresoc.v:171436$11664 + attribute \src "libresoc.v:174861.3-174879.6" + process $proc$libresoc.v:174861$12062 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:171437.5-171437.29" + attribute \src "libresoc.v:174862.5-174862.29" switch \initial - attribute \src "libresoc.v:171437.9-171437.17" + attribute \src "libresoc.v:174862.9-174862.17" case 1'1 case end @@ -356781,14 +364711,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:171455.3-171464.6" - process $proc$libresoc.v:171455$11665 + attribute \src "libresoc.v:174880.3-174889.6" + process $proc$libresoc.v:174880$12063 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:171456.5-171456.29" + attribute \src "libresoc.v:174881.5-174881.29" switch \initial - attribute \src "libresoc.v:171456.9-171456.17" + attribute \src "libresoc.v:174881.9-174881.17" case 1'1 case end @@ -356804,13 +364734,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:171465.3-171476.6" - process $proc$libresoc.v:171465$11666 + attribute \src "libresoc.v:174890.3-174901.6" + process $proc$libresoc.v:174890$12064 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:171466.5-171466.29" + attribute \src "libresoc.v:174891.5-174891.29" switch \initial - attribute \src "libresoc.v:171466.9-171466.17" + attribute \src "libresoc.v:174891.9-174891.17" case 1'1 case end @@ -356828,13 +364758,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:171477.3-171510.6" - process $proc$libresoc.v:171477$11667 + attribute \src "libresoc.v:174902.3-174935.6" + process $proc$libresoc.v:174902$12065 assign { } { } - assign $0\mb$8[6:0]$11668 $1\mb$8[6:0]$11669 - attribute \src "libresoc.v:171478.5-171478.29" + assign $0\mb$8[6:0]$12066 $1\mb$8[6:0]$12067 + attribute \src "libresoc.v:174903.5-174903.29" switch \initial - attribute \src "libresoc.v:171478.9-171478.17" + attribute \src "libresoc.v:174903.9-174903.17" case 1'1 case end @@ -356843,48 +364773,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$11669 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$11669 [6:5] $2\mb$8[6:5]$11670 + assign $1\mb$8[6:0]$12067 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12067 [6:5] $2\mb$8[6:5]$12068 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$11670 2'01 + assign $2\mb$8[6:5]$12068 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$11670 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12068 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$11669 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$11669 [6:5] $3\mb$8[6:5]$11671 + assign $1\mb$8[6:0]$12067 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12067 [6:5] $3\mb$8[6:5]$12069 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$11671 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12069 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$11671 \sh [6:5] + assign $3\mb$8[6:5]$12069 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$11669 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12067 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$11668 + update \mb$8 $0\mb$8[6:0]$12066 end - attribute \src "libresoc.v:171511.3-171525.6" - process $proc$libresoc.v:171511$11672 + attribute \src "libresoc.v:174936.3-174950.6" + process $proc$libresoc.v:174936$12070 assign { } { } - assign $0\me$13[6:0]$11673 $1\me$13[6:0]$11674 - attribute \src "libresoc.v:171512.5-171512.29" + assign $0\me$13[6:0]$12071 $1\me$13[6:0]$12072 + attribute \src "libresoc.v:174937.5-174937.29" switch \initial - attribute \src "libresoc.v:171512.9-171512.17" + attribute \src "libresoc.v:174937.9-174937.17" case 1'1 case end @@ -356893,57 +364823,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$11674 { 2'01 \me } + assign $1\me$13[6:0]$12072 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$11674 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$11674 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$11673 - end - connect \$9 $pos$libresoc.v:171336$11622_Y - connect \$11 $not$libresoc.v:171337$11623_Y - connect \$14 $and$libresoc.v:171338$11624_Y - connect \$16 $not$libresoc.v:171339$11625_Y - connect \$18 $and$libresoc.v:171340$11626_Y - connect \$20 $not$libresoc.v:171341$11627_Y - connect \$22 $le$libresoc.v:171342$11628_Y - connect \$25 $sub$libresoc.v:171343$11629_Y - connect \$27 $le$libresoc.v:171344$11630_Y - connect \$2 $neg$libresoc.v:171345$11631_Y - connect \$30 $sub$libresoc.v:171346$11632_Y - connect \$32 $not$libresoc.v:171347$11633_Y - connect \$34 $not$libresoc.v:171348$11634_Y - connect \$36 $and$libresoc.v:171349$11635_Y - connect \$38 $or$libresoc.v:171350$11636_Y - connect \$40 $and$libresoc.v:171351$11637_Y - connect \$42 $gt$libresoc.v:171352$11638_Y - connect \$44 $and$libresoc.v:171353$11639_Y - connect \$46 $and$libresoc.v:171354$11640_Y - connect \$48 $and$libresoc.v:171355$11641_Y - connect \$4 $not$libresoc.v:171356$11642_Y - connect \$51 $and$libresoc.v:171357$11643_Y - connect \$50 $not$libresoc.v:171358$11644_Y - connect \$54 $and$libresoc.v:171359$11645_Y - connect \$56 $or$libresoc.v:171360$11646_Y - connect \$58 $or$libresoc.v:171361$11647_Y - connect \$60 $and$libresoc.v:171362$11648_Y - connect \$63 $or$libresoc.v:171363$11649_Y - connect \$62 $not$libresoc.v:171364$11650_Y - connect \$66 $and$libresoc.v:171365$11651_Y - connect \$68 $or$libresoc.v:171366$11652_Y - connect \$6 $and$libresoc.v:171367$11653_Y - connect \$70 $and$libresoc.v:171368$11654_Y - connect \$72 $not$libresoc.v:171369$11655_Y - connect \$74 $or$libresoc.v:171370$11656_Y - connect \$77 $not$libresoc.v:171371$11657_Y - connect \$79 $and$libresoc.v:171372$11658_Y - connect \$76 $reduce_or$libresoc.v:171373$11659_Y + assign $1\me$13[6:0]$12072 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12072 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12071 + end + connect \$9 $pos$libresoc.v:174761$12020_Y + connect \$11 $not$libresoc.v:174762$12021_Y + connect \$14 $and$libresoc.v:174763$12022_Y + connect \$16 $not$libresoc.v:174764$12023_Y + connect \$18 $and$libresoc.v:174765$12024_Y + connect \$20 $not$libresoc.v:174766$12025_Y + connect \$22 $le$libresoc.v:174767$12026_Y + connect \$25 $sub$libresoc.v:174768$12027_Y + connect \$27 $le$libresoc.v:174769$12028_Y + connect \$2 $neg$libresoc.v:174770$12029_Y + connect \$30 $sub$libresoc.v:174771$12030_Y + connect \$32 $not$libresoc.v:174772$12031_Y + connect \$34 $not$libresoc.v:174773$12032_Y + connect \$36 $and$libresoc.v:174774$12033_Y + connect \$38 $or$libresoc.v:174775$12034_Y + connect \$40 $and$libresoc.v:174776$12035_Y + connect \$42 $gt$libresoc.v:174777$12036_Y + connect \$44 $and$libresoc.v:174778$12037_Y + connect \$46 $and$libresoc.v:174779$12038_Y + connect \$48 $and$libresoc.v:174780$12039_Y + connect \$4 $not$libresoc.v:174781$12040_Y + connect \$51 $and$libresoc.v:174782$12041_Y + connect \$50 $not$libresoc.v:174783$12042_Y + connect \$54 $and$libresoc.v:174784$12043_Y + connect \$56 $or$libresoc.v:174785$12044_Y + connect \$58 $or$libresoc.v:174786$12045_Y + connect \$60 $and$libresoc.v:174787$12046_Y + connect \$63 $or$libresoc.v:174788$12047_Y + connect \$62 $not$libresoc.v:174789$12048_Y + connect \$66 $and$libresoc.v:174790$12049_Y + connect \$68 $or$libresoc.v:174791$12050_Y + connect \$6 $and$libresoc.v:174792$12051_Y + connect \$70 $and$libresoc.v:174793$12052_Y + connect \$72 $not$libresoc.v:174794$12053_Y + connect \$74 $or$libresoc.v:174795$12054_Y + connect \$77 $not$libresoc.v:174796$12055_Y + connect \$79 $and$libresoc.v:174797$12056_Y + connect \$76 $reduce_or$libresoc.v:174798$12057_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -356956,15 +364886,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:171541.1-171555.10" +attribute \src "libresoc.v:174966.1-174980.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:171553.17-171553.32" - wire width 128 $shr$libresoc.v:171553$11677_Y - attribute \src "libresoc.v:171552.17-171552.100" - wire width 8 $sub$libresoc.v:171552$11676_Y + attribute \src "libresoc.v:174978.17-174978.32" + wire width 128 $shr$libresoc.v:174978$12075_Y + attribute \src "libresoc.v:174977.17-174977.100" + wire width 8 $sub$libresoc.v:174977$12074_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -356975,8 +364905,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:171553.17-171553.32" - cell $shr $shr$libresoc.v:171553$11677 + attribute \src "libresoc.v:174978.17-174978.32" + cell $shr $shr$libresoc.v:174978$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -356984,10 +364914,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:171553$11677_Y + connect \Y $shr$libresoc.v:174978$12075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:171552$11676 + cell $sub $sub$libresoc.v:174977$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356995,43 +364925,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:171552$11676_Y + connect \Y $sub$libresoc.v:174977$12074_Y end - connect \$2 $sub$libresoc.v:171552$11676_Y - connect \$1 $shr$libresoc.v:171553$11677_Y [63:0] + connect \$2 $sub$libresoc.v:174977$12074_Y + connect \$1 $shr$libresoc.v:174978$12075_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:171559.1-171617.10" +attribute \src "libresoc.v:174984.1-175042.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:171560.7-171560.20" + attribute \src "libresoc.v:174985.7-174985.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171605.3-171613.6" - wire $0\q_int$next[0:0]$11688 - attribute \src "libresoc.v:171603.3-171604.27" + attribute \src "libresoc.v:175030.3-175038.6" + wire $0\q_int$next[0:0]$12086 + attribute \src "libresoc.v:175028.3-175029.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171605.3-171613.6" - wire $1\q_int$next[0:0]$11689 - attribute \src "libresoc.v:171582.7-171582.19" + attribute \src "libresoc.v:175030.3-175038.6" + wire $1\q_int$next[0:0]$12087 + attribute \src "libresoc.v:175007.7-175007.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171595.17-171595.96" - wire $and$libresoc.v:171595$11678_Y - attribute \src "libresoc.v:171600.17-171600.96" - wire $and$libresoc.v:171600$11683_Y - attribute \src "libresoc.v:171597.18-171597.93" - wire $not$libresoc.v:171597$11680_Y - attribute \src "libresoc.v:171599.17-171599.92" - wire $not$libresoc.v:171599$11682_Y - attribute \src "libresoc.v:171602.17-171602.92" - wire $not$libresoc.v:171602$11685_Y - attribute \src "libresoc.v:171596.18-171596.98" - wire $or$libresoc.v:171596$11679_Y - attribute \src "libresoc.v:171598.18-171598.99" - wire $or$libresoc.v:171598$11681_Y - attribute \src "libresoc.v:171601.17-171601.97" - wire $or$libresoc.v:171601$11684_Y + attribute \src "libresoc.v:175020.17-175020.96" + wire $and$libresoc.v:175020$12076_Y + attribute \src "libresoc.v:175025.17-175025.96" + wire $and$libresoc.v:175025$12081_Y + attribute \src "libresoc.v:175022.18-175022.93" + wire $not$libresoc.v:175022$12078_Y + attribute \src "libresoc.v:175024.17-175024.92" + wire $not$libresoc.v:175024$12080_Y + attribute \src "libresoc.v:175027.17-175027.92" + wire $not$libresoc.v:175027$12083_Y + attribute \src "libresoc.v:175021.18-175021.98" + wire $or$libresoc.v:175021$12077_Y + attribute \src "libresoc.v:175023.18-175023.99" + wire $or$libresoc.v:175023$12079_Y + attribute \src "libresoc.v:175026.17-175026.97" + wire $or$libresoc.v:175026$12082_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -357048,11 +364978,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171560.7-171560.15" + attribute \src "libresoc.v:174985.7-174985.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -357069,7 +364999,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171595$11678 + cell $and $and$libresoc.v:175020$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357077,10 +365007,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171595$11678_Y + connect \Y $and$libresoc.v:175020$12076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171600$11683 + cell $and $and$libresoc.v:175025$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357088,34 +365018,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171600$11683_Y + connect \Y $and$libresoc.v:175025$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171597$11680 + cell $not $not$libresoc.v:175022$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171597$11680_Y + connect \Y $not$libresoc.v:175022$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171599$11682 + cell $not $not$libresoc.v:175024$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171599$11682_Y + connect \Y $not$libresoc.v:175024$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171602$11685 + cell $not $not$libresoc.v:175027$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171602$11685_Y + connect \Y $not$libresoc.v:175027$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171596$11679 + cell $or $or$libresoc.v:175021$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357123,10 +365053,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171596$11679_Y + connect \Y $or$libresoc.v:175021$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171598$11681 + cell $or $or$libresoc.v:175023$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357134,10 +365064,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171598$11681_Y + connect \Y $or$libresoc.v:175023$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171601$11684 + cell $or $or$libresoc.v:175026$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357145,39 +365075,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171601$11684_Y + connect \Y $or$libresoc.v:175026$12082_Y end - attribute \src "libresoc.v:171560.7-171560.20" - process $proc$libresoc.v:171560$11690 + attribute \src "libresoc.v:174985.7-174985.20" + process $proc$libresoc.v:174985$12088 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171582.7-171582.19" - process $proc$libresoc.v:171582$11691 + attribute \src "libresoc.v:175007.7-175007.19" + process $proc$libresoc.v:175007$12089 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171603.3-171604.27" - process $proc$libresoc.v:171603$11686 + attribute \src "libresoc.v:175028.3-175029.27" + process $proc$libresoc.v:175028$12084 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171605.3-171613.6" - process $proc$libresoc.v:171605$11687 + attribute \src "libresoc.v:175030.3-175038.6" + process $proc$libresoc.v:175030$12085 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11688 $1\q_int$next[0:0]$11689 - attribute \src "libresoc.v:171606.5-171606.29" + assign $0\q_int$next[0:0]$12086 $1\q_int$next[0:0]$12087 + attribute \src "libresoc.v:175031.5-175031.29" switch \initial - attribute \src "libresoc.v:171606.9-171606.17" + attribute \src "libresoc.v:175031.9-175031.17" case 1'1 case end @@ -357186,56 +365116,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11689 1'0 + assign $1\q_int$next[0:0]$12087 1'0 case - assign $1\q_int$next[0:0]$11689 \$5 + assign $1\q_int$next[0:0]$12087 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11688 + update \q_int$next $0\q_int$next[0:0]$12086 end - connect \$9 $and$libresoc.v:171595$11678_Y - connect \$11 $or$libresoc.v:171596$11679_Y - connect \$13 $not$libresoc.v:171597$11680_Y - connect \$15 $or$libresoc.v:171598$11681_Y - connect \$1 $not$libresoc.v:171599$11682_Y - connect \$3 $and$libresoc.v:171600$11683_Y - connect \$5 $or$libresoc.v:171601$11684_Y - connect \$7 $not$libresoc.v:171602$11685_Y + connect \$9 $and$libresoc.v:175020$12076_Y + connect \$11 $or$libresoc.v:175021$12077_Y + connect \$13 $not$libresoc.v:175022$12078_Y + connect \$15 $or$libresoc.v:175023$12079_Y + connect \$1 $not$libresoc.v:175024$12080_Y + connect \$3 $and$libresoc.v:175025$12081_Y + connect \$5 $or$libresoc.v:175026$12082_Y + connect \$7 $not$libresoc.v:175027$12083_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171621.1-171679.10" +attribute \src "libresoc.v:175046.1-175104.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" -module \rst_l$101 - attribute \src "libresoc.v:171622.7-171622.20" +module \rst_l$104 + attribute \src "libresoc.v:175047.7-175047.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171667.3-171675.6" - wire $0\q_int$next[0:0]$11702 - attribute \src "libresoc.v:171665.3-171666.27" + attribute \src "libresoc.v:175092.3-175100.6" + wire $0\q_int$next[0:0]$12100 + attribute \src "libresoc.v:175090.3-175091.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171667.3-171675.6" - wire $1\q_int$next[0:0]$11703 - attribute \src "libresoc.v:171644.7-171644.19" + attribute \src "libresoc.v:175092.3-175100.6" + wire $1\q_int$next[0:0]$12101 + attribute \src "libresoc.v:175069.7-175069.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171657.17-171657.96" - wire $and$libresoc.v:171657$11692_Y - attribute \src "libresoc.v:171662.17-171662.96" - wire $and$libresoc.v:171662$11697_Y - attribute \src "libresoc.v:171659.18-171659.93" - wire $not$libresoc.v:171659$11694_Y - attribute \src "libresoc.v:171661.17-171661.92" - wire $not$libresoc.v:171661$11696_Y - attribute \src "libresoc.v:171664.17-171664.92" - wire $not$libresoc.v:171664$11699_Y - attribute \src "libresoc.v:171658.18-171658.98" - wire $or$libresoc.v:171658$11693_Y - attribute \src "libresoc.v:171660.18-171660.99" - wire $or$libresoc.v:171660$11695_Y - attribute \src "libresoc.v:171663.17-171663.97" - wire $or$libresoc.v:171663$11698_Y + attribute \src "libresoc.v:175082.17-175082.96" + wire $and$libresoc.v:175082$12090_Y + attribute \src "libresoc.v:175087.17-175087.96" + wire $and$libresoc.v:175087$12095_Y + attribute \src "libresoc.v:175084.18-175084.93" + wire $not$libresoc.v:175084$12092_Y + attribute \src "libresoc.v:175086.17-175086.92" + wire $not$libresoc.v:175086$12094_Y + attribute \src "libresoc.v:175089.17-175089.92" + wire $not$libresoc.v:175089$12097_Y + attribute \src "libresoc.v:175083.18-175083.98" + wire $or$libresoc.v:175083$12091_Y + attribute \src "libresoc.v:175085.18-175085.99" + wire $or$libresoc.v:175085$12093_Y + attribute \src "libresoc.v:175088.17-175088.97" + wire $or$libresoc.v:175088$12096_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -357252,11 +365182,11 @@ module \rst_l$101 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171622.7-171622.15" + attribute \src "libresoc.v:175047.7-175047.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -357273,7 +365203,7 @@ module \rst_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171657$11692 + cell $and $and$libresoc.v:175082$12090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357281,10 +365211,10 @@ module \rst_l$101 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171657$11692_Y + connect \Y $and$libresoc.v:175082$12090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171662$11697 + cell $and $and$libresoc.v:175087$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357292,34 +365222,34 @@ module \rst_l$101 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171662$11697_Y + connect \Y $and$libresoc.v:175087$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171659$11694 + cell $not $not$libresoc.v:175084$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171659$11694_Y + connect \Y $not$libresoc.v:175084$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171661$11696 + cell $not $not$libresoc.v:175086$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171661$11696_Y + connect \Y $not$libresoc.v:175086$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171664$11699 + cell $not $not$libresoc.v:175089$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171664$11699_Y + connect \Y $not$libresoc.v:175089$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171658$11693 + cell $or $or$libresoc.v:175083$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357327,10 +365257,10 @@ module \rst_l$101 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171658$11693_Y + connect \Y $or$libresoc.v:175083$12091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171660$11695 + cell $or $or$libresoc.v:175085$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357338,10 +365268,10 @@ module \rst_l$101 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171660$11695_Y + connect \Y $or$libresoc.v:175085$12093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171663$11698 + cell $or $or$libresoc.v:175088$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357349,39 +365279,39 @@ module \rst_l$101 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171663$11698_Y + connect \Y $or$libresoc.v:175088$12096_Y end - attribute \src "libresoc.v:171622.7-171622.20" - process $proc$libresoc.v:171622$11704 + attribute \src "libresoc.v:175047.7-175047.20" + process $proc$libresoc.v:175047$12102 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171644.7-171644.19" - process $proc$libresoc.v:171644$11705 + attribute \src "libresoc.v:175069.7-175069.19" + process $proc$libresoc.v:175069$12103 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171665.3-171666.27" - process $proc$libresoc.v:171665$11700 + attribute \src "libresoc.v:175090.3-175091.27" + process $proc$libresoc.v:175090$12098 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171667.3-171675.6" - process $proc$libresoc.v:171667$11701 + attribute \src "libresoc.v:175092.3-175100.6" + process $proc$libresoc.v:175092$12099 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11702 $1\q_int$next[0:0]$11703 - attribute \src "libresoc.v:171668.5-171668.29" + assign $0\q_int$next[0:0]$12100 $1\q_int$next[0:0]$12101 + attribute \src "libresoc.v:175093.5-175093.29" switch \initial - attribute \src "libresoc.v:171668.9-171668.17" + attribute \src "libresoc.v:175093.9-175093.17" case 1'1 case end @@ -357390,56 +365320,56 @@ module \rst_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11703 1'0 + assign $1\q_int$next[0:0]$12101 1'0 case - assign $1\q_int$next[0:0]$11703 \$5 + assign $1\q_int$next[0:0]$12101 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11702 + update \q_int$next $0\q_int$next[0:0]$12100 end - connect \$9 $and$libresoc.v:171657$11692_Y - connect \$11 $or$libresoc.v:171658$11693_Y - connect \$13 $not$libresoc.v:171659$11694_Y - connect \$15 $or$libresoc.v:171660$11695_Y - connect \$1 $not$libresoc.v:171661$11696_Y - connect \$3 $and$libresoc.v:171662$11697_Y - connect \$5 $or$libresoc.v:171663$11698_Y - connect \$7 $not$libresoc.v:171664$11699_Y + connect \$9 $and$libresoc.v:175082$12090_Y + connect \$11 $or$libresoc.v:175083$12091_Y + connect \$13 $not$libresoc.v:175084$12092_Y + connect \$15 $or$libresoc.v:175085$12093_Y + connect \$1 $not$libresoc.v:175086$12094_Y + connect \$3 $and$libresoc.v:175087$12095_Y + connect \$5 $or$libresoc.v:175088$12096_Y + connect \$7 $not$libresoc.v:175089$12097_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171683.1-171741.10" +attribute \src "libresoc.v:175108.1-175166.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" -module \rst_l$119 - attribute \src "libresoc.v:171684.7-171684.20" +module \rst_l$122 + attribute \src "libresoc.v:175109.7-175109.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171729.3-171737.6" - wire $0\q_int$next[0:0]$11716 - attribute \src "libresoc.v:171727.3-171728.27" + attribute \src "libresoc.v:175154.3-175162.6" + wire $0\q_int$next[0:0]$12114 + attribute \src "libresoc.v:175152.3-175153.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171729.3-171737.6" - wire $1\q_int$next[0:0]$11717 - attribute \src "libresoc.v:171706.7-171706.19" + attribute \src "libresoc.v:175154.3-175162.6" + wire $1\q_int$next[0:0]$12115 + attribute \src "libresoc.v:175131.7-175131.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171719.17-171719.96" - wire $and$libresoc.v:171719$11706_Y - attribute \src "libresoc.v:171724.17-171724.96" - wire $and$libresoc.v:171724$11711_Y - attribute \src "libresoc.v:171721.18-171721.93" - wire $not$libresoc.v:171721$11708_Y - attribute \src "libresoc.v:171723.17-171723.92" - wire $not$libresoc.v:171723$11710_Y - attribute \src "libresoc.v:171726.17-171726.92" - wire $not$libresoc.v:171726$11713_Y - attribute \src "libresoc.v:171720.18-171720.98" - wire $or$libresoc.v:171720$11707_Y - attribute \src "libresoc.v:171722.18-171722.99" - wire $or$libresoc.v:171722$11709_Y - attribute \src "libresoc.v:171725.17-171725.97" - wire $or$libresoc.v:171725$11712_Y + attribute \src "libresoc.v:175144.17-175144.96" + wire $and$libresoc.v:175144$12104_Y + attribute \src "libresoc.v:175149.17-175149.96" + wire $and$libresoc.v:175149$12109_Y + attribute \src "libresoc.v:175146.18-175146.93" + wire $not$libresoc.v:175146$12106_Y + attribute \src "libresoc.v:175148.17-175148.92" + wire $not$libresoc.v:175148$12108_Y + attribute \src "libresoc.v:175151.17-175151.92" + wire $not$libresoc.v:175151$12111_Y + attribute \src "libresoc.v:175145.18-175145.98" + wire $or$libresoc.v:175145$12105_Y + attribute \src "libresoc.v:175147.18-175147.99" + wire $or$libresoc.v:175147$12107_Y + attribute \src "libresoc.v:175150.17-175150.97" + wire $or$libresoc.v:175150$12110_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -357456,11 +365386,11 @@ module \rst_l$119 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171684.7-171684.15" + attribute \src "libresoc.v:175109.7-175109.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -357477,7 +365407,7 @@ module \rst_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171719$11706 + cell $and $and$libresoc.v:175144$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357485,10 +365415,10 @@ module \rst_l$119 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171719$11706_Y + connect \Y $and$libresoc.v:175144$12104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171724$11711 + cell $and $and$libresoc.v:175149$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357496,34 +365426,34 @@ module \rst_l$119 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171724$11711_Y + connect \Y $and$libresoc.v:175149$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171721$11708 + cell $not $not$libresoc.v:175146$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171721$11708_Y + connect \Y $not$libresoc.v:175146$12106_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171723$11710 + cell $not $not$libresoc.v:175148$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171723$11710_Y + connect \Y $not$libresoc.v:175148$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171726$11713 + cell $not $not$libresoc.v:175151$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171726$11713_Y + connect \Y $not$libresoc.v:175151$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171720$11707 + cell $or $or$libresoc.v:175145$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357531,10 +365461,10 @@ module \rst_l$119 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171720$11707_Y + connect \Y $or$libresoc.v:175145$12105_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171722$11709 + cell $or $or$libresoc.v:175147$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357542,10 +365472,10 @@ module \rst_l$119 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171722$11709_Y + connect \Y $or$libresoc.v:175147$12107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171725$11712 + cell $or $or$libresoc.v:175150$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357553,39 +365483,39 @@ module \rst_l$119 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171725$11712_Y + connect \Y $or$libresoc.v:175150$12110_Y end - attribute \src "libresoc.v:171684.7-171684.20" - process $proc$libresoc.v:171684$11718 + attribute \src "libresoc.v:175109.7-175109.20" + process $proc$libresoc.v:175109$12116 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171706.7-171706.19" - process $proc$libresoc.v:171706$11719 + attribute \src "libresoc.v:175131.7-175131.19" + process $proc$libresoc.v:175131$12117 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171727.3-171728.27" - process $proc$libresoc.v:171727$11714 + attribute \src "libresoc.v:175152.3-175153.27" + process $proc$libresoc.v:175152$12112 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171729.3-171737.6" - process $proc$libresoc.v:171729$11715 + attribute \src "libresoc.v:175154.3-175162.6" + process $proc$libresoc.v:175154$12113 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11716 $1\q_int$next[0:0]$11717 - attribute \src "libresoc.v:171730.5-171730.29" + assign $0\q_int$next[0:0]$12114 $1\q_int$next[0:0]$12115 + attribute \src "libresoc.v:175155.5-175155.29" switch \initial - attribute \src "libresoc.v:171730.9-171730.17" + attribute \src "libresoc.v:175155.9-175155.17" case 1'1 case end @@ -357594,56 +365524,56 @@ module \rst_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11717 1'0 + assign $1\q_int$next[0:0]$12115 1'0 case - assign $1\q_int$next[0:0]$11717 \$5 + assign $1\q_int$next[0:0]$12115 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11716 + update \q_int$next $0\q_int$next[0:0]$12114 end - connect \$9 $and$libresoc.v:171719$11706_Y - connect \$11 $or$libresoc.v:171720$11707_Y - connect \$13 $not$libresoc.v:171721$11708_Y - connect \$15 $or$libresoc.v:171722$11709_Y - connect \$1 $not$libresoc.v:171723$11710_Y - connect \$3 $and$libresoc.v:171724$11711_Y - connect \$5 $or$libresoc.v:171725$11712_Y - connect \$7 $not$libresoc.v:171726$11713_Y + connect \$9 $and$libresoc.v:175144$12104_Y + connect \$11 $or$libresoc.v:175145$12105_Y + connect \$13 $not$libresoc.v:175146$12106_Y + connect \$15 $or$libresoc.v:175147$12107_Y + connect \$1 $not$libresoc.v:175148$12108_Y + connect \$3 $and$libresoc.v:175149$12109_Y + connect \$5 $or$libresoc.v:175150$12110_Y + connect \$7 $not$libresoc.v:175151$12111_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171745.1-171803.10" +attribute \src "libresoc.v:175170.1-175228.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" -module \rst_l$126 - attribute \src "libresoc.v:171746.7-171746.20" +module \rst_l$129 + attribute \src "libresoc.v:175171.7-175171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171791.3-171799.6" - wire $0\q_int$next[0:0]$11730 - attribute \src "libresoc.v:171789.3-171790.27" + attribute \src "libresoc.v:175216.3-175224.6" + wire $0\q_int$next[0:0]$12128 + attribute \src "libresoc.v:175214.3-175215.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171791.3-171799.6" - wire $1\q_int$next[0:0]$11731 - attribute \src "libresoc.v:171768.7-171768.19" + attribute \src "libresoc.v:175216.3-175224.6" + wire $1\q_int$next[0:0]$12129 + attribute \src "libresoc.v:175193.7-175193.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171781.17-171781.96" - wire $and$libresoc.v:171781$11720_Y - attribute \src "libresoc.v:171786.17-171786.96" - wire $and$libresoc.v:171786$11725_Y - attribute \src "libresoc.v:171783.18-171783.93" - wire $not$libresoc.v:171783$11722_Y - attribute \src "libresoc.v:171785.17-171785.92" - wire $not$libresoc.v:171785$11724_Y - attribute \src "libresoc.v:171788.17-171788.92" - wire $not$libresoc.v:171788$11727_Y - attribute \src "libresoc.v:171782.18-171782.98" - wire $or$libresoc.v:171782$11721_Y - attribute \src "libresoc.v:171784.18-171784.99" - wire $or$libresoc.v:171784$11723_Y - attribute \src "libresoc.v:171787.17-171787.97" - wire $or$libresoc.v:171787$11726_Y + attribute \src "libresoc.v:175206.17-175206.96" + wire $and$libresoc.v:175206$12118_Y + attribute \src "libresoc.v:175211.17-175211.96" + wire $and$libresoc.v:175211$12123_Y + attribute \src "libresoc.v:175208.18-175208.93" + wire $not$libresoc.v:175208$12120_Y + attribute \src "libresoc.v:175210.17-175210.92" + wire $not$libresoc.v:175210$12122_Y + attribute \src "libresoc.v:175213.17-175213.92" + wire $not$libresoc.v:175213$12125_Y + attribute \src "libresoc.v:175207.18-175207.98" + wire $or$libresoc.v:175207$12119_Y + attribute \src "libresoc.v:175209.18-175209.99" + wire $or$libresoc.v:175209$12121_Y + attribute \src "libresoc.v:175212.17-175212.97" + wire $or$libresoc.v:175212$12124_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -357660,11 +365590,11 @@ module \rst_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171746.7-171746.15" + attribute \src "libresoc.v:175171.7-175171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -357681,7 +365611,7 @@ module \rst_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171781$11720 + cell $and $and$libresoc.v:175206$12118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357689,10 +365619,10 @@ module \rst_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171781$11720_Y + connect \Y $and$libresoc.v:175206$12118_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171786$11725 + cell $and $and$libresoc.v:175211$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357700,34 +365630,34 @@ module \rst_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171786$11725_Y + connect \Y $and$libresoc.v:175211$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171783$11722 + cell $not $not$libresoc.v:175208$12120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171783$11722_Y + connect \Y $not$libresoc.v:175208$12120_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171785$11724 + cell $not $not$libresoc.v:175210$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171785$11724_Y + connect \Y $not$libresoc.v:175210$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171788$11727 + cell $not $not$libresoc.v:175213$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171788$11727_Y + connect \Y $not$libresoc.v:175213$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171782$11721 + cell $or $or$libresoc.v:175207$12119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357735,10 +365665,10 @@ module \rst_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171782$11721_Y + connect \Y $or$libresoc.v:175207$12119_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171784$11723 + cell $or $or$libresoc.v:175209$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357746,10 +365676,10 @@ module \rst_l$126 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171784$11723_Y + connect \Y $or$libresoc.v:175209$12121_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171787$11726 + cell $or $or$libresoc.v:175212$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357757,39 +365687,39 @@ module \rst_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171787$11726_Y + connect \Y $or$libresoc.v:175212$12124_Y end - attribute \src "libresoc.v:171746.7-171746.20" - process $proc$libresoc.v:171746$11732 + attribute \src "libresoc.v:175171.7-175171.20" + process $proc$libresoc.v:175171$12130 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171768.7-171768.19" - process $proc$libresoc.v:171768$11733 + attribute \src "libresoc.v:175193.7-175193.19" + process $proc$libresoc.v:175193$12131 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171789.3-171790.27" - process $proc$libresoc.v:171789$11728 + attribute \src "libresoc.v:175214.3-175215.27" + process $proc$libresoc.v:175214$12126 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171791.3-171799.6" - process $proc$libresoc.v:171791$11729 + attribute \src "libresoc.v:175216.3-175224.6" + process $proc$libresoc.v:175216$12127 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11730 $1\q_int$next[0:0]$11731 - attribute \src "libresoc.v:171792.5-171792.29" + assign $0\q_int$next[0:0]$12128 $1\q_int$next[0:0]$12129 + attribute \src "libresoc.v:175217.5-175217.29" switch \initial - attribute \src "libresoc.v:171792.9-171792.17" + attribute \src "libresoc.v:175217.9-175217.17" case 1'1 case end @@ -357798,56 +365728,56 @@ module \rst_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11731 1'0 + assign $1\q_int$next[0:0]$12129 1'0 case - assign $1\q_int$next[0:0]$11731 \$5 + assign $1\q_int$next[0:0]$12129 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11730 + update \q_int$next $0\q_int$next[0:0]$12128 end - connect \$9 $and$libresoc.v:171781$11720_Y - connect \$11 $or$libresoc.v:171782$11721_Y - connect \$13 $not$libresoc.v:171783$11722_Y - connect \$15 $or$libresoc.v:171784$11723_Y - connect \$1 $not$libresoc.v:171785$11724_Y - connect \$3 $and$libresoc.v:171786$11725_Y - connect \$5 $or$libresoc.v:171787$11726_Y - connect \$7 $not$libresoc.v:171788$11727_Y + connect \$9 $and$libresoc.v:175206$12118_Y + connect \$11 $or$libresoc.v:175207$12119_Y + connect \$13 $not$libresoc.v:175208$12120_Y + connect \$15 $or$libresoc.v:175209$12121_Y + connect \$1 $not$libresoc.v:175210$12122_Y + connect \$3 $and$libresoc.v:175211$12123_Y + connect \$5 $or$libresoc.v:175212$12124_Y + connect \$7 $not$libresoc.v:175213$12125_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171807.1-171865.10" +attribute \src "libresoc.v:175232.1-175290.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:171808.7-171808.20" + attribute \src "libresoc.v:175233.7-175233.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171853.3-171861.6" - wire $0\q_int$next[0:0]$11744 - attribute \src "libresoc.v:171851.3-171852.27" + attribute \src "libresoc.v:175278.3-175286.6" + wire $0\q_int$next[0:0]$12142 + attribute \src "libresoc.v:175276.3-175277.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171853.3-171861.6" - wire $1\q_int$next[0:0]$11745 - attribute \src "libresoc.v:171830.7-171830.19" + attribute \src "libresoc.v:175278.3-175286.6" + wire $1\q_int$next[0:0]$12143 + attribute \src "libresoc.v:175255.7-175255.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171843.17-171843.96" - wire $and$libresoc.v:171843$11734_Y - attribute \src "libresoc.v:171848.17-171848.96" - wire $and$libresoc.v:171848$11739_Y - attribute \src "libresoc.v:171845.18-171845.93" - wire $not$libresoc.v:171845$11736_Y - attribute \src "libresoc.v:171847.17-171847.92" - wire $not$libresoc.v:171847$11738_Y - attribute \src "libresoc.v:171850.17-171850.92" - wire $not$libresoc.v:171850$11741_Y - attribute \src "libresoc.v:171844.18-171844.98" - wire $or$libresoc.v:171844$11735_Y - attribute \src "libresoc.v:171846.18-171846.99" - wire $or$libresoc.v:171846$11737_Y - attribute \src "libresoc.v:171849.17-171849.97" - wire $or$libresoc.v:171849$11740_Y + attribute \src "libresoc.v:175268.17-175268.96" + wire $and$libresoc.v:175268$12132_Y + attribute \src "libresoc.v:175273.17-175273.96" + wire $and$libresoc.v:175273$12137_Y + attribute \src "libresoc.v:175270.18-175270.93" + wire $not$libresoc.v:175270$12134_Y + attribute \src "libresoc.v:175272.17-175272.92" + wire $not$libresoc.v:175272$12136_Y + attribute \src "libresoc.v:175275.17-175275.92" + wire $not$libresoc.v:175275$12139_Y + attribute \src "libresoc.v:175269.18-175269.98" + wire $or$libresoc.v:175269$12133_Y + attribute \src "libresoc.v:175271.18-175271.99" + wire $or$libresoc.v:175271$12135_Y + attribute \src "libresoc.v:175274.17-175274.97" + wire $or$libresoc.v:175274$12138_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -357864,11 +365794,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171808.7-171808.15" + attribute \src "libresoc.v:175233.7-175233.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -357885,7 +365815,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171843$11734 + cell $and $and$libresoc.v:175268$12132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357893,10 +365823,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171843$11734_Y + connect \Y $and$libresoc.v:175268$12132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171848$11739 + cell $and $and$libresoc.v:175273$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357904,34 +365834,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171848$11739_Y + connect \Y $and$libresoc.v:175273$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171845$11736 + cell $not $not$libresoc.v:175270$12134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171845$11736_Y + connect \Y $not$libresoc.v:175270$12134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171847$11738 + cell $not $not$libresoc.v:175272$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171847$11738_Y + connect \Y $not$libresoc.v:175272$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171850$11741 + cell $not $not$libresoc.v:175275$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171850$11741_Y + connect \Y $not$libresoc.v:175275$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171844$11735 + cell $or $or$libresoc.v:175269$12133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357939,10 +365869,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171844$11735_Y + connect \Y $or$libresoc.v:175269$12133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171846$11737 + cell $or $or$libresoc.v:175271$12135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357950,10 +365880,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171846$11737_Y + connect \Y $or$libresoc.v:175271$12135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171849$11740 + cell $or $or$libresoc.v:175274$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357961,39 +365891,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171849$11740_Y + connect \Y $or$libresoc.v:175274$12138_Y end - attribute \src "libresoc.v:171808.7-171808.20" - process $proc$libresoc.v:171808$11746 + attribute \src "libresoc.v:175233.7-175233.20" + process $proc$libresoc.v:175233$12144 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171830.7-171830.19" - process $proc$libresoc.v:171830$11747 + attribute \src "libresoc.v:175255.7-175255.19" + process $proc$libresoc.v:175255$12145 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171851.3-171852.27" - process $proc$libresoc.v:171851$11742 + attribute \src "libresoc.v:175276.3-175277.27" + process $proc$libresoc.v:175276$12140 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171853.3-171861.6" - process $proc$libresoc.v:171853$11743 + attribute \src "libresoc.v:175278.3-175286.6" + process $proc$libresoc.v:175278$12141 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11744 $1\q_int$next[0:0]$11745 - attribute \src "libresoc.v:171854.5-171854.29" + assign $0\q_int$next[0:0]$12142 $1\q_int$next[0:0]$12143 + attribute \src "libresoc.v:175279.5-175279.29" switch \initial - attribute \src "libresoc.v:171854.9-171854.17" + attribute \src "libresoc.v:175279.9-175279.17" case 1'1 case end @@ -358002,56 +365932,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11745 1'0 + assign $1\q_int$next[0:0]$12143 1'0 case - assign $1\q_int$next[0:0]$11745 \$5 + assign $1\q_int$next[0:0]$12143 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11744 + update \q_int$next $0\q_int$next[0:0]$12142 end - connect \$9 $and$libresoc.v:171843$11734_Y - connect \$11 $or$libresoc.v:171844$11735_Y - connect \$13 $not$libresoc.v:171845$11736_Y - connect \$15 $or$libresoc.v:171846$11737_Y - connect \$1 $not$libresoc.v:171847$11738_Y - connect \$3 $and$libresoc.v:171848$11739_Y - connect \$5 $or$libresoc.v:171849$11740_Y - connect \$7 $not$libresoc.v:171850$11741_Y + connect \$9 $and$libresoc.v:175268$12132_Y + connect \$11 $or$libresoc.v:175269$12133_Y + connect \$13 $not$libresoc.v:175270$12134_Y + connect \$15 $or$libresoc.v:175271$12135_Y + connect \$1 $not$libresoc.v:175272$12136_Y + connect \$3 $and$libresoc.v:175273$12137_Y + connect \$5 $or$libresoc.v:175274$12138_Y + connect \$7 $not$libresoc.v:175275$12139_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171869.1-171927.10" +attribute \src "libresoc.v:175294.1-175352.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:171870.7-171870.20" + attribute \src "libresoc.v:175295.7-175295.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171915.3-171923.6" - wire $0\q_int$next[0:0]$11758 - attribute \src "libresoc.v:171913.3-171914.27" + attribute \src "libresoc.v:175340.3-175348.6" + wire $0\q_int$next[0:0]$12156 + attribute \src "libresoc.v:175338.3-175339.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171915.3-171923.6" - wire $1\q_int$next[0:0]$11759 - attribute \src "libresoc.v:171892.7-171892.19" + attribute \src "libresoc.v:175340.3-175348.6" + wire $1\q_int$next[0:0]$12157 + attribute \src "libresoc.v:175317.7-175317.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171905.17-171905.96" - wire $and$libresoc.v:171905$11748_Y - attribute \src "libresoc.v:171910.17-171910.96" - wire $and$libresoc.v:171910$11753_Y - attribute \src "libresoc.v:171907.18-171907.93" - wire $not$libresoc.v:171907$11750_Y - attribute \src "libresoc.v:171909.17-171909.92" - wire $not$libresoc.v:171909$11752_Y - attribute \src "libresoc.v:171912.17-171912.92" - wire $not$libresoc.v:171912$11755_Y - attribute \src "libresoc.v:171906.18-171906.98" - wire $or$libresoc.v:171906$11749_Y - attribute \src "libresoc.v:171908.18-171908.99" - wire $or$libresoc.v:171908$11751_Y - attribute \src "libresoc.v:171911.17-171911.97" - wire $or$libresoc.v:171911$11754_Y + attribute \src "libresoc.v:175330.17-175330.96" + wire $and$libresoc.v:175330$12146_Y + attribute \src "libresoc.v:175335.17-175335.96" + wire $and$libresoc.v:175335$12151_Y + attribute \src "libresoc.v:175332.18-175332.93" + wire $not$libresoc.v:175332$12148_Y + attribute \src "libresoc.v:175334.17-175334.92" + wire $not$libresoc.v:175334$12150_Y + attribute \src "libresoc.v:175337.17-175337.92" + wire $not$libresoc.v:175337$12153_Y + attribute \src "libresoc.v:175331.18-175331.98" + wire $or$libresoc.v:175331$12147_Y + attribute \src "libresoc.v:175333.18-175333.99" + wire $or$libresoc.v:175333$12149_Y + attribute \src "libresoc.v:175336.17-175336.97" + wire $or$libresoc.v:175336$12152_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -358068,11 +365998,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171870.7-171870.15" + attribute \src "libresoc.v:175295.7-175295.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -358089,7 +366019,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171905$11748 + cell $and $and$libresoc.v:175330$12146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358097,10 +366027,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171905$11748_Y + connect \Y $and$libresoc.v:175330$12146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171910$11753 + cell $and $and$libresoc.v:175335$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358108,34 +366038,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171910$11753_Y + connect \Y $and$libresoc.v:175335$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171907$11750 + cell $not $not$libresoc.v:175332$12148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171907$11750_Y + connect \Y $not$libresoc.v:175332$12148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171909$11752 + cell $not $not$libresoc.v:175334$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171909$11752_Y + connect \Y $not$libresoc.v:175334$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171912$11755 + cell $not $not$libresoc.v:175337$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171912$11755_Y + connect \Y $not$libresoc.v:175337$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171906$11749 + cell $or $or$libresoc.v:175331$12147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358143,10 +366073,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171906$11749_Y + connect \Y $or$libresoc.v:175331$12147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171908$11751 + cell $or $or$libresoc.v:175333$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358154,10 +366084,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171908$11751_Y + connect \Y $or$libresoc.v:175333$12149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171911$11754 + cell $or $or$libresoc.v:175336$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358165,39 +366095,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171911$11754_Y + connect \Y $or$libresoc.v:175336$12152_Y end - attribute \src "libresoc.v:171870.7-171870.20" - process $proc$libresoc.v:171870$11760 + attribute \src "libresoc.v:175295.7-175295.20" + process $proc$libresoc.v:175295$12158 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171892.7-171892.19" - process $proc$libresoc.v:171892$11761 + attribute \src "libresoc.v:175317.7-175317.19" + process $proc$libresoc.v:175317$12159 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171913.3-171914.27" - process $proc$libresoc.v:171913$11756 + attribute \src "libresoc.v:175338.3-175339.27" + process $proc$libresoc.v:175338$12154 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171915.3-171923.6" - process $proc$libresoc.v:171915$11757 + attribute \src "libresoc.v:175340.3-175348.6" + process $proc$libresoc.v:175340$12155 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11758 $1\q_int$next[0:0]$11759 - attribute \src "libresoc.v:171916.5-171916.29" + assign $0\q_int$next[0:0]$12156 $1\q_int$next[0:0]$12157 + attribute \src "libresoc.v:175341.5-175341.29" switch \initial - attribute \src "libresoc.v:171916.9-171916.17" + attribute \src "libresoc.v:175341.9-175341.17" case 1'1 case end @@ -358206,56 +366136,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11759 1'0 + assign $1\q_int$next[0:0]$12157 1'0 case - assign $1\q_int$next[0:0]$11759 \$5 + assign $1\q_int$next[0:0]$12157 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11758 + update \q_int$next $0\q_int$next[0:0]$12156 end - connect \$9 $and$libresoc.v:171905$11748_Y - connect \$11 $or$libresoc.v:171906$11749_Y - connect \$13 $not$libresoc.v:171907$11750_Y - connect \$15 $or$libresoc.v:171908$11751_Y - connect \$1 $not$libresoc.v:171909$11752_Y - connect \$3 $and$libresoc.v:171910$11753_Y - connect \$5 $or$libresoc.v:171911$11754_Y - connect \$7 $not$libresoc.v:171912$11755_Y + connect \$9 $and$libresoc.v:175330$12146_Y + connect \$11 $or$libresoc.v:175331$12147_Y + connect \$13 $not$libresoc.v:175332$12148_Y + connect \$15 $or$libresoc.v:175333$12149_Y + connect \$1 $not$libresoc.v:175334$12150_Y + connect \$3 $and$libresoc.v:175335$12151_Y + connect \$5 $or$libresoc.v:175336$12152_Y + connect \$7 $not$libresoc.v:175337$12153_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171931.1-171989.10" +attribute \src "libresoc.v:175356.1-175414.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" -module \rst_l$39 - attribute \src "libresoc.v:171932.7-171932.20" +module \rst_l$42 + attribute \src "libresoc.v:175357.7-175357.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171977.3-171985.6" - wire $0\q_int$next[0:0]$11772 - attribute \src "libresoc.v:171975.3-171976.27" + attribute \src "libresoc.v:175402.3-175410.6" + wire $0\q_int$next[0:0]$12170 + attribute \src "libresoc.v:175400.3-175401.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:171977.3-171985.6" - wire $1\q_int$next[0:0]$11773 - attribute \src "libresoc.v:171954.7-171954.19" + attribute \src "libresoc.v:175402.3-175410.6" + wire $1\q_int$next[0:0]$12171 + attribute \src "libresoc.v:175379.7-175379.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:171967.17-171967.96" - wire $and$libresoc.v:171967$11762_Y - attribute \src "libresoc.v:171972.17-171972.96" - wire $and$libresoc.v:171972$11767_Y - attribute \src "libresoc.v:171969.18-171969.93" - wire $not$libresoc.v:171969$11764_Y - attribute \src "libresoc.v:171971.17-171971.92" - wire $not$libresoc.v:171971$11766_Y - attribute \src "libresoc.v:171974.17-171974.92" - wire $not$libresoc.v:171974$11769_Y - attribute \src "libresoc.v:171968.18-171968.98" - wire $or$libresoc.v:171968$11763_Y - attribute \src "libresoc.v:171970.18-171970.99" - wire $or$libresoc.v:171970$11765_Y - attribute \src "libresoc.v:171973.17-171973.97" - wire $or$libresoc.v:171973$11768_Y + attribute \src "libresoc.v:175392.17-175392.96" + wire $and$libresoc.v:175392$12160_Y + attribute \src "libresoc.v:175397.17-175397.96" + wire $and$libresoc.v:175397$12165_Y + attribute \src "libresoc.v:175394.18-175394.93" + wire $not$libresoc.v:175394$12162_Y + attribute \src "libresoc.v:175396.17-175396.92" + wire $not$libresoc.v:175396$12164_Y + attribute \src "libresoc.v:175399.17-175399.92" + wire $not$libresoc.v:175399$12167_Y + attribute \src "libresoc.v:175393.18-175393.98" + wire $or$libresoc.v:175393$12161_Y + attribute \src "libresoc.v:175395.18-175395.99" + wire $or$libresoc.v:175395$12163_Y + attribute \src "libresoc.v:175398.17-175398.97" + wire $or$libresoc.v:175398$12166_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -358272,11 +366202,11 @@ module \rst_l$39 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171932.7-171932.15" + attribute \src "libresoc.v:175357.7-175357.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -358293,7 +366223,7 @@ module \rst_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:171967$11762 + cell $and $and$libresoc.v:175392$12160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358301,10 +366231,10 @@ module \rst_l$39 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:171967$11762_Y + connect \Y $and$libresoc.v:175392$12160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:171972$11767 + cell $and $and$libresoc.v:175397$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358312,34 +366242,34 @@ module \rst_l$39 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:171972$11767_Y + connect \Y $and$libresoc.v:175397$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:171969$11764 + cell $not $not$libresoc.v:175394$12162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:171969$11764_Y + connect \Y $not$libresoc.v:175394$12162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:171971$11766 + cell $not $not$libresoc.v:175396$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171971$11766_Y + connect \Y $not$libresoc.v:175396$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:171974$11769 + cell $not $not$libresoc.v:175399$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:171974$11769_Y + connect \Y $not$libresoc.v:175399$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:171968$11763 + cell $or $or$libresoc.v:175393$12161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358347,10 +366277,10 @@ module \rst_l$39 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:171968$11763_Y + connect \Y $or$libresoc.v:175393$12161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:171970$11765 + cell $or $or$libresoc.v:175395$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358358,10 +366288,10 @@ module \rst_l$39 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:171970$11765_Y + connect \Y $or$libresoc.v:175395$12163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:171973$11768 + cell $or $or$libresoc.v:175398$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358369,39 +366299,39 @@ module \rst_l$39 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:171973$11768_Y + connect \Y $or$libresoc.v:175398$12166_Y end - attribute \src "libresoc.v:171932.7-171932.20" - process $proc$libresoc.v:171932$11774 + attribute \src "libresoc.v:175357.7-175357.20" + process $proc$libresoc.v:175357$12172 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171954.7-171954.19" - process $proc$libresoc.v:171954$11775 + attribute \src "libresoc.v:175379.7-175379.19" + process $proc$libresoc.v:175379$12173 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:171975.3-171976.27" - process $proc$libresoc.v:171975$11770 + attribute \src "libresoc.v:175400.3-175401.27" + process $proc$libresoc.v:175400$12168 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:171977.3-171985.6" - process $proc$libresoc.v:171977$11771 + attribute \src "libresoc.v:175402.3-175410.6" + process $proc$libresoc.v:175402$12169 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11772 $1\q_int$next[0:0]$11773 - attribute \src "libresoc.v:171978.5-171978.29" + assign $0\q_int$next[0:0]$12170 $1\q_int$next[0:0]$12171 + attribute \src "libresoc.v:175403.5-175403.29" switch \initial - attribute \src "libresoc.v:171978.9-171978.17" + attribute \src "libresoc.v:175403.9-175403.17" case 1'1 case end @@ -358410,56 +366340,56 @@ module \rst_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11773 1'0 + assign $1\q_int$next[0:0]$12171 1'0 case - assign $1\q_int$next[0:0]$11773 \$5 + assign $1\q_int$next[0:0]$12171 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11772 + update \q_int$next $0\q_int$next[0:0]$12170 end - connect \$9 $and$libresoc.v:171967$11762_Y - connect \$11 $or$libresoc.v:171968$11763_Y - connect \$13 $not$libresoc.v:171969$11764_Y - connect \$15 $or$libresoc.v:171970$11765_Y - connect \$1 $not$libresoc.v:171971$11766_Y - connect \$3 $and$libresoc.v:171972$11767_Y - connect \$5 $or$libresoc.v:171973$11768_Y - connect \$7 $not$libresoc.v:171974$11769_Y + connect \$9 $and$libresoc.v:175392$12160_Y + connect \$11 $or$libresoc.v:175393$12161_Y + connect \$13 $not$libresoc.v:175394$12162_Y + connect \$15 $or$libresoc.v:175395$12163_Y + connect \$1 $not$libresoc.v:175396$12164_Y + connect \$3 $and$libresoc.v:175397$12165_Y + connect \$5 $or$libresoc.v:175398$12166_Y + connect \$7 $not$libresoc.v:175399$12167_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:171993.1-172051.10" +attribute \src "libresoc.v:175418.1-175476.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" -module \rst_l$55 - attribute \src "libresoc.v:171994.7-171994.20" +module \rst_l$58 + attribute \src "libresoc.v:175419.7-175419.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172039.3-172047.6" - wire $0\q_int$next[0:0]$11786 - attribute \src "libresoc.v:172037.3-172038.27" + attribute \src "libresoc.v:175464.3-175472.6" + wire $0\q_int$next[0:0]$12184 + attribute \src "libresoc.v:175462.3-175463.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:172039.3-172047.6" - wire $1\q_int$next[0:0]$11787 - attribute \src "libresoc.v:172016.7-172016.19" + attribute \src "libresoc.v:175464.3-175472.6" + wire $1\q_int$next[0:0]$12185 + attribute \src "libresoc.v:175441.7-175441.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:172029.17-172029.96" - wire $and$libresoc.v:172029$11776_Y - attribute \src "libresoc.v:172034.17-172034.96" - wire $and$libresoc.v:172034$11781_Y - attribute \src "libresoc.v:172031.18-172031.93" - wire $not$libresoc.v:172031$11778_Y - attribute \src "libresoc.v:172033.17-172033.92" - wire $not$libresoc.v:172033$11780_Y - attribute \src "libresoc.v:172036.17-172036.92" - wire $not$libresoc.v:172036$11783_Y - attribute \src "libresoc.v:172030.18-172030.98" - wire $or$libresoc.v:172030$11777_Y - attribute \src "libresoc.v:172032.18-172032.99" - wire $or$libresoc.v:172032$11779_Y - attribute \src "libresoc.v:172035.17-172035.97" - wire $or$libresoc.v:172035$11782_Y + attribute \src "libresoc.v:175454.17-175454.96" + wire $and$libresoc.v:175454$12174_Y + attribute \src "libresoc.v:175459.17-175459.96" + wire $and$libresoc.v:175459$12179_Y + attribute \src "libresoc.v:175456.18-175456.93" + wire $not$libresoc.v:175456$12176_Y + attribute \src "libresoc.v:175458.17-175458.92" + wire $not$libresoc.v:175458$12178_Y + attribute \src "libresoc.v:175461.17-175461.92" + wire $not$libresoc.v:175461$12181_Y + attribute \src "libresoc.v:175455.18-175455.98" + wire $or$libresoc.v:175455$12175_Y + attribute \src "libresoc.v:175457.18-175457.99" + wire $or$libresoc.v:175457$12177_Y + attribute \src "libresoc.v:175460.17-175460.97" + wire $or$libresoc.v:175460$12180_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -358476,11 +366406,11 @@ module \rst_l$55 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:171994.7-171994.15" + attribute \src "libresoc.v:175419.7-175419.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -358497,7 +366427,7 @@ module \rst_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172029$11776 + cell $and $and$libresoc.v:175454$12174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358505,10 +366435,10 @@ module \rst_l$55 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172029$11776_Y + connect \Y $and$libresoc.v:175454$12174_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172034$11781 + cell $and $and$libresoc.v:175459$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358516,34 +366446,34 @@ module \rst_l$55 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172034$11781_Y + connect \Y $and$libresoc.v:175459$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172031$11778 + cell $not $not$libresoc.v:175456$12176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:172031$11778_Y + connect \Y $not$libresoc.v:175456$12176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172033$11780 + cell $not $not$libresoc.v:175458$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172033$11780_Y + connect \Y $not$libresoc.v:175458$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172036$11783 + cell $not $not$libresoc.v:175461$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172036$11783_Y + connect \Y $not$libresoc.v:175461$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172030$11777 + cell $or $or$libresoc.v:175455$12175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358551,10 +366481,10 @@ module \rst_l$55 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:172030$11777_Y + connect \Y $or$libresoc.v:175455$12175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172032$11779 + cell $or $or$libresoc.v:175457$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358562,10 +366492,10 @@ module \rst_l$55 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:172032$11779_Y + connect \Y $or$libresoc.v:175457$12177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172035$11782 + cell $or $or$libresoc.v:175460$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358573,39 +366503,39 @@ module \rst_l$55 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:172035$11782_Y + connect \Y $or$libresoc.v:175460$12180_Y end - attribute \src "libresoc.v:171994.7-171994.20" - process $proc$libresoc.v:171994$11788 + attribute \src "libresoc.v:175419.7-175419.20" + process $proc$libresoc.v:175419$12186 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172016.7-172016.19" - process $proc$libresoc.v:172016$11789 + attribute \src "libresoc.v:175441.7-175441.19" + process $proc$libresoc.v:175441$12187 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:172037.3-172038.27" - process $proc$libresoc.v:172037$11784 + attribute \src "libresoc.v:175462.3-175463.27" + process $proc$libresoc.v:175462$12182 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:172039.3-172047.6" - process $proc$libresoc.v:172039$11785 + attribute \src "libresoc.v:175464.3-175472.6" + process $proc$libresoc.v:175464$12183 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11786 $1\q_int$next[0:0]$11787 - attribute \src "libresoc.v:172040.5-172040.29" + assign $0\q_int$next[0:0]$12184 $1\q_int$next[0:0]$12185 + attribute \src "libresoc.v:175465.5-175465.29" switch \initial - attribute \src "libresoc.v:172040.9-172040.17" + attribute \src "libresoc.v:175465.9-175465.17" case 1'1 case end @@ -358614,56 +366544,56 @@ module \rst_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11787 1'0 + assign $1\q_int$next[0:0]$12185 1'0 case - assign $1\q_int$next[0:0]$11787 \$5 + assign $1\q_int$next[0:0]$12185 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11786 + update \q_int$next $0\q_int$next[0:0]$12184 end - connect \$9 $and$libresoc.v:172029$11776_Y - connect \$11 $or$libresoc.v:172030$11777_Y - connect \$13 $not$libresoc.v:172031$11778_Y - connect \$15 $or$libresoc.v:172032$11779_Y - connect \$1 $not$libresoc.v:172033$11780_Y - connect \$3 $and$libresoc.v:172034$11781_Y - connect \$5 $or$libresoc.v:172035$11782_Y - connect \$7 $not$libresoc.v:172036$11783_Y + connect \$9 $and$libresoc.v:175454$12174_Y + connect \$11 $or$libresoc.v:175455$12175_Y + connect \$13 $not$libresoc.v:175456$12176_Y + connect \$15 $or$libresoc.v:175457$12177_Y + connect \$1 $not$libresoc.v:175458$12178_Y + connect \$3 $and$libresoc.v:175459$12179_Y + connect \$5 $or$libresoc.v:175460$12180_Y + connect \$7 $not$libresoc.v:175461$12181_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:172055.1-172113.10" +attribute \src "libresoc.v:175480.1-175538.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" -module \rst_l$67 - attribute \src "libresoc.v:172056.7-172056.20" +module \rst_l$70 + attribute \src "libresoc.v:175481.7-175481.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172101.3-172109.6" - wire $0\q_int$next[0:0]$11800 - attribute \src "libresoc.v:172099.3-172100.27" + attribute \src "libresoc.v:175526.3-175534.6" + wire $0\q_int$next[0:0]$12198 + attribute \src "libresoc.v:175524.3-175525.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:172101.3-172109.6" - wire $1\q_int$next[0:0]$11801 - attribute \src "libresoc.v:172078.7-172078.19" + attribute \src "libresoc.v:175526.3-175534.6" + wire $1\q_int$next[0:0]$12199 + attribute \src "libresoc.v:175503.7-175503.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:172091.17-172091.96" - wire $and$libresoc.v:172091$11790_Y - attribute \src "libresoc.v:172096.17-172096.96" - wire $and$libresoc.v:172096$11795_Y - attribute \src "libresoc.v:172093.18-172093.93" - wire $not$libresoc.v:172093$11792_Y - attribute \src "libresoc.v:172095.17-172095.92" - wire $not$libresoc.v:172095$11794_Y - attribute \src "libresoc.v:172098.17-172098.92" - wire $not$libresoc.v:172098$11797_Y - attribute \src "libresoc.v:172092.18-172092.98" - wire $or$libresoc.v:172092$11791_Y - attribute \src "libresoc.v:172094.18-172094.99" - wire $or$libresoc.v:172094$11793_Y - attribute \src "libresoc.v:172097.17-172097.97" - wire $or$libresoc.v:172097$11796_Y + attribute \src "libresoc.v:175516.17-175516.96" + wire $and$libresoc.v:175516$12188_Y + attribute \src "libresoc.v:175521.17-175521.96" + wire $and$libresoc.v:175521$12193_Y + attribute \src "libresoc.v:175518.18-175518.93" + wire $not$libresoc.v:175518$12190_Y + attribute \src "libresoc.v:175520.17-175520.92" + wire $not$libresoc.v:175520$12192_Y + attribute \src "libresoc.v:175523.17-175523.92" + wire $not$libresoc.v:175523$12195_Y + attribute \src "libresoc.v:175517.18-175517.98" + wire $or$libresoc.v:175517$12189_Y + attribute \src "libresoc.v:175519.18-175519.99" + wire $or$libresoc.v:175519$12191_Y + attribute \src "libresoc.v:175522.17-175522.97" + wire $or$libresoc.v:175522$12194_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -358680,11 +366610,11 @@ module \rst_l$67 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:172056.7-172056.15" + attribute \src "libresoc.v:175481.7-175481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -358701,7 +366631,7 @@ module \rst_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172091$11790 + cell $and $and$libresoc.v:175516$12188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358709,10 +366639,10 @@ module \rst_l$67 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172091$11790_Y + connect \Y $and$libresoc.v:175516$12188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172096$11795 + cell $and $and$libresoc.v:175521$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358720,34 +366650,34 @@ module \rst_l$67 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172096$11795_Y + connect \Y $and$libresoc.v:175521$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172093$11792 + cell $not $not$libresoc.v:175518$12190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:172093$11792_Y + connect \Y $not$libresoc.v:175518$12190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172095$11794 + cell $not $not$libresoc.v:175520$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172095$11794_Y + connect \Y $not$libresoc.v:175520$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172098$11797 + cell $not $not$libresoc.v:175523$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172098$11797_Y + connect \Y $not$libresoc.v:175523$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172092$11791 + cell $or $or$libresoc.v:175517$12189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358755,10 +366685,10 @@ module \rst_l$67 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:172092$11791_Y + connect \Y $or$libresoc.v:175517$12189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172094$11793 + cell $or $or$libresoc.v:175519$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358766,10 +366696,10 @@ module \rst_l$67 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:172094$11793_Y + connect \Y $or$libresoc.v:175519$12191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172097$11796 + cell $or $or$libresoc.v:175522$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358777,39 +366707,39 @@ module \rst_l$67 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:172097$11796_Y + connect \Y $or$libresoc.v:175522$12194_Y end - attribute \src "libresoc.v:172056.7-172056.20" - process $proc$libresoc.v:172056$11802 + attribute \src "libresoc.v:175481.7-175481.20" + process $proc$libresoc.v:175481$12200 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172078.7-172078.19" - process $proc$libresoc.v:172078$11803 + attribute \src "libresoc.v:175503.7-175503.19" + process $proc$libresoc.v:175503$12201 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:172099.3-172100.27" - process $proc$libresoc.v:172099$11798 + attribute \src "libresoc.v:175524.3-175525.27" + process $proc$libresoc.v:175524$12196 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:172101.3-172109.6" - process $proc$libresoc.v:172101$11799 + attribute \src "libresoc.v:175526.3-175534.6" + process $proc$libresoc.v:175526$12197 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11800 $1\q_int$next[0:0]$11801 - attribute \src "libresoc.v:172102.5-172102.29" + assign $0\q_int$next[0:0]$12198 $1\q_int$next[0:0]$12199 + attribute \src "libresoc.v:175527.5-175527.29" switch \initial - attribute \src "libresoc.v:172102.9-172102.17" + attribute \src "libresoc.v:175527.9-175527.17" case 1'1 case end @@ -358818,56 +366748,56 @@ module \rst_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11801 1'0 + assign $1\q_int$next[0:0]$12199 1'0 case - assign $1\q_int$next[0:0]$11801 \$5 + assign $1\q_int$next[0:0]$12199 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11800 + update \q_int$next $0\q_int$next[0:0]$12198 end - connect \$9 $and$libresoc.v:172091$11790_Y - connect \$11 $or$libresoc.v:172092$11791_Y - connect \$13 $not$libresoc.v:172093$11792_Y - connect \$15 $or$libresoc.v:172094$11793_Y - connect \$1 $not$libresoc.v:172095$11794_Y - connect \$3 $and$libresoc.v:172096$11795_Y - connect \$5 $or$libresoc.v:172097$11796_Y - connect \$7 $not$libresoc.v:172098$11797_Y + connect \$9 $and$libresoc.v:175516$12188_Y + connect \$11 $or$libresoc.v:175517$12189_Y + connect \$13 $not$libresoc.v:175518$12190_Y + connect \$15 $or$libresoc.v:175519$12191_Y + connect \$1 $not$libresoc.v:175520$12192_Y + connect \$3 $and$libresoc.v:175521$12193_Y + connect \$5 $or$libresoc.v:175522$12194_Y + connect \$7 $not$libresoc.v:175523$12195_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:172117.1-172175.10" +attribute \src "libresoc.v:175542.1-175600.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" -module \rst_l$84 - attribute \src "libresoc.v:172118.7-172118.20" +module \rst_l$87 + attribute \src "libresoc.v:175543.7-175543.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172163.3-172171.6" - wire $0\q_int$next[0:0]$11814 - attribute \src "libresoc.v:172161.3-172162.27" + attribute \src "libresoc.v:175588.3-175596.6" + wire $0\q_int$next[0:0]$12212 + attribute \src "libresoc.v:175586.3-175587.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:172163.3-172171.6" - wire $1\q_int$next[0:0]$11815 - attribute \src "libresoc.v:172140.7-172140.19" + attribute \src "libresoc.v:175588.3-175596.6" + wire $1\q_int$next[0:0]$12213 + attribute \src "libresoc.v:175565.7-175565.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:172153.17-172153.96" - wire $and$libresoc.v:172153$11804_Y - attribute \src "libresoc.v:172158.17-172158.96" - wire $and$libresoc.v:172158$11809_Y - attribute \src "libresoc.v:172155.18-172155.93" - wire $not$libresoc.v:172155$11806_Y - attribute \src "libresoc.v:172157.17-172157.92" - wire $not$libresoc.v:172157$11808_Y - attribute \src "libresoc.v:172160.17-172160.92" - wire $not$libresoc.v:172160$11811_Y - attribute \src "libresoc.v:172154.18-172154.98" - wire $or$libresoc.v:172154$11805_Y - attribute \src "libresoc.v:172156.18-172156.99" - wire $or$libresoc.v:172156$11807_Y - attribute \src "libresoc.v:172159.17-172159.97" - wire $or$libresoc.v:172159$11810_Y + attribute \src "libresoc.v:175578.17-175578.96" + wire $and$libresoc.v:175578$12202_Y + attribute \src "libresoc.v:175583.17-175583.96" + wire $and$libresoc.v:175583$12207_Y + attribute \src "libresoc.v:175580.18-175580.93" + wire $not$libresoc.v:175580$12204_Y + attribute \src "libresoc.v:175582.17-175582.92" + wire $not$libresoc.v:175582$12206_Y + attribute \src "libresoc.v:175585.17-175585.92" + wire $not$libresoc.v:175585$12209_Y + attribute \src "libresoc.v:175579.18-175579.98" + wire $or$libresoc.v:175579$12203_Y + attribute \src "libresoc.v:175581.18-175581.99" + wire $or$libresoc.v:175581$12205_Y + attribute \src "libresoc.v:175584.17-175584.97" + wire $or$libresoc.v:175584$12208_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -358884,11 +366814,11 @@ module \rst_l$84 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:172118.7-172118.15" + attribute \src "libresoc.v:175543.7-175543.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -358905,7 +366835,7 @@ module \rst_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172153$11804 + cell $and $and$libresoc.v:175578$12202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358913,10 +366843,10 @@ module \rst_l$84 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:172153$11804_Y + connect \Y $and$libresoc.v:175578$12202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172158$11809 + cell $and $and$libresoc.v:175583$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358924,34 +366854,34 @@ module \rst_l$84 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:172158$11809_Y + connect \Y $and$libresoc.v:175583$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172155$11806 + cell $not $not$libresoc.v:175580$12204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:172155$11806_Y + connect \Y $not$libresoc.v:175580$12204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172157$11808 + cell $not $not$libresoc.v:175582$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172157$11808_Y + connect \Y $not$libresoc.v:175582$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172160$11811 + cell $not $not$libresoc.v:175585$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:172160$11811_Y + connect \Y $not$libresoc.v:175585$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172154$11805 + cell $or $or$libresoc.v:175579$12203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358959,10 +366889,10 @@ module \rst_l$84 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:172154$11805_Y + connect \Y $or$libresoc.v:175579$12203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172156$11807 + cell $or $or$libresoc.v:175581$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358970,10 +366900,10 @@ module \rst_l$84 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:172156$11807_Y + connect \Y $or$libresoc.v:175581$12205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172159$11810 + cell $or $or$libresoc.v:175584$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -358981,39 +366911,39 @@ module \rst_l$84 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:172159$11810_Y + connect \Y $or$libresoc.v:175584$12208_Y end - attribute \src "libresoc.v:172118.7-172118.20" - process $proc$libresoc.v:172118$11816 + attribute \src "libresoc.v:175543.7-175543.20" + process $proc$libresoc.v:175543$12214 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172140.7-172140.19" - process $proc$libresoc.v:172140$11817 + attribute \src "libresoc.v:175565.7-175565.19" + process $proc$libresoc.v:175565$12215 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:172161.3-172162.27" - process $proc$libresoc.v:172161$11812 + attribute \src "libresoc.v:175586.3-175587.27" + process $proc$libresoc.v:175586$12210 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:172163.3-172171.6" - process $proc$libresoc.v:172163$11813 + attribute \src "libresoc.v:175588.3-175596.6" + process $proc$libresoc.v:175588$12211 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11814 $1\q_int$next[0:0]$11815 - attribute \src "libresoc.v:172164.5-172164.29" + assign $0\q_int$next[0:0]$12212 $1\q_int$next[0:0]$12213 + attribute \src "libresoc.v:175589.5-175589.29" switch \initial - attribute \src "libresoc.v:172164.9-172164.17" + attribute \src "libresoc.v:175589.9-175589.17" case 1'1 case end @@ -359022,92 +366952,92 @@ module \rst_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$11815 1'0 + assign $1\q_int$next[0:0]$12213 1'0 case - assign $1\q_int$next[0:0]$11815 \$5 + assign $1\q_int$next[0:0]$12213 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$11814 + update \q_int$next $0\q_int$next[0:0]$12212 end - connect \$9 $and$libresoc.v:172153$11804_Y - connect \$11 $or$libresoc.v:172154$11805_Y - connect \$13 $not$libresoc.v:172155$11806_Y - connect \$15 $or$libresoc.v:172156$11807_Y - connect \$1 $not$libresoc.v:172157$11808_Y - connect \$3 $and$libresoc.v:172158$11809_Y - connect \$5 $or$libresoc.v:172159$11810_Y - connect \$7 $not$libresoc.v:172160$11811_Y + connect \$9 $and$libresoc.v:175578$12202_Y + connect \$11 $or$libresoc.v:175579$12203_Y + connect \$13 $not$libresoc.v:175580$12204_Y + connect \$15 $or$libresoc.v:175581$12205_Y + connect \$1 $not$libresoc.v:175582$12206_Y + connect \$3 $and$libresoc.v:175583$12207_Y + connect \$5 $or$libresoc.v:175584$12208_Y + connect \$7 $not$libresoc.v:175585$12209_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:172179.1-172582.10" +attribute \src "libresoc.v:175604.1-176007.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.setup_stage" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:172540.3-172565.6" + attribute \src "libresoc.v:175965.3-175990.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:172180.7-172180.20" + attribute \src "libresoc.v:175605.7-175605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172540.3-172565.6" + attribute \src "libresoc.v:175965.3-175990.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:172540.3-172565.6" + attribute \src "libresoc.v:175965.3-175990.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:172519.18-172519.122" - wire $and$libresoc.v:172519$11819_Y - attribute \src "libresoc.v:172521.18-172521.122" - wire $and$libresoc.v:172521$11821_Y - attribute \src "libresoc.v:172530.18-172530.105" - wire $and$libresoc.v:172530$11834_Y - attribute \src "libresoc.v:172533.18-172533.105" - wire $and$libresoc.v:172533$11837_Y - attribute \src "libresoc.v:172529.18-172529.123" - wire $eq$libresoc.v:172529$11833_Y - attribute \src "libresoc.v:172532.18-172532.123" - wire $eq$libresoc.v:172532$11836_Y - attribute \src "libresoc.v:172535.18-172535.117" - wire $eq$libresoc.v:172535$11839_Y - attribute \src "libresoc.v:172522.18-172522.97" - wire width 65 $extend$libresoc.v:172522$11822_Y - attribute \src "libresoc.v:172523.18-172523.91" - wire width 65 $extend$libresoc.v:172523$11824_Y - attribute \src "libresoc.v:172525.18-172525.97" - wire width 65 $extend$libresoc.v:172525$11827_Y - attribute \src "libresoc.v:172526.18-172526.91" - wire width 65 $extend$libresoc.v:172526$11829_Y - attribute \src "libresoc.v:172538.18-172538.99" - wire width 128 $extend$libresoc.v:172538$11842_Y - attribute \src "libresoc.v:172528.18-172528.112" - wire $ge$libresoc.v:172528$11832_Y - attribute \src "libresoc.v:172531.18-172531.124" - wire $ge$libresoc.v:172531$11835_Y - attribute \src "libresoc.v:172522.18-172522.97" - wire width 65 $neg$libresoc.v:172522$11823_Y - attribute \src "libresoc.v:172525.18-172525.97" - wire width 65 $neg$libresoc.v:172525$11828_Y - attribute \src "libresoc.v:172523.18-172523.91" - wire width 65 $pos$libresoc.v:172523$11825_Y - attribute \src "libresoc.v:172526.18-172526.91" - wire width 65 $pos$libresoc.v:172526$11830_Y - attribute \src "libresoc.v:172538.18-172538.99" - wire width 128 $pos$libresoc.v:172538$11843_Y - attribute \src "libresoc.v:172537.18-172537.117" - wire width 95 $sshl$libresoc.v:172537$11841_Y - attribute \src "libresoc.v:172539.18-172539.111" - wire width 191 $sshl$libresoc.v:172539$11844_Y - attribute \src "libresoc.v:172518.18-172518.131" - wire $ternary$libresoc.v:172518$11818_Y - attribute \src "libresoc.v:172520.18-172520.131" - wire $ternary$libresoc.v:172520$11820_Y - attribute \src "libresoc.v:172524.18-172524.119" - wire width 65 $ternary$libresoc.v:172524$11826_Y - attribute \src "libresoc.v:172527.18-172527.120" - wire width 65 $ternary$libresoc.v:172527$11831_Y - attribute \src "libresoc.v:172534.18-172534.130" - wire width 32 $ternary$libresoc.v:172534$11838_Y - attribute \src "libresoc.v:172536.18-172536.131" - wire width 32 $ternary$libresoc.v:172536$11840_Y + attribute \src "libresoc.v:175944.18-175944.122" + wire $and$libresoc.v:175944$12217_Y + attribute \src "libresoc.v:175946.18-175946.122" + wire $and$libresoc.v:175946$12219_Y + attribute \src "libresoc.v:175955.18-175955.105" + wire $and$libresoc.v:175955$12232_Y + attribute \src "libresoc.v:175958.18-175958.105" + wire $and$libresoc.v:175958$12235_Y + attribute \src "libresoc.v:175954.18-175954.123" + wire $eq$libresoc.v:175954$12231_Y + attribute \src "libresoc.v:175957.18-175957.123" + wire $eq$libresoc.v:175957$12234_Y + attribute \src "libresoc.v:175960.18-175960.117" + wire $eq$libresoc.v:175960$12237_Y + attribute \src "libresoc.v:175947.18-175947.97" + wire width 65 $extend$libresoc.v:175947$12220_Y + attribute \src "libresoc.v:175948.18-175948.91" + wire width 65 $extend$libresoc.v:175948$12222_Y + attribute \src "libresoc.v:175950.18-175950.97" + wire width 65 $extend$libresoc.v:175950$12225_Y + attribute \src "libresoc.v:175951.18-175951.91" + wire width 65 $extend$libresoc.v:175951$12227_Y + attribute \src "libresoc.v:175963.18-175963.99" + wire width 128 $extend$libresoc.v:175963$12240_Y + attribute \src "libresoc.v:175953.18-175953.112" + wire $ge$libresoc.v:175953$12230_Y + attribute \src "libresoc.v:175956.18-175956.124" + wire $ge$libresoc.v:175956$12233_Y + attribute \src "libresoc.v:175947.18-175947.97" + wire width 65 $neg$libresoc.v:175947$12221_Y + attribute \src "libresoc.v:175950.18-175950.97" + wire width 65 $neg$libresoc.v:175950$12226_Y + attribute \src "libresoc.v:175948.18-175948.91" + wire width 65 $pos$libresoc.v:175948$12223_Y + attribute \src "libresoc.v:175951.18-175951.91" + wire width 65 $pos$libresoc.v:175951$12228_Y + attribute \src "libresoc.v:175963.18-175963.99" + wire width 128 $pos$libresoc.v:175963$12241_Y + attribute \src "libresoc.v:175962.18-175962.117" + wire width 95 $sshl$libresoc.v:175962$12239_Y + attribute \src "libresoc.v:175964.18-175964.111" + wire width 191 $sshl$libresoc.v:175964$12242_Y + attribute \src "libresoc.v:175943.18-175943.131" + wire $ternary$libresoc.v:175943$12216_Y + attribute \src "libresoc.v:175945.18-175945.131" + wire $ternary$libresoc.v:175945$12218_Y + attribute \src "libresoc.v:175949.18-175949.119" + wire width 65 $ternary$libresoc.v:175949$12224_Y + attribute \src "libresoc.v:175952.18-175952.120" + wire width 65 $ternary$libresoc.v:175952$12229_Y + attribute \src "libresoc.v:175959.18-175959.130" + wire width 32 $ternary$libresoc.v:175959$12236_Y + attribute \src "libresoc.v:175961.18-175961.131" + wire width 32 $ternary$libresoc.v:175961$12238_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -359176,7 +367106,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:172180.7-172180.15" + attribute \src "libresoc.v:175605.7-175605.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -359447,7 +367377,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:172519$11819 + cell $and $and$libresoc.v:175944$12217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -359455,10 +367385,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:172519$11819_Y + connect \Y $and$libresoc.v:175944$12217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:172521$11821 + cell $and $and$libresoc.v:175946$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -359466,10 +367396,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:172521$11821_Y + connect \Y $and$libresoc.v:175946$12219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:172530$11834 + cell $and $and$libresoc.v:175955$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -359477,10 +367407,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:172530$11834_Y + connect \Y $and$libresoc.v:175955$12232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:172533$11837 + cell $and $and$libresoc.v:175958$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -359488,10 +367418,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:172533$11837_Y + connect \Y $and$libresoc.v:175958$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:172529$11833 + cell $eq $eq$libresoc.v:175954$12231 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -359499,10 +367429,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:172529$11833_Y + connect \Y $eq$libresoc.v:175954$12231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:172532$11836 + cell $eq $eq$libresoc.v:175957$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -359510,10 +367440,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:172532$11836_Y + connect \Y $eq$libresoc.v:175957$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:172535$11839 + cell $eq $eq$libresoc.v:175960$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -359521,50 +367451,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:172535$11839_Y + connect \Y $eq$libresoc.v:175960$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:172522$11822 + cell $pos $extend$libresoc.v:175947$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:172522$11822_Y + connect \Y $extend$libresoc.v:175947$12220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:172523$11824 + cell $pos $extend$libresoc.v:175948$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:172523$11824_Y + connect \Y $extend$libresoc.v:175948$12222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:172525$11827 + cell $pos $extend$libresoc.v:175950$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:172525$11827_Y + connect \Y $extend$libresoc.v:175950$12225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:172526$11829 + cell $pos $extend$libresoc.v:175951$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:172526$11829_Y + connect \Y $extend$libresoc.v:175951$12227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:172538$11842 + cell $pos $extend$libresoc.v:175963$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:172538$11842_Y + connect \Y $extend$libresoc.v:175963$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:172528$11832 + cell $ge $ge$libresoc.v:175953$12230 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -359572,10 +367502,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:172528$11832_Y + connect \Y $ge$libresoc.v:175953$12230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:172531$11835 + cell $ge $ge$libresoc.v:175956$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -359583,50 +367513,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:172531$11835_Y + connect \Y $ge$libresoc.v:175956$12233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:172522$11823 + cell $neg $neg$libresoc.v:175947$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:172522$11822_Y - connect \Y $neg$libresoc.v:172522$11823_Y + connect \A $extend$libresoc.v:175947$12220_Y + connect \Y $neg$libresoc.v:175947$12221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:172525$11828 + cell $neg $neg$libresoc.v:175950$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:172525$11827_Y - connect \Y $neg$libresoc.v:172525$11828_Y + connect \A $extend$libresoc.v:175950$12225_Y + connect \Y $neg$libresoc.v:175950$12226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:172523$11825 + cell $pos $pos$libresoc.v:175948$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:172523$11824_Y - connect \Y $pos$libresoc.v:172523$11825_Y + connect \A $extend$libresoc.v:175948$12222_Y + connect \Y $pos$libresoc.v:175948$12223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:172526$11830 + cell $pos $pos$libresoc.v:175951$12228 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:172526$11829_Y - connect \Y $pos$libresoc.v:172526$11830_Y + connect \A $extend$libresoc.v:175951$12227_Y + connect \Y $pos$libresoc.v:175951$12228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:172538$11843 + cell $pos $pos$libresoc.v:175963$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:172538$11842_Y - connect \Y $pos$libresoc.v:172538$11843_Y + connect \A $extend$libresoc.v:175963$12240_Y + connect \Y $pos$libresoc.v:175963$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:172537$11841 + cell $sshl $sshl$libresoc.v:175962$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -359634,10 +367564,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:172537$11841_Y + connect \Y $sshl$libresoc.v:175962$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:172539$11844 + cell $sshl $sshl$libresoc.v:175964$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -359645,72 +367575,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:172539$11844_Y + connect \Y $sshl$libresoc.v:175964$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:172518$11818 + cell $mux $ternary$libresoc.v:175943$12216 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:172518$11818_Y + connect \Y $ternary$libresoc.v:175943$12216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:172520$11820 + cell $mux $ternary$libresoc.v:175945$12218 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:172520$11820_Y + connect \Y $ternary$libresoc.v:175945$12218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:172524$11826 + cell $mux $ternary$libresoc.v:175949$12224 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:172524$11826_Y + connect \Y $ternary$libresoc.v:175949$12224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:172527$11831 + cell $mux $ternary$libresoc.v:175952$12229 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:172527$11831_Y + connect \Y $ternary$libresoc.v:175952$12229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:172534$11838 + cell $mux $ternary$libresoc.v:175959$12236 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:172534$11838_Y + connect \Y $ternary$libresoc.v:175959$12236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:172536$11840 + cell $mux $ternary$libresoc.v:175961$12238 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:172536$11840_Y + connect \Y $ternary$libresoc.v:175961$12238_Y end - attribute \src "libresoc.v:172180.7-172180.20" - process $proc$libresoc.v:172180$11846 + attribute \src "libresoc.v:175605.7-175605.20" + process $proc$libresoc.v:175605$12244 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172540.3-172565.6" - process $proc$libresoc.v:172540$11845 + attribute \src "libresoc.v:175965.3-175990.6" + process $proc$libresoc.v:175965$12243 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:172541.5-172541.29" + attribute \src "libresoc.v:175966.5-175966.29" switch \initial - attribute \src "libresoc.v:172541.9-172541.17" + attribute \src "libresoc.v:175966.9-175966.17" case 1'1 case end @@ -359742,28 +367672,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:172518$11818_Y - connect \$23 $and$libresoc.v:172519$11819_Y - connect \$25 $ternary$libresoc.v:172520$11820_Y - connect \$27 $and$libresoc.v:172521$11821_Y - connect \$30 $neg$libresoc.v:172522$11823_Y - connect \$32 $pos$libresoc.v:172523$11825_Y - connect \$34 $ternary$libresoc.v:172524$11826_Y - connect \$37 $neg$libresoc.v:172525$11828_Y - connect \$39 $pos$libresoc.v:172526$11830_Y - connect \$41 $ternary$libresoc.v:172527$11831_Y - connect \$43 $ge$libresoc.v:172528$11832_Y - connect \$45 $eq$libresoc.v:172529$11833_Y - connect \$47 $and$libresoc.v:172530$11834_Y - connect \$49 $ge$libresoc.v:172531$11835_Y - connect \$51 $eq$libresoc.v:172532$11836_Y - connect \$53 $and$libresoc.v:172533$11837_Y - connect \$55 $ternary$libresoc.v:172534$11838_Y - connect \$57 $eq$libresoc.v:172535$11839_Y - connect \$59 $ternary$libresoc.v:172536$11840_Y - connect \$62 $sshl$libresoc.v:172537$11841_Y - connect \$61 $pos$libresoc.v:172538$11843_Y - connect \$66 $sshl$libresoc.v:172539$11844_Y + connect \$21 $ternary$libresoc.v:175943$12216_Y + connect \$23 $and$libresoc.v:175944$12217_Y + connect \$25 $ternary$libresoc.v:175945$12218_Y + connect \$27 $and$libresoc.v:175946$12219_Y + connect \$30 $neg$libresoc.v:175947$12221_Y + connect \$32 $pos$libresoc.v:175948$12223_Y + connect \$34 $ternary$libresoc.v:175949$12224_Y + connect \$37 $neg$libresoc.v:175950$12226_Y + connect \$39 $pos$libresoc.v:175951$12228_Y + connect \$41 $ternary$libresoc.v:175952$12229_Y + connect \$43 $ge$libresoc.v:175953$12230_Y + connect \$45 $eq$libresoc.v:175954$12231_Y + connect \$47 $and$libresoc.v:175955$12232_Y + connect \$49 $ge$libresoc.v:175956$12233_Y + connect \$51 $eq$libresoc.v:175957$12234_Y + connect \$53 $and$libresoc.v:175958$12235_Y + connect \$55 $ternary$libresoc.v:175959$12236_Y + connect \$57 $eq$libresoc.v:175960$12237_Y + connect \$59 $ternary$libresoc.v:175961$12238_Y + connect \$62 $sshl$libresoc.v:175962$12239_Y + connect \$61 $pos$libresoc.v:175963$12241_Y + connect \$66 $sshl$libresoc.v:175964$12242_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -359781,505 +367711,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:172586.1-173777.10" +attribute \src "libresoc.v:176011.1-177212.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:173350.3-173351.25" + attribute \src "libresoc.v:176783.3-176784.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:173348.3-173349.46" + attribute \src "libresoc.v:176781.3-176782.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:173697.3-173705.6" - wire $0\alu_l_r_alu$next[0:0]$12061 - attribute \src "libresoc.v:173268.3-173269.39" + attribute \src "libresoc.v:177132.3-177140.6" + wire $0\alu_l_r_alu$next[0:0]$12462 + attribute \src "libresoc.v:176699.3-176700.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 - attribute \src "libresoc.v:173296.3-173297.75" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 + attribute \src "libresoc.v:176727.3-176728.75" wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 - attribute \src "libresoc.v:173298.3-173299.89" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 + attribute \src "libresoc.v:176729.3-176730.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 - attribute \src "libresoc.v:173300.3-173301.85" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 + attribute \src "libresoc.v:176731.3-176732.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 - attribute \src "libresoc.v:173312.3-173313.83" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 + attribute \src "libresoc.v:176745.3-176746.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 - attribute \src "libresoc.v:173316.3-173317.77" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 + attribute \src "libresoc.v:176749.3-176750.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 - attribute \src "libresoc.v:173324.3-173325.69" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 + attribute \src "libresoc.v:176757.3-176758.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 - attribute \src "libresoc.v:173294.3-173295.79" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 + attribute \src "libresoc.v:176725.3-176726.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 - attribute \src "libresoc.v:173320.3-173321.77" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 + attribute \src "libresoc.v:176743.3-176744.79" + wire $0\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 + attribute \src "libresoc.v:176753.3-176754.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 - attribute \src "libresoc.v:173322.3-173323.79" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 + attribute \src "libresoc.v:176755.3-176756.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 - attribute \src "libresoc.v:173306.3-173307.73" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 + attribute \src "libresoc.v:176737.3-176738.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 - attribute \src "libresoc.v:173308.3-173309.73" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 + attribute \src "libresoc.v:176739.3-176740.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 - attribute \src "libresoc.v:173314.3-173315.85" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 + attribute \src "libresoc.v:176747.3-176748.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 - attribute \src "libresoc.v:173318.3-173319.79" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 + attribute \src "libresoc.v:176751.3-176752.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 - attribute \src "libresoc.v:173304.3-173305.73" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 + attribute \src "libresoc.v:176735.3-176736.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 - attribute \src "libresoc.v:173302.3-173303.73" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 + attribute \src "libresoc.v:176733.3-176734.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 - attribute \src "libresoc.v:173310.3-173311.79" + attribute \src "libresoc.v:176969.3-177006.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 + attribute \src "libresoc.v:176741.3-176742.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:173688.3-173696.6" - wire $0\alui_l_r_alui$next[0:0]$12058 - attribute \src "libresoc.v:173270.3-173271.43" + attribute \src "libresoc.v:177123.3-177131.6" + wire $0\alui_l_r_alui$next[0:0]$12459 + attribute \src "libresoc.v:176701.3-176702.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:173572.3-173593.6" - wire width 64 $0\data_r0__o$next[63:0]$12019 - attribute \src "libresoc.v:173290.3-173291.37" + attribute \src "libresoc.v:177007.3-177028.6" + wire width 64 $0\data_r0__o$next[63:0]$12420 + attribute \src "libresoc.v:176721.3-176722.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:173572.3-173593.6" - wire $0\data_r0__o_ok$next[0:0]$12020 - attribute \src "libresoc.v:173292.3-173293.43" + attribute \src "libresoc.v:177007.3-177028.6" + wire $0\data_r0__o_ok$next[0:0]$12421 + attribute \src "libresoc.v:176723.3-176724.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:173594.3-173615.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12027 - attribute \src "libresoc.v:173286.3-173287.43" + attribute \src "libresoc.v:177029.3-177050.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12428 + attribute \src "libresoc.v:176717.3-176718.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:173594.3-173615.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12028 - attribute \src "libresoc.v:173288.3-173289.49" + attribute \src "libresoc.v:177029.3-177050.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12429 + attribute \src "libresoc.v:176719.3-176720.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:173616.3-173637.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12035 - attribute \src "libresoc.v:173282.3-173283.47" + attribute \src "libresoc.v:177051.3-177072.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12436 + attribute \src "libresoc.v:176713.3-176714.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:173616.3-173637.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12036 - attribute \src "libresoc.v:173284.3-173285.53" + attribute \src "libresoc.v:177051.3-177072.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12437 + attribute \src "libresoc.v:176715.3-176716.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:173706.3-173715.6" + attribute \src "libresoc.v:177141.3-177150.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:173716.3-173725.6" + attribute \src "libresoc.v:177151.3-177160.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:173726.3-173735.6" + attribute \src "libresoc.v:177161.3-177170.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:172587.7-172587.20" + attribute \src "libresoc.v:176012.7-176012.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173490.3-173498.6" - wire $0\opc_l_r_opc$next[0:0]$11965 - attribute \src "libresoc.v:173334.3-173335.39" + attribute \src "libresoc.v:176924.3-176932.6" + wire $0\opc_l_r_opc$next[0:0]$12364 + attribute \src "libresoc.v:176767.3-176768.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:173481.3-173489.6" - wire $0\opc_l_s_opc$next[0:0]$11962 - attribute \src "libresoc.v:173336.3-173337.39" + attribute \src "libresoc.v:176915.3-176923.6" + wire $0\opc_l_s_opc$next[0:0]$12361 + attribute \src "libresoc.v:176769.3-176770.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:173736.3-173744.6" - wire width 3 $0\prev_wr_go$next[2:0]$12067 - attribute \src "libresoc.v:173346.3-173347.37" + attribute \src "libresoc.v:177171.3-177179.6" + wire width 3 $0\prev_wr_go$next[2:0]$12468 + attribute \src "libresoc.v:176779.3-176780.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:173435.3-173444.6" + attribute \src "libresoc.v:176869.3-176878.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:173526.3-173534.6" - wire width 3 $0\req_l_r_req$next[2:0]$11977 - attribute \src "libresoc.v:173326.3-173327.39" + attribute \src "libresoc.v:176960.3-176968.6" + wire width 3 $0\req_l_r_req$next[2:0]$12376 + attribute \src "libresoc.v:176759.3-176760.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:173517.3-173525.6" - wire width 3 $0\req_l_s_req$next[2:0]$11974 - attribute \src "libresoc.v:173328.3-173329.39" + attribute \src "libresoc.v:176951.3-176959.6" + wire width 3 $0\req_l_s_req$next[2:0]$12373 + attribute \src "libresoc.v:176761.3-176762.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:173454.3-173462.6" - wire $0\rok_l_r_rdok$next[0:0]$11953 - attribute \src "libresoc.v:173342.3-173343.41" + attribute \src "libresoc.v:176888.3-176896.6" + wire $0\rok_l_r_rdok$next[0:0]$12352 + attribute \src "libresoc.v:176775.3-176776.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:173445.3-173453.6" - wire $0\rok_l_s_rdok$next[0:0]$11950 - attribute \src "libresoc.v:173344.3-173345.41" + attribute \src "libresoc.v:176879.3-176887.6" + wire $0\rok_l_s_rdok$next[0:0]$12349 + attribute \src "libresoc.v:176777.3-176778.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:173472.3-173480.6" - wire $0\rst_l_r_rst$next[0:0]$11959 - attribute \src "libresoc.v:173338.3-173339.39" + attribute \src "libresoc.v:176906.3-176914.6" + wire $0\rst_l_r_rst$next[0:0]$12358 + attribute \src "libresoc.v:176771.3-176772.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:173463.3-173471.6" - wire $0\rst_l_s_rst$next[0:0]$11956 - attribute \src "libresoc.v:173340.3-173341.39" + attribute \src "libresoc.v:176897.3-176905.6" + wire $0\rst_l_s_rst$next[0:0]$12355 + attribute \src "libresoc.v:176773.3-176774.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:173508.3-173516.6" - wire width 5 $0\src_l_r_src$next[4:0]$11971 - attribute \src "libresoc.v:173330.3-173331.39" + attribute \src "libresoc.v:176942.3-176950.6" + wire width 5 $0\src_l_r_src$next[4:0]$12370 + attribute \src "libresoc.v:176763.3-176764.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:173499.3-173507.6" - wire width 5 $0\src_l_s_src$next[4:0]$11968 - attribute \src "libresoc.v:173332.3-173333.39" + attribute \src "libresoc.v:176933.3-176941.6" + wire width 5 $0\src_l_s_src$next[4:0]$12367 + attribute \src "libresoc.v:176765.3-176766.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:173638.3-173647.6" - wire width 64 $0\src_r0$next[63:0]$12043 - attribute \src "libresoc.v:173280.3-173281.29" + attribute \src "libresoc.v:177073.3-177082.6" + wire width 64 $0\src_r0$next[63:0]$12444 + attribute \src "libresoc.v:176711.3-176712.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:173648.3-173657.6" - wire width 64 $0\src_r1$next[63:0]$12046 - attribute \src "libresoc.v:173278.3-173279.29" + attribute \src "libresoc.v:177083.3-177092.6" + wire width 64 $0\src_r1$next[63:0]$12447 + attribute \src "libresoc.v:176709.3-176710.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:173658.3-173667.6" - wire width 64 $0\src_r2$next[63:0]$12049 - attribute \src "libresoc.v:173276.3-173277.29" + attribute \src "libresoc.v:177093.3-177102.6" + wire width 64 $0\src_r2$next[63:0]$12450 + attribute \src "libresoc.v:176707.3-176708.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:173668.3-173677.6" - wire $0\src_r3$next[0:0]$12052 - attribute \src "libresoc.v:173274.3-173275.29" + attribute \src "libresoc.v:177103.3-177112.6" + wire $0\src_r3$next[0:0]$12453 + attribute \src "libresoc.v:176705.3-176706.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:173678.3-173687.6" - wire width 2 $0\src_r4$next[1:0]$12055 - attribute \src "libresoc.v:173272.3-173273.29" + attribute \src "libresoc.v:177113.3-177122.6" + wire width 2 $0\src_r4$next[1:0]$12456 + attribute \src "libresoc.v:176703.3-176704.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:172709.7-172709.24" + attribute \src "libresoc.v:176134.7-176134.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:172719.7-172719.26" + attribute \src "libresoc.v:176144.7-176144.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:173697.3-173705.6" - wire $1\alu_l_r_alu$next[0:0]$12062 - attribute \src "libresoc.v:172727.7-172727.25" + attribute \src "libresoc.v:177132.3-177140.6" + wire $1\alu_l_r_alu$next[0:0]$12463 + attribute \src "libresoc.v:176152.7-176152.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 - attribute \src "libresoc.v:172768.14-172768.53" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 + attribute \src "libresoc.v:176193.14-176193.53" wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 - attribute \src "libresoc.v:172772.14-172772.73" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 + attribute \src "libresoc.v:176197.14-176197.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 - attribute \src "libresoc.v:172776.7-172776.48" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 + attribute \src "libresoc.v:176201.7-176201.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 - attribute \src "libresoc.v:172784.13-172784.53" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 + attribute \src "libresoc.v:176209.13-176209.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 - attribute \src "libresoc.v:172788.7-172788.44" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 + attribute \src "libresoc.v:176213.7-176213.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 - attribute \src "libresoc.v:172792.14-172792.48" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 + attribute \src "libresoc.v:176217.14-176217.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 - attribute \src "libresoc.v:172870.13-172870.52" + attribute \src "libresoc.v:176969.3-177006.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 + attribute \src "libresoc.v:176295.13-176295.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 - attribute \src "libresoc.v:172874.7-172874.44" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 + attribute \src "libresoc.v:176299.7-176299.45" + wire $1\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 + attribute \src "libresoc.v:176303.7-176303.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 - attribute \src "libresoc.v:172878.7-172878.45" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 + attribute \src "libresoc.v:176307.7-176307.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 - attribute \src "libresoc.v:172882.7-172882.42" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 + attribute \src "libresoc.v:176311.7-176311.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 - attribute \src "libresoc.v:172886.7-172886.42" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 + attribute \src "libresoc.v:176315.7-176315.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 - attribute \src "libresoc.v:172890.7-172890.48" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 + attribute \src "libresoc.v:176319.7-176319.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 - attribute \src "libresoc.v:172894.7-172894.45" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 + attribute \src "libresoc.v:176323.7-176323.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 - attribute \src "libresoc.v:172898.7-172898.42" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 + attribute \src "libresoc.v:176327.7-176327.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 - attribute \src "libresoc.v:172902.7-172902.42" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 + attribute \src "libresoc.v:176331.7-176331.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 - attribute \src "libresoc.v:172906.7-172906.45" + attribute \src "libresoc.v:176969.3-177006.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 + attribute \src "libresoc.v:176335.7-176335.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:173688.3-173696.6" - wire $1\alui_l_r_alui$next[0:0]$12059 - attribute \src "libresoc.v:172918.7-172918.27" + attribute \src "libresoc.v:177123.3-177131.6" + wire $1\alui_l_r_alui$next[0:0]$12460 + attribute \src "libresoc.v:176347.7-176347.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:173572.3-173593.6" - wire width 64 $1\data_r0__o$next[63:0]$12021 - attribute \src "libresoc.v:172952.14-172952.47" + attribute \src "libresoc.v:177007.3-177028.6" + wire width 64 $1\data_r0__o$next[63:0]$12422 + attribute \src "libresoc.v:176381.14-176381.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:173572.3-173593.6" - wire $1\data_r0__o_ok$next[0:0]$12022 - attribute \src "libresoc.v:172956.7-172956.27" + attribute \src "libresoc.v:177007.3-177028.6" + wire $1\data_r0__o_ok$next[0:0]$12423 + attribute \src "libresoc.v:176385.7-176385.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:173594.3-173615.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12029 - attribute \src "libresoc.v:172960.13-172960.33" + attribute \src "libresoc.v:177029.3-177050.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12430 + attribute \src "libresoc.v:176389.13-176389.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:173594.3-173615.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12030 - attribute \src "libresoc.v:172964.7-172964.30" + attribute \src "libresoc.v:177029.3-177050.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12431 + attribute \src "libresoc.v:176393.7-176393.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:173616.3-173637.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12037 - attribute \src "libresoc.v:172968.13-172968.35" + attribute \src "libresoc.v:177051.3-177072.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12438 + attribute \src "libresoc.v:176397.13-176397.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:173616.3-173637.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12038 - attribute \src "libresoc.v:172972.7-172972.32" + attribute \src "libresoc.v:177051.3-177072.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12439 + attribute \src "libresoc.v:176401.7-176401.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:173706.3-173715.6" + attribute \src "libresoc.v:177141.3-177150.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:173716.3-173725.6" + attribute \src "libresoc.v:177151.3-177160.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:173726.3-173735.6" + attribute \src "libresoc.v:177161.3-177170.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:173490.3-173498.6" - wire $1\opc_l_r_opc$next[0:0]$11966 - attribute \src "libresoc.v:172989.7-172989.25" + attribute \src "libresoc.v:176924.3-176932.6" + wire $1\opc_l_r_opc$next[0:0]$12365 + attribute \src "libresoc.v:176418.7-176418.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:173481.3-173489.6" - wire $1\opc_l_s_opc$next[0:0]$11963 - attribute \src "libresoc.v:172993.7-172993.25" + attribute \src "libresoc.v:176915.3-176923.6" + wire $1\opc_l_s_opc$next[0:0]$12362 + attribute \src "libresoc.v:176422.7-176422.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:173736.3-173744.6" - wire width 3 $1\prev_wr_go$next[2:0]$12068 - attribute \src "libresoc.v:173120.13-173120.30" + attribute \src "libresoc.v:177171.3-177179.6" + wire width 3 $1\prev_wr_go$next[2:0]$12469 + attribute \src "libresoc.v:176551.13-176551.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:173435.3-173444.6" + attribute \src "libresoc.v:176869.3-176878.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:173526.3-173534.6" - wire width 3 $1\req_l_r_req$next[2:0]$11978 - attribute \src "libresoc.v:173128.13-173128.31" + attribute \src "libresoc.v:176960.3-176968.6" + wire width 3 $1\req_l_r_req$next[2:0]$12377 + attribute \src "libresoc.v:176559.13-176559.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:173517.3-173525.6" - wire width 3 $1\req_l_s_req$next[2:0]$11975 - attribute \src "libresoc.v:173132.13-173132.31" + attribute \src "libresoc.v:176951.3-176959.6" + wire width 3 $1\req_l_s_req$next[2:0]$12374 + attribute \src "libresoc.v:176563.13-176563.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:173454.3-173462.6" - wire $1\rok_l_r_rdok$next[0:0]$11954 - attribute \src "libresoc.v:173144.7-173144.26" + attribute \src "libresoc.v:176888.3-176896.6" + wire $1\rok_l_r_rdok$next[0:0]$12353 + attribute \src "libresoc.v:176575.7-176575.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:173445.3-173453.6" - wire $1\rok_l_s_rdok$next[0:0]$11951 - attribute \src "libresoc.v:173148.7-173148.26" + attribute \src "libresoc.v:176879.3-176887.6" + wire $1\rok_l_s_rdok$next[0:0]$12350 + attribute \src "libresoc.v:176579.7-176579.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:173472.3-173480.6" - wire $1\rst_l_r_rst$next[0:0]$11960 - attribute \src "libresoc.v:173152.7-173152.25" + attribute \src "libresoc.v:176906.3-176914.6" + wire $1\rst_l_r_rst$next[0:0]$12359 + attribute \src "libresoc.v:176583.7-176583.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:173463.3-173471.6" - wire $1\rst_l_s_rst$next[0:0]$11957 - attribute \src "libresoc.v:173156.7-173156.25" + attribute \src "libresoc.v:176897.3-176905.6" + wire $1\rst_l_s_rst$next[0:0]$12356 + attribute \src "libresoc.v:176587.7-176587.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:173508.3-173516.6" - wire width 5 $1\src_l_r_src$next[4:0]$11972 - attribute \src "libresoc.v:173174.13-173174.32" + attribute \src "libresoc.v:176942.3-176950.6" + wire width 5 $1\src_l_r_src$next[4:0]$12371 + attribute \src "libresoc.v:176605.13-176605.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:173499.3-173507.6" - wire width 5 $1\src_l_s_src$next[4:0]$11969 - attribute \src "libresoc.v:173178.13-173178.32" + attribute \src "libresoc.v:176933.3-176941.6" + wire width 5 $1\src_l_s_src$next[4:0]$12368 + attribute \src "libresoc.v:176609.13-176609.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:173638.3-173647.6" - wire width 64 $1\src_r0$next[63:0]$12044 - attribute \src "libresoc.v:173184.14-173184.43" + attribute \src "libresoc.v:177073.3-177082.6" + wire width 64 $1\src_r0$next[63:0]$12445 + attribute \src "libresoc.v:176615.14-176615.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:173648.3-173657.6" - wire width 64 $1\src_r1$next[63:0]$12047 - attribute \src "libresoc.v:173188.14-173188.43" + attribute \src "libresoc.v:177083.3-177092.6" + wire width 64 $1\src_r1$next[63:0]$12448 + attribute \src "libresoc.v:176619.14-176619.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:173658.3-173667.6" - wire width 64 $1\src_r2$next[63:0]$12050 - attribute \src "libresoc.v:173192.14-173192.43" + attribute \src "libresoc.v:177093.3-177102.6" + wire width 64 $1\src_r2$next[63:0]$12451 + attribute \src "libresoc.v:176623.14-176623.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:173668.3-173677.6" - wire $1\src_r3$next[0:0]$12053 - attribute \src "libresoc.v:173196.7-173196.20" + attribute \src "libresoc.v:177103.3-177112.6" + wire $1\src_r3$next[0:0]$12454 + attribute \src "libresoc.v:176627.7-176627.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:173678.3-173687.6" - wire width 2 $1\src_r4$next[1:0]$12056 - attribute \src "libresoc.v:173200.13-173200.26" + attribute \src "libresoc.v:177113.3-177122.6" + wire width 2 $1\src_r4$next[1:0]$12457 + attribute \src "libresoc.v:176631.13-176631.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:173535.3-173571.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 - attribute \src "libresoc.v:173535.3-173571.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 - attribute \src "libresoc.v:173535.3-173571.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 - attribute \src "libresoc.v:173535.3-173571.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 - attribute \src "libresoc.v:173535.3-173571.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 - attribute \src "libresoc.v:173535.3-173571.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 - attribute \src "libresoc.v:173572.3-173593.6" - wire width 64 $2\data_r0__o$next[63:0]$12023 - attribute \src "libresoc.v:173572.3-173593.6" - wire $2\data_r0__o_ok$next[0:0]$12024 - attribute \src "libresoc.v:173594.3-173615.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12031 - attribute \src "libresoc.v:173594.3-173615.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12032 - attribute \src "libresoc.v:173616.3-173637.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12039 - attribute \src "libresoc.v:173616.3-173637.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12040 - attribute \src "libresoc.v:173572.3-173593.6" - wire $3\data_r0__o_ok$next[0:0]$12025 - attribute \src "libresoc.v:173594.3-173615.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12033 - attribute \src "libresoc.v:173616.3-173637.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12041 - attribute \src "libresoc.v:173210.19-173210.114" - wire width 5 $and$libresoc.v:173210$11848_Y - attribute \src "libresoc.v:173211.19-173211.125" - wire $and$libresoc.v:173211$11849_Y - attribute \src "libresoc.v:173212.19-173212.125" - wire $and$libresoc.v:173212$11850_Y - attribute \src "libresoc.v:173213.19-173213.125" - wire $and$libresoc.v:173213$11851_Y - attribute \src "libresoc.v:173214.18-173214.110" - wire $and$libresoc.v:173214$11852_Y - attribute \src "libresoc.v:173215.19-173215.141" - wire width 3 $and$libresoc.v:173215$11853_Y - attribute \src "libresoc.v:173216.19-173216.121" - wire width 3 $and$libresoc.v:173216$11854_Y - attribute \src "libresoc.v:173217.19-173217.127" - wire $and$libresoc.v:173217$11855_Y - attribute \src "libresoc.v:173218.19-173218.127" - wire $and$libresoc.v:173218$11856_Y - attribute \src "libresoc.v:173219.19-173219.127" - wire $and$libresoc.v:173219$11857_Y - attribute \src "libresoc.v:173221.18-173221.98" - wire $and$libresoc.v:173221$11859_Y - attribute \src "libresoc.v:173223.18-173223.100" - wire $and$libresoc.v:173223$11861_Y - attribute \src "libresoc.v:173224.18-173224.149" - wire width 3 $and$libresoc.v:173224$11862_Y - attribute \src "libresoc.v:173226.18-173226.119" - wire width 3 $and$libresoc.v:173226$11864_Y - attribute \src "libresoc.v:173229.17-173229.123" - wire $and$libresoc.v:173229$11867_Y - attribute \src "libresoc.v:173230.18-173230.116" - wire $and$libresoc.v:173230$11868_Y - attribute \src "libresoc.v:173235.18-173235.113" - wire $and$libresoc.v:173235$11873_Y - attribute \src "libresoc.v:173236.18-173236.125" - wire width 3 $and$libresoc.v:173236$11874_Y - attribute \src "libresoc.v:173238.18-173238.112" - wire $and$libresoc.v:173238$11876_Y - attribute \src "libresoc.v:173240.18-173240.132" - wire $and$libresoc.v:173240$11878_Y - attribute \src "libresoc.v:173241.18-173241.132" - wire $and$libresoc.v:173241$11879_Y - attribute \src "libresoc.v:173242.18-173242.117" - wire $and$libresoc.v:173242$11880_Y - attribute \src "libresoc.v:173248.18-173248.136" - wire $and$libresoc.v:173248$11886_Y - attribute \src "libresoc.v:173249.18-173249.124" - wire width 3 $and$libresoc.v:173249$11887_Y - attribute \src "libresoc.v:173251.18-173251.116" - wire $and$libresoc.v:173251$11889_Y - attribute \src "libresoc.v:173252.18-173252.119" - wire $and$libresoc.v:173252$11890_Y - attribute \src "libresoc.v:173253.18-173253.121" - wire $and$libresoc.v:173253$11891_Y - attribute \src "libresoc.v:173263.18-173263.140" - wire $and$libresoc.v:173263$11901_Y - attribute \src "libresoc.v:173264.18-173264.138" - wire $and$libresoc.v:173264$11902_Y - attribute \src "libresoc.v:173265.18-173265.171" - wire width 5 $and$libresoc.v:173265$11903_Y - attribute \src "libresoc.v:173267.18-173267.129" - wire width 5 $and$libresoc.v:173267$11905_Y - attribute \src "libresoc.v:173237.18-173237.113" - wire $eq$libresoc.v:173237$11875_Y - attribute \src "libresoc.v:173239.18-173239.119" - wire $eq$libresoc.v:173239$11877_Y - attribute \src "libresoc.v:173209.19-173209.115" - wire width 5 $not$libresoc.v:173209$11847_Y - attribute \src "libresoc.v:173220.18-173220.97" - wire $not$libresoc.v:173220$11858_Y - attribute \src "libresoc.v:173222.18-173222.99" - wire $not$libresoc.v:173222$11860_Y - attribute \src "libresoc.v:173225.18-173225.113" - wire width 3 $not$libresoc.v:173225$11863_Y - attribute \src "libresoc.v:173228.18-173228.106" - wire $not$libresoc.v:173228$11866_Y - attribute \src "libresoc.v:173234.18-173234.126" - wire $not$libresoc.v:173234$11872_Y - attribute \src "libresoc.v:173245.17-173245.113" - wire width 5 $not$libresoc.v:173245$11883_Y - attribute \src "libresoc.v:173266.18-173266.136" - wire $not$libresoc.v:173266$11904_Y - attribute \src "libresoc.v:173233.18-173233.112" - wire $or$libresoc.v:173233$11871_Y - attribute \src "libresoc.v:173243.18-173243.122" - wire $or$libresoc.v:173243$11881_Y - attribute \src "libresoc.v:173244.18-173244.124" - wire $or$libresoc.v:173244$11882_Y - attribute \src "libresoc.v:173246.18-173246.155" - wire width 3 $or$libresoc.v:173246$11884_Y - attribute \src "libresoc.v:173247.18-173247.181" - wire width 5 $or$libresoc.v:173247$11885_Y - attribute \src "libresoc.v:173250.18-173250.120" - wire width 3 $or$libresoc.v:173250$11888_Y - attribute \src "libresoc.v:173256.17-173256.117" - wire width 5 $or$libresoc.v:173256$11894_Y - attribute \src "libresoc.v:173262.17-173262.104" - wire $reduce_and$libresoc.v:173262$11900_Y - attribute \src "libresoc.v:173227.18-173227.106" - wire $reduce_or$libresoc.v:173227$11865_Y - attribute \src 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\src "libresoc.v:176969.3-177006.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 + attribute \src "libresoc.v:176969.3-177006.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 + attribute \src "libresoc.v:176969.3-177006.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 + attribute \src "libresoc.v:176969.3-177006.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 + attribute \src "libresoc.v:176969.3-177006.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 + attribute \src "libresoc.v:177007.3-177028.6" + wire width 64 $2\data_r0__o$next[63:0]$12424 + attribute \src "libresoc.v:177007.3-177028.6" + wire $2\data_r0__o_ok$next[0:0]$12425 + attribute \src "libresoc.v:177029.3-177050.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12432 + attribute \src "libresoc.v:177029.3-177050.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12433 + attribute \src "libresoc.v:177051.3-177072.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12440 + attribute \src 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attribute \src "libresoc.v:176648.19-176648.127" + wire $and$libresoc.v:176648$12253_Y + attribute \src "libresoc.v:176649.19-176649.127" + wire $and$libresoc.v:176649$12254_Y + attribute \src "libresoc.v:176650.19-176650.127" + wire $and$libresoc.v:176650$12255_Y + attribute \src "libresoc.v:176652.18-176652.98" + wire $and$libresoc.v:176652$12257_Y + attribute \src "libresoc.v:176654.18-176654.100" + wire $and$libresoc.v:176654$12259_Y + attribute \src "libresoc.v:176655.18-176655.149" + wire width 3 $and$libresoc.v:176655$12260_Y + attribute \src "libresoc.v:176657.18-176657.119" + wire width 3 $and$libresoc.v:176657$12262_Y + attribute \src "libresoc.v:176660.17-176660.123" + wire $and$libresoc.v:176660$12265_Y + attribute \src "libresoc.v:176661.18-176661.116" + wire $and$libresoc.v:176661$12266_Y + attribute \src "libresoc.v:176666.18-176666.113" + wire $and$libresoc.v:176666$12271_Y + attribute \src "libresoc.v:176667.18-176667.125" + wire width 3 $and$libresoc.v:176667$12272_Y + attribute \src "libresoc.v:176669.18-176669.112" + wire $and$libresoc.v:176669$12274_Y + attribute \src "libresoc.v:176671.18-176671.132" + wire $and$libresoc.v:176671$12276_Y + attribute \src "libresoc.v:176672.18-176672.132" + wire $and$libresoc.v:176672$12277_Y + attribute \src "libresoc.v:176673.18-176673.117" + wire $and$libresoc.v:176673$12278_Y + attribute \src "libresoc.v:176679.18-176679.136" + wire $and$libresoc.v:176679$12284_Y + attribute \src "libresoc.v:176680.18-176680.124" + wire width 3 $and$libresoc.v:176680$12285_Y + attribute \src "libresoc.v:176682.18-176682.116" + wire $and$libresoc.v:176682$12287_Y + attribute \src "libresoc.v:176683.18-176683.119" + wire $and$libresoc.v:176683$12288_Y + attribute \src "libresoc.v:176684.18-176684.121" + wire $and$libresoc.v:176684$12289_Y + attribute \src "libresoc.v:176694.18-176694.140" + wire $and$libresoc.v:176694$12299_Y + attribute \src "libresoc.v:176695.18-176695.138" + wire $and$libresoc.v:176695$12300_Y + attribute \src "libresoc.v:176696.18-176696.171" + wire width 5 $and$libresoc.v:176696$12301_Y + attribute \src "libresoc.v:176698.18-176698.129" + wire width 5 $and$libresoc.v:176698$12303_Y + attribute \src "libresoc.v:176668.18-176668.113" + wire $eq$libresoc.v:176668$12273_Y + attribute \src "libresoc.v:176670.18-176670.119" + wire $eq$libresoc.v:176670$12275_Y + attribute \src "libresoc.v:176640.19-176640.115" + wire width 5 $not$libresoc.v:176640$12245_Y + attribute \src "libresoc.v:176651.18-176651.97" + wire $not$libresoc.v:176651$12256_Y + attribute \src "libresoc.v:176653.18-176653.99" + wire $not$libresoc.v:176653$12258_Y + attribute \src "libresoc.v:176656.18-176656.113" + wire width 3 $not$libresoc.v:176656$12261_Y + attribute \src "libresoc.v:176659.18-176659.106" + wire $not$libresoc.v:176659$12264_Y + attribute \src "libresoc.v:176665.18-176665.126" + wire $not$libresoc.v:176665$12270_Y + attribute \src "libresoc.v:176676.17-176676.113" + wire width 5 $not$libresoc.v:176676$12281_Y + attribute \src "libresoc.v:176697.18-176697.136" + wire $not$libresoc.v:176697$12302_Y + attribute \src "libresoc.v:176664.18-176664.112" + wire $or$libresoc.v:176664$12269_Y + attribute \src "libresoc.v:176674.18-176674.122" + wire $or$libresoc.v:176674$12279_Y + attribute \src "libresoc.v:176675.18-176675.124" + wire $or$libresoc.v:176675$12280_Y + attribute \src "libresoc.v:176677.18-176677.155" + wire width 3 $or$libresoc.v:176677$12282_Y + attribute \src "libresoc.v:176678.18-176678.181" + wire width 5 $or$libresoc.v:176678$12283_Y + attribute \src "libresoc.v:176681.18-176681.120" + wire width 3 $or$libresoc.v:176681$12286_Y + attribute \src "libresoc.v:176687.17-176687.117" + wire width 5 $or$libresoc.v:176687$12292_Y + attribute \src "libresoc.v:176693.17-176693.104" + wire $reduce_and$libresoc.v:176693$12298_Y + attribute \src "libresoc.v:176658.18-176658.106" + wire $reduce_or$libresoc.v:176658$12263_Y + attribute \src "libresoc.v:176662.18-176662.113" + wire $reduce_or$libresoc.v:176662$12267_Y + attribute \src "libresoc.v:176663.18-176663.112" + wire $reduce_or$libresoc.v:176663$12268_Y + attribute \src "libresoc.v:176685.18-176685.165" + wire $ternary$libresoc.v:176685$12290_Y + attribute \src "libresoc.v:176686.18-176686.182" + wire width 64 $ternary$libresoc.v:176686$12291_Y + attribute \src "libresoc.v:176688.18-176688.118" + wire width 64 $ternary$libresoc.v:176688$12293_Y + attribute \src "libresoc.v:176689.18-176689.115" + wire width 64 $ternary$libresoc.v:176689$12294_Y + attribute \src "libresoc.v:176690.18-176690.118" + wire width 64 $ternary$libresoc.v:176690$12295_Y + attribute \src "libresoc.v:176691.18-176691.118" + wire $ternary$libresoc.v:176691$12296_Y + attribute \src "libresoc.v:176692.18-176692.118" + wire width 2 $ternary$libresoc.v:176692$12297_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -360428,13 +368366,13 @@ module \shiftrot0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 \alu_shift_rot0_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire \alu_shift_rot0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_shift_rot0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_shift_rot0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_shift_rot0_p_ready_o @@ -360566,6 +368504,10 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 7 \alu_shift_rot0_sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__is_32bit$next @@ -360601,7 +368543,7 @@ module \shiftrot0 wire \alu_shift_rot0_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_shift_rot0_sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_shift_rot0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_shift_rot0_xer_ca$1 @@ -360615,32 +368557,32 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 36 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 35 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 37 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 18 \cu_busy_o + wire output 20 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 17 \cu_issue_i + wire input 19 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 21 \cu_rd__go_i + wire width 5 input 23 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 20 \cu_rd__rel_o + wire width 5 output 22 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 19 \cu_rdmaskn_i + wire width 5 input 21 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 29 \cu_wr__go_i + wire width 3 input 31 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 28 \cu_wr__rel_o + wire width 3 output 30 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -360668,15 +368610,15 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r2__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o + wire width 64 output 32 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o + wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o - attribute \src "libresoc.v:172587.7-172587.15" + wire width 2 output 36 \dest3_o + attribute \src "libresoc.v:176012.7-176012.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -360701,21 +368643,21 @@ module \shiftrot0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_shift_rot0__fn_unit + wire width 12 input 3 \oper_i_alu_shift_rot0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__data + wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_shift_rot0__imm_data__ok + wire input 5 \oper_i_alu_shift_rot0__imm_data__ok attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry + wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_shift_rot0__input_cr + wire input 14 \oper_i_alu_shift_rot0__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \oper_i_alu_shift_rot0__insn + wire width 32 input 18 \oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360791,25 +368733,27 @@ module \shiftrot0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type + wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_shift_rot0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_shift_rot0__is_32bit + wire input 16 \oper_i_alu_shift_rot0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_shift_rot0__is_signed + wire input 17 \oper_i_alu_shift_rot0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_shift_rot0__oe__oe + wire input 8 \oper_i_alu_shift_rot0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_shift_rot0__oe__ok + wire input 9 \oper_i_alu_shift_rot0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_shift_rot0__output_carry + wire input 13 \oper_i_alu_shift_rot0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_shift_rot0__output_cr + wire input 15 \oper_i_alu_shift_rot0__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_shift_rot0__rc__ok + wire input 7 \oper_i_alu_shift_rot0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_shift_rot0__rc__rc + wire input 6 \oper_i_alu_shift_rot0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_shift_rot0__write_cr0 + wire input 10 \oper_i_alu_shift_rot0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -360853,15 +368797,15 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 22 \src1_i + wire width 64 input 24 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 23 \src2_i + wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src3_i + wire width 64 input 26 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 25 \src4_i + wire input 27 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 26 \src5_i + wire width 2 input 28 \src5_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 5 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -360898,10 +368842,10 @@ module \shiftrot0 wire \src_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:173210$11848 + cell $and $and$libresoc.v:176641$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360909,10 +368853,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:173210$11848_Y + connect \Y $and$libresoc.v:176641$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:173211$11849 + cell $and $and$libresoc.v:176642$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360920,10 +368864,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:173211$11849_Y + connect \Y $and$libresoc.v:176642$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:173212$11850 + cell $and $and$libresoc.v:176643$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360931,10 +368875,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:173212$11850_Y + connect \Y $and$libresoc.v:176643$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:173213$11851 + cell $and $and$libresoc.v:176644$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360942,10 +368886,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:173213$11851_Y + connect \Y $and$libresoc.v:176644$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:173214$11852 + cell $and $and$libresoc.v:176645$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360953,10 +368897,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:173214$11852_Y + connect \Y $and$libresoc.v:176645$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:173215$11853 + cell $and $and$libresoc.v:176646$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360964,10 +368908,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:173215$11853_Y + connect \Y $and$libresoc.v:176646$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:173216$11854 + cell $and $and$libresoc.v:176647$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360975,10 +368919,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:173216$11854_Y + connect \Y $and$libresoc.v:176647$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:173217$11855 + cell $and $and$libresoc.v:176648$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360986,10 +368930,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:173217$11855_Y + connect \Y $and$libresoc.v:176648$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:173218$11856 + cell $and $and$libresoc.v:176649$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -360997,10 +368941,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:173218$11856_Y + connect \Y $and$libresoc.v:176649$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:173219$11857 + cell $and $and$libresoc.v:176650$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361008,10 +368952,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:173219$11857_Y + connect \Y $and$libresoc.v:176650$12255_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:173221$11859 + cell $and $and$libresoc.v:176652$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361019,10 +368963,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:173221$11859_Y + connect \Y $and$libresoc.v:176652$12257_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:173223$11861 + cell $and $and$libresoc.v:176654$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361030,10 +368974,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:173223$11861_Y + connect \Y $and$libresoc.v:176654$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:173224$11862 + cell $and $and$libresoc.v:176655$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361041,10 +368985,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:173224$11862_Y + connect \Y $and$libresoc.v:176655$12260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:173226$11864 + cell $and $and$libresoc.v:176657$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361052,10 +368996,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:173226$11864_Y + connect \Y $and$libresoc.v:176657$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:173229$11867 + cell $and $and$libresoc.v:176660$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361063,10 +369007,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:173229$11867_Y + connect \Y $and$libresoc.v:176660$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:173230$11868 + cell $and $and$libresoc.v:176661$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361074,10 +369018,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:173230$11868_Y + connect \Y $and$libresoc.v:176661$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:173235$11873 + cell $and $and$libresoc.v:176666$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361085,10 +369029,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:173235$11873_Y + connect \Y $and$libresoc.v:176666$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:173236$11874 + cell $and $and$libresoc.v:176667$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361096,10 +369040,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:173236$11874_Y + connect \Y $and$libresoc.v:176667$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:173238$11876 + cell $and $and$libresoc.v:176669$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361107,10 +369051,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:173238$11876_Y + connect \Y $and$libresoc.v:176669$12274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:173240$11878 + cell $and $and$libresoc.v:176671$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361118,10 +369062,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:173240$11878_Y + connect \Y $and$libresoc.v:176671$12276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:173241$11879 + cell $and $and$libresoc.v:176672$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361129,10 +369073,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:173241$11879_Y + connect \Y $and$libresoc.v:176672$12277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:173242$11880 + cell $and $and$libresoc.v:176673$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361140,10 +369084,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:173242$11880_Y + connect \Y $and$libresoc.v:176673$12278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:173248$11886 + cell $and $and$libresoc.v:176679$12284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361151,10 +369095,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:173248$11886_Y + connect \Y $and$libresoc.v:176679$12284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:173249$11887 + cell $and $and$libresoc.v:176680$12285 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361162,10 +369106,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:173249$11887_Y + connect \Y $and$libresoc.v:176680$12285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:173251$11889 + cell $and $and$libresoc.v:176682$12287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361173,10 +369117,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:173251$11889_Y + connect \Y $and$libresoc.v:176682$12287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:173252$11890 + cell $and $and$libresoc.v:176683$12288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361184,10 +369128,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:173252$11890_Y + connect \Y $and$libresoc.v:176683$12288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:173253$11891 + cell $and $and$libresoc.v:176684$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361195,10 +369139,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:173253$11891_Y + connect \Y $and$libresoc.v:176684$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:173263$11901 + cell $and $and$libresoc.v:176694$12299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361206,10 +369150,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:173263$11901_Y + connect \Y $and$libresoc.v:176694$12299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:173264$11902 + cell $and $and$libresoc.v:176695$12300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361217,10 +369161,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:173264$11902_Y + connect \Y $and$libresoc.v:176695$12300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:173265$11903 + cell $and $and$libresoc.v:176696$12301 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -361228,10 +369172,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:173265$11903_Y + connect \Y $and$libresoc.v:176696$12301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:173267$11905 + cell $and $and$libresoc.v:176698$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -361239,10 +369183,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:173267$11905_Y + connect \Y $and$libresoc.v:176698$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:173237$11875 + cell $eq $eq$libresoc.v:176668$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361250,10 +369194,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:173237$11875_Y + connect \Y $eq$libresoc.v:176668$12273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:173239$11877 + cell $eq $eq$libresoc.v:176670$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361261,74 +369205,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:173239$11877_Y + connect \Y $eq$libresoc.v:176670$12275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:173209$11847 + cell $not $not$libresoc.v:176640$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:173209$11847_Y + connect \Y $not$libresoc.v:176640$12245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:173220$11858 + cell $not $not$libresoc.v:176651$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:173220$11858_Y + connect \Y $not$libresoc.v:176651$12256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:173222$11860 + cell $not $not$libresoc.v:176653$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:173222$11860_Y + connect \Y $not$libresoc.v:176653$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:173225$11863 + cell $not $not$libresoc.v:176656$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:173225$11863_Y + connect \Y $not$libresoc.v:176656$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:173228$11866 + cell $not $not$libresoc.v:176659$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:173228$11866_Y + connect \Y $not$libresoc.v:176659$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:173234$11872 + cell $not $not$libresoc.v:176665$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:173234$11872_Y + connect \Y $not$libresoc.v:176665$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:173245$11883 + cell $not $not$libresoc.v:176676$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:173245$11883_Y + connect \Y $not$libresoc.v:176676$12281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:173266$11904 + cell $not $not$libresoc.v:176697$12302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:173266$11904_Y + connect \Y $not$libresoc.v:176697$12302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:173233$11871 + cell $or $or$libresoc.v:176664$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361336,10 +369280,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:173233$11871_Y + connect \Y $or$libresoc.v:176664$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:173243$11881 + cell $or $or$libresoc.v:176674$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361347,10 +369291,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:173243$11881_Y + connect \Y $or$libresoc.v:176674$12279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:173244$11882 + cell $or $or$libresoc.v:176675$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -361358,10 +369302,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:173244$11882_Y + connect \Y $or$libresoc.v:176675$12280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:173246$11884 + cell $or $or$libresoc.v:176677$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361369,10 +369313,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:173246$11884_Y + connect \Y $or$libresoc.v:176677$12282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:173247$11885 + cell $or $or$libresoc.v:176678$12283 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -361380,10 +369324,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:173247$11885_Y + connect \Y $or$libresoc.v:176678$12283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:173250$11888 + cell $or $or$libresoc.v:176681$12286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -361391,10 +369335,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:173250$11888_Y + connect \Y $or$libresoc.v:176681$12286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:173256$11894 + cell $or $or$libresoc.v:176687$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -361402,99 +369346,99 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:173256$11894_Y + connect \Y $or$libresoc.v:176687$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:173262$11900 + cell $reduce_and $reduce_and$libresoc.v:176693$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:173262$11900_Y + connect \Y $reduce_and$libresoc.v:176693$12298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:173227$11865 + cell $reduce_or $reduce_or$libresoc.v:176658$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:173227$11865_Y + connect \Y $reduce_or$libresoc.v:176658$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:173231$11869 + cell $reduce_or $reduce_or$libresoc.v:176662$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:173231$11869_Y + connect \Y $reduce_or$libresoc.v:176662$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:173232$11870 + cell $reduce_or $reduce_or$libresoc.v:176663$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:173232$11870_Y + connect \Y $reduce_or$libresoc.v:176663$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:173254$11892 + cell $mux $ternary$libresoc.v:176685$12290 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:173254$11892_Y + connect \Y $ternary$libresoc.v:176685$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:173255$11893 + cell $mux $ternary$libresoc.v:176686$12291 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:173255$11893_Y + connect \Y $ternary$libresoc.v:176686$12291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:173257$11895 + cell $mux $ternary$libresoc.v:176688$12293 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:173257$11895_Y + connect \Y $ternary$libresoc.v:176688$12293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:173258$11896 + cell $mux $ternary$libresoc.v:176689$12294 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:173258$11896_Y + connect \Y $ternary$libresoc.v:176689$12294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:173259$11897 + cell $mux $ternary$libresoc.v:176690$12295 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:173259$11897_Y + connect \Y $ternary$libresoc.v:176690$12295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:173260$11898 + cell $mux $ternary$libresoc.v:176691$12296 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:173260$11898_Y + connect \Y $ternary$libresoc.v:176691$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:173261$11899 + cell $mux $ternary$libresoc.v:176692$12297 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:173261$11899_Y + connect \Y $ternary$libresoc.v:176692$12297_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173352.15-173358.4" - cell \alu_l$122 \alu_l + attribute \src "libresoc.v:176785.15-176791.4" + cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -361502,7 +369446,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:173359.18-173393.4" + attribute \src "libresoc.v:176792.18-176827.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -361524,6 +369468,7 @@ module \shiftrot0 connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr connect \sr_op__insn \alu_shift_rot0_sr_op__insn connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe @@ -361539,8 +369484,8 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:173394.16-173400.4" - cell \alui_l$121 \alui_l + attribute \src "libresoc.v:176828.16-176834.4" + cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -361548,8 +369493,8 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:173401.15-173407.4" - cell \opc_l$117 \opc_l + attribute \src "libresoc.v:176835.15-176841.4" + cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -361557,8 +369502,8 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:173408.15-173414.4" - cell \req_l$118 \req_l + attribute \src "libresoc.v:176842.15-176848.4" + cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -361566,8 +369511,8 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:173415.15-173421.4" - cell \rok_l$120 \rok_l + attribute \src "libresoc.v:176849.15-176855.4" + cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -361575,668 +369520,683 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:173422.15-173427.4" - cell \rst_l$119 \rst_l + attribute \src "libresoc.v:176856.15-176861.4" + cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:173428.15-173434.4" - cell \src_l$116 \src_l + attribute \src "libresoc.v:176862.15-176868.4" + cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:172587.7-172587.20" - process $proc$libresoc.v:172587$12069 + attribute \src "libresoc.v:176012.7-176012.20" + process $proc$libresoc.v:176012$12470 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172709.7-172709.24" - process $proc$libresoc.v:172709$12070 + attribute \src "libresoc.v:176134.7-176134.24" + process $proc$libresoc.v:176134$12471 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:172719.7-172719.26" - process $proc$libresoc.v:172719$12071 + attribute \src "libresoc.v:176144.7-176144.26" + process $proc$libresoc.v:176144$12472 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:172727.7-172727.25" - process $proc$libresoc.v:172727$12072 + attribute \src "libresoc.v:176152.7-176152.25" + process $proc$libresoc.v:176152$12473 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:172768.14-172768.53" - process $proc$libresoc.v:172768$12073 + attribute \src "libresoc.v:176193.14-176193.53" + process $proc$libresoc.v:176193$12474 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] end - attribute \src "libresoc.v:172772.14-172772.73" - process $proc$libresoc.v:172772$12074 + attribute \src "libresoc.v:176197.14-176197.73" + process $proc$libresoc.v:176197$12475 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:172776.7-172776.48" - process $proc$libresoc.v:172776$12075 + attribute \src "libresoc.v:176201.7-176201.48" + process $proc$libresoc.v:176201$12476 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:172784.13-172784.53" - process $proc$libresoc.v:172784$12076 + attribute \src "libresoc.v:176209.13-176209.53" + process $proc$libresoc.v:176209$12477 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:172788.7-172788.44" - process $proc$libresoc.v:172788$12077 + attribute \src "libresoc.v:176213.7-176213.44" + process $proc$libresoc.v:176213$12478 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:172792.14-172792.48" - process $proc$libresoc.v:172792$12078 + attribute \src "libresoc.v:176217.14-176217.48" + process $proc$libresoc.v:176217$12479 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:172870.13-172870.52" - process $proc$libresoc.v:172870$12079 + attribute \src "libresoc.v:176295.13-176295.52" + process $proc$libresoc.v:176295$12480 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:172874.7-172874.44" - process $proc$libresoc.v:172874$12080 + attribute \src "libresoc.v:176299.7-176299.45" + process $proc$libresoc.v:176299$12481 + assign { } { } + assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:176303.7-176303.44" + process $proc$libresoc.v:176303$12482 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:172878.7-172878.45" - process $proc$libresoc.v:172878$12081 + attribute \src "libresoc.v:176307.7-176307.45" + process $proc$libresoc.v:176307$12483 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:172882.7-172882.42" - process $proc$libresoc.v:172882$12082 + attribute \src "libresoc.v:176311.7-176311.42" + process $proc$libresoc.v:176311$12484 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:172886.7-172886.42" - process $proc$libresoc.v:172886$12083 + attribute \src "libresoc.v:176315.7-176315.42" + process $proc$libresoc.v:176315$12485 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:172890.7-172890.48" - process $proc$libresoc.v:172890$12084 + attribute \src "libresoc.v:176319.7-176319.48" + process $proc$libresoc.v:176319$12486 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:172894.7-172894.45" - process $proc$libresoc.v:172894$12085 + attribute \src "libresoc.v:176323.7-176323.45" + process $proc$libresoc.v:176323$12487 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:172898.7-172898.42" - process $proc$libresoc.v:172898$12086 + attribute \src "libresoc.v:176327.7-176327.42" + process $proc$libresoc.v:176327$12488 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:172902.7-172902.42" - process $proc$libresoc.v:172902$12087 + attribute \src "libresoc.v:176331.7-176331.42" + process $proc$libresoc.v:176331$12489 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:172906.7-172906.45" - process $proc$libresoc.v:172906$12088 + attribute \src "libresoc.v:176335.7-176335.45" + process $proc$libresoc.v:176335$12490 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:172918.7-172918.27" - process $proc$libresoc.v:172918$12089 + attribute \src "libresoc.v:176347.7-176347.27" + process $proc$libresoc.v:176347$12491 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:172952.14-172952.47" - process $proc$libresoc.v:172952$12090 + attribute \src "libresoc.v:176381.14-176381.47" + process $proc$libresoc.v:176381$12492 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:172956.7-172956.27" - process $proc$libresoc.v:172956$12091 + attribute \src "libresoc.v:176385.7-176385.27" + process $proc$libresoc.v:176385$12493 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:172960.13-172960.33" - process $proc$libresoc.v:172960$12092 + attribute \src "libresoc.v:176389.13-176389.33" + process $proc$libresoc.v:176389$12494 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:172964.7-172964.30" - process $proc$libresoc.v:172964$12093 + attribute \src "libresoc.v:176393.7-176393.30" + process $proc$libresoc.v:176393$12495 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:172968.13-172968.35" - process $proc$libresoc.v:172968$12094 + attribute \src "libresoc.v:176397.13-176397.35" + process $proc$libresoc.v:176397$12496 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:172972.7-172972.32" - process $proc$libresoc.v:172972$12095 + attribute \src "libresoc.v:176401.7-176401.32" + process $proc$libresoc.v:176401$12497 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:172989.7-172989.25" - process $proc$libresoc.v:172989$12096 + attribute \src "libresoc.v:176418.7-176418.25" + process $proc$libresoc.v:176418$12498 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:172993.7-172993.25" - process $proc$libresoc.v:172993$12097 + attribute \src "libresoc.v:176422.7-176422.25" + process $proc$libresoc.v:176422$12499 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:173120.13-173120.30" - process $proc$libresoc.v:173120$12098 + attribute \src "libresoc.v:176551.13-176551.30" + process $proc$libresoc.v:176551$12500 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:173128.13-173128.31" - process $proc$libresoc.v:173128$12099 + attribute \src "libresoc.v:176559.13-176559.31" + process $proc$libresoc.v:176559$12501 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:173132.13-173132.31" - process $proc$libresoc.v:173132$12100 + attribute \src "libresoc.v:176563.13-176563.31" + process $proc$libresoc.v:176563$12502 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:173144.7-173144.26" - process $proc$libresoc.v:173144$12101 + attribute \src "libresoc.v:176575.7-176575.26" + process $proc$libresoc.v:176575$12503 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:173148.7-173148.26" - process $proc$libresoc.v:173148$12102 + attribute \src "libresoc.v:176579.7-176579.26" + process $proc$libresoc.v:176579$12504 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:173152.7-173152.25" - process $proc$libresoc.v:173152$12103 + attribute \src "libresoc.v:176583.7-176583.25" + process $proc$libresoc.v:176583$12505 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:173156.7-173156.25" - process $proc$libresoc.v:173156$12104 + attribute \src "libresoc.v:176587.7-176587.25" + process $proc$libresoc.v:176587$12506 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:173174.13-173174.32" - process $proc$libresoc.v:173174$12105 + attribute \src "libresoc.v:176605.13-176605.32" + process $proc$libresoc.v:176605$12507 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:173178.13-173178.32" - process $proc$libresoc.v:173178$12106 + attribute \src "libresoc.v:176609.13-176609.32" + process $proc$libresoc.v:176609$12508 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:173184.14-173184.43" - process $proc$libresoc.v:173184$12107 + attribute \src "libresoc.v:176615.14-176615.43" + process $proc$libresoc.v:176615$12509 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:173188.14-173188.43" - process $proc$libresoc.v:173188$12108 + attribute \src "libresoc.v:176619.14-176619.43" + process $proc$libresoc.v:176619$12510 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:173192.14-173192.43" - process $proc$libresoc.v:173192$12109 + attribute \src "libresoc.v:176623.14-176623.43" + process $proc$libresoc.v:176623$12511 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:173196.7-173196.20" - process $proc$libresoc.v:173196$12110 + attribute \src "libresoc.v:176627.7-176627.20" + process $proc$libresoc.v:176627$12512 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:173200.13-173200.26" - process $proc$libresoc.v:173200$12111 + attribute \src "libresoc.v:176631.13-176631.26" + process $proc$libresoc.v:176631$12513 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:173268.3-173269.39" - process $proc$libresoc.v:173268$11906 + attribute \src "libresoc.v:176699.3-176700.39" + process $proc$libresoc.v:176699$12304 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:173270.3-173271.43" - process $proc$libresoc.v:173270$11907 + attribute \src "libresoc.v:176701.3-176702.43" + process $proc$libresoc.v:176701$12305 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:173272.3-173273.29" - process $proc$libresoc.v:173272$11908 + attribute \src "libresoc.v:176703.3-176704.29" + process $proc$libresoc.v:176703$12306 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:173274.3-173275.29" - process $proc$libresoc.v:173274$11909 + attribute \src "libresoc.v:176705.3-176706.29" + process $proc$libresoc.v:176705$12307 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:173276.3-173277.29" - process $proc$libresoc.v:173276$11910 + attribute \src "libresoc.v:176707.3-176708.29" + process $proc$libresoc.v:176707$12308 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:173278.3-173279.29" - process $proc$libresoc.v:173278$11911 + attribute \src "libresoc.v:176709.3-176710.29" + process $proc$libresoc.v:176709$12309 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:173280.3-173281.29" - process $proc$libresoc.v:173280$11912 + attribute \src "libresoc.v:176711.3-176712.29" + process $proc$libresoc.v:176711$12310 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:173282.3-173283.47" - process $proc$libresoc.v:173282$11913 + attribute \src "libresoc.v:176713.3-176714.47" + process $proc$libresoc.v:176713$12311 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:173284.3-173285.53" - process $proc$libresoc.v:173284$11914 + attribute \src "libresoc.v:176715.3-176716.53" + process $proc$libresoc.v:176715$12312 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:173286.3-173287.43" - process $proc$libresoc.v:173286$11915 + attribute \src "libresoc.v:176717.3-176718.43" + process $proc$libresoc.v:176717$12313 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:173288.3-173289.49" - process $proc$libresoc.v:173288$11916 + attribute \src "libresoc.v:176719.3-176720.49" + process $proc$libresoc.v:176719$12314 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:173290.3-173291.37" - process $proc$libresoc.v:173290$11917 + attribute \src "libresoc.v:176721.3-176722.37" + process $proc$libresoc.v:176721$12315 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:173292.3-173293.43" - process $proc$libresoc.v:173292$11918 + attribute \src "libresoc.v:176723.3-176724.43" + process $proc$libresoc.v:176723$12316 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:173294.3-173295.79" - process $proc$libresoc.v:173294$11919 + attribute \src "libresoc.v:176725.3-176726.79" + process $proc$libresoc.v:176725$12317 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:173296.3-173297.75" - process $proc$libresoc.v:173296$11920 + attribute \src "libresoc.v:176727.3-176728.75" + process $proc$libresoc.v:176727$12318 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] end - attribute \src "libresoc.v:173298.3-173299.89" - process $proc$libresoc.v:173298$11921 + attribute \src "libresoc.v:176729.3-176730.89" + process $proc$libresoc.v:176729$12319 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:173300.3-173301.85" - process $proc$libresoc.v:173300$11922 + attribute \src "libresoc.v:176731.3-176732.85" + process $proc$libresoc.v:176731$12320 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:173302.3-173303.73" - process $proc$libresoc.v:173302$11923 + attribute \src "libresoc.v:176733.3-176734.73" + process $proc$libresoc.v:176733$12321 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:173304.3-173305.73" - process $proc$libresoc.v:173304$11924 + attribute \src "libresoc.v:176735.3-176736.73" + process $proc$libresoc.v:176735$12322 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:173306.3-173307.73" - process $proc$libresoc.v:173306$11925 + attribute \src "libresoc.v:176737.3-176738.73" + process $proc$libresoc.v:176737$12323 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:173308.3-173309.73" - process $proc$libresoc.v:173308$11926 + attribute \src "libresoc.v:176739.3-176740.73" + process $proc$libresoc.v:176739$12324 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:173310.3-173311.79" - process $proc$libresoc.v:173310$11927 + attribute \src "libresoc.v:176741.3-176742.79" + process $proc$libresoc.v:176741$12325 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:173312.3-173313.83" - process $proc$libresoc.v:173312$11928 + attribute \src "libresoc.v:176743.3-176744.79" + process $proc$libresoc.v:176743$12326 + assign { } { } + assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:176745.3-176746.83" + process $proc$libresoc.v:176745$12327 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:173314.3-173315.85" - process $proc$libresoc.v:173314$11929 + attribute \src "libresoc.v:176747.3-176748.85" + process $proc$libresoc.v:176747$12328 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:173316.3-173317.77" - process $proc$libresoc.v:173316$11930 + attribute \src "libresoc.v:176749.3-176750.77" + process $proc$libresoc.v:176749$12329 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:173318.3-173319.79" - process $proc$libresoc.v:173318$11931 + attribute \src "libresoc.v:176751.3-176752.79" + process $proc$libresoc.v:176751$12330 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:173320.3-173321.77" - process $proc$libresoc.v:173320$11932 + attribute \src "libresoc.v:176753.3-176754.77" + process $proc$libresoc.v:176753$12331 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:173322.3-173323.79" - process $proc$libresoc.v:173322$11933 + attribute \src "libresoc.v:176755.3-176756.79" + process $proc$libresoc.v:176755$12332 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:173324.3-173325.69" - process $proc$libresoc.v:173324$11934 + attribute \src "libresoc.v:176757.3-176758.69" + process $proc$libresoc.v:176757$12333 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:173326.3-173327.39" - process $proc$libresoc.v:173326$11935 + attribute \src "libresoc.v:176759.3-176760.39" + process $proc$libresoc.v:176759$12334 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:173328.3-173329.39" - process $proc$libresoc.v:173328$11936 + attribute \src "libresoc.v:176761.3-176762.39" + process $proc$libresoc.v:176761$12335 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:173330.3-173331.39" - process $proc$libresoc.v:173330$11937 + attribute \src "libresoc.v:176763.3-176764.39" + process $proc$libresoc.v:176763$12336 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:173332.3-173333.39" - process $proc$libresoc.v:173332$11938 + attribute \src "libresoc.v:176765.3-176766.39" + process $proc$libresoc.v:176765$12337 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:173334.3-173335.39" - process $proc$libresoc.v:173334$11939 + attribute \src "libresoc.v:176767.3-176768.39" + process $proc$libresoc.v:176767$12338 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:173336.3-173337.39" - process $proc$libresoc.v:173336$11940 + attribute \src "libresoc.v:176769.3-176770.39" + process $proc$libresoc.v:176769$12339 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:173338.3-173339.39" - process $proc$libresoc.v:173338$11941 + attribute \src "libresoc.v:176771.3-176772.39" + process $proc$libresoc.v:176771$12340 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:173340.3-173341.39" - process $proc$libresoc.v:173340$11942 + attribute \src "libresoc.v:176773.3-176774.39" + process $proc$libresoc.v:176773$12341 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:173342.3-173343.41" - process $proc$libresoc.v:173342$11943 + attribute \src "libresoc.v:176775.3-176776.41" + process $proc$libresoc.v:176775$12342 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:173344.3-173345.41" - process $proc$libresoc.v:173344$11944 + attribute \src "libresoc.v:176777.3-176778.41" + process $proc$libresoc.v:176777$12343 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:173346.3-173347.37" - process $proc$libresoc.v:173346$11945 + attribute \src "libresoc.v:176779.3-176780.37" + process $proc$libresoc.v:176779$12344 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:173348.3-173349.46" - process $proc$libresoc.v:173348$11946 + attribute \src "libresoc.v:176781.3-176782.46" + process $proc$libresoc.v:176781$12345 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:173350.3-173351.25" - process $proc$libresoc.v:173350$11947 + attribute \src "libresoc.v:176783.3-176784.25" + process $proc$libresoc.v:176783$12346 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:173435.3-173444.6" - process $proc$libresoc.v:173435$11948 + attribute \src "libresoc.v:176869.3-176878.6" + process $proc$libresoc.v:176869$12347 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:173436.5-173436.29" + attribute \src "libresoc.v:176870.5-176870.29" switch \initial - attribute \src "libresoc.v:173436.9-173436.17" + attribute \src "libresoc.v:176870.9-176870.17" case 1'1 case end @@ -362252,14 +370212,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:173445.3-173453.6" - process $proc$libresoc.v:173445$11949 + attribute \src "libresoc.v:176879.3-176887.6" + process $proc$libresoc.v:176879$12348 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$11950 $1\rok_l_s_rdok$next[0:0]$11951 - attribute \src "libresoc.v:173446.5-173446.29" + assign $0\rok_l_s_rdok$next[0:0]$12349 $1\rok_l_s_rdok$next[0:0]$12350 + attribute \src "libresoc.v:176880.5-176880.29" switch \initial - attribute \src "libresoc.v:173446.9-173446.17" + attribute \src "libresoc.v:176880.9-176880.17" case 1'1 case end @@ -362268,21 +370228,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$11951 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12350 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$11951 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12350 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$11950 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12349 end - attribute \src "libresoc.v:173454.3-173462.6" - process $proc$libresoc.v:173454$11952 + attribute \src "libresoc.v:176888.3-176896.6" + process $proc$libresoc.v:176888$12351 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$11953 $1\rok_l_r_rdok$next[0:0]$11954 - attribute \src "libresoc.v:173455.5-173455.29" + assign $0\rok_l_r_rdok$next[0:0]$12352 $1\rok_l_r_rdok$next[0:0]$12353 + attribute \src "libresoc.v:176889.5-176889.29" switch \initial - attribute \src "libresoc.v:173455.9-173455.17" + attribute \src "libresoc.v:176889.9-176889.17" case 1'1 case end @@ -362291,21 +370251,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$11954 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12353 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$11954 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12353 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$11953 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12352 end - attribute \src "libresoc.v:173463.3-173471.6" - process $proc$libresoc.v:173463$11955 + attribute \src "libresoc.v:176897.3-176905.6" + process $proc$libresoc.v:176897$12354 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$11956 $1\rst_l_s_rst$next[0:0]$11957 - attribute \src "libresoc.v:173464.5-173464.29" + assign $0\rst_l_s_rst$next[0:0]$12355 $1\rst_l_s_rst$next[0:0]$12356 + attribute \src "libresoc.v:176898.5-176898.29" switch \initial - attribute \src "libresoc.v:173464.9-173464.17" + attribute \src "libresoc.v:176898.9-176898.17" case 1'1 case end @@ -362314,21 +370274,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$11957 1'0 + assign $1\rst_l_s_rst$next[0:0]$12356 1'0 case - assign $1\rst_l_s_rst$next[0:0]$11957 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12356 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$11956 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12355 end - attribute \src "libresoc.v:173472.3-173480.6" - process $proc$libresoc.v:173472$11958 + attribute \src "libresoc.v:176906.3-176914.6" + process $proc$libresoc.v:176906$12357 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$11959 $1\rst_l_r_rst$next[0:0]$11960 - attribute \src "libresoc.v:173473.5-173473.29" + assign $0\rst_l_r_rst$next[0:0]$12358 $1\rst_l_r_rst$next[0:0]$12359 + attribute \src "libresoc.v:176907.5-176907.29" switch \initial - attribute \src "libresoc.v:173473.9-173473.17" + attribute \src "libresoc.v:176907.9-176907.17" case 1'1 case end @@ -362337,21 +370297,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$11960 1'1 + assign $1\rst_l_r_rst$next[0:0]$12359 1'1 case - assign $1\rst_l_r_rst$next[0:0]$11960 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12359 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$11959 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12358 end - attribute \src "libresoc.v:173481.3-173489.6" - process $proc$libresoc.v:173481$11961 + attribute \src "libresoc.v:176915.3-176923.6" + process $proc$libresoc.v:176915$12360 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$11962 $1\opc_l_s_opc$next[0:0]$11963 - attribute \src "libresoc.v:173482.5-173482.29" + assign $0\opc_l_s_opc$next[0:0]$12361 $1\opc_l_s_opc$next[0:0]$12362 + attribute \src "libresoc.v:176916.5-176916.29" switch \initial - attribute \src "libresoc.v:173482.9-173482.17" + attribute \src "libresoc.v:176916.9-176916.17" case 1'1 case end @@ -362360,21 +370320,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$11963 1'0 + assign $1\opc_l_s_opc$next[0:0]$12362 1'0 case - assign $1\opc_l_s_opc$next[0:0]$11963 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12362 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$11962 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12361 end - attribute \src "libresoc.v:173490.3-173498.6" - process $proc$libresoc.v:173490$11964 + attribute \src "libresoc.v:176924.3-176932.6" + process $proc$libresoc.v:176924$12363 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$11965 $1\opc_l_r_opc$next[0:0]$11966 - attribute \src "libresoc.v:173491.5-173491.29" + assign $0\opc_l_r_opc$next[0:0]$12364 $1\opc_l_r_opc$next[0:0]$12365 + attribute \src "libresoc.v:176925.5-176925.29" switch \initial - attribute \src "libresoc.v:173491.9-173491.17" + attribute \src "libresoc.v:176925.9-176925.17" case 1'1 case end @@ -362383,21 +370343,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$11966 1'1 + assign $1\opc_l_r_opc$next[0:0]$12365 1'1 case - assign $1\opc_l_r_opc$next[0:0]$11966 \req_done + assign $1\opc_l_r_opc$next[0:0]$12365 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$11965 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12364 end - attribute \src "libresoc.v:173499.3-173507.6" - process $proc$libresoc.v:173499$11967 + attribute \src "libresoc.v:176933.3-176941.6" + process $proc$libresoc.v:176933$12366 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$11968 $1\src_l_s_src$next[4:0]$11969 - attribute \src "libresoc.v:173500.5-173500.29" + assign $0\src_l_s_src$next[4:0]$12367 $1\src_l_s_src$next[4:0]$12368 + attribute \src "libresoc.v:176934.5-176934.29" switch \initial - attribute \src "libresoc.v:173500.9-173500.17" + attribute \src "libresoc.v:176934.9-176934.17" case 1'1 case end @@ -362406,21 +370366,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$11969 5'00000 + assign $1\src_l_s_src$next[4:0]$12368 5'00000 case - assign $1\src_l_s_src$next[4:0]$11969 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12368 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$11968 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12367 end - attribute \src "libresoc.v:173508.3-173516.6" - process $proc$libresoc.v:173508$11970 + attribute \src "libresoc.v:176942.3-176950.6" + process $proc$libresoc.v:176942$12369 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$11971 $1\src_l_r_src$next[4:0]$11972 - attribute \src "libresoc.v:173509.5-173509.29" + assign $0\src_l_r_src$next[4:0]$12370 $1\src_l_r_src$next[4:0]$12371 + attribute \src "libresoc.v:176943.5-176943.29" switch \initial - attribute \src "libresoc.v:173509.9-173509.17" + attribute \src "libresoc.v:176943.9-176943.17" case 1'1 case end @@ -362429,21 +370389,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$11972 5'11111 + assign $1\src_l_r_src$next[4:0]$12371 5'11111 case - assign $1\src_l_r_src$next[4:0]$11972 \reset_r + assign $1\src_l_r_src$next[4:0]$12371 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$11971 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12370 end - attribute \src "libresoc.v:173517.3-173525.6" - process $proc$libresoc.v:173517$11973 + attribute \src "libresoc.v:176951.3-176959.6" + process $proc$libresoc.v:176951$12372 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$11974 $1\req_l_s_req$next[2:0]$11975 - attribute \src "libresoc.v:173518.5-173518.29" + assign $0\req_l_s_req$next[2:0]$12373 $1\req_l_s_req$next[2:0]$12374 + attribute \src "libresoc.v:176952.5-176952.29" switch \initial - attribute \src "libresoc.v:173518.9-173518.17" + attribute \src "libresoc.v:176952.9-176952.17" case 1'1 case end @@ -362452,21 +370412,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$11975 3'000 + assign $1\req_l_s_req$next[2:0]$12374 3'000 case - assign $1\req_l_s_req$next[2:0]$11975 \$66 + assign $1\req_l_s_req$next[2:0]$12374 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$11974 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12373 end - attribute \src "libresoc.v:173526.3-173534.6" - process $proc$libresoc.v:173526$11976 + attribute \src "libresoc.v:176960.3-176968.6" + process $proc$libresoc.v:176960$12375 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$11977 $1\req_l_r_req$next[2:0]$11978 - attribute \src "libresoc.v:173527.5-173527.29" + assign $0\req_l_r_req$next[2:0]$12376 $1\req_l_r_req$next[2:0]$12377 + attribute \src "libresoc.v:176961.5-176961.29" switch \initial - attribute \src "libresoc.v:173527.9-173527.17" + attribute \src "libresoc.v:176961.9-176961.17" case 1'1 case end @@ -362475,15 +370435,16 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$11978 3'111 + assign $1\req_l_r_req$next[2:0]$12377 3'111 case - assign $1\req_l_r_req$next[2:0]$11978 \$68 + assign $1\req_l_r_req$next[2:0]$12377 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$11977 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12376 end - attribute \src "libresoc.v:173535.3-173571.6" - process $proc$libresoc.v:173535$11979 + attribute \src "libresoc.v:176969.3-177006.6" + process $proc$libresoc.v:176969$12378 + assign { } { } assign { } { } assign { } { } assign { } { } @@ -362516,31 +370477,33 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 - attribute \src "libresoc.v:173536.5-173536.29" + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 + attribute \src "libresoc.v:176970.5-176970.29" switch \initial - attribute \src "libresoc.v:173536.9-173536.17" + attribute \src "libresoc.v:176970.9-176970.17" case 1'1 case end @@ -362564,24 +370527,26 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11996 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11999 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12000 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12001 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12002 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12003 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12004 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12007 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12008 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12011 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -362593,52 +370558,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12012 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11997 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12013 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11998 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12014 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12005 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12015 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12006 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12016 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12009 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12017 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12010 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11980 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11981 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11982 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11983 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11984 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$11985 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11986 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11987 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11988 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11989 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11990 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11991 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11992 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11993 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11994 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11995 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 end - attribute \src "libresoc.v:173572.3-173593.6" - process $proc$libresoc.v:173572$12018 + attribute \src "libresoc.v:177007.3-177028.6" + process $proc$libresoc.v:177007$12419 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12019 $2\data_r0__o$next[63:0]$12023 + assign $0\data_r0__o$next[63:0]$12420 $2\data_r0__o$next[63:0]$12424 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12020 $3\data_r0__o_ok$next[0:0]$12025 - attribute \src "libresoc.v:173573.5-173573.29" + assign $0\data_r0__o_ok$next[0:0]$12421 $3\data_r0__o_ok$next[0:0]$12426 + attribute \src "libresoc.v:177008.5-177008.29" switch \initial - attribute \src "libresoc.v:173573.9-173573.17" + attribute \src "libresoc.v:177008.9-177008.17" case 1'1 case end @@ -362648,10 +370614,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12022 $1\data_r0__o$next[63:0]$12021 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12423 $1\data_r0__o$next[63:0]$12422 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12021 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12022 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12422 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12423 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -362659,38 +370625,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12024 $2\data_r0__o$next[63:0]$12023 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12425 $2\data_r0__o$next[63:0]$12424 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12023 $1\data_r0__o$next[63:0]$12021 - assign $2\data_r0__o_ok$next[0:0]$12024 $1\data_r0__o_ok$next[0:0]$12022 + assign $2\data_r0__o$next[63:0]$12424 $1\data_r0__o$next[63:0]$12422 + assign $2\data_r0__o_ok$next[0:0]$12425 $1\data_r0__o_ok$next[0:0]$12423 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12025 1'0 + assign $3\data_r0__o_ok$next[0:0]$12426 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12025 $2\data_r0__o_ok$next[0:0]$12024 + assign $3\data_r0__o_ok$next[0:0]$12426 $2\data_r0__o_ok$next[0:0]$12425 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12019 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12020 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12420 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12421 end - attribute \src "libresoc.v:173594.3-173615.6" - process $proc$libresoc.v:173594$12026 + attribute \src "libresoc.v:177029.3-177050.6" + process $proc$libresoc.v:177029$12427 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12027 $2\data_r1__cr_a$next[3:0]$12031 + assign $0\data_r1__cr_a$next[3:0]$12428 $2\data_r1__cr_a$next[3:0]$12432 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12028 $3\data_r1__cr_a_ok$next[0:0]$12033 - attribute \src "libresoc.v:173595.5-173595.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12429 $3\data_r1__cr_a_ok$next[0:0]$12434 + attribute \src "libresoc.v:177030.5-177030.29" switch \initial - attribute \src "libresoc.v:173595.9-173595.17" + attribute \src "libresoc.v:177030.9-177030.17" case 1'1 case end @@ -362700,10 +370666,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12030 $1\data_r1__cr_a$next[3:0]$12029 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12431 $1\data_r1__cr_a$next[3:0]$12430 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12029 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12030 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12430 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12431 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -362711,38 +370677,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12032 $2\data_r1__cr_a$next[3:0]$12031 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12433 $2\data_r1__cr_a$next[3:0]$12432 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12031 $1\data_r1__cr_a$next[3:0]$12029 - assign $2\data_r1__cr_a_ok$next[0:0]$12032 $1\data_r1__cr_a_ok$next[0:0]$12030 + assign $2\data_r1__cr_a$next[3:0]$12432 $1\data_r1__cr_a$next[3:0]$12430 + assign $2\data_r1__cr_a_ok$next[0:0]$12433 $1\data_r1__cr_a_ok$next[0:0]$12431 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12033 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12434 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12033 $2\data_r1__cr_a_ok$next[0:0]$12032 + assign $3\data_r1__cr_a_ok$next[0:0]$12434 $2\data_r1__cr_a_ok$next[0:0]$12433 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12027 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12028 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12428 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12429 end - attribute \src "libresoc.v:173616.3-173637.6" - process $proc$libresoc.v:173616$12034 + attribute \src "libresoc.v:177051.3-177072.6" + process $proc$libresoc.v:177051$12435 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12035 $2\data_r2__xer_ca$next[1:0]$12039 + assign $0\data_r2__xer_ca$next[1:0]$12436 $2\data_r2__xer_ca$next[1:0]$12440 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12036 $3\data_r2__xer_ca_ok$next[0:0]$12041 - attribute \src "libresoc.v:173617.5-173617.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12437 $3\data_r2__xer_ca_ok$next[0:0]$12442 + attribute \src "libresoc.v:177052.5-177052.29" switch \initial - attribute \src "libresoc.v:173617.9-173617.17" + attribute \src "libresoc.v:177052.9-177052.17" case 1'1 case end @@ -362752,10 +370718,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12038 $1\data_r2__xer_ca$next[1:0]$12037 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12439 $1\data_r2__xer_ca$next[1:0]$12438 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12037 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12038 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12438 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12439 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -362763,32 +370729,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12040 $2\data_r2__xer_ca$next[1:0]$12039 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12441 $2\data_r2__xer_ca$next[1:0]$12440 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12039 $1\data_r2__xer_ca$next[1:0]$12037 - assign $2\data_r2__xer_ca_ok$next[0:0]$12040 $1\data_r2__xer_ca_ok$next[0:0]$12038 + assign $2\data_r2__xer_ca$next[1:0]$12440 $1\data_r2__xer_ca$next[1:0]$12438 + assign $2\data_r2__xer_ca_ok$next[0:0]$12441 $1\data_r2__xer_ca_ok$next[0:0]$12439 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12041 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12442 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12041 $2\data_r2__xer_ca_ok$next[0:0]$12040 + assign $3\data_r2__xer_ca_ok$next[0:0]$12442 $2\data_r2__xer_ca_ok$next[0:0]$12441 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12035 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12036 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12436 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12437 end - attribute \src "libresoc.v:173638.3-173647.6" - process $proc$libresoc.v:173638$12042 + attribute \src "libresoc.v:177073.3-177082.6" + process $proc$libresoc.v:177073$12443 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12043 $1\src_r0$next[63:0]$12044 - attribute \src "libresoc.v:173639.5-173639.29" + assign $0\src_r0$next[63:0]$12444 $1\src_r0$next[63:0]$12445 + attribute \src "libresoc.v:177074.5-177074.29" switch \initial - attribute \src "libresoc.v:173639.9-173639.17" + attribute \src "libresoc.v:177074.9-177074.17" case 1'1 case end @@ -362797,21 +370763,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12044 \src1_i + assign $1\src_r0$next[63:0]$12445 \src1_i case - assign $1\src_r0$next[63:0]$12044 \src_r0 + assign $1\src_r0$next[63:0]$12445 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12043 + update \src_r0$next $0\src_r0$next[63:0]$12444 end - attribute \src "libresoc.v:173648.3-173657.6" - process $proc$libresoc.v:173648$12045 + attribute \src "libresoc.v:177083.3-177092.6" + process $proc$libresoc.v:177083$12446 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12046 $1\src_r1$next[63:0]$12047 - attribute \src "libresoc.v:173649.5-173649.29" + assign $0\src_r1$next[63:0]$12447 $1\src_r1$next[63:0]$12448 + attribute \src "libresoc.v:177084.5-177084.29" switch \initial - attribute \src "libresoc.v:173649.9-173649.17" + attribute \src "libresoc.v:177084.9-177084.17" case 1'1 case end @@ -362820,21 +370786,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12047 \src_or_imm + assign $1\src_r1$next[63:0]$12448 \src_or_imm case - assign $1\src_r1$next[63:0]$12047 \src_r1 + assign $1\src_r1$next[63:0]$12448 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12046 + update \src_r1$next $0\src_r1$next[63:0]$12447 end - attribute \src "libresoc.v:173658.3-173667.6" - process $proc$libresoc.v:173658$12048 + attribute \src "libresoc.v:177093.3-177102.6" + process $proc$libresoc.v:177093$12449 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12049 $1\src_r2$next[63:0]$12050 - attribute \src "libresoc.v:173659.5-173659.29" + assign $0\src_r2$next[63:0]$12450 $1\src_r2$next[63:0]$12451 + attribute \src "libresoc.v:177094.5-177094.29" switch \initial - attribute \src "libresoc.v:173659.9-173659.17" + attribute \src "libresoc.v:177094.9-177094.17" case 1'1 case end @@ -362843,21 +370809,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12050 \src3_i + assign $1\src_r2$next[63:0]$12451 \src3_i case - assign $1\src_r2$next[63:0]$12050 \src_r2 + assign $1\src_r2$next[63:0]$12451 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12049 + update \src_r2$next $0\src_r2$next[63:0]$12450 end - attribute \src "libresoc.v:173668.3-173677.6" - process $proc$libresoc.v:173668$12051 + attribute \src "libresoc.v:177103.3-177112.6" + process $proc$libresoc.v:177103$12452 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12052 $1\src_r3$next[0:0]$12053 - attribute \src "libresoc.v:173669.5-173669.29" + assign $0\src_r3$next[0:0]$12453 $1\src_r3$next[0:0]$12454 + attribute \src "libresoc.v:177104.5-177104.29" switch \initial - attribute \src "libresoc.v:173669.9-173669.17" + attribute \src "libresoc.v:177104.9-177104.17" case 1'1 case end @@ -362866,21 +370832,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12053 \src4_i + assign $1\src_r3$next[0:0]$12454 \src4_i case - assign $1\src_r3$next[0:0]$12053 \src_r3 + assign $1\src_r3$next[0:0]$12454 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12052 + update \src_r3$next $0\src_r3$next[0:0]$12453 end - attribute \src "libresoc.v:173678.3-173687.6" - process $proc$libresoc.v:173678$12054 + attribute \src "libresoc.v:177113.3-177122.6" + process $proc$libresoc.v:177113$12455 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12055 $1\src_r4$next[1:0]$12056 - attribute \src "libresoc.v:173679.5-173679.29" + assign $0\src_r4$next[1:0]$12456 $1\src_r4$next[1:0]$12457 + attribute \src "libresoc.v:177114.5-177114.29" switch \initial - attribute \src "libresoc.v:173679.9-173679.17" + attribute \src "libresoc.v:177114.9-177114.17" case 1'1 case end @@ -362889,21 +370855,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12056 \src5_i + assign $1\src_r4$next[1:0]$12457 \src5_i case - assign $1\src_r4$next[1:0]$12056 \src_r4 + assign $1\src_r4$next[1:0]$12457 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12055 + update \src_r4$next $0\src_r4$next[1:0]$12456 end - attribute \src "libresoc.v:173688.3-173696.6" - process $proc$libresoc.v:173688$12057 + attribute \src "libresoc.v:177123.3-177131.6" + process $proc$libresoc.v:177123$12458 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12058 $1\alui_l_r_alui$next[0:0]$12059 - attribute \src "libresoc.v:173689.5-173689.29" + assign $0\alui_l_r_alui$next[0:0]$12459 $1\alui_l_r_alui$next[0:0]$12460 + attribute \src "libresoc.v:177124.5-177124.29" switch \initial - attribute \src "libresoc.v:173689.9-173689.17" + attribute \src "libresoc.v:177124.9-177124.17" case 1'1 case end @@ -362912,21 +370878,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12059 1'1 + assign $1\alui_l_r_alui$next[0:0]$12460 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12059 \$90 + assign $1\alui_l_r_alui$next[0:0]$12460 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12058 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12459 end - attribute \src "libresoc.v:173697.3-173705.6" - process $proc$libresoc.v:173697$12060 + attribute \src "libresoc.v:177132.3-177140.6" + process $proc$libresoc.v:177132$12461 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12061 $1\alu_l_r_alu$next[0:0]$12062 - attribute \src "libresoc.v:173698.5-173698.29" + assign $0\alu_l_r_alu$next[0:0]$12462 $1\alu_l_r_alu$next[0:0]$12463 + attribute \src "libresoc.v:177133.5-177133.29" switch \initial - attribute \src "libresoc.v:173698.9-173698.17" + attribute \src "libresoc.v:177133.9-177133.17" case 1'1 case end @@ -362935,21 +370901,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12062 1'1 + assign $1\alu_l_r_alu$next[0:0]$12463 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12062 \$92 + assign $1\alu_l_r_alu$next[0:0]$12463 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12061 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12462 end - attribute \src "libresoc.v:173706.3-173715.6" - process $proc$libresoc.v:173706$12063 + attribute \src "libresoc.v:177141.3-177150.6" + process $proc$libresoc.v:177141$12464 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:173707.5-173707.29" + attribute \src "libresoc.v:177142.5-177142.29" switch \initial - attribute \src "libresoc.v:173707.9-173707.17" + attribute \src "libresoc.v:177142.9-177142.17" case 1'1 case end @@ -362965,14 +370931,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:173716.3-173725.6" - process $proc$libresoc.v:173716$12064 + attribute \src "libresoc.v:177151.3-177160.6" + process $proc$libresoc.v:177151$12465 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:173717.5-173717.29" + attribute \src "libresoc.v:177152.5-177152.29" switch \initial - attribute \src "libresoc.v:173717.9-173717.17" + attribute \src "libresoc.v:177152.9-177152.17" case 1'1 case end @@ -362988,14 +370954,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:173726.3-173735.6" - process $proc$libresoc.v:173726$12065 + attribute \src "libresoc.v:177161.3-177170.6" + process $proc$libresoc.v:177161$12466 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:173727.5-173727.29" + attribute \src "libresoc.v:177162.5-177162.29" switch \initial - attribute \src "libresoc.v:173727.9-173727.17" + attribute \src "libresoc.v:177162.9-177162.17" case 1'1 case end @@ -363011,14 +370977,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:173736.3-173744.6" - process $proc$libresoc.v:173736$12066 + attribute \src "libresoc.v:177171.3-177179.6" + process $proc$libresoc.v:177171$12467 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12067 $1\prev_wr_go$next[2:0]$12068 - attribute \src "libresoc.v:173737.5-173737.29" + assign $0\prev_wr_go$next[2:0]$12468 $1\prev_wr_go$next[2:0]$12469 + attribute \src "libresoc.v:177172.5-177172.29" switch \initial - attribute \src "libresoc.v:173737.9-173737.17" + attribute \src "libresoc.v:177172.9-177172.17" case 1'1 case end @@ -363027,72 +370993,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12068 3'000 - case - assign $1\prev_wr_go$next[2:0]$12068 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12067 - end - connect \$100 $not$libresoc.v:173209$11847_Y - connect \$102 $and$libresoc.v:173210$11848_Y - connect \$104 $and$libresoc.v:173211$11849_Y - connect \$106 $and$libresoc.v:173212$11850_Y - connect \$108 $and$libresoc.v:173213$11851_Y - connect \$10 $and$libresoc.v:173214$11852_Y - connect \$110 $and$libresoc.v:173215$11853_Y - connect \$112 $and$libresoc.v:173216$11854_Y - connect \$114 $and$libresoc.v:173217$11855_Y - connect \$116 $and$libresoc.v:173218$11856_Y - connect \$118 $and$libresoc.v:173219$11857_Y - connect \$12 $not$libresoc.v:173220$11858_Y - connect \$14 $and$libresoc.v:173221$11859_Y - connect \$16 $not$libresoc.v:173222$11860_Y - connect \$18 $and$libresoc.v:173223$11861_Y - connect \$20 $and$libresoc.v:173224$11862_Y - connect \$24 $not$libresoc.v:173225$11863_Y - connect \$26 $and$libresoc.v:173226$11864_Y - connect \$23 $reduce_or$libresoc.v:173227$11865_Y - connect \$22 $not$libresoc.v:173228$11866_Y - connect \$2 $and$libresoc.v:173229$11867_Y - connect \$30 $and$libresoc.v:173230$11868_Y - connect \$32 $reduce_or$libresoc.v:173231$11869_Y - connect \$34 $reduce_or$libresoc.v:173232$11870_Y - connect \$36 $or$libresoc.v:173233$11871_Y - connect \$38 $not$libresoc.v:173234$11872_Y - connect \$40 $and$libresoc.v:173235$11873_Y - connect \$42 $and$libresoc.v:173236$11874_Y - connect \$44 $eq$libresoc.v:173237$11875_Y - connect \$46 $and$libresoc.v:173238$11876_Y - connect \$48 $eq$libresoc.v:173239$11877_Y - connect \$50 $and$libresoc.v:173240$11878_Y - connect \$52 $and$libresoc.v:173241$11879_Y - connect \$54 $and$libresoc.v:173242$11880_Y - connect \$56 $or$libresoc.v:173243$11881_Y - connect \$58 $or$libresoc.v:173244$11882_Y - connect \$5 $not$libresoc.v:173245$11883_Y - connect \$60 $or$libresoc.v:173246$11884_Y - connect \$62 $or$libresoc.v:173247$11885_Y - connect \$64 $and$libresoc.v:173248$11886_Y - connect \$66 $and$libresoc.v:173249$11887_Y - connect \$68 $or$libresoc.v:173250$11888_Y - connect \$70 $and$libresoc.v:173251$11889_Y - connect \$72 $and$libresoc.v:173252$11890_Y - connect \$74 $and$libresoc.v:173253$11891_Y - connect \$76 $ternary$libresoc.v:173254$11892_Y - connect \$78 $ternary$libresoc.v:173255$11893_Y - connect \$7 $or$libresoc.v:173256$11894_Y - connect \$80 $ternary$libresoc.v:173257$11895_Y - connect \$82 $ternary$libresoc.v:173258$11896_Y - connect \$84 $ternary$libresoc.v:173259$11897_Y - connect \$86 $ternary$libresoc.v:173260$11898_Y - connect \$88 $ternary$libresoc.v:173261$11899_Y - connect \$4 $reduce_and$libresoc.v:173262$11900_Y - connect \$90 $and$libresoc.v:173263$11901_Y - connect \$92 $and$libresoc.v:173264$11902_Y - connect \$94 $and$libresoc.v:173265$11903_Y - connect \$96 $not$libresoc.v:173266$11904_Y - connect \$98 $and$libresoc.v:173267$11905_Y + assign $1\prev_wr_go$next[2:0]$12469 3'000 + case + assign $1\prev_wr_go$next[2:0]$12469 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12468 + end + connect \$100 $not$libresoc.v:176640$12245_Y + connect \$102 $and$libresoc.v:176641$12246_Y + connect \$104 $and$libresoc.v:176642$12247_Y + connect \$106 $and$libresoc.v:176643$12248_Y + connect \$108 $and$libresoc.v:176644$12249_Y + connect \$10 $and$libresoc.v:176645$12250_Y + connect \$110 $and$libresoc.v:176646$12251_Y + connect \$112 $and$libresoc.v:176647$12252_Y + connect \$114 $and$libresoc.v:176648$12253_Y + connect \$116 $and$libresoc.v:176649$12254_Y + connect \$118 $and$libresoc.v:176650$12255_Y + connect \$12 $not$libresoc.v:176651$12256_Y + connect \$14 $and$libresoc.v:176652$12257_Y + connect \$16 $not$libresoc.v:176653$12258_Y + connect \$18 $and$libresoc.v:176654$12259_Y + connect \$20 $and$libresoc.v:176655$12260_Y + connect \$24 $not$libresoc.v:176656$12261_Y + connect \$26 $and$libresoc.v:176657$12262_Y + connect \$23 $reduce_or$libresoc.v:176658$12263_Y + connect \$22 $not$libresoc.v:176659$12264_Y + connect \$2 $and$libresoc.v:176660$12265_Y + connect \$30 $and$libresoc.v:176661$12266_Y + connect \$32 $reduce_or$libresoc.v:176662$12267_Y + connect \$34 $reduce_or$libresoc.v:176663$12268_Y + connect \$36 $or$libresoc.v:176664$12269_Y + connect \$38 $not$libresoc.v:176665$12270_Y + connect \$40 $and$libresoc.v:176666$12271_Y + connect \$42 $and$libresoc.v:176667$12272_Y + connect \$44 $eq$libresoc.v:176668$12273_Y + connect \$46 $and$libresoc.v:176669$12274_Y + connect \$48 $eq$libresoc.v:176670$12275_Y + connect \$50 $and$libresoc.v:176671$12276_Y + connect \$52 $and$libresoc.v:176672$12277_Y + connect \$54 $and$libresoc.v:176673$12278_Y + connect \$56 $or$libresoc.v:176674$12279_Y + connect \$58 $or$libresoc.v:176675$12280_Y + connect \$5 $not$libresoc.v:176676$12281_Y + connect \$60 $or$libresoc.v:176677$12282_Y + connect \$62 $or$libresoc.v:176678$12283_Y + connect \$64 $and$libresoc.v:176679$12284_Y + connect \$66 $and$libresoc.v:176680$12285_Y + connect \$68 $or$libresoc.v:176681$12286_Y + connect \$70 $and$libresoc.v:176682$12287_Y + connect \$72 $and$libresoc.v:176683$12288_Y + connect \$74 $and$libresoc.v:176684$12289_Y + connect \$76 $ternary$libresoc.v:176685$12290_Y + connect \$78 $ternary$libresoc.v:176686$12291_Y + connect \$7 $or$libresoc.v:176687$12292_Y + connect \$80 $ternary$libresoc.v:176688$12293_Y + connect \$82 $ternary$libresoc.v:176689$12294_Y + connect \$84 $ternary$libresoc.v:176690$12295_Y + connect \$86 $ternary$libresoc.v:176691$12296_Y + connect \$88 $ternary$libresoc.v:176692$12297_Y + connect \$4 $reduce_and$libresoc.v:176693$12298_Y + connect \$90 $and$libresoc.v:176694$12299_Y + connect \$92 $and$libresoc.v:176695$12300_Y + connect \$94 $and$libresoc.v:176696$12301_Y + connect \$96 $not$libresoc.v:176697$12302_Y + connect \$98 $and$libresoc.v:176698$12303_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -363126,48 +371092,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:173781.1-173958.10" +attribute \src "libresoc.v:177216.1-177393.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.spr" +attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:173930.3-173933.6" - wire width 7 $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 - attribute \src "libresoc.v:173930.3-173933.6" - wire width 64 $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 - attribute \src "libresoc.v:173930.3-173933.6" - wire width 64 $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 - attribute \src "libresoc.v:173930.3-173933.6" + attribute \src "libresoc.v:177365.3-177368.6" + wire width 7 $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 + attribute \src "libresoc.v:177365.3-177368.6" + wire width 64 $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 + attribute \src "libresoc.v:177365.3-177368.6" + wire width 64 $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 + attribute \src "libresoc.v:177365.3-177368.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:173782.7-173782.20" + attribute \src "libresoc.v:177217.7-177217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173935.3-173943.6" - wire $0\ren_delay$next[0:0]$12230 - attribute \src "libresoc.v:173814.3-173815.35" + attribute \src "libresoc.v:177370.3-177378.6" + wire $0\ren_delay$next[0:0]$12632 + attribute \src "libresoc.v:177249.3-177250.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:173944.3-173953.6" + attribute \src "libresoc.v:177379.3-177388.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:173935.3-173943.6" - wire $1\ren_delay$next[0:0]$12231 - attribute \src "libresoc.v:173798.7-173798.23" + attribute \src "libresoc.v:177370.3-177378.6" + wire $1\ren_delay$next[0:0]$12633 + attribute \src "libresoc.v:177233.7-177233.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:173944.3-173953.6" + attribute \src "libresoc.v:177379.3-177388.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:173934.26-173934.32" - wire width 64 $memrd$\memory$libresoc.v:173934$12228_DATA + attribute \src "libresoc.v:177369.26-177369.32" + wire width 64 $memrd$\memory$libresoc.v:177369$12630_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:173932$12222_ADDR + wire width 7 $memwr$\memory$libresoc.v:177367$12624_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:173932$12222_DATA + wire width 64 $memwr$\memory$libresoc.v:177367$12624_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:173932$12222_EN - attribute \src "libresoc.v:173929.13-173929.16" + wire width 64 $memwr$\memory$libresoc.v:177367$12624_EN + attribute \src "libresoc.v:177364.13-177364.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 7 \coresync_rst - attribute \src "libresoc.v:173782.7-173782.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "libresoc.v:177217.7-177217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -363184,1121 +371150,1121 @@ module \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" wire \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 2 \spr1__addr + wire width 7 input 3 \spr1__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 5 \spr1__addr$1 + wire width 7 input 6 \spr1__addr$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \spr1__data_i + wire width 64 input 5 \spr1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \spr1__data_o + wire width 64 output 2 \spr1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 3 \spr1__ren + wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \spr1__wen - attribute \src "libresoc.v:173816.14-173816.20" + wire input 7 \spr1__wen + attribute \src "libresoc.v:177251.14-177251.20" memory width 64 size 110 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12233 + cell $meminit $meminit$\memory$libresoc.v:0$12635 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12233 + parameter \PRIORITY 12635 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12234 + cell $meminit $meminit$\memory$libresoc.v:0$12636 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12234 + parameter \PRIORITY 12636 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12235 + cell $meminit $meminit$\memory$libresoc.v:0$12637 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12235 + parameter \PRIORITY 12637 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12236 + cell $meminit $meminit$\memory$libresoc.v:0$12638 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12236 + parameter \PRIORITY 12638 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12237 + cell $meminit $meminit$\memory$libresoc.v:0$12639 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12237 + parameter \PRIORITY 12639 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12238 + cell $meminit $meminit$\memory$libresoc.v:0$12640 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12238 + parameter \PRIORITY 12640 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12239 + cell $meminit $meminit$\memory$libresoc.v:0$12641 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12239 + parameter \PRIORITY 12641 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12240 + cell $meminit $meminit$\memory$libresoc.v:0$12642 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12240 + parameter \PRIORITY 12642 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12241 + cell $meminit $meminit$\memory$libresoc.v:0$12643 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12241 + parameter \PRIORITY 12643 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12242 + cell $meminit $meminit$\memory$libresoc.v:0$12644 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12242 + parameter \PRIORITY 12644 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12243 + cell $meminit $meminit$\memory$libresoc.v:0$12645 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12243 + parameter \PRIORITY 12645 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12244 + cell $meminit $meminit$\memory$libresoc.v:0$12646 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12244 + parameter \PRIORITY 12646 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12245 + cell $meminit $meminit$\memory$libresoc.v:0$12647 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12245 + parameter \PRIORITY 12647 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12246 + cell $meminit $meminit$\memory$libresoc.v:0$12648 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12246 + parameter \PRIORITY 12648 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12247 + cell $meminit $meminit$\memory$libresoc.v:0$12649 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12247 + parameter \PRIORITY 12649 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12248 + cell $meminit $meminit$\memory$libresoc.v:0$12650 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12248 + parameter \PRIORITY 12650 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12249 + cell $meminit $meminit$\memory$libresoc.v:0$12651 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12249 + parameter \PRIORITY 12651 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12250 + cell $meminit $meminit$\memory$libresoc.v:0$12652 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12250 + parameter \PRIORITY 12652 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12251 + cell $meminit $meminit$\memory$libresoc.v:0$12653 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12251 + parameter \PRIORITY 12653 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12252 + cell $meminit $meminit$\memory$libresoc.v:0$12654 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12252 + parameter \PRIORITY 12654 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12253 + cell $meminit $meminit$\memory$libresoc.v:0$12655 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12253 + parameter \PRIORITY 12655 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12254 + cell $meminit $meminit$\memory$libresoc.v:0$12656 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12254 + parameter \PRIORITY 12656 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12255 + cell $meminit $meminit$\memory$libresoc.v:0$12657 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12255 + parameter \PRIORITY 12657 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12256 + cell $meminit $meminit$\memory$libresoc.v:0$12658 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12256 + parameter \PRIORITY 12658 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12257 + cell $meminit $meminit$\memory$libresoc.v:0$12659 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12257 + parameter \PRIORITY 12659 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12258 + cell $meminit $meminit$\memory$libresoc.v:0$12660 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12258 + parameter \PRIORITY 12660 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12259 + cell $meminit $meminit$\memory$libresoc.v:0$12661 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12259 + parameter \PRIORITY 12661 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12260 + cell $meminit $meminit$\memory$libresoc.v:0$12662 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12260 + parameter \PRIORITY 12662 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12261 + cell $meminit $meminit$\memory$libresoc.v:0$12663 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12261 + parameter \PRIORITY 12663 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12262 + cell $meminit $meminit$\memory$libresoc.v:0$12664 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12262 + parameter \PRIORITY 12664 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12263 + cell $meminit $meminit$\memory$libresoc.v:0$12665 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12263 + parameter \PRIORITY 12665 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12264 + cell $meminit $meminit$\memory$libresoc.v:0$12666 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12264 + parameter \PRIORITY 12666 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12265 + cell $meminit $meminit$\memory$libresoc.v:0$12667 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12265 + parameter \PRIORITY 12667 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12266 + cell $meminit $meminit$\memory$libresoc.v:0$12668 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12266 + parameter \PRIORITY 12668 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12267 + cell $meminit $meminit$\memory$libresoc.v:0$12669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12267 + parameter \PRIORITY 12669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12268 + cell $meminit $meminit$\memory$libresoc.v:0$12670 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12268 + parameter \PRIORITY 12670 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12269 + cell $meminit $meminit$\memory$libresoc.v:0$12671 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12269 + parameter \PRIORITY 12671 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12270 + cell $meminit $meminit$\memory$libresoc.v:0$12672 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12270 + parameter \PRIORITY 12672 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12271 + cell $meminit $meminit$\memory$libresoc.v:0$12673 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12271 + parameter \PRIORITY 12673 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12272 + cell $meminit $meminit$\memory$libresoc.v:0$12674 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12272 + parameter \PRIORITY 12674 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12273 + cell $meminit $meminit$\memory$libresoc.v:0$12675 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12273 + parameter \PRIORITY 12675 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12274 + cell $meminit $meminit$\memory$libresoc.v:0$12676 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12274 + parameter \PRIORITY 12676 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12275 + cell $meminit $meminit$\memory$libresoc.v:0$12677 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12275 + parameter \PRIORITY 12677 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12276 + cell $meminit $meminit$\memory$libresoc.v:0$12678 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12276 + parameter \PRIORITY 12678 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12277 + cell $meminit $meminit$\memory$libresoc.v:0$12679 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12277 + parameter \PRIORITY 12679 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12278 + cell $meminit $meminit$\memory$libresoc.v:0$12680 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12278 + parameter \PRIORITY 12680 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12279 + cell $meminit $meminit$\memory$libresoc.v:0$12681 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12279 + parameter \PRIORITY 12681 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12280 + cell $meminit $meminit$\memory$libresoc.v:0$12682 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12280 + parameter \PRIORITY 12682 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12281 + cell $meminit $meminit$\memory$libresoc.v:0$12683 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12281 + parameter \PRIORITY 12683 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12282 + cell $meminit $meminit$\memory$libresoc.v:0$12684 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12282 + parameter \PRIORITY 12684 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12283 + cell $meminit $meminit$\memory$libresoc.v:0$12685 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12283 + parameter \PRIORITY 12685 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12284 + cell $meminit $meminit$\memory$libresoc.v:0$12686 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12284 + parameter \PRIORITY 12686 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12285 + cell $meminit $meminit$\memory$libresoc.v:0$12687 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12285 + parameter \PRIORITY 12687 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12286 + cell $meminit $meminit$\memory$libresoc.v:0$12688 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12286 + parameter \PRIORITY 12688 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12287 + cell $meminit $meminit$\memory$libresoc.v:0$12689 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12287 + parameter \PRIORITY 12689 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12288 + cell $meminit $meminit$\memory$libresoc.v:0$12690 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12288 + parameter \PRIORITY 12690 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12289 + cell $meminit $meminit$\memory$libresoc.v:0$12691 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12289 + parameter \PRIORITY 12691 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12290 + cell $meminit $meminit$\memory$libresoc.v:0$12692 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12290 + parameter \PRIORITY 12692 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12291 + cell $meminit $meminit$\memory$libresoc.v:0$12693 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12291 + parameter \PRIORITY 12693 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12292 + cell $meminit $meminit$\memory$libresoc.v:0$12694 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12292 + parameter \PRIORITY 12694 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12293 + cell $meminit $meminit$\memory$libresoc.v:0$12695 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12293 + parameter \PRIORITY 12695 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12294 + cell $meminit $meminit$\memory$libresoc.v:0$12696 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12294 + parameter \PRIORITY 12696 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12295 + cell $meminit $meminit$\memory$libresoc.v:0$12697 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12295 + parameter \PRIORITY 12697 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12296 + cell $meminit $meminit$\memory$libresoc.v:0$12698 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12296 + parameter \PRIORITY 12698 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12297 + cell $meminit $meminit$\memory$libresoc.v:0$12699 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12297 + parameter \PRIORITY 12699 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12298 + cell $meminit $meminit$\memory$libresoc.v:0$12700 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12298 + parameter \PRIORITY 12700 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12299 + cell $meminit $meminit$\memory$libresoc.v:0$12701 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12299 + parameter \PRIORITY 12701 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12300 + cell $meminit $meminit$\memory$libresoc.v:0$12702 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12300 + parameter \PRIORITY 12702 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12301 + cell $meminit $meminit$\memory$libresoc.v:0$12703 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12301 + parameter \PRIORITY 12703 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12302 + cell $meminit $meminit$\memory$libresoc.v:0$12704 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12302 + parameter \PRIORITY 12704 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12303 + cell $meminit $meminit$\memory$libresoc.v:0$12705 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12303 + parameter \PRIORITY 12705 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12304 + cell $meminit $meminit$\memory$libresoc.v:0$12706 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12304 + parameter \PRIORITY 12706 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12305 + cell $meminit $meminit$\memory$libresoc.v:0$12707 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12305 + parameter \PRIORITY 12707 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12306 + cell $meminit $meminit$\memory$libresoc.v:0$12708 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12306 + parameter \PRIORITY 12708 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12307 + cell $meminit $meminit$\memory$libresoc.v:0$12709 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12307 + parameter \PRIORITY 12709 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12308 + cell $meminit $meminit$\memory$libresoc.v:0$12710 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12308 + parameter \PRIORITY 12710 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12309 + cell $meminit $meminit$\memory$libresoc.v:0$12711 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12309 + parameter \PRIORITY 12711 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12310 + cell $meminit $meminit$\memory$libresoc.v:0$12712 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12310 + parameter \PRIORITY 12712 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12311 + cell $meminit $meminit$\memory$libresoc.v:0$12713 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12311 + parameter \PRIORITY 12713 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12312 + cell $meminit $meminit$\memory$libresoc.v:0$12714 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12312 + parameter \PRIORITY 12714 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12313 + cell $meminit $meminit$\memory$libresoc.v:0$12715 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12313 + parameter \PRIORITY 12715 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12314 + cell $meminit $meminit$\memory$libresoc.v:0$12716 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12314 + parameter \PRIORITY 12716 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12315 + cell $meminit $meminit$\memory$libresoc.v:0$12717 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12315 + parameter \PRIORITY 12717 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12316 + cell $meminit $meminit$\memory$libresoc.v:0$12718 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12316 + parameter \PRIORITY 12718 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12317 + cell $meminit $meminit$\memory$libresoc.v:0$12719 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12317 + parameter \PRIORITY 12719 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12318 + cell $meminit $meminit$\memory$libresoc.v:0$12720 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12318 + parameter \PRIORITY 12720 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12319 + cell $meminit $meminit$\memory$libresoc.v:0$12721 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12319 + parameter \PRIORITY 12721 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12320 + cell $meminit $meminit$\memory$libresoc.v:0$12722 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12320 + parameter \PRIORITY 12722 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12321 + cell $meminit $meminit$\memory$libresoc.v:0$12723 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12321 + parameter \PRIORITY 12723 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12322 + cell $meminit $meminit$\memory$libresoc.v:0$12724 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12322 + parameter \PRIORITY 12724 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12323 + cell $meminit $meminit$\memory$libresoc.v:0$12725 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12323 + parameter \PRIORITY 12725 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12324 + cell $meminit $meminit$\memory$libresoc.v:0$12726 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12324 + parameter \PRIORITY 12726 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12325 + cell $meminit $meminit$\memory$libresoc.v:0$12727 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12325 + parameter \PRIORITY 12727 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12326 + cell $meminit $meminit$\memory$libresoc.v:0$12728 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12326 + parameter \PRIORITY 12728 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12327 + cell $meminit $meminit$\memory$libresoc.v:0$12729 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12327 + parameter \PRIORITY 12729 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12328 + cell $meminit $meminit$\memory$libresoc.v:0$12730 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12328 + parameter \PRIORITY 12730 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12329 + cell $meminit $meminit$\memory$libresoc.v:0$12731 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12329 + parameter \PRIORITY 12731 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12330 + cell $meminit $meminit$\memory$libresoc.v:0$12732 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12330 + parameter \PRIORITY 12732 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12331 + cell $meminit $meminit$\memory$libresoc.v:0$12733 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12331 + parameter \PRIORITY 12733 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12332 + cell $meminit $meminit$\memory$libresoc.v:0$12734 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12332 + parameter \PRIORITY 12734 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12333 + cell $meminit $meminit$\memory$libresoc.v:0$12735 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12333 + parameter \PRIORITY 12735 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12334 + cell $meminit $meminit$\memory$libresoc.v:0$12736 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12334 + parameter \PRIORITY 12736 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12335 + cell $meminit $meminit$\memory$libresoc.v:0$12737 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12335 + parameter \PRIORITY 12737 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12336 + cell $meminit $meminit$\memory$libresoc.v:0$12738 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12336 + parameter \PRIORITY 12738 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12337 + cell $meminit $meminit$\memory$libresoc.v:0$12739 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12337 + parameter \PRIORITY 12739 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12338 + cell $meminit $meminit$\memory$libresoc.v:0$12740 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12338 + parameter \PRIORITY 12740 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12339 + cell $meminit $meminit$\memory$libresoc.v:0$12741 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12339 + parameter \PRIORITY 12741 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12340 + cell $meminit $meminit$\memory$libresoc.v:0$12742 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12340 + parameter \PRIORITY 12742 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12341 + cell $meminit $meminit$\memory$libresoc.v:0$12743 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12341 + parameter \PRIORITY 12743 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12342 + cell $meminit $meminit$\memory$libresoc.v:0$12744 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12342 + parameter \PRIORITY 12744 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:173934.26-173934.32" - cell $memrd $memrd$\memory$libresoc.v:173934$12228 + attribute \src "libresoc.v:177369.26-177369.32" + cell $memrd $memrd$\memory$libresoc.v:177369$12630 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -364307,83 +372273,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:173934$12228_DATA + connect \DATA $memrd$\memory$libresoc.v:177369$12630_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12343 + cell $memwr $memwr$\memory$libresoc.v:0$12745 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 12343 + parameter \PRIORITY 12745 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:173932$12222_ADDR + connect \ADDR $memwr$\memory$libresoc.v:177367$12624_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:173932$12222_DATA - connect \EN $memwr$\memory$libresoc.v:173932$12222_EN + connect \DATA $memwr$\memory$libresoc.v:177367$12624_DATA + connect \EN $memwr$\memory$libresoc.v:177367$12624_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12346 + process $proc$libresoc.v:0$12748 sync always sync init end - attribute \src "libresoc.v:173782.7-173782.20" - process $proc$libresoc.v:173782$12344 + attribute \src "libresoc.v:177217.7-177217.20" + process $proc$libresoc.v:177217$12746 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173798.7-173798.23" - process $proc$libresoc.v:173798$12345 + attribute \src "libresoc.v:177233.7-177233.23" + process $proc$libresoc.v:177233$12747 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:173814.3-173815.35" - process $proc$libresoc.v:173814$12223 + attribute \src "libresoc.v:177249.3-177250.35" + process $proc$libresoc.v:177249$12625 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:173930.3-173933.6" - process $proc$libresoc.v:173930$12224 + attribute \src "libresoc.v:177365.3-177368.6" + process $proc$libresoc.v:177365$12626 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:173932.5-173932.59" + attribute \src "libresoc.v:177367.5-177367.59" switch \spr1__wen - attribute \src "libresoc.v:173932.9-173932.18" + attribute \src "libresoc.v:177367.9-177367.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:173932$12222_ADDR $0$memwr$\memory$libresoc.v:173932$12222_ADDR[6:0]$12225 - update $memwr$\memory$libresoc.v:173932$12222_DATA $0$memwr$\memory$libresoc.v:173932$12222_DATA[63:0]$12226 - update $memwr$\memory$libresoc.v:173932$12222_EN $0$memwr$\memory$libresoc.v:173932$12222_EN[63:0]$12227 + update $memwr$\memory$libresoc.v:177367$12624_ADDR $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 + update $memwr$\memory$libresoc.v:177367$12624_DATA $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 + update $memwr$\memory$libresoc.v:177367$12624_EN $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 end - attribute \src "libresoc.v:173935.3-173943.6" - process $proc$libresoc.v:173935$12229 + attribute \src "libresoc.v:177370.3-177378.6" + process $proc$libresoc.v:177370$12631 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12230 $1\ren_delay$next[0:0]$12231 - attribute \src "libresoc.v:173936.5-173936.29" + assign $0\ren_delay$next[0:0]$12632 $1\ren_delay$next[0:0]$12633 + attribute \src "libresoc.v:177371.5-177371.29" switch \initial - attribute \src "libresoc.v:173936.9-173936.17" + attribute \src "libresoc.v:177371.9-177371.17" case 1'1 case end @@ -364392,21 +372358,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12231 1'0 + assign $1\ren_delay$next[0:0]$12633 1'0 case - assign $1\ren_delay$next[0:0]$12231 \spr1__ren + assign $1\ren_delay$next[0:0]$12633 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12230 + update \ren_delay$next $0\ren_delay$next[0:0]$12632 end - attribute \src "libresoc.v:173944.3-173953.6" - process $proc$libresoc.v:173944$12232 + attribute \src "libresoc.v:177379.3-177388.6" + process $proc$libresoc.v:177379$12634 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:173945.5-173945.29" + attribute \src "libresoc.v:177380.5-177380.29" switch \initial - attribute \src "libresoc.v:173945.9-173945.17" + attribute \src "libresoc.v:177380.9-177380.17" case 1'1 case end @@ -364422,503 +372388,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:173934$12228_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:177369$12630_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:173962.1-175209.10" +attribute \src "libresoc.v:177397.1-178644.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:174706.3-174707.25" + attribute \src "libresoc.v:178141.3-178142.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:174704.3-174705.40" + attribute \src "libresoc.v:178139.3-178140.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:175100.3-175108.6" - wire $0\alu_l_r_alu$next[0:0]$12560 - attribute \src "libresoc.v:174634.3-174635.39" + attribute \src "libresoc.v:178535.3-178543.6" + wire $0\alu_l_r_alu$next[0:0]$12962 + attribute \src "libresoc.v:178069.3-178070.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 - attribute \src "libresoc.v:174676.3-174677.65" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 + attribute \src "libresoc.v:178111.3-178112.65" wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12483 - attribute \src "libresoc.v:174678.3-174679.59" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12885 + attribute \src "libresoc.v:178113.3-178114.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 - attribute \src "libresoc.v:174674.3-174675.69" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 + attribute \src "libresoc.v:178109.3-178110.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 - attribute \src "libresoc.v:174680.3-174681.67" + attribute \src "libresoc.v:178321.3-178333.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 + attribute \src "libresoc.v:178115.3-178116.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:175091.3-175099.6" - wire $0\alui_l_r_alui$next[0:0]$12557 - attribute \src "libresoc.v:174636.3-174637.43" + attribute \src "libresoc.v:178526.3-178534.6" + wire $0\alui_l_r_alui$next[0:0]$12959 + attribute \src "libresoc.v:178071.3-178072.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:174899.3-174920.6" - wire width 64 $0\data_r0__o$next[63:0]$12491 - attribute \src "libresoc.v:174670.3-174671.37" + attribute \src "libresoc.v:178334.3-178355.6" + wire width 64 $0\data_r0__o$next[63:0]$12893 + attribute \src "libresoc.v:178105.3-178106.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:174899.3-174920.6" - wire $0\data_r0__o_ok$next[0:0]$12492 - attribute \src "libresoc.v:174672.3-174673.43" + attribute \src "libresoc.v:178334.3-178355.6" + wire $0\data_r0__o_ok$next[0:0]$12894 + attribute \src "libresoc.v:178107.3-178108.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:174921.3-174942.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12499 - attribute \src "libresoc.v:174666.3-174667.43" + attribute \src "libresoc.v:178356.3-178377.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12901 + attribute \src "libresoc.v:178101.3-178102.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:174921.3-174942.6" - wire $0\data_r1__spr1_ok$next[0:0]$12500 - attribute \src "libresoc.v:174668.3-174669.49" + attribute \src "libresoc.v:178356.3-178377.6" + wire $0\data_r1__spr1_ok$next[0:0]$12902 + attribute \src "libresoc.v:178103.3-178104.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:174943.3-174964.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12507 - attribute \src "libresoc.v:174662.3-174663.45" + attribute \src "libresoc.v:178378.3-178399.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12909 + attribute \src "libresoc.v:178097.3-178098.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:174943.3-174964.6" - wire $0\data_r2__fast1_ok$next[0:0]$12508 - attribute \src "libresoc.v:174664.3-174665.51" + attribute \src "libresoc.v:178378.3-178399.6" + wire $0\data_r2__fast1_ok$next[0:0]$12910 + attribute \src "libresoc.v:178099.3-178100.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:174965.3-174986.6" - wire $0\data_r3__xer_so$next[0:0]$12515 - attribute \src "libresoc.v:174658.3-174659.47" + attribute \src "libresoc.v:178400.3-178421.6" + wire $0\data_r3__xer_so$next[0:0]$12917 + attribute \src "libresoc.v:178093.3-178094.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:174965.3-174986.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12516 - attribute \src "libresoc.v:174660.3-174661.53" + attribute \src "libresoc.v:178400.3-178421.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12918 + attribute \src "libresoc.v:178095.3-178096.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:174987.3-175008.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12523 - attribute \src "libresoc.v:174654.3-174655.47" + attribute \src "libresoc.v:178422.3-178443.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12925 + attribute \src "libresoc.v:178089.3-178090.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:174987.3-175008.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12524 - attribute \src "libresoc.v:174656.3-174657.53" + attribute \src "libresoc.v:178422.3-178443.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12926 + attribute \src "libresoc.v:178091.3-178092.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:175009.3-175030.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12531 - attribute \src "libresoc.v:174650.3-174651.47" + attribute \src "libresoc.v:178444.3-178465.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12933 + attribute \src "libresoc.v:178085.3-178086.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:175009.3-175030.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12532 - attribute \src "libresoc.v:174652.3-174653.53" + attribute \src "libresoc.v:178444.3-178465.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12934 + attribute \src "libresoc.v:178087.3-178088.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:175109.3-175118.6" + attribute \src "libresoc.v:178544.3-178553.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:175119.3-175128.6" + attribute \src "libresoc.v:178554.3-178563.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:175129.3-175138.6" + attribute \src "libresoc.v:178564.3-178573.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:175139.3-175148.6" + attribute \src "libresoc.v:178574.3-178583.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:175149.3-175158.6" + attribute \src "libresoc.v:178584.3-178593.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:175159.3-175168.6" + attribute \src "libresoc.v:178594.3-178603.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:173963.7-173963.20" + attribute \src "libresoc.v:177398.7-177398.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174841.3-174849.6" - wire $0\opc_l_r_opc$next[0:0]$12467 - attribute \src "libresoc.v:174690.3-174691.39" + attribute \src "libresoc.v:178276.3-178284.6" + wire $0\opc_l_r_opc$next[0:0]$12869 + attribute \src "libresoc.v:178125.3-178126.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:174832.3-174840.6" - wire $0\opc_l_s_opc$next[0:0]$12464 - attribute \src "libresoc.v:174692.3-174693.39" + attribute \src "libresoc.v:178267.3-178275.6" + wire $0\opc_l_s_opc$next[0:0]$12866 + attribute \src "libresoc.v:178127.3-178128.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:175169.3-175177.6" - wire width 6 $0\prev_wr_go$next[5:0]$12569 - attribute \src "libresoc.v:174702.3-174703.37" + attribute \src "libresoc.v:178604.3-178612.6" + wire width 6 $0\prev_wr_go$next[5:0]$12971 + attribute \src "libresoc.v:178137.3-178138.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:174786.3-174795.6" + attribute \src "libresoc.v:178221.3-178230.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:174877.3-174885.6" - wire width 6 $0\req_l_r_req$next[5:0]$12479 - attribute \src "libresoc.v:174682.3-174683.39" + attribute \src "libresoc.v:178312.3-178320.6" + wire width 6 $0\req_l_r_req$next[5:0]$12881 + attribute \src "libresoc.v:178117.3-178118.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:174868.3-174876.6" - wire width 6 $0\req_l_s_req$next[5:0]$12476 - attribute \src "libresoc.v:174684.3-174685.39" + attribute \src "libresoc.v:178303.3-178311.6" + wire width 6 $0\req_l_s_req$next[5:0]$12878 + attribute \src "libresoc.v:178119.3-178120.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:174805.3-174813.6" - wire $0\rok_l_r_rdok$next[0:0]$12455 - attribute \src "libresoc.v:174698.3-174699.41" + attribute \src "libresoc.v:178240.3-178248.6" + wire $0\rok_l_r_rdok$next[0:0]$12857 + attribute \src "libresoc.v:178133.3-178134.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:174796.3-174804.6" - wire $0\rok_l_s_rdok$next[0:0]$12452 - attribute \src "libresoc.v:174700.3-174701.41" + attribute \src "libresoc.v:178231.3-178239.6" + wire $0\rok_l_s_rdok$next[0:0]$12854 + attribute \src "libresoc.v:178135.3-178136.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:174823.3-174831.6" - wire $0\rst_l_r_rst$next[0:0]$12461 - attribute \src "libresoc.v:174694.3-174695.39" + attribute \src "libresoc.v:178258.3-178266.6" + wire $0\rst_l_r_rst$next[0:0]$12863 + attribute \src "libresoc.v:178129.3-178130.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:174814.3-174822.6" - wire $0\rst_l_s_rst$next[0:0]$12458 - attribute \src "libresoc.v:174696.3-174697.39" + attribute \src "libresoc.v:178249.3-178257.6" + wire $0\rst_l_s_rst$next[0:0]$12860 + attribute \src "libresoc.v:178131.3-178132.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:174859.3-174867.6" - wire width 6 $0\src_l_r_src$next[5:0]$12473 - attribute \src "libresoc.v:174686.3-174687.39" + attribute \src "libresoc.v:178294.3-178302.6" + wire width 6 $0\src_l_r_src$next[5:0]$12875 + attribute \src "libresoc.v:178121.3-178122.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:174850.3-174858.6" - wire width 6 $0\src_l_s_src$next[5:0]$12470 - attribute \src "libresoc.v:174688.3-174689.39" + attribute \src "libresoc.v:178285.3-178293.6" + wire width 6 $0\src_l_s_src$next[5:0]$12872 + attribute \src "libresoc.v:178123.3-178124.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:175031.3-175040.6" - wire width 64 $0\src_r0$next[63:0]$12539 - attribute \src "libresoc.v:174648.3-174649.29" + attribute \src "libresoc.v:178466.3-178475.6" + wire width 64 $0\src_r0$next[63:0]$12941 + attribute \src "libresoc.v:178083.3-178084.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:175041.3-175050.6" - wire width 64 $0\src_r1$next[63:0]$12542 - attribute \src "libresoc.v:174646.3-174647.29" + attribute \src "libresoc.v:178476.3-178485.6" + wire width 64 $0\src_r1$next[63:0]$12944 + attribute \src "libresoc.v:178081.3-178082.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:175051.3-175060.6" - wire width 64 $0\src_r2$next[63:0]$12545 - attribute \src "libresoc.v:174644.3-174645.29" + attribute \src "libresoc.v:178486.3-178495.6" + wire width 64 $0\src_r2$next[63:0]$12947 + attribute \src "libresoc.v:178079.3-178080.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:175061.3-175070.6" - wire $0\src_r3$next[0:0]$12548 - attribute \src "libresoc.v:174642.3-174643.29" + attribute \src "libresoc.v:178496.3-178505.6" + wire $0\src_r3$next[0:0]$12950 + attribute \src "libresoc.v:178077.3-178078.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:175071.3-175080.6" - wire width 2 $0\src_r4$next[1:0]$12551 - attribute \src "libresoc.v:174640.3-174641.29" + attribute \src "libresoc.v:178506.3-178515.6" + wire width 2 $0\src_r4$next[1:0]$12953 + attribute \src "libresoc.v:178075.3-178076.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:175081.3-175090.6" - wire width 2 $0\src_r5$next[1:0]$12554 - attribute \src "libresoc.v:174638.3-174639.29" + attribute \src "libresoc.v:178516.3-178525.6" + wire width 2 $0\src_r5$next[1:0]$12956 + attribute \src "libresoc.v:178073.3-178074.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:174099.7-174099.24" + attribute \src "libresoc.v:177534.7-177534.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:174109.7-174109.26" + attribute \src "libresoc.v:177544.7-177544.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:175100.3-175108.6" - wire $1\alu_l_r_alu$next[0:0]$12561 - attribute \src "libresoc.v:174117.7-174117.25" + attribute \src "libresoc.v:178535.3-178543.6" + wire $1\alu_l_r_alu$next[0:0]$12963 + attribute \src "libresoc.v:177552.7-177552.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 - attribute \src "libresoc.v:174160.14-174160.48" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 + attribute \src "libresoc.v:177595.14-177595.48" wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12487 - attribute \src "libresoc.v:174164.14-174164.43" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12889 + attribute \src "libresoc.v:177599.14-177599.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 - attribute \src "libresoc.v:174242.13-174242.47" + attribute \src "libresoc.v:178321.3-178333.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 + attribute \src "libresoc.v:177677.13-177677.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:174886.3-174898.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 - attribute \src "libresoc.v:174246.7-174246.39" + attribute \src "libresoc.v:178321.3-178333.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 + attribute \src "libresoc.v:177681.7-177681.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:175091.3-175099.6" - wire $1\alui_l_r_alui$next[0:0]$12558 - attribute \src "libresoc.v:174264.7-174264.27" + attribute \src "libresoc.v:178526.3-178534.6" + wire $1\alui_l_r_alui$next[0:0]$12960 + attribute \src "libresoc.v:177699.7-177699.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:174899.3-174920.6" - wire width 64 $1\data_r0__o$next[63:0]$12493 - attribute \src "libresoc.v:174296.14-174296.47" + attribute \src "libresoc.v:178334.3-178355.6" + wire width 64 $1\data_r0__o$next[63:0]$12895 + attribute \src "libresoc.v:177731.14-177731.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:174899.3-174920.6" - wire $1\data_r0__o_ok$next[0:0]$12494 - attribute \src "libresoc.v:174300.7-174300.27" + attribute \src "libresoc.v:178334.3-178355.6" + wire $1\data_r0__o_ok$next[0:0]$12896 + attribute \src "libresoc.v:177735.7-177735.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:174921.3-174942.6" - wire width 64 $1\data_r1__spr1$next[63:0]$12501 - attribute \src "libresoc.v:174304.14-174304.50" + attribute \src "libresoc.v:178356.3-178377.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12903 + attribute \src "libresoc.v:177739.14-177739.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:174921.3-174942.6" - wire $1\data_r1__spr1_ok$next[0:0]$12502 - attribute \src "libresoc.v:174308.7-174308.30" + attribute \src "libresoc.v:178356.3-178377.6" + wire $1\data_r1__spr1_ok$next[0:0]$12904 + attribute \src "libresoc.v:177743.7-177743.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:174943.3-174964.6" - wire width 64 $1\data_r2__fast1$next[63:0]$12509 - attribute \src "libresoc.v:174312.14-174312.51" + attribute \src "libresoc.v:178378.3-178399.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12911 + attribute \src "libresoc.v:177747.14-177747.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:174943.3-174964.6" - wire $1\data_r2__fast1_ok$next[0:0]$12510 - attribute \src "libresoc.v:174316.7-174316.31" + attribute \src "libresoc.v:178378.3-178399.6" + wire $1\data_r2__fast1_ok$next[0:0]$12912 + attribute \src "libresoc.v:177751.7-177751.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:174965.3-174986.6" - wire $1\data_r3__xer_so$next[0:0]$12517 - attribute \src "libresoc.v:174320.7-174320.29" + attribute \src "libresoc.v:178400.3-178421.6" + wire $1\data_r3__xer_so$next[0:0]$12919 + attribute \src "libresoc.v:177755.7-177755.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:174965.3-174986.6" - wire $1\data_r3__xer_so_ok$next[0:0]$12518 - attribute \src "libresoc.v:174324.7-174324.32" + attribute \src "libresoc.v:178400.3-178421.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12920 + attribute \src "libresoc.v:177759.7-177759.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:174987.3-175008.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$12525 - attribute \src "libresoc.v:174328.13-174328.35" + attribute \src "libresoc.v:178422.3-178443.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12927 + attribute \src "libresoc.v:177763.13-177763.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:174987.3-175008.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$12526 - attribute \src "libresoc.v:174332.7-174332.32" + attribute \src "libresoc.v:178422.3-178443.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12928 + attribute \src "libresoc.v:177767.7-177767.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:175009.3-175030.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$12533 - attribute \src "libresoc.v:174336.13-174336.35" + attribute \src "libresoc.v:178444.3-178465.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12935 + attribute \src "libresoc.v:177771.13-177771.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:175009.3-175030.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$12534 - attribute \src "libresoc.v:174340.7-174340.32" + attribute \src "libresoc.v:178444.3-178465.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12936 + attribute \src "libresoc.v:177775.7-177775.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:175109.3-175118.6" + attribute \src "libresoc.v:178544.3-178553.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:175119.3-175128.6" + attribute \src "libresoc.v:178554.3-178563.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:175129.3-175138.6" + attribute \src "libresoc.v:178564.3-178573.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:175139.3-175148.6" + attribute \src "libresoc.v:178574.3-178583.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:175149.3-175158.6" + attribute \src "libresoc.v:178584.3-178593.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:175159.3-175168.6" + attribute \src "libresoc.v:178594.3-178603.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:174841.3-174849.6" - wire $1\opc_l_r_opc$next[0:0]$12468 - attribute \src "libresoc.v:174368.7-174368.25" + attribute \src "libresoc.v:178276.3-178284.6" + wire $1\opc_l_r_opc$next[0:0]$12870 + attribute \src "libresoc.v:177803.7-177803.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:174832.3-174840.6" - wire $1\opc_l_s_opc$next[0:0]$12465 - attribute \src "libresoc.v:174372.7-174372.25" + attribute \src "libresoc.v:178267.3-178275.6" + wire $1\opc_l_s_opc$next[0:0]$12867 + attribute \src "libresoc.v:177807.7-177807.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:175169.3-175177.6" - wire width 6 $1\prev_wr_go$next[5:0]$12570 - attribute \src "libresoc.v:174471.13-174471.31" + attribute \src "libresoc.v:178604.3-178612.6" + wire width 6 $1\prev_wr_go$next[5:0]$12972 + attribute \src "libresoc.v:177906.13-177906.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:174786.3-174795.6" + attribute \src "libresoc.v:178221.3-178230.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:174877.3-174885.6" - wire width 6 $1\req_l_r_req$next[5:0]$12480 - attribute \src "libresoc.v:174479.13-174479.32" + attribute \src "libresoc.v:178312.3-178320.6" + wire width 6 $1\req_l_r_req$next[5:0]$12882 + attribute \src "libresoc.v:177914.13-177914.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:174868.3-174876.6" - wire width 6 $1\req_l_s_req$next[5:0]$12477 - attribute \src "libresoc.v:174483.13-174483.32" + attribute \src "libresoc.v:178303.3-178311.6" + wire width 6 $1\req_l_s_req$next[5:0]$12879 + attribute \src "libresoc.v:177918.13-177918.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:174805.3-174813.6" - wire $1\rok_l_r_rdok$next[0:0]$12456 - attribute \src "libresoc.v:174495.7-174495.26" + attribute \src "libresoc.v:178240.3-178248.6" + wire $1\rok_l_r_rdok$next[0:0]$12858 + attribute \src "libresoc.v:177930.7-177930.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:174796.3-174804.6" - wire $1\rok_l_s_rdok$next[0:0]$12453 - attribute \src "libresoc.v:174499.7-174499.26" + attribute \src "libresoc.v:178231.3-178239.6" + wire $1\rok_l_s_rdok$next[0:0]$12855 + attribute \src "libresoc.v:177934.7-177934.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:174823.3-174831.6" - wire $1\rst_l_r_rst$next[0:0]$12462 - attribute \src "libresoc.v:174503.7-174503.25" + attribute \src "libresoc.v:178258.3-178266.6" + wire $1\rst_l_r_rst$next[0:0]$12864 + attribute \src "libresoc.v:177938.7-177938.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:174814.3-174822.6" - wire $1\rst_l_s_rst$next[0:0]$12459 - attribute \src "libresoc.v:174507.7-174507.25" + attribute \src "libresoc.v:178249.3-178257.6" + wire $1\rst_l_s_rst$next[0:0]$12861 + attribute \src "libresoc.v:177942.7-177942.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:174859.3-174867.6" - wire width 6 $1\src_l_r_src$next[5:0]$12474 - attribute \src "libresoc.v:174529.13-174529.32" + attribute \src "libresoc.v:178294.3-178302.6" + wire width 6 $1\src_l_r_src$next[5:0]$12876 + attribute \src "libresoc.v:177964.13-177964.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:174850.3-174858.6" - wire width 6 $1\src_l_s_src$next[5:0]$12471 - attribute \src "libresoc.v:174533.13-174533.32" + attribute \src "libresoc.v:178285.3-178293.6" + wire width 6 $1\src_l_s_src$next[5:0]$12873 + attribute \src "libresoc.v:177968.13-177968.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:175031.3-175040.6" - wire width 64 $1\src_r0$next[63:0]$12540 - attribute \src "libresoc.v:174537.14-174537.43" + attribute \src "libresoc.v:178466.3-178475.6" + wire width 64 $1\src_r0$next[63:0]$12942 + attribute \src "libresoc.v:177972.14-177972.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:175041.3-175050.6" - wire width 64 $1\src_r1$next[63:0]$12543 - attribute \src "libresoc.v:174541.14-174541.43" + attribute \src "libresoc.v:178476.3-178485.6" + wire width 64 $1\src_r1$next[63:0]$12945 + attribute \src "libresoc.v:177976.14-177976.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:175051.3-175060.6" - wire width 64 $1\src_r2$next[63:0]$12546 - attribute \src "libresoc.v:174545.14-174545.43" + attribute \src "libresoc.v:178486.3-178495.6" + wire width 64 $1\src_r2$next[63:0]$12948 + attribute \src "libresoc.v:177980.14-177980.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:175061.3-175070.6" - wire $1\src_r3$next[0:0]$12549 - attribute \src "libresoc.v:174549.7-174549.20" + attribute \src "libresoc.v:178496.3-178505.6" + wire $1\src_r3$next[0:0]$12951 + attribute \src "libresoc.v:177984.7-177984.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:175071.3-175080.6" - wire width 2 $1\src_r4$next[1:0]$12552 - attribute \src "libresoc.v:174553.13-174553.26" + attribute \src "libresoc.v:178506.3-178515.6" + wire width 2 $1\src_r4$next[1:0]$12954 + attribute \src "libresoc.v:177988.13-177988.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:175081.3-175090.6" - wire width 2 $1\src_r5$next[1:0]$12555 - attribute \src "libresoc.v:174557.13-174557.26" + attribute \src "libresoc.v:178516.3-178525.6" + wire width 2 $1\src_r5$next[1:0]$12957 + attribute \src "libresoc.v:177992.13-177992.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:174899.3-174920.6" - wire width 64 $2\data_r0__o$next[63:0]$12495 - attribute \src "libresoc.v:174899.3-174920.6" - wire $2\data_r0__o_ok$next[0:0]$12496 - attribute \src "libresoc.v:174921.3-174942.6" - wire width 64 $2\data_r1__spr1$next[63:0]$12503 - attribute \src "libresoc.v:174921.3-174942.6" - wire $2\data_r1__spr1_ok$next[0:0]$12504 - attribute \src "libresoc.v:174943.3-174964.6" - wire width 64 $2\data_r2__fast1$next[63:0]$12511 - attribute \src "libresoc.v:174943.3-174964.6" - wire $2\data_r2__fast1_ok$next[0:0]$12512 - attribute \src "libresoc.v:174965.3-174986.6" - wire $2\data_r3__xer_so$next[0:0]$12519 - attribute \src "libresoc.v:174965.3-174986.6" - wire $2\data_r3__xer_so_ok$next[0:0]$12520 - attribute \src "libresoc.v:174987.3-175008.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$12527 - attribute \src "libresoc.v:174987.3-175008.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$12528 - attribute \src "libresoc.v:175009.3-175030.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$12535 - attribute \src "libresoc.v:175009.3-175030.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$12536 - attribute \src "libresoc.v:174899.3-174920.6" - wire $3\data_r0__o_ok$next[0:0]$12497 - attribute \src "libresoc.v:174921.3-174942.6" - wire $3\data_r1__spr1_ok$next[0:0]$12505 - attribute \src "libresoc.v:174943.3-174964.6" - wire $3\data_r2__fast1_ok$next[0:0]$12513 - attribute \src "libresoc.v:174965.3-174986.6" - wire $3\data_r3__xer_so_ok$next[0:0]$12521 - attribute \src "libresoc.v:174987.3-175008.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$12529 - attribute \src "libresoc.v:175009.3-175030.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$12537 - attribute \src "libresoc.v:174569.19-174569.133" - wire $and$libresoc.v:174569$12348_Y - attribute \src "libresoc.v:174570.19-174570.183" - wire width 6 $and$libresoc.v:174570$12349_Y - attribute \src "libresoc.v:174571.19-174571.115" - wire width 6 $and$libresoc.v:174571$12350_Y - attribute \src "libresoc.v:174573.19-174573.115" - wire width 6 $and$libresoc.v:174573$12352_Y - attribute \src "libresoc.v:174574.19-174574.125" - wire $and$libresoc.v:174574$12353_Y - attribute \src "libresoc.v:174575.19-174575.125" - wire $and$libresoc.v:174575$12354_Y - attribute \src "libresoc.v:174576.19-174576.125" - wire $and$libresoc.v:174576$12355_Y - attribute \src "libresoc.v:174577.19-174577.125" - wire $and$libresoc.v:174577$12356_Y - attribute \src "libresoc.v:174578.19-174578.125" - wire $and$libresoc.v:174578$12357_Y - attribute \src "libresoc.v:174580.19-174580.125" - wire $and$libresoc.v:174580$12359_Y - attribute \src "libresoc.v:174581.19-174581.165" - wire width 6 $and$libresoc.v:174581$12360_Y - attribute \src "libresoc.v:174582.19-174582.121" - wire width 6 $and$libresoc.v:174582$12361_Y - attribute \src "libresoc.v:174583.19-174583.127" - wire $and$libresoc.v:174583$12362_Y - attribute \src "libresoc.v:174584.19-174584.127" - wire $and$libresoc.v:174584$12363_Y - attribute \src "libresoc.v:174586.19-174586.127" - wire $and$libresoc.v:174586$12365_Y - attribute \src "libresoc.v:174587.19-174587.127" - wire $and$libresoc.v:174587$12366_Y - attribute \src "libresoc.v:174588.19-174588.127" - wire $and$libresoc.v:174588$12367_Y - attribute \src "libresoc.v:174589.19-174589.127" - wire $and$libresoc.v:174589$12368_Y - attribute \src "libresoc.v:174590.18-174590.110" - wire $and$libresoc.v:174590$12369_Y - attribute \src "libresoc.v:174592.18-174592.98" - wire $and$libresoc.v:174592$12371_Y - attribute \src "libresoc.v:174594.18-174594.100" - wire $and$libresoc.v:174594$12373_Y - attribute \src "libresoc.v:174595.18-174595.182" - wire width 6 $and$libresoc.v:174595$12374_Y - attribute \src "libresoc.v:174597.18-174597.119" - wire width 6 $and$libresoc.v:174597$12376_Y - attribute \src "libresoc.v:174600.18-174600.116" - wire $and$libresoc.v:174600$12379_Y - attribute \src "libresoc.v:174605.18-174605.113" - wire $and$libresoc.v:174605$12384_Y - attribute \src "libresoc.v:174606.18-174606.125" - wire width 6 $and$libresoc.v:174606$12385_Y - attribute \src "libresoc.v:174608.18-174608.112" - wire $and$libresoc.v:174608$12387_Y - attribute \src "libresoc.v:174610.18-174610.126" - wire $and$libresoc.v:174610$12389_Y - attribute \src "libresoc.v:174611.18-174611.126" - wire $and$libresoc.v:174611$12390_Y - attribute \src "libresoc.v:174612.18-174612.117" - wire $and$libresoc.v:174612$12391_Y - attribute \src "libresoc.v:174617.18-174617.130" - wire $and$libresoc.v:174617$12396_Y - attribute \src "libresoc.v:174618.17-174618.123" - wire $and$libresoc.v:174618$12397_Y - attribute \src "libresoc.v:174619.18-174619.124" - wire width 6 $and$libresoc.v:174619$12398_Y - attribute \src "libresoc.v:174621.18-174621.116" - wire $and$libresoc.v:174621$12400_Y - attribute \src "libresoc.v:174622.18-174622.119" - wire $and$libresoc.v:174622$12401_Y - attribute \src "libresoc.v:174623.18-174623.120" - wire $and$libresoc.v:174623$12402_Y - attribute \src "libresoc.v:174624.18-174624.121" - wire $and$libresoc.v:174624$12403_Y - attribute \src "libresoc.v:174625.18-174625.121" - wire $and$libresoc.v:174625$12404_Y - attribute \src "libresoc.v:174626.18-174626.121" - wire $and$libresoc.v:174626$12405_Y - attribute \src "libresoc.v:174633.18-174633.134" - wire $and$libresoc.v:174633$12412_Y - attribute \src "libresoc.v:174607.18-174607.113" - wire $eq$libresoc.v:174607$12386_Y - attribute \src "libresoc.v:174609.18-174609.119" - wire $eq$libresoc.v:174609$12388_Y - attribute \src "libresoc.v:174568.17-174568.113" - wire width 6 $not$libresoc.v:174568$12347_Y - attribute \src "libresoc.v:174572.19-174572.115" - wire width 6 $not$libresoc.v:174572$12351_Y - attribute \src "libresoc.v:174591.18-174591.97" - wire $not$libresoc.v:174591$12370_Y - attribute \src "libresoc.v:174593.18-174593.99" - wire $not$libresoc.v:174593$12372_Y - attribute \src "libresoc.v:174596.18-174596.113" - wire width 6 $not$libresoc.v:174596$12375_Y - attribute \src "libresoc.v:174599.18-174599.106" - wire $not$libresoc.v:174599$12378_Y - attribute \src "libresoc.v:174604.18-174604.120" - wire $not$libresoc.v:174604$12383_Y - attribute \src "libresoc.v:174579.18-174579.118" - wire width 6 $or$libresoc.v:174579$12358_Y - attribute \src "libresoc.v:174603.18-174603.112" - wire $or$libresoc.v:174603$12382_Y - attribute \src "libresoc.v:174613.18-174613.122" - wire $or$libresoc.v:174613$12392_Y - attribute \src "libresoc.v:174614.18-174614.124" - wire $or$libresoc.v:174614$12393_Y - attribute \src "libresoc.v:174615.18-174615.194" - wire width 6 $or$libresoc.v:174615$12394_Y - attribute \src "libresoc.v:174616.18-174616.194" - wire width 6 $or$libresoc.v:174616$12395_Y - attribute \src "libresoc.v:174620.18-174620.120" - wire width 6 $or$libresoc.v:174620$12399_Y - attribute \src "libresoc.v:174585.17-174585.105" - wire $reduce_and$libresoc.v:174585$12364_Y - attribute \src "libresoc.v:174598.18-174598.106" - wire $reduce_or$libresoc.v:174598$12377_Y - attribute \src "libresoc.v:174601.18-174601.113" - wire $reduce_or$libresoc.v:174601$12380_Y - attribute \src "libresoc.v:174602.18-174602.112" - wire $reduce_or$libresoc.v:174602$12381_Y - attribute \src "libresoc.v:174627.18-174627.118" - wire width 64 $ternary$libresoc.v:174627$12406_Y - attribute \src "libresoc.v:174628.18-174628.118" - wire width 64 $ternary$libresoc.v:174628$12407_Y - attribute \src "libresoc.v:174629.18-174629.118" - wire width 64 $ternary$libresoc.v:174629$12408_Y - attribute \src "libresoc.v:174630.18-174630.118" - wire $ternary$libresoc.v:174630$12409_Y - attribute \src "libresoc.v:174631.18-174631.118" - wire width 2 $ternary$libresoc.v:174631$12410_Y - attribute \src "libresoc.v:174632.18-174632.118" - wire width 2 $ternary$libresoc.v:174632$12411_Y + attribute \src "libresoc.v:178334.3-178355.6" + wire width 64 $2\data_r0__o$next[63:0]$12897 + attribute \src "libresoc.v:178334.3-178355.6" + wire $2\data_r0__o_ok$next[0:0]$12898 + attribute \src "libresoc.v:178356.3-178377.6" + wire width 64 $2\data_r1__spr1$next[63:0]$12905 + attribute \src "libresoc.v:178356.3-178377.6" + wire $2\data_r1__spr1_ok$next[0:0]$12906 + attribute \src "libresoc.v:178378.3-178399.6" + wire width 64 $2\data_r2__fast1$next[63:0]$12913 + attribute \src "libresoc.v:178378.3-178399.6" + wire $2\data_r2__fast1_ok$next[0:0]$12914 + attribute \src "libresoc.v:178400.3-178421.6" + wire $2\data_r3__xer_so$next[0:0]$12921 + attribute \src "libresoc.v:178400.3-178421.6" + wire $2\data_r3__xer_so_ok$next[0:0]$12922 + attribute \src "libresoc.v:178422.3-178443.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$12929 + attribute \src "libresoc.v:178422.3-178443.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$12930 + attribute \src "libresoc.v:178444.3-178465.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$12937 + attribute \src "libresoc.v:178444.3-178465.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$12938 + attribute \src "libresoc.v:178334.3-178355.6" + wire $3\data_r0__o_ok$next[0:0]$12899 + attribute \src "libresoc.v:178356.3-178377.6" + wire $3\data_r1__spr1_ok$next[0:0]$12907 + attribute \src "libresoc.v:178378.3-178399.6" + wire $3\data_r2__fast1_ok$next[0:0]$12915 + attribute \src "libresoc.v:178400.3-178421.6" + wire $3\data_r3__xer_so_ok$next[0:0]$12923 + attribute \src "libresoc.v:178422.3-178443.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$12931 + attribute \src "libresoc.v:178444.3-178465.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$12939 + attribute \src "libresoc.v:178004.19-178004.133" + wire $and$libresoc.v:178004$12750_Y + attribute \src "libresoc.v:178005.19-178005.183" + wire width 6 $and$libresoc.v:178005$12751_Y + attribute \src "libresoc.v:178006.19-178006.115" + wire width 6 $and$libresoc.v:178006$12752_Y + attribute \src "libresoc.v:178008.19-178008.115" + wire width 6 $and$libresoc.v:178008$12754_Y + attribute \src "libresoc.v:178009.19-178009.125" + wire $and$libresoc.v:178009$12755_Y + attribute \src "libresoc.v:178010.19-178010.125" + wire $and$libresoc.v:178010$12756_Y + attribute \src "libresoc.v:178011.19-178011.125" + wire $and$libresoc.v:178011$12757_Y + attribute \src "libresoc.v:178012.19-178012.125" + wire $and$libresoc.v:178012$12758_Y + attribute \src "libresoc.v:178013.19-178013.125" + wire $and$libresoc.v:178013$12759_Y + attribute \src "libresoc.v:178015.19-178015.125" + wire $and$libresoc.v:178015$12761_Y + attribute \src "libresoc.v:178016.19-178016.165" + wire width 6 $and$libresoc.v:178016$12762_Y + attribute \src "libresoc.v:178017.19-178017.121" + wire width 6 $and$libresoc.v:178017$12763_Y + attribute \src "libresoc.v:178018.19-178018.127" + wire $and$libresoc.v:178018$12764_Y + attribute \src "libresoc.v:178019.19-178019.127" + wire $and$libresoc.v:178019$12765_Y + attribute \src "libresoc.v:178021.19-178021.127" + wire $and$libresoc.v:178021$12767_Y + attribute \src "libresoc.v:178022.19-178022.127" + wire $and$libresoc.v:178022$12768_Y + attribute \src "libresoc.v:178023.19-178023.127" + wire $and$libresoc.v:178023$12769_Y + attribute \src "libresoc.v:178024.19-178024.127" + wire $and$libresoc.v:178024$12770_Y + attribute \src "libresoc.v:178025.18-178025.110" + wire $and$libresoc.v:178025$12771_Y + attribute \src "libresoc.v:178027.18-178027.98" + wire $and$libresoc.v:178027$12773_Y + attribute \src "libresoc.v:178029.18-178029.100" + wire $and$libresoc.v:178029$12775_Y + attribute \src "libresoc.v:178030.18-178030.182" + wire width 6 $and$libresoc.v:178030$12776_Y + attribute \src "libresoc.v:178032.18-178032.119" + wire width 6 $and$libresoc.v:178032$12778_Y + attribute \src "libresoc.v:178035.18-178035.116" + wire $and$libresoc.v:178035$12781_Y + attribute \src "libresoc.v:178040.18-178040.113" + wire $and$libresoc.v:178040$12786_Y + attribute \src "libresoc.v:178041.18-178041.125" + wire width 6 $and$libresoc.v:178041$12787_Y + attribute \src "libresoc.v:178043.18-178043.112" + wire $and$libresoc.v:178043$12789_Y + attribute \src "libresoc.v:178045.18-178045.126" + wire $and$libresoc.v:178045$12791_Y + attribute \src "libresoc.v:178046.18-178046.126" + wire $and$libresoc.v:178046$12792_Y + attribute \src "libresoc.v:178047.18-178047.117" + wire $and$libresoc.v:178047$12793_Y + attribute \src "libresoc.v:178052.18-178052.130" + wire $and$libresoc.v:178052$12798_Y + attribute \src "libresoc.v:178053.17-178053.123" + wire $and$libresoc.v:178053$12799_Y + attribute \src "libresoc.v:178054.18-178054.124" + wire width 6 $and$libresoc.v:178054$12800_Y + attribute \src "libresoc.v:178056.18-178056.116" + wire $and$libresoc.v:178056$12802_Y + attribute \src "libresoc.v:178057.18-178057.119" + wire $and$libresoc.v:178057$12803_Y + attribute \src "libresoc.v:178058.18-178058.120" + wire $and$libresoc.v:178058$12804_Y + attribute \src "libresoc.v:178059.18-178059.121" + wire $and$libresoc.v:178059$12805_Y + attribute \src "libresoc.v:178060.18-178060.121" + wire $and$libresoc.v:178060$12806_Y + attribute \src "libresoc.v:178061.18-178061.121" + wire $and$libresoc.v:178061$12807_Y + attribute \src "libresoc.v:178068.18-178068.134" + wire $and$libresoc.v:178068$12814_Y + attribute \src "libresoc.v:178042.18-178042.113" + wire $eq$libresoc.v:178042$12788_Y + attribute \src "libresoc.v:178044.18-178044.119" + wire $eq$libresoc.v:178044$12790_Y + attribute \src "libresoc.v:178003.17-178003.113" + wire width 6 $not$libresoc.v:178003$12749_Y + attribute \src "libresoc.v:178007.19-178007.115" + wire width 6 $not$libresoc.v:178007$12753_Y + attribute \src "libresoc.v:178026.18-178026.97" + wire $not$libresoc.v:178026$12772_Y + attribute \src "libresoc.v:178028.18-178028.99" + wire $not$libresoc.v:178028$12774_Y + attribute \src "libresoc.v:178031.18-178031.113" + wire width 6 $not$libresoc.v:178031$12777_Y + attribute \src "libresoc.v:178034.18-178034.106" + wire $not$libresoc.v:178034$12780_Y + attribute \src "libresoc.v:178039.18-178039.120" + wire $not$libresoc.v:178039$12785_Y + attribute \src "libresoc.v:178014.18-178014.118" + wire width 6 $or$libresoc.v:178014$12760_Y + attribute \src "libresoc.v:178038.18-178038.112" + wire $or$libresoc.v:178038$12784_Y + attribute \src "libresoc.v:178048.18-178048.122" + wire $or$libresoc.v:178048$12794_Y + attribute \src "libresoc.v:178049.18-178049.124" + wire $or$libresoc.v:178049$12795_Y + attribute \src "libresoc.v:178050.18-178050.194" + wire width 6 $or$libresoc.v:178050$12796_Y + attribute \src "libresoc.v:178051.18-178051.194" + wire width 6 $or$libresoc.v:178051$12797_Y + attribute \src "libresoc.v:178055.18-178055.120" + wire width 6 $or$libresoc.v:178055$12801_Y + attribute \src "libresoc.v:178020.17-178020.105" + wire $reduce_and$libresoc.v:178020$12766_Y + attribute \src "libresoc.v:178033.18-178033.106" + wire $reduce_or$libresoc.v:178033$12779_Y + attribute \src "libresoc.v:178036.18-178036.113" + wire $reduce_or$libresoc.v:178036$12782_Y + attribute \src "libresoc.v:178037.18-178037.112" + wire $reduce_or$libresoc.v:178037$12783_Y + attribute \src "libresoc.v:178062.18-178062.118" + wire width 64 $ternary$libresoc.v:178062$12808_Y + attribute \src "libresoc.v:178063.18-178063.118" + wire width 64 $ternary$libresoc.v:178063$12809_Y + attribute \src "libresoc.v:178064.18-178064.118" + wire width 64 $ternary$libresoc.v:178064$12810_Y + attribute \src "libresoc.v:178065.18-178065.118" + wire $ternary$libresoc.v:178065$12811_Y + attribute \src "libresoc.v:178066.18-178066.118" + wire width 2 $ternary$libresoc.v:178066$12812_Y + attribute \src "libresoc.v:178067.18-178067.118" + wire width 2 $ternary$libresoc.v:178067$12813_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -365081,7 +373047,7 @@ module \spr0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 6 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_spr0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_fast1$2 @@ -365089,7 +373055,7 @@ module \spr0 wire \alu_spr0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_spr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_spr0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_spr0_p_ready_o @@ -365097,7 +373063,7 @@ module \spr0 wire \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_spr0_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_spr0_spr1$1 @@ -365204,15 +373170,15 @@ module \spr0 wire \alu_spr0_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_spr0_spr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_spr0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 \alu_spr0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \alu_spr0_xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \alu_spr0_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \alu_spr0_xer_so$3 @@ -365224,30 +373190,30 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 6 \cu_busy_o + wire output 7 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 5 \cu_issue_i + wire input 6 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 9 \cu_rd__go_i + wire width 6 input 10 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 8 \cu_rd__rel_o + wire width 6 output 9 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 7 \cu_rdmaskn_i + wire width 6 input 8 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 18 \cu_wr__go_i + wire width 6 input 19 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 17 \cu_wr__rel_o + wire width 6 output 18 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 6 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -365299,23 +373265,23 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r5__xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 19 \dest1_o + wire width 64 output 20 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest2_o + wire width 64 output 30 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 27 \dest3_o + wire width 64 output 28 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 25 \dest4_o + wire output 26 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 23 \dest5_o + wire width 2 output 24 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 21 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \fast1_ok - attribute \src "libresoc.v:173963.7-173963.15" + wire width 2 output 22 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok + attribute \src "libresoc.v:177398.7-177398.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 16 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -365340,9 +373306,9 @@ module \spr0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_spr0__fn_unit + wire width 12 input 3 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_spr0__insn + wire width 32 input 4 \oper_i_alu_spr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -365418,9 +373384,9 @@ module \spr0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_spr0__insn_type + wire width 7 input 2 \oper_i_alu_spr0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \oper_i_alu_spr0__is_32bit + wire input 5 \oper_i_alu_spr0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 6 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -365463,20 +373429,20 @@ module \spr0 wire \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 10 \src1_i + wire width 64 input 11 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src2_i + wire width 64 input 16 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 14 \src3_i + wire width 64 input 15 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 11 \src4_i + wire input 12 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 13 \src5_i + wire width 2 input 14 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 12 \src6_i + wire width 2 input 13 \src6_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -365513,14 +373479,14 @@ module \spr0 wire width 2 \src_r5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 20 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 24 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:174569$12348 + cell $and $and$libresoc.v:178004$12750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365528,10 +373494,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:174569$12348_Y + connect \Y $and$libresoc.v:178004$12750_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:174570$12349 + cell $and $and$libresoc.v:178005$12751 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365539,10 +373505,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:174570$12349_Y + connect \Y $and$libresoc.v:178005$12751_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:174571$12350 + cell $and $and$libresoc.v:178006$12752 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365550,10 +373516,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:174571$12350_Y + connect \Y $and$libresoc.v:178006$12752_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:174573$12352 + cell $and $and$libresoc.v:178008$12754 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365561,10 +373527,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:174573$12352_Y + connect \Y $and$libresoc.v:178008$12754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174574$12353 + cell $and $and$libresoc.v:178009$12755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365572,10 +373538,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174574$12353_Y + connect \Y $and$libresoc.v:178009$12755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174575$12354 + cell $and $and$libresoc.v:178010$12756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365583,10 +373549,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174575$12354_Y + connect \Y $and$libresoc.v:178010$12756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174576$12355 + cell $and $and$libresoc.v:178011$12757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365594,10 +373560,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174576$12355_Y + connect \Y $and$libresoc.v:178011$12757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174577$12356 + cell $and $and$libresoc.v:178012$12758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365605,10 +373571,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174577$12356_Y + connect \Y $and$libresoc.v:178012$12758_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174578$12357 + cell $and $and$libresoc.v:178013$12759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365616,10 +373582,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174578$12357_Y + connect \Y $and$libresoc.v:178013$12759_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:174580$12359 + cell $and $and$libresoc.v:178015$12761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365627,10 +373593,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:174580$12359_Y + connect \Y $and$libresoc.v:178015$12761_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:174581$12360 + cell $and $and$libresoc.v:178016$12762 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365638,10 +373604,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:174581$12360_Y + connect \Y $and$libresoc.v:178016$12762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:174582$12361 + cell $and $and$libresoc.v:178017$12763 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365649,10 +373615,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:174582$12361_Y + connect \Y $and$libresoc.v:178017$12763_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174583$12362 + cell $and $and$libresoc.v:178018$12764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365660,10 +373626,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174583$12362_Y + connect \Y $and$libresoc.v:178018$12764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174584$12363 + cell $and $and$libresoc.v:178019$12765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365671,10 +373637,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174584$12363_Y + connect \Y $and$libresoc.v:178019$12765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174586$12365 + cell $and $and$libresoc.v:178021$12767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365682,10 +373648,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174586$12365_Y + connect \Y $and$libresoc.v:178021$12767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174587$12366 + cell $and $and$libresoc.v:178022$12768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365693,10 +373659,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174587$12366_Y + connect \Y $and$libresoc.v:178022$12768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174588$12367 + cell $and $and$libresoc.v:178023$12769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365704,10 +373670,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174588$12367_Y + connect \Y $and$libresoc.v:178023$12769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:174589$12368 + cell $and $and$libresoc.v:178024$12770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365715,10 +373681,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:174589$12368_Y + connect \Y $and$libresoc.v:178024$12770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:174590$12369 + cell $and $and$libresoc.v:178025$12771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365726,10 +373692,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:174590$12369_Y + connect \Y $and$libresoc.v:178025$12771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:174592$12371 + cell $and $and$libresoc.v:178027$12773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365737,10 +373703,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:174592$12371_Y + connect \Y $and$libresoc.v:178027$12773_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:174594$12373 + cell $and $and$libresoc.v:178029$12775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365748,10 +373714,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:174594$12373_Y + connect \Y $and$libresoc.v:178029$12775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:174595$12374 + cell $and $and$libresoc.v:178030$12776 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365759,10 +373725,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:174595$12374_Y + connect \Y $and$libresoc.v:178030$12776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:174597$12376 + cell $and $and$libresoc.v:178032$12778 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365770,10 +373736,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:174597$12376_Y + connect \Y $and$libresoc.v:178032$12778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:174600$12379 + cell $and $and$libresoc.v:178035$12781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365781,10 +373747,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:174600$12379_Y + connect \Y $and$libresoc.v:178035$12781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:174605$12384 + cell $and $and$libresoc.v:178040$12786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365792,10 +373758,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:174605$12384_Y + connect \Y $and$libresoc.v:178040$12786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:174606$12385 + cell $and $and$libresoc.v:178041$12787 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365803,10 +373769,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:174606$12385_Y + connect \Y $and$libresoc.v:178041$12787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:174608$12387 + cell $and $and$libresoc.v:178043$12789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365814,10 +373780,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:174608$12387_Y + connect \Y $and$libresoc.v:178043$12789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:174610$12389 + cell $and $and$libresoc.v:178045$12791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365825,10 +373791,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:174610$12389_Y + connect \Y $and$libresoc.v:178045$12791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:174611$12390 + cell $and $and$libresoc.v:178046$12792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365836,10 +373802,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:174611$12390_Y + connect \Y $and$libresoc.v:178046$12792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:174612$12391 + cell $and $and$libresoc.v:178047$12793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365847,10 +373813,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:174612$12391_Y + connect \Y $and$libresoc.v:178047$12793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:174617$12396 + cell $and $and$libresoc.v:178052$12798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365858,10 +373824,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:174617$12396_Y + connect \Y $and$libresoc.v:178052$12798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:174618$12397 + cell $and $and$libresoc.v:178053$12799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365869,10 +373835,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:174618$12397_Y + connect \Y $and$libresoc.v:178053$12799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:174619$12398 + cell $and $and$libresoc.v:178054$12800 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365880,10 +373846,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:174619$12398_Y + connect \Y $and$libresoc.v:178054$12800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174621$12400 + cell $and $and$libresoc.v:178056$12802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365891,10 +373857,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174621$12400_Y + connect \Y $and$libresoc.v:178056$12802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174622$12401 + cell $and $and$libresoc.v:178057$12803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365902,10 +373868,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174622$12401_Y + connect \Y $and$libresoc.v:178057$12803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174623$12402 + cell $and $and$libresoc.v:178058$12804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365913,10 +373879,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174623$12402_Y + connect \Y $and$libresoc.v:178058$12804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174624$12403 + cell $and $and$libresoc.v:178059$12805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365924,10 +373890,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174624$12403_Y + connect \Y $and$libresoc.v:178059$12805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174625$12404 + cell $and $and$libresoc.v:178060$12806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365935,10 +373901,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174625$12404_Y + connect \Y $and$libresoc.v:178060$12806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:174626$12405 + cell $and $and$libresoc.v:178061$12807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365946,10 +373912,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:174626$12405_Y + connect \Y $and$libresoc.v:178061$12807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:174633$12412 + cell $and $and$libresoc.v:178068$12814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -365957,10 +373923,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:174633$12412_Y + connect \Y $and$libresoc.v:178068$12814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:174607$12386 + cell $eq $eq$libresoc.v:178042$12788 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365968,10 +373934,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:174607$12386_Y + connect \Y $eq$libresoc.v:178042$12788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:174609$12388 + cell $eq $eq$libresoc.v:178044$12790 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -365979,66 +373945,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:174609$12388_Y + connect \Y $eq$libresoc.v:178044$12790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:174568$12347 + cell $not $not$libresoc.v:178003$12749 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:174568$12347_Y + connect \Y $not$libresoc.v:178003$12749_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:174572$12351 + cell $not $not$libresoc.v:178007$12753 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:174572$12351_Y + connect \Y $not$libresoc.v:178007$12753_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:174591$12370 + cell $not $not$libresoc.v:178026$12772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:174591$12370_Y + connect \Y $not$libresoc.v:178026$12772_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:174593$12372 + cell $not $not$libresoc.v:178028$12774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:174593$12372_Y + connect \Y $not$libresoc.v:178028$12774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:174596$12375 + cell $not $not$libresoc.v:178031$12777 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:174596$12375_Y + connect \Y $not$libresoc.v:178031$12777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:174599$12378 + cell $not $not$libresoc.v:178034$12780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:174599$12378_Y + connect \Y $not$libresoc.v:178034$12780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:174604$12383 + cell $not $not$libresoc.v:178039$12785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:174604$12383_Y + connect \Y $not$libresoc.v:178039$12785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:174579$12358 + cell $or $or$libresoc.v:178014$12760 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366046,10 +374012,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:174579$12358_Y + connect \Y $or$libresoc.v:178014$12760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:174603$12382 + cell $or $or$libresoc.v:178038$12784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366057,10 +374023,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:174603$12382_Y + connect \Y $or$libresoc.v:178038$12784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:174613$12392 + cell $or $or$libresoc.v:178048$12794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366068,10 +374034,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:174613$12392_Y + connect \Y $or$libresoc.v:178048$12794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:174614$12393 + cell $or $or$libresoc.v:178049$12795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -366079,10 +374045,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:174614$12393_Y + connect \Y $or$libresoc.v:178049$12795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:174615$12394 + cell $or $or$libresoc.v:178050$12796 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366090,10 +374056,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:174615$12394_Y + connect \Y $or$libresoc.v:178050$12796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:174616$12395 + cell $or $or$libresoc.v:178051$12797 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366101,10 +374067,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:174616$12395_Y + connect \Y $or$libresoc.v:178051$12797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:174620$12399 + cell $or $or$libresoc.v:178055$12801 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -366112,91 +374078,91 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:174620$12399_Y + connect \Y $or$libresoc.v:178055$12801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:174585$12364 + cell $reduce_and $reduce_and$libresoc.v:178020$12766 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:174585$12364_Y + connect \Y $reduce_and$libresoc.v:178020$12766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:174598$12377 + cell $reduce_or $reduce_or$libresoc.v:178033$12779 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:174598$12377_Y + connect \Y $reduce_or$libresoc.v:178033$12779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:174601$12380 + cell $reduce_or $reduce_or$libresoc.v:178036$12782 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:174601$12380_Y + connect \Y $reduce_or$libresoc.v:178036$12782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:174602$12381 + cell $reduce_or $reduce_or$libresoc.v:178037$12783 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:174602$12381_Y + connect \Y $reduce_or$libresoc.v:178037$12783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174627$12406 + cell $mux $ternary$libresoc.v:178062$12808 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:174627$12406_Y + connect \Y $ternary$libresoc.v:178062$12808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174628$12407 + cell $mux $ternary$libresoc.v:178063$12809 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:174628$12407_Y + connect \Y $ternary$libresoc.v:178063$12809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174629$12408 + cell $mux $ternary$libresoc.v:178064$12810 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:174629$12408_Y + connect \Y $ternary$libresoc.v:178064$12810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174630$12409 + cell $mux $ternary$libresoc.v:178065$12811 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:174630$12409_Y + connect \Y $ternary$libresoc.v:178065$12811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174631$12410 + cell $mux $ternary$libresoc.v:178066$12812 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:174631$12410_Y + connect \Y $ternary$libresoc.v:178066$12812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:174632$12411 + cell $mux $ternary$libresoc.v:178067$12813 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:174632$12411_Y + connect \Y $ternary$libresoc.v:178067$12813_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174708.14-174714.4" - cell \alu_l$70 \alu_l + attribute \src "libresoc.v:178143.14-178149.4" + cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -366204,7 +374170,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:174715.12-174744.4" + attribute \src "libresoc.v:178150.12-178179.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -366236,8 +374202,8 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:174745.15-174751.4" - cell \alui_l$69 \alui_l + attribute \src "libresoc.v:178180.15-178186.4" + cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -366245,8 +374211,8 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:174752.14-174758.4" - cell \opc_l$65 \opc_l + attribute \src "libresoc.v:178187.14-178193.4" + cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -366254,8 +374220,8 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:174759.14-174765.4" - cell \req_l$66 \req_l + attribute \src "libresoc.v:178194.14-178200.4" + cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -366263,8 +374229,8 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:174766.14-174772.4" - cell \rok_l$68 \rok_l + attribute \src "libresoc.v:178201.14-178207.4" + cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -366272,593 +374238,593 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:174773.14-174778.4" - cell \rst_l$67 \rst_l + attribute \src "libresoc.v:178208.14-178213.4" + cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:174779.14-174785.4" - cell \src_l$64 \src_l + attribute \src "libresoc.v:178214.14-178220.4" + cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:173963.7-173963.20" - process $proc$libresoc.v:173963$12571 + attribute \src "libresoc.v:177398.7-177398.20" + process $proc$libresoc.v:177398$12973 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174099.7-174099.24" - process $proc$libresoc.v:174099$12572 + attribute \src "libresoc.v:177534.7-177534.24" + process $proc$libresoc.v:177534$12974 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:174109.7-174109.26" - process $proc$libresoc.v:174109$12573 + attribute \src "libresoc.v:177544.7-177544.26" + process $proc$libresoc.v:177544$12975 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:174117.7-174117.25" - process $proc$libresoc.v:174117$12574 + attribute \src "libresoc.v:177552.7-177552.25" + process $proc$libresoc.v:177552$12976 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:174160.14-174160.48" - process $proc$libresoc.v:174160$12575 + attribute \src "libresoc.v:177595.14-177595.48" + process $proc$libresoc.v:177595$12977 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] end - attribute \src "libresoc.v:174164.14-174164.43" - process $proc$libresoc.v:174164$12576 + attribute \src "libresoc.v:177599.14-177599.43" + process $proc$libresoc.v:177599$12978 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:174242.13-174242.47" - process $proc$libresoc.v:174242$12577 + attribute \src "libresoc.v:177677.13-177677.47" + process $proc$libresoc.v:177677$12979 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:174246.7-174246.39" - process $proc$libresoc.v:174246$12578 + attribute \src "libresoc.v:177681.7-177681.39" + process $proc$libresoc.v:177681$12980 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:174264.7-174264.27" - process $proc$libresoc.v:174264$12579 + attribute \src "libresoc.v:177699.7-177699.27" + process $proc$libresoc.v:177699$12981 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:174296.14-174296.47" - process $proc$libresoc.v:174296$12580 + attribute \src "libresoc.v:177731.14-177731.47" + process $proc$libresoc.v:177731$12982 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:174300.7-174300.27" - process $proc$libresoc.v:174300$12581 + attribute \src "libresoc.v:177735.7-177735.27" + process $proc$libresoc.v:177735$12983 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:174304.14-174304.50" - process $proc$libresoc.v:174304$12582 + attribute \src "libresoc.v:177739.14-177739.50" + process $proc$libresoc.v:177739$12984 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:174308.7-174308.30" - process $proc$libresoc.v:174308$12583 + attribute \src "libresoc.v:177743.7-177743.30" + process $proc$libresoc.v:177743$12985 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:174312.14-174312.51" - process $proc$libresoc.v:174312$12584 + attribute \src "libresoc.v:177747.14-177747.51" + process $proc$libresoc.v:177747$12986 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:174316.7-174316.31" - process $proc$libresoc.v:174316$12585 + attribute \src "libresoc.v:177751.7-177751.31" + process $proc$libresoc.v:177751$12987 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:174320.7-174320.29" - process $proc$libresoc.v:174320$12586 + attribute \src "libresoc.v:177755.7-177755.29" + process $proc$libresoc.v:177755$12988 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:174324.7-174324.32" - process $proc$libresoc.v:174324$12587 + attribute \src "libresoc.v:177759.7-177759.32" + process $proc$libresoc.v:177759$12989 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:174328.13-174328.35" - process $proc$libresoc.v:174328$12588 + attribute \src "libresoc.v:177763.13-177763.35" + process $proc$libresoc.v:177763$12990 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:174332.7-174332.32" - process $proc$libresoc.v:174332$12589 + attribute \src "libresoc.v:177767.7-177767.32" + process $proc$libresoc.v:177767$12991 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:174336.13-174336.35" - process $proc$libresoc.v:174336$12590 + attribute \src "libresoc.v:177771.13-177771.35" + process $proc$libresoc.v:177771$12992 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:174340.7-174340.32" - process $proc$libresoc.v:174340$12591 + attribute \src "libresoc.v:177775.7-177775.32" + process $proc$libresoc.v:177775$12993 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:174368.7-174368.25" - process $proc$libresoc.v:174368$12592 + attribute \src "libresoc.v:177803.7-177803.25" + process $proc$libresoc.v:177803$12994 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:174372.7-174372.25" - process $proc$libresoc.v:174372$12593 + attribute \src "libresoc.v:177807.7-177807.25" + process $proc$libresoc.v:177807$12995 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:174471.13-174471.31" - process $proc$libresoc.v:174471$12594 + attribute \src "libresoc.v:177906.13-177906.31" + process $proc$libresoc.v:177906$12996 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:174479.13-174479.32" - process $proc$libresoc.v:174479$12595 + attribute \src "libresoc.v:177914.13-177914.32" + process $proc$libresoc.v:177914$12997 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:174483.13-174483.32" - process $proc$libresoc.v:174483$12596 + attribute \src "libresoc.v:177918.13-177918.32" + process $proc$libresoc.v:177918$12998 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:174495.7-174495.26" - process $proc$libresoc.v:174495$12597 + attribute \src "libresoc.v:177930.7-177930.26" + process $proc$libresoc.v:177930$12999 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:174499.7-174499.26" - process $proc$libresoc.v:174499$12598 + attribute \src "libresoc.v:177934.7-177934.26" + process $proc$libresoc.v:177934$13000 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:174503.7-174503.25" - process $proc$libresoc.v:174503$12599 + attribute \src "libresoc.v:177938.7-177938.25" + process $proc$libresoc.v:177938$13001 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:174507.7-174507.25" - process $proc$libresoc.v:174507$12600 + attribute \src "libresoc.v:177942.7-177942.25" + process $proc$libresoc.v:177942$13002 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:174529.13-174529.32" - process $proc$libresoc.v:174529$12601 + attribute \src "libresoc.v:177964.13-177964.32" + process $proc$libresoc.v:177964$13003 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:174533.13-174533.32" - process $proc$libresoc.v:174533$12602 + attribute \src "libresoc.v:177968.13-177968.32" + process $proc$libresoc.v:177968$13004 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:174537.14-174537.43" - process $proc$libresoc.v:174537$12603 + attribute \src "libresoc.v:177972.14-177972.43" + process $proc$libresoc.v:177972$13005 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:174541.14-174541.43" - process $proc$libresoc.v:174541$12604 + attribute \src "libresoc.v:177976.14-177976.43" + process $proc$libresoc.v:177976$13006 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:174545.14-174545.43" - process $proc$libresoc.v:174545$12605 + attribute \src "libresoc.v:177980.14-177980.43" + process $proc$libresoc.v:177980$13007 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:174549.7-174549.20" - process $proc$libresoc.v:174549$12606 + attribute \src "libresoc.v:177984.7-177984.20" + process $proc$libresoc.v:177984$13008 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:174553.13-174553.26" - process $proc$libresoc.v:174553$12607 + attribute \src "libresoc.v:177988.13-177988.26" + process $proc$libresoc.v:177988$13009 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:174557.13-174557.26" - process $proc$libresoc.v:174557$12608 + attribute \src "libresoc.v:177992.13-177992.26" + process $proc$libresoc.v:177992$13010 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:174634.3-174635.39" - process $proc$libresoc.v:174634$12413 + attribute \src "libresoc.v:178069.3-178070.39" + process $proc$libresoc.v:178069$12815 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:174636.3-174637.43" - process $proc$libresoc.v:174636$12414 + attribute \src "libresoc.v:178071.3-178072.43" + process $proc$libresoc.v:178071$12816 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:174638.3-174639.29" - process $proc$libresoc.v:174638$12415 + attribute \src "libresoc.v:178073.3-178074.29" + process $proc$libresoc.v:178073$12817 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:174640.3-174641.29" - process $proc$libresoc.v:174640$12416 + attribute \src "libresoc.v:178075.3-178076.29" + process $proc$libresoc.v:178075$12818 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:174642.3-174643.29" - process $proc$libresoc.v:174642$12417 + attribute \src "libresoc.v:178077.3-178078.29" + process $proc$libresoc.v:178077$12819 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:174644.3-174645.29" - process $proc$libresoc.v:174644$12418 + attribute \src "libresoc.v:178079.3-178080.29" + process $proc$libresoc.v:178079$12820 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:174646.3-174647.29" - process $proc$libresoc.v:174646$12419 + attribute \src "libresoc.v:178081.3-178082.29" + process $proc$libresoc.v:178081$12821 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:174648.3-174649.29" - process $proc$libresoc.v:174648$12420 + attribute \src "libresoc.v:178083.3-178084.29" + process $proc$libresoc.v:178083$12822 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:174650.3-174651.47" - process $proc$libresoc.v:174650$12421 + attribute \src "libresoc.v:178085.3-178086.47" + process $proc$libresoc.v:178085$12823 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:174652.3-174653.53" - process $proc$libresoc.v:174652$12422 + attribute \src "libresoc.v:178087.3-178088.53" + process $proc$libresoc.v:178087$12824 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:174654.3-174655.47" - process $proc$libresoc.v:174654$12423 + attribute \src "libresoc.v:178089.3-178090.47" + process $proc$libresoc.v:178089$12825 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:174656.3-174657.53" - process $proc$libresoc.v:174656$12424 + attribute \src "libresoc.v:178091.3-178092.53" + process $proc$libresoc.v:178091$12826 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:174658.3-174659.47" - process $proc$libresoc.v:174658$12425 + attribute \src "libresoc.v:178093.3-178094.47" + process $proc$libresoc.v:178093$12827 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:174660.3-174661.53" - process $proc$libresoc.v:174660$12426 + attribute \src "libresoc.v:178095.3-178096.53" + process $proc$libresoc.v:178095$12828 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:174662.3-174663.45" - process $proc$libresoc.v:174662$12427 + attribute \src "libresoc.v:178097.3-178098.45" + process $proc$libresoc.v:178097$12829 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:174664.3-174665.51" - process $proc$libresoc.v:174664$12428 + attribute \src "libresoc.v:178099.3-178100.51" + process $proc$libresoc.v:178099$12830 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:174666.3-174667.43" - process $proc$libresoc.v:174666$12429 + attribute \src "libresoc.v:178101.3-178102.43" + process $proc$libresoc.v:178101$12831 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:174668.3-174669.49" - process $proc$libresoc.v:174668$12430 + attribute \src "libresoc.v:178103.3-178104.49" + process $proc$libresoc.v:178103$12832 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:174670.3-174671.37" - process $proc$libresoc.v:174670$12431 + attribute \src "libresoc.v:178105.3-178106.37" + process $proc$libresoc.v:178105$12833 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:174672.3-174673.43" - process $proc$libresoc.v:174672$12432 + attribute \src "libresoc.v:178107.3-178108.43" + process $proc$libresoc.v:178107$12834 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:174674.3-174675.69" - process $proc$libresoc.v:174674$12433 + attribute \src "libresoc.v:178109.3-178110.69" + process $proc$libresoc.v:178109$12835 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:174676.3-174677.65" - process $proc$libresoc.v:174676$12434 + attribute \src "libresoc.v:178111.3-178112.65" + process $proc$libresoc.v:178111$12836 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] end - attribute \src "libresoc.v:174678.3-174679.59" - process $proc$libresoc.v:174678$12435 + attribute \src "libresoc.v:178113.3-178114.59" + process $proc$libresoc.v:178113$12837 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:174680.3-174681.67" - process $proc$libresoc.v:174680$12436 + attribute \src "libresoc.v:178115.3-178116.67" + process $proc$libresoc.v:178115$12838 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:174682.3-174683.39" - process $proc$libresoc.v:174682$12437 + attribute \src "libresoc.v:178117.3-178118.39" + process $proc$libresoc.v:178117$12839 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:174684.3-174685.39" - process $proc$libresoc.v:174684$12438 + attribute \src "libresoc.v:178119.3-178120.39" + process $proc$libresoc.v:178119$12840 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:174686.3-174687.39" - process $proc$libresoc.v:174686$12439 + attribute \src "libresoc.v:178121.3-178122.39" + process $proc$libresoc.v:178121$12841 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:174688.3-174689.39" - process $proc$libresoc.v:174688$12440 + attribute \src "libresoc.v:178123.3-178124.39" + process $proc$libresoc.v:178123$12842 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:174690.3-174691.39" - process $proc$libresoc.v:174690$12441 + attribute \src "libresoc.v:178125.3-178126.39" + process $proc$libresoc.v:178125$12843 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:174692.3-174693.39" - process $proc$libresoc.v:174692$12442 + attribute \src "libresoc.v:178127.3-178128.39" + process $proc$libresoc.v:178127$12844 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:174694.3-174695.39" - process $proc$libresoc.v:174694$12443 + attribute \src "libresoc.v:178129.3-178130.39" + process $proc$libresoc.v:178129$12845 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:174696.3-174697.39" - process $proc$libresoc.v:174696$12444 + attribute \src "libresoc.v:178131.3-178132.39" + process $proc$libresoc.v:178131$12846 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:174698.3-174699.41" - process $proc$libresoc.v:174698$12445 + attribute \src "libresoc.v:178133.3-178134.41" + process $proc$libresoc.v:178133$12847 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:174700.3-174701.41" - process $proc$libresoc.v:174700$12446 + attribute \src "libresoc.v:178135.3-178136.41" + process $proc$libresoc.v:178135$12848 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:174702.3-174703.37" - process $proc$libresoc.v:174702$12447 + attribute \src "libresoc.v:178137.3-178138.37" + process $proc$libresoc.v:178137$12849 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:174704.3-174705.40" - process $proc$libresoc.v:174704$12448 + attribute \src "libresoc.v:178139.3-178140.40" + process $proc$libresoc.v:178139$12850 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:174706.3-174707.25" - process $proc$libresoc.v:174706$12449 + attribute \src "libresoc.v:178141.3-178142.25" + process $proc$libresoc.v:178141$12851 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:174786.3-174795.6" - process $proc$libresoc.v:174786$12450 + attribute \src "libresoc.v:178221.3-178230.6" + process $proc$libresoc.v:178221$12852 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:174787.5-174787.29" + attribute \src "libresoc.v:178222.5-178222.29" switch \initial - attribute \src "libresoc.v:174787.9-174787.17" + attribute \src "libresoc.v:178222.9-178222.17" case 1'1 case end @@ -366874,14 +374840,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:174796.3-174804.6" - process $proc$libresoc.v:174796$12451 + attribute \src "libresoc.v:178231.3-178239.6" + process $proc$libresoc.v:178231$12853 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12452 $1\rok_l_s_rdok$next[0:0]$12453 - attribute \src "libresoc.v:174797.5-174797.29" + assign $0\rok_l_s_rdok$next[0:0]$12854 $1\rok_l_s_rdok$next[0:0]$12855 + attribute \src "libresoc.v:178232.5-178232.29" switch \initial - attribute \src "libresoc.v:174797.9-174797.17" + attribute \src "libresoc.v:178232.9-178232.17" case 1'1 case end @@ -366890,21 +374856,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12453 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12855 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12453 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12855 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12452 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12854 end - attribute \src "libresoc.v:174805.3-174813.6" - process $proc$libresoc.v:174805$12454 + attribute \src "libresoc.v:178240.3-178248.6" + process $proc$libresoc.v:178240$12856 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12455 $1\rok_l_r_rdok$next[0:0]$12456 - attribute \src "libresoc.v:174806.5-174806.29" + assign $0\rok_l_r_rdok$next[0:0]$12857 $1\rok_l_r_rdok$next[0:0]$12858 + attribute \src "libresoc.v:178241.5-178241.29" switch \initial - attribute \src "libresoc.v:174806.9-174806.17" + attribute \src "libresoc.v:178241.9-178241.17" case 1'1 case end @@ -366913,21 +374879,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12456 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12858 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12456 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12858 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12455 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12857 end - attribute \src "libresoc.v:174814.3-174822.6" - process $proc$libresoc.v:174814$12457 + attribute \src "libresoc.v:178249.3-178257.6" + process $proc$libresoc.v:178249$12859 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12458 $1\rst_l_s_rst$next[0:0]$12459 - attribute \src "libresoc.v:174815.5-174815.29" + assign $0\rst_l_s_rst$next[0:0]$12860 $1\rst_l_s_rst$next[0:0]$12861 + attribute \src "libresoc.v:178250.5-178250.29" switch \initial - attribute \src "libresoc.v:174815.9-174815.17" + attribute \src "libresoc.v:178250.9-178250.17" case 1'1 case end @@ -366936,21 +374902,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12459 1'0 + assign $1\rst_l_s_rst$next[0:0]$12861 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12459 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12861 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12458 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12860 end - attribute \src "libresoc.v:174823.3-174831.6" - process $proc$libresoc.v:174823$12460 + attribute \src "libresoc.v:178258.3-178266.6" + process $proc$libresoc.v:178258$12862 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12461 $1\rst_l_r_rst$next[0:0]$12462 - attribute \src "libresoc.v:174824.5-174824.29" + assign $0\rst_l_r_rst$next[0:0]$12863 $1\rst_l_r_rst$next[0:0]$12864 + attribute \src "libresoc.v:178259.5-178259.29" switch \initial - attribute \src "libresoc.v:174824.9-174824.17" + attribute \src "libresoc.v:178259.9-178259.17" case 1'1 case end @@ -366959,21 +374925,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12462 1'1 + assign $1\rst_l_r_rst$next[0:0]$12864 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12462 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12864 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12461 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12863 end - attribute \src "libresoc.v:174832.3-174840.6" - process $proc$libresoc.v:174832$12463 + attribute \src "libresoc.v:178267.3-178275.6" + process $proc$libresoc.v:178267$12865 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12464 $1\opc_l_s_opc$next[0:0]$12465 - attribute \src "libresoc.v:174833.5-174833.29" + assign $0\opc_l_s_opc$next[0:0]$12866 $1\opc_l_s_opc$next[0:0]$12867 + attribute \src "libresoc.v:178268.5-178268.29" switch \initial - attribute \src "libresoc.v:174833.9-174833.17" + attribute \src "libresoc.v:178268.9-178268.17" case 1'1 case end @@ -366982,21 +374948,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12465 1'0 + assign $1\opc_l_s_opc$next[0:0]$12867 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12465 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12867 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12464 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12866 end - attribute \src "libresoc.v:174841.3-174849.6" - process $proc$libresoc.v:174841$12466 + attribute \src "libresoc.v:178276.3-178284.6" + process $proc$libresoc.v:178276$12868 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12467 $1\opc_l_r_opc$next[0:0]$12468 - attribute \src "libresoc.v:174842.5-174842.29" + assign $0\opc_l_r_opc$next[0:0]$12869 $1\opc_l_r_opc$next[0:0]$12870 + attribute \src "libresoc.v:178277.5-178277.29" switch \initial - attribute \src "libresoc.v:174842.9-174842.17" + attribute \src "libresoc.v:178277.9-178277.17" case 1'1 case end @@ -367005,21 +374971,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12468 1'1 + assign $1\opc_l_r_opc$next[0:0]$12870 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12468 \req_done + assign $1\opc_l_r_opc$next[0:0]$12870 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12467 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12869 end - attribute \src "libresoc.v:174850.3-174858.6" - process $proc$libresoc.v:174850$12469 + attribute \src "libresoc.v:178285.3-178293.6" + process $proc$libresoc.v:178285$12871 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$12470 $1\src_l_s_src$next[5:0]$12471 - attribute \src "libresoc.v:174851.5-174851.29" + assign $0\src_l_s_src$next[5:0]$12872 $1\src_l_s_src$next[5:0]$12873 + attribute \src "libresoc.v:178286.5-178286.29" switch \initial - attribute \src "libresoc.v:174851.9-174851.17" + attribute \src "libresoc.v:178286.9-178286.17" case 1'1 case end @@ -367028,21 +374994,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$12471 6'000000 + assign $1\src_l_s_src$next[5:0]$12873 6'000000 case - assign $1\src_l_s_src$next[5:0]$12471 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12873 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12470 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12872 end - attribute \src "libresoc.v:174859.3-174867.6" - process $proc$libresoc.v:174859$12472 + attribute \src "libresoc.v:178294.3-178302.6" + process $proc$libresoc.v:178294$12874 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$12473 $1\src_l_r_src$next[5:0]$12474 - attribute \src "libresoc.v:174860.5-174860.29" + assign $0\src_l_r_src$next[5:0]$12875 $1\src_l_r_src$next[5:0]$12876 + attribute \src "libresoc.v:178295.5-178295.29" switch \initial - attribute \src "libresoc.v:174860.9-174860.17" + attribute \src "libresoc.v:178295.9-178295.17" case 1'1 case end @@ -367051,21 +375017,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$12474 6'111111 + assign $1\src_l_r_src$next[5:0]$12876 6'111111 case - assign $1\src_l_r_src$next[5:0]$12474 \reset_r + assign $1\src_l_r_src$next[5:0]$12876 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12473 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12875 end - attribute \src "libresoc.v:174868.3-174876.6" - process $proc$libresoc.v:174868$12475 + attribute \src "libresoc.v:178303.3-178311.6" + process $proc$libresoc.v:178303$12877 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$12476 $1\req_l_s_req$next[5:0]$12477 - attribute \src "libresoc.v:174869.5-174869.29" + assign $0\req_l_s_req$next[5:0]$12878 $1\req_l_s_req$next[5:0]$12879 + attribute \src "libresoc.v:178304.5-178304.29" switch \initial - attribute \src "libresoc.v:174869.9-174869.17" + attribute \src "libresoc.v:178304.9-178304.17" case 1'1 case end @@ -367074,21 +375040,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$12477 6'000000 + assign $1\req_l_s_req$next[5:0]$12879 6'000000 case - assign $1\req_l_s_req$next[5:0]$12477 \$70 + assign $1\req_l_s_req$next[5:0]$12879 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12476 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12878 end - attribute \src "libresoc.v:174877.3-174885.6" - process $proc$libresoc.v:174877$12478 + attribute \src "libresoc.v:178312.3-178320.6" + process $proc$libresoc.v:178312$12880 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$12479 $1\req_l_r_req$next[5:0]$12480 - attribute \src "libresoc.v:174878.5-174878.29" + assign $0\req_l_r_req$next[5:0]$12881 $1\req_l_r_req$next[5:0]$12882 + attribute \src "libresoc.v:178313.5-178313.29" switch \initial - attribute \src "libresoc.v:174878.9-174878.17" + attribute \src "libresoc.v:178313.9-178313.17" case 1'1 case end @@ -367097,15 +375063,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$12480 6'111111 + assign $1\req_l_r_req$next[5:0]$12882 6'111111 case - assign $1\req_l_r_req$next[5:0]$12480 \$72 + assign $1\req_l_r_req$next[5:0]$12882 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12479 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12881 end - attribute \src "libresoc.v:174886.3-174898.6" - process $proc$libresoc.v:174886$12481 + attribute \src "libresoc.v:178321.3-178333.6" + process $proc$libresoc.v:178321$12883 assign { } { } assign { } { } assign { } { } @@ -367114,13 +375080,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12483 $1\alu_spr0_spr_op__insn$next[31:0]$12487 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 - attribute \src "libresoc.v:174887.5-174887.29" + assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12885 $1\alu_spr0_spr_op__insn$next[31:0]$12889 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 + attribute \src "libresoc.v:178322.5-178322.29" switch \initial - attribute \src "libresoc.v:174887.9-174887.17" + attribute \src "libresoc.v:178322.9-178322.17" case 1'1 case end @@ -367132,33 +375098,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 $1\alu_spr0_spr_op__insn$next[31:0]$12487 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 $1\alu_spr0_spr_op__insn$next[31:0]$12889 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12486 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12487 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12488 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12489 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12889 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12482 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12483 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12484 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12485 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12885 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 end - attribute \src "libresoc.v:174899.3-174920.6" - process $proc$libresoc.v:174899$12490 + attribute \src "libresoc.v:178334.3-178355.6" + process $proc$libresoc.v:178334$12892 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12491 $2\data_r0__o$next[63:0]$12495 + assign $0\data_r0__o$next[63:0]$12893 $2\data_r0__o$next[63:0]$12897 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12492 $3\data_r0__o_ok$next[0:0]$12497 - attribute \src "libresoc.v:174900.5-174900.29" + assign $0\data_r0__o_ok$next[0:0]$12894 $3\data_r0__o_ok$next[0:0]$12899 + attribute \src "libresoc.v:178335.5-178335.29" switch \initial - attribute \src "libresoc.v:174900.9-174900.17" + attribute \src "libresoc.v:178335.9-178335.17" case 1'1 case end @@ -367168,10 +375134,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12494 $1\data_r0__o$next[63:0]$12493 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12896 $1\data_r0__o$next[63:0]$12895 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$12493 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12494 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12895 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12896 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367179,38 +375145,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12496 $2\data_r0__o$next[63:0]$12495 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12898 $2\data_r0__o$next[63:0]$12897 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12495 $1\data_r0__o$next[63:0]$12493 - assign $2\data_r0__o_ok$next[0:0]$12496 $1\data_r0__o_ok$next[0:0]$12494 + assign $2\data_r0__o$next[63:0]$12897 $1\data_r0__o$next[63:0]$12895 + assign $2\data_r0__o_ok$next[0:0]$12898 $1\data_r0__o_ok$next[0:0]$12896 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12497 1'0 + assign $3\data_r0__o_ok$next[0:0]$12899 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12497 $2\data_r0__o_ok$next[0:0]$12496 + assign $3\data_r0__o_ok$next[0:0]$12899 $2\data_r0__o_ok$next[0:0]$12898 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12491 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12492 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12893 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12894 end - attribute \src "libresoc.v:174921.3-174942.6" - process $proc$libresoc.v:174921$12498 + attribute \src "libresoc.v:178356.3-178377.6" + process $proc$libresoc.v:178356$12900 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$12499 $2\data_r1__spr1$next[63:0]$12503 + assign $0\data_r1__spr1$next[63:0]$12901 $2\data_r1__spr1$next[63:0]$12905 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12500 $3\data_r1__spr1_ok$next[0:0]$12505 - attribute \src "libresoc.v:174922.5-174922.29" + assign $0\data_r1__spr1_ok$next[0:0]$12902 $3\data_r1__spr1_ok$next[0:0]$12907 + attribute \src "libresoc.v:178357.5-178357.29" switch \initial - attribute \src "libresoc.v:174922.9-174922.17" + attribute \src "libresoc.v:178357.9-178357.17" case 1'1 case end @@ -367220,10 +375186,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12502 $1\data_r1__spr1$next[63:0]$12501 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12904 $1\data_r1__spr1$next[63:0]$12903 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$12501 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12502 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12903 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12904 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367231,38 +375197,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12504 $2\data_r1__spr1$next[63:0]$12503 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12906 $2\data_r1__spr1$next[63:0]$12905 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$12503 $1\data_r1__spr1$next[63:0]$12501 - assign $2\data_r1__spr1_ok$next[0:0]$12504 $1\data_r1__spr1_ok$next[0:0]$12502 + assign $2\data_r1__spr1$next[63:0]$12905 $1\data_r1__spr1$next[63:0]$12903 + assign $2\data_r1__spr1_ok$next[0:0]$12906 $1\data_r1__spr1_ok$next[0:0]$12904 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12505 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12907 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$12505 $2\data_r1__spr1_ok$next[0:0]$12504 + assign $3\data_r1__spr1_ok$next[0:0]$12907 $2\data_r1__spr1_ok$next[0:0]$12906 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12499 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12500 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12901 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12902 end - attribute \src "libresoc.v:174943.3-174964.6" - process $proc$libresoc.v:174943$12506 + attribute \src "libresoc.v:178378.3-178399.6" + process $proc$libresoc.v:178378$12908 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$12507 $2\data_r2__fast1$next[63:0]$12511 + assign $0\data_r2__fast1$next[63:0]$12909 $2\data_r2__fast1$next[63:0]$12913 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12508 $3\data_r2__fast1_ok$next[0:0]$12513 - attribute \src "libresoc.v:174944.5-174944.29" + assign $0\data_r2__fast1_ok$next[0:0]$12910 $3\data_r2__fast1_ok$next[0:0]$12915 + attribute \src "libresoc.v:178379.5-178379.29" switch \initial - attribute \src "libresoc.v:174944.9-174944.17" + attribute \src "libresoc.v:178379.9-178379.17" case 1'1 case end @@ -367272,10 +375238,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12510 $1\data_r2__fast1$next[63:0]$12509 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12912 $1\data_r2__fast1$next[63:0]$12911 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$12509 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12510 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12911 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12912 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367283,38 +375249,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12512 $2\data_r2__fast1$next[63:0]$12511 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12914 $2\data_r2__fast1$next[63:0]$12913 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$12511 $1\data_r2__fast1$next[63:0]$12509 - assign $2\data_r2__fast1_ok$next[0:0]$12512 $1\data_r2__fast1_ok$next[0:0]$12510 + assign $2\data_r2__fast1$next[63:0]$12913 $1\data_r2__fast1$next[63:0]$12911 + assign $2\data_r2__fast1_ok$next[0:0]$12914 $1\data_r2__fast1_ok$next[0:0]$12912 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12513 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12915 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12513 $2\data_r2__fast1_ok$next[0:0]$12512 + assign $3\data_r2__fast1_ok$next[0:0]$12915 $2\data_r2__fast1_ok$next[0:0]$12914 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12507 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12508 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12909 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12910 end - attribute \src "libresoc.v:174965.3-174986.6" - process $proc$libresoc.v:174965$12514 + attribute \src "libresoc.v:178400.3-178421.6" + process $proc$libresoc.v:178400$12916 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12515 $2\data_r3__xer_so$next[0:0]$12519 + assign $0\data_r3__xer_so$next[0:0]$12917 $2\data_r3__xer_so$next[0:0]$12921 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12516 $3\data_r3__xer_so_ok$next[0:0]$12521 - attribute \src "libresoc.v:174966.5-174966.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12918 $3\data_r3__xer_so_ok$next[0:0]$12923 + attribute \src "libresoc.v:178401.5-178401.29" switch \initial - attribute \src "libresoc.v:174966.9-174966.17" + attribute \src "libresoc.v:178401.9-178401.17" case 1'1 case end @@ -367324,10 +375290,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12518 $1\data_r3__xer_so$next[0:0]$12517 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12920 $1\data_r3__xer_so$next[0:0]$12919 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$12517 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12518 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12919 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12920 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367335,38 +375301,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12520 $2\data_r3__xer_so$next[0:0]$12519 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$12922 $2\data_r3__xer_so$next[0:0]$12921 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$12519 $1\data_r3__xer_so$next[0:0]$12517 - assign $2\data_r3__xer_so_ok$next[0:0]$12520 $1\data_r3__xer_so_ok$next[0:0]$12518 + assign $2\data_r3__xer_so$next[0:0]$12921 $1\data_r3__xer_so$next[0:0]$12919 + assign $2\data_r3__xer_so_ok$next[0:0]$12922 $1\data_r3__xer_so_ok$next[0:0]$12920 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12521 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$12923 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$12521 $2\data_r3__xer_so_ok$next[0:0]$12520 + assign $3\data_r3__xer_so_ok$next[0:0]$12923 $2\data_r3__xer_so_ok$next[0:0]$12922 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12515 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12516 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12917 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12918 end - attribute \src "libresoc.v:174987.3-175008.6" - process $proc$libresoc.v:174987$12522 + attribute \src "libresoc.v:178422.3-178443.6" + process $proc$libresoc.v:178422$12924 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12523 $2\data_r4__xer_ov$next[1:0]$12527 + assign $0\data_r4__xer_ov$next[1:0]$12925 $2\data_r4__xer_ov$next[1:0]$12929 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12524 $3\data_r4__xer_ov_ok$next[0:0]$12529 - attribute \src "libresoc.v:174988.5-174988.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$12926 $3\data_r4__xer_ov_ok$next[0:0]$12931 + attribute \src "libresoc.v:178423.5-178423.29" switch \initial - attribute \src "libresoc.v:174988.9-174988.17" + attribute \src "libresoc.v:178423.9-178423.17" case 1'1 case end @@ -367376,10 +375342,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12526 $1\data_r4__xer_ov$next[1:0]$12525 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12928 $1\data_r4__xer_ov$next[1:0]$12927 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$12525 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12526 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$12927 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12928 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367387,38 +375353,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12528 $2\data_r4__xer_ov$next[1:0]$12527 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$12930 $2\data_r4__xer_ov$next[1:0]$12929 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$12527 $1\data_r4__xer_ov$next[1:0]$12525 - assign $2\data_r4__xer_ov_ok$next[0:0]$12528 $1\data_r4__xer_ov_ok$next[0:0]$12526 + assign $2\data_r4__xer_ov$next[1:0]$12929 $1\data_r4__xer_ov$next[1:0]$12927 + assign $2\data_r4__xer_ov_ok$next[0:0]$12930 $1\data_r4__xer_ov_ok$next[0:0]$12928 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12529 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$12931 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$12529 $2\data_r4__xer_ov_ok$next[0:0]$12528 + assign $3\data_r4__xer_ov_ok$next[0:0]$12931 $2\data_r4__xer_ov_ok$next[0:0]$12930 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12523 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12524 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12925 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12926 end - attribute \src "libresoc.v:175009.3-175030.6" - process $proc$libresoc.v:175009$12530 + attribute \src "libresoc.v:178444.3-178465.6" + process $proc$libresoc.v:178444$12932 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12531 $2\data_r5__xer_ca$next[1:0]$12535 + assign $0\data_r5__xer_ca$next[1:0]$12933 $2\data_r5__xer_ca$next[1:0]$12937 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12532 $3\data_r5__xer_ca_ok$next[0:0]$12537 - attribute \src "libresoc.v:175010.5-175010.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$12934 $3\data_r5__xer_ca_ok$next[0:0]$12939 + attribute \src "libresoc.v:178445.5-178445.29" switch \initial - attribute \src "libresoc.v:175010.9-175010.17" + attribute \src "libresoc.v:178445.9-178445.17" case 1'1 case end @@ -367428,10 +375394,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12534 $1\data_r5__xer_ca$next[1:0]$12533 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12936 $1\data_r5__xer_ca$next[1:0]$12935 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$12533 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12534 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$12935 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12936 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -367439,32 +375405,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12536 $2\data_r5__xer_ca$next[1:0]$12535 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$12938 $2\data_r5__xer_ca$next[1:0]$12937 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$12535 $1\data_r5__xer_ca$next[1:0]$12533 - assign $2\data_r5__xer_ca_ok$next[0:0]$12536 $1\data_r5__xer_ca_ok$next[0:0]$12534 + assign $2\data_r5__xer_ca$next[1:0]$12937 $1\data_r5__xer_ca$next[1:0]$12935 + assign $2\data_r5__xer_ca_ok$next[0:0]$12938 $1\data_r5__xer_ca_ok$next[0:0]$12936 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12537 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$12939 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$12537 $2\data_r5__xer_ca_ok$next[0:0]$12536 + assign $3\data_r5__xer_ca_ok$next[0:0]$12939 $2\data_r5__xer_ca_ok$next[0:0]$12938 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12531 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12532 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12933 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12934 end - attribute \src "libresoc.v:175031.3-175040.6" - process $proc$libresoc.v:175031$12538 + attribute \src "libresoc.v:178466.3-178475.6" + process $proc$libresoc.v:178466$12940 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12539 $1\src_r0$next[63:0]$12540 - attribute \src "libresoc.v:175032.5-175032.29" + assign $0\src_r0$next[63:0]$12941 $1\src_r0$next[63:0]$12942 + attribute \src "libresoc.v:178467.5-178467.29" switch \initial - attribute \src "libresoc.v:175032.9-175032.17" + attribute \src "libresoc.v:178467.9-178467.17" case 1'1 case end @@ -367473,21 +375439,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12540 \src1_i + assign $1\src_r0$next[63:0]$12942 \src1_i case - assign $1\src_r0$next[63:0]$12540 \src_r0 + assign $1\src_r0$next[63:0]$12942 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12539 + update \src_r0$next $0\src_r0$next[63:0]$12941 end - attribute \src "libresoc.v:175041.3-175050.6" - process $proc$libresoc.v:175041$12541 + attribute \src "libresoc.v:178476.3-178485.6" + process $proc$libresoc.v:178476$12943 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12542 $1\src_r1$next[63:0]$12543 - attribute \src "libresoc.v:175042.5-175042.29" + assign $0\src_r1$next[63:0]$12944 $1\src_r1$next[63:0]$12945 + attribute \src "libresoc.v:178477.5-178477.29" switch \initial - attribute \src "libresoc.v:175042.9-175042.17" + attribute \src "libresoc.v:178477.9-178477.17" case 1'1 case end @@ -367496,21 +375462,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12543 \src2_i + assign $1\src_r1$next[63:0]$12945 \src2_i case - assign $1\src_r1$next[63:0]$12543 \src_r1 + assign $1\src_r1$next[63:0]$12945 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12542 + update \src_r1$next $0\src_r1$next[63:0]$12944 end - attribute \src "libresoc.v:175051.3-175060.6" - process $proc$libresoc.v:175051$12544 + attribute \src "libresoc.v:178486.3-178495.6" + process $proc$libresoc.v:178486$12946 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12545 $1\src_r2$next[63:0]$12546 - attribute \src "libresoc.v:175052.5-175052.29" + assign $0\src_r2$next[63:0]$12947 $1\src_r2$next[63:0]$12948 + attribute \src "libresoc.v:178487.5-178487.29" switch \initial - attribute \src "libresoc.v:175052.9-175052.17" + attribute \src "libresoc.v:178487.9-178487.17" case 1'1 case end @@ -367519,21 +375485,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12546 \src3_i + assign $1\src_r2$next[63:0]$12948 \src3_i case - assign $1\src_r2$next[63:0]$12546 \src_r2 + assign $1\src_r2$next[63:0]$12948 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12545 + update \src_r2$next $0\src_r2$next[63:0]$12947 end - attribute \src "libresoc.v:175061.3-175070.6" - process $proc$libresoc.v:175061$12547 + attribute \src "libresoc.v:178496.3-178505.6" + process $proc$libresoc.v:178496$12949 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12548 $1\src_r3$next[0:0]$12549 - attribute \src "libresoc.v:175062.5-175062.29" + assign $0\src_r3$next[0:0]$12950 $1\src_r3$next[0:0]$12951 + attribute \src "libresoc.v:178497.5-178497.29" switch \initial - attribute \src "libresoc.v:175062.9-175062.17" + attribute \src "libresoc.v:178497.9-178497.17" case 1'1 case end @@ -367542,21 +375508,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12549 \src4_i + assign $1\src_r3$next[0:0]$12951 \src4_i case - assign $1\src_r3$next[0:0]$12549 \src_r3 + assign $1\src_r3$next[0:0]$12951 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12548 + update \src_r3$next $0\src_r3$next[0:0]$12950 end - attribute \src "libresoc.v:175071.3-175080.6" - process $proc$libresoc.v:175071$12550 + attribute \src "libresoc.v:178506.3-178515.6" + process $proc$libresoc.v:178506$12952 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12551 $1\src_r4$next[1:0]$12552 - attribute \src "libresoc.v:175072.5-175072.29" + assign $0\src_r4$next[1:0]$12953 $1\src_r4$next[1:0]$12954 + attribute \src "libresoc.v:178507.5-178507.29" switch \initial - attribute \src "libresoc.v:175072.9-175072.17" + attribute \src "libresoc.v:178507.9-178507.17" case 1'1 case end @@ -367565,21 +375531,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12552 \src5_i + assign $1\src_r4$next[1:0]$12954 \src5_i case - assign $1\src_r4$next[1:0]$12552 \src_r4 + assign $1\src_r4$next[1:0]$12954 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12551 + update \src_r4$next $0\src_r4$next[1:0]$12953 end - attribute \src "libresoc.v:175081.3-175090.6" - process $proc$libresoc.v:175081$12553 + attribute \src "libresoc.v:178516.3-178525.6" + process $proc$libresoc.v:178516$12955 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$12554 $1\src_r5$next[1:0]$12555 - attribute \src "libresoc.v:175082.5-175082.29" + assign $0\src_r5$next[1:0]$12956 $1\src_r5$next[1:0]$12957 + attribute \src "libresoc.v:178517.5-178517.29" switch \initial - attribute \src "libresoc.v:175082.9-175082.17" + attribute \src "libresoc.v:178517.9-178517.17" case 1'1 case end @@ -367588,21 +375554,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$12555 \src6_i + assign $1\src_r5$next[1:0]$12957 \src6_i case - assign $1\src_r5$next[1:0]$12555 \src_r5 + assign $1\src_r5$next[1:0]$12957 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$12554 + update \src_r5$next $0\src_r5$next[1:0]$12956 end - attribute \src "libresoc.v:175091.3-175099.6" - process $proc$libresoc.v:175091$12556 + attribute \src "libresoc.v:178526.3-178534.6" + process $proc$libresoc.v:178526$12958 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12557 $1\alui_l_r_alui$next[0:0]$12558 - attribute \src "libresoc.v:175092.5-175092.29" + assign $0\alui_l_r_alui$next[0:0]$12959 $1\alui_l_r_alui$next[0:0]$12960 + attribute \src "libresoc.v:178527.5-178527.29" switch \initial - attribute \src "libresoc.v:175092.9-175092.17" + attribute \src "libresoc.v:178527.9-178527.17" case 1'1 case end @@ -367611,21 +375577,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12558 1'1 + assign $1\alui_l_r_alui$next[0:0]$12960 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12558 \$98 + assign $1\alui_l_r_alui$next[0:0]$12960 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12557 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12959 end - attribute \src "libresoc.v:175100.3-175108.6" - process $proc$libresoc.v:175100$12559 + attribute \src "libresoc.v:178535.3-178543.6" + process $proc$libresoc.v:178535$12961 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12560 $1\alu_l_r_alu$next[0:0]$12561 - attribute \src "libresoc.v:175101.5-175101.29" + assign $0\alu_l_r_alu$next[0:0]$12962 $1\alu_l_r_alu$next[0:0]$12963 + attribute \src "libresoc.v:178536.5-178536.29" switch \initial - attribute \src "libresoc.v:175101.9-175101.17" + attribute \src "libresoc.v:178536.9-178536.17" case 1'1 case end @@ -367634,21 +375600,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12561 1'1 + assign $1\alu_l_r_alu$next[0:0]$12963 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12561 \$100 + assign $1\alu_l_r_alu$next[0:0]$12963 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12560 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12962 end - attribute \src "libresoc.v:175109.3-175118.6" - process $proc$libresoc.v:175109$12562 + attribute \src "libresoc.v:178544.3-178553.6" + process $proc$libresoc.v:178544$12964 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:175110.5-175110.29" + attribute \src "libresoc.v:178545.5-178545.29" switch \initial - attribute \src "libresoc.v:175110.9-175110.17" + attribute \src "libresoc.v:178545.9-178545.17" case 1'1 case end @@ -367664,14 +375630,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:175119.3-175128.6" - process $proc$libresoc.v:175119$12563 + attribute \src "libresoc.v:178554.3-178563.6" + process $proc$libresoc.v:178554$12965 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:175120.5-175120.29" + attribute \src "libresoc.v:178555.5-178555.29" switch \initial - attribute \src "libresoc.v:175120.9-175120.17" + attribute \src "libresoc.v:178555.9-178555.17" case 1'1 case end @@ -367687,14 +375653,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:175129.3-175138.6" - process $proc$libresoc.v:175129$12564 + attribute \src "libresoc.v:178564.3-178573.6" + process $proc$libresoc.v:178564$12966 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:175130.5-175130.29" + attribute \src "libresoc.v:178565.5-178565.29" switch \initial - attribute \src "libresoc.v:175130.9-175130.17" + attribute \src "libresoc.v:178565.9-178565.17" case 1'1 case end @@ -367710,14 +375676,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:175139.3-175148.6" - process $proc$libresoc.v:175139$12565 + attribute \src "libresoc.v:178574.3-178583.6" + process $proc$libresoc.v:178574$12967 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:175140.5-175140.29" + attribute \src "libresoc.v:178575.5-178575.29" switch \initial - attribute \src "libresoc.v:175140.9-175140.17" + attribute \src "libresoc.v:178575.9-178575.17" case 1'1 case end @@ -367733,14 +375699,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:175149.3-175158.6" - process $proc$libresoc.v:175149$12566 + attribute \src "libresoc.v:178584.3-178593.6" + process $proc$libresoc.v:178584$12968 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:175150.5-175150.29" + attribute \src "libresoc.v:178585.5-178585.29" switch \initial - attribute \src "libresoc.v:175150.9-175150.17" + attribute \src "libresoc.v:178585.9-178585.17" case 1'1 case end @@ -367756,14 +375722,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:175159.3-175168.6" - process $proc$libresoc.v:175159$12567 + attribute \src "libresoc.v:178594.3-178603.6" + process $proc$libresoc.v:178594$12969 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:175160.5-175160.29" + attribute \src "libresoc.v:178595.5-178595.29" switch \initial - attribute \src "libresoc.v:175160.9-175160.17" + attribute \src "libresoc.v:178595.9-178595.17" case 1'1 case end @@ -367779,14 +375745,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:175169.3-175177.6" - process $proc$libresoc.v:175169$12568 + attribute \src "libresoc.v:178604.3-178612.6" + process $proc$libresoc.v:178604$12970 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$12569 $1\prev_wr_go$next[5:0]$12570 - attribute \src "libresoc.v:175170.5-175170.29" + assign $0\prev_wr_go$next[5:0]$12971 $1\prev_wr_go$next[5:0]$12972 + attribute \src "libresoc.v:178605.5-178605.29" switch \initial - attribute \src "libresoc.v:175170.9-175170.17" + attribute \src "libresoc.v:178605.9-178605.17" case 1'1 case end @@ -367795,79 +375761,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$12570 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12570 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12569 - end - connect \$9 $not$libresoc.v:174568$12347_Y - connect \$100 $and$libresoc.v:174569$12348_Y - connect \$102 $and$libresoc.v:174570$12349_Y - connect \$104 $and$libresoc.v:174571$12350_Y - connect \$106 $not$libresoc.v:174572$12351_Y - connect \$108 $and$libresoc.v:174573$12352_Y - connect \$110 $and$libresoc.v:174574$12353_Y - connect \$112 $and$libresoc.v:174575$12354_Y - connect \$114 $and$libresoc.v:174576$12355_Y - connect \$116 $and$libresoc.v:174577$12356_Y - connect \$118 $and$libresoc.v:174578$12357_Y - connect \$11 $or$libresoc.v:174579$12358_Y - connect \$120 $and$libresoc.v:174580$12359_Y - connect \$122 $and$libresoc.v:174581$12360_Y - connect \$124 $and$libresoc.v:174582$12361_Y - connect \$126 $and$libresoc.v:174583$12362_Y - connect \$128 $and$libresoc.v:174584$12363_Y - connect \$8 $reduce_and$libresoc.v:174585$12364_Y - connect \$130 $and$libresoc.v:174586$12365_Y - connect \$132 $and$libresoc.v:174587$12366_Y - connect \$134 $and$libresoc.v:174588$12367_Y - connect \$136 $and$libresoc.v:174589$12368_Y - connect \$14 $and$libresoc.v:174590$12369_Y - connect \$16 $not$libresoc.v:174591$12370_Y - connect \$18 $and$libresoc.v:174592$12371_Y - connect \$20 $not$libresoc.v:174593$12372_Y - connect \$22 $and$libresoc.v:174594$12373_Y - connect \$24 $and$libresoc.v:174595$12374_Y - connect \$28 $not$libresoc.v:174596$12375_Y - connect \$30 $and$libresoc.v:174597$12376_Y - connect \$27 $reduce_or$libresoc.v:174598$12377_Y - connect \$26 $not$libresoc.v:174599$12378_Y - connect \$34 $and$libresoc.v:174600$12379_Y - connect \$36 $reduce_or$libresoc.v:174601$12380_Y - connect \$38 $reduce_or$libresoc.v:174602$12381_Y - connect \$40 $or$libresoc.v:174603$12382_Y - connect \$42 $not$libresoc.v:174604$12383_Y - connect \$44 $and$libresoc.v:174605$12384_Y - connect \$46 $and$libresoc.v:174606$12385_Y - connect \$48 $eq$libresoc.v:174607$12386_Y - connect \$50 $and$libresoc.v:174608$12387_Y - connect \$52 $eq$libresoc.v:174609$12388_Y - connect \$54 $and$libresoc.v:174610$12389_Y - connect \$56 $and$libresoc.v:174611$12390_Y - connect \$58 $and$libresoc.v:174612$12391_Y - connect \$60 $or$libresoc.v:174613$12392_Y - connect \$62 $or$libresoc.v:174614$12393_Y - connect \$64 $or$libresoc.v:174615$12394_Y - connect \$66 $or$libresoc.v:174616$12395_Y - connect \$68 $and$libresoc.v:174617$12396_Y - connect \$6 $and$libresoc.v:174618$12397_Y - connect \$70 $and$libresoc.v:174619$12398_Y - connect \$72 $or$libresoc.v:174620$12399_Y - connect \$74 $and$libresoc.v:174621$12400_Y - connect \$76 $and$libresoc.v:174622$12401_Y - connect \$78 $and$libresoc.v:174623$12402_Y - connect \$80 $and$libresoc.v:174624$12403_Y - connect \$82 $and$libresoc.v:174625$12404_Y - connect \$84 $and$libresoc.v:174626$12405_Y - connect \$86 $ternary$libresoc.v:174627$12406_Y - connect \$88 $ternary$libresoc.v:174628$12407_Y - connect \$90 $ternary$libresoc.v:174629$12408_Y - connect \$92 $ternary$libresoc.v:174630$12409_Y - connect \$94 $ternary$libresoc.v:174631$12410_Y - connect \$96 $ternary$libresoc.v:174632$12411_Y - connect \$98 $and$libresoc.v:174633$12412_Y + assign $1\prev_wr_go$next[5:0]$12972 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12972 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12971 + end + connect \$9 $not$libresoc.v:178003$12749_Y + connect \$100 $and$libresoc.v:178004$12750_Y + connect \$102 $and$libresoc.v:178005$12751_Y + connect \$104 $and$libresoc.v:178006$12752_Y + connect \$106 $not$libresoc.v:178007$12753_Y + connect \$108 $and$libresoc.v:178008$12754_Y + connect \$110 $and$libresoc.v:178009$12755_Y + connect \$112 $and$libresoc.v:178010$12756_Y + connect \$114 $and$libresoc.v:178011$12757_Y + connect \$116 $and$libresoc.v:178012$12758_Y + connect \$118 $and$libresoc.v:178013$12759_Y + connect \$11 $or$libresoc.v:178014$12760_Y + connect \$120 $and$libresoc.v:178015$12761_Y + connect \$122 $and$libresoc.v:178016$12762_Y + connect \$124 $and$libresoc.v:178017$12763_Y + connect \$126 $and$libresoc.v:178018$12764_Y + connect \$128 $and$libresoc.v:178019$12765_Y + connect \$8 $reduce_and$libresoc.v:178020$12766_Y + connect \$130 $and$libresoc.v:178021$12767_Y + connect \$132 $and$libresoc.v:178022$12768_Y + connect \$134 $and$libresoc.v:178023$12769_Y + connect \$136 $and$libresoc.v:178024$12770_Y + connect \$14 $and$libresoc.v:178025$12771_Y + connect \$16 $not$libresoc.v:178026$12772_Y + connect \$18 $and$libresoc.v:178027$12773_Y + connect \$20 $not$libresoc.v:178028$12774_Y + connect \$22 $and$libresoc.v:178029$12775_Y + connect \$24 $and$libresoc.v:178030$12776_Y + connect \$28 $not$libresoc.v:178031$12777_Y + connect \$30 $and$libresoc.v:178032$12778_Y + connect \$27 $reduce_or$libresoc.v:178033$12779_Y + connect \$26 $not$libresoc.v:178034$12780_Y + connect \$34 $and$libresoc.v:178035$12781_Y + connect \$36 $reduce_or$libresoc.v:178036$12782_Y + connect \$38 $reduce_or$libresoc.v:178037$12783_Y + connect \$40 $or$libresoc.v:178038$12784_Y + connect \$42 $not$libresoc.v:178039$12785_Y + connect \$44 $and$libresoc.v:178040$12786_Y + connect \$46 $and$libresoc.v:178041$12787_Y + connect \$48 $eq$libresoc.v:178042$12788_Y + connect \$50 $and$libresoc.v:178043$12789_Y + connect \$52 $eq$libresoc.v:178044$12790_Y + connect \$54 $and$libresoc.v:178045$12791_Y + connect \$56 $and$libresoc.v:178046$12792_Y + connect \$58 $and$libresoc.v:178047$12793_Y + connect \$60 $or$libresoc.v:178048$12794_Y + connect \$62 $or$libresoc.v:178049$12795_Y + connect \$64 $or$libresoc.v:178050$12796_Y + connect \$66 $or$libresoc.v:178051$12797_Y + connect \$68 $and$libresoc.v:178052$12798_Y + connect \$6 $and$libresoc.v:178053$12799_Y + connect \$70 $and$libresoc.v:178054$12800_Y + connect \$72 $or$libresoc.v:178055$12801_Y + connect \$74 $and$libresoc.v:178056$12802_Y + connect \$76 $and$libresoc.v:178057$12803_Y + connect \$78 $and$libresoc.v:178058$12804_Y + connect \$80 $and$libresoc.v:178059$12805_Y + connect \$82 $and$libresoc.v:178060$12806_Y + connect \$84 $and$libresoc.v:178061$12807_Y + connect \$86 $ternary$libresoc.v:178062$12808_Y + connect \$88 $ternary$libresoc.v:178063$12809_Y + connect \$90 $ternary$libresoc.v:178064$12810_Y + connect \$92 $ternary$libresoc.v:178065$12811_Y + connect \$94 $ternary$libresoc.v:178066$12812_Y + connect \$96 $ternary$libresoc.v:178067$12813_Y + connect \$98 $and$libresoc.v:178068$12814_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -367900,111 +375866,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:175213.1-175727.10" +attribute \src "libresoc.v:178648.1-179162.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:175480.3-175495.6" - wire width 64 $0\fast1$7[63:0]$12617 - attribute \src "libresoc.v:175557.3-175572.6" + attribute \src "libresoc.v:178915.3-178930.6" + wire width 64 $0\fast1$7[63:0]$13019 + attribute \src "libresoc.v:178992.3-179007.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:175214.7-175214.20" + attribute \src "libresoc.v:178649.7-178649.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:175705.3-175723.6" - wire width 64 $0\spr1$6[63:0]$12642 - attribute \src "libresoc.v:175496.3-175514.6" + attribute \src "libresoc.v:179140.3-179158.6" + wire width 64 $0\spr1$6[63:0]$13044 + attribute \src "libresoc.v:178931.3-178949.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:175660.3-175683.6" - wire width 2 $0\xer_ca$10[1:0]$12636 - attribute \src "libresoc.v:175684.3-175704.6" + attribute \src "libresoc.v:179095.3-179118.6" + wire width 2 $0\xer_ca$10[1:0]$13038 + attribute \src "libresoc.v:179119.3-179139.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:175615.3-175638.6" - wire width 2 $0\xer_ov$9[1:0]$12630 - attribute \src "libresoc.v:175639.3-175659.6" + attribute \src "libresoc.v:179050.3-179073.6" + wire width 2 $0\xer_ov$9[1:0]$13032 + attribute \src "libresoc.v:179074.3-179094.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:175573.3-175593.6" - wire $0\xer_so$8[0:0]$12624 - attribute \src "libresoc.v:175594.3-175614.6" + attribute \src "libresoc.v:179008.3-179028.6" + wire $0\xer_so$8[0:0]$13026 + attribute \src "libresoc.v:179029.3-179049.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:175480.3-175495.6" - wire width 64 $1\fast1$7[63:0]$12618 - attribute \src "libresoc.v:175557.3-175572.6" + attribute \src "libresoc.v:178915.3-178930.6" + wire width 64 $1\fast1$7[63:0]$13020 + attribute \src "libresoc.v:178992.3-179007.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:175705.3-175723.6" - wire width 64 $1\spr1$6[63:0]$12643 - attribute \src "libresoc.v:175496.3-175514.6" + attribute \src "libresoc.v:179140.3-179158.6" + wire width 64 $1\spr1$6[63:0]$13045 + attribute \src "libresoc.v:178931.3-178949.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:175660.3-175683.6" - wire width 2 $1\xer_ca$10[1:0]$12637 - attribute \src "libresoc.v:175684.3-175704.6" + attribute \src "libresoc.v:179095.3-179118.6" + wire width 2 $1\xer_ca$10[1:0]$13039 + attribute \src "libresoc.v:179119.3-179139.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:175615.3-175638.6" - wire width 2 $1\xer_ov$9[1:0]$12631 - attribute \src "libresoc.v:175639.3-175659.6" + attribute \src "libresoc.v:179050.3-179073.6" + wire width 2 $1\xer_ov$9[1:0]$13033 + attribute \src "libresoc.v:179074.3-179094.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:175573.3-175593.6" - wire $1\xer_so$8[0:0]$12625 - attribute \src "libresoc.v:175594.3-175614.6" + attribute \src "libresoc.v:179008.3-179028.6" + wire $1\xer_so$8[0:0]$13027 + attribute \src "libresoc.v:179029.3-179049.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:175480.3-175495.6" - wire width 64 $2\fast1$7[63:0]$12619 - attribute \src "libresoc.v:175557.3-175572.6" + attribute \src "libresoc.v:178915.3-178930.6" + wire width 64 $2\fast1$7[63:0]$13021 + attribute \src "libresoc.v:178992.3-179007.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:175705.3-175723.6" - wire width 64 $2\spr1$6[63:0]$12644 - attribute \src "libresoc.v:175496.3-175514.6" + attribute \src "libresoc.v:179140.3-179158.6" + wire width 64 $2\spr1$6[63:0]$13046 + attribute \src "libresoc.v:178931.3-178949.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:175660.3-175683.6" - wire width 2 $2\xer_ca$10[1:0]$12638 - attribute \src "libresoc.v:175684.3-175704.6" + attribute \src "libresoc.v:179095.3-179118.6" + wire width 2 $2\xer_ca$10[1:0]$13040 + attribute \src "libresoc.v:179119.3-179139.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:175615.3-175638.6" - wire width 2 $2\xer_ov$9[1:0]$12632 - attribute \src "libresoc.v:175639.3-175659.6" + attribute \src "libresoc.v:179050.3-179073.6" + wire width 2 $2\xer_ov$9[1:0]$13034 + attribute \src "libresoc.v:179074.3-179094.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:175573.3-175593.6" - wire $2\xer_so$8[0:0]$12626 - attribute \src "libresoc.v:175594.3-175614.6" + attribute \src "libresoc.v:179008.3-179028.6" + wire $2\xer_so$8[0:0]$13028 + attribute \src "libresoc.v:179029.3-179049.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:175515.3-175556.6" + attribute \src "libresoc.v:178950.3-178991.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:175660.3-175683.6" - wire width 2 $3\xer_ca$10[1:0]$12639 - attribute \src "libresoc.v:175684.3-175704.6" + attribute \src "libresoc.v:179095.3-179118.6" + wire width 2 $3\xer_ca$10[1:0]$13041 + attribute \src "libresoc.v:179119.3-179139.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:175615.3-175638.6" - wire width 2 $3\xer_ov$9[1:0]$12633 - attribute \src "libresoc.v:175639.3-175659.6" + attribute \src "libresoc.v:179050.3-179073.6" + wire width 2 $3\xer_ov$9[1:0]$13035 + attribute \src "libresoc.v:179074.3-179094.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:175573.3-175593.6" - wire $3\xer_so$8[0:0]$12627 - attribute \src "libresoc.v:175594.3-175614.6" + attribute \src "libresoc.v:179008.3-179028.6" + wire $3\xer_so$8[0:0]$13029 + attribute \src "libresoc.v:179029.3-179049.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:175473.18-175473.106" - wire $eq$libresoc.v:175473$12609_Y - attribute \src "libresoc.v:175474.18-175474.106" - wire $eq$libresoc.v:175474$12610_Y - attribute \src "libresoc.v:175475.18-175475.106" - wire $eq$libresoc.v:175475$12611_Y - attribute \src "libresoc.v:175476.18-175476.106" - wire $eq$libresoc.v:175476$12612_Y - attribute \src "libresoc.v:175477.18-175477.106" - wire $eq$libresoc.v:175477$12613_Y - attribute \src "libresoc.v:175478.18-175478.106" - wire $eq$libresoc.v:175478$12614_Y - attribute \src "libresoc.v:175479.18-175479.106" - wire $eq$libresoc.v:175479$12615_Y + attribute \src "libresoc.v:178908.18-178908.106" + wire $eq$libresoc.v:178908$13011_Y + attribute \src "libresoc.v:178909.18-178909.106" + wire $eq$libresoc.v:178909$13012_Y + attribute \src "libresoc.v:178910.18-178910.106" + wire $eq$libresoc.v:178910$13013_Y + attribute \src "libresoc.v:178911.18-178911.106" + wire $eq$libresoc.v:178911$13014_Y + attribute \src "libresoc.v:178912.18-178912.106" + wire $eq$libresoc.v:178912$13015_Y + attribute \src "libresoc.v:178913.18-178913.106" + wire $eq$libresoc.v:178913$13016_Y + attribute \src "libresoc.v:178914.18-178914.106" + wire $eq$libresoc.v:178914$13017_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -368021,19 +375987,19 @@ module \spr_main wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 7 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 20 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:175214.7-175214.15" + attribute \src "libresoc.v:178649.7-178649.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 28 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 output 11 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \ra @@ -368041,9 +376007,9 @@ module \spr_main wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 6 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 18 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \spr1_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -368237,24 +376203,24 @@ module \spr_main wire output 15 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 10 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 26 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 input 9 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 2 output 24 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 8 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175473$12609 + cell $eq $eq$libresoc.v:178908$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368262,10 +376228,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175473$12609_Y + connect \Y $eq$libresoc.v:178908$13011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175474$12610 + cell $eq $eq$libresoc.v:178909$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368273,10 +376239,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175474$12610_Y + connect \Y $eq$libresoc.v:178909$13012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175475$12611 + cell $eq $eq$libresoc.v:178910$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368284,10 +376250,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175475$12611_Y + connect \Y $eq$libresoc.v:178910$13013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175476$12612 + cell $eq $eq$libresoc.v:178911$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368295,10 +376261,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175476$12612_Y + connect \Y $eq$libresoc.v:178911$13014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175477$12613 + cell $eq $eq$libresoc.v:178912$13015 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368306,10 +376272,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175477$12613_Y + connect \Y $eq$libresoc.v:178912$13015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:175478$12614 + cell $eq $eq$libresoc.v:178913$13016 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368317,10 +376283,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175478$12614_Y + connect \Y $eq$libresoc.v:178913$13016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:175479$12615 + cell $eq $eq$libresoc.v:178914$13017 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -368328,24 +376294,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:175479$12615_Y + connect \Y $eq$libresoc.v:178914$13017_Y end - attribute \src "libresoc.v:175214.7-175214.20" - process $proc$libresoc.v:175214$12645 + attribute \src "libresoc.v:178649.7-178649.20" + process $proc$libresoc.v:178649$13047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175480.3-175495.6" - process $proc$libresoc.v:175480$12616 + attribute \src "libresoc.v:178915.3-178930.6" + process $proc$libresoc.v:178915$13018 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$12617 $1\fast1$7[63:0]$12618 - attribute \src "libresoc.v:175481.5-175481.29" + assign $0\fast1$7[63:0]$13019 $1\fast1$7[63:0]$13020 + attribute \src "libresoc.v:178916.5-178916.29" switch \initial - attribute \src "libresoc.v:175481.9-175481.17" + attribute \src "libresoc.v:178916.9-178916.17" case 1'1 case end @@ -368354,30 +376320,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$12618 $2\fast1$7[63:0]$12619 + assign $1\fast1$7[63:0]$13020 $2\fast1$7[63:0]$13021 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$12619 \ra + assign $2\fast1$7[63:0]$13021 \ra case - assign $2\fast1$7[63:0]$12619 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13021 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$12618 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13020 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$12617 + update \fast1$7 $0\fast1$7[63:0]$13019 end - attribute \src "libresoc.v:175496.3-175514.6" - process $proc$libresoc.v:175496$12620 + attribute \src "libresoc.v:178931.3-178949.6" + process $proc$libresoc.v:178931$13022 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:175497.5-175497.29" + attribute \src "libresoc.v:178932.5-178932.29" switch \initial - attribute \src "libresoc.v:175497.9-175497.17" + attribute \src "libresoc.v:178932.9-178932.17" case 1'1 case end @@ -368403,17 +376369,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:175515.3-175556.6" - process $proc$libresoc.v:175515$12621 + attribute \src "libresoc.v:178950.3-178991.6" + process $proc$libresoc.v:178950$13023 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:175516.5-175516.29" + attribute \src "libresoc.v:178951.5-178951.29" switch \initial - attribute \src "libresoc.v:175516.9-175516.17" + attribute \src "libresoc.v:178951.9-178951.17" case 1'1 case end @@ -368464,14 +376430,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:175557.3-175572.6" - process $proc$libresoc.v:175557$12622 + attribute \src "libresoc.v:178992.3-179007.6" + process $proc$libresoc.v:178992$13024 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:175558.5-175558.29" + attribute \src "libresoc.v:178993.5-178993.29" switch \initial - attribute \src "libresoc.v:175558.9-175558.17" + attribute \src "libresoc.v:178993.9-178993.17" case 1'1 case end @@ -368496,14 +376462,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:175573.3-175593.6" - process $proc$libresoc.v:175573$12623 + attribute \src "libresoc.v:179008.3-179028.6" + process $proc$libresoc.v:179008$13025 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$12624 $1\xer_so$8[0:0]$12625 - attribute \src "libresoc.v:175574.5-175574.29" + assign $0\xer_so$8[0:0]$13026 $1\xer_so$8[0:0]$13027 + attribute \src "libresoc.v:179009.5-179009.29" switch \initial - attribute \src "libresoc.v:175574.9-175574.17" + attribute \src "libresoc.v:179009.9-179009.17" case 1'1 case end @@ -368512,39 +376478,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$12625 $2\xer_so$8[0:0]$12626 + assign $1\xer_so$8[0:0]$13027 $2\xer_so$8[0:0]$13028 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$12626 $3\xer_so$8[0:0]$12627 + assign $2\xer_so$8[0:0]$13028 $3\xer_so$8[0:0]$13029 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$12627 \ra [31] + assign $3\xer_so$8[0:0]$13029 \ra [31] case - assign $3\xer_so$8[0:0]$12627 1'0 + assign $3\xer_so$8[0:0]$13029 1'0 end case - assign $2\xer_so$8[0:0]$12626 1'0 + assign $2\xer_so$8[0:0]$13028 1'0 end case - assign $1\xer_so$8[0:0]$12625 1'0 + assign $1\xer_so$8[0:0]$13027 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$12624 + update \xer_so$8 $0\xer_so$8[0:0]$13026 end - attribute \src "libresoc.v:175594.3-175614.6" - process $proc$libresoc.v:175594$12628 + attribute \src "libresoc.v:179029.3-179049.6" + process $proc$libresoc.v:179029$13030 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:175595.5-175595.29" + attribute \src "libresoc.v:179030.5-179030.29" switch \initial - attribute \src "libresoc.v:175595.9-175595.17" + attribute \src "libresoc.v:179030.9-179030.17" case 1'1 case end @@ -368578,14 +376544,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:175615.3-175638.6" - process $proc$libresoc.v:175615$12629 + attribute \src "libresoc.v:179050.3-179073.6" + process $proc$libresoc.v:179050$13031 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$12630 $1\xer_ov$9[1:0]$12631 - attribute \src "libresoc.v:175616.5-175616.29" + assign $0\xer_ov$9[1:0]$13032 $1\xer_ov$9[1:0]$13033 + attribute \src "libresoc.v:179051.5-179051.29" switch \initial - attribute \src "libresoc.v:175616.9-175616.17" + attribute \src "libresoc.v:179051.9-179051.17" case 1'1 case end @@ -368594,40 +376560,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$12631 $2\xer_ov$9[1:0]$12632 + assign $1\xer_ov$9[1:0]$13033 $2\xer_ov$9[1:0]$13034 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$12632 $3\xer_ov$9[1:0]$12633 + assign $2\xer_ov$9[1:0]$13034 $3\xer_ov$9[1:0]$13035 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$12633 [0] \ra [30] - assign $3\xer_ov$9[1:0]$12633 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13035 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13035 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$12633 2'00 + assign $3\xer_ov$9[1:0]$13035 2'00 end case - assign $2\xer_ov$9[1:0]$12632 2'00 + assign $2\xer_ov$9[1:0]$13034 2'00 end case - assign $1\xer_ov$9[1:0]$12631 2'00 + assign $1\xer_ov$9[1:0]$13033 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$12630 + update \xer_ov$9 $0\xer_ov$9[1:0]$13032 end - attribute \src "libresoc.v:175639.3-175659.6" - process $proc$libresoc.v:175639$12634 + attribute \src "libresoc.v:179074.3-179094.6" + process $proc$libresoc.v:179074$13036 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:175640.5-175640.29" + attribute \src "libresoc.v:179075.5-179075.29" switch \initial - attribute \src "libresoc.v:175640.9-175640.17" + attribute \src "libresoc.v:179075.9-179075.17" case 1'1 case end @@ -368661,14 +376627,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:175660.3-175683.6" - process $proc$libresoc.v:175660$12635 + attribute \src "libresoc.v:179095.3-179118.6" + process $proc$libresoc.v:179095$13037 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$12636 $1\xer_ca$10[1:0]$12637 - attribute \src "libresoc.v:175661.5-175661.29" + assign $0\xer_ca$10[1:0]$13038 $1\xer_ca$10[1:0]$13039 + attribute \src "libresoc.v:179096.5-179096.29" switch \initial - attribute \src "libresoc.v:175661.9-175661.17" + attribute \src "libresoc.v:179096.9-179096.17" case 1'1 case end @@ -368677,40 +376643,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$12637 $2\xer_ca$10[1:0]$12638 + assign $1\xer_ca$10[1:0]$13039 $2\xer_ca$10[1:0]$13040 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$12638 $3\xer_ca$10[1:0]$12639 + assign $2\xer_ca$10[1:0]$13040 $3\xer_ca$10[1:0]$13041 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$12639 [0] \ra [29] - assign $3\xer_ca$10[1:0]$12639 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13041 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13041 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$12639 2'00 + assign $3\xer_ca$10[1:0]$13041 2'00 end case - assign $2\xer_ca$10[1:0]$12638 2'00 + assign $2\xer_ca$10[1:0]$13040 2'00 end case - assign $1\xer_ca$10[1:0]$12637 2'00 + assign $1\xer_ca$10[1:0]$13039 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$12636 + update \xer_ca$10 $0\xer_ca$10[1:0]$13038 end - attribute \src "libresoc.v:175684.3-175704.6" - process $proc$libresoc.v:175684$12640 + attribute \src "libresoc.v:179119.3-179139.6" + process $proc$libresoc.v:179119$13042 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:175685.5-175685.29" + attribute \src "libresoc.v:179120.5-179120.29" switch \initial - attribute \src "libresoc.v:175685.9-175685.17" + attribute \src "libresoc.v:179120.9-179120.17" case 1'1 case end @@ -368744,14 +376710,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:175705.3-175723.6" - process $proc$libresoc.v:175705$12641 + attribute \src "libresoc.v:179140.3-179158.6" + process $proc$libresoc.v:179140$13043 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$12642 $1\spr1$6[63:0]$12643 - attribute \src "libresoc.v:175706.5-175706.29" + assign $0\spr1$6[63:0]$13044 $1\spr1$6[63:0]$13045 + attribute \src "libresoc.v:179141.5-179141.29" switch \initial - attribute \src "libresoc.v:175706.9-175706.17" + attribute \src "libresoc.v:179141.9-179141.17" case 1'1 case end @@ -368760,64 +376726,64 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$12643 $2\spr1$6[63:0]$12644 + assign $1\spr1$6[63:0]$13045 $2\spr1$6[63:0]$13046 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$12644 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13046 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$12644 \ra + assign $2\spr1$6[63:0]$13046 \ra end case - assign $1\spr1$6[63:0]$12643 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13045 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$12642 + update \spr1$6 $0\spr1$6[63:0]$13044 end - connect \$11 $eq$libresoc.v:175473$12609_Y - connect \$13 $eq$libresoc.v:175474$12610_Y - connect \$15 $eq$libresoc.v:175475$12611_Y - connect \$17 $eq$libresoc.v:175476$12612_Y - connect \$19 $eq$libresoc.v:175477$12613_Y - connect \$21 $eq$libresoc.v:175478$12614_Y - connect \$23 $eq$libresoc.v:175479$12615_Y + connect \$11 $eq$libresoc.v:178908$13011_Y + connect \$13 $eq$libresoc.v:178909$13012_Y + connect \$15 $eq$libresoc.v:178910$13013_Y + connect \$17 $eq$libresoc.v:178911$13014_Y + connect \$19 $eq$libresoc.v:178912$13015_Y + connect \$21 $eq$libresoc.v:178913$13016_Y + connect \$23 $eq$libresoc.v:178914$13017_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:175731.1-176546.10" +attribute \src "libresoc.v:179166.1-179981.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:175858.3-175888.6" + attribute \src "libresoc.v:179293.3-179323.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:175889.3-175919.6" + attribute \src "libresoc.v:179324.3-179354.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:175732.7-175732.20" + attribute \src "libresoc.v:179167.7-179167.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175920.3-176232.6" + attribute \src "libresoc.v:179355.3-179667.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:176233.3-176545.6" + attribute \src "libresoc.v:179668.3-179980.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:175858.3-175888.6" + attribute \src "libresoc.v:179293.3-179323.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:175889.3-175919.6" + attribute \src "libresoc.v:179324.3-179354.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:175920.3-176232.6" + attribute \src "libresoc.v:179355.3-179667.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:176233.3-176545.6" + attribute \src "libresoc.v:179668.3-179980.6" wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:175732.7-175732.15" + attribute \src "libresoc.v:179167.7-179167.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -368930,30 +376896,30 @@ module \sprmap attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:175732.7-175732.20" - process $proc$libresoc.v:175732$12650 + attribute \src "libresoc.v:179167.7-179167.20" + process $proc$libresoc.v:179167$13052 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175858.3-175888.6" - process $proc$libresoc.v:175858$12646 + attribute \src "libresoc.v:179293.3-179323.6" + process $proc$libresoc.v:179293$13048 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:175859.5-175859.29" + attribute \src "libresoc.v:179294.5-179294.29" switch \initial - attribute \src "libresoc.v:175859.9-175859.17" + attribute \src "libresoc.v:179294.9-179294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -368993,18 +376959,18 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:175889.3-175919.6" - process $proc$libresoc.v:175889$12647 + attribute \src "libresoc.v:179324.3-179354.6" + process $proc$libresoc.v:179324$13049 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:175890.5-175890.29" + attribute \src "libresoc.v:179325.5-179325.29" switch \initial - attribute \src "libresoc.v:175890.9-175890.17" + attribute \src "libresoc.v:179325.9-179325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -369044,18 +377010,18 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:175920.3-176232.6" - process $proc$libresoc.v:175920$12648 + attribute \src "libresoc.v:179355.3-179667.6" + process $proc$libresoc.v:179355$13050 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:175921.5-175921.29" + attribute \src "libresoc.v:179356.5-179356.29" switch \initial - attribute \src "libresoc.v:175921.9-175921.17" + attribute \src "libresoc.v:179356.9-179356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -369471,18 +377437,18 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:176233.3-176545.6" - process $proc$libresoc.v:176233$12649 + attribute \src "libresoc.v:179668.3-179980.6" + process $proc$libresoc.v:179668$13051 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:176234.5-176234.29" + attribute \src "libresoc.v:179669.5-179669.29" switch \initial - attribute \src "libresoc.v:176234.9-176234.17" + attribute \src "libresoc.v:179669.9-179669.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -369899,36 +377865,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:176550.1-177365.10" +attribute \src "libresoc.v:179985.1-180800.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" -module \sprmap$209 - attribute \src "libresoc.v:176677.3-176707.6" +module \sprmap$212 + attribute \src "libresoc.v:180112.3-180142.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:176708.3-176738.6" + attribute \src "libresoc.v:180143.3-180173.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:176551.7-176551.20" + attribute \src "libresoc.v:179986.7-179986.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176739.3-177051.6" + attribute \src "libresoc.v:180174.3-180486.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:177052.3-177364.6" + attribute \src "libresoc.v:180487.3-180799.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:176677.3-176707.6" + attribute \src "libresoc.v:180112.3-180142.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:176708.3-176738.6" + attribute \src "libresoc.v:180143.3-180173.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:176739.3-177051.6" + attribute \src "libresoc.v:180174.3-180486.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:177052.3-177364.6" + attribute \src "libresoc.v:180487.3-180799.6" wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:176551.7-176551.15" + attribute \src "libresoc.v:179986.7-179986.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -370041,30 +378007,30 @@ module \sprmap$209 attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:176551.7-176551.20" - process $proc$libresoc.v:176551$12655 + attribute \src "libresoc.v:179986.7-179986.20" + process $proc$libresoc.v:179986$13057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176677.3-176707.6" - process $proc$libresoc.v:176677$12651 + attribute \src "libresoc.v:180112.3-180142.6" + process $proc$libresoc.v:180112$13053 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:176678.5-176678.29" + attribute \src "libresoc.v:180113.5-180113.29" switch \initial - attribute \src "libresoc.v:176678.9-176678.17" + attribute \src "libresoc.v:180113.9-180113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -370104,18 +378070,18 @@ module \sprmap$209 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:176708.3-176738.6" - process $proc$libresoc.v:176708$12652 + attribute \src "libresoc.v:180143.3-180173.6" + process $proc$libresoc.v:180143$13054 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:176709.5-176709.29" + attribute \src "libresoc.v:180144.5-180144.29" switch \initial - attribute \src "libresoc.v:176709.9-176709.17" + attribute \src "libresoc.v:180144.9-180144.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -370155,18 +378121,18 @@ module \sprmap$209 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:176739.3-177051.6" - process $proc$libresoc.v:176739$12653 + attribute \src "libresoc.v:180174.3-180486.6" + process $proc$libresoc.v:180174$13055 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:176740.5-176740.29" + attribute \src "libresoc.v:180175.5-180175.29" switch \initial - attribute \src "libresoc.v:176740.9-176740.17" + attribute \src "libresoc.v:180175.9-180175.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -370582,18 +378548,18 @@ module \sprmap$209 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:177052.3-177364.6" - process $proc$libresoc.v:177052$12654 + attribute \src "libresoc.v:180487.3-180799.6" + process $proc$libresoc.v:180487$13056 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:177053.5-177053.29" + attribute \src "libresoc.v:180488.5-180488.29" switch \initial - attribute \src "libresoc.v:177053.9-177053.17" + attribute \src "libresoc.v:180488.9-180488.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -371010,37 +378976,37 @@ module \sprmap$209 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:177369.1-177427.10" +attribute \src "libresoc.v:180804.1-180862.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:177370.7-177370.20" + attribute \src "libresoc.v:180805.7-180805.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177415.3-177423.6" - wire width 4 $0\q_int$next[3:0]$12666 - attribute \src "libresoc.v:177413.3-177414.27" + attribute \src "libresoc.v:180850.3-180858.6" + wire width 4 $0\q_int$next[3:0]$13068 + attribute \src "libresoc.v:180848.3-180849.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:177415.3-177423.6" - wire width 4 $1\q_int$next[3:0]$12667 - attribute \src "libresoc.v:177392.13-177392.25" + attribute \src "libresoc.v:180850.3-180858.6" + wire width 4 $1\q_int$next[3:0]$13069 + attribute \src "libresoc.v:180827.13-180827.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:177405.17-177405.96" - wire width 4 $and$libresoc.v:177405$12656_Y - attribute \src "libresoc.v:177410.17-177410.96" - wire width 4 $and$libresoc.v:177410$12661_Y - attribute \src "libresoc.v:177407.18-177407.93" - wire width 4 $not$libresoc.v:177407$12658_Y - attribute \src "libresoc.v:177409.17-177409.92" - wire width 4 $not$libresoc.v:177409$12660_Y - attribute \src "libresoc.v:177412.17-177412.92" - wire width 4 $not$libresoc.v:177412$12663_Y - attribute \src "libresoc.v:177406.18-177406.98" - wire width 4 $or$libresoc.v:177406$12657_Y - attribute \src "libresoc.v:177408.18-177408.99" - wire width 4 $or$libresoc.v:177408$12659_Y - attribute \src "libresoc.v:177411.17-177411.97" - wire width 4 $or$libresoc.v:177411$12662_Y + attribute \src "libresoc.v:180840.17-180840.96" + wire width 4 $and$libresoc.v:180840$13058_Y + attribute \src "libresoc.v:180845.17-180845.96" + wire width 4 $and$libresoc.v:180845$13063_Y + attribute \src "libresoc.v:180842.18-180842.93" + wire width 4 $not$libresoc.v:180842$13060_Y + attribute \src "libresoc.v:180844.17-180844.92" + wire width 4 $not$libresoc.v:180844$13062_Y + attribute \src "libresoc.v:180847.17-180847.92" + wire width 4 $not$libresoc.v:180847$13065_Y + attribute \src "libresoc.v:180841.18-180841.98" + wire width 4 $or$libresoc.v:180841$13059_Y + attribute \src "libresoc.v:180843.18-180843.99" + wire width 4 $or$libresoc.v:180843$13061_Y + attribute \src "libresoc.v:180846.17-180846.97" + wire width 4 $or$libresoc.v:180846$13064_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -371057,11 +379023,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177370.7-177370.15" + attribute \src "libresoc.v:180805.7-180805.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int @@ -371078,7 +379044,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177405$12656 + cell $and $and$libresoc.v:180840$13058 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371086,10 +379052,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177405$12656_Y + connect \Y $and$libresoc.v:180840$13058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177410$12661 + cell $and $and$libresoc.v:180845$13063 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371097,34 +379063,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177410$12661_Y + connect \Y $and$libresoc.v:180845$13063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177407$12658 + cell $not $not$libresoc.v:180842$13060 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:177407$12658_Y + connect \Y $not$libresoc.v:180842$13060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177409$12660 + cell $not $not$libresoc.v:180844$13062 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:177409$12660_Y + connect \Y $not$libresoc.v:180844$13062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177412$12663 + cell $not $not$libresoc.v:180847$13065 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:177412$12663_Y + connect \Y $not$libresoc.v:180847$13065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177406$12657 + cell $or $or$libresoc.v:180841$13059 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371132,10 +379098,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177406$12657_Y + connect \Y $or$libresoc.v:180841$13059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177408$12659 + cell $or $or$libresoc.v:180843$13061 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371143,10 +379109,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177408$12659_Y + connect \Y $or$libresoc.v:180843$13061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177411$12662 + cell $or $or$libresoc.v:180846$13064 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -371154,39 +379120,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177411$12662_Y + connect \Y $or$libresoc.v:180846$13064_Y end - attribute \src "libresoc.v:177370.7-177370.20" - process $proc$libresoc.v:177370$12668 + attribute \src "libresoc.v:180805.7-180805.20" + process $proc$libresoc.v:180805$13070 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177392.13-177392.25" - process $proc$libresoc.v:177392$12669 + attribute \src "libresoc.v:180827.13-180827.25" + process $proc$libresoc.v:180827$13071 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:177413.3-177414.27" - process $proc$libresoc.v:177413$12664 + attribute \src "libresoc.v:180848.3-180849.27" + process $proc$libresoc.v:180848$13066 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:177415.3-177423.6" - process $proc$libresoc.v:177415$12665 + attribute \src "libresoc.v:180850.3-180858.6" + process $proc$libresoc.v:180850$13067 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12666 $1\q_int$next[3:0]$12667 - attribute \src "libresoc.v:177416.5-177416.29" + assign $0\q_int$next[3:0]$13068 $1\q_int$next[3:0]$13069 + attribute \src "libresoc.v:180851.5-180851.29" switch \initial - attribute \src "libresoc.v:177416.9-177416.17" + attribute \src "libresoc.v:180851.9-180851.17" case 1'1 case end @@ -371195,56 +379161,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12667 4'0000 + assign $1\q_int$next[3:0]$13069 4'0000 case - assign $1\q_int$next[3:0]$12667 \$5 + assign $1\q_int$next[3:0]$13069 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12666 + update \q_int$next $0\q_int$next[3:0]$13068 end - connect \$9 $and$libresoc.v:177405$12656_Y - connect \$11 $or$libresoc.v:177406$12657_Y - connect \$13 $not$libresoc.v:177407$12658_Y - connect \$15 $or$libresoc.v:177408$12659_Y - connect \$1 $not$libresoc.v:177409$12660_Y - connect \$3 $and$libresoc.v:177410$12661_Y - connect \$5 $or$libresoc.v:177411$12662_Y - connect \$7 $not$libresoc.v:177412$12663_Y + connect \$9 $and$libresoc.v:180840$13058_Y + connect \$11 $or$libresoc.v:180841$13059_Y + connect \$13 $not$libresoc.v:180842$13060_Y + connect \$15 $or$libresoc.v:180843$13061_Y + connect \$1 $not$libresoc.v:180844$13062_Y + connect \$3 $and$libresoc.v:180845$13063_Y + connect \$5 $or$libresoc.v:180846$13064_Y + connect \$7 $not$libresoc.v:180847$13065_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177431.1-177489.10" +attribute \src "libresoc.v:180866.1-180924.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:177432.7-177432.20" + attribute \src "libresoc.v:180867.7-180867.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177477.3-177485.6" - wire width 6 $0\q_int$next[5:0]$12680 - attribute \src "libresoc.v:177475.3-177476.27" + attribute \src "libresoc.v:180912.3-180920.6" + wire width 6 $0\q_int$next[5:0]$13082 + attribute \src "libresoc.v:180910.3-180911.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:177477.3-177485.6" - wire width 6 $1\q_int$next[5:0]$12681 - attribute \src "libresoc.v:177454.13-177454.26" + attribute \src "libresoc.v:180912.3-180920.6" + wire width 6 $1\q_int$next[5:0]$13083 + attribute \src "libresoc.v:180889.13-180889.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:177467.17-177467.96" - wire width 6 $and$libresoc.v:177467$12670_Y - attribute \src "libresoc.v:177472.17-177472.96" - wire width 6 $and$libresoc.v:177472$12675_Y - attribute \src "libresoc.v:177469.18-177469.93" - wire width 6 $not$libresoc.v:177469$12672_Y - attribute \src "libresoc.v:177471.17-177471.92" - wire width 6 $not$libresoc.v:177471$12674_Y - attribute \src "libresoc.v:177474.17-177474.92" - wire width 6 $not$libresoc.v:177474$12677_Y - attribute \src "libresoc.v:177468.18-177468.98" - wire width 6 $or$libresoc.v:177468$12671_Y - attribute \src "libresoc.v:177470.18-177470.99" - wire width 6 $or$libresoc.v:177470$12673_Y - attribute \src "libresoc.v:177473.17-177473.97" - wire width 6 $or$libresoc.v:177473$12676_Y + attribute \src "libresoc.v:180902.17-180902.96" + wire width 6 $and$libresoc.v:180902$13072_Y + attribute \src "libresoc.v:180907.17-180907.96" + wire width 6 $and$libresoc.v:180907$13077_Y + attribute \src "libresoc.v:180904.18-180904.93" + wire width 6 $not$libresoc.v:180904$13074_Y + attribute \src "libresoc.v:180906.17-180906.92" + wire width 6 $not$libresoc.v:180906$13076_Y + attribute \src "libresoc.v:180909.17-180909.92" + wire width 6 $not$libresoc.v:180909$13079_Y + attribute \src "libresoc.v:180903.18-180903.98" + wire width 6 $or$libresoc.v:180903$13073_Y + attribute \src "libresoc.v:180905.18-180905.99" + wire width 6 $or$libresoc.v:180905$13075_Y + attribute \src "libresoc.v:180908.17-180908.97" + wire width 6 $or$libresoc.v:180908$13078_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -371261,11 +379227,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177432.7-177432.15" + attribute \src "libresoc.v:180867.7-180867.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 6 \q_int @@ -371282,7 +379248,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177467$12670 + cell $and $and$libresoc.v:180902$13072 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -371290,10 +379256,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177467$12670_Y + connect \Y $and$libresoc.v:180902$13072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177472$12675 + cell $and $and$libresoc.v:180907$13077 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -371301,34 +379267,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177472$12675_Y + connect \Y $and$libresoc.v:180907$13077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177469$12672 + cell $not $not$libresoc.v:180904$13074 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:177469$12672_Y + connect \Y $not$libresoc.v:180904$13074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177471$12674 + cell $not $not$libresoc.v:180906$13076 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:177471$12674_Y + connect \Y $not$libresoc.v:180906$13076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177474$12677 + cell $not $not$libresoc.v:180909$13079 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:177474$12677_Y + connect \Y $not$libresoc.v:180909$13079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177468$12671 + cell $or $or$libresoc.v:180903$13073 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -371336,10 +379302,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177468$12671_Y + connect \Y $or$libresoc.v:180903$13073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177470$12673 + cell $or $or$libresoc.v:180905$13075 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -371347,10 +379313,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177470$12673_Y + connect \Y $or$libresoc.v:180905$13075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177473$12676 + cell $or $or$libresoc.v:180908$13078 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -371358,39 +379324,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177473$12676_Y + connect \Y $or$libresoc.v:180908$13078_Y end - attribute \src "libresoc.v:177432.7-177432.20" - process $proc$libresoc.v:177432$12682 + attribute \src "libresoc.v:180867.7-180867.20" + process $proc$libresoc.v:180867$13084 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177454.13-177454.26" - process $proc$libresoc.v:177454$12683 + attribute \src "libresoc.v:180889.13-180889.26" + process $proc$libresoc.v:180889$13085 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:177475.3-177476.27" - process $proc$libresoc.v:177475$12678 + attribute \src "libresoc.v:180910.3-180911.27" + process $proc$libresoc.v:180910$13080 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:177477.3-177485.6" - process $proc$libresoc.v:177477$12679 + attribute \src "libresoc.v:180912.3-180920.6" + process $proc$libresoc.v:180912$13081 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12680 $1\q_int$next[5:0]$12681 - attribute \src "libresoc.v:177478.5-177478.29" + assign $0\q_int$next[5:0]$13082 $1\q_int$next[5:0]$13083 + attribute \src "libresoc.v:180913.5-180913.29" switch \initial - attribute \src "libresoc.v:177478.9-177478.17" + attribute \src "libresoc.v:180913.9-180913.17" case 1'1 case end @@ -371399,56 +379365,260 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12681 6'000000 + assign $1\q_int$next[5:0]$13083 6'000000 case - assign $1\q_int$next[5:0]$12681 \$5 + assign $1\q_int$next[5:0]$13083 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12680 + update \q_int$next $0\q_int$next[5:0]$13082 end - connect \$9 $and$libresoc.v:177467$12670_Y - connect \$11 $or$libresoc.v:177468$12671_Y - connect \$13 $not$libresoc.v:177469$12672_Y - connect \$15 $or$libresoc.v:177470$12673_Y - connect \$1 $not$libresoc.v:177471$12674_Y - connect \$3 $and$libresoc.v:177472$12675_Y - connect \$5 $or$libresoc.v:177473$12676_Y - connect \$7 $not$libresoc.v:177474$12677_Y + connect \$9 $and$libresoc.v:180902$13072_Y + connect \$11 $or$libresoc.v:180903$13073_Y + connect \$13 $not$libresoc.v:180904$13074_Y + connect \$15 $or$libresoc.v:180905$13075_Y + connect \$1 $not$libresoc.v:180906$13076_Y + connect \$3 $and$libresoc.v:180907$13077_Y + connect \$5 $or$libresoc.v:180908$13078_Y + connect \$7 $not$libresoc.v:180909$13079_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177493.1-177551.10" +attribute \src "libresoc.v:180928.1-180986.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" -module \src_l$116 - attribute \src "libresoc.v:177494.7-177494.20" +module \src_l$101 + attribute \src "libresoc.v:180929.7-180929.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177539.3-177547.6" - wire width 5 $0\q_int$next[4:0]$12694 - attribute \src "libresoc.v:177537.3-177538.27" + attribute \src "libresoc.v:180974.3-180982.6" + wire width 3 $0\q_int$next[2:0]$13096 + attribute \src "libresoc.v:180972.3-180973.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:180974.3-180982.6" + wire width 3 $1\q_int$next[2:0]$13097 + attribute \src "libresoc.v:180951.13-180951.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:180964.17-180964.96" + wire width 3 $and$libresoc.v:180964$13086_Y + attribute \src "libresoc.v:180969.17-180969.96" + wire width 3 $and$libresoc.v:180969$13091_Y + attribute \src "libresoc.v:180966.18-180966.93" + wire width 3 $not$libresoc.v:180966$13088_Y + attribute \src "libresoc.v:180968.17-180968.92" + wire width 3 $not$libresoc.v:180968$13090_Y + attribute \src "libresoc.v:180971.17-180971.92" + wire width 3 $not$libresoc.v:180971$13093_Y + attribute \src "libresoc.v:180965.18-180965.98" + wire width 3 $or$libresoc.v:180965$13087_Y + attribute \src "libresoc.v:180967.18-180967.99" + wire width 3 $or$libresoc.v:180967$13089_Y + attribute \src "libresoc.v:180970.17-180970.97" + wire width 3 $or$libresoc.v:180970$13092_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst + attribute \src "libresoc.v:180929.7-180929.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$libresoc.v:180964$13086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:180964$13086_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$libresoc.v:180969$13091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:180969$13091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$libresoc.v:180966$13088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:180966$13088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$libresoc.v:180968$13090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180968$13090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$libresoc.v:180971$13093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:180971$13093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$libresoc.v:180965$13087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:180965$13087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$libresoc.v:180967$13089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:180967$13089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$libresoc.v:180970$13092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:180970$13092_Y + end + attribute \src "libresoc.v:180929.7-180929.20" + process $proc$libresoc.v:180929$13098 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:180951.13-180951.25" + process $proc$libresoc.v:180951$13099 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:180972.3-180973.27" + process $proc$libresoc.v:180972$13094 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:180974.3-180982.6" + process $proc$libresoc.v:180974$13095 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13096 $1\q_int$next[2:0]$13097 + attribute \src "libresoc.v:180975.5-180975.29" + switch \initial + attribute \src "libresoc.v:180975.9-180975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13097 3'000 + case + assign $1\q_int$next[2:0]$13097 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13096 + end + connect \$9 $and$libresoc.v:180964$13086_Y + connect \$11 $or$libresoc.v:180965$13087_Y + connect \$13 $not$libresoc.v:180966$13088_Y + connect \$15 $or$libresoc.v:180967$13089_Y + connect \$1 $not$libresoc.v:180968$13090_Y + connect \$3 $and$libresoc.v:180969$13091_Y + connect \$5 $or$libresoc.v:180970$13092_Y + connect \$7 $not$libresoc.v:180971$13093_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:180990.1-181048.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$119 + attribute \src "libresoc.v:180991.7-180991.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181036.3-181044.6" + wire width 5 $0\q_int$next[4:0]$13110 + attribute \src "libresoc.v:181034.3-181035.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:177539.3-177547.6" - wire width 5 $1\q_int$next[4:0]$12695 - attribute \src "libresoc.v:177516.13-177516.26" + attribute \src "libresoc.v:181036.3-181044.6" + wire width 5 $1\q_int$next[4:0]$13111 + attribute \src "libresoc.v:181013.13-181013.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:177529.17-177529.96" - wire width 5 $and$libresoc.v:177529$12684_Y - attribute \src "libresoc.v:177534.17-177534.96" - wire width 5 $and$libresoc.v:177534$12689_Y - attribute \src "libresoc.v:177531.18-177531.93" - wire width 5 $not$libresoc.v:177531$12686_Y - attribute \src "libresoc.v:177533.17-177533.92" - wire width 5 $not$libresoc.v:177533$12688_Y - attribute \src "libresoc.v:177536.17-177536.92" - wire width 5 $not$libresoc.v:177536$12691_Y - attribute \src "libresoc.v:177530.18-177530.98" - wire width 5 $or$libresoc.v:177530$12685_Y - attribute \src "libresoc.v:177532.18-177532.99" - wire width 5 $or$libresoc.v:177532$12687_Y - attribute \src "libresoc.v:177535.17-177535.97" - wire width 5 $or$libresoc.v:177535$12690_Y + attribute \src "libresoc.v:181026.17-181026.96" + wire width 5 $and$libresoc.v:181026$13100_Y + attribute \src "libresoc.v:181031.17-181031.96" + wire width 5 $and$libresoc.v:181031$13105_Y + attribute \src "libresoc.v:181028.18-181028.93" + wire width 5 $not$libresoc.v:181028$13102_Y + attribute \src "libresoc.v:181030.17-181030.92" + wire width 5 $not$libresoc.v:181030$13104_Y + attribute \src "libresoc.v:181033.17-181033.92" + wire width 5 $not$libresoc.v:181033$13107_Y + attribute \src "libresoc.v:181027.18-181027.98" + wire width 5 $or$libresoc.v:181027$13101_Y + attribute \src "libresoc.v:181029.18-181029.99" + wire width 5 $or$libresoc.v:181029$13103_Y + attribute \src "libresoc.v:181032.17-181032.97" + wire width 5 $or$libresoc.v:181032$13106_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -371465,11 +379635,11 @@ module \src_l$116 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177494.7-177494.15" + attribute \src "libresoc.v:180991.7-180991.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 5 \q_int @@ -371486,7 +379656,7 @@ module \src_l$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177529$12684 + cell $and $and$libresoc.v:181026$13100 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371494,10 +379664,10 @@ module \src_l$116 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177529$12684_Y + connect \Y $and$libresoc.v:181026$13100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177534$12689 + cell $and $and$libresoc.v:181031$13105 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371505,34 +379675,34 @@ module \src_l$116 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177534$12689_Y + connect \Y $and$libresoc.v:181031$13105_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177531$12686 + cell $not $not$libresoc.v:181028$13102 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:177531$12686_Y + connect \Y $not$libresoc.v:181028$13102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177533$12688 + cell $not $not$libresoc.v:181030$13104 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:177533$12688_Y + connect \Y $not$libresoc.v:181030$13104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177536$12691 + cell $not $not$libresoc.v:181033$13107 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:177536$12691_Y + connect \Y $not$libresoc.v:181033$13107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177530$12685 + cell $or $or$libresoc.v:181027$13101 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371540,10 +379710,10 @@ module \src_l$116 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177530$12685_Y + connect \Y $or$libresoc.v:181027$13101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177532$12687 + cell $or $or$libresoc.v:181029$13103 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371551,10 +379721,10 @@ module \src_l$116 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177532$12687_Y + connect \Y $or$libresoc.v:181029$13103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177535$12690 + cell $or $or$libresoc.v:181032$13106 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -371562,39 +379732,39 @@ module \src_l$116 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177535$12690_Y + connect \Y $or$libresoc.v:181032$13106_Y end - attribute \src "libresoc.v:177494.7-177494.20" - process $proc$libresoc.v:177494$12696 + attribute \src "libresoc.v:180991.7-180991.20" + process $proc$libresoc.v:180991$13112 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177516.13-177516.26" - process $proc$libresoc.v:177516$12697 + attribute \src "libresoc.v:181013.13-181013.26" + process $proc$libresoc.v:181013$13113 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:177537.3-177538.27" - process $proc$libresoc.v:177537$12692 + attribute \src "libresoc.v:181034.3-181035.27" + process $proc$libresoc.v:181034$13108 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:177539.3-177547.6" - process $proc$libresoc.v:177539$12693 + attribute \src "libresoc.v:181036.3-181044.6" + process $proc$libresoc.v:181036$13109 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$12694 $1\q_int$next[4:0]$12695 - attribute \src "libresoc.v:177540.5-177540.29" + assign $0\q_int$next[4:0]$13110 $1\q_int$next[4:0]$13111 + attribute \src "libresoc.v:181037.5-181037.29" switch \initial - attribute \src "libresoc.v:177540.9-177540.17" + attribute \src "libresoc.v:181037.9-181037.17" case 1'1 case end @@ -371603,56 +379773,56 @@ module \src_l$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$12695 5'00000 + assign $1\q_int$next[4:0]$13111 5'00000 case - assign $1\q_int$next[4:0]$12695 \$5 + assign $1\q_int$next[4:0]$13111 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$12694 + update \q_int$next $0\q_int$next[4:0]$13110 end - connect \$9 $and$libresoc.v:177529$12684_Y - connect \$11 $or$libresoc.v:177530$12685_Y - connect \$13 $not$libresoc.v:177531$12686_Y - connect \$15 $or$libresoc.v:177532$12687_Y - connect \$1 $not$libresoc.v:177533$12688_Y - connect \$3 $and$libresoc.v:177534$12689_Y - connect \$5 $or$libresoc.v:177535$12690_Y - connect \$7 $not$libresoc.v:177536$12691_Y + connect \$9 $and$libresoc.v:181026$13100_Y + connect \$11 $or$libresoc.v:181027$13101_Y + connect \$13 $not$libresoc.v:181028$13102_Y + connect \$15 $or$libresoc.v:181029$13103_Y + connect \$1 $not$libresoc.v:181030$13104_Y + connect \$3 $and$libresoc.v:181031$13105_Y + connect \$5 $or$libresoc.v:181032$13106_Y + connect \$7 $not$libresoc.v:181033$13107_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177555.1-177613.10" +attribute \src "libresoc.v:181052.1-181110.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" -module \src_l$124 - attribute \src "libresoc.v:177556.7-177556.20" +module \src_l$127 + attribute \src "libresoc.v:181053.7-181053.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177601.3-177609.6" - wire width 3 $0\q_int$next[2:0]$12708 - attribute \src "libresoc.v:177599.3-177600.27" + attribute \src "libresoc.v:181098.3-181106.6" + wire width 3 $0\q_int$next[2:0]$13124 + attribute \src "libresoc.v:181096.3-181097.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:177601.3-177609.6" - wire width 3 $1\q_int$next[2:0]$12709 - attribute \src "libresoc.v:177578.13-177578.25" + attribute \src "libresoc.v:181098.3-181106.6" + wire width 3 $1\q_int$next[2:0]$13125 + attribute \src "libresoc.v:181075.13-181075.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:177591.17-177591.96" - wire width 3 $and$libresoc.v:177591$12698_Y - attribute \src "libresoc.v:177596.17-177596.96" - wire width 3 $and$libresoc.v:177596$12703_Y - attribute \src "libresoc.v:177593.18-177593.93" - wire width 3 $not$libresoc.v:177593$12700_Y - attribute \src "libresoc.v:177595.17-177595.92" - wire width 3 $not$libresoc.v:177595$12702_Y - attribute \src "libresoc.v:177598.17-177598.92" - wire width 3 $not$libresoc.v:177598$12705_Y - attribute \src "libresoc.v:177592.18-177592.98" - wire width 3 $or$libresoc.v:177592$12699_Y - attribute \src "libresoc.v:177594.18-177594.99" - wire width 3 $or$libresoc.v:177594$12701_Y - attribute \src "libresoc.v:177597.17-177597.97" - wire width 3 $or$libresoc.v:177597$12704_Y + attribute \src "libresoc.v:181088.17-181088.96" + wire width 3 $and$libresoc.v:181088$13114_Y + attribute \src "libresoc.v:181093.17-181093.96" + wire width 3 $and$libresoc.v:181093$13119_Y + attribute \src "libresoc.v:181090.18-181090.93" + wire width 3 $not$libresoc.v:181090$13116_Y + attribute \src "libresoc.v:181092.17-181092.92" + wire width 3 $not$libresoc.v:181092$13118_Y + attribute \src "libresoc.v:181095.17-181095.92" + wire width 3 $not$libresoc.v:181095$13121_Y + attribute \src "libresoc.v:181089.18-181089.98" + wire width 3 $or$libresoc.v:181089$13115_Y + attribute \src "libresoc.v:181091.18-181091.99" + wire width 3 $or$libresoc.v:181091$13117_Y + attribute \src "libresoc.v:181094.17-181094.97" + wire width 3 $or$libresoc.v:181094$13120_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -371669,11 +379839,11 @@ module \src_l$124 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177556.7-177556.15" + attribute \src "libresoc.v:181053.7-181053.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -371690,7 +379860,7 @@ module \src_l$124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177591$12698 + cell $and $and$libresoc.v:181088$13114 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371698,10 +379868,10 @@ module \src_l$124 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177591$12698_Y + connect \Y $and$libresoc.v:181088$13114_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177596$12703 + cell $and $and$libresoc.v:181093$13119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371709,34 +379879,34 @@ module \src_l$124 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177596$12703_Y + connect \Y $and$libresoc.v:181093$13119_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177593$12700 + cell $not $not$libresoc.v:181090$13116 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:177593$12700_Y + connect \Y $not$libresoc.v:181090$13116_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177595$12702 + cell $not $not$libresoc.v:181092$13118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177595$12702_Y + connect \Y $not$libresoc.v:181092$13118_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177598$12705 + cell $not $not$libresoc.v:181095$13121 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177598$12705_Y + connect \Y $not$libresoc.v:181095$13121_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177592$12699 + cell $or $or$libresoc.v:181089$13115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371744,10 +379914,10 @@ module \src_l$124 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177592$12699_Y + connect \Y $or$libresoc.v:181089$13115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177594$12701 + cell $or $or$libresoc.v:181091$13117 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371755,10 +379925,10 @@ module \src_l$124 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177594$12701_Y + connect \Y $or$libresoc.v:181091$13117_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177597$12704 + cell $or $or$libresoc.v:181094$13120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371766,39 +379936,39 @@ module \src_l$124 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177597$12704_Y + connect \Y $or$libresoc.v:181094$13120_Y end - attribute \src "libresoc.v:177556.7-177556.20" - process $proc$libresoc.v:177556$12710 + attribute \src "libresoc.v:181053.7-181053.20" + process $proc$libresoc.v:181053$13126 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177578.13-177578.25" - process $proc$libresoc.v:177578$12711 + attribute \src "libresoc.v:181075.13-181075.25" + process $proc$libresoc.v:181075$13127 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:177599.3-177600.27" - process $proc$libresoc.v:177599$12706 + attribute \src "libresoc.v:181096.3-181097.27" + process $proc$libresoc.v:181096$13122 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:177601.3-177609.6" - process $proc$libresoc.v:177601$12707 + attribute \src "libresoc.v:181098.3-181106.6" + process $proc$libresoc.v:181098$13123 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12708 $1\q_int$next[2:0]$12709 - attribute \src "libresoc.v:177602.5-177602.29" + assign $0\q_int$next[2:0]$13124 $1\q_int$next[2:0]$13125 + attribute \src "libresoc.v:181099.5-181099.29" switch \initial - attribute \src "libresoc.v:177602.9-177602.17" + attribute \src "libresoc.v:181099.9-181099.17" case 1'1 case end @@ -371807,56 +379977,56 @@ module \src_l$124 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12709 3'000 + assign $1\q_int$next[2:0]$13125 3'000 case - assign $1\q_int$next[2:0]$12709 \$5 + assign $1\q_int$next[2:0]$13125 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12708 + update \q_int$next $0\q_int$next[2:0]$13124 end - connect \$9 $and$libresoc.v:177591$12698_Y - connect \$11 $or$libresoc.v:177592$12699_Y - connect \$13 $not$libresoc.v:177593$12700_Y - connect \$15 $or$libresoc.v:177594$12701_Y - connect \$1 $not$libresoc.v:177595$12702_Y - connect \$3 $and$libresoc.v:177596$12703_Y - connect \$5 $or$libresoc.v:177597$12704_Y - connect \$7 $not$libresoc.v:177598$12705_Y + connect \$9 $and$libresoc.v:181088$13114_Y + connect \$11 $or$libresoc.v:181089$13115_Y + connect \$13 $not$libresoc.v:181090$13116_Y + connect \$15 $or$libresoc.v:181091$13117_Y + connect \$1 $not$libresoc.v:181092$13118_Y + connect \$3 $and$libresoc.v:181093$13119_Y + connect \$5 $or$libresoc.v:181094$13120_Y + connect \$7 $not$libresoc.v:181095$13121_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177617.1-177675.10" +attribute \src "libresoc.v:181114.1-181172.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:177618.7-177618.20" + attribute \src "libresoc.v:181115.7-181115.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177663.3-177671.6" - wire width 3 $0\q_int$next[2:0]$12722 - attribute \src "libresoc.v:177661.3-177662.27" + attribute \src "libresoc.v:181160.3-181168.6" + wire width 3 $0\q_int$next[2:0]$13138 + attribute \src "libresoc.v:181158.3-181159.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:177663.3-177671.6" - wire width 3 $1\q_int$next[2:0]$12723 - attribute \src "libresoc.v:177640.13-177640.25" + attribute \src "libresoc.v:181160.3-181168.6" + wire width 3 $1\q_int$next[2:0]$13139 + attribute \src "libresoc.v:181137.13-181137.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:177653.17-177653.96" - wire width 3 $and$libresoc.v:177653$12712_Y - attribute \src "libresoc.v:177658.17-177658.96" - wire width 3 $and$libresoc.v:177658$12717_Y - attribute \src "libresoc.v:177655.18-177655.93" - wire width 3 $not$libresoc.v:177655$12714_Y - attribute \src "libresoc.v:177657.17-177657.92" - wire width 3 $not$libresoc.v:177657$12716_Y - attribute \src "libresoc.v:177660.17-177660.92" - wire width 3 $not$libresoc.v:177660$12719_Y - attribute \src "libresoc.v:177654.18-177654.98" - wire width 3 $or$libresoc.v:177654$12713_Y - attribute \src "libresoc.v:177656.18-177656.99" - wire width 3 $or$libresoc.v:177656$12715_Y - attribute \src "libresoc.v:177659.17-177659.97" - wire width 3 $or$libresoc.v:177659$12718_Y + attribute \src "libresoc.v:181150.17-181150.96" + wire width 3 $and$libresoc.v:181150$13128_Y + attribute \src "libresoc.v:181155.17-181155.96" + wire width 3 $and$libresoc.v:181155$13133_Y + attribute \src "libresoc.v:181152.18-181152.93" + wire width 3 $not$libresoc.v:181152$13130_Y + attribute \src "libresoc.v:181154.17-181154.92" + wire width 3 $not$libresoc.v:181154$13132_Y + attribute \src "libresoc.v:181157.17-181157.92" + wire width 3 $not$libresoc.v:181157$13135_Y + attribute \src "libresoc.v:181151.18-181151.98" + wire width 3 $or$libresoc.v:181151$13129_Y + attribute \src "libresoc.v:181153.18-181153.99" + wire width 3 $or$libresoc.v:181153$13131_Y + attribute \src "libresoc.v:181156.17-181156.97" + wire width 3 $or$libresoc.v:181156$13134_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -371873,11 +380043,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177618.7-177618.15" + attribute \src "libresoc.v:181115.7-181115.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -371894,7 +380064,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177653$12712 + cell $and $and$libresoc.v:181150$13128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371902,10 +380072,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177653$12712_Y + connect \Y $and$libresoc.v:181150$13128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177658$12717 + cell $and $and$libresoc.v:181155$13133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371913,34 +380083,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177658$12717_Y + connect \Y $and$libresoc.v:181155$13133_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177655$12714 + cell $not $not$libresoc.v:181152$13130 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:177655$12714_Y + connect \Y $not$libresoc.v:181152$13130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177657$12716 + cell $not $not$libresoc.v:181154$13132 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177657$12716_Y + connect \Y $not$libresoc.v:181154$13132_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177660$12719 + cell $not $not$libresoc.v:181157$13135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177660$12719_Y + connect \Y $not$libresoc.v:181157$13135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177654$12713 + cell $or $or$libresoc.v:181151$13129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371948,10 +380118,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177654$12713_Y + connect \Y $or$libresoc.v:181151$13129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177656$12715 + cell $or $or$libresoc.v:181153$13131 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371959,10 +380129,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177656$12715_Y + connect \Y $or$libresoc.v:181153$13131_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177659$12718 + cell $or $or$libresoc.v:181156$13134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -371970,39 +380140,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177659$12718_Y + connect \Y $or$libresoc.v:181156$13134_Y end - attribute \src "libresoc.v:177618.7-177618.20" - process $proc$libresoc.v:177618$12724 + attribute \src "libresoc.v:181115.7-181115.20" + process $proc$libresoc.v:181115$13140 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177640.13-177640.25" - process $proc$libresoc.v:177640$12725 + attribute \src "libresoc.v:181137.13-181137.25" + process $proc$libresoc.v:181137$13141 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:177661.3-177662.27" - process $proc$libresoc.v:177661$12720 + attribute \src "libresoc.v:181158.3-181159.27" + process $proc$libresoc.v:181158$13136 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:177663.3-177671.6" - process $proc$libresoc.v:177663$12721 + attribute \src "libresoc.v:181160.3-181168.6" + process $proc$libresoc.v:181160$13137 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12722 $1\q_int$next[2:0]$12723 - attribute \src "libresoc.v:177664.5-177664.29" + assign $0\q_int$next[2:0]$13138 $1\q_int$next[2:0]$13139 + attribute \src "libresoc.v:181161.5-181161.29" switch \initial - attribute \src "libresoc.v:177664.9-177664.17" + attribute \src "libresoc.v:181161.9-181161.17" case 1'1 case end @@ -372011,56 +380181,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12723 3'000 + assign $1\q_int$next[2:0]$13139 3'000 case - assign $1\q_int$next[2:0]$12723 \$5 + assign $1\q_int$next[2:0]$13139 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12722 + update \q_int$next $0\q_int$next[2:0]$13138 end - connect \$9 $and$libresoc.v:177653$12712_Y - connect \$11 $or$libresoc.v:177654$12713_Y - connect \$13 $not$libresoc.v:177655$12714_Y - connect \$15 $or$libresoc.v:177656$12715_Y - connect \$1 $not$libresoc.v:177657$12716_Y - connect \$3 $and$libresoc.v:177658$12717_Y - connect \$5 $or$libresoc.v:177659$12718_Y - connect \$7 $not$libresoc.v:177660$12719_Y + connect \$9 $and$libresoc.v:181150$13128_Y + connect \$11 $or$libresoc.v:181151$13129_Y + connect \$13 $not$libresoc.v:181152$13130_Y + connect \$15 $or$libresoc.v:181153$13131_Y + connect \$1 $not$libresoc.v:181154$13132_Y + connect \$3 $and$libresoc.v:181155$13133_Y + connect \$5 $or$libresoc.v:181156$13134_Y + connect \$7 $not$libresoc.v:181157$13135_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177679.1-177737.10" +attribute \src "libresoc.v:181176.1-181234.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" -module \src_l$36 - attribute \src "libresoc.v:177680.7-177680.20" +module \src_l$39 + attribute \src "libresoc.v:181177.7-181177.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177725.3-177733.6" - wire width 4 $0\q_int$next[3:0]$12736 - attribute \src "libresoc.v:177723.3-177724.27" + attribute \src "libresoc.v:181222.3-181230.6" + wire width 4 $0\q_int$next[3:0]$13152 + attribute \src "libresoc.v:181220.3-181221.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:177725.3-177733.6" - wire width 4 $1\q_int$next[3:0]$12737 - attribute \src "libresoc.v:177702.13-177702.25" + attribute \src "libresoc.v:181222.3-181230.6" + wire width 4 $1\q_int$next[3:0]$13153 + attribute \src "libresoc.v:181199.13-181199.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:177715.17-177715.96" - wire width 4 $and$libresoc.v:177715$12726_Y - attribute \src "libresoc.v:177720.17-177720.96" - wire width 4 $and$libresoc.v:177720$12731_Y - attribute \src "libresoc.v:177717.18-177717.93" - wire width 4 $not$libresoc.v:177717$12728_Y - attribute \src "libresoc.v:177719.17-177719.92" - wire width 4 $not$libresoc.v:177719$12730_Y - attribute \src "libresoc.v:177722.17-177722.92" - wire width 4 $not$libresoc.v:177722$12733_Y - attribute \src "libresoc.v:177716.18-177716.98" - wire width 4 $or$libresoc.v:177716$12727_Y - attribute \src "libresoc.v:177718.18-177718.99" - wire width 4 $or$libresoc.v:177718$12729_Y - attribute \src "libresoc.v:177721.17-177721.97" - wire width 4 $or$libresoc.v:177721$12732_Y + attribute \src "libresoc.v:181212.17-181212.96" + wire width 4 $and$libresoc.v:181212$13142_Y + attribute \src "libresoc.v:181217.17-181217.96" + wire width 4 $and$libresoc.v:181217$13147_Y + attribute \src "libresoc.v:181214.18-181214.93" + wire width 4 $not$libresoc.v:181214$13144_Y + attribute \src "libresoc.v:181216.17-181216.92" + wire width 4 $not$libresoc.v:181216$13146_Y + attribute \src "libresoc.v:181219.17-181219.92" + wire width 4 $not$libresoc.v:181219$13149_Y + attribute \src "libresoc.v:181213.18-181213.98" + wire width 4 $or$libresoc.v:181213$13143_Y + attribute \src "libresoc.v:181215.18-181215.99" + wire width 4 $or$libresoc.v:181215$13145_Y + attribute \src "libresoc.v:181218.17-181218.97" + wire width 4 $or$libresoc.v:181218$13148_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -372077,11 +380247,11 @@ module \src_l$36 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177680.7-177680.15" + attribute \src "libresoc.v:181177.7-181177.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 4 \q_int @@ -372098,7 +380268,7 @@ module \src_l$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177715$12726 + cell $and $and$libresoc.v:181212$13142 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372106,10 +380276,10 @@ module \src_l$36 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177715$12726_Y + connect \Y $and$libresoc.v:181212$13142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177720$12731 + cell $and $and$libresoc.v:181217$13147 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372117,34 +380287,34 @@ module \src_l$36 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177720$12731_Y + connect \Y $and$libresoc.v:181217$13147_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177717$12728 + cell $not $not$libresoc.v:181214$13144 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:177717$12728_Y + connect \Y $not$libresoc.v:181214$13144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177719$12730 + cell $not $not$libresoc.v:181216$13146 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:177719$12730_Y + connect \Y $not$libresoc.v:181216$13146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177722$12733 + cell $not $not$libresoc.v:181219$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:177722$12733_Y + connect \Y $not$libresoc.v:181219$13149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177716$12727 + cell $or $or$libresoc.v:181213$13143 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372152,10 +380322,10 @@ module \src_l$36 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177716$12727_Y + connect \Y $or$libresoc.v:181213$13143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177718$12729 + cell $or $or$libresoc.v:181215$13145 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372163,10 +380333,10 @@ module \src_l$36 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177718$12729_Y + connect \Y $or$libresoc.v:181215$13145_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177721$12732 + cell $or $or$libresoc.v:181218$13148 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -372174,39 +380344,39 @@ module \src_l$36 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177721$12732_Y + connect \Y $or$libresoc.v:181218$13148_Y end - attribute \src "libresoc.v:177680.7-177680.20" - process $proc$libresoc.v:177680$12738 + attribute \src "libresoc.v:181177.7-181177.20" + process $proc$libresoc.v:181177$13154 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177702.13-177702.25" - process $proc$libresoc.v:177702$12739 + attribute \src "libresoc.v:181199.13-181199.25" + process $proc$libresoc.v:181199$13155 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:177723.3-177724.27" - process $proc$libresoc.v:177723$12734 + attribute \src "libresoc.v:181220.3-181221.27" + process $proc$libresoc.v:181220$13150 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:177725.3-177733.6" - process $proc$libresoc.v:177725$12735 + attribute \src "libresoc.v:181222.3-181230.6" + process $proc$libresoc.v:181222$13151 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12736 $1\q_int$next[3:0]$12737 - attribute \src "libresoc.v:177726.5-177726.29" + assign $0\q_int$next[3:0]$13152 $1\q_int$next[3:0]$13153 + attribute \src "libresoc.v:181223.5-181223.29" switch \initial - attribute \src "libresoc.v:177726.9-177726.17" + attribute \src "libresoc.v:181223.9-181223.17" case 1'1 case end @@ -372215,56 +380385,56 @@ module \src_l$36 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12737 4'0000 + assign $1\q_int$next[3:0]$13153 4'0000 case - assign $1\q_int$next[3:0]$12737 \$5 + assign $1\q_int$next[3:0]$13153 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12736 + update \q_int$next $0\q_int$next[3:0]$13152 end - connect \$9 $and$libresoc.v:177715$12726_Y - connect \$11 $or$libresoc.v:177716$12727_Y - connect \$13 $not$libresoc.v:177717$12728_Y - connect \$15 $or$libresoc.v:177718$12729_Y - connect \$1 $not$libresoc.v:177719$12730_Y - connect \$3 $and$libresoc.v:177720$12731_Y - connect \$5 $or$libresoc.v:177721$12732_Y - connect \$7 $not$libresoc.v:177722$12733_Y + connect \$9 $and$libresoc.v:181212$13142_Y + connect \$11 $or$libresoc.v:181213$13143_Y + connect \$13 $not$libresoc.v:181214$13144_Y + connect \$15 $or$libresoc.v:181215$13145_Y + connect \$1 $not$libresoc.v:181216$13146_Y + connect \$3 $and$libresoc.v:181217$13147_Y + connect \$5 $or$libresoc.v:181218$13148_Y + connect \$7 $not$libresoc.v:181219$13149_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177741.1-177799.10" +attribute \src "libresoc.v:181238.1-181296.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" -module \src_l$52 - attribute \src "libresoc.v:177742.7-177742.20" +module \src_l$55 + attribute \src "libresoc.v:181239.7-181239.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177787.3-177795.6" - wire width 3 $0\q_int$next[2:0]$12750 - attribute \src "libresoc.v:177785.3-177786.27" + attribute \src "libresoc.v:181284.3-181292.6" + wire width 3 $0\q_int$next[2:0]$13166 + attribute \src "libresoc.v:181282.3-181283.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:177787.3-177795.6" - wire width 3 $1\q_int$next[2:0]$12751 - attribute \src "libresoc.v:177764.13-177764.25" + attribute \src "libresoc.v:181284.3-181292.6" + wire width 3 $1\q_int$next[2:0]$13167 + attribute \src "libresoc.v:181261.13-181261.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:177777.17-177777.96" - wire width 3 $and$libresoc.v:177777$12740_Y - attribute \src "libresoc.v:177782.17-177782.96" - wire width 3 $and$libresoc.v:177782$12745_Y - attribute \src "libresoc.v:177779.18-177779.93" - wire width 3 $not$libresoc.v:177779$12742_Y - attribute \src "libresoc.v:177781.17-177781.92" - wire width 3 $not$libresoc.v:177781$12744_Y - attribute \src "libresoc.v:177784.17-177784.92" - wire width 3 $not$libresoc.v:177784$12747_Y - attribute \src "libresoc.v:177778.18-177778.98" - wire width 3 $or$libresoc.v:177778$12741_Y - attribute \src "libresoc.v:177780.18-177780.99" - wire width 3 $or$libresoc.v:177780$12743_Y - attribute \src "libresoc.v:177783.17-177783.97" - wire width 3 $or$libresoc.v:177783$12746_Y + attribute \src "libresoc.v:181274.17-181274.96" + wire width 3 $and$libresoc.v:181274$13156_Y + attribute \src "libresoc.v:181279.17-181279.96" + wire width 3 $and$libresoc.v:181279$13161_Y + attribute \src "libresoc.v:181276.18-181276.93" + wire width 3 $not$libresoc.v:181276$13158_Y + attribute \src "libresoc.v:181278.17-181278.92" + wire width 3 $not$libresoc.v:181278$13160_Y + attribute \src "libresoc.v:181281.17-181281.92" + wire width 3 $not$libresoc.v:181281$13163_Y + attribute \src "libresoc.v:181275.18-181275.98" + wire width 3 $or$libresoc.v:181275$13157_Y + attribute \src "libresoc.v:181277.18-181277.99" + wire width 3 $or$libresoc.v:181277$13159_Y + attribute \src "libresoc.v:181280.17-181280.97" + wire width 3 $or$libresoc.v:181280$13162_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -372281,11 +380451,11 @@ module \src_l$52 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177742.7-177742.15" + attribute \src "libresoc.v:181239.7-181239.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -372302,7 +380472,7 @@ module \src_l$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177777$12740 + cell $and $and$libresoc.v:181274$13156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372310,10 +380480,10 @@ module \src_l$52 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177777$12740_Y + connect \Y $and$libresoc.v:181274$13156_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177782$12745 + cell $and $and$libresoc.v:181279$13161 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372321,34 +380491,34 @@ module \src_l$52 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177782$12745_Y + connect \Y $and$libresoc.v:181279$13161_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177779$12742 + cell $not $not$libresoc.v:181276$13158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:177779$12742_Y + connect \Y $not$libresoc.v:181276$13158_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177781$12744 + cell $not $not$libresoc.v:181278$13160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177781$12744_Y + connect \Y $not$libresoc.v:181278$13160_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177784$12747 + cell $not $not$libresoc.v:181281$13163 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177784$12747_Y + connect \Y $not$libresoc.v:181281$13163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177778$12741 + cell $or $or$libresoc.v:181275$13157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372356,10 +380526,10 @@ module \src_l$52 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177778$12741_Y + connect \Y $or$libresoc.v:181275$13157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177780$12743 + cell $or $or$libresoc.v:181277$13159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372367,10 +380537,10 @@ module \src_l$52 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177780$12743_Y + connect \Y $or$libresoc.v:181277$13159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177783$12746 + cell $or $or$libresoc.v:181280$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372378,243 +380548,39 @@ module \src_l$52 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177783$12746_Y + connect \Y $or$libresoc.v:181280$13162_Y end - attribute \src "libresoc.v:177742.7-177742.20" - process $proc$libresoc.v:177742$12752 + attribute \src "libresoc.v:181239.7-181239.20" + process $proc$libresoc.v:181239$13168 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177764.13-177764.25" - process $proc$libresoc.v:177764$12753 + attribute \src "libresoc.v:181261.13-181261.25" + process $proc$libresoc.v:181261$13169 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:177785.3-177786.27" - process $proc$libresoc.v:177785$12748 + attribute \src "libresoc.v:181282.3-181283.27" + process $proc$libresoc.v:181282$13164 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:177787.3-177795.6" - process $proc$libresoc.v:177787$12749 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$12750 $1\q_int$next[2:0]$12751 - attribute \src "libresoc.v:177788.5-177788.29" - switch \initial - attribute \src "libresoc.v:177788.9-177788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[2:0]$12751 3'000 - case - assign $1\q_int$next[2:0]$12751 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$12750 - end - connect \$9 $and$libresoc.v:177777$12740_Y - connect \$11 $or$libresoc.v:177778$12741_Y - connect \$13 $not$libresoc.v:177779$12742_Y - connect \$15 $or$libresoc.v:177780$12743_Y - connect \$1 $not$libresoc.v:177781$12744_Y - connect \$3 $and$libresoc.v:177782$12745_Y - connect \$5 $or$libresoc.v:177783$12746_Y - connect \$7 $not$libresoc.v:177784$12747_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:177803.1-177861.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" -attribute \generator "nMigen" -module \src_l$64 - attribute \src "libresoc.v:177804.7-177804.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:177849.3-177857.6" - wire width 6 $0\q_int$next[5:0]$12764 - attribute \src "libresoc.v:177847.3-177848.27" - wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:177849.3-177857.6" - wire width 6 $1\q_int$next[5:0]$12765 - attribute \src "libresoc.v:177826.13-177826.26" - wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:177839.17-177839.96" - wire width 6 $and$libresoc.v:177839$12754_Y - attribute \src "libresoc.v:177844.17-177844.96" - wire width 6 $and$libresoc.v:177844$12759_Y - attribute \src "libresoc.v:177841.18-177841.93" - wire width 6 $not$libresoc.v:177841$12756_Y - attribute \src "libresoc.v:177843.17-177843.92" - wire width 6 $not$libresoc.v:177843$12758_Y - attribute \src "libresoc.v:177846.17-177846.92" - wire width 6 $not$libresoc.v:177846$12761_Y - attribute \src "libresoc.v:177840.18-177840.98" - wire width 6 $or$libresoc.v:177840$12755_Y - attribute \src "libresoc.v:177842.18-177842.99" - wire width 6 $or$libresoc.v:177842$12757_Y - attribute \src "libresoc.v:177845.17-177845.97" - wire width 6 $or$libresoc.v:177845$12760_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 1 \coresync_rst - attribute \src "libresoc.v:177804.7-177804.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177839$12754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:177839$12754_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177844$12759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:177844$12759_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177841$12756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $not$libresoc.v:177841$12756_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177843$12758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:177843$12758_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177846$12761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:177846$12761_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177840$12755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:177840$12755_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177842$12757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:177842$12757_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177845$12760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:177845$12760_Y - end - attribute \src "libresoc.v:177804.7-177804.20" - process $proc$libresoc.v:177804$12766 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:177826.13-177826.26" - process $proc$libresoc.v:177826$12767 - assign { } { } - assign $1\q_int[5:0] 6'000000 - sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "libresoc.v:177847.3-177848.27" - process $proc$libresoc.v:177847$12762 - assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] - end - attribute \src "libresoc.v:177849.3-177857.6" - process $proc$libresoc.v:177849$12763 + attribute \src "libresoc.v:181284.3-181292.6" + process $proc$libresoc.v:181284$13165 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12764 $1\q_int$next[5:0]$12765 - attribute \src "libresoc.v:177850.5-177850.29" + assign $0\q_int$next[2:0]$13166 $1\q_int$next[2:0]$13167 + attribute \src "libresoc.v:181285.5-181285.29" switch \initial - attribute \src "libresoc.v:177850.9-177850.17" + attribute \src "libresoc.v:181285.9-181285.17" case 1'1 case end @@ -372623,202 +380589,202 @@ module \src_l$64 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12765 6'000000 + assign $1\q_int$next[2:0]$13167 3'000 case - assign $1\q_int$next[5:0]$12765 \$5 + assign $1\q_int$next[2:0]$13167 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12764 + update \q_int$next $0\q_int$next[2:0]$13166 end - connect \$9 $and$libresoc.v:177839$12754_Y - connect \$11 $or$libresoc.v:177840$12755_Y - connect \$13 $not$libresoc.v:177841$12756_Y - connect \$15 $or$libresoc.v:177842$12757_Y - connect \$1 $not$libresoc.v:177843$12758_Y - connect \$3 $and$libresoc.v:177844$12759_Y - connect \$5 $or$libresoc.v:177845$12760_Y - connect \$7 $not$libresoc.v:177846$12761_Y + connect \$9 $and$libresoc.v:181274$13156_Y + connect \$11 $or$libresoc.v:181275$13157_Y + connect \$13 $not$libresoc.v:181276$13158_Y + connect \$15 $or$libresoc.v:181277$13159_Y + connect \$1 $not$libresoc.v:181278$13160_Y + connect \$3 $and$libresoc.v:181279$13161_Y + connect \$5 $or$libresoc.v:181280$13162_Y + connect \$7 $not$libresoc.v:181281$13163_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177865.1-177923.10" +attribute \src "libresoc.v:181300.1-181358.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" -module \src_l$81 - attribute \src "libresoc.v:177866.7-177866.20" +module \src_l$67 + attribute \src "libresoc.v:181301.7-181301.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177911.3-177919.6" - wire width 3 $0\q_int$next[2:0]$12778 - attribute \src "libresoc.v:177909.3-177910.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:177911.3-177919.6" - wire width 3 $1\q_int$next[2:0]$12779 - attribute \src "libresoc.v:177888.13-177888.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:177901.17-177901.96" - wire width 3 $and$libresoc.v:177901$12768_Y - attribute \src "libresoc.v:177906.17-177906.96" - wire width 3 $and$libresoc.v:177906$12773_Y - attribute \src "libresoc.v:177903.18-177903.93" - wire width 3 $not$libresoc.v:177903$12770_Y - attribute \src "libresoc.v:177905.17-177905.92" - wire width 3 $not$libresoc.v:177905$12772_Y - attribute \src "libresoc.v:177908.17-177908.92" - wire width 3 $not$libresoc.v:177908$12775_Y - attribute \src "libresoc.v:177902.18-177902.98" - wire width 3 $or$libresoc.v:177902$12769_Y - attribute \src "libresoc.v:177904.18-177904.99" - wire width 3 $or$libresoc.v:177904$12771_Y - attribute \src "libresoc.v:177907.17-177907.97" - wire width 3 $or$libresoc.v:177907$12774_Y + attribute \src "libresoc.v:181346.3-181354.6" + wire width 6 $0\q_int$next[5:0]$13180 + attribute \src "libresoc.v:181344.3-181345.27" + wire width 6 $0\q_int[5:0] + attribute \src "libresoc.v:181346.3-181354.6" + wire width 6 $1\q_int$next[5:0]$13181 + attribute \src "libresoc.v:181323.13-181323.26" + wire width 6 $1\q_int[5:0] + attribute \src "libresoc.v:181336.17-181336.96" + wire width 6 $and$libresoc.v:181336$13170_Y + attribute \src "libresoc.v:181341.17-181341.96" + wire width 6 $and$libresoc.v:181341$13175_Y + attribute \src "libresoc.v:181338.18-181338.93" + wire width 6 $not$libresoc.v:181338$13172_Y + attribute \src "libresoc.v:181340.17-181340.92" + wire width 6 $not$libresoc.v:181340$13174_Y + attribute \src "libresoc.v:181343.17-181343.92" + wire width 6 $not$libresoc.v:181343$13177_Y + attribute \src "libresoc.v:181337.18-181337.98" + wire width 6 $or$libresoc.v:181337$13171_Y + attribute \src "libresoc.v:181339.18-181339.99" + wire width 6 $or$libresoc.v:181339$13173_Y + attribute \src "libresoc.v:181342.17-181342.97" + wire width 6 $or$libresoc.v:181342$13176_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 + wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 + wire width 6 \$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 + wire width 6 \$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 + wire width 6 \$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 + wire width 6 \$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 + wire width 6 \$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 + wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177866.7-177866.15" + attribute \src "libresoc.v:181301.7-181301.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int + wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next + wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src + wire width 6 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src + wire width 6 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src + wire width 6 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src + wire width 6 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src + wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177901$12768 + cell $and $and$libresoc.v:181336$13170 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177901$12768_Y + connect \Y $and$libresoc.v:181336$13170_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177906$12773 + cell $and $and$libresoc.v:181341$13175 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177906$12773_Y + connect \Y $and$libresoc.v:181341$13175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177903$12770 + cell $not $not$libresoc.v:181338$13172 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:177903$12770_Y + connect \Y $not$libresoc.v:181338$13172_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177905$12772 + cell $not $not$libresoc.v:181340$13174 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:177905$12772_Y + connect \Y $not$libresoc.v:181340$13174_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177908$12775 + cell $not $not$libresoc.v:181343$13177 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:177908$12775_Y + connect \Y $not$libresoc.v:181343$13177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177902$12769 + cell $or $or$libresoc.v:181337$13171 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177902$12769_Y + connect \Y $or$libresoc.v:181337$13171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177904$12771 + cell $or $or$libresoc.v:181339$13173 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177904$12771_Y + connect \Y $or$libresoc.v:181339$13173_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177907$12774 + cell $or $or$libresoc.v:181342$13176 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177907$12774_Y + connect \Y $or$libresoc.v:181342$13176_Y end - attribute \src "libresoc.v:177866.7-177866.20" - process $proc$libresoc.v:177866$12780 + attribute \src "libresoc.v:181301.7-181301.20" + process $proc$libresoc.v:181301$13182 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177888.13-177888.25" - process $proc$libresoc.v:177888$12781 + attribute \src "libresoc.v:181323.13-181323.26" + process $proc$libresoc.v:181323$13183 assign { } { } - assign $1\q_int[2:0] 3'000 + assign $1\q_int[5:0] 6'000000 sync always sync init - update \q_int $1\q_int[2:0] + update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:177909.3-177910.27" - process $proc$libresoc.v:177909$12776 + attribute \src "libresoc.v:181344.3-181345.27" + process $proc$libresoc.v:181344$13178 assign { } { } - assign $0\q_int[2:0] \q_int$next + assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk - update \q_int $0\q_int[2:0] + update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:177911.3-177919.6" - process $proc$libresoc.v:177911$12777 + attribute \src "libresoc.v:181346.3-181354.6" + process $proc$libresoc.v:181346$13179 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12778 $1\q_int$next[2:0]$12779 - attribute \src "libresoc.v:177912.5-177912.29" + assign $0\q_int$next[5:0]$13180 $1\q_int$next[5:0]$13181 + attribute \src "libresoc.v:181347.5-181347.29" switch \initial - attribute \src "libresoc.v:177912.9-177912.17" + attribute \src "libresoc.v:181347.9-181347.17" case 1'1 case end @@ -372827,56 +380793,56 @@ module \src_l$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12779 3'000 + assign $1\q_int$next[5:0]$13181 6'000000 case - assign $1\q_int$next[2:0]$12779 \$5 + assign $1\q_int$next[5:0]$13181 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12778 + update \q_int$next $0\q_int$next[5:0]$13180 end - connect \$9 $and$libresoc.v:177901$12768_Y - connect \$11 $or$libresoc.v:177902$12769_Y - connect \$13 $not$libresoc.v:177903$12770_Y - connect \$15 $or$libresoc.v:177904$12771_Y - connect \$1 $not$libresoc.v:177905$12772_Y - connect \$3 $and$libresoc.v:177906$12773_Y - connect \$5 $or$libresoc.v:177907$12774_Y - connect \$7 $not$libresoc.v:177908$12775_Y + connect \$9 $and$libresoc.v:181336$13170_Y + connect \$11 $or$libresoc.v:181337$13171_Y + connect \$13 $not$libresoc.v:181338$13172_Y + connect \$15 $or$libresoc.v:181339$13173_Y + connect \$1 $not$libresoc.v:181340$13174_Y + connect \$3 $and$libresoc.v:181341$13175_Y + connect \$5 $or$libresoc.v:181342$13176_Y + connect \$7 $not$libresoc.v:181343$13177_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177927.1-177985.10" +attribute \src "libresoc.v:181362.1-181420.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" -module \src_l$98 - attribute \src "libresoc.v:177928.7-177928.20" +module \src_l$84 + attribute \src "libresoc.v:181363.7-181363.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177973.3-177981.6" - wire width 3 $0\q_int$next[2:0]$12792 - attribute \src "libresoc.v:177971.3-177972.27" + attribute \src "libresoc.v:181408.3-181416.6" + wire width 3 $0\q_int$next[2:0]$13194 + attribute \src "libresoc.v:181406.3-181407.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:177973.3-177981.6" - wire width 3 $1\q_int$next[2:0]$12793 - attribute \src "libresoc.v:177950.13-177950.25" + attribute \src "libresoc.v:181408.3-181416.6" + wire width 3 $1\q_int$next[2:0]$13195 + attribute \src "libresoc.v:181385.13-181385.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:177963.17-177963.96" - wire width 3 $and$libresoc.v:177963$12782_Y - attribute \src "libresoc.v:177968.17-177968.96" - wire width 3 $and$libresoc.v:177968$12787_Y - attribute \src "libresoc.v:177965.18-177965.93" - wire width 3 $not$libresoc.v:177965$12784_Y - attribute \src "libresoc.v:177967.17-177967.92" - wire width 3 $not$libresoc.v:177967$12786_Y - attribute \src "libresoc.v:177970.17-177970.92" - wire width 3 $not$libresoc.v:177970$12789_Y - attribute \src "libresoc.v:177964.18-177964.98" - wire width 3 $or$libresoc.v:177964$12783_Y - attribute \src "libresoc.v:177966.18-177966.99" - wire width 3 $or$libresoc.v:177966$12785_Y - attribute \src "libresoc.v:177969.17-177969.97" - wire width 3 $or$libresoc.v:177969$12788_Y + attribute \src "libresoc.v:181398.17-181398.96" + wire width 3 $and$libresoc.v:181398$13184_Y + attribute \src "libresoc.v:181403.17-181403.96" + wire width 3 $and$libresoc.v:181403$13189_Y + attribute \src "libresoc.v:181400.18-181400.93" + wire width 3 $not$libresoc.v:181400$13186_Y + attribute \src "libresoc.v:181402.17-181402.92" + wire width 3 $not$libresoc.v:181402$13188_Y + attribute \src "libresoc.v:181405.17-181405.92" + wire width 3 $not$libresoc.v:181405$13191_Y + attribute \src "libresoc.v:181399.18-181399.98" + wire width 3 $or$libresoc.v:181399$13185_Y + attribute \src "libresoc.v:181401.18-181401.99" + wire width 3 $or$libresoc.v:181401$13187_Y + attribute \src "libresoc.v:181404.17-181404.97" + wire width 3 $or$libresoc.v:181404$13190_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -372893,11 +380859,11 @@ module \src_l$98 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177928.7-177928.15" + attribute \src "libresoc.v:181363.7-181363.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire width 3 \q_int @@ -372914,7 +380880,7 @@ module \src_l$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:177963$12782 + cell $and $and$libresoc.v:181398$13184 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372922,10 +380888,10 @@ module \src_l$98 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:177963$12782_Y + connect \Y $and$libresoc.v:181398$13184_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:177968$12787 + cell $and $and$libresoc.v:181403$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372933,34 +380899,34 @@ module \src_l$98 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:177968$12787_Y + connect \Y $and$libresoc.v:181403$13189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:177965$12784 + cell $not $not$libresoc.v:181400$13186 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:177965$12784_Y + connect \Y $not$libresoc.v:181400$13186_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:177967$12786 + cell $not $not$libresoc.v:181402$13188 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177967$12786_Y + connect \Y $not$libresoc.v:181402$13188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:177970$12789 + cell $not $not$libresoc.v:181405$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:177970$12789_Y + connect \Y $not$libresoc.v:181405$13191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:177964$12783 + cell $or $or$libresoc.v:181399$13185 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372968,10 +380934,10 @@ module \src_l$98 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:177964$12783_Y + connect \Y $or$libresoc.v:181399$13185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:177966$12785 + cell $or $or$libresoc.v:181401$13187 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372979,10 +380945,10 @@ module \src_l$98 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:177966$12785_Y + connect \Y $or$libresoc.v:181401$13187_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:177969$12788 + cell $or $or$libresoc.v:181404$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -372990,39 +380956,39 @@ module \src_l$98 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:177969$12788_Y + connect \Y $or$libresoc.v:181404$13190_Y end - attribute \src "libresoc.v:177928.7-177928.20" - process $proc$libresoc.v:177928$12794 + attribute \src "libresoc.v:181363.7-181363.20" + process $proc$libresoc.v:181363$13196 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177950.13-177950.25" - process $proc$libresoc.v:177950$12795 + attribute \src "libresoc.v:181385.13-181385.25" + process $proc$libresoc.v:181385$13197 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:177971.3-177972.27" - process $proc$libresoc.v:177971$12790 + attribute \src "libresoc.v:181406.3-181407.27" + process $proc$libresoc.v:181406$13192 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:177973.3-177981.6" - process $proc$libresoc.v:177973$12791 + attribute \src "libresoc.v:181408.3-181416.6" + process $proc$libresoc.v:181408$13193 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12792 $1\q_int$next[2:0]$12793 - attribute \src "libresoc.v:177974.5-177974.29" + assign $0\q_int$next[2:0]$13194 $1\q_int$next[2:0]$13195 + attribute \src "libresoc.v:181409.5-181409.29" switch \initial - attribute \src "libresoc.v:177974.9-177974.17" + attribute \src "libresoc.v:181409.9-181409.17" case 1'1 case end @@ -373031,56 +380997,56 @@ module \src_l$98 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12793 3'000 + assign $1\q_int$next[2:0]$13195 3'000 case - assign $1\q_int$next[2:0]$12793 \$5 + assign $1\q_int$next[2:0]$13195 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12792 + update \q_int$next $0\q_int$next[2:0]$13194 end - connect \$9 $and$libresoc.v:177963$12782_Y - connect \$11 $or$libresoc.v:177964$12783_Y - connect \$13 $not$libresoc.v:177965$12784_Y - connect \$15 $or$libresoc.v:177966$12785_Y - connect \$1 $not$libresoc.v:177967$12786_Y - connect \$3 $and$libresoc.v:177968$12787_Y - connect \$5 $or$libresoc.v:177969$12788_Y - connect \$7 $not$libresoc.v:177970$12789_Y + connect \$9 $and$libresoc.v:181398$13184_Y + connect \$11 $or$libresoc.v:181399$13185_Y + connect \$13 $not$libresoc.v:181400$13186_Y + connect \$15 $or$libresoc.v:181401$13187_Y + connect \$1 $not$libresoc.v:181402$13188_Y + connect \$3 $and$libresoc.v:181403$13189_Y + connect \$5 $or$libresoc.v:181404$13190_Y + connect \$7 $not$libresoc.v:181405$13191_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:177989.1-178047.10" +attribute \src "libresoc.v:181424.1-181482.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:177990.7-177990.20" + attribute \src "libresoc.v:181425.7-181425.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178035.3-178043.6" - wire $0\q_int$next[0:0]$12806 - attribute \src "libresoc.v:178033.3-178034.27" + attribute \src "libresoc.v:181470.3-181478.6" + wire $0\q_int$next[0:0]$13208 + attribute \src "libresoc.v:181468.3-181469.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:178035.3-178043.6" - wire $1\q_int$next[0:0]$12807 - attribute \src "libresoc.v:178012.7-178012.19" + attribute \src "libresoc.v:181470.3-181478.6" + wire $1\q_int$next[0:0]$13209 + attribute \src "libresoc.v:181447.7-181447.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:178025.17-178025.96" - wire $and$libresoc.v:178025$12796_Y - attribute \src "libresoc.v:178030.17-178030.96" - wire $and$libresoc.v:178030$12801_Y - attribute \src "libresoc.v:178027.18-178027.99" - wire $not$libresoc.v:178027$12798_Y - attribute \src "libresoc.v:178029.17-178029.98" - wire $not$libresoc.v:178029$12800_Y - attribute \src "libresoc.v:178032.17-178032.98" - wire $not$libresoc.v:178032$12803_Y - attribute \src "libresoc.v:178026.18-178026.104" - wire $or$libresoc.v:178026$12797_Y - attribute \src "libresoc.v:178028.18-178028.105" - wire $or$libresoc.v:178028$12799_Y - attribute \src "libresoc.v:178031.17-178031.103" - wire $or$libresoc.v:178031$12802_Y + attribute \src "libresoc.v:181460.17-181460.96" + wire $and$libresoc.v:181460$13198_Y + attribute \src "libresoc.v:181465.17-181465.96" + wire $and$libresoc.v:181465$13203_Y + attribute \src "libresoc.v:181462.18-181462.99" + wire $not$libresoc.v:181462$13200_Y + attribute \src "libresoc.v:181464.17-181464.98" + wire $not$libresoc.v:181464$13202_Y + attribute \src "libresoc.v:181467.17-181467.98" + wire $not$libresoc.v:181467$13205_Y + attribute \src "libresoc.v:181461.18-181461.104" + wire $or$libresoc.v:181461$13199_Y + attribute \src "libresoc.v:181463.18-181463.105" + wire $or$libresoc.v:181463$13201_Y + attribute \src "libresoc.v:181466.17-181466.103" + wire $or$libresoc.v:181466$13204_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -373097,11 +381063,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:177990.7-177990.15" + attribute \src "libresoc.v:181425.7-181425.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -373118,7 +381084,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:178025$12796 + cell $and $and$libresoc.v:181460$13198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373126,10 +381092,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:178025$12796_Y + connect \Y $and$libresoc.v:181460$13198_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:178030$12801 + cell $and $and$libresoc.v:181465$13203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373137,34 +381103,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:178030$12801_Y + connect \Y $and$libresoc.v:181465$13203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:178027$12798 + cell $not $not$libresoc.v:181462$13200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:178027$12798_Y + connect \Y $not$libresoc.v:181462$13200_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:178029$12800 + cell $not $not$libresoc.v:181464$13202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:178029$12800_Y + connect \Y $not$libresoc.v:181464$13202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:178032$12803 + cell $not $not$libresoc.v:181467$13205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:178032$12803_Y + connect \Y $not$libresoc.v:181467$13205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:178026$12797 + cell $or $or$libresoc.v:181461$13199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373172,10 +381138,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:178026$12797_Y + connect \Y $or$libresoc.v:181461$13199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:178028$12799 + cell $or $or$libresoc.v:181463$13201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373183,10 +381149,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:178028$12799_Y + connect \Y $or$libresoc.v:181463$13201_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:178031$12802 + cell $or $or$libresoc.v:181466$13204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373194,39 +381160,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:178031$12802_Y + connect \Y $or$libresoc.v:181466$13204_Y end - attribute \src "libresoc.v:177990.7-177990.20" - process $proc$libresoc.v:177990$12808 + attribute \src "libresoc.v:181425.7-181425.20" + process $proc$libresoc.v:181425$13210 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178012.7-178012.19" - process $proc$libresoc.v:178012$12809 + attribute \src "libresoc.v:181447.7-181447.19" + process $proc$libresoc.v:181447$13211 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:178033.3-178034.27" - process $proc$libresoc.v:178033$12804 + attribute \src "libresoc.v:181468.3-181469.27" + process $proc$libresoc.v:181468$13206 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:178035.3-178043.6" - process $proc$libresoc.v:178035$12805 + attribute \src "libresoc.v:181470.3-181478.6" + process $proc$libresoc.v:181470$13207 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12806 $1\q_int$next[0:0]$12807 - attribute \src "libresoc.v:178036.5-178036.29" + assign $0\q_int$next[0:0]$13208 $1\q_int$next[0:0]$13209 + attribute \src "libresoc.v:181471.5-181471.29" switch \initial - attribute \src "libresoc.v:178036.9-178036.17" + attribute \src "libresoc.v:181471.9-181471.17" case 1'1 case end @@ -373235,56 +381201,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12807 1'0 + assign $1\q_int$next[0:0]$13209 1'0 case - assign $1\q_int$next[0:0]$12807 \$5 + assign $1\q_int$next[0:0]$13209 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12806 + update \q_int$next $0\q_int$next[0:0]$13208 end - connect \$9 $and$libresoc.v:178025$12796_Y - connect \$11 $or$libresoc.v:178026$12797_Y - connect \$13 $not$libresoc.v:178027$12798_Y - connect \$15 $or$libresoc.v:178028$12799_Y - connect \$1 $not$libresoc.v:178029$12800_Y - connect \$3 $and$libresoc.v:178030$12801_Y - connect \$5 $or$libresoc.v:178031$12802_Y - connect \$7 $not$libresoc.v:178032$12803_Y + connect \$9 $and$libresoc.v:181460$13198_Y + connect \$11 $or$libresoc.v:181461$13199_Y + connect \$13 $not$libresoc.v:181462$13200_Y + connect \$15 $or$libresoc.v:181463$13201_Y + connect \$1 $not$libresoc.v:181464$13202_Y + connect \$3 $and$libresoc.v:181465$13203_Y + connect \$5 $or$libresoc.v:181466$13204_Y + connect \$7 $not$libresoc.v:181467$13205_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:178051.1-178109.10" +attribute \src "libresoc.v:181486.1-181544.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:178052.7-178052.20" + attribute \src "libresoc.v:181487.7-181487.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178097.3-178105.6" - wire $0\q_int$next[0:0]$12820 - attribute \src "libresoc.v:178095.3-178096.27" + attribute \src "libresoc.v:181532.3-181540.6" + wire $0\q_int$next[0:0]$13222 + attribute \src "libresoc.v:181530.3-181531.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:178097.3-178105.6" - wire $1\q_int$next[0:0]$12821 - attribute \src "libresoc.v:178074.7-178074.19" + attribute \src "libresoc.v:181532.3-181540.6" + wire $1\q_int$next[0:0]$13223 + attribute \src "libresoc.v:181509.7-181509.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:178087.17-178087.96" - wire $and$libresoc.v:178087$12810_Y - attribute \src "libresoc.v:178092.17-178092.96" - wire $and$libresoc.v:178092$12815_Y - attribute \src "libresoc.v:178089.18-178089.97" - wire $not$libresoc.v:178089$12812_Y - attribute \src "libresoc.v:178091.17-178091.96" - wire $not$libresoc.v:178091$12814_Y - attribute \src "libresoc.v:178094.17-178094.96" - wire $not$libresoc.v:178094$12817_Y - attribute \src "libresoc.v:178088.18-178088.102" - wire $or$libresoc.v:178088$12811_Y - attribute \src "libresoc.v:178090.18-178090.103" - wire $or$libresoc.v:178090$12813_Y - attribute \src "libresoc.v:178093.17-178093.101" - wire $or$libresoc.v:178093$12816_Y + attribute \src "libresoc.v:181522.17-181522.96" + wire $and$libresoc.v:181522$13212_Y + attribute \src "libresoc.v:181527.17-181527.96" + wire $and$libresoc.v:181527$13217_Y + attribute \src "libresoc.v:181524.18-181524.97" + wire $not$libresoc.v:181524$13214_Y + attribute \src "libresoc.v:181526.17-181526.96" + wire $not$libresoc.v:181526$13216_Y + attribute \src "libresoc.v:181529.17-181529.96" + wire $not$libresoc.v:181529$13219_Y + attribute \src "libresoc.v:181523.18-181523.102" + wire $or$libresoc.v:181523$13213_Y + attribute \src "libresoc.v:181525.18-181525.103" + wire $or$libresoc.v:181525$13215_Y + attribute \src "libresoc.v:181528.17-181528.101" + wire $or$libresoc.v:181528$13218_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -373301,11 +381267,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:178052.7-178052.15" + attribute \src "libresoc.v:181487.7-181487.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -373322,7 +381288,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:178087$12810 + cell $and $and$libresoc.v:181522$13212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373330,10 +381296,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:178087$12810_Y + connect \Y $and$libresoc.v:181522$13212_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:178092$12815 + cell $and $and$libresoc.v:181527$13217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373341,34 +381307,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:178092$12815_Y + connect \Y $and$libresoc.v:181527$13217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:178089$12812 + cell $not $not$libresoc.v:181524$13214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:178089$12812_Y + connect \Y $not$libresoc.v:181524$13214_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:178091$12814 + cell $not $not$libresoc.v:181526$13216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:178091$12814_Y + connect \Y $not$libresoc.v:181526$13216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:178094$12817 + cell $not $not$libresoc.v:181529$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:178094$12817_Y + connect \Y $not$libresoc.v:181529$13219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:178088$12811 + cell $or $or$libresoc.v:181523$13213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373376,10 +381342,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:178088$12811_Y + connect \Y $or$libresoc.v:181523$13213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:178090$12813 + cell $or $or$libresoc.v:181525$13215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373387,10 +381353,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:178090$12813_Y + connect \Y $or$libresoc.v:181525$13215_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:178093$12816 + cell $or $or$libresoc.v:181528$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -373398,39 +381364,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:178093$12816_Y + connect \Y $or$libresoc.v:181528$13218_Y end - attribute \src "libresoc.v:178052.7-178052.20" - process $proc$libresoc.v:178052$12822 + attribute \src "libresoc.v:181487.7-181487.20" + process $proc$libresoc.v:181487$13224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178074.7-178074.19" - process $proc$libresoc.v:178074$12823 + attribute \src "libresoc.v:181509.7-181509.19" + process $proc$libresoc.v:181509$13225 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:178095.3-178096.27" - process $proc$libresoc.v:178095$12818 + attribute \src "libresoc.v:181530.3-181531.27" + process $proc$libresoc.v:181530$13220 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:178097.3-178105.6" - process $proc$libresoc.v:178097$12819 + attribute \src "libresoc.v:181532.3-181540.6" + process $proc$libresoc.v:181532$13221 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12820 $1\q_int$next[0:0]$12821 - attribute \src "libresoc.v:178098.5-178098.29" + assign $0\q_int$next[0:0]$13222 $1\q_int$next[0:0]$13223 + attribute \src "libresoc.v:181533.5-181533.29" switch \initial - attribute \src "libresoc.v:178098.9-178098.17" + attribute \src "libresoc.v:181533.9-181533.17" case 1'1 case end @@ -373439,72 +381405,72 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12821 1'0 + assign $1\q_int$next[0:0]$13223 1'0 case - assign $1\q_int$next[0:0]$12821 \$5 + assign $1\q_int$next[0:0]$13223 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12820 + update \q_int$next $0\q_int$next[0:0]$13222 end - connect \$9 $and$libresoc.v:178087$12810_Y - connect \$11 $or$libresoc.v:178088$12811_Y - connect \$13 $not$libresoc.v:178089$12812_Y - connect \$15 $or$libresoc.v:178090$12813_Y - connect \$1 $not$libresoc.v:178091$12814_Y - connect \$3 $and$libresoc.v:178092$12815_Y - connect \$5 $or$libresoc.v:178093$12816_Y - connect \$7 $not$libresoc.v:178094$12817_Y + connect \$9 $and$libresoc.v:181522$13212_Y + connect \$11 $or$libresoc.v:181523$13213_Y + connect \$13 $not$libresoc.v:181524$13214_Y + connect \$15 $or$libresoc.v:181525$13215_Y + connect \$1 $not$libresoc.v:181526$13216_Y + connect \$3 $and$libresoc.v:181527$13217_Y + connect \$5 $or$libresoc.v:181528$13218_Y + connect \$7 $not$libresoc.v:181529$13219_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:178113.1-178368.10" +attribute \src "libresoc.v:181548.1-181803.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.state" +attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:178341.3-178350.6" + attribute \src "libresoc.v:181776.3-181785.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:178114.7-178114.20" + attribute \src "libresoc.v:181549.7-181549.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178322.3-178331.6" + attribute \src "libresoc.v:181757.3-181766.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:178313.3-178321.6" - wire width 4 $0\ren_delay$12$next[3:0]$12836 - attribute \src "libresoc.v:178253.3-178254.43" - wire width 4 $0\ren_delay$12[3:0]$12833 - attribute \src "libresoc.v:178234.13-178234.34" - wire width 4 $0\ren_delay$12[3:0]$12846 - attribute \src "libresoc.v:178332.3-178340.6" - wire width 4 $0\ren_delay$next[3:0]$12840 - attribute \src "libresoc.v:178255.3-178256.35" + attribute \src "libresoc.v:181748.3-181756.6" + wire width 4 $0\ren_delay$12$next[3:0]$13238 + attribute \src "libresoc.v:181688.3-181689.43" + wire width 4 $0\ren_delay$12[3:0]$13235 + attribute \src "libresoc.v:181669.13-181669.34" + wire width 4 $0\ren_delay$12[3:0]$13248 + attribute \src "libresoc.v:181767.3-181775.6" + wire width 4 $0\ren_delay$next[3:0]$13242 + attribute \src "libresoc.v:181690.3-181691.35" wire width 4 $0\ren_delay[3:0] - attribute \src "libresoc.v:178341.3-178350.6" + attribute \src "libresoc.v:181776.3-181785.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:178322.3-178331.6" + attribute \src "libresoc.v:181757.3-181766.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:178313.3-178321.6" - wire width 4 $1\ren_delay$12$next[3:0]$12837 - attribute \src "libresoc.v:178332.3-178340.6" - wire width 4 $1\ren_delay$next[3:0]$12841 - attribute \src "libresoc.v:178232.13-178232.29" + attribute \src "libresoc.v:181748.3-181756.6" + wire width 4 $1\ren_delay$12$next[3:0]$13239 + attribute \src "libresoc.v:181767.3-181775.6" + wire width 4 $1\ren_delay$next[3:0]$13243 + attribute \src "libresoc.v:181667.13-181667.29" wire width 4 $1\ren_delay[3:0] - attribute \src "libresoc.v:178245.18-178245.95" - wire width 64 $or$libresoc.v:178245$12824_Y - attribute \src "libresoc.v:178247.18-178247.124" - wire width 64 $or$libresoc.v:178247$12826_Y - attribute \src "libresoc.v:178248.18-178248.124" - wire width 64 $or$libresoc.v:178248$12827_Y - attribute \src "libresoc.v:178249.18-178249.97" - wire width 64 $or$libresoc.v:178249$12828_Y - attribute \src "libresoc.v:178251.17-178251.123" - wire width 64 $or$libresoc.v:178251$12830_Y - attribute \src "libresoc.v:178252.17-178252.123" - wire width 64 $or$libresoc.v:178252$12831_Y - attribute \src "libresoc.v:178246.18-178246.100" - wire $reduce_or$libresoc.v:178246$12825_Y - attribute \src "libresoc.v:178250.17-178250.95" - wire $reduce_or$libresoc.v:178250$12829_Y + attribute \src "libresoc.v:181680.18-181680.95" + wire width 64 $or$libresoc.v:181680$13226_Y + attribute \src "libresoc.v:181682.18-181682.124" + wire width 64 $or$libresoc.v:181682$13228_Y + attribute \src "libresoc.v:181683.18-181683.124" + wire width 64 $or$libresoc.v:181683$13229_Y + attribute \src "libresoc.v:181684.18-181684.97" + wire width 64 $or$libresoc.v:181684$13230_Y + attribute \src "libresoc.v:181686.17-181686.123" + wire width 64 $or$libresoc.v:181686$13232_Y + attribute \src "libresoc.v:181687.17-181687.123" + wire width 64 $or$libresoc.v:181687$13233_Y + attribute \src "libresoc.v:181681.18-181681.100" + wire $reduce_or$libresoc.v:181681$13227_Y + attribute \src "libresoc.v:181685.17-181685.95" + wire $reduce_or$libresoc.v:181685$13231_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -373522,25 +381488,25 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" wire width 64 \$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \cia__data_o + wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 1 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + wire width 4 input 2 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 11 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \data_i + wire width 64 input 5 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 8 \data_i$1 + wire width 64 input 9 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$2 - attribute \src "libresoc.v:178114.7-178114.15" + wire width 64 input 10 \data_i$2 + attribute \src "libresoc.v:181549.7-181549.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 6 \msr__data_o + wire width 64 output 7 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 5 \msr__ren + wire width 4 input 6 \msr__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_0_cia0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -373630,13 +381596,13 @@ module \state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 4 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 7 \state_nia_wen + wire width 4 input 8 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 3 \wen + wire width 4 input 4 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 10 \wen$3 + wire width 4 input 11 \wen$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:178245$12824 + cell $or $or$libresoc.v:181680$13226 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373644,10 +381610,10 @@ module \state parameter \Y_WIDTH 64 connect \A \$6 connect \B \$8 - connect \Y $or$libresoc.v:178245$12824_Y + connect \Y $or$libresoc.v:181680$13226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:178247$12826 + cell $or $or$libresoc.v:181682$13228 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373655,10 +381621,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \reg_1_msr1__data_o - connect \Y $or$libresoc.v:178247$12826_Y + connect \Y $or$libresoc.v:181682$13228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:178248$12827 + cell $or $or$libresoc.v:181683$13229 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373666,10 +381632,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_2_msr2__data_o connect \B \reg_3_msr3__data_o - connect \Y $or$libresoc.v:178248$12827_Y + connect \Y $or$libresoc.v:181683$13229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:178249$12828 + cell $or $or$libresoc.v:181684$13230 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373677,10 +381643,10 @@ module \state parameter \Y_WIDTH 64 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:178249$12828_Y + connect \Y $or$libresoc.v:181684$13230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:178251$12830 + cell $or $or$libresoc.v:181686$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373688,10 +381654,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \reg_1_cia1__data_o - connect \Y $or$libresoc.v:178251$12830_Y + connect \Y $or$libresoc.v:181686$13232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:178252$12831 + cell $or $or$libresoc.v:181687$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -373699,27 +381665,27 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_2_cia2__data_o connect \B \reg_3_cia3__data_o - connect \Y $or$libresoc.v:178252$12831_Y + connect \Y $or$libresoc.v:181687$13233_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:178246$12825 + cell $reduce_or $reduce_or$libresoc.v:181681$13227 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:178246$12825_Y + connect \Y $reduce_or$libresoc.v:181681$13227_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:178250$12829 + cell $reduce_or $reduce_or$libresoc.v:181685$13231 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:178250$12829_Y + connect \Y $reduce_or$libresoc.v:181685$13231_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:178257.15-178270.4" - cell \reg_0$132 \reg_0 + attribute \src "libresoc.v:181692.15-181705.4" + cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren connect \coresync_clk \coresync_clk @@ -373734,8 +381700,8 @@ module \state connect \nia0__wen \reg_0_nia0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:178271.15-178284.4" - cell \reg_1$133 \reg_1 + attribute \src "libresoc.v:181706.15-181719.4" + cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren connect \coresync_clk \coresync_clk @@ -373750,8 +381716,8 @@ module \state connect \nia1__wen \reg_1_nia1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:178285.15-178298.4" - cell \reg_2$134 \reg_2 + attribute \src "libresoc.v:181720.15-181733.4" + cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren connect \coresync_clk \coresync_clk @@ -373766,8 +381732,8 @@ module \state connect \nia2__wen \reg_2_nia2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:178299.15-178312.4" - cell \reg_3$135 \reg_3 + attribute \src "libresoc.v:181734.15-181747.4" + cell \reg_3$138 \reg_3 connect \cia3__data_o \reg_3_cia3__data_o connect \cia3__ren \reg_3_cia3__ren connect \coresync_clk \coresync_clk @@ -373781,52 +381747,52 @@ module \state connect \nia3__data_i \reg_3_nia3__data_i connect \nia3__wen \reg_3_nia3__wen end - attribute \src "libresoc.v:178114.7-178114.20" - process $proc$libresoc.v:178114$12843 + attribute \src "libresoc.v:181549.7-181549.20" + process $proc$libresoc.v:181549$13245 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178232.13-178232.29" - process $proc$libresoc.v:178232$12844 + attribute \src "libresoc.v:181667.13-181667.29" + process $proc$libresoc.v:181667$13246 assign { } { } assign $1\ren_delay[3:0] 4'0000 sync always sync init update \ren_delay $1\ren_delay[3:0] end - attribute \src "libresoc.v:178234.13-178234.34" - process $proc$libresoc.v:178234$12845 + attribute \src "libresoc.v:181669.13-181669.34" + process $proc$libresoc.v:181669$13247 assign { } { } - assign $0\ren_delay$12[3:0]$12846 4'0000 + assign $0\ren_delay$12[3:0]$13248 4'0000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[3:0]$12846 + update \ren_delay$12 $0\ren_delay$12[3:0]$13248 end - attribute \src "libresoc.v:178253.3-178254.43" - process $proc$libresoc.v:178253$12832 + attribute \src "libresoc.v:181688.3-181689.43" + process $proc$libresoc.v:181688$13234 assign { } { } - assign $0\ren_delay$12[3:0]$12833 \ren_delay$12$next + assign $0\ren_delay$12[3:0]$13235 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[3:0]$12833 + update \ren_delay$12 $0\ren_delay$12[3:0]$13235 end - attribute \src "libresoc.v:178255.3-178256.35" - process $proc$libresoc.v:178255$12834 + attribute \src "libresoc.v:181690.3-181691.35" + process $proc$libresoc.v:181690$13236 assign { } { } assign $0\ren_delay[3:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[3:0] end - attribute \src "libresoc.v:178313.3-178321.6" - process $proc$libresoc.v:178313$12835 + attribute \src "libresoc.v:181748.3-181756.6" + process $proc$libresoc.v:181748$13237 assign { } { } assign { } { } - assign $0\ren_delay$12$next[3:0]$12836 $1\ren_delay$12$next[3:0]$12837 - attribute \src "libresoc.v:178314.5-178314.29" + assign $0\ren_delay$12$next[3:0]$13238 $1\ren_delay$12$next[3:0]$13239 + attribute \src "libresoc.v:181749.5-181749.29" switch \initial - attribute \src "libresoc.v:178314.9-178314.17" + attribute \src "libresoc.v:181749.9-181749.17" case 1'1 case end @@ -373835,21 +381801,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[3:0]$12837 4'0000 + assign $1\ren_delay$12$next[3:0]$13239 4'0000 case - assign $1\ren_delay$12$next[3:0]$12837 \msr__ren + assign $1\ren_delay$12$next[3:0]$13239 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[3:0]$12836 + update \ren_delay$12$next $0\ren_delay$12$next[3:0]$13238 end - attribute \src "libresoc.v:178322.3-178331.6" - process $proc$libresoc.v:178322$12838 + attribute \src "libresoc.v:181757.3-181766.6" + process $proc$libresoc.v:181757$13240 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:178323.5-178323.29" + attribute \src "libresoc.v:181758.5-181758.29" switch \initial - attribute \src "libresoc.v:178323.9-178323.17" + attribute \src "libresoc.v:181758.9-181758.17" case 1'1 case end @@ -373865,14 +381831,14 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - attribute \src "libresoc.v:178332.3-178340.6" - process $proc$libresoc.v:178332$12839 + attribute \src "libresoc.v:181767.3-181775.6" + process $proc$libresoc.v:181767$13241 assign { } { } assign { } { } - assign $0\ren_delay$next[3:0]$12840 $1\ren_delay$next[3:0]$12841 - attribute \src "libresoc.v:178333.5-178333.29" + assign $0\ren_delay$next[3:0]$13242 $1\ren_delay$next[3:0]$13243 + attribute \src "libresoc.v:181768.5-181768.29" switch \initial - attribute \src "libresoc.v:178333.9-178333.17" + attribute \src "libresoc.v:181768.9-181768.17" case 1'1 case end @@ -373881,21 +381847,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[3:0]$12841 4'0000 + assign $1\ren_delay$next[3:0]$13243 4'0000 case - assign $1\ren_delay$next[3:0]$12841 \cia__ren + assign $1\ren_delay$next[3:0]$13243 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[3:0]$12840 + update \ren_delay$next $0\ren_delay$next[3:0]$13242 end - attribute \src "libresoc.v:178341.3-178350.6" - process $proc$libresoc.v:178341$12842 + attribute \src "libresoc.v:181776.3-181785.6" + process $proc$libresoc.v:181776$13244 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:178342.5-178342.29" + attribute \src "libresoc.v:181777.5-181777.29" switch \initial - attribute \src "libresoc.v:178342.9-178342.17" + attribute \src "libresoc.v:181777.9-181777.17" case 1'1 case end @@ -373911,14 +381877,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - connect \$10 $or$libresoc.v:178245$12824_Y - connect \$13 $reduce_or$libresoc.v:178246$12825_Y - connect \$15 $or$libresoc.v:178247$12826_Y - connect \$17 $or$libresoc.v:178248$12827_Y - connect \$19 $or$libresoc.v:178249$12828_Y - connect \$4 $reduce_or$libresoc.v:178250$12829_Y - connect \$6 $or$libresoc.v:178251$12830_Y - connect \$8 $or$libresoc.v:178252$12831_Y + connect \$10 $or$libresoc.v:181680$13226_Y + connect \$13 $reduce_or$libresoc.v:181681$13227_Y + connect \$15 $or$libresoc.v:181682$13228_Y + connect \$17 $or$libresoc.v:181683$13229_Y + connect \$19 $or$libresoc.v:181684$13230_Y + connect \$4 $reduce_or$libresoc.v:181685$13231_Y + connect \$6 $or$libresoc.v:181686$13232_Y + connect \$8 $or$libresoc.v:181687$13233_Y connect \reg_3_d_wr13__data_i \data_i connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i @@ -373937,37 +381903,37 @@ module \state connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:178372.1-178430.10" +attribute \src "libresoc.v:181807.1-181865.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:178373.7-178373.20" + attribute \src "libresoc.v:181808.7-181808.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178418.3-178426.6" - wire $0\q_int$next[0:0]$12857 - attribute \src "libresoc.v:178416.3-178417.27" + attribute \src "libresoc.v:181853.3-181861.6" + wire $0\q_int$next[0:0]$13259 + attribute \src "libresoc.v:181851.3-181852.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:178418.3-178426.6" - wire $1\q_int$next[0:0]$12858 - attribute \src "libresoc.v:178395.7-178395.19" + attribute \src "libresoc.v:181853.3-181861.6" + wire $1\q_int$next[0:0]$13260 + attribute \src "libresoc.v:181830.7-181830.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:178408.17-178408.96" - wire $and$libresoc.v:178408$12847_Y - attribute \src "libresoc.v:178413.17-178413.96" - wire $and$libresoc.v:178413$12852_Y - attribute \src "libresoc.v:178410.18-178410.93" - wire $not$libresoc.v:178410$12849_Y - attribute \src "libresoc.v:178412.17-178412.92" - wire $not$libresoc.v:178412$12851_Y - attribute \src "libresoc.v:178415.17-178415.92" - wire $not$libresoc.v:178415$12854_Y - attribute \src "libresoc.v:178409.18-178409.98" - wire $or$libresoc.v:178409$12848_Y - attribute \src "libresoc.v:178411.18-178411.99" - wire $or$libresoc.v:178411$12850_Y - attribute \src "libresoc.v:178414.17-178414.97" - wire $or$libresoc.v:178414$12853_Y + attribute \src "libresoc.v:181843.17-181843.96" + wire $and$libresoc.v:181843$13249_Y + attribute \src "libresoc.v:181848.17-181848.96" + wire $and$libresoc.v:181848$13254_Y + attribute \src "libresoc.v:181845.18-181845.93" + wire $not$libresoc.v:181845$13251_Y + attribute \src "libresoc.v:181847.17-181847.92" + wire $not$libresoc.v:181847$13253_Y + attribute \src "libresoc.v:181850.17-181850.92" + wire $not$libresoc.v:181850$13256_Y + attribute \src "libresoc.v:181844.18-181844.98" + wire $or$libresoc.v:181844$13250_Y + attribute \src "libresoc.v:181846.18-181846.99" + wire $or$libresoc.v:181846$13252_Y + attribute \src "libresoc.v:181849.17-181849.97" + wire $or$libresoc.v:181849$13255_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -373984,11 +381950,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:178373.7-178373.15" + attribute \src "libresoc.v:181808.7-181808.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -374005,7 +381971,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:178408$12847 + cell $and $and$libresoc.v:181843$13249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374013,10 +381979,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:178408$12847_Y + connect \Y $and$libresoc.v:181843$13249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:178413$12852 + cell $and $and$libresoc.v:181848$13254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374024,34 +381990,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:178413$12852_Y + connect \Y $and$libresoc.v:181848$13254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:178410$12849 + cell $not $not$libresoc.v:181845$13251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:178410$12849_Y + connect \Y $not$libresoc.v:181845$13251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:178412$12851 + cell $not $not$libresoc.v:181847$13253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:178412$12851_Y + connect \Y $not$libresoc.v:181847$13253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:178415$12854 + cell $not $not$libresoc.v:181850$13256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:178415$12854_Y + connect \Y $not$libresoc.v:181850$13256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:178409$12848 + cell $or $or$libresoc.v:181844$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374059,10 +382025,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:178409$12848_Y + connect \Y $or$libresoc.v:181844$13250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:178411$12850 + cell $or $or$libresoc.v:181846$13252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374070,10 +382036,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:178411$12850_Y + connect \Y $or$libresoc.v:181846$13252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:178414$12853 + cell $or $or$libresoc.v:181849$13255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -374081,39 +382047,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:178414$12853_Y + connect \Y $or$libresoc.v:181849$13255_Y end - attribute \src "libresoc.v:178373.7-178373.20" - process $proc$libresoc.v:178373$12859 + attribute \src "libresoc.v:181808.7-181808.20" + process $proc$libresoc.v:181808$13261 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178395.7-178395.19" - process $proc$libresoc.v:178395$12860 + attribute \src "libresoc.v:181830.7-181830.19" + process $proc$libresoc.v:181830$13262 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:178416.3-178417.27" - process $proc$libresoc.v:178416$12855 + attribute \src "libresoc.v:181851.3-181852.27" + process $proc$libresoc.v:181851$13257 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:178418.3-178426.6" - process $proc$libresoc.v:178418$12856 + attribute \src "libresoc.v:181853.3-181861.6" + process $proc$libresoc.v:181853$13258 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12857 $1\q_int$next[0:0]$12858 - attribute \src "libresoc.v:178419.5-178419.29" + assign $0\q_int$next[0:0]$13259 $1\q_int$next[0:0]$13260 + attribute \src "libresoc.v:181854.5-181854.29" switch \initial - attribute \src "libresoc.v:178419.9-178419.17" + attribute \src "libresoc.v:181854.9-181854.17" case 1'1 case end @@ -374122,1385 +382088,2687 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12858 1'0 + assign $1\q_int$next[0:0]$13260 1'0 case - assign $1\q_int$next[0:0]$12858 \$5 + assign $1\q_int$next[0:0]$13260 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12857 + update \q_int$next $0\q_int$next[0:0]$13259 end - connect \$9 $and$libresoc.v:178408$12847_Y - connect \$11 $or$libresoc.v:178409$12848_Y - connect \$13 $not$libresoc.v:178410$12849_Y - connect \$15 $or$libresoc.v:178411$12850_Y - connect \$1 $not$libresoc.v:178412$12851_Y - connect \$3 $and$libresoc.v:178413$12852_Y - connect \$5 $or$libresoc.v:178414$12853_Y - connect \$7 $not$libresoc.v:178415$12854_Y + connect \$9 $and$libresoc.v:181843$13249_Y + connect \$11 $or$libresoc.v:181844$13250_Y + connect \$13 $not$libresoc.v:181845$13251_Y + connect \$15 $or$libresoc.v:181846$13252_Y + connect \$1 $not$libresoc.v:181847$13253_Y + connect \$3 $and$libresoc.v:181848$13254_Y + connect \$5 $or$libresoc.v:181849$13255_Y + connect \$7 $not$libresoc.v:181850$13256_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:178435.1-181610.10" +attribute \src "libresoc.v:181870.1-183013.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" attribute \generator "nMigen" module \test_issuer - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $0\core_asmcode$next[7:0]$13064 - attribute \src "libresoc.v:180143.3-180144.41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 372 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" + wire width 3 input 374 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" + wire \clksel_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire \clksel_pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire \clksel_pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:103" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 344 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 338 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 347 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 346 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 342 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 340 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 339 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 348 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 341 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 343 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 345 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 333 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 327 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 336 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 335 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 331 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 329 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 328 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 337 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 330 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 332 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 334 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 355 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 349 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 358 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 357 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 353 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 351 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 350 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 359 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 352 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 354 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 356 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 366 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 360 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 369 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 368 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 364 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 362 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 361 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 370 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 363 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 365 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 367 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 371 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 376 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:101" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" + wire output 375 \pll_48_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:78" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:79" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 373 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 274 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 275 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 292 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 293 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 298 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 299 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 304 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 305 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 310 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 311 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 316 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 317 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 322 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 323 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 324 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 280 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 281 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 286 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 287 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:182635.10-182641.4" + cell \clksel \clksel + connect \clk_24_i \clksel_clk_24_i + connect \clk_sel_i \clk_sel_i + connect \pll_48_o \pll_48_o + connect \pllclk_clk \clksel_pllclk_clk + connect \pllclk_rst \clksel_pllclk_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182642.7-182645.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:182646.6-183007.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + end + connect \clksel_pllclk_rst \rst + connect \pll_clk_24_i \clksel_clk_24_i + connect \clksel_clk_24_i \clk + connect \clksel_pllclk_clk \pll_clk_pll_o + connect \ti_coresync_clk \clk +end +attribute \src "libresoc.v:183017.1-186895.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti" +attribute \generator "nMigen" +module \ti + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $0\core_asmcode$next[7:0]$13512 + attribute \src "libresoc.v:185176.3-185177.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:181227.3-181263.6" - wire $0\core_bigendian_i$3$next[0:0]$13303 - attribute \src "libresoc.v:180139.3-180140.55" - wire $0\core_bigendian_i$3[0:0]$12926 - attribute \src "libresoc.v:178576.7-178576.34" - wire $0\core_bigendian_i$3[0:0]$13366 - attribute \src "libresoc.v:180951.3-180963.6" + attribute \src "libresoc.v:186638.3-186674.6" + wire $0\core_bigendian_i$10$next[0:0]$13794 + attribute \src "libresoc.v:185172.3-185173.57" + wire $0\core_bigendian_i$10[0:0]$13333 + attribute \src "libresoc.v:183160.7-183160.35" + wire $0\core_bigendian_i$10[0:0]$13825 + attribute \src "libresoc.v:186336.3-186348.6" wire width 4 $0\core_cia__ren[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13065 - attribute \src "libresoc.v:180219.3-180220.53" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13513 + attribute \src "libresoc.v:185244.3-185245.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13066 - attribute \src "libresoc.v:180245.3-180246.57" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13514 + attribute \src "libresoc.v:185288.3-185289.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13067 - attribute \src "libresoc.v:180247.3-180248.63" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13515 + attribute \src "libresoc.v:185290.3-185291.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13068 - attribute \src "libresoc.v:180249.3-180250.57" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13516 + attribute \src "libresoc.v:185292.3-185293.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 12 $0\core_core_core_fn_unit$next[11:0]$13069 - attribute \src "libresoc.v:180225.3-180226.61" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13517 + attribute \src "libresoc.v:185270.3-185271.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13386 + attribute \src "libresoc.v:183186.7-183186.44" + wire $0\core_core_core_exc_$signal$3[0:0]$13833 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13518 + attribute \src "libresoc.v:185272.3-185273.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13388 + attribute \src "libresoc.v:183190.7-183190.44" + wire $0\core_core_core_exc_$signal$4[0:0]$13835 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13519 + attribute \src "libresoc.v:185276.3-185277.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13392 + attribute \src "libresoc.v:183194.7-183194.44" + wire $0\core_core_core_exc_$signal$5[0:0]$13837 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13520 + attribute \src "libresoc.v:185278.3-185279.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13394 + attribute \src "libresoc.v:183198.7-183198.44" + wire $0\core_core_core_exc_$signal$6[0:0]$13839 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13521 + attribute \src "libresoc.v:185280.3-185281.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13396 + attribute \src "libresoc.v:183202.7-183202.44" + wire $0\core_core_core_exc_$signal$7[0:0]$13841 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13522 + attribute \src "libresoc.v:185282.3-185283.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13398 + attribute \src "libresoc.v:183206.7-183206.44" + wire $0\core_core_core_exc_$signal$8[0:0]$13843 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13523 + attribute \src "libresoc.v:185284.3-185285.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13400 + attribute \src "libresoc.v:183210.7-183210.44" + wire $0\core_core_core_exc_$signal$9[0:0]$13845 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13524 + attribute \src "libresoc.v:185268.3-185269.71" + wire $0\core_core_core_exc_$signal[0:0]$13384 + attribute \src "libresoc.v:183184.7-183184.42" + wire $0\core_core_core_exc_$signal[0:0]$13831 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 12 $0\core_core_core_fn_unit$next[11:0]$13525 + attribute \src "libresoc.v:185250.3-185251.61" wire width 12 $0\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13070 - attribute \src "libresoc.v:180239.3-180240.69" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13526 + attribute \src "libresoc.v:185264.3-185265.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13071 - attribute \src "libresoc.v:180221.3-180222.55" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13527 + attribute \src "libresoc.v:185246.3-185247.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13072 - attribute \src "libresoc.v:180223.3-180224.65" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13528 + attribute \src "libresoc.v:185248.3-185249.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_is_32bit$next[0:0]$13073 - attribute \src "libresoc.v:180253.3-180254.63" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_is_32bit$next[0:0]$13529 + attribute \src "libresoc.v:185298.3-185299.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13074 - attribute \src "libresoc.v:180217.3-180218.53" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13530 + attribute \src "libresoc.v:185242.3-185243.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_oe$next[0:0]$13075 - attribute \src "libresoc.v:180233.3-180234.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_oe$next[0:0]$13531 + attribute \src "libresoc.v:185260.3-185261.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_oe_ok$next[0:0]$13076 - attribute \src "libresoc.v:180235.3-180236.57" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_oe_ok$next[0:0]$13532 + attribute \src "libresoc.v:185262.3-185263.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_rc$next[0:0]$13077 - attribute \src "libresoc.v:180229.3-180230.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_rc$next[0:0]$13533 + attribute \src "libresoc.v:185256.3-185257.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_core_rc_ok$next[0:0]$13078 - attribute \src "libresoc.v:180231.3-180232.57" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_core_rc_ok$next[0:0]$13534 + attribute \src "libresoc.v:185258.3-185259.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13079 - attribute \src "libresoc.v:180243.3-180244.63" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13535 + attribute \src "libresoc.v:185286.3-185287.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $0\core_core_core_traptype$next[6:0]$13080 - attribute \src "libresoc.v:180241.3-180242.63" - wire width 7 $0\core_core_core_traptype[6:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_cr_in1$next[2:0]$13081 - attribute \src "libresoc.v:180199.3-180200.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13536 + attribute \src "libresoc.v:185266.3-185267.63" + wire width 8 $0\core_core_core_traptype[7:0] + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_cr_in1$next[2:0]$13537 + attribute \src "libresoc.v:185226.3-185227.49" wire width 3 $0\core_core_cr_in1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13082 - attribute \src "libresoc.v:180201.3-180202.55" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13538 + attribute \src "libresoc.v:185228.3-185229.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_cr_in2$1$next[2:0]$13083 - attribute \src "libresoc.v:180207.3-180208.55" - wire width 3 $0\core_core_cr_in2$1[2:0]$12962 - attribute \src "libresoc.v:178749.13-178749.40" - wire width 3 $0\core_core_cr_in2$1[2:0]$13387 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_cr_in2$next[2:0]$13084 - attribute \src "libresoc.v:180203.3-180204.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_cr_in2$1$next[2:0]$13539 + attribute \src "libresoc.v:185234.3-185235.55" + wire width 3 $0\core_core_cr_in2$1[2:0]$13365 + attribute \src "libresoc.v:183365.13-183365.40" + wire width 3 $0\core_core_cr_in2$1[2:0]$13862 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_cr_in2$next[2:0]$13540 + attribute \src "libresoc.v:185230.3-185231.49" wire width 3 $0\core_core_cr_in2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13085 - attribute \src "libresoc.v:180209.3-180210.61" - wire $0\core_core_cr_in2_ok$2[0:0]$12964 - attribute \src "libresoc.v:178757.7-178757.37" - wire $0\core_core_cr_in2_ok$2[0:0]$13390 - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13086 - attribute \src "libresoc.v:180205.3-180206.55" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13541 + attribute \src "libresoc.v:185236.3-185237.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13367 + attribute \src "libresoc.v:183373.7-183373.37" + wire $0\core_core_cr_in2_ok$2[0:0]$13865 + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13542 + attribute \src "libresoc.v:185232.3-185233.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_cr_out$next[2:0]$13087 - attribute \src "libresoc.v:180211.3-180212.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_cr_out$next[2:0]$13543 + attribute \src "libresoc.v:185238.3-185239.49" wire width 3 $0\core_core_cr_out[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13088 - attribute \src "libresoc.v:180251.3-180252.53" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13544 + attribute \src "libresoc.v:185294.3-185295.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $0\core_core_ea$next[4:0]$13089 - attribute \src "libresoc.v:180151.3-180152.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $0\core_core_ea$next[4:0]$13545 + attribute \src "libresoc.v:185182.3-185183.41" wire width 5 $0\core_core_ea[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_fast1$next[2:0]$13090 - attribute \src "libresoc.v:180181.3-180182.47" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_fast1$next[2:0]$13546 + attribute \src "libresoc.v:185210.3-185211.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_fast1_ok$next[0:0]$13091 - attribute \src "libresoc.v:180183.3-180184.53" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_fast1_ok$next[0:0]$13547 + attribute \src "libresoc.v:185212.3-185213.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_fast2$next[2:0]$13092 - attribute \src "libresoc.v:180185.3-180186.47" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_fast2$next[2:0]$13548 + attribute \src "libresoc.v:185214.3-185215.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_fast2_ok$next[0:0]$13093 - attribute \src "libresoc.v:180187.3-180188.53" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_fast2_ok$next[0:0]$13549 + attribute \src "libresoc.v:185216.3-185217.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13094 - attribute \src "libresoc.v:180189.3-180190.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13550 + attribute \src "libresoc.v:185218.3-185219.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13095 - attribute \src "libresoc.v:180195.3-180196.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13551 + attribute \src "libresoc.v:185222.3-185223.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_lk$next[0:0]$13096 - attribute \src "libresoc.v:180227.3-180228.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_lk$next[0:0]$13552 + attribute \src "libresoc.v:185254.3-185255.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $0\core_core_pc$next[63:0]$13341 - attribute \src "libresoc.v:180259.3-180260.41" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $0\core_core_pc$next[63:0]$13433 + attribute \src "libresoc.v:185156.3-185157.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $0\core_core_reg1$next[4:0]$13097 - attribute \src "libresoc.v:180155.3-180156.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $0\core_core_reg1$next[4:0]$13553 + attribute \src "libresoc.v:185186.3-185187.45" wire width 5 $0\core_core_reg1[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_reg1_ok$next[0:0]$13098 - attribute \src "libresoc.v:180157.3-180158.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_reg1_ok$next[0:0]$13554 + attribute \src "libresoc.v:185188.3-185189.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $0\core_core_reg2$next[4:0]$13099 - attribute \src "libresoc.v:180159.3-180160.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $0\core_core_reg2$next[4:0]$13555 + attribute \src "libresoc.v:185190.3-185191.45" wire width 5 $0\core_core_reg2[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_reg2_ok$next[0:0]$13100 - attribute \src "libresoc.v:180161.3-180162.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_reg2_ok$next[0:0]$13556 + attribute \src "libresoc.v:185192.3-185193.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $0\core_core_reg3$next[4:0]$13101 - attribute \src "libresoc.v:180163.3-180164.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $0\core_core_reg3$next[4:0]$13557 + attribute \src "libresoc.v:185194.3-185195.45" wire width 5 $0\core_core_reg3[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_reg3_ok$next[0:0]$13102 - attribute \src "libresoc.v:180165.3-180166.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_reg3_ok$next[0:0]$13558 + attribute \src "libresoc.v:185196.3-185197.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $0\core_core_rego$next[4:0]$13103 - attribute \src "libresoc.v:180145.3-180146.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $0\core_core_rego$next[4:0]$13559 + attribute \src "libresoc.v:185178.3-185179.45" wire width 5 $0\core_core_rego[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $0\core_core_spr1$next[9:0]$13104 - attribute \src "libresoc.v:180173.3-180174.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $0\core_core_spr1$next[9:0]$13560 + attribute \src "libresoc.v:185202.3-185203.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_core_spr1_ok$next[0:0]$13105 - attribute \src "libresoc.v:180175.3-180176.51" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_core_spr1_ok$next[0:0]$13561 + attribute \src "libresoc.v:185204.3-185205.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $0\core_core_spro$next[9:0]$13106 - attribute \src "libresoc.v:180167.3-180168.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $0\core_core_spro$next[9:0]$13562 + attribute \src "libresoc.v:185198.3-185199.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13107 - attribute \src "libresoc.v:180177.3-180178.49" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13563 + attribute \src "libresoc.v:185206.3-185207.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_cr_out_ok$next[0:0]$13108 - attribute \src "libresoc.v:180213.3-180214.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_cr_out_ok$next[0:0]$13564 + attribute \src "libresoc.v:185240.3-185241.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:180985.3-181005.6" + attribute \src "libresoc.v:186370.3-186390.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $0\core_dec$next[63:0]$13342 - attribute \src "libresoc.v:180129.3-180130.33" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $0\core_dec$next[63:0]$13434 + attribute \src "libresoc.v:185162.3-185163.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:180649.3-180658.6" + attribute \src "libresoc.v:186034.3-186043.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:180659.3-180668.6" + attribute \src "libresoc.v:186044.3-186053.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_ea_ok$next[0:0]$13109 - attribute \src "libresoc.v:180153.3-180154.37" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_ea_ok$next[0:0]$13565 + attribute \src "libresoc.v:185184.3-185185.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire $0\core_eint$next[0:0]$13343 - attribute \src "libresoc.v:180281.3-180282.35" + attribute \src "libresoc.v:185947.3-185978.6" + wire $0\core_eint$next[0:0]$13435 + attribute \src "libresoc.v:185160.3-185161.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_fasto1_ok$next[0:0]$13110 - attribute \src "libresoc.v:180191.3-180192.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_fasto1_ok$next[0:0]$13566 + attribute \src "libresoc.v:185220.3-185221.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_fasto2_ok$next[0:0]$13111 - attribute \src "libresoc.v:180197.3-180198.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_fasto2_ok$next[0:0]$13567 + attribute \src "libresoc.v:185224.3-185225.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:180698.3-180707.6" + attribute \src "libresoc.v:186083.3-186092.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:180737.3-180746.6" + attribute \src "libresoc.v:186122.3-186131.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:180845.3-180859.6" - wire width 3 $0\core_issue__addr$4[2:0]$13035 - attribute \src "libresoc.v:180776.3-180790.6" + attribute \src "libresoc.v:186230.3-186244.6" + wire width 3 $0\core_issue__addr$11[2:0]$13483 + attribute \src "libresoc.v:186161.3-186175.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:180875.3-180889.6" + attribute \src "libresoc.v:186260.3-186274.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:180791.3-180805.6" + attribute \src "libresoc.v:186176.3-186190.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:180860.3-180874.6" + attribute \src "libresoc.v:186245.3-186259.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:180638.3-180648.6" + attribute \src "libresoc.v:186023.3-186033.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:181571.3-181590.6" + attribute \src "libresoc.v:186003.3-186022.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $0\core_msr$next[63:0]$13344 - attribute \src "libresoc.v:180279.3-180280.33" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $0\core_msr$next[63:0]$13436 + attribute \src "libresoc.v:185158.3-185159.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:181006.3-181021.6" + attribute \src "libresoc.v:186391.3-186406.6" wire width 4 $0\core_msr__ren[3:0] - attribute \src "libresoc.v:181190.3-181226.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13297 - attribute \src "libresoc.v:180141.3-180142.47" + attribute \src "libresoc.v:186601.3-186637.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13788 + attribute \src "libresoc.v:185174.3-185175.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_rego_ok$next[0:0]$13112 - attribute \src "libresoc.v:180147.3-180148.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_rego_ok$next[0:0]$13568 + attribute \src "libresoc.v:185180.3-185181.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_spro_ok$next[0:0]$13113 - attribute \src "libresoc.v:180169.3-180170.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_spro_ok$next[0:0]$13569 + attribute \src "libresoc.v:185200.3-185201.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:181437.3-181455.6" + attribute \src "libresoc.v:186838.3-186856.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:180964.3-180984.6" + attribute \src "libresoc.v:186349.3-186369.6" wire width 4 $0\core_wen[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $0\core_xer_out$next[0:0]$13114 - attribute \src "libresoc.v:180179.3-180180.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire $0\core_xer_out$next[0:0]$13570 + attribute \src "libresoc.v:185208.3-185209.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:180261.3-180262.43" + attribute \src "libresoc.v:185304.3-185305.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:180708.3-180716.6" - wire $0\d_cr_delay$next[0:0]$13017 - attribute \src "libresoc.v:180193.3-180194.37" + attribute \src "libresoc.v:186093.3-186101.6" + wire $0\d_cr_delay$next[0:0]$13465 + attribute \src "libresoc.v:185318.3-185319.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:180669.3-180677.6" - wire $0\d_reg_delay$next[0:0]$13011 - attribute \src "libresoc.v:180215.3-180216.39" + attribute \src "libresoc.v:186054.3-186062.6" + wire $0\d_reg_delay$next[0:0]$13459 + attribute \src "libresoc.v:185152.3-185153.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:180747.3-180755.6" - wire $0\d_xer_delay$next[0:0]$13023 - attribute \src "libresoc.v:180171.3-180172.39" + attribute \src "libresoc.v:186132.3-186140.6" + wire $0\d_xer_delay$next[0:0]$13471 + attribute \src "libresoc.v:185296.3-185297.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:181456.3-181474.6" + attribute \src "libresoc.v:186857.3-186875.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:180727.3-180736.6" + attribute \src "libresoc.v:186112.3-186121.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:180717.3-180726.6" + attribute \src "libresoc.v:186102.3-186111.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:180688.3-180697.6" + attribute \src "libresoc.v:186073.3-186082.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:180678.3-180687.6" + attribute \src "libresoc.v:186063.3-186072.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:180766.3-180775.6" + attribute \src "libresoc.v:186151.3-186160.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:180756.3-180765.6" + attribute \src "libresoc.v:186141.3-186150.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:180620.3-180628.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13002 - attribute \src "libresoc.v:180277.3-180278.45" + attribute \src "libresoc.v:185889.3-185897.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13421 + attribute \src "libresoc.v:185322.3-185323.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:181022.3-181030.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13056 - attribute \src "libresoc.v:180271.3-180272.39" + attribute \src "libresoc.v:186407.3-186415.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13504 + attribute \src "libresoc.v:185314.3-185315.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:180629.3-180637.6" - wire $0\dbg_dmi_req_i$next[0:0]$13005 - attribute \src "libresoc.v:180275.3-180276.43" + attribute \src "libresoc.v:185898.3-185906.6" + wire $0\dbg_dmi_req_i$next[0:0]$13424 + attribute \src "libresoc.v:185320.3-185321.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:180917.3-180925.6" - wire $0\dbg_dmi_we_i$next[0:0]$13045 - attribute \src "libresoc.v:180273.3-180274.41" + attribute \src "libresoc.v:186302.3-186310.6" + wire $0\dbg_dmi_we_i$next[0:0]$13493 + attribute \src "libresoc.v:185316.3-185317.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:180890.3-180905.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13040 - attribute \src "libresoc.v:180127.3-180128.41" + attribute \src "libresoc.v:186275.3-186290.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13488 + attribute \src "libresoc.v:185252.3-185253.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:181181.3-181189.6" - wire $0\dec2_cur_eint$next[0:0]$13294 - attribute \src "libresoc.v:180265.3-180266.43" + attribute \src "libresoc.v:186582.3-186590.6" + wire $0\dec2_cur_eint$next[0:0]$13782 + attribute \src "libresoc.v:185308.3-185309.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:181475.3-181495.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13335 - attribute \src "libresoc.v:180131.3-180132.41" + attribute \src "libresoc.v:185907.3-185927.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13427 + attribute \src "libresoc.v:185164.3-185165.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:181330.3-181350.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13312 - attribute \src "libresoc.v:180137.3-180138.39" + attribute \src "libresoc.v:186741.3-186761.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13803 + attribute \src "libresoc.v:185170.3-185171.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:181496.3-181514.6" + attribute \src "libresoc.v:185928.3-185946.6" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:181427.3-181436.6" - wire width 2 $0\delay$next[1:0]$13330 - attribute \src "libresoc.v:180263.3-180264.27" + attribute \src "libresoc.v:186591.3-186600.6" + wire width 2 $0\delay$next[1:0]$13785 + attribute \src "libresoc.v:185306.3-185307.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:180806.3-180833.6" - wire width 2 $0\fsm_state$117$next[1:0]$13030 - attribute \src "libresoc.v:180149.3-180150.45" - wire width 2 $0\fsm_state$117[1:0]$12932 - attribute \src "libresoc.v:179708.13-179708.35" - wire width 2 $0\fsm_state$117[1:0]$13439 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $0\fsm_state$next[1:0]$13323 - attribute \src "libresoc.v:180133.3-180134.35" + attribute \src "libresoc.v:186191.3-186218.6" + wire width 2 $0\fsm_state$133$next[1:0]$13478 + attribute \src "libresoc.v:185274.3-185275.45" + wire width 2 $0\fsm_state$133[1:0]$13390 + attribute \src "libresoc.v:184350.13-184350.35" + wire width 2 $0\fsm_state$133[1:0]$13914 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $0\fsm_state$next[1:0]$13814 + attribute \src "libresoc.v:185166.3-185167.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:181547.3-181570.6" - wire width 32 $0\ilatch$next[31:0]$13358 - attribute \src "libresoc.v:180237.3-180238.29" + attribute \src "libresoc.v:185979.3-186002.6" + wire width 32 $0\ilatch$next[31:0]$13450 + attribute \src "libresoc.v:185154.3-185155.29" wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:181264.3-181279.6" + attribute \src "libresoc.v:186675.3-186690.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:181280.3-181304.6" + attribute \src "libresoc.v:186691.3-186715.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:181305.3-181329.6" + attribute \src "libresoc.v:186716.3-186740.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:178436.7-178436.20" + attribute \src "libresoc.v:183018.7-183018.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181163.3-181171.6" - wire $0\jtag_dmi0_ack_o$next[0:0]$13288 - attribute \src "libresoc.v:180269.3-180270.47" - wire $0\jtag_dmi0_ack_o[0:0] - attribute \src "libresoc.v:181172.3-181180.6" - wire width 64 $0\jtag_dmi0_dout$next[63:0]$13291 - attribute \src "libresoc.v:180267.3-180268.45" - wire width 64 $0\jtag_dmi0_dout[63:0] - attribute \src "libresoc.v:181351.3-181380.6" - wire $0\msr_read$next[0:0]$13317 - attribute \src "libresoc.v:180135.3-180136.33" + attribute \src "libresoc.v:186564.3-186572.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13776 + attribute \src "libresoc.v:185312.3-185313.49" + wire $0\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:186573.3-186581.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13779 + attribute \src "libresoc.v:185310.3-185311.47" + wire width 64 $0\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:186762.3-186791.6" + wire $0\msr_read$next[0:0]$13808 + attribute \src "libresoc.v:185168.3-185169.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:180834.3-180844.6" + attribute \src "libresoc.v:186219.3-186229.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:180906.3-180916.6" + attribute \src "libresoc.v:186291.3-186301.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:180935.3-180950.6" + attribute \src "libresoc.v:186320.3-186335.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:181031.3-181055.6" - wire $0\pc_changed$next[0:0]$13059 - attribute \src "libresoc.v:180255.3-180256.37" + attribute \src "libresoc.v:186416.3-186440.6" + wire $0\pc_changed$next[0:0]$13507 + attribute \src "libresoc.v:185300.3-185301.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:180926.3-180934.6" - wire $0\pc_ok_delay$next[0:0]$13048 - attribute \src "libresoc.v:180257.3-180258.39" + attribute \src "libresoc.v:186311.3-186319.6" + wire $0\pc_ok_delay$next[0:0]$13496 + attribute \src "libresoc.v:185302.3-185303.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $1\core_asmcode$next[7:0]$13115 - attribute \src "libresoc.v:178570.13-178570.33" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $1\core_asmcode$next[7:0]$13571 + attribute \src "libresoc.v:183154.13-183154.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:181227.3-181263.6" - wire $1\core_bigendian_i$3$next[0:0]$13304 - attribute \src "libresoc.v:180951.3-180963.6" + attribute \src "libresoc.v:186638.3-186674.6" + wire $1\core_bigendian_i$10$next[0:0]$13795 + attribute \src "libresoc.v:186336.3-186348.6" wire width 4 $1\core_cia__ren[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13116 - attribute \src "libresoc.v:178584.14-178584.55" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13572 + attribute \src "libresoc.v:183168.14-183168.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13117 - attribute \src "libresoc.v:178588.13-178588.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13573 + attribute \src "libresoc.v:183172.13-183172.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13118 - attribute \src "libresoc.v:178592.7-178592.37" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13574 + attribute \src "libresoc.v:183176.7-183176.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13119 - attribute \src "libresoc.v:178596.13-178596.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13575 + attribute \src "libresoc.v:183180.13-183180.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 12 $1\core_core_core_fn_unit$next[11:0]$13120 - attribute \src "libresoc.v:178613.14-178613.46" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13576 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13577 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13578 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13579 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13580 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13581 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13582 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13583 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 12 $1\core_core_core_fn_unit$next[11:0]$13584 + attribute \src "libresoc.v:183229.14-183229.46" wire width 12 $1\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13121 - attribute \src "libresoc.v:178621.13-178621.46" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13585 + attribute \src "libresoc.v:183237.13-183237.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13122 - attribute \src "libresoc.v:178625.14-178625.41" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13586 + attribute \src "libresoc.v:183241.14-183241.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13123 - attribute \src "libresoc.v:178703.13-178703.45" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13587 + attribute \src "libresoc.v:183319.13-183319.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_is_32bit$next[0:0]$13124 - attribute \src "libresoc.v:178707.7-178707.37" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_is_32bit$next[0:0]$13588 + attribute \src "libresoc.v:183323.7-183323.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13125 - attribute \src "libresoc.v:178711.14-178711.55" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13589 + attribute \src "libresoc.v:183327.14-183327.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_oe$next[0:0]$13126 - attribute \src "libresoc.v:178715.7-178715.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_oe$next[0:0]$13590 + attribute \src "libresoc.v:183331.7-183331.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_oe_ok$next[0:0]$13127 - attribute \src "libresoc.v:178719.7-178719.34" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_oe_ok$next[0:0]$13591 + attribute \src "libresoc.v:183335.7-183335.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_rc$next[0:0]$13128 - attribute \src "libresoc.v:178723.7-178723.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_rc$next[0:0]$13592 + attribute \src "libresoc.v:183339.7-183339.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_core_rc_ok$next[0:0]$13129 - attribute \src "libresoc.v:178727.7-178727.34" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_core_rc_ok$next[0:0]$13593 + attribute \src "libresoc.v:183343.7-183343.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13130 - attribute \src "libresoc.v:178731.14-178731.48" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13594 + attribute \src "libresoc.v:183347.14-183347.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $1\core_core_core_traptype$next[6:0]$13131 - attribute \src "libresoc.v:178735.13-178735.44" - wire width 7 $1\core_core_core_traptype[6:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_cr_in1$next[2:0]$13132 - attribute \src "libresoc.v:178739.13-178739.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13595 + attribute \src "libresoc.v:183351.13-183351.44" + wire width 8 $1\core_core_core_traptype[7:0] + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_cr_in1$next[2:0]$13596 + attribute \src "libresoc.v:183355.13-183355.36" wire width 3 $1\core_core_cr_in1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13133 - attribute \src "libresoc.v:178743.7-178743.33" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13597 + attribute \src "libresoc.v:183359.7-183359.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_cr_in2$1$next[2:0]$13134 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_cr_in2$next[2:0]$13135 - attribute \src "libresoc.v:178747.13-178747.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_cr_in2$1$next[2:0]$13598 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_cr_in2$next[2:0]$13599 + attribute \src "libresoc.v:183363.13-183363.36" wire width 3 $1\core_core_cr_in2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13136 - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13137 - attribute \src "libresoc.v:178755.7-178755.33" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13600 + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13601 + attribute \src "libresoc.v:183371.7-183371.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_cr_out$next[2:0]$13138 - attribute \src "libresoc.v:178763.13-178763.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_cr_out$next[2:0]$13602 + attribute \src "libresoc.v:183379.13-183379.36" wire width 3 $1\core_core_cr_out[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13139 - attribute \src "libresoc.v:178767.7-178767.32" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13603 + attribute \src "libresoc.v:183383.7-183383.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $1\core_core_ea$next[4:0]$13140 - attribute \src "libresoc.v:178771.13-178771.33" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $1\core_core_ea$next[4:0]$13604 + attribute \src "libresoc.v:183387.13-183387.33" wire width 5 $1\core_core_ea[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_fast1$next[2:0]$13141 - attribute \src "libresoc.v:178775.13-178775.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_fast1$next[2:0]$13605 + attribute \src "libresoc.v:183391.13-183391.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_fast1_ok$next[0:0]$13142 - attribute \src "libresoc.v:178779.7-178779.32" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_fast1_ok$next[0:0]$13606 + attribute \src "libresoc.v:183395.7-183395.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_fast2$next[2:0]$13143 - attribute \src "libresoc.v:178783.13-178783.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_fast2$next[2:0]$13607 + attribute \src "libresoc.v:183399.13-183399.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_fast2_ok$next[0:0]$13144 - attribute \src "libresoc.v:178787.7-178787.32" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_fast2_ok$next[0:0]$13608 + attribute \src "libresoc.v:183403.7-183403.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13145 - attribute \src "libresoc.v:178791.13-178791.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13609 + attribute \src "libresoc.v:183407.13-183407.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13146 - attribute \src "libresoc.v:178795.13-178795.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13610 + attribute \src "libresoc.v:183411.13-183411.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_lk$next[0:0]$13147 - attribute \src "libresoc.v:178799.7-178799.26" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_lk$next[0:0]$13611 + attribute \src "libresoc.v:183415.7-183415.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $1\core_core_pc$next[63:0]$13345 - attribute \src "libresoc.v:178803.14-178803.49" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $1\core_core_pc$next[63:0]$13437 + attribute \src "libresoc.v:183419.14-183419.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $1\core_core_reg1$next[4:0]$13148 - attribute \src "libresoc.v:178807.13-178807.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $1\core_core_reg1$next[4:0]$13612 + attribute \src "libresoc.v:183423.13-183423.35" wire width 5 $1\core_core_reg1[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_reg1_ok$next[0:0]$13149 - attribute \src "libresoc.v:178811.7-178811.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_reg1_ok$next[0:0]$13613 + attribute \src "libresoc.v:183427.7-183427.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $1\core_core_reg2$next[4:0]$13150 - attribute \src "libresoc.v:178815.13-178815.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $1\core_core_reg2$next[4:0]$13614 + attribute \src "libresoc.v:183431.13-183431.35" wire width 5 $1\core_core_reg2[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_reg2_ok$next[0:0]$13151 - attribute \src "libresoc.v:178819.7-178819.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_reg2_ok$next[0:0]$13615 + attribute \src "libresoc.v:183435.7-183435.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $1\core_core_reg3$next[4:0]$13152 - attribute \src "libresoc.v:178823.13-178823.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $1\core_core_reg3$next[4:0]$13616 + attribute \src "libresoc.v:183439.13-183439.35" wire width 5 $1\core_core_reg3[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_reg3_ok$next[0:0]$13153 - attribute \src "libresoc.v:178827.7-178827.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_reg3_ok$next[0:0]$13617 + attribute \src "libresoc.v:183443.7-183443.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $1\core_core_rego$next[4:0]$13154 - attribute \src "libresoc.v:178831.13-178831.35" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $1\core_core_rego$next[4:0]$13618 + attribute \src "libresoc.v:183447.13-183447.35" wire width 5 $1\core_core_rego[4:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $1\core_core_spr1$next[9:0]$13155 - attribute \src "libresoc.v:178948.13-178948.37" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $1\core_core_spr1$next[9:0]$13619 + attribute \src "libresoc.v:183562.13-183562.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_core_spr1_ok$next[0:0]$13156 - attribute \src "libresoc.v:178952.7-178952.31" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_core_spr1_ok$next[0:0]$13620 + attribute \src "libresoc.v:183566.7-183566.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $1\core_core_spro$next[9:0]$13157 - attribute \src "libresoc.v:179067.13-179067.37" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $1\core_core_spro$next[9:0]$13621 + attribute \src "libresoc.v:183681.13-183681.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13158 - attribute \src "libresoc.v:179073.13-179073.36" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13622 + attribute \src "libresoc.v:183687.13-183687.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_cr_out_ok$next[0:0]$13159 - attribute \src "libresoc.v:179081.7-179081.28" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_cr_out_ok$next[0:0]$13623 + attribute \src "libresoc.v:183695.7-183695.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:180985.3-181005.6" + attribute \src "libresoc.v:186370.3-186390.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $1\core_dec$next[63:0]$13346 - attribute \src "libresoc.v:179095.14-179095.45" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $1\core_dec$next[63:0]$13438 + attribute \src "libresoc.v:183709.14-183709.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:180649.3-180658.6" + attribute \src "libresoc.v:186034.3-186043.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:180659.3-180668.6" + attribute \src "libresoc.v:186044.3-186053.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_ea_ok$next[0:0]$13160 - attribute \src "libresoc.v:179105.7-179105.24" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_ea_ok$next[0:0]$13624 + attribute \src "libresoc.v:183719.7-183719.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire $1\core_eint$next[0:0]$13347 - attribute \src "libresoc.v:179109.7-179109.23" + attribute \src "libresoc.v:185947.3-185978.6" + wire $1\core_eint$next[0:0]$13439 + attribute \src "libresoc.v:183723.7-183723.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_fasto1_ok$next[0:0]$13161 - attribute \src "libresoc.v:179113.7-179113.28" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_fasto1_ok$next[0:0]$13625 + attribute \src "libresoc.v:183727.7-183727.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_fasto2_ok$next[0:0]$13162 - attribute \src "libresoc.v:179117.7-179117.28" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_fasto2_ok$next[0:0]$13626 + attribute \src "libresoc.v:183731.7-183731.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:180698.3-180707.6" + attribute \src "libresoc.v:186083.3-186092.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:180737.3-180746.6" + attribute \src "libresoc.v:186122.3-186131.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:180845.3-180859.6" - wire width 3 $1\core_issue__addr$4[2:0]$13036 - attribute \src "libresoc.v:180776.3-180790.6" + attribute \src "libresoc.v:186230.3-186244.6" + wire width 3 $1\core_issue__addr$11[2:0]$13484 + attribute \src "libresoc.v:186161.3-186175.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:180875.3-180889.6" + attribute \src "libresoc.v:186260.3-186274.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:180791.3-180805.6" + attribute \src "libresoc.v:186176.3-186190.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:180860.3-180874.6" + attribute \src "libresoc.v:186245.3-186259.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:180638.3-180648.6" + attribute \src "libresoc.v:186023.3-186033.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:181571.3-181590.6" + attribute \src "libresoc.v:186003.3-186022.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $1\core_msr$next[63:0]$13348 - attribute \src "libresoc.v:179145.14-179145.45" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $1\core_msr$next[63:0]$13440 + attribute \src "libresoc.v:183759.14-183759.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:181006.3-181021.6" + attribute \src "libresoc.v:186391.3-186406.6" wire width 4 $1\core_msr__ren[3:0] - attribute \src "libresoc.v:181190.3-181226.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13298 - attribute \src "libresoc.v:179153.14-179153.37" + attribute \src "libresoc.v:186601.3-186637.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13789 + attribute \src "libresoc.v:183767.14-183767.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_rego_ok$next[0:0]$13163 - attribute \src "libresoc.v:179157.7-179157.26" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_rego_ok$next[0:0]$13627 + attribute \src "libresoc.v:183771.7-183771.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_spro_ok$next[0:0]$13164 - attribute \src "libresoc.v:179161.7-179161.26" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_spro_ok$next[0:0]$13628 + attribute \src "libresoc.v:183775.7-183775.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:181437.3-181455.6" + attribute \src "libresoc.v:186838.3-186856.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:180964.3-180984.6" + attribute \src "libresoc.v:186349.3-186369.6" wire width 4 $1\core_wen[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $1\core_xer_out$next[0:0]$13165 - attribute \src "libresoc.v:179171.7-179171.26" + attribute \src "libresoc.v:186441.3-186563.6" + wire $1\core_xer_out$next[0:0]$13629 + attribute \src "libresoc.v:183787.7-183787.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:179175.7-179175.30" + attribute \src "libresoc.v:183793.7-183793.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:180708.3-180716.6" - wire $1\d_cr_delay$next[0:0]$13018 - attribute \src "libresoc.v:179181.7-179181.24" + attribute \src "libresoc.v:186093.3-186101.6" + wire $1\d_cr_delay$next[0:0]$13466 + attribute \src "libresoc.v:183799.7-183799.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:180669.3-180677.6" - wire $1\d_reg_delay$next[0:0]$13012 - attribute \src "libresoc.v:179185.7-179185.25" + attribute \src "libresoc.v:186054.3-186062.6" + wire $1\d_reg_delay$next[0:0]$13460 + attribute \src "libresoc.v:183803.7-183803.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:180747.3-180755.6" - wire $1\d_xer_delay$next[0:0]$13024 - attribute \src "libresoc.v:179189.7-179189.25" + attribute \src "libresoc.v:186132.3-186140.6" + wire $1\d_xer_delay$next[0:0]$13472 + attribute \src "libresoc.v:183807.7-183807.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:181456.3-181474.6" + attribute \src "libresoc.v:186857.3-186875.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:180727.3-180736.6" + attribute \src "libresoc.v:186112.3-186121.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:180717.3-180726.6" + attribute \src "libresoc.v:186102.3-186111.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:180688.3-180697.6" + attribute \src "libresoc.v:186073.3-186082.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:180678.3-180687.6" + attribute \src "libresoc.v:186063.3-186072.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:180766.3-180775.6" + attribute \src "libresoc.v:186151.3-186160.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:180756.3-180765.6" + attribute \src "libresoc.v:186141.3-186150.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:180620.3-180628.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13003 - attribute \src "libresoc.v:179225.13-179225.34" + attribute \src "libresoc.v:185889.3-185897.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13422 + attribute \src "libresoc.v:183843.13-183843.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:181022.3-181030.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13057 - attribute \src "libresoc.v:179229.14-179229.48" + attribute \src "libresoc.v:186407.3-186415.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13505 + attribute \src "libresoc.v:183847.14-183847.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:180629.3-180637.6" - wire $1\dbg_dmi_req_i$next[0:0]$13006 - attribute \src "libresoc.v:179235.7-179235.27" + attribute \src "libresoc.v:185898.3-185906.6" + wire $1\dbg_dmi_req_i$next[0:0]$13425 + attribute \src "libresoc.v:183853.7-183853.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:180917.3-180925.6" - wire $1\dbg_dmi_we_i$next[0:0]$13046 - attribute \src "libresoc.v:179239.7-179239.26" + attribute \src "libresoc.v:186302.3-186310.6" + wire $1\dbg_dmi_we_i$next[0:0]$13494 + attribute \src "libresoc.v:183857.7-183857.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:180890.3-180905.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13041 - attribute \src "libresoc.v:179297.14-179297.49" + attribute \src "libresoc.v:186275.3-186290.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13489 + attribute \src "libresoc.v:183911.14-183911.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:181181.3-181189.6" - wire $1\dec2_cur_eint$next[0:0]$13295 - attribute \src "libresoc.v:179301.7-179301.27" + attribute \src "libresoc.v:186582.3-186590.6" + wire $1\dec2_cur_eint$next[0:0]$13783 + attribute \src "libresoc.v:183915.7-183915.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:181475.3-181495.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13336 - attribute \src "libresoc.v:179305.14-179305.49" + attribute \src "libresoc.v:185907.3-185927.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13428 + attribute \src "libresoc.v:183919.14-183919.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:181330.3-181350.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13313 - attribute \src "libresoc.v:179309.14-179309.48" + attribute \src "libresoc.v:186741.3-186761.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13804 + attribute \src "libresoc.v:183923.14-183923.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:181496.3-181514.6" + attribute \src "libresoc.v:185928.3-185946.6" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:181427.3-181436.6" - wire width 2 $1\delay$next[1:0]$13331 - attribute \src "libresoc.v:179702.13-179702.25" + attribute \src "libresoc.v:186591.3-186600.6" + wire width 2 $1\delay$next[1:0]$13786 + attribute \src "libresoc.v:184332.13-184332.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:180806.3-180833.6" - wire width 2 $1\fsm_state$117$next[1:0]$13031 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $1\fsm_state$next[1:0]$13324 - attribute \src "libresoc.v:179706.13-179706.29" + attribute \src "libresoc.v:186191.3-186218.6" + wire width 2 $1\fsm_state$133$next[1:0]$13479 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $1\fsm_state$next[1:0]$13815 + attribute \src "libresoc.v:184348.13-184348.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:181547.3-181570.6" - wire width 32 $1\ilatch$next[31:0]$13359 - attribute \src "libresoc.v:179972.14-179972.28" + attribute \src "libresoc.v:185979.3-186002.6" + wire width 32 $1\ilatch$next[31:0]$13451 + attribute \src "libresoc.v:184592.14-184592.28" wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:181264.3-181279.6" + attribute \src "libresoc.v:186675.3-186690.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:181280.3-181304.6" + attribute \src "libresoc.v:186691.3-186715.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:181305.3-181329.6" + attribute \src "libresoc.v:186716.3-186740.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:181163.3-181171.6" - wire $1\jtag_dmi0_ack_o$next[0:0]$13289 - attribute \src "libresoc.v:179988.7-179988.29" - wire $1\jtag_dmi0_ack_o[0:0] - attribute \src "libresoc.v:181172.3-181180.6" - wire width 64 $1\jtag_dmi0_dout$next[63:0]$13292 - attribute \src "libresoc.v:179996.14-179996.51" - wire width 64 $1\jtag_dmi0_dout[63:0] - attribute \src "libresoc.v:181351.3-181380.6" - wire $1\msr_read$next[0:0]$13318 - attribute \src "libresoc.v:180024.7-180024.22" + attribute \src "libresoc.v:186564.3-186572.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13777 + attribute \src "libresoc.v:184610.7-184610.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:186573.3-186581.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13780 + attribute \src "libresoc.v:184618.14-184618.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:186762.3-186791.6" + wire $1\msr_read$next[0:0]$13809 + attribute \src "libresoc.v:184674.7-184674.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:180834.3-180844.6" + attribute \src "libresoc.v:186219.3-186229.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:180906.3-180916.6" + attribute \src "libresoc.v:186291.3-186301.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:180935.3-180950.6" + attribute \src "libresoc.v:186320.3-186335.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:181031.3-181055.6" - wire $1\pc_changed$next[0:0]$13060 - attribute \src "libresoc.v:180036.7-180036.24" + attribute \src "libresoc.v:186416.3-186440.6" + wire $1\pc_changed$next[0:0]$13508 + attribute \src "libresoc.v:184702.7-184702.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:180926.3-180934.6" - wire $1\pc_ok_delay$next[0:0]$13049 - attribute \src "libresoc.v:180046.7-180046.25" + attribute \src "libresoc.v:186311.3-186319.6" + wire $1\pc_ok_delay$next[0:0]$13497 + attribute \src "libresoc.v:184712.7-184712.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $2\core_asmcode$next[7:0]$13166 - attribute \src "libresoc.v:181227.3-181263.6" - wire $2\core_bigendian_i$3$next[0:0]$13305 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13167 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13168 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13169 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13170 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 12 $2\core_core_core_fn_unit$next[11:0]$13171 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13172 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13173 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13174 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_is_32bit$next[0:0]$13175 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13176 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_oe$next[0:0]$13177 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_oe_ok$next[0:0]$13178 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_rc$next[0:0]$13179 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_core_rc_ok$next[0:0]$13180 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13181 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $2\core_core_core_traptype$next[6:0]$13182 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_cr_in1$next[2:0]$13183 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_cr_in1_ok$next[0:0]$13184 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_cr_in2$1$next[2:0]$13185 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_cr_in2$next[2:0]$13186 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$13187 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_cr_in2_ok$next[0:0]$13188 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_cr_out$next[2:0]$13189 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_cr_wr_ok$next[0:0]$13190 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $2\core_core_ea$next[4:0]$13191 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_fast1$next[2:0]$13192 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_fast1_ok$next[0:0]$13193 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_fast2$next[2:0]$13194 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_fast2_ok$next[0:0]$13195 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_fasto1$next[2:0]$13196 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_fasto2$next[2:0]$13197 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_lk$next[0:0]$13198 - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $2\core_core_pc$next[63:0]$13349 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $2\core_core_reg1$next[4:0]$13199 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_reg1_ok$next[0:0]$13200 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $2\core_core_reg2$next[4:0]$13201 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_reg2_ok$next[0:0]$13202 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $2\core_core_reg3$next[4:0]$13203 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_reg3_ok$next[0:0]$13204 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $2\core_core_rego$next[4:0]$13205 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $2\core_core_spr1$next[9:0]$13206 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_core_spr1_ok$next[0:0]$13207 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $2\core_core_spro$next[9:0]$13208 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $2\core_core_xer_in$next[2:0]$13209 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_cr_out_ok$next[0:0]$13210 - attribute \src "libresoc.v:180985.3-181005.6" + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $2\core_asmcode$next[7:0]$13630 + attribute \src "libresoc.v:186638.3-186674.6" + wire $2\core_bigendian_i$10$next[0:0]$13796 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13631 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13632 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$13633 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$13634 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$13635 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$13636 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$13637 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$13638 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$13639 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$13640 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$13641 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_exc_$signal$next[0:0]$13642 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 12 $2\core_core_core_fn_unit$next[11:0]$13643 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$13644 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 32 $2\core_core_core_insn$next[31:0]$13645 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$13646 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_is_32bit$next[0:0]$13647 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $2\core_core_core_msr$next[63:0]$13648 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_oe$next[0:0]$13649 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_oe_ok$next[0:0]$13650 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_rc$next[0:0]$13651 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_core_rc_ok$next[0:0]$13652 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$13653 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$13654 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_cr_in1$next[2:0]$13655 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_cr_in1_ok$next[0:0]$13656 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_cr_in2$1$next[2:0]$13657 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_cr_in2$next[2:0]$13658 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$13659 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_cr_in2_ok$next[0:0]$13660 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_cr_out$next[2:0]$13661 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_cr_wr_ok$next[0:0]$13662 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $2\core_core_ea$next[4:0]$13663 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_fast1$next[2:0]$13664 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_fast1_ok$next[0:0]$13665 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_fast2$next[2:0]$13666 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_fast2_ok$next[0:0]$13667 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_fasto1$next[2:0]$13668 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_fasto2$next[2:0]$13669 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_lk$next[0:0]$13670 + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $2\core_core_pc$next[63:0]$13441 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $2\core_core_reg1$next[4:0]$13671 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_reg1_ok$next[0:0]$13672 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $2\core_core_reg2$next[4:0]$13673 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_reg2_ok$next[0:0]$13674 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $2\core_core_reg3$next[4:0]$13675 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_reg3_ok$next[0:0]$13676 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $2\core_core_rego$next[4:0]$13677 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $2\core_core_spr1$next[9:0]$13678 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_core_spr1_ok$next[0:0]$13679 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $2\core_core_spro$next[9:0]$13680 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $2\core_core_xer_in$next[2:0]$13681 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_cr_out_ok$next[0:0]$13682 + attribute \src "libresoc.v:186370.3-186390.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $2\core_dec$next[63:0]$13350 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_ea_ok$next[0:0]$13211 - attribute \src "libresoc.v:181515.3-181546.6" - wire $2\core_eint$next[0:0]$13351 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_fasto1_ok$next[0:0]$13212 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_fasto2_ok$next[0:0]$13213 - attribute \src "libresoc.v:181571.3-181590.6" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $2\core_dec$next[63:0]$13442 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_ea_ok$next[0:0]$13683 + attribute \src "libresoc.v:185947.3-185978.6" + wire $2\core_eint$next[0:0]$13443 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_fasto1_ok$next[0:0]$13684 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_fasto2_ok$next[0:0]$13685 + attribute \src "libresoc.v:186003.3-186022.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $2\core_msr$next[63:0]$13352 - attribute \src "libresoc.v:181006.3-181021.6" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $2\core_msr$next[63:0]$13444 + attribute \src "libresoc.v:186391.3-186406.6" wire width 4 $2\core_msr__ren[3:0] - attribute \src "libresoc.v:181190.3-181226.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13299 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_rego_ok$next[0:0]$13214 - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_spro_ok$next[0:0]$13215 - attribute \src "libresoc.v:181437.3-181455.6" + attribute \src "libresoc.v:186601.3-186637.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13790 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_rego_ok$next[0:0]$13686 + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_spro_ok$next[0:0]$13687 + attribute \src "libresoc.v:186838.3-186856.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:180964.3-180984.6" + attribute \src "libresoc.v:186349.3-186369.6" wire width 4 $2\core_wen[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $2\core_xer_out$next[0:0]$13216 - attribute \src "libresoc.v:181456.3-181474.6" + attribute \src "libresoc.v:186441.3-186563.6" + wire $2\core_xer_out$next[0:0]$13688 + attribute \src "libresoc.v:186857.3-186875.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:180890.3-180905.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13042 - attribute \src "libresoc.v:181475.3-181495.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13337 - attribute \src "libresoc.v:181330.3-181350.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13314 - attribute \src "libresoc.v:181496.3-181514.6" + attribute \src "libresoc.v:186275.3-186290.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13490 + attribute \src "libresoc.v:185907.3-185927.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13429 + attribute \src "libresoc.v:186741.3-186761.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13805 + attribute \src "libresoc.v:185928.3-185946.6" wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:180806.3-180833.6" - wire width 2 $2\fsm_state$117$next[1:0]$13032 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $2\fsm_state$next[1:0]$13325 - attribute \src "libresoc.v:181547.3-181570.6" - wire width 32 $2\ilatch$next[31:0]$13360 - attribute \src "libresoc.v:181264.3-181279.6" + attribute \src "libresoc.v:186191.3-186218.6" + wire width 2 $2\fsm_state$133$next[1:0]$13480 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $2\fsm_state$next[1:0]$13816 + attribute \src "libresoc.v:185979.3-186002.6" + wire width 32 $2\ilatch$next[31:0]$13452 + attribute \src "libresoc.v:186675.3-186690.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:181280.3-181304.6" + attribute \src "libresoc.v:186691.3-186715.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:181305.3-181329.6" + attribute \src "libresoc.v:186716.3-186740.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:181351.3-181380.6" - wire $2\msr_read$next[0:0]$13319 - attribute \src "libresoc.v:180935.3-180950.6" + attribute \src "libresoc.v:186762.3-186791.6" + wire $2\msr_read$next[0:0]$13810 + attribute \src "libresoc.v:186320.3-186335.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:181031.3-181055.6" - wire $2\pc_changed$next[0:0]$13061 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $3\core_asmcode$next[7:0]$13217 - attribute \src "libresoc.v:181227.3-181263.6" - wire $3\core_bigendian_i$3$next[0:0]$13306 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $3\core_core_core_cia$next[63:0]$13218 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $3\core_core_core_cr_rd$next[7:0]$13219 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$13220 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 8 $3\core_core_core_cr_wr$next[7:0]$13221 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 12 $3\core_core_core_fn_unit$next[11:0]$13222 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 2 $3\core_core_core_input_carry$next[1:0]$13223 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 32 $3\core_core_core_insn$next[31:0]$13224 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $3\core_core_core_insn_type$next[6:0]$13225 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_is_32bit$next[0:0]$13226 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 64 $3\core_core_core_msr$next[63:0]$13227 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_oe$next[0:0]$13228 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_oe_ok$next[0:0]$13229 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_rc$next[0:0]$13230 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_core_rc_ok$next[0:0]$13231 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 13 $3\core_core_core_trapaddr$next[12:0]$13232 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 7 $3\core_core_core_traptype$next[6:0]$13233 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_cr_in1$next[2:0]$13234 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_cr_in1_ok$next[0:0]$13235 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_cr_in2$1$next[2:0]$13236 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_cr_in2$next[2:0]$13237 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$13238 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_cr_in2_ok$next[0:0]$13239 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_cr_out$next[2:0]$13240 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_cr_wr_ok$next[0:0]$13241 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $3\core_core_ea$next[4:0]$13242 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_fast1$next[2:0]$13243 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_fast1_ok$next[0:0]$13244 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_fast2$next[2:0]$13245 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_fast2_ok$next[0:0]$13246 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_fasto1$next[2:0]$13247 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_fasto2$next[2:0]$13248 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_lk$next[0:0]$13249 - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $3\core_core_pc$next[63:0]$13353 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $3\core_core_reg1$next[4:0]$13250 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_reg1_ok$next[0:0]$13251 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $3\core_core_reg2$next[4:0]$13252 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_reg2_ok$next[0:0]$13253 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $3\core_core_reg3$next[4:0]$13254 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_reg3_ok$next[0:0]$13255 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 5 $3\core_core_rego$next[4:0]$13256 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $3\core_core_spr1$next[9:0]$13257 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_core_spr1_ok$next[0:0]$13258 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 10 $3\core_core_spro$next[9:0]$13259 - attribute \src "libresoc.v:181056.3-181162.6" - wire width 3 $3\core_core_xer_in$next[2:0]$13260 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_cr_out_ok$next[0:0]$13261 - attribute \src "libresoc.v:180985.3-181005.6" + attribute \src "libresoc.v:186416.3-186440.6" + wire $2\pc_changed$next[0:0]$13509 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $3\core_asmcode$next[7:0]$13689 + attribute \src "libresoc.v:186638.3-186674.6" + wire $3\core_bigendian_i$10$next[0:0]$13797 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $3\core_core_core_cia$next[63:0]$13690 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$13691 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$13692 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$13693 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$13694 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$13695 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$13696 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$13697 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$13698 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$13699 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$13700 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_exc_$signal$next[0:0]$13701 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 12 $3\core_core_core_fn_unit$next[11:0]$13702 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$13703 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 32 $3\core_core_core_insn$next[31:0]$13704 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$13705 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_is_32bit$next[0:0]$13706 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 64 $3\core_core_core_msr$next[63:0]$13707 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_oe$next[0:0]$13708 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_oe_ok$next[0:0]$13709 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_rc$next[0:0]$13710 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_core_rc_ok$next[0:0]$13711 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$13712 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 8 $3\core_core_core_traptype$next[7:0]$13713 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_cr_in1$next[2:0]$13714 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_cr_in1_ok$next[0:0]$13715 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_cr_in2$1$next[2:0]$13716 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_cr_in2$next[2:0]$13717 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$13718 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_cr_in2_ok$next[0:0]$13719 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_cr_out$next[2:0]$13720 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_cr_wr_ok$next[0:0]$13721 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $3\core_core_ea$next[4:0]$13722 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_fast1$next[2:0]$13723 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_fast1_ok$next[0:0]$13724 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_fast2$next[2:0]$13725 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_fast2_ok$next[0:0]$13726 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_fasto1$next[2:0]$13727 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_fasto2$next[2:0]$13728 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_lk$next[0:0]$13729 + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $3\core_core_pc$next[63:0]$13445 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $3\core_core_reg1$next[4:0]$13730 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_reg1_ok$next[0:0]$13731 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $3\core_core_reg2$next[4:0]$13732 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_reg2_ok$next[0:0]$13733 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $3\core_core_reg3$next[4:0]$13734 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_reg3_ok$next[0:0]$13735 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 5 $3\core_core_rego$next[4:0]$13736 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $3\core_core_spr1$next[9:0]$13737 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_core_spr1_ok$next[0:0]$13738 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 10 $3\core_core_spro$next[9:0]$13739 + attribute \src "libresoc.v:186441.3-186563.6" + wire width 3 $3\core_core_xer_in$next[2:0]$13740 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_cr_out_ok$next[0:0]$13741 + attribute \src "libresoc.v:186370.3-186390.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $3\core_dec$next[63:0]$13354 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_ea_ok$next[0:0]$13262 - attribute \src "libresoc.v:181515.3-181546.6" - wire $3\core_eint$next[0:0]$13355 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_fasto1_ok$next[0:0]$13263 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_fasto2_ok$next[0:0]$13264 - attribute \src "libresoc.v:181515.3-181546.6" - wire width 64 $3\core_msr$next[63:0]$13356 - attribute \src "libresoc.v:181190.3-181226.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13300 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_rego_ok$next[0:0]$13265 - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_spro_ok$next[0:0]$13266 - attribute \src "libresoc.v:180964.3-180984.6" + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $3\core_dec$next[63:0]$13446 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_ea_ok$next[0:0]$13742 + attribute \src "libresoc.v:185947.3-185978.6" + wire $3\core_eint$next[0:0]$13447 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_fasto1_ok$next[0:0]$13743 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_fasto2_ok$next[0:0]$13744 + attribute \src "libresoc.v:185947.3-185978.6" + wire width 64 $3\core_msr$next[63:0]$13448 + attribute \src "libresoc.v:186601.3-186637.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13791 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_rego_ok$next[0:0]$13745 + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_spro_ok$next[0:0]$13746 + attribute \src "libresoc.v:186349.3-186369.6" wire width 4 $3\core_wen[3:0] - attribute \src "libresoc.v:181056.3-181162.6" - wire $3\core_xer_out$next[0:0]$13267 - attribute \src "libresoc.v:181475.3-181495.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13338 - attribute \src "libresoc.v:181330.3-181350.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13315 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $3\fsm_state$next[1:0]$13326 - attribute \src "libresoc.v:181547.3-181570.6" - wire width 32 $3\ilatch$next[31:0]$13361 - attribute \src "libresoc.v:181280.3-181304.6" + attribute \src "libresoc.v:186441.3-186563.6" + wire $3\core_xer_out$next[0:0]$13747 + attribute \src "libresoc.v:185907.3-185927.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13430 + attribute \src "libresoc.v:186741.3-186761.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13806 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $3\fsm_state$next[1:0]$13817 + attribute \src "libresoc.v:185979.3-186002.6" + wire width 32 $3\ilatch$next[31:0]$13453 + attribute \src "libresoc.v:186691.3-186715.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:181305.3-181329.6" + attribute \src "libresoc.v:186716.3-186740.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:181351.3-181380.6" - wire $3\msr_read$next[0:0]$13320 - attribute \src "libresoc.v:181031.3-181055.6" - wire $3\pc_changed$next[0:0]$13062 - attribute \src "libresoc.v:181227.3-181263.6" - wire $4\core_bigendian_i$3$next[0:0]$13307 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_core_cr_rd_ok$next[0:0]$13268 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_core_oe_ok$next[0:0]$13269 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_core_rc_ok$next[0:0]$13270 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_cr_in1_ok$next[0:0]$13271 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_cr_in2_ok$2$next[0:0]$13272 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_cr_in2_ok$next[0:0]$13273 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_cr_wr_ok$next[0:0]$13274 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_fast1_ok$next[0:0]$13275 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_fast2_ok$next[0:0]$13276 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_reg1_ok$next[0:0]$13277 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_reg2_ok$next[0:0]$13278 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_reg3_ok$next[0:0]$13279 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_core_spr1_ok$next[0:0]$13280 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_cr_out_ok$next[0:0]$13281 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_ea_ok$next[0:0]$13282 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_fasto1_ok$next[0:0]$13283 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_fasto2_ok$next[0:0]$13284 - attribute \src "libresoc.v:181190.3-181226.6" - wire width 32 $4\core_raw_insn_i$next[31:0]$13301 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_rego_ok$next[0:0]$13285 - attribute \src "libresoc.v:181056.3-181162.6" - wire $4\core_spro_ok$next[0:0]$13286 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $4\fsm_state$next[1:0]$13327 - attribute \src "libresoc.v:181351.3-181380.6" - wire $4\msr_read$next[0:0]$13321 - attribute \src "libresoc.v:181381.3-181426.6" - wire width 2 $5\fsm_state$next[1:0]$13328 - attribute \src "libresoc.v:180082.19-180082.115" - wire width 65 $add$libresoc.v:180082$12874_Y - attribute \src "libresoc.v:180087.18-180087.107" - wire width 65 $add$libresoc.v:180087$12879_Y - attribute \src "libresoc.v:180071.18-180071.101" - wire $and$libresoc.v:180071$12861_Y - attribute \src "libresoc.v:180086.18-180086.109" - wire $and$libresoc.v:180086$12878_Y - attribute \src "libresoc.v:180095.18-180095.101" - wire $and$libresoc.v:180095$12887_Y - attribute \src "libresoc.v:180096.18-180096.114" - wire width 4 $and$libresoc.v:180096$12888_Y - attribute \src "libresoc.v:180103.18-180103.101" - wire $and$libresoc.v:180103$12895_Y - attribute \src "libresoc.v:180106.18-180106.101" - wire $and$libresoc.v:180106$12898_Y - attribute \src "libresoc.v:180109.18-180109.101" - wire $and$libresoc.v:180109$12901_Y - attribute \src "libresoc.v:180112.18-180112.101" - wire $and$libresoc.v:180112$12904_Y - attribute \src "libresoc.v:180115.18-180115.101" - wire $and$libresoc.v:180115$12907_Y - attribute \src "libresoc.v:180120.18-180120.101" - wire $and$libresoc.v:180120$12912_Y - attribute \src "libresoc.v:180124.18-180124.101" - wire $and$libresoc.v:180124$12916_Y - attribute \src "libresoc.v:180079.19-180079.114" - wire width 64 $extend$libresoc.v:180079$12869_Y - attribute \src "libresoc.v:180080.19-180080.113" - wire width 64 $extend$libresoc.v:180080$12871_Y - attribute \src "libresoc.v:180073.19-180073.111" - wire width 7 $mul$libresoc.v:180073$12863_Y - attribute \src "libresoc.v:180075.19-180075.111" - wire width 7 $mul$libresoc.v:180075$12865_Y - attribute \src "libresoc.v:180078.19-180078.123" - wire $ne$libresoc.v:180078$12868_Y - attribute \src "libresoc.v:180084.18-180084.102" - wire $ne$libresoc.v:180084$12876_Y - attribute \src "libresoc.v:180116.17-180116.101" - wire $ne$libresoc.v:180116$12908_Y - attribute \src "libresoc.v:180072.19-180072.100" - wire $not$libresoc.v:180072$12862_Y - attribute \src "libresoc.v:180085.18-180085.103" - wire $not$libresoc.v:180085$12877_Y - attribute \src "libresoc.v:180088.18-180088.98" - wire $not$libresoc.v:180088$12880_Y - attribute \src "libresoc.v:180089.18-180089.106" - wire $not$libresoc.v:180089$12881_Y - attribute \src "libresoc.v:180090.18-180090.101" - wire $not$libresoc.v:180090$12882_Y - attribute \src "libresoc.v:180091.18-180091.106" - wire $not$libresoc.v:180091$12883_Y - attribute \src "libresoc.v:180092.18-180092.101" - wire $not$libresoc.v:180092$12884_Y - attribute \src "libresoc.v:180093.18-180093.106" - wire $not$libresoc.v:180093$12885_Y - attribute \src "libresoc.v:180094.18-180094.108" - wire $not$libresoc.v:180094$12886_Y - attribute \src "libresoc.v:180098.18-180098.106" - wire $not$libresoc.v:180098$12890_Y - attribute \src "libresoc.v:180099.18-180099.106" - wire $not$libresoc.v:180099$12891_Y - attribute \src "libresoc.v:180100.18-180100.106" - wire $not$libresoc.v:180100$12892_Y - attribute \src "libresoc.v:180101.18-180101.106" - wire $not$libresoc.v:180101$12893_Y - attribute \src "libresoc.v:180102.18-180102.108" - wire $not$libresoc.v:180102$12894_Y - attribute \src "libresoc.v:180104.18-180104.106" - wire $not$libresoc.v:180104$12896_Y - attribute \src "libresoc.v:180105.18-180105.108" - wire $not$libresoc.v:180105$12897_Y - attribute \src "libresoc.v:180107.18-180107.106" - wire $not$libresoc.v:180107$12899_Y - attribute \src "libresoc.v:180108.18-180108.108" - wire $not$libresoc.v:180108$12900_Y - attribute \src "libresoc.v:180110.18-180110.106" - wire $not$libresoc.v:180110$12902_Y - attribute \src "libresoc.v:180111.18-180111.108" - wire $not$libresoc.v:180111$12903_Y - attribute \src "libresoc.v:180113.18-180113.106" - wire $not$libresoc.v:180113$12905_Y - attribute \src "libresoc.v:180114.18-180114.108" - wire $not$libresoc.v:180114$12906_Y - attribute \src "libresoc.v:180117.18-180117.99" - wire $not$libresoc.v:180117$12909_Y - attribute \src "libresoc.v:180118.18-180118.106" - wire $not$libresoc.v:180118$12910_Y - attribute \src "libresoc.v:180119.18-180119.108" - wire $not$libresoc.v:180119$12911_Y - attribute \src "libresoc.v:180121.18-180121.106" - wire $not$libresoc.v:180121$12913_Y - attribute \src "libresoc.v:180122.18-180122.106" - wire $not$libresoc.v:180122$12914_Y - attribute \src "libresoc.v:180123.18-180123.108" - wire $not$libresoc.v:180123$12915_Y - attribute \src "libresoc.v:180125.18-180125.106" - wire $not$libresoc.v:180125$12917_Y - attribute \src "libresoc.v:180126.18-180126.108" - wire $not$libresoc.v:180126$12918_Y - attribute \src "libresoc.v:180083.18-180083.110" - wire $or$libresoc.v:180083$12875_Y - attribute \src "libresoc.v:180079.19-180079.114" - wire width 64 $pos$libresoc.v:180079$12870_Y - attribute \src "libresoc.v:180080.19-180080.113" - wire width 64 $pos$libresoc.v:180080$12872_Y - attribute \src "libresoc.v:180097.18-180097.91" - wire $reduce_or$libresoc.v:180097$12889_Y - attribute \src "libresoc.v:180074.19-180074.42" - wire width 64 $shr$libresoc.v:180074$12864_Y - attribute \src "libresoc.v:180077.19-180077.42" - wire width 64 $shr$libresoc.v:180077$12867_Y - attribute \src "libresoc.v:180076.18-180076.101" - wire width 3 $sub$libresoc.v:180076$12866_Y - attribute \src "libresoc.v:180081.19-180081.115" - wire width 65 $sub$libresoc.v:180081$12873_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" - wire width 3 \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + attribute \src "libresoc.v:186762.3-186791.6" + wire $3\msr_read$next[0:0]$13811 + attribute \src "libresoc.v:186416.3-186440.6" + wire $3\pc_changed$next[0:0]$13510 + attribute \src "libresoc.v:186638.3-186674.6" + wire $4\core_bigendian_i$10$next[0:0]$13798 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$13748 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$3$next[0:0]$13749 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$4$next[0:0]$13750 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$5$next[0:0]$13751 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$6$next[0:0]$13752 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$7$next[0:0]$13753 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$8$next[0:0]$13754 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$9$next[0:0]$13755 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_exc_$signal$next[0:0]$13756 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_oe_ok$next[0:0]$13757 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_core_rc_ok$next[0:0]$13758 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_cr_in1_ok$next[0:0]$13759 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$13760 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_cr_in2_ok$next[0:0]$13761 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_cr_wr_ok$next[0:0]$13762 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_fast1_ok$next[0:0]$13763 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_fast2_ok$next[0:0]$13764 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_reg1_ok$next[0:0]$13765 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_reg2_ok$next[0:0]$13766 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_reg3_ok$next[0:0]$13767 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_core_spr1_ok$next[0:0]$13768 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_cr_out_ok$next[0:0]$13769 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_ea_ok$next[0:0]$13770 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_fasto1_ok$next[0:0]$13771 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_fasto2_ok$next[0:0]$13772 + attribute \src "libresoc.v:186601.3-186637.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$13792 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_rego_ok$next[0:0]$13773 + attribute \src "libresoc.v:186441.3-186563.6" + wire $4\core_spro_ok$next[0:0]$13774 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $4\fsm_state$next[1:0]$13818 + attribute \src "libresoc.v:186762.3-186791.6" + wire $4\msr_read$next[0:0]$13812 + attribute \src "libresoc.v:186792.3-186837.6" + wire width 2 $5\fsm_state$next[1:0]$13819 + attribute \src "libresoc.v:185113.19-185113.115" + wire width 65 $add$libresoc.v:185113$13283_Y + attribute \src "libresoc.v:185121.18-185121.107" + wire width 65 $add$libresoc.v:185121$13291_Y + attribute \src "libresoc.v:185096.19-185096.102" + wire $and$libresoc.v:185096$13264_Y + attribute \src "libresoc.v:185100.19-185100.104" + wire $and$libresoc.v:185100$13268_Y + attribute \src "libresoc.v:185103.19-185103.104" + wire $and$libresoc.v:185103$13271_Y + attribute \src "libresoc.v:185120.18-185120.109" + wire $and$libresoc.v:185120$13290_Y + attribute \src "libresoc.v:185129.18-185129.101" + wire $and$libresoc.v:185129$13299_Y + attribute \src "libresoc.v:185130.18-185130.114" + wire width 4 $and$libresoc.v:185130$13300_Y + attribute \src "libresoc.v:185137.18-185137.101" + wire $and$libresoc.v:185137$13307_Y + attribute \src "libresoc.v:185140.18-185140.101" + wire $and$libresoc.v:185140$13310_Y + attribute \src "libresoc.v:185143.18-185143.101" + wire $and$libresoc.v:185143$13313_Y + attribute \src "libresoc.v:185146.18-185146.101" + wire $and$libresoc.v:185146$13316_Y + attribute \src "libresoc.v:185149.18-185149.101" + wire $and$libresoc.v:185149$13319_Y + attribute \src "libresoc.v:185110.19-185110.114" + wire width 64 $extend$libresoc.v:185110$13278_Y + attribute \src "libresoc.v:185111.19-185111.113" + wire width 64 $extend$libresoc.v:185111$13280_Y + attribute \src "libresoc.v:185105.19-185105.111" + wire width 7 $mul$libresoc.v:185105$13273_Y + attribute \src "libresoc.v:185107.19-185107.111" + wire width 7 $mul$libresoc.v:185107$13275_Y + attribute \src "libresoc.v:185109.19-185109.123" + wire $ne$libresoc.v:185109$13277_Y + attribute \src "libresoc.v:185114.18-185114.102" + wire $ne$libresoc.v:185114$13284_Y + attribute \src "libresoc.v:185118.18-185118.102" + wire $ne$libresoc.v:185118$13288_Y + attribute \src "libresoc.v:185095.18-185095.108" + wire $not$libresoc.v:185095$13263_Y + attribute \src "libresoc.v:185097.19-185097.107" + wire $not$libresoc.v:185097$13265_Y + attribute \src "libresoc.v:185098.19-185098.107" + wire $not$libresoc.v:185098$13266_Y + attribute \src "libresoc.v:185099.19-185099.109" + wire $not$libresoc.v:185099$13267_Y + attribute \src "libresoc.v:185101.19-185101.107" + wire $not$libresoc.v:185101$13269_Y + attribute \src "libresoc.v:185102.19-185102.109" + wire $not$libresoc.v:185102$13270_Y + attribute \src "libresoc.v:185104.19-185104.100" + wire $not$libresoc.v:185104$13272_Y + attribute \src "libresoc.v:185119.18-185119.103" + wire $not$libresoc.v:185119$13289_Y + attribute \src "libresoc.v:185122.18-185122.98" + wire $not$libresoc.v:185122$13292_Y + attribute \src "libresoc.v:185123.18-185123.106" + wire $not$libresoc.v:185123$13293_Y + attribute \src "libresoc.v:185124.18-185124.101" + wire $not$libresoc.v:185124$13294_Y + attribute \src "libresoc.v:185125.18-185125.106" + wire $not$libresoc.v:185125$13295_Y + attribute \src "libresoc.v:185126.18-185126.101" + wire $not$libresoc.v:185126$13296_Y + attribute \src "libresoc.v:185127.18-185127.106" + wire $not$libresoc.v:185127$13297_Y + attribute \src "libresoc.v:185128.18-185128.108" + wire $not$libresoc.v:185128$13298_Y + attribute \src "libresoc.v:185132.18-185132.106" + wire $not$libresoc.v:185132$13302_Y + attribute \src "libresoc.v:185133.18-185133.106" + wire $not$libresoc.v:185133$13303_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" + wire width 32 \$119 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$108 + wire width 7 \$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" - wire \$111 + wire width 32 \$123 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" + wire \$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$113 + wire width 64 \$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" - wire width 65 \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" - wire width 65 \$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" - wire width 65 \$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" - wire width 65 \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" - wire \$14 + wire width 64 \$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" + wire width 65 \$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" + wire width 65 \$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + wire width 65 \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + wire width 65 \$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + wire width 3 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + wire width 3 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + wire \$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$16 + wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" - wire width 65 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" - wire width 65 \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 65 \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 65 \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - wire width 4 \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + wire width 4 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 11 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 9 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire output 8 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:39" - wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:90" - wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 6 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 342 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 178 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 333 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 343 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire output 3 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:103" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \core_bigendian_i$3 + wire \core_bigendian_i$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \core_bigendian_i$3$next + wire \core_bigendian_i$10$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \core_cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \core_core_core_cia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \core_core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \core_core_core_cr_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_cr_rd_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \core_core_core_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \core_core_core_cr_wr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_core_exc_$signal$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -375514,21 +384782,21 @@ module \test_issuer attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 \core_core_core_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 \core_core_core_fn_unit$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 \core_core_core_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 \core_core_core_input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 \core_core_core_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 \core_core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -375604,140 +384872,138 @@ module \test_issuer attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \core_core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \core_core_core_insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire \core_core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire \core_core_core_is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 \core_core_core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 \core_core_core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_oe_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_core_rc_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \core_core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \core_core_core_trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_core_traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \core_core_core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \core_core_core_traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in2$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in2$1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_in2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_in2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_cr_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_cr_wr_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_ea$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fasto1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \core_core_fasto2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire \core_core_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire \core_core_lk$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 \core_core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 \core_core_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_reg3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_reg3_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \core_core_rego$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" - wire \core_core_reset_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -375849,13 +385115,13 @@ module \test_issuer attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \core_core_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \core_core_spr1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_core_spr1_ok$next attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -375968,23 +385234,23 @@ module \test_issuer attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \core_core_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \core_core_spro$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" wire \core_core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \core_core_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire \core_coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire \core_coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire \core_cu_ad__go_i @@ -376006,21 +385272,21 @@ module \test_issuer wire width 64 \core_dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire \core_dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_ea_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" wire \core_eint attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" wire \core_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto2_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 32 \core_full_rd2__data_o @@ -376033,7 +385299,7 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \core_issue__addr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \core_issue__addr$4 + wire width 3 \core_issue__addr$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_issue__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -376058,41 +385324,45 @@ module \test_issuer wire width 32 \core_raw_insn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire width 32 \core_raw_insn_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_rego_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_spro_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \core_state_nia_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" wire \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \core_wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 4 \core_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 360 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire \cu_st__rel_o_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire \cu_st__rel_o_dly$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire \cu_st__rel_o_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:332" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:332" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" wire width 64 \dbg_core_dbg_msr @@ -376147,56 +385417,52 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" wire \dbg_terminate_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 138 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 132 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 141 \dbus__bte + wire input 9 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 140 \dbus__cti + wire width 45 output 14 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 136 \dbus__cyc + wire output 8 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 134 \dbus__dat_r + wire width 64 input 13 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 133 \dbus__dat_w + wire width 64 output 16 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 142 \dbus__err + wire input 10 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 135 \dbus__sel + wire width 8 output 12 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 137 \dbus__stb + wire output 11 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 139 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire output 15 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" wire \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_cr_in2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire \dec2_cr_in2_ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_in2_ok$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \dec2_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 8 \dec2_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_cr_wr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" wire width 64 \dec2_cur_dec @@ -376214,25 +385480,41 @@ module \test_issuer wire width 64 \dec2_cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 \dec2_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" @@ -376247,15 +385529,15 @@ module \test_issuer attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 12 \dec2_fn_unit attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -376331,39 +385613,39 @@ module \test_issuer attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" wire width 7 \dec2_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire \dec2_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire \dec2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rego_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -376476,9 +385758,9 @@ module \test_issuer attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \dec2_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spr1_ok attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -376591,291 +385873,281 @@ module \test_issuer attribute \enum_value_1110000000 "PPR" attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" wire width 2 \delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - wire width 2 \fsm_state$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - wire width 2 \fsm_state$117$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + wire width 2 \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + wire width 2 \fsm_state$133$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" wire width 2 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 25 \gpio_gpio0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 26 \gpio_gpio0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 27 \gpio_gpio0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 28 \gpio_gpio0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 29 \gpio_gpio0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 30 \gpio_gpio0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 85 \gpio_gpio10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 86 \gpio_gpio10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 87 \gpio_gpio10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 88 \gpio_gpio10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 89 \gpio_gpio10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 90 \gpio_gpio10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 91 \gpio_gpio11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 92 \gpio_gpio11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 93 \gpio_gpio11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 94 \gpio_gpio11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 95 \gpio_gpio11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 96 \gpio_gpio11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 97 \gpio_gpio12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 98 \gpio_gpio12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 99 \gpio_gpio12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 100 \gpio_gpio12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 101 \gpio_gpio12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 102 \gpio_gpio12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 103 \gpio_gpio13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 104 \gpio_gpio13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 105 \gpio_gpio13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 106 \gpio_gpio13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 107 \gpio_gpio13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 108 \gpio_gpio13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 109 \gpio_gpio14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 110 \gpio_gpio14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 111 \gpio_gpio14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 112 \gpio_gpio14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 113 \gpio_gpio14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 114 \gpio_gpio14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 115 \gpio_gpio15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 116 \gpio_gpio15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 117 \gpio_gpio15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 118 \gpio_gpio15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 119 \gpio_gpio15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 120 \gpio_gpio15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 31 \gpio_gpio1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 32 \gpio_gpio1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 33 \gpio_gpio1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 34 \gpio_gpio1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 35 \gpio_gpio1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 36 \gpio_gpio1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 37 \gpio_gpio2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 38 \gpio_gpio2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 39 \gpio_gpio2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 40 \gpio_gpio2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 41 \gpio_gpio2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 42 \gpio_gpio2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 43 \gpio_gpio3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 44 \gpio_gpio3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 45 \gpio_gpio3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 46 \gpio_gpio3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 47 \gpio_gpio3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 48 \gpio_gpio3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 49 \gpio_gpio4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 50 \gpio_gpio4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 51 \gpio_gpio4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 52 \gpio_gpio4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 53 \gpio_gpio4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 54 \gpio_gpio4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 55 \gpio_gpio5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 56 \gpio_gpio5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 57 \gpio_gpio5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 58 \gpio_gpio5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 59 \gpio_gpio5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 60 \gpio_gpio5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 61 \gpio_gpio6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 62 \gpio_gpio6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 63 \gpio_gpio6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 64 \gpio_gpio6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 65 \gpio_gpio6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 66 \gpio_gpio6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 67 \gpio_gpio7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 68 \gpio_gpio7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 69 \gpio_gpio7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 70 \gpio_gpio7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 71 \gpio_gpio7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 72 \gpio_gpio7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 73 \gpio_gpio8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 74 \gpio_gpio8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 75 \gpio_gpio8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 76 \gpio_gpio8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 77 \gpio_gpio8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 78 \gpio_gpio8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 79 \gpio_gpio9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 80 \gpio_gpio9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 81 \gpio_gpio9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 82 \gpio_gpio9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 83 \gpio_gpio9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 84 \gpio_gpio9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 127 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 121 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 130 \ibus__bte + wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 129 \ibus__cti + wire width 45 output 23 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 125 \ibus__cyc + wire output 17 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 123 \ibus__dat_r + wire width 64 input 22 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 122 \ibus__dat_w + wire input 19 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 131 \ibus__err + wire width 8 output 21 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 124 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 126 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 128 \ibus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 149 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 143 \icp_wb__adr + wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 2 input 152 \icp_wb__bte + wire output 344 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 3 input 151 \icp_wb__cti + wire width 28 input 350 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 147 \icp_wb__cyc + wire input 345 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 145 \icp_wb__dat_r + wire width 32 output 346 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 144 \icp_wb__dat_w + wire width 32 input 347 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 153 \icp_wb__err + wire width 4 input 351 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 146 \icp_wb__sel + wire input 348 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 148 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 150 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 160 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 154 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 2 input 163 \ics_wb__bte + wire input 349 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 3 input 162 \ics_wb__cti + wire output 357 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 158 \ics_wb__cyc + wire width 28 input 352 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 156 \ics_wb__dat_r + wire input 354 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 155 \ics_wb__dat_w + wire width 32 output 356 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 164 \ics_wb__err + wire width 32 input 358 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 157 \ics_wb__sel + wire input 355 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 159 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 161 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + wire input 359 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" wire width 32 \ilatch$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i @@ -376887,84 +386159,488 @@ module \test_issuer wire width 64 \imem_f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" wire \imem_f_valid_i - attribute \src "libresoc.v:178436.7-178436.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \imem_wb_icache_en + attribute \src "libresoc.v:183018.7-183018.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 165 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \jtag_dmi0_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \jtag_dmi0_ack_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \jtag_dmi0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \jtag_dmi0_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \jtag_dmi0_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \jtag_dmi0_dout$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \jtag_dmi0_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \jtag_dmi0_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 19 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 29 output 12 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 16 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 input 14 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire width 64 output 13 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire input 20 \jtag_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 15 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 17 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi2jtag.py:89" - wire output 18 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:91" - wire input 3 \memerr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + wire width 16 input 353 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 340 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 334 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 336 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 341 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 339 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 335 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 337 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" wire \msr_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:407" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:184" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 166 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:87" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:101" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 7 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 23 \uart_rx__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 24 \uart_rx__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire input 21 \uart_tx__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:48" - wire output 22 \uart_tx__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 2 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 324 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 169 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 327 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 173 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 174 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 328 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 329 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 330 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 175 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 331 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 332 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" + wire \ti_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" @@ -376975,8 +386651,8 @@ module \test_issuer wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:389" - cell $add $add$libresoc.v:180082$12874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + cell $add $add$libresoc.v:185113$13283 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -376984,10 +386660,10 @@ module \test_issuer parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:180082$12874_Y + connect \Y $add$libresoc.v:185113$13283_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:181" - cell $add $add$libresoc.v:180087$12879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + cell $add $add$libresoc.v:185121$13291 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -376995,54 +386671,54 @@ module \test_issuer parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:180087$12879_Y + connect \Y $add$libresoc.v:185121$13291_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180071$12861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185096$13264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$95 - connect \B \$97 - connect \Y $and$libresoc.v:180071$12861_Y + connect \A \$97 + connect \B \$99 + connect \Y $and$libresoc.v:185096$13264_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:180086$12878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185100$13268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B \$16 - connect \Y $and$libresoc.v:180086$12878_Y + connect \A \$105 + connect \B \$107 + connect \Y $and$libresoc.v:185100$13268_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180095$12887 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185103$13271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $and$libresoc.v:180095$12887_Y + connect \A \$111 + connect \B \$113 + connect \Y $and$libresoc.v:185103$13271_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - cell $and $and$libresoc.v:180096$12888 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:185120$13290 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \core_state_nia_wen - connect \B 1'1 - connect \Y $and$libresoc.v:180096$12888_Y + parameter \Y_WIDTH 1 + connect \A \core_cu_st__rel_o + connect \B \$32 + connect \Y $and$libresoc.v:185120$13290_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180103$12895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185129$13299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377050,65 +386726,65 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:180103$12895_Y + connect \Y $and$libresoc.v:185129$13299_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180106$12898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + cell $and $and$libresoc.v:185130$13300 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$55 - connect \B \$57 - connect \Y $and$libresoc.v:180106$12898_Y + parameter \Y_WIDTH 4 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:185130$13300_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180109$12901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185137$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$61 - connect \B \$63 - connect \Y $and$libresoc.v:180109$12901_Y + connect \A \$65 + connect \B \$67 + connect \Y $and$libresoc.v:185137$13307_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180112$12904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185140$13310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \$69 - connect \Y $and$libresoc.v:180112$12904_Y + connect \A \$71 + connect \B \$73 + connect \Y $and$libresoc.v:185140$13310_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180115$12907 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185143$13313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$libresoc.v:180115$12907_Y + connect \A \$77 + connect \B \$79 + connect \Y $and$libresoc.v:185143$13313_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180120$12912 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185146$13316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$81 - connect \B \$83 - connect \Y $and$libresoc.v:180120$12912_Y + connect \A \$83 + connect \B \$85 + connect \Y $and$libresoc.v:185146$13316_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $and $and$libresoc.v:180124$12916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $and $and$libresoc.v:185149$13319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377116,26 +386792,26 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:180124$12916_Y + connect \Y $and$libresoc.v:185149$13319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:180079$12869 + cell $pos $extend$libresoc.v:185110$13278 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:180079$12869_Y + connect \Y $extend$libresoc.v:185110$13278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:180080$12871 + cell $pos $extend$libresoc.v:185111$13280 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:180080$12871_Y + connect \Y $extend$libresoc.v:185111$13280_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:180073$12863 + cell $mul $mul$libresoc.v:185105$13273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377143,10 +386819,10 @@ module \test_issuer parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:180073$12863_Y + connect \Y $mul$libresoc.v:185105$13273_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:180075$12865 + cell $mul $mul$libresoc.v:185107$13275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377154,10 +386830,10 @@ module \test_issuer parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:180075$12865_Y + connect \Y $mul$libresoc.v:185107$13275_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" - cell $ne $ne$libresoc.v:180078$12868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" + cell $ne $ne$libresoc.v:185109$13277 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377165,272 +386841,272 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:180078$12868_Y + connect \Y $ne$libresoc.v:185109$13277_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" - cell $ne $ne$libresoc.v:180084$12876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + cell $ne $ne$libresoc.v:185114$13284 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay - connect \B \$12 - connect \Y $ne$libresoc.v:180084$12876_Y + connect \B 1'0 + connect \Y $ne$libresoc.v:185114$13284_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" - cell $ne $ne$libresoc.v:180116$12908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + cell $ne $ne$libresoc.v:185118$13288 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \delay - connect \B 1'0 - connect \Y $ne$libresoc.v:180116$12908_Y + connect \B \$28 + connect \Y $ne$libresoc.v:185118$13288_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" - cell $not $not$libresoc.v:180072$12862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185095$13263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:180072$12862_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185095$13263_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:180085$12877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185097$13265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:180085$12877_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:185097$13265_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:186" - cell $not $not$libresoc.v:180088$12880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185098$13266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:180088$12880_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185098$13266_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180089$12881 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185099$13267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180089$12881_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185099$13267_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:180090$12882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185101$13269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:180090$12882_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185101$13269_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180091$12883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185102$13270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180091$12883_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185102$13270_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - cell $not $not$libresoc.v:180092$12884 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + cell $not $not$libresoc.v:185104$13272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:180092$12884_Y + connect \A \msr_read + connect \Y $not$libresoc.v:185104$13272_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180093$12885 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:185119$13289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180093$12885_Y + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:185119$13289_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180094$12886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + cell $not $not$libresoc.v:185122$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180094$12886_Y + connect \A \pc_i_ok + connect \Y $not$libresoc.v:185122$13292_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180098$12890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185123$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180098$12890_Y + connect \Y $not$libresoc.v:185123$13293_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180099$12891 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + cell $not $not$libresoc.v:185124$13294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180099$12891_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:185124$13294_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180100$12892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185125$13295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180100$12892_Y + connect \Y $not$libresoc.v:185125$13295_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180101$12893 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + cell $not $not$libresoc.v:185126$13296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180101$12893_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:185126$13296_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180102$12894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185127$13297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180102$12894_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185127$13297_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180104$12896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185128$13298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180104$12896_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185128$13298_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180105$12897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185132$13302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180105$12897_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:185132$13302_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180107$12899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185133$13303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180107$12899_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:185133$13303_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180108$12900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + cell $not $not$libresoc.v:185134$13304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180108$12900_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:185134$13304_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180110$12902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185135$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180110$12902_Y + connect \Y $not$libresoc.v:185135$13305_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180111$12903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185136$13306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180111$12903_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185136$13306_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180113$12905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185138$13308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180113$12905_Y + connect \Y $not$libresoc.v:185138$13308_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180114$12906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185139$13309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180114$12906_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185139$13309_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" - cell $not $not$libresoc.v:180117$12909 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185141$13311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:180117$12909_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185141$13311_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180118$12910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185142$13312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180118$12910_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185142$13312_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180119$12911 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185144$13314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180119$12911_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185144$13314_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - cell $not $not$libresoc.v:180121$12913 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185145$13315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:180121$12913_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185145$13315_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180122$12914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185147$13317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180122$12914_Y + connect \Y $not$libresoc.v:185147$13317_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180123$12915 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185148$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180123$12915_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:185148$13318_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180125$12917 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + cell $not $not$libresoc.v:185150$13320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:180125$12917_Y + connect \A \msr_read + connect \Y $not$libresoc.v:185150$13320_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - cell $not $not$libresoc.v:180126$12918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + cell $not $not$libresoc.v:185151$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $not$libresoc.v:180126$12918_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:185151$13321_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:161" - cell $or $or$libresoc.v:180083$12875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + cell $or $or$libresoc.v:185116$13286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377438,86 +387114,105 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:180083$12875_Y + connect \Y $or$libresoc.v:185116$13286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" + cell $or $or$libresoc.v:185117$13287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \rst + connect \Y $or$libresoc.v:185117$13287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:180079$12870 + cell $pos $pos$libresoc.v:185110$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:180079$12869_Y - connect \Y $pos$libresoc.v:180079$12870_Y + connect \A $extend$libresoc.v:185110$13278_Y + connect \Y $pos$libresoc.v:185110$13279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:180080$12872 + cell $pos $pos$libresoc.v:185111$13281 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:180080$12871_Y - connect \Y $pos$libresoc.v:180080$12872_Y + connect \A $extend$libresoc.v:185111$13280_Y + connect \Y $pos$libresoc.v:185111$13281_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:180097$12889 + cell $reduce_or $reduce_or$libresoc.v:185131$13301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \$40 - connect \Y $reduce_or$libresoc.v:180097$12889_Y + connect \A \$56 + connect \Y $reduce_or$libresoc.v:185131$13301_Y end - attribute \src "libresoc.v:180074.19-180074.42" - cell $shr $shr$libresoc.v:180074$12864 + attribute \src "libresoc.v:185106.19-185106.42" + cell $shr $shr$libresoc.v:185106$13274 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$104 - connect \Y $shr$libresoc.v:180074$12864_Y + connect \B \$120 + connect \Y $shr$libresoc.v:185106$13274_Y end - attribute \src "libresoc.v:180077.19-180077.42" - cell $shr $shr$libresoc.v:180077$12867 + attribute \src "libresoc.v:185108.19-185108.42" + cell $shr $shr$libresoc.v:185108$13276 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$108 - connect \Y $shr$libresoc.v:180077$12867_Y + connect \B \$124 + connect \Y $shr$libresoc.v:185108$13276_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:157" - cell $sub $sub$libresoc.v:180076$12866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" + cell $sub $sub$libresoc.v:185112$13282 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:180076$12866_Y + connect \Y $sub$libresoc.v:185112$13282_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:373" - cell $sub $sub$libresoc.v:180081$12873 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + cell $sub $sub$libresoc.v:185115$13285 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o + parameter \Y_WIDTH 3 + connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:180081$12873_Y + connect \Y $sub$libresoc.v:185115$13285_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:180283.8-180367.4" + attribute \src "libresoc.v:185324.8-185417.4" cell \core \core - connect \bigendian_i \core_bigendian_i$3 + connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o connect \cia__ren \core_cia__ren connect \core_core_cia \core_core_core_cia connect \core_core_cr_rd \core_core_core_cr_rd connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_exc_$signal \core_core_core_exc_$signal + connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 + connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 + connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 + connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 + connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 + connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 + connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 connect \core_core_fn_unit \core_core_core_fn_unit connect \core_core_input_carry \core_core_core_input_carry connect \core_core_insn \core_core_core_insn @@ -377552,14 +387247,14 @@ module \test_issuer connect \core_reg3 \core_core_reg3 connect \core_reg3_ok \core_core_reg3_ok connect \core_rego \core_core_rego - connect \core_reset_i \core_core_reset_i connect \core_spr1 \core_core_spr1 connect \core_spr1_ok \core_core_spr1_ok connect \core_spro \core_core_spro connect \core_terminate_o \core_core_terminate_o connect \core_xer_in \core_core_xer_in connect \corebusy_o \core_corebusy_o - connect \coresync_clk \core_coresync_clk + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst connect \cu_ad__go_i \core_cu_ad__go_i connect \cu_ad__rel_o \core_cu_ad__rel_o connect \cu_st__go_i \core_cu_st__go_i @@ -377582,7 +387277,7 @@ module \test_issuer connect \full_rd__data_o \core_full_rd__data_o connect \full_rd__ren \core_full_rd__ren connect \issue__addr \core_issue__addr - connect \issue__addr$3 \core_issue__addr$4 + connect \issue__addr$10 \core_issue__addr$11 connect \issue__data_i \core_issue__data_i connect \issue__data_o \core_issue__data_o connect \issue__ren \core_issue__ren @@ -377593,10 +387288,11 @@ module \test_issuer connect \msr__ren \core_msr__ren connect \raw_insn_i \core_raw_insn_i connect \state_nia_wen \core_state_nia_wen + connect \wb_dcache_en \core_wb_dcache_en connect \wen \core_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:180368.7-180393.4" + attribute \src "libresoc.v:185418.7-185443.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_msr \dbg_core_dbg_msr @@ -377624,7 +387320,7 @@ module \test_issuer connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:180394.8-180452.4" + attribute \src "libresoc.v:185444.8-185510.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -377632,9 +387328,9 @@ module \test_issuer connect \cr_in1 \dec2_cr_in1 connect \cr_in1_ok \dec2_cr_in1_ok connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$5 + connect \cr_in2$1 \dec2_cr_in2$12 connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 + connect \cr_in2_ok$2 \dec2_cr_in2_ok$13 connect \cr_out \dec2_cr_out connect \cr_out_ok \dec2_cr_out_ok connect \cr_rd \dec2_cr_rd @@ -377647,6 +387343,14 @@ module \test_issuer connect \cur_pc \dec2_cur_pc connect \ea \dec2_ea connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$14 + connect \exc_$signal$4 \dec2_exc_$signal$15 + connect \exc_$signal$5 \dec2_exc_$signal$16 + connect \exc_$signal$6 \dec2_exc_$signal$17 + connect \exc_$signal$7 \dec2_exc_$signal$18 + connect \exc_$signal$8 \dec2_exc_$signal$19 + connect \exc_$signal$9 \dec2_exc_$signal$20 connect \fast1 \dec2_fast1 connect \fast1_ok \dec2_fast1_ok connect \fast2 \dec2_fast2 @@ -377685,7 +387389,7 @@ module \test_issuer connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:180453.8-180468.4" + attribute \src "libresoc.v:185511.8-185527.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -377701,117 +387405,124 @@ module \test_issuer connect \ibus__sel \ibus__sel connect \ibus__stb \ibus__stb connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:180469.8-180590.4" + attribute \src "libresoc.v:185528.8-185859.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_bus__tdo \TAP_bus__tdo connect \TAP_bus__tms \TAP_bus__tms connect \clk \clk - connect \dmi0_ack_o \jtag_dmi0_ack_o - connect \dmi0_addr_i \jtag_dmi0_addr_i - connect \dmi0_din \jtag_dmi0_din - connect \dmi0_dout \jtag_dmi0_dout - connect \dmi0_req_i \jtag_dmi0_req_i - connect \dmi0_we_i \jtag_dmi0_we_i - connect \gpio_gpio0__core__i \gpio_gpio0__core__i - connect \gpio_gpio0__core__o \gpio_gpio0__core__o - connect \gpio_gpio0__core__oe \gpio_gpio0__core__oe - connect \gpio_gpio0__pad__i \gpio_gpio0__pad__i - connect \gpio_gpio0__pad__o \gpio_gpio0__pad__o - connect \gpio_gpio0__pad__oe \gpio_gpio0__pad__oe - connect \gpio_gpio10__core__i \gpio_gpio10__core__i - connect \gpio_gpio10__core__o \gpio_gpio10__core__o - connect \gpio_gpio10__core__oe \gpio_gpio10__core__oe - connect \gpio_gpio10__pad__i \gpio_gpio10__pad__i - connect \gpio_gpio10__pad__o \gpio_gpio10__pad__o - connect \gpio_gpio10__pad__oe \gpio_gpio10__pad__oe - connect \gpio_gpio11__core__i \gpio_gpio11__core__i - connect \gpio_gpio11__core__o \gpio_gpio11__core__o - connect \gpio_gpio11__core__oe \gpio_gpio11__core__oe - connect \gpio_gpio11__pad__i \gpio_gpio11__pad__i - connect \gpio_gpio11__pad__o \gpio_gpio11__pad__o - connect \gpio_gpio11__pad__oe \gpio_gpio11__pad__oe - connect \gpio_gpio12__core__i \gpio_gpio12__core__i - connect \gpio_gpio12__core__o \gpio_gpio12__core__o - connect \gpio_gpio12__core__oe \gpio_gpio12__core__oe - connect \gpio_gpio12__pad__i \gpio_gpio12__pad__i - connect \gpio_gpio12__pad__o \gpio_gpio12__pad__o - connect \gpio_gpio12__pad__oe \gpio_gpio12__pad__oe - connect \gpio_gpio13__core__i \gpio_gpio13__core__i - connect \gpio_gpio13__core__o \gpio_gpio13__core__o - connect \gpio_gpio13__core__oe \gpio_gpio13__core__oe - connect \gpio_gpio13__pad__i \gpio_gpio13__pad__i - connect \gpio_gpio13__pad__o \gpio_gpio13__pad__o - connect \gpio_gpio13__pad__oe \gpio_gpio13__pad__oe - connect \gpio_gpio14__core__i \gpio_gpio14__core__i - connect \gpio_gpio14__core__o \gpio_gpio14__core__o - connect \gpio_gpio14__core__oe \gpio_gpio14__core__oe - connect \gpio_gpio14__pad__i \gpio_gpio14__pad__i - connect \gpio_gpio14__pad__o \gpio_gpio14__pad__o - connect \gpio_gpio14__pad__oe \gpio_gpio14__pad__oe - connect \gpio_gpio15__core__i \gpio_gpio15__core__i - connect \gpio_gpio15__core__o \gpio_gpio15__core__o - connect \gpio_gpio15__core__oe \gpio_gpio15__core__oe - connect \gpio_gpio15__pad__i \gpio_gpio15__pad__i - connect \gpio_gpio15__pad__o \gpio_gpio15__pad__o - connect \gpio_gpio15__pad__oe \gpio_gpio15__pad__oe - connect \gpio_gpio1__core__i \gpio_gpio1__core__i - connect \gpio_gpio1__core__o \gpio_gpio1__core__o - connect \gpio_gpio1__core__oe \gpio_gpio1__core__oe - connect \gpio_gpio1__pad__i \gpio_gpio1__pad__i - connect \gpio_gpio1__pad__o \gpio_gpio1__pad__o - connect \gpio_gpio1__pad__oe \gpio_gpio1__pad__oe - connect \gpio_gpio2__core__i \gpio_gpio2__core__i - connect \gpio_gpio2__core__o \gpio_gpio2__core__o - connect \gpio_gpio2__core__oe \gpio_gpio2__core__oe - connect \gpio_gpio2__pad__i \gpio_gpio2__pad__i - connect \gpio_gpio2__pad__o \gpio_gpio2__pad__o - connect \gpio_gpio2__pad__oe \gpio_gpio2__pad__oe - connect \gpio_gpio3__core__i \gpio_gpio3__core__i - connect \gpio_gpio3__core__o \gpio_gpio3__core__o - connect \gpio_gpio3__core__oe \gpio_gpio3__core__oe - connect \gpio_gpio3__pad__i \gpio_gpio3__pad__i - connect \gpio_gpio3__pad__o \gpio_gpio3__pad__o - connect \gpio_gpio3__pad__oe \gpio_gpio3__pad__oe - connect \gpio_gpio4__core__i \gpio_gpio4__core__i - connect \gpio_gpio4__core__o \gpio_gpio4__core__o - connect \gpio_gpio4__core__oe \gpio_gpio4__core__oe - connect \gpio_gpio4__pad__i \gpio_gpio4__pad__i - connect \gpio_gpio4__pad__o \gpio_gpio4__pad__o - connect \gpio_gpio4__pad__oe \gpio_gpio4__pad__oe - connect \gpio_gpio5__core__i \gpio_gpio5__core__i - connect \gpio_gpio5__core__o \gpio_gpio5__core__o - connect \gpio_gpio5__core__oe \gpio_gpio5__core__oe - connect \gpio_gpio5__pad__i \gpio_gpio5__pad__i - connect \gpio_gpio5__pad__o \gpio_gpio5__pad__o - connect \gpio_gpio5__pad__oe \gpio_gpio5__pad__oe - connect \gpio_gpio6__core__i \gpio_gpio6__core__i - connect \gpio_gpio6__core__o \gpio_gpio6__core__o - connect \gpio_gpio6__core__oe \gpio_gpio6__core__oe - connect \gpio_gpio6__pad__i \gpio_gpio6__pad__i - connect \gpio_gpio6__pad__o \gpio_gpio6__pad__o - connect \gpio_gpio6__pad__oe \gpio_gpio6__pad__oe - connect \gpio_gpio7__core__i \gpio_gpio7__core__i - connect \gpio_gpio7__core__o \gpio_gpio7__core__o - connect \gpio_gpio7__core__oe \gpio_gpio7__core__oe - connect \gpio_gpio7__pad__i \gpio_gpio7__pad__i - connect \gpio_gpio7__pad__o \gpio_gpio7__pad__o - connect \gpio_gpio7__pad__oe \gpio_gpio7__pad__oe - connect \gpio_gpio8__core__i \gpio_gpio8__core__i - connect \gpio_gpio8__core__o \gpio_gpio8__core__o - connect \gpio_gpio8__core__oe \gpio_gpio8__core__oe - connect \gpio_gpio8__pad__i \gpio_gpio8__pad__i - connect \gpio_gpio8__pad__o \gpio_gpio8__pad__o - connect \gpio_gpio8__pad__oe \gpio_gpio8__pad__oe - connect \gpio_gpio9__core__i \gpio_gpio9__core__i - connect \gpio_gpio9__core__o \gpio_gpio9__core__o - connect \gpio_gpio9__core__oe \gpio_gpio9__core__oe - connect \gpio_gpio9__pad__i \gpio_gpio9__pad__i - connect \gpio_gpio9__pad__o \gpio_gpio9__pad__o - connect \gpio_gpio9__pad__oe \gpio_gpio9__pad__oe + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe connect \jtag_wb__ack \jtag_wb__ack connect \jtag_wb__adr \jtag_wb__adr connect \jtag_wb__cyc \jtag_wb__cyc @@ -377820,14 +387531,218 @@ module \test_issuer connect \jtag_wb__sel \jtag_wb__sel connect \jtag_wb__stb \jtag_wb__stb connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o connect \rst \rst - connect \uart_rx__core__i \uart_rx__core__i - connect \uart_rx__pad__i \uart_rx__pad__i - connect \uart_tx__core__o \uart_tx__core__o - connect \uart_tx__pad__o \uart_tx__pad__o + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_dcache_en \core_wb_dcache_en + connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:180591.12-180605.4" + attribute \src "libresoc.v:185860.12-185874.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -377844,7 +387759,7 @@ module \test_issuer connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:180606.12-180619.4" + attribute \src "libresoc.v:185875.12-185888.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -377859,1242 +387774,1598 @@ module \test_issuer connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:178436.7-178436.20" - process $proc$libresoc.v:178436$13363 + attribute \src "libresoc.v:183018.7-183018.20" + process $proc$libresoc.v:183018$13822 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178570.13-178570.33" - process $proc$libresoc.v:178570$13364 + attribute \src "libresoc.v:183154.13-183154.33" + process $proc$libresoc.v:183154$13823 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:178576.7-178576.34" - process $proc$libresoc.v:178576$13365 + attribute \src "libresoc.v:183160.7-183160.35" + process $proc$libresoc.v:183160$13824 assign { } { } - assign $0\core_bigendian_i$3[0:0]$13366 1'0 + assign $0\core_bigendian_i$10[0:0]$13825 1'0 sync always sync init - update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$13366 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13825 end - attribute \src "libresoc.v:178584.14-178584.55" - process $proc$libresoc.v:178584$13367 + attribute \src "libresoc.v:183168.14-183168.55" + process $proc$libresoc.v:183168$13826 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:178588.13-178588.41" - process $proc$libresoc.v:178588$13368 + attribute \src "libresoc.v:183172.13-183172.41" + process $proc$libresoc.v:183172$13827 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:178592.7-178592.37" - process $proc$libresoc.v:178592$13369 + attribute \src "libresoc.v:183176.7-183176.37" + process $proc$libresoc.v:183176$13828 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:178596.13-178596.41" - process $proc$libresoc.v:178596$13370 + attribute \src "libresoc.v:183180.13-183180.41" + process $proc$libresoc.v:183180$13829 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:178613.14-178613.46" - process $proc$libresoc.v:178613$13371 + attribute \src "libresoc.v:183184.7-183184.42" + process $proc$libresoc.v:183184$13830 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13831 1'0 + sync always + sync init + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13831 + end + attribute \src "libresoc.v:183186.7-183186.44" + process $proc$libresoc.v:183186$13832 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13833 1'0 + sync always + sync init + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13833 + end + attribute \src "libresoc.v:183190.7-183190.44" + process $proc$libresoc.v:183190$13834 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13835 1'0 + sync always + sync init + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13835 + end + attribute \src "libresoc.v:183194.7-183194.44" + process $proc$libresoc.v:183194$13836 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13837 1'0 + sync always + sync init + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13837 + end + attribute \src "libresoc.v:183198.7-183198.44" + process $proc$libresoc.v:183198$13838 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13839 1'0 + sync always + sync init + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13839 + end + attribute \src "libresoc.v:183202.7-183202.44" + process $proc$libresoc.v:183202$13840 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$13841 1'0 + sync always + sync init + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13841 + end + attribute \src "libresoc.v:183206.7-183206.44" + process $proc$libresoc.v:183206$13842 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13843 1'0 + sync always + sync init + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13843 + end + attribute \src "libresoc.v:183210.7-183210.44" + process $proc$libresoc.v:183210$13844 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13845 1'0 + sync always + sync init + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13845 + end + attribute \src "libresoc.v:183229.14-183229.46" + process $proc$libresoc.v:183229$13846 assign { } { } assign $1\core_core_core_fn_unit[11:0] 12'000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] end - attribute \src "libresoc.v:178621.13-178621.46" - process $proc$libresoc.v:178621$13372 + attribute \src "libresoc.v:183237.13-183237.46" + process $proc$libresoc.v:183237$13847 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:178625.14-178625.41" - process $proc$libresoc.v:178625$13373 + attribute \src "libresoc.v:183241.14-183241.41" + process $proc$libresoc.v:183241$13848 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:178703.13-178703.45" - process $proc$libresoc.v:178703$13374 + attribute \src "libresoc.v:183319.13-183319.45" + process $proc$libresoc.v:183319$13849 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:178707.7-178707.37" - process $proc$libresoc.v:178707$13375 + attribute \src "libresoc.v:183323.7-183323.37" + process $proc$libresoc.v:183323$13850 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:178711.14-178711.55" - process $proc$libresoc.v:178711$13376 + attribute \src "libresoc.v:183327.14-183327.55" + process $proc$libresoc.v:183327$13851 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:178715.7-178715.31" - process $proc$libresoc.v:178715$13377 + attribute \src "libresoc.v:183331.7-183331.31" + process $proc$libresoc.v:183331$13852 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:178719.7-178719.34" - process $proc$libresoc.v:178719$13378 + attribute \src "libresoc.v:183335.7-183335.34" + process $proc$libresoc.v:183335$13853 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:178723.7-178723.31" - process $proc$libresoc.v:178723$13379 + attribute \src "libresoc.v:183339.7-183339.31" + process $proc$libresoc.v:183339$13854 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:178727.7-178727.34" - process $proc$libresoc.v:178727$13380 + attribute \src "libresoc.v:183343.7-183343.34" + process $proc$libresoc.v:183343$13855 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:178731.14-178731.48" - process $proc$libresoc.v:178731$13381 + attribute \src "libresoc.v:183347.14-183347.48" + process $proc$libresoc.v:183347$13856 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:178735.13-178735.44" - process $proc$libresoc.v:178735$13382 + attribute \src "libresoc.v:183351.13-183351.44" + process $proc$libresoc.v:183351$13857 assign { } { } - assign $1\core_core_core_traptype[6:0] 7'0000000 + assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init - update \core_core_core_traptype $1\core_core_core_traptype[6:0] + update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:178739.13-178739.36" - process $proc$libresoc.v:178739$13383 + attribute \src "libresoc.v:183355.13-183355.36" + process $proc$libresoc.v:183355$13858 assign { } { } assign $1\core_core_cr_in1[2:0] 3'000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[2:0] end - attribute \src "libresoc.v:178743.7-178743.33" - process $proc$libresoc.v:178743$13384 + attribute \src "libresoc.v:183359.7-183359.33" + process $proc$libresoc.v:183359$13859 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:178747.13-178747.36" - process $proc$libresoc.v:178747$13385 + attribute \src "libresoc.v:183363.13-183363.36" + process $proc$libresoc.v:183363$13860 assign { } { } assign $1\core_core_cr_in2[2:0] 3'000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[2:0] end - attribute \src "libresoc.v:178749.13-178749.40" - process $proc$libresoc.v:178749$13386 + attribute \src "libresoc.v:183365.13-183365.40" + process $proc$libresoc.v:183365$13861 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$13387 3'000 + assign $0\core_core_cr_in2$1[2:0]$13862 3'000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13387 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13862 end - attribute \src "libresoc.v:178755.7-178755.33" - process $proc$libresoc.v:178755$13388 + attribute \src "libresoc.v:183371.7-183371.33" + process $proc$libresoc.v:183371$13863 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:178757.7-178757.37" - process $proc$libresoc.v:178757$13389 + attribute \src "libresoc.v:183373.7-183373.37" + process $proc$libresoc.v:183373$13864 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13390 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$13865 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13390 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13865 end - attribute \src "libresoc.v:178763.13-178763.36" - process $proc$libresoc.v:178763$13391 + attribute \src "libresoc.v:183379.13-183379.36" + process $proc$libresoc.v:183379$13866 assign { } { } assign $1\core_core_cr_out[2:0] 3'000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[2:0] end - attribute \src "libresoc.v:178767.7-178767.32" - process $proc$libresoc.v:178767$13392 + attribute \src "libresoc.v:183383.7-183383.32" + process $proc$libresoc.v:183383$13867 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:178771.13-178771.33" - process $proc$libresoc.v:178771$13393 + attribute \src "libresoc.v:183387.13-183387.33" + process $proc$libresoc.v:183387$13868 assign { } { } assign $1\core_core_ea[4:0] 5'00000 sync always sync init update \core_core_ea $1\core_core_ea[4:0] end - attribute \src "libresoc.v:178775.13-178775.35" - process $proc$libresoc.v:178775$13394 + attribute \src "libresoc.v:183391.13-183391.35" + process $proc$libresoc.v:183391$13869 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:178779.7-178779.32" - process $proc$libresoc.v:178779$13395 + attribute \src "libresoc.v:183395.7-183395.32" + process $proc$libresoc.v:183395$13870 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:178783.13-178783.35" - process $proc$libresoc.v:178783$13396 + attribute \src "libresoc.v:183399.13-183399.35" + process $proc$libresoc.v:183399$13871 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:178787.7-178787.32" - process $proc$libresoc.v:178787$13397 + attribute \src "libresoc.v:183403.7-183403.32" + process $proc$libresoc.v:183403$13872 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:178791.13-178791.36" - process $proc$libresoc.v:178791$13398 + attribute \src "libresoc.v:183407.13-183407.36" + process $proc$libresoc.v:183407$13873 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:178795.13-178795.36" - process $proc$libresoc.v:178795$13399 + attribute \src "libresoc.v:183411.13-183411.36" + process $proc$libresoc.v:183411$13874 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:178799.7-178799.26" - process $proc$libresoc.v:178799$13400 + attribute \src "libresoc.v:183415.7-183415.26" + process $proc$libresoc.v:183415$13875 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:178803.14-178803.49" - process $proc$libresoc.v:178803$13401 + attribute \src "libresoc.v:183419.14-183419.49" + process $proc$libresoc.v:183419$13876 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:178807.13-178807.35" - process $proc$libresoc.v:178807$13402 + attribute \src "libresoc.v:183423.13-183423.35" + process $proc$libresoc.v:183423$13877 assign { } { } assign $1\core_core_reg1[4:0] 5'00000 sync always sync init update \core_core_reg1 $1\core_core_reg1[4:0] end - attribute \src "libresoc.v:178811.7-178811.31" - process $proc$libresoc.v:178811$13403 + attribute \src "libresoc.v:183427.7-183427.31" + process $proc$libresoc.v:183427$13878 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:178815.13-178815.35" - process $proc$libresoc.v:178815$13404 + attribute \src "libresoc.v:183431.13-183431.35" + process $proc$libresoc.v:183431$13879 assign { } { } assign $1\core_core_reg2[4:0] 5'00000 sync always sync init update \core_core_reg2 $1\core_core_reg2[4:0] end - attribute \src "libresoc.v:178819.7-178819.31" - process $proc$libresoc.v:178819$13405 + attribute \src "libresoc.v:183435.7-183435.31" + process $proc$libresoc.v:183435$13880 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:178823.13-178823.35" - process $proc$libresoc.v:178823$13406 + attribute \src "libresoc.v:183439.13-183439.35" + process $proc$libresoc.v:183439$13881 assign { } { } assign $1\core_core_reg3[4:0] 5'00000 sync always sync init update \core_core_reg3 $1\core_core_reg3[4:0] end - attribute \src "libresoc.v:178827.7-178827.31" - process $proc$libresoc.v:178827$13407 + attribute \src "libresoc.v:183443.7-183443.31" + process $proc$libresoc.v:183443$13882 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:178831.13-178831.35" - process $proc$libresoc.v:178831$13408 + attribute \src "libresoc.v:183447.13-183447.35" + process $proc$libresoc.v:183447$13883 assign { } { } assign $1\core_core_rego[4:0] 5'00000 sync always sync init update \core_core_rego $1\core_core_rego[4:0] end - attribute \src "libresoc.v:178948.13-178948.37" - process $proc$libresoc.v:178948$13409 + attribute \src "libresoc.v:183562.13-183562.37" + process $proc$libresoc.v:183562$13884 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:178952.7-178952.31" - process $proc$libresoc.v:178952$13410 + attribute \src "libresoc.v:183566.7-183566.31" + process $proc$libresoc.v:183566$13885 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:179067.13-179067.37" - process $proc$libresoc.v:179067$13411 + attribute \src "libresoc.v:183681.13-183681.37" + process $proc$libresoc.v:183681$13886 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:179073.13-179073.36" - process $proc$libresoc.v:179073$13412 + attribute \src "libresoc.v:183687.13-183687.36" + process $proc$libresoc.v:183687$13887 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:179081.7-179081.28" - process $proc$libresoc.v:179081$13413 + attribute \src "libresoc.v:183695.7-183695.28" + process $proc$libresoc.v:183695$13888 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:179095.14-179095.45" - process $proc$libresoc.v:179095$13414 + attribute \src "libresoc.v:183709.14-183709.45" + process $proc$libresoc.v:183709$13889 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:179105.7-179105.24" - process $proc$libresoc.v:179105$13415 + attribute \src "libresoc.v:183719.7-183719.24" + process $proc$libresoc.v:183719$13890 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:179109.7-179109.23" - process $proc$libresoc.v:179109$13416 + attribute \src "libresoc.v:183723.7-183723.23" + process $proc$libresoc.v:183723$13891 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:179113.7-179113.28" - process $proc$libresoc.v:179113$13417 + attribute \src "libresoc.v:183727.7-183727.28" + process $proc$libresoc.v:183727$13892 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:179117.7-179117.28" - process $proc$libresoc.v:179117$13418 + attribute \src "libresoc.v:183731.7-183731.28" + process $proc$libresoc.v:183731$13893 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:179145.14-179145.45" - process $proc$libresoc.v:179145$13419 + attribute \src "libresoc.v:183759.14-183759.45" + process $proc$libresoc.v:183759$13894 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:179153.14-179153.37" - process $proc$libresoc.v:179153$13420 + attribute \src "libresoc.v:183767.14-183767.37" + process $proc$libresoc.v:183767$13895 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:179157.7-179157.26" - process $proc$libresoc.v:179157$13421 + attribute \src "libresoc.v:183771.7-183771.26" + process $proc$libresoc.v:183771$13896 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:179161.7-179161.26" - process $proc$libresoc.v:179161$13422 + attribute \src "libresoc.v:183775.7-183775.26" + process $proc$libresoc.v:183775$13897 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:179171.7-179171.26" - process $proc$libresoc.v:179171$13423 + attribute \src "libresoc.v:183787.7-183787.26" + process $proc$libresoc.v:183787$13898 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:179175.7-179175.30" - process $proc$libresoc.v:179175$13424 + attribute \src "libresoc.v:183793.7-183793.30" + process $proc$libresoc.v:183793$13899 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:179181.7-179181.24" - process $proc$libresoc.v:179181$13425 + attribute \src "libresoc.v:183799.7-183799.24" + process $proc$libresoc.v:183799$13900 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:179185.7-179185.25" - process $proc$libresoc.v:179185$13426 + attribute \src "libresoc.v:183803.7-183803.25" + process $proc$libresoc.v:183803$13901 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:179189.7-179189.25" - process $proc$libresoc.v:179189$13427 + attribute \src "libresoc.v:183807.7-183807.25" + process $proc$libresoc.v:183807$13902 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:179225.13-179225.34" - process $proc$libresoc.v:179225$13428 + attribute \src "libresoc.v:183843.13-183843.34" + process $proc$libresoc.v:183843$13903 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:179229.14-179229.48" - process $proc$libresoc.v:179229$13429 + attribute \src "libresoc.v:183847.14-183847.48" + process $proc$libresoc.v:183847$13904 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:179235.7-179235.27" - process $proc$libresoc.v:179235$13430 + attribute \src "libresoc.v:183853.7-183853.27" + process $proc$libresoc.v:183853$13905 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:179239.7-179239.26" - process $proc$libresoc.v:179239$13431 + attribute \src "libresoc.v:183857.7-183857.26" + process $proc$libresoc.v:183857$13906 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:179297.14-179297.49" - process $proc$libresoc.v:179297$13432 + attribute \src "libresoc.v:183911.14-183911.49" + process $proc$libresoc.v:183911$13907 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:179301.7-179301.27" - process $proc$libresoc.v:179301$13433 + attribute \src "libresoc.v:183915.7-183915.27" + process $proc$libresoc.v:183915$13908 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:179305.14-179305.49" - process $proc$libresoc.v:179305$13434 + attribute \src "libresoc.v:183919.14-183919.49" + process $proc$libresoc.v:183919$13909 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:179309.14-179309.48" - process $proc$libresoc.v:179309$13435 + attribute \src "libresoc.v:183923.14-183923.48" + process $proc$libresoc.v:183923$13910 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:179702.13-179702.25" - process $proc$libresoc.v:179702$13436 + attribute \src "libresoc.v:184332.13-184332.25" + process $proc$libresoc.v:184332$13911 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:179706.13-179706.29" - process $proc$libresoc.v:179706$13437 + attribute \src "libresoc.v:184348.13-184348.29" + process $proc$libresoc.v:184348$13912 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:179708.13-179708.35" - process $proc$libresoc.v:179708$13438 + attribute \src "libresoc.v:184350.13-184350.35" + process $proc$libresoc.v:184350$13913 assign { } { } - assign $0\fsm_state$117[1:0]$13439 2'00 + assign $0\fsm_state$133[1:0]$13914 2'00 sync always sync init - update \fsm_state$117 $0\fsm_state$117[1:0]$13439 + update \fsm_state$133 $0\fsm_state$133[1:0]$13914 end - attribute \src "libresoc.v:179972.14-179972.28" - process $proc$libresoc.v:179972$13440 + attribute \src "libresoc.v:184592.14-184592.28" + process $proc$libresoc.v:184592$13915 assign { } { } assign $1\ilatch[31:0] 0 sync always sync init update \ilatch $1\ilatch[31:0] end - attribute \src "libresoc.v:179988.7-179988.29" - process $proc$libresoc.v:179988$13441 + attribute \src "libresoc.v:184610.7-184610.30" + process $proc$libresoc.v:184610$13916 assign { } { } - assign $1\jtag_dmi0_ack_o[0:0] 1'0 + assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init - update \jtag_dmi0_ack_o $1\jtag_dmi0_ack_o[0:0] + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:179996.14-179996.51" - process $proc$libresoc.v:179996$13442 + attribute \src "libresoc.v:184618.14-184618.52" + process $proc$libresoc.v:184618$13917 assign { } { } - assign $1\jtag_dmi0_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \jtag_dmi0_dout $1\jtag_dmi0_dout[63:0] + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:180024.7-180024.22" - process $proc$libresoc.v:180024$13443 + attribute \src "libresoc.v:184674.7-184674.22" + process $proc$libresoc.v:184674$13918 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:180036.7-180036.24" - process $proc$libresoc.v:180036$13444 + attribute \src "libresoc.v:184702.7-184702.24" + process $proc$libresoc.v:184702$13919 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:180046.7-180046.25" - process $proc$libresoc.v:180046$13445 + attribute \src "libresoc.v:184712.7-184712.25" + process $proc$libresoc.v:184712$13920 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:180127.3-180128.41" - process $proc$libresoc.v:180127$12919 + attribute \src "libresoc.v:185152.3-185153.39" + process $proc$libresoc.v:185152$13322 assign { } { } - assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk - update \dec2_cur_dec $0\dec2_cur_dec[63:0] + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:185154.3-185155.29" + process $proc$libresoc.v:185154$13323 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:185156.3-185157.41" + process $proc$libresoc.v:185156$13324 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:185158.3-185159.33" + process $proc$libresoc.v:185158$13325 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:185160.3-185161.35" + process $proc$libresoc.v:185160$13326 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:180129.3-180130.33" - process $proc$libresoc.v:180129$12920 + attribute \src "libresoc.v:185162.3-185163.33" + process $proc$libresoc.v:185162$13327 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:180131.3-180132.41" - process $proc$libresoc.v:180131$12921 + attribute \src "libresoc.v:185164.3-185165.41" + process $proc$libresoc.v:185164$13328 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:180133.3-180134.35" - process $proc$libresoc.v:180133$12922 + attribute \src "libresoc.v:185166.3-185167.35" + process $proc$libresoc.v:185166$13329 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:180135.3-180136.33" - process $proc$libresoc.v:180135$12923 + attribute \src "libresoc.v:185168.3-185169.33" + process $proc$libresoc.v:185168$13330 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:180137.3-180138.39" - process $proc$libresoc.v:180137$12924 + attribute \src "libresoc.v:185170.3-185171.39" + process $proc$libresoc.v:185170$13331 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:180139.3-180140.55" - process $proc$libresoc.v:180139$12925 + attribute \src "libresoc.v:185172.3-185173.57" + process $proc$libresoc.v:185172$13332 assign { } { } - assign $0\core_bigendian_i$3[0:0]$12926 \core_bigendian_i$3$next + assign $0\core_bigendian_i$10[0:0]$13333 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12926 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13333 end - attribute \src "libresoc.v:180141.3-180142.47" - process $proc$libresoc.v:180141$12927 + attribute \src "libresoc.v:185174.3-185175.47" + process $proc$libresoc.v:185174$13334 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:180143.3-180144.41" - process $proc$libresoc.v:180143$12928 + attribute \src "libresoc.v:185176.3-185177.41" + process $proc$libresoc.v:185176$13335 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:180145.3-180146.45" - process $proc$libresoc.v:180145$12929 + attribute \src "libresoc.v:185178.3-185179.45" + process $proc$libresoc.v:185178$13336 assign { } { } assign $0\core_core_rego[4:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[4:0] end - attribute \src "libresoc.v:180147.3-180148.41" - process $proc$libresoc.v:180147$12930 + attribute \src "libresoc.v:185180.3-185181.41" + process $proc$libresoc.v:185180$13337 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:180149.3-180150.45" - process $proc$libresoc.v:180149$12931 - assign { } { } - assign $0\fsm_state$117[1:0]$12932 \fsm_state$117$next - sync posedge \clk - update \fsm_state$117 $0\fsm_state$117[1:0]$12932 - end - attribute \src "libresoc.v:180151.3-180152.41" - process $proc$libresoc.v:180151$12933 + attribute \src "libresoc.v:185182.3-185183.41" + process $proc$libresoc.v:185182$13338 assign { } { } assign $0\core_core_ea[4:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[4:0] end - attribute \src "libresoc.v:180153.3-180154.37" - process $proc$libresoc.v:180153$12934 + attribute \src "libresoc.v:185184.3-185185.37" + process $proc$libresoc.v:185184$13339 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:180155.3-180156.45" - process $proc$libresoc.v:180155$12935 + attribute \src "libresoc.v:185186.3-185187.45" + process $proc$libresoc.v:185186$13340 assign { } { } assign $0\core_core_reg1[4:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[4:0] end - attribute \src "libresoc.v:180157.3-180158.51" - process $proc$libresoc.v:180157$12936 + attribute \src "libresoc.v:185188.3-185189.51" + process $proc$libresoc.v:185188$13341 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:180159.3-180160.45" - process $proc$libresoc.v:180159$12937 + attribute \src "libresoc.v:185190.3-185191.45" + process $proc$libresoc.v:185190$13342 assign { } { } assign $0\core_core_reg2[4:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[4:0] end - attribute \src "libresoc.v:180161.3-180162.51" - process $proc$libresoc.v:180161$12938 + attribute \src "libresoc.v:185192.3-185193.51" + process $proc$libresoc.v:185192$13343 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:180163.3-180164.45" - process $proc$libresoc.v:180163$12939 + attribute \src "libresoc.v:185194.3-185195.45" + process $proc$libresoc.v:185194$13344 assign { } { } assign $0\core_core_reg3[4:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[4:0] end - attribute \src "libresoc.v:180165.3-180166.51" - process $proc$libresoc.v:180165$12940 + attribute \src "libresoc.v:185196.3-185197.51" + process $proc$libresoc.v:185196$13345 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:180167.3-180168.45" - process $proc$libresoc.v:180167$12941 + attribute \src "libresoc.v:185198.3-185199.45" + process $proc$libresoc.v:185198$13346 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:180169.3-180170.41" - process $proc$libresoc.v:180169$12942 + attribute \src "libresoc.v:185200.3-185201.41" + process $proc$libresoc.v:185200$13347 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:180171.3-180172.39" - process $proc$libresoc.v:180171$12943 - assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] - end - attribute \src "libresoc.v:180173.3-180174.45" - process $proc$libresoc.v:180173$12944 + attribute \src "libresoc.v:185202.3-185203.45" + process $proc$libresoc.v:185202$13348 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:180175.3-180176.51" - process $proc$libresoc.v:180175$12945 + attribute \src "libresoc.v:185204.3-185205.51" + process $proc$libresoc.v:185204$13349 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:180177.3-180178.49" - process $proc$libresoc.v:180177$12946 + attribute \src "libresoc.v:185206.3-185207.49" + process $proc$libresoc.v:185206$13350 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:180179.3-180180.41" - process $proc$libresoc.v:180179$12947 + attribute \src "libresoc.v:185208.3-185209.41" + process $proc$libresoc.v:185208$13351 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:180181.3-180182.47" - process $proc$libresoc.v:180181$12948 + attribute \src "libresoc.v:185210.3-185211.47" + process $proc$libresoc.v:185210$13352 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:180183.3-180184.53" - process $proc$libresoc.v:180183$12949 + attribute \src "libresoc.v:185212.3-185213.53" + process $proc$libresoc.v:185212$13353 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:180185.3-180186.47" - process $proc$libresoc.v:180185$12950 + attribute \src "libresoc.v:185214.3-185215.47" + process $proc$libresoc.v:185214$13354 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:180187.3-180188.53" - process $proc$libresoc.v:180187$12951 + attribute \src "libresoc.v:185216.3-185217.53" + process $proc$libresoc.v:185216$13355 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:180189.3-180190.49" - process $proc$libresoc.v:180189$12952 + attribute \src "libresoc.v:185218.3-185219.49" + process $proc$libresoc.v:185218$13356 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:180191.3-180192.45" - process $proc$libresoc.v:180191$12953 + attribute \src "libresoc.v:185220.3-185221.45" + process $proc$libresoc.v:185220$13357 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:180193.3-180194.37" - process $proc$libresoc.v:180193$12954 - assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] - end - attribute \src "libresoc.v:180195.3-180196.49" - process $proc$libresoc.v:180195$12955 + attribute \src "libresoc.v:185222.3-185223.49" + process $proc$libresoc.v:185222$13358 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:180197.3-180198.45" - process $proc$libresoc.v:180197$12956 + attribute \src "libresoc.v:185224.3-185225.45" + process $proc$libresoc.v:185224$13359 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:180199.3-180200.49" - process $proc$libresoc.v:180199$12957 + attribute \src "libresoc.v:185226.3-185227.49" + process $proc$libresoc.v:185226$13360 assign { } { } assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[2:0] end - attribute \src "libresoc.v:180201.3-180202.55" - process $proc$libresoc.v:180201$12958 + attribute \src "libresoc.v:185228.3-185229.55" + process $proc$libresoc.v:185228$13361 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:180203.3-180204.49" - process $proc$libresoc.v:180203$12959 + attribute \src "libresoc.v:185230.3-185231.49" + process $proc$libresoc.v:185230$13362 assign { } { } assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[2:0] end - attribute \src "libresoc.v:180205.3-180206.55" - process $proc$libresoc.v:180205$12960 + attribute \src "libresoc.v:185232.3-185233.55" + process $proc$libresoc.v:185232$13363 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:180207.3-180208.55" - process $proc$libresoc.v:180207$12961 + attribute \src "libresoc.v:185234.3-185235.55" + process $proc$libresoc.v:185234$13364 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$12962 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[2:0]$13365 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12962 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13365 end - attribute \src "libresoc.v:180209.3-180210.61" - process $proc$libresoc.v:180209$12963 + attribute \src "libresoc.v:185236.3-185237.61" + process $proc$libresoc.v:185236$13366 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$12964 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13367 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12964 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13367 end - attribute \src "libresoc.v:180211.3-180212.49" - process $proc$libresoc.v:180211$12965 + attribute \src "libresoc.v:185238.3-185239.49" + process $proc$libresoc.v:185238$13368 assign { } { } assign $0\core_core_cr_out[2:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[2:0] end - attribute \src "libresoc.v:180213.3-180214.45" - process $proc$libresoc.v:180213$12966 + attribute \src "libresoc.v:185240.3-185241.45" + process $proc$libresoc.v:185240$13369 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:180215.3-180216.39" - process $proc$libresoc.v:180215$12967 - assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next - sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] - end - attribute \src "libresoc.v:180217.3-180218.53" - process $proc$libresoc.v:180217$12968 + attribute \src "libresoc.v:185242.3-185243.53" + process $proc$libresoc.v:185242$13370 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:180219.3-180220.53" - process $proc$libresoc.v:180219$12969 + attribute \src "libresoc.v:185244.3-185245.53" + process $proc$libresoc.v:185244$13371 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:180221.3-180222.55" - process $proc$libresoc.v:180221$12970 + attribute \src "libresoc.v:185246.3-185247.55" + process $proc$libresoc.v:185246$13372 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:180223.3-180224.65" - process $proc$libresoc.v:180223$12971 + attribute \src "libresoc.v:185248.3-185249.65" + process $proc$libresoc.v:185248$13373 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:180225.3-180226.61" - process $proc$libresoc.v:180225$12972 + attribute \src "libresoc.v:185250.3-185251.61" + process $proc$libresoc.v:185250$13374 assign { } { } assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] end - attribute \src "libresoc.v:180227.3-180228.41" - process $proc$libresoc.v:180227$12973 + attribute \src "libresoc.v:185252.3-185253.41" + process $proc$libresoc.v:185252$13375 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:185254.3-185255.41" + process $proc$libresoc.v:185254$13376 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:180229.3-180230.51" - process $proc$libresoc.v:180229$12974 + attribute \src "libresoc.v:185256.3-185257.51" + process $proc$libresoc.v:185256$13377 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:180231.3-180232.57" - process $proc$libresoc.v:180231$12975 + attribute \src "libresoc.v:185258.3-185259.57" + process $proc$libresoc.v:185258$13378 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:180233.3-180234.51" - process $proc$libresoc.v:180233$12976 + attribute \src "libresoc.v:185260.3-185261.51" + process $proc$libresoc.v:185260$13379 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:180235.3-180236.57" - process $proc$libresoc.v:180235$12977 + attribute \src "libresoc.v:185262.3-185263.57" + process $proc$libresoc.v:185262$13380 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:180237.3-180238.29" - process $proc$libresoc.v:180237$12978 + attribute \src "libresoc.v:185264.3-185265.69" + process $proc$libresoc.v:185264$13381 assign { } { } - assign $0\ilatch[31:0] \ilatch$next + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk - update \ilatch $0\ilatch[31:0] + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:180239.3-180240.69" - process $proc$libresoc.v:180239$12979 + attribute \src "libresoc.v:185266.3-185267.63" + process $proc$libresoc.v:185266$13382 assign { } { } - assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk - update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + update \core_core_core_traptype $0\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:185268.3-185269.71" + process $proc$libresoc.v:185268$13383 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13384 \core_core_core_exc_$signal$next + sync posedge \clk + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13384 + end + attribute \src "libresoc.v:185270.3-185271.75" + process $proc$libresoc.v:185270$13385 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13386 \core_core_core_exc_$signal$3$next + sync posedge \clk + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13386 + end + attribute \src "libresoc.v:185272.3-185273.75" + process $proc$libresoc.v:185272$13387 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13388 \core_core_core_exc_$signal$4$next + sync posedge \clk + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13388 + end + attribute \src "libresoc.v:185274.3-185275.45" + process $proc$libresoc.v:185274$13389 + assign { } { } + assign $0\fsm_state$133[1:0]$13390 \fsm_state$133$next + sync posedge \clk + update \fsm_state$133 $0\fsm_state$133[1:0]$13390 + end + attribute \src "libresoc.v:185276.3-185277.75" + process $proc$libresoc.v:185276$13391 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13392 \core_core_core_exc_$signal$5$next + sync posedge \clk + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13392 + end + attribute \src "libresoc.v:185278.3-185279.75" + process $proc$libresoc.v:185278$13393 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13394 \core_core_core_exc_$signal$6$next + sync posedge \clk + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13394 end - attribute \src "libresoc.v:180241.3-180242.63" - process $proc$libresoc.v:180241$12980 + attribute \src "libresoc.v:185280.3-185281.75" + process $proc$libresoc.v:185280$13395 assign { } { } - assign $0\core_core_core_traptype[6:0] \core_core_core_traptype$next + assign $0\core_core_core_exc_$signal$7[0:0]$13396 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_traptype $0\core_core_core_traptype[6:0] + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13396 end - attribute \src "libresoc.v:180243.3-180244.63" - process $proc$libresoc.v:180243$12981 + attribute \src "libresoc.v:185282.3-185283.75" + process $proc$libresoc.v:185282$13397 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13398 \core_core_core_exc_$signal$8$next + sync posedge \clk + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13398 + end + attribute \src "libresoc.v:185284.3-185285.75" + process $proc$libresoc.v:185284$13399 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13400 \core_core_core_exc_$signal$9$next + sync posedge \clk + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13400 + end + attribute \src "libresoc.v:185286.3-185287.63" + process $proc$libresoc.v:185286$13401 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:180245.3-180246.57" - process $proc$libresoc.v:180245$12982 + attribute \src "libresoc.v:185288.3-185289.57" + process $proc$libresoc.v:185288$13402 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:180247.3-180248.63" - process $proc$libresoc.v:180247$12983 + attribute \src "libresoc.v:185290.3-185291.63" + process $proc$libresoc.v:185290$13403 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:180249.3-180250.57" - process $proc$libresoc.v:180249$12984 + attribute \src "libresoc.v:185292.3-185293.57" + process $proc$libresoc.v:185292$13404 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:180251.3-180252.53" - process $proc$libresoc.v:180251$12985 + attribute \src "libresoc.v:185294.3-185295.53" + process $proc$libresoc.v:185294$13405 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:180253.3-180254.63" - process $proc$libresoc.v:180253$12986 + attribute \src "libresoc.v:185296.3-185297.39" + process $proc$libresoc.v:185296$13406 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:185298.3-185299.63" + process $proc$libresoc.v:185298$13407 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:180255.3-180256.37" - process $proc$libresoc.v:180255$12987 + attribute \src "libresoc.v:185300.3-185301.37" + process $proc$libresoc.v:185300$13408 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:180257.3-180258.39" - process $proc$libresoc.v:180257$12988 + attribute \src "libresoc.v:185302.3-185303.39" + process $proc$libresoc.v:185302$13409 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:180259.3-180260.41" - process $proc$libresoc.v:180259$12989 - assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next - sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] - end - attribute \src "libresoc.v:180261.3-180262.43" - process $proc$libresoc.v:180261$12990 + attribute \src "libresoc.v:185304.3-185305.43" + process $proc$libresoc.v:185304$13410 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:180263.3-180264.27" - process $proc$libresoc.v:180263$12991 + attribute \src "libresoc.v:185306.3-185307.27" + process $proc$libresoc.v:185306$13411 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:180265.3-180266.43" - process $proc$libresoc.v:180265$12992 + attribute \src "libresoc.v:185308.3-185309.43" + process $proc$libresoc.v:185308$13412 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:180267.3-180268.45" - process $proc$libresoc.v:180267$12993 + attribute \src "libresoc.v:185310.3-185311.47" + process $proc$libresoc.v:185310$13413 assign { } { } - assign $0\jtag_dmi0_dout[63:0] \jtag_dmi0_dout$next + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk - update \jtag_dmi0_dout $0\jtag_dmi0_dout[63:0] + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:180269.3-180270.47" - process $proc$libresoc.v:180269$12994 + attribute \src "libresoc.v:185312.3-185313.49" + process $proc$libresoc.v:185312$13414 assign { } { } - assign $0\jtag_dmi0_ack_o[0:0] \jtag_dmi0_ack_o$next + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk - update \jtag_dmi0_ack_o $0\jtag_dmi0_ack_o[0:0] + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:180271.3-180272.39" - process $proc$libresoc.v:180271$12995 + attribute \src "libresoc.v:185314.3-185315.39" + process $proc$libresoc.v:185314$13415 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:180273.3-180274.41" - process $proc$libresoc.v:180273$12996 + attribute \src "libresoc.v:185316.3-185317.41" + process $proc$libresoc.v:185316$13416 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:180275.3-180276.43" - process $proc$libresoc.v:180275$12997 + attribute \src "libresoc.v:185318.3-185319.37" + process $proc$libresoc.v:185318$13417 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:185320.3-185321.43" + process $proc$libresoc.v:185320$13418 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:180277.3-180278.45" - process $proc$libresoc.v:180277$12998 + attribute \src "libresoc.v:185322.3-185323.45" + process $proc$libresoc.v:185322$13419 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:180279.3-180280.33" - process $proc$libresoc.v:180279$12999 + attribute \src "libresoc.v:185889.3-185897.6" + process $proc$libresoc.v:185889$13420 assign { } { } - assign $0\core_msr[63:0] \core_msr$next - sync posedge \clk - update \core_msr $0\core_msr[63:0] + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13421 $1\dbg_dmi_addr_i$next[3:0]$13422 + attribute \src "libresoc.v:185890.5-185890.29" + switch \initial + attribute \src "libresoc.v:185890.9-185890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13422 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13422 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13421 end - attribute \src "libresoc.v:180281.3-180282.35" - process $proc$libresoc.v:180281$13000 + attribute \src "libresoc.v:185898.3-185906.6" + process $proc$libresoc.v:185898$13423 assign { } { } - assign $0\core_eint[0:0] \core_eint$next - sync posedge \clk - update \core_eint $0\core_eint[0:0] + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$13424 $1\dbg_dmi_req_i$next[0:0]$13425 + attribute \src "libresoc.v:185899.5-185899.29" + switch \initial + attribute \src "libresoc.v:185899.9-185899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$13425 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$13425 \jtag_dmi0__req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13424 end - attribute \src "libresoc.v:180620.3-180628.6" - process $proc$libresoc.v:180620$13001 + attribute \src "libresoc.v:185907.3-185927.6" + process $proc$libresoc.v:185907$13426 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13002 $1\dbg_dmi_addr_i$next[3:0]$13003 - attribute \src "libresoc.v:180621.5-180621.29" + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$13427 $3\dec2_cur_msr$next[63:0]$13430 + attribute \src "libresoc.v:185908.5-185908.29" switch \initial - attribute \src "libresoc.v:180621.9-180621.17" + attribute \src "libresoc.v:185908.9-185908.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$13428 $2\dec2_cur_msr$next[63:0]$13429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13429 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13429 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$13428 \dec2_cur_msr + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13003 4'0000 + assign $3\dec2_cur_msr$next[63:0]$13430 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13003 \jtag_dmi0_addr_i + assign $3\dec2_cur_msr$next[63:0]$13430 $1\dec2_cur_msr$next[63:0]$13428 end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13002 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13427 end - attribute \src "libresoc.v:180629.3-180637.6" - process $proc$libresoc.v:180629$13004 + attribute \src "libresoc.v:185928.3-185946.6" + process $proc$libresoc.v:185928$13431 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13005 $1\dbg_dmi_req_i$next[0:0]$13006 - attribute \src "libresoc.v:180630.5-180630.29" + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:185929.5-185929.29" switch \initial - attribute \src "libresoc.v:180630.9-180630.17" + attribute \src "libresoc.v:185929.9-185929.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$119 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:185947.3-185978.6" + process $proc$libresoc.v:185947$13432 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_pc$next[63:0]$13433 $3\core_core_pc$next[63:0]$13445 + assign $0\core_dec$next[63:0]$13434 $3\core_dec$next[63:0]$13446 + assign $0\core_eint$next[0:0]$13435 $3\core_eint$next[0:0]$13447 + assign $0\core_msr$next[63:0]$13436 $3\core_msr$next[63:0]$13448 + attribute \src "libresoc.v:185948.5-185948.29" + switch \initial + attribute \src "libresoc.v:185948.9-185948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_pc$next[63:0]$13437 $2\core_core_pc$next[63:0]$13441 + assign $1\core_dec$next[63:0]$13438 $2\core_dec$next[63:0]$13442 + assign $1\core_eint$next[0:0]$13439 $2\core_eint$next[0:0]$13443 + assign $1\core_msr$next[63:0]$13440 $2\core_msr$next[63:0]$13444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_core_pc$next[63:0]$13441 \core_core_pc + assign $2\core_dec$next[63:0]$13442 \core_dec + assign $2\core_eint$next[0:0]$13443 \core_eint + assign $2\core_msr$next[63:0]$13444 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$13442 $2\core_eint$next[0:0]$13443 $2\core_msr$next[63:0]$13444 $2\core_core_pc$next[63:0]$13441 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_core_pc$next[63:0]$13437 \core_core_pc + assign $1\core_dec$next[63:0]$13438 \core_dec + assign $1\core_eint$next[0:0]$13439 \core_eint + assign $1\core_msr$next[63:0]$13440 \core_msr + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13006 1'0 + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$13445 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13448 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13447 1'0 + assign $3\core_dec$next[63:0]$13446 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_core_pc$next[63:0]$13445 $1\core_core_pc$next[63:0]$13437 + assign $3\core_dec$next[63:0]$13446 $1\core_dec$next[63:0]$13438 + assign $3\core_eint$next[0:0]$13447 $1\core_eint$next[0:0]$13439 + assign $3\core_msr$next[63:0]$13448 $1\core_msr$next[63:0]$13440 + end + sync always + update \core_core_pc$next $0\core_core_pc$next[63:0]$13433 + update \core_dec$next $0\core_dec$next[63:0]$13434 + update \core_eint$next $0\core_eint$next[0:0]$13435 + update \core_msr$next $0\core_msr$next[63:0]$13436 + end + attribute \src "libresoc.v:185979.3-186002.6" + process $proc$libresoc.v:185979$13449 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$13450 $3\ilatch$next[31:0]$13453 + attribute \src "libresoc.v:185980.5-185980.29" + switch \initial + attribute \src "libresoc.v:185980.9-185980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$13451 $2\ilatch$next[31:0]$13452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$13452 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$13452 \$123 + end + case + assign $1\ilatch$next[31:0]$13451 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$13453 0 + case + assign $3\ilatch$next[31:0]$13453 $1\ilatch$next[31:0]$13451 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$13450 + end + attribute \src "libresoc.v:186003.3-186022.6" + process $proc$libresoc.v:186003$13454 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:186004.5-186004.29" + switch \initial + attribute \src "libresoc.v:186004.9-186004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end case - assign $1\dbg_dmi_req_i$next[0:0]$13006 \jtag_dmi0_req_i + assign $1\core_ivalid_i[0:0] 1'0 end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13005 + update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:180638.3-180648.6" - process $proc$libresoc.v:180638$13007 + attribute \src "libresoc.v:186023.3-186033.6" + process $proc$libresoc.v:186023$13455 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:180639.5-180639.29" + attribute \src "libresoc.v:186024.5-186024.29" switch \initial - attribute \src "libresoc.v:180639.9-180639.17" + attribute \src "libresoc.v:186024.9-186024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -379106,18 +389377,18 @@ module \test_issuer sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:180649.3-180658.6" - process $proc$libresoc.v:180649$13008 + attribute \src "libresoc.v:186034.3-186043.6" + process $proc$libresoc.v:186034$13456 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:180650.5-180650.29" + attribute \src "libresoc.v:186035.5-186035.29" switch \initial - attribute \src "libresoc.v:180650.9-180650.17" + attribute \src "libresoc.v:186035.9-186035.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379129,18 +389400,18 @@ module \test_issuer sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:180659.3-180668.6" - process $proc$libresoc.v:180659$13009 + attribute \src "libresoc.v:186044.3-186053.6" + process $proc$libresoc.v:186044$13457 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:180660.5-180660.29" + attribute \src "libresoc.v:186045.5-186045.29" switch \initial - attribute \src "libresoc.v:180660.9-180660.17" + attribute \src "libresoc.v:186045.9-186045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379152,14 +389423,14 @@ module \test_issuer sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:180669.3-180677.6" - process $proc$libresoc.v:180669$13010 + attribute \src "libresoc.v:186054.3-186062.6" + process $proc$libresoc.v:186054$13458 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13011 $1\d_reg_delay$next[0:0]$13012 - attribute \src "libresoc.v:180670.5-180670.29" + assign $0\d_reg_delay$next[0:0]$13459 $1\d_reg_delay$next[0:0]$13460 + attribute \src "libresoc.v:186055.5-186055.29" switch \initial - attribute \src "libresoc.v:180670.9-180670.17" + attribute \src "libresoc.v:186055.9-186055.17" case 1'1 case end @@ -379168,25 +389439,25 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13012 1'0 + assign $1\d_reg_delay$next[0:0]$13460 1'0 case - assign $1\d_reg_delay$next[0:0]$13012 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13460 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13011 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13459 end - attribute \src "libresoc.v:180678.3-180687.6" - process $proc$libresoc.v:180678$13013 + attribute \src "libresoc.v:186063.3-186072.6" + process $proc$libresoc.v:186063$13461 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:180679.5-180679.29" + attribute \src "libresoc.v:186064.5-186064.29" switch \initial - attribute \src "libresoc.v:180679.9-180679.17" + attribute \src "libresoc.v:186064.9-186064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:334" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379198,18 +389469,18 @@ module \test_issuer sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:180688.3-180697.6" - process $proc$libresoc.v:180688$13014 + attribute \src "libresoc.v:186073.3-186082.6" + process $proc$libresoc.v:186073$13462 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:180689.5-180689.29" + attribute \src "libresoc.v:186074.5-186074.29" switch \initial - attribute \src "libresoc.v:180689.9-180689.17" + attribute \src "libresoc.v:186074.9-186074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:334" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379221,18 +389492,18 @@ module \test_issuer sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:180698.3-180707.6" - process $proc$libresoc.v:180698$13015 + attribute \src "libresoc.v:186083.3-186092.6" + process $proc$libresoc.v:186083$13463 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:180699.5-180699.29" + attribute \src "libresoc.v:186084.5-186084.29" switch \initial - attribute \src "libresoc.v:180699.9-180699.17" + attribute \src "libresoc.v:186084.9-186084.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379244,14 +389515,14 @@ module \test_issuer sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:180708.3-180716.6" - process $proc$libresoc.v:180708$13016 + attribute \src "libresoc.v:186093.3-186101.6" + process $proc$libresoc.v:186093$13464 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13017 $1\d_cr_delay$next[0:0]$13018 - attribute \src "libresoc.v:180709.5-180709.29" + assign $0\d_cr_delay$next[0:0]$13465 $1\d_cr_delay$next[0:0]$13466 + attribute \src "libresoc.v:186094.5-186094.29" switch \initial - attribute \src "libresoc.v:180709.9-180709.17" + attribute \src "libresoc.v:186094.9-186094.17" case 1'1 case end @@ -379260,48 +389531,48 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13018 1'0 + assign $1\d_cr_delay$next[0:0]$13466 1'0 case - assign $1\d_cr_delay$next[0:0]$13018 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13466 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13017 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13465 end - attribute \src "libresoc.v:180717.3-180726.6" - process $proc$libresoc.v:180717$13019 + attribute \src "libresoc.v:186102.3-186111.6" + process $proc$libresoc.v:186102$13467 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:180718.5-180718.29" + attribute \src "libresoc.v:186103.5-186103.29" switch \initial - attribute \src "libresoc.v:180718.9-180718.17" + attribute \src "libresoc.v:186103.9-186103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$113 + assign $1\dbg_d_cr_data[63:0] \$129 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:180727.3-180736.6" - process $proc$libresoc.v:180727$13020 + attribute \src "libresoc.v:186112.3-186121.6" + process $proc$libresoc.v:186112$13468 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:180728.5-180728.29" + attribute \src "libresoc.v:186113.5-186113.29" switch \initial - attribute \src "libresoc.v:180728.9-180728.17" + attribute \src "libresoc.v:186113.9-186113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379313,18 +389584,18 @@ module \test_issuer sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:180737.3-180746.6" - process $proc$libresoc.v:180737$13021 + attribute \src "libresoc.v:186122.3-186131.6" + process $proc$libresoc.v:186122$13469 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:180738.5-180738.29" + attribute \src "libresoc.v:186123.5-186123.29" switch \initial - attribute \src "libresoc.v:180738.9-180738.17" + attribute \src "libresoc.v:186123.9-186123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:331" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379336,14 +389607,14 @@ module \test_issuer sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:180747.3-180755.6" - process $proc$libresoc.v:180747$13022 + attribute \src "libresoc.v:186132.3-186140.6" + process $proc$libresoc.v:186132$13470 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13023 $1\d_xer_delay$next[0:0]$13024 - attribute \src "libresoc.v:180748.5-180748.29" + assign $0\d_xer_delay$next[0:0]$13471 $1\d_xer_delay$next[0:0]$13472 + attribute \src "libresoc.v:186133.5-186133.29" switch \initial - attribute \src "libresoc.v:180748.9-180748.17" + attribute \src "libresoc.v:186133.9-186133.17" case 1'1 case end @@ -379352,48 +389623,48 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13024 1'0 + assign $1\d_xer_delay$next[0:0]$13472 1'0 case - assign $1\d_xer_delay$next[0:0]$13024 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13472 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13023 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13471 end - attribute \src "libresoc.v:180756.3-180765.6" - process $proc$libresoc.v:180756$13025 + attribute \src "libresoc.v:186141.3-186150.6" + process $proc$libresoc.v:186141$13473 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:180757.5-180757.29" + attribute \src "libresoc.v:186142.5-186142.29" switch \initial - attribute \src "libresoc.v:180757.9-180757.17" + attribute \src "libresoc.v:186142.9-186142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$115 + assign $1\dbg_d_xer_data[63:0] \$131 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:180766.3-180775.6" - process $proc$libresoc.v:180766$13026 + attribute \src "libresoc.v:186151.3-186160.6" + process $proc$libresoc.v:186151$13474 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:180767.5-180767.29" + attribute \src "libresoc.v:186152.5-186152.29" switch \initial - attribute \src "libresoc.v:180767.9-180767.17" + attribute \src "libresoc.v:186152.9-186152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379405,19 +389676,19 @@ module \test_issuer sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:180776.3-180790.6" - process $proc$libresoc.v:180776$13027 + attribute \src "libresoc.v:186161.3-186175.6" + process $proc$libresoc.v:186161$13475 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:180777.5-180777.29" + attribute \src "libresoc.v:186162.5-186162.29" switch \initial - attribute \src "libresoc.v:180777.9-180777.17" + attribute \src "libresoc.v:186162.9-186162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } @@ -379432,19 +389703,19 @@ module \test_issuer sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:180791.3-180805.6" - process $proc$libresoc.v:180791$13028 + attribute \src "libresoc.v:186176.3-186190.6" + process $proc$libresoc.v:186176$13476 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:180792.5-180792.29" + attribute \src "libresoc.v:186177.5-186177.29" switch \initial - attribute \src "libresoc.v:180792.9-180792.17" + attribute \src "libresoc.v:186177.9-186177.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } @@ -379459,114 +389730,114 @@ module \test_issuer sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:180806.3-180833.6" - process $proc$libresoc.v:180806$13029 + attribute \src "libresoc.v:186191.3-186218.6" + process $proc$libresoc.v:186191$13477 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$117$next[1:0]$13030 $2\fsm_state$117$next[1:0]$13032 - attribute \src "libresoc.v:180807.5-180807.29" + assign $0\fsm_state$133$next[1:0]$13478 $2\fsm_state$133$next[1:0]$13480 + attribute \src "libresoc.v:186192.5-186192.29" switch \initial - attribute \src "libresoc.v:180807.9-180807.17" + attribute \src "libresoc.v:186192.9-186192.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$117$next[1:0]$13031 2'01 + assign $1\fsm_state$133$next[1:0]$13479 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$117$next[1:0]$13031 2'10 + assign $1\fsm_state$133$next[1:0]$13479 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$117$next[1:0]$13031 2'11 + assign $1\fsm_state$133$next[1:0]$13479 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$117$next[1:0]$13031 2'00 + assign $1\fsm_state$133$next[1:0]$13479 2'00 case - assign $1\fsm_state$117$next[1:0]$13031 \fsm_state$117 + assign $1\fsm_state$133$next[1:0]$13479 \fsm_state$133 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$117$next[1:0]$13032 2'00 + assign $2\fsm_state$133$next[1:0]$13480 2'00 case - assign $2\fsm_state$117$next[1:0]$13032 $1\fsm_state$117$next[1:0]$13031 + assign $2\fsm_state$133$next[1:0]$13480 $1\fsm_state$133$next[1:0]$13479 end sync always - update \fsm_state$117$next $0\fsm_state$117$next[1:0]$13030 + update \fsm_state$133$next $0\fsm_state$133$next[1:0]$13478 end - attribute \src "libresoc.v:180834.3-180844.6" - process $proc$libresoc.v:180834$13033 + attribute \src "libresoc.v:186219.3-186229.6" + process $proc$libresoc.v:186219$13481 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:180835.5-180835.29" + attribute \src "libresoc.v:186220.5-186220.29" switch \initial - attribute \src "libresoc.v:180835.9-180835.17" + attribute \src "libresoc.v:186220.9-186220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$118 [63:0] + assign $1\new_dec[63:0] \$134 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:180845.3-180859.6" - process $proc$libresoc.v:180845$13034 + attribute \src "libresoc.v:186230.3-186244.6" + process $proc$libresoc.v:186230$13482 assign { } { } assign { } { } - assign $0\core_issue__addr$4[2:0]$13035 $1\core_issue__addr$4[2:0]$13036 - attribute \src "libresoc.v:180846.5-180846.29" + assign $0\core_issue__addr$11[2:0]$13483 $1\core_issue__addr$11[2:0]$13484 + attribute \src "libresoc.v:186231.5-186231.29" switch \initial - attribute \src "libresoc.v:180846.9-180846.17" + attribute \src "libresoc.v:186231.9-186231.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$4[2:0]$13036 3'110 + assign $1\core_issue__addr$11[2:0]$13484 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$4[2:0]$13036 3'111 + assign $1\core_issue__addr$11[2:0]$13484 3'111 case - assign $1\core_issue__addr$4[2:0]$13036 3'000 + assign $1\core_issue__addr$11[2:0]$13484 3'000 end sync always - update \core_issue__addr$4 $0\core_issue__addr$4[2:0]$13035 + update \core_issue__addr$11 $0\core_issue__addr$11[2:0]$13483 end - attribute \src "libresoc.v:180860.3-180874.6" - process $proc$libresoc.v:180860$13037 + attribute \src "libresoc.v:186245.3-186259.6" + process $proc$libresoc.v:186245$13485 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:180861.5-180861.29" + attribute \src "libresoc.v:186246.5-186246.29" switch \initial - attribute \src "libresoc.v:180861.9-180861.17" + attribute \src "libresoc.v:186246.9-186246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -379581,19 +389852,19 @@ module \test_issuer sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:180875.3-180889.6" - process $proc$libresoc.v:180875$13038 + attribute \src "libresoc.v:186260.3-186274.6" + process $proc$libresoc.v:186260$13486 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:180876.5-180876.29" + attribute \src "libresoc.v:186261.5-186261.29" switch \initial - attribute \src "libresoc.v:180876.9-180876.17" + attribute \src "libresoc.v:186261.9-186261.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -379608,70 +389879,70 @@ module \test_issuer sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:180890.3-180905.6" - process $proc$libresoc.v:180890$13039 + attribute \src "libresoc.v:186275.3-186290.6" + process $proc$libresoc.v:186275$13487 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13040 $2\dec2_cur_dec$next[63:0]$13042 - attribute \src "libresoc.v:180891.5-180891.29" + assign $0\dec2_cur_dec$next[63:0]$13488 $2\dec2_cur_dec$next[63:0]$13490 + attribute \src "libresoc.v:186276.5-186276.29" switch \initial - attribute \src "libresoc.v:180891.9-180891.17" + attribute \src "libresoc.v:186276.9-186276.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13041 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13489 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13041 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13489 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13042 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13490 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13042 $1\dec2_cur_dec$next[63:0]$13041 + assign $2\dec2_cur_dec$next[63:0]$13490 $1\dec2_cur_dec$next[63:0]$13489 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13040 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13488 end - attribute \src "libresoc.v:180906.3-180916.6" - process $proc$libresoc.v:180906$13043 + attribute \src "libresoc.v:186291.3-186301.6" + process $proc$libresoc.v:186291$13491 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:180907.5-180907.29" + attribute \src "libresoc.v:186292.5-186292.29" switch \initial - attribute \src "libresoc.v:180907.9-180907.17" + attribute \src "libresoc.v:186292.9-186292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:361" - switch \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" + switch \fsm_state$133 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$121 [63:0] + assign $1\new_tb[63:0] \$137 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:180917.3-180925.6" - process $proc$libresoc.v:180917$13044 + attribute \src "libresoc.v:186302.3-186310.6" + process $proc$libresoc.v:186302$13492 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13045 $1\dbg_dmi_we_i$next[0:0]$13046 - attribute \src "libresoc.v:180918.5-180918.29" + assign $0\dbg_dmi_we_i$next[0:0]$13493 $1\dbg_dmi_we_i$next[0:0]$13494 + attribute \src "libresoc.v:186303.5-186303.29" switch \initial - attribute \src "libresoc.v:180918.9-180918.17" + attribute \src "libresoc.v:186303.9-186303.17" case 1'1 case end @@ -379680,21 +389951,21 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13046 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13494 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13046 \jtag_dmi0_we_i + assign $1\dbg_dmi_we_i$next[0:0]$13494 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13045 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13493 end - attribute \src "libresoc.v:180926.3-180934.6" - process $proc$libresoc.v:180926$13047 + attribute \src "libresoc.v:186311.3-186319.6" + process $proc$libresoc.v:186311$13495 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13048 $1\pc_ok_delay$next[0:0]$13049 - attribute \src "libresoc.v:180927.5-180927.29" + assign $0\pc_ok_delay$next[0:0]$13496 $1\pc_ok_delay$next[0:0]$13497 + attribute \src "libresoc.v:186312.5-186312.29" switch \initial - attribute \src "libresoc.v:180927.9-180927.17" + attribute \src "libresoc.v:186312.9-186312.17" case 1'1 case end @@ -379703,26 +389974,26 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13049 1'0 + assign $1\pc_ok_delay$next[0:0]$13497 1'0 case - assign $1\pc_ok_delay$next[0:0]$13049 \$23 + assign $1\pc_ok_delay$next[0:0]$13497 \$39 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13048 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13496 end - attribute \src "libresoc.v:180935.3-180950.6" - process $proc$libresoc.v:180935$13050 + attribute \src "libresoc.v:186320.3-186335.6" + process $proc$libresoc.v:186320$13498 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:180936.5-180936.29" + attribute \src "libresoc.v:186321.5-186321.29" switch \initial - attribute \src "libresoc.v:180936.9-180936.17" + attribute \src "libresoc.v:186321.9-186321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379731,7 +390002,7 @@ module \test_issuer case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379743,18 +390014,18 @@ module \test_issuer sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:180951.3-180963.6" - process $proc$libresoc.v:180951$13051 + attribute \src "libresoc.v:186336.3-186348.6" + process $proc$libresoc.v:186336$13499 assign { } { } assign { } { } assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] - attribute \src "libresoc.v:180952.5-180952.29" + attribute \src "libresoc.v:186337.5-186337.29" switch \initial - attribute \src "libresoc.v:180952.9-180952.17" + attribute \src "libresoc.v:186337.9-186337.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:187" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -379767,31 +390038,31 @@ module \test_issuer sync always update \core_cia__ren $0\core_cia__ren[3:0] end - attribute \src "libresoc.v:180964.3-180984.6" - process $proc$libresoc.v:180964$13052 + attribute \src "libresoc.v:186349.3-186369.6" + process $proc$libresoc.v:186349$13500 assign { } { } assign { } { } assign $0\core_wen[3:0] $1\core_wen[3:0] - attribute \src "libresoc.v:180965.5-180965.29" + attribute \src "libresoc.v:186350.5-186350.29" switch \initial - attribute \src "libresoc.v:180965.9-180965.17" + attribute \src "libresoc.v:186350.9-186350.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_wen[3:0] $2\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_wen[3:0] $3\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + switch \$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -379808,31 +390079,31 @@ module \test_issuer sync always update \core_wen $0\core_wen[3:0] end - attribute \src "libresoc.v:180985.3-181005.6" - process $proc$libresoc.v:180985$13053 + attribute \src "libresoc.v:186370.3-186390.6" + process $proc$libresoc.v:186370$13501 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:180986.5-180986.29" + attribute \src "libresoc.v:186371.5-186371.29" switch \initial - attribute \src "libresoc.v:180986.9-180986.17" + attribute \src "libresoc.v:186371.9-186371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" - switch \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + switch \$47 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -379849,25 +390120,25 @@ module \test_issuer sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:181006.3-181021.6" - process $proc$libresoc.v:181006$13054 + attribute \src "libresoc.v:186391.3-186406.6" + process $proc$libresoc.v:186391$13502 assign { } { } assign { } { } assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] - attribute \src "libresoc.v:181007.5-181007.29" + attribute \src "libresoc.v:186392.5-186392.29" switch \initial - attribute \src "libresoc.v:181007.9-181007.17" + attribute \src "libresoc.v:186392.9-186392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -379881,14 +390152,14 @@ module \test_issuer sync always update \core_msr__ren $0\core_msr__ren[3:0] end - attribute \src "libresoc.v:181022.3-181030.6" - process $proc$libresoc.v:181022$13055 + attribute \src "libresoc.v:186407.3-186415.6" + process $proc$libresoc.v:186407$13503 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13056 $1\dbg_dmi_din$next[63:0]$13057 - attribute \src "libresoc.v:181023.5-181023.29" + assign $0\dbg_dmi_din$next[63:0]$13504 $1\dbg_dmi_din$next[63:0]$13505 + attribute \src "libresoc.v:186408.5-186408.29" switch \initial - attribute \src "libresoc.v:181023.9-181023.17" + attribute \src "libresoc.v:186408.9-186408.17" case 1'1 case end @@ -379897,61 +390168,69 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13057 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13505 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13057 \jtag_dmi0_din + assign $1\dbg_dmi_din$next[63:0]$13505 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13056 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13504 end - attribute \src "libresoc.v:181031.3-181055.6" - process $proc$libresoc.v:181031$13058 + attribute \src "libresoc.v:186416.3-186440.6" + process $proc$libresoc.v:186416$13506 assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13059 $3\pc_changed$next[0:0]$13062 - attribute \src "libresoc.v:181032.5-181032.29" + assign $0\pc_changed$next[0:0]$13507 $3\pc_changed$next[0:0]$13510 + attribute \src "libresoc.v:186417.5-186417.29" switch \initial - attribute \src "libresoc.v:181032.9-181032.17" + attribute \src "libresoc.v:186417.9-186417.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\pc_changed$next[0:0]$13060 1'0 + assign $1\pc_changed$next[0:0]$13508 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\pc_changed$next[0:0]$13060 $2\pc_changed$next[0:0]$13061 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" - switch \$39 + assign $1\pc_changed$next[0:0]$13508 $2\pc_changed$next[0:0]$13509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\pc_changed$next[0:0]$13061 1'1 + assign $2\pc_changed$next[0:0]$13509 1'1 case - assign $2\pc_changed$next[0:0]$13061 \pc_changed + assign $2\pc_changed$next[0:0]$13509 \pc_changed end case - assign $1\pc_changed$next[0:0]$13060 \pc_changed + assign $1\pc_changed$next[0:0]$13508 \pc_changed end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13062 1'0 + assign $3\pc_changed$next[0:0]$13510 1'0 case - assign $3\pc_changed$next[0:0]$13062 $1\pc_changed$next[0:0]$13060 + assign $3\pc_changed$next[0:0]$13510 $1\pc_changed$next[0:0]$13508 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13059 + update \pc_changed$next $0\pc_changed$next[0:0]$13507 end - attribute \src "libresoc.v:181056.3-181162.6" - process $proc$libresoc.v:181056$13063 + attribute \src "libresoc.v:186441.3-186563.6" + process $proc$libresoc.v:186441$13511 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -380054,83 +390333,107 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13064 $1\core_asmcode$next[7:0]$13115 - assign $0\core_core_core_cia$next[63:0]$13065 $1\core_core_core_cia$next[63:0]$13116 - assign $0\core_core_core_cr_rd$next[7:0]$13066 $1\core_core_core_cr_rd$next[7:0]$13117 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13068 $1\core_core_core_cr_wr$next[7:0]$13119 - assign $0\core_core_core_fn_unit$next[11:0]$13069 $1\core_core_core_fn_unit$next[11:0]$13120 - assign $0\core_core_core_input_carry$next[1:0]$13070 $1\core_core_core_input_carry$next[1:0]$13121 - assign $0\core_core_core_insn$next[31:0]$13071 $1\core_core_core_insn$next[31:0]$13122 - assign $0\core_core_core_insn_type$next[6:0]$13072 $1\core_core_core_insn_type$next[6:0]$13123 - assign $0\core_core_core_is_32bit$next[0:0]$13073 $1\core_core_core_is_32bit$next[0:0]$13124 - assign $0\core_core_core_msr$next[63:0]$13074 $1\core_core_core_msr$next[63:0]$13125 - assign $0\core_core_core_oe$next[0:0]$13075 $1\core_core_core_oe$next[0:0]$13126 assign { } { } - assign $0\core_core_core_rc$next[0:0]$13077 $1\core_core_core_rc$next[0:0]$13128 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13079 $1\core_core_core_trapaddr$next[12:0]$13130 - assign $0\core_core_core_traptype$next[6:0]$13080 $1\core_core_core_traptype$next[6:0]$13131 - assign $0\core_core_cr_in1$next[2:0]$13081 $1\core_core_cr_in1$next[2:0]$13132 assign { } { } - assign $0\core_core_cr_in2$1$next[2:0]$13083 $1\core_core_cr_in2$1$next[2:0]$13134 - assign $0\core_core_cr_in2$next[2:0]$13084 $1\core_core_cr_in2$next[2:0]$13135 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[2:0]$13087 $1\core_core_cr_out$next[2:0]$13138 assign { } { } - assign $0\core_core_ea$next[4:0]$13089 $1\core_core_ea$next[4:0]$13140 - assign $0\core_core_fast1$next[2:0]$13090 $1\core_core_fast1$next[2:0]$13141 assign { } { } - assign $0\core_core_fast2$next[2:0]$13092 $1\core_core_fast2$next[2:0]$13143 + assign $0\core_asmcode$next[7:0]$13512 $1\core_asmcode$next[7:0]$13571 + assign $0\core_core_core_cia$next[63:0]$13513 $1\core_core_core_cia$next[63:0]$13572 + assign $0\core_core_core_cr_rd$next[7:0]$13514 $1\core_core_core_cr_rd$next[7:0]$13573 assign { } { } - assign $0\core_core_fasto1$next[2:0]$13094 $1\core_core_fasto1$next[2:0]$13145 - assign $0\core_core_fasto2$next[2:0]$13095 $1\core_core_fasto2$next[2:0]$13146 - assign $0\core_core_lk$next[0:0]$13096 $1\core_core_lk$next[0:0]$13147 - assign $0\core_core_reg1$next[4:0]$13097 $1\core_core_reg1$next[4:0]$13148 + assign $0\core_core_core_cr_wr$next[7:0]$13516 $1\core_core_core_cr_wr$next[7:0]$13575 assign { } { } - assign $0\core_core_reg2$next[4:0]$13099 $1\core_core_reg2$next[4:0]$13150 assign { } { } - assign $0\core_core_reg3$next[4:0]$13101 $1\core_core_reg3$next[4:0]$13152 assign { } { } - assign $0\core_core_rego$next[4:0]$13103 $1\core_core_rego$next[4:0]$13154 - assign $0\core_core_spr1$next[9:0]$13104 $1\core_core_spr1$next[9:0]$13155 assign { } { } - assign $0\core_core_spro$next[9:0]$13106 $1\core_core_spro$next[9:0]$13157 - assign $0\core_core_xer_in$next[2:0]$13107 $1\core_core_xer_in$next[2:0]$13158 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\core_core_core_fn_unit$next[11:0]$13525 $1\core_core_core_fn_unit$next[11:0]$13584 + assign $0\core_core_core_input_carry$next[1:0]$13526 $1\core_core_core_input_carry$next[1:0]$13585 + assign $0\core_core_core_insn$next[31:0]$13527 $1\core_core_core_insn$next[31:0]$13586 + assign $0\core_core_core_insn_type$next[6:0]$13528 $1\core_core_core_insn_type$next[6:0]$13587 + assign $0\core_core_core_is_32bit$next[0:0]$13529 $1\core_core_core_is_32bit$next[0:0]$13588 + assign $0\core_core_core_msr$next[63:0]$13530 $1\core_core_core_msr$next[63:0]$13589 + assign $0\core_core_core_oe$next[0:0]$13531 $1\core_core_core_oe$next[0:0]$13590 assign { } { } + assign $0\core_core_core_rc$next[0:0]$13533 $1\core_core_core_rc$next[0:0]$13592 assign { } { } - assign $0\core_xer_out$next[0:0]$13114 $1\core_xer_out$next[0:0]$13165 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13067 $4\core_core_core_cr_rd_ok$next[0:0]$13268 - assign $0\core_core_core_oe_ok$next[0:0]$13076 $4\core_core_core_oe_ok$next[0:0]$13269 - assign $0\core_core_core_rc_ok$next[0:0]$13078 $4\core_core_core_rc_ok$next[0:0]$13270 - assign $0\core_core_cr_in1_ok$next[0:0]$13082 $4\core_core_cr_in1_ok$next[0:0]$13271 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13085 $4\core_core_cr_in2_ok$2$next[0:0]$13272 - assign $0\core_core_cr_in2_ok$next[0:0]$13086 $4\core_core_cr_in2_ok$next[0:0]$13273 - assign $0\core_core_cr_wr_ok$next[0:0]$13088 $4\core_core_cr_wr_ok$next[0:0]$13274 - assign $0\core_core_fast1_ok$next[0:0]$13091 $4\core_core_fast1_ok$next[0:0]$13275 - assign $0\core_core_fast2_ok$next[0:0]$13093 $4\core_core_fast2_ok$next[0:0]$13276 - assign $0\core_core_reg1_ok$next[0:0]$13098 $4\core_core_reg1_ok$next[0:0]$13277 - assign $0\core_core_reg2_ok$next[0:0]$13100 $4\core_core_reg2_ok$next[0:0]$13278 - assign $0\core_core_reg3_ok$next[0:0]$13102 $4\core_core_reg3_ok$next[0:0]$13279 - assign $0\core_core_spr1_ok$next[0:0]$13105 $4\core_core_spr1_ok$next[0:0]$13280 - assign $0\core_cr_out_ok$next[0:0]$13108 $4\core_cr_out_ok$next[0:0]$13281 - assign $0\core_ea_ok$next[0:0]$13109 $4\core_ea_ok$next[0:0]$13282 - assign $0\core_fasto1_ok$next[0:0]$13110 $4\core_fasto1_ok$next[0:0]$13283 - assign $0\core_fasto2_ok$next[0:0]$13111 $4\core_fasto2_ok$next[0:0]$13284 - assign $0\core_rego_ok$next[0:0]$13112 $4\core_rego_ok$next[0:0]$13285 - assign $0\core_spro_ok$next[0:0]$13113 $4\core_spro_ok$next[0:0]$13286 - attribute \src "libresoc.v:181057.5-181057.29" + assign $0\core_core_core_trapaddr$next[12:0]$13535 $1\core_core_core_trapaddr$next[12:0]$13594 + assign $0\core_core_core_traptype$next[7:0]$13536 $1\core_core_core_traptype$next[7:0]$13595 + assign $0\core_core_cr_in1$next[2:0]$13537 $1\core_core_cr_in1$next[2:0]$13596 + assign { } { } + assign $0\core_core_cr_in2$1$next[2:0]$13539 $1\core_core_cr_in2$1$next[2:0]$13598 + assign $0\core_core_cr_in2$next[2:0]$13540 $1\core_core_cr_in2$next[2:0]$13599 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[2:0]$13543 $1\core_core_cr_out$next[2:0]$13602 + assign { } { } + assign $0\core_core_ea$next[4:0]$13545 $1\core_core_ea$next[4:0]$13604 + assign $0\core_core_fast1$next[2:0]$13546 $1\core_core_fast1$next[2:0]$13605 + assign { } { } + assign $0\core_core_fast2$next[2:0]$13548 $1\core_core_fast2$next[2:0]$13607 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$13550 $1\core_core_fasto1$next[2:0]$13609 + assign $0\core_core_fasto2$next[2:0]$13551 $1\core_core_fasto2$next[2:0]$13610 + assign $0\core_core_lk$next[0:0]$13552 $1\core_core_lk$next[0:0]$13611 + assign $0\core_core_reg1$next[4:0]$13553 $1\core_core_reg1$next[4:0]$13612 + assign { } { } + assign $0\core_core_reg2$next[4:0]$13555 $1\core_core_reg2$next[4:0]$13614 + assign { } { } + assign $0\core_core_reg3$next[4:0]$13557 $1\core_core_reg3$next[4:0]$13616 + assign { } { } + assign $0\core_core_rego$next[4:0]$13559 $1\core_core_rego$next[4:0]$13618 + assign $0\core_core_spr1$next[9:0]$13560 $1\core_core_spr1$next[9:0]$13619 + assign { } { } + assign $0\core_core_spro$next[9:0]$13562 $1\core_core_spro$next[9:0]$13621 + assign $0\core_core_xer_in$next[2:0]$13563 $1\core_core_xer_in$next[2:0]$13622 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$13570 $1\core_xer_out$next[0:0]$13629 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13515 $4\core_core_core_cr_rd_ok$next[0:0]$13748 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13517 $4\core_core_core_exc_$signal$3$next[0:0]$13749 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13518 $4\core_core_core_exc_$signal$4$next[0:0]$13750 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13519 $4\core_core_core_exc_$signal$5$next[0:0]$13751 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13520 $4\core_core_core_exc_$signal$6$next[0:0]$13752 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13521 $4\core_core_core_exc_$signal$7$next[0:0]$13753 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13522 $4\core_core_core_exc_$signal$8$next[0:0]$13754 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13523 $4\core_core_core_exc_$signal$9$next[0:0]$13755 + assign $0\core_core_core_exc_$signal$next[0:0]$13524 $4\core_core_core_exc_$signal$next[0:0]$13756 + assign $0\core_core_core_oe_ok$next[0:0]$13532 $4\core_core_core_oe_ok$next[0:0]$13757 + assign $0\core_core_core_rc_ok$next[0:0]$13534 $4\core_core_core_rc_ok$next[0:0]$13758 + assign $0\core_core_cr_in1_ok$next[0:0]$13538 $4\core_core_cr_in1_ok$next[0:0]$13759 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13541 $4\core_core_cr_in2_ok$2$next[0:0]$13760 + assign $0\core_core_cr_in2_ok$next[0:0]$13542 $4\core_core_cr_in2_ok$next[0:0]$13761 + assign $0\core_core_cr_wr_ok$next[0:0]$13544 $4\core_core_cr_wr_ok$next[0:0]$13762 + assign $0\core_core_fast1_ok$next[0:0]$13547 $4\core_core_fast1_ok$next[0:0]$13763 + assign $0\core_core_fast2_ok$next[0:0]$13549 $4\core_core_fast2_ok$next[0:0]$13764 + assign $0\core_core_reg1_ok$next[0:0]$13554 $4\core_core_reg1_ok$next[0:0]$13765 + assign $0\core_core_reg2_ok$next[0:0]$13556 $4\core_core_reg2_ok$next[0:0]$13766 + assign $0\core_core_reg3_ok$next[0:0]$13558 $4\core_core_reg3_ok$next[0:0]$13767 + assign $0\core_core_spr1_ok$next[0:0]$13561 $4\core_core_spr1_ok$next[0:0]$13768 + assign $0\core_cr_out_ok$next[0:0]$13564 $4\core_cr_out_ok$next[0:0]$13769 + assign $0\core_ea_ok$next[0:0]$13565 $4\core_ea_ok$next[0:0]$13770 + assign $0\core_fasto1_ok$next[0:0]$13566 $4\core_fasto1_ok$next[0:0]$13771 + assign $0\core_fasto2_ok$next[0:0]$13567 $4\core_fasto2_ok$next[0:0]$13772 + assign $0\core_rego_ok$next[0:0]$13568 $4\core_rego_ok$next[0:0]$13773 + assign $0\core_spro_ok$next[0:0]$13569 $4\core_spro_ok$next[0:0]$13774 + attribute \src "libresoc.v:186442.5-186442.29" switch \initial - attribute \src "libresoc.v:181057.9-181057.17" + attribute \src "libresoc.v:186442.9-186442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 @@ -380185,7 +390488,15 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13124 $1\core_core_cr_wr_ok$next[0:0]$13139 $1\core_core_core_cr_wr$next[7:0]$13119 $1\core_core_core_cr_rd_ok$next[0:0]$13118 $1\core_core_core_cr_rd$next[7:0]$13117 $1\core_core_core_trapaddr$next[12:0]$13130 $1\core_core_core_traptype$next[6:0]$13131 $1\core_core_core_input_carry$next[1:0]$13121 $1\core_core_core_oe_ok$next[0:0]$13127 $1\core_core_core_oe$next[0:0]$13126 $1\core_core_core_rc_ok$next[0:0]$13129 $1\core_core_core_rc$next[0:0]$13128 $1\core_core_lk$next[0:0]$13147 $1\core_core_core_fn_unit$next[11:0]$13120 $1\core_core_core_insn_type$next[6:0]$13123 $1\core_core_core_insn$next[31:0]$13122 $1\core_core_core_cia$next[63:0]$13116 $1\core_core_core_msr$next[63:0]$13125 $1\core_cr_out_ok$next[0:0]$13159 $1\core_core_cr_out$next[2:0]$13138 $1\core_core_cr_in2_ok$2$next[0:0]$13136 $1\core_core_cr_in2$1$next[2:0]$13134 $1\core_core_cr_in2_ok$next[0:0]$13137 $1\core_core_cr_in2$next[2:0]$13135 $1\core_core_cr_in1_ok$next[0:0]$13133 $1\core_core_cr_in1$next[2:0]$13132 $1\core_fasto2_ok$next[0:0]$13162 $1\core_core_fasto2$next[2:0]$13146 $1\core_fasto1_ok$next[0:0]$13161 $1\core_core_fasto1$next[2:0]$13145 $1\core_core_fast2_ok$next[0:0]$13144 $1\core_core_fast2$next[2:0]$13143 $1\core_core_fast1_ok$next[0:0]$13142 $1\core_core_fast1$next[2:0]$13141 $1\core_xer_out$next[0:0]$13165 $1\core_core_xer_in$next[2:0]$13158 $1\core_core_spr1_ok$next[0:0]$13156 $1\core_core_spr1$next[9:0]$13155 $1\core_spro_ok$next[0:0]$13164 $1\core_core_spro$next[9:0]$13157 $1\core_core_reg3_ok$next[0:0]$13153 $1\core_core_reg3$next[4:0]$13152 $1\core_core_reg2_ok$next[0:0]$13151 $1\core_core_reg2$next[4:0]$13150 $1\core_core_reg1_ok$next[0:0]$13149 $1\core_core_reg1$next[4:0]$13148 $1\core_ea_ok$next[0:0]$13160 $1\core_core_ea$next[4:0]$13140 $1\core_rego_ok$next[0:0]$13163 $1\core_core_rego$next[4:0]$13154 $1\core_asmcode$next[7:0]$13115 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_core_is_32bit$next[0:0]$13588 $1\core_core_cr_wr_ok$next[0:0]$13603 $1\core_core_core_cr_wr$next[7:0]$13575 $1\core_core_core_cr_rd_ok$next[0:0]$13574 $1\core_core_core_cr_rd$next[7:0]$13573 $1\core_core_core_trapaddr$next[12:0]$13594 $1\core_core_core_exc_$signal$9$next[0:0]$13582 $1\core_core_core_exc_$signal$8$next[0:0]$13581 $1\core_core_core_exc_$signal$7$next[0:0]$13580 $1\core_core_core_exc_$signal$6$next[0:0]$13579 $1\core_core_core_exc_$signal$5$next[0:0]$13578 $1\core_core_core_exc_$signal$4$next[0:0]$13577 $1\core_core_core_exc_$signal$3$next[0:0]$13576 $1\core_core_core_exc_$signal$next[0:0]$13583 $1\core_core_core_traptype$next[7:0]$13595 $1\core_core_core_input_carry$next[1:0]$13585 $1\core_core_core_oe_ok$next[0:0]$13591 $1\core_core_core_oe$next[0:0]$13590 $1\core_core_core_rc_ok$next[0:0]$13593 $1\core_core_core_rc$next[0:0]$13592 $1\core_core_lk$next[0:0]$13611 $1\core_core_core_fn_unit$next[11:0]$13584 $1\core_core_core_insn_type$next[6:0]$13587 $1\core_core_core_insn$next[31:0]$13586 $1\core_core_core_cia$next[63:0]$13572 $1\core_core_core_msr$next[63:0]$13589 $1\core_cr_out_ok$next[0:0]$13623 $1\core_core_cr_out$next[2:0]$13602 $1\core_core_cr_in2_ok$2$next[0:0]$13600 $1\core_core_cr_in2$1$next[2:0]$13598 $1\core_core_cr_in2_ok$next[0:0]$13601 $1\core_core_cr_in2$next[2:0]$13599 $1\core_core_cr_in1_ok$next[0:0]$13597 $1\core_core_cr_in1$next[2:0]$13596 $1\core_fasto2_ok$next[0:0]$13626 $1\core_core_fasto2$next[2:0]$13610 $1\core_fasto1_ok$next[0:0]$13625 $1\core_core_fasto1$next[2:0]$13609 $1\core_core_fast2_ok$next[0:0]$13608 $1\core_core_fast2$next[2:0]$13607 $1\core_core_fast1_ok$next[0:0]$13606 $1\core_core_fast1$next[2:0]$13605 $1\core_xer_out$next[0:0]$13629 $1\core_core_xer_in$next[2:0]$13622 $1\core_core_spr1_ok$next[0:0]$13620 $1\core_core_spr1$next[9:0]$13619 $1\core_spro_ok$next[0:0]$13628 $1\core_core_spro$next[9:0]$13621 $1\core_core_reg3_ok$next[0:0]$13617 $1\core_core_reg3$next[4:0]$13616 $1\core_core_reg2_ok$next[0:0]$13615 $1\core_core_reg2$next[4:0]$13614 $1\core_core_reg1_ok$next[0:0]$13613 $1\core_core_reg1$next[4:0]$13612 $1\core_ea_ok$next[0:0]$13624 $1\core_core_ea$next[4:0]$13604 $1\core_rego_ok$next[0:0]$13627 $1\core_core_rego$next[4:0]$13618 $1\core_asmcode$next[7:0]$13571 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -380239,112 +390550,136 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13115 $2\core_asmcode$next[7:0]$13166 - assign $1\core_core_core_cia$next[63:0]$13116 $2\core_core_core_cia$next[63:0]$13167 - assign $1\core_core_core_cr_rd$next[7:0]$13117 $2\core_core_core_cr_rd$next[7:0]$13168 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 $2\core_core_core_cr_rd_ok$next[0:0]$13169 - assign $1\core_core_core_cr_wr$next[7:0]$13119 $2\core_core_core_cr_wr$next[7:0]$13170 - assign $1\core_core_core_fn_unit$next[11:0]$13120 $2\core_core_core_fn_unit$next[11:0]$13171 - assign $1\core_core_core_input_carry$next[1:0]$13121 $2\core_core_core_input_carry$next[1:0]$13172 - assign $1\core_core_core_insn$next[31:0]$13122 $2\core_core_core_insn$next[31:0]$13173 - assign $1\core_core_core_insn_type$next[6:0]$13123 $2\core_core_core_insn_type$next[6:0]$13174 - assign $1\core_core_core_is_32bit$next[0:0]$13124 $2\core_core_core_is_32bit$next[0:0]$13175 - assign $1\core_core_core_msr$next[63:0]$13125 $2\core_core_core_msr$next[63:0]$13176 - assign $1\core_core_core_oe$next[0:0]$13126 $2\core_core_core_oe$next[0:0]$13177 - assign $1\core_core_core_oe_ok$next[0:0]$13127 $2\core_core_core_oe_ok$next[0:0]$13178 - assign $1\core_core_core_rc$next[0:0]$13128 $2\core_core_core_rc$next[0:0]$13179 - assign $1\core_core_core_rc_ok$next[0:0]$13129 $2\core_core_core_rc_ok$next[0:0]$13180 - assign $1\core_core_core_trapaddr$next[12:0]$13130 $2\core_core_core_trapaddr$next[12:0]$13181 - assign $1\core_core_core_traptype$next[6:0]$13131 $2\core_core_core_traptype$next[6:0]$13182 - assign $1\core_core_cr_in1$next[2:0]$13132 $2\core_core_cr_in1$next[2:0]$13183 - assign $1\core_core_cr_in1_ok$next[0:0]$13133 $2\core_core_cr_in1_ok$next[0:0]$13184 - assign $1\core_core_cr_in2$1$next[2:0]$13134 $2\core_core_cr_in2$1$next[2:0]$13185 - assign $1\core_core_cr_in2$next[2:0]$13135 $2\core_core_cr_in2$next[2:0]$13186 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 $2\core_core_cr_in2_ok$2$next[0:0]$13187 - assign $1\core_core_cr_in2_ok$next[0:0]$13137 $2\core_core_cr_in2_ok$next[0:0]$13188 - assign $1\core_core_cr_out$next[2:0]$13138 $2\core_core_cr_out$next[2:0]$13189 - assign $1\core_core_cr_wr_ok$next[0:0]$13139 $2\core_core_cr_wr_ok$next[0:0]$13190 - assign $1\core_core_ea$next[4:0]$13140 $2\core_core_ea$next[4:0]$13191 - assign $1\core_core_fast1$next[2:0]$13141 $2\core_core_fast1$next[2:0]$13192 - assign $1\core_core_fast1_ok$next[0:0]$13142 $2\core_core_fast1_ok$next[0:0]$13193 - assign $1\core_core_fast2$next[2:0]$13143 $2\core_core_fast2$next[2:0]$13194 - assign $1\core_core_fast2_ok$next[0:0]$13144 $2\core_core_fast2_ok$next[0:0]$13195 - assign $1\core_core_fasto1$next[2:0]$13145 $2\core_core_fasto1$next[2:0]$13196 - assign $1\core_core_fasto2$next[2:0]$13146 $2\core_core_fasto2$next[2:0]$13197 - assign $1\core_core_lk$next[0:0]$13147 $2\core_core_lk$next[0:0]$13198 - assign $1\core_core_reg1$next[4:0]$13148 $2\core_core_reg1$next[4:0]$13199 - assign $1\core_core_reg1_ok$next[0:0]$13149 $2\core_core_reg1_ok$next[0:0]$13200 - assign $1\core_core_reg2$next[4:0]$13150 $2\core_core_reg2$next[4:0]$13201 - assign $1\core_core_reg2_ok$next[0:0]$13151 $2\core_core_reg2_ok$next[0:0]$13202 - assign $1\core_core_reg3$next[4:0]$13152 $2\core_core_reg3$next[4:0]$13203 - assign $1\core_core_reg3_ok$next[0:0]$13153 $2\core_core_reg3_ok$next[0:0]$13204 - assign $1\core_core_rego$next[4:0]$13154 $2\core_core_rego$next[4:0]$13205 - assign $1\core_core_spr1$next[9:0]$13155 $2\core_core_spr1$next[9:0]$13206 - assign $1\core_core_spr1_ok$next[0:0]$13156 $2\core_core_spr1_ok$next[0:0]$13207 - assign $1\core_core_spro$next[9:0]$13157 $2\core_core_spro$next[9:0]$13208 - assign $1\core_core_xer_in$next[2:0]$13158 $2\core_core_xer_in$next[2:0]$13209 - assign $1\core_cr_out_ok$next[0:0]$13159 $2\core_cr_out_ok$next[0:0]$13210 - assign $1\core_ea_ok$next[0:0]$13160 $2\core_ea_ok$next[0:0]$13211 - assign $1\core_fasto1_ok$next[0:0]$13161 $2\core_fasto1_ok$next[0:0]$13212 - assign $1\core_fasto2_ok$next[0:0]$13162 $2\core_fasto2_ok$next[0:0]$13213 - assign $1\core_rego_ok$next[0:0]$13163 $2\core_rego_ok$next[0:0]$13214 - assign $1\core_spro_ok$next[0:0]$13164 $2\core_spro_ok$next[0:0]$13215 - assign $1\core_xer_out$next[0:0]$13165 $2\core_xer_out$next[0:0]$13216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13571 $2\core_asmcode$next[7:0]$13630 + assign $1\core_core_core_cia$next[63:0]$13572 $2\core_core_core_cia$next[63:0]$13631 + assign $1\core_core_core_cr_rd$next[7:0]$13573 $2\core_core_core_cr_rd$next[7:0]$13632 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 $2\core_core_core_cr_rd_ok$next[0:0]$13633 + assign $1\core_core_core_cr_wr$next[7:0]$13575 $2\core_core_core_cr_wr$next[7:0]$13634 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 $2\core_core_core_exc_$signal$3$next[0:0]$13635 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 $2\core_core_core_exc_$signal$4$next[0:0]$13636 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 $2\core_core_core_exc_$signal$5$next[0:0]$13637 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 $2\core_core_core_exc_$signal$6$next[0:0]$13638 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 $2\core_core_core_exc_$signal$7$next[0:0]$13639 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 $2\core_core_core_exc_$signal$8$next[0:0]$13640 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 $2\core_core_core_exc_$signal$9$next[0:0]$13641 + assign $1\core_core_core_exc_$signal$next[0:0]$13583 $2\core_core_core_exc_$signal$next[0:0]$13642 + assign $1\core_core_core_fn_unit$next[11:0]$13584 $2\core_core_core_fn_unit$next[11:0]$13643 + assign $1\core_core_core_input_carry$next[1:0]$13585 $2\core_core_core_input_carry$next[1:0]$13644 + assign $1\core_core_core_insn$next[31:0]$13586 $2\core_core_core_insn$next[31:0]$13645 + assign $1\core_core_core_insn_type$next[6:0]$13587 $2\core_core_core_insn_type$next[6:0]$13646 + assign $1\core_core_core_is_32bit$next[0:0]$13588 $2\core_core_core_is_32bit$next[0:0]$13647 + assign $1\core_core_core_msr$next[63:0]$13589 $2\core_core_core_msr$next[63:0]$13648 + assign $1\core_core_core_oe$next[0:0]$13590 $2\core_core_core_oe$next[0:0]$13649 + assign $1\core_core_core_oe_ok$next[0:0]$13591 $2\core_core_core_oe_ok$next[0:0]$13650 + assign $1\core_core_core_rc$next[0:0]$13592 $2\core_core_core_rc$next[0:0]$13651 + assign $1\core_core_core_rc_ok$next[0:0]$13593 $2\core_core_core_rc_ok$next[0:0]$13652 + assign $1\core_core_core_trapaddr$next[12:0]$13594 $2\core_core_core_trapaddr$next[12:0]$13653 + assign $1\core_core_core_traptype$next[7:0]$13595 $2\core_core_core_traptype$next[7:0]$13654 + assign $1\core_core_cr_in1$next[2:0]$13596 $2\core_core_cr_in1$next[2:0]$13655 + assign $1\core_core_cr_in1_ok$next[0:0]$13597 $2\core_core_cr_in1_ok$next[0:0]$13656 + assign $1\core_core_cr_in2$1$next[2:0]$13598 $2\core_core_cr_in2$1$next[2:0]$13657 + assign $1\core_core_cr_in2$next[2:0]$13599 $2\core_core_cr_in2$next[2:0]$13658 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 $2\core_core_cr_in2_ok$2$next[0:0]$13659 + assign $1\core_core_cr_in2_ok$next[0:0]$13601 $2\core_core_cr_in2_ok$next[0:0]$13660 + assign $1\core_core_cr_out$next[2:0]$13602 $2\core_core_cr_out$next[2:0]$13661 + assign $1\core_core_cr_wr_ok$next[0:0]$13603 $2\core_core_cr_wr_ok$next[0:0]$13662 + assign $1\core_core_ea$next[4:0]$13604 $2\core_core_ea$next[4:0]$13663 + assign $1\core_core_fast1$next[2:0]$13605 $2\core_core_fast1$next[2:0]$13664 + assign $1\core_core_fast1_ok$next[0:0]$13606 $2\core_core_fast1_ok$next[0:0]$13665 + assign $1\core_core_fast2$next[2:0]$13607 $2\core_core_fast2$next[2:0]$13666 + assign $1\core_core_fast2_ok$next[0:0]$13608 $2\core_core_fast2_ok$next[0:0]$13667 + assign $1\core_core_fasto1$next[2:0]$13609 $2\core_core_fasto1$next[2:0]$13668 + assign $1\core_core_fasto2$next[2:0]$13610 $2\core_core_fasto2$next[2:0]$13669 + assign $1\core_core_lk$next[0:0]$13611 $2\core_core_lk$next[0:0]$13670 + assign $1\core_core_reg1$next[4:0]$13612 $2\core_core_reg1$next[4:0]$13671 + assign $1\core_core_reg1_ok$next[0:0]$13613 $2\core_core_reg1_ok$next[0:0]$13672 + assign $1\core_core_reg2$next[4:0]$13614 $2\core_core_reg2$next[4:0]$13673 + assign $1\core_core_reg2_ok$next[0:0]$13615 $2\core_core_reg2_ok$next[0:0]$13674 + assign $1\core_core_reg3$next[4:0]$13616 $2\core_core_reg3$next[4:0]$13675 + assign $1\core_core_reg3_ok$next[0:0]$13617 $2\core_core_reg3_ok$next[0:0]$13676 + assign $1\core_core_rego$next[4:0]$13618 $2\core_core_rego$next[4:0]$13677 + assign $1\core_core_spr1$next[9:0]$13619 $2\core_core_spr1$next[9:0]$13678 + assign $1\core_core_spr1_ok$next[0:0]$13620 $2\core_core_spr1_ok$next[0:0]$13679 + assign $1\core_core_spro$next[9:0]$13621 $2\core_core_spro$next[9:0]$13680 + assign $1\core_core_xer_in$next[2:0]$13622 $2\core_core_xer_in$next[2:0]$13681 + assign $1\core_cr_out_ok$next[0:0]$13623 $2\core_cr_out_ok$next[0:0]$13682 + assign $1\core_ea_ok$next[0:0]$13624 $2\core_ea_ok$next[0:0]$13683 + assign $1\core_fasto1_ok$next[0:0]$13625 $2\core_fasto1_ok$next[0:0]$13684 + assign $1\core_fasto2_ok$next[0:0]$13626 $2\core_fasto2_ok$next[0:0]$13685 + assign $1\core_rego_ok$next[0:0]$13627 $2\core_rego_ok$next[0:0]$13686 + assign $1\core_spro_ok$next[0:0]$13628 $2\core_spro_ok$next[0:0]$13687 + assign $1\core_xer_out$next[0:0]$13629 $2\core_xer_out$next[0:0]$13688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\core_asmcode$next[7:0]$13166 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13167 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13168 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13169 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13170 \core_core_core_cr_wr - assign $2\core_core_core_fn_unit$next[11:0]$13171 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13172 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13173 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13174 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13175 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13176 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13177 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13178 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13179 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13180 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13181 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[6:0]$13182 \core_core_core_traptype - assign $2\core_core_cr_in1$next[2:0]$13183 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$13184 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[2:0]$13185 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[2:0]$13186 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$13187 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$13188 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[2:0]$13189 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$13190 \core_core_cr_wr_ok - assign $2\core_core_ea$next[4:0]$13191 \core_core_ea - assign $2\core_core_fast1$next[2:0]$13192 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$13193 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$13194 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$13195 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$13196 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$13197 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$13198 \core_core_lk - assign $2\core_core_reg1$next[4:0]$13199 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$13200 \core_core_reg1_ok - assign $2\core_core_reg2$next[4:0]$13201 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$13202 \core_core_reg2_ok - assign $2\core_core_reg3$next[4:0]$13203 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$13204 \core_core_reg3_ok - assign $2\core_core_rego$next[4:0]$13205 \core_core_rego - assign $2\core_core_spr1$next[9:0]$13206 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$13207 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$13208 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$13209 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$13210 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$13211 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$13212 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$13213 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$13214 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$13215 \core_spro_ok - assign $2\core_xer_out$next[0:0]$13216 \core_xer_out + assign $2\core_asmcode$next[7:0]$13630 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13631 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13632 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$13633 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$13634 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$13635 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$13636 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$13637 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$13638 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$13639 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$13640 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$13641 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$13642 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[11:0]$13643 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$13644 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$13645 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$13646 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$13647 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$13648 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$13649 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$13650 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$13651 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$13652 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$13653 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$13654 \core_core_core_traptype + assign $2\core_core_cr_in1$next[2:0]$13655 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$13656 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[2:0]$13657 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[2:0]$13658 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$13659 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$13660 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[2:0]$13661 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$13662 \core_core_cr_wr_ok + assign $2\core_core_ea$next[4:0]$13663 \core_core_ea + assign $2\core_core_fast1$next[2:0]$13664 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$13665 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$13666 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$13667 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$13668 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$13669 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$13670 \core_core_lk + assign $2\core_core_reg1$next[4:0]$13671 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$13672 \core_core_reg1_ok + assign $2\core_core_reg2$next[4:0]$13673 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$13674 \core_core_reg2_ok + assign $2\core_core_reg3$next[4:0]$13675 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$13676 \core_core_reg3_ok + assign $2\core_core_rego$next[4:0]$13677 \core_core_rego + assign $2\core_core_spr1$next[9:0]$13678 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$13679 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$13680 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$13681 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$13682 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$13683 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$13684 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$13685 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$13686 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$13687 \core_spro_ok + assign $2\core_xer_out$next[0:0]$13688 \core_xer_out attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -380398,7 +390733,15 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13175 $2\core_core_cr_wr_ok$next[0:0]$13190 $2\core_core_core_cr_wr$next[7:0]$13170 $2\core_core_core_cr_rd_ok$next[0:0]$13169 $2\core_core_core_cr_rd$next[7:0]$13168 $2\core_core_core_trapaddr$next[12:0]$13181 $2\core_core_core_traptype$next[6:0]$13182 $2\core_core_core_input_carry$next[1:0]$13172 $2\core_core_core_oe_ok$next[0:0]$13178 $2\core_core_core_oe$next[0:0]$13177 $2\core_core_core_rc_ok$next[0:0]$13180 $2\core_core_core_rc$next[0:0]$13179 $2\core_core_lk$next[0:0]$13198 $2\core_core_core_fn_unit$next[11:0]$13171 $2\core_core_core_insn_type$next[6:0]$13174 $2\core_core_core_insn$next[31:0]$13173 $2\core_core_core_cia$next[63:0]$13167 $2\core_core_core_msr$next[63:0]$13176 $2\core_cr_out_ok$next[0:0]$13210 $2\core_core_cr_out$next[2:0]$13189 $2\core_core_cr_in2_ok$2$next[0:0]$13187 $2\core_core_cr_in2$1$next[2:0]$13185 $2\core_core_cr_in2_ok$next[0:0]$13188 $2\core_core_cr_in2$next[2:0]$13186 $2\core_core_cr_in1_ok$next[0:0]$13184 $2\core_core_cr_in1$next[2:0]$13183 $2\core_fasto2_ok$next[0:0]$13213 $2\core_core_fasto2$next[2:0]$13197 $2\core_fasto1_ok$next[0:0]$13212 $2\core_core_fasto1$next[2:0]$13196 $2\core_core_fast2_ok$next[0:0]$13195 $2\core_core_fast2$next[2:0]$13194 $2\core_core_fast1_ok$next[0:0]$13193 $2\core_core_fast1$next[2:0]$13192 $2\core_xer_out$next[0:0]$13216 $2\core_core_xer_in$next[2:0]$13209 $2\core_core_spr1_ok$next[0:0]$13207 $2\core_core_spr1$next[9:0]$13206 $2\core_spro_ok$next[0:0]$13215 $2\core_core_spro$next[9:0]$13208 $2\core_core_reg3_ok$next[0:0]$13204 $2\core_core_reg3$next[4:0]$13203 $2\core_core_reg2_ok$next[0:0]$13202 $2\core_core_reg2$next[4:0]$13201 $2\core_core_reg1_ok$next[0:0]$13200 $2\core_core_reg1$next[4:0]$13199 $2\core_ea_ok$next[0:0]$13211 $2\core_core_ea$next[4:0]$13191 $2\core_rego_ok$next[0:0]$13214 $2\core_core_rego$next[4:0]$13205 $2\core_asmcode$next[7:0]$13166 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$6 \dec2_cr_in2$5 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$13647 $2\core_core_cr_wr_ok$next[0:0]$13662 $2\core_core_core_cr_wr$next[7:0]$13634 $2\core_core_core_cr_rd_ok$next[0:0]$13633 $2\core_core_core_cr_rd$next[7:0]$13632 $2\core_core_core_trapaddr$next[12:0]$13653 $2\core_core_core_exc_$signal$9$next[0:0]$13641 $2\core_core_core_exc_$signal$8$next[0:0]$13640 $2\core_core_core_exc_$signal$7$next[0:0]$13639 $2\core_core_core_exc_$signal$6$next[0:0]$13638 $2\core_core_core_exc_$signal$5$next[0:0]$13637 $2\core_core_core_exc_$signal$4$next[0:0]$13636 $2\core_core_core_exc_$signal$3$next[0:0]$13635 $2\core_core_core_exc_$signal$next[0:0]$13642 $2\core_core_core_traptype$next[7:0]$13654 $2\core_core_core_input_carry$next[1:0]$13644 $2\core_core_core_oe_ok$next[0:0]$13650 $2\core_core_core_oe$next[0:0]$13649 $2\core_core_core_rc_ok$next[0:0]$13652 $2\core_core_core_rc$next[0:0]$13651 $2\core_core_lk$next[0:0]$13670 $2\core_core_core_fn_unit$next[11:0]$13643 $2\core_core_core_insn_type$next[6:0]$13646 $2\core_core_core_insn$next[31:0]$13645 $2\core_core_core_cia$next[63:0]$13631 $2\core_core_core_msr$next[63:0]$13648 $2\core_cr_out_ok$next[0:0]$13682 $2\core_core_cr_out$next[2:0]$13661 $2\core_core_cr_in2_ok$2$next[0:0]$13659 $2\core_core_cr_in2$1$next[2:0]$13657 $2\core_core_cr_in2_ok$next[0:0]$13660 $2\core_core_cr_in2$next[2:0]$13658 $2\core_core_cr_in1_ok$next[0:0]$13656 $2\core_core_cr_in1$next[2:0]$13655 $2\core_fasto2_ok$next[0:0]$13685 $2\core_core_fasto2$next[2:0]$13669 $2\core_fasto1_ok$next[0:0]$13684 $2\core_core_fasto1$next[2:0]$13668 $2\core_core_fast2_ok$next[0:0]$13667 $2\core_core_fast2$next[2:0]$13666 $2\core_core_fast1_ok$next[0:0]$13665 $2\core_core_fast1$next[2:0]$13664 $2\core_xer_out$next[0:0]$13688 $2\core_core_xer_in$next[2:0]$13681 $2\core_core_spr1_ok$next[0:0]$13679 $2\core_core_spr1$next[9:0]$13678 $2\core_spro_ok$next[0:0]$13687 $2\core_core_spro$next[9:0]$13680 $2\core_core_reg3_ok$next[0:0]$13676 $2\core_core_reg3$next[4:0]$13675 $2\core_core_reg2_ok$next[0:0]$13674 $2\core_core_reg2$next[4:0]$13673 $2\core_core_reg1_ok$next[0:0]$13672 $2\core_core_reg1$next[4:0]$13671 $2\core_ea_ok$next[0:0]$13683 $2\core_core_ea$next[4:0]$13663 $2\core_rego_ok$next[0:0]$13686 $2\core_core_rego$next[4:0]$13677 $2\core_asmcode$next[7:0]$13630 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$14 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$13 \dec2_cr_in2$12 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } end attribute \src "libresoc.v:0.0-0.0" case 2'11 @@ -380453,59 +390796,75 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$13115 $3\core_asmcode$next[7:0]$13217 - assign $1\core_core_core_cia$next[63:0]$13116 $3\core_core_core_cia$next[63:0]$13218 - assign $1\core_core_core_cr_rd$next[7:0]$13117 $3\core_core_core_cr_rd$next[7:0]$13219 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 $3\core_core_core_cr_rd_ok$next[0:0]$13220 - assign $1\core_core_core_cr_wr$next[7:0]$13119 $3\core_core_core_cr_wr$next[7:0]$13221 - assign $1\core_core_core_fn_unit$next[11:0]$13120 $3\core_core_core_fn_unit$next[11:0]$13222 - assign $1\core_core_core_input_carry$next[1:0]$13121 $3\core_core_core_input_carry$next[1:0]$13223 - assign $1\core_core_core_insn$next[31:0]$13122 $3\core_core_core_insn$next[31:0]$13224 - assign $1\core_core_core_insn_type$next[6:0]$13123 $3\core_core_core_insn_type$next[6:0]$13225 - assign $1\core_core_core_is_32bit$next[0:0]$13124 $3\core_core_core_is_32bit$next[0:0]$13226 - assign $1\core_core_core_msr$next[63:0]$13125 $3\core_core_core_msr$next[63:0]$13227 - assign $1\core_core_core_oe$next[0:0]$13126 $3\core_core_core_oe$next[0:0]$13228 - assign $1\core_core_core_oe_ok$next[0:0]$13127 $3\core_core_core_oe_ok$next[0:0]$13229 - assign $1\core_core_core_rc$next[0:0]$13128 $3\core_core_core_rc$next[0:0]$13230 - assign $1\core_core_core_rc_ok$next[0:0]$13129 $3\core_core_core_rc_ok$next[0:0]$13231 - assign $1\core_core_core_trapaddr$next[12:0]$13130 $3\core_core_core_trapaddr$next[12:0]$13232 - assign $1\core_core_core_traptype$next[6:0]$13131 $3\core_core_core_traptype$next[6:0]$13233 - assign $1\core_core_cr_in1$next[2:0]$13132 $3\core_core_cr_in1$next[2:0]$13234 - assign $1\core_core_cr_in1_ok$next[0:0]$13133 $3\core_core_cr_in1_ok$next[0:0]$13235 - assign $1\core_core_cr_in2$1$next[2:0]$13134 $3\core_core_cr_in2$1$next[2:0]$13236 - assign $1\core_core_cr_in2$next[2:0]$13135 $3\core_core_cr_in2$next[2:0]$13237 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 $3\core_core_cr_in2_ok$2$next[0:0]$13238 - assign $1\core_core_cr_in2_ok$next[0:0]$13137 $3\core_core_cr_in2_ok$next[0:0]$13239 - assign $1\core_core_cr_out$next[2:0]$13138 $3\core_core_cr_out$next[2:0]$13240 - assign $1\core_core_cr_wr_ok$next[0:0]$13139 $3\core_core_cr_wr_ok$next[0:0]$13241 - assign $1\core_core_ea$next[4:0]$13140 $3\core_core_ea$next[4:0]$13242 - assign $1\core_core_fast1$next[2:0]$13141 $3\core_core_fast1$next[2:0]$13243 - assign $1\core_core_fast1_ok$next[0:0]$13142 $3\core_core_fast1_ok$next[0:0]$13244 - assign $1\core_core_fast2$next[2:0]$13143 $3\core_core_fast2$next[2:0]$13245 - assign $1\core_core_fast2_ok$next[0:0]$13144 $3\core_core_fast2_ok$next[0:0]$13246 - assign $1\core_core_fasto1$next[2:0]$13145 $3\core_core_fasto1$next[2:0]$13247 - assign $1\core_core_fasto2$next[2:0]$13146 $3\core_core_fasto2$next[2:0]$13248 - assign $1\core_core_lk$next[0:0]$13147 $3\core_core_lk$next[0:0]$13249 - assign $1\core_core_reg1$next[4:0]$13148 $3\core_core_reg1$next[4:0]$13250 - assign $1\core_core_reg1_ok$next[0:0]$13149 $3\core_core_reg1_ok$next[0:0]$13251 - assign $1\core_core_reg2$next[4:0]$13150 $3\core_core_reg2$next[4:0]$13252 - assign $1\core_core_reg2_ok$next[0:0]$13151 $3\core_core_reg2_ok$next[0:0]$13253 - assign $1\core_core_reg3$next[4:0]$13152 $3\core_core_reg3$next[4:0]$13254 - assign $1\core_core_reg3_ok$next[0:0]$13153 $3\core_core_reg3_ok$next[0:0]$13255 - assign $1\core_core_rego$next[4:0]$13154 $3\core_core_rego$next[4:0]$13256 - assign $1\core_core_spr1$next[9:0]$13155 $3\core_core_spr1$next[9:0]$13257 - assign $1\core_core_spr1_ok$next[0:0]$13156 $3\core_core_spr1_ok$next[0:0]$13258 - assign $1\core_core_spro$next[9:0]$13157 $3\core_core_spro$next[9:0]$13259 - assign $1\core_core_xer_in$next[2:0]$13158 $3\core_core_xer_in$next[2:0]$13260 - assign $1\core_cr_out_ok$next[0:0]$13159 $3\core_cr_out_ok$next[0:0]$13261 - assign $1\core_ea_ok$next[0:0]$13160 $3\core_ea_ok$next[0:0]$13262 - assign $1\core_fasto1_ok$next[0:0]$13161 $3\core_fasto1_ok$next[0:0]$13263 - assign $1\core_fasto2_ok$next[0:0]$13162 $3\core_fasto2_ok$next[0:0]$13264 - assign $1\core_rego_ok$next[0:0]$13163 $3\core_rego_ok$next[0:0]$13265 - assign $1\core_spro_ok$next[0:0]$13164 $3\core_spro_ok$next[0:0]$13266 - assign $1\core_xer_out$next[0:0]$13165 $3\core_xer_out$next[0:0]$13267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$43 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$13571 $3\core_asmcode$next[7:0]$13689 + assign $1\core_core_core_cia$next[63:0]$13572 $3\core_core_core_cia$next[63:0]$13690 + assign $1\core_core_core_cr_rd$next[7:0]$13573 $3\core_core_core_cr_rd$next[7:0]$13691 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 $3\core_core_core_cr_rd_ok$next[0:0]$13692 + assign $1\core_core_core_cr_wr$next[7:0]$13575 $3\core_core_core_cr_wr$next[7:0]$13693 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 $3\core_core_core_exc_$signal$3$next[0:0]$13694 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 $3\core_core_core_exc_$signal$4$next[0:0]$13695 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 $3\core_core_core_exc_$signal$5$next[0:0]$13696 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 $3\core_core_core_exc_$signal$6$next[0:0]$13697 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 $3\core_core_core_exc_$signal$7$next[0:0]$13698 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 $3\core_core_core_exc_$signal$8$next[0:0]$13699 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 $3\core_core_core_exc_$signal$9$next[0:0]$13700 + assign $1\core_core_core_exc_$signal$next[0:0]$13583 $3\core_core_core_exc_$signal$next[0:0]$13701 + assign $1\core_core_core_fn_unit$next[11:0]$13584 $3\core_core_core_fn_unit$next[11:0]$13702 + assign $1\core_core_core_input_carry$next[1:0]$13585 $3\core_core_core_input_carry$next[1:0]$13703 + assign $1\core_core_core_insn$next[31:0]$13586 $3\core_core_core_insn$next[31:0]$13704 + assign $1\core_core_core_insn_type$next[6:0]$13587 $3\core_core_core_insn_type$next[6:0]$13705 + assign $1\core_core_core_is_32bit$next[0:0]$13588 $3\core_core_core_is_32bit$next[0:0]$13706 + assign $1\core_core_core_msr$next[63:0]$13589 $3\core_core_core_msr$next[63:0]$13707 + assign $1\core_core_core_oe$next[0:0]$13590 $3\core_core_core_oe$next[0:0]$13708 + assign $1\core_core_core_oe_ok$next[0:0]$13591 $3\core_core_core_oe_ok$next[0:0]$13709 + assign $1\core_core_core_rc$next[0:0]$13592 $3\core_core_core_rc$next[0:0]$13710 + assign $1\core_core_core_rc_ok$next[0:0]$13593 $3\core_core_core_rc_ok$next[0:0]$13711 + assign $1\core_core_core_trapaddr$next[12:0]$13594 $3\core_core_core_trapaddr$next[12:0]$13712 + assign $1\core_core_core_traptype$next[7:0]$13595 $3\core_core_core_traptype$next[7:0]$13713 + assign $1\core_core_cr_in1$next[2:0]$13596 $3\core_core_cr_in1$next[2:0]$13714 + assign $1\core_core_cr_in1_ok$next[0:0]$13597 $3\core_core_cr_in1_ok$next[0:0]$13715 + assign $1\core_core_cr_in2$1$next[2:0]$13598 $3\core_core_cr_in2$1$next[2:0]$13716 + assign $1\core_core_cr_in2$next[2:0]$13599 $3\core_core_cr_in2$next[2:0]$13717 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 $3\core_core_cr_in2_ok$2$next[0:0]$13718 + assign $1\core_core_cr_in2_ok$next[0:0]$13601 $3\core_core_cr_in2_ok$next[0:0]$13719 + assign $1\core_core_cr_out$next[2:0]$13602 $3\core_core_cr_out$next[2:0]$13720 + assign $1\core_core_cr_wr_ok$next[0:0]$13603 $3\core_core_cr_wr_ok$next[0:0]$13721 + assign $1\core_core_ea$next[4:0]$13604 $3\core_core_ea$next[4:0]$13722 + assign $1\core_core_fast1$next[2:0]$13605 $3\core_core_fast1$next[2:0]$13723 + assign $1\core_core_fast1_ok$next[0:0]$13606 $3\core_core_fast1_ok$next[0:0]$13724 + assign $1\core_core_fast2$next[2:0]$13607 $3\core_core_fast2$next[2:0]$13725 + assign $1\core_core_fast2_ok$next[0:0]$13608 $3\core_core_fast2_ok$next[0:0]$13726 + assign $1\core_core_fasto1$next[2:0]$13609 $3\core_core_fasto1$next[2:0]$13727 + assign $1\core_core_fasto2$next[2:0]$13610 $3\core_core_fasto2$next[2:0]$13728 + assign $1\core_core_lk$next[0:0]$13611 $3\core_core_lk$next[0:0]$13729 + assign $1\core_core_reg1$next[4:0]$13612 $3\core_core_reg1$next[4:0]$13730 + assign $1\core_core_reg1_ok$next[0:0]$13613 $3\core_core_reg1_ok$next[0:0]$13731 + assign $1\core_core_reg2$next[4:0]$13614 $3\core_core_reg2$next[4:0]$13732 + assign $1\core_core_reg2_ok$next[0:0]$13615 $3\core_core_reg2_ok$next[0:0]$13733 + assign $1\core_core_reg3$next[4:0]$13616 $3\core_core_reg3$next[4:0]$13734 + assign $1\core_core_reg3_ok$next[0:0]$13617 $3\core_core_reg3_ok$next[0:0]$13735 + assign $1\core_core_rego$next[4:0]$13618 $3\core_core_rego$next[4:0]$13736 + assign $1\core_core_spr1$next[9:0]$13619 $3\core_core_spr1$next[9:0]$13737 + assign $1\core_core_spr1_ok$next[0:0]$13620 $3\core_core_spr1_ok$next[0:0]$13738 + assign $1\core_core_spro$next[9:0]$13621 $3\core_core_spro$next[9:0]$13739 + assign $1\core_core_xer_in$next[2:0]$13622 $3\core_core_xer_in$next[2:0]$13740 + assign $1\core_cr_out_ok$next[0:0]$13623 $3\core_cr_out_ok$next[0:0]$13741 + assign $1\core_ea_ok$next[0:0]$13624 $3\core_ea_ok$next[0:0]$13742 + assign $1\core_fasto1_ok$next[0:0]$13625 $3\core_fasto1_ok$next[0:0]$13743 + assign $1\core_fasto2_ok$next[0:0]$13626 $3\core_fasto2_ok$next[0:0]$13744 + assign $1\core_rego_ok$next[0:0]$13627 $3\core_rego_ok$next[0:0]$13745 + assign $1\core_spro_ok$next[0:0]$13628 $3\core_spro_ok$next[0:0]$13746 + assign $1\core_xer_out$next[0:0]$13629 $3\core_xer_out$next[0:0]$13747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -380559,112 +390918,136 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign { $3\core_core_core_is_32bit$next[0:0]$13226 $3\core_core_cr_wr_ok$next[0:0]$13241 $3\core_core_core_cr_wr$next[7:0]$13221 $3\core_core_core_cr_rd_ok$next[0:0]$13220 $3\core_core_core_cr_rd$next[7:0]$13219 $3\core_core_core_trapaddr$next[12:0]$13232 $3\core_core_core_traptype$next[6:0]$13233 $3\core_core_core_input_carry$next[1:0]$13223 $3\core_core_core_oe_ok$next[0:0]$13229 $3\core_core_core_oe$next[0:0]$13228 $3\core_core_core_rc_ok$next[0:0]$13231 $3\core_core_core_rc$next[0:0]$13230 $3\core_core_lk$next[0:0]$13249 $3\core_core_core_fn_unit$next[11:0]$13222 $3\core_core_core_insn_type$next[6:0]$13225 $3\core_core_core_insn$next[31:0]$13224 $3\core_core_core_cia$next[63:0]$13218 $3\core_core_core_msr$next[63:0]$13227 $3\core_cr_out_ok$next[0:0]$13261 $3\core_core_cr_out$next[2:0]$13240 $3\core_core_cr_in2_ok$2$next[0:0]$13238 $3\core_core_cr_in2$1$next[2:0]$13236 $3\core_core_cr_in2_ok$next[0:0]$13239 $3\core_core_cr_in2$next[2:0]$13237 $3\core_core_cr_in1_ok$next[0:0]$13235 $3\core_core_cr_in1$next[2:0]$13234 $3\core_fasto2_ok$next[0:0]$13264 $3\core_core_fasto2$next[2:0]$13248 $3\core_fasto1_ok$next[0:0]$13263 $3\core_core_fasto1$next[2:0]$13247 $3\core_core_fast2_ok$next[0:0]$13246 $3\core_core_fast2$next[2:0]$13245 $3\core_core_fast1_ok$next[0:0]$13244 $3\core_core_fast1$next[2:0]$13243 $3\core_xer_out$next[0:0]$13267 $3\core_core_xer_in$next[2:0]$13260 $3\core_core_spr1_ok$next[0:0]$13258 $3\core_core_spr1$next[9:0]$13257 $3\core_spro_ok$next[0:0]$13266 $3\core_core_spro$next[9:0]$13259 $3\core_core_reg3_ok$next[0:0]$13255 $3\core_core_reg3$next[4:0]$13254 $3\core_core_reg2_ok$next[0:0]$13253 $3\core_core_reg2$next[4:0]$13252 $3\core_core_reg1_ok$next[0:0]$13251 $3\core_core_reg1$next[4:0]$13250 $3\core_ea_ok$next[0:0]$13262 $3\core_core_ea$next[4:0]$13242 $3\core_rego_ok$next[0:0]$13265 $3\core_core_rego$next[4:0]$13256 $3\core_asmcode$next[7:0]$13217 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_core_is_32bit$next[0:0]$13706 $3\core_core_cr_wr_ok$next[0:0]$13721 $3\core_core_core_cr_wr$next[7:0]$13693 $3\core_core_core_cr_rd_ok$next[0:0]$13692 $3\core_core_core_cr_rd$next[7:0]$13691 $3\core_core_core_trapaddr$next[12:0]$13712 $3\core_core_core_exc_$signal$9$next[0:0]$13700 $3\core_core_core_exc_$signal$8$next[0:0]$13699 $3\core_core_core_exc_$signal$7$next[0:0]$13698 $3\core_core_core_exc_$signal$6$next[0:0]$13697 $3\core_core_core_exc_$signal$5$next[0:0]$13696 $3\core_core_core_exc_$signal$4$next[0:0]$13695 $3\core_core_core_exc_$signal$3$next[0:0]$13694 $3\core_core_core_exc_$signal$next[0:0]$13701 $3\core_core_core_traptype$next[7:0]$13713 $3\core_core_core_input_carry$next[1:0]$13703 $3\core_core_core_oe_ok$next[0:0]$13709 $3\core_core_core_oe$next[0:0]$13708 $3\core_core_core_rc_ok$next[0:0]$13711 $3\core_core_core_rc$next[0:0]$13710 $3\core_core_lk$next[0:0]$13729 $3\core_core_core_fn_unit$next[11:0]$13702 $3\core_core_core_insn_type$next[6:0]$13705 $3\core_core_core_insn$next[31:0]$13704 $3\core_core_core_cia$next[63:0]$13690 $3\core_core_core_msr$next[63:0]$13707 $3\core_cr_out_ok$next[0:0]$13741 $3\core_core_cr_out$next[2:0]$13720 $3\core_core_cr_in2_ok$2$next[0:0]$13718 $3\core_core_cr_in2$1$next[2:0]$13716 $3\core_core_cr_in2_ok$next[0:0]$13719 $3\core_core_cr_in2$next[2:0]$13717 $3\core_core_cr_in1_ok$next[0:0]$13715 $3\core_core_cr_in1$next[2:0]$13714 $3\core_fasto2_ok$next[0:0]$13744 $3\core_core_fasto2$next[2:0]$13728 $3\core_fasto1_ok$next[0:0]$13743 $3\core_core_fasto1$next[2:0]$13727 $3\core_core_fast2_ok$next[0:0]$13726 $3\core_core_fast2$next[2:0]$13725 $3\core_core_fast1_ok$next[0:0]$13724 $3\core_core_fast1$next[2:0]$13723 $3\core_xer_out$next[0:0]$13747 $3\core_core_xer_in$next[2:0]$13740 $3\core_core_spr1_ok$next[0:0]$13738 $3\core_core_spr1$next[9:0]$13737 $3\core_spro_ok$next[0:0]$13746 $3\core_core_spro$next[9:0]$13739 $3\core_core_reg3_ok$next[0:0]$13735 $3\core_core_reg3$next[4:0]$13734 $3\core_core_reg2_ok$next[0:0]$13733 $3\core_core_reg2$next[4:0]$13732 $3\core_core_reg1_ok$next[0:0]$13731 $3\core_core_reg1$next[4:0]$13730 $3\core_ea_ok$next[0:0]$13742 $3\core_core_ea$next[4:0]$13722 $3\core_rego_ok$next[0:0]$13745 $3\core_core_rego$next[4:0]$13736 $3\core_asmcode$next[7:0]$13689 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $3\core_asmcode$next[7:0]$13217 \core_asmcode - assign $3\core_core_core_cia$next[63:0]$13218 \core_core_core_cia - assign $3\core_core_core_cr_rd$next[7:0]$13219 \core_core_core_cr_rd - assign $3\core_core_core_cr_rd_ok$next[0:0]$13220 \core_core_core_cr_rd_ok - assign $3\core_core_core_cr_wr$next[7:0]$13221 \core_core_core_cr_wr - assign $3\core_core_core_fn_unit$next[11:0]$13222 \core_core_core_fn_unit - assign $3\core_core_core_input_carry$next[1:0]$13223 \core_core_core_input_carry - assign $3\core_core_core_insn$next[31:0]$13224 \core_core_core_insn - assign $3\core_core_core_insn_type$next[6:0]$13225 \core_core_core_insn_type - assign $3\core_core_core_is_32bit$next[0:0]$13226 \core_core_core_is_32bit - assign $3\core_core_core_msr$next[63:0]$13227 \core_core_core_msr - assign $3\core_core_core_oe$next[0:0]$13228 \core_core_core_oe - assign $3\core_core_core_oe_ok$next[0:0]$13229 \core_core_core_oe_ok - assign $3\core_core_core_rc$next[0:0]$13230 \core_core_core_rc - assign $3\core_core_core_rc_ok$next[0:0]$13231 \core_core_core_rc_ok - assign $3\core_core_core_trapaddr$next[12:0]$13232 \core_core_core_trapaddr - assign $3\core_core_core_traptype$next[6:0]$13233 \core_core_core_traptype - assign $3\core_core_cr_in1$next[2:0]$13234 \core_core_cr_in1 - assign $3\core_core_cr_in1_ok$next[0:0]$13235 \core_core_cr_in1_ok - assign $3\core_core_cr_in2$1$next[2:0]$13236 \core_core_cr_in2$1 - assign $3\core_core_cr_in2$next[2:0]$13237 \core_core_cr_in2 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13238 \core_core_cr_in2_ok$2 - assign $3\core_core_cr_in2_ok$next[0:0]$13239 \core_core_cr_in2_ok - assign $3\core_core_cr_out$next[2:0]$13240 \core_core_cr_out - assign $3\core_core_cr_wr_ok$next[0:0]$13241 \core_core_cr_wr_ok - assign $3\core_core_ea$next[4:0]$13242 \core_core_ea - assign $3\core_core_fast1$next[2:0]$13243 \core_core_fast1 - assign $3\core_core_fast1_ok$next[0:0]$13244 \core_core_fast1_ok - assign $3\core_core_fast2$next[2:0]$13245 \core_core_fast2 - assign $3\core_core_fast2_ok$next[0:0]$13246 \core_core_fast2_ok - assign $3\core_core_fasto1$next[2:0]$13247 \core_core_fasto1 - assign $3\core_core_fasto2$next[2:0]$13248 \core_core_fasto2 - assign $3\core_core_lk$next[0:0]$13249 \core_core_lk - assign $3\core_core_reg1$next[4:0]$13250 \core_core_reg1 - assign $3\core_core_reg1_ok$next[0:0]$13251 \core_core_reg1_ok - assign $3\core_core_reg2$next[4:0]$13252 \core_core_reg2 - assign $3\core_core_reg2_ok$next[0:0]$13253 \core_core_reg2_ok - assign $3\core_core_reg3$next[4:0]$13254 \core_core_reg3 - assign $3\core_core_reg3_ok$next[0:0]$13255 \core_core_reg3_ok - assign $3\core_core_rego$next[4:0]$13256 \core_core_rego - assign $3\core_core_spr1$next[9:0]$13257 \core_core_spr1 - assign $3\core_core_spr1_ok$next[0:0]$13258 \core_core_spr1_ok - assign $3\core_core_spro$next[9:0]$13259 \core_core_spro - assign $3\core_core_xer_in$next[2:0]$13260 \core_core_xer_in - assign $3\core_cr_out_ok$next[0:0]$13261 \core_cr_out_ok - assign $3\core_ea_ok$next[0:0]$13262 \core_ea_ok - assign $3\core_fasto1_ok$next[0:0]$13263 \core_fasto1_ok - assign $3\core_fasto2_ok$next[0:0]$13264 \core_fasto2_ok - assign $3\core_rego_ok$next[0:0]$13265 \core_rego_ok - assign $3\core_spro_ok$next[0:0]$13266 \core_spro_ok - assign $3\core_xer_out$next[0:0]$13267 \core_xer_out + assign $3\core_asmcode$next[7:0]$13689 \core_asmcode + assign $3\core_core_core_cia$next[63:0]$13690 \core_core_core_cia + assign $3\core_core_core_cr_rd$next[7:0]$13691 \core_core_core_cr_rd + assign $3\core_core_core_cr_rd_ok$next[0:0]$13692 \core_core_core_cr_rd_ok + assign $3\core_core_core_cr_wr$next[7:0]$13693 \core_core_core_cr_wr + assign $3\core_core_core_exc_$signal$3$next[0:0]$13694 \core_core_core_exc_$signal$3 + assign $3\core_core_core_exc_$signal$4$next[0:0]$13695 \core_core_core_exc_$signal$4 + assign $3\core_core_core_exc_$signal$5$next[0:0]$13696 \core_core_core_exc_$signal$5 + assign $3\core_core_core_exc_$signal$6$next[0:0]$13697 \core_core_core_exc_$signal$6 + assign $3\core_core_core_exc_$signal$7$next[0:0]$13698 \core_core_core_exc_$signal$7 + assign $3\core_core_core_exc_$signal$8$next[0:0]$13699 \core_core_core_exc_$signal$8 + assign $3\core_core_core_exc_$signal$9$next[0:0]$13700 \core_core_core_exc_$signal$9 + assign $3\core_core_core_exc_$signal$next[0:0]$13701 \core_core_core_exc_$signal + assign $3\core_core_core_fn_unit$next[11:0]$13702 \core_core_core_fn_unit + assign $3\core_core_core_input_carry$next[1:0]$13703 \core_core_core_input_carry + assign $3\core_core_core_insn$next[31:0]$13704 \core_core_core_insn + assign $3\core_core_core_insn_type$next[6:0]$13705 \core_core_core_insn_type + assign $3\core_core_core_is_32bit$next[0:0]$13706 \core_core_core_is_32bit + assign $3\core_core_core_msr$next[63:0]$13707 \core_core_core_msr + assign $3\core_core_core_oe$next[0:0]$13708 \core_core_core_oe + assign $3\core_core_core_oe_ok$next[0:0]$13709 \core_core_core_oe_ok + assign $3\core_core_core_rc$next[0:0]$13710 \core_core_core_rc + assign $3\core_core_core_rc_ok$next[0:0]$13711 \core_core_core_rc_ok + assign $3\core_core_core_trapaddr$next[12:0]$13712 \core_core_core_trapaddr + assign $3\core_core_core_traptype$next[7:0]$13713 \core_core_core_traptype + assign $3\core_core_cr_in1$next[2:0]$13714 \core_core_cr_in1 + assign $3\core_core_cr_in1_ok$next[0:0]$13715 \core_core_cr_in1_ok + assign $3\core_core_cr_in2$1$next[2:0]$13716 \core_core_cr_in2$1 + assign $3\core_core_cr_in2$next[2:0]$13717 \core_core_cr_in2 + assign $3\core_core_cr_in2_ok$2$next[0:0]$13718 \core_core_cr_in2_ok$2 + assign $3\core_core_cr_in2_ok$next[0:0]$13719 \core_core_cr_in2_ok + assign $3\core_core_cr_out$next[2:0]$13720 \core_core_cr_out + assign $3\core_core_cr_wr_ok$next[0:0]$13721 \core_core_cr_wr_ok + assign $3\core_core_ea$next[4:0]$13722 \core_core_ea + assign $3\core_core_fast1$next[2:0]$13723 \core_core_fast1 + assign $3\core_core_fast1_ok$next[0:0]$13724 \core_core_fast1_ok + assign $3\core_core_fast2$next[2:0]$13725 \core_core_fast2 + assign $3\core_core_fast2_ok$next[0:0]$13726 \core_core_fast2_ok + assign $3\core_core_fasto1$next[2:0]$13727 \core_core_fasto1 + assign $3\core_core_fasto2$next[2:0]$13728 \core_core_fasto2 + assign $3\core_core_lk$next[0:0]$13729 \core_core_lk + assign $3\core_core_reg1$next[4:0]$13730 \core_core_reg1 + assign $3\core_core_reg1_ok$next[0:0]$13731 \core_core_reg1_ok + assign $3\core_core_reg2$next[4:0]$13732 \core_core_reg2 + assign $3\core_core_reg2_ok$next[0:0]$13733 \core_core_reg2_ok + assign $3\core_core_reg3$next[4:0]$13734 \core_core_reg3 + assign $3\core_core_reg3_ok$next[0:0]$13735 \core_core_reg3_ok + assign $3\core_core_rego$next[4:0]$13736 \core_core_rego + assign $3\core_core_spr1$next[9:0]$13737 \core_core_spr1 + assign $3\core_core_spr1_ok$next[0:0]$13738 \core_core_spr1_ok + assign $3\core_core_spro$next[9:0]$13739 \core_core_spro + assign $3\core_core_xer_in$next[2:0]$13740 \core_core_xer_in + assign $3\core_cr_out_ok$next[0:0]$13741 \core_cr_out_ok + assign $3\core_ea_ok$next[0:0]$13742 \core_ea_ok + assign $3\core_fasto1_ok$next[0:0]$13743 \core_fasto1_ok + assign $3\core_fasto2_ok$next[0:0]$13744 \core_fasto2_ok + assign $3\core_rego_ok$next[0:0]$13745 \core_rego_ok + assign $3\core_spro_ok$next[0:0]$13746 \core_spro_ok + assign $3\core_xer_out$next[0:0]$13747 \core_xer_out end case - assign $1\core_asmcode$next[7:0]$13115 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13116 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13117 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13118 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13119 \core_core_core_cr_wr - assign $1\core_core_core_fn_unit$next[11:0]$13120 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13121 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13122 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13123 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13124 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13125 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13126 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13127 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13128 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13129 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13130 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[6:0]$13131 \core_core_core_traptype - assign $1\core_core_cr_in1$next[2:0]$13132 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13133 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[2:0]$13134 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[2:0]$13135 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13136 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13137 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[2:0]$13138 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13139 \core_core_cr_wr_ok - assign $1\core_core_ea$next[4:0]$13140 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13141 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13142 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13143 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13144 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13145 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13146 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13147 \core_core_lk - assign $1\core_core_reg1$next[4:0]$13148 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13149 \core_core_reg1_ok - assign $1\core_core_reg2$next[4:0]$13150 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13151 \core_core_reg2_ok - assign $1\core_core_reg3$next[4:0]$13152 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13153 \core_core_reg3_ok - assign $1\core_core_rego$next[4:0]$13154 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13155 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13156 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13157 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13158 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13159 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13160 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13161 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13162 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13163 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13164 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13165 \core_xer_out + assign $1\core_asmcode$next[7:0]$13571 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13572 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13573 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13575 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13583 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[11:0]$13584 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13585 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13586 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13587 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13588 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13589 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13590 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13591 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13592 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13593 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13594 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13595 \core_core_core_traptype + assign $1\core_core_cr_in1$next[2:0]$13596 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13597 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[2:0]$13598 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[2:0]$13599 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13601 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[2:0]$13602 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13603 \core_core_cr_wr_ok + assign $1\core_core_ea$next[4:0]$13604 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13605 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13606 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13607 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13608 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13609 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13610 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13611 \core_core_lk + assign $1\core_core_reg1$next[4:0]$13612 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13613 \core_core_reg1_ok + assign $1\core_core_reg2$next[4:0]$13614 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13615 \core_core_reg2_ok + assign $1\core_core_reg3$next[4:0]$13616 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13617 \core_core_reg3_ok + assign $1\core_core_rego$next[4:0]$13618 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13619 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13620 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13621 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13622 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13623 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13624 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13625 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13626 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13627 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13628 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13629 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -380689,107 +391072,139 @@ module \test_issuer assign { } { } assign { } { } assign { } { } - assign $4\core_rego_ok$next[0:0]$13285 1'0 - assign $4\core_ea_ok$next[0:0]$13282 1'0 - assign $4\core_core_reg1_ok$next[0:0]$13277 1'0 - assign $4\core_core_reg2_ok$next[0:0]$13278 1'0 - assign $4\core_core_reg3_ok$next[0:0]$13279 1'0 - assign $4\core_spro_ok$next[0:0]$13286 1'0 - assign $4\core_core_spr1_ok$next[0:0]$13280 1'0 - assign $4\core_core_fast1_ok$next[0:0]$13275 1'0 - assign $4\core_core_fast2_ok$next[0:0]$13276 1'0 - assign $4\core_fasto1_ok$next[0:0]$13283 1'0 - assign $4\core_fasto2_ok$next[0:0]$13284 1'0 - assign $4\core_core_cr_in1_ok$next[0:0]$13271 1'0 - assign $4\core_core_cr_in2_ok$next[0:0]$13273 1'0 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13272 1'0 - assign $4\core_cr_out_ok$next[0:0]$13281 1'0 - assign $4\core_core_core_rc_ok$next[0:0]$13270 1'0 - assign $4\core_core_core_oe_ok$next[0:0]$13269 1'0 - assign $4\core_core_core_cr_rd_ok$next[0:0]$13268 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$13274 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$13773 1'0 + assign $4\core_ea_ok$next[0:0]$13770 1'0 + assign $4\core_core_reg1_ok$next[0:0]$13765 1'0 + assign $4\core_core_reg2_ok$next[0:0]$13766 1'0 + assign $4\core_core_reg3_ok$next[0:0]$13767 1'0 + assign $4\core_spro_ok$next[0:0]$13774 1'0 + assign $4\core_core_spr1_ok$next[0:0]$13768 1'0 + assign $4\core_core_fast1_ok$next[0:0]$13763 1'0 + assign $4\core_core_fast2_ok$next[0:0]$13764 1'0 + assign $4\core_fasto1_ok$next[0:0]$13771 1'0 + assign $4\core_fasto2_ok$next[0:0]$13772 1'0 + assign $4\core_core_cr_in1_ok$next[0:0]$13759 1'0 + assign $4\core_core_cr_in2_ok$next[0:0]$13761 1'0 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13760 1'0 + assign $4\core_cr_out_ok$next[0:0]$13769 1'0 + assign $4\core_core_core_rc_ok$next[0:0]$13758 1'0 + assign $4\core_core_core_oe_ok$next[0:0]$13757 1'0 + assign $4\core_core_core_exc_$signal$next[0:0]$13756 1'0 + assign $4\core_core_core_exc_$signal$3$next[0:0]$13749 1'0 + assign $4\core_core_core_exc_$signal$4$next[0:0]$13750 1'0 + assign $4\core_core_core_exc_$signal$5$next[0:0]$13751 1'0 + assign $4\core_core_core_exc_$signal$6$next[0:0]$13752 1'0 + assign $4\core_core_core_exc_$signal$7$next[0:0]$13753 1'0 + assign $4\core_core_core_exc_$signal$8$next[0:0]$13754 1'0 + assign $4\core_core_core_exc_$signal$9$next[0:0]$13755 1'0 + assign $4\core_core_core_cr_rd_ok$next[0:0]$13748 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$13762 1'0 case - assign $4\core_core_core_cr_rd_ok$next[0:0]$13268 $1\core_core_core_cr_rd_ok$next[0:0]$13118 - assign $4\core_core_core_oe_ok$next[0:0]$13269 $1\core_core_core_oe_ok$next[0:0]$13127 - assign $4\core_core_core_rc_ok$next[0:0]$13270 $1\core_core_core_rc_ok$next[0:0]$13129 - assign $4\core_core_cr_in1_ok$next[0:0]$13271 $1\core_core_cr_in1_ok$next[0:0]$13133 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13272 $1\core_core_cr_in2_ok$2$next[0:0]$13136 - assign $4\core_core_cr_in2_ok$next[0:0]$13273 $1\core_core_cr_in2_ok$next[0:0]$13137 - assign $4\core_core_cr_wr_ok$next[0:0]$13274 $1\core_core_cr_wr_ok$next[0:0]$13139 - assign $4\core_core_fast1_ok$next[0:0]$13275 $1\core_core_fast1_ok$next[0:0]$13142 - assign $4\core_core_fast2_ok$next[0:0]$13276 $1\core_core_fast2_ok$next[0:0]$13144 - assign $4\core_core_reg1_ok$next[0:0]$13277 $1\core_core_reg1_ok$next[0:0]$13149 - assign $4\core_core_reg2_ok$next[0:0]$13278 $1\core_core_reg2_ok$next[0:0]$13151 - assign $4\core_core_reg3_ok$next[0:0]$13279 $1\core_core_reg3_ok$next[0:0]$13153 - assign $4\core_core_spr1_ok$next[0:0]$13280 $1\core_core_spr1_ok$next[0:0]$13156 - assign $4\core_cr_out_ok$next[0:0]$13281 $1\core_cr_out_ok$next[0:0]$13159 - assign $4\core_ea_ok$next[0:0]$13282 $1\core_ea_ok$next[0:0]$13160 - assign $4\core_fasto1_ok$next[0:0]$13283 $1\core_fasto1_ok$next[0:0]$13161 - assign $4\core_fasto2_ok$next[0:0]$13284 $1\core_fasto2_ok$next[0:0]$13162 - assign $4\core_rego_ok$next[0:0]$13285 $1\core_rego_ok$next[0:0]$13163 - assign $4\core_spro_ok$next[0:0]$13286 $1\core_spro_ok$next[0:0]$13164 + assign $4\core_core_core_cr_rd_ok$next[0:0]$13748 $1\core_core_core_cr_rd_ok$next[0:0]$13574 + assign $4\core_core_core_exc_$signal$3$next[0:0]$13749 $1\core_core_core_exc_$signal$3$next[0:0]$13576 + assign $4\core_core_core_exc_$signal$4$next[0:0]$13750 $1\core_core_core_exc_$signal$4$next[0:0]$13577 + assign $4\core_core_core_exc_$signal$5$next[0:0]$13751 $1\core_core_core_exc_$signal$5$next[0:0]$13578 + assign $4\core_core_core_exc_$signal$6$next[0:0]$13752 $1\core_core_core_exc_$signal$6$next[0:0]$13579 + assign $4\core_core_core_exc_$signal$7$next[0:0]$13753 $1\core_core_core_exc_$signal$7$next[0:0]$13580 + assign $4\core_core_core_exc_$signal$8$next[0:0]$13754 $1\core_core_core_exc_$signal$8$next[0:0]$13581 + assign $4\core_core_core_exc_$signal$9$next[0:0]$13755 $1\core_core_core_exc_$signal$9$next[0:0]$13582 + assign $4\core_core_core_exc_$signal$next[0:0]$13756 $1\core_core_core_exc_$signal$next[0:0]$13583 + assign $4\core_core_core_oe_ok$next[0:0]$13757 $1\core_core_core_oe_ok$next[0:0]$13591 + assign $4\core_core_core_rc_ok$next[0:0]$13758 $1\core_core_core_rc_ok$next[0:0]$13593 + assign $4\core_core_cr_in1_ok$next[0:0]$13759 $1\core_core_cr_in1_ok$next[0:0]$13597 + assign $4\core_core_cr_in2_ok$2$next[0:0]$13760 $1\core_core_cr_in2_ok$2$next[0:0]$13600 + assign $4\core_core_cr_in2_ok$next[0:0]$13761 $1\core_core_cr_in2_ok$next[0:0]$13601 + assign $4\core_core_cr_wr_ok$next[0:0]$13762 $1\core_core_cr_wr_ok$next[0:0]$13603 + assign $4\core_core_fast1_ok$next[0:0]$13763 $1\core_core_fast1_ok$next[0:0]$13606 + assign $4\core_core_fast2_ok$next[0:0]$13764 $1\core_core_fast2_ok$next[0:0]$13608 + assign $4\core_core_reg1_ok$next[0:0]$13765 $1\core_core_reg1_ok$next[0:0]$13613 + assign $4\core_core_reg2_ok$next[0:0]$13766 $1\core_core_reg2_ok$next[0:0]$13615 + assign $4\core_core_reg3_ok$next[0:0]$13767 $1\core_core_reg3_ok$next[0:0]$13617 + assign $4\core_core_spr1_ok$next[0:0]$13768 $1\core_core_spr1_ok$next[0:0]$13620 + assign $4\core_cr_out_ok$next[0:0]$13769 $1\core_cr_out_ok$next[0:0]$13623 + assign $4\core_ea_ok$next[0:0]$13770 $1\core_ea_ok$next[0:0]$13624 + assign $4\core_fasto1_ok$next[0:0]$13771 $1\core_fasto1_ok$next[0:0]$13625 + assign $4\core_fasto2_ok$next[0:0]$13772 $1\core_fasto2_ok$next[0:0]$13626 + assign $4\core_rego_ok$next[0:0]$13773 $1\core_rego_ok$next[0:0]$13627 + assign $4\core_spro_ok$next[0:0]$13774 $1\core_spro_ok$next[0:0]$13628 end sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13064 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13065 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13066 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13067 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13068 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13069 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13070 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13071 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13072 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13073 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13074 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13075 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13076 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13077 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13078 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13079 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[6:0]$13080 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13081 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13082 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13083 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13084 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13085 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13086 - update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13087 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13088 - update \core_core_ea$next $0\core_core_ea$next[4:0]$13089 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13090 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13091 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13092 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13093 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13094 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13095 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13096 - update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13097 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13098 - update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13099 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13100 - update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13101 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13102 - update \core_core_rego$next $0\core_core_rego$next[4:0]$13103 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13104 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13105 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13106 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13107 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13108 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13109 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13110 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13111 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13112 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13113 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13114 - end - attribute \src "libresoc.v:181163.3-181171.6" - process $proc$libresoc.v:181163$13287 - assign { } { } - assign { } { } - assign $0\jtag_dmi0_ack_o$next[0:0]$13288 $1\jtag_dmi0_ack_o$next[0:0]$13289 - attribute \src "libresoc.v:181164.5-181164.29" - switch \initial - attribute \src "libresoc.v:181164.9-181164.17" + update \core_asmcode$next $0\core_asmcode$next[7:0]$13512 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13513 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13514 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13515 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13516 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13517 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13518 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13519 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13520 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13521 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13522 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13523 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13524 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13525 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13526 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13527 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13528 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13529 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13530 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13531 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13532 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13533 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13534 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13535 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13536 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13537 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13538 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13539 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13540 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13541 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13542 + update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13543 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13544 + update \core_core_ea$next $0\core_core_ea$next[4:0]$13545 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13546 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13547 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13548 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13549 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13550 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13551 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13552 + update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13553 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13554 + update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13555 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13556 + update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13557 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13558 + update \core_core_rego$next $0\core_core_rego$next[4:0]$13559 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13560 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13561 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13562 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13563 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13564 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13565 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13566 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13567 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13568 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13569 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13570 + end + attribute \src "libresoc.v:186564.3-186572.6" + process $proc$libresoc.v:186564$13775 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$13776 $1\jtag_dmi0__ack_o$next[0:0]$13777 + attribute \src "libresoc.v:186565.5-186565.29" + switch \initial + attribute \src "libresoc.v:186565.9-186565.17" case 1'1 case end @@ -380798,21 +391213,21 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0_ack_o$next[0:0]$13289 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13777 1'0 case - assign $1\jtag_dmi0_ack_o$next[0:0]$13289 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13777 \dbg_dmi_ack_o end sync always - update \jtag_dmi0_ack_o$next $0\jtag_dmi0_ack_o$next[0:0]$13288 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13776 end - attribute \src "libresoc.v:181172.3-181180.6" - process $proc$libresoc.v:181172$13290 + attribute \src "libresoc.v:186573.3-186581.6" + process $proc$libresoc.v:186573$13778 assign { } { } assign { } { } - assign $0\jtag_dmi0_dout$next[63:0]$13291 $1\jtag_dmi0_dout$next[63:0]$13292 - attribute \src "libresoc.v:181173.5-181173.29" + assign $0\jtag_dmi0__dout$next[63:0]$13779 $1\jtag_dmi0__dout$next[63:0]$13780 + attribute \src "libresoc.v:186574.5-186574.29" switch \initial - attribute \src "libresoc.v:181173.9-181173.17" + attribute \src "libresoc.v:186574.9-186574.17" case 1'1 case end @@ -380821,21 +391236,21 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0_dout$next[63:0]$13292 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13780 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0_dout$next[63:0]$13292 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13780 \dbg_dmi_dout end sync always - update \jtag_dmi0_dout$next $0\jtag_dmi0_dout$next[63:0]$13291 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13779 end - attribute \src "libresoc.v:181181.3-181189.6" - process $proc$libresoc.v:181181$13293 + attribute \src "libresoc.v:186582.3-186590.6" + process $proc$libresoc.v:186582$13781 assign { } { } assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13294 $1\dec2_cur_eint$next[0:0]$13295 - attribute \src "libresoc.v:181182.5-181182.29" + assign $0\dec2_cur_eint$next[0:0]$13782 $1\dec2_cur_eint$next[0:0]$13783 + attribute \src "libresoc.v:186583.5-186583.29" switch \initial - attribute \src "libresoc.v:181182.9-181182.17" + attribute \src "libresoc.v:186583.9-186583.17" case 1'1 case end @@ -380844,152 +391259,175 @@ module \test_issuer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13295 1'0 + assign $1\dec2_cur_eint$next[0:0]$13783 1'0 case - assign $1\dec2_cur_eint$next[0:0]$13295 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$13783 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13294 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13782 end - attribute \src "libresoc.v:181190.3-181226.6" - process $proc$libresoc.v:181190$13296 + attribute \src "libresoc.v:186591.3-186600.6" + process $proc$libresoc.v:186591$13784 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13785 $1\delay$next[1:0]$13786 + attribute \src "libresoc.v:186592.5-186592.29" + switch \initial + attribute \src "libresoc.v:186592.9-186592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13786 \$23 [1:0] + case + assign $1\delay$next[1:0]$13786 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$13785 + end + attribute \src "libresoc.v:186601.3-186637.6" + process $proc$libresoc.v:186601$13787 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13297 $4\core_raw_insn_i$next[31:0]$13301 - attribute \src "libresoc.v:181191.5-181191.29" + assign $0\core_raw_insn_i$next[31:0]$13788 $4\core_raw_insn_i$next[31:0]$13792 + attribute \src "libresoc.v:186602.5-186602.29" switch \initial - attribute \src "libresoc.v:181191.9-181191.17" + attribute \src "libresoc.v:186602.9-186602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13298 0 + assign $1\core_raw_insn_i$next[31:0]$13789 0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13298 $2\core_raw_insn_i$next[31:0]$13299 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + assign $1\core_raw_insn_i$next[31:0]$13789 $2\core_raw_insn_i$next[31:0]$13790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\core_raw_insn_i$next[31:0]$13299 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13790 \core_raw_insn_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13299 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13790 \dec2_raw_opcode_in end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13298 $3\core_raw_insn_i$next[31:0]$13300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$45 + assign $1\core_raw_insn_i$next[31:0]$13789 $3\core_raw_insn_i$next[31:0]$13791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$61 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13300 0 + assign $3\core_raw_insn_i$next[31:0]$13791 0 case - assign $3\core_raw_insn_i$next[31:0]$13300 \core_raw_insn_i + assign $3\core_raw_insn_i$next[31:0]$13791 \core_raw_insn_i end case - assign $1\core_raw_insn_i$next[31:0]$13298 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13789 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\core_raw_insn_i$next[31:0]$13301 0 + assign $4\core_raw_insn_i$next[31:0]$13792 0 case - assign $4\core_raw_insn_i$next[31:0]$13301 $1\core_raw_insn_i$next[31:0]$13298 + assign $4\core_raw_insn_i$next[31:0]$13792 $1\core_raw_insn_i$next[31:0]$13789 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13297 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13788 end - attribute \src "libresoc.v:181227.3-181263.6" - process $proc$libresoc.v:181227$13302 + attribute \src "libresoc.v:186638.3-186674.6" + process $proc$libresoc.v:186638$13793 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$3$next[0:0]$13303 $4\core_bigendian_i$3$next[0:0]$13307 - attribute \src "libresoc.v:181228.5-181228.29" + assign $0\core_bigendian_i$10$next[0:0]$13794 $4\core_bigendian_i$10$next[0:0]$13798 + attribute \src "libresoc.v:186639.5-186639.29" switch \initial - attribute \src "libresoc.v:181228.9-181228.17" + attribute \src "libresoc.v:186639.9-186639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$13304 1'0 + assign $1\core_bigendian_i$10$next[0:0]$13795 1'0 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$13304 $2\core_bigendian_i$3$next[0:0]$13305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + assign $1\core_bigendian_i$10$next[0:0]$13795 $2\core_bigendian_i$10$next[0:0]$13796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\core_bigendian_i$3$next[0:0]$13305 \core_bigendian_i$3 + assign $2\core_bigendian_i$10$next[0:0]$13796 \core_bigendian_i$10 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\core_bigendian_i$3$next[0:0]$13305 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13796 \core_bigendian_i end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_bigendian_i$3$next[0:0]$13304 $3\core_bigendian_i$3$next[0:0]$13306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$47 + assign $1\core_bigendian_i$10$next[0:0]$13795 $3\core_bigendian_i$10$next[0:0]$13797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$3$next[0:0]$13306 1'0 + assign $3\core_bigendian_i$10$next[0:0]$13797 1'0 case - assign $3\core_bigendian_i$3$next[0:0]$13306 \core_bigendian_i$3 + assign $3\core_bigendian_i$10$next[0:0]$13797 \core_bigendian_i$10 end case - assign $1\core_bigendian_i$3$next[0:0]$13304 \core_bigendian_i$3 + assign $1\core_bigendian_i$10$next[0:0]$13795 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\core_bigendian_i$3$next[0:0]$13307 1'0 + assign $4\core_bigendian_i$10$next[0:0]$13798 1'0 case - assign $4\core_bigendian_i$3$next[0:0]$13307 $1\core_bigendian_i$3$next[0:0]$13304 + assign $4\core_bigendian_i$10$next[0:0]$13798 $1\core_bigendian_i$10$next[0:0]$13795 end sync always - update \core_bigendian_i$3$next $0\core_bigendian_i$3$next[0:0]$13303 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13794 end - attribute \src "libresoc.v:181264.3-181279.6" - process $proc$libresoc.v:181264$13308 + attribute \src "libresoc.v:186675.3-186690.6" + process $proc$libresoc.v:186675$13799 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:181265.5-181265.29" + attribute \src "libresoc.v:186676.5-186676.29" switch \initial - attribute \src "libresoc.v:181265.9-181265.17" + attribute \src "libresoc.v:186676.9-186676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -381003,25 +391441,25 @@ module \test_issuer sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:181280.3-181304.6" - process $proc$libresoc.v:181280$13309 + attribute \src "libresoc.v:186691.3-186715.6" + process $proc$libresoc.v:186691$13800 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:181281.5-181281.29" + attribute \src "libresoc.v:186692.5-186692.29" switch \initial - attribute \src "libresoc.v:181281.9-181281.17" + attribute \src "libresoc.v:186692.9-186692.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$75 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -381033,7 +391471,7 @@ module \test_issuer case 2'01 assign { } { } assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -381048,25 +391486,25 @@ module \test_issuer sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:181305.3-181329.6" - process $proc$libresoc.v:181305$13310 + attribute \src "libresoc.v:186716.3-186740.6" + process $proc$libresoc.v:186716$13801 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:181306.5-181306.29" + attribute \src "libresoc.v:186717.5-186717.29" switch \initial - attribute \src "libresoc.v:181306.9-181306.17" + attribute \src "libresoc.v:186717.9-186717.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$81 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -381078,7 +391516,7 @@ module \test_issuer case 2'01 assign { } { } assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -381093,218 +391531,195 @@ module \test_issuer sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:181330.3-181350.6" - process $proc$libresoc.v:181330$13311 + attribute \src "libresoc.v:186741.3-186761.6" + process $proc$libresoc.v:186741$13802 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13312 $3\dec2_cur_pc$next[63:0]$13315 - attribute \src "libresoc.v:181331.5-181331.29" + assign $0\dec2_cur_pc$next[63:0]$13803 $3\dec2_cur_pc$next[63:0]$13806 + attribute \src "libresoc.v:186742.5-186742.29" switch \initial - attribute \src "libresoc.v:181331.9-181331.17" + attribute \src "libresoc.v:186742.9-186742.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13313 $2\dec2_cur_pc$next[63:0]$13314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$71 + assign $1\dec2_cur_pc$next[63:0]$13804 $2\dec2_cur_pc$next[63:0]$13805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13314 \pc + assign $2\dec2_cur_pc$next[63:0]$13805 \pc case - assign $2\dec2_cur_pc$next[63:0]$13314 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13805 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13313 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13804 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13315 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13806 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13315 $1\dec2_cur_pc$next[63:0]$13313 + assign $3\dec2_cur_pc$next[63:0]$13806 $1\dec2_cur_pc$next[63:0]$13804 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13312 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13803 end - attribute \src "libresoc.v:181351.3-181380.6" - process $proc$libresoc.v:181351$13316 + attribute \src "libresoc.v:186762.3-186791.6" + process $proc$libresoc.v:186762$13807 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13317 $4\msr_read$next[0:0]$13321 - attribute \src "libresoc.v:181352.5-181352.29" + assign $0\msr_read$next[0:0]$13808 $4\msr_read$next[0:0]$13812 + attribute \src "libresoc.v:186763.5-186763.29" switch \initial - attribute \src "libresoc.v:181352.9-181352.17" + attribute \src "libresoc.v:186763.9-186763.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13318 $2\msr_read$next[0:0]$13319 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$77 + assign $1\msr_read$next[0:0]$13809 $2\msr_read$next[0:0]$13810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$93 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13319 1'0 + assign $2\msr_read$next[0:0]$13810 1'0 case - assign $2\msr_read$next[0:0]$13319 \msr_read + assign $2\msr_read$next[0:0]$13810 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13318 $3\msr_read$next[0:0]$13320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" - switch \$79 + assign $1\msr_read$next[0:0]$13809 $3\msr_read$next[0:0]$13811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + switch \$95 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13320 1'1 + assign $3\msr_read$next[0:0]$13811 1'1 case - assign $3\msr_read$next[0:0]$13320 \msr_read + assign $3\msr_read$next[0:0]$13811 \msr_read end case - assign $1\msr_read$next[0:0]$13318 \msr_read + assign $1\msr_read$next[0:0]$13809 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13321 1'1 + assign $4\msr_read$next[0:0]$13812 1'1 case - assign $4\msr_read$next[0:0]$13321 $1\msr_read$next[0:0]$13318 + assign $4\msr_read$next[0:0]$13812 $1\msr_read$next[0:0]$13809 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13317 + update \msr_read$next $0\msr_read$next[0:0]$13808 end - attribute \src "libresoc.v:181381.3-181426.6" - process $proc$libresoc.v:181381$13322 + attribute \src "libresoc.v:186792.3-186837.6" + process $proc$libresoc.v:186792$13813 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13323 $5\fsm_state$next[1:0]$13328 - attribute \src "libresoc.v:181382.5-181382.29" + assign $0\fsm_state$next[1:0]$13814 $5\fsm_state$next[1:0]$13819 + attribute \src "libresoc.v:186793.5-186793.29" switch \initial - attribute \src "libresoc.v:181382.9-181382.17" + attribute \src "libresoc.v:186793.9-186793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13324 $2\fsm_state$next[1:0]$13325 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$85 + assign $1\fsm_state$next[1:0]$13815 $2\fsm_state$next[1:0]$13816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13325 2'01 + assign $2\fsm_state$next[1:0]$13816 2'01 case - assign $2\fsm_state$next[1:0]$13325 \fsm_state + assign $2\fsm_state$next[1:0]$13816 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13324 $3\fsm_state$next[1:0]$13326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" + assign $1\fsm_state$next[1:0]$13815 $3\fsm_state$next[1:0]$13817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fsm_state$next[1:0]$13326 \fsm_state + assign $3\fsm_state$next[1:0]$13817 \fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fsm_state$next[1:0]$13326 2'10 + assign $3\fsm_state$next[1:0]$13817 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13324 2'11 + assign $1\fsm_state$next[1:0]$13815 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13324 $4\fsm_state$next[1:0]$13327 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" - switch \$87 + assign $1\fsm_state$next[1:0]$13815 $4\fsm_state$next[1:0]$13818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$13327 2'00 + assign $4\fsm_state$next[1:0]$13818 2'00 case - assign $4\fsm_state$next[1:0]$13327 \fsm_state + assign $4\fsm_state$next[1:0]$13818 \fsm_state end case - assign $1\fsm_state$next[1:0]$13324 \fsm_state + assign $1\fsm_state$next[1:0]$13815 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$13328 2'00 - case - assign $5\fsm_state$next[1:0]$13328 $1\fsm_state$next[1:0]$13324 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13323 - end - attribute \src "libresoc.v:181427.3-181436.6" - process $proc$libresoc.v:181427$13329 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$13330 $1\delay$next[1:0]$13331 - attribute \src "libresoc.v:181428.5-181428.29" - switch \initial - attribute \src "libresoc.v:181428.9-181428.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:156" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$13331 \$9 [1:0] + assign $5\fsm_state$next[1:0]$13819 2'00 case - assign $1\delay$next[1:0]$13331 \delay + assign $5\fsm_state$next[1:0]$13819 $1\fsm_state$next[1:0]$13815 end sync always - update \delay$next $0\delay$next[1:0]$13330 + update \fsm_state$next $0\fsm_state$next[1:0]$13814 end - attribute \src "libresoc.v:181437.3-181455.6" - process $proc$libresoc.v:181437$13332 + attribute \src "libresoc.v:186838.3-186856.6" + process $proc$libresoc.v:186838$13820 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:181438.5-181438.29" + attribute \src "libresoc.v:186839.5-186839.29" switch \initial - attribute \src "libresoc.v:181438.9-181438.17" + attribute \src "libresoc.v:186839.9-186839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$109 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\core_stopped_i[0:0] 1'0 @@ -381319,25 +391734,25 @@ module \test_issuer sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:181456.3-181474.6" - process $proc$libresoc.v:181456$13333 + attribute \src "libresoc.v:186857.3-186875.6" + process $proc$libresoc.v:186857$13821 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:181457.5-181457.29" + attribute \src "libresoc.v:186858.5-186858.29" switch \initial - attribute \src "libresoc.v:181457.9-181457.17" + attribute \src "libresoc.v:186858.9-186858.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" - switch \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign $2\dbg_core_stopped_i[0:0] 1'0 @@ -381352,789 +391767,562 @@ module \test_issuer sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:181475.3-181495.6" - process $proc$libresoc.v:181475$13334 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13335 $3\dec2_cur_msr$next[63:0]$13338 - attribute \src "libresoc.v:181476.5-181476.29" - switch \initial - attribute \src "libresoc.v:181476.9-181476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13336 $2\dec2_cur_msr$next[63:0]$13337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:255" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13337 \core_msr__data_o - case - assign $2\dec2_cur_msr$next[63:0]$13337 \dec2_cur_msr - end - case - assign $1\dec2_cur_msr$next[63:0]$13336 \dec2_cur_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13338 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_msr$next[63:0]$13338 $1\dec2_cur_msr$next[63:0]$13336 - end - sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13335 - end - attribute \src "libresoc.v:181496.3-181514.6" - process $proc$libresoc.v:181496$13339 - assign { } { } - assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:181497.5-181497.29" - switch \initial - attribute \src "libresoc.v:181497.9-181497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$103 - end - case - assign $1\dec2_raw_opcode_in[31:0] 0 - end - sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] - end - attribute \src "libresoc.v:181515.3-181546.6" - process $proc$libresoc.v:181515$13340 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_core_pc$next[63:0]$13341 $3\core_core_pc$next[63:0]$13353 - assign $0\core_dec$next[63:0]$13342 $3\core_dec$next[63:0]$13354 - assign $0\core_eint$next[0:0]$13343 $3\core_eint$next[0:0]$13355 - assign $0\core_msr$next[63:0]$13344 $3\core_msr$next[63:0]$13356 - attribute \src "libresoc.v:181516.5-181516.29" - switch \initial - attribute \src "libresoc.v:181516.9-181516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\core_core_pc$next[63:0]$13345 $2\core_core_pc$next[63:0]$13349 - assign $1\core_dec$next[63:0]$13346 $2\core_dec$next[63:0]$13350 - assign $1\core_eint$next[0:0]$13347 $2\core_eint$next[0:0]$13351 - assign $1\core_msr$next[63:0]$13348 $2\core_msr$next[63:0]$13352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_core_pc$next[63:0]$13349 \core_core_pc - assign $2\core_dec$next[63:0]$13350 \core_dec - assign $2\core_eint$next[0:0]$13351 \core_eint - assign $2\core_msr$next[63:0]$13352 \core_msr - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_dec$next[63:0]$13350 $2\core_eint$next[0:0]$13351 $2\core_msr$next[63:0]$13352 $2\core_core_pc$next[63:0]$13349 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - case - assign $1\core_core_pc$next[63:0]$13345 \core_core_pc - assign $1\core_dec$next[63:0]$13346 \core_dec - assign $1\core_eint$next[0:0]$13347 \core_eint - assign $1\core_msr$next[63:0]$13348 \core_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\core_core_pc$next[63:0]$13353 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13356 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13355 1'0 - assign $3\core_dec$next[63:0]$13354 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_core_pc$next[63:0]$13353 $1\core_core_pc$next[63:0]$13345 - assign $3\core_dec$next[63:0]$13354 $1\core_dec$next[63:0]$13346 - assign $3\core_eint$next[0:0]$13355 $1\core_eint$next[0:0]$13347 - assign $3\core_msr$next[63:0]$13356 $1\core_msr$next[63:0]$13348 - end - sync always - update \core_core_pc$next $0\core_core_pc$next[63:0]$13341 - update \core_dec$next $0\core_dec$next[63:0]$13342 - update \core_eint$next $0\core_eint$next[0:0]$13343 - update \core_msr$next $0\core_msr$next[63:0]$13344 - end - attribute \src "libresoc.v:181547.3-181570.6" - process $proc$libresoc.v:181547$13357 - assign { } { } - assign { } { } - assign { } { } - assign $0\ilatch$next[31:0]$13358 $3\ilatch$next[31:0]$13361 - attribute \src "libresoc.v:181548.5-181548.29" - switch \initial - attribute \src "libresoc.v:181548.9-181548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\ilatch$next[31:0]$13359 $2\ilatch$next[31:0]$13360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:258" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$13360 \ilatch - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$13360 \$107 - end - case - assign $1\ilatch$next[31:0]$13359 \ilatch - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ilatch$next[31:0]$13361 0 - case - assign $3\ilatch$next[31:0]$13361 $1\ilatch$next[31:0]$13359 - end - sync always - update \ilatch$next $0\ilatch$next[31:0]$13358 - end - attribute \src "libresoc.v:181571.3-181590.6" - process $proc$libresoc.v:181571$13362 - assign { } { } - assign { } { } - assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:181572.5-181572.29" - switch \initial - attribute \src "libresoc.v:181572.9-181572.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\core_ivalid_i[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_ivalid_i[0:0] 1'1 - case - assign $2\core_ivalid_i[0:0] 1'0 - end - case - assign $1\core_ivalid_i[0:0] 1'0 - end - sync always - update \core_ivalid_i $0\core_ivalid_i[0:0] - end - connect \$99 $and$libresoc.v:180071$12861_Y - connect \$101 $not$libresoc.v:180072$12862_Y - connect \$104 $mul$libresoc.v:180073$12863_Y - connect \$103 $shr$libresoc.v:180074$12864_Y [31:0] - connect \$108 $mul$libresoc.v:180075$12865_Y - connect \$10 $sub$libresoc.v:180076$12866_Y - connect \$107 $shr$libresoc.v:180077$12867_Y [31:0] - connect \$111 $ne$libresoc.v:180078$12868_Y - connect \$113 $pos$libresoc.v:180079$12870_Y - connect \$115 $pos$libresoc.v:180080$12872_Y - connect \$119 $sub$libresoc.v:180081$12873_Y - connect \$122 $add$libresoc.v:180082$12874_Y - connect \$12 $or$libresoc.v:180083$12875_Y - connect \$14 $ne$libresoc.v:180084$12876_Y - connect \$16 $not$libresoc.v:180085$12877_Y - connect \$18 $and$libresoc.v:180086$12878_Y - connect \$21 $add$libresoc.v:180087$12879_Y - connect \$23 $not$libresoc.v:180088$12880_Y - connect \$25 $not$libresoc.v:180089$12881_Y - connect \$27 $not$libresoc.v:180090$12882_Y - connect \$29 $not$libresoc.v:180091$12883_Y - connect \$31 $not$libresoc.v:180092$12884_Y - connect \$33 $not$libresoc.v:180093$12885_Y - connect \$35 $not$libresoc.v:180094$12886_Y - connect \$37 $and$libresoc.v:180095$12887_Y - connect \$40 $and$libresoc.v:180096$12888_Y - connect \$39 $reduce_or$libresoc.v:180097$12889_Y - connect \$43 $not$libresoc.v:180098$12890_Y - connect \$45 $not$libresoc.v:180099$12891_Y - connect \$47 $not$libresoc.v:180100$12892_Y - connect \$49 $not$libresoc.v:180101$12893_Y - connect \$51 $not$libresoc.v:180102$12894_Y - connect \$53 $and$libresoc.v:180103$12895_Y - connect \$55 $not$libresoc.v:180104$12896_Y - connect \$57 $not$libresoc.v:180105$12897_Y - connect \$59 $and$libresoc.v:180106$12898_Y - connect \$61 $not$libresoc.v:180107$12899_Y - connect \$63 $not$libresoc.v:180108$12900_Y - connect \$65 $and$libresoc.v:180109$12901_Y - connect \$67 $not$libresoc.v:180110$12902_Y - connect \$69 $not$libresoc.v:180111$12903_Y - connect \$71 $and$libresoc.v:180112$12904_Y - connect \$73 $not$libresoc.v:180113$12905_Y - connect \$75 $not$libresoc.v:180114$12906_Y - connect \$77 $and$libresoc.v:180115$12907_Y - connect \$7 $ne$libresoc.v:180116$12908_Y - connect \$79 $not$libresoc.v:180117$12909_Y - connect \$81 $not$libresoc.v:180118$12910_Y - connect \$83 $not$libresoc.v:180119$12911_Y - connect \$85 $and$libresoc.v:180120$12912_Y - connect \$87 $not$libresoc.v:180121$12913_Y - connect \$89 $not$libresoc.v:180122$12914_Y - connect \$91 $not$libresoc.v:180123$12915_Y - connect \$93 $and$libresoc.v:180124$12916_Y - connect \$95 $not$libresoc.v:180125$12917_Y - connect \$97 $not$libresoc.v:180126$12918_Y - connect \$9 \$10 - connect \$20 \$21 - connect \$118 \$119 - connect \$121 \$122 + connect \$99 $not$libresoc.v:185095$13263_Y + connect \$101 $and$libresoc.v:185096$13264_Y + connect \$103 $not$libresoc.v:185097$13265_Y + connect \$105 $not$libresoc.v:185098$13266_Y + connect \$107 $not$libresoc.v:185099$13267_Y + connect \$109 $and$libresoc.v:185100$13268_Y + connect \$111 $not$libresoc.v:185101$13269_Y + connect \$113 $not$libresoc.v:185102$13270_Y + connect \$115 $and$libresoc.v:185103$13271_Y + connect \$117 $not$libresoc.v:185104$13272_Y + connect \$120 $mul$libresoc.v:185105$13273_Y + connect \$119 $shr$libresoc.v:185106$13274_Y [31:0] + connect \$124 $mul$libresoc.v:185107$13275_Y + connect \$123 $shr$libresoc.v:185108$13276_Y [31:0] + connect \$127 $ne$libresoc.v:185109$13277_Y + connect \$129 $pos$libresoc.v:185110$13279_Y + connect \$131 $pos$libresoc.v:185111$13281_Y + connect \$135 $sub$libresoc.v:185112$13282_Y + connect \$138 $add$libresoc.v:185113$13283_Y + connect \$21 $ne$libresoc.v:185114$13284_Y + connect \$24 $sub$libresoc.v:185115$13285_Y + connect \$26 $or$libresoc.v:185116$13286_Y + connect \$28 $or$libresoc.v:185117$13287_Y + connect \$30 $ne$libresoc.v:185118$13288_Y + connect \$32 $not$libresoc.v:185119$13289_Y + connect \$34 $and$libresoc.v:185120$13290_Y + connect \$37 $add$libresoc.v:185121$13291_Y + connect \$39 $not$libresoc.v:185122$13292_Y + connect \$41 $not$libresoc.v:185123$13293_Y + connect \$43 $not$libresoc.v:185124$13294_Y + connect \$45 $not$libresoc.v:185125$13295_Y + connect \$47 $not$libresoc.v:185126$13296_Y + connect \$49 $not$libresoc.v:185127$13297_Y + connect \$51 $not$libresoc.v:185128$13298_Y + connect \$53 $and$libresoc.v:185129$13299_Y + connect \$56 $and$libresoc.v:185130$13300_Y + connect \$55 $reduce_or$libresoc.v:185131$13301_Y + connect \$59 $not$libresoc.v:185132$13302_Y + connect \$61 $not$libresoc.v:185133$13303_Y + connect \$63 $not$libresoc.v:185134$13304_Y + connect \$65 $not$libresoc.v:185135$13305_Y + connect \$67 $not$libresoc.v:185136$13306_Y + connect \$69 $and$libresoc.v:185137$13307_Y + connect \$71 $not$libresoc.v:185138$13308_Y + connect \$73 $not$libresoc.v:185139$13309_Y + connect \$75 $and$libresoc.v:185140$13310_Y + connect \$77 $not$libresoc.v:185141$13311_Y + connect \$79 $not$libresoc.v:185142$13312_Y + connect \$81 $and$libresoc.v:185143$13313_Y + connect \$83 $not$libresoc.v:185144$13314_Y + connect \$85 $not$libresoc.v:185145$13315_Y + connect \$87 $and$libresoc.v:185146$13316_Y + connect \$89 $not$libresoc.v:185147$13317_Y + connect \$91 $not$libresoc.v:185148$13318_Y + connect \$93 $and$libresoc.v:185149$13319_Y + connect \$95 $not$libresoc.v:185150$13320_Y + connect \$97 $not$libresoc.v:185151$13321_Y + connect \$23 \$24 + connect \$36 \$37 + connect \$134 \$135 + connect \$137 \$138 connect \dbg_core_dbg_msr \dec2_cur_msr connect \dbg_core_dbg_pc \pc connect \dbg_terminate_i \core_core_terminate_o - connect \nia \$21 [63:0] + connect \nia \$37 [63:0] connect \pc_o \dec2_cur_pc connect \core_cu_st__go_i \cu_st__rel_o_rise connect \core_cu_ad__go_i \core_cu_ad__rel_o - connect \cu_st__rel_o_rise \$18 + connect \cu_st__rel_o_rise \$34 connect \cu_st__rel_o_dly$next \core_cu_st__rel_o connect \dec2_bigendian \core_bigendian_i connect \busy_o \core_corebusy_o - connect \core_core_reset_i \$14 - connect \core_coresync_clk \clk + connect \core_coresync_rst \ti_rst + connect \ti_rst \$30 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "libresoc.v:181614.1-182789.10" +attribute \src "libresoc.v:186899.1-188084.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:182336.3-182337.25" + attribute \src "libresoc.v:187629.3-187630.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:182334.3-182335.41" + attribute \src "libresoc.v:187627.3-187628.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:182692.3-182700.6" - wire $0\alu_l_r_alu$next[0:0]$13648 - attribute \src "libresoc.v:182264.3-182265.39" + attribute \src "libresoc.v:187987.3-187995.6" + wire $0\alu_l_r_alu$next[0:0]$14126 + attribute \src "libresoc.v:187555.3-187556.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13576 - attribute \src "libresoc.v:182304.3-182305.61" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14052 + attribute \src "libresoc.v:187595.3-187596.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 - attribute \src "libresoc.v:182298.3-182299.69" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 + attribute \src "libresoc.v:187589.3-187590.69" wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13578 - attribute \src "libresoc.v:182300.3-182301.63" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14054 + attribute \src "libresoc.v:187591.3-187592.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 - attribute \src "libresoc.v:182296.3-182297.73" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 + attribute \src "libresoc.v:187587.3-187588.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 - attribute \src "libresoc.v:182306.3-182307.71" + attribute \src "libresoc.v:187810.3-187827.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 + attribute \src "libresoc.v:187597.3-187598.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13581 - attribute \src "libresoc.v:182302.3-182303.61" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 + attribute \src "libresoc.v:187603.3-187604.71" + wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:187810.3-187827.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14058 + attribute \src "libresoc.v:187593.3-187594.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 - attribute \src "libresoc.v:182310.3-182311.71" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 + attribute \src "libresoc.v:187601.3-187602.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 7 $0\alu_trap0_trap_op__traptype$next[6:0]$13583 - attribute \src "libresoc.v:182308.3-182309.71" - wire width 7 $0\alu_trap0_trap_op__traptype[6:0] - attribute \src "libresoc.v:182683.3-182691.6" - wire $0\alui_l_r_alui$next[0:0]$13645 - attribute \src "libresoc.v:182266.3-182267.43" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14060 + attribute \src "libresoc.v:187599.3-187600.71" + wire width 8 $0\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:187978.3-187986.6" + wire $0\alui_l_r_alui$next[0:0]$14123 + attribute \src "libresoc.v:187557.3-187558.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:182533.3-182554.6" - wire width 64 $0\data_r0__o$next[63:0]$13593 - attribute \src "libresoc.v:182292.3-182293.37" + attribute \src "libresoc.v:187828.3-187849.6" + wire width 64 $0\data_r0__o$next[63:0]$14071 + attribute \src "libresoc.v:187583.3-187584.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:182533.3-182554.6" - wire $0\data_r0__o_ok$next[0:0]$13594 - attribute \src "libresoc.v:182294.3-182295.43" + attribute \src "libresoc.v:187828.3-187849.6" + wire $0\data_r0__o_ok$next[0:0]$14072 + attribute \src "libresoc.v:187585.3-187586.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:182555.3-182576.6" - wire width 64 $0\data_r1__fast1$next[63:0]$13601 - attribute \src "libresoc.v:182288.3-182289.45" + attribute \src "libresoc.v:187850.3-187871.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14079 + attribute \src "libresoc.v:187579.3-187580.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:182555.3-182576.6" - wire $0\data_r1__fast1_ok$next[0:0]$13602 - attribute \src "libresoc.v:182290.3-182291.51" + attribute \src "libresoc.v:187850.3-187871.6" + wire $0\data_r1__fast1_ok$next[0:0]$14080 + attribute \src "libresoc.v:187581.3-187582.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:182577.3-182598.6" - wire width 64 $0\data_r2__fast2$next[63:0]$13609 - attribute \src "libresoc.v:182284.3-182285.45" + attribute \src "libresoc.v:187872.3-187893.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14087 + attribute \src "libresoc.v:187575.3-187576.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:182577.3-182598.6" - wire $0\data_r2__fast2_ok$next[0:0]$13610 - attribute \src "libresoc.v:182286.3-182287.51" + attribute \src "libresoc.v:187872.3-187893.6" + wire $0\data_r2__fast2_ok$next[0:0]$14088 + attribute \src "libresoc.v:187577.3-187578.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:182599.3-182620.6" - wire width 64 $0\data_r3__nia$next[63:0]$13617 - attribute \src "libresoc.v:182280.3-182281.41" + attribute \src "libresoc.v:187894.3-187915.6" + wire width 64 $0\data_r3__nia$next[63:0]$14095 + attribute \src "libresoc.v:187571.3-187572.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:182599.3-182620.6" - wire $0\data_r3__nia_ok$next[0:0]$13618 - attribute \src "libresoc.v:182282.3-182283.47" + attribute \src "libresoc.v:187894.3-187915.6" + wire $0\data_r3__nia_ok$next[0:0]$14096 + attribute \src "libresoc.v:187573.3-187574.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:182621.3-182642.6" - wire width 64 $0\data_r4__msr$next[63:0]$13625 - attribute \src "libresoc.v:182276.3-182277.41" + attribute \src "libresoc.v:187916.3-187937.6" + wire width 64 $0\data_r4__msr$next[63:0]$14103 + attribute \src "libresoc.v:187567.3-187568.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:182621.3-182642.6" - wire $0\data_r4__msr_ok$next[0:0]$13626 - attribute \src "libresoc.v:182278.3-182279.47" + attribute \src "libresoc.v:187916.3-187937.6" + wire $0\data_r4__msr_ok$next[0:0]$14104 + attribute \src "libresoc.v:187569.3-187570.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:182701.3-182710.6" + attribute \src "libresoc.v:187996.3-188005.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:182711.3-182720.6" + attribute \src "libresoc.v:188006.3-188015.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:182721.3-182730.6" + attribute \src "libresoc.v:188016.3-188025.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:182731.3-182740.6" + attribute \src "libresoc.v:188026.3-188035.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:182741.3-182750.6" + attribute \src "libresoc.v:188036.3-188045.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:181615.7-181615.20" + attribute \src "libresoc.v:186900.7-186900.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182471.3-182479.6" - wire $0\opc_l_r_opc$next[0:0]$13561 - attribute \src "libresoc.v:182320.3-182321.39" + attribute \src "libresoc.v:187765.3-187773.6" + wire $0\opc_l_r_opc$next[0:0]$14037 + attribute \src "libresoc.v:187613.3-187614.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:182462.3-182470.6" - wire $0\opc_l_s_opc$next[0:0]$13558 - attribute \src "libresoc.v:182322.3-182323.39" + attribute \src "libresoc.v:187756.3-187764.6" + wire $0\opc_l_s_opc$next[0:0]$14034 + attribute \src "libresoc.v:187615.3-187616.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:182751.3-182759.6" - wire width 5 $0\prev_wr_go$next[4:0]$13656 - attribute \src "libresoc.v:182332.3-182333.37" + attribute \src "libresoc.v:188046.3-188054.6" + wire width 5 $0\prev_wr_go$next[4:0]$14134 + attribute \src "libresoc.v:187625.3-187626.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:182416.3-182425.6" + attribute \src "libresoc.v:187710.3-187719.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:182507.3-182515.6" - wire width 5 $0\req_l_r_req$next[4:0]$13573 - attribute \src "libresoc.v:182312.3-182313.39" + attribute \src "libresoc.v:187801.3-187809.6" + wire width 5 $0\req_l_r_req$next[4:0]$14049 + attribute \src "libresoc.v:187605.3-187606.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:182498.3-182506.6" - wire width 5 $0\req_l_s_req$next[4:0]$13570 - attribute \src "libresoc.v:182314.3-182315.39" + attribute \src "libresoc.v:187792.3-187800.6" + wire width 5 $0\req_l_s_req$next[4:0]$14046 + attribute \src "libresoc.v:187607.3-187608.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:182435.3-182443.6" - wire $0\rok_l_r_rdok$next[0:0]$13549 - attribute \src "libresoc.v:182328.3-182329.41" + attribute \src "libresoc.v:187729.3-187737.6" + wire $0\rok_l_r_rdok$next[0:0]$14025 + attribute \src "libresoc.v:187621.3-187622.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:182426.3-182434.6" - wire $0\rok_l_s_rdok$next[0:0]$13546 - attribute \src "libresoc.v:182330.3-182331.41" + attribute \src "libresoc.v:187720.3-187728.6" + wire $0\rok_l_s_rdok$next[0:0]$14022 + attribute \src "libresoc.v:187623.3-187624.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:182453.3-182461.6" - wire $0\rst_l_r_rst$next[0:0]$13555 - attribute \src "libresoc.v:182324.3-182325.39" + attribute \src "libresoc.v:187747.3-187755.6" + wire $0\rst_l_r_rst$next[0:0]$14031 + attribute \src "libresoc.v:187617.3-187618.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:182444.3-182452.6" - wire $0\rst_l_s_rst$next[0:0]$13552 - attribute \src "libresoc.v:182326.3-182327.39" + attribute \src "libresoc.v:187738.3-187746.6" + wire $0\rst_l_s_rst$next[0:0]$14028 + attribute \src "libresoc.v:187619.3-187620.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:182489.3-182497.6" - wire width 4 $0\src_l_r_src$next[3:0]$13567 - attribute \src "libresoc.v:182316.3-182317.39" + attribute \src "libresoc.v:187783.3-187791.6" + wire width 4 $0\src_l_r_src$next[3:0]$14043 + attribute \src "libresoc.v:187609.3-187610.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:182480.3-182488.6" - wire width 4 $0\src_l_s_src$next[3:0]$13564 - attribute \src "libresoc.v:182318.3-182319.39" + attribute \src "libresoc.v:187774.3-187782.6" + wire width 4 $0\src_l_s_src$next[3:0]$14040 + attribute \src "libresoc.v:187611.3-187612.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:182643.3-182652.6" - wire width 64 $0\src_r0$next[63:0]$13633 - attribute \src "libresoc.v:182274.3-182275.29" + attribute \src "libresoc.v:187938.3-187947.6" + wire width 64 $0\src_r0$next[63:0]$14111 + attribute \src "libresoc.v:187565.3-187566.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:182653.3-182662.6" - wire width 64 $0\src_r1$next[63:0]$13636 - attribute \src "libresoc.v:182272.3-182273.29" + attribute \src "libresoc.v:187948.3-187957.6" + wire width 64 $0\src_r1$next[63:0]$14114 + attribute \src "libresoc.v:187563.3-187564.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:182663.3-182672.6" - wire width 64 $0\src_r2$next[63:0]$13639 - attribute \src "libresoc.v:182270.3-182271.29" + attribute \src "libresoc.v:187958.3-187967.6" + wire width 64 $0\src_r2$next[63:0]$14117 + attribute \src "libresoc.v:187561.3-187562.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:182673.3-182682.6" - wire width 64 $0\src_r3$next[63:0]$13642 - attribute \src "libresoc.v:182268.3-182269.29" + attribute \src "libresoc.v:187968.3-187977.6" + wire width 64 $0\src_r3$next[63:0]$14120 + attribute \src "libresoc.v:187559.3-187560.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:181741.7-181741.24" + attribute \src "libresoc.v:187026.7-187026.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:181751.7-181751.26" + attribute \src "libresoc.v:187036.7-187036.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:182692.3-182700.6" - wire $1\alu_l_r_alu$next[0:0]$13649 - attribute \src "libresoc.v:181759.7-181759.25" + attribute \src "libresoc.v:187987.3-187995.6" + wire $1\alu_l_r_alu$next[0:0]$14127 + attribute \src "libresoc.v:187044.7-187044.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13584 - attribute \src "libresoc.v:181795.14-181795.59" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14061 + attribute \src "libresoc.v:187080.14-187080.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 - attribute \src "libresoc.v:181812.14-181812.50" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 + attribute \src "libresoc.v:187097.14-187097.50" wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13586 - attribute \src "libresoc.v:181816.14-181816.45" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14063 + attribute \src "libresoc.v:187101.14-187101.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 - attribute \src "libresoc.v:181894.13-181894.49" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 + attribute \src "libresoc.v:187179.13-187179.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 - attribute \src "libresoc.v:181898.7-181898.41" + attribute \src "libresoc.v:187810.3-187827.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 + attribute \src "libresoc.v:187183.7-187183.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13589 - attribute \src "libresoc.v:181902.14-181902.59" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 + attribute \src "libresoc.v:187187.13-187187.48" + wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:187810.3-187827.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14067 + attribute \src "libresoc.v:187191.14-187191.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 - attribute \src "libresoc.v:181906.14-181906.52" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 + attribute \src "libresoc.v:187195.14-187195.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:182516.3-182532.6" - wire width 7 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 - attribute \src "libresoc.v:181910.13-181910.48" - wire width 7 $1\alu_trap0_trap_op__traptype[6:0] - attribute \src "libresoc.v:182683.3-182691.6" - wire $1\alui_l_r_alui$next[0:0]$13646 - attribute \src "libresoc.v:181916.7-181916.27" + attribute \src "libresoc.v:187810.3-187827.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14069 + attribute \src "libresoc.v:187199.13-187199.48" + wire width 8 $1\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:187978.3-187986.6" + wire $1\alui_l_r_alui$next[0:0]$14124 + attribute \src "libresoc.v:187205.7-187205.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:182533.3-182554.6" - wire width 64 $1\data_r0__o$next[63:0]$13595 - attribute \src "libresoc.v:181948.14-181948.47" + attribute \src "libresoc.v:187828.3-187849.6" + wire width 64 $1\data_r0__o$next[63:0]$14073 + attribute \src "libresoc.v:187237.14-187237.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:182533.3-182554.6" - wire $1\data_r0__o_ok$next[0:0]$13596 - attribute \src "libresoc.v:181952.7-181952.27" + attribute \src "libresoc.v:187828.3-187849.6" + wire $1\data_r0__o_ok$next[0:0]$14074 + attribute \src "libresoc.v:187241.7-187241.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:182555.3-182576.6" - wire width 64 $1\data_r1__fast1$next[63:0]$13603 - attribute \src "libresoc.v:181956.14-181956.51" + attribute \src "libresoc.v:187850.3-187871.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14081 + attribute \src "libresoc.v:187245.14-187245.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:182555.3-182576.6" - wire $1\data_r1__fast1_ok$next[0:0]$13604 - attribute \src "libresoc.v:181960.7-181960.31" + attribute \src "libresoc.v:187850.3-187871.6" + wire $1\data_r1__fast1_ok$next[0:0]$14082 + attribute \src "libresoc.v:187249.7-187249.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:182577.3-182598.6" - wire width 64 $1\data_r2__fast2$next[63:0]$13611 - attribute \src "libresoc.v:181964.14-181964.51" + attribute \src "libresoc.v:187872.3-187893.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14089 + attribute \src "libresoc.v:187253.14-187253.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:182577.3-182598.6" - wire $1\data_r2__fast2_ok$next[0:0]$13612 - attribute \src "libresoc.v:181968.7-181968.31" + attribute \src "libresoc.v:187872.3-187893.6" + wire $1\data_r2__fast2_ok$next[0:0]$14090 + attribute \src "libresoc.v:187257.7-187257.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:182599.3-182620.6" - wire width 64 $1\data_r3__nia$next[63:0]$13619 - attribute \src "libresoc.v:181972.14-181972.49" + attribute \src "libresoc.v:187894.3-187915.6" + wire width 64 $1\data_r3__nia$next[63:0]$14097 + attribute \src "libresoc.v:187261.14-187261.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:182599.3-182620.6" - wire $1\data_r3__nia_ok$next[0:0]$13620 - attribute \src "libresoc.v:181976.7-181976.29" + attribute \src "libresoc.v:187894.3-187915.6" + wire $1\data_r3__nia_ok$next[0:0]$14098 + attribute \src "libresoc.v:187265.7-187265.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:182621.3-182642.6" - wire width 64 $1\data_r4__msr$next[63:0]$13627 - attribute \src "libresoc.v:181980.14-181980.49" + attribute \src "libresoc.v:187916.3-187937.6" + wire width 64 $1\data_r4__msr$next[63:0]$14105 + attribute \src "libresoc.v:187269.14-187269.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:182621.3-182642.6" - wire $1\data_r4__msr_ok$next[0:0]$13628 - attribute \src "libresoc.v:181984.7-181984.29" + attribute \src "libresoc.v:187916.3-187937.6" + wire $1\data_r4__msr_ok$next[0:0]$14106 + attribute \src "libresoc.v:187273.7-187273.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:182701.3-182710.6" + attribute \src "libresoc.v:187996.3-188005.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:182711.3-182720.6" + attribute \src "libresoc.v:188006.3-188015.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:182721.3-182730.6" + attribute \src "libresoc.v:188016.3-188025.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:182731.3-182740.6" + attribute \src "libresoc.v:188026.3-188035.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:182741.3-182750.6" + attribute \src "libresoc.v:188036.3-188045.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:182471.3-182479.6" - wire $1\opc_l_r_opc$next[0:0]$13562 - attribute \src "libresoc.v:182015.7-182015.25" + attribute \src "libresoc.v:187765.3-187773.6" + wire $1\opc_l_r_opc$next[0:0]$14038 + attribute \src "libresoc.v:187304.7-187304.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:182462.3-182470.6" - wire $1\opc_l_s_opc$next[0:0]$13559 - attribute \src "libresoc.v:182019.7-182019.25" + attribute \src "libresoc.v:187756.3-187764.6" + wire $1\opc_l_s_opc$next[0:0]$14035 + attribute \src "libresoc.v:187308.7-187308.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:182751.3-182759.6" - wire width 5 $1\prev_wr_go$next[4:0]$13657 - attribute \src "libresoc.v:182126.13-182126.31" + attribute \src "libresoc.v:188046.3-188054.6" + wire width 5 $1\prev_wr_go$next[4:0]$14135 + attribute \src "libresoc.v:187417.13-187417.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:182416.3-182425.6" + attribute \src "libresoc.v:187710.3-187719.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:182507.3-182515.6" - wire width 5 $1\req_l_r_req$next[4:0]$13574 - attribute \src "libresoc.v:182134.13-182134.32" + attribute \src "libresoc.v:187801.3-187809.6" + wire width 5 $1\req_l_r_req$next[4:0]$14050 + attribute \src "libresoc.v:187425.13-187425.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:182498.3-182506.6" - wire width 5 $1\req_l_s_req$next[4:0]$13571 - attribute \src "libresoc.v:182138.13-182138.32" + attribute \src "libresoc.v:187792.3-187800.6" + wire width 5 $1\req_l_s_req$next[4:0]$14047 + attribute \src "libresoc.v:187429.13-187429.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:182435.3-182443.6" - wire $1\rok_l_r_rdok$next[0:0]$13550 - attribute \src "libresoc.v:182150.7-182150.26" + attribute \src "libresoc.v:187729.3-187737.6" + wire $1\rok_l_r_rdok$next[0:0]$14026 + attribute \src "libresoc.v:187441.7-187441.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:182426.3-182434.6" - wire $1\rok_l_s_rdok$next[0:0]$13547 - attribute \src "libresoc.v:182154.7-182154.26" + attribute \src "libresoc.v:187720.3-187728.6" + wire $1\rok_l_s_rdok$next[0:0]$14023 + attribute \src "libresoc.v:187445.7-187445.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:182453.3-182461.6" - wire $1\rst_l_r_rst$next[0:0]$13556 - attribute \src "libresoc.v:182158.7-182158.25" + attribute \src "libresoc.v:187747.3-187755.6" + wire $1\rst_l_r_rst$next[0:0]$14032 + attribute \src "libresoc.v:187449.7-187449.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:182444.3-182452.6" - wire $1\rst_l_s_rst$next[0:0]$13553 - attribute \src "libresoc.v:182162.7-182162.25" + attribute \src "libresoc.v:187738.3-187746.6" + wire $1\rst_l_s_rst$next[0:0]$14029 + attribute \src "libresoc.v:187453.7-187453.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:182489.3-182497.6" - wire width 4 $1\src_l_r_src$next[3:0]$13568 - attribute \src "libresoc.v:182178.13-182178.31" + attribute \src "libresoc.v:187783.3-187791.6" + wire width 4 $1\src_l_r_src$next[3:0]$14044 + attribute \src "libresoc.v:187469.13-187469.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:182480.3-182488.6" - wire width 4 $1\src_l_s_src$next[3:0]$13565 - attribute \src "libresoc.v:182182.13-182182.31" + attribute \src "libresoc.v:187774.3-187782.6" + wire width 4 $1\src_l_s_src$next[3:0]$14041 + attribute \src "libresoc.v:187473.13-187473.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:182643.3-182652.6" - wire width 64 $1\src_r0$next[63:0]$13634 - attribute \src "libresoc.v:182186.14-182186.43" + attribute \src "libresoc.v:187938.3-187947.6" + wire width 64 $1\src_r0$next[63:0]$14112 + attribute \src "libresoc.v:187477.14-187477.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:182653.3-182662.6" - wire width 64 $1\src_r1$next[63:0]$13637 - attribute \src "libresoc.v:182190.14-182190.43" + attribute \src "libresoc.v:187948.3-187957.6" + wire width 64 $1\src_r1$next[63:0]$14115 + attribute \src "libresoc.v:187481.14-187481.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:182663.3-182672.6" - wire width 64 $1\src_r2$next[63:0]$13640 - attribute \src "libresoc.v:182194.14-182194.43" + attribute \src "libresoc.v:187958.3-187967.6" + wire width 64 $1\src_r2$next[63:0]$14118 + attribute \src "libresoc.v:187485.14-187485.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:182673.3-182682.6" - wire width 64 $1\src_r3$next[63:0]$13643 - attribute \src "libresoc.v:182198.14-182198.43" + attribute \src "libresoc.v:187968.3-187977.6" + wire width 64 $1\src_r3$next[63:0]$14121 + attribute \src "libresoc.v:187489.14-187489.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:182533.3-182554.6" - wire width 64 $2\data_r0__o$next[63:0]$13597 - attribute \src "libresoc.v:182533.3-182554.6" - wire $2\data_r0__o_ok$next[0:0]$13598 - attribute \src "libresoc.v:182555.3-182576.6" - wire width 64 $2\data_r1__fast1$next[63:0]$13605 - attribute \src "libresoc.v:182555.3-182576.6" - wire $2\data_r1__fast1_ok$next[0:0]$13606 - attribute \src "libresoc.v:182577.3-182598.6" - wire width 64 $2\data_r2__fast2$next[63:0]$13613 - attribute \src "libresoc.v:182577.3-182598.6" - wire $2\data_r2__fast2_ok$next[0:0]$13614 - attribute \src "libresoc.v:182599.3-182620.6" - wire width 64 $2\data_r3__nia$next[63:0]$13621 - attribute \src "libresoc.v:182599.3-182620.6" - wire $2\data_r3__nia_ok$next[0:0]$13622 - attribute \src "libresoc.v:182621.3-182642.6" - wire width 64 $2\data_r4__msr$next[63:0]$13629 - attribute \src "libresoc.v:182621.3-182642.6" - wire $2\data_r4__msr_ok$next[0:0]$13630 - attribute \src "libresoc.v:182533.3-182554.6" - wire $3\data_r0__o_ok$next[0:0]$13599 - attribute \src "libresoc.v:182555.3-182576.6" - wire $3\data_r1__fast1_ok$next[0:0]$13607 - attribute \src "libresoc.v:182577.3-182598.6" - wire $3\data_r2__fast2_ok$next[0:0]$13615 - attribute \src "libresoc.v:182599.3-182620.6" - wire $3\data_r3__nia_ok$next[0:0]$13623 - attribute \src "libresoc.v:182621.3-182642.6" - wire $3\data_r4__msr_ok$next[0:0]$13631 - attribute \src "libresoc.v:182204.18-182204.112" - wire width 4 $and$libresoc.v:182204$13447_Y - attribute \src "libresoc.v:182205.19-182205.125" - wire $and$libresoc.v:182205$13448_Y - attribute \src "libresoc.v:182206.19-182206.125" - wire $and$libresoc.v:182206$13449_Y - attribute \src "libresoc.v:182207.19-182207.125" - wire $and$libresoc.v:182207$13450_Y - attribute \src "libresoc.v:182208.19-182208.125" - wire $and$libresoc.v:182208$13451_Y - attribute \src "libresoc.v:182209.19-182209.125" - wire $and$libresoc.v:182209$13452_Y - attribute \src "libresoc.v:182210.19-182210.157" - wire width 5 $and$libresoc.v:182210$13453_Y - attribute \src "libresoc.v:182211.19-182211.121" - wire width 5 $and$libresoc.v:182211$13454_Y - attribute \src "libresoc.v:182212.19-182212.127" - wire $and$libresoc.v:182212$13455_Y - attribute \src "libresoc.v:182213.19-182213.127" - wire $and$libresoc.v:182213$13456_Y - attribute \src "libresoc.v:182214.18-182214.110" - wire $and$libresoc.v:182214$13457_Y - attribute \src "libresoc.v:182215.19-182215.127" - wire $and$libresoc.v:182215$13458_Y - attribute \src "libresoc.v:182216.19-182216.127" - wire $and$libresoc.v:182216$13459_Y - attribute \src "libresoc.v:182217.19-182217.127" - wire $and$libresoc.v:182217$13460_Y - attribute \src "libresoc.v:182219.18-182219.98" - wire $and$libresoc.v:182219$13462_Y - attribute \src "libresoc.v:182221.18-182221.100" - wire $and$libresoc.v:182221$13464_Y - attribute \src "libresoc.v:182222.18-182222.171" - wire width 5 $and$libresoc.v:182222$13465_Y - attribute \src "libresoc.v:182224.18-182224.119" - wire width 5 $and$libresoc.v:182224$13467_Y - attribute \src "libresoc.v:182227.18-182227.116" - wire $and$libresoc.v:182227$13470_Y - attribute \src "libresoc.v:182231.17-182231.123" - wire $and$libresoc.v:182231$13474_Y - attribute \src "libresoc.v:182233.18-182233.113" - wire $and$libresoc.v:182233$13476_Y - attribute \src "libresoc.v:182234.18-182234.125" - wire width 5 $and$libresoc.v:182234$13477_Y - attribute \src "libresoc.v:182236.18-182236.112" - wire $and$libresoc.v:182236$13479_Y - attribute \src "libresoc.v:182238.18-182238.127" - wire $and$libresoc.v:182238$13481_Y - attribute \src "libresoc.v:182239.18-182239.127" - wire $and$libresoc.v:182239$13482_Y - attribute \src "libresoc.v:182240.18-182240.117" - wire $and$libresoc.v:182240$13483_Y - attribute \src "libresoc.v:182245.18-182245.131" - wire $and$libresoc.v:182245$13488_Y - attribute \src "libresoc.v:182246.18-182246.124" - wire width 5 $and$libresoc.v:182246$13489_Y - attribute \src "libresoc.v:182249.18-182249.116" - wire $and$libresoc.v:182249$13492_Y - attribute \src "libresoc.v:182250.18-182250.120" - wire $and$libresoc.v:182250$13493_Y - attribute \src "libresoc.v:182251.18-182251.120" - wire $and$libresoc.v:182251$13494_Y - attribute \src "libresoc.v:182252.18-182252.118" - wire $and$libresoc.v:182252$13495_Y - attribute \src "libresoc.v:182253.18-182253.118" - wire $and$libresoc.v:182253$13496_Y - attribute \src "libresoc.v:182259.18-182259.135" - wire $and$libresoc.v:182259$13502_Y - attribute \src "libresoc.v:182260.18-182260.133" - wire $and$libresoc.v:182260$13503_Y - attribute \src "libresoc.v:182261.18-182261.160" - wire width 4 $and$libresoc.v:182261$13504_Y - attribute \src "libresoc.v:182262.18-182262.112" - wire width 4 $and$libresoc.v:182262$13505_Y - attribute \src "libresoc.v:182235.18-182235.113" - wire $eq$libresoc.v:182235$13478_Y - attribute \src "libresoc.v:182237.18-182237.119" - wire $eq$libresoc.v:182237$13480_Y - attribute \src "libresoc.v:182218.18-182218.97" - wire $not$libresoc.v:182218$13461_Y - attribute \src "libresoc.v:182220.18-182220.99" - wire $not$libresoc.v:182220$13463_Y - attribute \src "libresoc.v:182223.18-182223.113" - wire width 5 $not$libresoc.v:182223$13466_Y - attribute \src "libresoc.v:182226.18-182226.106" - wire $not$libresoc.v:182226$13469_Y - attribute \src "libresoc.v:182232.18-182232.121" - wire $not$libresoc.v:182232$13475_Y - attribute \src "libresoc.v:182247.17-182247.113" - wire width 4 $not$libresoc.v:182247$13490_Y - attribute \src "libresoc.v:182263.18-182263.114" - wire width 4 $not$libresoc.v:182263$13506_Y - attribute \src "libresoc.v:182230.18-182230.112" - wire $or$libresoc.v:182230$13473_Y - attribute \src "libresoc.v:182241.18-182241.122" - wire $or$libresoc.v:182241$13484_Y - attribute \src "libresoc.v:182242.18-182242.124" - wire $or$libresoc.v:182242$13485_Y - attribute \src "libresoc.v:182243.18-182243.181" - wire width 5 $or$libresoc.v:182243$13486_Y - attribute \src "libresoc.v:182244.18-182244.168" - wire width 4 $or$libresoc.v:182244$13487_Y - attribute \src "libresoc.v:182248.18-182248.120" - wire width 5 $or$libresoc.v:182248$13491_Y - attribute \src "libresoc.v:182258.17-182258.117" - wire width 4 $or$libresoc.v:182258$13501_Y - attribute \src "libresoc.v:182203.17-182203.104" - wire $reduce_and$libresoc.v:182203$13446_Y - attribute \src "libresoc.v:182225.18-182225.106" - wire $reduce_or$libresoc.v:182225$13468_Y - attribute \src "libresoc.v:182228.18-182228.113" - wire $reduce_or$libresoc.v:182228$13471_Y - attribute \src "libresoc.v:182229.18-182229.112" - wire $reduce_or$libresoc.v:182229$13472_Y - attribute \src "libresoc.v:182254.18-182254.118" - wire width 64 $ternary$libresoc.v:182254$13497_Y - attribute \src "libresoc.v:182255.18-182255.118" - wire width 64 $ternary$libresoc.v:182255$13498_Y - attribute \src "libresoc.v:182256.18-182256.118" - wire width 64 $ternary$libresoc.v:182256$13499_Y - attribute \src "libresoc.v:182257.18-182257.118" - wire width 64 $ternary$libresoc.v:182257$13500_Y + attribute \src "libresoc.v:187828.3-187849.6" + wire width 64 $2\data_r0__o$next[63:0]$14075 + attribute \src "libresoc.v:187828.3-187849.6" + wire $2\data_r0__o_ok$next[0:0]$14076 + attribute \src "libresoc.v:187850.3-187871.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14083 + attribute \src "libresoc.v:187850.3-187871.6" + wire $2\data_r1__fast1_ok$next[0:0]$14084 + attribute \src "libresoc.v:187872.3-187893.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14091 + attribute \src "libresoc.v:187872.3-187893.6" + wire $2\data_r2__fast2_ok$next[0:0]$14092 + attribute \src "libresoc.v:187894.3-187915.6" + wire width 64 $2\data_r3__nia$next[63:0]$14099 + attribute \src "libresoc.v:187894.3-187915.6" + wire $2\data_r3__nia_ok$next[0:0]$14100 + attribute \src "libresoc.v:187916.3-187937.6" + wire width 64 $2\data_r4__msr$next[63:0]$14107 + attribute \src "libresoc.v:187916.3-187937.6" + wire $2\data_r4__msr_ok$next[0:0]$14108 + attribute \src "libresoc.v:187828.3-187849.6" + wire $3\data_r0__o_ok$next[0:0]$14077 + attribute \src "libresoc.v:187850.3-187871.6" + wire $3\data_r1__fast1_ok$next[0:0]$14085 + attribute \src "libresoc.v:187872.3-187893.6" + wire $3\data_r2__fast2_ok$next[0:0]$14093 + attribute \src "libresoc.v:187894.3-187915.6" + wire $3\data_r3__nia_ok$next[0:0]$14101 + attribute \src "libresoc.v:187916.3-187937.6" + wire $3\data_r4__msr_ok$next[0:0]$14109 + attribute \src "libresoc.v:187495.18-187495.112" + wire width 4 $and$libresoc.v:187495$13922_Y + attribute \src "libresoc.v:187496.19-187496.125" + wire $and$libresoc.v:187496$13923_Y + attribute \src "libresoc.v:187497.19-187497.125" + wire $and$libresoc.v:187497$13924_Y + attribute \src "libresoc.v:187498.19-187498.125" + wire $and$libresoc.v:187498$13925_Y + attribute \src "libresoc.v:187499.19-187499.125" + wire $and$libresoc.v:187499$13926_Y + attribute \src "libresoc.v:187500.19-187500.125" + wire $and$libresoc.v:187500$13927_Y + attribute \src "libresoc.v:187501.19-187501.157" + wire width 5 $and$libresoc.v:187501$13928_Y + attribute \src "libresoc.v:187502.19-187502.121" + wire width 5 $and$libresoc.v:187502$13929_Y + attribute \src "libresoc.v:187503.19-187503.127" + wire $and$libresoc.v:187503$13930_Y + attribute \src "libresoc.v:187504.19-187504.127" + wire $and$libresoc.v:187504$13931_Y + attribute \src "libresoc.v:187505.18-187505.110" + wire $and$libresoc.v:187505$13932_Y + attribute \src "libresoc.v:187506.19-187506.127" + wire $and$libresoc.v:187506$13933_Y + attribute \src "libresoc.v:187507.19-187507.127" + wire $and$libresoc.v:187507$13934_Y + attribute \src "libresoc.v:187508.19-187508.127" + wire $and$libresoc.v:187508$13935_Y + attribute \src "libresoc.v:187510.18-187510.98" + wire $and$libresoc.v:187510$13937_Y + attribute \src "libresoc.v:187512.18-187512.100" + wire $and$libresoc.v:187512$13939_Y + attribute \src "libresoc.v:187513.18-187513.171" + wire width 5 $and$libresoc.v:187513$13940_Y + attribute \src "libresoc.v:187515.18-187515.119" + wire width 5 $and$libresoc.v:187515$13942_Y + attribute \src "libresoc.v:187518.18-187518.116" + wire $and$libresoc.v:187518$13945_Y + attribute \src "libresoc.v:187522.17-187522.123" + wire $and$libresoc.v:187522$13949_Y + attribute \src "libresoc.v:187524.18-187524.113" + wire $and$libresoc.v:187524$13951_Y + attribute \src "libresoc.v:187525.18-187525.125" + wire width 5 $and$libresoc.v:187525$13952_Y + attribute \src "libresoc.v:187527.18-187527.112" + wire $and$libresoc.v:187527$13954_Y + attribute \src "libresoc.v:187529.18-187529.127" + wire $and$libresoc.v:187529$13956_Y + attribute \src "libresoc.v:187530.18-187530.127" + wire $and$libresoc.v:187530$13957_Y + attribute \src "libresoc.v:187531.18-187531.117" + wire $and$libresoc.v:187531$13958_Y + attribute \src "libresoc.v:187536.18-187536.131" + wire $and$libresoc.v:187536$13963_Y + attribute \src "libresoc.v:187537.18-187537.124" + wire width 5 $and$libresoc.v:187537$13964_Y + attribute \src "libresoc.v:187540.18-187540.116" + wire $and$libresoc.v:187540$13967_Y + attribute \src "libresoc.v:187541.18-187541.120" + wire $and$libresoc.v:187541$13968_Y + attribute \src "libresoc.v:187542.18-187542.120" + wire $and$libresoc.v:187542$13969_Y + attribute \src "libresoc.v:187543.18-187543.118" + wire $and$libresoc.v:187543$13970_Y + attribute \src "libresoc.v:187544.18-187544.118" + wire $and$libresoc.v:187544$13971_Y + attribute \src "libresoc.v:187550.18-187550.135" + wire $and$libresoc.v:187550$13977_Y + attribute \src "libresoc.v:187551.18-187551.133" + wire $and$libresoc.v:187551$13978_Y + attribute \src "libresoc.v:187552.18-187552.160" + wire width 4 $and$libresoc.v:187552$13979_Y + attribute \src "libresoc.v:187553.18-187553.112" + wire width 4 $and$libresoc.v:187553$13980_Y + attribute \src "libresoc.v:187526.18-187526.113" + wire $eq$libresoc.v:187526$13953_Y + attribute \src "libresoc.v:187528.18-187528.119" + wire $eq$libresoc.v:187528$13955_Y + attribute \src "libresoc.v:187509.18-187509.97" + wire $not$libresoc.v:187509$13936_Y + attribute \src "libresoc.v:187511.18-187511.99" + wire $not$libresoc.v:187511$13938_Y + attribute \src "libresoc.v:187514.18-187514.113" + wire width 5 $not$libresoc.v:187514$13941_Y + attribute \src "libresoc.v:187517.18-187517.106" + wire $not$libresoc.v:187517$13944_Y + attribute \src "libresoc.v:187523.18-187523.121" + wire $not$libresoc.v:187523$13950_Y + attribute \src "libresoc.v:187538.17-187538.113" + wire width 4 $not$libresoc.v:187538$13965_Y + attribute \src "libresoc.v:187554.18-187554.114" + wire width 4 $not$libresoc.v:187554$13981_Y + attribute \src "libresoc.v:187521.18-187521.112" + wire $or$libresoc.v:187521$13948_Y + attribute \src "libresoc.v:187532.18-187532.122" + wire $or$libresoc.v:187532$13959_Y + attribute \src "libresoc.v:187533.18-187533.124" + wire $or$libresoc.v:187533$13960_Y + attribute \src "libresoc.v:187534.18-187534.181" + wire width 5 $or$libresoc.v:187534$13961_Y + attribute \src "libresoc.v:187535.18-187535.168" + wire width 4 $or$libresoc.v:187535$13962_Y + attribute \src "libresoc.v:187539.18-187539.120" + wire width 5 $or$libresoc.v:187539$13966_Y + attribute \src "libresoc.v:187549.17-187549.117" + wire width 4 $or$libresoc.v:187549$13976_Y + attribute \src "libresoc.v:187494.17-187494.104" + wire $reduce_and$libresoc.v:187494$13921_Y + attribute \src "libresoc.v:187516.18-187516.106" + wire $reduce_or$libresoc.v:187516$13943_Y + attribute \src "libresoc.v:187519.18-187519.113" + wire $reduce_or$libresoc.v:187519$13946_Y + attribute \src "libresoc.v:187520.18-187520.112" + wire $reduce_or$libresoc.v:187520$13947_Y + attribute \src "libresoc.v:187545.18-187545.118" + wire width 64 $ternary$libresoc.v:187545$13972_Y + attribute \src "libresoc.v:187546.18-187546.118" + wire width 64 $ternary$libresoc.v:187546$13973_Y + attribute \src "libresoc.v:187547.18-187547.118" + wire width 64 $ternary$libresoc.v:187547$13974_Y + attribute \src "libresoc.v:187548.18-187548.118" + wire width 64 $ternary$libresoc.v:187548$13975_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -382287,23 +392475,23 @@ module \trap0 wire \alu_pulse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 5 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \alu_trap0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire \alu_trap0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire \alu_trap0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \alu_trap0_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" wire \alu_trap0_p_ready_o @@ -382421,6 +392609,10 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_trap0_trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \alu_trap0_trap_op__ldst_exc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \alu_trap0_trap_op__msr$next @@ -382429,9 +392621,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 13 \alu_trap0_trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype + wire width 8 \alu_trap0_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype$next + wire width 8 \alu_trap0_trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \alui_l_q_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -382440,30 +392632,30 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 10 \cu_busy_o + wire output 12 \cu_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire \cu_done_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire \cu_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 9 \cu_issue_i + wire input 11 \cu_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 13 \cu_rd__go_i + wire width 4 input 15 \cu_rd__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 12 \cu_rd__rel_o + wire width 4 output 14 \cu_rd__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 11 \cu_rdmaskn_i + wire width 4 input 13 \cu_rdmaskn_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire \cu_shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 20 \cu_wr__go_i + wire width 5 input 22 \cu_wr__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 19 \cu_wr__rel_o + wire width 5 output 21 \cu_wr__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 5 \cu_wrmask_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" @@ -382507,27 +392699,27 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire \data_r4__msr_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 21 \dest1_o + wire width 64 output 23 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest2_o + wire width 64 output 26 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 25 \dest3_o + wire width 64 output 27 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 27 \dest4_o + wire width 64 output 29 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 22 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 23 \fast2_ok - attribute \src "libresoc.v:181615.7-181615.15" + wire width 64 output 31 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "libresoc.v:186900.7-186900.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 28 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire output 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 20 \o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire \opc_l_q_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -382539,7 +392731,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire \opc_l_s_opc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_trap0__cia + wire width 64 input 6 \oper_i_alu_trap0__cia attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -382554,9 +392746,9 @@ module \trap0 attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \oper_i_alu_trap0__fn_unit + wire width 12 input 3 \oper_i_alu_trap0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_trap0__insn + wire width 32 input 4 \oper_i_alu_trap0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -382632,15 +392824,17 @@ module \trap0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_trap0__insn_type + wire width 7 input 2 \oper_i_alu_trap0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_trap0__is_32bit + wire input 7 \oper_i_alu_trap0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_trap0__msr + wire width 8 input 10 \oper_i_alu_trap0__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \oper_i_alu_trap0__trapaddr + wire width 64 input 5 \oper_i_alu_trap0__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \oper_i_alu_trap0__traptype + wire width 13 input 9 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 8 \oper_i_alu_trap0__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 5 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" @@ -382684,13 +392878,13 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 14 \src1_i + wire width 64 input 16 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src2_i + wire width 64 input 17 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src3_i + wire width 64 input 18 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 17 \src4_i + wire width 64 input 19 \src4_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" @@ -382720,7 +392914,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:182204$13447 + cell $and $and$libresoc.v:187495$13922 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -382728,10 +392922,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:182204$13447_Y + connect \Y $and$libresoc.v:187495$13922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:182205$13448 + cell $and $and$libresoc.v:187496$13923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382739,10 +392933,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:182205$13448_Y + connect \Y $and$libresoc.v:187496$13923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:182206$13449 + cell $and $and$libresoc.v:187497$13924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382750,10 +392944,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:182206$13449_Y + connect \Y $and$libresoc.v:187497$13924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:182207$13450 + cell $and $and$libresoc.v:187498$13925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382761,10 +392955,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:182207$13450_Y + connect \Y $and$libresoc.v:187498$13925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:182208$13451 + cell $and $and$libresoc.v:187499$13926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382772,10 +392966,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:182208$13451_Y + connect \Y $and$libresoc.v:187499$13926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:182209$13452 + cell $and $and$libresoc.v:187500$13927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382783,10 +392977,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:182209$13452_Y + connect \Y $and$libresoc.v:187500$13927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:182210$13453 + cell $and $and$libresoc.v:187501$13928 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382794,10 +392988,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:182210$13453_Y + connect \Y $and$libresoc.v:187501$13928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:182211$13454 + cell $and $and$libresoc.v:187502$13929 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382805,10 +392999,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:182211$13454_Y + connect \Y $and$libresoc.v:187502$13929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:182212$13455 + cell $and $and$libresoc.v:187503$13930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382816,10 +393010,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:182212$13455_Y + connect \Y $and$libresoc.v:187503$13930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:182213$13456 + cell $and $and$libresoc.v:187504$13931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382827,10 +393021,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:182213$13456_Y + connect \Y $and$libresoc.v:187504$13931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:182214$13457 + cell $and $and$libresoc.v:187505$13932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382838,10 +393032,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:182214$13457_Y + connect \Y $and$libresoc.v:187505$13932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:182215$13458 + cell $and $and$libresoc.v:187506$13933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382849,10 +393043,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:182215$13458_Y + connect \Y $and$libresoc.v:187506$13933_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:182216$13459 + cell $and $and$libresoc.v:187507$13934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382860,10 +393054,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:182216$13459_Y + connect \Y $and$libresoc.v:187507$13934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:182217$13460 + cell $and $and$libresoc.v:187508$13935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382871,10 +393065,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:182217$13460_Y + connect \Y $and$libresoc.v:187508$13935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:182219$13462 + cell $and $and$libresoc.v:187510$13937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382882,10 +393076,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:182219$13462_Y + connect \Y $and$libresoc.v:187510$13937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:182221$13464 + cell $and $and$libresoc.v:187512$13939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382893,10 +393087,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:182221$13464_Y + connect \Y $and$libresoc.v:187512$13939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:182222$13465 + cell $and $and$libresoc.v:187513$13940 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382904,10 +393098,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:182222$13465_Y + connect \Y $and$libresoc.v:187513$13940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:182224$13467 + cell $and $and$libresoc.v:187515$13942 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382915,10 +393109,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:182224$13467_Y + connect \Y $and$libresoc.v:187515$13942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:182227$13470 + cell $and $and$libresoc.v:187518$13945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382926,10 +393120,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:182227$13470_Y + connect \Y $and$libresoc.v:187518$13945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:182231$13474 + cell $and $and$libresoc.v:187522$13949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382937,10 +393131,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:182231$13474_Y + connect \Y $and$libresoc.v:187522$13949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:182233$13476 + cell $and $and$libresoc.v:187524$13951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382948,10 +393142,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:182233$13476_Y + connect \Y $and$libresoc.v:187524$13951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:182234$13477 + cell $and $and$libresoc.v:187525$13952 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -382959,10 +393153,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:182234$13477_Y + connect \Y $and$libresoc.v:187525$13952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:182236$13479 + cell $and $and$libresoc.v:187527$13954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382970,10 +393164,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:182236$13479_Y + connect \Y $and$libresoc.v:187527$13954_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:182238$13481 + cell $and $and$libresoc.v:187529$13956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382981,10 +393175,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:182238$13481_Y + connect \Y $and$libresoc.v:187529$13956_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:182239$13482 + cell $and $and$libresoc.v:187530$13957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382992,10 +393186,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:182239$13482_Y + connect \Y $and$libresoc.v:187530$13957_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:182240$13483 + cell $and $and$libresoc.v:187531$13958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383003,10 +393197,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:182240$13483_Y + connect \Y $and$libresoc.v:187531$13958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:182245$13488 + cell $and $and$libresoc.v:187536$13963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383014,10 +393208,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:182245$13488_Y + connect \Y $and$libresoc.v:187536$13963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:182246$13489 + cell $and $and$libresoc.v:187537$13964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -383025,10 +393219,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:182246$13489_Y + connect \Y $and$libresoc.v:187537$13964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:182249$13492 + cell $and $and$libresoc.v:187540$13967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383036,10 +393230,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:182249$13492_Y + connect \Y $and$libresoc.v:187540$13967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:182250$13493 + cell $and $and$libresoc.v:187541$13968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383047,10 +393241,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:182250$13493_Y + connect \Y $and$libresoc.v:187541$13968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:182251$13494 + cell $and $and$libresoc.v:187542$13969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383058,10 +393252,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:182251$13494_Y + connect \Y $and$libresoc.v:187542$13969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:182252$13495 + cell $and $and$libresoc.v:187543$13970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383069,10 +393263,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:182252$13495_Y + connect \Y $and$libresoc.v:187543$13970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:182253$13496 + cell $and $and$libresoc.v:187544$13971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383080,10 +393274,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:182253$13496_Y + connect \Y $and$libresoc.v:187544$13971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:182259$13502 + cell $and $and$libresoc.v:187550$13977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383091,10 +393285,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:182259$13502_Y + connect \Y $and$libresoc.v:187550$13977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:182260$13503 + cell $and $and$libresoc.v:187551$13978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383102,10 +393296,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:182260$13503_Y + connect \Y $and$libresoc.v:187551$13978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:182261$13504 + cell $and $and$libresoc.v:187552$13979 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -383113,10 +393307,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:182261$13504_Y + connect \Y $and$libresoc.v:187552$13979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:182262$13505 + cell $and $and$libresoc.v:187553$13980 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -383124,10 +393318,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:182262$13505_Y + connect \Y $and$libresoc.v:187553$13980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:182235$13478 + cell $eq $eq$libresoc.v:187526$13953 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -383135,10 +393329,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:182235$13478_Y + connect \Y $eq$libresoc.v:187526$13953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:182237$13480 + cell $eq $eq$libresoc.v:187528$13955 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -383146,66 +393340,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:182237$13480_Y + connect \Y $eq$libresoc.v:187528$13955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:182218$13461 + cell $not $not$libresoc.v:187509$13936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:182218$13461_Y + connect \Y $not$libresoc.v:187509$13936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:182220$13463 + cell $not $not$libresoc.v:187511$13938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:182220$13463_Y + connect \Y $not$libresoc.v:187511$13938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:182223$13466 + cell $not $not$libresoc.v:187514$13941 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:182223$13466_Y + connect \Y $not$libresoc.v:187514$13941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:182226$13469 + cell $not $not$libresoc.v:187517$13944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:182226$13469_Y + connect \Y $not$libresoc.v:187517$13944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:182232$13475 + cell $not $not$libresoc.v:187523$13950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:182232$13475_Y + connect \Y $not$libresoc.v:187523$13950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:182247$13490 + cell $not $not$libresoc.v:187538$13965 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:182247$13490_Y + connect \Y $not$libresoc.v:187538$13965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:182263$13506 + cell $not $not$libresoc.v:187554$13981 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:182263$13506_Y + connect \Y $not$libresoc.v:187554$13981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:182230$13473 + cell $or $or$libresoc.v:187521$13948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383213,10 +393407,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:182230$13473_Y + connect \Y $or$libresoc.v:187521$13948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:182241$13484 + cell $or $or$libresoc.v:187532$13959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383224,10 +393418,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:182241$13484_Y + connect \Y $or$libresoc.v:187532$13959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:182242$13485 + cell $or $or$libresoc.v:187533$13960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383235,10 +393429,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:182242$13485_Y + connect \Y $or$libresoc.v:187533$13960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:182243$13486 + cell $or $or$libresoc.v:187534$13961 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -383246,10 +393440,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:182243$13486_Y + connect \Y $or$libresoc.v:187534$13961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:182244$13487 + cell $or $or$libresoc.v:187535$13962 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -383257,10 +393451,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:182244$13487_Y + connect \Y $or$libresoc.v:187535$13962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:182248$13491 + cell $or $or$libresoc.v:187539$13966 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -383268,10 +393462,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:182248$13491_Y + connect \Y $or$libresoc.v:187539$13966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:182258$13501 + cell $or $or$libresoc.v:187549$13976 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -383279,75 +393473,75 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:182258$13501_Y + connect \Y $or$libresoc.v:187549$13976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:182203$13446 + cell $reduce_and $reduce_and$libresoc.v:187494$13921 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:182203$13446_Y + connect \Y $reduce_and$libresoc.v:187494$13921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:182225$13468 + cell $reduce_or $reduce_or$libresoc.v:187516$13943 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:182225$13468_Y + connect \Y $reduce_or$libresoc.v:187516$13943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:182228$13471 + cell $reduce_or $reduce_or$libresoc.v:187519$13946 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:182228$13471_Y + connect \Y $reduce_or$libresoc.v:187519$13946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:182229$13472 + cell $reduce_or $reduce_or$libresoc.v:187520$13947 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:182229$13472_Y + connect \Y $reduce_or$libresoc.v:187520$13947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:182254$13497 + cell $mux $ternary$libresoc.v:187545$13972 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:182254$13497_Y + connect \Y $ternary$libresoc.v:187545$13972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:182255$13498 + cell $mux $ternary$libresoc.v:187546$13973 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:182255$13498_Y + connect \Y $ternary$libresoc.v:187546$13973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:182256$13499 + cell $mux $ternary$libresoc.v:187547$13974 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:182256$13499_Y + connect \Y $ternary$libresoc.v:187547$13974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:182257$13500 + cell $mux $ternary$libresoc.v:187548$13975 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:182257$13500_Y + connect \Y $ternary$libresoc.v:187548$13975_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:182338.14-182344.4" - cell \alu_l$42 \alu_l + attribute \src "libresoc.v:187631.14-187637.4" + cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -383355,7 +393549,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:182345.13-182374.4" + attribute \src "libresoc.v:187638.13-187668.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -383382,13 +393576,14 @@ module \trap0 connect \trap_op__insn \alu_trap0_trap_op__insn connect \trap_op__insn_type \alu_trap0_trap_op__insn_type connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc connect \trap_op__msr \alu_trap0_trap_op__msr connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:182375.15-182381.4" - cell \alui_l$41 \alui_l + attribute \src "libresoc.v:187669.15-187675.4" + cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -383396,8 +393591,8 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:182382.14-182388.4" - cell \opc_l$37 \opc_l + attribute \src "libresoc.v:187676.14-187682.4" + cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -383405,8 +393600,8 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:182389.14-182395.4" - cell \req_l$38 \req_l + attribute \src "libresoc.v:187683.14-187689.4" + cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -383414,8 +393609,8 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:182396.14-182402.4" - cell \rok_l$40 \rok_l + attribute \src "libresoc.v:187690.14-187696.4" + cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -383423,593 +393618,608 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:182403.14-182408.4" - cell \rst_l$39 \rst_l + attribute \src "libresoc.v:187697.14-187702.4" + cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \r_rst \rst_l_r_rst connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:182409.14-182415.4" - cell \src_l$36 \src_l + attribute \src "libresoc.v:187703.14-187709.4" + cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_src \src_l_q_src connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:181615.7-181615.20" - process $proc$libresoc.v:181615$13658 + attribute \src "libresoc.v:186900.7-186900.20" + process $proc$libresoc.v:186900$14136 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181741.7-181741.24" - process $proc$libresoc.v:181741$13659 + attribute \src "libresoc.v:187026.7-187026.24" + process $proc$libresoc.v:187026$14137 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:181751.7-181751.26" - process $proc$libresoc.v:181751$13660 + attribute \src "libresoc.v:187036.7-187036.26" + process $proc$libresoc.v:187036$14138 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:181759.7-181759.25" - process $proc$libresoc.v:181759$13661 + attribute \src "libresoc.v:187044.7-187044.25" + process $proc$libresoc.v:187044$14139 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:181795.14-181795.59" - process $proc$libresoc.v:181795$13662 + attribute \src "libresoc.v:187080.14-187080.59" + process $proc$libresoc.v:187080$14140 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:181812.14-181812.50" - process $proc$libresoc.v:181812$13663 + attribute \src "libresoc.v:187097.14-187097.50" + process $proc$libresoc.v:187097$14141 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:181816.14-181816.45" - process $proc$libresoc.v:181816$13664 + attribute \src "libresoc.v:187101.14-187101.45" + process $proc$libresoc.v:187101$14142 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:181894.13-181894.49" - process $proc$libresoc.v:181894$13665 + attribute \src "libresoc.v:187179.13-187179.49" + process $proc$libresoc.v:187179$14143 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:181898.7-181898.41" - process $proc$libresoc.v:181898$13666 + attribute \src "libresoc.v:187183.7-187183.41" + process $proc$libresoc.v:187183$14144 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:181902.14-181902.59" - process $proc$libresoc.v:181902$13667 + attribute \src "libresoc.v:187187.13-187187.48" + process $proc$libresoc.v:187187$14145 + assign { } { } + assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:187191.14-187191.59" + process $proc$libresoc.v:187191$14146 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:181906.14-181906.52" - process $proc$libresoc.v:181906$13668 + attribute \src "libresoc.v:187195.14-187195.52" + process $proc$libresoc.v:187195$14147 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:181910.13-181910.48" - process $proc$libresoc.v:181910$13669 + attribute \src "libresoc.v:187199.13-187199.48" + process $proc$libresoc.v:187199$14148 assign { } { } - assign $1\alu_trap0_trap_op__traptype[6:0] 7'0000000 + assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init - update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[6:0] + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:181916.7-181916.27" - process $proc$libresoc.v:181916$13670 + attribute \src "libresoc.v:187205.7-187205.27" + process $proc$libresoc.v:187205$14149 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:181948.14-181948.47" - process $proc$libresoc.v:181948$13671 + attribute \src "libresoc.v:187237.14-187237.47" + process $proc$libresoc.v:187237$14150 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:181952.7-181952.27" - process $proc$libresoc.v:181952$13672 + attribute \src "libresoc.v:187241.7-187241.27" + process $proc$libresoc.v:187241$14151 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:181956.14-181956.51" - process $proc$libresoc.v:181956$13673 + attribute \src "libresoc.v:187245.14-187245.51" + process $proc$libresoc.v:187245$14152 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:181960.7-181960.31" - process $proc$libresoc.v:181960$13674 + attribute \src "libresoc.v:187249.7-187249.31" + process $proc$libresoc.v:187249$14153 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:181964.14-181964.51" - process $proc$libresoc.v:181964$13675 + attribute \src "libresoc.v:187253.14-187253.51" + process $proc$libresoc.v:187253$14154 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:181968.7-181968.31" - process $proc$libresoc.v:181968$13676 + attribute \src "libresoc.v:187257.7-187257.31" + process $proc$libresoc.v:187257$14155 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:181972.14-181972.49" - process $proc$libresoc.v:181972$13677 + attribute \src "libresoc.v:187261.14-187261.49" + process $proc$libresoc.v:187261$14156 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:181976.7-181976.29" - process $proc$libresoc.v:181976$13678 + attribute \src "libresoc.v:187265.7-187265.29" + process $proc$libresoc.v:187265$14157 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:181980.14-181980.49" - process $proc$libresoc.v:181980$13679 + attribute \src "libresoc.v:187269.14-187269.49" + process $proc$libresoc.v:187269$14158 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:181984.7-181984.29" - process $proc$libresoc.v:181984$13680 + attribute \src "libresoc.v:187273.7-187273.29" + process $proc$libresoc.v:187273$14159 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:182015.7-182015.25" - process $proc$libresoc.v:182015$13681 + attribute \src "libresoc.v:187304.7-187304.25" + process $proc$libresoc.v:187304$14160 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:182019.7-182019.25" - process $proc$libresoc.v:182019$13682 + attribute \src "libresoc.v:187308.7-187308.25" + process $proc$libresoc.v:187308$14161 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:182126.13-182126.31" - process $proc$libresoc.v:182126$13683 + attribute \src "libresoc.v:187417.13-187417.31" + process $proc$libresoc.v:187417$14162 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:182134.13-182134.32" - process $proc$libresoc.v:182134$13684 + attribute \src "libresoc.v:187425.13-187425.32" + process $proc$libresoc.v:187425$14163 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:182138.13-182138.32" - process $proc$libresoc.v:182138$13685 + attribute \src "libresoc.v:187429.13-187429.32" + process $proc$libresoc.v:187429$14164 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:182150.7-182150.26" - process $proc$libresoc.v:182150$13686 + attribute \src "libresoc.v:187441.7-187441.26" + process $proc$libresoc.v:187441$14165 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:182154.7-182154.26" - process $proc$libresoc.v:182154$13687 + attribute \src "libresoc.v:187445.7-187445.26" + process $proc$libresoc.v:187445$14166 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:182158.7-182158.25" - process $proc$libresoc.v:182158$13688 + attribute \src "libresoc.v:187449.7-187449.25" + process $proc$libresoc.v:187449$14167 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:182162.7-182162.25" - process $proc$libresoc.v:182162$13689 + attribute \src "libresoc.v:187453.7-187453.25" + process $proc$libresoc.v:187453$14168 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:182178.13-182178.31" - process $proc$libresoc.v:182178$13690 + attribute \src "libresoc.v:187469.13-187469.31" + process $proc$libresoc.v:187469$14169 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:182182.13-182182.31" - process $proc$libresoc.v:182182$13691 + attribute \src "libresoc.v:187473.13-187473.31" + process $proc$libresoc.v:187473$14170 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:182186.14-182186.43" - process $proc$libresoc.v:182186$13692 + attribute \src "libresoc.v:187477.14-187477.43" + process $proc$libresoc.v:187477$14171 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:182190.14-182190.43" - process $proc$libresoc.v:182190$13693 + attribute \src "libresoc.v:187481.14-187481.43" + process $proc$libresoc.v:187481$14172 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:182194.14-182194.43" - process $proc$libresoc.v:182194$13694 + attribute \src "libresoc.v:187485.14-187485.43" + process $proc$libresoc.v:187485$14173 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:182198.14-182198.43" - process $proc$libresoc.v:182198$13695 + attribute \src "libresoc.v:187489.14-187489.43" + process $proc$libresoc.v:187489$14174 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:182264.3-182265.39" - process $proc$libresoc.v:182264$13507 + attribute \src "libresoc.v:187555.3-187556.39" + process $proc$libresoc.v:187555$13982 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:182266.3-182267.43" - process $proc$libresoc.v:182266$13508 + attribute \src "libresoc.v:187557.3-187558.43" + process $proc$libresoc.v:187557$13983 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:182268.3-182269.29" - process $proc$libresoc.v:182268$13509 + attribute \src "libresoc.v:187559.3-187560.29" + process $proc$libresoc.v:187559$13984 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:182270.3-182271.29" - process $proc$libresoc.v:182270$13510 + attribute \src "libresoc.v:187561.3-187562.29" + process $proc$libresoc.v:187561$13985 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:182272.3-182273.29" - process $proc$libresoc.v:182272$13511 + attribute \src "libresoc.v:187563.3-187564.29" + process $proc$libresoc.v:187563$13986 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:182274.3-182275.29" - process $proc$libresoc.v:182274$13512 + attribute \src "libresoc.v:187565.3-187566.29" + process $proc$libresoc.v:187565$13987 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:182276.3-182277.41" - process $proc$libresoc.v:182276$13513 + attribute \src "libresoc.v:187567.3-187568.41" + process $proc$libresoc.v:187567$13988 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:182278.3-182279.47" - process $proc$libresoc.v:182278$13514 + attribute \src "libresoc.v:187569.3-187570.47" + process $proc$libresoc.v:187569$13989 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:182280.3-182281.41" - process $proc$libresoc.v:182280$13515 + attribute \src "libresoc.v:187571.3-187572.41" + process $proc$libresoc.v:187571$13990 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:182282.3-182283.47" - process $proc$libresoc.v:182282$13516 + attribute \src "libresoc.v:187573.3-187574.47" + process $proc$libresoc.v:187573$13991 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:182284.3-182285.45" - process $proc$libresoc.v:182284$13517 + attribute \src "libresoc.v:187575.3-187576.45" + process $proc$libresoc.v:187575$13992 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:182286.3-182287.51" - process $proc$libresoc.v:182286$13518 + attribute \src "libresoc.v:187577.3-187578.51" + process $proc$libresoc.v:187577$13993 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:182288.3-182289.45" - process $proc$libresoc.v:182288$13519 + attribute \src "libresoc.v:187579.3-187580.45" + process $proc$libresoc.v:187579$13994 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:182290.3-182291.51" - process $proc$libresoc.v:182290$13520 + attribute \src "libresoc.v:187581.3-187582.51" + process $proc$libresoc.v:187581$13995 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:182292.3-182293.37" - process $proc$libresoc.v:182292$13521 + attribute \src "libresoc.v:187583.3-187584.37" + process $proc$libresoc.v:187583$13996 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:182294.3-182295.43" - process $proc$libresoc.v:182294$13522 + attribute \src "libresoc.v:187585.3-187586.43" + process $proc$libresoc.v:187585$13997 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:182296.3-182297.73" - process $proc$libresoc.v:182296$13523 + attribute \src "libresoc.v:187587.3-187588.73" + process $proc$libresoc.v:187587$13998 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:182298.3-182299.69" - process $proc$libresoc.v:182298$13524 + attribute \src "libresoc.v:187589.3-187590.69" + process $proc$libresoc.v:187589$13999 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] end - attribute \src "libresoc.v:182300.3-182301.63" - process $proc$libresoc.v:182300$13525 + attribute \src "libresoc.v:187591.3-187592.63" + process $proc$libresoc.v:187591$14000 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:182302.3-182303.61" - process $proc$libresoc.v:182302$13526 + attribute \src "libresoc.v:187593.3-187594.61" + process $proc$libresoc.v:187593$14001 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:182304.3-182305.61" - process $proc$libresoc.v:182304$13527 + attribute \src "libresoc.v:187595.3-187596.61" + process $proc$libresoc.v:187595$14002 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:182306.3-182307.71" - process $proc$libresoc.v:182306$13528 + attribute \src "libresoc.v:187597.3-187598.71" + process $proc$libresoc.v:187597$14003 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:182308.3-182309.71" - process $proc$libresoc.v:182308$13529 + attribute \src "libresoc.v:187599.3-187600.71" + process $proc$libresoc.v:187599$14004 assign { } { } - assign $0\alu_trap0_trap_op__traptype[6:0] \alu_trap0_trap_op__traptype$next + assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk - update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[6:0] + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:182310.3-182311.71" - process $proc$libresoc.v:182310$13530 + attribute \src "libresoc.v:187601.3-187602.71" + process $proc$libresoc.v:187601$14005 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:182312.3-182313.39" - process $proc$libresoc.v:182312$13531 + attribute \src "libresoc.v:187603.3-187604.71" + process $proc$libresoc.v:187603$14006 + assign { } { } + assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:187605.3-187606.39" + process $proc$libresoc.v:187605$14007 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:182314.3-182315.39" - process $proc$libresoc.v:182314$13532 + attribute \src "libresoc.v:187607.3-187608.39" + process $proc$libresoc.v:187607$14008 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:182316.3-182317.39" - process $proc$libresoc.v:182316$13533 + attribute \src "libresoc.v:187609.3-187610.39" + process $proc$libresoc.v:187609$14009 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:182318.3-182319.39" - process $proc$libresoc.v:182318$13534 + attribute \src "libresoc.v:187611.3-187612.39" + process $proc$libresoc.v:187611$14010 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:182320.3-182321.39" - process $proc$libresoc.v:182320$13535 + attribute \src "libresoc.v:187613.3-187614.39" + process $proc$libresoc.v:187613$14011 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:182322.3-182323.39" - process $proc$libresoc.v:182322$13536 + attribute \src "libresoc.v:187615.3-187616.39" + process $proc$libresoc.v:187615$14012 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:182324.3-182325.39" - process $proc$libresoc.v:182324$13537 + attribute \src "libresoc.v:187617.3-187618.39" + process $proc$libresoc.v:187617$14013 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:182326.3-182327.39" - process $proc$libresoc.v:182326$13538 + attribute \src "libresoc.v:187619.3-187620.39" + process $proc$libresoc.v:187619$14014 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:182328.3-182329.41" - process $proc$libresoc.v:182328$13539 + attribute \src "libresoc.v:187621.3-187622.41" + process $proc$libresoc.v:187621$14015 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:182330.3-182331.41" - process $proc$libresoc.v:182330$13540 + attribute \src "libresoc.v:187623.3-187624.41" + process $proc$libresoc.v:187623$14016 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:182332.3-182333.37" - process $proc$libresoc.v:182332$13541 + attribute \src "libresoc.v:187625.3-187626.37" + process $proc$libresoc.v:187625$14017 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:182334.3-182335.41" - process $proc$libresoc.v:182334$13542 + attribute \src "libresoc.v:187627.3-187628.41" + process $proc$libresoc.v:187627$14018 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:182336.3-182337.25" - process $proc$libresoc.v:182336$13543 + attribute \src "libresoc.v:187629.3-187630.25" + process $proc$libresoc.v:187629$14019 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:182416.3-182425.6" - process $proc$libresoc.v:182416$13544 + attribute \src "libresoc.v:187710.3-187719.6" + process $proc$libresoc.v:187710$14020 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:182417.5-182417.29" + attribute \src "libresoc.v:187711.5-187711.29" switch \initial - attribute \src "libresoc.v:182417.9-182417.17" + attribute \src "libresoc.v:187711.9-187711.17" case 1'1 case end @@ -384025,14 +394235,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:182426.3-182434.6" - process $proc$libresoc.v:182426$13545 + attribute \src "libresoc.v:187720.3-187728.6" + process $proc$libresoc.v:187720$14021 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13546 $1\rok_l_s_rdok$next[0:0]$13547 - attribute \src "libresoc.v:182427.5-182427.29" + assign $0\rok_l_s_rdok$next[0:0]$14022 $1\rok_l_s_rdok$next[0:0]$14023 + attribute \src "libresoc.v:187721.5-187721.29" switch \initial - attribute \src "libresoc.v:182427.9-182427.17" + attribute \src "libresoc.v:187721.9-187721.17" case 1'1 case end @@ -384041,21 +394251,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13547 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14023 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$13547 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14023 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13546 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14022 end - attribute \src "libresoc.v:182435.3-182443.6" - process $proc$libresoc.v:182435$13548 + attribute \src "libresoc.v:187729.3-187737.6" + process $proc$libresoc.v:187729$14024 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13549 $1\rok_l_r_rdok$next[0:0]$13550 - attribute \src "libresoc.v:182436.5-182436.29" + assign $0\rok_l_r_rdok$next[0:0]$14025 $1\rok_l_r_rdok$next[0:0]$14026 + attribute \src "libresoc.v:187730.5-187730.29" switch \initial - attribute \src "libresoc.v:182436.9-182436.17" + attribute \src "libresoc.v:187730.9-187730.17" case 1'1 case end @@ -384064,21 +394274,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13550 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14026 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$13550 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14026 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13549 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14025 end - attribute \src "libresoc.v:182444.3-182452.6" - process $proc$libresoc.v:182444$13551 + attribute \src "libresoc.v:187738.3-187746.6" + process $proc$libresoc.v:187738$14027 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13552 $1\rst_l_s_rst$next[0:0]$13553 - attribute \src "libresoc.v:182445.5-182445.29" + assign $0\rst_l_s_rst$next[0:0]$14028 $1\rst_l_s_rst$next[0:0]$14029 + attribute \src "libresoc.v:187739.5-187739.29" switch \initial - attribute \src "libresoc.v:182445.9-182445.17" + attribute \src "libresoc.v:187739.9-187739.17" case 1'1 case end @@ -384087,21 +394297,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13553 1'0 + assign $1\rst_l_s_rst$next[0:0]$14029 1'0 case - assign $1\rst_l_s_rst$next[0:0]$13553 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14029 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13552 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14028 end - attribute \src "libresoc.v:182453.3-182461.6" - process $proc$libresoc.v:182453$13554 + attribute \src "libresoc.v:187747.3-187755.6" + process $proc$libresoc.v:187747$14030 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13555 $1\rst_l_r_rst$next[0:0]$13556 - attribute \src "libresoc.v:182454.5-182454.29" + assign $0\rst_l_r_rst$next[0:0]$14031 $1\rst_l_r_rst$next[0:0]$14032 + attribute \src "libresoc.v:187748.5-187748.29" switch \initial - attribute \src "libresoc.v:182454.9-182454.17" + attribute \src "libresoc.v:187748.9-187748.17" case 1'1 case end @@ -384110,21 +394320,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13556 1'1 + assign $1\rst_l_r_rst$next[0:0]$14032 1'1 case - assign $1\rst_l_r_rst$next[0:0]$13556 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14032 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13555 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14031 end - attribute \src "libresoc.v:182462.3-182470.6" - process $proc$libresoc.v:182462$13557 + attribute \src "libresoc.v:187756.3-187764.6" + process $proc$libresoc.v:187756$14033 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$13558 $1\opc_l_s_opc$next[0:0]$13559 - attribute \src "libresoc.v:182463.5-182463.29" + assign $0\opc_l_s_opc$next[0:0]$14034 $1\opc_l_s_opc$next[0:0]$14035 + attribute \src "libresoc.v:187757.5-187757.29" switch \initial - attribute \src "libresoc.v:182463.9-182463.17" + attribute \src "libresoc.v:187757.9-187757.17" case 1'1 case end @@ -384133,21 +394343,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$13559 1'0 + assign $1\opc_l_s_opc$next[0:0]$14035 1'0 case - assign $1\opc_l_s_opc$next[0:0]$13559 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14035 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13558 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14034 end - attribute \src "libresoc.v:182471.3-182479.6" - process $proc$libresoc.v:182471$13560 + attribute \src "libresoc.v:187765.3-187773.6" + process $proc$libresoc.v:187765$14036 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$13561 $1\opc_l_r_opc$next[0:0]$13562 - attribute \src "libresoc.v:182472.5-182472.29" + assign $0\opc_l_r_opc$next[0:0]$14037 $1\opc_l_r_opc$next[0:0]$14038 + attribute \src "libresoc.v:187766.5-187766.29" switch \initial - attribute \src "libresoc.v:182472.9-182472.17" + attribute \src "libresoc.v:187766.9-187766.17" case 1'1 case end @@ -384156,21 +394366,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$13562 1'1 + assign $1\opc_l_r_opc$next[0:0]$14038 1'1 case - assign $1\opc_l_r_opc$next[0:0]$13562 \req_done + assign $1\opc_l_r_opc$next[0:0]$14038 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13561 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14037 end - attribute \src "libresoc.v:182480.3-182488.6" - process $proc$libresoc.v:182480$13563 + attribute \src "libresoc.v:187774.3-187782.6" + process $proc$libresoc.v:187774$14039 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$13564 $1\src_l_s_src$next[3:0]$13565 - attribute \src "libresoc.v:182481.5-182481.29" + assign $0\src_l_s_src$next[3:0]$14040 $1\src_l_s_src$next[3:0]$14041 + attribute \src "libresoc.v:187775.5-187775.29" switch \initial - attribute \src "libresoc.v:182481.9-182481.17" + attribute \src "libresoc.v:187775.9-187775.17" case 1'1 case end @@ -384179,21 +394389,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$13565 4'0000 + assign $1\src_l_s_src$next[3:0]$14041 4'0000 case - assign $1\src_l_s_src$next[3:0]$13565 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14041 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13564 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14040 end - attribute \src "libresoc.v:182489.3-182497.6" - process $proc$libresoc.v:182489$13566 + attribute \src "libresoc.v:187783.3-187791.6" + process $proc$libresoc.v:187783$14042 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$13567 $1\src_l_r_src$next[3:0]$13568 - attribute \src "libresoc.v:182490.5-182490.29" + assign $0\src_l_r_src$next[3:0]$14043 $1\src_l_r_src$next[3:0]$14044 + attribute \src "libresoc.v:187784.5-187784.29" switch \initial - attribute \src "libresoc.v:182490.9-182490.17" + attribute \src "libresoc.v:187784.9-187784.17" case 1'1 case end @@ -384202,21 +394412,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$13568 4'1111 + assign $1\src_l_r_src$next[3:0]$14044 4'1111 case - assign $1\src_l_r_src$next[3:0]$13568 \reset_r + assign $1\src_l_r_src$next[3:0]$14044 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13567 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14043 end - attribute \src "libresoc.v:182498.3-182506.6" - process $proc$libresoc.v:182498$13569 + attribute \src "libresoc.v:187792.3-187800.6" + process $proc$libresoc.v:187792$14045 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$13570 $1\req_l_s_req$next[4:0]$13571 - attribute \src "libresoc.v:182499.5-182499.29" + assign $0\req_l_s_req$next[4:0]$14046 $1\req_l_s_req$next[4:0]$14047 + attribute \src "libresoc.v:187793.5-187793.29" switch \initial - attribute \src "libresoc.v:182499.9-182499.17" + attribute \src "libresoc.v:187793.9-187793.17" case 1'1 case end @@ -384225,21 +394435,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$13571 5'00000 + assign $1\req_l_s_req$next[4:0]$14047 5'00000 case - assign $1\req_l_s_req$next[4:0]$13571 \$67 + assign $1\req_l_s_req$next[4:0]$14047 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13570 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14046 end - attribute \src "libresoc.v:182507.3-182515.6" - process $proc$libresoc.v:182507$13572 + attribute \src "libresoc.v:187801.3-187809.6" + process $proc$libresoc.v:187801$14048 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$13573 $1\req_l_r_req$next[4:0]$13574 - attribute \src "libresoc.v:182508.5-182508.29" + assign $0\req_l_r_req$next[4:0]$14049 $1\req_l_r_req$next[4:0]$14050 + attribute \src "libresoc.v:187802.5-187802.29" switch \initial - attribute \src "libresoc.v:182508.9-182508.17" + attribute \src "libresoc.v:187802.9-187802.17" case 1'1 case end @@ -384248,15 +394458,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$13574 5'11111 + assign $1\req_l_r_req$next[4:0]$14050 5'11111 case - assign $1\req_l_r_req$next[4:0]$13574 \$69 + assign $1\req_l_r_req$next[4:0]$14050 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13573 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14049 end - attribute \src "libresoc.v:182516.3-182532.6" - process $proc$libresoc.v:182516$13575 + attribute \src "libresoc.v:187810.3-187827.6" + process $proc$libresoc.v:187810$14051 assign { } { } assign { } { } assign { } { } @@ -384273,17 +394483,20 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$13576 $1\alu_trap0_trap_op__cia$next[63:0]$13584 - assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 - assign $0\alu_trap0_trap_op__insn$next[31:0]$13578 $1\alu_trap0_trap_op__insn$next[31:0]$13586 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 - assign $0\alu_trap0_trap_op__msr$next[63:0]$13581 $1\alu_trap0_trap_op__msr$next[63:0]$13589 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 - assign $0\alu_trap0_trap_op__traptype$next[6:0]$13583 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 - attribute \src "libresoc.v:182517.5-182517.29" + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$14052 $1\alu_trap0_trap_op__cia$next[63:0]$14061 + assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14054 $1\alu_trap0_trap_op__insn$next[31:0]$14063 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14058 $1\alu_trap0_trap_op__msr$next[63:0]$14067 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14060 $1\alu_trap0_trap_op__traptype$next[7:0]$14069 + attribute \src "libresoc.v:187811.5-187811.29" switch \initial - attribute \src "libresoc.v:182517.9-182517.17" + attribute \src "libresoc.v:187811.9-187811.17" case 1'1 case end @@ -384299,41 +394512,44 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 $1\alu_trap0_trap_op__traptype$next[6:0]$13591 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 $1\alu_trap0_trap_op__cia$next[63:0]$13584 $1\alu_trap0_trap_op__msr$next[63:0]$13589 $1\alu_trap0_trap_op__insn$next[31:0]$13586 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { } { } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 $1\alu_trap0_trap_op__traptype$next[7:0]$14069 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 $1\alu_trap0_trap_op__cia$next[63:0]$14061 $1\alu_trap0_trap_op__msr$next[63:0]$14067 $1\alu_trap0_trap_op__insn$next[31:0]$14063 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$13584 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$13585 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$13586 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13587 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13588 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__msr$next[63:0]$13589 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13590 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[6:0]$13591 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14061 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14063 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14067 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14069 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13576 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$13577 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13578 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13579 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13580 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13581 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13582 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[6:0]$13583 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14052 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14054 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14058 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14060 end - attribute \src "libresoc.v:182533.3-182554.6" - process $proc$libresoc.v:182533$13592 + attribute \src "libresoc.v:187828.3-187849.6" + process $proc$libresoc.v:187828$14070 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$13593 $2\data_r0__o$next[63:0]$13597 + assign $0\data_r0__o$next[63:0]$14071 $2\data_r0__o$next[63:0]$14075 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$13594 $3\data_r0__o_ok$next[0:0]$13599 - attribute \src "libresoc.v:182534.5-182534.29" + assign $0\data_r0__o_ok$next[0:0]$14072 $3\data_r0__o_ok$next[0:0]$14077 + attribute \src "libresoc.v:187829.5-187829.29" switch \initial - attribute \src "libresoc.v:182534.9-182534.17" + attribute \src "libresoc.v:187829.9-187829.17" case 1'1 case end @@ -384343,10 +394559,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$13596 $1\data_r0__o$next[63:0]$13595 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14074 $1\data_r0__o$next[63:0]$14073 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$13595 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$13596 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14073 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14074 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -384354,38 +394570,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$13598 $2\data_r0__o$next[63:0]$13597 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14076 $2\data_r0__o$next[63:0]$14075 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$13597 $1\data_r0__o$next[63:0]$13595 - assign $2\data_r0__o_ok$next[0:0]$13598 $1\data_r0__o_ok$next[0:0]$13596 + assign $2\data_r0__o$next[63:0]$14075 $1\data_r0__o$next[63:0]$14073 + assign $2\data_r0__o_ok$next[0:0]$14076 $1\data_r0__o_ok$next[0:0]$14074 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$13599 1'0 + assign $3\data_r0__o_ok$next[0:0]$14077 1'0 case - assign $3\data_r0__o_ok$next[0:0]$13599 $2\data_r0__o_ok$next[0:0]$13598 + assign $3\data_r0__o_ok$next[0:0]$14077 $2\data_r0__o_ok$next[0:0]$14076 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$13593 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13594 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14071 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14072 end - attribute \src "libresoc.v:182555.3-182576.6" - process $proc$libresoc.v:182555$13600 + attribute \src "libresoc.v:187850.3-187871.6" + process $proc$libresoc.v:187850$14078 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$13601 $2\data_r1__fast1$next[63:0]$13605 + assign $0\data_r1__fast1$next[63:0]$14079 $2\data_r1__fast1$next[63:0]$14083 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$13602 $3\data_r1__fast1_ok$next[0:0]$13607 - attribute \src "libresoc.v:182556.5-182556.29" + assign $0\data_r1__fast1_ok$next[0:0]$14080 $3\data_r1__fast1_ok$next[0:0]$14085 + attribute \src "libresoc.v:187851.5-187851.29" switch \initial - attribute \src "libresoc.v:182556.9-182556.17" + attribute \src "libresoc.v:187851.9-187851.17" case 1'1 case end @@ -384395,10 +394611,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$13604 $1\data_r1__fast1$next[63:0]$13603 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14082 $1\data_r1__fast1$next[63:0]$14081 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$13603 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$13604 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14081 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14082 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -384406,38 +394622,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$13606 $2\data_r1__fast1$next[63:0]$13605 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14084 $2\data_r1__fast1$next[63:0]$14083 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$13605 $1\data_r1__fast1$next[63:0]$13603 - assign $2\data_r1__fast1_ok$next[0:0]$13606 $1\data_r1__fast1_ok$next[0:0]$13604 + assign $2\data_r1__fast1$next[63:0]$14083 $1\data_r1__fast1$next[63:0]$14081 + assign $2\data_r1__fast1_ok$next[0:0]$14084 $1\data_r1__fast1_ok$next[0:0]$14082 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$13607 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14085 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$13607 $2\data_r1__fast1_ok$next[0:0]$13606 + assign $3\data_r1__fast1_ok$next[0:0]$14085 $2\data_r1__fast1_ok$next[0:0]$14084 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13601 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13602 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14079 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14080 end - attribute \src "libresoc.v:182577.3-182598.6" - process $proc$libresoc.v:182577$13608 + attribute \src "libresoc.v:187872.3-187893.6" + process $proc$libresoc.v:187872$14086 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$13609 $2\data_r2__fast2$next[63:0]$13613 + assign $0\data_r2__fast2$next[63:0]$14087 $2\data_r2__fast2$next[63:0]$14091 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$13610 $3\data_r2__fast2_ok$next[0:0]$13615 - attribute \src "libresoc.v:182578.5-182578.29" + assign $0\data_r2__fast2_ok$next[0:0]$14088 $3\data_r2__fast2_ok$next[0:0]$14093 + attribute \src "libresoc.v:187873.5-187873.29" switch \initial - attribute \src "libresoc.v:182578.9-182578.17" + attribute \src "libresoc.v:187873.9-187873.17" case 1'1 case end @@ -384447,10 +394663,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$13612 $1\data_r2__fast2$next[63:0]$13611 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14090 $1\data_r2__fast2$next[63:0]$14089 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$13611 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$13612 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14089 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14090 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -384458,38 +394674,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$13614 $2\data_r2__fast2$next[63:0]$13613 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14092 $2\data_r2__fast2$next[63:0]$14091 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$13613 $1\data_r2__fast2$next[63:0]$13611 - assign $2\data_r2__fast2_ok$next[0:0]$13614 $1\data_r2__fast2_ok$next[0:0]$13612 + assign $2\data_r2__fast2$next[63:0]$14091 $1\data_r2__fast2$next[63:0]$14089 + assign $2\data_r2__fast2_ok$next[0:0]$14092 $1\data_r2__fast2_ok$next[0:0]$14090 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$13615 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14093 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$13615 $2\data_r2__fast2_ok$next[0:0]$13614 + assign $3\data_r2__fast2_ok$next[0:0]$14093 $2\data_r2__fast2_ok$next[0:0]$14092 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13609 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13610 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14087 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14088 end - attribute \src "libresoc.v:182599.3-182620.6" - process $proc$libresoc.v:182599$13616 + attribute \src "libresoc.v:187894.3-187915.6" + process $proc$libresoc.v:187894$14094 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$13617 $2\data_r3__nia$next[63:0]$13621 + assign $0\data_r3__nia$next[63:0]$14095 $2\data_r3__nia$next[63:0]$14099 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$13618 $3\data_r3__nia_ok$next[0:0]$13623 - attribute \src "libresoc.v:182600.5-182600.29" + assign $0\data_r3__nia_ok$next[0:0]$14096 $3\data_r3__nia_ok$next[0:0]$14101 + attribute \src "libresoc.v:187895.5-187895.29" switch \initial - attribute \src "libresoc.v:182600.9-182600.17" + attribute \src "libresoc.v:187895.9-187895.17" case 1'1 case end @@ -384499,10 +394715,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$13620 $1\data_r3__nia$next[63:0]$13619 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14098 $1\data_r3__nia$next[63:0]$14097 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$13619 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$13620 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14097 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14098 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -384510,38 +394726,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$13622 $2\data_r3__nia$next[63:0]$13621 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14100 $2\data_r3__nia$next[63:0]$14099 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$13621 $1\data_r3__nia$next[63:0]$13619 - assign $2\data_r3__nia_ok$next[0:0]$13622 $1\data_r3__nia_ok$next[0:0]$13620 + assign $2\data_r3__nia$next[63:0]$14099 $1\data_r3__nia$next[63:0]$14097 + assign $2\data_r3__nia_ok$next[0:0]$14100 $1\data_r3__nia_ok$next[0:0]$14098 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$13623 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14101 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$13623 $2\data_r3__nia_ok$next[0:0]$13622 + assign $3\data_r3__nia_ok$next[0:0]$14101 $2\data_r3__nia_ok$next[0:0]$14100 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$13617 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$13618 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14095 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14096 end - attribute \src "libresoc.v:182621.3-182642.6" - process $proc$libresoc.v:182621$13624 + attribute \src "libresoc.v:187916.3-187937.6" + process $proc$libresoc.v:187916$14102 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$13625 $2\data_r4__msr$next[63:0]$13629 + assign $0\data_r4__msr$next[63:0]$14103 $2\data_r4__msr$next[63:0]$14107 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$13626 $3\data_r4__msr_ok$next[0:0]$13631 - attribute \src "libresoc.v:182622.5-182622.29" + assign $0\data_r4__msr_ok$next[0:0]$14104 $3\data_r4__msr_ok$next[0:0]$14109 + attribute \src "libresoc.v:187917.5-187917.29" switch \initial - attribute \src "libresoc.v:182622.9-182622.17" + attribute \src "libresoc.v:187917.9-187917.17" case 1'1 case end @@ -384551,10 +394767,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$13628 $1\data_r4__msr$next[63:0]$13627 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14106 $1\data_r4__msr$next[63:0]$14105 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$13627 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$13628 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14105 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14106 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -384562,32 +394778,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$13630 $2\data_r4__msr$next[63:0]$13629 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14108 $2\data_r4__msr$next[63:0]$14107 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$13629 $1\data_r4__msr$next[63:0]$13627 - assign $2\data_r4__msr_ok$next[0:0]$13630 $1\data_r4__msr_ok$next[0:0]$13628 + assign $2\data_r4__msr$next[63:0]$14107 $1\data_r4__msr$next[63:0]$14105 + assign $2\data_r4__msr_ok$next[0:0]$14108 $1\data_r4__msr_ok$next[0:0]$14106 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$13631 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14109 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$13631 $2\data_r4__msr_ok$next[0:0]$13630 + assign $3\data_r4__msr_ok$next[0:0]$14109 $2\data_r4__msr_ok$next[0:0]$14108 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$13625 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$13626 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14103 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14104 end - attribute \src "libresoc.v:182643.3-182652.6" - process $proc$libresoc.v:182643$13632 + attribute \src "libresoc.v:187938.3-187947.6" + process $proc$libresoc.v:187938$14110 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$13633 $1\src_r0$next[63:0]$13634 - attribute \src "libresoc.v:182644.5-182644.29" + assign $0\src_r0$next[63:0]$14111 $1\src_r0$next[63:0]$14112 + attribute \src "libresoc.v:187939.5-187939.29" switch \initial - attribute \src "libresoc.v:182644.9-182644.17" + attribute \src "libresoc.v:187939.9-187939.17" case 1'1 case end @@ -384596,21 +394812,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$13634 \src1_i + assign $1\src_r0$next[63:0]$14112 \src1_i case - assign $1\src_r0$next[63:0]$13634 \src_r0 + assign $1\src_r0$next[63:0]$14112 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$13633 + update \src_r0$next $0\src_r0$next[63:0]$14111 end - attribute \src "libresoc.v:182653.3-182662.6" - process $proc$libresoc.v:182653$13635 + attribute \src "libresoc.v:187948.3-187957.6" + process $proc$libresoc.v:187948$14113 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$13636 $1\src_r1$next[63:0]$13637 - attribute \src "libresoc.v:182654.5-182654.29" + assign $0\src_r1$next[63:0]$14114 $1\src_r1$next[63:0]$14115 + attribute \src "libresoc.v:187949.5-187949.29" switch \initial - attribute \src "libresoc.v:182654.9-182654.17" + attribute \src "libresoc.v:187949.9-187949.17" case 1'1 case end @@ -384619,21 +394835,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$13637 \src2_i + assign $1\src_r1$next[63:0]$14115 \src2_i case - assign $1\src_r1$next[63:0]$13637 \src_r1 + assign $1\src_r1$next[63:0]$14115 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$13636 + update \src_r1$next $0\src_r1$next[63:0]$14114 end - attribute \src "libresoc.v:182663.3-182672.6" - process $proc$libresoc.v:182663$13638 + attribute \src "libresoc.v:187958.3-187967.6" + process $proc$libresoc.v:187958$14116 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$13639 $1\src_r2$next[63:0]$13640 - attribute \src "libresoc.v:182664.5-182664.29" + assign $0\src_r2$next[63:0]$14117 $1\src_r2$next[63:0]$14118 + attribute \src "libresoc.v:187959.5-187959.29" switch \initial - attribute \src "libresoc.v:182664.9-182664.17" + attribute \src "libresoc.v:187959.9-187959.17" case 1'1 case end @@ -384642,21 +394858,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$13640 \src3_i + assign $1\src_r2$next[63:0]$14118 \src3_i case - assign $1\src_r2$next[63:0]$13640 \src_r2 + assign $1\src_r2$next[63:0]$14118 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$13639 + update \src_r2$next $0\src_r2$next[63:0]$14117 end - attribute \src "libresoc.v:182673.3-182682.6" - process $proc$libresoc.v:182673$13641 + attribute \src "libresoc.v:187968.3-187977.6" + process $proc$libresoc.v:187968$14119 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$13642 $1\src_r3$next[63:0]$13643 - attribute \src "libresoc.v:182674.5-182674.29" + assign $0\src_r3$next[63:0]$14120 $1\src_r3$next[63:0]$14121 + attribute \src "libresoc.v:187969.5-187969.29" switch \initial - attribute \src "libresoc.v:182674.9-182674.17" + attribute \src "libresoc.v:187969.9-187969.17" case 1'1 case end @@ -384665,21 +394881,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$13643 \src4_i + assign $1\src_r3$next[63:0]$14121 \src4_i case - assign $1\src_r3$next[63:0]$13643 \src_r3 + assign $1\src_r3$next[63:0]$14121 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$13642 + update \src_r3$next $0\src_r3$next[63:0]$14120 end - attribute \src "libresoc.v:182683.3-182691.6" - process $proc$libresoc.v:182683$13644 + attribute \src "libresoc.v:187978.3-187986.6" + process $proc$libresoc.v:187978$14122 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$13645 $1\alui_l_r_alui$next[0:0]$13646 - attribute \src "libresoc.v:182684.5-182684.29" + assign $0\alui_l_r_alui$next[0:0]$14123 $1\alui_l_r_alui$next[0:0]$14124 + attribute \src "libresoc.v:187979.5-187979.29" switch \initial - attribute \src "libresoc.v:182684.9-182684.17" + attribute \src "libresoc.v:187979.9-187979.17" case 1'1 case end @@ -384688,21 +394904,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$13646 1'1 + assign $1\alui_l_r_alui$next[0:0]$14124 1'1 case - assign $1\alui_l_r_alui$next[0:0]$13646 \$89 + assign $1\alui_l_r_alui$next[0:0]$14124 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13645 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14123 end - attribute \src "libresoc.v:182692.3-182700.6" - process $proc$libresoc.v:182692$13647 + attribute \src "libresoc.v:187987.3-187995.6" + process $proc$libresoc.v:187987$14125 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$13648 $1\alu_l_r_alu$next[0:0]$13649 - attribute \src "libresoc.v:182693.5-182693.29" + assign $0\alu_l_r_alu$next[0:0]$14126 $1\alu_l_r_alu$next[0:0]$14127 + attribute \src "libresoc.v:187988.5-187988.29" switch \initial - attribute \src "libresoc.v:182693.9-182693.17" + attribute \src "libresoc.v:187988.9-187988.17" case 1'1 case end @@ -384711,21 +394927,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13649 1'1 + assign $1\alu_l_r_alu$next[0:0]$14127 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13649 \$91 + assign $1\alu_l_r_alu$next[0:0]$14127 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13648 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14126 end - attribute \src "libresoc.v:182701.3-182710.6" - process $proc$libresoc.v:182701$13650 + attribute \src "libresoc.v:187996.3-188005.6" + process $proc$libresoc.v:187996$14128 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:182702.5-182702.29" + attribute \src "libresoc.v:187997.5-187997.29" switch \initial - attribute \src "libresoc.v:182702.9-182702.17" + attribute \src "libresoc.v:187997.9-187997.17" case 1'1 case end @@ -384741,14 +394957,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:182711.3-182720.6" - process $proc$libresoc.v:182711$13651 + attribute \src "libresoc.v:188006.3-188015.6" + process $proc$libresoc.v:188006$14129 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:182712.5-182712.29" + attribute \src "libresoc.v:188007.5-188007.29" switch \initial - attribute \src "libresoc.v:182712.9-182712.17" + attribute \src "libresoc.v:188007.9-188007.17" case 1'1 case end @@ -384764,14 +394980,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:182721.3-182730.6" - process $proc$libresoc.v:182721$13652 + attribute \src "libresoc.v:188016.3-188025.6" + process $proc$libresoc.v:188016$14130 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:182722.5-182722.29" + attribute \src "libresoc.v:188017.5-188017.29" switch \initial - attribute \src "libresoc.v:182722.9-182722.17" + attribute \src "libresoc.v:188017.9-188017.17" case 1'1 case end @@ -384787,14 +395003,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:182731.3-182740.6" - process $proc$libresoc.v:182731$13653 + attribute \src "libresoc.v:188026.3-188035.6" + process $proc$libresoc.v:188026$14131 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:182732.5-182732.29" + attribute \src "libresoc.v:188027.5-188027.29" switch \initial - attribute \src "libresoc.v:182732.9-182732.17" + attribute \src "libresoc.v:188027.9-188027.17" case 1'1 case end @@ -384810,14 +395026,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:182741.3-182750.6" - process $proc$libresoc.v:182741$13654 + attribute \src "libresoc.v:188036.3-188045.6" + process $proc$libresoc.v:188036$14132 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:182742.5-182742.29" + attribute \src "libresoc.v:188037.5-188037.29" switch \initial - attribute \src "libresoc.v:182742.9-182742.17" + attribute \src "libresoc.v:188037.9-188037.17" case 1'1 case end @@ -384833,14 +395049,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:182751.3-182759.6" - process $proc$libresoc.v:182751$13655 + attribute \src "libresoc.v:188046.3-188054.6" + process $proc$libresoc.v:188046$14133 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$13656 $1\prev_wr_go$next[4:0]$13657 - attribute \src "libresoc.v:182752.5-182752.29" + assign $0\prev_wr_go$next[4:0]$14134 $1\prev_wr_go$next[4:0]$14135 + attribute \src "libresoc.v:188047.5-188047.29" switch \initial - attribute \src "libresoc.v:182752.9-182752.17" + attribute \src "libresoc.v:188047.9-188047.17" case 1'1 case end @@ -384849,74 +395065,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$13657 5'00000 - case - assign $1\prev_wr_go$next[4:0]$13657 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$13656 - end - connect \$5 $reduce_and$libresoc.v:182203$13446_Y - connect \$99 $and$libresoc.v:182204$13447_Y - connect \$101 $and$libresoc.v:182205$13448_Y - connect \$103 $and$libresoc.v:182206$13449_Y - connect \$105 $and$libresoc.v:182207$13450_Y - connect \$107 $and$libresoc.v:182208$13451_Y - connect \$109 $and$libresoc.v:182209$13452_Y - connect \$111 $and$libresoc.v:182210$13453_Y - connect \$113 $and$libresoc.v:182211$13454_Y - connect \$115 $and$libresoc.v:182212$13455_Y - connect \$117 $and$libresoc.v:182213$13456_Y - connect \$11 $and$libresoc.v:182214$13457_Y - connect \$119 $and$libresoc.v:182215$13458_Y - connect \$121 $and$libresoc.v:182216$13459_Y - connect \$123 $and$libresoc.v:182217$13460_Y - connect \$13 $not$libresoc.v:182218$13461_Y - connect \$15 $and$libresoc.v:182219$13462_Y - connect \$17 $not$libresoc.v:182220$13463_Y - connect \$19 $and$libresoc.v:182221$13464_Y - connect \$21 $and$libresoc.v:182222$13465_Y - connect \$25 $not$libresoc.v:182223$13466_Y - connect \$27 $and$libresoc.v:182224$13467_Y - connect \$24 $reduce_or$libresoc.v:182225$13468_Y - connect \$23 $not$libresoc.v:182226$13469_Y - connect \$31 $and$libresoc.v:182227$13470_Y - connect \$33 $reduce_or$libresoc.v:182228$13471_Y - connect \$35 $reduce_or$libresoc.v:182229$13472_Y - connect \$37 $or$libresoc.v:182230$13473_Y - connect \$3 $and$libresoc.v:182231$13474_Y - connect \$39 $not$libresoc.v:182232$13475_Y - connect \$41 $and$libresoc.v:182233$13476_Y - connect \$43 $and$libresoc.v:182234$13477_Y - connect \$45 $eq$libresoc.v:182235$13478_Y - connect \$47 $and$libresoc.v:182236$13479_Y - connect \$49 $eq$libresoc.v:182237$13480_Y - connect \$51 $and$libresoc.v:182238$13481_Y - connect \$53 $and$libresoc.v:182239$13482_Y - connect \$55 $and$libresoc.v:182240$13483_Y - connect \$57 $or$libresoc.v:182241$13484_Y - connect \$59 $or$libresoc.v:182242$13485_Y - connect \$61 $or$libresoc.v:182243$13486_Y - connect \$63 $or$libresoc.v:182244$13487_Y - connect \$65 $and$libresoc.v:182245$13488_Y - connect \$67 $and$libresoc.v:182246$13489_Y - connect \$6 $not$libresoc.v:182247$13490_Y - connect \$69 $or$libresoc.v:182248$13491_Y - connect \$71 $and$libresoc.v:182249$13492_Y - connect \$73 $and$libresoc.v:182250$13493_Y - connect \$75 $and$libresoc.v:182251$13494_Y - connect \$77 $and$libresoc.v:182252$13495_Y - connect \$79 $and$libresoc.v:182253$13496_Y - connect \$81 $ternary$libresoc.v:182254$13497_Y - connect \$83 $ternary$libresoc.v:182255$13498_Y - connect \$85 $ternary$libresoc.v:182256$13499_Y - connect \$87 $ternary$libresoc.v:182257$13500_Y - connect \$8 $or$libresoc.v:182258$13501_Y - connect \$89 $and$libresoc.v:182259$13502_Y - connect \$91 $and$libresoc.v:182260$13503_Y - connect \$93 $and$libresoc.v:182261$13504_Y - connect \$95 $and$libresoc.v:182262$13505_Y - connect \$97 $not$libresoc.v:182263$13506_Y + assign $1\prev_wr_go$next[4:0]$14135 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14135 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14134 + end + connect \$5 $reduce_and$libresoc.v:187494$13921_Y + connect \$99 $and$libresoc.v:187495$13922_Y + connect \$101 $and$libresoc.v:187496$13923_Y + connect \$103 $and$libresoc.v:187497$13924_Y + connect \$105 $and$libresoc.v:187498$13925_Y + connect \$107 $and$libresoc.v:187499$13926_Y + connect \$109 $and$libresoc.v:187500$13927_Y + connect \$111 $and$libresoc.v:187501$13928_Y + connect \$113 $and$libresoc.v:187502$13929_Y + connect \$115 $and$libresoc.v:187503$13930_Y + connect \$117 $and$libresoc.v:187504$13931_Y + connect \$11 $and$libresoc.v:187505$13932_Y + connect \$119 $and$libresoc.v:187506$13933_Y + connect \$121 $and$libresoc.v:187507$13934_Y + connect \$123 $and$libresoc.v:187508$13935_Y + connect \$13 $not$libresoc.v:187509$13936_Y + connect \$15 $and$libresoc.v:187510$13937_Y + connect \$17 $not$libresoc.v:187511$13938_Y + connect \$19 $and$libresoc.v:187512$13939_Y + connect \$21 $and$libresoc.v:187513$13940_Y + connect \$25 $not$libresoc.v:187514$13941_Y + connect \$27 $and$libresoc.v:187515$13942_Y + connect \$24 $reduce_or$libresoc.v:187516$13943_Y + connect \$23 $not$libresoc.v:187517$13944_Y + connect \$31 $and$libresoc.v:187518$13945_Y + connect \$33 $reduce_or$libresoc.v:187519$13946_Y + connect \$35 $reduce_or$libresoc.v:187520$13947_Y + connect \$37 $or$libresoc.v:187521$13948_Y + connect \$3 $and$libresoc.v:187522$13949_Y + connect \$39 $not$libresoc.v:187523$13950_Y + connect \$41 $and$libresoc.v:187524$13951_Y + connect \$43 $and$libresoc.v:187525$13952_Y + connect \$45 $eq$libresoc.v:187526$13953_Y + connect \$47 $and$libresoc.v:187527$13954_Y + connect \$49 $eq$libresoc.v:187528$13955_Y + connect \$51 $and$libresoc.v:187529$13956_Y + connect \$53 $and$libresoc.v:187530$13957_Y + connect \$55 $and$libresoc.v:187531$13958_Y + connect \$57 $or$libresoc.v:187532$13959_Y + connect \$59 $or$libresoc.v:187533$13960_Y + connect \$61 $or$libresoc.v:187534$13961_Y + connect \$63 $or$libresoc.v:187535$13962_Y + connect \$65 $and$libresoc.v:187536$13963_Y + connect \$67 $and$libresoc.v:187537$13964_Y + connect \$6 $not$libresoc.v:187538$13965_Y + connect \$69 $or$libresoc.v:187539$13966_Y + connect \$71 $and$libresoc.v:187540$13967_Y + connect \$73 $and$libresoc.v:187541$13968_Y + connect \$75 $and$libresoc.v:187542$13969_Y + connect \$77 $and$libresoc.v:187543$13970_Y + connect \$79 $and$libresoc.v:187544$13971_Y + connect \$81 $ternary$libresoc.v:187545$13972_Y + connect \$83 $ternary$libresoc.v:187546$13973_Y + connect \$85 $ternary$libresoc.v:187547$13974_Y + connect \$87 $ternary$libresoc.v:187548$13975_Y + connect \$8 $or$libresoc.v:187549$13976_Y + connect \$89 $and$libresoc.v:187550$13977_Y + connect \$91 $and$libresoc.v:187551$13978_Y + connect \$93 $and$libresoc.v:187552$13979_Y + connect \$95 $and$libresoc.v:187553$13980_Y + connect \$97 $not$libresoc.v:187554$13981_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -384947,37 +395163,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:182793.1-182851.10" +attribute \src "libresoc.v:188088.1-188146.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:182794.7-182794.20" + attribute \src "libresoc.v:188089.7-188089.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182839.3-182847.6" - wire $0\q_int$next[0:0]$13706 - attribute \src "libresoc.v:182837.3-182838.27" + attribute \src "libresoc.v:188134.3-188142.6" + wire $0\q_int$next[0:0]$14185 + attribute \src "libresoc.v:188132.3-188133.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182839.3-182847.6" - wire $1\q_int$next[0:0]$13707 - attribute \src "libresoc.v:182816.7-182816.19" + attribute \src "libresoc.v:188134.3-188142.6" + wire $1\q_int$next[0:0]$14186 + attribute \src "libresoc.v:188111.7-188111.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182829.17-182829.96" - wire $and$libresoc.v:182829$13696_Y - attribute \src "libresoc.v:182834.17-182834.96" - wire $and$libresoc.v:182834$13701_Y - attribute \src "libresoc.v:182831.18-182831.93" - wire $not$libresoc.v:182831$13698_Y - attribute \src "libresoc.v:182833.17-182833.92" - wire $not$libresoc.v:182833$13700_Y - attribute \src "libresoc.v:182836.17-182836.92" - wire $not$libresoc.v:182836$13703_Y - attribute \src "libresoc.v:182830.18-182830.98" - wire $or$libresoc.v:182830$13697_Y - attribute \src "libresoc.v:182832.18-182832.99" - wire $or$libresoc.v:182832$13699_Y - attribute \src "libresoc.v:182835.17-182835.97" - wire $or$libresoc.v:182835$13702_Y + attribute \src "libresoc.v:188124.17-188124.96" + wire $and$libresoc.v:188124$14175_Y + attribute \src "libresoc.v:188129.17-188129.96" + wire $and$libresoc.v:188129$14180_Y + attribute \src "libresoc.v:188126.18-188126.93" + wire $not$libresoc.v:188126$14177_Y + attribute \src "libresoc.v:188128.17-188128.92" + wire $not$libresoc.v:188128$14179_Y + attribute \src "libresoc.v:188131.17-188131.92" + wire $not$libresoc.v:188131$14182_Y + attribute \src "libresoc.v:188125.18-188125.98" + wire $or$libresoc.v:188125$14176_Y + attribute \src "libresoc.v:188127.18-188127.99" + wire $or$libresoc.v:188127$14178_Y + attribute \src "libresoc.v:188130.17-188130.97" + wire $or$libresoc.v:188130$14181_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -384994,11 +395210,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:182794.7-182794.15" + attribute \src "libresoc.v:188089.7-188089.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -385015,7 +395231,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:182829$13696 + cell $and $and$libresoc.v:188124$14175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385023,10 +395239,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182829$13696_Y + connect \Y $and$libresoc.v:188124$14175_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:182834$13701 + cell $and $and$libresoc.v:188129$14180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385034,34 +395250,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182834$13701_Y + connect \Y $and$libresoc.v:188129$14180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:182831$13698 + cell $not $not$libresoc.v:188126$14177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:182831$13698_Y + connect \Y $not$libresoc.v:188126$14177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:182833$13700 + cell $not $not$libresoc.v:188128$14179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:182833$13700_Y + connect \Y $not$libresoc.v:188128$14179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:182836$13703 + cell $not $not$libresoc.v:188131$14182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:182836$13703_Y + connect \Y $not$libresoc.v:188131$14182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:182830$13697 + cell $or $or$libresoc.v:188125$14176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385069,10 +395285,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:182830$13697_Y + connect \Y $or$libresoc.v:188125$14176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:182832$13699 + cell $or $or$libresoc.v:188127$14178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385080,10 +395296,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:182832$13699_Y + connect \Y $or$libresoc.v:188127$14178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:182835$13702 + cell $or $or$libresoc.v:188130$14181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385091,39 +395307,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:182835$13702_Y + connect \Y $or$libresoc.v:188130$14181_Y end - attribute \src "libresoc.v:182794.7-182794.20" - process $proc$libresoc.v:182794$13708 + attribute \src "libresoc.v:188089.7-188089.20" + process $proc$libresoc.v:188089$14187 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182816.7-182816.19" - process $proc$libresoc.v:182816$13709 + attribute \src "libresoc.v:188111.7-188111.19" + process $proc$libresoc.v:188111$14188 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182837.3-182838.27" - process $proc$libresoc.v:182837$13704 + attribute \src "libresoc.v:188132.3-188133.27" + process $proc$libresoc.v:188132$14183 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182839.3-182847.6" - process $proc$libresoc.v:182839$13705 + attribute \src "libresoc.v:188134.3-188142.6" + process $proc$libresoc.v:188134$14184 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13706 $1\q_int$next[0:0]$13707 - attribute \src "libresoc.v:182840.5-182840.29" + assign $0\q_int$next[0:0]$14185 $1\q_int$next[0:0]$14186 + attribute \src "libresoc.v:188135.5-188135.29" switch \initial - attribute \src "libresoc.v:182840.9-182840.17" + attribute \src "libresoc.v:188135.9-188135.17" case 1'1 case end @@ -385132,56 +395348,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13707 1'0 + assign $1\q_int$next[0:0]$14186 1'0 case - assign $1\q_int$next[0:0]$13707 \$5 + assign $1\q_int$next[0:0]$14186 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13706 + update \q_int$next $0\q_int$next[0:0]$14185 end - connect \$9 $and$libresoc.v:182829$13696_Y - connect \$11 $or$libresoc.v:182830$13697_Y - connect \$13 $not$libresoc.v:182831$13698_Y - connect \$15 $or$libresoc.v:182832$13699_Y - connect \$1 $not$libresoc.v:182833$13700_Y - connect \$3 $and$libresoc.v:182834$13701_Y - connect \$5 $or$libresoc.v:182835$13702_Y - connect \$7 $not$libresoc.v:182836$13703_Y + connect \$9 $and$libresoc.v:188124$14175_Y + connect \$11 $or$libresoc.v:188125$14176_Y + connect \$13 $not$libresoc.v:188126$14177_Y + connect \$15 $or$libresoc.v:188127$14178_Y + connect \$1 $not$libresoc.v:188128$14179_Y + connect \$3 $and$libresoc.v:188129$14180_Y + connect \$5 $or$libresoc.v:188130$14181_Y + connect \$7 $not$libresoc.v:188131$14182_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:182855.1-182913.10" +attribute \src "libresoc.v:188150.1-188208.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:182856.7-182856.20" + attribute \src "libresoc.v:188151.7-188151.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182901.3-182909.6" - wire $0\q_int$next[0:0]$13720 - attribute \src "libresoc.v:182899.3-182900.27" + attribute \src "libresoc.v:188196.3-188204.6" + wire $0\q_int$next[0:0]$14199 + attribute \src "libresoc.v:188194.3-188195.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182901.3-182909.6" - wire $1\q_int$next[0:0]$13721 - attribute \src "libresoc.v:182878.7-182878.19" + attribute \src "libresoc.v:188196.3-188204.6" + wire $1\q_int$next[0:0]$14200 + attribute \src "libresoc.v:188173.7-188173.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182891.17-182891.96" - wire $and$libresoc.v:182891$13710_Y - attribute \src "libresoc.v:182896.17-182896.96" - wire $and$libresoc.v:182896$13715_Y - attribute \src "libresoc.v:182893.18-182893.95" - wire $not$libresoc.v:182893$13712_Y - attribute \src "libresoc.v:182895.17-182895.94" - wire $not$libresoc.v:182895$13714_Y - attribute \src "libresoc.v:182898.17-182898.94" - wire $not$libresoc.v:182898$13717_Y - attribute \src "libresoc.v:182892.18-182892.100" - wire $or$libresoc.v:182892$13711_Y - attribute \src "libresoc.v:182894.18-182894.101" - wire $or$libresoc.v:182894$13713_Y - attribute \src "libresoc.v:182897.17-182897.99" - wire $or$libresoc.v:182897$13716_Y + attribute \src "libresoc.v:188186.17-188186.96" + wire $and$libresoc.v:188186$14189_Y + attribute \src "libresoc.v:188191.17-188191.96" + wire $and$libresoc.v:188191$14194_Y + attribute \src "libresoc.v:188188.18-188188.95" + wire $not$libresoc.v:188188$14191_Y + attribute \src "libresoc.v:188190.17-188190.94" + wire $not$libresoc.v:188190$14193_Y + attribute \src "libresoc.v:188193.17-188193.94" + wire $not$libresoc.v:188193$14196_Y + attribute \src "libresoc.v:188187.18-188187.100" + wire $or$libresoc.v:188187$14190_Y + attribute \src "libresoc.v:188189.18-188189.101" + wire $or$libresoc.v:188189$14192_Y + attribute \src "libresoc.v:188192.17-188192.99" + wire $or$libresoc.v:188192$14195_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -385198,11 +395414,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:182856.7-182856.15" + attribute \src "libresoc.v:188151.7-188151.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -385219,7 +395435,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:182891$13710 + cell $and $and$libresoc.v:188186$14189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385227,10 +395443,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182891$13710_Y + connect \Y $and$libresoc.v:188186$14189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:182896$13715 + cell $and $and$libresoc.v:188191$14194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385238,34 +395454,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182896$13715_Y + connect \Y $and$libresoc.v:188191$14194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:182893$13712 + cell $not $not$libresoc.v:188188$14191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:182893$13712_Y + connect \Y $not$libresoc.v:188188$14191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:182895$13714 + cell $not $not$libresoc.v:188190$14193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:182895$13714_Y + connect \Y $not$libresoc.v:188190$14193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:182898$13717 + cell $not $not$libresoc.v:188193$14196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:182898$13717_Y + connect \Y $not$libresoc.v:188193$14196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:182892$13711 + cell $or $or$libresoc.v:188187$14190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385273,10 +395489,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:182892$13711_Y + connect \Y $or$libresoc.v:188187$14190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:182894$13713 + cell $or $or$libresoc.v:188189$14192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385284,10 +395500,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:182894$13713_Y + connect \Y $or$libresoc.v:188189$14192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:182897$13716 + cell $or $or$libresoc.v:188192$14195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385295,39 +395511,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:182897$13716_Y + connect \Y $or$libresoc.v:188192$14195_Y end - attribute \src "libresoc.v:182856.7-182856.20" - process $proc$libresoc.v:182856$13722 + attribute \src "libresoc.v:188151.7-188151.20" + process $proc$libresoc.v:188151$14201 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182878.7-182878.19" - process $proc$libresoc.v:182878$13723 + attribute \src "libresoc.v:188173.7-188173.19" + process $proc$libresoc.v:188173$14202 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182899.3-182900.27" - process $proc$libresoc.v:182899$13718 + attribute \src "libresoc.v:188194.3-188195.27" + process $proc$libresoc.v:188194$14197 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182901.3-182909.6" - process $proc$libresoc.v:182901$13719 + attribute \src "libresoc.v:188196.3-188204.6" + process $proc$libresoc.v:188196$14198 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13720 $1\q_int$next[0:0]$13721 - attribute \src "libresoc.v:182902.5-182902.29" + assign $0\q_int$next[0:0]$14199 $1\q_int$next[0:0]$14200 + attribute \src "libresoc.v:188197.5-188197.29" switch \initial - attribute \src "libresoc.v:182902.9-182902.17" + attribute \src "libresoc.v:188197.9-188197.17" case 1'1 case end @@ -385336,56 +395552,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13721 1'0 + assign $1\q_int$next[0:0]$14200 1'0 case - assign $1\q_int$next[0:0]$13721 \$5 + assign $1\q_int$next[0:0]$14200 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13720 + update \q_int$next $0\q_int$next[0:0]$14199 end - connect \$9 $and$libresoc.v:182891$13710_Y - connect \$11 $or$libresoc.v:182892$13711_Y - connect \$13 $not$libresoc.v:182893$13712_Y - connect \$15 $or$libresoc.v:182894$13713_Y - connect \$1 $not$libresoc.v:182895$13714_Y - connect \$3 $and$libresoc.v:182896$13715_Y - connect \$5 $or$libresoc.v:182897$13716_Y - connect \$7 $not$libresoc.v:182898$13717_Y + connect \$9 $and$libresoc.v:188186$14189_Y + connect \$11 $or$libresoc.v:188187$14190_Y + connect \$13 $not$libresoc.v:188188$14191_Y + connect \$15 $or$libresoc.v:188189$14192_Y + connect \$1 $not$libresoc.v:188190$14193_Y + connect \$3 $and$libresoc.v:188191$14194_Y + connect \$5 $or$libresoc.v:188192$14195_Y + connect \$7 $not$libresoc.v:188193$14196_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:182917.1-182975.10" +attribute \src "libresoc.v:188212.1-188270.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:182918.7-182918.20" + attribute \src "libresoc.v:188213.7-188213.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182963.3-182971.6" - wire $0\q_int$next[0:0]$13734 - attribute \src "libresoc.v:182961.3-182962.27" + attribute \src "libresoc.v:188258.3-188266.6" + wire $0\q_int$next[0:0]$14213 + attribute \src "libresoc.v:188256.3-188257.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:182963.3-182971.6" - wire $1\q_int$next[0:0]$13735 - attribute \src "libresoc.v:182940.7-182940.19" + attribute \src "libresoc.v:188258.3-188266.6" + wire $1\q_int$next[0:0]$14214 + attribute \src "libresoc.v:188235.7-188235.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:182953.17-182953.96" - wire $and$libresoc.v:182953$13724_Y - attribute \src "libresoc.v:182958.17-182958.96" - wire $and$libresoc.v:182958$13729_Y - attribute \src "libresoc.v:182955.18-182955.93" - wire $not$libresoc.v:182955$13726_Y - attribute \src "libresoc.v:182957.17-182957.92" - wire $not$libresoc.v:182957$13728_Y - attribute \src "libresoc.v:182960.17-182960.92" - wire $not$libresoc.v:182960$13731_Y - attribute \src "libresoc.v:182954.18-182954.98" - wire $or$libresoc.v:182954$13725_Y - attribute \src "libresoc.v:182956.18-182956.99" - wire $or$libresoc.v:182956$13727_Y - attribute \src "libresoc.v:182959.17-182959.97" - wire $or$libresoc.v:182959$13730_Y + attribute \src "libresoc.v:188248.17-188248.96" + wire $and$libresoc.v:188248$14203_Y + attribute \src "libresoc.v:188253.17-188253.96" + wire $and$libresoc.v:188253$14208_Y + attribute \src "libresoc.v:188250.18-188250.93" + wire $not$libresoc.v:188250$14205_Y + attribute \src "libresoc.v:188252.17-188252.92" + wire $not$libresoc.v:188252$14207_Y + attribute \src "libresoc.v:188255.17-188255.92" + wire $not$libresoc.v:188255$14210_Y + attribute \src "libresoc.v:188249.18-188249.98" + wire $or$libresoc.v:188249$14204_Y + attribute \src "libresoc.v:188251.18-188251.99" + wire $or$libresoc.v:188251$14206_Y + attribute \src "libresoc.v:188254.17-188254.97" + wire $or$libresoc.v:188254$14209_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" @@ -385402,11 +395618,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \coresync_rst - attribute \src "libresoc.v:182918.7-182918.15" + attribute \src "libresoc.v:188213.7-188213.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \q_int @@ -385423,7 +395639,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:182953$13724 + cell $and $and$libresoc.v:188248$14203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385431,10 +395647,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:182953$13724_Y + connect \Y $and$libresoc.v:188248$14203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:182958$13729 + cell $and $and$libresoc.v:188253$14208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385442,34 +395658,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:182958$13729_Y + connect \Y $and$libresoc.v:188253$14208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:182955$13726 + cell $not $not$libresoc.v:188250$14205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:182955$13726_Y + connect \Y $not$libresoc.v:188250$14205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:182957$13728 + cell $not $not$libresoc.v:188252$14207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:182957$13728_Y + connect \Y $not$libresoc.v:188252$14207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:182960$13731 + cell $not $not$libresoc.v:188255$14210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:182960$13731_Y + connect \Y $not$libresoc.v:188255$14210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:182954$13725 + cell $or $or$libresoc.v:188249$14204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385477,10 +395693,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:182954$13725_Y + connect \Y $or$libresoc.v:188249$14204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:182956$13727 + cell $or $or$libresoc.v:188251$14206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385488,10 +395704,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:182956$13727_Y + connect \Y $or$libresoc.v:188251$14206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:182959$13730 + cell $or $or$libresoc.v:188254$14209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385499,39 +395715,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:182959$13730_Y + connect \Y $or$libresoc.v:188254$14209_Y end - attribute \src "libresoc.v:182918.7-182918.20" - process $proc$libresoc.v:182918$13736 + attribute \src "libresoc.v:188213.7-188213.20" + process $proc$libresoc.v:188213$14215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182940.7-182940.19" - process $proc$libresoc.v:182940$13737 + attribute \src "libresoc.v:188235.7-188235.19" + process $proc$libresoc.v:188235$14216 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:182961.3-182962.27" - process $proc$libresoc.v:182961$13732 + attribute \src "libresoc.v:188256.3-188257.27" + process $proc$libresoc.v:188256$14211 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:182963.3-182971.6" - process $proc$libresoc.v:182963$13733 + attribute \src "libresoc.v:188258.3-188266.6" + process $proc$libresoc.v:188258$14212 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13734 $1\q_int$next[0:0]$13735 - attribute \src "libresoc.v:182964.5-182964.29" + assign $0\q_int$next[0:0]$14213 $1\q_int$next[0:0]$14214 + attribute \src "libresoc.v:188259.5-188259.29" switch \initial - attribute \src "libresoc.v:182964.9-182964.17" + attribute \src "libresoc.v:188259.9-188259.17" case 1'1 case end @@ -385540,54 +395756,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13735 1'0 + assign $1\q_int$next[0:0]$14214 1'0 case - assign $1\q_int$next[0:0]$13735 \$5 + assign $1\q_int$next[0:0]$14214 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13734 + update \q_int$next $0\q_int$next[0:0]$14213 end - connect \$9 $and$libresoc.v:182953$13724_Y - connect \$11 $or$libresoc.v:182954$13725_Y - connect \$13 $not$libresoc.v:182955$13726_Y - connect \$15 $or$libresoc.v:182956$13727_Y - connect \$1 $not$libresoc.v:182957$13728_Y - connect \$3 $and$libresoc.v:182958$13729_Y - connect \$5 $or$libresoc.v:182959$13730_Y - connect \$7 $not$libresoc.v:182960$13731_Y + connect \$9 $and$libresoc.v:188248$14203_Y + connect \$11 $or$libresoc.v:188249$14204_Y + connect \$13 $not$libresoc.v:188250$14205_Y + connect \$15 $or$libresoc.v:188251$14206_Y + connect \$1 $not$libresoc.v:188252$14207_Y + connect \$3 $and$libresoc.v:188253$14208_Y + connect \$5 $or$libresoc.v:188254$14209_Y + connect \$7 $not$libresoc.v:188255$14210_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:182979.1-183045.10" +attribute \src "libresoc.v:188274.1-188340.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:183024.17-183024.91" - wire $not$libresoc.v:183024$13738_Y - attribute \src "libresoc.v:183026.18-183026.93" - wire $not$libresoc.v:183026$13740_Y - attribute \src "libresoc.v:183028.18-183028.93" - wire $not$libresoc.v:183028$13742_Y - attribute \src "libresoc.v:183029.17-183029.89" - wire width 6 $not$libresoc.v:183029$13743_Y - attribute \src "libresoc.v:183031.18-183031.93" - wire $not$libresoc.v:183031$13745_Y - attribute \src "libresoc.v:183034.17-183034.91" - wire $not$libresoc.v:183034$13748_Y - attribute \src "libresoc.v:183025.18-183025.106" - wire $reduce_or$libresoc.v:183025$13739_Y - attribute \src "libresoc.v:183027.18-183027.106" - wire $reduce_or$libresoc.v:183027$13741_Y - attribute \src "libresoc.v:183030.18-183030.106" - wire $reduce_or$libresoc.v:183030$13744_Y - attribute \src "libresoc.v:183032.18-183032.90" - wire $reduce_or$libresoc.v:183032$13746_Y - attribute \src "libresoc.v:183033.17-183033.103" - wire $reduce_or$libresoc.v:183033$13747_Y - attribute \src "libresoc.v:183035.17-183035.105" - wire $reduce_or$libresoc.v:183035$13749_Y + attribute \src "libresoc.v:188319.17-188319.91" + wire $not$libresoc.v:188319$14217_Y + attribute \src "libresoc.v:188321.18-188321.93" + wire $not$libresoc.v:188321$14219_Y + attribute \src "libresoc.v:188323.18-188323.93" + wire $not$libresoc.v:188323$14221_Y + attribute \src "libresoc.v:188324.17-188324.89" + wire width 6 $not$libresoc.v:188324$14222_Y + attribute \src "libresoc.v:188326.18-188326.93" + wire $not$libresoc.v:188326$14224_Y + attribute \src "libresoc.v:188329.17-188329.91" + wire $not$libresoc.v:188329$14227_Y + attribute \src "libresoc.v:188320.18-188320.106" + wire $reduce_or$libresoc.v:188320$14218_Y + attribute \src "libresoc.v:188322.18-188322.106" + wire $reduce_or$libresoc.v:188322$14220_Y + attribute \src "libresoc.v:188325.18-188325.106" + wire $reduce_or$libresoc.v:188325$14223_Y + attribute \src "libresoc.v:188327.18-188327.90" + wire $reduce_or$libresoc.v:188327$14225_Y + attribute \src "libresoc.v:188328.17-188328.103" + wire $reduce_or$libresoc.v:188328$14226_Y + attribute \src "libresoc.v:188330.17-188330.105" + wire $reduce_or$libresoc.v:188330$14228_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -385633,113 +395849,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183024$13738 + cell $not $not$libresoc.v:188319$14217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183024$13738_Y + connect \Y $not$libresoc.v:188319$14217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183026$13740 + cell $not $not$libresoc.v:188321$14219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:183026$13740_Y + connect \Y $not$libresoc.v:188321$14219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183028$13742 + cell $not $not$libresoc.v:188323$14221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:183028$13742_Y + connect \Y $not$libresoc.v:188323$14221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183029$13743 + cell $not $not$libresoc.v:188324$14222 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:183029$13743_Y + connect \Y $not$libresoc.v:188324$14222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183031$13745 + cell $not $not$libresoc.v:188326$14224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:183031$13745_Y + connect \Y $not$libresoc.v:188326$14224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183034$13748 + cell $not $not$libresoc.v:188329$14227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183034$13748_Y + connect \Y $not$libresoc.v:188329$14227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183025$13739 + cell $reduce_or $reduce_or$libresoc.v:188320$14218 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:183025$13739_Y + connect \Y $reduce_or$libresoc.v:188320$14218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183027$13741 + cell $reduce_or $reduce_or$libresoc.v:188322$14220 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:183027$13741_Y + connect \Y $reduce_or$libresoc.v:188322$14220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183030$13744 + cell $reduce_or $reduce_or$libresoc.v:188325$14223 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:183030$13744_Y + connect \Y $reduce_or$libresoc.v:188325$14223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183032$13746 + cell $reduce_or $reduce_or$libresoc.v:188327$14225 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183032$13746_Y + connect \Y $reduce_or$libresoc.v:188327$14225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183033$13747 + cell $reduce_or $reduce_or$libresoc.v:188328$14226 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183033$13747_Y + connect \Y $reduce_or$libresoc.v:188328$14226_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183035$13749 + cell $reduce_or $reduce_or$libresoc.v:188330$14228 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183035$13749_Y - end - connect \$7 $not$libresoc.v:183024$13738_Y - connect \$12 $reduce_or$libresoc.v:183025$13739_Y - connect \$11 $not$libresoc.v:183026$13740_Y - connect \$16 $reduce_or$libresoc.v:183027$13741_Y - connect \$15 $not$libresoc.v:183028$13742_Y - connect \$1 $not$libresoc.v:183029$13743_Y - connect \$20 $reduce_or$libresoc.v:183030$13744_Y - connect \$19 $not$libresoc.v:183031$13745_Y - connect \$23 $reduce_or$libresoc.v:183032$13746_Y - connect \$4 $reduce_or$libresoc.v:183033$13747_Y - connect \$3 $not$libresoc.v:183034$13748_Y - connect \$8 $reduce_or$libresoc.v:183035$13749_Y + connect \Y $reduce_or$libresoc.v:188330$14228_Y + end + connect \$7 $not$libresoc.v:188319$14217_Y + connect \$12 $reduce_or$libresoc.v:188320$14218_Y + connect \$11 $not$libresoc.v:188321$14219_Y + connect \$16 $reduce_or$libresoc.v:188322$14220_Y + connect \$15 $not$libresoc.v:188323$14221_Y + connect \$1 $not$libresoc.v:188324$14222_Y + connect \$20 $reduce_or$libresoc.v:188325$14223_Y + connect \$19 $not$libresoc.v:188326$14224_Y + connect \$23 $reduce_or$libresoc.v:188327$14225_Y + connect \$4 $reduce_or$libresoc.v:188328$14226_Y + connect \$3 $not$libresoc.v:188329$14227_Y + connect \$8 $reduce_or$libresoc.v:188330$14228_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -385750,15 +395966,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183049.1-183070.10" +attribute \src "libresoc.v:188344.1-188365.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:183064.17-183064.89" - wire $not$libresoc.v:183064$13750_Y - attribute \src "libresoc.v:183065.17-183065.89" - wire $reduce_or$libresoc.v:183065$13751_Y + attribute \src "libresoc.v:188359.17-188359.89" + wire $not$libresoc.v:188359$14229_Y + attribute \src "libresoc.v:188360.17-188360.89" + wire $reduce_or$libresoc.v:188360$14230_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -385774,53 +395990,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183064$13750 + cell $not $not$libresoc.v:188359$14229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:183064$13750_Y + connect \Y $not$libresoc.v:188359$14229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183065$13751 + cell $reduce_or $reduce_or$libresoc.v:188360$14230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183065$13751_Y + connect \Y $reduce_or$libresoc.v:188360$14230_Y end - connect \$1 $not$libresoc.v:183064$13750_Y - connect \$3 $reduce_or$libresoc.v:183065$13751_Y + connect \$1 $not$libresoc.v:188359$14229_Y + connect \$3 $reduce_or$libresoc.v:188360$14230_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:183074.1-183131.10" +attribute \src "libresoc.v:188369.1-188426.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:183113.17-183113.91" - wire $not$libresoc.v:183113$13752_Y - attribute \src "libresoc.v:183115.18-183115.93" - wire $not$libresoc.v:183115$13754_Y - attribute \src "libresoc.v:183117.18-183117.93" - wire $not$libresoc.v:183117$13756_Y - attribute \src "libresoc.v:183118.17-183118.89" - wire width 5 $not$libresoc.v:183118$13757_Y - attribute \src "libresoc.v:183121.17-183121.91" - wire $not$libresoc.v:183121$13760_Y - attribute \src "libresoc.v:183114.18-183114.106" - wire $reduce_or$libresoc.v:183114$13753_Y - attribute \src "libresoc.v:183116.18-183116.106" - wire $reduce_or$libresoc.v:183116$13755_Y - attribute \src "libresoc.v:183119.18-183119.90" - wire $reduce_or$libresoc.v:183119$13758_Y - attribute \src "libresoc.v:183120.17-183120.103" - wire $reduce_or$libresoc.v:183120$13759_Y - attribute \src "libresoc.v:183122.17-183122.105" - wire $reduce_or$libresoc.v:183122$13761_Y + attribute \src "libresoc.v:188408.17-188408.91" + wire $not$libresoc.v:188408$14231_Y + attribute \src "libresoc.v:188410.18-188410.93" + wire $not$libresoc.v:188410$14233_Y + attribute \src "libresoc.v:188412.18-188412.93" + wire $not$libresoc.v:188412$14235_Y + attribute \src "libresoc.v:188413.17-188413.89" + wire width 5 $not$libresoc.v:188413$14236_Y + attribute \src "libresoc.v:188416.17-188416.91" + wire $not$libresoc.v:188416$14239_Y + attribute \src "libresoc.v:188409.18-188409.106" + wire $reduce_or$libresoc.v:188409$14232_Y + attribute \src "libresoc.v:188411.18-188411.106" + wire $reduce_or$libresoc.v:188411$14234_Y + attribute \src "libresoc.v:188414.18-188414.90" + wire $reduce_or$libresoc.v:188414$14237_Y + attribute \src "libresoc.v:188415.17-188415.103" + wire $reduce_or$libresoc.v:188415$14238_Y + attribute \src "libresoc.v:188417.17-188417.105" + wire $reduce_or$libresoc.v:188417$14240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -385860,95 +396076,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183113$13752 + cell $not $not$libresoc.v:188408$14231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183113$13752_Y + connect \Y $not$libresoc.v:188408$14231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183115$13754 + cell $not $not$libresoc.v:188410$14233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:183115$13754_Y + connect \Y $not$libresoc.v:188410$14233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183117$13756 + cell $not $not$libresoc.v:188412$14235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:183117$13756_Y + connect \Y $not$libresoc.v:188412$14235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183118$13757 + cell $not $not$libresoc.v:188413$14236 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:183118$13757_Y + connect \Y $not$libresoc.v:188413$14236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183121$13760 + cell $not $not$libresoc.v:188416$14239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183121$13760_Y + connect \Y $not$libresoc.v:188416$14239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183114$13753 + cell $reduce_or $reduce_or$libresoc.v:188409$14232 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:183114$13753_Y + connect \Y $reduce_or$libresoc.v:188409$14232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183116$13755 + cell $reduce_or $reduce_or$libresoc.v:188411$14234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:183116$13755_Y + connect \Y $reduce_or$libresoc.v:188411$14234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183119$13758 + cell $reduce_or $reduce_or$libresoc.v:188414$14237 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183119$13758_Y + connect \Y $reduce_or$libresoc.v:188414$14237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183120$13759 + cell $reduce_or $reduce_or$libresoc.v:188415$14238 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183120$13759_Y + connect \Y $reduce_or$libresoc.v:188415$14238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183122$13761 + cell $reduce_or $reduce_or$libresoc.v:188417$14240 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183122$13761_Y - end - connect \$7 $not$libresoc.v:183113$13752_Y - connect \$12 $reduce_or$libresoc.v:183114$13753_Y - connect \$11 $not$libresoc.v:183115$13754_Y - connect \$16 $reduce_or$libresoc.v:183116$13755_Y - connect \$15 $not$libresoc.v:183117$13756_Y - connect \$1 $not$libresoc.v:183118$13757_Y - connect \$19 $reduce_or$libresoc.v:183119$13758_Y - connect \$4 $reduce_or$libresoc.v:183120$13759_Y - connect \$3 $not$libresoc.v:183121$13760_Y - connect \$8 $reduce_or$libresoc.v:183122$13761_Y + connect \Y $reduce_or$libresoc.v:188417$14240_Y + end + connect \$7 $not$libresoc.v:188408$14231_Y + connect \$12 $reduce_or$libresoc.v:188409$14232_Y + connect \$11 $not$libresoc.v:188410$14233_Y + connect \$16 $reduce_or$libresoc.v:188411$14234_Y + connect \$15 $not$libresoc.v:188412$14235_Y + connect \$1 $not$libresoc.v:188413$14236_Y + connect \$19 $reduce_or$libresoc.v:188414$14237_Y + connect \$4 $reduce_or$libresoc.v:188415$14238_Y + connect \$3 $not$libresoc.v:188416$14239_Y + connect \$8 $reduce_or$libresoc.v:188417$14240_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -385958,51 +396174,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183135.1-183237.10" +attribute \src "libresoc.v:188430.1-188532.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:183204.17-183204.91" - wire $not$libresoc.v:183204$13762_Y - attribute \src "libresoc.v:183206.18-183206.93" - wire $not$libresoc.v:183206$13764_Y - attribute \src "libresoc.v:183208.18-183208.93" - wire $not$libresoc.v:183208$13766_Y - attribute \src "libresoc.v:183209.17-183209.89" - wire width 10 $not$libresoc.v:183209$13767_Y - attribute \src "libresoc.v:183211.18-183211.93" - wire $not$libresoc.v:183211$13769_Y - attribute \src "libresoc.v:183213.18-183213.93" - wire $not$libresoc.v:183213$13771_Y - attribute \src "libresoc.v:183215.18-183215.93" - wire $not$libresoc.v:183215$13773_Y - attribute \src "libresoc.v:183217.18-183217.93" - wire $not$libresoc.v:183217$13775_Y - attribute \src "libresoc.v:183219.18-183219.93" - wire $not$libresoc.v:183219$13777_Y - attribute \src "libresoc.v:183222.17-183222.91" - wire $not$libresoc.v:183222$13780_Y - attribute \src "libresoc.v:183205.18-183205.106" - wire $reduce_or$libresoc.v:183205$13763_Y - attribute \src "libresoc.v:183207.18-183207.106" - wire $reduce_or$libresoc.v:183207$13765_Y - attribute \src "libresoc.v:183210.18-183210.106" - wire $reduce_or$libresoc.v:183210$13768_Y - attribute \src "libresoc.v:183212.18-183212.106" - wire $reduce_or$libresoc.v:183212$13770_Y - attribute \src "libresoc.v:183214.18-183214.106" - wire $reduce_or$libresoc.v:183214$13772_Y - attribute \src "libresoc.v:183216.18-183216.106" - wire $reduce_or$libresoc.v:183216$13774_Y - attribute \src "libresoc.v:183218.18-183218.106" - wire $reduce_or$libresoc.v:183218$13776_Y - attribute \src "libresoc.v:183220.18-183220.90" - wire $reduce_or$libresoc.v:183220$13778_Y - attribute \src "libresoc.v:183221.17-183221.103" - wire $reduce_or$libresoc.v:183221$13779_Y - attribute \src "libresoc.v:183223.17-183223.105" - wire $reduce_or$libresoc.v:183223$13781_Y + attribute \src "libresoc.v:188499.17-188499.91" + wire $not$libresoc.v:188499$14241_Y + attribute \src "libresoc.v:188501.18-188501.93" + wire $not$libresoc.v:188501$14243_Y + attribute \src "libresoc.v:188503.18-188503.93" + wire $not$libresoc.v:188503$14245_Y + attribute \src "libresoc.v:188504.17-188504.89" + wire width 10 $not$libresoc.v:188504$14246_Y + attribute \src "libresoc.v:188506.18-188506.93" + wire $not$libresoc.v:188506$14248_Y + attribute \src "libresoc.v:188508.18-188508.93" + wire $not$libresoc.v:188508$14250_Y + attribute \src "libresoc.v:188510.18-188510.93" + wire $not$libresoc.v:188510$14252_Y + attribute \src "libresoc.v:188512.18-188512.93" + wire $not$libresoc.v:188512$14254_Y + attribute \src "libresoc.v:188514.18-188514.93" + wire $not$libresoc.v:188514$14256_Y + attribute \src "libresoc.v:188517.17-188517.91" + wire $not$libresoc.v:188517$14259_Y + attribute \src "libresoc.v:188500.18-188500.106" + wire $reduce_or$libresoc.v:188500$14242_Y + attribute \src "libresoc.v:188502.18-188502.106" + wire $reduce_or$libresoc.v:188502$14244_Y + attribute \src "libresoc.v:188505.18-188505.106" + wire $reduce_or$libresoc.v:188505$14247_Y + attribute \src "libresoc.v:188507.18-188507.106" + wire $reduce_or$libresoc.v:188507$14249_Y + attribute \src "libresoc.v:188509.18-188509.106" + wire $reduce_or$libresoc.v:188509$14251_Y + attribute \src "libresoc.v:188511.18-188511.106" + wire $reduce_or$libresoc.v:188511$14253_Y + attribute \src "libresoc.v:188513.18-188513.106" + wire $reduce_or$libresoc.v:188513$14255_Y + attribute \src "libresoc.v:188515.18-188515.90" + wire $reduce_or$libresoc.v:188515$14257_Y + attribute \src "libresoc.v:188516.17-188516.103" + wire $reduce_or$libresoc.v:188516$14258_Y + attribute \src "libresoc.v:188518.17-188518.105" + wire $reduce_or$libresoc.v:188518$14260_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -386072,185 +396288,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183204$13762 + cell $not $not$libresoc.v:188499$14241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183204$13762_Y + connect \Y $not$libresoc.v:188499$14241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183206$13764 + cell $not $not$libresoc.v:188501$14243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:183206$13764_Y + connect \Y $not$libresoc.v:188501$14243_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183208$13766 + cell $not $not$libresoc.v:188503$14245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:183208$13766_Y + connect \Y $not$libresoc.v:188503$14245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183209$13767 + cell $not $not$libresoc.v:188504$14246 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:183209$13767_Y + connect \Y $not$libresoc.v:188504$14246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183211$13769 + cell $not $not$libresoc.v:188506$14248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:183211$13769_Y + connect \Y $not$libresoc.v:188506$14248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183213$13771 + cell $not $not$libresoc.v:188508$14250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:183213$13771_Y + connect \Y $not$libresoc.v:188508$14250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183215$13773 + cell $not $not$libresoc.v:188510$14252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:183215$13773_Y + connect \Y $not$libresoc.v:188510$14252_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183217$13775 + cell $not $not$libresoc.v:188512$14254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:183217$13775_Y + connect \Y $not$libresoc.v:188512$14254_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183219$13777 + cell $not $not$libresoc.v:188514$14256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:183219$13777_Y + connect \Y $not$libresoc.v:188514$14256_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183222$13780 + cell $not $not$libresoc.v:188517$14259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183222$13780_Y + connect \Y $not$libresoc.v:188517$14259_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183205$13763 + cell $reduce_or $reduce_or$libresoc.v:188500$14242 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:183205$13763_Y + connect \Y $reduce_or$libresoc.v:188500$14242_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183207$13765 + cell $reduce_or $reduce_or$libresoc.v:188502$14244 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:183207$13765_Y + connect \Y $reduce_or$libresoc.v:188502$14244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183210$13768 + cell $reduce_or $reduce_or$libresoc.v:188505$14247 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:183210$13768_Y + connect \Y $reduce_or$libresoc.v:188505$14247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183212$13770 + cell $reduce_or $reduce_or$libresoc.v:188507$14249 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:183212$13770_Y + connect \Y $reduce_or$libresoc.v:188507$14249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183214$13772 + cell $reduce_or $reduce_or$libresoc.v:188509$14251 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:183214$13772_Y + connect \Y $reduce_or$libresoc.v:188509$14251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183216$13774 + cell $reduce_or $reduce_or$libresoc.v:188511$14253 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:183216$13774_Y + connect \Y $reduce_or$libresoc.v:188511$14253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183218$13776 + cell $reduce_or $reduce_or$libresoc.v:188513$14255 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:183218$13776_Y + connect \Y $reduce_or$libresoc.v:188513$14255_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183220$13778 + cell $reduce_or $reduce_or$libresoc.v:188515$14257 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183220$13778_Y + connect \Y $reduce_or$libresoc.v:188515$14257_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183221$13779 + cell $reduce_or $reduce_or$libresoc.v:188516$14258 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183221$13779_Y + connect \Y $reduce_or$libresoc.v:188516$14258_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183223$13781 + cell $reduce_or $reduce_or$libresoc.v:188518$14260 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183223$13781_Y - end - connect \$7 $not$libresoc.v:183204$13762_Y - connect \$12 $reduce_or$libresoc.v:183205$13763_Y - connect \$11 $not$libresoc.v:183206$13764_Y - connect \$16 $reduce_or$libresoc.v:183207$13765_Y - connect \$15 $not$libresoc.v:183208$13766_Y - connect \$1 $not$libresoc.v:183209$13767_Y - connect \$20 $reduce_or$libresoc.v:183210$13768_Y - connect \$19 $not$libresoc.v:183211$13769_Y - connect \$24 $reduce_or$libresoc.v:183212$13770_Y - connect \$23 $not$libresoc.v:183213$13771_Y - connect \$28 $reduce_or$libresoc.v:183214$13772_Y - connect \$27 $not$libresoc.v:183215$13773_Y - connect \$32 $reduce_or$libresoc.v:183216$13774_Y - connect \$31 $not$libresoc.v:183217$13775_Y - connect \$36 $reduce_or$libresoc.v:183218$13776_Y - connect \$35 $not$libresoc.v:183219$13777_Y - connect \$39 $reduce_or$libresoc.v:183220$13778_Y - connect \$4 $reduce_or$libresoc.v:183221$13779_Y - connect \$3 $not$libresoc.v:183222$13780_Y - connect \$8 $reduce_or$libresoc.v:183223$13781_Y + connect \Y $reduce_or$libresoc.v:188518$14260_Y + end + connect \$7 $not$libresoc.v:188499$14241_Y + connect \$12 $reduce_or$libresoc.v:188500$14242_Y + connect \$11 $not$libresoc.v:188501$14243_Y + connect \$16 $reduce_or$libresoc.v:188502$14244_Y + connect \$15 $not$libresoc.v:188503$14245_Y + connect \$1 $not$libresoc.v:188504$14246_Y + connect \$20 $reduce_or$libresoc.v:188505$14247_Y + connect \$19 $not$libresoc.v:188506$14248_Y + connect \$24 $reduce_or$libresoc.v:188507$14249_Y + connect \$23 $not$libresoc.v:188508$14250_Y + connect \$28 $reduce_or$libresoc.v:188509$14251_Y + connect \$27 $not$libresoc.v:188510$14252_Y + connect \$32 $reduce_or$libresoc.v:188511$14253_Y + connect \$31 $not$libresoc.v:188512$14254_Y + connect \$36 $reduce_or$libresoc.v:188513$14255_Y + connect \$35 $not$libresoc.v:188514$14256_Y + connect \$39 $reduce_or$libresoc.v:188515$14257_Y + connect \$4 $reduce_or$libresoc.v:188516$14258_Y + connect \$3 $not$libresoc.v:188517$14259_Y + connect \$8 $reduce_or$libresoc.v:188518$14260_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -386265,15 +396481,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183241.1-183262.10" +attribute \src "libresoc.v:188536.1-188557.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:183256.17-183256.89" - wire $not$libresoc.v:183256$13782_Y - attribute \src "libresoc.v:183257.17-183257.89" - wire $reduce_or$libresoc.v:183257$13783_Y + attribute \src "libresoc.v:188551.17-188551.89" + wire $not$libresoc.v:188551$14261_Y + attribute \src "libresoc.v:188552.17-188552.89" + wire $reduce_or$libresoc.v:188552$14262_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -386289,37 +396505,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183256$13782 + cell $not $not$libresoc.v:188551$14261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:183256$13782_Y + connect \Y $not$libresoc.v:188551$14261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183257$13783 + cell $reduce_or $reduce_or$libresoc.v:188552$14262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183257$13783_Y + connect \Y $reduce_or$libresoc.v:188552$14262_Y end - connect \$1 $not$libresoc.v:183256$13782_Y - connect \$3 $reduce_or$libresoc.v:183257$13783_Y + connect \$1 $not$libresoc.v:188551$14261_Y + connect \$3 $reduce_or$libresoc.v:188552$14262_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:183266.1-183287.10" +attribute \src "libresoc.v:188561.1-188582.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:183281.17-183281.89" - wire $not$libresoc.v:183281$13784_Y - attribute \src "libresoc.v:183282.17-183282.89" - wire $reduce_or$libresoc.v:183282$13785_Y + attribute \src "libresoc.v:188576.17-188576.89" + wire $not$libresoc.v:188576$14263_Y + attribute \src "libresoc.v:188577.17-188577.89" + wire $reduce_or$libresoc.v:188577$14264_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -386335,41 +396551,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183281$13784 + cell $not $not$libresoc.v:188576$14263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:183281$13784_Y + connect \Y $not$libresoc.v:188576$14263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183282$13785 + cell $reduce_or $reduce_or$libresoc.v:188577$14264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183282$13785_Y + connect \Y $reduce_or$libresoc.v:188577$14264_Y end - connect \$1 $not$libresoc.v:183281$13784_Y - connect \$3 $reduce_or$libresoc.v:183282$13785_Y + connect \$1 $not$libresoc.v:188576$14263_Y + connect \$3 $reduce_or$libresoc.v:188577$14264_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:183291.1-183321.10" +attribute \src "libresoc.v:188586.1-188616.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:183312.17-183312.89" - wire width 2 $not$libresoc.v:183312$13786_Y - attribute \src "libresoc.v:183314.17-183314.91" - wire $not$libresoc.v:183314$13788_Y - attribute \src "libresoc.v:183313.17-183313.103" - wire $reduce_or$libresoc.v:183313$13787_Y - attribute \src "libresoc.v:183315.17-183315.89" - wire $reduce_or$libresoc.v:183315$13789_Y + attribute \src "libresoc.v:188607.17-188607.89" + wire width 2 $not$libresoc.v:188607$14265_Y + attribute \src "libresoc.v:188609.17-188609.91" + wire $not$libresoc.v:188609$14267_Y + attribute \src "libresoc.v:188608.17-188608.103" + wire $reduce_or$libresoc.v:188608$14266_Y + attribute \src "libresoc.v:188610.17-188610.89" + wire $reduce_or$libresoc.v:188610$14268_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -386391,64 +396607,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183312$13786 + cell $not $not$libresoc.v:188607$14265 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:183312$13786_Y + connect \Y $not$libresoc.v:188607$14265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183314$13788 + cell $not $not$libresoc.v:188609$14267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183314$13788_Y + connect \Y $not$libresoc.v:188609$14267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183313$13787 + cell $reduce_or $reduce_or$libresoc.v:188608$14266 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183313$13787_Y + connect \Y $reduce_or$libresoc.v:188608$14266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183315$13789 + cell $reduce_or $reduce_or$libresoc.v:188610$14268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183315$13789_Y + connect \Y $reduce_or$libresoc.v:188610$14268_Y end - connect \$1 $not$libresoc.v:183312$13786_Y - connect \$4 $reduce_or$libresoc.v:183313$13787_Y - connect \$3 $not$libresoc.v:183314$13788_Y - connect \$7 $reduce_or$libresoc.v:183315$13789_Y + connect \$1 $not$libresoc.v:188607$14265_Y + connect \$4 $reduce_or$libresoc.v:188608$14266_Y + connect \$3 $not$libresoc.v:188609$14267_Y + connect \$7 $reduce_or$libresoc.v:188610$14268_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183325.1-183364.10" +attribute \src "libresoc.v:188620.1-188659.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:183352.17-183352.91" - wire $not$libresoc.v:183352$13790_Y - attribute \src "libresoc.v:183354.17-183354.89" - wire width 3 $not$libresoc.v:183354$13792_Y - attribute \src "libresoc.v:183356.17-183356.91" - wire $not$libresoc.v:183356$13794_Y - attribute \src "libresoc.v:183353.18-183353.90" - wire $reduce_or$libresoc.v:183353$13791_Y - attribute \src "libresoc.v:183355.17-183355.103" - wire $reduce_or$libresoc.v:183355$13793_Y - attribute \src "libresoc.v:183357.17-183357.105" - wire $reduce_or$libresoc.v:183357$13795_Y + attribute \src "libresoc.v:188647.17-188647.91" + wire $not$libresoc.v:188647$14269_Y + attribute \src "libresoc.v:188649.17-188649.89" + wire width 3 $not$libresoc.v:188649$14271_Y + attribute \src "libresoc.v:188651.17-188651.91" + wire $not$libresoc.v:188651$14273_Y + attribute \src "libresoc.v:188648.18-188648.90" + wire $reduce_or$libresoc.v:188648$14270_Y + attribute \src "libresoc.v:188650.17-188650.103" + wire $reduce_or$libresoc.v:188650$14272_Y + attribute \src "libresoc.v:188652.17-188652.105" + wire $reduce_or$libresoc.v:188652$14274_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" @@ -386476,59 +396692,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183352$13790 + cell $not $not$libresoc.v:188647$14269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183352$13790_Y + connect \Y $not$libresoc.v:188647$14269_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183354$13792 + cell $not $not$libresoc.v:188649$14271 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:183354$13792_Y + connect \Y $not$libresoc.v:188649$14271_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183356$13794 + cell $not $not$libresoc.v:188651$14273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183356$13794_Y + connect \Y $not$libresoc.v:188651$14273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183353$13791 + cell $reduce_or $reduce_or$libresoc.v:188648$14270 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183353$13791_Y + connect \Y $reduce_or$libresoc.v:188648$14270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183355$13793 + cell $reduce_or $reduce_or$libresoc.v:188650$14272 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183355$13793_Y + connect \Y $reduce_or$libresoc.v:188650$14272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183357$13795 + cell $reduce_or $reduce_or$libresoc.v:188652$14274 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183357$13795_Y - end - connect \$7 $not$libresoc.v:183352$13790_Y - connect \$11 $reduce_or$libresoc.v:183353$13791_Y - connect \$1 $not$libresoc.v:183354$13792_Y - connect \$4 $reduce_or$libresoc.v:183355$13793_Y - connect \$3 $not$libresoc.v:183356$13794_Y - connect \$8 $reduce_or$libresoc.v:183357$13795_Y + connect \Y $reduce_or$libresoc.v:188652$14274_Y + end + connect \$7 $not$libresoc.v:188647$14269_Y + connect \$11 $reduce_or$libresoc.v:188648$14270_Y + connect \$1 $not$libresoc.v:188649$14271_Y + connect \$4 $reduce_or$libresoc.v:188650$14272_Y + connect \$3 $not$libresoc.v:188651$14273_Y + connect \$8 $reduce_or$libresoc.v:188652$14274_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -386536,27 +396752,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183368.1-183416.10" +attribute \src "libresoc.v:188663.1-188711.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:183401.17-183401.91" - wire $not$libresoc.v:183401$13796_Y - attribute \src "libresoc.v:183403.18-183403.93" - wire $not$libresoc.v:183403$13798_Y - attribute \src "libresoc.v:183405.17-183405.89" - wire width 4 $not$libresoc.v:183405$13800_Y - attribute \src "libresoc.v:183407.17-183407.91" - wire $not$libresoc.v:183407$13802_Y - attribute \src "libresoc.v:183402.18-183402.106" - wire $reduce_or$libresoc.v:183402$13797_Y - attribute \src "libresoc.v:183404.18-183404.90" - wire $reduce_or$libresoc.v:183404$13799_Y - attribute \src "libresoc.v:183406.17-183406.103" - wire $reduce_or$libresoc.v:183406$13801_Y - attribute \src "libresoc.v:183408.17-183408.105" - wire $reduce_or$libresoc.v:183408$13803_Y + attribute \src "libresoc.v:188696.17-188696.91" + wire $not$libresoc.v:188696$14275_Y + attribute \src "libresoc.v:188698.18-188698.93" + wire $not$libresoc.v:188698$14277_Y + attribute \src "libresoc.v:188700.17-188700.89" + wire width 4 $not$libresoc.v:188700$14279_Y + attribute \src "libresoc.v:188702.17-188702.91" + wire $not$libresoc.v:188702$14281_Y + attribute \src "libresoc.v:188697.18-188697.106" + wire $reduce_or$libresoc.v:188697$14276_Y + attribute \src "libresoc.v:188699.18-188699.90" + wire $reduce_or$libresoc.v:188699$14278_Y + attribute \src "libresoc.v:188701.17-188701.103" + wire $reduce_or$libresoc.v:188701$14280_Y + attribute \src "libresoc.v:188703.17-188703.105" + wire $reduce_or$libresoc.v:188703$14282_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -386590,77 +396806,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183401$13796 + cell $not $not$libresoc.v:188696$14275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183401$13796_Y + connect \Y $not$libresoc.v:188696$14275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183403$13798 + cell $not $not$libresoc.v:188698$14277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:183403$13798_Y + connect \Y $not$libresoc.v:188698$14277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183405$13800 + cell $not $not$libresoc.v:188700$14279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:183405$13800_Y + connect \Y $not$libresoc.v:188700$14279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183407$13802 + cell $not $not$libresoc.v:188702$14281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183407$13802_Y + connect \Y $not$libresoc.v:188702$14281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183402$13797 + cell $reduce_or $reduce_or$libresoc.v:188697$14276 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:183402$13797_Y + connect \Y $reduce_or$libresoc.v:188697$14276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183404$13799 + cell $reduce_or $reduce_or$libresoc.v:188699$14278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183404$13799_Y + connect \Y $reduce_or$libresoc.v:188699$14278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183406$13801 + cell $reduce_or $reduce_or$libresoc.v:188701$14280 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183406$13801_Y + connect \Y $reduce_or$libresoc.v:188701$14280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183408$13803 + cell $reduce_or $reduce_or$libresoc.v:188703$14282 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183408$13803_Y - end - connect \$7 $not$libresoc.v:183401$13796_Y - connect \$12 $reduce_or$libresoc.v:183402$13797_Y - connect \$11 $not$libresoc.v:183403$13798_Y - connect \$15 $reduce_or$libresoc.v:183404$13799_Y - connect \$1 $not$libresoc.v:183405$13800_Y - connect \$4 $reduce_or$libresoc.v:183406$13801_Y - connect \$3 $not$libresoc.v:183407$13802_Y - connect \$8 $reduce_or$libresoc.v:183408$13803_Y + connect \Y $reduce_or$libresoc.v:188703$14282_Y + end + connect \$7 $not$libresoc.v:188696$14275_Y + connect \$12 $reduce_or$libresoc.v:188697$14276_Y + connect \$11 $not$libresoc.v:188698$14277_Y + connect \$15 $reduce_or$libresoc.v:188699$14278_Y + connect \$1 $not$libresoc.v:188700$14279_Y + connect \$4 $reduce_or$libresoc.v:188701$14280_Y + connect \$3 $not$libresoc.v:188702$14281_Y + connect \$8 $reduce_or$libresoc.v:188703$14282_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -386669,27 +396885,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183420.1-183468.10" +attribute \src "libresoc.v:188715.1-188763.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:183453.17-183453.91" - wire $not$libresoc.v:183453$13804_Y - attribute \src "libresoc.v:183455.18-183455.93" - wire $not$libresoc.v:183455$13806_Y - attribute \src "libresoc.v:183457.17-183457.89" - wire width 4 $not$libresoc.v:183457$13808_Y - attribute \src "libresoc.v:183459.17-183459.91" - wire $not$libresoc.v:183459$13810_Y - attribute \src "libresoc.v:183454.18-183454.106" - wire $reduce_or$libresoc.v:183454$13805_Y - attribute \src "libresoc.v:183456.18-183456.90" - wire $reduce_or$libresoc.v:183456$13807_Y - attribute \src "libresoc.v:183458.17-183458.103" - wire $reduce_or$libresoc.v:183458$13809_Y - attribute \src "libresoc.v:183460.17-183460.105" - wire $reduce_or$libresoc.v:183460$13811_Y + attribute \src "libresoc.v:188748.17-188748.91" + wire $not$libresoc.v:188748$14283_Y + attribute \src "libresoc.v:188750.18-188750.93" + wire $not$libresoc.v:188750$14285_Y + attribute \src "libresoc.v:188752.17-188752.89" + wire width 4 $not$libresoc.v:188752$14287_Y + attribute \src "libresoc.v:188754.17-188754.91" + wire $not$libresoc.v:188754$14289_Y + attribute \src "libresoc.v:188749.18-188749.106" + wire $reduce_or$libresoc.v:188749$14284_Y + attribute \src "libresoc.v:188751.18-188751.90" + wire $reduce_or$libresoc.v:188751$14286_Y + attribute \src "libresoc.v:188753.17-188753.103" + wire $reduce_or$libresoc.v:188753$14288_Y + attribute \src "libresoc.v:188755.17-188755.105" + wire $reduce_or$libresoc.v:188755$14290_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" @@ -386723,77 +396939,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183453$13804 + cell $not $not$libresoc.v:188748$14283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:183453$13804_Y + connect \Y $not$libresoc.v:188748$14283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183455$13806 + cell $not $not$libresoc.v:188750$14285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:183455$13806_Y + connect \Y $not$libresoc.v:188750$14285_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:183457$13808 + cell $not $not$libresoc.v:188752$14287 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:183457$13808_Y + connect \Y $not$libresoc.v:188752$14287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:183459$13810 + cell $not $not$libresoc.v:188754$14289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:183459$13810_Y + connect \Y $not$libresoc.v:188754$14289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183454$13805 + cell $reduce_or $reduce_or$libresoc.v:188749$14284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:183454$13805_Y + connect \Y $reduce_or$libresoc.v:188749$14284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:183456$13807 + cell $reduce_or $reduce_or$libresoc.v:188751$14286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:183456$13807_Y + connect \Y $reduce_or$libresoc.v:188751$14286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183458$13809 + cell $reduce_or $reduce_or$libresoc.v:188753$14288 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:183458$13809_Y + connect \Y $reduce_or$libresoc.v:188753$14288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:183460$13811 + cell $reduce_or $reduce_or$libresoc.v:188755$14290 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:183460$13811_Y - end - connect \$7 $not$libresoc.v:183453$13804_Y - connect \$12 $reduce_or$libresoc.v:183454$13805_Y - connect \$11 $not$libresoc.v:183455$13806_Y - connect \$15 $reduce_or$libresoc.v:183456$13807_Y - connect \$1 $not$libresoc.v:183457$13808_Y - connect \$4 $reduce_or$libresoc.v:183458$13809_Y - connect \$3 $not$libresoc.v:183459$13810_Y - connect \$8 $reduce_or$libresoc.v:183460$13811_Y + connect \Y $reduce_or$libresoc.v:188755$14290_Y + end + connect \$7 $not$libresoc.v:188748$14283_Y + connect \$12 $reduce_or$libresoc.v:188749$14284_Y + connect \$11 $not$libresoc.v:188750$14285_Y + connect \$15 $reduce_or$libresoc.v:188751$14286_Y + connect \$1 $not$libresoc.v:188752$14287_Y + connect \$4 $reduce_or$libresoc.v:188753$14288_Y + connect \$3 $not$libresoc.v:188754$14289_Y + connect \$8 $reduce_or$libresoc.v:188755$14290_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -386802,67 +397018,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:183472.1-183792.10" +attribute \src "libresoc.v:188767.1-189087.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.core.xer" +attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:183473.7-183473.20" + attribute \src "libresoc.v:188768.7-188768.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183752.3-183760.6" - wire width 3 $0\ren_delay$11$next[2:0]$13835 - attribute \src "libresoc.v:183650.3-183651.43" - wire width 3 $0\ren_delay$11[2:0]$13824 - attribute \src "libresoc.v:183609.13-183609.34" - wire width 3 $0\ren_delay$11[2:0]$13841 - attribute \src "libresoc.v:183714.3-183722.6" - wire width 3 $0\ren_delay$18$next[2:0]$13827 - attribute \src "libresoc.v:183648.3-183649.43" - wire width 3 $0\ren_delay$18[2:0]$13822 - attribute \src "libresoc.v:183613.13-183613.34" - wire width 3 $0\ren_delay$18[2:0]$13843 - attribute \src "libresoc.v:183733.3-183741.6" - wire width 3 $0\ren_delay$next[2:0]$13831 - attribute \src "libresoc.v:183652.3-183653.35" + attribute \src "libresoc.v:189047.3-189055.6" + wire width 3 $0\ren_delay$11$next[2:0]$14314 + attribute \src "libresoc.v:188945.3-188946.43" + wire width 3 $0\ren_delay$11[2:0]$14303 + attribute \src "libresoc.v:188904.13-188904.34" + wire width 3 $0\ren_delay$11[2:0]$14320 + attribute \src "libresoc.v:189009.3-189017.6" + wire width 3 $0\ren_delay$18$next[2:0]$14306 + attribute \src "libresoc.v:188943.3-188944.43" + wire width 3 $0\ren_delay$18[2:0]$14301 + attribute \src "libresoc.v:188908.13-188908.34" + wire width 3 $0\ren_delay$18[2:0]$14322 + attribute \src "libresoc.v:189028.3-189036.6" + wire width 3 $0\ren_delay$next[2:0]$14310 + attribute \src "libresoc.v:188947.3-188948.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:183742.3-183751.6" + attribute \src "libresoc.v:189037.3-189046.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:183761.3-183770.6" + attribute \src "libresoc.v:189056.3-189065.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:183723.3-183732.6" + attribute \src "libresoc.v:189018.3-189027.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:183752.3-183760.6" - wire width 3 $1\ren_delay$11$next[2:0]$13836 - attribute \src "libresoc.v:183714.3-183722.6" - wire width 3 $1\ren_delay$18$next[2:0]$13828 - attribute \src "libresoc.v:183733.3-183741.6" - wire width 3 $1\ren_delay$next[2:0]$13832 - attribute \src "libresoc.v:183607.13-183607.29" + attribute \src "libresoc.v:189047.3-189055.6" + wire width 3 $1\ren_delay$11$next[2:0]$14315 + attribute \src "libresoc.v:189009.3-189017.6" + wire width 3 $1\ren_delay$18$next[2:0]$14307 + attribute \src "libresoc.v:189028.3-189036.6" + wire width 3 $1\ren_delay$next[2:0]$14311 + attribute \src "libresoc.v:188902.13-188902.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:183742.3-183751.6" + attribute \src "libresoc.v:189037.3-189046.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:183761.3-183770.6" + attribute \src "libresoc.v:189056.3-189065.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:183723.3-183732.6" + attribute \src "libresoc.v:189018.3-189027.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:183639.17-183639.109" - wire width 2 $or$libresoc.v:183639$13812_Y - attribute \src "libresoc.v:183641.18-183641.126" - wire width 2 $or$libresoc.v:183641$13814_Y - attribute \src "libresoc.v:183642.18-183642.111" - wire width 2 $or$libresoc.v:183642$13815_Y - attribute \src "libresoc.v:183644.18-183644.126" - wire width 2 $or$libresoc.v:183644$13817_Y - attribute \src "libresoc.v:183645.18-183645.111" - wire width 2 $or$libresoc.v:183645$13818_Y - attribute \src "libresoc.v:183647.17-183647.125" - wire width 2 $or$libresoc.v:183647$13820_Y - attribute \src "libresoc.v:183640.18-183640.100" - wire $reduce_or$libresoc.v:183640$13813_Y - attribute \src "libresoc.v:183643.18-183643.100" - wire $reduce_or$libresoc.v:183643$13816_Y - attribute \src "libresoc.v:183646.17-183646.95" - wire $reduce_or$libresoc.v:183646$13819_Y + attribute \src "libresoc.v:188934.17-188934.109" + wire width 2 $or$libresoc.v:188934$14291_Y + attribute \src "libresoc.v:188936.18-188936.126" + wire width 2 $or$libresoc.v:188936$14293_Y + attribute \src "libresoc.v:188937.18-188937.111" + wire width 2 $or$libresoc.v:188937$14294_Y + attribute \src "libresoc.v:188939.18-188939.126" + wire width 2 $or$libresoc.v:188939$14296_Y + attribute \src "libresoc.v:188940.18-188940.111" + wire width 2 $or$libresoc.v:188940$14297_Y + attribute \src "libresoc.v:188942.17-188942.125" + wire width 2 $or$libresoc.v:188942$14299_Y + attribute \src "libresoc.v:188935.18-188935.100" + wire $reduce_or$libresoc.v:188935$14292_Y + attribute \src "libresoc.v:188938.18-188938.100" + wire $reduce_or$libresoc.v:188938$14295_Y + attribute \src "libresoc.v:188941.17-188941.95" + wire $reduce_or$libresoc.v:188941$14298_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" @@ -386881,25 +397097,25 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:152" - wire input 15 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \data_i + wire width 2 input 10 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \data_i$1 + wire width 2 input 12 \data_i$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \data_i$3 + wire width 2 input 14 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 output 2 \full_rd__data_o + wire width 6 output 3 \full_rd__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \full_rd__ren + wire width 3 input 2 \full_rd__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \full_wr__wen - attribute \src "libresoc.v:183473.7-183473.15" + attribute \src "libresoc.v:188768.7-188768.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \reg_0_dest10__data_i @@ -387010,25 +397226,25 @@ module \xer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src1__data_o + wire width 2 output 4 \src1__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \src1__ren + wire width 3 input 5 \src1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src2__data_o + wire width 2 output 6 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \src2__ren + wire width 3 input 7 \src2__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src3__data_o + wire width 2 output 8 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src3__ren + wire width 3 input 9 \src3__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen + wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \wen$2 + wire width 3 input 13 \wen$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \wen$4 + wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:183639$13812 + cell $or $or$libresoc.v:188934$14291 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387036,10 +397252,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:183639$13812_Y + connect \Y $or$libresoc.v:188934$14291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:183641$13814 + cell $or $or$libresoc.v:188936$14293 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387047,10 +397263,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:183641$13814_Y + connect \Y $or$libresoc.v:188936$14293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:183642$13815 + cell $or $or$libresoc.v:188937$14294 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387058,10 +397274,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:183642$13815_Y + connect \Y $or$libresoc.v:188937$14294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:183644$13817 + cell $or $or$libresoc.v:188939$14296 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387069,10 +397285,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:183644$13817_Y + connect \Y $or$libresoc.v:188939$14296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:183645$13818 + cell $or $or$libresoc.v:188940$14297 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387080,10 +397296,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:183645$13818_Y + connect \Y $or$libresoc.v:188940$14297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:183647$13820 + cell $or $or$libresoc.v:188942$14299 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -387091,35 +397307,35 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:183647$13820_Y + connect \Y $or$libresoc.v:188942$14299_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:183640$13813 + cell $reduce_or $reduce_or$libresoc.v:188935$14292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:183640$13813_Y + connect \Y $reduce_or$libresoc.v:188935$14292_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:183643$13816 + cell $reduce_or $reduce_or$libresoc.v:188938$14295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:183643$13816_Y + connect \Y $reduce_or$libresoc.v:188938$14295_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:183646$13819 + cell $reduce_or $reduce_or$libresoc.v:188941$14298 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:183646$13819_Y + connect \Y $reduce_or$libresoc.v:188941$14298_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:183654.15-183673.4" - cell \reg_0$129 \reg_0 + attribute \src "libresoc.v:188949.15-188968.4" + cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest10__data_i \reg_0_dest10__data_i @@ -387140,8 +397356,8 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:183674.15-183693.4" - cell \reg_1$130 \reg_1 + attribute \src "libresoc.v:188969.15-188988.4" + cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest11__data_i \reg_1_dest11__data_i @@ -387162,8 +397378,8 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:183694.15-183713.4" - cell \reg_2$131 \reg_2 + attribute \src "libresoc.v:188989.15-189008.4" + cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \dest12__data_i \reg_2_dest12__data_i @@ -387183,67 +397399,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:183473.7-183473.20" - process $proc$libresoc.v:183473$13838 + attribute \src "libresoc.v:188768.7-188768.20" + process $proc$libresoc.v:188768$14317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183607.13-183607.29" - process $proc$libresoc.v:183607$13839 + attribute \src "libresoc.v:188902.13-188902.29" + process $proc$libresoc.v:188902$14318 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:183609.13-183609.34" - process $proc$libresoc.v:183609$13840 + attribute \src "libresoc.v:188904.13-188904.34" + process $proc$libresoc.v:188904$14319 assign { } { } - assign $0\ren_delay$11[2:0]$13841 3'000 + assign $0\ren_delay$11[2:0]$14320 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$13841 + update \ren_delay$11 $0\ren_delay$11[2:0]$14320 end - attribute \src "libresoc.v:183613.13-183613.34" - process $proc$libresoc.v:183613$13842 + attribute \src "libresoc.v:188908.13-188908.34" + process $proc$libresoc.v:188908$14321 assign { } { } - assign $0\ren_delay$18[2:0]$13843 3'000 + assign $0\ren_delay$18[2:0]$14322 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$13843 + update \ren_delay$18 $0\ren_delay$18[2:0]$14322 end - attribute \src "libresoc.v:183648.3-183649.43" - process $proc$libresoc.v:183648$13821 + attribute \src "libresoc.v:188943.3-188944.43" + process $proc$libresoc.v:188943$14300 assign { } { } - assign $0\ren_delay$18[2:0]$13822 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14301 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$13822 + update \ren_delay$18 $0\ren_delay$18[2:0]$14301 end - attribute \src "libresoc.v:183650.3-183651.43" - process $proc$libresoc.v:183650$13823 + attribute \src "libresoc.v:188945.3-188946.43" + process $proc$libresoc.v:188945$14302 assign { } { } - assign $0\ren_delay$11[2:0]$13824 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14303 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$13824 + update \ren_delay$11 $0\ren_delay$11[2:0]$14303 end - attribute \src "libresoc.v:183652.3-183653.35" - process $proc$libresoc.v:183652$13825 + attribute \src "libresoc.v:188947.3-188948.35" + process $proc$libresoc.v:188947$14304 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:183714.3-183722.6" - process $proc$libresoc.v:183714$13826 + attribute \src "libresoc.v:189009.3-189017.6" + process $proc$libresoc.v:189009$14305 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$13827 $1\ren_delay$18$next[2:0]$13828 - attribute \src "libresoc.v:183715.5-183715.29" + assign $0\ren_delay$18$next[2:0]$14306 $1\ren_delay$18$next[2:0]$14307 + attribute \src "libresoc.v:189010.5-189010.29" switch \initial - attribute \src "libresoc.v:183715.9-183715.17" + attribute \src "libresoc.v:189010.9-189010.17" case 1'1 case end @@ -387252,21 +397468,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$13828 3'000 + assign $1\ren_delay$18$next[2:0]$14307 3'000 case - assign $1\ren_delay$18$next[2:0]$13828 \src3__ren + assign $1\ren_delay$18$next[2:0]$14307 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$13827 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14306 end - attribute \src "libresoc.v:183723.3-183732.6" - process $proc$libresoc.v:183723$13829 + attribute \src "libresoc.v:189018.3-189027.6" + process $proc$libresoc.v:189018$14308 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:183724.5-183724.29" + attribute \src "libresoc.v:189019.5-189019.29" switch \initial - attribute \src "libresoc.v:183724.9-183724.17" + attribute \src "libresoc.v:189019.9-189019.17" case 1'1 case end @@ -387282,14 +397498,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:183733.3-183741.6" - process $proc$libresoc.v:183733$13830 + attribute \src "libresoc.v:189028.3-189036.6" + process $proc$libresoc.v:189028$14309 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13831 $1\ren_delay$next[2:0]$13832 - attribute \src "libresoc.v:183734.5-183734.29" + assign $0\ren_delay$next[2:0]$14310 $1\ren_delay$next[2:0]$14311 + attribute \src "libresoc.v:189029.5-189029.29" switch \initial - attribute \src "libresoc.v:183734.9-183734.17" + attribute \src "libresoc.v:189029.9-189029.17" case 1'1 case end @@ -387298,21 +397514,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13832 3'000 + assign $1\ren_delay$next[2:0]$14311 3'000 case - assign $1\ren_delay$next[2:0]$13832 \src1__ren + assign $1\ren_delay$next[2:0]$14311 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13831 + update \ren_delay$next $0\ren_delay$next[2:0]$14310 end - attribute \src "libresoc.v:183742.3-183751.6" - process $proc$libresoc.v:183742$13833 + attribute \src "libresoc.v:189037.3-189046.6" + process $proc$libresoc.v:189037$14312 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:183743.5-183743.29" + attribute \src "libresoc.v:189038.5-189038.29" switch \initial - attribute \src "libresoc.v:183743.9-183743.17" + attribute \src "libresoc.v:189038.9-189038.17" case 1'1 case end @@ -387328,14 +397544,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:183752.3-183760.6" - process $proc$libresoc.v:183752$13834 + attribute \src "libresoc.v:189047.3-189055.6" + process $proc$libresoc.v:189047$14313 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$13835 $1\ren_delay$11$next[2:0]$13836 - attribute \src "libresoc.v:183753.5-183753.29" + assign $0\ren_delay$11$next[2:0]$14314 $1\ren_delay$11$next[2:0]$14315 + attribute \src "libresoc.v:189048.5-189048.29" switch \initial - attribute \src "libresoc.v:183753.9-183753.17" + attribute \src "libresoc.v:189048.9-189048.17" case 1'1 case end @@ -387344,21 +397560,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$13836 3'000 + assign $1\ren_delay$11$next[2:0]$14315 3'000 case - assign $1\ren_delay$11$next[2:0]$13836 \src2__ren + assign $1\ren_delay$11$next[2:0]$14315 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$13835 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14314 end - attribute \src "libresoc.v:183761.3-183770.6" - process $proc$libresoc.v:183761$13837 + attribute \src "libresoc.v:189056.3-189065.6" + process $proc$libresoc.v:189056$14316 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:183762.5-183762.29" + attribute \src "libresoc.v:189057.5-189057.29" switch \initial - attribute \src "libresoc.v:183762.9-183762.17" + attribute \src "libresoc.v:189057.9-189057.17" case 1'1 case end @@ -387374,15 +397590,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:183639$13812_Y - connect \$12 $reduce_or$libresoc.v:183640$13813_Y - connect \$14 $or$libresoc.v:183641$13814_Y - connect \$16 $or$libresoc.v:183642$13815_Y - connect \$19 $reduce_or$libresoc.v:183643$13816_Y - connect \$21 $or$libresoc.v:183644$13817_Y - connect \$23 $or$libresoc.v:183645$13818_Y - connect \$5 $reduce_or$libresoc.v:183646$13819_Y - connect \$7 $or$libresoc.v:183647$13820_Y + connect \$9 $or$libresoc.v:188934$14291_Y + connect \$12 $reduce_or$libresoc.v:188935$14292_Y + connect \$14 $or$libresoc.v:188936$14293_Y + connect \$16 $or$libresoc.v:188937$14294_Y + connect \$19 $reduce_or$libresoc.v:188938$14295_Y + connect \$21 $or$libresoc.v:188939$14296_Y + connect \$23 $or$libresoc.v:188940$14297_Y + connect \$5 $reduce_or$libresoc.v:188941$14298_Y + connect \$7 $or$libresoc.v:188942$14299_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -387405,153 +397621,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:183796.1-184110.10" +attribute \src "libresoc.v:189091.1-189405.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.xics_icp" +attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:183974.3-184002.6" + attribute \src "libresoc.v:189269.3-189297.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:184025.3-184033.6" - wire $0\core_irq_o$next[0:0]$13879 - attribute \src "libresoc.v:183916.3-183917.37" + attribute \src "libresoc.v:189320.3-189328.6" + wire $0\core_irq_o$next[0:0]$14358 + attribute \src "libresoc.v:189211.3-189212.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $0\cppr$10[7:0]$13883 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 8 $0\cppr$next[7:0]$13862 - attribute \src "libresoc.v:183920.3-183921.25" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $0\cppr$10[7:0]$14362 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 8 $0\cppr$next[7:0]$14341 + attribute \src "libresoc.v:189215.3-189216.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:184034.3-184043.6" + attribute \src "libresoc.v:189329.3-189338.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:183797.7-183797.20" + attribute \src "libresoc.v:189092.7-189092.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire $0\irq$12[0:0]$13884 - attribute \src "libresoc.v:183930.3-183945.6" - wire $0\irq$next[0:0]$13863 - attribute \src "libresoc.v:183924.3-183925.23" + attribute \src "libresoc.v:189339.3-189401.6" + wire $0\irq$12[0:0]$14363 + attribute \src "libresoc.v:189225.3-189240.6" + wire $0\irq$next[0:0]$14342 + attribute \src "libresoc.v:189219.3-189220.23" wire $0\irq[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $0\mfrr$11[7:0]$13885 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 8 $0\mfrr$next[7:0]$13864 - attribute \src "libresoc.v:183922.3-183923.25" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $0\mfrr$11[7:0]$14364 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 8 $0\mfrr$next[7:0]$14343 + attribute \src "libresoc.v:189217.3-189218.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:184013.3-184024.6" + attribute \src "libresoc.v:189308.3-189319.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:184003.3-184012.6" + attribute \src "libresoc.v:189298.3-189307.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire $0\wb_ack$14[0:0]$13886 - attribute \src "libresoc.v:183930.3-183945.6" - wire $0\wb_ack$next[0:0]$13865 - attribute \src "libresoc.v:183928.3-183929.29" + attribute \src "libresoc.v:189339.3-189401.6" + wire $0\wb_ack$14[0:0]$14365 + attribute \src "libresoc.v:189225.3-189240.6" + wire $0\wb_ack$next[0:0]$14344 + attribute \src "libresoc.v:189223.3-189224.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 32 $0\wb_rd_data$13[31:0]$13887 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 32 $0\wb_rd_data$next[31:0]$13866 - attribute \src "libresoc.v:183926.3-183927.37" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 32 $0\wb_rd_data$13[31:0]$14366 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 32 $0\wb_rd_data$next[31:0]$14345 + attribute \src "libresoc.v:189221.3-189222.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:183946.3-183973.6" + attribute \src "libresoc.v:189241.3-189268.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 24 $0\xisr$9[23:0]$13888 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 24 $0\xisr$next[23:0]$13867 - attribute \src "libresoc.v:183918.3-183919.25" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 24 $0\xisr$9[23:0]$14367 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 24 $0\xisr$next[23:0]$14346 + attribute \src "libresoc.v:189213.3-189214.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:183974.3-184002.6" + attribute \src "libresoc.v:189269.3-189297.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:184025.3-184033.6" - wire $1\core_irq_o$next[0:0]$13880 - attribute \src "libresoc.v:183826.7-183826.24" + attribute \src "libresoc.v:189320.3-189328.6" + wire $1\core_irq_o$next[0:0]$14359 + attribute \src "libresoc.v:189121.7-189121.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $1\cppr$10[7:0]$13889 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 8 $1\cppr$next[7:0]$13868 - attribute \src "libresoc.v:183830.13-183830.25" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $1\cppr$10[7:0]$14368 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 8 $1\cppr$next[7:0]$14347 + attribute \src "libresoc.v:189125.13-189125.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:184034.3-184043.6" + attribute \src "libresoc.v:189329.3-189338.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire $1\irq$12[0:0]$13899 - attribute \src "libresoc.v:183930.3-183945.6" - wire $1\irq$next[0:0]$13869 - attribute \src "libresoc.v:183859.7-183859.17" + attribute \src "libresoc.v:189339.3-189401.6" + wire $1\irq$12[0:0]$14378 + attribute \src "libresoc.v:189225.3-189240.6" + wire $1\irq$next[0:0]$14348 + attribute \src "libresoc.v:189154.7-189154.17" wire $1\irq[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $1\mfrr$11[7:0]$13890 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 8 $1\mfrr$next[7:0]$13870 - attribute \src "libresoc.v:183867.13-183867.25" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $1\mfrr$11[7:0]$14369 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 8 $1\mfrr$next[7:0]$14349 + attribute \src "libresoc.v:189162.13-189162.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:184013.3-184024.6" + attribute \src "libresoc.v:189308.3-189319.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:184003.3-184012.6" + attribute \src "libresoc.v:189298.3-189307.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire $1\wb_ack$14[0:0]$13891 - attribute \src "libresoc.v:183930.3-183945.6" - wire $1\wb_ack$next[0:0]$13871 - attribute \src "libresoc.v:183881.7-183881.20" + attribute \src "libresoc.v:189339.3-189401.6" + wire $1\wb_ack$14[0:0]$14370 + attribute \src "libresoc.v:189225.3-189240.6" + wire $1\wb_ack$next[0:0]$14350 + attribute \src "libresoc.v:189176.7-189176.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:183930.3-183945.6" - wire width 32 $1\wb_rd_data$next[31:0]$13872 - attribute \src "libresoc.v:183889.14-183889.32" + attribute \src "libresoc.v:189225.3-189240.6" + wire width 32 $1\wb_rd_data$next[31:0]$14351 + attribute \src "libresoc.v:189184.14-189184.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:183946.3-183973.6" + attribute \src "libresoc.v:189241.3-189268.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 24 $1\xisr$9[23:0]$13896 - attribute \src "libresoc.v:183930.3-183945.6" - wire width 24 $1\xisr$next[23:0]$13873 - attribute \src "libresoc.v:183899.14-183899.31" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 24 $1\xisr$9[23:0]$14375 + attribute \src "libresoc.v:189225.3-189240.6" + wire width 24 $1\xisr$next[23:0]$14352 + attribute \src "libresoc.v:189194.14-189194.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:183974.3-184002.6" + attribute \src "libresoc.v:189269.3-189297.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $2\cppr$10[7:0]$13892 - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $2\mfrr$11[7:0]$13893 - attribute \src "libresoc.v:183946.3-183973.6" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $2\cppr$10[7:0]$14371 + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $2\mfrr$11[7:0]$14372 + attribute \src "libresoc.v:189241.3-189268.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 24 $2\xisr$9[23:0]$13897 - attribute \src "libresoc.v:183974.3-184002.6" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 24 $2\xisr$9[23:0]$14376 + attribute \src "libresoc.v:189269.3-189297.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $3\cppr$10[7:0]$13894 - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $3\mfrr$11[7:0]$13895 - attribute \src "libresoc.v:183946.3-183973.6" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $3\cppr$10[7:0]$14373 + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $3\mfrr$11[7:0]$14374 + attribute \src "libresoc.v:189241.3-189268.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:184044.3-184106.6" - wire width 8 $4\cppr$10[7:0]$13898 - attribute \src "libresoc.v:183946.3-183973.6" + attribute \src "libresoc.v:189339.3-189401.6" + wire width 8 $4\cppr$10[7:0]$14377 + attribute \src "libresoc.v:189241.3-189268.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:183906.18-183906.116" - wire $and$libresoc.v:183906$13844_Y - attribute \src "libresoc.v:183910.18-183910.116" - wire $and$libresoc.v:183910$13848_Y - attribute \src "libresoc.v:183912.18-183912.116" - wire $and$libresoc.v:183912$13850_Y - attribute \src "libresoc.v:183915.17-183915.109" - wire $and$libresoc.v:183915$13853_Y - attribute \src "libresoc.v:183911.18-183911.110" - wire $eq$libresoc.v:183911$13849_Y - attribute \src "libresoc.v:183908.18-183908.114" - wire $lt$libresoc.v:183908$13846_Y - attribute \src "libresoc.v:183909.18-183909.109" - wire $lt$libresoc.v:183909$13847_Y - attribute \src "libresoc.v:183914.18-183914.114" - wire $lt$libresoc.v:183914$13852_Y - attribute \src "libresoc.v:183907.18-183907.109" - wire $ne$libresoc.v:183907$13845_Y - attribute \src "libresoc.v:183913.18-183913.109" - wire $ne$libresoc.v:183913$13851_Y + attribute \src "libresoc.v:189201.18-189201.116" + wire $and$libresoc.v:189201$14323_Y + attribute \src "libresoc.v:189205.18-189205.116" + wire $and$libresoc.v:189205$14327_Y + attribute \src "libresoc.v:189207.18-189207.116" + wire $and$libresoc.v:189207$14329_Y + attribute \src "libresoc.v:189210.17-189210.109" + wire $and$libresoc.v:189210$14332_Y + attribute \src "libresoc.v:189206.18-189206.110" + wire $eq$libresoc.v:189206$14328_Y + attribute \src "libresoc.v:189203.18-189203.114" + wire $lt$libresoc.v:189203$14325_Y + attribute \src "libresoc.v:189204.18-189204.109" + wire $lt$libresoc.v:189204$14326_Y + attribute \src "libresoc.v:189209.18-189209.114" + wire $lt$libresoc.v:189209$14331_Y + attribute \src "libresoc.v:189202.18-189202.109" + wire $ne$libresoc.v:189202$14324_Y + attribute \src "libresoc.v:189208.18-189208.109" + wire $ne$libresoc.v:189208$14330_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -387576,10 +397792,10 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 3 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire output 2 \core_irq_o + wire output 4 \core_irq_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \core_irq_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" @@ -387607,10 +397823,10 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" wire input 10 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 input 1 \ics_i_pri + wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 input 13 \ics_i_src - attribute \src "libresoc.v:183797.7-183797.15" + wire width 4 input 2 \ics_i_src + attribute \src "libresoc.v:189092.7-189092.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -387632,8 +397848,8 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 4 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" @@ -387661,7 +397877,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:183906$13844 + cell $and $and$libresoc.v:189201$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387669,10 +397885,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:183906$13844_Y + connect \Y $and$libresoc.v:189201$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:183910$13848 + cell $and $and$libresoc.v:189205$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387680,10 +397896,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:183910$13848_Y + connect \Y $and$libresoc.v:189205$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:183912$13850 + cell $and $and$libresoc.v:189207$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387691,10 +397907,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:183912$13850_Y + connect \Y $and$libresoc.v:189207$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:183915$13853 + cell $and $and$libresoc.v:189210$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387702,10 +397918,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:183915$13853_Y + connect \Y $and$libresoc.v:189210$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:183911$13849 + cell $eq $eq$libresoc.v:189206$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -387713,10 +397929,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:183911$13849_Y + connect \Y $eq$libresoc.v:189206$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:183908$13846 + cell $lt $lt$libresoc.v:189203$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387724,10 +397940,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:183908$13846_Y + connect \Y $lt$libresoc.v:189203$14325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:183909$13847 + cell $lt $lt$libresoc.v:189204$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387735,10 +397951,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:183909$13847_Y + connect \Y $lt$libresoc.v:189204$14326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:183914$13852 + cell $lt $lt$libresoc.v:189209$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387746,10 +397962,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:183914$13852_Y + connect \Y $lt$libresoc.v:189209$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:183907$13845 + cell $ne $ne$libresoc.v:189202$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387757,10 +397973,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:183907$13845_Y + connect \Y $ne$libresoc.v:189202$14324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:183913$13851 + cell $ne $ne$libresoc.v:189208$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -387768,123 +397984,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:183913$13851_Y + connect \Y $ne$libresoc.v:189208$14330_Y end - attribute \src "libresoc.v:183797.7-183797.20" - process $proc$libresoc.v:183797$13900 + attribute \src "libresoc.v:189092.7-189092.20" + process $proc$libresoc.v:189092$14379 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183826.7-183826.24" - process $proc$libresoc.v:183826$13901 + attribute \src "libresoc.v:189121.7-189121.24" + process $proc$libresoc.v:189121$14380 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:183830.13-183830.25" - process $proc$libresoc.v:183830$13902 + attribute \src "libresoc.v:189125.13-189125.25" + process $proc$libresoc.v:189125$14381 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:183859.7-183859.17" - process $proc$libresoc.v:183859$13903 + attribute \src "libresoc.v:189154.7-189154.17" + process $proc$libresoc.v:189154$14382 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:183867.13-183867.25" - process $proc$libresoc.v:183867$13904 + attribute \src "libresoc.v:189162.13-189162.25" + process $proc$libresoc.v:189162$14383 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:183881.7-183881.20" - process $proc$libresoc.v:183881$13905 + attribute \src "libresoc.v:189176.7-189176.20" + process $proc$libresoc.v:189176$14384 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:183889.14-183889.32" - process $proc$libresoc.v:183889$13906 + attribute \src "libresoc.v:189184.14-189184.32" + process $proc$libresoc.v:189184$14385 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:183899.14-183899.31" - process $proc$libresoc.v:183899$13907 + attribute \src "libresoc.v:189194.14-189194.31" + process $proc$libresoc.v:189194$14386 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:183916.3-183917.37" - process $proc$libresoc.v:183916$13854 + attribute \src "libresoc.v:189211.3-189212.37" + process $proc$libresoc.v:189211$14333 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:183918.3-183919.25" - process $proc$libresoc.v:183918$13855 + attribute \src "libresoc.v:189213.3-189214.25" + process $proc$libresoc.v:189213$14334 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:183920.3-183921.25" - process $proc$libresoc.v:183920$13856 + attribute \src "libresoc.v:189215.3-189216.25" + process $proc$libresoc.v:189215$14335 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:183922.3-183923.25" - process $proc$libresoc.v:183922$13857 + attribute \src "libresoc.v:189217.3-189218.25" + process $proc$libresoc.v:189217$14336 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:183924.3-183925.23" - process $proc$libresoc.v:183924$13858 + attribute \src "libresoc.v:189219.3-189220.23" + process $proc$libresoc.v:189219$14337 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:183926.3-183927.37" - process $proc$libresoc.v:183926$13859 + attribute \src "libresoc.v:189221.3-189222.37" + process $proc$libresoc.v:189221$14338 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:183928.3-183929.29" - process $proc$libresoc.v:183928$13860 + attribute \src "libresoc.v:189223.3-189224.29" + process $proc$libresoc.v:189223$14339 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:183930.3-183945.6" - process $proc$libresoc.v:183930$13861 + attribute \src "libresoc.v:189225.3-189240.6" + process $proc$libresoc.v:189225$14340 assign { } { } assign { } { } assign { } { } @@ -387892,15 +398108,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$13862 $1\cppr$next[7:0]$13868 - assign $0\irq$next[0:0]$13863 $1\irq$next[0:0]$13869 - assign $0\mfrr$next[7:0]$13864 $1\mfrr$next[7:0]$13870 - assign $0\wb_ack$next[0:0]$13865 $1\wb_ack$next[0:0]$13871 - assign $0\wb_rd_data$next[31:0]$13866 $1\wb_rd_data$next[31:0]$13872 - assign $0\xisr$next[23:0]$13867 $1\xisr$next[23:0]$13873 - attribute \src "libresoc.v:183931.5-183931.29" + assign $0\cppr$next[7:0]$14341 $1\cppr$next[7:0]$14347 + assign $0\irq$next[0:0]$14342 $1\irq$next[0:0]$14348 + assign $0\mfrr$next[7:0]$14343 $1\mfrr$next[7:0]$14349 + assign $0\wb_ack$next[0:0]$14344 $1\wb_ack$next[0:0]$14350 + assign $0\wb_rd_data$next[31:0]$14345 $1\wb_rd_data$next[31:0]$14351 + assign $0\xisr$next[23:0]$14346 $1\xisr$next[23:0]$14352 + attribute \src "libresoc.v:189226.5-189226.29" switch \initial - attribute \src "libresoc.v:183931.9-183931.17" + attribute \src "libresoc.v:189226.9-189226.17" case 1'1 case end @@ -387914,36 +398130,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$13873 24'000000000000000000000000 - assign $1\cppr$next[7:0]$13868 8'00000000 - assign $1\mfrr$next[7:0]$13870 8'11111111 - assign $1\irq$next[0:0]$13869 1'0 - assign $1\wb_rd_data$next[31:0]$13872 0 - assign $1\wb_ack$next[0:0]$13871 1'0 + assign $1\xisr$next[23:0]$14352 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14347 8'00000000 + assign $1\mfrr$next[7:0]$14349 8'11111111 + assign $1\irq$next[0:0]$14348 1'0 + assign $1\wb_rd_data$next[31:0]$14351 0 + assign $1\wb_ack$next[0:0]$14350 1'0 case - assign $1\cppr$next[7:0]$13868 \cppr$2 - assign $1\irq$next[0:0]$13869 \irq$4 - assign $1\mfrr$next[7:0]$13870 \mfrr$3 - assign $1\wb_ack$next[0:0]$13871 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$13872 \wb_rd_data$5 - assign $1\xisr$next[23:0]$13873 \xisr$1 + assign $1\cppr$next[7:0]$14347 \cppr$2 + assign $1\irq$next[0:0]$14348 \irq$4 + assign $1\mfrr$next[7:0]$14349 \mfrr$3 + assign $1\wb_ack$next[0:0]$14350 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14351 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14352 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$13862 - update \irq$next $0\irq$next[0:0]$13863 - update \mfrr$next $0\mfrr$next[7:0]$13864 - update \wb_ack$next $0\wb_ack$next[0:0]$13865 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$13866 - update \xisr$next $0\xisr$next[23:0]$13867 + update \cppr$next $0\cppr$next[7:0]$14341 + update \irq$next $0\irq$next[0:0]$14342 + update \mfrr$next $0\mfrr$next[7:0]$14343 + update \wb_ack$next $0\wb_ack$next[0:0]$14344 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14345 + update \xisr$next $0\xisr$next[23:0]$14346 end - attribute \src "libresoc.v:183946.3-183973.6" - process $proc$libresoc.v:183946$13874 + attribute \src "libresoc.v:189241.3-189268.6" + process $proc$libresoc.v:189241$14353 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:183947.5-183947.29" + attribute \src "libresoc.v:189242.5-189242.29" switch \initial - attribute \src "libresoc.v:183947.9-183947.17" + attribute \src "libresoc.v:189242.9-189242.17" case 1'1 case end @@ -387987,14 +398203,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:183974.3-184002.6" - process $proc$libresoc.v:183974$13875 + attribute \src "libresoc.v:189269.3-189297.6" + process $proc$libresoc.v:189269$14354 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:183975.5-183975.29" + attribute \src "libresoc.v:189270.5-189270.29" switch \initial - attribute \src "libresoc.v:183975.9-183975.17" + attribute \src "libresoc.v:189270.9-189270.17" case 1'1 case end @@ -388037,14 +398253,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:184003.3-184012.6" - process $proc$libresoc.v:184003$13876 + attribute \src "libresoc.v:189298.3-189307.6" + process $proc$libresoc.v:189298$14355 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:184004.5-184004.29" + attribute \src "libresoc.v:189299.5-189299.29" switch \initial - attribute \src "libresoc.v:184004.9-184004.17" + attribute \src "libresoc.v:189299.9-189299.17" case 1'1 case end @@ -388060,13 +398276,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:184013.3-184024.6" - process $proc$libresoc.v:184013$13877 + attribute \src "libresoc.v:189308.3-189319.6" + process $proc$libresoc.v:189308$14356 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:184014.5-184014.29" + attribute \src "libresoc.v:189309.5-189309.29" switch \initial - attribute \src "libresoc.v:184014.9-184014.17" + attribute \src "libresoc.v:189309.9-189309.17" case 1'1 case end @@ -388084,14 +398300,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:184025.3-184033.6" - process $proc$libresoc.v:184025$13878 + attribute \src "libresoc.v:189320.3-189328.6" + process $proc$libresoc.v:189320$14357 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$13879 $1\core_irq_o$next[0:0]$13880 - attribute \src "libresoc.v:184026.5-184026.29" + assign $0\core_irq_o$next[0:0]$14358 $1\core_irq_o$next[0:0]$14359 + attribute \src "libresoc.v:189321.5-189321.29" switch \initial - attribute \src "libresoc.v:184026.9-184026.17" + attribute \src "libresoc.v:189321.9-189321.17" case 1'1 case end @@ -388100,21 +398316,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$13880 1'0 + assign $1\core_irq_o$next[0:0]$14359 1'0 case - assign $1\core_irq_o$next[0:0]$13880 \irq + assign $1\core_irq_o$next[0:0]$14359 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$13879 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14358 end - attribute \src "libresoc.v:184034.3-184043.6" - process $proc$libresoc.v:184034$13881 + attribute \src "libresoc.v:189329.3-189338.6" + process $proc$libresoc.v:189329$14360 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:184035.5-184035.29" + attribute \src "libresoc.v:189330.5-189330.29" switch \initial - attribute \src "libresoc.v:184035.9-184035.17" + attribute \src "libresoc.v:189330.9-189330.17" case 1'1 case end @@ -388130,8 +398346,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:184044.3-184106.6" - process $proc$libresoc.v:184044$13882 + attribute \src "libresoc.v:189339.3-189401.6" + process $proc$libresoc.v:189339$14361 assign { } { } assign { } { } assign { } { } @@ -388141,18 +398357,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$13885 $1\mfrr$11[7:0]$13890 - assign $0\wb_ack$14[0:0]$13886 $1\wb_ack$14[0:0]$13891 + assign $0\mfrr$11[7:0]$14364 $1\mfrr$11[7:0]$14369 + assign $0\wb_ack$14[0:0]$14365 $1\wb_ack$14[0:0]$14370 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$13888 $2\xisr$9[23:0]$13897 - assign $0\cppr$10[7:0]$13883 $4\cppr$10[7:0]$13898 - assign $0\wb_rd_data$13[31:0]$13887 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$13884 $1\irq$12[0:0]$13899 - attribute \src "libresoc.v:184045.5-184045.29" + assign $0\xisr$9[23:0]$14367 $2\xisr$9[23:0]$14376 + assign $0\cppr$10[7:0]$14362 $4\cppr$10[7:0]$14377 + assign $0\wb_rd_data$13[31:0]$14366 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14363 $1\irq$12[0:0]$14378 + attribute \src "libresoc.v:189340.5-189340.29" switch \initial - attribute \src "libresoc.v:184045.9-184045.17" + attribute \src "libresoc.v:189340.9-189340.17" case 1'1 case end @@ -388163,712 +398379,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$13891 1'1 - assign $1\cppr$10[7:0]$13889 $2\cppr$10[7:0]$13892 - assign $1\mfrr$11[7:0]$13890 $2\mfrr$11[7:0]$13893 + assign $1\wb_ack$14[0:0]$14370 1'1 + assign $1\cppr$10[7:0]$14368 $2\cppr$10[7:0]$14371 + assign $1\mfrr$11[7:0]$14369 $2\mfrr$11[7:0]$14372 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$13892 $3\cppr$10[7:0]$13894 - assign $2\mfrr$11[7:0]$13893 $3\mfrr$11[7:0]$13895 + assign $2\cppr$10[7:0]$14371 $3\cppr$10[7:0]$14373 + assign $2\mfrr$11[7:0]$14372 $3\mfrr$11[7:0]$14374 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$13895 \mfrr - assign $3\cppr$10[7:0]$13894 \be_in [31:24] + assign $3\mfrr$11[7:0]$14374 \mfrr + assign $3\cppr$10[7:0]$14373 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$13895 \mfrr - assign $3\cppr$10[7:0]$13894 \be_in [31:24] + assign $3\mfrr$11[7:0]$14374 \mfrr + assign $3\cppr$10[7:0]$14373 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$13894 \cppr + assign $3\cppr$10[7:0]$14373 \cppr assign { } { } - assign $3\mfrr$11[7:0]$13895 \be_in [31:24] + assign $3\mfrr$11[7:0]$14374 \be_in [31:24] case - assign $3\cppr$10[7:0]$13894 \cppr - assign $3\mfrr$11[7:0]$13895 \mfrr + assign $3\cppr$10[7:0]$14373 \cppr + assign $3\mfrr$11[7:0]$14374 \mfrr end case - assign $2\cppr$10[7:0]$13892 \cppr - assign $2\mfrr$11[7:0]$13893 \mfrr + assign $2\cppr$10[7:0]$14371 \cppr + assign $2\mfrr$11[7:0]$14372 \mfrr end case - assign $1\cppr$10[7:0]$13889 \cppr - assign $1\mfrr$11[7:0]$13890 \mfrr - assign $1\wb_ack$14[0:0]$13891 1'0 + assign $1\cppr$10[7:0]$14368 \cppr + assign $1\mfrr$11[7:0]$14369 \mfrr + assign $1\wb_ack$14[0:0]$14370 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$13896 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14375 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$13896 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14375 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$13897 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14376 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$13897 $1\xisr$9[23:0]$13896 + assign $2\xisr$9[23:0]$14376 $1\xisr$9[23:0]$14375 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$13898 \min_pri + assign $4\cppr$10[7:0]$14377 \min_pri case - assign $4\cppr$10[7:0]$13898 $1\cppr$10[7:0]$13889 + assign $4\cppr$10[7:0]$14377 $1\cppr$10[7:0]$14368 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$13899 1'1 + assign $1\irq$12[0:0]$14378 1'1 case - assign $1\irq$12[0:0]$13899 1'0 + assign $1\irq$12[0:0]$14378 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$13883 - update \irq$12 $0\irq$12[0:0]$13884 - update \mfrr$11 $0\mfrr$11[7:0]$13885 - update \wb_ack$14 $0\wb_ack$14[0:0]$13886 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$13887 - update \xisr$9 $0\xisr$9[23:0]$13888 + update \cppr$10 $0\cppr$10[7:0]$14362 + update \irq$12 $0\irq$12[0:0]$14363 + update \mfrr$11 $0\mfrr$11[7:0]$14364 + update \wb_ack$14 $0\wb_ack$14[0:0]$14365 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14366 + update \xisr$9 $0\xisr$9[23:0]$14367 end - connect \$15 $and$libresoc.v:183906$13844_Y - connect \$17 $ne$libresoc.v:183907$13845_Y - connect \$19 $lt$libresoc.v:183908$13846_Y - connect \$21 $lt$libresoc.v:183909$13847_Y - connect \$23 $and$libresoc.v:183910$13848_Y - connect \$25 $eq$libresoc.v:183911$13849_Y - connect \$27 $and$libresoc.v:183912$13850_Y - connect \$29 $ne$libresoc.v:183913$13851_Y - connect \$31 $lt$libresoc.v:183914$13852_Y - connect \$7 $and$libresoc.v:183915$13853_Y + connect \$15 $and$libresoc.v:189201$14323_Y + connect \$17 $ne$libresoc.v:189202$14324_Y + connect \$19 $lt$libresoc.v:189203$14325_Y + connect \$21 $lt$libresoc.v:189204$14326_Y + connect \$23 $and$libresoc.v:189205$14327_Y + connect \$25 $eq$libresoc.v:189206$14328_Y + connect \$27 $and$libresoc.v:189207$14329_Y + connect \$29 $ne$libresoc.v:189208$14330_Y + connect \$31 $lt$libresoc.v:189209$14331_Y + connect \$7 $and$libresoc.v:189210$14332_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:184114.1-185163.10" +attribute \src "libresoc.v:189409.1-190458.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.xics_ics" +attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:185044.3-185093.6" + attribute \src "libresoc.v:190339.3-190388.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:184755.3-184764.6" + attribute \src "libresoc.v:190050.3-190059.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:184964.3-184973.6" + attribute \src "libresoc.v:190259.3-190268.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:184984.3-184993.6" + attribute \src "libresoc.v:190279.3-190288.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:185004.3-185013.6" + attribute \src "libresoc.v:190299.3-190308.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:185024.3-185033.6" + attribute \src "libresoc.v:190319.3-190328.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:185094.3-185103.6" + attribute \src "libresoc.v:190389.3-190398.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:185114.3-185123.6" + attribute \src "libresoc.v:190409.3-190418.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:184775.3-184784.6" + attribute \src "libresoc.v:190070.3-190079.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:184795.3-184804.6" + attribute \src "libresoc.v:190090.3-190099.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:184815.3-184824.6" + attribute \src "libresoc.v:190110.3-190119.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:184844.3-184853.6" + attribute \src "libresoc.v:190139.3-190148.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:184864.3-184873.6" + attribute \src "libresoc.v:190159.3-190168.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:184884.3-184893.6" + attribute \src "libresoc.v:190179.3-190188.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:184904.3-184913.6" + attribute \src "libresoc.v:190199.3-190208.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:184924.3-184933.6" + attribute \src "libresoc.v:190219.3-190228.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:184944.3-184953.6" + attribute \src "libresoc.v:190239.3-190248.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:184745.3-184754.6" + attribute \src "libresoc.v:190040.3-190049.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:184954.3-184963.6" + attribute \src "libresoc.v:190249.3-190258.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:184974.3-184983.6" + attribute \src "libresoc.v:190269.3-190278.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:184994.3-185003.6" + attribute \src "libresoc.v:190289.3-190298.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:185014.3-185023.6" + attribute \src "libresoc.v:190309.3-190318.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:185034.3-185043.6" + attribute \src "libresoc.v:190329.3-190338.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:185104.3-185113.6" + attribute \src "libresoc.v:190399.3-190408.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:184765.3-184774.6" + attribute \src "libresoc.v:190060.3-190069.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:184785.3-184794.6" + attribute \src "libresoc.v:190080.3-190089.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:184805.3-184814.6" + attribute \src "libresoc.v:190100.3-190109.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:184825.3-184834.6" + attribute \src "libresoc.v:190120.3-190129.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:184854.3-184863.6" + attribute \src "libresoc.v:190149.3-190158.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:184874.3-184883.6" + attribute \src "libresoc.v:190169.3-190178.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:184894.3-184903.6" + attribute \src "libresoc.v:190189.3-190198.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:184914.3-184923.6" + attribute \src "libresoc.v:190209.3-190218.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:184934.3-184943.6" + attribute \src "libresoc.v:190229.3-190238.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:185124.3-185133.6" + attribute \src "libresoc.v:190419.3-190428.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:184619.3-184620.25" + attribute \src "libresoc.v:189940.3-189941.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:184617.3-184618.28" + attribute \src "libresoc.v:189938.3-189939.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:185143.3-185151.6" - wire $0\ics_wb__ack$next[0:0]$14154 - attribute \src "libresoc.v:184653.3-184654.39" + attribute \src "libresoc.v:190438.3-190446.6" + wire $0\ics_wb__ack$next[0:0]$14633 + attribute \src "libresoc.v:189932.3-189933.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:185134.3-185142.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14151 - attribute \src "libresoc.v:184655.3-184656.43" + attribute \src "libresoc.v:190429.3-190437.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$14630 + attribute \src "libresoc.v:189934.3-189935.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:184115.7-184115.20" + attribute \src "libresoc.v:189410.7-189410.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184835.3-184843.6" - wire width 16 $0\int_level_l$next[15:0]$14123 - attribute \src "libresoc.v:184657.3-184658.39" + attribute \src "libresoc.v:190130.3-190138.6" + wire width 16 $0\int_level_l$next[15:0]$14602 + attribute \src "libresoc.v:189936.3-189937.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive0_pri$next[7:0]$14033 - attribute \src "libresoc.v:184621.3-184622.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive0_pri$next[7:0]$14512 + attribute \src "libresoc.v:189942.3-189943.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive10_pri$next[7:0]$14034 - attribute \src "libresoc.v:184641.3-184642.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive10_pri$next[7:0]$14513 + attribute \src "libresoc.v:189920.3-189921.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive11_pri$next[7:0]$14035 - attribute \src "libresoc.v:184643.3-184644.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive11_pri$next[7:0]$14514 + attribute \src "libresoc.v:189922.3-189923.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive12_pri$next[7:0]$14036 - attribute \src "libresoc.v:184645.3-184646.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive12_pri$next[7:0]$14515 + attribute \src "libresoc.v:189924.3-189925.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive13_pri$next[7:0]$14037 - attribute \src "libresoc.v:184647.3-184648.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive13_pri$next[7:0]$14516 + attribute \src "libresoc.v:189926.3-189927.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive14_pri$next[7:0]$14038 - attribute \src "libresoc.v:184649.3-184650.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive14_pri$next[7:0]$14517 + attribute \src "libresoc.v:189928.3-189929.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive15_pri$next[7:0]$14039 - attribute \src "libresoc.v:184651.3-184652.37" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive15_pri$next[7:0]$14518 + attribute \src "libresoc.v:189930.3-189931.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive1_pri$next[7:0]$14040 - attribute \src "libresoc.v:184623.3-184624.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive1_pri$next[7:0]$14519 + attribute \src "libresoc.v:189944.3-189945.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive2_pri$next[7:0]$14041 - attribute \src "libresoc.v:184625.3-184626.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive2_pri$next[7:0]$14520 + attribute \src "libresoc.v:189946.3-189947.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive3_pri$next[7:0]$14042 - attribute \src "libresoc.v:184627.3-184628.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive3_pri$next[7:0]$14521 + attribute \src "libresoc.v:189948.3-189949.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive4_pri$next[7:0]$14043 - attribute \src "libresoc.v:184629.3-184630.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive4_pri$next[7:0]$14522 + attribute \src "libresoc.v:189950.3-189951.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive5_pri$next[7:0]$14044 - attribute \src "libresoc.v:184631.3-184632.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive5_pri$next[7:0]$14523 + attribute \src "libresoc.v:189952.3-189953.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive6_pri$next[7:0]$14045 - attribute \src "libresoc.v:184633.3-184634.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive6_pri$next[7:0]$14524 + attribute \src "libresoc.v:189912.3-189913.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive7_pri$next[7:0]$14046 - attribute \src "libresoc.v:184635.3-184636.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive7_pri$next[7:0]$14525 + attribute \src "libresoc.v:189914.3-189915.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive8_pri$next[7:0]$14047 - attribute \src "libresoc.v:184637.3-184638.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive8_pri$next[7:0]$14526 + attribute \src "libresoc.v:189916.3-189917.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:184659.3-184744.6" - wire width 8 $0\xive9_pri$next[7:0]$14048 - attribute \src "libresoc.v:184639.3-184640.35" + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $0\xive9_pri$next[7:0]$14527 + attribute \src "libresoc.v:189918.3-189919.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:185044.3-185093.6" + attribute \src "libresoc.v:190339.3-190388.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:184755.3-184764.6" + attribute \src "libresoc.v:190050.3-190059.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:184964.3-184973.6" + attribute \src "libresoc.v:190259.3-190268.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:184984.3-184993.6" + attribute \src "libresoc.v:190279.3-190288.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:185004.3-185013.6" + attribute \src "libresoc.v:190299.3-190308.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:185024.3-185033.6" + attribute \src "libresoc.v:190319.3-190328.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:185094.3-185103.6" + attribute \src "libresoc.v:190389.3-190398.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:185114.3-185123.6" + attribute \src "libresoc.v:190409.3-190418.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:184775.3-184784.6" + attribute \src "libresoc.v:190070.3-190079.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:184795.3-184804.6" + attribute \src "libresoc.v:190090.3-190099.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:184815.3-184824.6" + attribute \src "libresoc.v:190110.3-190119.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:184844.3-184853.6" + attribute \src "libresoc.v:190139.3-190148.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:184864.3-184873.6" + attribute \src "libresoc.v:190159.3-190168.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:184884.3-184893.6" + attribute \src "libresoc.v:190179.3-190188.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:184904.3-184913.6" + attribute \src "libresoc.v:190199.3-190208.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:184924.3-184933.6" + attribute \src "libresoc.v:190219.3-190228.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:184944.3-184953.6" + attribute \src "libresoc.v:190239.3-190248.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:184745.3-184754.6" + attribute \src "libresoc.v:190040.3-190049.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:184954.3-184963.6" + attribute \src "libresoc.v:190249.3-190258.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:184974.3-184983.6" + attribute \src "libresoc.v:190269.3-190278.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:184994.3-185003.6" + attribute \src "libresoc.v:190289.3-190298.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:185014.3-185023.6" + attribute \src "libresoc.v:190309.3-190318.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:185034.3-185043.6" + attribute \src "libresoc.v:190329.3-190338.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:185104.3-185113.6" + attribute \src "libresoc.v:190399.3-190408.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:184765.3-184774.6" + attribute \src "libresoc.v:190060.3-190069.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:184785.3-184794.6" + attribute \src "libresoc.v:190080.3-190089.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:184805.3-184814.6" + attribute \src "libresoc.v:190100.3-190109.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:184825.3-184834.6" + attribute \src "libresoc.v:190120.3-190129.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:184854.3-184863.6" + attribute \src "libresoc.v:190149.3-190158.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:184874.3-184883.6" + attribute \src "libresoc.v:190169.3-190178.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:184894.3-184903.6" + attribute \src "libresoc.v:190189.3-190198.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:184914.3-184923.6" + attribute \src "libresoc.v:190209.3-190218.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:184934.3-184943.6" + attribute \src "libresoc.v:190229.3-190238.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:185124.3-185133.6" + attribute \src "libresoc.v:190419.3-190428.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:184396.13-184396.30" + attribute \src "libresoc.v:189691.13-189691.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:184401.13-184401.29" + attribute \src "libresoc.v:189696.13-189696.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:185143.3-185151.6" - wire $1\ics_wb__ack$next[0:0]$14155 - attribute \src "libresoc.v:184410.7-184410.25" + attribute \src "libresoc.v:190438.3-190446.6" + wire $1\ics_wb__ack$next[0:0]$14634 + attribute \src "libresoc.v:189705.7-189705.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:185134.3-185142.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14152 - attribute \src "libresoc.v:184419.14-184419.35" + attribute \src "libresoc.v:190429.3-190437.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$14631 + attribute \src "libresoc.v:189714.14-189714.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:184835.3-184843.6" - wire width 16 $1\int_level_l$next[15:0]$14124 - attribute \src "libresoc.v:184431.14-184431.36" + attribute \src "libresoc.v:190130.3-190138.6" + wire width 16 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$ternary$libresoc.v:184573$13967_Y - attribute \src "libresoc.v:184575.18-184575.116" - wire width 8 $ternary$libresoc.v:184575$13969_Y - attribute \src "libresoc.v:184577.18-184577.116" - wire width 8 $ternary$libresoc.v:184577$13971_Y - attribute \src "libresoc.v:184579.18-184579.116" - wire width 8 $ternary$libresoc.v:184579$13973_Y - attribute \src "libresoc.v:184581.18-184581.116" - wire width 8 $ternary$libresoc.v:184581$13975_Y - attribute \src "libresoc.v:184583.18-184583.116" - wire width 8 $ternary$libresoc.v:184583$13977_Y - attribute \src "libresoc.v:184586.18-184586.116" - wire width 8 $ternary$libresoc.v:184586$13980_Y - attribute \src "libresoc.v:184588.18-184588.116" - wire width 8 $ternary$libresoc.v:184588$13982_Y - attribute \src "libresoc.v:184590.18-184590.117" - wire width 8 $ternary$libresoc.v:184590$13984_Y - attribute \src "libresoc.v:184592.18-184592.117" - wire width 8 $ternary$libresoc.v:184592$13986_Y - attribute \src "libresoc.v:184594.18-184594.117" - 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$3\xive10_pri$next[7:0]$14561 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive11_pri$next[7:0]$14562 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive12_pri$next[7:0]$14563 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive13_pri$next[7:0]$14564 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive14_pri$next[7:0]$14565 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive15_pri$next[7:0]$14566 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive1_pri$next[7:0]$14567 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive2_pri$next[7:0]$14568 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive3_pri$next[7:0]$14569 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive4_pri$next[7:0]$14570 + attribute \src "libresoc.v:189954.3-190039.6" + wire width 8 $3\xive5_pri$next[7:0]$14571 + attribute \src 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"libresoc.v:189818.19-189818.112" + wire $lt$libresoc.v:189818$14396_Y + attribute \src "libresoc.v:189820.19-189820.112" + wire $lt$libresoc.v:189820$14398_Y + attribute \src "libresoc.v:189822.19-189822.112" + wire $lt$libresoc.v:189822$14400_Y + attribute \src "libresoc.v:189824.19-189824.112" + wire $lt$libresoc.v:189824$14402_Y + attribute \src "libresoc.v:189827.19-189827.112" + wire $lt$libresoc.v:189827$14405_Y + attribute \src "libresoc.v:189829.19-189829.112" + wire $lt$libresoc.v:189829$14407_Y + attribute \src "libresoc.v:189832.19-189832.112" + wire $lt$libresoc.v:189832$14410_Y + attribute \src "libresoc.v:189834.19-189834.112" + wire $lt$libresoc.v:189834$14412_Y + attribute \src "libresoc.v:189836.19-189836.112" + wire $lt$libresoc.v:189836$14414_Y + attribute \src "libresoc.v:189838.19-189838.112" + wire $lt$libresoc.v:189838$14416_Y + attribute \src "libresoc.v:189840.19-189840.113" + wire $lt$libresoc.v:189840$14418_Y + attribute \src "libresoc.v:189842.19-189842.113" + wire $lt$libresoc.v:189842$14420_Y + attribute \src "libresoc.v:189844.19-189844.114" + wire $lt$libresoc.v:189844$14422_Y + attribute \src "libresoc.v:189846.19-189846.114" + wire $lt$libresoc.v:189846$14424_Y + attribute \src "libresoc.v:189849.19-189849.114" + wire $lt$libresoc.v:189849$14427_Y + attribute \src "libresoc.v:189851.19-189851.114" + wire $lt$libresoc.v:189851$14429_Y + attribute \src "libresoc.v:189854.19-189854.114" + wire $lt$libresoc.v:189854$14432_Y + attribute \src "libresoc.v:189856.19-189856.114" + wire $lt$libresoc.v:189856$14434_Y + attribute \src "libresoc.v:189858.19-189858.114" + wire $lt$libresoc.v:189858$14436_Y + attribute \src "libresoc.v:189860.19-189860.114" + wire $lt$libresoc.v:189860$14438_Y + attribute \src "libresoc.v:189862.19-189862.114" + wire $lt$libresoc.v:189862$14440_Y + attribute \src "libresoc.v:189865.19-189865.114" + wire $lt$libresoc.v:189865$14443_Y + attribute \src "libresoc.v:189899.18-189899.110" + wire $lt$libresoc.v:189899$14477_Y + attribute \src "libresoc.v:189901.18-189901.110" + wire $lt$libresoc.v:189901$14479_Y + attribute \src "libresoc.v:189903.18-189903.111" + wire $lt$libresoc.v:189903$14481_Y + attribute \src "libresoc.v:189905.18-189905.111" + wire $lt$libresoc.v:189905$14483_Y + attribute \src "libresoc.v:189908.18-189908.111" + wire $lt$libresoc.v:189908$14486_Y + attribute \src "libresoc.v:189910.18-189910.111" + wire $lt$libresoc.v:189910$14488_Y + attribute \src "libresoc.v:189897.18-189897.40" + wire width 16 $shr$libresoc.v:189897$14475_Y + attribute \src "libresoc.v:189809.17-189809.114" + wire width 8 $ternary$libresoc.v:189809$14387_Y + attribute \src "libresoc.v:189831.18-189831.116" + wire width 8 $ternary$libresoc.v:189831$14409_Y + attribute \src "libresoc.v:189853.18-189853.116" + wire width 8 $ternary$libresoc.v:189853$14431_Y + attribute \src "libresoc.v:189868.19-189868.118" + wire width 8 $ternary$libresoc.v:189868$14446_Y + attribute \src "libresoc.v:189870.18-189870.116" + wire width 8 $ternary$libresoc.v:189870$14448_Y + attribute \src "libresoc.v:189872.18-189872.116" + wire width 8 $ternary$libresoc.v:189872$14450_Y + attribute \src "libresoc.v:189874.18-189874.116" + wire width 8 $ternary$libresoc.v:189874$14452_Y + attribute \src "libresoc.v:189876.18-189876.116" + wire width 8 $ternary$libresoc.v:189876$14454_Y + attribute \src "libresoc.v:189878.18-189878.116" + wire width 8 $ternary$libresoc.v:189878$14456_Y + attribute \src "libresoc.v:189881.18-189881.116" + wire width 8 $ternary$libresoc.v:189881$14459_Y + attribute \src "libresoc.v:189883.18-189883.116" + wire width 8 $ternary$libresoc.v:189883$14461_Y + attribute \src "libresoc.v:189885.18-189885.117" + wire width 8 $ternary$libresoc.v:189885$14463_Y + attribute \src "libresoc.v:189887.18-189887.117" + wire width 8 $ternary$libresoc.v:189887$14465_Y + attribute \src "libresoc.v:189889.18-189889.117" + wire width 8 $ternary$libresoc.v:189889$14467_Y + attribute \src "libresoc.v:189892.18-189892.117" + wire width 8 $ternary$libresoc.v:189892$14470_Y + attribute \src "libresoc.v:189894.18-189894.117" + wire width 8 $ternary$libresoc.v:189894$14472_Y + attribute \src "libresoc.v:189896.18-189896.117" + wire width 8 $ternary$libresoc.v:189896$14474_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -389079,8 +399295,8 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 2 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" @@ -389148,11 +399364,11 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" wire \ibit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 output 1 \icp_o_pri + wire width 8 output 3 \icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" wire width 8 \icp_o_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 output 12 \icp_o_src + wire width 4 output 2 \icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \icp_o_src$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" @@ -389177,7 +399393,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:184115.7-184115.15" + attribute \src "libresoc.v:189410.7-189410.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -389197,8 +399413,8 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:151" - wire input 3 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" @@ -389266,7 +399482,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184516$13910 + cell $and $and$libresoc.v:189811$14389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389274,10 +399490,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:184516$13910_Y + connect \Y $and$libresoc.v:189811$14389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184518$13912 + cell $and $and$libresoc.v:189813$14391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389285,10 +399501,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:184518$13912_Y + connect \Y $and$libresoc.v:189813$14391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184520$13914 + cell $and $and$libresoc.v:189815$14393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389296,10 +399512,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:184520$13914_Y + connect \Y $and$libresoc.v:189815$14393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184522$13916 + cell $and $and$libresoc.v:189817$14395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389307,10 +399523,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:184522$13916_Y + connect \Y $and$libresoc.v:189817$14395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184524$13918 + cell $and $and$libresoc.v:189819$14397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389318,10 +399534,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:184524$13918_Y + connect \Y $and$libresoc.v:189819$14397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184526$13920 + cell $and $and$libresoc.v:189821$14399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389329,10 +399545,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:184526$13920_Y + connect \Y $and$libresoc.v:189821$14399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184528$13922 + cell $and $and$libresoc.v:189823$14401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389340,10 +399556,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:184528$13922_Y + connect \Y $and$libresoc.v:189823$14401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184531$13925 + cell $and $and$libresoc.v:189826$14404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389351,10 +399567,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:184531$13925_Y + connect \Y $and$libresoc.v:189826$14404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184533$13927 + cell $and $and$libresoc.v:189828$14406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389362,10 +399578,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:184533$13927_Y + connect \Y $and$libresoc.v:189828$14406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184535$13929 + cell $and $and$libresoc.v:189830$14408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389373,10 +399589,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:184535$13929_Y + connect \Y $and$libresoc.v:189830$14408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184538$13932 + cell $and $and$libresoc.v:189833$14411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389384,10 +399600,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:184538$13932_Y + connect \Y $and$libresoc.v:189833$14411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184540$13934 + cell $and $and$libresoc.v:189835$14413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389395,10 +399611,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:184540$13934_Y + connect \Y $and$libresoc.v:189835$14413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184542$13936 + cell $and $and$libresoc.v:189837$14415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389406,10 +399622,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:184542$13936_Y + connect \Y $and$libresoc.v:189837$14415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184544$13938 + cell $and $and$libresoc.v:189839$14417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389417,10 +399633,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:184544$13938_Y + connect \Y $and$libresoc.v:189839$14417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184546$13940 + cell $and $and$libresoc.v:189841$14419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389428,10 +399644,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:184546$13940_Y + connect \Y $and$libresoc.v:189841$14419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184548$13942 + cell $and $and$libresoc.v:189843$14421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389439,10 +399655,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:184548$13942_Y + connect \Y $and$libresoc.v:189843$14421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184550$13944 + cell $and $and$libresoc.v:189845$14423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389450,10 +399666,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:184550$13944_Y + connect \Y $and$libresoc.v:189845$14423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184553$13947 + cell $and $and$libresoc.v:189848$14426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389461,10 +399677,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:184553$13947_Y + connect \Y $and$libresoc.v:189848$14426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184555$13949 + cell $and $and$libresoc.v:189850$14428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389472,10 +399688,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:184555$13949_Y + connect \Y $and$libresoc.v:189850$14428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184557$13951 + cell $and $and$libresoc.v:189852$14430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389483,10 +399699,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:184557$13951_Y + connect \Y $and$libresoc.v:189852$14430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184560$13954 + cell $and $and$libresoc.v:189855$14433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389494,10 +399710,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:184560$13954_Y + connect \Y $and$libresoc.v:189855$14433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184562$13956 + cell $and $and$libresoc.v:189857$14435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389505,10 +399721,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:184562$13956_Y + connect \Y $and$libresoc.v:189857$14435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184564$13958 + cell $and $and$libresoc.v:189859$14437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389516,10 +399732,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:184564$13958_Y + connect \Y $and$libresoc.v:189859$14437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184566$13960 + cell $and $and$libresoc.v:189861$14439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389527,10 +399743,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:184566$13960_Y + connect \Y $and$libresoc.v:189861$14439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184568$13962 + cell $and $and$libresoc.v:189863$14441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389538,10 +399754,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:184568$13962_Y + connect \Y $and$libresoc.v:189863$14441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184571$13965 + cell $and $and$libresoc.v:189866$14444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389549,10 +399765,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:184571$13965_Y + connect \Y $and$libresoc.v:189866$14444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:184595$13989 + cell $and $and$libresoc.v:189890$14468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389560,10 +399776,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:184595$13989_Y + connect \Y $and$libresoc.v:189890$14468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:184603$13997 + cell $and $and$libresoc.v:189898$14476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389571,10 +399787,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:184603$13997_Y + connect \Y $and$libresoc.v:189898$14476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184605$13999 + cell $and $and$libresoc.v:189900$14478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389582,10 +399798,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:184605$13999_Y + connect \Y $and$libresoc.v:189900$14478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184607$14001 + cell $and $and$libresoc.v:189902$14480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389593,10 +399809,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:184607$14001_Y + connect \Y $and$libresoc.v:189902$14480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184609$14003 + cell $and $and$libresoc.v:189904$14482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389604,10 +399820,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:184609$14003_Y + connect \Y $and$libresoc.v:189904$14482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184612$14006 + cell $and $and$libresoc.v:189907$14485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389615,10 +399831,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:184612$14006_Y + connect \Y $and$libresoc.v:189907$14485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184614$14008 + cell $and $and$libresoc.v:189909$14487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389626,10 +399842,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:184614$14008_Y + connect \Y $and$libresoc.v:189909$14487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:184616$14010 + cell $and $and$libresoc.v:189911$14489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389637,10 +399853,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:184616$14010_Y + connect \Y $and$libresoc.v:189911$14489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184530$13924 + cell $eq $eq$libresoc.v:189825$14403 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389648,10 +399864,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184530$13924_Y + connect \Y $eq$libresoc.v:189825$14403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184552$13946 + cell $eq $eq$libresoc.v:189847$14425 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389659,10 +399875,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184552$13946_Y + connect \Y $eq$libresoc.v:189847$14425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:184569$13963 + cell $eq $eq$libresoc.v:189864$14442 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389670,10 +399886,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:184569$13963_Y + connect \Y $eq$libresoc.v:189864$14442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184572$13966 + cell $eq $eq$libresoc.v:189867$14445 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389681,10 +399897,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:184572$13966_Y + connect \Y $eq$libresoc.v:189867$14445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184574$13968 + cell $eq $eq$libresoc.v:189869$14447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389692,10 +399908,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184574$13968_Y + connect \Y $eq$libresoc.v:189869$14447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184576$13970 + cell $eq $eq$libresoc.v:189871$14449 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389703,10 +399919,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184576$13970_Y + connect \Y $eq$libresoc.v:189871$14449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184578$13972 + cell $eq $eq$libresoc.v:189873$14451 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389714,10 +399930,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184578$13972_Y + connect \Y $eq$libresoc.v:189873$14451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184580$13974 + cell $eq $eq$libresoc.v:189875$14453 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389725,10 +399941,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184580$13974_Y + connect \Y $eq$libresoc.v:189875$14453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184582$13976 + cell $eq $eq$libresoc.v:189877$14455 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389736,10 +399952,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184582$13976_Y + connect \Y $eq$libresoc.v:189877$14455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:184584$13978 + cell $eq $eq$libresoc.v:189879$14457 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -389747,10 +399963,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:184584$13978_Y + connect \Y $eq$libresoc.v:189879$14457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184585$13979 + cell $eq $eq$libresoc.v:189880$14458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389758,10 +399974,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184585$13979_Y + connect \Y $eq$libresoc.v:189880$14458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184587$13981 + cell $eq $eq$libresoc.v:189882$14460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389769,10 +399985,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184587$13981_Y + connect \Y $eq$libresoc.v:189882$14460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184589$13983 + cell $eq $eq$libresoc.v:189884$14462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389780,10 +399996,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184589$13983_Y + connect \Y $eq$libresoc.v:189884$14462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184591$13985 + cell $eq $eq$libresoc.v:189886$14464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389791,10 +400007,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184591$13985_Y + connect \Y $eq$libresoc.v:189886$14464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184593$13987 + cell $eq $eq$libresoc.v:189888$14466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389802,10 +400018,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184593$13987_Y + connect \Y $eq$libresoc.v:189888$14466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184596$13990 + cell $eq $eq$libresoc.v:189891$14469 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389813,10 +400029,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184596$13990_Y + connect \Y $eq$libresoc.v:189891$14469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184598$13992 + cell $eq $eq$libresoc.v:189893$14471 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389824,10 +400040,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184598$13992_Y + connect \Y $eq$libresoc.v:189893$14471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184600$13994 + cell $eq $eq$libresoc.v:189895$14473 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389835,10 +400051,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184600$13994_Y + connect \Y $eq$libresoc.v:189895$14473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:184611$14005 + cell $eq $eq$libresoc.v:189906$14484 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389846,10 +400062,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:184611$14005_Y + connect \Y $eq$libresoc.v:189906$14484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184515$13909 + cell $lt $lt$libresoc.v:189810$14388 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389857,10 +400073,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:184515$13909_Y + connect \Y $lt$libresoc.v:189810$14388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184517$13911 + cell $lt $lt$libresoc.v:189812$14390 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389868,10 +400084,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:184517$13911_Y + connect \Y $lt$libresoc.v:189812$14390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184519$13913 + cell $lt $lt$libresoc.v:189814$14392 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389879,10 +400095,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:184519$13913_Y + connect \Y $lt$libresoc.v:189814$14392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184521$13915 + cell $lt $lt$libresoc.v:189816$14394 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389890,10 +400106,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:184521$13915_Y + connect \Y $lt$libresoc.v:189816$14394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184523$13917 + cell $lt $lt$libresoc.v:189818$14396 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389901,10 +400117,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:184523$13917_Y + connect \Y $lt$libresoc.v:189818$14396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184525$13919 + cell $lt $lt$libresoc.v:189820$14398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389912,10 +400128,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:184525$13919_Y + connect \Y $lt$libresoc.v:189820$14398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184527$13921 + cell $lt $lt$libresoc.v:189822$14400 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389923,10 +400139,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:184527$13921_Y + connect \Y $lt$libresoc.v:189822$14400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184529$13923 + cell $lt $lt$libresoc.v:189824$14402 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389934,10 +400150,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:184529$13923_Y + connect \Y $lt$libresoc.v:189824$14402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184532$13926 + cell $lt $lt$libresoc.v:189827$14405 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389945,10 +400161,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:184532$13926_Y + connect \Y $lt$libresoc.v:189827$14405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184534$13928 + cell $lt $lt$libresoc.v:189829$14407 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389956,10 +400172,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:184534$13928_Y + connect \Y $lt$libresoc.v:189829$14407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184537$13931 + cell $lt $lt$libresoc.v:189832$14410 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389967,10 +400183,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:184537$13931_Y + connect \Y $lt$libresoc.v:189832$14410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184539$13933 + cell $lt $lt$libresoc.v:189834$14412 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389978,10 +400194,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:184539$13933_Y + connect \Y $lt$libresoc.v:189834$14412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184541$13935 + cell $lt $lt$libresoc.v:189836$14414 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -389989,10 +400205,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:184541$13935_Y + connect \Y $lt$libresoc.v:189836$14414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184543$13937 + cell $lt $lt$libresoc.v:189838$14416 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390000,10 +400216,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:184543$13937_Y + connect \Y $lt$libresoc.v:189838$14416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184545$13939 + cell $lt $lt$libresoc.v:189840$14418 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390011,10 +400227,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:184545$13939_Y + connect \Y $lt$libresoc.v:189840$14418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184547$13941 + cell $lt $lt$libresoc.v:189842$14420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390022,10 +400238,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:184547$13941_Y + connect \Y $lt$libresoc.v:189842$14420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184549$13943 + cell $lt $lt$libresoc.v:189844$14422 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390033,10 +400249,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:184549$13943_Y + connect \Y $lt$libresoc.v:189844$14422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184551$13945 + cell $lt $lt$libresoc.v:189846$14424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390044,10 +400260,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:184551$13945_Y + connect \Y $lt$libresoc.v:189846$14424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184554$13948 + cell $lt $lt$libresoc.v:189849$14427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390055,10 +400271,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:184554$13948_Y + connect \Y $lt$libresoc.v:189849$14427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184556$13950 + cell $lt $lt$libresoc.v:189851$14429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390066,10 +400282,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:184556$13950_Y + connect \Y $lt$libresoc.v:189851$14429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184559$13953 + cell $lt $lt$libresoc.v:189854$14432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390077,10 +400293,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:184559$13953_Y + connect \Y $lt$libresoc.v:189854$14432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184561$13955 + cell $lt $lt$libresoc.v:189856$14434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390088,10 +400304,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:184561$13955_Y + connect \Y $lt$libresoc.v:189856$14434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184563$13957 + cell $lt $lt$libresoc.v:189858$14436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390099,10 +400315,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:184563$13957_Y + connect \Y $lt$libresoc.v:189858$14436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184565$13959 + cell $lt $lt$libresoc.v:189860$14438 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390110,10 +400326,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:184565$13959_Y + connect \Y $lt$libresoc.v:189860$14438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184567$13961 + cell $lt $lt$libresoc.v:189862$14440 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390121,10 +400337,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:184567$13961_Y + connect \Y $lt$libresoc.v:189862$14440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184570$13964 + cell $lt $lt$libresoc.v:189865$14443 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390132,10 +400348,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:184570$13964_Y + connect \Y $lt$libresoc.v:189865$14443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184604$13998 + cell $lt $lt$libresoc.v:189899$14477 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390143,10 +400359,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:184604$13998_Y + connect \Y $lt$libresoc.v:189899$14477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184606$14000 + cell $lt $lt$libresoc.v:189901$14479 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390154,10 +400370,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:184606$14000_Y + connect \Y $lt$libresoc.v:189901$14479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184608$14002 + cell $lt $lt$libresoc.v:189903$14481 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390165,10 +400381,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:184608$14002_Y + connect \Y $lt$libresoc.v:189903$14481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184610$14004 + cell $lt $lt$libresoc.v:189905$14483 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390176,10 +400392,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:184610$14004_Y + connect \Y $lt$libresoc.v:189905$14483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184613$14007 + cell $lt $lt$libresoc.v:189908$14486 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390187,10 +400403,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:184613$14007_Y + connect \Y $lt$libresoc.v:189908$14486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:184615$14009 + cell $lt $lt$libresoc.v:189910$14488 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -390198,10 +400414,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:184615$14009_Y + connect \Y $lt$libresoc.v:189910$14488_Y end - attribute \src "libresoc.v:184602.18-184602.40" - cell $shr $shr$libresoc.v:184602$13996 + attribute \src "libresoc.v:189897.18-189897.40" + cell $shr $shr$libresoc.v:189897$14475 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -390209,469 +400425,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:184602$13996_Y + connect \Y $shr$libresoc.v:189897$14475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184514$13908 + cell $mux $ternary$libresoc.v:189809$14387 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:184514$13908_Y + connect \Y $ternary$libresoc.v:189809$14387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184536$13930 + cell $mux $ternary$libresoc.v:189831$14409 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:184536$13930_Y + connect \Y $ternary$libresoc.v:189831$14409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184558$13952 + cell $mux $ternary$libresoc.v:189853$14431 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:184558$13952_Y + connect \Y $ternary$libresoc.v:189853$14431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184573$13967 + cell $mux $ternary$libresoc.v:189868$14446 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:184573$13967_Y + connect \Y $ternary$libresoc.v:189868$14446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184575$13969 + cell $mux $ternary$libresoc.v:189870$14448 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:184575$13969_Y + connect \Y $ternary$libresoc.v:189870$14448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184577$13971 + cell $mux $ternary$libresoc.v:189872$14450 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:184577$13971_Y + connect \Y $ternary$libresoc.v:189872$14450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184579$13973 + cell $mux $ternary$libresoc.v:189874$14452 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:184579$13973_Y + connect \Y $ternary$libresoc.v:189874$14452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184581$13975 + cell $mux $ternary$libresoc.v:189876$14454 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:184581$13975_Y + connect \Y $ternary$libresoc.v:189876$14454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184583$13977 + cell $mux $ternary$libresoc.v:189878$14456 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:184583$13977_Y + connect \Y $ternary$libresoc.v:189878$14456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184586$13980 + cell $mux $ternary$libresoc.v:189881$14459 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:184586$13980_Y + connect \Y $ternary$libresoc.v:189881$14459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184588$13982 + cell $mux $ternary$libresoc.v:189883$14461 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:184588$13982_Y + connect \Y $ternary$libresoc.v:189883$14461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184590$13984 + cell $mux $ternary$libresoc.v:189885$14463 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:184590$13984_Y + connect \Y $ternary$libresoc.v:189885$14463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184592$13986 + cell $mux $ternary$libresoc.v:189887$14465 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:184592$13986_Y + connect \Y $ternary$libresoc.v:189887$14465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184594$13988 + cell $mux $ternary$libresoc.v:189889$14467 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:184594$13988_Y + connect \Y $ternary$libresoc.v:189889$14467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184597$13991 + cell $mux $ternary$libresoc.v:189892$14470 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:184597$13991_Y + connect \Y $ternary$libresoc.v:189892$14470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184599$13993 + cell $mux $ternary$libresoc.v:189894$14472 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:184599$13993_Y + connect \Y $ternary$libresoc.v:189894$14472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:184601$13995 + cell $mux $ternary$libresoc.v:189896$14474 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:184601$13995_Y + connect \Y $ternary$libresoc.v:189896$14474_Y end - attribute \src "libresoc.v:184115.7-184115.20" - process $proc$libresoc.v:184115$14156 + attribute \src "libresoc.v:189410.7-189410.20" + process $proc$libresoc.v:189410$14635 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184396.13-184396.30" - process $proc$libresoc.v:184396$14157 + attribute \src "libresoc.v:189691.13-189691.30" + process $proc$libresoc.v:189691$14636 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:184401.13-184401.29" - process $proc$libresoc.v:184401$14158 + attribute \src "libresoc.v:189696.13-189696.29" + process $proc$libresoc.v:189696$14637 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:184410.7-184410.25" - process $proc$libresoc.v:184410$14159 + attribute \src "libresoc.v:189705.7-189705.25" + process $proc$libresoc.v:189705$14638 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:184419.14-184419.35" - process $proc$libresoc.v:184419$14160 + attribute \src "libresoc.v:189714.14-189714.35" + process $proc$libresoc.v:189714$14639 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:184431.14-184431.36" - process $proc$libresoc.v:184431$14161 + attribute \src "libresoc.v:189726.14-189726.36" + process $proc$libresoc.v:189726$14640 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:184451.13-184451.30" - process $proc$libresoc.v:184451$14162 + attribute \src "libresoc.v:189746.13-189746.30" + process $proc$libresoc.v:189746$14641 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:184455.13-184455.31" - process $proc$libresoc.v:184455$14163 + attribute \src "libresoc.v:189750.13-189750.31" + process $proc$libresoc.v:189750$14642 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:184459.13-184459.31" - process $proc$libresoc.v:184459$14164 + attribute \src "libresoc.v:189754.13-189754.31" + process $proc$libresoc.v:189754$14643 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:184463.13-184463.31" - process $proc$libresoc.v:184463$14165 + attribute \src "libresoc.v:189758.13-189758.31" + process $proc$libresoc.v:189758$14644 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:184467.13-184467.31" - process $proc$libresoc.v:184467$14166 + attribute \src "libresoc.v:189762.13-189762.31" + process $proc$libresoc.v:189762$14645 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:184471.13-184471.31" - process $proc$libresoc.v:184471$14167 + attribute \src "libresoc.v:189766.13-189766.31" + process $proc$libresoc.v:189766$14646 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:184475.13-184475.31" - process $proc$libresoc.v:184475$14168 + attribute \src "libresoc.v:189770.13-189770.31" + process $proc$libresoc.v:189770$14647 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:184479.13-184479.30" - process $proc$libresoc.v:184479$14169 + attribute \src "libresoc.v:189774.13-189774.30" + process $proc$libresoc.v:189774$14648 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:184483.13-184483.30" - process $proc$libresoc.v:184483$14170 + attribute \src "libresoc.v:189778.13-189778.30" + process $proc$libresoc.v:189778$14649 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:184487.13-184487.30" - process $proc$libresoc.v:184487$14171 + attribute \src "libresoc.v:189782.13-189782.30" + process $proc$libresoc.v:189782$14650 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:184491.13-184491.30" - process $proc$libresoc.v:184491$14172 + attribute \src "libresoc.v:189786.13-189786.30" + process $proc$libresoc.v:189786$14651 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:184495.13-184495.30" - process $proc$libresoc.v:184495$14173 + attribute \src "libresoc.v:189790.13-189790.30" + process $proc$libresoc.v:189790$14652 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:184499.13-184499.30" - process $proc$libresoc.v:184499$14174 + attribute \src "libresoc.v:189794.13-189794.30" + process $proc$libresoc.v:189794$14653 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:184503.13-184503.30" - process $proc$libresoc.v:184503$14175 + attribute \src "libresoc.v:189798.13-189798.30" + process $proc$libresoc.v:189798$14654 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:184507.13-184507.30" - process $proc$libresoc.v:184507$14176 + attribute \src "libresoc.v:189802.13-189802.30" + process $proc$libresoc.v:189802$14655 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:184511.13-184511.30" - process $proc$libresoc.v:184511$14177 + attribute \src "libresoc.v:189806.13-189806.30" + process $proc$libresoc.v:189806$14656 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:184617.3-184618.28" - process $proc$libresoc.v:184617$14011 - assign { } { } - assign $0\icp_o_src[3:0] \cur_idx15 - sync posedge \clk - update \icp_o_src $0\icp_o_src[3:0] - end - attribute \src "libresoc.v:184619.3-184620.25" - process $proc$libresoc.v:184619$14012 - assign { } { } - assign $0\icp_o_pri[7:0] \$203 - sync posedge \clk - update \icp_o_pri $0\icp_o_pri[7:0] - end - attribute \src "libresoc.v:184621.3-184622.35" - process $proc$libresoc.v:184621$14013 - assign { } { } - assign $0\xive0_pri[7:0] \xive0_pri$next - sync posedge \clk - update \xive0_pri $0\xive0_pri[7:0] - end - attribute \src "libresoc.v:184623.3-184624.35" - process $proc$libresoc.v:184623$14014 - assign { } { } - assign $0\xive1_pri[7:0] \xive1_pri$next - sync posedge \clk - update \xive1_pri $0\xive1_pri[7:0] - end - attribute \src "libresoc.v:184625.3-184626.35" - process $proc$libresoc.v:184625$14015 - assign { } { } - assign $0\xive2_pri[7:0] \xive2_pri$next - sync posedge \clk - update \xive2_pri $0\xive2_pri[7:0] - end - attribute \src "libresoc.v:184627.3-184628.35" - process $proc$libresoc.v:184627$14016 - assign { } { } - assign $0\xive3_pri[7:0] \xive3_pri$next - sync posedge \clk - update \xive3_pri $0\xive3_pri[7:0] - end - attribute \src "libresoc.v:184629.3-184630.35" - process $proc$libresoc.v:184629$14017 - assign { } { } - assign $0\xive4_pri[7:0] \xive4_pri$next - sync posedge \clk - update \xive4_pri $0\xive4_pri[7:0] - end - attribute \src "libresoc.v:184631.3-184632.35" - process $proc$libresoc.v:184631$14018 - assign { } { } - assign $0\xive5_pri[7:0] \xive5_pri$next - sync posedge \clk - update \xive5_pri $0\xive5_pri[7:0] - end - attribute \src "libresoc.v:184633.3-184634.35" - process $proc$libresoc.v:184633$14019 + attribute \src "libresoc.v:189912.3-189913.35" + process $proc$libresoc.v:189912$14490 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:184635.3-184636.35" - process $proc$libresoc.v:184635$14020 + attribute \src "libresoc.v:189914.3-189915.35" + process $proc$libresoc.v:189914$14491 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:184637.3-184638.35" - process $proc$libresoc.v:184637$14021 + attribute \src "libresoc.v:189916.3-189917.35" + process $proc$libresoc.v:189916$14492 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:184639.3-184640.35" - process $proc$libresoc.v:184639$14022 + attribute \src "libresoc.v:189918.3-189919.35" + process $proc$libresoc.v:189918$14493 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:184641.3-184642.37" - process $proc$libresoc.v:184641$14023 + attribute \src "libresoc.v:189920.3-189921.37" + process $proc$libresoc.v:189920$14494 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:184643.3-184644.37" - process $proc$libresoc.v:184643$14024 + attribute \src "libresoc.v:189922.3-189923.37" + process $proc$libresoc.v:189922$14495 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:184645.3-184646.37" - process $proc$libresoc.v:184645$14025 + attribute \src "libresoc.v:189924.3-189925.37" + process $proc$libresoc.v:189924$14496 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:184647.3-184648.37" - process $proc$libresoc.v:184647$14026 + attribute \src "libresoc.v:189926.3-189927.37" + process $proc$libresoc.v:189926$14497 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:184649.3-184650.37" - process $proc$libresoc.v:184649$14027 + attribute \src "libresoc.v:189928.3-189929.37" + process $proc$libresoc.v:189928$14498 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:184651.3-184652.37" - process $proc$libresoc.v:184651$14028 + attribute \src "libresoc.v:189930.3-189931.37" + process $proc$libresoc.v:189930$14499 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:184653.3-184654.39" - process $proc$libresoc.v:184653$14029 + attribute \src "libresoc.v:189932.3-189933.39" + process $proc$libresoc.v:189932$14500 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:184655.3-184656.43" - process $proc$libresoc.v:184655$14030 + attribute \src "libresoc.v:189934.3-189935.43" + process $proc$libresoc.v:189934$14501 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:184657.3-184658.39" - process $proc$libresoc.v:184657$14031 + attribute \src "libresoc.v:189936.3-189937.39" + process $proc$libresoc.v:189936$14502 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:184659.3-184744.6" - process $proc$libresoc.v:184659$14032 + attribute \src "libresoc.v:189938.3-189939.28" + process $proc$libresoc.v:189938$14503 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:189940.3-189941.25" + process $proc$libresoc.v:189940$14504 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:189942.3-189943.35" + process $proc$libresoc.v:189942$14505 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:189944.3-189945.35" + process $proc$libresoc.v:189944$14506 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:189946.3-189947.35" + process $proc$libresoc.v:189946$14507 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:189948.3-189949.35" + process $proc$libresoc.v:189948$14508 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:189950.3-189951.35" + process $proc$libresoc.v:189950$14509 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:189952.3-189953.35" + process $proc$libresoc.v:189952$14510 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:189954.3-190039.6" + process $proc$libresoc.v:189954$14511 assign { } { } assign { } { } assign { } { } @@ -390720,25 +400936,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14033 $4\xive0_pri$next[7:0]$14097 - assign $0\xive10_pri$next[7:0]$14034 $4\xive10_pri$next[7:0]$14098 - assign $0\xive11_pri$next[7:0]$14035 $4\xive11_pri$next[7:0]$14099 - assign $0\xive12_pri$next[7:0]$14036 $4\xive12_pri$next[7:0]$14100 - assign $0\xive13_pri$next[7:0]$14037 $4\xive13_pri$next[7:0]$14101 - assign $0\xive14_pri$next[7:0]$14038 $4\xive14_pri$next[7:0]$14102 - assign $0\xive15_pri$next[7:0]$14039 $4\xive15_pri$next[7:0]$14103 - assign $0\xive1_pri$next[7:0]$14040 $4\xive1_pri$next[7:0]$14104 - assign $0\xive2_pri$next[7:0]$14041 $4\xive2_pri$next[7:0]$14105 - assign $0\xive3_pri$next[7:0]$14042 $4\xive3_pri$next[7:0]$14106 - assign $0\xive4_pri$next[7:0]$14043 $4\xive4_pri$next[7:0]$14107 - assign $0\xive5_pri$next[7:0]$14044 $4\xive5_pri$next[7:0]$14108 - assign $0\xive6_pri$next[7:0]$14045 $4\xive6_pri$next[7:0]$14109 - assign $0\xive7_pri$next[7:0]$14046 $4\xive7_pri$next[7:0]$14110 - assign $0\xive8_pri$next[7:0]$14047 $4\xive8_pri$next[7:0]$14111 - assign $0\xive9_pri$next[7:0]$14048 $4\xive9_pri$next[7:0]$14112 - attribute \src "libresoc.v:184660.5-184660.29" + assign $0\xive0_pri$next[7:0]$14512 $4\xive0_pri$next[7:0]$14576 + assign $0\xive10_pri$next[7:0]$14513 $4\xive10_pri$next[7:0]$14577 + assign $0\xive11_pri$next[7:0]$14514 $4\xive11_pri$next[7:0]$14578 + assign $0\xive12_pri$next[7:0]$14515 $4\xive12_pri$next[7:0]$14579 + assign $0\xive13_pri$next[7:0]$14516 $4\xive13_pri$next[7:0]$14580 + assign $0\xive14_pri$next[7:0]$14517 $4\xive14_pri$next[7:0]$14581 + assign $0\xive15_pri$next[7:0]$14518 $4\xive15_pri$next[7:0]$14582 + assign $0\xive1_pri$next[7:0]$14519 $4\xive1_pri$next[7:0]$14583 + assign $0\xive2_pri$next[7:0]$14520 $4\xive2_pri$next[7:0]$14584 + assign $0\xive3_pri$next[7:0]$14521 $4\xive3_pri$next[7:0]$14585 + assign $0\xive4_pri$next[7:0]$14522 $4\xive4_pri$next[7:0]$14586 + assign $0\xive5_pri$next[7:0]$14523 $4\xive5_pri$next[7:0]$14587 + assign $0\xive6_pri$next[7:0]$14524 $4\xive6_pri$next[7:0]$14588 + assign $0\xive7_pri$next[7:0]$14525 $4\xive7_pri$next[7:0]$14589 + assign $0\xive8_pri$next[7:0]$14526 $4\xive8_pri$next[7:0]$14590 + assign $0\xive9_pri$next[7:0]$14527 $4\xive9_pri$next[7:0]$14591 + attribute \src "libresoc.v:189955.5-189955.29" switch \initial - attribute \src "libresoc.v:184660.9-184660.17" + attribute \src "libresoc.v:189955.9-189955.17" case 1'1 case end @@ -390762,22 +400978,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14049 $2\xive0_pri$next[7:0]$14065 - assign $1\xive10_pri$next[7:0]$14050 $2\xive10_pri$next[7:0]$14066 - assign $1\xive11_pri$next[7:0]$14051 $2\xive11_pri$next[7:0]$14067 - assign $1\xive12_pri$next[7:0]$14052 $2\xive12_pri$next[7:0]$14068 - assign $1\xive13_pri$next[7:0]$14053 $2\xive13_pri$next[7:0]$14069 - assign $1\xive14_pri$next[7:0]$14054 $2\xive14_pri$next[7:0]$14070 - assign $1\xive15_pri$next[7:0]$14055 $2\xive15_pri$next[7:0]$14071 - assign $1\xive1_pri$next[7:0]$14056 $2\xive1_pri$next[7:0]$14072 - assign $1\xive2_pri$next[7:0]$14057 $2\xive2_pri$next[7:0]$14073 - assign $1\xive3_pri$next[7:0]$14058 $2\xive3_pri$next[7:0]$14074 - assign $1\xive4_pri$next[7:0]$14059 $2\xive4_pri$next[7:0]$14075 - assign $1\xive5_pri$next[7:0]$14060 $2\xive5_pri$next[7:0]$14076 - assign $1\xive6_pri$next[7:0]$14061 $2\xive6_pri$next[7:0]$14077 - assign $1\xive7_pri$next[7:0]$14062 $2\xive7_pri$next[7:0]$14078 - assign $1\xive8_pri$next[7:0]$14063 $2\xive8_pri$next[7:0]$14079 - assign $1\xive9_pri$next[7:0]$14064 $2\xive9_pri$next[7:0]$14080 + assign $1\xive0_pri$next[7:0]$14528 $2\xive0_pri$next[7:0]$14544 + assign $1\xive10_pri$next[7:0]$14529 $2\xive10_pri$next[7:0]$14545 + assign $1\xive11_pri$next[7:0]$14530 $2\xive11_pri$next[7:0]$14546 + assign $1\xive12_pri$next[7:0]$14531 $2\xive12_pri$next[7:0]$14547 + assign $1\xive13_pri$next[7:0]$14532 $2\xive13_pri$next[7:0]$14548 + assign $1\xive14_pri$next[7:0]$14533 $2\xive14_pri$next[7:0]$14549 + assign $1\xive15_pri$next[7:0]$14534 $2\xive15_pri$next[7:0]$14550 + assign $1\xive1_pri$next[7:0]$14535 $2\xive1_pri$next[7:0]$14551 + assign $1\xive2_pri$next[7:0]$14536 $2\xive2_pri$next[7:0]$14552 + assign $1\xive3_pri$next[7:0]$14537 $2\xive3_pri$next[7:0]$14553 + assign $1\xive4_pri$next[7:0]$14538 $2\xive4_pri$next[7:0]$14554 + assign $1\xive5_pri$next[7:0]$14539 $2\xive5_pri$next[7:0]$14555 + assign $1\xive6_pri$next[7:0]$14540 $2\xive6_pri$next[7:0]$14556 + assign $1\xive7_pri$next[7:0]$14541 $2\xive7_pri$next[7:0]$14557 + assign $1\xive8_pri$next[7:0]$14542 $2\xive8_pri$next[7:0]$14558 + assign $1\xive9_pri$next[7:0]$14543 $2\xive9_pri$next[7:0]$14559 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -390798,381 +401014,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14065 $3\xive0_pri$next[7:0]$14081 - assign $2\xive10_pri$next[7:0]$14066 $3\xive10_pri$next[7:0]$14082 - assign $2\xive11_pri$next[7:0]$14067 $3\xive11_pri$next[7:0]$14083 - assign $2\xive12_pri$next[7:0]$14068 $3\xive12_pri$next[7:0]$14084 - assign $2\xive13_pri$next[7:0]$14069 $3\xive13_pri$next[7:0]$14085 - assign $2\xive14_pri$next[7:0]$14070 $3\xive14_pri$next[7:0]$14086 - assign $2\xive15_pri$next[7:0]$14071 $3\xive15_pri$next[7:0]$14087 - assign $2\xive1_pri$next[7:0]$14072 $3\xive1_pri$next[7:0]$14088 - assign $2\xive2_pri$next[7:0]$14073 $3\xive2_pri$next[7:0]$14089 - assign $2\xive3_pri$next[7:0]$14074 $3\xive3_pri$next[7:0]$14090 - assign $2\xive4_pri$next[7:0]$14075 $3\xive4_pri$next[7:0]$14091 - assign $2\xive5_pri$next[7:0]$14076 $3\xive5_pri$next[7:0]$14092 - assign $2\xive6_pri$next[7:0]$14077 $3\xive6_pri$next[7:0]$14093 - assign $2\xive7_pri$next[7:0]$14078 $3\xive7_pri$next[7:0]$14094 - assign $2\xive8_pri$next[7:0]$14079 $3\xive8_pri$next[7:0]$14095 - assign $2\xive9_pri$next[7:0]$14080 $3\xive9_pri$next[7:0]$14096 + assign $2\xive0_pri$next[7:0]$14544 $3\xive0_pri$next[7:0]$14560 + assign $2\xive10_pri$next[7:0]$14545 $3\xive10_pri$next[7:0]$14561 + assign $2\xive11_pri$next[7:0]$14546 $3\xive11_pri$next[7:0]$14562 + assign $2\xive12_pri$next[7:0]$14547 $3\xive12_pri$next[7:0]$14563 + assign $2\xive13_pri$next[7:0]$14548 $3\xive13_pri$next[7:0]$14564 + assign $2\xive14_pri$next[7:0]$14549 $3\xive14_pri$next[7:0]$14565 + assign $2\xive15_pri$next[7:0]$14550 $3\xive15_pri$next[7:0]$14566 + assign $2\xive1_pri$next[7:0]$14551 $3\xive1_pri$next[7:0]$14567 + assign $2\xive2_pri$next[7:0]$14552 $3\xive2_pri$next[7:0]$14568 + assign $2\xive3_pri$next[7:0]$14553 $3\xive3_pri$next[7:0]$14569 + assign $2\xive4_pri$next[7:0]$14554 $3\xive4_pri$next[7:0]$14570 + assign $2\xive5_pri$next[7:0]$14555 $3\xive5_pri$next[7:0]$14571 + assign $2\xive6_pri$next[7:0]$14556 $3\xive6_pri$next[7:0]$14572 + assign $2\xive7_pri$next[7:0]$14557 $3\xive7_pri$next[7:0]$14573 + assign $2\xive8_pri$next[7:0]$14558 $3\xive8_pri$next[7:0]$14574 + assign $2\xive9_pri$next[7:0]$14559 $3\xive9_pri$next[7:0]$14575 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive0_pri$next[7:0]$14081 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive0_pri$next[7:0]$14560 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive1_pri$next[7:0]$14088 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive1_pri$next[7:0]$14567 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive2_pri$next[7:0]$14089 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive2_pri$next[7:0]$14568 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive3_pri$next[7:0]$14090 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive3_pri$next[7:0]$14569 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive4_pri$next[7:0]$14091 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive4_pri$next[7:0]$14570 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive5_pri$next[7:0]$14092 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive5_pri$next[7:0]$14571 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive6_pri$next[7:0]$14093 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive6_pri$next[7:0]$14572 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive7_pri$next[7:0]$14094 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive7_pri$next[7:0]$14573 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive8_pri$next[7:0]$14095 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive8_pri$next[7:0]$14574 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14096 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14575 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive10_pri$next[7:0]$14082 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive10_pri$next[7:0]$14561 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive11_pri$next[7:0]$14083 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive11_pri$next[7:0]$14562 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive12_pri$next[7:0]$14084 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive12_pri$next[7:0]$14563 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive13_pri$next[7:0]$14085 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive13_pri$next[7:0]$14564 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive14_pri$next[7:0]$14086 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive14_pri$next[7:0]$14565 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri - assign $3\xive15_pri$next[7:0]$14087 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive15_pri$next[7:0]$14566 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14081 \xive0_pri - assign $3\xive10_pri$next[7:0]$14082 \xive10_pri - assign $3\xive11_pri$next[7:0]$14083 \xive11_pri - assign $3\xive12_pri$next[7:0]$14084 \xive12_pri - assign $3\xive13_pri$next[7:0]$14085 \xive13_pri - assign $3\xive14_pri$next[7:0]$14086 \xive14_pri - assign $3\xive15_pri$next[7:0]$14087 \xive15_pri - assign $3\xive1_pri$next[7:0]$14088 \xive1_pri - assign $3\xive2_pri$next[7:0]$14089 \xive2_pri - assign $3\xive3_pri$next[7:0]$14090 \xive3_pri - assign $3\xive4_pri$next[7:0]$14091 \xive4_pri - assign $3\xive5_pri$next[7:0]$14092 \xive5_pri - assign $3\xive6_pri$next[7:0]$14093 \xive6_pri - assign $3\xive7_pri$next[7:0]$14094 \xive7_pri - assign $3\xive8_pri$next[7:0]$14095 \xive8_pri - assign $3\xive9_pri$next[7:0]$14096 \xive9_pri + assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive9_pri$next[7:0]$14575 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14065 \xive0_pri - assign $2\xive10_pri$next[7:0]$14066 \xive10_pri - assign $2\xive11_pri$next[7:0]$14067 \xive11_pri - assign $2\xive12_pri$next[7:0]$14068 \xive12_pri - assign $2\xive13_pri$next[7:0]$14069 \xive13_pri - assign $2\xive14_pri$next[7:0]$14070 \xive14_pri - assign $2\xive15_pri$next[7:0]$14071 \xive15_pri - assign $2\xive1_pri$next[7:0]$14072 \xive1_pri - assign $2\xive2_pri$next[7:0]$14073 \xive2_pri - assign $2\xive3_pri$next[7:0]$14074 \xive3_pri - assign $2\xive4_pri$next[7:0]$14075 \xive4_pri - assign $2\xive5_pri$next[7:0]$14076 \xive5_pri - assign $2\xive6_pri$next[7:0]$14077 \xive6_pri - assign $2\xive7_pri$next[7:0]$14078 \xive7_pri - assign $2\xive8_pri$next[7:0]$14079 \xive8_pri - assign $2\xive9_pri$next[7:0]$14080 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14049 \xive0_pri - assign $1\xive10_pri$next[7:0]$14050 \xive10_pri - assign $1\xive11_pri$next[7:0]$14051 \xive11_pri - assign $1\xive12_pri$next[7:0]$14052 \xive12_pri - assign $1\xive13_pri$next[7:0]$14053 \xive13_pri - assign $1\xive14_pri$next[7:0]$14054 \xive14_pri - assign $1\xive15_pri$next[7:0]$14055 \xive15_pri - assign $1\xive1_pri$next[7:0]$14056 \xive1_pri - assign $1\xive2_pri$next[7:0]$14057 \xive2_pri - assign $1\xive3_pri$next[7:0]$14058 \xive3_pri - assign $1\xive4_pri$next[7:0]$14059 \xive4_pri - assign $1\xive5_pri$next[7:0]$14060 \xive5_pri - assign $1\xive6_pri$next[7:0]$14061 \xive6_pri - assign $1\xive7_pri$next[7:0]$14062 \xive7_pri - assign $1\xive8_pri$next[7:0]$14063 \xive8_pri - assign $1\xive9_pri$next[7:0]$14064 \xive9_pri + assign $2\xive0_pri$next[7:0]$14544 \xive0_pri + assign $2\xive10_pri$next[7:0]$14545 \xive10_pri + assign $2\xive11_pri$next[7:0]$14546 \xive11_pri + assign $2\xive12_pri$next[7:0]$14547 \xive12_pri + assign $2\xive13_pri$next[7:0]$14548 \xive13_pri + assign $2\xive14_pri$next[7:0]$14549 \xive14_pri + assign $2\xive15_pri$next[7:0]$14550 \xive15_pri + assign $2\xive1_pri$next[7:0]$14551 \xive1_pri + assign $2\xive2_pri$next[7:0]$14552 \xive2_pri + assign $2\xive3_pri$next[7:0]$14553 \xive3_pri + assign $2\xive4_pri$next[7:0]$14554 \xive4_pri + assign $2\xive5_pri$next[7:0]$14555 \xive5_pri + assign $2\xive6_pri$next[7:0]$14556 \xive6_pri + assign $2\xive7_pri$next[7:0]$14557 \xive7_pri + assign $2\xive8_pri$next[7:0]$14558 \xive8_pri + assign $2\xive9_pri$next[7:0]$14559 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14528 \xive0_pri + assign $1\xive10_pri$next[7:0]$14529 \xive10_pri + assign $1\xive11_pri$next[7:0]$14530 \xive11_pri + assign $1\xive12_pri$next[7:0]$14531 \xive12_pri + assign $1\xive13_pri$next[7:0]$14532 \xive13_pri + assign $1\xive14_pri$next[7:0]$14533 \xive14_pri + assign $1\xive15_pri$next[7:0]$14534 \xive15_pri + assign $1\xive1_pri$next[7:0]$14535 \xive1_pri + assign $1\xive2_pri$next[7:0]$14536 \xive2_pri + assign $1\xive3_pri$next[7:0]$14537 \xive3_pri + assign $1\xive4_pri$next[7:0]$14538 \xive4_pri + assign $1\xive5_pri$next[7:0]$14539 \xive5_pri + assign $1\xive6_pri$next[7:0]$14540 \xive6_pri + assign $1\xive7_pri$next[7:0]$14541 \xive7_pri + assign $1\xive8_pri$next[7:0]$14542 \xive8_pri + assign $1\xive9_pri$next[7:0]$14543 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -391194,66 +401410,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14097 8'11111111 - assign $4\xive1_pri$next[7:0]$14104 8'11111111 - assign $4\xive2_pri$next[7:0]$14105 8'11111111 - assign $4\xive3_pri$next[7:0]$14106 8'11111111 - assign $4\xive4_pri$next[7:0]$14107 8'11111111 - assign $4\xive5_pri$next[7:0]$14108 8'11111111 - assign $4\xive6_pri$next[7:0]$14109 8'11111111 - assign $4\xive7_pri$next[7:0]$14110 8'11111111 - assign $4\xive8_pri$next[7:0]$14111 8'11111111 - assign $4\xive9_pri$next[7:0]$14112 8'11111111 - assign $4\xive10_pri$next[7:0]$14098 8'11111111 - assign $4\xive11_pri$next[7:0]$14099 8'11111111 - assign $4\xive12_pri$next[7:0]$14100 8'11111111 - assign $4\xive13_pri$next[7:0]$14101 8'11111111 - assign $4\xive14_pri$next[7:0]$14102 8'11111111 - assign $4\xive15_pri$next[7:0]$14103 8'11111111 + assign $4\xive0_pri$next[7:0]$14576 8'11111111 + assign $4\xive1_pri$next[7:0]$14583 8'11111111 + assign $4\xive2_pri$next[7:0]$14584 8'11111111 + assign $4\xive3_pri$next[7:0]$14585 8'11111111 + assign $4\xive4_pri$next[7:0]$14586 8'11111111 + assign $4\xive5_pri$next[7:0]$14587 8'11111111 + assign $4\xive6_pri$next[7:0]$14588 8'11111111 + assign $4\xive7_pri$next[7:0]$14589 8'11111111 + assign $4\xive8_pri$next[7:0]$14590 8'11111111 + assign $4\xive9_pri$next[7:0]$14591 8'11111111 + assign $4\xive10_pri$next[7:0]$14577 8'11111111 + assign $4\xive11_pri$next[7:0]$14578 8'11111111 + assign $4\xive12_pri$next[7:0]$14579 8'11111111 + assign $4\xive13_pri$next[7:0]$14580 8'11111111 + assign $4\xive14_pri$next[7:0]$14581 8'11111111 + assign $4\xive15_pri$next[7:0]$14582 8'11111111 case - assign $4\xive0_pri$next[7:0]$14097 $1\xive0_pri$next[7:0]$14049 - assign $4\xive10_pri$next[7:0]$14098 $1\xive10_pri$next[7:0]$14050 - assign $4\xive11_pri$next[7:0]$14099 $1\xive11_pri$next[7:0]$14051 - assign $4\xive12_pri$next[7:0]$14100 $1\xive12_pri$next[7:0]$14052 - assign $4\xive13_pri$next[7:0]$14101 $1\xive13_pri$next[7:0]$14053 - assign $4\xive14_pri$next[7:0]$14102 $1\xive14_pri$next[7:0]$14054 - assign $4\xive15_pri$next[7:0]$14103 $1\xive15_pri$next[7:0]$14055 - assign $4\xive1_pri$next[7:0]$14104 $1\xive1_pri$next[7:0]$14056 - assign $4\xive2_pri$next[7:0]$14105 $1\xive2_pri$next[7:0]$14057 - assign $4\xive3_pri$next[7:0]$14106 $1\xive3_pri$next[7:0]$14058 - assign $4\xive4_pri$next[7:0]$14107 $1\xive4_pri$next[7:0]$14059 - assign $4\xive5_pri$next[7:0]$14108 $1\xive5_pri$next[7:0]$14060 - assign $4\xive6_pri$next[7:0]$14109 $1\xive6_pri$next[7:0]$14061 - assign $4\xive7_pri$next[7:0]$14110 $1\xive7_pri$next[7:0]$14062 - assign $4\xive8_pri$next[7:0]$14111 $1\xive8_pri$next[7:0]$14063 - assign $4\xive9_pri$next[7:0]$14112 $1\xive9_pri$next[7:0]$14064 + assign $4\xive0_pri$next[7:0]$14576 $1\xive0_pri$next[7:0]$14528 + assign $4\xive10_pri$next[7:0]$14577 $1\xive10_pri$next[7:0]$14529 + assign $4\xive11_pri$next[7:0]$14578 $1\xive11_pri$next[7:0]$14530 + assign $4\xive12_pri$next[7:0]$14579 $1\xive12_pri$next[7:0]$14531 + assign $4\xive13_pri$next[7:0]$14580 $1\xive13_pri$next[7:0]$14532 + assign $4\xive14_pri$next[7:0]$14581 $1\xive14_pri$next[7:0]$14533 + assign $4\xive15_pri$next[7:0]$14582 $1\xive15_pri$next[7:0]$14534 + assign $4\xive1_pri$next[7:0]$14583 $1\xive1_pri$next[7:0]$14535 + assign $4\xive2_pri$next[7:0]$14584 $1\xive2_pri$next[7:0]$14536 + assign $4\xive3_pri$next[7:0]$14585 $1\xive3_pri$next[7:0]$14537 + assign $4\xive4_pri$next[7:0]$14586 $1\xive4_pri$next[7:0]$14538 + assign $4\xive5_pri$next[7:0]$14587 $1\xive5_pri$next[7:0]$14539 + assign $4\xive6_pri$next[7:0]$14588 $1\xive6_pri$next[7:0]$14540 + assign $4\xive7_pri$next[7:0]$14589 $1\xive7_pri$next[7:0]$14541 + assign $4\xive8_pri$next[7:0]$14590 $1\xive8_pri$next[7:0]$14542 + assign $4\xive9_pri$next[7:0]$14591 $1\xive9_pri$next[7:0]$14543 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14033 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14034 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14035 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14036 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14037 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14038 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14039 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14040 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14041 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14042 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14043 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14044 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14045 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14046 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14047 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14048 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14512 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14513 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14514 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14515 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14516 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14517 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14518 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14519 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14520 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14521 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14522 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14523 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14524 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14525 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14526 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14527 end - attribute \src "libresoc.v:184745.3-184754.6" - process $proc$libresoc.v:184745$14113 + attribute \src "libresoc.v:190040.3-190049.6" + process $proc$libresoc.v:190040$14592 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:184746.5-184746.29" + attribute \src "libresoc.v:190041.5-190041.29" switch \initial - attribute \src "libresoc.v:184746.9-184746.17" + attribute \src "libresoc.v:190041.9-190041.17" case 1'1 case end @@ -391269,14 +401485,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:184755.3-184764.6" - process $proc$libresoc.v:184755$14114 + attribute \src "libresoc.v:190050.3-190059.6" + process $proc$libresoc.v:190050$14593 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:184756.5-184756.29" + attribute \src "libresoc.v:190051.5-190051.29" switch \initial - attribute \src "libresoc.v:184756.9-184756.17" + attribute \src "libresoc.v:190051.9-190051.17" case 1'1 case end @@ -391292,14 +401508,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:184765.3-184774.6" - process $proc$libresoc.v:184765$14115 + attribute \src "libresoc.v:190060.3-190069.6" + process $proc$libresoc.v:190060$14594 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:184766.5-184766.29" + attribute \src "libresoc.v:190061.5-190061.29" switch \initial - attribute \src "libresoc.v:184766.9-184766.17" + attribute \src "libresoc.v:190061.9-190061.17" case 1'1 case end @@ -391315,14 +401531,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:184775.3-184784.6" - process $proc$libresoc.v:184775$14116 + attribute \src "libresoc.v:190070.3-190079.6" + process $proc$libresoc.v:190070$14595 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:184776.5-184776.29" + attribute \src "libresoc.v:190071.5-190071.29" switch \initial - attribute \src "libresoc.v:184776.9-184776.17" + attribute \src "libresoc.v:190071.9-190071.17" case 1'1 case end @@ -391338,14 +401554,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:184785.3-184794.6" - process $proc$libresoc.v:184785$14117 + attribute \src "libresoc.v:190080.3-190089.6" + process $proc$libresoc.v:190080$14596 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:184786.5-184786.29" + attribute \src "libresoc.v:190081.5-190081.29" switch \initial - attribute \src "libresoc.v:184786.9-184786.17" + attribute \src "libresoc.v:190081.9-190081.17" case 1'1 case end @@ -391361,14 +401577,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:184795.3-184804.6" - process $proc$libresoc.v:184795$14118 + attribute \src "libresoc.v:190090.3-190099.6" + process $proc$libresoc.v:190090$14597 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:184796.5-184796.29" + attribute \src "libresoc.v:190091.5-190091.29" switch \initial - attribute \src "libresoc.v:184796.9-184796.17" + attribute \src "libresoc.v:190091.9-190091.17" case 1'1 case end @@ -391384,14 +401600,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:184805.3-184814.6" - process $proc$libresoc.v:184805$14119 + attribute \src "libresoc.v:190100.3-190109.6" + process $proc$libresoc.v:190100$14598 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:184806.5-184806.29" + attribute \src "libresoc.v:190101.5-190101.29" switch \initial - attribute \src "libresoc.v:184806.9-184806.17" + attribute \src "libresoc.v:190101.9-190101.17" case 1'1 case end @@ -391407,14 +401623,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:184815.3-184824.6" - process $proc$libresoc.v:184815$14120 + attribute \src "libresoc.v:190110.3-190119.6" + process $proc$libresoc.v:190110$14599 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:184816.5-184816.29" + attribute \src "libresoc.v:190111.5-190111.29" switch \initial - attribute \src "libresoc.v:184816.9-184816.17" + attribute \src "libresoc.v:190111.9-190111.17" case 1'1 case end @@ -391430,14 +401646,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:184825.3-184834.6" - process $proc$libresoc.v:184825$14121 + attribute \src "libresoc.v:190120.3-190129.6" + process $proc$libresoc.v:190120$14600 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:184826.5-184826.29" + attribute \src "libresoc.v:190121.5-190121.29" switch \initial - attribute \src "libresoc.v:184826.9-184826.17" + attribute \src "libresoc.v:190121.9-190121.17" case 1'1 case end @@ -391453,14 +401669,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:184835.3-184843.6" - process $proc$libresoc.v:184835$14122 + attribute \src "libresoc.v:190130.3-190138.6" + process $proc$libresoc.v:190130$14601 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14123 $1\int_level_l$next[15:0]$14124 - attribute \src "libresoc.v:184836.5-184836.29" + assign $0\int_level_l$next[15:0]$14602 $1\int_level_l$next[15:0]$14603 + attribute \src "libresoc.v:190131.5-190131.29" switch \initial - attribute \src "libresoc.v:184836.9-184836.17" + attribute \src "libresoc.v:190131.9-190131.17" case 1'1 case end @@ -391469,21 +401685,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14124 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14603 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14124 \int_level_i + assign $1\int_level_l$next[15:0]$14603 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14123 + update \int_level_l$next $0\int_level_l$next[15:0]$14602 end - attribute \src "libresoc.v:184844.3-184853.6" - process $proc$libresoc.v:184844$14125 + attribute \src "libresoc.v:190139.3-190148.6" + process $proc$libresoc.v:190139$14604 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:184845.5-184845.29" + attribute \src "libresoc.v:190140.5-190140.29" switch \initial - attribute \src "libresoc.v:184845.9-184845.17" + attribute \src "libresoc.v:190140.9-190140.17" case 1'1 case end @@ -391499,14 +401715,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:184854.3-184863.6" - process $proc$libresoc.v:184854$14126 + attribute \src "libresoc.v:190149.3-190158.6" + process $proc$libresoc.v:190149$14605 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:184855.5-184855.29" + attribute \src "libresoc.v:190150.5-190150.29" switch \initial - attribute \src "libresoc.v:184855.9-184855.17" + attribute \src "libresoc.v:190150.9-190150.17" case 1'1 case end @@ -391522,14 +401738,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:184864.3-184873.6" - process $proc$libresoc.v:184864$14127 + attribute \src "libresoc.v:190159.3-190168.6" + process $proc$libresoc.v:190159$14606 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:184865.5-184865.29" + attribute \src "libresoc.v:190160.5-190160.29" switch \initial - attribute \src "libresoc.v:184865.9-184865.17" + attribute \src "libresoc.v:190160.9-190160.17" case 1'1 case end @@ -391545,14 +401761,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:184874.3-184883.6" - process $proc$libresoc.v:184874$14128 + attribute \src "libresoc.v:190169.3-190178.6" + process $proc$libresoc.v:190169$14607 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:184875.5-184875.29" + attribute \src "libresoc.v:190170.5-190170.29" switch \initial - attribute \src "libresoc.v:184875.9-184875.17" + attribute \src "libresoc.v:190170.9-190170.17" case 1'1 case end @@ -391568,14 +401784,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:184884.3-184893.6" - process $proc$libresoc.v:184884$14129 + attribute \src "libresoc.v:190179.3-190188.6" + process $proc$libresoc.v:190179$14608 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:184885.5-184885.29" + attribute \src "libresoc.v:190180.5-190180.29" switch \initial - attribute \src "libresoc.v:184885.9-184885.17" + attribute \src "libresoc.v:190180.9-190180.17" case 1'1 case end @@ -391591,14 +401807,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:184894.3-184903.6" - process $proc$libresoc.v:184894$14130 + attribute \src "libresoc.v:190189.3-190198.6" + process $proc$libresoc.v:190189$14609 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:184895.5-184895.29" + attribute \src "libresoc.v:190190.5-190190.29" switch \initial - attribute \src "libresoc.v:184895.9-184895.17" + attribute \src "libresoc.v:190190.9-190190.17" case 1'1 case end @@ -391614,14 +401830,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:184904.3-184913.6" - process $proc$libresoc.v:184904$14131 + attribute \src "libresoc.v:190199.3-190208.6" + process $proc$libresoc.v:190199$14610 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:184905.5-184905.29" + attribute \src "libresoc.v:190200.5-190200.29" switch \initial - attribute \src "libresoc.v:184905.9-184905.17" + attribute \src "libresoc.v:190200.9-190200.17" case 1'1 case end @@ -391637,14 +401853,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:184914.3-184923.6" - process $proc$libresoc.v:184914$14132 + attribute \src "libresoc.v:190209.3-190218.6" + process $proc$libresoc.v:190209$14611 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:184915.5-184915.29" + attribute \src "libresoc.v:190210.5-190210.29" switch \initial - attribute \src "libresoc.v:184915.9-184915.17" + attribute \src "libresoc.v:190210.9-190210.17" case 1'1 case end @@ -391660,14 +401876,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:184924.3-184933.6" - process $proc$libresoc.v:184924$14133 + attribute \src "libresoc.v:190219.3-190228.6" + process $proc$libresoc.v:190219$14612 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:184925.5-184925.29" + attribute \src "libresoc.v:190220.5-190220.29" switch \initial - attribute \src "libresoc.v:184925.9-184925.17" + attribute \src "libresoc.v:190220.9-190220.17" case 1'1 case end @@ -391683,14 +401899,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:184934.3-184943.6" - process $proc$libresoc.v:184934$14134 + attribute \src "libresoc.v:190229.3-190238.6" + process $proc$libresoc.v:190229$14613 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:184935.5-184935.29" + attribute \src "libresoc.v:190230.5-190230.29" switch \initial - attribute \src "libresoc.v:184935.9-184935.17" + attribute \src "libresoc.v:190230.9-190230.17" case 1'1 case end @@ -391706,14 +401922,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:184944.3-184953.6" - process $proc$libresoc.v:184944$14135 + attribute \src "libresoc.v:190239.3-190248.6" + process $proc$libresoc.v:190239$14614 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:184945.5-184945.29" + attribute \src "libresoc.v:190240.5-190240.29" switch \initial - attribute \src "libresoc.v:184945.9-184945.17" + attribute \src "libresoc.v:190240.9-190240.17" case 1'1 case end @@ -391729,14 +401945,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:184954.3-184963.6" - process $proc$libresoc.v:184954$14136 + attribute \src "libresoc.v:190249.3-190258.6" + process $proc$libresoc.v:190249$14615 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:184955.5-184955.29" + attribute \src "libresoc.v:190250.5-190250.29" switch \initial - attribute \src "libresoc.v:184955.9-184955.17" + attribute \src "libresoc.v:190250.9-190250.17" case 1'1 case end @@ -391752,14 +401968,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:184964.3-184973.6" - process $proc$libresoc.v:184964$14137 + attribute \src "libresoc.v:190259.3-190268.6" + process $proc$libresoc.v:190259$14616 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:184965.5-184965.29" + attribute \src "libresoc.v:190260.5-190260.29" switch \initial - attribute \src "libresoc.v:184965.9-184965.17" + attribute \src "libresoc.v:190260.9-190260.17" case 1'1 case end @@ -391775,14 +401991,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:184974.3-184983.6" - process $proc$libresoc.v:184974$14138 + attribute \src "libresoc.v:190269.3-190278.6" + process $proc$libresoc.v:190269$14617 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:184975.5-184975.29" + attribute \src "libresoc.v:190270.5-190270.29" switch \initial - attribute \src "libresoc.v:184975.9-184975.17" + attribute \src "libresoc.v:190270.9-190270.17" case 1'1 case end @@ -391798,14 +402014,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:184984.3-184993.6" - process $proc$libresoc.v:184984$14139 + attribute \src "libresoc.v:190279.3-190288.6" + process $proc$libresoc.v:190279$14618 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:184985.5-184985.29" + attribute \src "libresoc.v:190280.5-190280.29" switch \initial - attribute \src "libresoc.v:184985.9-184985.17" + attribute \src "libresoc.v:190280.9-190280.17" case 1'1 case end @@ -391821,14 +402037,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:184994.3-185003.6" - process $proc$libresoc.v:184994$14140 + attribute \src "libresoc.v:190289.3-190298.6" + process $proc$libresoc.v:190289$14619 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:184995.5-184995.29" + attribute \src "libresoc.v:190290.5-190290.29" switch \initial - attribute \src "libresoc.v:184995.9-184995.17" + attribute \src "libresoc.v:190290.9-190290.17" case 1'1 case end @@ -391844,14 +402060,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:185004.3-185013.6" - process $proc$libresoc.v:185004$14141 + attribute \src "libresoc.v:190299.3-190308.6" + process $proc$libresoc.v:190299$14620 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:185005.5-185005.29" + attribute \src "libresoc.v:190300.5-190300.29" switch \initial - attribute \src "libresoc.v:185005.9-185005.17" + attribute \src "libresoc.v:190300.9-190300.17" case 1'1 case end @@ -391867,14 +402083,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:185014.3-185023.6" - process $proc$libresoc.v:185014$14142 + attribute \src "libresoc.v:190309.3-190318.6" + process $proc$libresoc.v:190309$14621 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:185015.5-185015.29" + attribute \src "libresoc.v:190310.5-190310.29" switch \initial - attribute \src "libresoc.v:185015.9-185015.17" + attribute \src "libresoc.v:190310.9-190310.17" case 1'1 case end @@ -391890,14 +402106,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:185024.3-185033.6" - process $proc$libresoc.v:185024$14143 + attribute \src "libresoc.v:190319.3-190328.6" + process $proc$libresoc.v:190319$14622 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:185025.5-185025.29" + attribute \src "libresoc.v:190320.5-190320.29" switch \initial - attribute \src "libresoc.v:185025.9-185025.17" + attribute \src "libresoc.v:190320.9-190320.17" case 1'1 case end @@ -391913,14 +402129,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:185034.3-185043.6" - process $proc$libresoc.v:185034$14144 + attribute \src "libresoc.v:190329.3-190338.6" + process $proc$libresoc.v:190329$14623 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:185035.5-185035.29" + attribute \src "libresoc.v:190330.5-190330.29" switch \initial - attribute \src "libresoc.v:185035.9-185035.17" + attribute \src "libresoc.v:190330.9-190330.17" case 1'1 case end @@ -391936,14 +402152,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:185044.3-185093.6" - process $proc$libresoc.v:185044$14145 + attribute \src "libresoc.v:190339.3-190388.6" + process $proc$libresoc.v:190339$14624 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:185045.5-185045.29" + attribute \src "libresoc.v:190340.5-190340.29" switch \initial - attribute \src "libresoc.v:185045.9-185045.17" + attribute \src "libresoc.v:190340.9-190340.17" case 1'1 case end @@ -392036,14 +402252,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:185094.3-185103.6" - process $proc$libresoc.v:185094$14146 + attribute \src "libresoc.v:190389.3-190398.6" + process $proc$libresoc.v:190389$14625 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:185095.5-185095.29" + attribute \src "libresoc.v:190390.5-190390.29" switch \initial - attribute \src "libresoc.v:185095.9-185095.17" + attribute \src "libresoc.v:190390.9-190390.17" case 1'1 case end @@ -392059,14 +402275,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:185104.3-185113.6" - process $proc$libresoc.v:185104$14147 + attribute \src "libresoc.v:190399.3-190408.6" + process $proc$libresoc.v:190399$14626 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:185105.5-185105.29" + attribute \src "libresoc.v:190400.5-190400.29" switch \initial - attribute \src "libresoc.v:185105.9-185105.17" + attribute \src "libresoc.v:190400.9-190400.17" case 1'1 case end @@ -392082,14 +402298,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:185114.3-185123.6" - process $proc$libresoc.v:185114$14148 + attribute \src "libresoc.v:190409.3-190418.6" + process $proc$libresoc.v:190409$14627 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:185115.5-185115.29" + attribute \src "libresoc.v:190410.5-190410.29" switch \initial - attribute \src "libresoc.v:185115.9-185115.17" + attribute \src "libresoc.v:190410.9-190410.17" case 1'1 case end @@ -392105,14 +402321,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:185124.3-185133.6" - process $proc$libresoc.v:185124$14149 + attribute \src "libresoc.v:190419.3-190428.6" + process $proc$libresoc.v:190419$14628 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:185125.5-185125.29" + attribute \src "libresoc.v:190420.5-190420.29" switch \initial - attribute \src "libresoc.v:185125.9-185125.17" + attribute \src "libresoc.v:190420.9-190420.17" case 1'1 case end @@ -392128,14 +402344,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:185134.3-185142.6" - process $proc$libresoc.v:185134$14150 + attribute \src "libresoc.v:190429.3-190437.6" + process $proc$libresoc.v:190429$14629 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14151 $1\ics_wb__dat_r$next[31:0]$14152 - attribute \src "libresoc.v:185135.5-185135.29" + assign $0\ics_wb__dat_r$next[31:0]$14630 $1\ics_wb__dat_r$next[31:0]$14631 + attribute \src "libresoc.v:190430.5-190430.29" switch \initial - attribute \src "libresoc.v:185135.9-185135.17" + attribute \src "libresoc.v:190430.9-190430.17" case 1'1 case end @@ -392144,21 +402360,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14152 0 + assign $1\ics_wb__dat_r$next[31:0]$14631 0 case - assign $1\ics_wb__dat_r$next[31:0]$14152 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$14631 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14151 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14630 end - attribute \src "libresoc.v:185143.3-185151.6" - process $proc$libresoc.v:185143$14153 + attribute \src "libresoc.v:190438.3-190446.6" + process $proc$libresoc.v:190438$14632 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14154 $1\ics_wb__ack$next[0:0]$14155 - attribute \src "libresoc.v:185144.5-185144.29" + assign $0\ics_wb__ack$next[0:0]$14633 $1\ics_wb__ack$next[0:0]$14634 + attribute \src "libresoc.v:190439.5-190439.29" switch \initial - attribute \src "libresoc.v:185144.9-185144.17" + attribute \src "libresoc.v:190439.9-190439.17" case 1'1 case end @@ -392167,116 +402383,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14155 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14155 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14154 - end - connect \$7 $ternary$libresoc.v:184514$13908_Y - connect \$99 $lt$libresoc.v:184515$13909_Y - connect \$101 $and$libresoc.v:184516$13910_Y - connect \$103 $lt$libresoc.v:184517$13911_Y - connect \$105 $and$libresoc.v:184518$13912_Y - connect \$107 $lt$libresoc.v:184519$13913_Y - connect \$109 $and$libresoc.v:184520$13914_Y - connect \$111 $lt$libresoc.v:184521$13915_Y - connect \$113 $and$libresoc.v:184522$13916_Y - connect \$115 $lt$libresoc.v:184523$13917_Y - connect \$117 $and$libresoc.v:184524$13918_Y - connect \$119 $lt$libresoc.v:184525$13919_Y - connect \$121 $and$libresoc.v:184526$13920_Y - connect \$123 $lt$libresoc.v:184527$13921_Y - connect \$125 $and$libresoc.v:184528$13922_Y - connect \$127 $lt$libresoc.v:184529$13923_Y - connect \$12 $eq$libresoc.v:184530$13924_Y - connect \$129 $and$libresoc.v:184531$13925_Y - connect \$131 $lt$libresoc.v:184532$13926_Y - connect \$133 $and$libresoc.v:184533$13927_Y - connect \$135 $lt$libresoc.v:184534$13928_Y - connect \$137 $and$libresoc.v:184535$13929_Y - connect \$11 $ternary$libresoc.v:184536$13930_Y - connect \$139 $lt$libresoc.v:184537$13931_Y - connect \$141 $and$libresoc.v:184538$13932_Y - connect \$143 $lt$libresoc.v:184539$13933_Y - connect \$145 $and$libresoc.v:184540$13934_Y - connect \$147 $lt$libresoc.v:184541$13935_Y - connect \$149 $and$libresoc.v:184542$13936_Y - connect \$151 $lt$libresoc.v:184543$13937_Y - connect \$153 $and$libresoc.v:184544$13938_Y - connect \$155 $lt$libresoc.v:184545$13939_Y - connect \$157 $and$libresoc.v:184546$13940_Y - connect \$159 $lt$libresoc.v:184547$13941_Y - connect \$161 $and$libresoc.v:184548$13942_Y - connect \$163 $lt$libresoc.v:184549$13943_Y - connect \$165 $and$libresoc.v:184550$13944_Y - connect \$167 $lt$libresoc.v:184551$13945_Y - connect \$16 $eq$libresoc.v:184552$13946_Y - connect \$169 $and$libresoc.v:184553$13947_Y - connect \$171 $lt$libresoc.v:184554$13948_Y - connect \$173 $and$libresoc.v:184555$13949_Y - connect \$175 $lt$libresoc.v:184556$13950_Y - connect \$177 $and$libresoc.v:184557$13951_Y - connect \$15 $ternary$libresoc.v:184558$13952_Y - connect \$179 $lt$libresoc.v:184559$13953_Y - connect \$181 $and$libresoc.v:184560$13954_Y - connect \$183 $lt$libresoc.v:184561$13955_Y - connect \$185 $and$libresoc.v:184562$13956_Y - connect \$187 $lt$libresoc.v:184563$13957_Y - connect \$189 $and$libresoc.v:184564$13958_Y - connect \$191 $lt$libresoc.v:184565$13959_Y - connect \$193 $and$libresoc.v:184566$13960_Y - connect \$195 $lt$libresoc.v:184567$13961_Y - connect \$197 $and$libresoc.v:184568$13962_Y - connect \$1 $eq$libresoc.v:184569$13963_Y - connect \$199 $lt$libresoc.v:184570$13964_Y - connect \$201 $and$libresoc.v:184571$13965_Y - connect \$204 $eq$libresoc.v:184572$13966_Y - connect \$203 $ternary$libresoc.v:184573$13967_Y - connect \$20 $eq$libresoc.v:184574$13968_Y - connect \$19 $ternary$libresoc.v:184575$13969_Y - connect \$24 $eq$libresoc.v:184576$13970_Y - connect \$23 $ternary$libresoc.v:184577$13971_Y - connect \$28 $eq$libresoc.v:184578$13972_Y - connect \$27 $ternary$libresoc.v:184579$13973_Y - connect \$32 $eq$libresoc.v:184580$13974_Y - connect \$31 $ternary$libresoc.v:184581$13975_Y - connect \$36 $eq$libresoc.v:184582$13976_Y - connect \$35 $ternary$libresoc.v:184583$13977_Y - connect \$3 $eq$libresoc.v:184584$13978_Y - connect \$40 $eq$libresoc.v:184585$13979_Y - connect \$39 $ternary$libresoc.v:184586$13980_Y - connect \$44 $eq$libresoc.v:184587$13981_Y - connect \$43 $ternary$libresoc.v:184588$13982_Y - connect \$48 $eq$libresoc.v:184589$13983_Y - connect \$47 $ternary$libresoc.v:184590$13984_Y - connect \$52 $eq$libresoc.v:184591$13985_Y - connect \$51 $ternary$libresoc.v:184592$13986_Y - connect \$56 $eq$libresoc.v:184593$13987_Y - connect \$55 $ternary$libresoc.v:184594$13988_Y - connect \$5 $and$libresoc.v:184595$13989_Y - connect \$60 $eq$libresoc.v:184596$13990_Y - connect \$59 $ternary$libresoc.v:184597$13991_Y - connect \$64 $eq$libresoc.v:184598$13992_Y - connect \$63 $ternary$libresoc.v:184599$13993_Y - connect \$68 $eq$libresoc.v:184600$13994_Y - connect \$67 $ternary$libresoc.v:184601$13995_Y - connect \$71 $shr$libresoc.v:184602$13996_Y [0] - connect \$73 $and$libresoc.v:184603$13997_Y - connect \$75 $lt$libresoc.v:184604$13998_Y - connect \$77 $and$libresoc.v:184605$13999_Y - connect \$79 $lt$libresoc.v:184606$14000_Y - connect \$81 $and$libresoc.v:184607$14001_Y - connect \$83 $lt$libresoc.v:184608$14002_Y - connect \$85 $and$libresoc.v:184609$14003_Y - connect \$87 $lt$libresoc.v:184610$14004_Y - connect \$8 $eq$libresoc.v:184611$14005_Y - connect \$89 $and$libresoc.v:184612$14006_Y - connect \$91 $lt$libresoc.v:184613$14007_Y - connect \$93 $and$libresoc.v:184614$14008_Y - connect \$95 $lt$libresoc.v:184615$14009_Y - connect \$97 $and$libresoc.v:184616$14010_Y + assign $1\ics_wb__ack$next[0:0]$14634 1'0 + case + assign $1\ics_wb__ack$next[0:0]$14634 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14633 + end + connect \$7 $ternary$libresoc.v:189809$14387_Y + connect \$99 $lt$libresoc.v:189810$14388_Y + connect \$101 $and$libresoc.v:189811$14389_Y + connect \$103 $lt$libresoc.v:189812$14390_Y + connect \$105 $and$libresoc.v:189813$14391_Y + connect \$107 $lt$libresoc.v:189814$14392_Y + connect \$109 $and$libresoc.v:189815$14393_Y + connect \$111 $lt$libresoc.v:189816$14394_Y + connect \$113 $and$libresoc.v:189817$14395_Y + connect \$115 $lt$libresoc.v:189818$14396_Y + connect \$117 $and$libresoc.v:189819$14397_Y + connect \$119 $lt$libresoc.v:189820$14398_Y + connect \$121 $and$libresoc.v:189821$14399_Y + connect \$123 $lt$libresoc.v:189822$14400_Y + connect \$125 $and$libresoc.v:189823$14401_Y + connect \$127 $lt$libresoc.v:189824$14402_Y + connect \$12 $eq$libresoc.v:189825$14403_Y + connect \$129 $and$libresoc.v:189826$14404_Y + connect \$131 $lt$libresoc.v:189827$14405_Y + connect \$133 $and$libresoc.v:189828$14406_Y + connect \$135 $lt$libresoc.v:189829$14407_Y + connect \$137 $and$libresoc.v:189830$14408_Y + connect \$11 $ternary$libresoc.v:189831$14409_Y + connect \$139 $lt$libresoc.v:189832$14410_Y + connect \$141 $and$libresoc.v:189833$14411_Y + connect \$143 $lt$libresoc.v:189834$14412_Y + connect \$145 $and$libresoc.v:189835$14413_Y + connect \$147 $lt$libresoc.v:189836$14414_Y + connect \$149 $and$libresoc.v:189837$14415_Y + connect \$151 $lt$libresoc.v:189838$14416_Y + connect \$153 $and$libresoc.v:189839$14417_Y + connect \$155 $lt$libresoc.v:189840$14418_Y + connect \$157 $and$libresoc.v:189841$14419_Y + connect \$159 $lt$libresoc.v:189842$14420_Y + connect \$161 $and$libresoc.v:189843$14421_Y + connect \$163 $lt$libresoc.v:189844$14422_Y + connect \$165 $and$libresoc.v:189845$14423_Y + connect \$167 $lt$libresoc.v:189846$14424_Y + connect \$16 $eq$libresoc.v:189847$14425_Y + connect \$169 $and$libresoc.v:189848$14426_Y + connect \$171 $lt$libresoc.v:189849$14427_Y + connect \$173 $and$libresoc.v:189850$14428_Y + connect \$175 $lt$libresoc.v:189851$14429_Y + connect \$177 $and$libresoc.v:189852$14430_Y + connect \$15 $ternary$libresoc.v:189853$14431_Y + connect \$179 $lt$libresoc.v:189854$14432_Y + connect \$181 $and$libresoc.v:189855$14433_Y + connect \$183 $lt$libresoc.v:189856$14434_Y + connect \$185 $and$libresoc.v:189857$14435_Y + connect \$187 $lt$libresoc.v:189858$14436_Y + connect \$189 $and$libresoc.v:189859$14437_Y + connect \$191 $lt$libresoc.v:189860$14438_Y + connect \$193 $and$libresoc.v:189861$14439_Y + connect \$195 $lt$libresoc.v:189862$14440_Y + connect \$197 $and$libresoc.v:189863$14441_Y + connect \$1 $eq$libresoc.v:189864$14442_Y + connect \$199 $lt$libresoc.v:189865$14443_Y + connect \$201 $and$libresoc.v:189866$14444_Y + connect \$204 $eq$libresoc.v:189867$14445_Y + connect \$203 $ternary$libresoc.v:189868$14446_Y + connect \$20 $eq$libresoc.v:189869$14447_Y + connect \$19 $ternary$libresoc.v:189870$14448_Y + connect \$24 $eq$libresoc.v:189871$14449_Y + connect \$23 $ternary$libresoc.v:189872$14450_Y + connect \$28 $eq$libresoc.v:189873$14451_Y + connect \$27 $ternary$libresoc.v:189874$14452_Y + connect \$32 $eq$libresoc.v:189875$14453_Y + connect \$31 $ternary$libresoc.v:189876$14454_Y + connect \$36 $eq$libresoc.v:189877$14455_Y + connect \$35 $ternary$libresoc.v:189878$14456_Y + connect \$3 $eq$libresoc.v:189879$14457_Y + connect \$40 $eq$libresoc.v:189880$14458_Y + connect \$39 $ternary$libresoc.v:189881$14459_Y + connect \$44 $eq$libresoc.v:189882$14460_Y + connect \$43 $ternary$libresoc.v:189883$14461_Y + connect \$48 $eq$libresoc.v:189884$14462_Y + connect \$47 $ternary$libresoc.v:189885$14463_Y + connect \$52 $eq$libresoc.v:189886$14464_Y + connect \$51 $ternary$libresoc.v:189887$14465_Y + connect \$56 $eq$libresoc.v:189888$14466_Y + connect \$55 $ternary$libresoc.v:189889$14467_Y + connect \$5 $and$libresoc.v:189890$14468_Y + connect \$60 $eq$libresoc.v:189891$14469_Y + connect \$59 $ternary$libresoc.v:189892$14470_Y + connect \$64 $eq$libresoc.v:189893$14471_Y + connect \$63 $ternary$libresoc.v:189894$14472_Y + connect \$68 $eq$libresoc.v:189895$14473_Y + connect \$67 $ternary$libresoc.v:189896$14474_Y + connect \$71 $shr$libresoc.v:189897$14475_Y [0] + connect \$73 $and$libresoc.v:189898$14476_Y + connect \$75 $lt$libresoc.v:189899$14477_Y + connect \$77 $and$libresoc.v:189900$14478_Y + connect \$79 $lt$libresoc.v:189901$14479_Y + connect \$81 $and$libresoc.v:189902$14480_Y + connect \$83 $lt$libresoc.v:189903$14481_Y + connect \$85 $and$libresoc.v:189904$14482_Y + connect \$87 $lt$libresoc.v:189905$14483_Y + connect \$8 $eq$libresoc.v:189906$14484_Y + connect \$89 $and$libresoc.v:189907$14485_Y + connect \$91 $lt$libresoc.v:189908$14486_Y + connect \$93 $and$libresoc.v:189909$14487_Y + connect \$95 $lt$libresoc.v:189910$14488_Y + connect \$97 $and$libresoc.v:189911$14489_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 diff --git a/pinmux b/pinmux index 24c4414..18409e4 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit 24c4414dee7455efbdbafb555517020fa405a4f4 +Subproject commit 18409e43e4385b4c78eeceb5c875153a85a958cb -- 2.30.2